Patent Publication Number: US-10319699-B2

Title: Chip package having die structures of different heights

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. patent application Ser. No. 15/003,150, filed on Jan. 21, 2016, entitled “Chip Package Having Die Structures of Different Heights and Method of Forming Same,” which claims the benefit of U.S. Provisional Application No. 62/188,169, filed on Jul. 2, 2015, entitled “Structure and Formation Method of Package,” which applications are hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. These semiconductor devices are fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers over a semiconductor substrate, and patterning the various material layers using lithography and etching processes to form circuit components and elements on the semiconductor substrate. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also use a smaller package that utilizes less area or a smaller height, in some applications. 
     New packaging technologies have been developed to improve the density and functions of semiconductor devices. These relatively new types of packaging technologies for semiconductor devices face manufacturing challenges. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1A-1F  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIG. 2  is a cross-sectional view of a chip package, in accordance with some embodiments. 
         FIGS. 3A-3E  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. 
         FIG. 4  is a cross-sectional view of a chip package, in accordance with some embodiments. 
         FIG. 5  is a cross-sectional view of a chip package, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Some embodiments of the disclosure are described.  FIGS. 1A-1F  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. Additional operations can be provided before, during, and/or after the stages described in  FIGS. 1A-1F . Some of the stages that are described can be replaced or eliminated for different embodiments. Additional features can be added to the semiconductor device structure. Some of the features described below can be replaced or eliminated for different embodiments. Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. 
     As shown in  FIG. 1A , a semiconductor chip  10  and chip stacks  20  and  30  are bonded over a substrate  180 , in accordance with some embodiments. In some embodiments, the semiconductor chip  10  is higher than the chip stack  20  or  30 . In some embodiments, the semiconductor chip  10  includes a semiconductor substrate  100  and an interconnection structure (not shown) formed on the semiconductor substrate  100 . For example, the interconnection structure is formed on a bottom surface of the semiconductor substrate  100 . The interconnection structure includes multiple interlayer dielectric layers and multiple conductive features formed in the interlayer dielectric layers. These conductive features include conductive lines, conductive vias, and conductive contacts. Some portions of the conductive features may be used as conductive pads. 
     In some embodiments, various device elements are formed in the semiconductor substrate  100 . Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements. 
     The device elements are interconnected through the interconnection structure to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof. In some embodiments, the semiconductor chip  10  is a system-on-chip (SoC) chip that includes multiple functions. 
     In some embodiments, each of the chip stacks  20  and  30  includes multiple semiconductor dies that are stacked. As shown in  FIG. 1A , the chip stack  20  includes semiconductor dies  200 ,  202 A,  202 B,  202 C,  202 D,  202 E,  202 F,  202 G, and  202 H. In some embodiments, the chip stack  20  includes a molding compound layer  210  that encapsulates and protects these semiconductor dies. The molding compound layer  210  may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. 
     In some embodiments, the semiconductor dies  202 A,  202 B,  202 C,  202 D,  202 E,  202 F,  202 G, and  202 H are memory dies. The memory dies may include memory devices such as static random access memory (SRAM) devices, dynamic random access memory (DRAM) devices, other suitable devices, or a combination thereof. In some embodiments, the semiconductor die  200  is a control die that is electrically connected to the memory dies stacked thereon. The chip stack  20  may function as a high bandwidth memory (HBM). In some embodiments, the chip stack  30  is also a high bandwidth memory that includes multiple stacked memory dies. 
     Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, one of the chip stacks  20  and  30  includes only a single chip. In these cases, the reference number  20  or  30  can be used to designate a semiconductor chip. 
     In some embodiments, conductive bonding structures  206  are formed between these semiconductor dies  200 ,  202 A,  202 B,  202 C,  202 D,  202 E,  202 F,  202 G, and  202 H to bond them together, as shown in  FIG. 1A . In some embodiments, each of the conductive bonding structures  206  includes metal pillars and/or solder bumps. In some embodiments, underfill elements  208  are formed between these semiconductor dies to surround and protect the conductive bonding structures  206 . In some embodiments, the underfill element  208  includes an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the size and/or density of the fillers dispersed in the underfill element  208  is smaller than those dispersed in the molding compound layer  210 . 
     In some embodiments, multiple conductive features  282  are formed in some of the semiconductor dies in the chip stack  20 , as shown in  FIG. 1A . Each of the conductive features  282  penetrates through one of the semiconductor dies  200 ,  202 A,  202 B,  202 C,  202 D,  202 E,  202 F,  202 G, and  202 H and is electrically connected to one of the conductive bonding structures  206 . The conductive features  282  are used as through substrate vias (TSVs). Electrical signals can be transmitted between these vertically stacked semiconductor dies through the conductive features  282 . 
     As shown in  FIG. 1A , the semiconductor chip  10  and the chip stacks  20  and  30  are bonded onto the substrate  180  through conductive bonding structures  106 , in accordance with some embodiments. In some embodiments, the conductive bonding structures  106  include solder bumps, metal pillar bumps, other suitable structures, or a combination thereof. In some embodiments, each of the conductive bonding structures  106  includes a metal pillar bump  102 , a solder element  104 , and a metal pillar bump  184 , as shown in  FIG. 1A . For example, the metal pillar bumps  102  and  184  are substantially made of copper. 
     In some embodiments, a number of metal pillar bumps  102  are formed over the bottom surfaces of the semiconductor chip  10  and the chip stacks  20  and  30 . In some embodiments, a number of metal pillar bumps  184  are formed over the substrate  180  before the bonding with the semiconductor chip  10  and the chip stacks  20  and  30 . 
     In some embodiments, solder material, such as solder paste, is applied on one or both of the metal pillar bumps  102  and  184  before the bonding process. Afterwards, the metal pillar bumps  102  and  184  are bonded together through the solder material. The solder material forms the solder elements  104  between the metal pillar bumps  102  and  184 . As a result, the conductive bonding structures  106  are formed, as shown in  FIG. 1A . In some embodiments, the solder material is an alloy material that includes tin (Sn). The solder material also includes another element. The element may include lead, silver, copper, nickel, bismuth, another suitable element, or a combination thereof. In some embodiments, the solder material does not include lead. 
     In some embodiments, the substrate  180  includes a semiconductor material, a ceramic material, an insulating material, a polymer material, another suitable material, or a combination thereof. In some embodiments, the substrate  180  is a semiconductor substrate. The semiconductor substrate may be a semiconductor wafer, such as a silicon wafer. 
     As shown in  FIG. 1A , a number of conductive features  182  are formed in the substrate  180 , in accordance with some embodiments. In some embodiments, the conductive features  182  are formed before the formation of the metal pillar bumps  184 . In some embodiments, each of the conductive features  182  is electrically connected to one of the metal pillar bumps  184 . Interconnection structures (not shown) including, for example, redistribution layers may be used to form electrical connections between the conductive features  182  and the metal pillar bumps  184 . In some embodiments, insulating elements (not shown) are formed between the conductive features  182  and the substrate  180  to prevent short circuiting between different conductive features  182 . 
     In some embodiments, the conductive features  182  are made of copper, aluminum, titanium, tungsten, cobalt, gold, platinum, another suitable material, or a combination thereof. In some embodiments, the insulating elements are made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. In some embodiments, one or more photolithography and etching processes are used to form a number of openings that define the positions of the conductive features  182 . Afterwards, an insulating layer and a conductive layer are sequentially deposited over the substrate  180  to fill the openings. A planarization process is then performed to remove the portions of the insulating layer and the conductive layer outside of the openings. As a result, the remaining portions of the insulating layer and the conductive layer in the openings form the insulating elements and the conductive features  182 , respectively. 
     As shown in  FIG. 1B , an underfill layer  108  is formed to surround and protect the conductive bonding structures  106 , in accordance with some embodiments. In some embodiments, the underfill layer  108  is in direct contact with the conductive bonding structures  106 . In some embodiments, a liquid underfill material is dispensed by capillary action and cured to form the underfill layer  108 . In some embodiments, the underfill layer  108  includes an epoxy-based resin with fillers dispersed therein. The fillers may include fibers, particles, other suitable elements, or a combination thereof. 
     As shown in  FIG. 1C , a package layer  110  is formed over the substrate  180  to encapsulate the semiconductor chip  10  and the chip stacks  20  and  30 , in accordance with some embodiments. In some embodiments, the package layer  110  fills gaps between the semiconductor chip  10  and the chip stack  20  or  30 . In some embodiments, the package layer  110  is in direct contact with the underfill layer  108 . In some embodiments, the package layer  110  is not in direct contact with the conductive bonding structures  106 . In some embodiments, the package layer  110  is in direct contact with the molding compound layers  210  of the chip stacks  20  and  30 . 
     In some embodiments, the package layer  110  includes a polymer material. In some embodiments, the package layer  110  is a molding compound layer. The molding compound layer may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. In some embodiments, the size and/or density of the fillers dispersed in the package layer  110  is greater than those dispersed in the underfill layer  108 . 
     In some embodiments, a liquid molding compound material is applied, and a thermal operation is then applied to cure the liquid molding compound material. As a result, the liquid molding compound material is hardened and transformed into the package layer  110 . In some embodiments, the thermal operation is performed at a temperature in a range from about 200 degrees C. to about 230 degrees C. The operation time of the thermal operation may be in a range from about 1 hour to about 3 hours. 
     As shown in  FIG. 1D , the package layer  110  is planarized such that the top surface of the semiconductor chip  10  is exposed, in accordance with some embodiments. In some embodiments, the top surfaces of the semiconductor chip  10  and the package layer  110  are substantially coplanar with each other. In some embodiments, the package layer  110  is planarized using a grinding process, a chemical mechanical polishing (CMP) process, another applicable process, or a combination thereof. In some embodiments, the top surface of the chip stack  20  or  30  remains covered by the package layer  110 . In some embodiments, the chip stacks  20  and  30  are protected by the package layer  110  during the planarization process. The chip stacks  20  and  30  are not ground during the planarization process. Therefore, the chip stacks  20  and  30  are prevented from being damaged during the planarization process. The quality and reliability of the chip stacks  20  and  30  are significantly improved. 
     In some embodiments, the package layer  110  covers the top and the sidewalls of the chip stacks  20  and  30 , as shown in  FIG. 1D . In some embodiments, the top surface of the semiconductor chip  10  is not covered by the package layer  110 . In some embodiments, the top surface of the package layer  110  is substantially coplanar with the top surface of the semiconductor chip  10 , which may facilitate subsequent processes. 
     As shown in  FIG. 1E , the substrate  180  is thinned to expose the conductive features  182 , in accordance with some embodiments. In some embodiments, each of the conductive features  182  penetrates through the substrate  180 . In some embodiments, each of the conductive features  182  is electrically connected to one of the conductive bonding structures  106 . In some embodiments, the structure shown in  FIG. 1D  is turned upside down. Afterwards, the substrate  180  is thinned using a planarization process to expose the conductive features  182 . The planarization process may include a CMP process, a grinding process, an etching process, another applicable process, or a combination thereof. 
     Afterwards, conductive elements are formed over the substrate  180 , as shown in  FIG. 1E  in accordance with some embodiments. In some embodiments, the conductive elements include metal pillars  114  and solder elements  116 , as shown in  FIG. 1E . However, many variations and/or modifications can be made to embodiments of the disclosure. In some other embodiments, the conductive elements have different structures. For example, the conductive elements do not include metal pillars. The conductive elements may only include solder bumps. In some embodiments, a buffer layer  112  is formed to protect the conductive elements. In some embodiments, each of the metal pillars  114  is electrically connected to one of the conductive features  182 . In some embodiments, the buffer layer  112  extends along portions of the sidewalls of the metal pillars  114 , as shown in  FIG. 1E . In some embodiments, the buffer layer  112  is made of silicon nitride, silicon oxynitride, silicon oxide, polyimide, epoxy resin, polybenzoxazole (PBO), another suitable material, or a combination thereof. 
     As shown in  FIG. 1F , the structure shown in  FIG. 1E  is bonded onto a substrate  118 , in accordance with some embodiments. In some embodiments, the substrate  118  is a circuit board such as a printed circuit board. In some other embodiments, the substrate  118  is a ceramic substrate. In some embodiments, conductive elements  120  and  124  are formed on opposite surfaces of the substrate  118 , as shown in  FIG. 1F . In some embodiments, the conductive elements  120  and  124  are solder bumps such as controlled collapse chip connection (C4) bumps and/or ball grid array (BGA) bumps. In some embodiments, the conductive elements  120  and the solder elements  116  are reflowed and bonded together, as shown in  FIG. 1F . 
     In some embodiments, each of the conductive elements  120  is electrically connected to one of the conductive elements  124  through conductive features (not shown) formed in the substrate  118 . The conductive features may include conductive lines and conductive vias. In some embodiments, an underfill layer  122  is then formed between the substrate  118  and the substrate  180  to protect the conductive bonding structures therebetween. 
     Many variations and/or modifications can be made to embodiments of the disclosure.  FIG. 2  is a cross-sectional view of a chip package, in accordance with some embodiments. In some embodiments, the underfill layer  108  is not formed. In some embodiments, the package layer  110  fills the space between the substrate  180  and the semiconductor chips including the semiconductor chip  10  and the chip stacks  20  and  30 . The package layer  110  surrounds the conductive bonding structures  106 . In some embodiments, since the underfill layer  108  is not formed, the package layer  110  is in direct contact with the conductive bonding structures  106 . 
     In some embodiments, the substrate  180  is used as an interposer. In some embodiments, the interposer does not include active devices therein. In some other embodiments, the interposer includes one or more active devices formed therein. In some embodiments, the substrate  180  is a silicon interposer. The substrate  180  may be used to improve the structural strength and reliability of the chip package. However, embodiments of the disclosure are not limited thereto. Many variations and/or modifications can be made to embodiments of the disclosure. In some embodiments, the substrate  180  is not formed. 
       FIGS. 3A-3E  are cross-sectional views of various stages of a process for forming a chip package, in accordance with some embodiments. As shown in  FIG. 3A , the semiconductor chip  10  and the chip stacks  20  and  30  are attached on a carrier substrate  300 , in accordance with some embodiments. An adhesion layer (not shown) may be used to attach the semiconductor chip  10  and the chip stacks  20  and  30  onto the carrier substrate  300 . In some embodiments, the carrier substrate  300  includes a glass substrate, a ceramic substrate, a semiconductor substrate, a polymer substrate, another suitable substrate, or a combination thereof. In some embodiments, the carrier substrate  300  is a temporary substrate to support the semiconductor chip  10  and the chip stacks  20  and  30  during subsequent processes. Afterwards, the carrier substrate  300  may be removed. 
     As shown in  FIG. 3B , a package layer  310  is formed over the carrier substrate  300  to encapsulate the semiconductor chip  10  and the chip stacks  20  and  30 , in accordance with some embodiments. In some embodiments, the package layer  310  fills gaps between the semiconductor chip  10  and the chip stack  20  or  30 . In some embodiments, the package layer  310  is in direct contact with the molding compound layers  210  of the chip stacks  20  and  30 . 
     In some embodiments, the package layer  310  includes a polymer material. In some embodiments, the package layer  310  is a molding compound layer. The molding compound layer may include an epoxy-based resin with fillers dispersed therein. The fillers may include insulating fibers, insulating particles, other suitable elements, or a combination thereof. 
     In some embodiments, a liquid molding compound material is applied, and a thermal operation is then applied to cure the liquid molding compound material. As a result, the liquid molding compound material is hardened and transformed into the package layer  310 . In some embodiments, the thermal operation is performed at a temperature in a range from about 200 degrees C. to about 230 degrees C. The operation time of the thermal operation may be in a range from about 1 hour to about 3 hours. 
     As shown in  FIG. 3C , the package layer  310  is planarized so that the top surface of the semiconductor chip  10  is exposed, in accordance with some embodiments. In some embodiments, the package layer  310  is planarized using a grinding process, a chemical mechanical polishing (CMP) process, another applicable process, or a combination thereof. In some embodiments, the top surface of the chip stack  20  or  30  remains covered by the package layer  310 . In some embodiments, the chip stacks  20  and  30  are protected by the package layer  310  during the planarization process. The chip stacks  20  and  30  are not ground during the planarization process. Therefore, the chip stacks  20  and  30  are prevented from being damaged during the planarization process. The quality and reliability of the chip stacks  20  and  30  are significantly improved. 
     In some embodiments, the package layer  310  covers the top and the sidewalls of the chip stacks  20  and  30 , as shown in  FIG. 3C . In some embodiments, the top surface of the semiconductor chip  10  is not covered by the package layer  310 . In some embodiments, the top surface of the package layer  310  is substantially coplanar with the top surface of the semiconductor chip  10 , which may facilitate subsequent processes. 
     As shown in  FIG. 3D , the carrier substrate  300  is removed such that the bottom surfaces of the semiconductor chip  10 , the chip stacks  20  and  30 , and the package layer  310  are exposed, in accordance with some embodiments. In some embodiments, the bottom surfaces of the semiconductor chip  10 , the chip stacks  20  and  30 , and the package layer  310  are substantially coplanar with each other. 
     Afterwards, conductive elements are formed over the bottom surfaces of the semiconductor chip  10  and the chip stacks  20  and  30 , as shown in  FIG. 3D  in accordance with some embodiments. In some embodiments, the conductive elements include metal pillars  314  and solder elements  316 , as shown in  FIG. 1E . In some other embodiments, the conductive elements include other configurations. In some embodiments, a buffer layer (not shown) is formed to protect the conductive elements. 
     As shown in  FIG. 3E , the structure shown in  FIG. 3D  is bonded onto a substrate  318 , in accordance with some embodiments. In some embodiments, the substrate  318  is a circuit board such as a printed circuit board. In some other embodiments, the substrate  318  is a ceramic substrate. In some embodiments, conductive elements  320  and  324  are formed on opposite surfaces of the substrate  318 , as shown in  FIG. 3E . In some embodiments, the conductive elements  320  and  324  are solder bumps such as controlled collapse chip connection (C4) bumps and/or ball grid array (BGA) bumps. In some embodiments, the conductive elements  320  and the solder elements  316  are reflowed and bonded together, as shown in  FIG. 3E . 
     In some embodiments, each of the conductive elements  320  is electrically connected to one of the conductive elements  324  through conductive features (not shown) formed in the substrate  318 . The conductive features may include conductive lines and conductive vias. In some embodiments, an underfill layer  322  is then formed between the substrate  318  and the chips including the semiconductor chip  10  and the chip stacks  20  and  30  to protect the conductive bonding structures therebetween. In some embodiments, the package layer  310  is not in direct contact with the conductive bonding structures therebetween. 
     In some embodiments, due to the protection of the package layer  310 , the chip stacks  20  and  30  are prevented from being damaged during the fabrication processes. For example, the stress generated from the planarization of the package layer  310  and the bonding process to the substrate  318  is buffered. The quality of the chip package is improved. 
     Many variations and/or modifications can be made to embodiments of the disclosure.  FIG. 4  is a cross-sectional view of a chip package, in accordance with some embodiments. In some embodiments, the underfill layer  108  not only surrounds the conductive bonding structures  106  but further extends on sidewalls of the semiconductor chip  10 . Portions of the sidewalls of the semiconductor chip  10  are covered by the underfill layer  108 . In some embodiments, the underfill layer  108  extends on the chip stacks  20  and  30 . Portions of the sidewalls of the chip stacks  20  and  30  are covered by the underfill layer  108 . 
     Many variations and/or modifications can be made to embodiments of the disclosure.  FIG. 5  is a cross-sectional view of a chip package, in accordance with some embodiments. The structure shown in  FIG. 5  is similar to that shown in  FIG. 1F . In some embodiments, the semiconductor chip  10  is positioned between the chip stack  20  and a semiconductor chip  40 . In some embodiments, the semiconductor chip  10  is higher than the chip stack  20  or the semiconductor chip  40 . In some embodiments, the heights of the semiconductor chip  40  and the chip stack  20  are different from each other. In some embodiments, the semiconductor chip  40  is higher than the chip stack  20 . 
     In some embodiments, the semiconductor chip  40  includes a semiconductor substrate  400  and an interconnection structure (not shown) formed on the semiconductor substrate  400 . For example, the interconnection structure is formed on a bottom surface of the semiconductor substrate  400 . The interconnection structure includes multiple interlayer dielectric layers and multiple conductive features formed in the interlayer dielectric layers. These conductive features include conductive lines, conductive vias, and conductive contacts. Some portions of the conductive features may be used as conductive pads. 
     In some embodiments, similar to the semiconductor substrate  100 , various device elements are formed in the semiconductor substrate  400 . Examples of the various device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high voltage transistors, high frequency transistors, p-channel and/or n-channel field effect transistors (PFETs/NFETs), etc.), diodes, or other suitable elements. 
     The device elements are interconnected through the interconnection structure to form integrated circuit devices. The integrated circuit devices include logic devices, memory devices (e.g., static random access memories, SRAMs), radio frequency (RF) devices, input/output (I/O) devices, system-on-chip (SoC) devices, other applicable types of devices, or a combination thereof. In some embodiments, the semiconductor chip  40  is a system-on-chip (SoC) chip that includes multiple functions. In some embodiments, one or more of the functions of the semiconductor chips  10  and  40  are different from each other. 
     Embodiments of the disclosure form a chip package including a first semiconductor chip and a second semiconductor chip that may be a chip stack. The heights of the first semiconductor chip and the second semiconductor chip are different. A package layer, such as a molding compound layer, is formed to encapsulate the first semiconductor chip and the second semiconductor chip. The package layer is thinned to expose the first semiconductor chip. During the thinning process, the second semiconductor chip is protected by the package layer without being directly ground. The second semiconductor chip (or chip stack) is prevented from negatively affected due to the protection of the package layer during the thinning process. The performance and reliability of the chip package are significantly improved. 
     In accordance with some embodiments, a chip package is provided. The chip package includes a chip stack including a number of semiconductor dies. The chip package also includes a semiconductor chip, and the semiconductor chip is higher than the chip stack. The chip package further includes a package layer covering a top and sidewalls of the chip stack and sidewalls of the semiconductor chip. 
     In accordance with some embodiments, a chip package is provided. The chip package includes a first semiconductor chip and a second semiconductor chip. The chip package also includes a molding compound layer surrounding the first semiconductor chip and the second semiconductor chip. The molding compound layer covers a top surface of the first semiconductor chip, and a top surface of the molding compound layer is substantially coplanar with a top surface of the second semiconductor chip. 
     In accordance with some embodiments, a method for forming a chip package is provided. The method includes bonding a first semiconductor chip and a second semiconductor chip over a substrate. The method also includes forming a package layer over the substrate to encapsulate the first semiconductor chip and the second semiconductor chip. The method further includes planarizing the package layer so that a top surface of the second semiconductor chip is exposed, and a top surface of the first semiconductor chip is covered by the package layer. 
     In accordance with some embodiments, a package is provided. The package includes a substrate, and a first chip stack bonded to the substrate. The package also includes a second chip stack bonded to the substrate adjacent the first chip stack. The package further includes a molding compound layer extending along a first side of the first chip stack, the first side of the first chip stack being a farthest side of the first chip stack from the substrate. 
     In accordance with some embodiments, a package is provided. The package includes a substrate, and a first semiconductor chip attached to the substrate. The package also includes a second semiconductor chip attached to the substrate, the first semiconductor chip and the second semiconductor chip being attached to a same side of the substrate. The package further includes a molding compound layer surrounding the first semiconductor chip and the second semiconductor chip, the molding compound layer covering a top surface of the first semiconductor chip. 
     In accordance with some embodiments, a package is provided. The package includes a substrate, a semiconductor chip bonded to the substrate, and a first chip stack bonded to the substrate. The package also includes an underfill layer extending between the semiconductor chip and the substrate and between the first chip stack and the substrate, at least a portion of the underfill layer extending along sidewalls of the semiconductor chip and along sidewalls of the first chip stack. The package further includes a package layer over the underfill layer, the package layer extending along a topmost surface of the first chip stack, an interface between the underfill layer and package layer being above a bottommost surface of the first chip stack and below the topmost surface of the first chip stack. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.