Patent Publication Number: US-4150311-A

Title: Differential amplifier circuit

Description:
BACKGROUND OF INVENTION 
     This invention relates to a differential amplifier circuit, and more particularly to a differential signal amplifying circuit which is utilized as a sense amplifier for a memory circuit. 
     Recently, MOS one transistor memory cells have been used widely as this type of memory cell has a minimum number of active elements, thus allowing the construction of small memory cells. 
     As shown in FIG. 1, this type of memory cell consists of a storage capacitor Co and a transistor Qo having a gate electrode, a source electrode and a drain electrode. The gate electrode is electrically connected to a row select line 10, the source electrode is electrically connected to a column-select line 20 and the drain electrode is electrically connected to the capacitor Co. 
     In a one transistor memory cell, information read-out is dependent on that charge or lack of charge stored in capacitor Qo. Due to the fact that the charge stored in capacitor Qo is very small it is extremely difficult to detect the information stored in the memory cell. Therefore, a MOS differential signal amplifier is commonly used as a sense amplifier for detecting the stored information. Such a differential signal amplifier is essentially constructed from a balanced flip-flop circuit wherein the same electrical potential is initially impressed on both input terminals of the flip-flop circuit and thereafter the information to be read out from the memory cell is impressed on one of the input terminals. The potential of the read out information impressed on the one of the input terminals, causes an imbalance in the flip-flop which tips the flip-flop in a predictable direction to produce an output signal. 
     Therefore what occurs is that the differential input signal is amplified due to the amplifying function of the flip-flop circuit to produce a complementary output at the two input/output terminals. In such a differential amplifier, a relatively high voltage is necessarily impressed on the gate electrode of one of the MOS transistors included in the flip-flop subsequent to the amplifying operation. The result is that an electric field is applied to the gate insulating film of the MOS transistor for a considerable period of time causing a polarization of a phosphorous glass layer placed on the gate insulating film and/or causing a drift of cations in the gate insulating film which changes the value of the threshold voltage of the MOS transistor. This change in the threshold voltage is undesirable for any amplifier and especially for a differential amplifier utilized to amplify the above-described small input signals because it lowers the reliability and sensitivity of the amplifier. These types of prior art devices are disclosed in &#34;Electronics&#34; magazine, dated Sept. 13, 1973, on pages 113 to 121. 
     With reference to FIGS. 2 and 3, the differential type sense amplifier circuit according to the prior art will be described. As shown in FIG. 2, n channel field effect transistors Q 1 , Q 2 , Q 3  and Q 4  comprise a flip-flop circuit, in which transistors Q 1  and Q 2  are provided with a constant voltage V DD  at their drain electrodes and are used as load transistors in accordance with clock signal SE. Similarly transistors Q 3  and Q 4  are used as amplifying transistors. 
     N channel field effect transistors Q 5 , Q 7  and Q 8  are used to charge input terminals 1 and 2, and to charge node 3 of the flip-flop circuit with a constant voltage source V M  by controlling the potential of the gate electrodes of transitions Q 5 , Q 7  and Q 8  with signal P before clock signal SE is impressed on the gate electrode of n channel field effect transistor Q 6 . Transistor Q 6  controls an operation of the flip-flop circuit as will be described hereinafter. N channel field effect transistor Q 9  inserted between input terminals 1 and 2 is used to equalize the potential between terminals 1 and 2 in accordance with the signal P. 
     Refer to FIG. 3 wherein it is illustrated that in the operation of this amplifier, the signal P is maintained at a high level till time T 1  thereby allowing terminals 1 and 2 and node 3 to be charged. Thereafter chip-enable signal CE goes high and is impressed on a relevant memory cell (not shown) for activation thereof and information read from the memory cell is impressed on the terminals 1 and 2 as a differential signal input. At time T 2 , the clock signal SE goes high and is impressed on the gate electrodes of the transistors Q 1 , Q 2  and Q 6  to activate the flip-flop circuit for amplifying the differential signal input. Thus, the amplified output of the read-out information can be detected at the terminals 1 and 2. Finally, at time T 3 , the levels of the chip-enable signal CE and clock signal SE change to a low level and the level of the signal P again becomes high to complete the sensing operation. 
     However, after the amplified output is developed, a relatively high voltage is still impressed on the gate electrode of one of the transistors Q 3  and Q 4  during the relatively long period of time between T 2  and T 3 , which is the period that the clock signal SE is at a high level. This causes a polarization of a phosphorous glass layer in the gate oxide film included in the transistor which results in a change in the threshold voltage of the transistor. Thus the sensitivity and reliability of this amplifier is adversely affected. 
     It is therefore an object of this invention to prevent changes in the threshold voltage of a differential signal amplifier. 
     It is another object of this invention to increase the sensitivity of a differential signal amplifier. 
     It is a further object of this invention to provide a sensitive sense amplifier for a memory circuit which is resistant to changes in threshold voltage. 
     SUMMARY OF INVENTION 
     A differential type amplifier according to this invention comprises a first stage amplifier comprising two amplifying means, a second stage differential type amplifier, and means for clamping input terminals of the amplifying means of the first stage amplifier to a predetermined potential that does not affect the performance of the two amplifying means. The first stage amplifier is initially enabled and low level differential input signals are applied to the input terminals of the two amplifying means, whereby the first stage amplifier produces amplified differential signals, the level of which is sufficient to operate the second stage amplifier. In this manner the amplified differential signals from the first stage amplifier are further amplified and maintained by the second stage amplifier. Subsequent thereto, the potential of the input terminals of the two amplifying means is clamped to the predetermined potential. A high voltage is impressed on the second stage amplifier so that the threshold voltage thereof may be varied. However, in the first stage amplifier, which is receiving low level input signals, the threshold voltage thereof is not varied, so that a differential signal may be amplified accurately. Accordingly, even if the threshold voltage is varied in the second stage amplifier, the differential input signal is amplified such that it is free of the influence of variations in the threshold voltage of the second stage amplifier thereby solving the problems previously experienced with prior art amplifying circuits. 
     The present invention is applicable to, and effective with various kinds of field-effect transistors. 
     The foregoing and other objects and features of this invention will be more fully understood from the following description of an illustrative embodiment thereof taken in conjunction with the accompanying drawings. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a transistor memory cell. 
     FIG. 2 is a circuit diagram showing a prior art differential type sense amplifier. 
     FIG. 3 is a diagram showing the wave forms of respective signals for operating the circuit of FIG. 2; 
     FIG. 4 is a circuit diagram of one embodiment of the invention; and 
     FIG. 5 is a diagram showing the wave forms of respective signals for operating the circuit of FIG. 4. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENT 
     Now, with reference to FIGS. 4 to 5, an embodiment according to this invention will be described. In this embodiment, all transistors Q 1  to Q 17  are assumed to be n-channel enhancement type MOS transistors. A first stage flip-flop amplifier includes transistors Q 1 , Q 2 , Q 3  and Q 4 . Transistors Q 10  and Q 11  are used for operatively applying a differential signal input to the first stage amplifier. Drain electrodes and gate electrodes of the transistors Q 1  and Q 2  are commonly connected to a constant voltage source V DD  and to a clock signal SE, respectively. A source electrode of Q 1  and a drain electrode of transistor Q 3  are connected at a node 1, to which is also connected a source or drain electrode of transistor Q 11 , the remaining drain or source electrode of Q 11  being electrically connected to a gate electrode of transistor Q 4 . A source electrode of Q 2  and a drain electrode of transistor Q 4  is connected at a node 2 to which is also connected a source or drain electrode of transistor Q 10 , the remaining drain or source electrode of which is electrically connected to a gate electrode of transistor Q 3 . Source electrodes of transistors Q 3  and Q 4  are connected in common at a node 3 and also coupled to a drain electrode of transistor Q 6 . The gate and source electrodes of Q 6  are connected to a clock signal SE and to the ground potential, respectively. Gate electrodes of the transistors Q 10  and Q 11  are connected in common and supplied with a timing signal PX. 
     A second stage differential amplifier includes transistor Q 1 , Q 2 , Q 14 , Q 15  and Q 17 , in which transistors Q 1  and Q 2  are used as load transistors in common with the first stage flip-flop amplifier. The source electrode of the transistor Q 1  is connected at the node 1 to a drain electrode of the transistor Q 14  and to a gate electrode of the transistor Q 15 . The source electrode of Q 2  is connected at the node 2 to a drain electrode of the transistor Q 15  and to a gate electrode of the transistor Q 14 . Source electrodes of the transistors Q 14  and Q 15  are connected in common and coupled to a drain electrode of the transistor Q 17  at a node 7. Gate and source electrodes of Q 17  are connected to a timing signal SE&#39; and to the ground potential, respectively. 
     Other transistors Q 7 , Q 8 , Q 5  and Q 16  are used for charging the nodes 1, 2, 3, and 7 respectively before the amplifying operation. Drain electrodes and gate electrodes of these transistors Q 7 , Q 8 , Q 5  and Q 16  are connected to voltage source V M  and to a signal source P, respectively. Source electrodes of these transistors Q 7 , Q 8 , Q 5  and Q 16  are connected to nodes 1, 2, 3 and 7, respectively. 
     Transistor Q 9  is inserted between the nodes 1 and 2 for equalizing the potential at nodes 1 and 2 in response to the signal P. Transistors Q 12  and Q 13  are provided between the gate electrodes and the source electrodes of the transistors Q 3  and Q 4 , respectively for short-circuiting gates and sources of Q 3  and Q 4  in response to the timing signal SD impressed on the gate electrodes of Q 12  and Q 13  to thereby clamp the gate electrodes of Q 3  and Q 4  to the ground potential. The nodes 1 and 2 serve as both input and output terminals of the circuit. 
     A description of this amplifier will now be given with reference to FIG. 5. At a time T 1  when the nodes 1, 2, 3 and 7 have been charged by voltage V M  via Q 7 , Q 8 , Q 5  and Q 16  in conjunction with the signal P, the signal P is changed to a low level. At this same time, the chip-enable signal CE is raised to a high level, and a differential signal such as information read-out from a memory cell (not shown) is applied to the nodes 1, 2. At time T 2  the timing signal SE is raised to a high level and the signal PX is also high to activate the first stage flip-flop amplifier consisting of transistors Q 3  and Q 4 . This results in amplifying the input signal to a value which is large when compared with an unbalanced value of threshold voltages existing between transistors Q 14  and Q 15  in the second stage flip-flop amplifier, the unbalanced value being developed due to the polarization occurring in the gate portions of Q 14  and Q 15 . At this time the gate electrodes of the transistors Q 3  and Q 4  are electrically connected to the nodes 2 and 1 respectively, since the transistors Q 10  and Q 11  are maintained &#34;ON&#34; by the signal PX which is at a high level. At this same time, the transistors Q 14  and Q 15  of the second stage flip-flop amplifier are not enabled, since the level of signal SE&#39; is low. 
     At time T 3 , the timing signal SE&#39; is raised to a high level to enable the second stage flip-flop amplifier. Thereafter at time T 4 , the signal PX goes low to turn the transistors Q 10  and Q 11  &#34;OFF&#34;. The signal SD is immediately raised to a high level to turn the transistors Q 12  and Q 13  &#34;ON&#34; at time T 5 , thereby connecting the gate electrodes of the transistors Q 3  and Q 4  to the ground potential by way of enable transistor Q 6 . 
     Thus, after amplifying the differential input signal to a level free from the influence of the above-described polarization in the second stage flip-flop amplifier, the first stage flip-flop amplifier transfers its amplified differential signal to the second stage flip-flop amplifier, while at the same time any change in threshold voltages of the transistors Q 3  and Q 4  is prevented by clamping the gate electrode potentials of the transistors Q 3  and Q 4  to the ground potential. The input differential signal for the second stage flip-flop amplifier is amplified by the first stage flip-flop amplifier to such a level that the second stage flip-flop amplifier can operate irrespective of any change in the threshold voltages present in Q 14  and Q 15 . The output signal of the circuit which, has been amplified by the second stage amplifier is derived from the nodes 1 and 2. 
     At time T 6 , the levels of the signals SD, SE&#39;, SE and chip-enable signal CE go low and at the same time the levels of the signals P and PX go high. This completes the operation of this sense amplifier. 
     In the operation of the circuit, the duration between time T 3  and time T 5  are not critical. More particularly, the changes in the level of the signals SE&#39;, PX and SD may occur at the same time during the interval between times T 3  to T 5 . Other types of field-effect transistors can also be used in this invention and the described usages of source and drain electrodes for the transistors are not restricted in the above embodiment. 
     Although a specific embodiment of this invention has been shown and described, it will be understood that various modifications may be made without departing from the spirit of this invention.