Patent Publication Number: US-8994350-B2

Title: Load transient detection and clock reset circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to power electronics and, more specifically, to a switching voltage regulator. 
     2. Description of the Related Arts 
     Switching voltage regulators are commonly utilized in a wide variety of electronic circuits because of their high power conversion efficiency. A common concern in the design and use of switching regulators is switching loss. Generally, switching loss increases as the switching frequency of the regulator increases. Thus, to reduce switching loss, a slower switching frequency should be used. However, as the switching frequency decreases, the load transient response of the switching regulator also becomes slower. A slow transient response may cause the output voltage to deviate from its desired value because the regulator cannot respond quickly enough to changing load demands. 
       FIG. 1A  is a block diagram illustrating a conventional switching regulator  100 . Switching regulator  100  comprises boost converter  102  and PWM controller  104 . Other conventional circuit components are omitted for clarity of description. Boost converter  102  receives input voltage V IN  and supplies regulated output voltage V OUT  to drive a load  106 . PWM controller  104  controls switching of boost converter  102  via control signal PWM_CTRL according to a conventional pulse width modulation (PWM) technique. PWM_CTRL comprises a series of variable width pulses outputted at a fixed frequency. PWM controller  104  outputs one pulse of PWM_CTRL for each clock cycle of CLK_IN. PWM controller  104  also monitors various characteristics of boost converter  102  via feedback control signal FB_CTRL, and varies the duty cycle of PWM_CTRL to achieve the desired output power regulation. 
       FIG. 1B  is a waveform diagram illustrating the transient response problem in the context of conventional switching regulator  100 . The waveforms illustrate a load current I L  through load  106 , clock signal CLK_IN, and PWM control signal PWM_CTRL. Between times t 0  and t 1 , load current I L  remains constant and PWM_CTRL controls switching of boost controller  102  according to a fixed duty cycle. At a time t 1 , the load demand changes and load current I L  increases. To meet the increased load demand, PWM controller  104  must increase the duty cycle of PWM_CTRL. However, PWM controller  104  cannot begin adjusting the duty cycle of PWM_CTRL until the start of the next clock cycle at time t 2 . Thus, there is a transient delay, t d =t 2 −t 1 , during which V OUT  may begin to droop. This transient delay problem is exacerbated further as switching frequency is reduced. As a result, designers and users of conventional switching regulators are faced with an undesirable tradeoff between power efficiency and transient response when selecting a switching frequency. 
     SUMMARY OF THE INVENTION 
     A switching regulator, controller circuit, and method for controlling a switching regulator according to various embodiments of the present invention advantageously utilizes a slower PWM clock to control switching of a power converter while utilizing a faster internal clock to adjust the PWM to load transients. As a result, the switching regulator provides improved transient response compared to conventional architectures without sacrificing power efficiency. 
     In a first aspect, a switching regulator comprises a PWM controller, a power converter, a load transient detection circuit, and a clock generator. The PWM controller is configured to receive a PWM clock and generate a PWM control signal based on the PWM clock. The power converter receives the PWM control signal and provides regulated power to a load. The regulated power is controllable by varying the duty cycle of the PWM control signal. The load transient detection circuit is configured to detect an increase in load that exceeds a detection threshold and output a load transient detection signal to a clock generator. The clock generator generates the PWM clock from a faster internal clock (e.g., using a clock divider circuit). The clock generator furthermore resets the PWM clock synchronously with the fast clock responsive to detecting the increase in load. In one embodiment, resetting the PWM clock comprises generating a new clock cycle of the PWM clock synchronously with a next clock cycle of the fast clock after the reset. Then, the clock generator continues to generate new clock cycles of the PWM clock at the configured PWM clock frequency. In one embodiment, the load transient detection circuit furthermore asserts a non-switching mode control signal responsive to the detecting a decrease in load demand. Responsive to the non-switching mode being asserted, the PWM controller enters a non-switching mode. In non-switching mode, the PWM controller monitors feedback signals from the power converter and returns to switching mode synchronously with the fast clock when a sensed output voltage drops below a threshold voltage. 
     In a second aspect, a controller circuit for a switching regulator controls operation of a power converter. A PWM controller is configured to receive a PWM clock and generate a PWM control signal based on the PWM clock for controlling switching of a power converter. A load transient detection circuit is configured to detect an increase in load that exceeds a detection threshold and output a load transient detection signal to a clock generator. The clock generator receives a fast clock and generates the PWM clock having a slower frequency than the fast clock. In response to detecting the increase in load, the clock generator resets the PWM clock synchronously with the fast clock. 
     In a third aspect, a method controls a switching regulator according to the operating principles described above. 
     The features and advantages described in the specification are not all inclusive and, in particular, many additional features and advantages will be apparent to one of ordinary skill in the art in view of the drawings, specification, and claims. Moreover, it should be noted that the language used in the specification has been principally selected for readability and instructional purposes, and may not have been selected to delineate or circumscribe the inventive subject matter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The teachings of the embodiments of the present invention can be readily understood by considering the following detailed description in conjunction with the accompanying drawings. 
         FIG. 1A  illustrates a typical switching regulator. 
         FIG. 1B  illustrates typical waveforms associated with operation of a typical switching regulator. 
         FIG. 2  illustrates a switching regulator according to one embodiment of the present invention. 
         FIG. 3  illustrates a clock generator according to one embodiment of the present invention. 
         FIG. 4  illustrates example waveforms associated with operation of the switching regulator, according to one embodiment of the present invention. 
         FIG. 5  illustrates example waveforms associated with operation of the switching regulator, according to one embodiment of the present invention. 
         FIG. 6A  is a circuit diagram modeling input errors of a comparator and error amplifier circuit. 
         FIG. 6B  illustrates example waveforms illustrating the effect of varying input errors associated with different devices. 
         FIG. 7  is a circuit diagram illustrating a combined error amplifier/comparator, according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The Figures (FIG.) and the following description relate to preferred embodiments of the present invention by way of illustration only. It should be noted that from the following discussion, alternative embodiments of the structures and methods disclosed herein will be readily recognized as viable alternatives that may be employed without departing from the principles of the claimed invention. 
     Reference will now be made in detail to several embodiments of the present invention(s), examples of which are illustrated in the accompanying figures. It is noted that wherever practicable similar or like reference numbers may be used in the figures and may indicate similar or like functionality. The figures depict embodiments of the present invention for purposes of illustration only. One skilled in the art will readily recognize from the following description that alternative embodiments of the structures and methods illustrated herein may be employed without departing from the principles of the invention described herein. 
     As will be explained in more detail below with reference to the figures, a switching regulator, controller, and a method according to various embodiments of the present invention provides regulated power to a load with improved transient response relative to conventional architectures. In one embodiment, the switching regulator detects light to heavy load transients exceeding a detection threshold and resets a PWM clock synchronously with a fast clock operating at a higher frequency than the PWM clock. Furthermore, when operating in non-switching mode, the PWM controller can return to switching mode synchronously with the fast clock. By doing so, the switching regulator beneficially responds more quickly to changes in the load because it can adjust to the transient synchronously with the faster clock rather than with the slower PWM clock. This provides improved transient response without sacrificing the power efficiency generally resulting from a slower switching frequency. 
       FIG. 2  illustrates a switching regulator  200  in accordance with one embodiment of the present invention. Switching regulator  200  comprises converter  202 , current sensor  208 , error amplifier  204 , first comparator  206 , second comparator  214 , clock generator  210 , Pulse Width Modulation (PWM) controller  212 , a voltage divider comprising resistors R 1  and R 2 , and an output filter comprising resistor R 3  and capacitors C 2 , C 3 . Other conventional circuit components are omitted from the figure for clarity of description. 
     Converter  202  receives supply voltage V IN  and provides regulated output voltage V OUT  to load  214 . In one embodiment, converter  202  comprises inductor L 1 , diode D 1 , capacitor C 1 , and switch Q 1  (e.g., an NMOS transistor) arranged in a conventional boost converter configuration. When switch Q 1  turns on, current increases through inductor L 1 . The input power from supply voltage V IN  is stored in inductor L 1  because diode D 1  becomes reverse biased and output power is provided to load  214  via capacitor C 1 . When switch Q 1  turns off, diode D 1  becomes forward biased and the input power stored in inductor L 1  is transferred to V OUT . Output voltage V OUT  provides power to the load and charges the output capacitor C 1 . Switching of Q 1  is controlled by control signal PWM_CTRL according to a PWM technique in order to maintain V OUT  at a desired voltage. 
     While converter  202  is illustrated and described as a boost converter, other types of conventional converters may alternatively be used. For example, in various embodiments, converter  202  may comprise a buck converter, a buck-boost converter, a flyback converter, or another conventional type of converter. 
     PWM controller  212  receives voltage feedback V FB , current feedback I FB , and input clock PWM_CLK, and NO_SWITCH, and generates PWM control signal PWM_CTRL to control switching of converter  202  via a PWM technique. In PWM, the output power of converter  202  is controlled by varying the widths of the pulses driving switch Q 1 . In one embodiment, PWM controller  212  can operate in either a switching mode or a non-switching mode (or sleep mode) based on a mode control input NO_SWITCH. In switching mode, PWM controller  212  controls the duty cycle of PWM_CTRL in order to stabilize V OUT  at a substantially constant voltage as described below. In non-switching mode, PWM controller  212  turns off switching (i.e., sets the duty cycle of PWM_CTRL to 0%). Non-switching mode is useful as a power saving mechanism during the transient period when the load demand decreases, i.e., the load changes from heavy to light. 
     In one embodiment, PWM controller  212  utilizes a current mode control technique to control the duty cycle of PWM_CTRL when in switching mode. In current mode control operation, the PWM controller  212  utilizes both current and voltage feedback signals (I FB  and V FB  respectively) to maintain output voltage V OUT  at a desired level and limit the peak current through PWM switch Q 1 . The frequency of the pulses in PWM_CTRL is controlled by PWM_CLK such that PWM controller  204  generates one pulse in PWM_CTRL for each clock cycle of PWM_CLK (e.g., on the rising edge of PWM_CLK). Widths of the pulses in PWM_CTRL are varied based on control signal V FB  and I FB  in order to maintain V OUT  at a substantially constant level when the load demand is stable, and limit current through PWM switch Q 1  to a peak current level. In non-switching mode, the duty cycle of PWM_CTRL is set to 0% and switching is effectively turned off. 
     Voltage feedback signal V FB  and current feedback signal I FB  are utilized by PWM controller  212  to regulate the duty cycle of PWM_CTRL. To produce voltage feedback signal V FB , output voltage V OUT  is sensed and an error signal V FB  is generated representing the difference between the sensed voltage and a reference voltage. In one embodiment, resistors R 1 , R 2  are coupled to V OUT  in a voltage divider configuration. The voltage divider produces a sensed voltage V SENSE  proportional to V OUT . V SENSE  is coupled to a first input terminal (e.g., a negative input terminal) of error amplifier  204 . A first reference voltage V REF     —     A  is coupled to a second input terminal (e.g., a positive input terminal) of error amplifier  204 . Error amplifier  204  outputs error signal V FB  proportional to the difference between V SENSE  and V REF . Thus, if V OUT  begins to drop during a transient state (e.g., due to increased load demand), error signal V FB  increases, and PWM controller  212  will increase the duty cycle of PWM_CTRL. Similarly, if V OUT  begins to rise during a transient state (e.g., due to decreased load demand), error signal V FB  decreases and PWM_CTRL will decrease the duty cycle of PWM_CTRL. Thus, V FB  represents changes to the load because V FB  will rise when the load is changing from light to heavy, and V FB  will fall when the load is changing from heavy to light. When the load is stable, PWM controller  212  acts to maintain V FB  at a substantially constant voltage. Resistor R 3  and capacitors C 2 , C 3  are configured in an integrator configuration as an output filter to stabilize V FB . 
     In a current feedback path, current sensor  208  senses the current through PWM transistor Q 1  using any conventional current sensing technique and generates a feedback voltage I FB  representing the sensed current. I FB  is provided as a feedback signal to PWM controller  212  and utilized to allow PWM controller  212  to limit the peak current through PWM switch Q 1 . 
     A load transient detection circuit detects light to heavy load transients in switching regulator  200 . In one embodiment, the load transient detection circuit comprises first comparator  206  that compares V REF     —     A  to V SENSE  and outputs comparison signal LT_DETECT. LT_DETECT indicates whether the sensed voltage (proportional to V OUT ) is higher or lower than V REF     —     A . Thus, a rising edge of LT_DETECT indicates a load transient from a lighter load to a heavier load that exceeds a detection threshold. Beneficially, LT_DETECT will respond to a light to heavy load transient relatively fast compared to V FB . V FB  responds relatively slowly to changes in the load because it is a stabilized output. In contrast, LT_DETECT will be asserted almost immediately when V SENSE  falls below V REF     —     A . LT_DETECT is outputted to clock generator  210  as utilized as described below. 
     Clock generator  210  is configured to receive LT_DETECT from first comparator  206  and to receive an input clock FAST_CLK. Clock generator  210  generates a new clock PWM_CLK that is slower than FAST_CLK. For example, PWM_CLK may run 20-30 times slower than FAST_CLK. By monitoring LT_DETECT, clock generator  210  detects when V SENSE  falls below a detection threshold (represented by V REF A ) and applies a reset to PWM_CLK on the next cycle of FAST_CLK. For example, in one embodiment, CLK generator  210  applies the reset upon detection of a rising edge of LT_DETECT, i.e., when the load transient detection circuit detects a transition from a lighter load to a heavier load that exceeds a detection threshold (such that V SENSE  drops below V REF     —     A ). 
     When the reset occurs, PWM_CLK begins a new clock cycle and then continues to operate with the same clock frequency during steady state operation (i.e., when the load is stable). Thus, the reset effectively applies a phase shift to PWM_CLK. By resetting PWM_CLK synchronously with FAST_CLK when a load transient is detected, switching regulator  200  beneficially responds to the transient more quickly. Thus, in the worst case scenario, switching regulator  200  begins adjusting to the transient within one clock period of FAST_CLK rather than the longer period of PWM_CLK. However, during steady state operation, switching regulator  200  still switches according to the slower PWM_CLK for improved power efficiency. Thus, relative to conventional regulators, switching regulator  200  provides improved transient response without sacrificing power efficiency. 
       FIG. 3  illustrates a more detailed embodiment of clock generator  210 . In the illustrated embodiment, clock generator  210  comprises clock divider  302  and reset logic  304 . Clock divider  302  receives FAST_CLK and generates PWM_CLK having a slower clock frequency than FAST_CLK. Clock divider  302  also receives a reset signal (RESET) that when asserted, restarts CLK_OUT on the next cycle of FAST_CLK. 
     Reset logic  304  comprises digital logic for generating the reset signal when reset conditions are met. For example, reset logic  304  may be configured to detect a rising edge of LT_DETECT and generate the reset signal upon the detection. 
       FIG. 4  is a waveform diagram illustrating an example operation of first comparator  206 , clock generator  210 , and PWM controller  212  in response to an increase in load demand. In the illustrated waveforms, PWM_CLK operates at a constant frequency 4 times slower than FAST_CLK (in practice, PWM_CLK and FAST_CLK may have a different frequency ratio. For example, PWM_CLK may be 20 to 30 times slower than FAST_CLK). Between time t 0  and t 1 , V SENSE  is above V REF     —     A  and LT_DETECT is therefore low. At time t 1 , V SENSE  drops below V REF  (e.g., due to an increase in load demand) and LT_DETECT is asserted. Clock generator detects the rising edge of LT_DETECT, and at the start of the next cycle of FAST_CLK following t 1 , clock generator  210  resets PWM_CLK. Thus, a new cycle of PWM_CLK begins synchronously with the next cycle of FAST_CLK following t 1 . Following the reset, PWM_CLK continues to operate at its configured frequency (e.g., 4 times slower than FAST_CLK). PWM_CTRL therefore adjusts its duty cycle to compensate for the increase in load demand synchronously with FAST_CLK rather than needing to wait for a full cycle of the slower PWM clock to complete. As a result, converter  202  can stabilize V OUT  faster and power converter  202  will exhibit improved transient response compared to conventional architectures. 
     Referring back to  FIG. 2 , operation of non-switching mode is now described. A switch mode control circuit generates NO_SWITCH to toggle PWM controller  212  between switching mode and non-switching mode. Generally, during steady-state operation (i.e., no load transients are present), NO_SWITCH configures PWM controller  212  to operate in switching mode. However, when the switch mode control circuit detects a change in load demand from a heavier load to a lighter load (i.e., V FB  falls below a detection threshold), NO_SWITCH controls PWM controller  212  to enter non-switching mode. The PWM controller returns to switch mode once V OUT  is substantially stabilized. 
     In one embodiment of the switch mode control circuit, second comparator  214  compares error signal V FB  to a second reference voltage V REF     —     B  and produces a switching mode control output NO_SWITCH indicating whether V FB  is higher or lower than V REF     —     B . Generally, V REF     —     B  is set such that NO_SWITCH will be low during steady state operation, and PWM controller  212  will operate in switching mode. When the load becomes lighter, V SENSE  increases with respect to V REF A , thereby decreasing V FB  with respect to V REF     —     B . If V FB  drops below V REF     —     B  comparator  214  asserts NO_SWITCH, causing PWM controller  212  to enter non-switching mode. In one embodiment, PWM controller may be configured to enter switching mode synchronously with the fast clock rather than the slower PWM clock. Once in non-switching mode, V OUT  will begin to drop, thereby increasing V FB  with respect V REF     —     B . When V FB  rises above V REF     —     B , NO_SWITCH resets causing PWM controller  212  to return to switching mode operation. 
     In one embodiment, PWM controller  212 , when in non-switching mode, monitors LT_DETECT and returns to switching mode when a rising edge of LT_DETECT is detected. As described above, feedback signal V FB  responds relatively slowly to changes in V OUT  as compared to LT_DETECT because V FB  is stabilized by the output filtering. Thus, as V OUT  decreases in non-switching mode, LT_DETECT may be asserted as soon as V SENSE  falls below V REF A  and before NO_SWITCH turns off. The PWM controller  212  thus detects when LT_DETECT is asserted and returns PWM controller  212  to switching mode. Furthermore, because PWM_CLK will also be reset upon assertion of LT_DETECT, PWM controller  212  will return to switching mode synchronously with the next cycle of FAST_CLK. 
       FIG. 5  is a waveform diagram illustrating the switching mode control operation described above when the load demand decreases. Between t 0  and t 1 , V FB  decreases in response to the decrease in the load demand. At time t 1 , V FB  drops below V REF     —     B  and NO_SWITCH is asserted causing PWM controller  212  to enter non-switching mode. As illustrated, no output pulses are generated on PWM_CTRL while PWM controller  212  is in non-switching mode. Once in non-switching mode, V OUT  will eventually begin to fall back down and V FB  will rise. At time t 2 , LT_DETECT is asserted because V SENSE  falls below V REF     —     A . When PWM controller  212  detects the rising edge of LT_DETECT, PWM controller  212  returns to switching mode. At the same time, clock generator  210  resets the PWM_CLK on the next cycle of FAST_CLK as described above. PWM controller  212  then continues to operate in switching mode. Thus, the PWM controller  212  enter switching mode synchronously with FAST_CLK instead of waiting for V FB  to rise above V REF     —     B  (and NO_SWITCH to reset) at time t 3 . Instead, the PWM controller  212  enters switching mode based on the rising edge of LT_DETECT, which has a faster response time than V FB . As a result, converter  202  will be able to stabilize V OUT  in response to the load transient more quickly compared to conventional architectures. 
     Although error amplifier  204  and first comparator  206  are illustrated as separate devices for clarity of description, in one embodiment, a combined error amplifier/comparator may be used in order to alleviate potential imprecision associated with varying intrinsic characteristics of separate devices. As illustrated in  FIG. 6A , different intrinsic device characteristics of a comparator  602  and error amplifier  604  are modeled as input errors E 1  and E 2  on the reference voltage input V REF     —     A .  FIG. 6B  is a waveform diagram illustrating the effect of the input errors. As can be seen, comparator  602  effectively compares V SENSE  to an offset reference voltage V REF     —     A +E 1  while error amplifier  604  effectively compares V SENSE  to a different offset reference voltage V REF     —     A +E 2 . As a result, the comparator  602  may detect load transients earlier than, or later than, desired depending on the magnitude of the input errors E 1 , E 2 . 
       FIG. 7  illustrates a combined error amplifier/comparator  706  that outputs both LT_DETECT and the error amplifier output V FB . Rather than use separate internal transistors to implement the comparator  206  and the error amplifier  204 , the combined error amplifier/comparator  706  uses the comparator transistors internal to the error amplifier to generate LT_DETECT. For example, in one embodiment, the combined error amplifier/comparator  706  comprises a conventional error amplifier for generating error signal V FB , and additionally includes a buffer that buffers V FB  to produce comparator output LT_DETECT. In this manner, any input error E affecting V REF     —     A  will affect V FB  and LT_DETECT equally, thus eliminating the error offset problem described above. 
     Thus, the switching regulator of the present invention beneficially utilizes a fast clock to adjust PWM control to load transients, while using a slower PWM clock for steady-state switching. As a result, the switching regulator responds more quickly to changes in the load than with conventional architectures that utilize only the slower PWM clock. Beneficially, the switching regulator therefore provides improved transient response without sacrificing the power efficiency. 
     Upon reading this disclosure, those of skill in the art will appreciate still additional alternative designs for a switching voltage regulator having the features described herein. Thus, while particular embodiments and applications of the present invention have been illustrated and described, it is to be understood that the invention is not limited to the precise construction and components disclosed herein and that various modifications, changes and variations which will be apparent to those skilled in the art may be made in the arrangement, operation and details of the method and apparatus of the present invention disclosed herein without departing from the spirit and scope of the invention as defined in the appended claims.