Patent Publication Number: US-11023230-B2

Title: Apparatus for calculating and retaining a bound on error during floating-point operations and methods thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 15/811,617 (now U.S. Pat. No. 10,540,143) that was filed on Nov. 13, 2017, which is a continuation-in-part of U.S. patent application Ser. No. 15/331,901 (now U.S. Pat. No. 9,817,662) filed on Oct. 23, 2016, which claimed the benefit of Provisional Patent Application No. 62/246,021 filed on Oct. 24, 2015, U.S. Provisional Patent Application No. 62/277,137 filed on Jan. 11, 2016, and U.S. Provisional Patent Application No. 62/375,422 filed on Aug. 15, 2016, all of which are incorporated herein in their entirety. A related application is PCT/US16/58551 filed on Oct. 24, 2016. 
    
    
     FIELD OF INVENTION 
     This invention relates generally to logic circuits that perform certain floating-point arithmetic operations in a processing device and, more particularly, a bounded floating-point unit that calculates and retain a bound on error introduced through alignment and normalization. 
     BACKGROUND OF THE INVENTION 
     In the design of floating-point arithmetic systems for use in a floating-point processing device, it is desirable that results are consistent to achieve conformity in the calculations and solutions to problems even though the problems are solved using different computer systems. 
     An American national standard has been developed in order to provide a uniform system of rules for governing the implementation of floating-point arithmetic systems. This standard is identified as IEEE Standard No. 754-2008 and international standard ISO/IEC/IEEE 60599:2011, which are both incorporated by reference herein. The standard specifies basic and extended floating-point number formats, arithmetic operations, conversions between integer and floating-point formats, conversions between different floating-point formats, and conversions between basic format floating-point numbers and decimal strings, and the handling of certain floating-point exceptions. 
     The typical floating-point arithmetic operation may be accomplished using formats of various (usually standard) widths (for example, 32-bit, 64-bit, etc.). Each of these formats utilizes a sign, exponent and fraction field (or significand), where the respective fields occupy predefined portions of the floating-point number. For example, in the case of a 32-bit single precision number the sign field is a single bit occupying the most significant bit position; the exponent field is an 8-bit quantity occupying the next-most significant bit positions; the fraction field occupies the least significant 23-bit positions. Similarly, in the case of a 64-bit double precision number the sign field is a single bit, the exponent field is 11 bits, and the fraction field is 52 bits. Additional formats provide the same information, but with varied field widths, with larger field widths providing the potential for greater accuracy and value range. 
     After each floating-point result is developed, it must be normalized and then rounded. When the result is normalized, the number of leading zeros in the fraction field is counted. This number is then subtracted from the exponent, and the fraction is shifted left until a “1” resides in the most significant bit position of the fraction field. Certain floating-point answers cannot be normalized because the exponent is already at its lowest possible value and the most significant bit of the fraction field is not a “1.” This is a “subnormal number” with fewer significant digits than a normalized number. 
     In designing the circuits for performing floating-point arithmetic operations in conformance with this standard, it is necessary and desirable to incorporate certain additional indicator bits into the floating-point hardware operations. These indicator bits are injected into the fraction field of the floating-point number and are used by the arithmetic control circuit to indicate when certain conditions exist in the floating-point operation. In non-subnormal (normalized) numbers, for example, an “implicit” bit (generally referred to as the “hidden bit”) is created by the arithmetic control circuit when the exponent of the floating-point number has a nonzero value. This “hidden bit” is not represented in the storage format but is assumed. It is inserted at the time a floating-point number is loaded into the arithmetic registers and occupies the most significant bit position of the fraction field of the number. During addition, a single “guard” bit is set by the floating-point control circuit during certain arithmetic operations, as an indicator of the loss of significant bits of the floating-point number being processed. The guard bit is set when a right shift, required for normalization, shifts a bit from the right side of the fraction field capacity. The guard bit occupies a portion of the fraction field. Finally, a “sticky” bit is set in certain floating-point arithmetic operations as an indicator that the floating-point number has lost some significant bits. 
     These extra bits in the fraction field are used exclusively for rounding operations, after the result has been normalized. The guard bit is treated as if it is a part of the fraction and is shifted with the rest of the fraction during normalization and exponent alignment and is utilized by the arithmetic. The sticky bit is not shifted with the fraction but is utilized by the arithmetic. It acts as a “catcher” for bits shifted off the right of the fraction; when a 1 is shifted off the right side of the fraction, the sticky bit will remain a 1 until normalization and rounding are finished. 
     There are typically four modes of rounding, as follows: (1.) round to nearest; (2.) round to positive infinity; (3.) round to negative infinity; and (4.) round to zero. Each of these may introduce error into the calculation. 
     Though this standard is widely used and is useful for many operations, this standard defines “precision” as the maximum number of digits available for the significand of the real number representation and does not define precision as the number of correct digits in a real number representation. Neither does this standard provide for the calculation and storage of error information and therefore permits propagation of error including the potential loss of all significant bits. These problems in the current standard can lead to substantial accumulated rounding error and catastrophic cancellation error. Cancellation occurs when closely similar values are subtracted, and it injects significant error without a corresponding indication of this error in the result. 
     Various authors have contributed to the standard or noted these significant problems, but the problem persists. 
     U.S. Pat. No. 3,037,701 to Sierra issued in 1962 establishes the basis for hardware to perform fixed word length floating-point arithmetic including normalization, rounding, and zero conversion. The Sierra patent describes the potential for introducing error in floating-point operations including total loss of useful information. No method is described for calculating or retaining error information of any type. 
     In 2010, in his book  Handbook of Floating - Point Arithmetic , Muller et al. describe the state-of-the-art of the application of floating-point including the ISO/IEC/IEEE 60599:2011 and describe error problems. They state, “Sometimes, even with a correctly implemented floating-point arithmetic, the result of a computation is far from what could be expected.” 
     In 1991, David Goldberg, in “What Every Computer Scientist Should Know About Floating-Point Arithmetic,” provides a detailed description and mathematical analysis of floating-point error. This paper describes rounding error (p. 6), relative error and error units in the last place (Ulps) (p. 8), the use of guard digits (p. 9), and cancellation error types, both catastrophic and benign (p. 10). Recommended error mitigation is limited to extending precision (again defined as digits available for real number representation) requiring additional storage space for computational results (p. 17) and numerical error analysis of a given problem to determine the method of computation to minimize and limit the error introduced by the computation. 
     Thus, many authors have acknowledged the existence of these types of errors in the current standard for floating-point operations. In response, numerous attempts to address these significant problems have been made. 
     In 2012 in the article “Floating-Point Numbers with Error Estimates,” Glauco Masotti describes adding a data structure to standard floating-point format to contain statistical estimates of the accumulated floating-point error. This technique increases required storage space, adds computation time, and does not provide bounds for the error. 
     In 2008 in “The Pitfalls of Verifying Floating-Point Computations,” David Monniaux presents the limitations on static program analysis to determine the expected error generated by code to perform a sequence of floating-point operations. However, static error analysis is prone to error and relies on and assumes a lengthy and expensive algorithm error analysis to ensure that the algorithm will provide sufficiently accurate results. 
     In summary, the current state-of-the-art does not retain error information within the associated floating-point data structure. At present, any retention of bounds on floating-point error requires significantly more memory space and computation time (or correspondingly more hardware) to perform error interval computations. 
     Further, in the current standard, when two values are compared by subtraction in which cancellation occurs, program flow decisions based on this erroneous comparison can result in an incorrect decision. No validity of the resulting comparison is provided by the standard conventions. 
     Importantly, the standard provides no indication when the result of a computation no longer provides a sufficient number of significant digits. 
     Additionally, conversion from external to internal format or conversion between floating-point formats may inject an error in the initial representation of a real number without recording that error. 
     Further, floating-point values are converted to external representation without indication of loss of significant bits even if no significant bits remain in the output data. 
     Notably, current technology does not permit allowing programmers to specify the number of required retained significant digits. 
     Thus, the various methods provided by the current art for floating-point error mitigation have unresolved problems. Accordingly, there is a need for an apparatus and method for calculating and retaining a bound on error during floating-point operations. 
     The discussion above is merely provided for general background information and is not intended to be used as an aid in determining the scope of the claimed subject matter. 
     SUMMARY OF THE INVENTION 
     The present invention is directed to a bounded floating-point processing device, to a processing system including a bounded floating-point processing device, and to associated methods for calculating and retaining a bound on error during floating-point operations by the insertion of an additional bounding field into the ANSI/IEEE 754-2008 standard floating-point arithmetic format. This bound B Field has two major parts, the lost bits field (D Field) and the accumulated rounding error field (N Field). The N Field is subsequently divided into the rounding bits field (R Field) and the rounding error count field (C Field), representing the sum of the carries from the sum of the R Fields. The lost bits D Field is the number of bits in the floating-point representation that are no longer significant. The bounds on the real value represented are determined from the truncated (round to zero) floating-point value (first bound) and the addition of the error determined by the number of lost bits (second bound). By a special command this lost bits D Field is compared to the unacceptable loss of significant bits to provide a fail-safe, real-time notification of the loss of significant bits. This field may be used to limit the external representation of represented real value to the actual significant digits. 
     The C Field of the floating-point format of the present invention, which is the sum of the carries from the sum of the R Fields. (The term “field” refers to either a portion of a register or the value of that portion of structure register, unless otherwise contextually defined.) When the logarithm of the extension count exceeds the current lost bits, one is added to the lost bits and the C Field is set to zero. However, when the logarithm of the extension count exceeds the capacity of the C Field, the carry out of the C Field is added to the lost bits. The R Field is the sum of the rounded most significant bits of the rounding error, lost during truncation. 
     The apparatus and method of the current invention can be used in conjunction with the apparatus and method implementing the current floating-point standard. Conversion between the inventive format and the current format can be accomplished when needed; therefore, existing software that is dependent upon the current floating-point standard need not be discarded. The new bounding field is inserted into the conventional floating-point standard to provide accumulated information for the bound of the error that delimits the real number represented. 
     Current standards for floating-point have no means of measuring and/or recording floating-point rounding and cancellation error. The present invention provides an apparatus and method that classifies (as acceptable or as not acceptable) the accumulated loss of significant bits resulting from a floating-point operation. This is accomplished by comparing the loss of significant bits of the current operation against the unacceptable limit of the loss of significant bits. The unacceptable limits for different widths of floating-point numbers can be provided in two ways, hardware or programmable. The hardware provides a default value. For example, in single precision (32-bit), the default value could require 3 significant decimal digits, which necessitates that the significand retains 10 significant bits. In a 64-bit double precision example, the default value could require 6 significant decimal digits, which necessitates that the significand retains 20 significant bits. The second way to provide the unacceptable limit is by a special floating-point instruction that sets the limit on the error bound for the specified precision. The current invention provides a means of measuring, accumulating, recording, and reporting these errors, as well as allowing the programmer to assert an exception to provide real-time notification of an unacceptable amount of error. 
     This is an advantage over the current technology that does not permit any control on the allowable error. The current invention not only detects the loss of significant bits, but optionally allows the number of required retained significant digits to be specified with an error limit set/check command. 
     When the loss of significant bits is greater than or equal to the unacceptable limit, an inventive signaling NaN that signals insufficient significant bits, termed “sNaN(isb),” is generated indicating that the result does not have the required number of significant bits. This contrasts with the current technology, which does not provide an indication when the result of a computation no longer provides a sufficient number of significant bits. 
     In contrast to the conventional floating-point standard, which does not retain error information within the associated floating-point data structure, the present invention provides error information in the lost bits D Field within the floating-point data structure. Two bounds are provided. The first bound is the real number represented by the exponent and the truncated significand, and the second bound is determined by adding to the first bound a maximum error value represented by the lost bits D Field. 
     Using current technology, error can be reduced by increasing computation time and/or memory space. The present invention provides this error information within the inventive data structure with little impact on space and performance. 
     In the standard floating-point implementation cancellation injects significant error without a corresponding indication in the result. In contrast, the present invention accounts for cancellation error in the lost bits D Field. 
     The instant invention provides a method of recording the error injected by the conversion of an external representation to the inventive internal representation (or of recording the error in conversion between internal representations). 
     Currently floating-point values are converted to external representation without indication of loss of significant digits even when no significant bits exist. In contrast, the current invention provides the inventive quiet Not-a-Number, qNaN(isb), when insufficient significant bits remain when converting to external representation; the external representation displays indicia (such as qNaN(isb)) that indicates to the viewer that insufficient significant bits remain. And, in the current invention, when sufficient significance is retained, it is then possible to provide an external representation of the real number represented that is absolutely accurate to the last digit. 
     In the current art, static error analysis requires significant mathematical analysis and cannot determine actual error in real time. This work must be done by highly skilled mathematician programmers. Therefore, error analysis is only used for critical projects because of the greatly increased cost and time required. In contrast, the present invention provides error computation in real time with, at most, a small increase in computation time and a small increase in the required memory or a decrease in the maximum number of bits available for the significand. 
     The dynamic error analysis by means of error injection, used in the current technology, has similar problems requiring multiple executions of algorithms that require floating point. Such techniques would be of little use when using adaptive algorithms or when error information is required in real time. The present invention eliminates the need for multiple executions and provides error information in real time but allows for stress testing of algorithms by operating the application software with successively larger precision requirements to determine failure points and the available precision at that failure point. 
     Adding additional storage to retain statistical information on error, which is a commonly proposed solution, significantly increases computation time and required storage. The present invention makes a slight increase in the required memory space or a slight decrease in the maximum number of bits available for the significand for real number representation in order to accommodate space for error information. 
     Though interval arithmetic provides a means of computing bounds for floating-point computations, it requires greatly increased computation time and at least twice as much storage. In contrast, the present apparatus for calculating and retaining a bound computes both the first and second bounds on the real number represented and does this within the execution of a single instruction. The computed bounds are failsafe. 
     An object of the present invention is to bound floating-point error when performing certain floating-point arithmetic operations in a floating-point processing device. 
     These and other objects, features, and advantages of the present invention will become more readily apparent from the attached drawings and from the detailed description of the preferred embodiments which follow. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The preferred embodiments of the invention will hereinafter be described in conjunction with the appended drawings, provided to illustrate and not to limit the invention, where like designations denote like elements. 
         FIG. 1  is a diagram of the inventive bounded floating-point format showing the new bound B Field of the present invention which is composed of the lost bits D Field and the N Field, where the N Field is, in turn, composed of the C Field and the R Field. 
         FIGS. 2A-2B  is a diagrammatic example of the circuit and control logic of the floating-point operation showing the inventive error bounding of an exemplary addition or subtraction operation. 
         FIG. 3  is a circuit diagram for the calculation of the exponent that provides information utilized in the inventive bound logic of  FIGS. 2A, 4, and 7 . 
         FIG. 4  is a circuit diagram for the inventive dominant bound logic and control of the error bounding of the present invention. 
         FIG. 5  is a diagram of the format of the post normalization result derived from  FIG. 7  that will contribute to the determination of the inventive bound B Field. 
         FIGS. 6A-6B  is a circuit diagram of the inventive main bound computation circuit and control logic of the present invention that provides information used in  FIG. 2B  and  FIG. 8 . 
         FIG. 7  is a circuit diagram of the normalization circuit and control logic that produces a normalized result that will contribute to the determination of the inventive bound B Field and is used in  FIGS. 2B, 6A, and 6B . 
         FIG. 8  is a circuit diagram of the inventive exception circuit and control logic that determines if the error boundary has been exceeded, which generates the inventive sNaN(isb) and also determines if the result is significantly zero. 
         FIG. 9  is a block diagram of the bounded floating-point system  900 . 
     
    
    
     Like reference numerals refer to like parts throughout the several views of the drawings. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Shown throughout the figures, the present invention is directed toward a bounded floating-point system  900  including a bounded floating-point processing unit (BFPU)  950  and method for calculating and retaining a bound on error during floating-point operations, an example of which is shown generally as reference number  200  ( FIGS. 2A-2B ). In contrast to the standard floating-point implementation that introduces error without notification or warning, the present bounded floating-point format  100  provides a new error bound B Field  52  ( FIG. 1 ) that identifies and records a bound on the error and enables detection and notification of loss of significant bits via an inventive error limit set/check command  901  that generates sNaN(isb)  262  signal, when insufficient significant bits remain. 
     Using the current floating-point standard, error can be introduced during alignment or normalization. In the inventive apparatus and method, normalization during subtract and other floating-point operations can still result in the loss of significant bits, such as through cancellation. When this loss is significant in the current computation, this loss is recorded in the bound on the number of lost significant bits, which is termed the “result bound lost bits D”  54 F ( FIG. 8 ) stored in the lost bits field, the D Field  54 . 
     The circuitry for determining loss of significant bits may contain a programmable bound limit memory circuit  802  to allow user determination of the number of significant bits required by the user resulting from a floating-point calculation. The bound limit memory circuit  802  contains a default value for each precision floating-point width and can be programmed by the user. 
     When the inventive bounded floating-point format  100  is implemented, it can be used concurrently with implementations of the current floating-point standard. Therefore, existing software that is dependent upon the current floating-point standard need not be discarded. 
     The new bound B Field  52  is added to the conventional floating-point standard to provide accumulated information on the bound of error that delimits the real number represented. 
       FIG. 1  provides a virtual bitwise layout of the bounded floating-point format  100  for word width of width k  101  showing the inventive bound B Field  52  (having a width b  103 ), which is composed of two parts, the lost bits D Field  54  (having a width d  105 ) and the N Field  55  (having a width n  106 ), as well as the standard floating-point format fields. The N Field  55  is further composed of two fields, the C Field  56  (having a width c  107 ) and the R Field  57  (having a width r  108 ). The standard fields include the sign bit field, which is the S Field  50 , the exponent E Field  51  (having a width e  102 ), and the significand field, which is the T Field  53  (having a width t  104 ). 
     This bound B Field  52  is a new field added to the floating-point standard format to provide accumulated information on the bound of the represented real number. The bound B Field  52  accounts for both rounding and cancellation errors. This bound B Field  52  keeps track of the loss of significant bits resulting from all previous operations and the current operation. Recording this loss of significant bits then allows a determination to be made as to whether insufficient significant bits have been retained. When an error limit set/check command  901  is issued and a sufficient loss of significant bits occurs, this is signaled to the main processing unit  910  by the sNaN(isb) exception  950  signal. ( FIG. 8 ). The exception and result multiplexer  270  selects between the calculated result  260  and the bounded floating-point representation of zero  261  as determined by the zero-selection control signal  860  ( FIG. 8 ). The bounded floating-point representation of zero  261  is identical to the standard representation where all fields S  50 , E  51 , and T  53  are set to zero, but the bound field B  52  is also set to zero. The exception and result multiplexer  270  provides the bounded floating-point result  280  stored in the final result register  285 . 
     The lost bits D Field  54  ( FIG. 1 ) contains the representation of the number of bits in the floating-point representation that are no longer significant. 
     The N Field  55  is the accumulation of the rounding errors that occur from alignment and normalization. 
     The C Field  56  contains the representation of the sum of the carries out of the R Field  57 R ( FIG. 5 ), which like the R Field  57  has a width r  108 , where the “R” designates the result after normalization. The logical OR of the bits of the extended rounding error X Field  60 R, of width x  502 , which is used instead of the conventional carry and guard bits. The count power circuit  680  is the inventive circuit that determines the lost bits power  61  for the dominant bound lost bits D  54 C as determined by the count field  56  selected by the operation width control  801 . When the value that would be developed by this circuit is greater in width than the width of the C field  56 , c  107 , the value selected is the maximum value that can be represented by the C field. When the floor of the base 2 logarithm of the extension count exceeds the current lost bits, one is added to the lost bits and the C Field is set to zero. However, when the logarithm of the extension count exceeds the capacity of the C Field, the carry out of the C Field is added to the lost bits. ( FIG. 6 ). 
     The R Field  57  contains the sum of the current R  57  and the resulting rounding bits R  57 R ( FIG. 5 ), which is the most significant r  108  bits lost due to truncation of the normalized result  720 . The apparatus and method for calculating and retaining a bound on error during floating-point operations is shown in the exemplary bounded floating-point addition/subtraction circuit  200  shown on the diagram of  FIG. 2A  and continuing onto  FIG. 2B . This diagram provides the circuit and control logic for an exemplary floating-point addition or subtraction operation showing the inventive bounding of the floating-point error (normally caused by alignment and normalization) of the present invention. 
     The bounded floating-point system  900  includes a processing device with a plurality of registers  990  ( FIG. 9 ), a main processing unit  910 , and a bounded floating-point unit (BFPU)  950  that is communicably coupled to the main processing unit  910 . The main processing unit  910  executes internal instructions and outputs at least two types of BFPU instructions, a bounded floating-point arithmetic instruction  930 , or an error limit set/check command  910  to the BFPU  950 . The inventive BFPU  950  is a processing component, which may be a separate component or may be integrated with a physical conventional floating-point component sharing registers and logical circuits with the conventional floating-point unit or the integrated floating-point unit may be integrated with a conventional main processing unit  910  sharing registers  990  and logical circuits with the conventional main processing unit  910 . The main processing unit executes internal instructions accessing data  201 ,  202 ,  280  from, and to, a plurality of registers  990  (where a register may be a hardware register, a location in a register file, or a memory location that may be an integral part of the main processing unit  910 ) and outputs or executes floating-point or bounded floating-point commands  901 ,  930  and outputs or utilizes the data, the first operand  201 , the second operand  202 , the maximum lost bits  54 L, and the operation width control  902 . The first type is a bounded floating-point arithmetic instruction  930 , which instructs the BFPU  950  on the type of arithmetic operation to be performed and provides the two input operands  201 ,  202 . The second type is a bound limit set/check command  901 , which is to set a programmed bound limit in the bound limit memory  810  and to trigger an sNaN(isb) exception  940  if the specified first operand  201  does not have the required significant digits. 
     The arithmetic operation is performed on two input operands  201 ,  202 , which in the example of  FIGS. 2A, 2B , are stored in the first operand conglomerate register  210  and the second operand conglomerate register  220 , respectively. Then the BFPU  950  generates a result value, the bounded floating-point result  280 , from executing the FPU instructions on the bounded floating-point number inputs  201 ,  202 . This bounded floating-point result  280  includes an error bound value obtained from the accumulated cancellation error and the accumulated rounding error. The BFPU  950  also writes the bounded floating-point result  280  to a main processing unit  910  solution register of the plurality of registers  990 , thereby storing the results from the operation of the bounded floating-point unit  950 . 
     The first operand conglomerate register  210  of  FIG. 2A  is the register (where a register may be a hardware register, a location in a register file, or a memory location) with registers that contain the corresponding fields of the first operand  201  in the bounded floating-point format  100 . The first operand sign bit register  1 A is the conventional single bit register that holds the first operand register  201  sign bit. The first operand exponent register  2 A is the conventional register that holds the first operand  201  exponent. The first operand bound register  3 A is the inventive conglomerate register that holds the first operand  201  bound. Though the first operand significand register  4 A exists in conventional registers and holds the first operand  201  significand, it is changed in the invention to hold a foreshortened first operand  201  significand; thus allowing for the new first operand bound register  3 A. Registers utilized by the bounded floating-point unit  950  may be integrated into the bounded floating-point unit  950 , or may be located in other nearby processing structures; for example, they may be part of, and integrated into, a conventional floating-point unit, or may be part of, and integrated into, the main processing unit  910 . 
     The first operand  201  of  FIG. 2A  is the bounded floating-point first addend for an addition operation or is the minuend for a subtraction operation. The first operand  201  includes a first operand sign S value  50 A, a first operand exponent E value  51 A, a first operand bound B value  52 A, and the first operand significand T value  53 A. 
     The second operand conglomerate register operand  220  of  FIG. 2A  is the register (where a register may be a hardware register, a location in a register file, or a memory location) with registers that contain the corresponding fields of the second operand  202  in the bounded floating-point format  100 . The second operand sign bit register is the conventional single bit register that holds the second operand  202  sign bit. The second operand exponent register is the conventional register that holds the second operand  202  exponent. The second operand bound register is the inventive conglomerate register that holds the second operand  202  bound. The second operand significand register is the conventional register that holds the second operand  202  significand foreshortened to allow for the new second operand bound register  3 B. 
     The second operand  202  is the bounded floating-point second addend for an addition operation or is the subtrahend for a subtraction operation. The second operand  202  includes a second operand sign bit S  50 B, a second operand exponent  51 B, a second operand bound B  52 B, and the second operand significand T  53 B. 
     Many circuits within this bounded floating-point addition/subtraction circuit  200  of  FIGS. 2A-2B  are conventional circuits (which are generally denoted by dashed lines), though some results from these conventional circuits are utilized in the inventive apparatus and method. 
     Turning to the exponent circuit  300  of  FIGS. 2A, 3 , the first operand exponent  51 A with the first operand significand  53 A (coming from the first operand  201  of  FIG. 2A ) and the second operand exponent  51 B with the second operand significand  53 B (coming from the second operand  202  of  FIG. 2A ) are compared in the value comparator  301  to determine the largest value control  302 . The largest value control  302  is the control signal that controls the first and second significand swap multiplexers  230 ,  231  ( FIG. 2A ), controls the largest and smallest exponent selection multiplexers  310 ,  311 , and controls the inventive first and second bound swap multiplexers  401 ,  402  ( FIG. 4 ). 
     Additionally, as seen on  FIG. 3 , the largest value control  302  is the control signal identifying the larger of the first operand exponent  51 A or the second operand exponent  51 B and controls the largest exponent selection multiplexer  310 . The largest exponent selection multiplexer  310  selects the largest exponent  51 D from the first operand exponent  51 A and the second operand exponent  51 B controlled by the largest exponent control  302 . The smallest exponent selection multiplexer  311  is also controlled by the largest value control  302  and selects the smallest exponent  51 E from the first operand exponent  51 A and the second operand exponent  51 B. The exponent difference  321  is calculated by the exponent subtractor  320  that subtracts the smallest exponent  51 E from the largest exponent  51 D. The exponent difference  321  controls the alignment shifter  240  ( FIG. 2A ) and in this invention is used unconventionally by the lost bits subtractor  410  by subtracting the exponent difference  321  from the count portion of the smallest operand bound B  52 D to produce the adjusted bound of the operand with smallest exponent B  52 F ( FIG. 4 ). 
     Additionally, as seen on  FIG. 2A , the largest exponent control  302  provides control for the first and second significand swap multiplexers  230 ,  231  ( FIG. 2A ). The first significand swap multiplexer  230  selects from either the first operand significand T  53 A or the second operand significand T  53 B and produces the significand T of the operand with the smallest value E  53 D. Similarly, the second significand swap multiplexer  231  selects the significand T of the operand with the largest value E  53 E from either the first or second operand significands T  53 A,  53 B. 
     The alignment shifter  240  ( FIG. 2A ) shifts the significand T of the operand with the smallest value E  53 D to the right by the number of bits determined by the exponent difference  321  (coming from the exponent circuit  300 ,  FIG. 3 ) to produce the aligned significand  241  (where the aligned significand  241  is the aligned significand T of the operand with the smallest exponent E). Only one bits (not zero bits) shifted out of the alignment shifter  240  causing alignment shift loss  242  are inserted into the least significant bit of the aligned significand  241  ensuring that a significand excess  741  will be detected. 
     The significand adder  250  ( FIG. 2A ) calculates the sum or difference  251  of the aligned significand  241  and the significand T of the operand with the largest value E  53 E. The virtual width v  501  ( FIG. 5 ) of the significand adder is the width of the resulting sum or difference taking into account possible need for multiple additions necessary to accommodate extended bounded floating-point formats. This is an exemplary circuit that represents a conventional arithmetic circuit that calculates arithmetic functions such as multiply, divide, square root, or other arithmetic functions. 
       FIG. 5  provides a detail of the format  500  of the post normalization result, which is the format of the bounded floating-point significand adder result  720  after normalization. This format includes: (1.) the standard hidden bit H Field  510 , the left justified hidden bit H Field  510  after normalization; (2.) the resulting normalized significand T  53 R (t  104  bits in width), the resulting significand after normalization; (3.) the resulting rounding bits R Field  57 R of width r  108  holding the most significant bits of the resulting significand that are lost due to truncation; and (4.) the extended rounding error X Field  60 R of width x  502  containing the bits of the result lost due to truncation, which is to the right of the R Field  57 R in the format. 
     The calculated sum or difference  251  ( FIG. 2A ) is utilized in the normalization circuit  700  of  FIG. 2B , which is expanded on  FIG. 7 . Turning to the details of the normalization circuit  700  of  FIG. 7 , the sum or difference  251  is used by the right shifter  703  or left shifter  712  to arrive at the normalized result  720 . The first control for this determination is the right shift control  702  controlling the right shifter  703 , which is determined by the carry detection  701 . The right shifter  703 , when indicated by the right shift control  702 , shifts the sum or difference  251  right one bit producing the right shift result  704 . The right shift loss circuit  705  is a one bit shifted out of the right shift result  704 . When this occurs, a one bit is inserted into the least significant bit of the right shift result  704  ensuring that a significand excess  741  will be detected. This right shift result  704  is utilized in the left shifter  712 . When the right shift control  702  is not asserted, the right shift result  704  is equal to the sum or difference  251 . 
     Also, in  FIG. 7 , the sum or difference  251  is used in the most significant zeros counter  710 , which is another control. The zeros counter  710  counts the most significant zeros of the sum or difference  251 , which produces the number of leading zeros  711  necessary to normalize the result. The number of leading zeros  711  controls the left shifter  712  by shifting the right shift result  704  left producing the normalized result  720  comprised of the truncated resulting significand T  53 C, the normalized rounding error R  57 A, and the normalized extension X  60 A. If the most significant zeros counter  710  determines that there are no leading zeros, the normalized result  720  is equal to the right shift result  704 . If there is no right or left shift, the value is merely passed through (which occurs if there is no carry and if there are no significant zeros). The number of leading zeros  711  is also used in the exponent normalization adder  730  and is further used in the inventive main bound circuit  600  of  FIG. 2B , which is expanded on  FIG. 6 . 
     Still on  FIG. 7 , the largest exponent  51 D (from  FIG. 3 ) is adjusted for normalization by the exponent normalization adder  730  using the right shift control  702  and the number of leading zeros  711 . 
     The normalized extension X  60 A is derived from the X Field  60 R of the post normalization result format  500  ( FIG. 5 ) of the normalized result  720 . 
     The excess significand detector circuit  740  produces the logical OR of all bits of the normalized extension X  60 A producing the significand excess  741 . The significand excess  741  is utilized by the rounding error adder  640  ( FIG. 6B ) of the inventive main bound circuit  600  ( FIGS. 2B, 6A-6B ). 
     The exponent normalization adder  730  ( FIG. 7 ) adds the right shift control  702 , or subtracts the number of leading zeros  711 , to or from the largest exponent  51 D to produce the result exponent  51 C, which is the exponent in the inventive calculated result  260  of  FIG. 2B . 
     The sign circuit  290  of  FIG. 2B  operates in the conventional manner, determining the result sign bit S  50 C from the operand sign bit S  50 A, the second operand sign bit S  50 B, and the right shift control  702 . 
     Turning to the exemplary diagram  200  of the circuit and control logic of the inventive apparatus and method of  FIG. 2B , the calculated result  260  is created from the concatenation of the result sign bit S  50 C, the result exponent  51 C of  FIG. 7 , the result bound B  52 C of  FIG. 6A , and the truncated resulting significand T  53 C of  FIG. 7 . 
     Turning to the exemplary diagram  200  of the circuit and control logic of the inventive apparatus and method of  FIG. 2A , the first operand bound B  52 A of  FIG. 2A , obtained from the first operand bound register  3 A, the second operand bound B  52 B of  FIG. 2A , obtained from the second operand bound register  3 B the largest value control  302  of  FIG. 3 , and the exponent difference  321  of  FIG. 3  are used in the dominant bound circuit  400  of  FIG. 2A , which is expanded in  FIG. 4 . 
     In an arithmetic operation, the operand with the least number of significant digits determines (“dominates”) the number of significant digits of the result. When, after being aligned, the number of significant bits in one operand is less than the significant bits in the other operand, the significant bits of the operand with fewer significant bits governs or dominates the base significant bits of the result. The dominant bound circuit  400  selects the bound from the initial operands, first operand bound B  52 A and the second operand bound B  52 B, to determine the bound with the most influence on the bound of the result prior to accounting for cancellation and rounding. 
     As seen in the inventive dominant bound circuit  400  of  FIG. 4 , the bounds of both operands (first and second operand bounds B  52 A,  52 B of  FIG. 2A ) are compared—with one bound adjusted before comparison. The dominant bound circuit  400  determines the dominant bound B  5211 . The dominant bound B  5211  is the larger of (1.) the adjusted bound B of the smallest operand  52 F and (2.) the bound of the operand with the largest exponent (largest operand bound B  52 E). This dominant bound B  5211  is the best-case bound of the operand when there is no rounding or cancellation. In an arithmetic operation, the operand with the least number of significant bits after exponent alignment dominates the initial determination of the bound of the result, because the dominant bound B  5211  (from the bounds B  52 F or  52 E, where  52 F is the concatenation of the clamped lost bits D  54 G and the smallest operand bound accumulated rounding error N  55 A) with the largest number of lost bits is this best-case bound. 
     Turning to the details of  FIG. 4 , the first bound swap multiplexer  401 , controlled by the largest value control  302  (from  FIG. 3 ), selects from either the content of the register holding the first operand bound B  52 A or the register holding the second operand bound B  52 B (both from  FIG. 2A ), resulting in the smallest operand bound  52 D to be stored in a register. The second bound swap multiplexer  402 , which is also controlled by the largest value control  302 , selects from either the content of the second operand bound register B  52 B or content of the first operand bound register B  52 A, which results in the largest operand bound B  52 E. 
     The lost bits subtractor  410  is a circuit that subtracts the exponent difference  321  ( FIG. 3 ) from the smallest exponent operand bound lost bits D  54 A, the lost bits portion of the smallest operand bound B  52 D, producing the adjusted smallest exponent operand bound lost bits D  54 B. The adjusted smallest operand bound lost bits D  54 B is concatenated with the smallest exponent operand bound accumulated rounding error N  55 A to form the adjusted bound B of the smallest operand B  52 F. The subtraction may produce a negative adjusted smallest operand bound lost bits D  54 B indicating that there are no significant digits lost during alignment at the alignment shifter  240  ( FIG. 2A ); this case is dealt with via the bound clamp  420 . The bound clamp  420  prohibits the adjusted bound B of the smallest operand B  52 F from underflowing to less than zero. This limits the clamped bound B  52 G to zero or greater. Zero indicates that all the bits of this adjusted operand are significant. 
     The bound comparator  430  compares the largest operand bound B  52 E to the clamped bound B  52 G to determine the dominant bound selection control  431 . This dominant bound selection control  431  is asserted when the largest operand bound B  52 E is greater than the clamped bound B  52 G. The dominant bound selection control  431  is used by the dominant bound multiplexer  440  that selects the dominant bound B  5211  from either the largest operand bound B  52 E or the clamped bound B  52 G and is utilized in the main bound circuit  600  of  FIG. 6A . 
     Turning now to  FIG. 6A , the inventive aggregate main bound circuit  600  determines the result bound B  52 C of the calculated result  260  ( FIG. 2B ) of the current operation. The inputs for this are (1.) the dominant bound B  5211  of  FIG. 4 , (2.) the number of leading zeros  711  (the number of most significant zeros, from  FIG. 7 ), and (3.) the carry adjusted bound B  52 M of  FIG. 6B . The result bound B  52 C is utilized by the calculated result  260  of  FIG. 2B  and the determination of the result bound lost bits D  54 F of  FIG. 8 . 
     In this cancellation path, when shifting right, significant bits may be lost. These lost significant bits must be added to the dominant bound lost bits D  54 C. The dominant bound lost bits D  54 C is the lost bits  54  of the dominant bound B  5211 . This dominant bound lost bits D  54 C is used in the lost bits adder  610 , which adds the number of leading zeros  711  (from  FIG. 7 ) to the dominant bound lost bits D  54 C when the dominant bound lost bits D  54 C are zero indicating that the operand values were precise, resulting in the adjusted lost bits D  54 D. The adjusted lost bits D  54 D is limited to the significand capacity  805  by the first maximum lost bits detector  617  and the first lost bits selector  615  to produce the resulting lost bits D  5411 . 
     The first maximum lost bits detector  616  compares the adjusted lost bits D  54 D against the significand capacity  805  to determine the first maximum lost bits  617  that asserts that the adjusted lost bits D  54 D is greater than the significand capacity  805  to control the first lost bits selector  615 . 
     The first lost bits selector  615  sets the resulting lost bits D  5411  to either the adjusted lost bits D  54 D or the significand capacity  805  depending on the first maximum lost bits  617  clamping the first lost bits selector  615  to no more than the significand capacity  805 . 
     The resulting lost bits D  5411  is concatenated with the dominant bound accumulated rounding error N  55 B to create the cancellation adjusted bound B  52 J. The dominant bound accumulated rounding error N  55 B is the accumulated rounding error of the dominant bound B  5211 . 
     Turning to  FIG. 6B , the rounding error adder  640  adds the significand excess  741  and the normalized rounding error R  57 A to the dominant bound B  5211  yielding the rounding error sum B  52 K. 
     The count comparator  650  asserts the count overflow  651  when the updated accumulated rounding error extension count C  54 K is equal to the lost bits power  61 . When the lost bits power  61  is equal to −1 (see count power circuit  680 ), the count overflow  651  is not asserted. The updated accumulated rounding error extension count C  54 K is the extension count  56  C field of the accumulated rounding error N field of the rounding error sum  52 K. The dominant bound lost bits D  54 C and the count overflow  651  are utilized by the lost bits incrementer  660  and the count power circuit  680 . 
     The lost bits incrementer  660  adds one to the dominant bound lost bits D  54 C when the count overflow  651  is asserted producing the incremented lost bits D  54 E. The incremented lost bits D  54 E is limited to the significand capacity  805  by the second maximum lost bits detector  661  and the second lost bits selector  665  to produce the clamped incremented lost bits D  54 J. 
     The second maximum lost bits detector  661  compares the incremented lost bits D  54 E against the significand capacity  805  to determine the second maximum lost bits  662  that asserts that the incremented lost bits D  54 E is greater than or equal to the significand capacity  805  to control the second lost bits selector  665 . 
     The second lost bits selector  665  sets the clamped incremented lost bits D  54 J to either the incremented lost bits D  54 E or the significand capacity  805  depending on the second maximum lost bits  662  clamping the clamped incremented lost bits D  54 J to no more than the significand capacity  805 . 
     The lost bits adjusted bound B  52 L is the bound comprised of the concatenation of the clamped incremented lost bits D  54 J, an extension count C having a value of zero, and the updated accumulated rounding error rounding bits N  57 B. 
     The rounding error sum B  52 K is calculated by the rounding error adder  640  by adding the significand excess  741  and the normalized rounding error R  57 A to the dominant bound B  5211 . 
     The adjusted bound multiplexer  670  is the inventive circuit that selects either the lost bits adjusted bound B  52 L when the count overflow  651  is asserted, or selects the rounding error sum B  52 K to produce the carry adjusted bound B  52 M utilized by the result bound multiplexer  630  of  FIG. 6A . 
     The cancellation detector circuit  620  ( FIG. 6A ) is the inventive circuit that asserts cancellation control  621  when there is cancellation by determining that the number of leading zeros  711  is greater than one. This condition would be false, for instance, during an add operation with like signs. This condition is true when cancellation has occurred during a subtract or other operation in which cancellation may occur. 
     The result bound multiplexer  630  ( FIG. 6A ) in the inventive circuit that selects either the cancellation adjusted bound B  52 J or the carry adjusted bound B  52 M of  FIG. 6B  depending on the cancellation control  621 . The result is the result bound B  52 C to be included in the final result of the current operation (the calculated result  260  of  FIG. 2B ). 
     Referring now to the inventive composite exception circuit  800  of  FIG. 8 , the exception circuit  800  provides two inventive circuits, the zero-selection control signal  860 , and one that asserts the sNaN(isb) exception  940 . The selection of the bounded floating-point representation of zero  261  ( FIG. 2B ) is selected by the assertion of the zero-selection control signal  860 . The zero-selection control signal  860  is determined from the significand capacity  805 , the dominant bound lost bits D  54 C ( FIG. 6A ), the number of leading zeros  711  ( FIG. 7 ), and the bound limit  54 M. 
     The circuit for significantly zero detection  861  determines the zero-selection control signal  860  that is asserted when both the significant leading zero detected  831  is asserted and significant digits  871  is asserted. The significant zeros detector  830  asserts the significant leading zero detected  831  when the number of leading zeros  711  ( FIG. 7 ) is greater than or equal to the available significant bits  841 . The significant bits subtractor  840  provides the available significant bits  841  by subtracting the dominant bound lost bits D  54 C ( FIG. 6A ) from the significand capacity  805 . 
     The significant digits detector  870  circuit asserts the significant digit  871  when the dominant bound lost bits D  54 C ( FIG. 6A ) is less than or equal to the bound limit  54 M. 
     Considering the specialized representation of the sNaN(isb)  262  (of  FIG. 2B )], if it is determined that the results lost bits D  54 F is greater than the unacceptable limit  804 , then the bounded floating-point result  280 ,  FIG. 2B , is the specialized representation “sNaN(isb).” 
     The significand capacity memory circuit  820  is a static memory that provides the size  104  of the T Field  53  plus one for the hidden bit H Field  510  ( FIG. 1 ) for the width of the current operation. Memory is addressed by the operation width control  902 . The operation width control  902  is a signal provided by the processor indicating the width of the current bounded floating-point operation in the form of an address. The significand capacity memory circuit  820  produces the significand capacity  805 , which is the total number of bits of the significand of the result (including the hidden bit H  510 ). 
     The results lost bits D  54 F is the lost bits of the result bound B  52 C ( FIGS. 2B, 6A ). The zero-detection comparator  820  asserts the zero-selection control  821  ( FIG. 2B ) when the total lost bits D  841  is greater than or equal to the significand capacity  805 . The inventive total lost bits adder circuit  840  adds the dominant bound lost bits D  54 C to the number of leading zeros  711  to produce the total lost bits  841 . 
     The bound limit memory  802  is a memory (static or optionally dynamic) containing the unacceptable limit  804  on the result lost bits D  54 F for the current operation format width. This bound limit memory circuit  802 , also addressed by the operation width control  801 , provides the unacceptable bound limit  804 . 
     In the inventive apparatus and method, initially the bound limit memory circuit  810  contains the default bound limit  54 M values, which can be static (default) or programmed (maximum lost bits D  54 L). 
     In the optional dynamic case shown on the left in  FIG. 8 , the bound limit can be changed from the maximum lost bits D  54 L value(s). The maximum lost bits D  54 L is a value provided by an error limit set/check command  901 . The error limit set/check command  901  is the command from the main processing unit  910  storing the command specified maximum lost bits D  54 L for the current instruction width in the bound limit memory  810  and commanding an error limit check that generates an sNaN(sig)  940  by comparing against the lost bits  54 F of the specified operand  201 . Note that an error limit set/check command against an operand with no lost bits only sets the bound limit memory for succeeding instructions such as subtract operations when testing for equality. This error limit set/check command  901  stores a maximum lost bits  54 L value in the bound limit memory circuit  810  in a location determined by the operation width control  902 . 
     In a first example, for single precision (32-bit, width k  101 =32) bounded floating-point operation, if the T Field  53  is 16 bits in width (t  104 =16) providing 17 significant bits including the hidden bit H  510  (5 significant decimal digits), then the width of the lost bits D Field  54  (d  105 ) and C Field  56  (c  107 ), would need to be 3 bits each. This accommodates the standard 8-bit exponent, E Field  51  (width e  102 ) and allows 1 bit for the R Field  57  making the N Field  55  4 bits (n  106 =4). If the desired default significance is 3 decimal digits, then 10 binary bits including the hidden bit H  510  are required. This would mean that the allowable number of results lost bits D Field  54 F (width d  105 ) could not exceed 7, the required value of the acceptable bound limit  804  for the bound limit memory circuit  802  selected by the operation width control  801  for a single precision bounded floating-point operation. 
     As an additional example, for a double precision (64-bit, width k  101 =64) bounded floating-point operation, if the T Field  53  is 36 bits in width (width t  104 =36), providing 37 significant bits (11+ significant decimal digits) including the hidden bit H  510 , as specified in the significand capacity memory circuit  803  location corresponding to a double precision operation, then the width of the lost bits D Field  54  (d  105 ) and the C Field  54  (c  107 ) would need to be 6 bits each allowing 4 bits for the R Field  57  (width r  108 =4) thereby making the N Field  55  10 bits (width n  106 =10). If the desired default decimal significance is 6 decimal digits, then 20 binary bits, including the hidden bit H  510 , are required. This would mean that the allowable number of results lost bits D  54 F could not exceed 17, the required value of the acceptable bound limit  804  for the bound limit memory circuit  802  selected by the operation width control  801  for a double precision bounded floating-point operation. 
     Turning back to  FIG. 2B , the exception and result multiplexer  270  selects the bounded floating-point result  280  from either the calculated result  260  or BFP zero  261  based on the zero-selection control. If the zero-selection control  821  is not asserted, then the bounded floating-point result  280  is the calculated floating-point result  260 . 
     Where O is the exponent offset, t is the width of the significand  102 , T is the value of the significand  53 , S is the sign 0 or 1  50 , E is the exponent  51 , D is the lost bits  54 , and 2 t  is the hidden bit H  510 : 
     the real value represented by a non-zero normalized bounded floating-point value lies between the following:
 
−1 S ×((T+2 T )/2 t-1 ) E-O  and −1 S ×((T+2 t +2 D )/2 t-1 ) E-O  
 
     and for denormalized values (where the value of the E Field is zero and there are no hidden bits), the first and second bounds are the following:
 
−1 S ×T/2 t-1  and −1 S ×(T+2 D )/2 t-1  
 
     and the expected value is the average of the first and second bounds. 
     Error that is introduced into floating-point values when converted from an external decimal representation can be recorded in this inventive floating-point representation. Conversion to external representation of a real number in decimal can be confined to only significant digits or can be expressed as a bounded real number of the form v+/−e where v is the expected real value expressed as a real number (in the format x×10 p , where x is a decimal value and p is an integer power of 10) and e is the first and second bound of the error expressed as a similarly formatted real number. 
     In the present inventive apparatus and methods when two values are compared by subtraction in which cancellation occurs two considerations are made, as follows. 
     In considering equality, when the two operands are equal in their significant bits, the result will truly be zero. As noted above, when the number of lost bits exceeds the number of bits available for the significand (or exceeds the significand capacity  805 ), the result of the equality comparison operation is set to the bounded floating-point representation of zero. 
     In considering non-equality, in which there are typically four instances, which are greater-than, less-than, greater-than-or-equal-to, and less-than-or-equal-to, there are only two instances that need to be considered, because equal-to is handled as noted above. In considering greater-than, if the maximum value of the first operand is greater than the maximum value of the second operand, then the first operand is greater than the second operand. Similarly, if the minimum value of the second operand is less than the minimum value of the first operand, then the first operand is greater than the second operand. 
     In some instances, the sign of the result of the operation does not necessarily reflect the greater-than or less-than condition. This occurs when the minimum value of the first operand is less than the maximum value of the second operand and the maximum value of the second operand is greater than the minimum value of the first operand. In this instance, conventional methods may be relied upon to determine the result. These instances may also require special bounded floating-point instructions. 
     In the present inventive apparatus and method, conversion of one bounded floating-point width to a larger bounded floating-point width (e.g., 32-bit to 64-bit, etc.) requires conversion of the loss of significant bits D Field  54  from the narrow width to the wider width. This requires that the number of retained significant bits be calculated for the first width and then converted to loss of significant bits for the second width. This may result in the generation of the sNaN(isb)  262  when converting, for instance, from 32-bit to 64-bit bounded floating-point representations, when the newly computed loss of significant bits exceeds the limit value (unacceptable bound limit  804 ) for the new width. Similarly, when converting from wider to narrower bounded floating-point widths, all the bits may be significant, but bits lost from the X Field  60 R ( FIG. 5 ) obtained from the wider representation must be accumulated as the initial loss of significant bits. 
     The exemplary embodiment depicted herein, describes a bounded floating-point circuit with real-time error bound tracking within or in association with a processor, computer system, or other processing apparatus. In this description, numerous specific details such as processing circuits, processor types, micro-architectural conditions, events, enablement mechanisms, and the like are set forth in order to provide a more thorough understanding of embodiments of the present invention. It will be appreciated, however, by one skilled in the art, that the invention may be practiced without such specific details. Additionally, some well-known structures, circuits, and the like have not been shown in detail to avoid unnecessarily obscuring embodiments of the present invention. 
     One embodiment of the present invention may provide a single core or multi-core bounded floating-point processor or may be included in other floating-point or general-purpose processors. The processor may comprise a register file and a permutation (multiplexer) unit coupled to the register file. The register file may have a plurality of register banks and an input to receive a selection signal. The selection signal may select one or more unit widths of a register bank as a data element boundary for read or write operations. 
     Although the herein described embodiments are described with reference to a processor, other embodiments are applicable to other types of integrated circuits and logic devices. Similar techniques and teachings of embodiments of the present invention can be applied to other types of circuits or semiconductor devices that can benefit from higher pipeline throughput and improved performance. The teachings of embodiments of the present invention are applicable to any processor or machine that performs data manipulations. However, the present invention is not limited to processors or machines that perform specific data width operations and can be applied to any processor and machine in which manipulation or management of data is performed whether such operations are conducted with binary, decimal, or binary encoded decimal data representations. 
     In addition, though the embodiment presented herein represents an apparatus and associated method for bounded floating-point addition and subtraction, it is presented as an example of bounded floating-point operations. By extension, the same inventive apparatus for calculating and retaining a bound on error during floating-point operations can be used in other floating-point operations such as multiplication, division, square root, multiply-add, and other floating-point functions. Other embodiments may contain ancillary bounded floating-point operations such as conversion between floating-point formats including, but not limited to, external representations of real numbers, standard floating point, bounded floating point, and includes formats of varying width. 
     Although the examples provided herein describe instruction handling and distribution in the context of execution units and logic circuits, other embodiments of the present invention can be accomplished by way of data or instructions stored on a machine-readable, tangible medium, which, when performed by a machine, cause the machine to perform functions consistent with at least one embodiment of the invention. In one embodiment, functions associated with embodiments of the present invention are embodied in machine-executable instructions. The instructions can be used to cause a general-purpose or special-purpose processor that is programmed with the instructions to perform the steps of the present invention. Embodiments of the present invention may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to embodiments of the present invention. Alternatively, steps of embodiments of the present invention might be performed by specific hardware components that contain fixed-function circuits for performing the steps, or by any combination of programmed computer components and fixed-function hardware components. 
     Instructions used to program logic to perform embodiments of the invention can be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media. Thus a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet or other networks via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.). Accordingly, the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer). 
     A design may go through various stages, from creation to simulation to fabrication. Data representing a design may represent the design in a number of manners. First, as is useful in simulations, the hardware may be represented using a hardware description language (HDL, e.g. VHDL) or another functional description language. Additionally, a circuit level model with logic and/or transistor gates may be produced. Furthermore, most designs, at some stage, reach a level of data representing the physical placement of various devices in the hardware model. In the case where conventional semiconductor fabrication techniques are used, the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit. In any representation of the design, the data may be stored in any form of a machine-readable medium. A memory or a magnetic or optical storage such as a disc may be the machine-readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information. When an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that copying, buffering, or re-transmission of the electrical signal is performed, a new copy is made. Thus, a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention. 
     In modern processors, several different execution units are used to process and execute a variety of code and instructions. Not all instructions are created equal as some are quicker to complete while others can take a number of clock cycles to complete. The faster the throughput of instructions, the better the overall performance of the processor. Thus, it would be advantageous to have as many instructions execute as fast as possible. However, there are certain instructions that have greater complexity and require more in terms of execution time and processor resources. For example, there are floating-point instructions, load/store operations, data moves, etc. 
     As more computer systems are used in Internet, text, and multimedia applications, additional processor support has been introduced over time. In one embodiment, an instruction set may be associated with one or more computer architectures, including data types, instructions, register architecture, addressing modes, memory architecture, interrupt and exception handling, and external input and output (I/O). 
     In one embodiment, the instruction set architecture (ISA) may be implemented by one or more micro-architectures, with associated micro-code, which includes processor logic and circuits used to implement one or more instruction sets. Accordingly, processors with different micro-architectures can share at least a portion of a common instruction set. For example, Intel® processors, Intel® Core™ processors, and processors from Advanced Micro Devices implement nearly identical versions of the x86 instruction set (with some extensions that have been added with newer versions), but have different internal designs. Similarly, processors designed by other processor development companies, such as ARM Holdings, Ltd., MIPS, or their licensees or adopters, may share at least a portion a common instruction set, but may include different processor designs. For example, the same register architecture of the ISA may be implemented in different ways in different micro-architectures using new or well-known techniques, including dedicated physical registers, one or more dynamically allocated physical registers using a register renaming mechanism (e.g., the use of a Register Alias Table (RAT), a Reorder Buffer (ROB) and a retirement register file). In one embodiment, registers may include one or more registers, register architectures, register files, or other register sets that may or may not be addressable by a software programmer. 
     In one embodiment, a floating-point format may include additional fields or formats indicating various fields (number of bits, location of bits, etc.). Some floating-point formats may be further broken down into or defined by data templates (or sub formats). For example, the data templates of a given data format may be defined to have different subsets of the data format&#39;s fields and/or defined to have a given field interpreted differently. 
     Scientific, financial, auto-vectorized general purpose, RMS (recognition, mining, and synthesis), and visual and multimedia applications (e.g., 2D/3D graphics, image processing, video compression/decompression, voice recognition algorithms and audio manipulation) may require the same operation to be performed on a large number of data items. In one embodiment, Single Instruction Multiple Data (SIMD) refers to a type of instruction that causes a processor to perform an operation on multiple data elements. SIMD technology may be used in processors that can logically divide the bits in a register into a number of fixed-sized or variable-sized data elements, each of which represents a separate value. For example, in one embodiment, the bits in a 64-bit register may be organized as a source operand containing four separate 16-bit data elements, each of which represents a separate 16-bit value. This type of data may be referred to as ‘packed’ data type or ‘vector’ data type, and operands of this data type are referred to as packed data operands or vector operands. In one embodiment, a packed data item or vector may be a sequence of packed data elements stored within a single register, and a packed data operand or a vector operand may a source or destination operand of a SIMD instruction (or ‘packed data instruction’ or a ‘vector instruction’). In one embodiment, a SIMD instruction specifies a single vector operation to be performed on two or more source vector operands to generate a destination vector operand (also referred to as a result vector operand) of the same or different size, with the same or different number of data elements, and in the same or different data element order. 
     In one embodiment, destination and source registers/data are generic terms to represent the source and destination of the corresponding data or operation. In some embodiments, they may be implemented by registers, memory, or other storage areas having other names or functions other than those depicted. For example, in one embodiment, the calculated result  260  may be a temporary storage register or other storage area, whereas the first operand  201  and the second operand  202  may be a first and second source storage register or other storage area, and so forth. In other embodiments, two or more of the operand and result storage areas may correspond to different data storage elements within the same storage area (e.g., a SIMD register). In one embodiment, one of the source registers may also act as a destination register by, for example, writing back the result of an operation performed on the first and second source data to one of the two source registers serving as destination registers. 
     In one embodiment, a non-transitory machine-readable storage medium comprising all computer-readable media except for a transitory, propagating signal, may contain all or part of the invention described herein. 
     Glossary 
     
       
         
           
               
               
               
             
               
                   
               
               
                 No. 
                 Name 
                 Description 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
            
               
                 FIG. 1 
               
            
           
           
               
               
               
            
               
                   
                 field 
                 refers to either the value of a register or a portion of the value of a 
               
               
                   
                   
                 register. 
               
               
                 100 
                 bounded floating- 
                 provides a virtual bitwise layout of the new floating-point format. 
               
               
                   
                 point format 
               
               
                 50 
                 sign bit field 
                 is the standard or conventional floating-point sign bit as defined by 
               
               
                   
                 (S Field) 
                 the floating-point standard: Information Technology - 
               
               
                   
                   
                 Microprocessor Systems - Floating-Point Arithmetic, International 
               
               
                   
                   
                 Standard, ISO/IEC/IEEE 60569: 2011. Geneva: ISO, 2011, p. 9. 
               
               
                 51 
                 exponent field 
                 is the conventional biased floating-point exponent. 
               
               
                   
                 (E Field) 
               
               
                 52 
                 bound field 
                 is a newly defined field added to the floating-point standard to 
               
               
                   
                 (B Field) 
                 provide accumulated information on the bound of the represented 
               
               
                   
                   
                 real number. 
               
               
                 53 
                 significand field 
                 is the conventional floating-point significand of width 1104. It is the 
               
               
                   
                 (T Field) 
                 fraction of the floating-point value less the hidden bit H 510 of width 
               
               
                   
                   
                 t 104 of the current art. 
               
               
                 54 
                 lost bits field 
                 is the number of bits in the floating-point representation that are no 
               
               
                   
                 (D Field) 
                 longer significant. This is a subfield of the bound B Field 52 of the 
               
               
                   
                   
                 bounded floating-point format 100. 
               
               
                 55 
                 accumulated 
                 is the accumulation of the rounding errors that occur from alignment 
               
               
                   
                 rounding error field 
                 and normalization. This is a subfield of width n 106 of the bound B 
               
               
                   
                 (N Field) 
                 Field 52 of width n 106 of the bounded floating-point format 100. It 
               
               
                   
                   
                 is composed of the C Field 56 and the R Field 57. 
               
               
                 56 
                 rounding error 
                 is the sum of the carries from the sum of the R Field 57R from 
               
               
                   
                 count field (C Field) 
                 successive operations. This is a subfield of width c 107 of the N 
               
               
                   
                   
                 Field 55 of the bounded floating-point format 100. 
               
               
                 57 
                 rounding bits field 
                 is the sum of the rounded most significant bits of the rounding error, 
               
               
                   
                 (R Field) 
                 lost during truncation plus the resulting bit from the right shift loss 
               
               
                   
                   
                 circuit 705. This is a subfield of width r 108 of the N Field 55 of the 
               
               
                   
                   
                 bounded floating-point format 100. 
               
               
                 101 
                 bounded floating- 
                 is the width of a bounded floating-point number 100. 
               
               
                   
                 point width 
               
               
                 102 
                 width e 
                 is the conventional width, e, of the exponent E Field 51. 
               
               
                 103 
                 width b 
                 is the inventive width, b, of the bound B Field 52. 
               
               
                 104 
                 width t 
                 is the conventional definition of width, t, of the T Fields 53 (FIG. 1), 
               
               
                   
                   
                 53R (FIG. 5) 
               
               
                 105 
                 width d 
                 is the inventive width, d, of the lost bits D Field 54. 
               
               
                 106 
                 width n 
                 is the inventive width, n, of the N Field 55. 
               
               
                 107 
                 width c 
                 is the inventive width, c, of the C Field 56. 
               
               
                 108 
                 width r 
                 is the inventive width, r, of the R Fields 57 (FIG. 1), 57R (FIG. 5). 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 2A &amp; 2B 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 200 
                 bounded floating- 
                 is the data and control flow circuit diagram of the apparatus for 
               
               
                   
                 point 
                 computing the exemplary bounded floating-point addition and 
               
               
                   
                 addition/subtraction 
                 subtraction operations, which can also be applied to other 
               
               
                   
                 diagram 
                 mathematical operations. 
               
               
                 201 
                 first operand 
                 data from the first operand conglome.rate register 210 of the registers 
               
               
                   
                   
                 990 (where a register may be a hardware register, a location in a 
               
               
                   
                   
                 register file, or a memory location) with registers conforming to the 
               
               
                   
                   
                 corresponding fields of the bounded floating-point format 100 for an 
               
               
                   
                   
                 addition operation and the minuend for a subtract operation. 
               
               
                 202 
                 second operand 
                 data from the second operand conglomerate register 220 of the 
               
               
                   
                   
                 registers 990 (where a register may be a hardware register, a location 
               
               
                   
                   
                 in a register file, or a memory location) with registers conforming to 
               
               
                   
                   
                 the corresponding fields of the bounded floating-point format 100 for 
               
               
                   
                   
                 an addition operation and the subtrahend for a subtract operation. 
               
               
                 210 
                 first operand 
                 is the conglomerate register (where a register may be a hardware 
               
               
                   
                 register 
                 register, a location in a register file, or a memory location) 990 with 
               
               
                   
                   
                 registers that contain the corresponding fields of the first operand 
               
               
                   
                   
                 201 in the bounded floating-point format 100. 
               
               
                  1A 
                 first operand sign 
                 is the conventional single bit register that holds the first operand 
               
               
                   
                 bit register 
                 register 201 sign bit. 
               
               
                  2A 
                 first operand 
                 is the conventional register that holds the first operand register 201 
               
               
                   
                 exponent register 
                 exponent. 
               
               
                  3A 
                 first operand bound 
                 is the inventive conglomerate register that holds the first operand 
               
               
                   
                 register 
                 register 201 bound. 
               
               
                  4A 
                 first operand 
                 is the conventional register that holds the first operand register 201 
               
               
                   
                 significand register 
                 significand. 
               
               
                 220 
                 second operand 
                 is the conglomerate register (where a register may be a hardware 
               
               
                   
                 register 
                 register, a location in a register file, or a memory location) 990 with 
               
               
                   
                   
                 registers that contain the corresponding fields of the first operand 
               
               
                   
                   
                 202 in the bounded floating-point format 100. 
               
               
                  1B 
                 second operand sign 
                 is the conventional single bit register that holds the second register 
               
               
                   
                 bit register 
                 202 operand sign bit. 
               
               
                  2B 
                 second operand 
                 is the conventional register that holds the second operand register 
               
               
                   
                 exponent register 
                 202 exponent. 
               
               
                  3B 
                 second operand 
                 is the inventive conglomerate register that holds the second operand 
               
               
                   
                 bound register 
                 register 202 bound. 
               
               
                  4B 
                 second operand 
                 is the conventional register that holds the second operand register 
               
               
                   
                 significand register 
                 202. 
               
               
                  50A 
                 first operand sign 
                 is the sign bit of the first operand 201 obtained from the first operand 
               
               
                   
                 bit S Field 
                 sign bit field of register 1A. 
               
               
                  51A 
                 first operand 
                 is the exponent of the first operand 201 obtained from the first 
               
               
                   
                 exponent E 
                 operand exponent E field 51 of register 2A. 
               
               
                  52A 
                 first operand bound 
                 provides the inventive bound for the first operand 201 obtained from 
               
               
                   
                 B 
                 the first operand bound B Field 52 of register 3A. 
               
               
                  53A 
                 first operand 
                 is the significand of the first operand 201 obtained from the first 
               
               
                   
                 significand T 
                 operand significand T Field of register 4A. 
               
               
                  50B 
                 second operand sign 
                 is the sign bit of the second operand 202 obtained from the second 
               
               
                   
                 bit S Field 
                 operand sign bit S Field of register 1B. 
               
               
                  51B 
                 second operand 
                 is the exponent of the second operand 202 obtained from the second 
               
               
                   
                 exponent E 
                 operand exponent E Field of register 2B. 
               
               
                  52B 
                 second operand 
                 provides the inventive error bound B Field 52 of the second operand 
               
               
                   
                 bound B 
                 obtained from the second operand bound register 3B. 
               
               
                  53B 
                 second operand 
                 is the significand of the second operand 202 obtained from the 
               
               
                   
                 significand T 
                 second operand significand T Field of register 4B. 
               
               
                 230 
                 first significand 
                 is the conventional circuit that selects the significand T of the 
               
               
                   
                 swap multiplexer 
                 operand with the smallest value 53D from either the first operand 
               
               
                   
                   
                 significand T 53A or the second operand significand T 53B 
               
               
                   
                   
                 controlled by the largest value control 302. 
               
               
                 231 
                 second significand 
                 is the conventional circuit that selects the significand T of the 
               
               
                   
                 swap multiplexer 
                 operand with the largest value 53E from either the first operand 
               
               
                   
                   
                 significand T 53A or the second operand significand T 53B 
               
               
                   
                   
                 controlled by the largest value control 302. 
               
               
                  53D 
                 significand T of the 
                 is the significand T of the operand with the smallest value that is 
               
               
                   
                 operand with the 
                 modified by the insertion of the hidden bit H 510 with the modified 
               
               
                   
                 smallest value 
                 significand left justified. 
               
               
                  53E 
                 significand T of the 
                 is the significand T of the operand with the largest value that is 
               
               
                   
                 operand with the 
                 modified by the insertion of the hidden bit H 510 with the modified 
               
               
                   
                 largest value 
                 significand left justified. 
               
               
                 240 
                 alignment shifter 
                 is the conventional circuit that shifts the significand T of the operand 
               
               
                   
                   
                 with the smallest value 53D to the right by the number of bits 
               
               
                   
                   
                 determined by the exponent difference 321. In addition, this may 
               
               
                   
                   
                 shift out bits and the associated bound must be adjusted (see FIG. 4, 
               
               
                   
                   
                 Dominant Bound Circuit). Bits shifted out of the end of the 
               
               
                   
                   
                 alignment shifter 242 are re-inserted into the least significant bit of 
               
               
                   
                   
                 the result of the alignment shifter. 
               
               
                 241 
                 aligned significand 
                 is the aligned significand T of the operand with the smallest exponent 
               
               
                   
                   
                 E. 
               
               
                 242 
                 alignment shift loss 
                 is a one bit shifted out of the alignment shifter 240. When this 
               
               
                   
                   
                 occurs, a one bit is re-inserted into the aligned significand E 241 
               
               
                   
                   
                 ensuring that a significand excess 741 will be detected. 
               
               
                 250 
                 significand adder 
                 is the conventional circuit that calculates the sum or difference 251 
               
               
                   
                   
                 of the aligned significand E 241 and the significand T of the operand 
               
               
                   
                   
                 with the largest value 53E. This is an exemplary circuit that 
               
               
                   
                   
                 represents a conventional arithmetic circuit that calculates arithmetic 
               
               
                   
                   
                 functions such as multiply, divide, square root, or other arithmetic 
               
               
                   
                   
                 functions. 
               
               
                 251 
                 sum or difference 
                 is the resulting aligned significand 241 and the significand T of the 
               
               
                   
                   
                 operand with the largest value 53E produced by the exemplary 
               
               
                   
                   
                 significand adder 250. This is an exemplary result that represents the 
               
               
                   
                   
                 result of arithmetic functions such as multiply, divide, square root, or 
               
               
                   
                   
                 other arithmetic functions. 
               
               
                  51C 
                 result exponent E 
                 is the final value of the exponent after normalization adjustment. 
               
               
                  52C 
                 result bound B 
                 is the inventive bound to be included in the final result. 
               
               
                  53C 
                 truncated resulting 
                 is the truncated resulting significand after normalization. (See FIG. 
               
               
                   
                 significand T 
                 7.). 
               
               
                 260 
                 calculated result 
                 is the final calculated result as the concatenation of the result sign bit 
               
               
                   
                   
                 S 50C, the result exponent E 51C, the inventive result bound B 52C, 
               
               
                   
                   
                 and the truncated resulting significand T 53C. 
               
               
                 261 
                 BFP zero 
                 is the standard floating-point representation of zero with the bound B 
               
               
                   
                   
                 set to zero. 
               
               
                 270 
                 exception and result 
                 selects the bounded floating-point result 280 from either the 
               
               
                   
                 multiplexer 
                 calculated result 260, or BFP zero 261 based on the inventive zero 
               
               
                   
                   
                 selection control signal 860. 
               
               
                 280 
                 bounded floating- 
                 is the final value stored in the final inventive bounded floating-point 
               
               
                   
                 point result 
                 result register 285 of the registers 990 (where register may be a 
               
               
                   
                   
                 hardware register, a location in a register file, or a memory location) 
               
               
                   
                   
                 of the operation, a bounded floating-point value or zero. 
               
               
                 285 
                 final result register 
                 is a register of the registers 990 (where register may be a hardware 
               
               
                   
                   
                 register, a location in a register file, or a memory location) containing 
               
               
                   
                   
                 the inventive bounded floating-point result 280. 
               
               
                 290 
                 sign circuit 
                 is the conventional circuit that determines the result sign bit S 50C 
               
               
                   
                   
                 from the first operand sign bit S 50A and the second operand sign bit 
               
               
                   
                   
                 S 50B and the right shift control 702 (the effect on the sign after 
               
               
                   
                   
                 subtraction). 
               
               
                  50C 
                 result sign bit S 
                 is the sign of the calculated result 260. 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 3 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 300 
                 exponent circuit 
                 is the conventional circuit that calculates the exponent difference 321 
               
               
                   
                   
                 and identifies the largest value control 302. 
               
               
                 301 
                 value comparator 
                 is the conventional circuit that compares the first operand value E, T 
               
               
                   
                   
                 51A, 53A with the second operand value E, T 51B, 53B to determine 
               
               
                   
                   
                 the largest value control 302. 
               
               
                 302 
                 largest value control 
                 is the control signal identifying the largest of the first operand value 
               
               
                   
                   
                 E,T 51A, 53A or the second operand value E,T 51B, 53B and 
               
               
                   
                   
                 controls the first and second significand swap multiplexers 230, 231, 
               
               
                   
                   
                 the largest and smallest exponent selection multiplexers 310, 311, 
               
               
                   
                   
                 and the inventive first and second bound swap multiplexers 401, 402. 
               
               
                 310 
                 largest exponent 
                 is the conventional circuit that selects either the largest exponent E 
               
               
                   
                 selection 
                 51D from first operand exponent E 51A or the second operand 
               
               
                   
                 multiplexer 
                 exponent 51B controlled by the largest value control 302. 
               
               
                 311 
                 smallest exponent 
                 is the conventional circuit that selects either the smallest exponent E 
               
               
                   
                 selection 
                 51E from the first operand exponent E 51A or the second operand 
               
               
                   
                 multiplexer 
                 exponent E 51B controlled by the largest value control 302. 
               
               
                  51D 
                 largest exponent E 
                 is the largest of the first operand exponent E 51A and the second 
               
               
                   
                   
                 operand exponent E 51B determined by largest value control 302. 
               
               
                  51E 
                 smallest exponent E 
                 is the smallest of the first operand exponent E 51A and the second 
               
               
                   
                   
                 operand exponent E 51B determined by largest value control 302. 
               
               
                 320 
                 exponent subtractor 
                 is the conventional circuit that calculates the exponent difference 321 
               
               
                   
                   
                 between the largest exponent E 51D and the smallest exponent E 
               
               
                   
                   
                 51E. 
               
               
                 321 
                 exponent difference 
                 is the magnitude of the difference between the first operand exponent 
               
               
                   
                   
                 E 51A and the second operand exponent E 51B and controls the 
               
               
                   
                   
                 alignment shifter 240. In this invention the exponent difference is 
               
               
                   
                   
                 also used unconventionally by the lost bits subtractor 410 by 
               
               
                   
                   
                 subtracting the exponent difference 321 from the smallest operand 
               
               
                   
                   
                 bound lost bits D 54A to produce the adjusted bound B of the 
               
               
                   
                   
                 operand 52F. (See FIG. 4.) 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 4 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 400 
                 dominant bound 
                 is a newly invented circuit that uses the first operand bound B 52A, 
               
               
                   
                 circuit 
                 the second operand bound B 52B, the largest value control 302, and 
               
               
                   
                   
                 the exponent difference 321 to determine the dominant bound B 
               
               
                   
                   
                 52H. In an arithmetic operation, the operand with the least number of 
               
               
                   
                   
                 significant digits after exponent alignment determines (“dominates”) 
               
               
                   
                   
                 the initial number of significant digits of input operands. 
               
               
                 401 
                 first bound swap 
                 is a newly invented circuit that selects either the smallest operand 
               
               
                   
                 multiplexer 
                 bound B 52D from first operand bound B 52A or the second operand 
               
               
                   
                   
                 bound B 52B controlled by the largest value control 302. 
               
               
                 402 
                 second bound swap 
                 is a newly invented circuit that selects either the largest operand 
               
               
                   
                 multiplexer 
                 bound B 52E from the first operand bound B 52A or the second 
               
               
                   
                   
                 operand bound B 52B controlled by the largest value control 302. 
               
               
                  52D 
                 smallest operand 
                 is the inventive bound of the operand with the smallest operand. 
               
               
                   
                 bound B 
               
               
                  52E 
                 largest operand 
                 is the inventive bound of the operand with the largest operand. 
               
               
                   
                 bound B 
               
               
                  54A 
                 smallest operand 
                 is the inventive lost bits D field of the smallest operand bound B 
               
               
                   
                 bound lost bits D 
                 52D. 
               
               
                  55A 
                 smallest operand 
                 is the inventive accumulated rounding error field N of the smallest 
               
               
                   
                 bound accumulated 
                 operand bound B 52D. 
               
               
                   
                 rounding error N 
               
               
                 410 
                 lost bits subtractor 
                 is a newly invented circuit that subtracts the exponent difference 321 
               
               
                   
                   
                 from the smallest operand bound lost bits D 54A producing the 
               
               
                   
                   
                 adjusted smallest operand bound lost bits D 54B. 
               
               
                  54B 
                 adjusted smallest 
                 is the inventive smallest operand bound lost bits D 54A adjusted by 
               
               
                   
                 operand bound lost 
                 the exponent difference 321 to account for the increase in the 
               
               
                   
                 bits D 
                 significant bits of the operand with the smallest operand bound B 
               
               
                   
                   
                 52D due to exponent alignment. Significand realignment to match 
               
               
                   
                   
                 exponents decreases the number of lost bits in that significand. 
               
               
                 420 
                 lost bits clamp 
                 is a newly invented circuit that prohibits the lost bits of the adjusted 
               
               
                   
                   
                 bound D 54B of the smallest operand bound B 52D from 
               
               
                   
                   
                 underflowing to less than zero when the lost bits subtractor 410 
               
               
                   
                   
                 produces a negative value for the adjusted smallest operand bound 
               
               
                   
                   
                 lost bits D 54B. This limits the clamped lost bits D 54G to zero or 
               
               
                   
                   
                 greater. 
               
               
                  54G 
                 clamped lost bits D 
                 is the adjusted smallest operand bound lost bits D limited to zero or 
               
               
                   
                   
                 greater. 
               
               
                  52F 
                 adjusted bound B of 
                 is the concatenation of the clamped lost bits D 54G and the smallest 
               
               
                   
                 the smallest 
                 operand bound accumulated rounding error N 55A. 
               
               
                   
                 operand 
               
               
                 430 
                 bound comparator 
                 is a newly invented circuit that compares the largest operand bound 
               
               
                   
                   
                 B 52E to the adjusted bound B of the smallest operand 52F to 
               
               
                   
                   
                 determine the dominant bound selection control 431. 
               
               
                 431 
                 dominant bound 
                 is the control signal for the dominant bound multiplexer 440 to select 
               
               
                   
                 selection control 
                 the dominant bound B 52H, asserted when the largest operand bound 
               
               
                   
                   
                 B 52E is greater than the adjusted bound B of the smallest operand 
               
               
                   
                   
                 52F. 
               
               
                 440 
                 dominant bound 
                 is a newly invented circuit that selects either the largest operand 
               
               
                   
                 multiplexer 
                 bound B 52E adjusted bound B of the smallest operand 52F selected 
               
               
                   
                   
                 by the dominant bound selection control 431 to determine the 
               
               
                   
                   
                 dominant bound B 52H. 
               
               
                  52H 
                 dominant bound B 
                 is the largest of the largest operand bound B 52E and the adjusted 
               
               
                   
                   
                 bound B of the smallest operand 52F. This is the bound of the 
               
               
                   
                   
                 operand with the least number of significant bits after alignment. 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 5 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 500 
                 post normalization 
                 is the format of the bounded floating-point significand adder result 
               
               
                   
                 result format 
                 720 after normalization. 
               
               
                 501 
                 virtual width of 
                 is the width v of the resulting sum or difference taking into account 
               
               
                   
                 significand adder 
                 possible need for multiple additions necessary to accommodate 
               
               
                   
                   
                 extended bounded floating-point formats. 
               
               
                 510 
                 hidden bit H 
                 is the conventional left justified hidden bit field after normalization. 
               
               
                  53R 
                 resulting 
                 is the conventional resulting significand after normalization. This 
               
               
                   
                 normalized 
                 result is truncated (round to zero) to form the final result significand 
               
               
                   
                 significand T 
                 T 53R. This field is t 104 bits in width. 
               
               
                  57R 
                 resulting rounding 
                 is a field (of width r 108) holding the most significant bits of the 
               
               
                   
                 bits R Field 
                 resulting significand that are lost due to truncation. These bits are 
               
               
                   
                   
                 used inventively to accumulate rounding error. 
               
               
                  60R 
                 extended rounding 
                 is a field (of width x 502) holding the bits of the result lost due to 
               
               
                   
                 error X Field 
                 truncation, which is to the right of the R Field 57R in the format. 
               
               
                   
                   
                 These bits provide something similar to the conventional “sticky bit.” 
               
               
                 502 
                 extended rounding 
                 is the virtual width, x, of the X Field 60R. 
               
               
                   
                 error width x 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIGS. 6A and 6B 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 600 
                 main bound circuit 
                 is the inventive aggregate circuit that calculates the result bound B 
               
               
                   
                   
                 52C from the dominant bound B 52H, the carry adjusted bound B 
               
               
                   
                   
                 52M, the number of leading zeros 711, and the significand capacity 
               
               
                   
                   
                 805. 
               
               
                  54C 
                 dominant bound 
                 is the lost bits D Field 54 of the dominant bound B 52H. 
               
               
                   
                 lost bits D 
               
               
                  55B 
                 dominant bound 
                 is the accumulated rounding error N Field 55 of the dominant bound 
               
               
                   
                 accumulated 
                 B 52H. 
               
               
                   
                 rounding error N 
               
               
                 610 
                 lost bits adder 
                 is the inventive circuit that adds the number of leading zeros 711 to 
               
               
                   
                   
                 the dominant bound lost bits D 54C to obtain the adjusted lost bits D 
               
               
                   
                   
                 54D clamped to t 104 or less. When a significand is shifted left to 
               
               
                   
                   
                 normalize (cancellation), insignificant bits are shifted in from the 
               
               
                   
                   
                 right increasing the number of lost bits in the result. 
               
               
                  54D 
                 adjusted lost bits D 
                 is the dominant bound lost bits D 54C adjusted by the number of 
               
               
                   
                   
                 leading zeros 711, the number of bits shifted left during 
               
               
                   
                   
                 normalization. The adjusted lost bits cannot exceed the width t 104 
               
               
                   
                   
                 of the significand field T 53. 
               
               
                 616 
                 max lost bits 
                 is the newly invented maximum lost bits detector that determines 
               
               
                   
                 detector 1 
                 when the adjusted lost bits D 54D is greater than the significand 
               
               
                   
                   
                 capacity 805. This controls the 1 st  lost bits selector 615. 
               
               
                 617 
                 max lost bits 1 
                 is the signal indicating that the adjusted lost bits 54D is greater than 
               
               
                   
                   
                 the significand capacity 805 indicating that there are no significant 
               
               
                   
                   
                 bits. This controls the 1 st  lost bits selector 615. 
               
               
                 615 
                 1 st  lost bits selector 
                 is a newly invented circuit that prohibits the lost bits of the adjusted 
               
               
                   
                   
                 bound D 54D from exceeding the significand capacity 805. When the 
               
               
                   
                   
                 max lost bits detector 616 is asserted the resulting lost bits D 54H is 
               
               
                   
                   
                 constrained to the significand capacity 805 indicating that the 
               
               
                   
                   
                 significand contains no significant digits otherwise the resulting lost 
               
               
                   
                   
                 bits D 54H is set to the adjusted lost bits D 54D. 
               
               
                  54H 
                 resulting lost bits D 
                 is the adjusted lost bits D 54D constrained to the significand capacity 
               
               
                   
                   
                 805 controlled by max lost bits 1 617 signal indicating that the 
               
               
                   
                   
                 significand contains no significant digits. 
               
               
                  52J 
                 cancellation 
                 is the concatenation of the adjusted lost bits D 54D and the dominant 
               
               
                   
                 adjusted bound B 
                 bound accumulated rounding error N 55B. 
               
               
                 620 
                 cancellation 
                 is the inventive circuit that asserts cancelation control 621 when 
               
               
                   
                 detector circuit 
                 there is cancellation by determining that the number of leading zeros 
               
               
                   
                   
                 711 is greater than one. 
               
               
                 621 
                 cancellation control 
                 is the control signal indicating that cancellation has occurred as 
               
               
                   
                   
                 determined by the cancellation detector circuit 620 controlling the 
               
               
                   
                   
                 result of the result bound multiplexer 630. 
               
               
                 630 
                 result bound 
                 is the inventive circuit that selects either the cancellation adjusted 
               
               
                   
                 multiplexer 
                 bound B 52J or the carry adjusted bound B 52M depending on 
               
               
                   
                   
                 whether cancellation occurred (cancellation control 621). This 
               
               
                   
                   
                 determines the result bound B 52C. 
               
               
                 640 
                 rounding error 
                 is the inventive circuit that adds the significand excess 741 and the 
               
               
                   
                 adder 
                 normalized rounding error R 57A to the dominant bound B 52H 
               
               
                   
                   
                 yielding the rounding error sum B 52K. 
               
               
                  52K 
                 rounding error sum 
                 is the bound calculated by the rounding error adder 640 by adding 
               
               
                   
                 B 
                 the significand excess 741 and the normalized rounding error R 57A 
               
               
                   
                   
                 to the dominant bound B 52H as a single value with carries from the 
               
               
                   
                   
                 rounding bits field R 57 of accumulated rounding error field N 54 
               
               
                   
                   
                 adding to the rounding error count field C 56 with further carries 
               
               
                   
                   
                 from the rounding error count field C 56 adding to the lost bits field 
               
               
                   
                   
                 D 54 of the dominant bound B 52H. 
               
               
                  54K 
                 updated 
                 is the extension count 56 C field of the accumulated rounding error 
               
               
                   
                 accumulated 
                 55 N field of the rounding error sum B 52K. 
               
               
                   
                 rounding error 
               
               
                   
                 extension count C 
               
               
                 680 
                 count logarithm 
                 is the inventive circuit that determines the rounding count logarithm 
               
               
                   
                 circuit 
                 61 for the updated accumulated rounding error extension count C 
               
               
                   
                   
                 54K. 
               
               
                  61 
                 rounding count 
                 is the floor function of the base 2 logarithm of the updated 
               
               
                   
                 logarithm 
                 accumulated rounding error extension count C 54K. 
               
               
                 650 
                 log count 
                 is the inventive circuit that compares the dominant bound lost bits D 
               
               
                   
                 comparator 
                 54C to the rounding count logarithm 61 to produce the count 
               
               
                   
                   
                 overflow 651. 
               
               
                 651 
                 count overflow 
                 is asserted by the count comparator 650 when the rounding count 
               
               
                   
                   
                 logarithm 61 is greater than or equal to the dominant bound lost bits 
               
               
                   
                   
                 D 54C. The count overflow controls the adjusted bound multiplexer 
               
               
                   
                   
                 670 and provides input to the lost bits incrementor 660, 
               
               
                 660 
                 lost bits 
                 is the inventive circuit that adds one to the dominant bound lost bits 
               
               
                   
                 incrementer 
                 D 54C when the count overflow 651 is asserted. 
               
               
                  54E 
                 incremented lost 
                 is the dominant bound lost bits D 54C adjusted by the count 
               
               
                   
                 bits D 
                 overflow 651. 
               
               
                 661 
                 max lost bits 
                 is the newly invented second maximum lost bits that detects when 
               
               
                   
                 detector 2 
                 the incremented lost bits 54E is greater than the significand capacity 
               
               
                   
                   
                 805 contributing to the second lost bits selector 665. 
               
               
                 662 
                 max lost bits 2 
                 is the signal indicating that the incremented lost bits 54E is greater 
               
               
                   
                   
                 than the significand capacity 805 indicating that there are no 
               
               
                   
                   
                 significant bits indicated in the dominant bound 52H while 
               
               
                   
                   
                 controlling the second lost bits selector 665. 
               
               
                 665 
                 2nd lost bits 
                 is a newly invented circuit that prohibits the incremented lost bits D 
               
               
                   
                 selector 
                 54E from exceeding the significand capacity 805. When the lost bits 
               
               
                   
                   
                 incrementer 660 produces a value greater than the significand 
               
               
                   
                   
                 capacity 805 the clamped incremented lost bits D 54J is constrained 
               
               
                   
                   
                 to the significand capacity 805 indicating that the significand 
               
               
                   
                   
                 contains no significant digits. 
               
               
                  54J 
                 clamped 
                 is the clamped incremented lost bits D 54E constrained to the 
               
               
                   
                 incremented lost 
                 significand capacity 805 indicating that the significand contains no 
               
               
                   
                 bits D 
                 significant digits. 
               
               
                  52L 
                 lost bits adjusted 
                 is the bound comprised of the concatenation of the clamped 
               
               
                   
                 bound B 
                 incremented lost bits D 54J and a zero for the value of the 
               
               
                   
                   
                 accumulated rounding error field N 55 and the updated accumulated 
               
               
                   
                   
                 rounding error rounding bits R 57B. This adds one to the lost bits 
               
               
                   
                   
                 when the logarithm of the number of bits lost due to rounding equals 
               
               
                   
                   
                 the current number of lost bits. 
               
               
                  57B 
                 updated 
                 is the rounding bits 57 R field of the accumulated rounding error 55 
               
               
                   
                 accumulated 
                 N field of the rounding error sum B 52K. 
               
               
                   
                 rounding error 
               
               
                   
                 rounding bits 
               
               
                 670 
                 adjusted bound 
                 is the inventive circuit that selects either the lost bits adjusted bound 
               
               
                   
                 multiplexer 
                 B 52L, when count overflow 651 is asserted, or the rounding error 
               
               
                   
                   
                 sum B 52K producing the carry adjusted bound B 52M. 
               
               
                  52M 
                 carry adjusted 
                 is the bound adjusted for potential rounding error selected between 
               
               
                   
                 bound B 
                 the rounding error sum B 52K and the lost bits adjusted bound B 
               
               
                   
                   
                 52L. 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 7 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 700 
                 normalization 
                 is the modified conventional compound circuit that produces the 
               
               
                   
                 circuit 
                 truncated resulting T 53C, the result exponent E 51C, the 
               
               
                   
                   
                 number of leading zeros 711, the significand excess 741, and the 
               
               
                   
                   
                 carry detection 701 from the sum or difference 251 and the largest 
               
               
                   
                   
                 exponent E 51D. This circuit inventively also provides number of 
               
               
                   
                   
                 leading zeros 711 to the inventive main bound circuit 600 and the 
               
               
                   
                   
                 inventive exception circuit 800. In addition it contains the inventive 
               
               
                   
                   
                 circuit, the excess significance detector circuit 740. 
               
               
                 701 
                 carry detection 
                 is the conventional circuit that determines whether the sum or 
               
               
                   
                   
                 difference 251 had a carry out requiring a right shift to normalize and 
               
               
                   
                   
                 establishes the right shift control 702 and contributes to the exponent 
               
               
                   
                   
                 normalization adder 730. 
               
               
                 702 
                 right shift control 
                 is the conventional circuit that controls whether the sum or difference 
               
               
                   
                   
                 251 must be shifted right to normalize the significand. Controls the 
               
               
                   
                   
                 right shifter 703. 
               
               
                 703 
                 right shifter 
                 is the modified conventional circuit that, when indicated by the right 
               
               
                   
                   
                 shift control 702, shifts the sum or difference 251 right one bit 
               
               
                   
                   
                 producing the right shift result 704. It is modified by the addition of 
               
               
                   
                   
                 the inventive right shift loss circuit 705. 
               
               
                 704 
                 right shift result 
                 is the result after normalizing the sum or difference 251 determined 
               
               
                   
                   
                 by the right shift control 702. When the right shift control 702 is not 
               
               
                   
                   
                 asserted the right shift result 704 is equal to the sum or difference 
               
               
                   
                   
                 251. 
               
               
                 705 
                 right shift loss 
                 is the inventive circuit that, when a one bit (a true bit) is shifted out 
               
               
                   
                 circuit 
                 of the right shift result 704, a one bit is inserted into the right shift 
               
               
                   
                   
                 result 704 ensuring that a significand excess 741 will be detected. 
               
               
                 710 
                 most significant 
                 is the extended conventional circuit that counts most significant zeros 
               
               
                   
                 zeros counter 
                 of the sum or difference 251 necessary to normalize by shifting left. 
               
               
                   
                   
                 Produces the number of leading zeros 711 to control the left shifter 
               
               
                   
                   
                 712 and to contribute to the computation of the result exponent E 
               
               
                   
                   
                 51C. In addition, it inventively contributes to the main bound circuit 
               
               
                   
                   
                 600 by providing the input to the cancellation detector circuit 620 
               
               
                   
                   
                 and the input to the exception circuit 800 by providing input to the 
               
               
                   
                   
                 significant zeros detector 830. 
               
               
                 711 
                 number of leading 
                 is the number of most significant leading zeros. Controls the left 
               
               
                   
                 zeros 
                 shifter 712 and the cancellation detector circuit 620 and provides 
               
               
                   
                   
                 input to the significant zeros detector 830. 
               
               
                 712 
                 left shifter 
                 is the conventional normalization circuit that shifts the right shift 
               
               
                   
                   
                 result 704 left the number of bits specified by number of leading 
               
               
                   
                   
                 zeros 711 required to normalize the right shift result 704 to produce 
               
               
                   
                   
                 the normalized result 720. If the most significant zeros counter 710 
               
               
                   
                   
                 results in no leading zeros, the normalized result 720 is equal to the 
               
               
                   
                   
                 right shift result 704 and can be no greater than the significand width 
               
               
                   
                   
                 t 104. 
               
               
                 720 
                 normalized result 
                 is the result of normalizing the sum or difference 251. 
               
               
                 730 
                 exponent 
                 is the conventional circuit that adjusts the largest exponent E 51D for 
               
               
                   
                 normalization adder 
                 normalization. When the right shift control 702 is asserted one is 
               
               
                   
                   
                 added to the largest exponent E 51D; otherwise the number of 
               
               
                   
                   
                 leading zeros 711 is subtracted from the largest exponent E 51D. 
               
               
                   
                   
                 Either case produces the result exponent E 51C. 
               
               
                  57A 
                 normalized 
                 is the inventive most significant r bits 108 of the normalized result 
               
               
                   
                 rounding error R 
                 720 that are lost due to truncation. 
               
               
                  60A 
                 normalized 
                 is the x 502 inventive bits of the normalized result 720 to the right of 
               
               
                   
                 extension X 
                 the normalized rounding error R 57A created by alignment or 
               
               
                   
                   
                 normalization but lost due to truncation. 
               
               
                 740 
                 excess significand 
                 creates the logical OR of all bits of the normalized extension X 60A 
               
               
                   
                 detector circuit 
                 producing the significand excess 741. 
               
               
                 741 
                 significand excess 
                 is the logical OR of all bits of the normalized extension X 60A and 
               
               
                   
                   
                 contributes to the rounding error sum 52K. 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 8 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 800 
                 exception circuit 
                 is the inventive aggregate circuit that determines zero control signal 
               
               
                   
                   
                 860 from the significand capacity 805 from the significand capacity 
               
               
                   
                   
                 memory circuit 820, the dominant bound lost bits D 54C, the bound 
               
               
                   
                   
                 limit 54M from the bound limit memory 810 and the number of 
               
               
                   
                   
                 leading zeros 711. This circuit also generates an sNaN(isb) exception 
               
               
                   
                   
                 940 derived from the bound limit 54M from the bound limit memory 
               
               
                   
                   
                 810 and the operand bound lost bits 54F under program control of 
               
               
                   
                   
                 the processor error limit set/check command 901. 
               
               
                 810 
                 bound limit 
                 provides the maximum allowed lost bits; the bound limit 54M as set 
               
               
                   
                 memory 
                 by the processor error limit set/check command 901 to the value 
               
               
                   
                   
                 determined by the maximum lost bits 54. 
               
               
                  54M 
                 bound limit 
                 is the maximum allowed lost bits for the specified operation width 
               
               
                   
                   
                 control 902 and is utilized by the sNaN detection comparator 850 to 
               
               
                   
                   
                 determine the sNaN(isb) exception 940 and by the significant bits 
               
               
                   
                   
                 subtractor 840 to provide the zero selection control signal 860 
               
               
                   
                   
                 indicating that the current result is significantly zero. 
               
               
                 820 
                 significand capacity 
                 is an inventive static memory that provides the size of the significand 
               
               
                   
                 memory circuit 
                 (t + 1), significand capacity 805 for the width of the current operation. 
               
               
                   
                   
                 Memory is addressed by the operation width control 902. 
               
               
                 805 
                 significand capacity 
                 is the number of bits representing the significand (t + 1), including the 
               
               
                   
                   
                 hidden bit H 510, in the operands of the current bounded floating- 
               
               
                   
                   
                 point operation. 
               
               
                 840 
                 significant bits 
                 determines the available significant bits 841 by subtracting the 
               
               
                   
                 subtractor 
                 dominant bound lost bits D 54C from the significand capacity 805. 
               
               
                 841 
                 available significant 
                 is the number of significant bits available from the operands after 
               
               
                   
                 bits 
                 exponent alignment determined by subtracting the dominant bound 
               
               
                   
                   
                 lost bits D 54C from the significand capacity 805. 
               
               
                 830 
                 significant zeros 
                 is the new and unique device that compares the available significant 
               
               
                   
                 detector 
                 bits 841 to the number of leading zeros 711 to produce significant 
               
               
                   
                   
                 leading zeros detected 831. 
               
               
                 831 
                 significant leading 
                 is the signal indicating that significant leading zeros have been 
               
               
                   
                 zeros detected 
                 detected, but not necessarily a significant result. This is used by the 
               
               
                   
                   
                 significantly zero detection circuit 861 to determine if the result is 
               
               
                   
                   
                 significantly zero to generate the zero-selection control signal 860. 
               
               
                 861 
                 significantly zero 
                 is the newly invented circuit that assert the zero-sei ection control 
               
               
                   
                 detector 
                 signal 860 when there are significant leading zeros detected 831 and 
               
               
                   
                   
                 there are significant digits 871. 
               
               
                 870 
                 significant digits 
                 is the newly invented circuit that asserts the significant digits signal 
               
               
                   
                 detector 
                 871 when the dominant bound lost bits D 54C is less than or equal to 
               
               
                   
                   
                 the bound limit 54M indicating that the dominant bound B 52H 
               
               
                   
                   
                 contains significant digits. 
               
               
                 871 
                 significant digits 
                 is a signal that indicates that the dominant bound B 52H contains 
               
               
                   
                   
                 significant digits. 
               
               
                 860 
                 zero selection 
                 is the signal provided to the exception and result multiplexer 270 to 
               
               
                   
                 control signal 
                 select zero as the bounded floating-point result 280. 
               
               
                  54F 
                 operand bound lost 
                 is the data in the lost bits D Field 54 portion of the first operand 
               
               
                   
                 bits D 
                 bound B 52A of the operand selected by the error limit set/check 
               
               
                   
                   
                 command 901. 
               
               
                 850 
                 sNaN detection 
                 recognizes the error limit set/check command 901 and produces the 
               
               
                   
                 comparator 
                 sNaN(isb) exception 940 when operand bound lost bits D 54F is 
               
               
                   
                   
                 greater than the bound limit 54M. 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 FIG. 9 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 900 
                 bounded floating- 
                 is a system for computing numbers in bounded floating-point format 
               
               
                   
                 point system 
                 consisting of a main processing unit 910 with associated registers 
               
               
                   
                   
                 990 and communicating with a bounded floating-point unit (BFPU) 
               
               
                   
                   
                 950. The bounded floating-point unit 950 may be integrated with a 
               
               
                   
                   
                 physical conventional floating-point unit sharing registers and logical 
               
               
                   
                   
                 circuits with the conventional floating-point unit or the integrated 
               
               
                   
                   
                 floating-point unit may be integrated with a conventional main 
               
               
                   
                   
                 processing unit 910 sharing registers 990 and logical circuits with the 
               
               
                   
                   
                 conventional main processing unit 910. 
               
               
                 901 
                 error limit set/check 
                 is the command from the main processing unit 910 storing the 
               
               
                   
                 command 
                 command specified maximum lost bits D 54L for the current 
               
               
                   
                   
                 instruction width in the bound limit memory 810 and commanding 
               
               
                   
                   
                 an error limit check that generates an sNaN(sig) 940 by comparing 
               
               
                   
                   
                 against the lost bits 54F of the specified operand 201. Note that an 
               
               
                   
                   
                 error limit set/check command against an operand with no lost bits 
               
               
                   
                   
                 only sets the bound limit memory for succeeding instructions such as 
               
               
                   
                   
                 subtract operations when testing for equality. 
               
               
                 902 
                 operation width 
                 is a signal provided by the processor indicating the width of the 
               
               
                   
                 control 
                 current bounded floating-point operation in the form of an address. 
               
               
                 910 
                 main processing 
                 executes internal instructions accessing data 201, 202, 831, 280 from, 
               
               
                   
                 unit 
                 and to, a plurality of registers 990 (where a register may be a 
               
               
                   
                   
                 hardware register, a location in a register file, or a memory location 
               
               
                   
                   
                 that may be an integral part of the main processing unit 910) and 
               
               
                   
                   
                 outputs or executes floating-point or bounded floating-point 
               
               
                   
                   
                 commands 831, 901 and outputs or utilizes the data, the first operand 
               
               
                   
                   
                 201, the second operand 202, and the programmed bound limit 831. 
               
               
                 930 
                 bounded floating- 
                 a bounded floating-point arithmetic instruction such as multiply, 
               
               
                   
                 point arithmetic 
                 divide, square root, subtract, or the exemplar bounded floating-point 
               
               
                   
                 instruction 
                 add operation. 
               
               
                  54L 
                 maximum lost bits 
                 is the maximum number of lost bits specified by the error limit 
               
               
                   
                 D 
                 set/check command 901 to be compared to the lost bits 54F of the 
               
               
                   
                   
                 specified operand 201 and when larger generates a signaling 
               
               
                   
                   
                 sNaN(isb) exception 940. 
               
               
                 940 
                 sNaN(isb) 
                 a bounded floating-point signaling NaN processor exception as 
               
               
                   
                 exception 
                 determined by the sNaN detection comparator 810. 
               
               
                 950 
                 bounded floating- 
                 is the portion of the bounded floating-point system 900 that executes 
               
               
                   
                 point unit (BFPU) 
                 bounded floating-point arithmetic instructions 930 on the first 
               
               
                   
                   
                 operand 201 and the second operand 202 producing the bounded 
               
               
                   
                   
                 floating-point result 280 or generate a sNaN(isb) exception 940, 
               
               
                   
                   
                 when the processing unit 910 issues a precision check command 910 
               
               
                   
                   
                 and the maximum lost bits D 54L is greater than or equal to the 
               
               
                   
                   
                 operand bound lost bits D 54F from the first operand 201. The 
               
               
                   
                   
                 conceptual bounded floating-point unit may be integrated with a 
               
               
                   
                   
                 conventional floating-point unit sharing registers 990 and logical 
               
               
                   
                   
                 circuits with the conventional floating-point unit or the integrated 
               
               
                   
                   
                 floating-point unit may be integrated with a conventional main 
               
               
                   
                   
                 processing unit 910 sharing registers 990 and logical circuits with the 
               
               
                   
                   
                 conventional main processing unit 910. 
               
               
                 990 
                 registers 
                 is a plurality of registers (where a register may be a hardware 
               
               
                   
                   
                 register, a location in a register file, or a memory location). Provides 
               
               
                   
                   
                 storage for the bounded floating-point first input operand 201, the 
               
               
                   
                   
                 bounded floating-point second input operand 202, bounded floating- 
               
               
                   
                   
                 point result (280). Registers utilized by the bounded floating-point 
               
               
                   
                   
                 unit 950 may be integrated into the bounded floating-point unit 950 
               
               
                   
                   
                 or may be part of, and integrated into, a conventional floating-point 
               
               
                   
                   
                 unit, or may be part of, and integrated into, the main processing unit 
               
               
                   
                   
                 910.