Patent Publication Number: US-10325051-B2

Title: Exact delay synthesis

Description:
RELATED APPLICATION 
     This application is a continuation-in-part of pending U.S. application Ser. No. 15/382,406, which was filed on 16 Dec. 2016, the contents of which are herein incorporated by reference in their entirety for all purposes. This application also claims priority to U.S. Provisional Application No. 62/489,674, filed on 25 Apr. 2017, the contents of which are herein incorporated by reference in their entirety for all purposes. 
    
    
     BACKGROUND 
     Technical Field 
     This disclosure relates to optimization. More specifically, this disclosure relates to timing optimization in integrated circuit (IC) designs. 
     Related Art 
     Advances in process technology and an almost unlimited appetite for consumer electronics have fueled a rapid increase in the size and complexity of IC designs. Software tools can be used to perform various operations on IC designs, e.g., creating and editing schematics and layouts, synthesizing, optimizing, and verifying IC designs, etc. What are needed are high-performance user-friendly software tools that enable an IC designer to create IC designs that reduce the overall IC design time and/or improve the overall quality of results (QoR). 
     SUMMARY 
     Some embodiments described herein feature systems and techniques for optimizing an IC design. Some embodiments can determine a logic function that is implemented by a combinational logic circuit in the IC design. Next, the embodiments can determine a permutation class representative and a permutation based on the logic function. The embodiments can then determine a first index based on the permutation class representative. Next, the embodiments can obtain an arrival time pattern by compressing a set of input arrival times corresponding to the combinational logic circuit. The embodiments can then apply the permutation to the arrival time pattern to obtain a permutated arrival time pattern. Next, the embodiments can determine a second index based on the permutated arrival time pattern. The embodiments can then perform an exact delay database lookup using the first index and the second index to obtain an optimized combinational logic circuit. Next, the embodiments can permute inputs of the optimized combinational logic circuit according to the permutation to obtain an optimized-and-permutated combinational logic circuit. The embodiments can then obtain an optimized IC design by replacing the combinational logic circuit in the IC design with the optimized-and-permutated combinational logic circuit in the IC design. 
     In some embodiments, obtaining the arrival time pattern by compressing the set of input arrival times corresponding to the combinational logic circuit comprises: (1) determining an upper bound for a critical path delay of an optimized version of the combinational logic circuit; (2) determining a first value by subtracting the upper bound from a maximum input arrival time in the set of input arrival times; (3) for each input arrival time t that is less than the first value, setting t to be equal to the first value; and (4) subtracting a minimum input arrival time in the set of input arrival times from each input arrival time in the set of input arrival times. 
     In some embodiments, determining the second index based on the permutated arrival time pattern comprises converting the permutated arrival time pattern into an integer in base (D+1), where D is an upper bound for a critical path delay of an optimized version of the combinational logic circuit. 
     In some embodiments, rational valued input arrival times and delays can be converted into integer valued input arrival times and delays by dividing each input arrival time and delay by a minimum delay precision of a gate library that is used to implement the IC design. 
    
    
     
       BRIEF DESCRIPTION OF THE FIGURES 
         FIGS. 1A-1C  illustrate how timing information can be propagated in an IC design. 
         FIG. 2A  illustrates a process for creating a database of optimal circuit implementations in accordance with some embodiments described herein. 
         FIG. 2B  illustrates pseudocode for explicitly enumerating exact delay circuits in accordance with some embodiments described herein. 
         FIG. 2C  illustrates pseudocode for Satisfiability Modulo Theory (SMT)-based exact delay synthesis in accordance with some embodiments described herein. 
         FIG. 3  illustrates how a logic-function identifier can be determined for a logic function in accordance with some embodiments described herein. 
         FIG. 4  illustrates how the optimal circuit implementation can depend on the arrival time in accordance with some embodiments described herein. 
         FIG. 5A  illustrates a process for determining an arrival-time-pattern identifier in accordance with some embodiments described herein. 
         FIG. 5B  illustrates a process for determining an arrival-time-pattern identifier in accordance with some embodiments described herein. 
         FIG. 6A  illustrates a process for performing timing optimization in an IC design in accordance with some embodiments described herein. 
         FIG. 6B  illustrates a process for performing timing optimization in an IC design in accordance with some embodiments described herein 
         FIG. 7  illustrates how a fan-in combinational-logic-cone can be determined in accordance with some embodiments described herein. 
         FIG. 8  illustrates an IC design system in accordance with some embodiments described herein. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is presented to enable any person skilled in the art to make and use the invention, and is provided in the context of a particular application and its requirements. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the present invention. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     Overview of IC Design and Manufacturing 
     IC design software tools can be used to create an IC design. Once the IC design is finalized, it can undergo fabrication, packaging, and assembly to produce IC chips. The overall IC design and manufacturing process can involve multiple entities, e.g., one company may create the software for designing ICs, another company may use the software to create the IC design, and yet another company may manufacture IC chips based on the IC design. An IC design flow can include multiple steps, and each step can involve using one or more IC design software tools. An improvement to one or more of these steps in the IC design flow results in an improvement to the overall IC design and manufacturing process. Specifically, the improved IC design and manufacturing process can produce IC chips with a shorter time-to-market (TTM) and/or higher quality of results (QoR). Some examples of IC design steps and the associated software tools are described below. These examples are for illustrative purposes only and are not intended to limit the embodiments to the forms disclosed. 
     Some IC design software tools enable IC designers to describe the functionality that the IC designers want to implement. These tools also enable IC designers to perform what-if planning to refine functionality, check costs, etc. During logic design and functional verification, the HDL (hardware description language), e.g., SystemVerilog, code can be written and the design can be checked for functional accuracy, e.g., the design can be checked to ensure that it produces the correct outputs. 
     During synthesis and design for test, the HDL code can be translated to a netlist using one or more IC design software tools. Further, the netlist can be optimized for the target technology, and tests can be designed and implemented to check the finished chips. During netlist verification, the netlist can be checked for compliance with timing constraints and for correspondence with the HDL code. Embodiments described herein can be used in multiple steps of the IC design flow. Specifically, some embodiments can be used during synthesis. 
     During design planning, an overall floorplan for the chip can be constructed and analyzed for timing and top-level routing. During physical implementation, circuit elements can be positioned in the layout and can be electrically coupled. 
     During analysis and extraction, the IC design&#39;s functionality can be verified at a transistor level and parasitics can be extracted. During physical verification, the design can be checked to ensure correctness for manufacturing, electrical issues, lithographic issues, and circuitry. 
     During resolution enhancement, geometric manipulations can be performed on the layout to improve manufacturability of the design. During mask data preparation, the design can be “taped-out” to produce masks which are used during fabrication. 
     Static Timing Analysis (STA) 
     An important performance metric for an IC design is the clock frequency at which the manufactured IC can reliably operate. STA is an invaluable tool for determining whether an IC design will reliably operate at a given clock frequency. Since STA uses an approximate model for the IC design, even if STA concludes that an IC design will reliably operate at a particular clock frequency, the IC design may fail to do so. Nevertheless, STA has emerged as the method of choice for verifying timing constraints for large IC designs because STA performs a reasonably accurate timing analysis within a reasonable amount of time. 
     In STA, the required times and arrival times are propagated through a graph-based representation of the IC design. Timing violations in the IC design can then be determined using the required times and the arrival times. Note that there are at least two types of timing violations: setup time violation and a hold time violation. In a setup time violation, a signal reaches a pin later than it is supposed to reach, e.g., a setup time violation may occur when a signal reaches a register input after the clock transition. In a hold time violation, a signal does not remain stable for a sufficient amount of time, e.g., a signal at a register&#39;s input may change before the register can capture the signal&#39;s value. General background information on static timing analysis and propagation of timing information can be found in Luciano Lavagno (Editor), Louis Scheffer (Editor), Grant Martin (Editor),  EDA for IC Implementation, Circuit Design, and Process Technology  ( Electronic Design Automation for Integrated Circuits Handbook ), CRC Press, 1 st  Ed., March 2006. 
       FIGS. 1A-1C  illustrate how timing information can be propagated in an IC design.  FIG. 1A  illustrates an IC design with delay values, arrival times, and required times. IC design  100  includes circuit blocks  102 ,  104 ,  106 ,  108 ,  110 ,  112 , and  114 . A circuit block can be an arbitrary portion of an IC design. Specifically, a circuit block can include one or more cells and/or one or more gates. IC design  100  has three inputs A, B, and C, and three outputs X, Y, and Z. The term “timing endpoints” or “endpoints” for short can generally be any set of terminals or pins (e.g., inputs or outputs of combinational or sequential circuit elements) in the IC design where the timing information is of interest. The timing endpoints are typically the outputs of an IC design, or an input of a register in the IC design. The timing endpoints in  FIGS. 1A-1C  are outputs X, Y, and Z because we are interested in the timing information at these points. 
     The delay for each circuit block is shown within the circuit block. For example, circuit block  102  includes text “d=6”, which specifies that circuit block  102  has a delay of 6 time units (for example, if each time unit is equal to 5 ns, then a delay of 6 time units will be equal to 30 ns). A simplified delay model has been used in  FIGS. 1A-1C  for the sake of clarity and ease of discourse. A more complicated delay model can have different delay values for each input/output pair, considering output loading and input transition values. Further, the delay model can have different delay values for different rise and fall transition times. Additionally, the delay model may consider various forms of net (wire) delays and parasitic capacitances. Although  FIGS. 1A-1C  use a simplified delay model, it will be apparent to a person having ordinary skill in the art that techniques and systems described in this disclosure are readily applicable to more complex delay models. 
     The arrival times at inputs A, B, and C are shown next to the inputs. For example, the text “a=2” appears next to input A, which indicates that the arrival time at input A is equal to 2 time units. The arrival time at a pin indicates when the signal arrives at the pin. The required times at outputs X, Y, and Z are shown next to the outputs. For example, the text “r=11” appears next to output X, which indicates that the required time at output X is equal to 11 time units. The required time at a pin indicates when the signal is required to arrive at the pin. 
       FIG. 1B  illustrates the result of propagating arrival times in a forward direction (i.e., from inputs to outputs) and propagating required times in a backward direction (i.e., from outputs to inputs) through the IC design. At each circuit block, the worst-case arrival time is propagated forward. Similarly, the worst-case required time is propagated backward. Note that the definition of “worst case” depends on whether the timing information is being propagated for determining setup violations or for determining hold violations. Specifically, in the case of setup violations, the maximum values are propagated, whereas in the case of hold violations, the minimum values are propagated. 
       FIG. 1C  illustrates how slack values can be determined. At each pin, the arrival time is subtracted from the required time to obtain the slack value. For example, the slack value at the output of circuit block  102  is equal to −2 (6−8). Slack values for other pins can be determined in a similar fashion. 
     The slack value indicates whether a timing constraint is being violated or not. Typically, a user can specify an acceptable slack value, that is, a slack threshold. The slack at a pin can be compared with the slack value to determine whether or not the pin has violated a timing constraint. Different slack thresholds can be used for different parts of the IC design. Further, the definition of a violation can depend on the type of the timing constraint. For example, for one type of timing constraint, a violation may occur if the slack value is less than the threshold, whereas for another type of timing constraint, a violation may occur if the slack value is greater than the threshold. Typically, the slack threshold is zero for setup timing constraints, and a violation occurs when the slack value is negative. A path is a violating path if the slack at the path&#39;s endpoint is a violating slack. The worst negative slack corresponds to the worst timing or worst slack of the IC design. 
     The IC design  100  in  FIG. 1C  has two endpoints, namely X and Y, with negative slack values: endpoint X has slack value −1 and endpoint Y has slack value −2. Endpoint Z, however, has a positive slack value 1. The critical path for endpoint Y is shown in bold, tracing the path starting at primary input C through circuit block  106  and circuit block  114  to endpoint Y. The path terminating at endpoint Z is not a violating path because its slack value is positive (in this example, we are assuming that a slack value is violating if it is negative). The critical path length or the critical path delay of a critical path is the total delay along the critical path. The critical path delay can be determined by aggregating the delays along the critical path. For example, the critical path delay of the critical path between input C and output Y is 7 time units. 
     Exact Delay Synthesis 
     Consider the following timing optimization problem: determine a circuit implementation that minimizes the arrival time at an output of the circuit implementation given (1) a logic function (i.e., a Boolean function) that the circuit implementation is supposed to implement, (2) a set of arrival times at the inputs of the Boolean function, and (3) a set of primitive gates with associated delay values that can be used for creating the circuit implementation. Existing approaches include techniques based on Huffman decomposition, Shannon co-factoring, redundancy removal, etc. These approaches are based on heuristics, and as such they do not guarantee that the globally optimal circuit implementation will be found. In contrast to such approaches, some embodiments described herein determine and use the globally optimal solution to the above-mentioned timing optimization problem. 
     Specifically, some embodiments described herein create a database of optimal circuit implementations. Given (1) a logic function that the circuit implementation is supposed to implement, (2) a set of arrival times at the inputs of the logic function, and (3) a set of primitive gates with associated delay values that can be used for creating the circuit implementation, the embodiments create a database of optimal circuit implementations that can be indexed based on the logic function and the set of arrival times at the inputs of the logic function. 
     There are many challenges for computing such a database. First, the arrival times are unbounded, i.e., each arrival time can potentially take on a value between 0 and +∞. If there are n inputs, then we need to account for ∞ n  sets of arrival times. Second, the number of possible Boolean functions (i.e., logic functions) is super exponential in the number of inputs, i.e., there are 2 2^n  possible Boolean functions with n inputs. Third, the delay computation depends on the given library of gates, and the gate delay depends on the specific semiconductor manufacturing technology that is used for fabricating the IC chip. Moreover, the delay ratio between a basic 2-input AND gate and more complex gates (e.g., a 2-input XOR gate) is not fixed. 
     Of these challenges, handling the potentially ∞ n  sets of arrival times is the most difficult. Some embodiments described herein map the set of arrival times to an arrival time pattern that is selected from a finite set of arrival time patterns without compromising the optimality of the final circuit implementation. In other words, the optimal circuit implementation for a given arrival time pattern is guaranteed to be the optimal circuit implementation for all of the sets of arrival times (which are infinite in number) that map to the given arrival time pattern. For example, for a 4-input Boolean function, the ∞ 4  sets of arrival times can be mapped to 280 distinct arrival time patterns. Likewise, for a 5-input Boolean function, the ∞ 5  sets of arrival times can be mapped to about 1,000 distinct arrival time patterns. Some embodiments described herein assume that a 2-input AND gate and a 2-input OR gate have a unit delay. More complex gates are assumed to have delays that are represented in terms of this unit delay, e.g., a 2-input XOR gate or MUX gates have a delay of 2 units. Moreover, arrival times are normalized based on the unit delays of the 2-input AND gate and the 2-input OR gate. 
       FIG. 2A  illustrates a process for creating a database of optimal circuit implementations in accordance with some embodiments described herein. The process can begin by selecting a logic function from a set of possible logic functions (block  202 ). Next, the process can select an arrival time pattern from a set of possible arrival time patterns (block  204 ). The process can then determine an optimal circuit implementation for the selected arrival time pattern, wherein the optimal circuit implementation implements the logic function (block  206 ). Next, the process can store the optimal circuit implementation in a database, and associate the optimal circuit implementation with (1) a logic-function identifier that corresponds to the selected logic function, and (2) an arrival-time-pattern identifier that corresponds to the selected arrival time pattern (block  208 ). The association is stored in the database, thereby allowing the optimal circuit implementation to be looked-up based on the logic-function identifier and the arrival-time-pattern identifier. The process can then check if more arrival time patterns need to be processed (block  210 ). If so, the process can return to block  204  and select the next arrival time pattern. Otherwise, the process can check if more logic functions need to be processed (block  212 ). If so, the process can return to block  202  and select the next logic function. Otherwise, the process can report that the database has been created (block  214 ). In an alternative embodiment, the location of blocks  210  and  212  in  FIG. 2  can be swapped. 
       FIG. 2B  illustrates pseudocode for explicitly enumerating exact delay circuits in accordance with some embodiments described herein. Explicit circuit enumeration techniques explore the logic representation space exhaustively. This is convenient when a complete exact delay database needs to be populated. The pseudocode in  FIG. 2B  is an example of a process that can be used for explicit circuit enumeration for exact delay synthesis. The process operates as follows. We first store trivial circuits for the logic constants and input variables. These circuits, which are simple wires, are delay optimal by construction. Then, we start the enumeration loop and we try to add a new gate from L, in increasing delay order, having as fanin some of the already stored functions, also in increasing arrival time order. If the generated function is not already stored, we save it. Otherwise, we already have a better delay implementation stored for the generated function. We keep iterating this procedure until we have stored circuits for all the 2 2^n  functions. It can be easily seen that this procedure only stores exact delay circuits. Please note that the procedure shown in  FIG. 2B  can be sped up by taking into account library considerations and function filtering. On the library side, we can filter based on the gate properties, e.g., functional symmetry, delay dominance and decomposition, etc. On the function side, we can filter based on considerations on NPNclass properties (see e.g., E. A. Ernst,  Optimal combinational multi - level logic synthesis , PhD thesis, The University of Michigan, 2009) of the already stored functions. With all filtering, explicit enumeration runs quite fast. For example, it takes less than 2 minutes to generate edd(4, L) for a typical gate library L in CMOS technology. 
       FIG. 2C  illustrates pseudocode for SMT-based exact delay synthesis in accordance with some embodiments described herein. We can solve the task of exact delay synthesis by encoding the problem as in instance of the Boolean satisfiability (SAT) problem. For this purpose, one encodes the problem “Does there exists a circuit with r gates from gate library L that implements function ƒ with input arrival times T respecting an output delay of t?” 
     Let us refer to a SAT encoding of this problem as hasCircuit(f; L; r; T; t). This procedure either yields to a circuit satisfying the constraints if it exists, or unsatisfiable otherwise. We can solve the task of exact delay synthesis by encoding the problem as an instance of the SMT problem. The pseudocode in  FIG. 2C  depicts an example of an SMT procedure for exact delay synthesis. We start by setting t to minT, the minimum physical output arrival time possible. We try to find a circuit with r gates by choosing suitable values for r. For example, we can increase r until an upper bound of gates is reached. If no satisfying solution and therefore no circuit can be found, t is incremented by the library delay precision d   p   (L). This procedure is guaranteed to hit the exact delay circuit eventually. 
       FIG. 3  illustrates how a logic-function identifier can be determined for a logic function in accordance with some embodiments described herein. As illustrated by the truth tables in  FIG. 3 , there are a total of 2 2^2 =16 possible 2-input Boolean functions (the inputs are labeled “A” and “B”, and the functions are labeled “F0” through “F15”). In some embodiments, the truth table for each Boolean function can be interpreted as an integer, and the value of this integer can be used as the logic-function identifier. As shown in  FIG. 3 , the logic-function identifier for function F0 can be “0” and the logic-function identifier for function F9 can be “9.” More generally, the logic-function identifier can be a 2 n -bit integer, wherein n is the number of inputs of the logic function, and wherein each bit in the 2 n -bit integer can correspond to a binary value in a truth table for the logic function. 
       FIG. 4  illustrates how the optimal circuit implementation can depend on the arrival time in accordance with some embodiments described herein. Circuit implementations  402 ,  404 , and  406  are three possible circuit implementations for the 3-input logic function “x∧y∧z.” In circuit implementation  402 , the “x” and “y” inputs are delayed by 1 unit more than the “z” input because the “x” and “y” inputs pass through two AND gates, whereas the “z” input passes through only one AND gate. Likewise, in circuit implementation  404 , the “x” and “z” inputs are delayed by 1 unit more than the “y” input, and in circuit implementation  406 , the “y” and “z” inputs are delayed by 1 unit more than the “x” input. 
     Note that the arrival time at the output depends on the circuit implementation and the arrival times at the inputs. Therefore, the optimal circuit implementation (i.e., the circuit implementation that results in the minimum arrival time at the output) depends on the set of arrival times at the inputs. For example, if the arrival times at inputs “x”, “y”, and “z” are 1, 1, and 2, then circuit implementation  402  will be the optimal circuit implementation because it will result in an arrival time of 3 units at the output (which is the minimum arrival time at the output across all three circuit implementations), whereas the other two circuit implementations  404  and  406  will result in an arrival time of 4 units at the output. Likewise, if the arrival times at inputs “x”, “y”, and “z” are 1, 2, and 1, then circuit implementation  404  will be the optimal circuit implementation because it will result in the minimum arrival time at the output. 
       FIG. 5A  illustrates a process for determining an arrival-time-pattern identifier in accordance with some embodiments described herein. The process can begin by subtracting a minimum arrival time in the set of arrival times from each arrival time in the set of arrival times (block  502 ). The insight for this operation is that a common delay offset does not change the best delay implementation. 
     Next, for each arrival time t other than the maximum arrival time tmax in the set of arrival times, the process can set t equal to the maximum of (tmax−t) and (tmax−T), wherein T is a threshold value that depends on the logic function (block  504 ). The threshold value T can correspond to the maximum non-degenerate depth for the logic function. In other words, the threshold T can be equal to the height of a binary decision diagram (BDD) corresponding to the logic function when the BDD is decomposed into the primitive gates. The insight is that if the difference in arrival time between two inputs is larger than the maximum non-degenerate depth, then the difference can be normalized without affecting the best delay implementation because if the difference is so large, then tmax is going to determine the output arrival time. The process can then subtract a minimum arrival time in the set of arrival times from each arrival time in the set of arrival times (block  506 ). Note that, in the final set of arrival times, each arrival time is an integer between 0 and T. Therefore, the total number of distinct arrival time patterns for n inputs is n T . 
     For example, suppose the arrival times for the 3-input function described in  FIG. 4  are (5, 5, 105), i.e., suppose the arrival times at inputs “x”, “y”, and “z” are 5, 5, and 105, respectively. In block  502 , the process can modify the set of arrival times to (0, 0, 100) by subtracting “5” (which is the minimum arrival time in the set of arrival times) from each arrival time in the set of arrival times. Note that the threshold T is equal to 3 for the 3-input function described in  FIG. 4 . Therefore, in block  504 , the process can modify the set of arrival times to (97, 97, 100). Finally, in block  506 , the process can modify the set of arrival times to (0, 0, 3) by subtracting “97” (which is the minimum arrival time in the set of arrival times) from each arrival time in the set of arrival times. Thus, the final set of arrival times is (0, 0, 3). The final set of arrival times can be used itself as the arrival-time-pattern identifier, e.g., the string with comma-delimited-values “0,0,3” can be used as the arrival-time-pattern identifier. Alternatively, the process can convert the final set of arrival times into an integer, e.g., by multiplying each arrival time value by a corresponding coefficient and summing the individual products. For example, in one embodiment, the final set of arrival times (t 1 , t 2 , t 3 ) can be converted into the integer value (70×t 1 +10×t 2 +t 3 ), which can then be used as the arrival-time-pattern identifier. In some embodiments, the coefficients can be chosen so that each distinct arrival time pattern maps to a distinct integer, i.e., no two distinct arrival time patterns map to the same integer. 
       FIG. 5B  illustrates pseudocode for determining an arrival-time-pattern identifier in accordance with some embodiments described herein. Note that the process depicted in  FIG. 5B  is different from the one depicted in  FIG. 5A . Either of these processes can be used for arrival time pattern compression. The notation in  FIG. 5B  is also different from the notation in  FIG. 5A . First, a few preliminary definitions and notations. Let ƒ be an n-variable Boolean function, L be a library of gates with associated delay values, and T=(t 1 , . . . t n ) be the input arrival times. An exact delay circuit is a logic circuit, composed of gates from L, that implements ƒ with the minimum arrival time at its output. We refer to the minimum output arrival time as min t (ƒ, L, T). Let C be a (not necessarily exact) circuit that implements a Boolean function ƒ. Then, an Essential Critical Path (ECP) of C is a path from an input x i  to C&#39;s output such that for any ε&gt;0, there exists an input assignment to C such that by replacing t 1  (which is the arrival time at x i ) with t i +ε, the output arrival time of C increases. Note that there may exist multiple ECPs in the same circuit. Also, note that the ECP&#39;s location strongly depends on the input arrival times and the logic structure of C. It is easy to see that the output arrival time of a circuit is the sum of t i  and the delay of the ECP, where x i  is the starting node of the ECP. 
     In  FIG. 5B , maxT is the maximum input arrival time in T, minT is the minimum input arrival time in T, and Δ(n, L) is n times the best delay for a MUX operation implemented using gates in L. Note that, for every n-variable function ƒ, there always exists a circuit such that the delay of its ECP is bounded by Δ(n, L). The pseudocode shown in  FIG. 5B  takes the set of arrival times T as input, modifies the input arrival times as shown in  FIG. 5B , and outputs the set of arrival times T, which now contains the compressed input arrival time pattern. This compressed arrival time pattern can then be used to build the exact delay database, and can also be used to perform a lookup on the exact delay database during IC design optimization. 
       FIG. 6A  illustrates a process for performing timing optimization in an IC design in accordance with some embodiments described herein. The process can begin by determining a logic-function identifier based on a fan-in combinational-logic-cone, wherein the logic-function identifier corresponds to a logic function that is implemented by the fan-in combinational-logic-cone (block  602 ). 
     Prior to block  602 , the process can (1) determine timing slacks for a set of pins in the IC design, (2) identify a pin in the IC design for timing optimization based on the timing slacks, and (3) determine a fan-in combinational-logic-cone by starting at the pin and traversing the IC design in an output-to-input direction.  FIG. 7  illustrates how a fan-in combinational-logic-cone can be determined in accordance with some embodiments described herein. IC design  700  can include combinational gates G 1 -G 8 . Note that the gate symbol used for illustrating gates G 1 -G 8  can represent any logical operation, and does not necessarily represent the “AND” operation, e.g., G 1  can be an “OR” gate, G 2  can be an “AND” gate, etc. Let us assume that the process has selected pin  702  (i.e., output pin of gate G 1 ) for timing optimization. The process can then determine a fan-in combinational-logic-cone by starting at pin  702  and traversing IC design  700  in an output-to-input direction until a desired portion of the IC design has been traversed. In some embodiments, the IC design can be traversed in the output-to-input direction until the number of inputs of the fan-in combinational-logic-cone is equal to a predetermined number, e.g., three, four, five, etc. 
     For example, in  FIG. 7 , if the number of inputs of the fan-in combinational-logic-cone is desired to be 3, then the process can select one of the following sets of gates to be in the fan-in combinational-logic-cone: {G 1 , G 2 } or {G 1 , G 3 }. Likewise, if the number of inputs of the fan-in combinational-logic-cone is desired to be 4, then the process can select one of the following sets of gates to be in the fan-in combinational-logic-cone: {G 1 , G 2 , G 3 }, {G 1 , G 3 , G 8 }, {G 1 , G 2 , G 4 }, or {G 1 , G 2 , G 7 }. Once the fan-in combinational-logic-cone is determined, the process can then determine the logic function that is implemented by the combinational-logic-cone, and determine the logic-function identifier based on the logic function. For example, the process can determine the truth table for the fan-in combinational-logic-cone, and use the binary values in the truth table to construct the logic-function identifier as explained in reference to  FIG. 3 . 
     Next, referring to the process shown in  FIG. 6 , the process can determine an arrival-time-pattern identifier based on a set of arrival times at inputs of the fan-in combinational-logic-cone (block  604 ). For example, if the fan-in combinational-logic-cone includes gates {G 1 , G 2 , G 3 }, then the set of arrival times (which includes four arrival time values) includes the arrival times at the inputs of gates G 2  and G 3 . Once the set of arrival times is determined, then the process illustrated in  FIG. 5  can be used to determine the arrival-time-pattern identifier. The process can then determine an optimized combinational-logic-cone by performing a database lookup based on the logic-function identifier and the arrival-time-pattern identifier (block  606 ). Finally, the process can replace the fan-in combinational-logic-cone with the optimized combinational-logic-cone in the IC design (block  608 ). 
       FIG. 6B  illustrates pseudocode for performing a lookup on an exact delay database in accordance with some embodiments described herein. The pseudocode in  FIG. 6B  is explained below by using an example. Let us suppose exact delay database edd(3, L) exists, which is an exact delay database for functions with  3  inputs and that uses gates from library L. Let also assume that gate library L={NAND, NOR, XNOR, MUX, INV}. The timing information (i.e., gate delay) is t NAND =t NOR =t INV =1 and t XNOR =t mux =2. 
     In the embodiment shown in  FIG. 6B , the permutation class of a logic function is used as the logic-function identifier. Further details of how logic fucntions can be classified into permutation classes can be found in (1) V. Correia, A. Reis. “Classifying n-input Boolean functions”, Proc. IWLS 2001, and (2) M. Harrison, “The number of equivalence classes of Boolean functions under groups containing negation”, IEEE Transactions on Electronic Computers 5 (1963): 559-561. Therefore, the edd(3, L) has 80 rows and 343 columns. Each row points to a permutation class, and we have 80 different permutation classes of 3 variables. Each column points to an equioptimizable pattern, and we have 343 equioptimizable patterns because D=Δ(3, L)=t MUX ×3=6, and the number of patterns is (D+1) n =(6+1) 3 =343. Please note that the number of equioptimizable patterns can be further reduced as discussed below in this disclosure. In this example, we want to retrieve from edd(3, L) an exact delay circuit for function ƒ=x 1 ⊕x 2 + x   3  and arrival times t a =12, t b =0 and t c =1. As shown in line  652 , we first find the permutation class representative g= x   1 +x 2 ⊕x 3 , and permutation is π=(2, 3, 1). The index i of permutation class g is 16 (line  654 ), but this number can be arbitrarily changed as rows in the EDD can be swapped with no effect on the results. In line  656 , we apply the time arrival compression process illustrated in  FIG. 5B  to T=(12, 0, 1), thereby obtaining T=(6, 0, 1). Next, in line  658 , we apply permutation π to T, thereby obtaining T=(1, 6, 0). In line  660 , the index of the equioptimizable pattern is computed as j=1+6×7+0×7 2 =43. At this point (line  662 ), we look for the entry at (16, 43) in the exact delay database. The circuit stored at that entry is C=MUX(x 2 , NAND(x 1 , INV(x 3 )) NOR(x 1 , x 3 )). In line  664 , permutation π is applied to C&#39;s inputs, thereby obtaining the exact delay circuit C=MUX(x 1 , NAND(x 3 , INV(x 2 )), NOR(x 3 , x 2 )). The returned circuit (i.e., exact delay circuit C) achieves t ƒ =14 which is the minimum output arrival time possible given the function and input arrival times. 
     Multiple Outputs and Rational Delays 
     The theory of equioptimizable patterns is also valid for multiple outputs. To notice this, it is sufficient to consider the latest arriving output among all outputs of a circuit. All other arguments follow when treating this output as the single output in previous considerations. Therefore, the embodiments disclosed herein can also be used to optimize circuits that have multiple outputs. 
     Real physical delays take real values, because of the continuous nature of time. However, technology libraries have delay values defined on a minimum delay precision. We can transform any exact synthesis problem defined using rational delays into an equivalent problem defined in integral delays by normalizing all values using an appropriate factor. One obtains integer values by dividing all delays for library gates and all arrival times by d p (L), which is the minimum delay precision of library L. 
     Reducing Database Size 
     The size of an exact delay database can grow very quickly with the number of inputs n, and the complexity of the gate library L. We can reduce the size of an EDD using some of the following techniques:
         a. Tighten Δ(n, L): The original bound on Δ(n, L) is quite loose. For small cases, i.e., n&lt;5, it is possible to compute a much tighter bound with brute force methods, e.g., exhaustive exploration of the search space. A tighter bound leads to fewer equioptimizable patterns to store.   b. Merge Equioptimizable Patterns: Even with a tight bound on Δ(n, L), there may exist equioptimizable patterns still leading to the same exact synthesis solution. Indeed, the equioptimizable patterns theory is agnostic of the specific function considered. A post processing pass on an EDD can identify pattern candidates for merging.   c. Disregard Inverters: While inverters carry delay information, there are applications where they can be neglected as first approximation. This is the case, for example, for LUT synthesis or other technology independent optimization flows. With this assumption, the EDD can consider NPN classification instead of P classification. This leads to much fewer classes and therefore to fewer rows in the EDD.   d. Partial Databases: In practical synthesis problems, only a fraction of all possible functions over n variables are encountered. The larger n is, the smaller the fraction of encountered functions becomes. Exact delay databases can be optimized to contain only such frequently appearing function classes, and their equioptimizable patterns. This leads to a better control on the EDD size.
 
IC Design System
       

     The term “IC design system” generally refers to a hardware-based system that facilitates designing ICs.  FIG. 8  illustrates an IC design system in accordance with some embodiments described herein. IC design system  802  can include processor  804 , memory  806 , and storage device  808 . Specifically, memory locations in memory  806  can be addressable by processor  804 , thereby enabling processor  804  to access (e.g., via load/store instructions) and manipulate (e.g., via logical/floating point/arithmetic instructions) the data stored in memory  806 . IC design system  802  can be coupled to display device  814 , keyboard  810 , and pointing device  812 . Storage device  808  can store operating system  816 , IC design tool  818 , and data  820 . Data  820  can include input required by IC design tool  818  and/or output generated by IC design tool  818 . 
     IC design system  802  may automatically (or with user help) perform one or more operations that are implicitly or explicitly described in this disclosure. Specifically, IC design system  802  can load IC design tool  818  into memory  806 , and IC design tool  818  can then be used to create a database of optimal circuit implementations, and to optimize IC designs by using the database. 
     The above description is presented to enable any person skilled in the art to make and use the embodiments. Various modifications to the disclosed embodiments will be readily apparent to those skilled in the art, and the general principles defined herein are applicable to other embodiments and applications without departing from the spirit and scope of the present disclosure. Thus, the present invention is not limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein. 
     The data structures and code described in this disclosure can be partially or fully stored on a computer-readable storage medium and/or a hardware module and/or hardware apparatus. A computer-readable storage medium includes, but is not limited to, volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tape, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media, now known or later developed, that are capable of storing code and/or data. Hardware modules or apparatuses described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and/or other hardware modules or apparatuses now known or later developed. 
     The methods and processes described in this disclosure can be partially or fully embodied as code and/or data stored in a computer-readable storage medium or device, so that when a computer system reads and executes the code and/or data, the computer system performs the associated methods and processes. The methods and processes can also be partially or fully embodied in hardware modules or apparatuses, so that when the hardware modules or apparatuses are activated, they perform the associated methods and processes. Note that the methods and processes can be embodied using a combination of code, data, and hardware modules or apparatuses. 
     The foregoing descriptions of embodiments of the present invention have been presented only for purposes of illustration and description. They are not intended to be exhaustive or to limit the present invention to the forms disclosed. Accordingly, many modifications and variations will be apparent to practitioners skilled in the art. Additionally, the above disclosure is not intended to limit the present invention. The scope of the present invention is defined by the appended claims.