Patent Publication Number: US-8525715-B2

Title: A/D conversion apparatus and DC-DC conversion apparatus

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2011-185216, filed on Aug. 26, 2011, the entire contents of which are incorporated herein by reference. 
     FIELD 
     The present embodiment relates to an A/D conversion apparatus and a DC-DC conversion apparatus having the A/D conversion apparatus mounted thereon, and, for example, relates to, an A/D conversion apparatus which conducts A/D conversion by converting a single-ended signal such as an output DC voltage of a digital power supply IC to a differential signal. 
     BACKGROUND 
     DC offset cancel in a conventional A/D converter is conducted by inputting two analog signals serving as references, detecting a DC offset error and a gain error of A/D conversion, and canceling the errors in digital processing in a subsequent stage. 
     However, the above-described conventional technique has a problem that two different reference analog signals are needed. Furthermore, precisions are required of the two different reference analog signals. In addition, there is a problem of an error of the A/D converter involving single-ended to differential conversion, when conducting single-ended to differential conversion on an input signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing a configuration of an A/D conversion apparatus according to a first embodiment; 
         FIG. 2  is a block diagram showing a configuration of an A/D conversion apparatus according to a second embodiment; 
         FIG. 3  is a block diagram showing a configuration of an A/D conversion apparatus according to a third embodiment; and 
         FIG. 4  is a block diagram showing a configuration of a DC-DC conversion apparatus having an A/D conversion apparatus according to one of the first to third embodiments mounted thereon. 
     
    
    
     DETAILED DESCRIPTION 
     According to an embodiment, there is provided with an A/D conversion apparatus including: a first terminal, a single-ended to differential converter, an A/D converter, a digital circuit, and a second terminal. 
     The first terminal receives a reference voltage signal. 
     The single-ended to differential converter conducts single-ended to differential conversion on the reference voltage signal to obtain a first differential signal. 
     The A/D converter conducts A/D conversion on the first differential signal on the basis of the reference voltage signal to obtain a first digital signal. 
     The digital circuit detects a DC offset which is a difference between the first digital signal and a digital signal representing a predetermined code. 
     The second terminal receives an input signal. 
     The single-ended to differential converter conducts single-ended to differential conversion on the input signal to acquire a second differential signal. 
     The A/D converter conducts A/D conversion on the second differential signal on the basis of the reference voltage signal to acquire a second digital signal. 
     The digital circuit subtracts the DC offset from the second digital signal to obtain a third digital signal and outputs the third digital signal. 
     Hereafter, embodiments of the present invention will be described in detail with reference to the drawings. 
       FIG. 1  shows a configuration of an A/D conversion apparatus according to a first embodiment. 
     An A/D conversion apparatus  100  includes a single-ended to differential converter  110 , an A/D converter (ADC)  120 , a digital circuit  130 , switches Sw 1 , Sw 2 , Sw 3  and Sw 4 , and terminals  101 ,  102 ,  103 ,  104 ,  105 ,  106  and  107 . The terminals  103  to  105  correspond to first terminals. The terminals  101  and  102  correspond to second terminals. 
     A single-ended voltage signal (input signal) Vins which is an analog signal is received at the terminal  101 , and input to the single-ended to differential converter  110  via the switch Sw 1 . 
     A ground signal (input signal) GND is received at the terminal  102 , and input to the single-ended to differential converter  110  via the switch Sw 2 . 
     A plus-side reference voltage signal (reference signal) Vrp is received at the terminal  103 . The signal Vrp is input to the ADC  120  and input to the single-ended to differential converter  110  via the switch Sw 3 . 
     A minus-side reference voltage signal (reference signal) Vrm is received at the terminal  104 . The signal Vrm is input to the ADC  120  and input to the single-ended to differential converter  110  via the switch Sw 4 . 
     A reference voltage signal Vcom is received at the terminal  105  and input to the single-ended to differential converter  110  and the ADC  120 . 
     The reference voltage signals Vrp, Vrm and Vcom are supplied from an external reference voltage source (see  FIG. 4  which will be described later). 
     A mode signal Dcnt which is a digital signal is received at the terminal  106  and input to the digital circuit  130 . The mode signal Dcnt is supplied to the switches Sw 1 , Sw 2 , Sw 3  and Sw 4  as their respective control signals. The mode signal Dcnt sets an operation mode of the A/D conversion apparatus. 
     As operation modes, there are an offset detection mode and an offset cancel mode. In the offset detection mode, a DC offset in the A/D conversion apparatus is detected before an ordinary operation. In the offset cancel mode, A/D conversion with the DC offset canceled is conducted at the time of the ordinary operation. 
     In the offset detection mode, the switches Sw 1  and Sw 2  are turned off and the switches Sw 3  and Sw 4  are turned on. As a result, the signals Vrp and Vrm are input to the single-ended to differential converter  110 . 
     In the offset cancel mode, the switches Sw 1  and Sw 2  are turned on and the switches Sw 3  and Sw 4  are turned off. As a result, the signals Vins and GND are input to the single-ended to differential converter  110 . 
     Note that, the mode signal Dcnt is input directly to the switches. Alternatively, a control circuit which generates control signals respectively for the switches on the basis of the mode signal and outputs the control signals respectively to the switches may be provided. 
     The single-ended to differential converter  110  converts a difference between two input signals to a differential signal by using the reference voltage signals Vrp, Vrm and Vcom as references, and outputs the differential signal. 
     Denoting the difference between the two signals by V1, conversion of the signal V1 (single-ended signal) to a differential signal being a pair of Vinp and Vinm is represented by the following Equation (1) and Equation (2). Vcom is a middle value between Vrp and Vrm as indicated by Equation (3). 
     
       
         
           
             
               
                 
                   
                     v 
                     inp 
                   
                   = 
                   
                     
                       
                         
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                               v 
                               rp 
                             
                             - 
                             
                               v 
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                       com 
                     
                   
                 
               
               
                 
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                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     1 
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                     v 
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                               v 
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                   ⁢ 
                   
                       
                   
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                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     ( 
                     3 
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     The differential signal of Vinp and Vinm is output from the single-ended to differential converter  110  and input to the ADC  120 . 
     The ADC  120  conducts A/D conversion on the differential signal of Vinp and Vinm which are input, in a voltage range depending upon the reference voltage signals. The ADC  120  outputs a digital signal Dout 1  which is obtained as a result of the A/D conversion. The digital signal Dout 1  is input to the digital circuit  130 . 
     The digital circuit  130  conducts predetermined digital processing on the digital signal Dout 1 , and outputs a digital signal Dout 2  which is a processing result. Operation of the digital circuit  130  differs depending upon the mode signal Dcnt. In the offset detection mode, an offset quantity is detected by using a method which will be described later and stored as a digital value Dofs. In the offset cancel mode, DC offset cancel is conducted by subtracting the digital value Dofs which indicates the detected offset quantity from the digital signal Dout 1  which is output from the ADC  120 . The digital circuit  130  outputs a result of the offset cancel (A/D conversion result) as the digital signal Dout 2 . 
     A method for detecting the DC offset in the A/D conversion apparatus  100  will now be described. 
     In the A/D conversion apparatus  100 , a DC offset is caused in the single-ended to differential converter  110  and the ADC  120  due to element variations and the like in analog circuits. An analog voltage of the DC offset to the input (equivalent input voltage) is denoted by Vofs. 
     If the single-ended voltage signal Vins is subjected to A/D conversion as it is, in the A/D conversion apparatus  100  which contains the equivalent input voltage Vofs, then the digital signal Dout 1  becomes a signal obtained by adding Dofs to a digital value obtained when there is no DC offset (i.e., a digital value obtained when there is no DC offset+Dofs). Therefore, an A/D conversion error depending upon Dofs is generated. 
     For detecting the DC offset Dofs, the reference voltage signals Vrp and Vrm are used as the voltage signals which are input to the single-ended to differential converter  110 . 
     The reference voltage signal Vrp is input to the single-ended to differential converter  110  via the switch Sw 3 , and the reference voltage signal Vrm is input to the single-ended to differential converter  110  via the switch Sw 4 . Note that, at this time, the mode signal Dcnt indicating the offset detection mode is input to the terminal  106 , the switches Sw 3  and Sw 4  are turned on whereas the switches Sw 1  and Sw 2  are turned off. 
     If there is no DC offset Dofs, then a difference between the reference voltage signals Vrp and Vrm is processed as a single-ended signal and the output signal (differential signal of Vinp and Vinm) of the single-ended to differential converter  110  are indicated by Equation (4) and Equation (5). 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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                         = 
                         
                           
                             
                               
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                     4 
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                                       v 
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                     ( 
                     5 
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     When values of each signal forming the differential signal which are input are equal to each other and equal to Vcom, the ADC  120  always outputs a middle code. The middle code is a code which is 1 only in the highest order bit and 0 in other bits. (In the case of a 5-bit signal, the middle code is 10000). Here, the middle code is described as Dcen. 
     When the reference voltage signals Vrp and Vrm are input to the single-ended to differential converter  110 , therefore, it follows that Vinp=Vinm=Vcom and consequently the digital output value of the ADC  120  becomes the middle code Dcen. 
     If the DC offset Dofs exists, then the DC offset Vofs is added to the input and consequently the differential signal of Vinp and Vinm are indicated by Equation (6) and Equation (7). 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           v 
                           inp 
                         
                         = 
                         
                           
                             
                               
                                 v 
                                 ins 
                               
                               - 
                               
                                 ( 
                                 
                                   
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                                     rp 
                                   
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                     ( 
                     6 
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                         = 
                         
                           
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                     7 
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     Therefore, the DC offset Dofs which is the equivalent input voltage Vofs (error) is added. As a result, the digital output obtained by the A/D conversion in the ADC  120  becomes the middle code Dcen+DC offset Dofs. Accordingly, the DC offset Dofs can be detected by subtracting the middle code Dcen from the digital output. 
     For example, if “10011” is output as the output Dout 1  of the ADC  120 , then the DC offset Dofs becomes “00011” because 10011−10000=00011. If “01101” is output as the output Dout 1  of the ADC  120 , then the DC offset Dofs becomes “11101” because 01101−10000=11101. The digital circuit  130  stores the detected DC offset Dofs (digital value) therein. 
     At the time of the ordinary operation, the mode signal Dcnt which indicates the offset cancel mode is input. As a result, the switches Sw 1  and Sw 2  are turned on whereas the switches Sw 3  and Sw 4  are turned off, and the digital circuit  130  conducts the offset cancel operation. Since the switches Sw 1  and Sw 2  are turned on, Vins and GND are input to the single-ended to differential converter  110  and the differential signal is obtained. The differential signal is subject to the A/D conversion in the ADC  120 , and Dout 1  is output. The digital circuit  130  subtracts the DC offset Dofs from Dout 1 , and thereby obtains the digital signal Dout 2  with the DC offset canceled. The digital circuit  130  outputs the digital signal Dout 2  from the terminal  107 . 
     An example of detection of the DC offset will now be described by using a concrete example. 
     A 6-bit ADC is supposed as an example. It is supposed that Vins has a full scale of 1 V, and Vrp=0.75 V, Vrm=0.25 V and Vcom=0.5 V. Furthermore, it is supposed that Vofs=0.07 V. Since the full scale of the input to the ADC is 1 V, a voltage of the LSB in the 6 bits is V1sb=0.03125 V. 
     At this time, the DC offset is detected as described hereafter. 
     At the time of the offset detection, an offset detection mode signal is received at the terminal  106  as the mode signal Dcnt and the switches Sw 1  and Sw 2  are turned off whereas the switches Sw 3  and Sw 4  are turned on. Vrp and Vrm are input to the single-ended to differential converter  110 . The DC offset of 0.07 V is added to the single-ended input of 0.5 V, and consequently the input containing the DC offset becomes 0.57 V. This is subject to the single-ended to differential conversion, and resultant differential signal (first differential signal) become Vinp=0.535 V and Vinm=0.465 V. An A/D conversion result (a first digital signal) of the differential signal becomes Dout 1 =10010. The digital circuit  130  subtracts the middle code Vcen=10000 from Dout 1 =10010 and detects Dofs=00010 as the DC offset (offset). The digital circuit  130  stores the detected DC offset therein. 
     At the time of the ordinary operation, an offset cancel mode signal is received at the terminal  106  as the mode signal Dcnt and the switches Sw 1  and Sw 2  are turned on whereas the switches Sw 3  and Sw 4  are turned off. Then, Vins and GND are input to the single-ended to differential converter  110 . The single-ended to differential converter  110  converts a single-ended signal obtained by Vins and GND to a differential signal (second differential signal). The ADC  120  conducts A/D conversion on the differential signal. The digital circuit  103  subtracts the offset value stored therein from the result of the A/D conversion Dout 1  (a second digital signal). As a result, the output value Dout 2  (a third digital signal) with the DC offset Vofs canceled is obtained. The output value Dout 2  is output from the terminal  107 . 
       FIG. 2  shows a configuration of an A/D conversion apparatus according to a second embodiment. 
     A buffer amplifier  240  is disposed between the switch Sw 1  and the single-ended to differential converter  210 . The configuration shown in  FIG. 2  is a configuration for conducting impedance conversion on a single-ended signal which is an analog signal, conducting sampling, and then conducting A/D conversion. The buffer amplifier  240  is a buffer which drives a capacitance in the single-ended to differential converter  210 . 
     Terminals  201 ,  202 ,  203 ,  204 ,  205 ,  206  and  207  have the same configurations as those of the terminals  101 ,  102 ,  103 ,  104 ,  105 ,  106  and  107  shown in  FIG. 1 . A single-ended to differential converter  210 , an ADC  220 , and a digital circuit  230  have the same configurations as those of the single-ended to differential converter  110 , the ADC  120 , and the digital circuit  130  shown in  FIG. 1 . 
     In the case of the configuration in which the buffer amplifier is disposed on a line of an input single-ended as shown in  FIG. 2 , the buffer amplifier itself has a DC offset. The input voltage becomes equivalent to a value containing the DC offset as well. In this configuration, therefore, the DC offset Dofs containing the DC offset of the buffer amplifier  240  as well can be detected. 
     Operations other than the operation described above are the same as those in the first embodiment. Therefore, duplicated description will not be repeated. 
       FIG. 3  shows a configuration which converts the detected DC offset value to an analog value, and cancels the analog offset value from the input signal, as a third embodiment. 
     The digital value Dofs which indicates the offset voltage of the ADC  120  is output from the A/D conversion apparatus  100  and input to a converter  300 . Note that, at this time, the offset detection mode signal is being input to the A/D conversion apparatus  100 . The converter  300  conducts DA conversion on the digital value Dofs, and outputs the corresponding analog voltage Vofs (analog offset). 
     At the time of the ordinary operation, a subtraction circuit  301  subtracts the analog voltage Vofs from Vins and inputs a voltage of Vins−Vofs to the A/D conversion apparatus  100 . Since Vins−Vofs is a voltage obtained by subtracting the offset voltage from Vins, the offset can be previously canceled. 
     In other words, within the ADC  120 , the offset voltage Vofs is added to the input voltage (Vins−Vofs) from the terminal  101 . As a result, a code Dout corresponding to (Vins−Vofs)+Vofs=Vins is output from the ADC  120 . The digital circuit  130  outputs the code Dout as it is. Or the digital circuit  130  conducts arbitrary digital processing on the code Dout and outputs a result. Note that, at this time, the offset cancel mode signal is being input to the A/D conversion apparatus  100 . 
     In the present embodiment, a differential signal obtained by converting the voltage after the subtraction, in the single-ended to differential converter  110  corresponds to a third differential signal. Furthermore, a digital signal obtained by conducting A/D conversion on the third differential signal in the ADC  120  corresponds to a fourth digital signal. 
     It becomes unnecessary to subtract the offset voltage in a digital domain by subtracting the offset voltage in the analog domain in this way. Therefore, the offset cancel becomes possible without reducing the digital output code width by a value corresponding to the offset voltage. 
       FIG. 4  shows a configuration of a DC-DC converter involving digital control, according to a fourth embodiment. 
     The DC-DC converter steps down an input voltage V BAT  to a desired voltage V REF  and outputs an output voltage Vout. Vout is a single-ended signal, and a difference between GND which is located directly under a capacitor  401  and Vout is an output of the DC-DC converter. The output of the DC-DC converter is a single-ended signal around GND. The DC-DC converter includes the A/D conversion apparatus  100  according to the first embodiment shown in  FIG. 1 . The DC-DC converter may include the A/D conversion apparatus according to the second embodiment shown in  FIG. 2  or the A/D conversion apparatus according to the third embodiment shown in  FIG. 3 . 
     The single-ended signal obtained by the output voltage Vout and GND is converted to a digital signal by the A/D conversion apparatus  100  and fed back from the terminal  107 . If the A/D conversion apparatus according to the first or second embodiment is used, the digital signal fed back corresponds to the third digital signal. If the A/D conversion apparatus according to the third embodiment is used, the digital signal fed back corresponds to the fourth digital signal. 
     A controller  404  controls on/off of a high-side switch  402  and a low-side switch  403  on the basis of a difference between the digital signal fed back and the desired voltage V REF . As a result, the input voltage V BAT  is stepped down. A reference voltage source  405  generates the reference voltage signals Vrp, Vrm and Vcom and supplies them to the terminals  103 ,  104  and  105  of the A/D conversion apparatus  100 . The terminal  106  receives the mode signal which is a digital signal from the external. The high-side switch  402 , the low-side switch  403 , and a coil  406  constitute a power stage  407  which steps down the input voltage to the output voltage. 
     A large current flows to GND in the DC-DC converter with a time change. Therefore, it is necessary to convert the single-ended signal to a differential signal by using a single-ended to differential converter in order to prevent influence of noise. Furthermore, since the output value Dout+Doft containing the DC offset value error of the ADC becomes the value of Vout, it is necessary to remove Doft. Therefore, the DC offset is detected and canceled by using a method which is similar to that in the first embodiment. 
     In addition, when conducting single-ended to differential conversion in the case where, for example, resistive voltage division is conducted on Vout, a buffer amplifier for conducting impedance conversion is needed in some cases. Since the GND signal is very low in impedance, the buffer amplifier is not needed. Offset cancel at that time also becomes possible by using a method which is similar to that in the second embodiment. 
     In the present embodiment, the case where the input voltage is stepped down has been shown. However, a configuration which steps up the input voltage is also possible. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.