Patent Publication Number: US-10770982-B2

Title: Isolated synchronous rectifying DC/DC converter

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     The present application claims priority under 35 U.S.C. § 119(e) to Japanese Patent Application No. 2018-005618, filed on Jan. 17, 2018, the entire contents of which are incorporated herein by reference. 
     TECHNICAL FIELD 
     The present disclosure relates to an isolated synchronous rectifying DC/DC converter. 
     BACKGROUND 
     An isolated synchronous rectifying DC/DC converter is utilized for various power source circuits including an AC/DC converter. 
       FIG. 7  is a circuit diagram illustrating an example of a partial configuration on a secondary side of an isolated synchronous rectifying DC/DC converter. The configuration on the secondary side illustrated in  FIG. 7  is common to a flyback converter and an LLC converter. 
     A secondary winding W 200  illustrated in  FIG. 7  is included in a transformer Tr. A primary side (not shown) of the isolated synchronous rectifying DC/DC converter includes a primary winding of the transformer Tr, a switching transistor, a primary side controller for driving the switching transistor, and the like. 
     One end of the secondary winding W 200  is connected to an output terminal (not shown), and the other end thereof is connected to a drain of a synchronous rectification transistor M 200 . A source of the synchronous rectification transistor M 200  is connected to a ground application terminal. 
     The isolated synchronous rectifying DC/DC converter includes a synchronous rectification controller  300 S on the secondary side. The synchronous rectification controller  300 S has a gate terminal G 10 , a drain terminal D 10 , a source terminal S 10 , and a ground terminal GND as external terminals. A gate of the synchronous rectification transistor M 200  is connected to the gate terminal G 10 . The drain of the synchronous rectification transistor M 200  is connected to the drain terminal D 10 . The source of the synchronous rectification transistor M 200  is connected to the source terminal S 10 . The ground application terminal is connected to the ground terminal GND. 
     The synchronous rectification controller  300 S outputs a gate signal GS from the gate terminal G 10  based on a drain voltage VDS 2  generated at the drain terminal D 10  to control switching of the synchronous rectification transistor M 200 . By the switching of the switching transistor on the primary side and the switching of the synchronous rectification transistor M 200 , an input voltage applied to the primary winding is converted to an output voltage and outputted from the output terminal. 
     Specifically, the synchronous rectification controller  300 S includes a driver Dr 1 , a first comparator CP 1 , a second comparator CP 2 , a flip-flop FF 1 , a first diode D 1 , and a second diode D 2 . 
     The drain terminal D 10  is connected to an inverting input terminal (−) of the first comparator CP 1 . A first threshold voltage VthA is applied to a non-inverting input terminal (+) of the first comparator CP 1 . An output terminal of the first comparator CP 1  is connected to a clock terminal of the flip-flop FF 1 . The drain terminal D 10  is connected to an inverting input terminal (−) of the second comparator CP 2 . A second threshold voltage VthB is applied to a non-inverting input terminal (+) of the second comparator CP 2 . An output terminal of the second comparator CP 2  is connected to a reset terminal of the flip-flop FF 1 . A predetermined power supply voltage is applied to a D input terminal of the flip-flop FF 1 . A Q output terminal of the flip-flop FF 1  is connected to an input terminal of the driver Dr 1 . An output terminal of the driver Dr 1  is connected to the gate terminal G 10 . A low potential side of the driver Dr 1  is connected to the source terminal S 10 . 
     The first threshold voltage VthA and the second threshold voltage VthB are set based on a potential of the source terminal S 10 . A negative voltage is generated in the drain voltage VDS 2  by the switching of the switching transistor on the primary side, and the first comparator CP 1  detects that the drain voltage VDS 2  becomes equal to or lower than the first threshold voltage VthA (e.g., −200 mV), and asserts an ON signal Son. Accordingly, the flip-flop FF 1  sets a signal of the output terminal Q to a High level, the gate signal GS output from the driver Dr 1  becomes an ON level, and the synchronous rectification transistor M 200  is turned on. 
     When the synchronous rectification transistor M 200  is turned on, a current Is starts to flow from the source to the drain of the synchronous rectification transistor M 200 . The drain voltage VDS 2  is generated by the current Is and on-resistance of the synchronous rectification transistor M 200 , and the second comparator CP 2  detects zero current at which the current Is becomes substantially zero based on the drain voltage VDS 2 . Specifically, when the second comparator CP 2  detects that the drain voltage VDS 2  becomes equal to or higher than the second threshold voltage VthB (e.g., −6 mV), an OFF signal Soff is asserted. Accordingly, the flip-flop FF 1  is reset, the signal of the Q output terminal is set to a Low level, the gate signal GS output from the driver Dr 1  becomes an OFF level, and the synchronous rectification transistor M 200  is turned off. 
     Here, if the second threshold voltage VthB of the second comparator CP 2  is set based on a ground, the detection by the second comparator CP 2  is affected by parasitic impedance R 1  between the ground and the source of the synchronous rectification transistor M 200 . Therefore, by setting the second threshold voltage VthB based on the potential of the source terminal S 10 , the drain voltage VDS 2 , which is set based on the source that is not affected by the impedance R 1 , can be used for detection of the second comparator CP 2 . Thus, it is possible to accurately detect the timing of turning off the synchronous rectification transistor M 200 . 
     In addition, the first diode D 1  and the second diode D 2 , which are connected in parallel in opposite directions to each other, are arranged between the source terminal S 10  and the ground terminal GND. Thus, when the source terminal S 10  and the source of the synchronous rectification transistor M 200  are opened (source open), i.e., when an abnormality occurs, assuming that a forward voltage of the first diode D 1  is Vf 1  and a forward voltage of the second diode D 2  is Vf 2 , the voltage of the source terminal S 10  is clamped in a voltage of not less than −Vf 1  and not more than +Vf 2 , thereby preventing it from being unstable. 
     However, in the configuration illustrated in  FIG. 7 , when a source open occurs, there may be a case where the threshold voltage applied to the non-inverting input terminal of the second comparator CP 2  becomes Vf 2 +VthB. For example, when Vf 2  is +0.6 V and VthB is −6 mA, Vf 2 +VthB becomes a positive voltage which is approximately +0.6 V. 
     Then, the second comparator CP 2  cannot assert an OFF signal Soff unless the drain voltage VDS 2 , which is set based on the current Is flowing when the synchronous rectification transistor M 200  is turned on, is equal to or higher than a predetermined positive voltage (e.g., +0.6 V). Therefore, after the current Is flowing from the source to the drain of the synchronous rectification transistor M 200  flows backward, an OFF signal Soff is asserted and the synchronous rectification transistor M 200  is turned off. At this time, since the energy stored in the secondary winding W 200  is applied to the synchronous rectification transistor M 200 , there may be a concern that an avalanche breakdown in which a large current flows through the synchronous rectification transistor M 200  occurs and the synchronous rectification transistor M 200  is destroyed. 
     Even when the source terminal S 10  and the ground terminal GND are not connected by a diode, if the voltage of the source terminal S 10  is unstable and becomes a positive voltage when a source open occurs, the threshold voltage applied to the non-inverting input terminal of the second comparator CP 2  becomes a positive voltage, which causes the problem as described above. 
     SUMMARY 
     Some embodiments of the present disclosure provide an isolated synchronous rectifying DC/DC converter capable of detecting an abnormality of source open of a source terminal of a synchronous rectification controller. 
     According to one embodiment of the present disclosure, there is provided a configuration that includes a synchronous rectification transistor disposed on a secondary side of the DC/DC converter, and a synchronous rectification controller configured to control driving of the synchronous rectification transistor, wherein the synchronous rectification controller includes a drain terminal connected to a drain of the synchronous rectification transistor, a source terminal connected to a source of the synchronous rectification transistor, a comparator configured to compare a drain voltage of the drain terminal with a predetermined threshold voltage which is set based on a potential of the source terminal, a first flip-flop to which an OFF signal output from the comparator is input, a driver configured to output a gate signal to the synchronous rectification transistor based on an output signal of the first flip-flop, and a first abnormality detection circuit including an abnormality detection comparator configured to compare a voltage of the source terminal with a detection threshold voltage, and configured to output a first abnormality detection signal based on an output of the abnormality detection comparator (first configuration). 
     In the first configuration, the synchronous rectification controller may further include an AND circuit configured to receive the output signal of the first flip-flop and the first abnormality detection signal to output an output signal to the driver (second configuration). 
     In the second configuration, the first abnormality detection circuit may further include a second flip-flop to which an output of the abnormality detection comparator is input, and an inverter configured to receive an output of the second flip-flop to output the first abnormality detection signal (third configuration). 
     In the first configuration, the synchronous rectification controller may further include an abnormality output terminal as an external terminal, and the first abnormality detection circuit may be configured to output the first abnormality detection signal via the abnormality output terminal based on an output of the abnormality detection comparator (fourth configuration). 
     In any one of the first to the fourth configurations, the synchronous rectification controller may further include a ground terminal, and diodes connected in parallel in reverse directions to each other between the source terminal and the ground terminal (fifth configuration). 
     In any one of the first to the fourth configurations, the synchronous rectification controller may further include a ground terminal, and the source terminal and the ground terminal may be disconnected inside the synchronous rectification controller (sixth configuration). 
     In any one of the first to the sixth configurations, the abnormality detection comparator may be configured to assert an output signal when a state in which a voltage of the source terminal exceeds the detection threshold voltage continues for a predetermined period of time (seventh configuration). 
     In any one of the first to the seventh configurations, the synchronous rectification controller may further include a second abnormality detection circuit configured to stop switching of a switching transistor arranged on a primary side of the DC/DC converter by a primary side controller by asserting a second abnormality detection signal when an open of the drain terminal is detected (eighth configuration). 
     In the eighth configuration, the second abnormality detection circuit may be configured to assert the second abnormality detection signal when a periodic signal is not generated at the drain terminal and an output voltage of the isolated synchronous rectifying DC/DC converter is generated (ninth configuration). 
     In the eighth or the ninth configuration, a photocoupler and a feedback circuit configured to generate a feedback signal to the primary side controller by driving a light emitting element of the photocoupler based on the output voltage of the isolated synchronous rectifying DC/DC converter may be further included, and the synchronous rectification controller may further include a transistor connected to the light emitting element and configured to be driven by the second abnormality detection signal (tenth configuration). 
     In any one of the first to the tenth configurations, the DC/DC converter may be configured as an LLC converter having a first synchronous rectification transistor and a second synchronous rectification transistor, and the synchronous rectification controller may further include: a first drain terminal connected to a drain of the first synchronous rectification transistor; a second drain terminal connected to a drain of the second synchronous rectification transistor; a first source terminal connected to a source of the first synchronous rectification transistor; a second source terminal connected to a source of the second synchronous rectification transistor; a first gate terminal connected to a gate of the first synchronous rectification transistor; a second gate terminal connected to a gate of the second synchronous rectification transistor; a first driver configured to output a gate signal from the first gate terminal; a second driver configured to output a gate signal from the second gate terminal; a frequency divider to which an output signal of the first flip-flop is input; and a selector configured to switch a path of the comparator between the first drain terminal and the second drain terminal based on an output of the frequency divider, and to switch a path of the first flip-flop between the first driver and the second driver, wherein the predetermined threshold voltage may be set based on potentials of the first source terminal and the second source terminal, and wherein the abnormality detection comparator may be configured to compare a higher one of a voltage of the first source terminal and a voltage of the second source terminal, with the detection threshold voltage (eleventh configuration). 
     In the eleventh configuration, the synchronous rectification controller may further include an AND circuit configured to receive an output signal of the first flip-flop and the first abnormality detection signal to output an output signal to the selector. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  is a circuit diagram of a DC/DC converter according to a first embodiment of the present disclosure. 
         FIG. 2  is a circuit diagram illustrating one configuration example of a frequency divider. 
         FIG. 3  is a timing chart illustrating a normal operation of the DC/DC converter according to the first embodiment of the present disclosure. 
         FIG. 4  is a circuit diagram of a DC/DC converter according to a second embodiment of the present disclosure. 
         FIG. 5  is a circuit diagram of a DC/DC converter according to a third embodiment of the present disclosure. 
         FIG. 6  is a circuit diagram of a DC/DC converter according to a fourth embodiment of the present disclosure. 
         FIG. 7  is a circuit diagram illustrating one configuration example of a synchronous rectification controller. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present disclosure will be now described in detail with reference to the drawings. 
     &lt;1. First Embodiment&gt; 
     &lt;&lt;Overall Configuration of the LLC Converter&gt;&gt; 
       FIG. 1  is a circuit diagram of a DC/DC converter  200 A according to a first embodiment of the present disclosure. The DC/DC converter  200 A is an isolated synchronous rectifying DC/DC converter as an LLC converter. The DC/DC converter  200 A generates an output voltage Vout based on an input voltage Vin applied to an input terminal P 1  and outputs it from an output terminal P 2 . 
     The DC/DC converter  200 A includes switching transistors M 11  and M 12 , a primary side controller  202 A, a resonant capacitor Cr and a primary winding W 1  of a transformer T 1  as a primary side configuration, and secondary windings W 21  and W 22  of the transformer T 1 , synchronous rectification transistors M 21  and M 22 , an output capacitor C 1 , resistors R 21  and R 22 , a diode DD, a capacitor CC and a synchronous rectification controller  300 A as a secondary side configuration. 
     A drain of the switching transistor M 11  is connected to the input terminal P 1  to which a DC input voltage Vin is applied. A source of the switching transistor M 11  is connected to a drain of the switching transistor M 12 . A source of the switching transistor M 12  is connected to a ground application terminal. One end of the resonant capacitor Cr is connected to a connection node to which the switching transistor M 11  and the switching transistor M 12  are connected. The other end of the resonance capacitor Cr is connected to one end of the primary winding W 1 . The other end of the primary winding W 1  is connected to the source of the switching transistor M 12 . 
     The primary side controller  202 A controls switching of the switching transistors M 11  and M 12  by outputting a driving signal to gates of the switching transistors M 11  and M 12 . 
     One end of the secondary winding W 21  is connected to a drain of the first synchronous rectification transistor M 21 . The first synchronous rectification transistor M 21  has a body diode BD 1 . A source of the first synchronous rectification transistor M 21  is connected to a ground terminal P 3 . The ground terminal P 3  is connected to a ground application terminal. 
     The other end of the secondary winding W 21  is connected to one end of the secondary winding W 22 . The other end of the secondary winding W 22  is connected to a drain of the second synchronous rectification transistor M 22 . The second synchronous rectification transistor M 22  has a body diode BD 2 . A source of the second synchronous rectification transistor M 22  is connected to the ground terminal P 3 . 
     A connection node, to which the secondary winding W 21  and the secondary winding W 22  are connected, is connected to the output terminal P 2 . The output capacitor C 1  is connected between the output terminal P 2  and the ground terminal P 3 . The resistor R 21  and the resistor R 22  are connected in series between the output terminal P 2  and the ground terminal P 3 . A feedback (FB) circuit  206  is connected to a connection node to which the resistors R 21  and R 22  are connected. 
     The FB circuit  206  has, for example, a shunt regulator and the like, and drives a light emitting element of a photocoupler  204  by a current corresponding to an error between a voltage obtained by dividing the output voltage Vout by the resistors R 21  and R 22  and a predetermined target voltage. A feedback current Ifb corresponding to the error flows through a light receiving element of the photocoupler  204 . A feedback signal Vfb corresponding to the feedback current Ifb is generated at a feedback (FB) pin of the primary side controller  202 A, and the primary side controller  202 A drives the switching transistors M 11  and M 12  based on the feedback signal Vfb. 
     The synchronous rectification controller  300 A has a low dropout (LDO) regulator  301 , a selector  302 , a frequency divider  303 , a flip-flop  304 , a first comparator  305 , a second comparator  306 , a source open abnormality detection circuit  307 , an AND circuit  308 , a selector  309 , a first driver Dr 21 , a second driver Dr 22 , diodes D 211  and D 212 , and diodes D 221  and D 222 , in one package. 
     In addition, the synchronous rectification controller  300 A includes a first drain terminal D 21 , a first gate terminal G 21 , a first source terminal S 21 , a second drain terminal D 22 , a second gate terminal G 22 , a second source terminal S 22 , a power terminal VCC, and a ground terminal GND for establishing electrical connection with the outside. 
     The first drain terminal D 21 , to which the drain of the first synchronous rectification transistor M 21  is connected, is connected to one terminal of an input terminal  302 A of the selector  302 . The second drain terminal D 22 , to which the drain of the second synchronous rectification transistor M 22  is connected, is connected to the other terminal of the input terminal  302 A. An output terminal  302 B of the selector  302  is connected to an inverting input terminal (−) of each of the first comparator  305  and the second comparator  306 . The selector  302  switches between conduction of a path from the first drain terminal D 21  to the output terminal  302 B and conduction of a path from the second drain terminal D 22  to the output terminal  302 B. That is, the selector  302  selects one of a drain voltage VDS 21  of the first drain terminal D 21  and a drain voltage VDS 22  of the second drain terminal D 22  as a detection target of the first comparator  305  and the second comparator  306 . 
     A first threshold voltage VthA is applied to a non-inverting input terminal (+) of the first comparator  305 . An output terminal  309 B of the selector  309  becomes a reference potential of the first threshold voltage VthA. One terminal of an input terminal  309 A of the selector  309  is connected to the first source terminal S 21  and the other terminal of the input terminal  309 A is connected to the second source terminal S 22 . When the first source terminal S 21  and the output terminal  309 B are conducted by the selector  309 , the first threshold voltage VthA is set based on a potential of the first source terminal S 21 , and when the second source terminal S 22  and the output terminal  309 B are conducted by the selector  309 , the first threshold voltage VthA is set based on a potential of the second source terminal S 22 . An output terminal of the first comparator  305  is connected to a set terminal of the flip-flop  304 . The first comparator  305  detects that the drain voltages VDS 21  and VDS 22  have dropped to a negative voltage by turning on the switching transistors M 11  and M 12  when the drain voltages VDS 21  and VDS 22  have become equal to or lower than the first threshold voltage VthA (e.g., −200 mV). At this time, the first comparator  305  asserts an ON signal Son. The first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  are turned on by the asserted ON signal Son. 
     A second threshold voltage VthB is applied to a non-inverting input terminal (+) of the second comparator  306 . A potential of the output terminal  309 B of the selector  309  becomes a reference potential of the second threshold voltage VthB. When the first source terminal S 21  and the output terminal  309 B are conducted by the selector  309 , a potential of the first source terminal S 21  becomes a reference of the second threshold voltage VthB, and when the second source terminal S 22  and the output terminal  309 B are conducted by the selector  309 , a potential of the second source terminal S 22  becomes a reference of the second threshold voltage VthB. The output terminal of the second comparator  306  is connected to a reset terminal of the flip-flop  304 . The second comparator  306  detects zero current at which currents Is 1  and Is 2  flowing by the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22 , which are turned on, become substantially zero when the drain voltages VDS 21  and VDS 22  have become equal to or higher than the second threshold voltage VthB (e.g., −6 mV). At this time, the second comparator  306  asserts an OFF signal Soff. The first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  are turned off by the asserted OFF signal Soff. 
     Since the potential of the first source terminal S 21  is the reference of the second threshold voltage VthB, the drain voltage VDS 21  can be used for detection by using the source as a reference, which is not affected by parasitic impedance between the ground and the first synchronous rectification transistor M 21  when the first synchronous rectification transistor M 21  is turned on. Similarly, since the potential of the second source terminal S 22  is the reference of the second threshold voltage VthB, the drain voltage VDS 22  can be used for detection by using the source as a reference, which is not affected by parasitic impedance between the ground and the second synchronous rectification transistor M 22  when the second synchronous rectification transistor M 22  is turned on. 
     A Q output terminal of the flip-flop  304  is connected to an input terminal of the AND circuit  308  as described hereinbelow together with the input terminal of the frequency divider  303 . The frequency divider  303  has, for example, a configuration illustrated in  FIG. 2 , and includes a D flip-flop  303 A and an inverter  303 B. A Q output signal SQ from the flip-flop  304  is input to a clock terminal of the D flip-flop  303 A. An input terminal of the inverter  303 B is connected to the output terminal Q of the D flip-flop  303 A. An output terminal of the inverter  303 B is connected to an input terminal D of the D flip-flop  303 A. 
     With this configuration, a frequency divider output signal Sf output from the output terminal Q of the D flip-flop  303 A is switched between High and Low at every falling timing from H to Low of the Q output signal SQ. The frequency divider  303  outputs the frequency divider output signal Sf by doubling a cycle of the input Q output signal SQ. 
     The frequency divider output signal Sf is output to the selector  302 . The selector  302  performs switching between the input terminal  302 A and the output terminal  302 B and between the input terminal  302 D and the output terminal  302 C according to a level of the frequency divider output signal Sf. An output terminal of the AND circuit  308 , to which the Q output signal SQ is input, is connected to the input terminal  302 D. One terminal of the output terminal  302 C is connected to an input terminal of the first driver Dr 21 . An output terminal of the first driver Dr 21  is connected to the gate of the first synchronous rectification transistor M 21  via the first gate terminal G 21 . The first driver Dr 21  outputs a gate signal SG 21  whose level is switched according to a level of the input signal. 
     The other terminal of the output terminal  302 C is connected to an input terminal of the second driver Dr 22 . An output terminal of the second driver Dr 22  is connected to the gate of the second synchronous rectification transistor M 22  via the second gate terminal G 22 . The second driver Dr 22  outputs a gate signal SG 22  whose level is switched according to the level of the input signal. 
     The conduction of a path from the output terminal of the AND circuit  308  to the first driver Dr 21  and the conduction of a path from the output terminal of the AND circuit  308  to the second driver Dr 22  are switched by the selector  302 . 
     The frequency divider output signal Sf is also output to the selector  309 . The selector  309  switches the conduction between the input terminal  309 A and the output terminal  309 B according to the level of the frequency divider output signal Sf. 
     An anode of the diode DD is connected to the output terminal P 2 . A cathode of the diode DD is connected to one end of the capacitor CC together with the power terminal VCC. The other end of the capacitor CC is connected to the ground terminal P 3 . The LDO regulator  301  generates and outputs an internal voltage based on the input voltage applied to the power terminal VCC. A portion of the internal voltage is supplied to high potential sides of the first driver Dr 21  and the second driver Dr 22 . A low potential side of the first driver Dr 21  is connected to the first source terminal S 21 . A low potential side of the second driver Dr 22  is connected to the second source terminal S 22 . 
     In addition, the diodes D 211  and D 212  connected in parallel in reverse directions to each other are connected between the first source terminal S 21  and the ground terminal GND. Accordingly, even when an abnormality in which a source open occurs between the first source terminal S 21  and the source of the first synchronous rectification transistor M 21  occurs, the voltage of the first source terminal S 21  is clamped by the forward voltages of the diodes D 211  and D 212 , thereby preventing it from being unstable. 
     Similarly, the diodes D 221  and D 222  connected in parallel in reverse directions to each other are connected between the second source terminal S 22  and the ground terminal GND. Accordingly, even when an abnormality in which a source open occurs between the second source terminal S 22  and the source of the second synchronous rectification transistor M 22  occurs, the voltage of the second source terminal S 22  is clamped by the forward voltages of the diodes D 211  and D 212 , thereby preventing it from being unstable. 
     The source open abnormality detection circuit  307  is a circuit for detecting a source open of the first source terminal S 21  and the second source terminal S 22 , the details of which will be described later. 
     &lt;&lt;Basic Operation of the LLC Converter&gt;&gt; 
     Next, an operation of the DC/DC converter  200 A configured as described above will be described. Here, an operation in a state that a source open does not occur at both the first source terminal S 21  and the second source terminal S 22 , and an abnormality detection signal SFL, which is output from the source open abnormality detection circuit  307  to be described later and input to one input terminal of the AND circuit  308 , is High indicative of normal, and the Q output signal SQ is directly input to the input terminal  302 D of the selector  302 , will be described with reference to a timing chart illustrated in  FIG. 3 . 
     Before a timing t0, the frequency divider output signal Sf is Low, and the drain voltage VDS 22  of the second drain terminal D 22  as a detection target and the second driver Dr 22  as an output destination of the Q output signal SQ are selected by the selector  302 . In addition, the potential of the second source terminal S 22  is selected as reference potential of the first threshold voltage VthA and the second threshold voltage VthB by the selector  309 . Then, when the switching transistor M 11  is turned on at the timing t0, the current Is 2  starts to flow through the body diode BD 2  of the second synchronous rectification transistor M 22 , and the first comparator  305  detects that the drain voltage VDS 22  has dropped to a negative voltage, and asserts an ON signal Son. Accordingly, the Q output signal SQ is switched to High, the gate signal SG 22  becomes an ON level by the second driver Dr 22 , and the second synchronous rectification transistor M 22  is turned on at a timing t1. Thus, the current Is 2  starts to flow from the source to the drain side of the second synchronous rectification transistor M 22 . 
     The current Is 2  is a resonant current, and has a sinusoidal shape. Then, at a timing t2, the second comparator  306  detects that the current Is 2  has become zero current based on the drain voltage VDS 22 , and asserts an OFF signal Soff. Accordingly, the Q output signal SQ is switched to Low, the gate signal SG 22  becomes an OFF level, and the second synchronous rectification transistor M 22  is turned off. At this time, the frequency divider output signal Sf is switched to High. Accordingly, the drain voltage VDS 21  of the first drain terminal D 21  as a detection target and the first driver Dr 21  as an output destination of the Q output signal SQ are selected by the selector  302 . In addition, the potential of the first source terminal S 21  is selected as reference potential of the first threshold voltage VthA and the second threshold voltage VthB by the selector  309 . 
     Furthermore, in the second synchronous rectification transistor M 22  which is turned off, the current Is 2  continues to flow through the body diode BD 2 , and the current Is 2  does not flow at a timing t3. 
     Then, when the switching transistor M 12  is turned on at a timing t4, the current Is 1  starts to flow through the body diode BD 1  of the first synchronous rectification transistor M 21 , and the first comparator  305  detects that the drain voltage VDS 21  has dropped to a negative voltage, and asserts an ON signal Son. Accordingly, the Q output signal SQ is switched to High, the gate signal SG 21  becomes an ON level by the first driver Dr 21 , and the first synchronous rectification transistor M 21  is turned on at a timing t5. Thus, the current Is 1  starts to flow from the source to the drain side of the first synchronous rectification transistor M 21 . 
     The current Is 1  is a resonant current, and has a sinusoidal shape. Then, at a timing t6, the second comparator  306  detects that the current Is 1  has become zero current based on the drain voltage VDS 21 , and assets an OFF signal Soff. Accordingly, the Q output signal SQ is switched to Low, the gate signal SG 21  becomes an OFF level, and the first synchronous rectification transistor M 1  is turned off. At this time, the frequency divider output signal Sf is switched to Low. Accordingly, the drain voltage VDS 22  of the second drain terminal D 22  as a detection target and the second driver Dr  22  as an output destination of the Q output signal SQ are selected by the selector  302 . In addition, the potential of the second source terminal S 22  is selected as reference potential of the first threshold voltage VthA and the second threshold voltage VthB by the selector  309 . 
     Furthermore, in the first synchronous rectification transistor M 21  which is turned off, the current Is 1  continues to flow through the body diode BD 1 , and the current Is 1  does not flow at a timing t7. Thereafter, the same repetitive operation is performed. 
     &lt;&lt;About the Source Open Abnormality Detection Circuit&gt;&gt; 
     Next, the source open abnormality detection circuit  307  will be described in detail. As illustrated in  FIG. 1 , the source open abnormality detection circuit  307  has a comparator  307 A, a flip-flop  307 B, and an inverter  307 C. 
     The first source terminal S 21  is connected to one non-inverting input terminal of the comparator  307 A, and the second source terminal S 22  is connected to the other non-inverting input terminal thereof. A predetermined threshold voltage Vth 307  is applied to an inverting input terminal of the comparator  307 A. An output terminal of the comparator  307 A is connected to a clock terminal of the flip-flop  307 B. A predetermined power source voltage is applied to a D input terminal of the flip-flop  307 B. An input terminal of the inverter  307 C is connected to a Q output terminal of the flip-flop  307 B. An output terminal of the inverter  307 C is connected to one input terminal of the AND circuit  308 . 
     The comparator  307 A compares a higher one of the voltage of the first source terminal S 21  and the voltage of the second source terminal S 22  with the threshold voltage Vth 307 , and when a state where it is higher than the threshold voltage Vth 307  continues for a predetermined period of time (e.g., 10 μs) as the comparison result, a signal output to the clock terminal of the flip-flop  307 B is switched to High. When a source open occurs at the first source terminal S 21 , there may be a case where a forward voltage (e.g., +0.6 V) of the diode D 212  is generated at the first source terminal S 21 . When a source open occurs at the second source terminal S 22 , there may be a case where a forward voltage (e.g., +0.6 V) of the diode D 222  is generated at the second source terminal S 22 . Therefore, if the threshold voltage Vth 307  is set to a value lower than the forward voltage of the diodes D 212  and D 222 , when a source open occurs in at least one of the first source terminal S 21  and the second source terminal S 22 , the source open can be detected by the comparator  307 A. 
     In addition, when the state continues for the predetermined period time as described above, the output of the High signal is to suppress false detection due to noise. When the signal output from the comparator  307 A is switched to High, since the flip-flop  307 B outputs a High signal from the Q output terminal to the inverter  307 C, a Low signal indicative of an abnormality is input to one input terminal of the AND circuit  308 . Accordingly, regardless of the level of the Q output signal SQ, the output of the AND circuit  308  becomes Low, the gate signals SG 21  and SG 22  become an OFF level, and the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  are turned off. 
     When a source open occurs in the first source terminal S 21  and the second source terminal S 22 , there may be a case where the forward voltages of the diodes D 212  and D 222  are added to the second threshold voltage VthB and the voltage applied to the non-inverting input terminal of the second comparator  306  becomes a positive voltage. However, since the source open abnormality detection circuit  307  detects the source open and turns off the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22 , it is possible to avoid occurrence of a reverse flow in the currents Is 1  and Is 2 . 
     That is, it is possible to avoid the destruction of the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  which may be generated because the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  cannot be turned off until the currents Is 1  and Is 2  flow backward from the sources to the drain sides of the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  and an avalanche breakdown occurs in the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  when they are turned off. 
     In addition, if it is configured that no diode is arranged between the first source terminal S 21  and the second source terminal S 22 , and the ground terminal GND, when a source open occurs, the voltages of the first source terminal S 21  and the second source terminal S 22  become unstable, but when the voltages exceed the threshold voltage Vth 307 , the comparator  307 A can detect it and the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 2   s  can be turned off. 
     &lt;2. Second Embodiment&gt; 
       FIG. 4  is a circuit diagram of a DC/DC converter  200 B according to a second embodiment of the present disclosure. The DC/DC converter  200 B has a synchronous rectification controller  300 B having a configuration different from that of the first embodiment described above ( FIG. 1 ). The synchronous rectification controller  300 B has a function of detecting an abnormality of a drain open of the first drain terminal D 21  and the second drain terminal D 22 , in addition to the function of detecting an abnormality of source open. 
     The synchronous rectification controller  300 B is different from the synchronous rectification controller  300 A ( FIG. 1 ) in that it has an output voltage terminal VOUT and a photocoupler terminal PC as external terminals and also has a drain open abnormality detection circuit  310  and a transistor M 30 . 
     A divided voltage DV obtained by dividing an output voltage Vout by the resistors R 21  and R 22  is applied to the output voltage terminal VOUT. The divided voltage DV is input to the drain open abnormality detection circuit  310  via the output voltage terminal VOUT. The first drain terminal D 21  and the second drain terminal D 22  are connected to the drain open abnormality detection circuit  310 . 
     A drain of the transistor M 30  is connected to a cathode of a light emitting element of the photocoupler  204  via the photocoupler terminal PC. A source of the transistor M 30  is connected to a ground application terminal. The drain open abnormality detection circuit  310  drives a gate of the transistor M 30  by an abnormality detection signal S 13 . 
     When a periodic signal is not generated in at least one of the first drain terminal D 21  and the second drain terminal D 22  and the output voltage Vout is generated, the drain open abnormality detection circuit  310  asserts the abnormality detection signal S 13 . 
     For example, the drain open abnormality detection circuit  310  has a pulse detector. The pulse detector includes a detector for detecting edges of the drain voltages VDS 21  and VDS 22 , and asserts a detection signal when an edge is not detected in at least one drain voltage for a predetermined period of time. In addition, for example, the drain open abnormality detection circuit  310  has a comparator, which compares the divided voltage VD with a predetermined threshold voltage, and when the divided voltage VD becomes higher, it asserts an output determination signal. Furthermore, for example, the drain open abnormality detection circuit  310  has a logic gate for asserting the abnormality detection signal S 13  when both the detection signal and the output determination signal are asserted. The logic gate is, for example, an AND gate. 
     In this manner, the drain open abnormality detection circuit  310  detects a drain open of at least one of the first drain terminal D 21  and the second drain terminal D 22 , and asserts the abnormality detection signal S 13 . At this time, a large current Top flows through the photocoupler  204  by driving the gate of the transistor M 30 , which increases a feedback current Ifb. Accordingly, since the potential of the feedback signal Vfb decreases, a primary side controller  202 A stops switching of the switching transistors M 11  and M 12 . 
     As described above, according to the DC/DC converter  200 B of the present embodiment, the synchronous rectification controller  300 B is provided with a function of detecting an abnormality of drain open, so that, when a drain open occurs, it is possible to avoid the DC/DC converter  200 B from continuing to operate at high power in a diode rectification mode by the body diodes BD 1  and BD 2 , and to improve the reliability. 
     &lt;3. Third Embodiment&gt; 
       FIG. 5  is a circuit diagram of a DC/DC converter  200 C according to a third embodiment of the present disclosure. The DC/DC converter  200 C has a synchronous rectification controller  300 C having a configuration different from the first embodiment described above ( FIG. 1 ). 
     A difference of the synchronous rectification controller  300 C from the synchronous rectification controller  300 A ( FIG. 1 ) is a source open abnormality detection circuit  3071 . Similar to the source open abnormality detection circuit  307 , the source open abnormality detection circuit  3071  has a comparator  307 A and a flip-flop  307 B. The synchronous rectification controller  300 C has an abnormality output terminal FL as an external terminal. A Q output terminal of the flip-flop  307 B is connected to the abnormality output terminal FL. 
     The comparator  307 A compares a higher one of a voltage of a first source terminal S 21  and a voltage of a second source terminal S 22  with a threshold voltage Vth 307 , and when a state where it is higher than the threshold voltage Vth 307  continues for a predetermined period of time (e.g., 10 μs) as the comparison result, a signal output to a clock terminal of the flip-flop  307 B is switched to High. Then, an abnormality detection signal SF output from the Q output terminal to the outside via the abnormality output terminal FL is asserted by the flip-flop  307 B. 
     As described above, according to the present embodiment, the synchronous rectification controller  300 C is provided with the source open abnormality detection circuit  3071 , so that, when a source open occurs, it is possible to notify an abnormality state to the outside by the abnormality detection signal SF. Furthermore, in the present embodiment, since the Q output signal SQ output from the flip-flop  304  is directly input to the selector  302 , even when a source open occurs, the operations of the first synchronous rectification transistor M 21  and the second synchronous rectification transistor M 22  will be continued. 
     &lt;4. Fourth Embodiment&gt; 
     The present disclosure may be applied not only to the LLC converter exemplified in the aforementioned embodiments but also to a flyback converter.  FIG. 6  is a circuit diagram of a DC/DC converter  200 D according to a fourth embodiment of the present disclosure. The DC/DC converter  200 D is an isolated synchronous rectifying DC/DC converter as a flyback converter. The DC/DC converter  200 D generates an output voltage Vout based on an input voltage Vin applied to an input terminal P 1  and outputs it from an output terminal P 2 . 
     The DC/DC converter  200 D includes a primary winding W 1  included in a transformer T 10 , a switching transistor M 1  and a primary side controller  202 D, which are a primary side configuration, and a secondary winding W 2  included in the transformer T 10 , an output capacitor C 1 , a synchronous rectification transistor M 2  and a synchronous rectification controller  300 D, which are a secondary side configuration. 
     The input terminal P 1 , to which a DC input voltage Vin is applied, is connected to one end of the primary winding W 1 . The other end of the primary winding W 1  is connected to a drain of the switching transistor M 1 . A source of the switching transistor M 1  is connected to a ground application terminal. 
     One end of the secondary winding W 2  is connected to the output terminal P 2 . The other end of the secondary winding W 2  is connected to a drain of the synchronous rectification transistor M 2 . A source of the synchronous rectification transistor M 2  is connected to a ground terminal P 3 . The ground terminal P 3  is connected to the ground application terminal. The output capacitor C 1  is connected between the output terminal P 1  and the ground terminal P 3 . 
     The DC/DC converter  200 D also includes an FB circuit  206 . The FB circuit  206  drives a light emitting element of a photocoupler  204  with a current corresponding to an error between the output voltage Vout and a target voltage. A feedback current Ifb corresponding to the error flows through a light receiving element of the photocoupler  204 . A feedback signal Vfb according to the feedback current Ifb is generated at an FB pin of the primary side controller  202 D, and the primary side controller  202 D drives the switching transistor M 1  based on the feedback signal Vfb. 
     The synchronous rectification controller  300 D has an LDO regulator  301 , a flip-flop  304 , a first comparator  305 , a second comparator  306 , a source open abnormality detection circuit  3072 , an AND circuit  308 , a driver Dr 10 , and diodes D 10  and D 20 , in one package. In addition, the synchronous rectification controller  300 D has a drain terminal D 1 , a gate terminal G 1 , a source terminal S 1 , a power terminal VCC, and a ground terminal GND for establishing electrical connection with the outside. 
     The drain terminal D 1 , to which the drain of the synchronous rectification transistor M 2  is connected, is connected to an inverting input terminal (−) of each of the first comparator  305  and the second comparator  306 . A first threshold voltage VthA (e.g., −100 mV) is applied to a non-inverting input terminal (+) of the first comparator  305 . A second threshold voltage VthB (e.g., −6 mV) is applied to a non-inverting input terminal of the second comparator  306 . An output terminal of the first comparator  305  is connected to a set terminal of the flip-flop  304 . An output terminal of the second comparator  306  is connected to a reset terminal of the flip-flop  304 . 
     Similar to the first embodiment ( FIG. 1 ) described above, the source open abnormality detection circuit  3072  also has a comparator  3072 A, a flip-flop  3072 B, and an inverter  3072 C. 
     A source terminal S 1  is connected to a non-inverting input terminal of the comparator  3072 A. A predetermined threshold voltage Vth 3072  is applied to an inverting input terminal of the comparator  3072 A. An output terminal of the comparator  3072 A is connected to a clock terminal of the flip-flop  3072 B. A Q output terminal of the flip-flop  3072 B is connected to an input terminal of the inverter  3072 C. An output terminal of the inverter  3072 C is connected to one input terminal of the AND circuit  308 . A Q output terminal of the flip-flop  304  is connected to the other input terminal of the AND circuit  308 . 
     An output terminal of the AND circuit  308  is connected to an input terminal of the driver Dr 10 . An output terminal of the driver Dr 10  is connected to the gate terminal G 1  to which the gate of the synchronous rectification transistor M 2  is connected. A low potential side of the driver Dr 10  is connected to the source terminal S 1 . 
     In addition, the first threshold voltage VthA and the second threshold voltage VthB are set based on the potential of the source terminal S 1 . This allows a drain voltage VDS 2  of the drain terminal D 1 , which is not affected by parasitic impedance between the ground and the source of the synchronous rectification transistor M 2 , to be an object detected by the first comparator  305  and the second comparator  306 . 
     Furthermore, the diodes D 10  and D 20 , which are connected in parallel in opposite directions to each other, are arranged between the source terminal S 1  and the ground terminal GND. Then, even when a source open of the source terminal S 1  occurs, it is possible to prevent the voltage of the source terminal S 1  from being unstable. 
     An operation of the DC/DC converter  200 D having such a configuration in a state where the source open abnormality detection circuit  3072  does not detect an abnormality will be described. That is, the state is a state where an abnormality detection signal SFL output from the inverter  3072 C is High indicative of a normal state, and the Q output signal SQ output from the Q output terminal of the flip-flop  304  is directly input to the driver Dr 10  via the AND circuit  308 . 
     When the switching transistor M 1  is turned off, the drain voltage VDS 2  becomes a negative voltage, which is detected by the first comparator  305 , and an ON signal Son is asserted. Accordingly, the Q output signal SQ is switched to High, a gate signal SG 2  output by the driver Dr 10  through the gate terminal G 1  becomes an ON level, and the synchronous rectification transistor M 2  is turned on. 
     Thus, a current Is starts to flow from the source to the drain side of the synchronous rectification transistor M 2 . When the current Is decreases and reaches zero current, the second comparator  306  detects this based on the drain voltage VDS 2  and asserts an OFF signal Soff. Then, the Q output signal SQ is switched to Low, the gate signal SG 2  becomes an OFF level, and the synchronous rectification transistor M 2  is turned off. Thereafter, the switching transistor M 1  is turned on. 
     Next, an operation of the source open abnormality detection circuit  3072  will be described. When a source open occurs at the source terminal S 1 , there may be a case where a predetermined positive voltage is generated in the voltage of the source terminal S 1  by a forward voltage of the diode D 20 . Accordingly, when the comparator  3072 A detects that a state where the voltage of source terminal S 1  exceeds the threshold voltage Vth 3072  continues for a predetermined period of time, the signal output to the clock terminal of flip-flop  3072 B is switched to High. 
     Then, the abnormality detection signal SFL, which is the output of the inverter  3072 C, becomes Low by the Q output, which is output from the flip-flop  3072 B. Accordingly, the output of the AND circuit  308  becomes Low regardless of the Q output signal SQ. Thus, the gate signal SG 2  becomes an OFF level and the synchronous rectification transistor M 2  is turned off. 
     When a source open occurs, there may be a case where the forward voltage of the diode D 20  is added to the second threshold voltage VthB, and the voltage applied to the non-inverting input terminal of the second comparator  306  becomes a positive voltage. However, since the source open is detected by the source open abnormality detection circuit  3072  and the synchronous rectification transistor M 2  is turned off, it is possible to avoid the occurrence of reverse flow in the current Is. 
     That is, it is possible to avoid the destruction of the synchronous rectification transistor M 2  which may occur because the synchronous rectification transistor M 2  cannot be turned off until the current Is flows in a reverse direction of a direction from the source to the drain side of the synchronous rectification transistor M 2 , and an avalanche breakdown occurs in the synchronous rectification transistor M 2  when it is turned off. 
     In addition, if it is configured that no diode is arranged between the source terminal S 1  and the ground terminal GND, the voltage of the source terminal S 1  becomes unstable when a source open occurs, but when the voltage exceeds the threshold voltage Vth 3072 , the detection by the comparator  3072 A becomes possible and the synchronous rectification transistor M 2  can be turned off. 
     &lt;5. Others&gt; 
     While the embodiments of the present disclosure have been described above, the embodiments may be differently modified without departing from the spirit of the present disclosure. 
     The present disclosure can be applied to, for example, an LLC converter and the like. 
     According to the present disclosure in some embodiments, it is possible to detect an abnormality of source open of a source terminal by an isolated synchronous rectifying DC/DC converter of the present disclosure. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosures. Indeed, the embodiments described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the disclosures. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosures.