Patent Publication Number: US-2011056838-A1

Title: Method of manufacturing printed wiring board

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This patent application claims the benefit of priority to U.S. Provisional Patent Application No. 61/239,995, filed Sep. 4, 2009, the contents of which are incorporated by reference in their entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     In connection with methods for manufacturing a printed wiring board, International Publication WO 2006/033315A1 discloses a method for filling penetrating holes and non-penetrating holes with an electrolytic plated film while an insulative body is in contact with the surface to be plated. 
     BRIEF SUMMARY OF THE INVENTION 
     In a method for manufacturing a printed wiring board according to one embodiment of the present invention, an opening is formed in a substrate, and a seed layer for electrolytic plating is formed on an inner wall of the opening and a surface of the substrate. The substrate with the seed layer is placed in an electrolytic plating solution, and an insulative body is placed in the electrolytic plating solution. The substrate and the insulative body are moved relative to each other to form an electrolytic plated film on the substrate and fill the opening with the electrolytic plated film. A conductive circuit is formed on the substrate. The electrolytic plating solution includes copper sulfate, sulfuric acid, and iron ions. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING(S) 
       A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein: 
         FIGS. 1A-1E  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 2A-2E  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 3A-3D  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 4A-4C  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 5A and 5B  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIG. 6  is a cross-sectional view of a multilayer printed wiring board produced by a manufacturing method according to one embodiment of the invention. 
         FIGS. 7A-7D  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 8A-8F  are cross-sectional views showing the steps of a method for manufacturing a printed wiring board according to one embodiment of the invention. 
         FIG. 9  is a perspective view schematically showing the structure of a plating apparatus used in a method for manufacturing a printed wiring board according to one embodiment of the invention. 
         FIG. 10  is a schematic illustration showing the structure of a conveyor mechanism in a plating tank of a plating apparatus used in a method for manufacturing a printed wiring board according to one embodiment of the invention. 
         FIG. 11  is a schematic illustration showing the structure of a conveyor mechanism in a plating tank of a plating apparatus used in a method for manufacturing a printed wiring board according to one embodiment of the invention. 
         FIGS. 12A-12E  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
         FIGS. 13A-13F  are cross-sectional views showing the steps of a method for manufacturing a multilayer printed wiring board according to one embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The embodiments will now be described with reference to the accompanying drawings, wherein like reference numerals designate corresponding or identical elements throughout the various drawings. 
     First Embodiment 
     A plating apparatus used in a method for manufacturing a printed wiring board according to First Embodiment of the present invention is described with reference to  FIG. 9 . A plating apparatus  10  includes a plating tank  14 , a circulation device  16 , insulative bodies ( 20 A,  20 B), elevator bars  22 , and an elevator device  24 . The plating tank  14  is filled with a plating solution  12 . The circulation device  16  circulates the plating solution  12 . The insulative body ( 20 A) is comprised of a porous material such as a porous resin (e.g., sponge). For plating surfaces of a printed wiring board  30 , the insulative body ( 20 A) is placed in the plating solution  12  and brought into contact with one of the surfaces to be plated, e.g., a front surface of the printed wiring board  30 . The insulative body ( 20 B) is comprised of a porous material such as a porous resin (e.g., sponge). For plating the surface of a printed wiring board  30 , the insulative body ( 20 B) is placed in the plating solution  12  and brought into contact with the other surface to be plated (e.g., a back surface) of the printed wiring board  30 . The elevator device  24  vertically moves the insulative bodies ( 20 A,  20 B) along the printed wiring board  30 . The insulative bodies ( 20 A,  20 B) are moved by the elevator bars  22  which move vertically by means of the elevator device  24 . The printed wiring board  30  is connected to a cathode side. Inside the plating tank  14 , an anode not shown in the drawing is provided, and metal sources such as copper balls are stored in the anode. The plating solution  12  contains, e.g., copper sulfate, sulfuric acid and iron ions. The plating solution  12  before the plating is started contains iron(III) ions. As the plating proceeds, iron(II) ions are produced, and thus iron(II) and iron(III) ions exist in the plating solution  12 . As for the iron-ion source, iron(II) sulfate is preferred. Hydrates are preferred as iron sulfate; iron sulfate 7-hydrate (FeSO 4 .7H 2 O) is preferred. By performing dummy plating, the concentration of Fe 2+  and the concentration of Fe 3+  can be adjusted. 
     With reference to  FIGS. 13A-13F , the following describes a method that uses the plating apparatus  10  to form an electrolytic plated film for a printed wiring board (substrate)  30 . Openings ( 31   a ,  31   b ) are formed in the substrate  30  having a first surface ( 30 A) and a second surface ( 30 B) opposite the first surface ( 30 A) ( FIG. 13A ). The openings ( 31   a ,  31   b ) include penetrating holes for through-hole conductors (through-hole conductor openings) and via holes. In this example, the opening ( 31   a ) is a penetrating hole and the opening ( 31   b ) is a non-penetrating hole (via-conductor opening). A seed layer  34  is formed on the first and second surfaces ( 30 A,  30 B) of the substrate  30  and the inner walls of the openings ( 31   a ,  31   b ) ( FIG. 13B ). As examples of a seed layer, an electroless plated film, a sputtered film and a vapor-deposited film can be listed. Alternatively, by providing conductive particles such as Pd or C on the inner walls of the through holes and the substrate surfaces, an electrolytic plated film can be formed directly on the substrate surfaces and the inner walls of the openings ( 31   a ,  31   b ). In such a case, conductive particles work as a seed layer. The seed layer  34  in this example is an electroless copper-plated film. The substrate  30  with the seed layer  34  is placed in the plating solution  12  to form an electrolytic plated film  36 . An example of the composition of the plating solution  12  and the plating conditions are below. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Plating Solution 12&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 Copper sulfate concentration:  
                 0.8 ± 0.1 mol/L 
               
               
                 Sulfuric acid concentration: 
                 0.5 ± 0.15 mol/L 
               
               
                 Chloride-ion concentration: 
                 5-100 ppm 
               
               
                 Iron-ion concentration: 
                 1 g/L-20 g/L 
               
            
           
           
               
            
               
                 The iron-ion concentration is the total value of those of iron(II) ions and  
               
               
                 iron(III) ions. 
               
               
                 The concentration of iron(II) ions:concentration of iron(III) ions = 1:2-1:4 
               
            
           
           
               
               
            
               
                 Additive concentration: 
                   5 ± 1 mol/L 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 &lt;Plating Conditions&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 Current density: 
                 0.5-5 A/dm 2   
               
               
                   
                   
               
            
           
         
       
     
     The insulative body ( 20 A) is pressed against the first surface ( 30 A) of the substrate  30 , and the insulative body ( 20 B) is pressed against the second surface ( 30 B) of the substrate  30  ( FIG. 13C ). When the insulative bodies ( 20 A,  20 B) contact the substrate  30 , the insulative bodies ( 20 A,  20 B) are preferably pushed further by, for example, 1.0-15.0 mm into the substrate surfaces after they come in contact with the substrate surfaces (surfaces to be plated). If the amount to be pushed is less than 1.0 mm, the result tends to be the same as plating without using the insulative bodies ( 20 A,  20 B). If the amount to be pushed exceeds 15.0 mm, the thickness of the plated film in the openings ( 31   a ,  31   b ) tends to vary, since the supply of the plating solution  12  will be hampered. The amount to be pushed is most preferably 2-8 mm. The variation in the plated film on the substrate surfaces and in the openings ( 31   a ,  31   b ) will be less. Also, the thickness of the electrolytic plated film formed on the substrate surfaces will be reduced. 
     While the insulative bodies ( 20 A,  20 B) are in contact with the substrate  30 , the substrate  30  and the insulative bodies ( 20 A,  20 B) move relative to each other ( FIG. 13C )). The moving speed of the insulative bodies ( 20 A,  20 B) relative to the substrate  30  is preferably 1.0-16.0 m/min. Within such a range, iron ions can be appropriately fed onto the substrate surfaces. As a result, the film thickness of the electrolytic plated film  36  formed on the substrate surfaces can be reduced. In addition, since the plating solution  12  can be fed into the openings ( 31   a ,  31   b ) by the insulative bodies ( 20 A,  20 B), plating can be filled in the openings ( 31   a ,  31   b ). 
     In the present embodiment, the substrate  30  with seed layers  34  (see  FIG. 13B ) is placed in the plating solution  12  described above. Then, the insulative bodies ( 20 A,  20 B) are pressed against the substrate  30 . While the insulative bodies ( 20 A,  20 B) are pressed against the substrate  30 , the insulative bodies ( 20 A,  20 B) and the substrate  30  move relative to each other. While such conditions are sustained, the electrolytic plated film  36  is formed on the surfaces of the substrate  30  and in the openings ( 31   a ,  31   b ) ( FIG. 13C ). 
     In the embodiment, while the insulative bodies ( 20 A,  20 B) are in contact with the substrate  30  in an electrolytic plating solution containing iron ions, the electrolytic plated film  36  is formed on the surfaces of the substrate  30  and in the openings ( 31   a ,  31   b ) of the substrate  30 . Accordingly, iron(III) ions can be readily fed onto the substrate surfaces that are to be plated. Without wishing to be bound by any theory, it is thought that the following reaction occurs on the surfaces of plated films. 
       2Fe 3+ +Cu 2Fe 2+ +Cu 2+   Reaction Formula (1)
 
     If the above reaction occurs, it is thought that deposition and dissolution of the plated film will occur in areas with which the insulative bodies ( 20 A,  20 B) are in contact. It is thought that the growth speed of the plated film on the substrate surfaces will slow down. By contrast, since the plated film in the openings ( 31   a ,  31   b ) does not make contact with the insulative bodies ( 20 A,  20 B) at the initial point of plating, it is thought that the growth of the electrolytic plated film  36  in the openings ( 31   a ,  31   b ) will seldom be suppressed by the iron ions. Since iron(III) ions are diffused into the openings ( 31   a ,  31   b ) through the concentration gradient, the concentration of iron(III) ions is thought to be low. Thus, in the embodiment, it is thought that the openings ( 31   a ,  31   b ) (including penetrating holes and non-penetrating holes (via holes)) can be filled with the electrolytic plated film  36  while the thickness of the electrolytic plated film  36  on the substrate surfaces is relatively small. When the electrolytic plated film  36  in the openings ( 31   a ,  31   b ) gradually thickens, the insulative bodies ( 20 A,  20 B) come in contact with the surface of the electrolytic plated film  36  that fills the openings ( 31   a ,  31   b ). When being in contact with the insulative bodies ( 20 A,  20 B), the electrolytic plated film  36  filling the openings ( 31   a ,  31   b ) and the electrolytic plated film  36  on the substrate surfaces have growth speeds that are thought to become the same. Accordingly, the electrolytic plated films  36  obtained in the present embodiment are thought to be uniform and thin. 
     Without wishing to be bound by any theory, an alternative mechanism may be possible in which plating is suppressed from deposition through the following reaction. 
       Fe 3+ +Cu 2+ +3 e   −   Fe 2+ +Cu  Reaction Formula (2)
 
     In Reaction Formula (2), since electrons for depositing copper-plated film are used to reduce iron(III) ions into iron(II) ions, it is thought that the growth of the plated film is suppressed. In Reaction Formula (2), for the same reason as in Reaction Formula (1), it is thought that plating is filled in the openings ( 31   a ,  31   b ), while the thickness of the plated film on the substrate surfaces remains relatively small. 
     The above reactions (Reaction Formula (1) and Reaction Formula (2)) could occur as well with ions other than iron ions. However, in the embodiment, since it is thought that iron ions are forcibly fed onto the plated-film surface using the insulative bodies ( 20 A,  20 B), iron is considered to be preferred as the metal ions added to the plating solution  12 . That may be because ionization tendencies of iron and copper are similar. Compared with conventional technology, the method for forming a plated film on the substrate surfaces and in the openings ( 31   a ,  31   b ) of the substrate  30  while insulative bodies ( 20 A,  20 B) are in contact with the substrate  30  in an electrolytic plating solution containing iron ions is excellent in forming fine wiring, for example. When an electrolytic plated film is formed on a substrate with openings using the embodiment of the present invention and conventional technology, the thickness of electrolytic plated film (the thickness of the plated film formed on the substrate) obtained using the embodiment of the present invention is approximately one-half to one-third of the thickness of the electrolytic plated film (the thickness of the plated film formed on the substrate) obtained using conventional technology. Openings can be filled with plated film in the embodiment of the present invention the same as in conventional technology. 
     By using the plating method of the embodiment, the openings ( 31   a ,  31   b ) can be filled with plating, and the surface of the plated film exposed through the openings ( 31   a ,  31   b ) tend to be flat (see  FIGS. 13D and 13E ). Moreover, the top surface of the plated film exposed through the openings and the top surface of the plated film formed on a substrate surface may be positioned on the same level, and the electrolytic plated film  36  on the substrate surfaces can be formed thinly. According to the plating method of the present embodiment, filling deep openings with plated film and reducing the thickness of the plated film formed on the substrate surfaces can be achieved at the same time. After that, by patterning the thin electrolytic plated film  36  and the seed layer  34  on the substrate surfaces, fine-pitch conductive circuits can be formed ( FIG. 13F ). At the same time, through-hole conductors  42 , via conductors  60  and conductive circuits  58  are completed. 
     Furthermore, if the insulative bodies ( 20 A,  20 B) comprised of a porous resin (e.g., sponge) or a brush are used, iron(III) ions tend to be fed onto the surfaces that are to be plated. This may be because the plating solution  12  is easily fed onto the substrate surfaces through the pores of the porous resin or the spaces between the bristles of the brush. The plated film formed on the substrate surfaces tends to be thin. 
     In areas with which the insulative bodies ( 20 A,  20 B) are in contact, the growth of the electrolytic plated film  36  slows down. Namely, iron ions are forcibly fed by the insulative bodies ( 20 A,  20 B) onto plating interfaces, a reaction to reduce iron(III) ions to iron(II) ions occurs, and deposition of copper is suppressed. In the penetrating holes ( 31   a ) with which the insulative bodies ( 20 A,  20 B) are not in contact, iron(III) ions are not fed forcibly, but are only diffused by the concentration gradient onto plating interfaces, the degree of reduction reaction of iron(III) ions is low, and the electrolytic plated film  36  grows. Accordingly, the electrolytic plated film  36  on the surface of a core substrate can be formed thinly, while the through-hole conductor  42  is filled. 
     According to the embodiment of the present invention, not only can the openings be filled with electrolytic plated film, but the electrolytic plated film formed on the substrate surfaces can remain thin. Therefore, the embodiment of the present invention is applicable especially to the procedure for forming an electrolytic plated film by methods (such as the subtractive method and tenting method) where the electrolytic plated film is formed on the entire substrate surfaces, and conductive circuits are formed by etching. Since fine-pitch conductive circuits can be formed, applying the embodiment of the present invention is advantageous for making a highly integrated board. 
     &lt;Manufacturing Method 1&gt; 
     A method for manufacturing a multilayer printed wiring board (Manufacturing Method 1) is described with reference to  FIGS. 1A-6 . 
       FIG. 6  is a cross-sectional view of a multilayer printed wiring board  100 . The multilayer printed wiring board  100  has a core substrate  30 , conductive circuits  40 , through-hole conductors  42 , and interlayer resin insulation layers ( 50 ,  150 ). The core substrate  30  has a first surface (top surface in  FIG. 6 ) and a second surface (bottom surface in  FIG. 6 ) opposite the first surface. The conductive circuits  40  are provided on the first and second surfaces of the core substrate  30 . The conductive circuits  40  are connected by the through-hole conductors  42 . Formed on the core substrate  30  and the conductive circuits  40  are the interlayer resin insulation layers  50 , where via conductors  60  and conductive circuits  58  are formed. The interlayer resin insulation layers  150 , where via conductors  160  and conductive circuits  158  are formed, are formed on the interlayer resin insulation layers  50 . A solder-resist layer  70  with opening portions  71  is formed on the via conductors  160 , conductive circuits  158  and interlayer resin insulation layer  150 . Bumps ( 76 U,  76 D) are formed on the via conductors  160  and conductive circuits  158  exposed through the opening portions  71  in the solder-resist layer  70 . 
     In the following, the steps for manufacturing the multilayer printed wiring board  100  shown in  FIG. 6  are described with reference to  FIGS. 1A-5B . 
     A double-sided copper-clad laminate with a thickness of, for example, 0.8 mm is prepared ( FIG. 1A ). The core substrate (insulative substrate)  30  of the double-sided copper-clad laminate is made of a glass-epoxy resin or a BT (bismaleimide triazine) resin and a core material such as glass cloth. On the first surface of the core substrate  30  and on the second surface opposite the first surface, copper foils ( 130 A,  130 B) are laminated. Penetrating holes  32  for through-hole conductors are formed in the double-sided copper-clad laminate using a drill or a laser ( FIG. 1B ). 
     Catalyst nuclei are attached to the surfaces of the double-sided copper-clad laminate and the inner-wall surfaces of the penetrating holes  32  for through-hole conductors (not shown in the drawings). The core substrate  30  with the attached catalyst is immersed in a commercially available electroless copper plating solution (such as THRU-CUP made by C. Uyemura Co., Ltd.) to form an electroless copper-plated film  34  with a thickness of 0.3-3.0 μm on the substrate surfaces and inner walls of the penetrating holes  32  ( FIG. 1C ). 
     After being cleansed with 50° C. water to degrease, washed with 25° C. water, and further cleansed with sulfuric acid, the core substrate  30  is immersed in an electrolytic copper plating solution  12  with the following composition. After that, by using the plating apparatus  10  described above with reference to  FIG. 9 , an electrolytic plated film  36  is formed on both surfaces of the copper-clad laminate and in the penetrating holes under the following conditions ( FIG. 1D ). 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution 12&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.5  
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.8  
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 5  
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50 
                 mg/L 
               
               
                   
                 Polishing agent  
                 50  
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 &lt;Electrolytic Plating Conditions&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 Current density 
                 1 A/dm 2   
               
               
                   
                 Time 
                 65 minutes 
               
               
                   
                 Temperature 
                 22 ± 2° C. 
               
               
                   
                   
               
            
           
         
       
     
     Here, as described above with reference to  FIG. 9 , the insulative bodies ( 20 A,  20 B), using a porous resin, are vertically moved along the surfaces that are to be plated, and the electrolytic copper-plated film  36  is formed on the core substrate  30  while penetrating holes  32  are filled with plating. The penetrating holes  32  are filled with the electrolytic copper-plated film  36 . During that time, the moving speed of the insulative bodies ( 20 A,  20 B) is 7 m/min., the size of the insulative bodies ( 20 A,  20 B) relative to that of the core substrate is 0.80, and the amount that the insulative bodies ( 20 A,  20 B) are to be pushed is 8 mm. 
     Thereafter, an etching resist  38  with a predetermined pattern is formed on the electrolytic plated films  36  ( FIG. 1E ). 
     The electrolytic plated film  36 , the electroless plated film  34  and the copper foils ( 130 A,  130 B) left exposed by the etching resists  38  are removed by etching, and the through-hole conductors  40  and conductive circuits  42  are formed ( FIG. 2A ). 
     A roughened surface ( 40   a ) is formed on the entire surfaces of the conductive circuits  40  and the top surfaces of the through-hole conductors  42  ( FIG. 2B ). 
     &lt;Forming Built-Up Layers&gt; 
     On both surfaces of the core substrate  30 , a resin film (brand name: ABF-45SH, made by Ajinomoto Fine-Techno Co., Inc.) for interlayer resin insulation layers is laminated. Then, by curing the resin film for interlayer resin insulation layers, the interlayer resin insulation layer  50  is formed on both surfaces of the core substrate  30  ( FIG. 2C ). 
     By using a CO 2  gas laser, via-conductor openings ( 50   a ) with a diameter of 80 μm are formed in the interlayer resin insulation layers  50  ( FIG. 2D ). 
     The substrate  30  with the via-conductor openings ( 50   a ) is immersed for 10 minutes in an 80° C. solution containing 60 g/L of permanganic acid, and the roughened surface ( 50 α) is formed on the surfaces of the interlayer resin insulation layers  50  including the inner walls of the via-conductor openings ( 50   a ) ( FIG. 2E ). 
     The substrate  30  is immersed in a neutralizing solution (made by Shipley Company) and then washed with water. Furthermore, catalyst nuclei (not shown in the drawings) are attached to the surfaces of interlayer resin insulation layers  50  and the inner-wall surfaces of via-conductor openings ( 50   a ). 
     The substrate  30  with attached catalyst is immersed in a commercially available electroless copper plating solution to form an electroless copper-plated film  52  with a thickness of 0.3-3.0 μm on the surfaces of the interlayer resin insulation layers  50  and the inner walls of the via-conductor openings ( 50   a ) ( FIG. 3A ). 
     After being cleansed with 50° C. water to degrease, washed with 25° C. water, and further cleansed with sulfuric acid, the substrate  30  with the interlayer resin insulation layers  50  is immersed in the electrolytic copper plating solution  12  having the same composition as above. Using the plating apparatus  10  described above with reference to  FIG. 9 , under the conditions described above, an electrolytic copper-plated film  56  is formed on the interlayer resin insulation layers  50  and in via-conductor openings ( 50   a ) ( FIG. 3B ). The via-conductor openings ( 50   a ) are filled with the electrolytic copper-plated film  56 . 
     Here, as described above with reference to  FIG. 9 , while the insulative bodies ( 20 A,  20 B) using a porous resin are vertically moved along the surfaces that are to be plated, plating is filled in the openings ( 50   a ) and the electrolytic copper-plated film  56  with a thickness of 12 μm is also formed on the surfaces of the interlayer resin insulation layers  50 . The moving speed of the insulative bodies ( 20 A,  20 B) is 7 m/min., the size of the insulative bodies ( 20 A,  20 B) relative to that of the core substrate  30  is 0.80, and the amount that the insulative bodies ( 20 A,  20 B) are to be pushed is 8 mm. 
     Thereafter, an etching resist  54  is formed on electroless copper-plated films  56  ( FIG. 3C ). The electrolytic plated film  56  and electroless plated-film  52  left exposed by the etching resists  54  are removed by etching. Then, by removing the etching resists  54 , independent upper-layer conductive circuits  58  and filled vias  60  are formed ( FIG. 3D ). Roughened surfaces ( 58 α,  60 α) are formed on the surfaces of upper-layer conductive circuits  58  and filled vias  60  ( FIG. 4A ). 
     By repeating the above steps described with reference to  FIGS. 2B-4A , further upper-layer interlayer insulation layers  150 , conductive circuits  158  and filled vias  160  are formed, and a multilayer wiring board  300  is obtained ( FIG. 4B ). 
     A commercially available solder-resist composition (such as SR  7200  made by Hitachi Chemical Co., Ltd.)  70  is applied on both surfaces of the multilayer wiring board  300  to be 20 μm thick ( FIG. 4C ), on which a dry treatment is conducted at 70° C. for 20 minutes and at 70° C. for 30 minutes. After that, through exposure and development treatments, openings  71  to expose conductive circuits and filled vias are formed in solder-resist composition ( FIG. 5A ). Then, by conducting heat treatments under the conditions of 80° C. for an hour, 100° C. for an hour, 120° C. for an hour and 150° C. for three hours respectively, the solder-resist composition is cured, and the solder-resist layer  70  with openings to expose conductive circuits and filled vias is formed on interlayer resin insulation layers. The top surfaces of the conductive circuits and filled vias exposed through the openings in the solder-resist layers work as pads for mounting electronic components and pins. 
     A nickel layer, a palladium layer and a gold layer are formed in that order on the pads exposed through the openings in the solder-resist layer  70 . After that, solder balls are supplied onto the pads and then reflowed. Accordingly solder bumps (solder bodies) ( 76 U,  76 D) are formed on the pads. The multilayer printed wiring board  100  having the solder bumps ( 76 U,  76 D) is completed ( FIG. 6 ). 
     &lt;Manufacturing Method 2&gt; 
     In the following, the manufacturing steps according to Manufacturing Method 2 are described with reference to  FIGS. 7A-7D . As illustrated in  FIG. 7B , a plating resist  54  is formed on an intermediate substrate which is in the state shown in  FIG. 3A . This is different from Method 1 described above with reference to  FIGS. 3A-3D  where an electrolytic plated film  56  is formed on the entire surface of an electroless plated film  53 . 
     After being cleansed with 50° C. water to degrease, washed with 25° C. water and further cleansed with sulfuric acid, the substrate  30  is immersed in an electrolytic copper plating solution  12  having the same composition described in Method 1. An electrolytic copper-plated film  56  is formed on interlayer resin insulation layers  50  and in the via-conductor openings under the same conditions as above, and via-conductor openings are filled with the electrolytic copper-plated film  56  ( FIG. 7C ). 
     Here, as described above with reference to  FIG. 9 , insulative bodies ( 20 A,  20 B) using a porous resin are vertically moved along the surfaces that are to be plated, and the electrolytic copper-plated film  56  is formed on the interlayer resin insulation layers  50  and in the via-conductor openings, while the via-conductor openings are filled with plating. The via-conductor openings are filled with the electrolytic copper-plated film  56 . The moving speed of the insulative bodies ( 20 A,  20 B) is 7 m/min., the size of the insulative bodies ( 20 A,  20 B) relative to that of the core substrate  30  is 0.80, and the amount that the insulative bodies ( 20 A,  20 B) are to be pushed is 8 mm. 
     Plating resists  54  are removed using a 5% KOH solution. After that, by removing the electroless plated film  52  that are not covered by the electrolytic plated film  56 , independent upper-layer conductive circuits  58  and filled vias  60  are formed ( FIG. 7D ). Since the subsequent steps are the same as in Manufacturing Method 1, their descriptions are omitted. 
     &lt;Manufacturing Method 3&gt; 
     In the following, the manufacturing steps according to Manufacturing Method 3 are described with reference to  FIGS. 8A-8F . This method is an example relating to a method for manufacturing a printed wiring board having hourglass-shaped through-hole conductors. Here, an hourglass-shaped through-hole conductor indicates a through-hole conductor made by filling plating in a penetrating hole which is made up of a first opening tapering from the first surface of core substrate  30  toward the second surface, and of a second opening tapering from the second surface toward the first surface. 
     A double-sided copper-clad laminate ( 30 C) is prepared, made by laminating copper foils ( 130 A,  130 B) on both surfaces of the core substrate  30 . The core substrate  30  has a first surface and a second surface opposite the first surface. Copper foil ( 130 A) is formed on the first surface of the core substrate  30  and the copper foil ( 130 B) is formed on the second surface of the core substrate  30  ( FIG. 8A ). 
     CO 2  laser is applied from the first-surface side of the core substrate  30 . A first opening ( 136 A) is formed, penetrating the copper foil ( 130 A) and tapering from the first surface of the core substrate  30  toward the second surface ( FIG. 8B ). Tapering from the first surface toward the second surface has the diameter of the first opening ( 136 A) gradually becoming smaller from the first surface toward the second surface. Regarding the diameter of the first opening ( 136 A), when the first opening ( 136 A) is sliced by a plane parallel to the first surface, the distance across the cross section is the diameter if the first opening ( 136 A) is a circle, and the major axis if it is an oval. 
     Then, CO 2  laser is applied from the second-surface side of the core substrate  30 . The position to be irradiated by a laser is opposite the first opening ( 136 A). A second opening ( 136 B) is formed, penetrating the copper foil ( 130 B) and tapering from the second surface of the core substrate  30  toward the first surface. By forming the second opening ( 136 B), the first and second openings ( 136 A,  136 B) are joined inside the core substrate  30 , and a penetrating hole  136  comprised of the first and second openings ( 136 A,  136 B) is formed in the core substrate  30  ( FIG. 8C ). Tapering from the second surface toward the first surface has the diameter of the second opening ( 136 B) gradually becoming smaller from the second surface toward the first surface. Regarding the diameter of the second opening, when the second opening is sliced by a plane parallel to the first surface, the distance across the cross section is the diameter if the second opening is a circle, and the major axis if it is an oval. 
     A seed layer  137  made of a sputtered film is formed on the surfaces of the copper foils ( 130 A,  130 B) and the inner walls of the penetrating hole  136 . The seed layers  137  are made of copper. Since the first and second openings ( 136 A,  136 B) are tapered, the seed layers  137  are easily formed by sputtering. However, the seed layers  137  can be formed by electroless plating. 
     An electrolytic copper-plated film  134  is formed on the first and second surfaces of the core substrate  39  using the same plating apparatus  10 , plating solution  12 , plating method and plating conditions as described in Manufacturing Method 1. During that time, penetrating hole  136  is filled with an electrolytic copper-plated film  134  ( FIG. 8E ). While the penetrating hole  32  in Manufacturing Method 1 is in a substantially straight shape, the penetrating hole  136  in this Manufacturing Method 3 is in an hourglass shape. When forming a penetrating hole in the same core substrate to have the same diameter (the diameter on the front and back surfaces of the core substrate), the volume of an hourglass-shaped penetrating hole is smaller than the volume of a straight-shaped penetrating hole. Due to such a difference, the thickness of the electrolytic plated film on the core substrate in Manufacturing Method 3 tends to be thinner than the thickness of the electrolytic plated film on the substrate in Manufacturing Method 1. As such, fine conductive circuits can be formed by Manufacturing Method 3. 
     In the same manner as in Manufacturing Method 1, an etching resist is formed on electrolytic copper-plated films  134 . After that, the electrolytic plated film  134 , sputtered film  137  and copper foils ( 30 A,  30 B) left exposed by the etching resists are dissolved and removed. Accordingly, independent conductive circuits ( 134 A) and through-hole conductors  142  are formed ( FIG. 8E ). Then, built-up layers may be formed on the core substrate in the same manner as in Manufacturing Method 1. 
     Second Embodiment 
     A plating apparatus used in a method for manufacturing a printed wiring board according to Second Embodiment of the present invention is described with reference to  FIGS. 10 and 11 . 
       FIG. 11  is a schematic illustration showing a side view of a plating apparatus  210 , and  FIG. 10  is a schematic illustration showing a structure of the conveyor mechanism positioned on one side of the plating tank in the plating apparatus  210 . The plating apparatus  210  performs plating on a strip-type substrate for flexible printed wiring boards. In this plating apparatus  210 , electrolytic plating is conducted on one surface of a strip substrate ( 230 A) pulled from a reel ( 298 A) on which a 180 mm-wide and 120 m-long strip substrate is wound. Then, the strip-type substrate ( 230 A) will be wound onto a reel ( 298 B). The plating apparatus  210  has insulative cylindrical contact bodies  220  making contact with the surface of the strip substrate ( 230 A) to be plated, a back board  228  to prevent strip substrate ( 230 A) from warping caused by the contact body (insulative body)  220 , and an anode  204 . In the anode  204 , copper balls  206  are accommodated to supplement copper ingredients in the plating solution. A plating tank  212  is a total of 20 m long. Instead of an insulative material for the contact body  220 , a semiconductor contact body can also be used. The contact body  220  in Second Embodiment has substantially the same function as that of the insulative bodies ( 20 A,  20 B) described in First Embodiment. 
     The contact body  220  is formed with a cylindrical brush made of PVC (polyvinyl chloride) with a height of 200 mm and a diameter of 100 mm. In the contact body  220 , the tip of the brush makes contact with a printed wiring board and bends. The contact body  220  is supported by a support bar ( 220 A) made of stainless steel and is rotated by a gear which is not shown in the drawing. 
     Forming filled vias and conductive circuits using the plating apparatus  210  is described with reference to  FIGS. 12A-12E .  FIG. 12A  shows a double-sided copper-clad flexible substrate comprised of a substrate  230  and copper foils ( 33 U,  33 D). A commercially available dry film is laminated on one surface of the substrate  230 , and the copper foil ( 33 U) is etched away using a known photographic method from areas where via-conductor openings  37  will be formed. Using the copper foil ( 33 U) as a mask, via-conductor openings  37  are formed by a carbon-dioxide gas laser (see  FIG. 12B ). An electroless plated film  34  is formed on the copper foil ( 33 U) and the inner walls of the via-conductor openings  37  ( FIG. 12C ), and then an electrolytic plated film  36  is formed using the plating apparatus  210  shown in  FIG. 10  ( FIG. 12D ). The plated film  36  is formed while part of the contact body  220  is in contact with at least part of the surface of the printed wiring board. The contact body  220  makes contact with the electroless plated film  34  on the printed wiring board at the initial point of electroplating, and comes in contact with the electrolytic plated film  36  once the electrolytic plated film  36  is formed. 
     According to Second Embodiment, the plating solution  12  contains copper sulfate, sulfuric acid and iron ions, as in First Embodiment. Since the plating solution  12  contains iron(III) ions, the thickness of the electrolytic plated film  36  formed on substrate surfaces is smaller, compared with that obtained by using plating solutions that do not contain iron(III) ions at a high concentration. In addition, since the plated film  36  is formed using the contact body  220 , via-conductor openings can be filled with the electrolytic plated film  36 . 
     The size of a contact body is preferably the same as or greater than the area to be plated on the strip substrate. The amount that a contact body is to be pushed into a printed wiring board (after the tip of a contact body comes in contact with a surface of the printed wiring board, the amount of the tip to be further pushed) is preferably 1.0-15.0 mm into the surface. If the amount is less than 1.0 mm, the result may be the same as that of a plating method without using a contact body. If the amount exceeds 15.0 mm, it is thought that feeding iron(III) ions onto the substrate surface will become difficult. Also, the contact body tends to enter via-conductor openings and through-hole conductor openings, and thus the concentration of iron(III) ions in the openings is thought to rise. The amount to be pushed is preferably 2-8 mm. That is because variations in plated film may seldom occur. 
     As for a contact body, one selected from among flexible brushes and spatulas can be preferably used. Being flexible, a contact body follows the irregularities on a substrate and can form a plated film with a uniform thickness on the irregular surface. 
     A resin brush can be used as a contact body. In such a case, the bristle tips make contact with a surface to be plated. Here, the diameter of the bristle is preferably greater than the diameter of an opening, because the bristle tips will not enter the openings and plated film can be filled appropriately in the openings. As for a resin brush, PP, PVC (polyvinyl chloride), PTFE (polytetrafluoroethylene) or the like having tolerance to plating solutions can be used. Also, resin and rubber can be used. Furthermore, as for a bristle tip, resin fabric such as vinyl-chloride woven fabric or non-woven fabric can also be used. 
     &lt;Manufacturing Method 4&gt; 
     A method for manufacturing a printed wiring board using a plating apparatus according to Second Embodiment (using, e.g., subtractive method, tenting method) is described with reference to  FIGS. 12A-12E . The method is referred to as Manufacturing Method 4 below. 
     A laminated strip-type substrate ( 230 A) is prepared as a starting material, in which 9 μm copper foil ( 33 U) is laminated on a front surface (first surface) of 25 μm-thick polyimide strip substrate  230 , and 12 μm copper foil ( 33 D) is laminated on a back surface (second surface) ( FIG. 12A ). The copper foil on the second surface is covered with a resist. The thickness of 9 μm copper foil ( 33 U) on the front surface is adjusted by light etching to be 7 μm. After that, a black-oxide treatment is conducted on the copper foil on the first surface. By irradiating a laser from the first-surface side, via-conductor openings  37  are formed which penetrate copper foil ( 33 U) and polyimide strip substrate  30 , and reach the back surface of copper foil ( 33 D) ( FIG. 12B ). Then, a palladium catalyst is attached to the surface of strip substrate ( 230 A) (not shown in the drawing). 
     The substrate with attached catalyst is immersed in an electroless plating solution (Thru-Cup) made by C. Uyemura Co., Ltd. and 1.0 μm-thick electroless plated film (seed layer)  34  is formed on the first surface of strip substrate ( 230 A) ( FIG. 12C ). 
     After being cleansed with 50° C. water to degrease, washed with 25° C. water, and further cleansed with sulfuric acid, the strip substrate ( 230 A) is immersed in a plating tank containing an electrolytic copper plating solution with the following composition. Using plating apparatus  210  described above with reference to  FIG. 10 , the electrolytic plated film  36  is formed on the seed layer  34  under the following conditions ( FIG. 12D ). 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.5  
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.8 
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 100  
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50  
                 mg/L 
               
               
                   
                 Polishing agent 
                 50  
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                   
               
               
                 &lt;Electrolytic Plating Conditions&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                   
                 Current density 
                 5.0-30 mA/cm 2   
               
               
                   
                 Time 
                  10-90 minutes 
               
               
                   
                 Temperature 
                 22 ± 2° C. 
               
               
                   
                   
               
            
           
         
       
     
     Here, the current density is preferably set at 5.0-30 mA/cm 2 , especially at 10 mA/cm 2  or greater. Then, by forming a resist with a predetermined pattern on both surfaces of the strip substrate and conducting etching, conductive circuits ( 42 U) and conductive circuits ( 42 D) are formed ( FIG. 12E ). This is a so-called subtractive method or a tenting method. 
     &lt;Manufacturing Method 5&gt; 
     The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in Manufacturing Method 3. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.5  
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.8 
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 50 
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50  
                 mg/L 
               
               
                   
                 Polishing agent 
                 50 
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     &lt;Manufacturing Method 6&gt; 
     The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in Manufacturing Method 3. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.5  
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.8 
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 100  
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50  
                 mg/L 
               
               
                   
                 Polishing agent 
                 50 
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     When Manufacturing Methods 5 and 6 are compared, the plated film exposed through the openings tends to be recessed in Manufacturing Method 6. This is assumed to be because plating growth inside the openings is slow due to a larger amount of iron(III) ions in Manufacturing Method 6. If a concentration of iron ions is 1 g/L-10 g/L, the plated film exposed through the openings will show a higher flatness feature. Thus, an interlayer resin insulation layer may be easily formed on the plated film. The iron ions in the plating solution are iron(II) ions and iron(III) ions. If the ratio of the concentration of iron(II) ions and that of iron(III) ions in an electrolytic plating solution is in the range of 1:2-1:4, plated film will be effectively suppressed from being deposited on a substrate surface. Filling the openings and reducing the film thickness of the plated film on a substrate surface may both tend to be achieved. Iron sulfate 7-hydrate (FeSO 4 .7H 2 O) is preferably added in the amount of 5-100 g to 1,000 mL of the electrolytic plating solution. If the concentration of iron ions is in the range of 1 g/L-20 g/L, openings may be filled with plating while reducing the thickness of the plated film on a substrate surface. 
     &lt;Manufacturing Method 7&gt; 
     The composition of the electrolytic plating solution in the Manufacturing Method 3 is changed to the following composition. The rest is the same as in Manufacturing Method 3. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.65 
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.7  
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 50  
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50  
                 mg/L 
               
               
                   
                 Polishing agent 
                 50  
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     &lt;Manufacturing Method 8&gt; 
     The composition of the electrolytic plating solution in Manufacturing Method 3 is changed to the following composition. The rest is the same as in Manufacturing Method 3. 
     
       
         
           
               
             
               
                   
               
               
                 &lt;Composition of Electrolytic Plating Solution&gt; 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                   
                 Sulfuric acid 
                 0.35 
                 mol/L 
               
               
                   
                 Copper sulfate 
                 0.9  
                 mol/L 
               
               
                   
                 Iron sulfate 7-hydrate  
                 50  
                 g/L 
               
               
                   
                 (FeSO 4 •7H 2 O) 
                   
                   
               
               
                   
                 Leveling agent 
                 50 
                 mg/L 
               
               
                   
                 Polishing agent 
                 50 
                 mg/L 
               
            
           
           
               
               
               
            
               
                   
                 Fe 2+ :Fe 3+   
                 1:2-1:4 
               
               
                   
                   
               
            
           
         
       
     
     In the embodiments and examples of the present invention, an insulative body makes contact with a surface to be plated, and electrolytic plating is conducted while moving the insulative body relative to the surface to be plated. On the surface to be plated with which the insulative body makes contact, the growth of plated film slows down. It is thought that iron ions are forcibly fed by an insulative body onto the surface to be plated, causing reduction reactions of iron ions on the surface to be plated. Thus, it is thought that growth of electrolytic plated film will be suppressed. By contrast, in areas with which the insulative body does not make contact, since iron ions are diffused onto the surface to be plated due to a concentration gradient, reduction reactions of iron ions are less likely to occur on the surface to be plated. Thus, it is thought that the growth speed of electrolytic plated film will be faster. Accordingly, the electrolytic plated film grows faster in the via-conductor openings and through-hole conductor openings, but the plated film on the surface to be plated excluding the openings will be suppressed from being too thick. Namely, the via-conductor openings and through-hole conductor openings are surely filled with the electrolytic plated film, and the plated film on the surface to be plated (substrate surface) can be formed to be relatively thin compared with the thickness of the electrolytic plated film formed in the openings, or compared with the film thickness of conductive circuits in conventional technology. In the embodiments and examples of the present invention, since thin plated films are patterned, finer conductive circuits can be formed more easily than in conventional cases. 
     The order and contents of the procedure in the above embodiment may be modified freely within a scope that will not deviate from the gist of the present invention. Also, some steps may be omitted according to usage requirements or the like. For example, corrections may also be made based on image rendering data other than vector data. 
     Obviously, numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.