Patent Publication Number: US-10762261-B2

Title: Methods and apparatus for transforming the function of an integrated circuit

Description:
CLAIM OF BENEFIT TO PRIOR APPLICATION 
     This application is a Continuation-in-Part of U.S. Non-provisional patent application Ser. No. 15/405,329, entitled “Methods and Apparatus for Automatic Detection and Elimination of Functional Hardware Trojans in IC Designs”, filed on Jan. 13, 2017, which claims benefit to U.S. Provisional Patent Application 62/281,738, entitled “To Detect, Locate, and Mask Hardware Trojans in Digital Circuits”, filed on Jan. 22, 2016, the content of which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to circuits, and more particularly to methods and apparatus that improve efficiency in transforming a function of an integrated circuit. 
     BACKGROUND 
     Modern circuits (such as integrated circuits (ICs)) are enormously complicated. For example, an average desktop computer chip can have over 1 billion transistors. Due to the complexity and high cost, IC design is often outsourced to a third party that completes the circuit design by using hardware that incorporates software (such as Electronic design automation (EDA) or Computer Aided Design (CAD) tools). Such outsourcing provides opportunities for attackers to take over the designed IC by introducing malicious alterations or hardware Trojans (HTs), which causes serious security concerns especially for security-critical applications such as military applications. A HT can cause malfunction for a circuit into which the HT is embedded or destroy a system incorporating such circuit, lower circuit reliability and leak confidential information. 
     New methods and apparatus that assist in advancing technological and security needs and industrial applications in circuit technology, IC design, verification, and fabrication processes are desirable. 
     In addition, in designing very large-scale integration (VLSI) circuits, the function of the IC may have to be changed some time after its initial design for various reasons such as to improve its performance, to introduce new features or to mask HT. Such change is generally implemented by performing engineering change orders (ECO). However, existing ECO techniques are slow and inefficient. Therefore, new methods and apparatus for transforming the function of an IC is desired. 
     SUMMARY OF THE INVENTION 
     One example embodiment provides a method to detect, locate, and mask a functional hardware Trojan (HT) in an arithmetic circuit to improve circuit security over conventional methods. The method provides a first netlist and a second netlist of the arithmetic circuit, extracts arithmetic macros from the first netlist and the second netlist to obtain a first plurality of arithmetic macros and a second plurality of arithmetic macros, detects the HT by comparing the first plurality of arithmetic macros with the second plurality of arithmetic macros, locates the HT in the second netlist, and improves security of the arithmetic circuit by masking the HT with addition of a patch in the second netlist to obtain a patched netlist. 
     One example embodiment provides a method to transform the function of a circuit. The method provides a first register-transfer level (RTL) document of an original specification and a second RTL document of a revised specification, generates a first gate level (GTL) netlist and a second GTL netlist, compares the two RTL documents to identify the instances to be modified, locates the instances to be modified in the first GTL netlist, and transforms the function of the circuit by patching the circuit such that the patched first GTL netlist is equivalent to the second GTL netlist. 
     Other example embodiments are discussed herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a graph illustrating a scenario of hardware Trojan (HT) implantation during a circuit design process in accordance with an example embodiment. 
         FIG. 2A  shows a graph illustrating a gate-level (GTL) circuit in accordance with an example embodiment. 
         FIG. 2B  shows a graph illustrating an HT injection in a GTL circuit in accordance with an example embodiment. 
         FIG. 2C  shows a graph illustrating a patched GTL circuit in accordance with an example embodiment. 
         FIG. 2D  shows a graph illustrating a HT diagnostic report in accordance with an example embodiment. 
         FIG. 3  shows a flow diagram illustrating an example method in accordance with an example embodiment. 
         FIG. 4A  shows a graph illustrating a multiplier in accordance with an example embodiment. 
         FIG. 4B  shows a graph illustrating a multiplier in accordance with an example embodiment. 
         FIG. 5  shows construction of an XOR forest in accordance with an example embodiment. 
         FIG. 6  shows a table illustrating example reverse engineering in accordance with an example embodiment. 
         FIG. 7A  shows a graph illustrating an examined netlist in accordance with an example embodiment. 
         FIG. 7B  shows a graph illustrating a golden netlist in accordance with an example embodiment. 
         FIG. 7C  shows a graph illustrating a trimmed netlist in accordance with an example embodiment. 
         FIG. 8A  shows a graph illustrating patch creation before patching in accordance with an example embodiment. 
         FIG. 8B  shows a graph illustrating patch creation after patching in accordance with an example embodiment. 
         FIG. 9A  shows a graph illustrating conservative patch creation before patching in accordance with an example embodiment. 
         FIG. 9B  shows a graph illustrating conservative patch creation after patching in accordance with an example embodiment. 
         FIG. 10A  shows a graph illustrating aggressive patch creation before patching in accordance with an example embodiment. 
         FIG. 10B  shows a graph illustrating aggressive patch creation after patching in accordance with an example embodiment. 
         FIG. 11A  shows a graph illustrating a patch before an Add-First rewiring transformation in accordance with an example embodiment. 
         FIG. 11B  shows a graph illustrating a patch after an Add-First rewiring transformation in accordance with an example embodiment. 
         FIG. 12A  shows a graph illustrating a patch before a Cut-First rewiring transformation in accordance with an example embodiment. 
         FIG. 12B  shows a graph illustrating a patch after a Cut-First rewiring transformation in accordance with an example embodiment. 
         FIG. 13  shows a table illustrating characteristics of benchmarks in accordance with an example embodiment. 
         FIG. 14  shows a table illustrating example methods in accordance with an example embodiment. 
         FIG. 15  shows a computer system in accordance with an example embodiment. 
         FIG. 16  shows a flow diagram illustrating an example method of transforming the function of a circuit in accordance with an example embodiment. 
         FIG. 17  shows a diagram illustrating an example method of generating a netlist to be patched in accordance with an example embodiment. 
         FIG. 18  shows a diagram illustrating an example method of obtaining the instances, module ports and signals to be patched in accordance with an example embodiment. 
         FIG. 19  shows a diagram illustrating an example of an ECO procedure in accordance with an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments relate to methods and apparatus that improve circuit security. 
     Circuit (such as integrated circuits (ICs)) or chip design and fabrication are enormously complicated. A modern IC typically includes millions of miniscule electronic components, such as gates, transistors and diodes (e.g. an average desktop computer chip nowadays can have over 1 billion transistors), which makes it impossible for a person to design such circuits or chips mentally or manually with a pencil and paper. Hardware, such as a computer device or system that incorporates or embeds software (such as Electronic design automation (EDA) or Computer Aided Design (CAD) tools), is generally employed to complete such tasks. 
     Due to the significantly increased complexity of IC design and fabrication, design is often outsourced by using third party Intellectual Properties (3PIPs) from a vendor. Risks are raised because a hardware Trojan (HT) or bug (e.g. unintended or unauthorized functional hardware insertion, malicious hardware insertion, or unauthorized design modification) can be injected into a circuit by an attacker (such as an untrusted person or dishonest engineer or spy). In addition, it is possible for unexpected functions to be fitted to a circuit or chip by an untrusted foundry and/or distributor. 
     A HT or bug harms a circuit or chip in many ways. For example, a HT maliciously changes or modifies functionality of a circuit by adding, deleting or modifying circuit&#39;s one or more components (such as logic gates, transistors, diodes, etc.). As another example, a HT changes circuit function indirectly by modifying one or more parameters to be fed into a circuit. A HT can disrupt operation of a circuit (such as an IC) or other circuits that couple to the circuit. By way of example, a HT causes an IC to malfunction and/or conduct one or more functions that constitute a security attack. A HT can also be designed or implanted by a spy to retrieve sensitive data or information, or be designed to change a hosting circuitry specification such as delay, power consumption and reliability. For example, a circuit or chip that is specified to function properly for ten years may be reliable for only one year if a HT is implanted or embedded in the circuit. 
     Detecting presence of a HT or bug in a circuit (e.g. arithmetic circuits, such as an IC) and masking or killing such HT is therefore of great importance for industries such as IC design, verification and fabrication, consumer products and military applications etc. Effectiveness and efficiency to detect and remove such HTs or bugs to improve circuit security have great importance in these industries. Undetected HTs in a circuit such as IC can make the circuit worthless or in great danger in terms of a number of aspects such as sensitive information leakage. Low efficiency (such as high runtime or time complexity) in detecting and removing HTs lengthens design cycles and increases time-to-market and jeopardizes profit margins. Furthermore, unsatisfactory efficiency or runtime complexity requires more resource usage (such as memory usage), high performance (such as high processing capacity and speed) for a computer device, and also increases network consumption when data is transmitted over a network to a remote server for processing as an example. Thus, unsatisfactory methods or schemes for HT detection and capture not only jeopardize many industries (such as IC industry and other industries that relate to or depend on IC industry) technologically and economically, but also require costly computer hardware by demanding large resource consumption such as memory usage and high processing speed. 
     Existing or conventional methods are flawed or have difficulties in detecting and killing HTs in circuits. On one hand, this is because presence of a HT cannot be easily detected. A HT may reside within a testing circuit of a chip to avoid being detected during normal operation and be activated occasionally to carry out malicious operations. Also, the amount of logic gates in a modern IC or chip is too large that exhaustive testing is infeasible. On the other hand, the existing methods have flaws intrinsically in one or more aspects. 
     For example, many existing methods can only extract simple logic patterns such as gates from a gate-level (GTL) netlist, but cannot handle complex but basic arithmetic blocks such as adders and multipliers. Some existing methods use simulation tools to identify logic gates that have low activation probability, which, however, is inaccurate. Some existing methods employ satisfiability (SAT)-based functional formal verification techniques to detect HTs in circuits, which, however, is incapable in verifying certain arithmetic logics designed in different styles (e.g. Non-Booth versus Booth multipliers). A main reason that the existing SAT-based functional formal verification techniques do not work well is because existing SAT solvers highly rely on successfully locating of internal equivalent points of compared logics. When few internal equivalent points are found, even for a quite small circuit, the solving time or runtime grows exponentially in the worst cases such as when performing comparison between multipliers designed in different styles (e.g. non-Booth versus Booth). Existing SAT solvers also show inability or inefficiency in terms of equivalence checking for circuits (e.g. arithmetic circuits), such as incapability in proving equality between two arithmetic circuits. Furthermore, existing methods fail to detect and locate where the body and boundary of a HT exactly is in a circuit for the chip owner or designer to analyze intending damage of the HT, and do not have a 100% guarantee of catching all HTs in a circuit. 
     Thus, existing methods or schemes are neither effective nor efficient in detecting and masking or removing a HT in a circuit or arithmetic circuit (such as IC, Application Specific Integrated Circuit (ASIC), and Field-Programmable Gate array (FPGA), Digital Signal Processor (DSP), etc.), which jeopardizes circuit industry by lengthening design cycle and causing serious problems such as circuit failure, short circuit lifetime, and sensitive information leakage or stolen etc. Exiting methods or schemes are also unfavorable from perspective of computer technology because a less efficient process of detecting and masking HTs may be trapped into exponential time (e.g. high time complexity, several tens of hours or days, or even not converging (“forever” runtime that leaves subject problem unsolved)), which demands large resource usage (such as memory usage and network consumption) and costly computer device (such as high processing capacity). 
     Example embodiments solve the above-stated problems by providing technical solutions in new methods and apparatus that function in unconventional ways to benefit circuit industry and computer industry. Example embodiments benefit circuit (such as IC, ASIC, FPGA, DSP, etc.) industry by preventing (such as detecting, locating, and masking or removing) HTs in a circuit with significantly improved or enhanced effectiveness and efficiency, which, on one hand, increases circuit production (e.g. yield) and lifetime by reducing or preventing circuit failure and malfunctions caused by HTs, and on the other hand, improves circuit security by avoiding sensitive data leakage or by avoiding a circuit or an apparatus or machine that incorporates such circuit being taken over by an attacker or spy. Example embodiments further benefit computer technology by reducing resource consumption (e.g. memory usage and network consumption). Example methods can be executed by a computer device or system with lower hardware requirement to perform circuit design and thus mitigate demand of costly computers with expensive chips, memory and other internal electronic components. 
     Example embodiments solve the above-stated problems by providing technical solutions in new methods and apparatus that detect one or more functionality differences between circuits (such as between two circuit netlists or macros) that are likely be caused by one or more HTs or bugs, locate or output the differences to correct the HTs or to investigate the tampering intention or purpose, and kill, mask, or remove the HTs by restoring the functionality back to original specification (e.g. golden specification or correct specification). By way of example, example embodiments restore the functionality of a circuit or chip back to original specification with a minimum circuitry change to avoid affecting performance (such as clock and timing, etc.) of the circuit or chip significantly. Example embodiments improve circuit security by blocking intentional or plotted damage to a circuit at an early stage and figuring out a spy source by revealing the HT intention. 
     By way of example, example embodiments solve the above-stated problems by providing technical solutions with incorporation or combination of reverse engineering, formal verification, functional Engineering Change Order (ECO), and logic rewiring to detect, locate, and mask HTs in a circuit. As an example, example embodiments handle a number of HTs automatically with guarantee of catching 100% of HTs in a circuit. 
     By way of example, example embodiments solve the above-stated problems by providing technical solutions that couple or combine reverse engineer and formal verification (so-called Complementary Greedy Coupling (CGC) formal verification scheme) to overcome the incapability of SAT solvers in arithmetic verification. Example reverse engineering performs well in verification or proof of equality, and example SAT solvers perform well in verification or proof of inequality. Coupling of reverse engineering and SAT techniques takes advantage of strong points of both reverse engineering and SAT and obtains a combined advantage, which improves HT detection with reduced runtime complexity and increased capability such as capability to tackle NP-complete circuits efficiently. By way of example, example embodiments can formally compare the functionality between a netlist of correct or golden design and an examined design with a HT embedded or implanted. 
     In an example embodiment, when a logic difference is detected, a functional-ECO technique is applied to locate HTs and a patch or rectification patch logic is inserted or added to mask the HTs. In another example embodiment, a logic rewiring treatment or technique is applied to optimize the patch such that size of the path is minimized, which improves circuit (such as IC) technology because perturbation or interference (such as timing perturbation) to a target circuit or chip is reduced or minimized to increase circuit performance. 
     By way of example, runtime of example embodiments to detect, locate and mask multiple HTs (no limit on the number of HTs) in an IC with millions of logic gates is within minutes in contrast with hours or days for existing methods. 
     Example embodiments include a computer system with specific software incorporated, as well as such a computer system embedded in a network. Example computer system solves technical problems raised in circuit industry such as IC industry by executing example methods herein. When executing example methods, example computer system improves hardware performance by reducing resource usage such as memory usage and network consumption. 
       FIG. 1  shows a graph illustrating a scenario of HT implantation during a circuit design process in accordance with an example embodiment. The graph  100  includes a customer or party  110 , a design house  120 , a chip  130 , and a spy or attacker  140 . 
     By way of example, the customer  110  has a plan or proposed specification (e.g. a microarchitecture and a system-level specification, etc.) for designing a new circuit or chip (e.g. IC, ASIC, FPGA, DSP, etc.) to fit into an industry segment. As an example, the plan or proposed specification is specified using a register transfer level (RTL) specification language (such as Verilog and VHDL). The plan or proposed specification then goes through a long tract of design processes in the design house  120  where a design team processes circuit design with hardware (such as a computer) that incorporates software (such as EDA or CAD tools). The design house  120  belongs to either the customer  110  or a third part to which a design task is outsourced. 
     By way of example, the design processes performed in the design house  120  include logical synthesis and physical place and route (P&amp;R). As shown in  FIG. 1  for example, a RTL-level circuit  122  is synthesized into a gate-level (GTL) circuit  124  that is then synthesized into a circuit-level circuit  126 . Based on the completed circuit design, the chip  130  is fabricated or produced. 
     As shown in  FIG. 1 , during design phase in the design house  120 , the spy  140  (such as an untrusted person or dishonest engineer) maliciously injects or embeds a HT or bug into the circuit or chip. As an example, the HT can be introduced to the circuit at either intermediate stage in the design house  120 , such as either design process of the RTL-level circuit  122 , the Gate-level circuit  124 , and circuit-level circuit  126 . 
     For the customer  110  that concerns circuit security, the HT must be detected and removed effectively and efficiently (e.g. 100% capture within a practical time limit such as polynomial time and even linear time). Otherwise, the spy  140 , with the injected HT, can cause malfunctions of the circuit or chip, destroy a system that incorporates the chip, or steal confidential information. The customer  100  is also likely to favor a HT-capture process that is not expensive (e.g. lower requirement for hardware such as a computer device). 
       FIGS. 2A-2D  show graphs illustrating an HT injection in a gate-level (GTL) circuit in accordance with an example embodiment. For illustrative purpose only,  FIG. 2A  shows an original GTL circuit  210  that includes a 8-AND gate  214  (herein “8-AND” indicates there are eight inputs for the AND gate) with an input vector  212  (shown as in[7:0] which indicates that there are 8 input signals named in[7], in[6], . . . in[0]) and a AND gate  216 . The AND gate  216  has one output  218  (shown as out) and two inputs, one being the output of the 8-AND gate  214  and the other being an input  213  (shown as s). 
     As an example, the GTL circuit  210  in  FIG. 2A  is an original netlist of a circuit. By way of example, the input  213  receives from the input  213  a redundant internal signal s that is a stuck-at logic 1 during the normal working mode or normal operation. 
       FIG. 2B  shows a HT-tempered netlist  220  that includes a malicious logic or HT  225  in accordance with an example embodiment. As a result, the AND gate  216  in  FIG. 2A  is replaced with or changed into a multiplexer (MUX)  226 . The added malicious logic  225  is not triggered on a normal working mode and is thus unable to be tested or detected by simulation using conventional methods such as normal input testing vectors. 
       FIG. 2C  shows a patched netlist  230  in accordance with an example embodiment. As shown, the patched netlist  230  includes a patch or patch logic  235  that masks or kills the malicious logic or HT  225 . In one example embodiment, the patch  235  is minimized in size to reduce timing perturbation for the target circuit or chip. A target circuit or chip, as an example, is a final product based on the finalized design of a circuit with HTs removed or masked through a circuit varication or checking process. 
       FIG. 2D  shows a HT diagnostic report  240  in accordance with an example embodiment. The HT diagnostic report  240  includes a first part  242  that shows netlist of the patch  235 , and a second part  244  that shows the MUX  236  after correction or rectification with the patch  235 . 
     As illustrated in  FIGS. 2A-2D , circuit security is improved with example methods by detecting, locating, and masking or killing an inserted or implanted HT or bug in a circuit. The inserted HT is masked by introducing a patch such that the circuit is restored back to a circuit in accordance with original or correct specification. 
       FIG. 3  shows a flow diagram in accordance with an example embodiment. The flow diagram  300  illustrates an example method that is executed by a computer that incorporates software or an apparatus that incorporates such computer. The computer includes electronic devices such as a computer system or electronic system, wearable electronic devices, servers, portable electronic devices, handheld portable electronic devices, and hardware (e.g., a processor, processing unit, digital signal processor, controller, memory, etc.). 
     The example method, when executed by the computer, solves one or more existing technical problems as stated above in circuit industry by improving effectiveness and efficiency (such as reduced runtime complexity) for circuit design. The example method also improves performance of the computer that executes the example method by consuming less resource such as memory, processor, and network usage such as bandwidth. 
     Block  302  states providing a first netlist of an arithmetic circuit. 
     For example, the first netlist is an originally specified (golden or correct) netlist that conforms to a customer or person&#39;s plan or proposed specification. By way of example, the first netlist is a gate-level (GTL) netlist that is synthesized from a golden register-transfer level (RTL) circuit. 
     Block  304  states providing a second netlist of an arithmetic circuit. 
     For example, the second netlist is an examined netlist. By way of example, the second netlist is HT-tempered or injected, for example, by a spy or an attacker. To improve circuit security, the second netlist is examined to detect and mask or remove one or more HTs or bugs that are maliciously inserted or injected. 
     Block  306  states extracting arithmetic macros from the first netlist to obtain a first plurality of arithmetic macros. Block  308  states extracting arithmetic macros from the second netlist to obtain a second plurality of arithmetic macros. 
     By way of example, a macro or operator macro is defined to be a block of logic which is a building component in a circuit (e.g. an IC) such as adders, multipliers, multiplexers (MUX) or a formula such as (A+B)×C. 
     In an example embodiment, example reverse engineering (RE) techniques are applied to extract and compare all arithmetic macros such as adders and multipliers with their formula forms. The arithmetic macros are often constructed by a number of elementary components “1-bit adders” which include 1-bit half adders (HA) and/or 1-bit full adders (FA) in specific styles. The reverse engineering technique first identifies all these elementary components from the whole circuit. Secondly, RE builds a 1-bit adder graph where the output of one adder is the input of another adder. The functionality or formula of the arithmetic logics is obtained from the style of the built adder graph. 
     By way of example, arithmetic components (such as an adder and a multiplier) are implemented in a number of styles such as carry-look ahead adder (CLA), Ripple, Booth and Non-Booth which are constructed by 1-bit adders. For example,  FIGS. 4A-4B  show two graphs in accordance with an example embodiment. The graph in  FIG. 4A  is an illustrative multiplier  410 , and the graph in  FIG. 4B  is an illustrative multiplier  420 , wherein FA represents a 1-bit full adder and HA represents a 1-bit half adder. As illustrated, the multiplier  410  and the multiplier  420  share some common structural units (such as 1-bit adders). 
     In an example embodiment, all 1-bit adders including their connections are extracted firstly. A 1-bit full adder has 3 input signals (e.g. a, b and c), and 2 output signals (e.g. sum and carry (also called co)). The functionality of a 1-bit full adder is as follows:
 
 FA   sum   =a⊗b⊗c  
 
 FA   co   =a &amp; b+b &amp; c+a &amp; c   (1)
 
where “⊗” is also called “XOR” operation means Boolean “exclusive or” function, “+” means Boolean “or” function, and “&amp;” means Boolean “and” function.
 
     A 1-bit half adder has two input signals (e.g. a and b), and 2 output signals (e.g. sum and carry (also called co)). The functionality of a 1-bit half adder is as follows:
 
 FA   sum   =a⊗b  
 
 FA   co   =a &amp; b  
 
By way of example, both an adder and a multiplier are composed of one or more 1-bit adders. For example, the third output of a 4-bit multiplier in Non-Booth style is expressed as:
 
     
       
         
           
             
               
                 
                   
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     As an example, the fourth output of a 4-bit multiplier in Non-Booth style is expressed as: 
                     z   3     =         HA   sum     ⁡     (         FA   sum     ⁡     (         FA   sum     ⁡     (         a   0     ⁢     b   3       ,       a   1     ⁢     b   2       ,       a   2     ⁢     b   1         )       ,       a   3     ⁢     b   0       ,     FA   co       )       ,     HA   co       )       =     a   ⁢           ⁢   0   ⁢   b   ⁢           ⁢     3   ⊗   a     ⁢           ⁢   1   ⁢   b   ⁢           ⁢     2   ⊗   a     ⁢           ⁢   2   ⁢   b   ⁢           ⁢     1   ⊗   a     ⁢           ⁢   3   ⁢   b   ⁢           ⁢     0   ⊗   HAco   ⊗   FAco                 (   3   )               
where FA co  and HA co  are carry out signals from other adders
 
     In an example embodiment, to figure out 1-bit adder graph, all 1-bit adders are firstly identified. To figure out 1-bit adders, all 2-input single-output sub circuits whose function is exclusive or (XOR) are firstly identified. Then one or more XOR trees which contain multiple 2-input XOR sub circuits and where an input of a first XOR sub circuit is an output of a second XOR sub circuit are identified. Inputs of the one or more XOR trees are either bit products of adders and multipliers or carry signals of internal 1-bit adders. On basis of the one or more XOR trees, carry signals are deduced and the one or more XOR trees are connected to form or create a XOR forest. As an example, the XOR forest is considered as a 1-bit adder graph. Construction of a 1-bit adder graph in accordance with an example embodiment is shown in  FIG. 5 . 
       FIG. 6  shows a table illustrating reverse engineering in accordance with an example embodiment. The example method illustrated in the table  600  includes identifying or determining a plurality of 2-input XOR sub-circuits, building a plurality of XOR trees based on that an output of one XOR operation is an input of another XOR operation, determining carry signals of internal 1-bit adders from the plurality of XOR trees and connecting the plurality of XOR trees to form an XOR forest such as 1-bit adder graph such that one or more 1-bit adder graphs are obtained, and determining arithmetic functions and arithmetic boundaries for each of the one or more XOR forests such that a plurality of arithmetic macros are extracted. In an example embodiment, after the network of 1-bit-adders (such as a XOR forest) is formed or built, arithmetic functions such as additions, subtractions and multiplications are determined with the XOR forest. A complex arithmetic logic (e.g. combination of adders and multipliers (such as (a+b)×c, a×b+c×d, etc.)) is built or determined bottom up. 
     Return back to  FIG. 3 , Block  310  states detecting a HT by comparing the first plurality of arithmetic macros with the second plurality of arithmetic macros. 
     In an example embodiment, the process as stated in Block  310  is considered as global HT locating because it globally determine which one or more areas HTs are located. In another example embodiment, to improve efficiency of locating one or more HTs globally, a trimming technique or process is applied. 
     By way of example, with trimming treatment or technique, equivalent sub-circuit pairs or areas are identified and stripped from a circuit, and all HTs only exist or locate inside the non-equivalent sub-circuit areas. As an example, if a first part of a first circuit and a second part of a second circuit are equivalent sub-circuit pairs, the first part and the second part have same function, or they are functionally equivalent. If the first part and the second part have different function, they are functionally non-equivalent and are not equivalent sub-circuit pairs. As another example, the first plurality of arithmetic macros consist of part A 1  and part B 1 , and the second plurality of arithmetic macros consist of part A 2  and part B 2 . The part A 1  and the part A 2  are functionally equivalent, and the part B 1  and the part B 2  are functionally non-equivalent. As an example, the part A 2  is trimmed out from the second plurality of arithmetic macros such that a HT is determined to be located in the part B 2  of the second plurality of arithmetic macros. 
     By way of example,  FIG. 7A-7C  show graphs illustrating a trimming process in accordance with example embodiment.  FIG. 7A  shows an examined netlist  710  (or a second netlist) that is HT injected. The examined netlist  710  includes a part  714  that has a 6-XOR sub-circuit (i.e. implementing a 6-input XOR function) and a part  712  indicating other part of the examined netlist  710 .  FIG. 7B  shows a golden or correct netlist  720  (or a first netlist) that is originally specified. The golden netlist  720  includes a part  724  that has a 6-XOR sub-circuit and a part  722  indicating other part of the golden netlist  720 . Thus, the part  714  and the part  724  have same function or are functionally equivalent but with different implementation style. 
     As shown in  FIG. 7C , an equivalent pair, the part  714  and the part  724 , is trimmed out or stripped away from respective netlist to obtain a trimmed netlist  730 . In an example embodiment, a trimming or stripping process is iteratively performed to minimize the non-equivalent circuit part. In another example embodiment, a trimming or stripping process is iteratively performed until no equivalent sub-circuit pair or equivalent pair is found between the examined netlist  710  and the golden netlist  720 . 
     Return back to  FIG. 3 , Block  312  states locating, with a functional-Engineering Change Order (ECO) engine, the HT in the second netlist. 
     By way of example, a functional-ECO engine or technique is applied to locating and masking HTs. 
     Block  314  states improving security of the arithmetic circuit by masking the HT with addition of a patch in the second netlist to obtain a patched netlist with ECO engine. 
     By way of example, functional ECO engine denotes a set of primary inputs (PIs) in a circuit as a set of Boolean variables X={x 1 , . . . , x n }. Functions of primary outputs (POs) in an examined design or specification and a golden or correct specification are denoted by F(X)={f 1 (X), f 2 (X), . . . , f m (X)} and G(X)={g 1 (X), g 2 (X), . . . , g m (X)} respectively. 
     For an examined and golden function pair, f i  and g i , a diff-set characterizes a set of input assignments for which the functions f i  and g i  have opposite values and is defined as follows:
 
diff i ( X )= f   i ( X )⊕ g   i ( X )  (4)
 
     The functional ECO engine minimizes the diff-set for every function pair by adding patch logics/circuits incrementally until all diff-sets are empty, which indicates that the examined function and golden function are equivalent and the HT is eliminated. In an example embodiment, a patch logic is inserted into the circuit to minimize the diff-set. 
     For example, for an internal signal r within the circuit where the patch logic is to be inserted, assume function of r is t(X), and a PO (PO i  driven by r whose function is f i ), f i (X,r) is expressed in terms X and r, then the care-set for r is defined as follows:
 
care i   r   =f   i ( X,t ( X ))⊕ f   i ( X,¬t ( X ))  (5)
 
A care-set characterizes a set of input assignments for which any change at signal r can be observed at the output function f i . In an example embodiment, the care-set overlaps with the diff-set and is divided into two partitions:
         (i) care-out-diff: including Boolean expression resulting in 1 for the output (min-terms) in the care-set but not in the diff-set, care r   i ∧¬diff i ; and   (ii) care-in-diff: including min-terms in both the care-set and diff-set, care r   i ∧¬diff i .       

     By way of example, changing values of the min-terms in the care-out-diff changes value of f i  and enlarges the diff-set. Hence, the min-terms in the function t is preserved and the following constraint is satisfied by the patch function p(X):
 
 p ( X )⊇ t ( X ) care i   r ( X )   diff i ( X )  (6)
 
On the other hand, in order to minimize the diff-set, t&#39;s min-terms inside the care-in-diff is evaluated to the opposite values:
 
 p ( X )⊇   t ( X ) care i   r ( X ) diff i ( X )  (7)
 
     Therefore, if p(X) and diff-set satisfy the following condition,
 
 p ( X )⊇   t ( X ) diff i ( X )  (8)
 
which implies that
 
care i   r ( X )⊇diff i ( X )  (9)
 
then p(X) completely empties diff i (X) and accomplishes the golden function g i .
 
     Specifically, for example, when r=PO i , care i   T (X)⊇diff i (X) is always satisfied, which implies that a patch function can be found that satisfies constraint Equation (8), which completely empties diff i (X) and accomplishes golden function g i  (e.g., g i  is directly used as a patch function). 
       FIGS. 8A-8B  show graphs illustrating patch function creation in accordance with an example embodiment.  FIG. 8A  shows a graph  810  before patching. The graph  810  includes a care-set  812  and a diff-set  814  that have an overlap  816  (i.e. care-in-diff). The care-set  812  with the care-in-diff  816  excluded is care-out-diff.  FIG. 8B  shows a graph  820  after patching. The graph  820  includes a diff-set  824  that is smaller than the diff-set  814 . The diff-set is reduced in size after generation of a patch. 
     By way of example, constraints Equation (6-8) are considered when creating patch or patch functions. If the signal r only drives a single output, the corresponding patch function must satisfy both Equation (6) and Equation (7). In an example embodiment, to enhance possibility of creating an effective patch while avoiding exhaustive searches, the patch is one of conservative patch and aggressive patch. 
       FIGS. 9A-9B  show graphs illustrating conservative patch in accordance with an example embodiment.  FIG. 9A  shows a graph  910  illustrating conservative patch creation before pathing.  FIG. 9B  shows a graph  920  illustrating conservative patch creation after pathing. 
     In the conservative patch or strategy, a patch at signal r guarantees that no diff-set of the Primary Out (PO) is worsened. Thus constraint Equation (6) is satisfied for all POs. By way of example, a subset of POs is selected from the PO set {PO 1 , PO 2 , . . . , PO m }. The subset {PO i1 , PO i2 , . . . , PO il } is called an improved PO set. A created patch at r cuts down the diff-set of POs in the improved PO set. In other words, for each PO in this set, constraint Equation (7) is satisfied. 
     By way of example, the selection of POs and the size of the improved PO set is adjusted dynamically as the logic patching proceeds. The smaller the improved PO set size is, the easier to create a satisfying patch. 
     As shown in  FIGS. 9A-9B , a conservative patch is created at an internal signal driving two primary outputs. The diff-sets of both outputs are minimized as shown. 
       FIGS. 10A-10B  show graphs illustrating aggressive patch in accordance with an example embodiment.  FIG. 10A  shows a graph  1010  illustrating aggressive patch creation before pathing.  FIG. 10B  shows a graph  1020  illustrating aggressive patch creation after pathing. 
     By way of example, diff-sets of some POs are improved while diff-sets of some other POs are ignored. In an example, a PO set is divided into three subsets:
         (i) Ignored Set: POs in the set is not considered during a patching process, and in an example embodiment, diff-sets of such POs become worse after patching.   (ii) No Change Set: diff-sets of POs in this set do not become worse. In an example embodiment, diff-sets of POs in this set do not improve either. Constraint Equation (6) is satisfied for every PO in this set. The POs that have been fixed in previous iterations (e.g. their diff-sets are already empty) are assigned to this set, to such that they do not become unfixed again.   (iii) Improved Set: diff-sets of POs in this set are improved by a created patch. Both constraints Equation (6) and Equation (7) are satisfied. Furthermore, for at least one PO in this set, constraint Equation (8) is satisfied, which implies that the patch created is able to fix at least one PO completely.       

     As shown in  FIGS. 10A-10B , the diff-set of o1 can be completely eliminated while the diff-set of o2 is enlarged. 
     In an example embodiment, example methods include improving efficiency of locating the HT in a netlist with a functional-Engineering Change Order (ECO) engine. As an example, a conservative patch candidate and an aggressive patch candidate are generated, and then a patch candidate with a smaller size between the conservative patch candidate and the aggressive patch candidate is chosen or selected as a real patch. 
     In some example embodiments, a patch is improved by optimizing the patch with logic rewiring treatment to minimize size of the patch, which have many benefits such as helping reduce timing perturbation for a target circuit or chip. As an example, a patch optimization process or treatment includes an Add-First rewiring transformation and a Cut-First rewiring transformation. 
       FIGS. 11A-11B  show graphs illustrating an Add-First rewiring transformation in accordance with an example embodiment. The graph  1110  in  FIG. 11A  shows a patch before an Add-First rewiring transformation, and the graph  1120  in  FIG. 11B  shows a patch after an Add-First rewiring transformation. 
     As shown, for Add-First rewiring transformation, a wire or redundant wire  1112  is added into a patch circuit first (e.g. a wire from g5 to g9 in the figure). Then several wires and consequentially several gates (e.g. g4, g6, and g7) become redundant and are thus removable or can be removed as shown in  FIG. 11B . As shown, the optimized patch is minimized with reduced size. The detail implementation of the rewiring transformation is described in paper “Combinational and Sequential Logic Optimization by Redundancy Addition and Removal” written by L. A. Entrena and K.-T. Cheng, published in IEEE transaction on Computer-Aided Design on 1995. 
       FIGS. 12A-12B  show graphs illustrating a Cut-First rewiring transformation in accordance with an example embodiment. The graph  1210  in  FIG. 12A  shows a patch before a Cut-First rewiring transformation, and the graph  1220  in  FIG. 12B  shows a patch after a Cut-First rewiring transformation. 
     As shown, a wire from b to g6 is removed first, which causes observable errors propagating from g6 to o2. By an error cancellation analysis, all errors are correctable by adding additional logics at g8 and g9. The corrected patch requires fewer gates and wires as shown in  FIG. 12B . The implementation of Cut-First rewiring transformation is described in paper “ECR: a low complexity generalized error cancellation rewiring scheme”, written by Xiao Qing Yang, Tak-Kei Lam and Yu-Liang Wu, published in Proceedings of the 47th Design Automation Conference on 2010. 
     By way of example, for a serial of Internet of Things (IoT) chips with a few minor differences to be designed, given that each chip requires 3 months to complete a P&amp;R process, existing methods requires 3+3=6 months to complete design of two chips. In contrast, example methods in accordance with some example embodiments complete the same task in in 3 months+10 minutes. 
       FIG. 13  shows a table illustrating characteristics of benchmarks in accordance with an example embodiment. In the table  1300 , in the column of “Style”, B represents Booth multiplier, and NB represents Non-Booth multiplier. As shown, besides multiplication, some more complicated arithmetic functions (see the column of “Extracted arithmetics” in the table  1300 ) also exist in the benchmarks. 
     In the table  1300 , the first column is the name of a case suite. Each suite includes 13 benchmarks which implement similar arithmetic functions but with different operands&#39; bitwidths. Example extracted arithmetic logics as well as their design styles (in Booth or in Non-Booth) and operands&#39; bit-widths are shown at columns 3-5. Example methods extract most (97%) of the benchmarks with only suites ut36 and hid10 failed. With the arithmetic logics successfully extracted, example formal verification techniques such as example SAT solvers are employed or called for the extracted circuits to detect presence of one or more HTs. 
     By way of example, each of these benchmarks is a gate-level (GTL) combinational circuit including arithmetic logics. Example reverse engineering techniques are applied to locate the arithmetic logics from flatten circuits (like “sea of gates”) without knowing of the component input/output (I/O) and boundaries. The table  1300  shows that the formulae are successfully extracted with example methods. 
       FIG. 14  shows a table illustrating example methods in accordance with an example embodiment. 
     In the table  1400 , the first three columns show benchmark information. Each benchmark has two circuits g1 and g2, which have logic differences. As an example, g1 is a HT-tampered or examined circuit and g2 is the golden or correct circuit. The next 2 columns show patch size in gates and runtime with example methods or schemes. Last 2 columns show the patch size in gates and runtime using two example methods (i.e. Example method 1 and Example method 2). As shown, example methods generate patches 40% smaller with central processing unit (CPU) time reduced by 86%. 
       FIG. 15  shows a computer system or electronic system in accordance with an example embodiment. The computer system  1500  includes one or more computers or electronic devices (such as one or more servers)  1510  that includes a processor or processing unit  1512  (such as one or more processors, microprocessors, and/or microcontrollers), one or more components of computer readable medium (CRM) or memory  1514 , and a circuit security enhancer  1518 . 
     The memory  1514  stores instructions that when executed cause the processor  1512  to execute a method discussed herein and/or one or more blocks discussed herein. The circuit security enhancer  1518  is example of specialized hardware and/or software that assist in improving performance of a computer and/or execution of a method discussed herein and/or one or more blocks discussed herein. Example functions of a circuit security enhancer are discussed in connection with  FIG. 3 . 
     In an example embodiment, the computer system  1500  includes a storage or memory  1530 , a portable electronic device or PED  1540  in communication over one or more networks  1520 . 
     The storage  1530  can include one or more of memory or databases that store one or more of image files, audio files, video files, software applications, and other information discussed herein. By way of example, the storage  1530  store image, instructions or software application that are retrieved by the server  1510  over the network  1520  such that a method discussed herein and/or one or more blocks discussed herein are executed. 
     The PED  1540  includes a processor or processing unit  1542  (such as one or more processors, microprocessors, and/or microcontrollers), one or more components of computer readable medium (CRM) or memory  1544 , one or more displays  1546 , and a circuit security enhancer  1548 . 
     The PED  1540  can execute a method discussed herein and/or one or more blocks discussed herein and display an image or a file (such as a netlist) for review. Alternatively or additionally, the PED  1540  can retrieve files such as images and files and software instructions from the storage  1530  over the network  1520  and execute a method discussed herein and/or one or more blocks discussed herein. 
     In an example embodiment, the computer system  1500  includes a PED  1550  that includes a processor or processing unit  1552  (such as one or more processors, microprocessors, and/or microcontrollers), one or more components of computer readable medium (CRM) or memory  1554 , and one or more displays  1556 . 
     By way of example, the PED  1550  communicates with the server  1510  and/or the storage  1530  over the network  1520  such that a method discussed herein and/or one or more blocks discussed herein is executed either by the server  1510  and results are sent back to the PED  1550  for output, storage and review. 
     The network  1520  can include one or more of a cellular network, a public switch telephone network, the Internet, a local area network (LAN), a wide area network (WAN), a metropolitan area network (MAN), a personal area network (PAN), home area network (HAM), and other public and/or private networks. Additionally, the electronic devices need not communicate with each other through a network. As one example, electronic devices can couple together via one or more wires, such as a direct wired-connection. As another example, electronic devices can communicate directly through a wireless protocol, such as Bluetooth, near field communication (NFC), or other wireless communication protocol. 
     In some example embodiments, the methods illustrated herein and data and instructions associated therewith, are stored in respective storage devices that are implemented as non-transitory computer-readable and/or machine-readable storage media, physical or tangible media, and/or non-transitory storage media. These storage media include different forms of memory including semiconductor memory devices such as DRAM, or SRAM, Erasable and Programmable Read-Only Memories (EPROMs), Electrically Erasable and Programmable Read-Only Memories (EEPROMs) and flash memories; magnetic disks such as fixed and removable disks; other magnetic media including tape; optical media such as Compact Disks (CDs) or Digital Versatile Disks (DVDs). Note that the instructions of the software discussed above can be provided on computer-readable or machine-readable storage medium, or alternatively, can be provided on multiple computer-readable or machine-readable storage media distributed in a large system having possibly plural nodes. Such computer-readable or machine-readable medium or media is (are) considered to be part of an article (or article of manufacture). An article or article of manufacture can refer to a manufactured single component or multiple components. 
     Blocks and/or methods discussed herein can be executed a processor, controller, and other hardware discussed herein. Furthermore, blocks and/or methods discussed herein can be executed automatically with or without instruction from a user. 
     In another aspect of the present invention, methods and apparatus for transforming the function of a circuit is disclosed. 
     When an IC chip is being designed, the design follows a particular specification. However, in many circumstances, the design has to be revised to another specification sometime after the initial design. There can be various reasons behind the revision, for example detection of a bug that affects circuit operation or reliability, fulfilling new requirements, or improving performance by reducing resource usage for performing a function, addition of new features, or changing to another approach to perform a function. 
     The changes to be made to the existing design is known as engineering change orders (ECO). ECO works by adding a patch to the original specification to produce a transformed specification of the circuit. ECOs can be performed manually or using automatic ECO tools, but existing ECO tools do not produce an optimized ECO result, and may affect circuit properties and performance as a result. The effect may be significant enough for the circuit to fail performance, safety or usage requirements. 
     In other embodiments, a method of transforming the function of a circuit is disclosed. Referring to method  1600  of  FIG. 16 , in block  1602 , a first register-transfer level (RTL) document is provided for the circuit. The first RTL document is being of an original specification or implementation, which is the circuit before any engineering changes has taken place. 
     In block  1604 , a second RTL document is provided for the circuit, the second RTL document is being of a revised specification. Since the revised specification is designed by the user, the second RTL is known and can be provided. In preferred embodiments, the first and RTL documents are both golden specifications. 
     In block  1606 , a first gate level (GTL) netlist is generated or synthesized from the first RTL document. In block  1808 , a second GTL netlist is generated or synthesized from the second RTL document. The netlists can be netlist after synthesis or netlist after placement and routing. 
     In block  1610 , the first RTL document is compared with the second RTL document. By comparing the RTL documents, the instances to be modified can be extracted and identified. In general circumstances, only a part of the instances is modified, and the rest remains unmodified, since some function of the original design is retained for ECO to be effective and efficient. As such, this comparing step eliminates the unnecessary instances to be ECOed and thus reduces the instances modified to a minimum, hence optimizing the ECO or function transformation operation. As in the context of the present specification, instances include module ports, sequential instances and signals. 
     In block  1612 , the instances to be modified in the first RTL document are located in the first GTL netlist. Based on the located instances, modules in the first GTL netlist to be ECOed are identified. In one embodiment, the modules to be patched by ECO is defined as a first list of modules, and the modules that are not affected by ECO or preserved in the ECO operation is defined as a second list of modules. By preserving the second list of modules not to be patched, the resource usage of the ECO engine is reduced and the ECO process may be completed faster. 
     In block  1614 , ECO is performed to the first list of modules. The ECO engine first refers to the second GTL netlist to determine how the modules should be patched, then an ECO patch is applied to the first list of modules to transform the function of the circuit, such that the first GTL netlist after ECO is equivalent or identical to the second GTL netlist, which also means the patched circuit is functionally equivalent to the revised design. In an embodiment, the implementation of the necessary changes may involve at least one of rewiring, rewriting, technology mapping cut sweeping and any other logic synthesis techniques. 
     In other embodiments, the instances to be modified in the first GTL netlist are further specified using hardware description language (HDL). HDL may be used to specify the signals in the first netlist that needs to be modified, and also to identify the corresponding signals in the second GTL netlist. This allows the ECO process to be further optimized in cases where the location of instances in the first RTL document by the computer system is not perfect. 
     In other embodiments, the modules in the first netlist to be modified is determined by iteration. First, a first group of modules are identified as those modules where the instances to be modified reside. Next, the first group of modules is traversed forward and backward to identify any additional modules that are affected by the patch. These additional modules are defined as the second group of modules. The traversal process is repeated using the newly affected modules identified as the input, and the iteration ends when no more additional affected modules are discovered. 
     In other embodiments, multi-bit registers in the first netlist are preserved in the ECO process. In existing ECO technologies, multi-bit registers are treated just as multiple separate single-bit registers. These multi-bit registers, when their function have to be modified, are generally split into single-bit registers. However, such type of modification induces significant change in circuit properties such as logical and physical properties. By preserving the multi-bit registers, even though the function e.g. clock functions, clock gating functions or data functions have to be modified, the change in circuit properties is minimized, and also allows formal verification checking. 
       FIG. 17  shows a diagram  1700  illustrating an example method of generating a netlist to be patched in accordance with an example embodiment. 
     Referring to  FIG. 17 , old RTL document  1701  is the document that describe an original specification, wherein the original specification is the definition and requirements about the circuit design before any ECO process. Old synthesis netlist  1702  is the netlist after synthesis of the old RTL document  1701 . The Old post-APR netlist  1703  is the netlist after placement and routing of the old synthesis netlist  1702 . The old synthesis netlist  1702  and old post-APR netlist  1703 , separately or together, is also referred to as “the old netlist” in example embodiments. 
     New RTL document  1704  is the document that describe a revised specification, wherein the revised specification is the definition and requirements about the circuit design after ECO process, i.e. a target circuit design. New synthesis netlist  1705  is the netlist after synthesis of the new RTL document  1704 . 
     In the method shown in diagram  1700 , firstly, the old RTL document  1701  and the new RTL document  1704  are generated for describing the original specification and the revised specification, respectively. The old RTL document  1701  and the new RTL document  1704  are further synthesized to be the old synthesis netlist  1702  and the new synthesis netlist  1705 . The old RTL document  1701  and the new RTL document  1704  are then compared to generate the ECOed netlist  1706 . The ECOed netlist  1706  is a list of modules that need to be patched in the original circuit design. After patching the list of modules, the patched old netlist is thus functionally equivalent to the new RTL netlist  1704 . 
     In an example embodiment, the old synthesis netlist  1702  is a GTL netlist generated from the old RTL document  1701 . The new synthesis netlist  1705  is a GTL netlist generated from the new RTL document  1704 . 
     In an example embodiment, the patches are applied on either the old synthesis netlist  1702  or the old post-APR netlist  1703 , depending on the implementation of the engineering change orders, to make the old netlist functionally equivalent to the new RTL netlist  1704 . 
     In one example embodiments, the old RTL document  1701  and the new RTL document  1704  are compared to identify the signals that need to be modified in the old synthesis netlist such that the revised specification can be implemented. The identified to-be-modified signals allow a minimum amount of changes made to modify the old netlist into the new netlist. 
     In one example embodiments, hardware description language (HDL) is used to further fine-tune the signals-to-be-modified. Signals in the old synthesis netlist  1702  whose functions need to be changed and the corresponding signals in the new synthesis netlist  1705  are specified in HDL respectively. The information will then be applied to further pinpoint the signals-to-be-modified in the old synthesis netlist  1702 . 
     In one example embodiment, the old netlists (old synthesis netlist  1702  or old post-APR netlist  1703 , depending on the need) are searched for the signals-to-be-modified. These signals may reside in one or more modules. We refer this group of modules as the first group of modules. Since the initial set of signals-to-be-modified may affect other signals before or after them, the aggregated set of signals-to-be-modified may be larger than the initial set. 
     In one embodiment, the fan-in and fan-out cones of the signals-to-be-modified are established, and the first list of modules that need to be patched are identified recursively in the fan-in and fan-out cones of the signals-to-be-modified. As a result of the traversal over the modules affected by ECO, the list of signals to-be-modified is populated automatically. All other sub-modules which are not affected by the modification are identified as the second list of modules and will not be modified. After that, the new netlist is analyzed and used as a reference to make the necessary and exact changes, i.e., the patches, in the old netlist. 
     In one example embodiment, the multi-bit registers in the old netlist are preserved during the implementation of the necessary changes. The multi-bit registers are not split into single-bit registers even if their functions (clock functions, clock gating functions or data functions) have to be modified. This allows a minimum amount of changes in terms of logical and physical properties of the circuit. Besides introducing minimum disturbance to the circuit properties, this practice also facilities formal verification checking. 
     In one example embodiment, the patching/modification is implemented by performing engineering change orders. The implementation of the engineering change orders may involve rewiring, rewriting, technology mapping, cut sweeping, and/or any other logic synthesis techniques. 
     In one example embodiment, the circuit mentioned herein is an arithmetic circuit. 
     By adopting the above-mentioned steps, the present invention verifies the ECO result efficiently, makes small patches and minimum change to the circuit properties, and reduces the calculation time. 
       FIG. 18  shows a diagram  1800  illustrating an example method of obtaining the instances, module ports and signals to be patched in a circuit in accordance with an example embodiment. 
     In  FIG. 18 , the old RTL document  1801  and new RTL document  1802  are generated for describing the original specification and the revised specification, i.e. the target specification, respectively. The old RTL document  1801  and new RTL document  1802  are then input into a formal verification tool  1803  for verification. The formal verification tool  1803  performs comparison between the old RTL document  1801  and the new RTL document  1802 , and indicates with great precision at which point there exists a difference between the old RTL document  1801  and new RTL document  1802 . Finally, the formal verification tool  1803  outputs the to-be-modified module ports  1804 , to-be-modified sequential instances  1805  and/or to-be-modified signals. 
     In one example embodiment, the formal verification tool  1803  is a logic equivalence checking (LEC) tool that exhaustively verifies the GTL, which is much faster than traditional gate-level simulation and decreases the risk of missing critical bugs with independent verification technology. 
       FIG. 19  shows a diagram  1900  illustrating an example of an ECO procedure in accordance with an example embodiment. 
     In  FIG. 19 , the non-equivalent module ports  1901 , the non-equivalent sequential instances  1902 , the old synthesis netlist  1903  the old post-APR netlist  1904  and the new synthesis netlist  1905  are provided to the ECO tool  1906  to generate an ECOed netlist  1907 , wherein the non-equivalent module ports  1901 , the non-equivalent sequential instances  1902  are generated by comparison of the old RTL document with the new RTL document. 
     The methods in accordance with example embodiments are provided as examples, and examples from one method should not be construed to limit examples from another method. Figures and other information show example data and example structures; other data and other database structures can be implemented with example embodiments. Further, methods discussed within different figures can be added to or exchanged with methods in other figures. Further yet, specific numerical data values (such as specific quantities, numbers, categories, etc.) or other specific information should be interpreted as illustrative for discussing example embodiments. Such specific information is not provided to limit example embodiments. 
     As used herein, the term “hardware Trojan” (HT) refers to an unauthorized or unintended alteration, modification, insertion, implantation or inclusion to a circuit. For example, a HT causes malfunction, reduced reliability, confidential information leakage, etc. or combination thereof. 
     As used herein, the term “arithmetic circuit” refers to a circuit in which one or more parts of the circuit are used to accomplish arithmetic operations such as addition, subtraction, multiplication and any other arithmetic operations. 
     As used herein, the term “netlist” lists the connectivity between logic gates forming a circuit. 
     As used herein, the term “macro” or “arithmetic macro” refers to a number of logic primitives or standard cells which compose a component in a circuit (e.g. an IC) such as adders, multipliers, multiplexers (MUX) or a formula such as (A+B)×C, etc. 
     As used herein, the term “sub circuit” refers to term “macro” and these two terms can be used interchangeably. 
     As used herein, the term “2-input exclusive-or (XOR) sub circuit” refers to a sub circuit which has 2 input signals and 1 output signal. The functionality of the output signal is the exclusive or function of two input signals. 
     As used herein, the term “XOR tree” refers to a sub circuit which is composed of one or more 2-input XOR sub circuits and their connections. 
     As used herein, the term “1-bit adder” refers to 1-bit half adder and/or 1-bit full adder. 
     As used herein, the term “1-bit half adder” refers to an arithmetic macro which has 2 inputs (e.g. a and b) and  2  outputs (e.g. sum and co). “co” can be also called carry or carry out. The functionality of sum is “exclusive or” function of a and b; the functionality of co is “and” function of a and b. 
     As used herein, the term “1-bit full adder” refers to an arithmetic macro which has 3 inputs (e.g. a, b, and c) and  2  outputs (e.g. sum and co). “co” can be also called carry or carry out. The functionality of sum is “exclusive or” function of a, b and c; the functionality of co is “majority” function of a, b and c. 
     As used herein, the term “1-bit adder graph” refers to a sub circuit which is composed of one or more 1-bit adders and their connections. 
     As used herein, the term “XOR forest” refers to the term “1-bit adder graph” and these two terms can be used interchangeably. 
     As used herein, the term “reverse engineering (RE)” refers to the process to extract arithmetic macros from a circuit. An RE process comprises identifying 2-input exclusive-or (XOR) sub circuits, XOR trees, 1-bit adders, 1-bit adder graphs, and arithmetic macros. 
     As used herein, the term “exponential time” refers to running time for an algorithm or a method is upper bounded by 2 poly(n) , where poly(n) is some polynomial in n, wherein n is size of the input for the algorithm. 
     As used herein, the term “polynomial time” refers to running time for an algorithm or a method is upper bounded by a polynomial expression in the size of the input for the algorithm. 
     As used herein, the term “linear time” refers to running time for an algorithm or a method increases linearly with the size of the input for the algorithm.