Patent Publication Number: US-2011068758-A1

Title: Regulated circuits and operational amplifier circuits

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to a circuit and a control method thereof, and more particularly, to an operational amplifier and a regulated circuit and a control method thereof. 
     2. Description of the Prior Art 
     Most circuits require a stable and specific voltage for proper operation. While grid power lines or batteries are convenient for use, they may not be suitable for each and every circuit because the voltages they provide range widely. Therefore, different regulator circuits are developed to convert output voltage of an energy source to a stable voltage for different circuit applications. 
     A low dropout (LDO) voltage regulator is a voltage converter used to convert a DC power source and deliver a stable output voltage. An LDO voltage regulator, for example, comprises a power switch, which is typically a field effect transistor, coupled between an input power source and an output power source. Channel resistance of the power switch is controlled via a feedback mechanism so as to regulate the output voltage. 
       FIG. 1  is a diagram of a conventional LDO voltage regulator. P-type metal oxide semiconductor (PMOS) transistor MP 0  acts as a power switch. Resistors R 1  and R 2  generate feedback voltage V fb . Transconductance amplifier GM compares feedback voltage V fb  with a predetermined reference voltage V ref . Transconductance amplifier GM usually has a large output resistance, so when driving the gate end of PMOS transistor MP 0 , the signal transient response speed of the LDO voltage regulator is relatively slow due to the large parasitic capacitance at the gate end of PMOS transistor MP 0 . Therefore, buffer BUFFER is disposed between transconductance amplifier GM and PMOS transistor MP 0  to provide a higher input resistance and a lower output resistance. By this way, the signal transient response speed of the LDO voltage regulator can be increased. 
     Numerous buffer structures are disclosed in the prior art. According to U.S. Pat. Nos. 6,501,305 and 5,861,736, the buffer may be an emitter follower, a source follower or a push-pull amplifier, as shown in  FIG. 2A ,  2 B and  2 C, respectively. 
     SUMMARY OF THE INVENTION 
     The present invention discloses a regulated circuit for providing a regulated voltage. The regulated circuit comprises an output stage, an amplifier stage and a buffer. The output stage comprises a power switch with a control node, a power input node and a power output node. The power input node is coupled to a source voltage. The power output node is for providing the regulated voltage. The amplifier stage comprises a first output node and a second output node, for comparing a feedback voltage approximately proportional to the regulated voltage with a reference voltage. The buffer comprises an output node and an input node coupled to the first output node. The output node of the buffer and the second output node of the amplifier stage collectively drive the control node of the output stage. Output resistance of the output node of the buffer is lower than that of the second output node of the amplifier stage. 
     The present invention further discloses an operational amplifier circuit. The operational amplifier comprises an amplifier stage and a push-pull buffer. The amplifier stage comprises a pair of first output nodes and a second output node, for comparing a first input signal and a second input signal. The push-pull buffer comprises a pair of input nodes and an output node, the pair of input nodes coupled to the pair of first output nodes accordingly. The output node of the buffer and the second output node of the amplifier stage collectively drive an output load. Output resistance of the output node of the buffer is lower than that of the second output node of the amplifier stage. 
     The present invention further discloses a regulated circuit for providing a regulated voltage. The regulated circuit comprises an output stage, an amplifier stage and a buffer. The output stage comprises a power switch with a control node, a power input node and a power output node. The power input node is coupled to a source voltage. The power output node is for providing the regulated voltage. The amplifier stage comprises a pair of first output nodes and a second output node, for comparing a feedback voltage approximately proportional to the regulated voltage with a reference voltage. The buffer comprises a class AB push-pull amplifier with a pair of input nodes and an output node, the pair of input nodes is coupled to the pair of first output nodes. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram of a conventional LDO voltage regulator. 
         FIG. 2A-2C  are diagrams of numerous buffer structures. 
         FIG. 3  is a diagram of an LDO voltage regulator according to an embodiment of the present invention. 
         FIG. 4  is a diagram of the LDO voltage regulator in  FIG. 3  according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Further objects of the present invention and more practical merits obtained by the present invention will become more apparent from the description of the embodiments which will be given below with reference to the accompanying drawings. For explanation purposes, components with equivalent or similar functionalities are represented by the same symbols. Hence components of different embodiments with the same symbol are not necessarily identical. Here, it is to be noted that the present invention is not limited thereto. 
     When the LDO voltage regulator of  FIG. 1  is paired with any of the buffers shown in  FIG. 2A-2C , a problem rises: the gate voltage at the gate end of PMOS transistor MP 0  does not swing rail-to-rail. Taking the buffer in  FIG. 2C  as an example, even if voltage V 1  is as high as source voltage V in  of the input power source, gate voltage V g  can only be pulled, at best, to the voltage level equivalent to source voltage V in  minus activating voltage V be-ON  of an NPN transistor. In other words, the gate voltage of PMOS transistor MP 0  cannot fully swing between voltage levels of the source voltage V in  and ground, consequently lowering dynamic range of the LDO voltage regulator. 
       FIG. 3  is a diagram of an LDO voltage regulator according to an embodiment of the present invention. As shown in  FIG. 3 , transconductance amplifier GM, which is utilized as an amplifier stage, compares feedback voltage V fb  and reference voltage V ref  at two input nodes. Transconductance amplifier GM comprises two output nodes. Buffer BUFFER, as a buffer stage, is coupled between the first output node of transconductance amplifier GM and a gate end of PMOS transistor MP 0 . Buffer BUFFER can be realized with an emitter follower or a source follower as shown in  FIG. 2A-2C . Buffer BUFFER can also be realized with a class A, class B or class AB amplifier. Overall, transconductance amplifier GM as the amplifier stage and buffer BUFFER as the buffer stage together form an operational amplifier circuit. Voltage gain of buffer BUFFER can approximately be 1. In PMOS transistor MP 0  as an output stage, the gate end is not only driven by the output node of buffer BUFFER, but also driven by the second output node of transconductance amplifier GM, as illustrated in  FIG. 3 . The source end of PMOS transistor MP 0  is coupled to source voltage V in , and the drain end provides regulated voltage V out . 
       FIG. 4  is a diagram of the LDO voltage regulator in  FIG. 3  according to another embodiment of the present invention. Transconductance amplifier  20  comprises differential amplifier  22 , which compares feedback voltage V fb  and reference voltage V ref . Differential amplifier  22  comprises positive output node np and negative output node nn. Differential amplifier  22  may also be realized by other differential circuits. Circuit  24 , together with PMOS transistors MP 1  and MP 2 , may act as a gain circuit with two current output nodes respectively disposed at drain ends of PMOS transistors MP 1  and MP 2 . N-type metal oxide semiconductor (NMOS) transistors MN 1  and MN 2  may act as another gain circuit with two current output nodes disposed at drain ends of NMOS transistors MN 1  and MN 2  respectively. The drain ends of PMOS transistor MP 1  and NMOS transistor MN 1  may operate as one pair of output nodes of transconductance amplifier  20 , while the drain ends of PMOS transistor MP 2  and NMOS transistor MN 2  may operate as another pair of output nodes of transconductance amplifier  20 . 
     Buffer  26  may be a class AB push-pull amplifier and comprises NMOS transistors MN 3  and MN 4 , as well as PMOS transistors MP 3  and MP 4 . Upper input node nu of buffer  26  is coupled to the drain end of PMOS transistor MP 1 , and lower input node nd is coupled to the drain end of NMOS transistor MN 1 . In the embodiment illustrated in  FIG. 4 , NMOS transistors MN 3  and MN 4  are depletion-mode MOS transistors, while the other NMOS transistors are enhancement-mode MOS transistors. As known by those skilled in the art, an enhancement-mode MOS transistor needs an extra voltage to form a conductive channel between the drain and source ends, while a depletion-mode MOS transistor needs no extra voltage to form the conductive channel. For instance, threshold voltage of an enhancement-mode NMOS transistor has a positive value, and threshold voltage of a depletion-mode MOS transistor is 0 Volts or a negative value. Since NMOS transistors MN 3  and MN 4  are depletion-mode MOS transistors, when voltage level of upper input node nu reaches voltage level of source voltage V in , gate voltage V g  at the gate end of PMOS MP 0  may also be pulled up to the voltage level of source voltage V in . 
     The output node (i.e. the joint node of the source ends of NMOS transistor MN 4  and PMOS transistor MP 4 ) of buffer  26  is coupled to one current output node (i.e. the joint node of the drain ends of NMOS transistor MN 2  and PMOS transistor MP 2 ) of transconductance amplifier  20  so as to collectively drive the gate end of PMOS transistor MP 0  (equivalent to control node ng). 
     In  FIG. 4 , output resistance of buffer  26  can be designed to be lower than any output resistance of MN 1 , MN 2 , MP 1 , and MP 2 . Therefore, buffer  26  may rapidly charge/discharge control node ng, providing a higher signal transient response speed. 
     When voltage level of lower input node ng of buffer  26  approaches 0V (ground voltage level), buffer  26  is unable to pull gate voltage V g  down to 0V since PMOS transistor MP 4  is enhancement-mode. However, gate voltage V g  may be pulled down to 0V by transconductance amplifier  20  via NMOS transistor MN 2 . In other words, although buffer  26  is unable to cause gate voltage V g  to swing rail-to-rail, since control node ng is also directly driven by one output of transconductance amplifier  20 , gate voltage V g  can therefore attain rail-to-rail variation. 
     During normal operation, when feedback voltage V fb  diverges from reference voltage V ref , buffer  26  in  FIG. 4  promptly drives control node ng to adjust the channel resistance of PMOS transistor MP 0 , rapidly increasing or decreasing regulated voltage V out  so as to make feedback voltage V fb  approach to reference voltage V ref . In this embodiment, buffer  26  is a class AB push-pull amplifier with two input nodes connecting to nodes nu and nd respectively, so buffer  26  may react to a comparison result of differential amplifier  22  promptly, and quickly alter gate voltage V g  at control node ng through push or pull. 
     Once gate voltage V g  exceeds the driving range of buffer  26 , transconductance amplifier  20  directly drives control node ng via PMOS transistor MP 2  or NMOS transistor MN 2 , so gate voltage V g  can swing rail-to-rail for sustaining the dynamic range. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.