Patent Publication Number: US-9837370-B2

Title: Bump structures for multi-chip packaging

Description:
PRIORITY CLAIM 
     The present application is a continuation application of U.S. patent application Ser. No. 14/310,488, filed Jun. 20, 2014, entitled “Bump Structures for Multi-chip Packaging,” which is a continuation application of U.S. application Ser. No. 13/427,753, now U.S. Pat. No. 8,779,588, filed Mar. 22, 2012, entitled “Bump Structures for Multi-chip Packaging,” which claims priority of U.S. Provisional Patent Application No. 61/564,594, filed Nov. 29, 2011, all of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     The fabrication of modern circuits involves several steps. Integrated circuits are first fabricated on a semiconductor wafer, which contains multiple duplicated semiconductor chips, each comprising integrated circuits. The semiconductor chips are then sawed from the wafer and packaged. The packaging processes have two main purposes: to protect delicate semiconductor chips, and to connect interior integrated circuits to exterior connections. 
     In packaging integrated circuit (IC) chips, solder joining is one of the commonly used methods for bonding IC chips to package substrates, which may or may not include integrated circuits and/or other passive components. In packaging processes, a semiconductor die (or chip) may be mounted on a package substrate using flip-chip bonding. The package substrate may be an interposer that includes metal connections for routing electrical signals between opposite sides. Other types of substrates may also be used. The die may be bonded to the substrate through direct metal bonding, solder bonding, or the like. There are many challenges in chip packaging. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
         FIGS. 1A and 1B  show cross sectional views of a process sequence for forming bump structures between an integrated circuit (IC) die (or chip) and a substrate, in accordance with some embodiments. 
         FIGS. 1C and 1D  show cross-sectional views of two bump structures, in accordance with some embodiments. 
         FIG. 2A  shows a top view of a multi-chip package with a number of chips bonded to a substrate, in accordance with some embodiments. 
         FIG. 2B  shows a cross-sectional view of a portion of the multi-chip package of  FIG. 2A  cut along line P-P, in accordance with some embodiments. 
         FIGS. 2C and 2D  show cross-sectional views of two bump structures, in accordance with some embodiments. 
         FIGS. 3A and 3B  show cross sectional views of a process sequence for forming bump structures between a chip and a substrate, in accordance with some embodiments. 
         FIGS. 3C and 3D  show cross sectional views of a process sequence for forming bump structures between a chip and a substrate, in accordance with some embodiments. 
         FIG. 3E  shows top views of different numbers and arrangements of micro-bumps for bonding to a larger flip-chip bump, in accordance with some embodiments. 
         FIG. 4  shows a process flow of forming a multi-chip package, in accordance with some embodiments. 
         FIG. 5  shows a more detailed cross sectional view of a multi-chip package of  FIG. 2A  cut along line P-P, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
       FIG. 1A  shows a cross sectional view of an integrated circuit (IC) die (or chip)  120  and a substrate  125  after bumps  121  and  126  are formed respectively, in accordance with some embodiments. Bumps  121  and  126  are connected to metal pads  128   C  and  128   S  via under bump metallurgy (UBM) layers  145   C  and  145   S  respectively, as shown in  FIG. 1A . Bumps  121  are aligned with bumps  126  for bonding. The width of bumps  121  is W. In some embodiments, the width of bumps  126  is about the same as the width of bumps  121 . Substrate  125  may be a semiconductor wafer, or a portion of a wafer. Substrate  125  may include silicon, gallium arsenide, silicon on insulator (“SOI”) or other similar materials. Substrate  125  may also include passive devices such as resistors, capacitors, inductors and the like, or active devices such as transistors. Substrate  125  may be an interposer and may further include through substrate vias (TSVs)  135 , as shown in  FIG. 1A . In addition, the substrate  125  may also be of other materials in alternative embodiments. For example, multiple layer circuit boards may be used. Substrate  125  may also include bismaleimide triazine (BT) resin, FR-4 (a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant), ceramic, glass, plastic, tape, film, or other supporting materials that may carry the conductive pads or lands needed to receive the connector terminals  115  for the flip-chip IC die  120 . 
       FIG. 1B  shows a cross-sectional view of chip  120  bonded to substrate  125  to form package  122 , in accordance with some embodiments. Bumps  121  and  126  are joined together by a solder layer  123 , which is formed of solder from bumps  121  and  126 , to form bump structures  127 . The bump structures  127  in  FIG. 1B  have a pitch P and a spacing (or distance) S between bumps  127 . 
     For advanced packaging of IC dies with many function circuitries, the sizes of bumps  121  and  126  are relatively small to enable more bumps to connect to an input/output (I/O) of chip  120 . In some embodiments, the widths of bumps  121  and  126  are in a range from about 5 μm to about 40 μm, in accordance with some embodiments. Such bumps may also be called micro-bumps. In some other embodiments, the widths of bumps  121  and  126  are smaller and range from about 2 μm to about 10 μm. Micro-bumps may include copper posts and may be called copper post (or pillar) bumps. The pitch P of bumps (micro-bumps)  121  and  126  are in a range from about 10 μm to about 60 μm, in accordance with some embodiments. The spacing S of bumps (micro-bumps)  121  and  126  are in a range from about 5 μm to about 30 μm, in accordance with some embodiments. In some other embodiments, when the widths of bumps  121  and  126  ranges from about 2 μm to about 10 μm, the spacing S of bumps (micro-bumps)  121  and  126  ranges from about 1.5 μm to about 10 μm. 
       FIG. 1C  shows a bump structure  100  with a substrate  110 , in accordance with some embodiments. Substrate  110  may be a semiconductor substrate, such as a bulk silicon substrate, although it may include other semiconductor materials, such as group III, group IV, and/or group V elements. Substrate  110  may include silicon, gallium arsenide, silicon on insulator (“SOI”) or other similar materials. Semiconductor devices  114 , such as transistors, may be formed at the surface of substrate  110 . Substrate  110  may also include passive devices such as resistors, capacitors, inductors and the like, or active devices such as transistors. Substrate  100  may, in an exemplary embodiment, include additional integrated circuits. Substrate  110  may be an interposer. In addition, the substrate  110  may also be of other materials in alternative embodiments. For example, multiple layer circuit boards may be used. Substrate  110  may also include bismaleimide triazine (BT) resin, FR-4 (a composite material composed of woven fiberglass cloth with an epoxy resin binder that is flame resistant), ceramic, glass, plastic, tape, film, or other supporting materials. 
     An interconnect structure  112 , which includes metal lines and vias (not shown) formed therein and connected to semiconductor devices  114 , is formed over substrate  110 . The metal lines and vias may be formed of copper or copper alloys, and may be formed using the well-known damascene processes. Interconnect structure  112  may include commonly known inter-layer dielectrics (ILDs) and inter-metal dielectrics (IMDs). 
     A metal pad  128  is formed over interconnect structure  112 . Metal pad  128  may comprise aluminum, and hence may also be referred to as aluminum pad  128 , although it may also be formed of, or include, other materials, such as copper, silver, gold, nickel, tungsten, alloys thereof, and/or multi-layers thereof. Metal pad  128  may be electrically connected to semiconductor devices  114 , for example, through underlying interconnection structure  112 . The metal pad  128  may be a top metal layer or a redistribution layer (RDL). In some embodiments, a passivation layer  130  is formed to cover edge portions of metal pad  128 . The passivation layer  130  may be formed of polyimide or other suitable dielectric materials. Additional passivation layers may be formed over interconnect structure  112  and at the same level, or over, metal pad  128 . The additional passivation layers may be formed of materials such as silicon oxide, silicon nitride, un-doped silicate glass (USG), polyimide, and/or multi-layers thereof. 
     The bump structure  100  includes a diffusion barrier layer  140  and a thin seed layer  142 , in accordance with some embodiments. Diffusion barrier layer  140  may be a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer. The materials of seed layer  142  may include copper or copper alloys, and hence is referred to as copper seed layer  142  hereinafter. However, other metals, such as silver, gold, aluminum, and combinations thereof, may also be included. The combined diffusion barrier layer  140  and copper seed layer  142  may also be referred to as an under bump metallurgy (UBM) layer  145 . 
     In some embodiments, bump structure  100  also includes a copper layer  150 , a metal layer  152 , and a solder layer  160 . The copper layer  150 , the metal layer  152 , and the solder layer  160  are formed by plating with a photo mask defining the openings, in accordance with some embodiments. In some embodiments, metal layer  152  is a nickel-containing layer comprising, for example, a nickel layer or a nickel alloy layer by plating. Metal layer  152  prevents the formation of an inter-metallic compound (IMC) between copper and solder. Solder layer  160  may be a lead-free pre-solder layer formed of, for example, SnAg, or a solder material, including alloys of tin, lead, silver, copper, nickel, bismuth, or combinations thereof. In  FIG. 1A , the solder layer  160  is rounded as a result of reflow. In some embodiments, bump structure  100  does not include solder layer  160 . In some embodiments, bump structure  100  does not include solder layer  160  and metal layer  152 . 
     When the thickness of copper layer  150  is larger than the thickness of solder layer  160 , the bump structure is referred to as a copper post (or pillar) bump. For advanced chip packaging, the bump pitch and bump width are reduced. Copper post bump enables reduction of bump pitch and width. The embodiment shown in  FIG. 1A  is merely an example; other embodiments of bumps are also possible. Further details of bump formation process may be found in U.S. patent application Ser. No. 12/842,617, filed on Jul. 23, 2010 and entitled “Preventing UBM Oxidation in Bump Formation Processes,” and U.S. patent application Ser. No. 12/846,353, filed on Jul. 29, 2010 and entitled “Mechanisms for Forming Copper Pillar Bumps,” both of which are incorporated herein in their entireties. 
       FIG. 1D  shows a bump structure  150 , in accordance with some other embodiments. Bump structure  150  has many features similar to bump structure  100 . The same numbering is used for similar layers or structures. Bump structure  150  does not have solder layer  160 . In addition, the metal layer  152 ″ is formed to cap an entire surface of copper layer  150 . Copper layer  150  formed after the UBM layer  145  and extending from the boundary of copper layer  150  has been removed. 
     With the increased popularity of handheld electronic devices, memory chips are packaged with logic chip(s) to improve the package form factor. A chip package with more than one chip is called multi-chip package. Some chips, such as memory chips, have lower counts of input/output (I/O) connections. Such chips are manufactured with larger bumps, due to the relatively lower number of I/O connections needed. In addition, larger bumps are easier to make and can be made by less advanced processing technologies.  FIG. 2A  shows a top view of a multi-chip package  200  with a number of chips  201 - 205  bonded to a substrate  210 , in accordance with some embodiments. Substrate  210  has bumps to bond with bumps on chips  201 - 205 . Although in some embodiments the bumps on substrate  210  have different sizes, the manufacturing process is more complicated and more expensive as the number of different sized bumps increases. As a result, in some embodiments, the bumps on substrate  210  have about the same sizes. 
     Chips  201 - 204  are chips with low numbers of I/O connections (bumps), such as memory chips compared to chip  205  with higher number of bumps. For example, chip  205  could be a logic chip, which needs a large number of I/O connections to achieve its functions. As a result, bumps with fine pitches and sizes, such as micro-bumps, are used for external connections. In contrast, memory chips  201 - 204  do not need such bumps, since the number of bumps needed are much lower. It is also possible to make the bump sizes and pitches for memory chips  201 - 204  to be the same as those for logic chip  205 ; however, not every memory manufacturer has the capability or capacity to make smaller bumps, such as micro-bumps. It is a challenge to bond chips with different bump sizes on a single substrate. 
       FIG. 2B  shows a cross-sectional view of a portion of multi-chip package  200  of  FIG. 2A  cut along line P-P, in accordance with some embodiments.  FIG. 2B  shows that chip  201  mounted on substrate  210  with larger bump structures  221  than the bump structures  222  for chip  205 . Although  FIG. 2B  shows that chips  201  and  205  are at the same height after bonding, this is not a requirement. Chips  201  and  205  could be at different heights after bonding. Bump structures  221  and  222  are represented by round shapes in  FIG. 2B  for simplicity. An exemplary bump structure  222  is bump structure  127 , whose formation process has been described above and shown in  FIGS. 1A and 1B . Details of how to form bump structures  221  are described below. 
       FIG. 2C  shows a cross-sectional view of a flip-chip bump  100 * for chip  201 , in accordance with some embodiments. The various layers in flip-chip bump  100 * are similar to those of micro-bump  100  ( FIG. 1C ) described above. The width of bump  100 * is larger than bump  100 , which is a micro-bump in accordance with some embodiments. In some embodiments, the width of bump  100 * is greater than about 40 μm and equal to or less than about 120 μm. Bumps  100 * may also be called C4 bump. C4 stands for controlled collapse chip connection. In addition, the ratio of the thickness of copper layer  150 * to the thickness of solder layer  160 * of bump  100 * is different from the ratio for bump  100 . Bump  100 * has a solder layer  160 * thicker than the copper layer  150 * and is not a copper post bump. In contrast, micro-bump  100  is a copper post bump with copper layer  150  being thicker than solder layer  160 . In some embodiments, the thickness of copper layer  150 * of bump  100 * is in a range from about 5 μm to about 50 μm. The thickness of solder layer  160 * is in a range from about 15 μm to about 60 μm, in accordance with some embodiments. 
       FIG. 2D  shows a cross-sectional view of a flip-chip bump  100 ′ for chip  201 , in accordance with some embodiments. The various layers in flip-chip bump  100 ′ are similar to those of bump  100 * described above. However, bump  100 ′ does not have copper layer  150 * and metal layer  152 * of  FIG. 2C . The solder layer  160 ′ is directly deposited on UBM layer  145 ′. The solder layer  160 ′ is rounded due to reflow. In some embodiments, the UBM layer  145 ′ does not include the copper seed layer  142 ′. The range of width of flip-chip  100 ′ is similar to flip-chip  100 *. In some embodiments, the thickness of solder layer  160 ′ is in a range from about 15 μm to about 120 μm. 
       FIG. 3A  shows a cross-sectional view of chip  201  in  FIGS. 2A and 2B  (referred to as chip  201   A  in  FIGS. 3A and 3B ) with a bump  231   A  being placed above substrate  210  (referred to as substrate  210   A  in  FIGS. 3A and 3B ) with micro-bumps  241   A  and  242   A , in accordance with some embodiments. Bump  231   A  has a structure described in  FIG. 2C . The structures of micro-bumps  241   A  and  242   A  have been described in  FIG. 1C . In some embodiments, micro-bumps  241   A  and  242   A  do not have solder layer  160 A and metal layer  152   A . Chip  201   A  and substrate  210   A  are then pressed together to allow bump  231   A  to come in contact with micro-bumps  241   A  and  242   A . Afterwards, the solder layers of the bumps  231   A ,  241   A , and  242   A  are reflowed to form a single layer (or entity)  233   A , which is part of bump structure  245   A  as shown in  FIG. 3B , in accordance with some embodiments. By using more than one micro-bump, bumps  241   A  and  242   A , of substrate  210   A  to contract flip-chip bump  231   A  of chip  201   A , the bump structure  245   A  is stronger than a bump structure involving only one single micro-bump (with only bump  241   A  or bump  242   A ). In addition, micro-bumps  241   A  and  242   A  can share the burden of carrying current to or from bump  231   A . 
       FIG. 3C  shows a cross-sectional view of chip  201  in  FIGS. 2A and 2B  (referred to as chip  201   B  with a bump  231   B  being placed above substrate  210  (referred to as substrate  210   B  in  FIGS. 3A and 3B ) with micro-bumps  241   B  and  242   B , in accordance with some embodiments. Bump  231   B  has a structure described in  FIG. 2D . The structures of micro-bumps  241   B  and  242   B  have been described in  FIG. 1D . In some embodiments,  241   B  and  242   B  do not have metal layer  152   B . Chip  201   E  and substrate  210   B  are then pressed together to allow bumps  231   B  to come in contact with micro-bumps  241   B  and  242   B . Afterwards, the solder layer  160   E  of the bump  231   B s is reflowed to become layer  233   B , which surrounds micro-bumps  241   B  and  242   B , and forms bump structure  245   B , as shown in  FIG. 3D , in accordance with some embodiments. The bumps on chips and substrates and bump structures formed described in  FIGS. 3A-3D  are merely examples. Other types or bumps and combinations of bumps on chips and substrates may also be used to formed different variation of bump structures. 
     The bump structures  245 A and  245 B described above in  FIGS. 3B and 3D  involved only two micro-bumps in each structure. Alternatively, more than two micro-bumps may be used to connect with a flip-chip bump.  FIG. 3E  shows exemplary top views of different numbers and arrangements of micro-bumps for bonding to a larger flip-chip bump.  FIG. 3E  (I) shows 3 micro-bumps spaced evenly.  FIG. 3E  (II) shows 4 micro-bumps spaced evenly.  FIG. 3E  (III) and (IV) show two different arrangements of 5 micro-bumps for bonding with a flip-chip bump.  FIG. 3E  (V) shows 6 micro-bumps spaced evenly. However, un-evenly spaced micro-bumps may also be used. The numbers and arrangements of micro-bumps shown in  FIG. 3E  area merely examples. Additional numbers and/or different arrangements of micro-bumps may also be used. 
     Although chips  201 - 204  of  FIGS. 2A and 2B  and chips  201   A  and  201   B  of  FIGS. 3A-3D  are described above as memory chips, chips  201 - 204  and chips  201   A  and  201   B  could be any chips with flip-chip bumps larger than the bumps on chip  205 . The mechanism of forming a bump structure by bonding a large bump with two or more smaller bumps can be applied to various packaged devices. The smaller bumps on the substrate  210 ,  210   A , and/or  210   B  do not need to be micro-bumps. They just need to be smaller than bumps on chips  201 - 204 ,  201   A  and  210   B . The mechanisms can apply for bonding bumps on chips with bumps having different sizes on substrates. For example, the larger bump could be a micro-bump with a width in a range from about 10 μm to about 40 μm and the smaller bumps could be bumps smaller than micro-bumps, with a width in a range from about 2 μm to about 10 μm. Two or more such bumps that are smaller than micro-bumps may be bonded to a micro-bump in mechanisms described above. 
       FIG. 4  shows a process flow  400  of forming a multi-chip package, in accordance with some embodiments. At operation  401 , two chips with different bump sizes are provided. Each of the bumps on a chip are about the same size. One chip has a bump size much larger than a bump size of the other chip, such as equal to or greater than about 1.5 times. At operation  402 , a substrate for bonding with the two chips is provided. The substrate has bumps with sizes about the same as the chip with smaller bumps. In some embodiments, the pitch(es) of the bumps on the substrate are about the same as the pitch(es) on the chip with smaller bumps. The order of operations  401  and  402  can be reversed. At operation  403 , the chips are placed on the substrate with the bumps on the chips aligned above the bumps on the substrate. Each of the bumps on the chip with larger bumps is disposed above more than one bumps on the substrate. Afterwards, at operation  404 , the bumps are pressed together and the solder between the aligned bumps are reflowed to form bump structures between the chips and the substrate. A multi-chip package is thus formed, as illustrated in  FIG. 5 , wherein bump structure  100  may be, for example, bump structure  100 * or bump structure  100 ′ discussed above with reference to  FIGS. 2C and 2D , respectively, wherein bump structures  241 ,  242  may be, for example, bump structures  241 A,  242 A or bump structures  241 B,  242 B discussed above with reference to  FIGS. 3A and 3C , respectively, wherein bump structures  121  may be, for example, bump structure  121  discussed above with reference to  FIGS. 1A and 1B , and wherein the bump structures  126  may be, for example, bump structure  121  discussed above with reference to  FIGS. 1A and 1B . Additional processing may be performed to complete the packaging process. For example, underfill may be formed to fill the space between the chips and the substrate. 
     The mechanisms for forming a multi-chip package described above enable chips with different bump sizes being packaged to a common substrate. A chip with larger bumps can be bonded with two or more smaller bumps on a substrate. Conversely, two or more small bumps on a chip may be bonded with a large bump on a substrate. By allowing bumps with different sizes to be bonded together, chips with different bump sizes can be packaged together to form a multi-chip package. 
     One aspect of this description relates to a multi-chip package. The multi-chip package includes a substrate having a plurality of first bump structures. A pitch between adjacent first bump structures of the plurality of first bump structures is uniform across a surface of the substrate. The multi-chip package further includes a first chip bonded to the substrate. The first chip includes a plurality of second bump structures, and the plurality of second bump structures are bonded to a first set of first bump structures of the plurality of first bump structures. The multi-chip package further includes a second chip bonded to the substrate. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a second set of first bump structures of the plurality of first bump structures. A pitch between adjacent second bump structures of the plurality of second bump structures is different from a pitch between adjacent third bump structures of the plurality of third bump structures. 
     Another aspect of this description relates to a multi-chip package. The multi-package chip includes a substrate having a plurality of first bump structures. The multi-package chip further includes a first chip bonded to the substrate. The first chip includes a plurality of second bump structures, and at least one second bump structure of the plurality of second bump structures covers an entirety of each sidewall of at least two first bump structures of the plurality of first bump structures. The multi-package chip further includes a second chip bonded to the substrate. The second chip includes a plurality of third bump structures, and the plurality of third bump structures are bonded to a set of first bump structures of the plurality of first bump structures. 
     Still another aspect of this description relates to a method of forming a multi-chip package. The method includes bonding a first chip to a substrate, wherein the substrate has a plurality of first bump structures. The first chip includes a plurality of second bump structures, and bonding the first chip to the substrate comprises covering an entirety of each sidewall of at least two first bump structures of the plurality of first bump structures with a second bump structure of the plurality of second bump structures. The method further includes bonding a second chip to the substrate. The second chip includes a plurality of third bump structures, and bonding the second chip to the substrate includes bonding the plurality of third bump structures to a set of first bump structures of the plurality of first bump structures. 
     Although the embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the embodiments as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, and composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. In addition, each claim constitutes a separate embodiment, and the combination of various claims and embodiments are within the scope of the disclosure.