Patent Publication Number: US-7903433-B2

Title: Current balancing for multi-phase converters

Description:
TECHNICAL FIELD 
     This invention relates to electronics, and more specifically to current balancing for multiphase converters. 
     BACKGROUND 
     As mobile and personal electronic devices power requirements increase, the problems associated with supplying power to the devices have been solved by balancing multiple current phases switched out-of-phase in order to provide the required load current. One factor influencing the success of multi-phase converters is the ability to balance the load current between phases. Without current balancing, one of the phases will carry more current than the others, potentially resulting in thermal and system overload problems. 
     Typically, traditional pulse width modulated (PWM) current mode converters are used as a balancing solution for various applications. Constant on-time converters have also been used, for example in notebook applications because they typically provide better transient response than traditional PWM converters, resulting in smaller, more economical systems for the customer. However, constant on-time converters typically require complex algorithms and calculations to be programmed by a designer its intended application. 
     SUMMARY 
     One embodiment of the present invention includes a converter for a multi-phase current network can include a plurality of current sensors, each of the plurality of current sensors being configured to detect current for a respective phase of the multi-phase network. A current averaging circuit is configured to provide an indication of the average current for the multi-phase network based on the current detected by each of the plurality of current sensors. A modulator is configured to modulate at least one phase of the multi-phase network independently of each other phase of the multi-phase network based on a difference between the current detected for the at least one phase and the average current for the multi-phase network. 
     Another embodiment of the present invention includes a converter for balancing current among different channels of a multi-phase network. The converter includes a first current sensor for sensing current through an inductor of a first phase of the multi-phase network and for providing a first current signal representing the current through the inductor of the first phase and a second sensor for sensing current through an inductor of a second phase of the multi-phase network and for providing a second current signal representing the current through the inductor of the second phase. A first current sharing amplifier provides a scaled output that is proportional to a difference between an average current for the multi-phase network and the current through the inductor of the first phase. A second current sharing amplifier provides a scaled output that is proportional to a difference between an average current for the multi-phase network and the current through the inductor of the second phase. A modulator independently modulates an ON-time for each of first and second phases of the multi-phase network based on the scaled output provided by the first current sharing amplifier and the scaled output provided by the second current sharing amplifier. 
     Yet another embodiment of the present invention includes a converter for a multi-phase current network that includes a plurality of current sensing amplifiers, each of the plurality of current sensing amplifiers being configured to provide a sensor output signal that represents current through an inductor of a respective phase of the multi-phase network. The converter also includes a plurality of current sharing amplifiers, each of the plurality of current sharing amplifiers for a given phase being configured to provide shared current output signal that is proportional to a difference between a determined average current for the multi-phase network and the current through the inductor of the given phase. At least one modulator is configured to modulate at least one phase of the multi-phase network independently of each other phase of the multi-phase network based on a difference between the current detected for the at least one phase and the average current for the multi-phase network. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an example of a current sharing system constructed in accordance with an aspect of the invention. 
         FIG. 2  illustrates an example of a current sharing converter constructed in accordance with an aspect of the invention. 
         FIG. 3  illustrates yet another example of a current sharing converter constructed in accordance with an aspect of the invention. 
         FIG. 4  is a graphical illustration of a timing diagram showing deviation from a normal pulse width for the current sharing systems of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     This invention relates to electronics, and more specifically to a system and method to balance current in a multiphase converter. As one example, such a multi-phase converter system includes a balancing circuit that can balance the current in the different phases by modulating the current in at least one of a plurality of phases independently. As used herein, current balancing can mean an adjustment to achieve equal balance (e.g., equalized current) or it can be employed to achieve other proportional relationships among the phases. The modulation can be implemented by individually modulating such phase (or phases) based on a difference between the current detected for each such phase relative to an average of the current for the entire multi-phase network. To achieve this functionality, the system can include a current sensor configured to sense current for each phase and an averaging circuit that determines the average current for the multi-phase network. The modulator can in turn modulate one or more of the phases independently, thereby eliminating the need for complex calculations or algorithms required in existing types of multi-phase converters. 
       FIG. 1  depicts an example embodiment illustrating a multiphase current sharing system  100 . The multiphase current sharing system  100  includes a current balancing converter, which can be implemented in whole or partially in an integrated circuit (IC)  102 . In the example of  FIG. 1 , the IC  102  is coupled to external circuitry located outside of the IC. The external circuitry can include two or more drivers  104  and  106  of the multiphase system that receive modulated outputs M 1  and M 2  from the current balancing converter. The converter IC  102  provides a modulated output M 1 , M 2  for each channel (e.g., channel  1 , channel  2 ) to an input side of respective external drivers  104 ,  106 . While only two channels are shown, the converter IC  102  is capable of supporting any number of current channels or phases. Each of the drivers  104 ,  106  are coupled on their respective output side to drive a respective switch, schematically depicted at  108 ,  110 . The drivers selectively activate the switches  108  and  110  to provide a corresponding output current to inductors L 1  and L 2 . The inductors L 1  and L 2  are connected in parallel to a capacitor C 1 . The capacitor C 1  is connected between ajunction on output sides L 1   o  and L 2   o  of the inductors L 1 , L 2  and ground. The junction between the capacitor C 1  and inductors L 1 , L 2  provides an output signal V OUT  with a constant current to be provided across several sources. 
     While the example of  FIG. 1  demonstrates certain circuitry as being implemented in the converter IC and other circuitry as being external to the IC, it will be understood that the invention herein contemplates different levels of integration. For example, any of the circuitry, including the drivers  104  and  106 , the switch devices  108  and  110  can be implemented in the IC  102 . Additionally or alternatively, the inductors L 1  and L 2  may also be integrated into the same IC package as the other components of the converter. Thus, those skilled in the art will appreciate various levels of integration that can be achieved according to an aspect of the invention. Additionally, the current balancing approach described herein is applicable to balancing phases for other types of output systems. For example, the converter can be configured to balance the load current or voltage for a multi-phase charge pump (which may include no inductors). 
     An indication of phase current through each of the inductors L 1  and L 2  can be provided as feedback to the converter IC  102 , which feedback is indicated at FB 1  and FB 2 . As one example, a current sensor  112 ,  114  can be coupled to detect the phase current and provide a current sensor output signal with a value (e.g., a voltage) that represents the sensed phase current. The current sensors  112  and  114  could be any known method or construction of circuitry configured for current sensing. In one embodiment, the current sensors can be implemented as current sense amplifiers having a gain set to provide an output voltage indicative of the sensed phase current. Other examples for current sensing in the analog domain include amplifying voltage across a current sense resistor, a hall effect device, MOSFET RDS(on), inductor direct current resistance (DCR), and the like. Each of these devices 
     The converter IC  102  also includes a current averaging circuit  116  configured to determine an average phase current for the multi-phase network. In the example of  FIG. 1 , the current averaging circuit  116  includes inputs coupled to receive an output from each current sensor  112 ,  114 , and accordingly averages the current according to the phase current sensed for each respective channel. The current averaging circuit  116  provides an output signal  118  having a value corresponding to the average current that is provided to the plurality of phases. The average current output signal  118  and the current sensor output signals for each phase are provided to a phase control/equalization circuit  120 . The phase control/equalization circuit  120  is configured to adjust phase current through at least one and suitably each of the channels as a function of the average phase current (indicated by output  118 ) and the indication of the phase currents provided by the current sensors  112  and  114 . As described herein, for example, the phase control/equalization circuit  120  can generate reference signals for each phase based on a difference between the current detected for each phase relative to the average current for the entire multi-phase network. 
     In the example of  FIG. 1 , the output signal  118  can be provided to the inverting input of first and second current share amplifiers  122  and  124 , respectively. The output of current sensor  112  is coupled to the non-inverting input of amplifier  122 , and the output of current sensor  114  is coupled to the non-inverting input of amplifier  124 . The gain amplifiers,  122  and  124  can be implemented as analog summation circuits. The gain amplifiers  122  and  124  each is configured with a gain so that each amplifier provides a respective output signal Vd 1  and Vd 2  having a value that represents the gain multiplied by the difference between the phase current and the average current. 
     Modulators  130  and  132  each receive the same system reference VREF for output voltage control. The modulators  130  and  132  also receive respective input signals Vd 1  and Vd 2 . The modulators  130  and  132  are configured to adjust the pulse width of each respective phase by using Vd 1  and Vd 2  to equalize the current of each channel. Each modulator  130 ,  132  provides a corresponding modulator output signal M 1  and M 2  to respective phase drivers  104  and  106  for controlling output switch devices  108  and  110 . The modulators  130  and  132  can be any type of current modulator, such as pulse width modulators, constant on-time modulators, frequency modulators, and the like, for providing respective modulated signals to the drivers  104  and  106 , respectively. 
     The construction of the converter IC  102  illustrated in  FIG. 1  provides all summing and differentiating operations as analog circuitry internal to the IC, eliminating the need for complex calculation required in conventional converters. The size and costs of the converter is also advantageously reduced. Further, the speed of the current sharing is increased as a result of the converter IC  102  construction. Although two share loops work in tandem to equalize the current in two-phases in the system, from feedback loop operation perspective each can be treated separately. 
     By way of example, let A SH (S) and A CS (s) represent the DC gain for each of the share amplifiers  122 ,  124  and the current-sense amplifier  112 ,  114 , respectively. The small-signal open-loop transfer function of the feedback loop provides insight that can help with the design of the share amplifier and its compensation circuit. For loop analysis, nonlinear elements in the loop can be represented by their time-averaged, linearized models. The open loop transfer function of the system can be given by: 
     
       
         
           
             
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             where: R s  is the resistance of a current sense resistor in series with the inductors L 1  and L 2 ;
           R p  is the phase resistance for the respective loop;   P SH  represents the pole associated with the current share amplifiers  122 ,  124 ;   p CS  represents the pole associated with the current sense amplifiers  112 ,  114 ; and   L is the phase inductance.   
         
           
         
       
    
     Illustrated in  FIG. 2  is another example embodiment of a multiphase current balancing system  200  according to an aspect of the invention. The system  200  includes a plurality of channels I 1 , I 2 , and In (where n is a positive integer denoting the number of channels) representing multiple current phases. The converter IC  202  includes a corresponding current sensing amplifier  204 ,  206 , and  208  that receives a signal from each channel, namely CS 1 , CS 2 , and CSn, respectively. The amplifiers  204 ,  206 , and  208  provide an output signal  205 ,  207 , and  209  indicative of the phase current for each channel. The output signals  205 ,  207 ,  209  are received as inputs side by a respective averaging filter  210 ,  212 , and  214 . The averaging filters  210 ,  212 , and  214  can be any type of filter and may vary in size based on the given frequency in a particular channel. In one example embodiment, the averaging filters  210 ,  212 , and  214  are resistance/capacitance (RC) filters having a desired time constant. For instance, the averaging filters can be 5 μS filters. Each of the averaging filters  210 ,  212 , and  214 , provides respective filtered (e.g. delayed) signals  211 ,  213 , and  215  to an input of a current averaging circuit  216 . The current averaging circuit  216  averages the current received from the output of each channel averaging filter. As one example, the current averaging circuit  216  sums the current valves sensed for each channel, namely I 1 , I 2 , and In to acquire a total summed current and divides the total summed current by the total number of channels, namely n. The quotient resulting from the division of the total number of channels n into the total summed current becomes an output signal IAVG. The output signal IAVG is further illustrated in Equation (A). 
     
       
         
           
             
               
                 
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                   Equation 
                   ⁢ 
                   
                       
                   
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     Also located within the converter IC  202  are differential elements  217 ,  218 , and  220  that receive the IAVG signal from the current averaging circuit  216  at a minus input on each differential element. The differential elements  217 ,  218 , and  220  further receive the output signals  211 ,  213 , and  215  from their respective averaging filters  210 ,  212 , and  214  at a plus input on each differential. Each differential element  217 ,  218 , and  220  produces a respective output signal  222 ,  224 , and  226  being the difference between the current of the respective channel I 1 , I 2 , and In from output signal IAVG. The differential elements  217 ,  218  and  220  multiply a gain factor K by the difference between the phase current and the average current signals to provide corresponding output signals  222 ,  224 , and  226  for scaling the current sharing. The gain factor K may be the same for each channel or different gain factors can be used for different channels. The differential elements  217 ,  218  and  220  provide the resulting output signals  222 ,  224 , and  226  to an inverting input of a respective summer  228 ,  230  and  232  for each channel. The summers  228 ,  230 , and  232  also receive at a positive input a VDAC signal. The summers  228 ,  230  and  232  compare the VDAC signal relative to the summation output signals  222 ,  224 , and  226  (e.g., by subtracting the signals from VDAC) to provide phase control signals  234 ,  236 , and  238 . The phase control signals  234 ,  236  and  238  correspond to reference signals that can be employed to perform modulation for equalizing current in each of the respective phases. 
     In the example of  FIG. 2 , each of the summer output signals  234 ,  236 , and  238  are coupled to a respective constant on-time modulator  240 ,  242 , and  244 , respectively. The modulators  240 ,  242 , and  244  can reside internal to the converter IC  202 . For example, each of the on-time modulators  240 ,  242 , and  244  includes a resistor R, capacitor C, and amplifier  246 . A feedback loop is provided through phase nodes LL 1 , LL 2 , and LLn for each channel. By way of further example, a PWM comparator (not shown) starts the pulse for each phase or channel and provides a voltage Vin that passes through the resistor R to charge capacitor C for each channel according to the RC time constant provided by the resistor and capacitor. When the voltage charge at the capacitor C reaches a voltage equal to the summer output signal  234 ,  236 ,  238 , the pulse is turned off for that particular channel, allowing current sharing to different devices through the amplifier  246 . The amplifier  246  of each modulator  240 ,  242 , and  244  thus generates respective PWM 1 , PWM 2 , and PWMn outputs based on the respective input voltage at the inverting input thereof relative to the respective summer output signals  234 ,  236  and  238 . In addition to providing a current sharing source to various devices and drivers, the outputs PWM 1 , PWM 2 , and PWMn can provide a pulse width modulated signal to phase nodes LL 1 , LL 2 , and LLn for each respective channel. 
       FIG. 3  depicts another example embodiment of a multi-phase current converter system  300 , having dual channels I 1  and I 2 . The system includes a converter IC  302  that contains the analog circuitry configured to perform current balancing according to an aspect of the invention. The converter IC  302  includes corresponding current sensing amplifiers  304  and  306  that receive a signal for each channel, namely CS  1  and CS 2 , respectively, which signal is proportional to phase current. The amplifiers  304  and  306  provide an output  305  and  307  having a value (e.g., an analog voltage) indicative of the phase current for each channel. The output signals  305  and  307  are received on an input side of a respective averaging filter  310  and  312 . The averaging filters  310  and  312  can be any type of filter and may vary in size based on the given frequency of a channel. In one example embodiment, the averaging filters  310  and  312  are implemented as resistance/capacitance (RC) networks having a time constant selected to provide a time averaged indication of the detected phase current. Each of the averaging filters  310  and  312  provides a respective output signal  311  and  313  to a negative input of summation blocks  318  and  317 , respectively located on an opposite channel. The output signals  311  and  313  also are coupled to a positive input to the summation blocks  317  and  318 , respectively on the same channel as the averaging filter. The summation blocks  317  and  318  can be implemented as a differential amplifier having a gain factor (k) configured to perform an averaging of the detected phase currents, which gain can vary depending on the number of channels. The summation blocks  317  and  318  produce an averaged output signal, being a weighted (e.g., multiplied by gain factor K) difference between the phases for each channel, namely output signal  322  for channel I 1  (e.g., corresponding to K*(I 1 −I 2 )) and output signal  324  for channel I 2  (e.g., corresponding to K*(I 2 −I 1 )).The gain factor K can be set according to the number of channels so that the output signals each represents a scaled difference between the average phase current and the individual phase current. That is, each of the summation blocks  317  and  318  define current share amplifiers that provide a scaled output having a value that is proportional to the difference between the current detected for each respective phase and the average current for the multi-phase network. As mentioned above, in this two phase system  300 , the current share amplifiers (summation blocks  317  and  318 ) are configured to also determine the average system phase current. As a result, separate averaging circuitry can be omitted from the design and the system  300  can be manufactured at reduced cost. 
     A first multiplexer  326  receives the output signals  322  and  324  and is controlled by a selection signal to provide one of the output signals according to which of the phase currents is to be modulated during a given part of an operating cycle. 
     The multiplexer  326  provides a selected output signal  328  (corresponding to one of the signals  322  or  324 ) to a negative input of summer  330 . A reference VDAC signal is also provided to positive input of the summer  330 . The summer  330  compares the selected output signal  328  relative to VDAC (e.g., by subtracting the output signal from VDAC) to provide a corresponding output signal  330 . The variations on the output signal  330  are further demonstrated with reference to  FIG. 4 . 
     The difference output signal  330  is provided to a modulator, such as an on-time modulator  340  that is internal to the converter IC  302 . In the example of  FIG. 3 , the on-time modulator  340  includes a resistor R, capacitor C and amplifier  342 . The node between the resistor R and the capacitor C is coupled to the inverting input of the differential amplifier  340 . The difference output signal  330  is provided to a non-inverting input of the differential amplifier  342 . A feedback loop is provided through phase nodes LL 1  and LL 2  for each channel, namely, I 1  and I 2  respectively. As an example, PWM comparator (not shown) starts the pulse for each current phase or channel and provides a voltage Vin that is received by a second multiplexer  327 . The second multiplexer  327  is synchronized with the first multiplexer  326 , such that the Vin signal for the respective channel is selected provided to charge the capacitor through the resistor R of the modulator  340 . When the capacitor C charges to provide a voltage at the inverting input of the amplifier  342  equal to the difference output signal at  330 , the PWM output pulse is turned off for that particular channel, which allows current sharing to different devices for another channel through respective through the amplifier  342  to a PWM output. Additionally, switching circuitry (e.g., a de-multiplexer, not shown) can also be provided at the output of amplifier  342  for routing the PWM output to a driver (High-side and Low-side FETs) for the selected phase. The operation of such de-multiplexer for routing the PWM output signal can be synchronized with the operation of the multiplexers  326  and  327 . In addition to providing a current sharing source to various devices and drivers, the output PWM provides a pulse width to phase nodes LL 1  and LL 2  for each respective channel. 
     It will be appreciated by those skilled in that art that the dual channel implementation of  FIG. 3  affords the advantage over other numbers of phases by eliminating the need for a separate averaging circuit to determine the aggregate average phase current for the system  300 . That is, in the example of  FIG. 3 , the circuitry for determining a system average phase current is integrated into each phase&#39;s current balancing circuitry  317  and  318 . Thus, by eliminating a separate current averaging circuit, the system  300  can be manufactured at a reduced cost relative to other comparable systems. While the example of  FIG. 3  depicts a multiplexed single modulator  340 , it will be understood that separate modulators could be provided for each phase similar to as shown and described with respect to the examples of  FIGS. 1 and 2 . Conversely, the multiplexed modulator approach of  FIG. 3  can also be utilized in the systems of  FIGS. 1 and 2 . 
       FIG. 4  is a timing diagram showing deviation from a nominal pulse width for the current sharing systems of the invention. If the phase current in different channels are equal, namely I 1 =I 2 , then the PWM modulator of the current sharing system terminates when the voltage in the modulator reaches a value equal to VDAC and a normal pulse width is delivered to the system. If the phase current I 1  is less than the phase current I 2 , an offset is subtracted from VDAC, and the pulse width for channel  1  is shortened, thereby reducing the current in the first channel. If the current I 1  is greater than the current I 2 , a longer pulse is produced. Because the increase in pulse width is proportional to the difference between the actual phase current and the ideal current, the system converges smoothly to equilibrium. Because filtering is lighter than conventional current sharing schemes, the settling time is very fast. This speed increase will be advantageous as processor speeds increase. The construct of the above systems further provide rapid dynamic current and output voltage changes while maintaining current balance. 
     In view of the foregoing examples, it will be appreciated that the approach shown and described herein provides a solution of unconditionally stable current sharing loop that can be implemented into any multi-phase converter. Having the small-signal transfer function model of the current-sharing loop provides a high degree of confidence in the current sharing performance. Because the loop can be integrated means that no external pins or components are required, and no user calculations are required to provide the stable current sharing. This invention allows rapid dynamic current and output voltage changes while maintaining current balance. As a result, the approach translates to an inexpensive, small, and easy-to-use solution that affords desirable performance for multi-phase systems. 
     What have been described above are examples of the present invention. It is, of course, not possible to describe every conceivable combination of components or methodologies for purposes of describing the present invention, but one of ordinary skill in the art will recognize that many further combinations and permutations of the present invention are possible. Accordingly, the present invention is intended to embrace all such alterations, modifications, and variations that fall within the spirit and scope of the appended claims.