Patent Publication Number: US-2009240930-A1

Title: Executing An Application On A Parallel Computer

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The field of the invention is data processing, or, more specifically, methods, apparatus, and products for executing an application on a parallel computer. 
     2. Description of Related Art 
     The development of the EDVAC computer system of 1948 is often cited as the beginning of the computer era. Since that time, computer systems have evolved into extremely complicated devices. Today&#39;s computers are much more sophisticated than early systems such as the EDVAC. Computer systems typically include a combination of hardware and software components, application programs, operating systems, processors, buses, memory, input/output devices, and so on. As advances in semiconductor processing and computer architecture push the performance of the computer higher and higher, more sophisticated computer software has evolved to take advantage of the higher performance of the hardware, resulting in computer systems today that are much more powerful than just a few years ago. 
     Parallel computing is an area of computer technology that has experienced advances. Parallel computing is the simultaneous execution of the same task (split up and specially adapted) on multiple processors in order to obtain results faster. Parallel computing is based on the fact that the process of solving a problem usually can be divided into smaller tasks, which may be carried out simultaneously with some coordination. 
     Parallel computers execute parallel algorithms. A parallel algorithm can be split up to be executed a piece at a time on many different processing devices, and then put back together again at the end to get a data processing result. Some algorithms are easy to divide up into pieces. Splitting up the job of checking all of the numbers from one to a hundred thousand to see which are primes could be done, for example, by assigning a subset of the numbers to each available processor, and then putting the list of positive results back together. In this specification, the multiple processing devices that execute the individual pieces of a parallel program are referred to as ‘compute nodes.’ A parallel computer is composed of compute nodes and other processing nodes as well, including, for example, input/output (‘I/O’) nodes, and service nodes. 
     Parallel algorithms are valuable because it is faster to perform some kinds of large computing tasks via a parallel algorithm than it is via a serial (non-parallel) algorithm, because of the way modern processors work. It is far more difficult to construct a computer with a single fast processor than one with many slow processors with the same throughput. There are also certain theoretical limits to the potential speed of serial processors. On the other hand, every parallel algorithm has a serial part and so parallel algorithms have a saturation point. After that point adding more processors does not yield any more throughput but only increases the overhead and cost. 
     Parallel algorithms are designed also to optimize one more resource the data communications requirements among the nodes of a parallel computer. There are two ways parallel processors communicate, shared memory or message passing. Shared memory processing needs additional locking for the data and imposes the overhead of additional processor and bus cycles and also serializes some portion of the algorithm. Message passing processing uses high-speed data communications networks and message buffers, but this communication adds transfer overhead on the data communications networks as well as additional memory need for message buffers and latency in the data communications among nodes. Designs of parallel computers use specially designed data communications links so that the communication overhead will be small but it is the parallel algorithm that decides the volume of the traffic. 
     Many data communications network architectures are used for message passing among nodes in parallel computers. Compute nodes may be organized in a network as a ‘torus’ or ‘mesh,’ for example. Also, compute nodes may be organized in a network as a tree. A torus network connects the nodes in a three-dimensional mesh with wrap around links. Every node is connected to its six neighbors through this torus network, and each node is addressed by its x,y,z coordinate in the mesh. In a tree network, the nodes typically are connected into a binary tree: each node has a parent, and two children (although some nodes may only have zero children or one child, depending on the hardware configuration). In computers that use a torus and a tree network, the two networks typically are implemented independently of one another, with separate routing circuits, separate physical links, and separate message buffers. 
     A torus network generally supports point-to-point communications. A tree network, however, typically only supports communications where data from one compute node migrates through tiers of the tree network to a root compute node or where data is multicast from the root to all of the other compute nodes in the tree network. In such a manner, the tree network lends itself to collective operations such as, for example, reduction operations or broadcast operations. In the current art, however, the tree network does not lend itself to and is typically inefficient for point-to-point operations. Although in general the torus network and the tree network are each optimized for certain communications patterns, those communications patterns may be supported by either network. 
     Many parallel computers consist of compute nodes that each only supports a single thread. Such parallel computers are sufficient for processing a parallel application in which the application consists of instructions that are only executed serially on each compute node using a single thread. To further enhance performance, however, more robust parallel computers include compute nodes that each supports multiple threads using a multi-processor architecture. Using these more robust parallel computers, software engineers have developed parallel applications in which each application consists of segments of instructions that are only executed serially on each node using a single thread and other segments that may be executed in parallel on each node using multiple threads. That is, each compute node utilizes a single processor while executing the serial code segments and spawns threads to the other processors on that node while executing the parallel code segments. The drawback to executing multi-threaded parallel applications on these more robust parallel computers in such a manner is that computing resources are being underutilized when the compute nodes are executing the serial code segments. As mentioned above, when the compute nodes are executing the serial code segments, each compute node is processing only a single thread, and thereby only utilizing a single processor in its multi-processor architecture. 
     SUMMARY OF THE INVENTION 
     Methods, systems, and products are disclosed for executing an application on a parallel computer. The parallel computer includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors capable of operating independently for serial processing among the processors and capable of operating symmetrically for parallel processing among the processors. The application has parallel segments designated for parallel processing and serial segments designated for serial processing. Executing an application on a parallel computer according to the present invention includes: booting up a first subset of the plurality of compute nodes in a serial processing mode; booting up a second subset of the plurality of compute nodes in a parallel processing mode; and executing the application on the plurality of compute nodes, including: migrating the application to the compute nodes booted up in the parallel processing mode upon encountering the parallel segments during execution, and migrating the application to the compute nodes booted up in the serial processing mode upon encountering the serial segments during execution. 
     The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates an exemplary parallel computer for executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 2  sets forth a block diagram of an exemplary compute node useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 3A  illustrates an exemplary Point To Point Adapter useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 3B  illustrates an exemplary Global Combining Network Adapter useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 4  sets forth a line drawing illustrating an exemplary data communications network optimized for point to point operations useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 5  sets forth a line drawing illustrating an exemplary data communications network optimized for collective operations useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. 
         FIG. 6  sets forth a line drawing illustrating exemplary compute nodes of a parallel computer capable of executing an application on the parallel computer according to embodiments of the present invention. 
         FIG. 7  sets forth a flow chart illustrating an exemplary method for executing an application on a parallel computer according to the present invention. 
         FIG. 8  sets forth a line drawing illustrating further exemplary compute nodes of a parallel computer capable of executing an application on the parallel computer according to embodiments of the present invention. 
         FIG. 9  sets forth a flow chart illustrating a further exemplary method for executing an application on a parallel computer according to the present invention. 
         FIG. 10  sets forth a line drawing illustrating further exemplary compute nodes of a parallel computer capable of executing an application on the parallel computer according to embodiments of the present invention. 
         FIG. 11  sets forth a flow chart illustrating a further exemplary method for executing an application on a parallel computer according to the present invention. 
     
    
    
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Exemplary methods, apparatus, and computer program products for executing an application on a parallel computer according to embodiments of the present invention are described with reference to the accompanying drawings, beginning with  FIG. 1 .  FIG. 1  illustrates an exemplary parallel computer for executing an application on a parallel computer according to embodiments of the present invention. The system of  FIG. 1  includes a parallel computer ( 100 ), non-volatile memory for the computer in the form of data storage device ( 118 ), an output device for the computer in the form of printer ( 120 ), and an input/output device for the computer in the form of computer terminal ( 122 ). Parallel computer ( 100 ) in the example of  FIG. 1  includes a plurality of compute nodes ( 102 ). 
     Each compute node ( 102 ) includes a plurality of processors for use in executing an application on the parallel computer ( 100 ) according to embodiments of the present invention. The processors of each compute node ( 102 ) in  FIG. 1  are operatively coupled to computer memory such as, for example, random access memory (‘RAM’). Each compute node ( 102 ) may operate in several distinct modes that affect the relationship among the processors and the memory on that node such as, for example, serial processing mode, parallel processing mode, partitioned parallel processing mode, and hybrid processing mode. The mode in which the compute nodes operate is generally set during the node&#39;s boot processes and does not change until the node reboots. 
     In a serial processing mode, often referred to a ‘virtual node mode,’ the processors of a compute node operate independently of one another, and each processor has access to a partition of the node&#39;s memory that is exclusively dedicated to that processor. For example, if a compute node has four processors and two Gigabytes (GB) of RAM, when operating in serial processing mode, each processor may process a thread independently of the other processors on that node, and each processor may access a portion of that node&#39;s 2 GB of RAM. 
     In a parallel processing mode, often referred to as ‘symmetric multiprocessing mode,’ one of the processors acts as a master, and the remaining processors serve as slaves to the master processor. Each processor has access to the full range of computer memory on the compute node. Continuing with the exemplary node above having four processors and 2 GB of RAM, for example, each slave processor may cooperatively process threads spawned from the master processor, and all of the processors have access to the node&#39;s entire 2 GB of RAM. 
     In a partitioned parallel processing mode, a node&#39;s processors are divided into two or more sets of processors and a portion of the node&#39;s memory is partitioned for each processor set. Each processor set consists of one master processor and one or more additional slave processors that all access the same partition of the node&#39;s memory. The master processor of each set supports a thread for execution and may spawn threads for cooperative execution on each of the slave processors in the processor set. For example, continuing with the exemplary node above having four processors and 2 GB of RAM, the processor may be divided into two processor sets, each set having two processors—a master processor and a slave processor. The master and slave processors in each processor set have access to a portion of the node&#39;s 2 GB of RAM. Typically, the master and slave processor of the first set may have access to the same 1 GB of memory, while the master and slave processor of the second set have access to the remaining 1 GB of memory. 
     In a hybrid processing mode, a node&#39;s processors are divided into two or more sets of processors. At least one set of processors on that node includes processors operating independently for serial processing among the processor in that set. Each processor in that serial processing processor set has access to a portion of the node&#39;s computer memory that is exclusively dedicated to that processor. While the node has at least one serial processing processor set in a hybrid processing mode, at least one set of processors on that compute node include processors that provide parallel processing among the processor in that set. Parallel processing processor set consists of one master processor and one or more additional slave processors that all access the same partition of the node&#39;s memory—a partition distinct from the partitions accessed by processing in the serial processing processor set. The master processor of the parallel processor set supports a thread for execution and may spawn threads for cooperative execution on each of the slave processors in the parallel processing processor set. For example, continuing with the exemplary node above having four processors and 2 GB of RAM, the processor may be divided into one serial processing processor set and one parallel processing processor set—each set having two processors each. The processors in the serial processor set may each support a single thread of execution and have access to different partitions of the node&#39;s memory that are, for example, 512 megabytes (MB) in size. The processors in the parallel processor set may support multiple threads—one thread running on the master processor, which in turn may spawn a thread to run on the slave processor. The processors in such an example may each access the entire partition of remaining node memory that is, for example, 1 GB in size. 
     In the parallel computer ( 100 ) of  FIG. 1 , the compute nodes ( 102 ) are coupled for data communications by several independent data communications networks including a Joint Test Action Group (‘JTAG’) network ( 104 ), a global combining network ( 106 ) which is optimized for collective operations, and a torus network ( 108 ) which is optimized point to point operations. The global combining network ( 106 ) is a data communications network that includes data communications links connected to the compute nodes so as to organize the compute nodes as a tree. Each data communications network is implemented with network links among the compute nodes ( 102 ). The network links provide data communications for parallel operations among the compute nodes of the parallel computer. The links between compute nodes are bi-directional links that are typically implemented using two separate directional data communications paths. 
     In addition, the compute nodes ( 102 ) of parallel computer are organized into at least one operational group ( 132 ) of compute nodes for collective parallel operations on parallel computer ( 100 ). An operational group of compute nodes is the set of compute nodes upon which a collective parallel operation executes. Collective operations are implemented with data communications among the compute nodes of an operational group. Collective operations are those functions that involve all the compute nodes of an operational group. A collective operation is an operation, a message-passing computer program instruction that is executed simultaneously, that is, at approximately the same time, by all the compute nodes in an operational group of compute nodes. Such an operational group may include all the compute nodes in a parallel computer ( 100 ) or a subset all the compute nodes. Collective operations are often built around point to point operations. A collective operation requires that all processes on all compute nodes within an operational group call the same collective operation with matching arguments. A ‘broadcast’ is an example of a collective operation for moving data among compute nodes of an operational group. A ‘reduce’ operation is an example of a collective operation that executes arithmetic or logical functions on data distributed among the compute nodes of an operational group. An operational group may be implemented as, for example, an MPI ‘communicator.’ 
     ‘MPI’ refers to ‘Message Passing Interface,’ a prior art parallel communications library, a module of computer program instructions for data communications on parallel computers. Examples of prior-art parallel communications libraries that may be improved for use with systems according to embodiments of the present invention include MPI and the ‘Parallel Virtual Machine’ (‘PVM’) library. PVM was developed by the University of Tennessee, The Oak Ridge National Laboratory, and Emory University. MPI is promulgated by the MPI Forum, an open group with representatives from many organizations that define and maintain the MPI standard. MPI at the time of this writing is a de facto standard for communication among compute nodes running a parallel program on a distributed memory parallel computer. This specification sometimes uses MPI terminology for ease of explanation, although the use of MPI as such is not a requirement or limitation of the present invention. 
     Some collective operations have a single originating or receiving process running on a particular compute node in an operational group. For example, in a ‘broadcast’ collective operation, the process on the compute node that distributes the data to all the other compute nodes is an originating process. In a ‘gather’ operation, for example, the process on the compute node that received all the data from the other compute nodes is a receiving process. The compute node on which such an originating or receiving process runs is typically referred to as a logical root. 
     Most collective operations are variations or combinations of four basic operations: broadcast, gather, scatter, and reduce. The interfaces for these collective operations are defined in the MPI standards promulgated by the MPI Forum. Algorithms for executing collective operations, however, are not defined in the MPI standards. In a broadcast operation, all processes specify the same root process, whose buffer contents will be sent. Processes other than the root specify receive buffers. After the operation, all buffers contain the message from the root process. 
     In a scatter operation, the logical root divides data on the root into segments and distributes a different segment to each compute node in the operational group. In scatter operation, all processes typically specify the same receive count. The send arguments are only significant to the root process, whose buffer actually contains sendcount * N elements of a given data type, where N is the number of processes in the given group of compute nodes. The send buffer is divided and dispersed to all processes (including the process on the logical root). Each compute node is assigned a sequential identifier termed a ‘rank.’ After the operation, the root has sent sendcount data elements to each process in increasing rank order. Rank  0  receives the first sendcount data elements from the send buffer. Rank  1  receives the second sendcount data elements from the send buffer, and so on. 
     A gather operation is a many-to-one collective operation that is a complete reverse of the description of the scatter operation. That is, a gather is a many-to-one collective operation in which elements of a datatype are gathered from the various processes running on the ranked compute nodes into a receive buffer in a root node. 
     A reduce operation is also a many-to-one collective operation that includes an arithmetic or logical function performed on two data elements. All processes specify the same ‘count’ and the same arithmetic or logical function. After the reduction, all processes have sent count data elements from computer node send buffers to the root process. In a reduction operation, data elements from corresponding send buffer locations are combined pair-wise by arithmetic or logical operations to yield a single corresponding element in the root process&#39;s receive buffer. Application specific reduction operations can be defined at runtime. Parallel communications libraries may support predefined operations. MPI, for example, provides the following pre-defined reduction operations: 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 MPI_MAX 
                 maximum 
               
               
                   
                 MPI_MIN 
                 minimum 
               
               
                   
                 MPI_SUM 
                 sum 
               
               
                   
                 MPI_PROD 
                 product 
               
               
                   
                 MPI_LAND 
                 logical and 
               
               
                   
                 MPI_BAND 
                 bitwise and 
               
               
                   
                 MPI_LOR 
                 logical or 
               
               
                   
                 MPI_BOR 
                 bitwise or 
               
               
                   
                 MPI_LXOR 
                 logical exclusive or 
               
               
                   
                 MPI_BXOR 
                 bitwise exclusive or 
               
               
                   
                   
               
            
           
         
       
     
     As mentioned above, most collective operation communications patterns build off of these basic collective operations. One such communications pattern is a gossiping communications pattern in which one set of compute nodes communicates with another set of compute nodes. The two sets of nodes participating in the gossip communications pattern could be the same or different. Examples of gossiping communications patterns implemented using MPI may include an all-to-all operation, an all-to-allv operation, an allgather operation, an allgatherv operation, and so on. 
     In addition to compute nodes, the parallel computer ( 100 ) includes input/output (‘I/O’) nodes ( 110 ,  114 ) coupled to compute nodes ( 102 ) through the global combining network ( 106 ). The I/O nodes ( 110 ,  114 ) provide I/O services between compute nodes ( 102 ) and I/O devices ( 118 ,  120 ,  122 ). I/O nodes ( 110 ,  114 ) are connected for data communications I/O devices ( 118 ,  120 ,  122 ) through local area network (‘LAN’) ( 130 ) implemented using high-speed Ethernet. The parallel computer ( 100 ) also includes a service node ( 116 ) coupled to the compute nodes through one of the networks ( 104 ). Service node ( 116 ) provides services common to pluralities of compute nodes, administering the configuration of compute nodes, loading programs into the compute nodes, starting program execution on the compute nodes, retrieving results of program operations on the computer nodes, and so on. Service node ( 116 ) runs a service application ( 124 ) and communicates with users ( 128 ) through a service application interface ( 126 ) that runs on computer terminal ( 122 ). 
     As described in more detail below in this specification, the parallel computer ( 100 ) of  FIG. 1  operates generally for executing an application on a parallel computer according to embodiments of the present invention. The application is computer software having parallel segments designated for parallel processing on each compute node and serial segments designated for serial processing on each compute node. The parallel computer ( 100 ) of  FIG. 1  operates generally for executing an application on a parallel computer according to embodiments of the present invention by: booting up a first subset of the plurality of compute nodes ( 102 ) in a serial processing mode; booting up a second subset of the plurality of compute nodes ( 102 ) in a parallel processing mode; and executing the application on the plurality of compute nodes ( 102 ), including: migrating the application to the compute nodes ( 102 ) booted up in a parallel processing mode upon encountering the parallel segments during execution, and migrating the application to the compute nodes ( 102 ) booted up in the serial processing mode upon encountering the serial segments during execution. 
     Readers will note that the term ‘booting’ as applied to compute nodes generally refers to the process of initializing compute node components to prepare the compute node for executing application layer software. Such booting may occur when power is first applied to each compute node, when power is cycled to each compute node, or when certain reset values are written to component registers. The process of booting a compute node may include loading system layer software such as an operating system to provide an interface through which application layer software may access the node&#39;s hardware. Such system layer software however may be quite lightweight by comparison with system layer software of general purpose computers. That is, such system layer software may be a pared down version as it were of system layer software developed for general purpose computers. 
     The arrangement of nodes, networks, and I/O devices making up the exemplary system illustrated in  FIG. 1  are for explanation only, not for limitation of the present invention. Data processing systems capable of executing an application on a parallel computer according to embodiments of the present invention may include additional nodes, networks, devices, and architectures, not shown in  FIG. 1 , as will occur to those of skill in the art. Although the parallel computer ( 100 ) in the example of  FIG. 1  includes sixteen compute nodes ( 102 ), readers will note that parallel computers capable of determining when a set of compute nodes participating in a barrier operation are ready to exit the barrier operation according to embodiments of the present invention may include any number of compute nodes. In addition to Ethernet and JTAG, networks in such data processing systems may support many data communications protocols including for example TCP (Transmission Control Protocol), IP (Internet Protocol), and others as will occur to those of skill in the art. Various embodiments of the present invention may be implemented on a variety of hardware platforms in addition to those illustrated in  FIG. 1 . 
     Executing an application on a parallel computer according to embodiments of the present invention may be generally implemented on a parallel computer that includes a plurality of compute nodes. In fact, such computers may include thousands of such compute nodes. Each compute node is in turn itself a kind of computer composed of a plurality of computer processors (or processing cores), its own computer memory, and its own input/output adapters. For further explanation, therefore,  FIG. 2  sets forth a block diagram of an exemplary compute node useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. The compute node ( 152 ) of  FIG. 2  includes a plurality of processors ( 164 ) as well as random access memory (‘RAM’) ( 156 ). The processors ( 164 ) are connected to RAM ( 156 ) through a high-speed memory bus ( 154 ) and through a bus adapter ( 194 ) and an extension bus ( 168 ) to other components of the compute node ( 152 ). 
     Stored in RAM ( 156 ) is an application program ( 158 ), a module of computer program instructions that carries out parallel, user-level data processing using parallel algorithms. The application ( 158 ) of  FIG. 2  has both parallel segments designated for parallel processing on each compute node and serial segments designated for serial processing on each compute node. The serial segments are portions of the application ( 158 ) that include computer program instructions for execution serially in a single thread on the compute node. The parallel segments are portions of the application ( 158 ) that include computer program instructions for execution in parallel on the compute node using multiple threads—typically one thread per processor ( 164 ). 
     Also stored in RAM ( 156 ) is a messaging module ( 160 ), a library of computer program instructions that carry out parallel communications among compute nodes, including point to point operations as well as collective operations. Application program ( 158 ) executes collective operations by calling software routines in the messaging module ( 160 ). A library of parallel communications routines may be developed from scratch for use in systems according to embodiments of the present invention, using a traditional programming language such as the C programming language, and using traditional programming methods to write parallel communications routines that send and receive data among nodes on two independent data communications networks. Alternatively, existing prior art libraries may be improved to operate according to embodiments of the present invention. Examples of prior-art parallel communications libraries include the ‘Message Passing Interface’ (‘MPI’) library and the ‘Parallel Virtual Machine’ (‘PVM’) library. 
     Also stored in RAM ( 156 ) is a multi-processing module ( 161 ), a library of computer program instructions that carry out shared memory multi-processing among the plurality of processors ( 164 ) on the compute node ( 152 ). Application program ( 158 ) executes shared memory multi-processing operations using the functionality provided by the multi-processing module ( 161 ). The multi-processing module ( 161 ) may implement functionality specified in various shared memory multi-processing platforms such as, for example, the OpenMP™ shared memory multi-processing platform. Although illustrated in  FIG. 2  as a separate component, readers will recognize that the multi-processing module ( 161 ) of  FIG. 2  may be implemented as a component of an operating system. 
     Also stored in RAM ( 156 ) is an operating system ( 162 ), a module of computer program instructions and routines for an application program&#39;s access to other resources of the compute node. The operating system ( 162 ) may be quite lightweight by comparison with operating systems of general purpose computers, a pared down version as it were, or an operating system developed specifically for operations on a particular parallel computer. Operating systems that may usefully be improved, simplified, for use in a compute node include UNIX™, Linux™, Microsoft XP™, AIX™, IBM&#39;s i5/OS™, and others as will occur to those of skill in the art. 
     Although the operating system ( 162 ) generally controls execution of the application ( 158 ) in the example of  FIG. 2 , the operating system ( 162 ) also includes a migration manager ( 200 ), which is a set of computer program instructions for migrating the application ( 158 ) from one compute node to another according to embodiments of the present invention. The migration manager ( 200 ) of  FIG. 2  generally operates according to embodiments of the present invention by: migrating the application ( 158 ) to the compute nodes booted up in a parallel processing mode upon encountering the parallel segments during execution and migrating the application ( 158 ) to the compute nodes booted up in the serial processing mode upon encountering the serial segments during execution. The migration manager ( 200 ) of  FIG. 2  may also operate according to embodiments of the present invention by: migrating the application ( 158 ) to the compute nodes booted up in a partitioned parallel processing mode upon encountering the parallel segments during execution or migrating the application ( 158 ) to the compute nodes booted up in a hybrid processing mode upon encountering the parallel segments during execution. The mode in which the compute node boots up is generally determined by values set in registers for the processors ( 164 ), the bus adapter ( 194 ), and the RAM ( 168 ). A system administrator may set these values remotely through a JTAG network or in other ways as will occur to those of skill in the art. 
     The exemplary compute node ( 152 ) of  FIG. 2  includes several communications adapters ( 172 ,  176 ,  180 ,  188 ) for implementing data communications with other nodes of a parallel computer. Such data communications may be carried out serially through RS-232 connections, through external buses such as Universal Serial Bus (‘USB’), through data communications networks such as IP networks, and in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a network. Examples of communications adapters useful in systems for executing an application on a parallel computer according to embodiments of the present invention include modems for wired communications, Ethernet (IEEE 802.3) adapters for wired network communications, and 802.11b adapters for wireless network communications. 
     The data communications adapters in the example of  FIG. 2  include a Gigabit Ethernet adapter ( 172 ) that couples example compute node ( 152 ) for data communications to a Gigabit Ethernet ( 174 ). Gigabit Ethernet is a network transmission standard, defined in the IEEE 802.3 standard, that provides a data rate of 1 billion bits per second (one gigabit). Gigabit Ethernet is a variant of Ethernet that operates over multimode fiber optic cable, single mode fiber optic cable, or unshielded twisted pair. 
     The data communications adapters in the example of  FIG. 2  includes a JTAG Slave circuit ( 176 ) that couples example compute node ( 152 ) for data communications to a JTAG Master circuit ( 178 ). JTAG is the usual name used for the IEEE 1149.1 standard entitled Standard Test Access Port and Boundary-Scan Architecture for test access ports used for testing printed circuit boards using boundary scan. JTAG is so widely adapted that, at this time, boundary scan is more or less synonymous with JTAG. JTAG is used not only for printed circuit boards, but also for conducting boundary scans of integrated circuits, and is also useful as a mechanism for debugging embedded systems, providing a convenient “back door” into the system. The example compute node of  FIG. 2  may be all three of these: It typically includes one or more integrated circuits installed on a printed circuit board and may be implemented as an embedded system having its own processor, its own memory, and its own I/O capability. JTAG boundary scans through JTAG Slave ( 176 ) may efficiently configure processor registers and memory in compute node ( 152 ) for use in executing an application on a parallel computer according to embodiments of the present invention. 
     The data communications adapters in the example of  FIG. 2  includes a Point To Point Adapter ( 180 ) that couples example compute node ( 152 ) for data communications to a network ( 108 ) that is optimal for point to point message passing operations such as, for example, a network configured as a three-dimensional torus or mesh. Point To Point Adapter ( 180 ) provides data communications in six directions on three communications axes, x, y, and z, through six bidirectional links: +x ( 181 ), −x ( 182 ), +y ( 183 ), −y ( 184 ), +z ( 185 ), and −z ( 186 ). 
     The data communications adapters in the example of  FIG. 2  includes a Global Combining Network Adapter ( 188 ) that couples example compute node ( 152 ) for data communications to a network ( 106 ) that is optimal for collective message passing operations on a global combining network configured, for example, as a binary tree. The Global Combining Network Adapter ( 188 ) provides data communications through three bidirectional links: two to children nodes ( 190 ) and one to a parent node ( 192 ). 
     Example compute node ( 152 ) includes two arithmetic logic units (‘ALUs’). ALU ( 166 ) is a component of each processing core ( 164 ), and a separate ALU ( 170 ) is dedicated to the exclusive use of Global Combining Network Adapter ( 188 ) for use in performing the arithmetic and logical functions of reduction operations. Computer program instructions of a reduction routine in parallel communications library ( 160 ) may latch an instruction for an arithmetic or logical function into instruction register ( 169 ). When the arithmetic or logical function of a reduction operation is a ‘sum’ or a ‘logical or,’ for example, Global Combining Network Adapter ( 188 ) may execute the arithmetic or logical operation by use of ALU ( 166 ) in processor ( 164 ) or, typically much faster, by use dedicated ALU ( 170 ). 
     The example compute node ( 152 ) of  FIG. 2  includes a direct memory access (‘DMA’) controller ( 195 ), which is computer hardware for direct memory access and a DMA engine ( 197 ), which is computer software for direct memory access. In the example of  FIG. 2 , the DMA engine ( 197 ) is configured in computer memory of the DMA controller ( 195 ). Direct memory access includes reading and writing to memory of compute nodes with reduced operational burden on the central processing units ( 164 ). A DMA transfer essentially copies a block of memory from one location to another, typically from one compute node to another. While the CPU may initiate the DMA transfer, the CPU does not execute it. 
     For further explanation,  FIG. 3A  illustrates an exemplary Point To Point Adapter ( 180 ) useful in a parallel computer capable of executing an application on a parallel computer according to embodiments of the present invention. Point To Point Adapter ( 180 ) is designed for use in a data communications network optimized for point to point operations, a network that organizes compute nodes in a three-dimensional torus or mesh. Point To Point Adapter ( 180 ) in the example of  FIG. 3A  provides data communication along an x-axis through four unidirectional data communications links, to and from the next node in the −x direction ( 182 ) and to and from the next node in the +x direction ( 181 ). Point To Point Adapter ( 180 ) also provides data communication along a y-axis through four unidirectional data communications links, to and from the next node in the −y direction ( 184 ) and to and from the next node in the +y direction ( 183 ). Point To Point Adapter ( 180 ) in  FIG. 3A  also provides data communication along a z-axis through four unidirectional data communications links, to and from the next node in the −z direction ( 186 ) and to and from the next node in the +z direction ( 185 ). 
     For further explanation,  FIG. 3B  illustrates an exemplary Global Combining Network Adapter ( 188 ) useful in a parallel computer capable of broadcasting collective operation contributions throughout the parallel computer according to embodiments of the present invention. Global Combining Network Adapter ( 188 ) is designed for use in a network optimized for collective operations, a network that organizes compute nodes of a parallel computer in a binary tree. Global Combining Network Adapter ( 188 ) in the example of  FIG. 3B  provides data communication to and from two children nodes ( 190 ) through two links. Each link to each child node ( 190 ) is formed from two unidirectional data communications paths. Global Combining Network Adapter ( 188 ) also provides data communication to and from a parent node ( 192 ) through a link formed from two unidirectional data communications paths. 
     For further explanation,  FIG. 4  sets forth a line drawing illustrating an exemplary data communications network ( 108 ) optimized for point to point operations useful in a parallel computer capable of executing an application on a parallel computer in accordance with embodiments of the present invention. In the example of  FIG. 4 , dots represent compute nodes ( 102 ) of a parallel computer, and the dotted lines between the dots represent data communications links ( 103 ) between compute nodes. The data communications links are implemented with point to point data communications adapters similar to the one illustrated for example in  FIG. 3A , with data communications links on three axes, x, y, and z, and to and from in six directions +x ( 181 ), −x ( 182 ), +y ( 183 ), −y ( 184 ), +z ( 185 ), and −z ( 186 ). The links and compute nodes are organized by this data communications network optimized for point to point operations into a three dimensional mesh ( 105 ). The mesh ( 105 ) has wrap-around links on each axis that connect the outermost compute nodes in the mesh ( 105 ) on opposite sides of the mesh ( 105 ). These wrap-around links form part of a torus ( 107 ). Each compute node in the torus has a location in the torus that is uniquely specified by a set of x, y, z coordinates. Readers will note that the wrap-around links in the y and z directions have been omitted for clarity, but are configured in a similar manner to the wrap-around link illustrated in the x direction. For clarity of explanation, the data communications network of  FIG. 4  is illustrated with only 27 compute nodes, but readers will recognize that a data communications network optimized for point to point operations for use in executing an application on a parallel computer in accordance with embodiments of the present invention may contain only a few compute nodes or may contain thousands of compute nodes. 
     For further explanation,  FIG. 5  sets forth a line drawing illustrating an exemplary data communications network ( 106 ) optimized for collective operations useful in a parallel computer capable of executing an application on a parallel computer in accordance with embodiments of the present invention. The example data communications network of  FIG. 5  includes data communications links connected to the compute nodes so as to organize the compute nodes as a tree. In the example of  FIG. 5 , dots represent compute nodes ( 102 ) of a parallel computer, and the dotted lines ( 103 ) between the dots represent data communications links between compute nodes. The data communications links are implemented with global combining network adapters similar to the one illustrated for example in  FIG. 3B , with each node typically providing data communications to and from two children nodes and data communications to and from a parent node, with some exceptions. Nodes in a binary tree ( 106 ) may be characterized as a physical root node ( 202 ), branch nodes ( 204 ), and leaf nodes ( 206 ). The root node ( 202 ) has two children but no parent. The leaf nodes ( 206 ) each has a parent, but leaf nodes have no children. The branch nodes ( 204 ) each has both a parent and two children. The links and compute nodes are thereby organized by this data communications network optimized for collective operations into a binary tree ( 106 ). For clarity of explanation, the data communications network of  FIG. 5  is illustrated with only 31 compute nodes, but readers will recognize that a data communications network optimized for collective operations for use in a parallel computer for executing an application on a parallel computer in accordance with embodiments of the present invention may contain only a few compute nodes or may contain thousands of compute nodes. 
     In the example of  FIG. 5 , each node in the tree is assigned a unit identifier referred to as a ‘rank’ ( 250 ). A node&#39;s rank uniquely identifies the node&#39;s location in the tree network for use in both point to point and collective operations in the tree network. The ranks in this example are assigned as integers beginning with 0 assigned to the root node ( 202 ), 1 assigned to the first node in the second layer of the tree, 2 assigned to the second node in the second layer of the tree, 3 assigned to the first node in the third layer of the tree, 4 assigned to the second node in the third layer of the tree, and so on. For ease of illustration, only the ranks of the first three layers of the tree are shown here, but all compute nodes in the tree network are assigned a unique rank. For further explanation,  FIG. 6  sets forth a line drawing illustrating exemplary compute nodes of a parallel computer ( 100 ) capable of executing an application on the parallel computer according to embodiments of the present invention. The parallel computer ( 100 ) of  FIG. 6  includes sixteen compute nodes labeled  0 - 15  and connected together through a data communications network. Each compute node  0 - 15  has four processors, or processing cores, labeled P 0 , P 1 , P 2 , and P 3 . The processors of each compute node  0 - 15  are capable of operating independently for serial processing among the processors P 0 -P 3  and capable of operating symmetrically for parallel processing among the processors P 0 -P 3 . In the example of  FIG. 6 , a service node (not shown) boots up a first subset of nodes that includes nodes  0 - 3  in a serial processing mode ( 610 ). The service node (not shown) also boots up a second subset of nodes that includes nodes  4 - 15  in a parallel processing mode ( 612 ). 
     In the example of  FIG. 6 , the parallel computer ( 100 ) executes an application ( 158 ) on the computer&#39;s compute nodes. The application ( 158 ) of  FIG. 6  has both a parallel segment ( 604 ) designated for parallel processing and serial segments ( 602 ,  606 ) designated for serial processing. The serial segments ( 602 ,  606 ) include computer program instructions for execution serially in a single thread, while the parallel segment ( 604 ) includes computer program instructions for execution among multiple threads in parallel. In the example of  FIG. 6 , the application ( 158 ) distinguishes the serial segments ( 602 ,  606 ) from the parallel segment ( 604 ) using the directive ‘#pragma omp parallel.’ Readers will note that such an exemplary directive is for explanation only and not for limitation. In fact, the serial segments ( 602 ,  606 ) may be distinguished from the parallel segment ( 604 ) in many other ways as will occur to those of skill in the art such as, for example, operation codes, historical execution information, an application profile, and so on. 
     For discussion purposes with respect to  FIG. 6 , let us consider that an application developer or a system administrator has decided that twelve instances of the application ( 158 ) will be executed on the parallel computer ( 100 ). That is, twelve instances of the application ( 158 ) will be processed concurrently using twelve processors of the parallel computer ( 100 ). Accordingly, the serial segments ( 602 ,  606 ) of the application ( 158 ) will be executed using a minimum of twelve threads. That is, during serial segments, the parallel computer ( 100 ) will process twelve instances of the application ( 158 ), each instance utilizing a single thread of execution. Additional threads, however, may be utilized during parallel segments of the application ( 158 ) as each of those twelve initial threads spawn threads for enhanced performance during those parallel segments. From the above description, readers will note that during serial segments of the application a certain level of parallel processing is being performed, but during the parallel segments of the application where additional threads are spawned, an even greater level of parallel processing may be utilized to enhance performance. 
     Because the application ( 158 ) begins with a serial segment ( 602 ), a service node (not shown) initially configures twelve instances of the application ( 158 ) on twelve processors across three compute nodes booted up in serial processing mode ( 610 ). Specifically, the service node configures the application ( 158 ) on each processor P 0 -P 3  of compute nodes  0 - 2  as indicated by the shading of each of those processors. Because each instance of the application ( 158 ) only uses one thread during the serial segments ( 602 ,  606 ), the application ( 158 ) only uses twelve processing cores for execution, those twelve processing cores processing the twelve instances independently of one another. Readers will note that because all processors P 0 -P 3  on each compute node  0 - 2  are utilized for processing the serial segment ( 602 ), the processing resources of each compute node  0 - 2  are not squandered. 
     While all of the processors P 0 -P 3  of each compute node  0 - 2  are being utilized for execution of the application ( 158 ), no additional processors are available on nodes  0 - 2  to process threads spawned when a parallel segment ( 604 ) of the application ( 158 ) is encountered. Upon encountering the parallel segment ( 604 ) during execution, therefore the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in a parallel processing mode ( 612 ) according to embodiments of the present invention. Specifically in the example of  FIG. 6 , the following migration occurs: the application instance on P 0  of node  0  is migrated to P 0  of node  4 ; the application instance on P 1  of node  0  is migrated to P 0  of node  5 ; the application instance on P 2  of node  0  is migrated to P 0  of node  6 ; the application instance on P 3  of node  0  is migrated to P 0  of node  7 ; the application instance on P 0  of node  1  is migrated to P 0  of node  8 ; the application instance on P 1  of node  1  is migrated to P 0  of node  9 ; the application instance on P 2  of node  1  is migrated to P 0  of node  10 ; the application instance on P 3  of node  1  is migrated to P 0  of node  11 ; the application instance on P 0  of node  2  is migrated to P 0  of node  12 ; the application instance on P 1  of node  2  is migrated to P 0  of node  13 ; the application instance on P 2  of node  2  is migrated to P 0  of node  14 ; and the application instance on P 3  of node  2  is migrated to P 0  of node  15 . In such a manner, the twelve instances of application ( 158 ) execute on P 0  of nodes  4 - 15  as indicated by the shading of PO in nodes  4 - 15 . Because nodes  4 - 15  are booted in parallel processing mode ( 612 ), P 0  serves as a master processor and the remaining processors P 1 - 3  serve as slave processors to P 0 . During execution of the parallel segment ( 604 ) of  FIG. 6 , therefore, each application instance on PO of nodes  4 - 15  may spawn threads to processors P 1 - 3  of each node to aid in processing the parallel segment ( 604 ) as represented in  FIG. 6  using arrows from P 0  to P 1 - 3  in nodes  4 - 15 . 
     While all of the processors P 0 - 3  of each compute node  4 - 15  are being utilized for execution of the application ( 158 ), none of the processors are underutilized because each processor executes either the main thread of an instance of the application ( 158 ) or a thread spawned from the main thread. Executing the serial segments ( 602 ,  606 ) of the application ( 158 ) on compute node  4 - 15 , however, would result in three processors P 1 - 3  not being utilized. Upon encountering the serial segments ( 602 ,  606 ) during execution of the application ( 158 ) in the example of  FIG. 6 , therefore, the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in the serial processing mode ( 610 ). 
     For further explanation,  FIG. 7  sets forth a flow chart illustrating an exemplary method for executing an application on a parallel computer according to the present invention. The parallel computer described with reference to  FIG. 7  includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors capable of operating independently for serial processing among the processors and capable of operating symmetrically for parallel processing among the processors. The application ( 158 ) of  FIG. 7  has parallel segments ( 704 ) designated for parallel processing and serial segments ( 702 ) designated for serial processing. 
     The method of  FIG. 7  includes profiling ( 700 ) the application ( 158 ) prior to execution to identify the serial segments ( 702 ) and the parallel segments ( 704 ). Profiling ( 700 ) the application ( 158 ) according to the method of  FIG. 7  may be carried out by a service node for the parallel computer or one or more compute nodes. The application profile ( 706 ) of  FIG. 7  is a data structure that specifies the serial segments ( 702 ) and the parallel segments ( 704 ) in the application&#39;s execution sequence. The application profile ( 706 ) may specify the serial segments ( 702 ) and the parallel segments ( 704 ) using processor instructions counter values that denote the beginning and the end of the serial segments ( 702 ) and the parallel segments ( 704 ). Readers will note, however, that such an implementation of an exemplary application profile ( 706 ) is for explanation only and not for limitation. Other implementations of an application profile as will occur to those of skill in the art may also be useful in executing an application on a parallel computer according to embodiments of the present invention. 
     Profiling ( 700 ) the application ( 158 ) prior to execution to identify the serial segments ( 702 ) and the parallel segments ( 704 ) according to the method of  FIG. 7  may be carried out by parsing the application ( 158 ) for computer program instructions that specify using multiple threads to execute a particular section of the application ( 158 ). For example, a OpenMP™ directive ‘#pragma omp parallel { . . . }’ specifies that all of the instructions in the curly braces may be executed in parallel using multiple threads that shared the same memory. For another example, consider the UNIX instruction ‘thr_create( )’ that invokes a function to create a thread that execute concurrently with the thread calling the function. 
     The method of  FIG. 7  also includes booting up ( 708 ) a first subset ( 710 ) of the plurality of compute nodes in a serial processing mode. Booting up ( 708 ) a first subset ( 710 ) of the plurality of compute nodes in a serial processing mode according to the method of  FIG. 7  may be carried out by setting register values in processors, memory, or bus circuitry of each compute node in the first subset ( 710 ) to instruct the node to operate in a serial processing mode. The number of nodes included in the first subset ( 710 ) may be determined by dividing the number of instances of the application ( 158 ) that the application developer or system administrator desires to run concurrently on the parallel computer by the number of processors on each compute node. For example, if an application developer or a system administrator desires to have the parallel computer execute sixteen instances of the application ( 158 ) concurrently and each compute node has four processors, then the first subset ( 710 ) of nodes should include at least four compute nodes. 
     The method of  FIG. 7  also includes booting up ( 712 ) a second subset ( 714 ) of the plurality of compute nodes in a parallel processing mode. Booting up ( 712 ) a second subset ( 714 ) of the plurality of compute nodes in a parallel processing mode according to the method of  FIG. 7  may be carried out by setting register values in processors, memory, or bus circuitry of each compute node in the second subset ( 714 ) to instruct the node to operate in a parallel processing mode. The number of nodes included in the second subset ( 714 ) may be determined to be the number of instances of the application ( 158 ) that the application developer or system administrator desires to run concurrently on the parallel computer by the number of processors on each compute node. For example, if an application developer or a system administrator desire to have the parallel computer execute sixteen instances of the application ( 158 ) concurrently, then the second subset ( 714 ) of nodes may include at least sixteen compute nodes. 
     The method of  FIG. 7  includes executing ( 716 ) the application ( 158 ) on the plurality of compute nodes. Executing ( 716 ) the application ( 158 ) on the plurality of compute nodes according to the method of  FIG. 7  includes migrating ( 718 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode upon encountering the parallel segments ( 704 ) during execution and migrating ( 722 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode upon encountering the serial segments ( 702 ) during execution. 
     Migrating ( 718 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode upon encountering the parallel segments ( 704 ) during execution according to the method of  FIG. 7  includes migrating ( 720 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode in dependence upon the profile ( 706 ) of the application ( 158 ). Migrating ( 720 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode in dependence upon the profile ( 706 ) of the application ( 158 ) according to the method of  FIG. 7  may be carried out by identifying that a parallel segment ( 704 ) is large enough to warrant migration using the size of the parallel segment ( 704 ) specified in the application profile ( 706 ) and some predefined threshold, selecting compute nodes in the second subset ( 714 ) for processing each instance of the application ( 158 ), and transferring each instance of the application ( 158 ) to the selected node in the second subset ( 714 ). The data transferred may include, for example, all data corresponding to each instance of the application ( 158 ) such as register values, data structures in memory, program instructions, and so on. 
     Migrating ( 722 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode upon encountering the serial segments ( 702 ) during execution according to the method of  FIG. 7  includes migrating ( 724 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode in dependence upon the profile ( 706 ) of the application ( 158 ). Migrating ( 724 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode in dependence upon the profile ( 706 ) of the application ( 158 ) according to the method of  FIG. 7  may be carried out by identifying that a serial segment ( 702 ) is large enough to warrant migration using the size of the serial segment ( 702 ) specified in the application profile ( 706 ) and some predefined threshold, selecting compute nodes in the first subset ( 712 ) for processing each instance of the application ( 158 ), and transferring each instance of the application ( 158 ) to the selected node in the first subset ( 712 ). Readers will note that as parallel and serial segments alternate during the execution sequence of the application ( 158 ) of  FIG. 7 , the parallel computer migrates the application ( 158 ) back and forth between the first subset ( 710 ) and the second subset ( 714 ) to maximize the use of the parallel computer&#39;s processing resources. 
     Readers will note that the migrations described above with reference to  FIG. 7  are based upon an application profile. Using an application profile to effect such migrations from nodes booted in one mode to another mode are for explanation only and not for limitation. In some other embodiments, these migrations may occur based on historical performance data or real-time performance monitoring. For example, historical or real-time performance data may indicate that certain segments of the application experiences poor performance typically because those segments could be enhanced by executing those segments with multiple threads. As such, the parallel computer may migrate the application upon encountering those segments to compute nodes booted up in a parallel processing mode if the application is being run on node booted up in a serial processing mode. 
     The explanation above with reference to  FIG. 7  describes booting up compute nodes in the parallel computer in both a serial processing mode and a parallel processing mode and migrating the application between the nodes booted up in the serial processing mode and the parallel processing mode. In some other embodiments, some of the compute nodes may be booted up in a partitioned parallel processing mode so that each compute node may provide processing for the parallel segments of more than one application instance. For further explanation, consider  FIG. 8  that sets forth a line drawing illustrating further exemplary compute nodes of a parallel computer capable of executing an application on the parallel computer according to embodiments of the present invention. 
     The parallel computer ( 100 ) of  FIG. 8  includes twelve compute nodes labeled  0 - 11  and connected together through a data communications network. Each compute node  0 - 11  has four processors, or processing cores, labeled P 0 , P 1 , P 2 , and P 3 . The processors of each compute node  0 - 11  are capable of operating independently for serial processing among the processors P 0 -P 3  and capable of operating symmetrically for parallel processing among the processors P 0 -P 3 . In addition, each of the compute nodes  0 - 11  are capable of being booted up in a partitioned parallel processing mode that allows two or more sets of processors on that compute node to independently provide parallel processing among the processors in each set. In the example of  FIG. 8 , a service node (not shown) boots up a first subset of nodes that includes nodes  0 - 3  in a serial processing mode ( 610 ). The service node also boots up a second subset of nodes that includes nodes  4 - 7  in a parallel processing mode ( 612 ). Moreover, the service node boots up a third subset of nodes that includes nodes  8 - 11  in a partitioned parallel processing mode ( 800 ). 
     As mentioned above, in a partitioned parallel processing mode, a node&#39;s processors are dividing into two or more sets of processors and a portion of the node&#39;s memory is partitioned for each processor set. Each processor set consists of one master processor and one or more additional slave processors that all access the same partition of the node&#39;s memory. The master processor of each set supports a thread for execution and may spawn threads for cooperative execution on each of the slave processors in the processor set. For example, consider node  10  in the example of  FIG. 8 . Compute node  10  includes two processor sets ( 802 ) that each have one master processor and one slave processor. The memory for compute node  10  is split between each processor set ( 802 ). 
     In the example of  FIG. 8 , the parallel computer ( 100 ) executes an application ( 158 ) on the computer&#39;s compute nodes. The application ( 158 ) of  FIG. 8  has both a parallel segment ( 604 ) designated for parallel processing and serial segments ( 602 ,  606 ) designated for serial processing. The serial segments ( 602 ,  606 ) include computer program instructions for execution serially in a single thread, while the parallel segment ( 604 ) includes computer program instructions for execution among multiple threads in parallel. In the example of  FIG. 8 , the application ( 158 ) distinguishes the serial segments ( 602 ,  606 ) from the parallel segment ( 604 ) using the directive ‘#pragma omp parallel.’ Readers will note that such an exemplary directive is for explanation only and not for limitation. In fact, the serial segments ( 602 ,  606 ) may be distinguished from the parallel segment ( 604 ) in many other ways as will occur to those of skill in the art such as, for example, operation codes, historical execution information, an application profile, and so on. 
     For discussion purposes with respect to  FIG. 8 , let us again consider that an application developer or a system administrator has decided that twelve instances of the application ( 158 ) will be executed on the parallel computer ( 100 ). That is, twelve instances of the application ( 158 ) will be processed concurrently using twelve processors of the parallel computer ( 100 ). Accordingly, the serial segments ( 602 ,  606 ) of the application ( 158 ) will be executed using a minimum of twelve threads. That is, during serial segments, the parallel computer ( 100 ) will process twelve instances of the application ( 158 ), each instance utilizing a single thread of execution. Additional threads, however, may be utilized during parallel segments of the application ( 158 ) as each of those twelve initial threads spawn threads for enhanced performance. 
     Because the application ( 158 ) begins with a serial segment ( 602 ), a service node (not shown) initially configures twelve instances of the application ( 158 ) on twelve processors across three compute nodes booted up in serial processing mode ( 610 ). Specifically, the service node configures the application ( 158 ) on each processor P 0 -P 3  of compute nodes  0 - 2  as indicated by the shading of each of those processors. Because each instance of the application ( 158 ) only uses one thread during the serial segments ( 602 ,  606 ), the application ( 158 ) only uses twelve processing cores for execution, those twelve processing cores processing the twelve instances independently of one another. Readers will note that because all processors P 0 -P 3  on each compute node  0 - 2  are utilized for processing the serial segment ( 602 ), the processing resources of each compute node  0 - 2  are not squandered. 
     While all of the processors P 0 -P 3  of each compute node  0 - 2  are being utilized for execution of the application ( 158 ), no additional processors are available on nodes  0 - 2  to process threads spawned when a parallel segment ( 604 ) of the application ( 158 ) is encountered. Upon encountering the parallel segment ( 604 ) during execution, therefore the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in a parallel processing mode ( 612 ) and booted up in a partitioned parallel processing mode ( 800 ) according to embodiments of the present invention. Specifically in the example of  FIG. 8 , the following migration occurs: the application instance on P 0  of node  0  is migrated to P 0  of node  4 ; the application instance on P 1  of node  0  is migrated to P 0  of node  5 ; the application instance on P 2  of node  0  is migrated to P 0  of node  6 ; the application instance on P 3  of node  0  is migrated to P 0  of node  7 ; the application instance on P 0  of node  1  is migrated to P 0  of node  8 ; the application instance on P 1  of node  1  is migrated to P 1  of node  8 ; the application instance on P 2  of node  1  is migrated to P 0  of node  9 ; the application instance on P 3  of node  1  is migrated to P 1  of node  9 ; the application instance on P 0  of node  2  is migrated to P 0  of node  10 ; the application instance on P 1  of node  2  is migrated to P 1  of node  10 ; the application instance on P 2  of node  2  is migrated to P 0  of node  11 ; and the application instance on P 3  of node  2  is migrated to P 1  of node  11 . 
     In such a manner, the four instances of application ( 158 ) execute on the nodes  4 - 7  booted up in parallel processing mode ( 612 ) as indicated by the shading of PO in nodes  4 - 7 . Because nodes  4 - 7  are booted in parallel processing mode ( 612 ), P 0  serves as a master processor and the remaining processors P 1 - 3  serve as slave processors to P 0 . During execution of the parallel segment ( 604 ) of  FIG. 8 , therefore, each application instance on PO of nodes  4 - 7  may spawn threads to processors P 1 - 3  of each node to aid in processing the parallel segment ( 604 ) as represented in  FIG. 8  using arrows from P 0  to P 1 - 3  in nodes  4 - 7 . 
     The remaining eight instances of application ( 158 ) execute on nodes  8 - 11  booted up in partitioned parallel processing mode ( 800 ) as indicated by the shading of P 0  and P 1  in nodes  8 - 11 . Because nodes  8 - 11  are booted in partitioned parallel processing mode ( 800 ), P 0  serves as a master processor to P 2  while P 1  serves as a master processor to P 3 . During execution of the parallel segment ( 604 ) of  FIG. 8 , therefore, each application instance on P 0  and P 1  of nodes  8 - 11  may spawn threads to processors P 2  and P 3  respectively to aid in processing the parallel segment ( 604 ) as represented in  FIG. 8  using arrows from P 0  to P 2  and from P 1  to P 3  in nodes  8 - 11 . 
     While all of the processors P 0 - 3  of each compute node  4 - 11  are being utilized for execution of the application ( 158 ), none of the processors are underutilized because each processor executes either the main thread of an instance of the application ( 158 ) or a thread spawned from the main thread. Executing the serial segments ( 602 ,  606 ) of the application ( 158 ) on compute node  4 - 11 , however, would result in two or three processors on each compute node not being utilized. Upon encountering the serial segments ( 602 ,  606 ) during execution of the application ( 158 ) in the example of  FIG. 6 , therefore, the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in the serial processing mode ( 610 ). 
     For further explanation,  FIG. 9  sets forth a flow chart illustrating a further exemplary method for executing an application on a parallel computer according to the present invention. The parallel computer described with reference to  FIG. 9  includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors capable of operating independently for serial processing among the processors and capable of operating symmetrically for parallel processing among the processors. At least one of the compute nodes is capable of being booted up in a partitioned parallel processing mode that allows two or more sets of processors on that compute node to independently provide parallel processing among the processors in each set. The application ( 158 ) of  FIG. 9  has parallel segments ( 704 ) designated for parallel processing and serial segments ( 702 ) designated for serial processing. 
     The method of  FIG. 9  is similar to the method of  FIG. 7 . That is, the method of  FIG. 9  includes: booting up ( 708 ) a first subset ( 710 ) of the plurality of compute nodes in a serial processing mode; booting up ( 712 ) a second subset ( 714 ) of the plurality of compute nodes in a parallel processing mode; and executing ( 716 ) the application ( 158 ) on the plurality of compute nodes, including: migrating ( 718 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode upon encountering the parallel segments during execution, and migrating ( 722 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode upon encountering the serial segments during execution. 
     The method of  FIG. 9  also includes booting up ( 900 ) a third subset ( 902 ) of the plurality of compute nodes in the partitioned parallel processing mode. Booting up ( 900 ) a third subset ( 902 ) of the plurality of compute nodes in the partitioned parallel processing mode according to the method of  FIG. 9  may be carried out by setting register values in processors, memory, or bus circuitry of each compute node in the third subset ( 902 ) to instruct the node to operate in a partitioned parallel processing mode. The number of nodes included in the third subset ( 902 ) may be determined by dividing the number of instances of the application ( 158 ) that the application developer or system administrator desires to run concurrently on the parallel computer minus the number of node booted in parallel processor mode by the number of processor sets on each compute node booted in partitioned parallel processing mode. For example, if an application developer or a system administrator desires to have the parallel computer execute sixteen instances of the application ( 158 ) concurrently, four node are booted in parallel processing mode, and each compute node booted in partitioned parallel processing mode has two sets of processors to provide parallel processing among the processors in each set, then the third subset ( 902 ) of nodes should include at least six compute nodes. 
     In the method of  FIG. 9 , executing ( 716 ) the application ( 158 ) on the plurality of compute nodes includes migrating ( 904 ) the application ( 158 ) to the compute nodes booted up in partitioned parallel processing mode upon encountering parallel segments during execution. Migrating ( 904 ) the application ( 158 ) to the compute nodes booted up in partitioned parallel processing mode upon encountering parallel segments during execution according to the method of  FIG. 9  may be carried out by identifying that a parallel segment ( 704 ) is large enough to warrant migration using the size of the parallel segment ( 704 ) and some predefined threshold, selecting compute nodes in the third subset ( 902 ) for processing each instance of the application ( 158 ), and transferring each instance of the application ( 158 ) to the selected node in the third subset ( 902 ). The data transferred may include, for example, all data corresponding to each instance of the application ( 158 ) such as register values, data structures in memory, program instructions, and so on. 
     The explanation above with reference to  FIG. 9  describes booting up compute nodes in the parallel computer in a serial processing mode, a parallel processing mode, and a partitioned parallel processing mode. The parallel computer may then migrate the application between the nodes booted up in the various modes to enhance resource utilization. In some other embodiments, some of the compute nodes may be booted up in a hybrid processing mode so that each compute node may provide processing for the parallel segments of more than one application instance. For further explanation, consider  FIG. 10  that sets forth a line drawing illustrating further exemplary compute nodes of a parallel computer capable of executing an application on the parallel computer according to embodiments of the present invention. 
     The parallel computer ( 100 ) of  FIG. 10  includes sixteen compute nodes labeled  0 - 15  and connected together through a data communications network. Each compute node  0 - 15  has four processors, or processing cores, labeled P 0 , P 1 , P 2 , and P 3 . The processors of each compute node  0 - 15  are capable of operating independently for serial processing among the processors P 0 -P 3  and capable of operating symmetrically for parallel processing among the processors P 0 -P 3 . In addition, each of the compute nodes  0 - 15  are capable of being booted up in a hybrid processing mode that partitions the processors on that compute node into two or more sets of processors such that at least one set of processors on that compute node includes processors operating independently for serial processing among the processor in that set and at least one set of processors on that compute node includes processors that provide parallel processing among the processor in that set. In the example of  FIG. 10 , a service node (not shown) boots up a first subset of nodes that includes nodes  0 - 3  in a serial processing mode ( 610 ). The service node (not shown) also boots up a second subset of nodes that includes nodes  4 - 7  in a parallel processing mode ( 612 ). Moreover, the service node (not shown) boots up a third subset of nodes that includes nodes  8 - 15  in a hybrid processing mode ( 1000 ). 
     As mentioned above, in a hybrid processing mode, a node&#39;s processors are dividing into two or more sets of processors. At least one set of processors on that node includes processors operating independently for serial processing among the processor in that set. Each processor in that serial processing processor set has access to a portion of the node&#39;s computer memory that is exclusively dedicated to that processor. While the node has at least one serial processing processor set in a hybrid processing mode, at least one set of processors on that compute node include processors that provide parallel processing among the processor in that set. Parallel processing processor set consists of one master processor and one or more additional slave processors that all access the same partition of the node&#39;s memory—a partition distinct from the partitions accessed by processing in the serial processing processor set. The master processor of the parallel processor set supports a thread for execution and may spawn threads for cooperative execution on each of the slave processors in the parallel processing processor set. For example, consider compute node  14  in the example of  FIG. 10 . The processors of compute node  14  are divided into a processor set ( 1002 ) for parallel processing and a processor set ( 1004 ) for serial processing. In the processor set ( 1002 ) for parallel processing, processor P 0  is the master processor and P 2  is the slave processor. In the processor set ( 1004 ) for serial processing, processor P 1  and P 3  operate independently of one another for serial processing. 
     In the example of  FIG. 10 , the parallel computer ( 100 ) executes an application ( 158 ) on the computer&#39;s compute nodes. The application ( 158 ) of  FIG. 10  has both a parallel segment ( 604 ) designated for parallel processing and serial segments ( 602 ,  606 ) designated for serial processing. The serial segments ( 602 ,  606 ) include computer program instructions for execution serially in a single thread, while the parallel segment ( 604 ) includes computer program instructions for execution among multiple threads in parallel. In the example of  FIG. 10 , the application ( 158 ) distinguishes the serial segments ( 602 ,  606 ) from the parallel segment ( 604 ) using the directive ‘#pragma omp parallel.’ Readers will note that such an exemplary directive is for explanation only and not for limitation. In fact, the serial segments ( 602 ,  606 ) may be distinguished from the parallel segment ( 604 ) in many other ways as will occur to those of skill in the art such as, for example, processor operation codes, historical execution information, an application profile, and so on. 
     For discussion purposes with respect to  FIG. 10 , let us again consider that an application developer or a system administrator has decided that twelve instances of the application ( 158 ) will be executed on the parallel computer ( 100 ). That is, twelve instances of the application ( 158 ) will be processed concurrently using twelve processors of the parallel computer ( 100 ). Accordingly, the serial segments ( 602 ,  606 ) of the application ( 158 ) will be executed using a minimum of twelve threads. That is, during serial segments, the parallel computer ( 100 ) will process twelve instances of the application ( 158 ), each instance utilizing a single thread of execution. Additional threads, however, may be utilized during parallel segments of the application ( 158 ) as each of those twelve initial threads spawn threads for enhanced performance. 
     Because the application ( 158 ) begins with a serial segment ( 602 ), a service node (not shown) initially configures twelve instances of the application ( 158 ) on twelve processors across three compute nodes booted up in serial processing mode ( 610 ). Specifically, the service node configures the application ( 158 ) on each processor P 0 -P 3  of compute nodes  0 - 2  as indicated by the shading of each of those processors. Because each instance of the application ( 158 ) only uses one thread during the serial segments ( 602 ,  606 ), the application ( 158 ) only uses twelve processing cores for execution, those twelve processing cores processing the twelve instances independently of one another. Readers will note that because all processors P 0 -P 3  on each compute node  0 - 2  are utilized for processing the serial segment ( 602 ), the processing resources of each compute node  0 - 2  are not squandered. 
     While all of the processors P 0 -P 3  of each compute node  0 - 2  are being utilized for execution of the application ( 158 ), no additional processors are available on nodes  0 - 2  to process threads spawned when a parallel segment ( 604 ) of the application ( 158 ) is encountered. Upon encountering the parallel segment ( 604 ) during execution, therefore the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in a parallel processing mode ( 612 ) and booted up in a hybrid processing mode ( 1000 ) according to embodiments of the present invention. Specifically in the example of  FIG. 10 , the following migration occurs: the application instance on P 0  of node  0  is migrated to P 0  of node  4 ; the application instance on P 1  of node  0  is migrated to P 0  of node  5 ; the application instance on P 2  of node  0  is migrated to P 0  of node  6 ; the application instance on P 3  of node  0  is migrated to P 0  of node  7 ; the application instance on P 0  of node  1  is migrated to P 0  of node  8 ; the application instance on P 1  of node  1  is migrated to P 0  of node  9 ; the application instance on P 2  of node  1  is migrated to P 0  of node  10 ; the application instance on P 3  of node  1  is migrated to P 0  of node  11 ; the application instance on P 0  of node  2  is migrated to P 0  of node  12 ; the application instance on P 1  of node  2  is migrated to P 0  of node  13 ; the application instance on P 2  of node  2  is migrated to P 0  of node  14 ; and the application instance on P 3  of node  2  is migrated to P 0  of node  15   
     In such a manner, the four instances of application ( 158 ) execute on the nodes  4 - 7  booted up in parallel processing mode ( 612 ) as indicated by the shading of PO in nodes  4 - 7 . Because nodes  4 - 7  are booted in parallel processing mode ( 612 ), P 0  serves as a master processor and the remaining processors P 1 - 3  serve as slave processors to P 0 . During execution of the parallel segment ( 604 ) of  FIG. 10 , therefore, each application instance on PO of nodes  4 - 7  may spawn threads to processors P 1 - 3  of each node to aid in processing the parallel segment ( 604 ) as represented in  FIG. 10  using arrows from P 0  to P 1 - 3  in nodes  4 - 7 . 
     The remaining eight instances of application ( 158 ) execute on nodes  8 - 15  booted up in hybrid processing mode ( 1000 ) as indicated by the shading of P 0  in nodes  8 - 15 . Because nodes  8 - 15  are booted in hybrid processing mode ( 1000 ), P 0  serves as a master processor to P 2  while P 1  and P 3  operate independently. During execution of the parallel segment ( 604 ) of  FIG. 10 , therefore, each application instance on P 0  of nodes  8 - 15  may spawn a additional threads to processor P 2  to aid in processing the parallel segment ( 604 ) as represented in  FIG. 10  using arrows from P 0  to P 2  in nodes  8 - 15 . Because processors P 1  and P 3  of nodes  8 - 15  operate independently of the other processors, processors P 1  and P 3  on nodes  8 - 15  may be utilized for other processing tasks related to other applications so those processing resources are not wasted. 
     While all of the processors of each compute node  4 - 15  are being utilized for execution of the application ( 158 ) or some other processes, none of the processors are underutilized because each processor executes either the main thread of an instance of the application ( 158 ) or a thread spawned from the main thread. Executing the serial segments ( 602 ,  606 ) of the application ( 158 ) on compute node  4 - 15 , however, would result in two or three processors on each compute node not being utilized. Upon encountering the serial segments ( 602 ,  606 ) during execution of the application ( 158 ) in the example of  FIG. 6 , therefore, the parallel computer ( 100 ) migrates the application ( 158 ) to the compute nodes booted up in the serial processing mode ( 610 ). 
     For further explanation,  FIG. 11  sets forth a flow chart illustrating a further exemplary method for executing an application on a parallel computer according to the present invention. The parallel computer described with reference to  FIG. 11  includes a plurality of compute nodes connected together through a data communications network. Each compute node has a plurality of processors capable of operating independently for serial processing among the processors and capable of operating symmetrically for parallel processing among the processors. At least one of the compute nodes is capable of being booted up in a hybrid processing mode that partitions the processors on that compute node into two or more sets of processors. At least one set of processors on that compute node includes processors operating independently for serial processing among the processor in that set, and at least one set of processors on that compute node includes processors that provide parallel processing among the processor in that set. The application ( 158 ) of  FIG. 11  has parallel segments ( 704 ) designated for parallel processing and serial segments ( 702 ) designated for serial processing. 
     The method of  FIG. 11  is similar to the method of  FIG. 7 . That is, the method of  FIG. 11  includes: booting up ( 708 ) a first subset ( 710 ) of the plurality of compute nodes in a serial processing mode; booting up ( 712 ) a second subset ( 714 ) of the plurality of compute nodes in a parallel processing mode; and executing ( 716 ) the application ( 158 ) on the plurality of compute nodes, including: migrating ( 718 ) the application ( 158 ) to the compute nodes booted up in a parallel processing mode upon encountering the parallel segments during execution, and migrating ( 722 ) the application ( 158 ) to the compute nodes booted up in the serial processing mode upon encountering the serial segments during execution. 
     The method of  FIG. 11  also includes booting up ( 1100 ) a third subset ( 1102 ) of the plurality of compute nodes in the hybrid processing mode. Booting up ( 1100 ) a third subset ( 1102 ) of the plurality of compute nodes in the hybrid processing mode according to the method of  FIG. 11  may be carried out by setting register values in processors, memory, or bus circuitry of each compute node in the third subset ( 1102 ) to instruct the node to operate in a hybrid processing mode. The number of nodes included in the third subset ( 1102 ) may be determined by dividing the number of instances of the application ( 158 ) that the application developer or system administrator desires to run concurrently on the parallel computer minus the number of node booted in parallel processing mode by the number of parallel processing processor sets on each compute node booted in hybrid mode. For example, if an application developer or a system administrator desires to have the parallel computer execute sixteen instances of the application ( 158 ) concurrently, four node are booted in parallel processing mode, and the nodes booted in hybrid mode each have only one processing set of processors to provide parallel processing, then the third subset ( 1102 ) of nodes should include at least six compute nodes. 
     In the method of  FIG. 11 , executing ( 716 ) the application ( 158 ) on the plurality of compute nodes includes migrating ( 1104 ) the application ( 158 ) to the compute nodes booted up in hybrid processing mode upon encountering parallel segments ( 704 ) during execution. Migrating ( 1104 ) the application ( 158 ) to the compute nodes booted up in hybrid processing mode upon encountering parallel segments ( 704 ) during execution according to the method of  FIG. 11  may be carried out by identifying that a parallel segment ( 704 ) is large enough to warrant migration using the size of the parallel segment ( 704 ) and some predefined threshold, selecting compute nodes in the third subset ( 1102 ) for processing each instance of the application ( 158 ), and transferring each instance of the application ( 158 ) to the selected node in the third subset ( 1102 ). The data transferred may include, for example, all data corresponding to each instance of the application ( 158 ) such as register values, data structures in memory, program instructions, and so on. 
     Exemplary embodiments of the present invention are described largely in the context of a fully functional parallel computer system for providing nearest neighbor point-to-point communications among compute nodes of an operational group in a global combining network. Readers of skill in the art will recognize, however, that the present invention also may be embodied in a computer program product disposed on computer readable media for use with any suitable data processing system. Such computer readable media may be transmission media or recordable media for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of recordable media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Examples of transmission media include telephone networks for voice communications and digital data communications networks such as, for example, Ethernets™ and networks that communicate with the Internet Protocol and the World Wide Web as well as wireless transmission media such as, for example, networks implemented according to the IEEE 802.11 family of specifications. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the invention as embodied in a program product. Persons skilled in the art will recognize immediately that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present invention. 
     It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.