Patent Publication Number: US-11641116-B2

Title: Charge/discharge control circuit and battery device having the same

Description:
RELATED APPLICATIONS 
     This application claims priority to Japanese Patent Application No. 2020-016155, filed Feb. 3, 2020, the entire content of which is incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a charge/discharge control circuit and a battery device. 
     2. Description of the Related Art 
       FIG.  3    is a circuit diagram for illustrating a conventional battery device having a cell balance circuit. 
     The conventional battery device has a charge/discharge control circuit  30 , batteries  31   a  and  31   b , resistors  32   a  and  32   b  for cell-balance discharging, Nch FETs  33   a  and  33   b  for cell-balance discharging, protection resistors  34   a  and  34   b , a discharge control FET  35 , a charge control FET  36 , and external terminals EB+ and EB−. The charge/discharge control circuit  30  has overcharge detection circuits  301   a  and  301   b , overdischarge detection circuits  302   a  and  302   b , cell-balance detection circuits  303   a  and  303   b , a control circuit  304 , a power supply terminal VDD, a ground terminal VSS, an input terminal VC, and output terminals CB 1 , CB 2 , CO, and DO. 
     The charge/discharge control circuit  30  monitors voltages of the batteries  31   a  and  31   b , and controls the voltages of the batteries  31   a  and  31   b  through turning on/off the discharge control FET  35  and the charge control FET  36  by the control circuit  304  based on the condition of the voltages. 
     Connection of a charger between the external terminals EB+ and EB− starts charging of the batteries  31   a  and  31   b  so that voltages of the power supply terminal VDD and the input terminal VC gradually increase. In a state in which the voltage of one of the batteries, for example, the voltage of the battery  31   a , that is, the VDD-VC voltage, exceeds the cell-balance detection voltage, the cell-balance detection circuit  303   a  sends a detection signal to the control circuit  304 . In response to the reception of the detection signal from the cell-balance detection circuit  303   a , the control circuit  304  sends a cell-balance control signal to the Nch FET  33   a . In response to the reception of the cell-balance control signal, the Nch FET  33   a  for cell-balance discharging turns on to discharge the battery  31   a . Consequently, the charging speed of the battery  31   a  is reduced compared to the battery  31   b.    
     Likewise, in a state in which the voltage of the battery  31   b  exceeds the cell-balance detection voltage, the control circuit  304  turns on the Nch FET  33   b  for cell-balance discharging to discharge the battery  31   b.    
     Through the above-mentioned charging operation, the charge/discharge control circuit  30  eliminates voltage deviation between the batteries  31   a  and  31   b , that is, performs cell balance operation (see, for example, Japanese Patent Application Laid-open No. 2013-192394). 
     As a conceivable measure for responding to a demand for reducing cost for the charge/discharge control circuit  30 , reduction of the number of terminals thereof may be considered. However, with the conventional circuit configuration, it is difficult to omit any more terminals. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to reduce the cost for a charge/discharge control circuit and a battery device. 
     A charge/discharge control circuit according to an embodiment of the present invention includes: a power supply terminal to which a positive electrode of a first battery is connected; an input terminal to which a negative electrode of the first battery and a positive electrode of a second battery are connected; a ground terminal to which a negative electrode of the second battery is connected; an output terminal configured to send a cell-balance control signal to each of a first cell balance circuit and a second cell balance circuit; a first voltage detection circuit connected between the power supply terminal and the input terminal; a second voltage detection circuit connected between the input terminal and the ground terminal; a control circuit configured to send a first control signal and a second control signal in accordance with a detection signal provided from at least one of the first voltage detection circuit and the second voltage detection circuit; and an output circuit configured to send a selected voltage to the output terminal, the selected voltage being selected from one of a voltage of the power supply terminal, a voltage of the input terminal, and a voltage of the ground terminal in accordance with the first control signal and the second control signal. 
     According to a charge/discharge control circuit of the present invention, the number of output terminals for controlling the cell-balance discharging FETs connected in parallel to the two series-connected batteries, respectively, can be reduced to one. As a result, the cost for the charge/discharge control circuit and the battery device can be reduced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a circuit diagram for illustrating a battery device including a charge/discharge control circuit according to an embodiment of the present invention. 
         FIG.  2    is a circuit diagram for illustrating another example of the charge/discharge control circuit according to the embodiment of the present invention. 
         FIG.  3    is a circuit diagram for illustrating a conventional battery device. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG.  1    is a circuit diagram for illustrating a battery device including a charge/discharge control circuit according to the embodiment of the present invention. 
     The battery device includes a charge/discharge control circuit  10 , batteries  11   a  and  11   b , resistors  12   a  and  12   b  for cell-balance discharging, an Nch FET  13   a  and Pch FET  13   b  for cell-balance discharging, protection resistors  14   a  and  14   b , a discharge control FET  15 , a charge control FET  16 , and external terminals EB+ and EB−. The resistor  12   a  and the Nch FET  13   a  form a first cell balance circuit  17   a , and the resistor  12   b  and the Pch FET  13   b  form a second cell balance circuit  17   b . The charge/discharge control circuit  10  includes a power supply terminal VDD, a ground terminal VSS, an input terminal VC, and output terminals CB, DO, and CO. 
     The battery  11   a  has a positive terminal connected to the external terminal EB+ and to the power supply terminal VDD via the protection resistor  14   a , and has a negative terminal connected to a positive terminal of the battery  11   b  and to the input terminal VC via the protection resistor  14   b . The battery  11   b  has a negative terminal connected to the ground terminal VSS. The Nch FET  13   a  has a drain connected to the positive terminal of the battery  11   a  via the resistor  12   a , a source connected to the negative terminal of the battery  11   a  and to the positive terminal of the battery  11   b , and a gate connected to the output terminal CB. The Pch FET  13   b  has a source connected to the negative terminal of the battery  11   a  and to the positive terminal of the battery  11   b , a drain connected to the negative terminal of the battery  11   b  via the resistor  12   b , and a gate connected to the output terminal CB. The discharge control FET  15  has a drain connected to a drain of the charge control FET  16 , a source connected to the negative terminal of the battery  11   b , and a gate connected to the output terminal DO. The charge control FET  16  has a source connected to the external terminal EB− and a gate connected to the output terminal CO. 
     The charge/discharge control circuit  10  includes overcharge detection circuits  101   a  and  101   b , overdischarge detection circuits  102   a  and  102   b , cell-balance detection circuits  103   a  and  103   b , a control circuit  104 , and an output circuit  105 . Detection voltages of the respective detection circuits satisfy a relation VOD&lt;VCB&lt;VOC where VOD is an overdischarge detection voltage, VCB is a cell-balance detection voltage, and VOC is an overcharge detection voltage. The output circuit  105  includes a current limiting resistor  111 , a switch  112   a  constructed by an Nch FET, and a switch  112   b  constructed by a Pch FET. 
     The overcharge detection circuit  101   a , the overdischarge detection circuit  102   a , and the cell-balance detection circuit  103   a  are connected between the power supply terminal VDD and the input terminal VC while respective output terminals are connected to a first input terminal, second input terminal, and third input terminal of the control circuit  104 , respectively. The overcharge detection circuit  101   b , the overdischarge detection circuit  102   b , and the cell-balance detection circuit  103   b  are connected between the input terminal VC and the ground terminal VSS. Output terminals of the overcharge detection circuit  101   b , the overdischarge detection circuit  102   b , and the cell-balance detection circuit  103   b  are connected to a fourth input terminal, fifth input terminal, and sixth input terminal of the control circuit  104 , respectively. 
     The control circuit  104  has a first output terminal connected to a control terminal of the switch  112   a , has a second output terminal connected to a control terminal of the switch  112   b , has a third output terminal connected to the output terminal DO, and has a fourth output terminal connected to the output terminal CO. 
     The output circuit  105  has a first input terminal connected to the power supply terminal VDD, a second input terminal connected to the ground terminal VSS, a third input terminal connected to the input terminal VC, and an output terminal connected to the output terminal CB. The switch  112   a  is connected between the first input terminal and the output terminal. The switch  112   b  is connected between the output terminal and the second input terminal. The current limiting resistor  111  is connected between the third input terminal and the output terminal. 
     Operation of the battery device constructed as above is then described below. 
     The batteries  11   a  and  11   b  whose voltages are reduced through discharging to a load are charged by a charger connected between the external terminal EB+ and the external terminal EB−. In a case in which voltages of the battery  11   a  and the battery  11   b  are lower than the cell-balance detection voltage, the overcharge detection circuits  101   a  and  101   b , the overdischarge detection circuits  102   a  and  102   b , and the cell-balance detection circuits  103   a  and  103   b  each send no detection signal to the control circuit  104 . 
     The control circuit  104  receives no detection signal from any of the detection circuits, and hence the control circuit  104  sends a control signal for turning off the switches  112   a  and  112   b  from the first and second output terminals, respectively, sends a control signal for turning on the discharge control FET  15  from the third output terminal, and sends a control signal for turning on the charge control FET  16  from the fourth output terminal. The switches  112   a  and  112   b  are turned off, and hence the output circuit  105  applies the voltage of the input terminal VC to the output terminal CB. The Nch FET  13   a  and the Pch FET  13   b  are turned off because the gate voltage is equal to the source voltage. 
     Next, description is given of operation of the charge/discharge control circuit  10  in a case in which the voltage of the battery  11   a  exceeds the cell-balance detection voltage, and the voltage of the battery  11   b  does not exceed the cell-balance detection voltage. 
     In the case in which the voltage of the battery  11   a  exceeds the cell-balance detection voltage, the cell-balance detection circuit  103   a  sends a cell-balance detection signal to the third input terminal of the control circuit  104 . Receiving the cell-balance detection signal at the third input terminal, the control circuit  104  sends a control signal for turning on the switch  112   a  from the first output terminal and sends a control signal for turning off the switch  112   b  from the second output terminal. Consequently, in the output circuit  105 , the switch  112   a  is turned on and the switch  112   b  is turned off. Thus, the output circuit  105  applies a voltage of the power supply terminal VDD to the output terminal CB. 
     The Nch FET  13   a  is turned on because the voltage of the power supply terminal VDD is applied to the gate. As a result, the cell-balance discharging current flows through the resistor  12   a  and the Nch FET  13   a . Thus, voltage increase of the battery  11   a  caused by the charging current is suppressed. The Pch FET  13   b  is turned off because the voltage of the power supply terminal VDD is applied to the gate. As a result, no cell-balance discharging current flows through the Pch FET  13   b.    
     Through the above-mentioned operation of the charge/discharge control circuit  10 , voltages of cells, namely, the battery  11   a  and the battery  11   b , can be balanced. 
     Next, description is given of operation of the charge/discharge control circuit  10  in a case in which the voltage of the battery  11   b  exceeds the cell-balance detection voltage, and the voltage of the battery  11   a  does not exceed the cell-balance detection voltage. 
     In the case in which the voltage of the battery  11   b  exceeds the cell-balance detection voltage, the cell-balance detection circuit  103   b  sends a cell-balance detection signal to the sixth input terminal of the control circuit  104 . Receiving the cell-balance detection signal at the sixth input terminal, the control circuit  104  sends a control signal for turning off the switch  112   a  from the first output terminal and sends a control signal for turning on the switch  112   b  from the second output terminal. Consequently, in the output circuit  105 , the switch  112   a  is turned off and the switch  112   b  is turned on. Thus, the output circuit  105  applies the voltage of the ground terminal VSS to the output terminal CB. 
     The Pch FET  13   b  is turned on because the voltage of the ground terminal VSS is applied to the gate. As a result, a cell-balance discharging current flows through the Pch FET  13   b  and the resistor  12   b . Thus, voltage increase of the battery  11   b  caused by a charging current is suppressed. The Nch FET  13   a  is turned off because the voltage of the ground terminal VSS is applied to the gate. As a result, no cell-balance discharging current flows through the Nch FET  13   a.    
     Through the above-mentioned operation of the charge/discharge control circuit  10 , voltages of cells, namely, the battery  11   a  and the battery  11   b , can be balanced. 
     Next, description is given of operation of the charge/discharge control circuit  10  in a case in which the voltages of the battery  11   a  and the battery  11   b  exceed the cell-balance detection voltage. 
     In the case in which the voltages of the batteries  11   a  and  11   b  exceed the cell-balance detection voltage, the cell-balance detection circuit  103   a  sends a cell-balance detection signal to the third input terminal of the control circuit  104 , and the cell-balance detection circuit  103   b  sends a cell-balance detection signal to the sixth input terminal of the control circuit  104 . Receiving the cell-balance detection signals at both of the third input terminal and the sixth input terminal, the control circuit  104  sends a control signal for turning off the switch  112   a  from the first output terminal, and sends a control signal for turning off the switch  112   b  from the second output terminal. Because the switch  112   a  and the switch  112   b  are turned off, the output circuit  105  applies the voltage of the input terminal VC to the output terminal CB. 
     The Nch FET  13   a  is turned off because the voltage of the input terminal VC is applied to the gate. The Pch FET  13   b  is turned off because the voltage of the input terminal VC is applied to the gate. That is, in a case in which the voltages of both the batteries  11   a  and  11   b  exceed the cell-balance detection voltage, the control circuit  104  considers that the cells are balanced and causes no cell-balance discharging current to flow. 
     As described above, according to the charge/discharge control circuit according to the embodiment of the present invention, because three levels of output voltages can be applied from one output terminal to control the cell-balance discharging FETs connected in parallel to the two batteries, respectively, one output terminal can be omitted. That is, the cost for the charge/discharge control circuit and the battery device can be reduced. 
       FIG.  2    is a circuit diagram for illustrating another example of the charge/discharge control circuit according the embodiment of the present invention. 
     A charge/discharge control circuit  20  shows an example in which the overcharge detection circuits  102   a  and  102   b  serve also as the cell-balance detection circuits  103   a  and  103   b . In a case in which the cell-balance detection voltage and the overcharge detection voltage can be the same, the above-mentioned configuration is applicable. 
     Further, the output circuit  205  of the charge/discharge control circuit  20  includes a switching circuit  211  in place of the current limiting resistor  111 . The switching circuit  211  is turned on/off in accordance with the control signal sent from the fifth output terminal of the control circuit  204 . The switching circuit  211  is constructed by a transmission gate, for example. The switching circuit  211  is turned on in a case in which both the switch  112   a  and the switch  112   b  are turned off, to thereby apply the voltage of the input terminal VC to the output terminal CB. 
     The battery device of  FIG.  2    can also produce the same effects as those of the battery device of  FIG.  1    with the use of the charge/discharge control circuit  20  constructed as above. 
     The embodiment of the present invention has been described above, but the present invention is not limited to the above-mentioned embodiment, and various modifications can be made thereto without departing from the gist of the present invention. 
     In the embodiment of the present invention, the description is given of cell balancing against overcharging, for example, but the present invention is also applicable to cell balancing against overdischarging. In this case, in response to overdischarge cell-balance detection, a cell balance current is caused to flow through a battery having a voltage equal to or higher than an overdischarge cell-balance detection voltage. In this case, the overdischarge detection circuit may serve also as the cell-balance detection circuit. 
     Further, the switching circuit  211 , for example, does not have to be the transmission gate and is not limited to the transmission gate as long as the operation as a switch capable of turning off the cell balance FET is secured.