Patent Publication Number: US-9417640-B2

Title: Input pin control

Description:
BACKGROUND 
     1. Field of the Invention 
     The present invention relates generally to integrated circuits, and more particularly to pull-up and pull-down circuitry for input/output pads of integrated circuits. 
     2. Description of Related Art 
     Integrated circuits include input/output (I/O) pads used for receiving and transmitting signals. During operation, if an I/O pad is left “floating”, meaning that the pad is not being driven to a predictable voltage by external or internal drivers, the pad may float at a voltage level sufficient to cause input buffer circuitry connected to the pad to turn-on and operate unpredictably. This unpredictable operation increases power consumption for the device and may cause damage to the input buffer circuitry. A floating voltage on the pad may also place the input buffer circuitry in an indeterminate state, resulting in indeterminate signals propagating to the internal circuitry of the device and causing oscillations and other spurious effects. 
     In order to avoid such issues, integrated circuits may include pull-up or pull-down circuitry to bias the pad to a predictable voltage level when the pad is left in a floating condition. In one example, such as U.S. Pat. No. 8,400,190 (Issue Date 19 Mar. 2013, Chun Hsiung Hung et al.), a pad can be pre-charged to either a high reference voltage or a low reference voltage, as manufactured. However, a pad of an integrated circuit may need to be coupled to a pull-up circuitry for one application, but coupled to a pull-down circuitry for another application, depending on requirements of a system that includes the integrated circuit. 
     It is therefore desirable to provide improved pull-up and/or pull-down circuitry for pads of integrated circuits that allow setting individual pads to predictable voltage levels. 
     SUMMARY 
     An integrated circuit device described herein includes a pad adapted to receive a signal from an external driver, such as a user input signal driven by a bus line. A state register is programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry on the integrated circuit device responsive to the state for the pad. The voltage level may for example correspond to one of a logic low level and a logic high level. A voltage holding circuit is coupled to the pad and the state register, and is configured to force the pad to the indicated voltage level in response to an event that causes the initialization. The pad can be further adapted to receive a signal from an output buffer circuit in the integrated circuit device, such that the pad can be driven by the output buffer circuit when the output buffer circuit is enabled to output data from the device to the bus line. 
     The voltage holding circuit can be configured to quickly set the voltage level at the pad with a first current, and to subsequently hold the voltage level at the pad with a second current weaker than the first current, where the second current is sufficiently weak such that the voltage level held at the pad is overridable by a signal applied by a driver coupled to the pad. 
     The integrated circuit can include a plurality of pads configured to receive signals that can have an effect during initialization. Thus, in such embodiments, a second state register can be programmed with a second state that indicates a second voltage level to set for the pad upon the initialization. A second voltage holding circuit can be coupled to the pad and the second state register, and be configured to force the pad to the second voltage level in response to the event that causes the initialization. 
     The second voltage holding circuit can be configured to quickly set the second voltage level at the pad with a first current, and to subsequently hold the second voltage level at the pad with a second current weaker than the first current. 
     A plurality of state registers can be programmed with a state indicating a voltage level to set for pads in the plurality of pads during initialization of circuitry on the integrated circuit device responsive to the state for the pads. A plurality of voltage holding circuits can be coupled to pads in the plurality of pads and state registers in the plurality of state registers, and configured to force the pads to the indicated voltage level in response to an event that causes the initialization. The pads can be further adapted to receive signals from output buffer circuits in the integrated circuit device. 
     A second plurality of state registers can be programmed with a second state indicating a second voltage level to set for pads in the plurality of pads upon the initialization. A second plurality of voltage holding circuits can be coupled to pads in the plurality of pads and state registers in the second plurality of state registers, and configured to force the pads to the second voltage level in response to the event that causes the initialization. 
     Methods for biasing a pad of an integrated circuit described herein include forcing the pad to a voltage level in response to an event that causes initialization of circuitry responsive to the external signal, where the voltage level is indicated by a state programmed in a state register. 
     The step of forcing the pad to a voltage level can include setting the voltage level at the pad with a first current, and subsequently holding the voltage level at the pad with a second current, where the second current is weaker than the first current, and is sufficiently weak such that the voltage level held at the pad is overridable by the external signal. 
     The methods can include forcing the pad to a second voltage level in response to the event that causes initialization of circuitry responsive to the external signal, where the second voltage level is indicated by a second state programmed in a second state register. 
     The step of forcing the pad to a second voltage level can include setting the second voltage level at the pad with a first current, and subsequently holding the second voltage level at the pad with a second current, where the second current is weaker than the first current, and is sufficiently weak such that the second voltage level held at the pad is overridable by the external signal. 
     Other aspects and advantages of the present invention can be seen on review of the drawings, the detailed description, and the claims which follow. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified functional block diagram of input/output circuitry for a pad of an integrated circuit device. 
         FIG. 2  is a schematic diagram of an embodiment of the voltage holding circuit and the second voltage holding circuit for the pad. 
         FIG. 3  illustrates an embodiment of a timing diagram for operating the architecture including the voltage holding circuit of  FIGS. 1 and 2 . 
         FIG. 4  illustrates an embodiment of a timing diagram for operating the architecture including the second voltage holding circuit of  FIGS. 1 . 
         FIG. 5  is a flow chart of a method for biasing the pad. 
         FIG. 6  illustrates a plurality of pull-up state registers for a plurality of pads in an integrated circuit device. 
         FIG. 7  illustrates a plurality of pull-down state registers for a plurality of pads in an integrated circuit device. 
     
    
    
     DETAILED DESCRIPTION 
     A detailed description of embodiments of the present invention is provided with reference to the Figures. The following description will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals. 
       FIG. 1  is a simplified functional block diagram of input/output circuitry for a pad  102  of an integrated circuit device  100 . As used herein, the term “pad” refers to a circuit node adapted to receive a signal from an external driver, such as a user input signal driven by a bus line, or from an output buffer circuit in the integrated circuit device. For example, the pad  102  can be adapted to receive an external signal  101  when output buffer circuit  190  is disabled, or to receive a signal from output buffer circuit  190  when output buffer circuit  190  is enabled to output data from the integrated circuit device  100  to a bus line coupled to pads of the integrated circuit device including the pad  102 . 
     As illustrated in the example of  FIG. 1 , the input/output circuitry for pad  102  includes a state register  110  and a voltage holding circuit  115 . The state register  110  can be programmed with a state that indicates a voltage level to set for the pad during initialization of circuitry responsive to the state for the pad. The voltage level can correspond to one of a logic low level (e.g. ‘0’) and a logic high level (e.g. ‘1’). The voltage holding circuit  115  is coupled to the pad  102  and the state register  115 , and is configured to force the pad to the voltage level in response to an event that causes the initialization, so that the voltage level will be in a known state at initialization of the circuit. For instance, the event can be a power-on reset event (POR) generated by the internal circuitry  140  after electrical power is applied to the integrated circuit device  100 . For instance, in the SPI (serial peripheral interface) standard as can be used with the present technology, the limit on input load current can be between −2 μA and 2 μA, and the strength of a weak pullup path or a weak pulldown path can be 10% of the limit, i.e., between −0.2 μA and 0.2 μA. The strength of the weak pullup or pulldown path can be modified such that the voltage at the pad is within the range of VIL (input low voltage) and VIH (input high voltage), for example as specified by the SPI standard, when the pad is forced by an external signal. 
     Control signals A and B are generated in this example, in response to the state programmed in the state register  110  to control the voltage holding circuit  115 , and are further described in connection with  FIGS. 2 and 3 . 
     The pad  102  is connected to an input buffer circuit  130 . Input voltage levels applied to the pad  102  are buffered by the input buffer circuit  130  and applied to internal circuitry  140  that responds to the voltage level on the pad, such as a controller having a state machine, power management logic, or the like. The pad  102  can also be connected to an output terminal of the output buffer circuit  190 . An input terminal of the output buffer circuit  190  can be connected to the internal circuitry  140 . The output buffer circuit  190  can be enabled or disabled by a control signal (not shown) from the internal circuitry  140 . 
     The input/output circuitry for pad  102  can include a second state register  120  and a second voltage holding circuit  125 . The state register  120  can be programmed with a second state that indicates a second voltage level to set for the pad during initialization of circuitry responsive to the second state for the pad. In one embodiment, the voltage level for the state register  110  can correspond to a logic high level (e.g. ‘1’), while the second voltage level for the second state register  120  can correspond to a logic low level (e.g. ‘0’). In another embodiment, the voltage level for the state register  110  can correspond to a logic low level (e.g. ‘0’), while the second voltage level for the second state register  120  can correspond to a logic high level (e.g. ‘1’). The second voltage holding circuit  125  is coupled to the pad  102  and the second state register  125 , and is configured to force the pad to the second voltage level in response to the event that causes the initialization. 
     Control signals C and D are generated in response to the state programmed in the state register  120  to control the second voltage holding circuit  125 , and are further described in connection with  FIGS. 2 and 4 . 
       FIG. 2  is a schematic diagram of an embodiment of the voltage holding circuit  115  and the second voltage holding circuit  125 . As shown in the example of  FIG. 2 , the voltage holding circuit  115  includes two pull-up circuits  210  and  220 . The pull-up circuit  210  includes a PMOS pass transistor M 1  coupled to the pad  102  at one conduction terminal, and coupled to a supply voltage VDD at another conduction terminal. The PMOS pass transistor M 1  is sized to provide a strong current (high power pull-up) to the pad  102  such that the pad can reach the voltage level in a relative fast time. The pull-up circuit  210  is controlled by the control signal A, which is connected to the control terminal of the PMOS pass transistor M 1 . 
     The pull-up circuit  220  includes a set of PMOS pass transistors in series (e.g. M 2 -M 5 ) coupled to the pad  102  at one end of the set, and coupled to the supply voltage VDD at another end of the set. PMOS pass transistors in the set are sized to provide a weaker current to the pad  102  (low power holding) such that the pad does not float, and the voltage level held at the pad is overridable by the external signal  101 . The external signal can be applied according to a specified input signal current level, such as for example a current level specified according to the SPI standard, that can override the low current holding. In the example using the SPI standard, the low current holding can be between −0.2 μA and 0.2 μA, while an external signal can have current between −2 μA and 2 μA and thus can override the weak pullup. The pull-up circuit  220  is controlled by the control signal B, which is connected to the control terminals of the PMOS pass transistors M 2 -M 5 . 
     The PMOS pass transistors in the set are said to be “weak” in the sense that when a voltage less than the supply voltage VDD is asserted on the pad  102  by an external driver, or by an output buffer circuit in the integrated circuit device, the driver or the output buffer circuit provides a stronger pull-down action than the pull-up action of the PMOS pass transistors in the set. The external driver or the output buffer circuit thus “wins”, and changes the voltage at the pad  102  to a known state, preventing propagating indeterminate signals to the internal circuitry of the device or to a bus line coupled to the device. 
     Thus, the voltage holding circuit  115  can be configured quickly to set the voltage level at the pad with a first current through the pull-up circuit  210  during initialization of the internal circuits responsive to the state for the pad, and to subsequently hold the voltage level at the pad  102  with a second current through the pull-up circuit  220  after initialization of the internal circuits responsive to the voltage level on the pad. The second current is weaker than the first current, and is sufficiently weak such that the voltage level held at the pad  102  is overridable by the external signal  101 . 
     As shown in the example of  FIG. 2 , the voltage holding circuit  125  includes two pull-down circuits  230  and  240 . The pull-down circuit  230  includes an NMOS pass transistor M 6  coupled to the pad  102  at one conduction terminal, and coupled to a reference voltage, such as ground GND on another conduction terminal. The NMOS pass transistor M 6  is sized to provide a strong current (high power pull-down) to the pad  102  such that the pad can reach the second voltage level in a relative fast time. The pull-down circuit  230  is controlled by the control signal C, which is connected to the control terminal of the NMOS pass transistor M 6 . 
     The pull-down circuit  240  includes a set of PMOS pass transistors in series (e.g. M 7 -M 10 ) coupled to the pad  102  at one end of the set, and coupled to ground at another end of the set. NMOS pass transistors in the set are sized to provide a weaker current to the pad  102  (low power holding) such that the pad does not float, and the second voltage level held at the pad is overridable by the external signal  101 . In the example using the SPI standard, the low current holding can be between −0.2 μA and 0.2 μA, while an external signal can have current between −2 μA and 2 μA and thus can override the weak pulldown. The pull-down circuit  240  is controlled by the control signal D, which is connected to the control terminals of the NMOS pass transistors M 7 -M 10 . 
     The NMOS pass transistors in the set are said to be “weak” in the sense that when a voltage greater than the reference voltage GND is asserted on the pad  102  by an external driver, or by an output buffer circuit in the integrated circuit device, the driver or the output buffer circuit provides a stronger pull-up action than the pull-down action of the NMOS pass transistors in the set. The external driver or the output buffer circuit thus “wins”, and changes the voltage at the pad  102  to a known state. 
     Thus, the voltage holding circuit  125  can be configured quickly to set the second voltage level at the pad with a first current through the pull-down circuit  230  during initialization of the internal circuits responsive to the state for the pad, and to subsequently hold the second voltage level at the pad  102  with a second current through the pull-down circuit  240  after initialization of the internal circuits responsive to the voltage level on the pad. The second current is weaker than the first current, and is sufficiently weak such that the second voltage level held at the pad  102  is overridable by the external signal  101 . 
       FIG. 3  illustrates an embodiment of a timing diagram for operating the architecture including the voltage holding circuit of  FIGS. 1 and 2  using the methods described herein. As will be understood the timing diagram of  FIG. 3  is simplified and not necessarily to scale. 
     The sequence begins at time T 1  in response to an initialization event. In the illustrated example, the initialization event is a power-on event during which the internal circuitry  140  generates a power-on reset “POR” signal in response to the application of power to the integrated circuit device  100 . More generally, the initialization event may be any other event, for which a signal is generated internally or externally to begin the sequence which causes circuitry on the integrated circuit that is responsive to the voltage level on the pad to reset or restart. 
     During the power-on process, the POR signal is set to a high state at time T 2  by the internal circuitry  140 . Following the power-on process the POR signal is returned to a low state at time T 3 . 
     At time T 4 , control signal A is set to a low state, turning on the pull-up circuit  210  to set the voltage level at the pad  102  with a first current. At time T 5 , control signal B is set to a low state, turning on the pull-up circuit  220  to hold the voltage level at the pad  102  with a second current, while control signal A is set to a high state, turning off the pull-up circuit  210 . As described herein, the second current is weaker than the first current, and is sufficiently weak such that the voltage level held at the pad  102  is overridable by the external signal  101 . 
     Voltage levels are unknown or unpredictable before T 1  for VDD, before T 2  for POR, and before T 4  for A, B, and PAD. After T 5 , the device and method described herein ensure that the input buffer circuit (e.g.  130 ) is in a known state following the initialization event. 
       FIG. 4  illustrates an embodiment of a timing diagram for operating the architecture including the second voltage holding circuit of  FIGS. 1 and 2  using the methods described herein. As will be understood the timing diagram of  FIG. 4  is simplified and not necessarily to scale. 
     The sequence begins at time T 1  in response to an initialization event. In the illustrated example, the initialization event is a power-on event during which the internal circuitry  140  generates a power-on reset “POR” signal in response to the application of power to the integrated circuit device  100 . More generally, the initialization event may be any other event which could lead to an indeterminate floating voltage on the pad, for which a signal is generated internally or externally to begin the sequence. 
     During the power-on process, the POR signal is set to a high state at time T 2  by the internal circuitry  140 . Following the power-on process the POR signal is returned to a low state at time T 3 . 
     At time T 4 , control signal C is set to a high state, turning on the pull-down circuit  230  to set the second voltage level at the pad  102  with a first current. At time T 5 , control signal D is set to a high state, turning on the pull-down circuit  240  to hold the voltage level at the pad  102  with a second current, while control signal C is set to a low state, turning off the pull-down circuit  230 . 
     Voltage levels are unknown or unpredictable before T 1  for VDD, before T 2  for POR, and before T 4  for A, B, and PAD. After T 5 , the device and method described herein ensure that the input buffer circuit (e.g.  130 ) is in a known state following the initialization event. 
       FIG. 5  is a flow chart of a method  500  for biasing the pad  102 . The method  500  begins at step  510  in response to an initialization event. The initialization event may be, for example, a power-up event of the device  100 , or any other event which could lead to an indeterminate floating voltage on the pad  102 . If a state register is programmed with a state indicating a voltage level to set for the pad (step  510 ), then the pad can be forced to the voltage level in two steps. At step  520 , the voltage level is set at the pad with a first current, and at step  530 , the voltage level at the pad is held with a second current. The second current is weaker than the first current, and is sufficiently weak such that the voltage level held at the pad is overridable by the external signal. The voltage level corresponds to a logic low level or a logic high level. If the voltage level is not forced to such a voltage level, an indeterminate floating voltage can remain on the pad  102 . 
       FIG. 6  illustrates a plurality of pull-up state registers for a plurality of pads in an integrated circuit device. As illustrated in the example of  FIG. 6 , pull-up state registers  0 - 7  correspond to pads  0 - 7  adapted to receive respective external signals or signals from output buffer circuits in the integrated circuit device. Pull-up state registers  0 - 5  are programmed with a pull-up enable state that indicates to set a voltage level corresponding to a logic high level for respective pads  0 - 5  in response to an event, such as a POR event, that causes initialization of the circuitry responsive to the external signal. Pull-up state registers  6 - 7  are programmed with a pull-up off state, so a voltage level corresponding to a logic high level is not to be set for respective pads  6 - 7  in response to the event. 
       FIG. 7  illustrates a plurality of pull-down state registers for a plurality of pads in an integrated circuit device. As illustrated in the example of  FIG. 7 , pull-down state registers  0 - 7  correspond to pads  0 - 7  adapted to receive respective external signals or signals from output buffer circuits in the integrated circuit device. Pull-down state registers  0 - 5  are programmed with a pull-down enable state that indicates to set a voltage level corresponding to a logic low level for respective pads  0 - 5  in response to an event, such as a POR event, that causes initialization of the circuitry responsive to the external signal. Pull-down state registers  6 - 7  are programmed with a pull-down off state, so a voltage level corresponding to a logic low level is not to be set for respective pads  6 - 7  in response to the event. 
     If the pull-up state register for a pad is not set to the pull-up enable state, the pull-down state register for the pad is not set to the pull-down enable state, and the pad is not being driven to a predictable voltage by external drivers or output buffer circuits in the integrated circuit device, then the pad remains “floating” after the initialization of circuitry responsive to the external signal. 
     While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will readily occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims.