Patent Publication Number: US-6708294-B1

Title: Cache memory apparatus and computer readable recording medium on which a program for controlling a cache memory is recorded

Description:
This application is a continuation in part of Ser. No. 09/531,014 Mar. 20, 2000 now U.S. Pat. No. 6,546,501. 
    
    
     FIELD OF THE INVENTION 
     The present invention relates to a cache memory apparatus having a plurality of cache memories and a computer readable recording medium on which a program for controlling the cache memory is recorded thereon. More particularly, this invention relates to a cache memory apparatus being capable of avoiding system down caused by occurrence of a parity error and a computer readable recording medium on which a program for controlling the cache memory is recorded thereon. 
     BACKGROUND OF THE INVENTION 
     With the popularization of personal computers, high-speed performance is further demanded. Accordingly, systems each comprising a cache memory apparatus constituted by a plurality of cache memories to achieve high-speed access are popularly used. On the other hand, since an amount of processing performed by a computer increases, emphasis is required to be given on the improvement in reliability of such systems. It is also desired that the system continues to operate without stopping the system even if a minor failure occurs. 
     FIG. 28 is a block diagram showing the configuration of a conventional cache memory apparatus. Th e cache memory apparatus shown in FIG. 28 comprises a multiple cache memory (primary cache memory  13  and secondary cache memory  14 ) to eliminate a difference in the processing speed between a CPU (Central Processing Unit)  11  and a main memory device  16 . The CPU  11  accesses the primary cache memory  13 , the secondary cache memory  14 , or the main memory device  16  to read/write data. The main memory device  16  is a hard disk drive for example. The main memory device  16  has, as characteristic features, a large capacity and an access time which is longer than that of the primary cache memory  13  or the secondary cache memory  14 . All the data that is used by the CPU  11  is stored in the main memory device  16 . 
     The primary cache memory  13  and the secondary cache memory  14  are SRAMs (Static Random Access Memories) for example, and has, as characteristic features, an access time which is shorter than that of the main memory device  16 . The primary cache memory  13  also has, as characteristic features, an access time which is shorter than that of the secondary cache memory  14 . More specifically, of the primary cache memory  13 , the secondary cache memory  14 , and the main memory device  16 , the primary cache memory  13  has the shortest access time, the secondary cache memory  14  has an access time which is longer than that of the primary cache memory  13 , and the main memory device  16  has the longest access time. In addition, with respect to a memory capacity, the memory capacity of the main memory device  16  is largest, the memory capacity of the secondary cache memory  14  is second largest, and the memory capacity of the primary cache memory  13  is the smallest. 
     Data transmission between a CPU and a cache memory (main memory device) is generally performed in units of lines. Several methods are available which allow data on the main memory device to correspond to lines in the cache memory. As a typical method, the following set associative method is known. That is, the main memory device and the cache memory are divided into a plurality of sets (set of lines: called way), and data on the main memory device can be placed on determined lines in the way. The set associative method including N ways is called an N-way set associative method. A method in which a cache memory is handled as one way is called a direct mapping method (or one-way set associative method). 
     The primary cache memory  13  stores a part of the data stored in the main memory device  16 , and is a memory using a 4-way set associative method as shown in FIG.  30 . As shown in FIG. 30, primary cache memory  13  is constituted by a primary tag RAM  13   a  for holding addresses A, B, C, and D or the like of data a, b, c, and d or the like, and a primary data RAM  13   b  for holding the data a, b, c, and d or the like. The primary tag RAM  13   a  and the primary data RAM  13   b  are divided into a plurality of ways to be managed. The way of the primary tag RAM  13   a  and the way of the primary data RAM  13   b  correspond to each other in a one-to-one relationship. For example, the address A held in a unit (to be referred to as an entry) constituting way  0  in the primary tag RAM  13   a  and the data a held in the entry of way  0  in the primary data RAM  13   b  correspond to each other in a one-to-one relationship. 
     The secondary cache memory  14  is a memory for storing part of data held in the main memory device  16 . This secondary cache memory  14  uses a direct mapping method. As shown in FIG. 30, the secondary cache memory  14  is constituted by a secondary tag RAM  14   a  for holding tag information consisting of an address ADR, an INCL bit, and a way WAY, and a secondary data RAM  14   b  for holding the real data. The address ADR represents the address of data held in the secondary data RAM  14   b . The INCL bit represents whether corresponding data is held in the primary data RAM  13   b  or not. The INCL bit is “1” if the data is held in the primary data RAM  13   b , and it is “0” if no data is held in the primary data RAM  13   b . The way WAY represents the number of a way in the primary cache memory  13  in which the corresponding data is held. 
     Referring again to FIG. 28, a primary cache access control device  12  controls access from the CPU  11  to the primary cache memory  13 , and compares the address of data to be read with an address of the primary tag RAM  13   a  according to a read request from the CPU  11 . When the addresses are equal to each other (this state is called cache hit), the primary cache access control device  12  performs control or the like to read the data corresponding to the address. On the other hand, when the addresses are not equal to each other (this state is called cache miss), the primary cache access control device  12  performs control to access the secondary cache memory  14 . A secondary cache access control device  15  controls access from the CPU  11  to the secondary cache memory  14 , and compares the address of data to be read with an address of the secondary tag RAM  14   a . In case of cache hit, the secondary cache access control device  15  performs control or the like to read the data corresponding to the address. In case of cache miss, the secondary cache access control device  15  performs control or the like to access the main memory device  16 . 
     Operation of a conventional cache memory apparatus will be explained below with reference to FIG. 28, FIG. 30, and the flow chart shown in FIG.  29 . In step SA 1  shown in FIG. 29, the primary cache access control device  12  checks whether a read request is generated by the CPU  11 . If the check result is “No”, this check is repeated. The read request is a request that data should be read from the primary cache memory  13 , the secondary cache memory  14  or the main memory device  16 . 
     For example, when a read request for requesting that the data e of the address E shown in FIG. 30 should be read is generated by the CPU  11 , the primary cache access control device  12  sets the check result in step SA 1  as “Yes”. In this manner, in step SA 2 , the primary cache access control device  12  accesses the primary cache memory  13  (r 1  in FIG. 30) to compare the address E with an address held in the primary tag RAM  13   a . 
     In step SA 3 , the primary cache access control device  12  checks whether the address E is present in the primary tag RAM  13   a  or not, i.e., whether cache hit is established or not. In this case, since the address E is not present in the primary tag RAM  13   a , the primary cache access control device  12  determines cache miss (r 2  in FIG. 30) to set the check result in step SA 3  in “No”. If the check result in step SA 3  is “Yes”, in step SA 4 , the CPU  11  reads a data corresponding to the address E from the primary data RAM  13   b.    
     In step SA 5 , the secondary cache access control device  15  accesses the secondary cache memory  14  (r 1  in FIG.  30 ). In step SA 6 , the secondary cache access control device  15  checks whether an INCL bit of “1” exists in the secondary tag RAM  14   a . In this case, since the INCL bit of the address D is “1”, the secondary cache access control device  15  sets the check result in step SA 6  in “Yes” and then shifts the process to step SA 7 . When the INCL bit of “1” does not exist in the secondary tag RAM  14   a , the secondary cache access control device  15  considers the check result in step SA 6  as “No”. 
     Since the INCL bit and the way are “1” and “3” respectively, with respect to the address D in the secondary cache memory  14 , it is understood that the latest data d of the address D is held in way  3  in the primary data RAM  13   b . Data d′ corresponding to the address D in the secondary data RAM  14   b  is a data that is older than the data d, and it is the data that must be updated. 
     In step SA 7 , the secondary cache access control device  15  writes back the data of the corresponding address in the primary cache memory  13  to the secondary cache memory  14 . More specifically, in this case, the secondary cache access control device  15  writes back the data d (latest data) existing in the primary data RAM  13   b  to a region corresponding to the address D in the secondary data RAM  14   b  with reference to the address D existing in way  3  of the primary tag RAM  13   a  (r 3  in FIG.  30 ). In this manner, the data d′ (old data) corresponding to the address Din the secondary data RAM  14   b  is updated to the data d (latest data). 
     In step SA 8 , the secondary cache access control device  15  checks whether an address E exists in the secondary tag RAM  14   a  or not, i.e., whether cache hit is established or not. In this case, since the address E exists in the secondary tag RAM  14   a , the secondary cache access control device  15  considers the check result in step SA 8  as “Yes”. In the next step SA 9 , the CPU  11  reads data e corresponding to the address E from the secondary data RAM  14   b . The secondary cache access control device  15  moves the read data e and the address E of the data e from the secondary cache memory  14  into the primary cache memory  13  (r 4  in FIG.  30 ). 
     When some data exists in the secondary cache memory  14 , and that data does not exist in the primary cache memory  13 , the data is moved from the secondary cache memory  14  into the primary cache memory  13  to shorten an access time for the data next time. In this case, the secondary cache access control device  15  updates the address D of way  3  in the primary tag RAM  13   a  to the address E in the secondary tag RAM  14   a . Similarly, the secondary cache access control device  15  updates the data d of way  3  in the primary data RAM  13   b  to the data e in the secondary data RAM  14   b.    
     On the other hand, if the check result in step SA 8  is “No”, the CPU  11  accesses the main memory device  16  in step SA 10 . In step SA 11 , the CPU  11  reads the data corresponding the address E from the main memory device  16 . In this manner, in the conventional cache memory apparatus, when data corresponding to a certain address is to be read, the CPU  11  accesses the primary cache memory  13 , then the secondary cache memory  14 , and finally the main memory device  16 . 
     As described above, in the conventional cache memory apparatus, as shown in FIG. 30, at a certain timing, the data d (latest data) held in the primary cache memory  13  (primary data RAM  13   b ) is written back to the secondary cache memory  14  (secondary data RAM  14   b ), so that the data d′ (old data) is updated to the latest data. In this case, the data d is written back to the region of the address D in the secondary cache memory  14  with reference to the address D of the data d in the primary tag RAM  13   a.    
     Recently, in answer to the demand for reduction in size and high-density storage, integrated circuits each having a high degree of integration have been frequently used as the memory elements in the primary cache memory  13  and the secondary cache memory  14 . In such an integrated circuit having a high degree of integration, since the constituent parts of the circuit are minute, it is known that, in addition to a hardware error which is a fixed failure such as disconnection of the circuit itself, a failure called a software error occurs. This software error is a phenomenon in which bits are inverted at random due to a small radiation from a very minute radiation source contained in the package of the integrated circuit that envelops the memory elements. 
     In this manner, in case of write back, when the software error occurs in the address D of the primary tag RAM  13   a  shown in FIG. 30, an address to which the data is written back becomes unknown. Therefore, data d cannot be written back to the region of the address D in the secondary cache memory  14 . In this case, a serious failure that causes immediate system down occurs, and the reliability of the apparatus is degraded. In particular, since the degrees of integration of circuits is increasing every year, the probability of occurrence of the software errors is also increasing. An effective solution to the problem is earnestly desired. 
     SUMMARY OF THE INVENTION 
     It is an object of this invention to provide a cache memory apparatus capable of avoiding system down and capable of improving the reliability of the apparatus, and a computer readable recording medium on which a program for controlling the cache memory is recorded thereon. 
     The cache memory apparatus according to one aspect of the present invention comprises a primary cache memory having at least one way, which way having at least one entry; an error detection unit which detects an error in an entry of the way; a secondary cache memory which holds data, a registration position information and a status information of data in said first cache memory; a replace prohibition unit which, when error is detected in an entry of a way by said error detection unit, prohibits that particular way from being replaced; a write back unit which, when an error is detected in an entry of a way by said error detection unit, writes back the data held in that particular entry of the way in said primary cache memory to an entry of said secondary cache memory; a release unit which releases the prohibition of replacement of that particular way of said primary cache memory upon completion of the write back operation by said write back unit; and a write unit which, when the entry of said secondary cache memory is accessed, writes the data which is written back in the entry in said primary cache memory. 
     According to the above invention, when a parity error occurs in the entry of the primary cache memory, the way including the entry in which the error is detected is prohibited by the replace prohibition unit from being replaced, and the data held in the entry is written back to the entry of the secondary cache memory by the write back unit. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the prohibition of replacement is released by the release unit, and the data which is written back is written in the entry of the primary cache memory by the write unit, so that the status before the parity error occurs is set. 
     Thus, when a parity error occurs, after the data is written back from the primary cache memory to the secondary cache memory, the data is written from the secondary cache memory into the primary cache memory. Thus, even if a parity error occurs, the data can be normally read from the secondary cache memory. Therefore, according to the present invention of the first aspect, even if a parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is improved. 
     The cache memory apparatus according to another aspect of the present invention comprises a primary cache memory having at least one way, which way having at least one entry; an error detection unit which detects an error in an entry of the way; a secondary cache memory which holds data, a registration position information and a status information of data in said first cache memory; a replace prohibition unit which, when error is detected in an entry of a way by said error detection unit, prohibits that particular entry of the way from being replaced; a write back unit which, when error is detected in an entry of a way by said error detection unit, writes back the data held in that particular entry of the way in said primary cache memory to an entry of said secondary cache memory; a release unit which releases the prohibition of replacement of that particular entry of the way in said primary cache memory upon completion of the write back operation by said write back unit; and a write unit which, when the entry of said secondary cache memory is accessed, writes the data which is written back in the entry in said primary cache memory. 
     According to the above invention, when a parity error occurs in the entry of the primary cache memory, the entry in which the error is detected is prohibited by the replace prohibition unit from being replaced, and the data held in the entry is written back to the entry of the secondary cache memory by the write back unit. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the prohibition of replacement is released by the release unit, and the data which is written back is written in the entry of the primary cache memory by the write unit, so that the status before the parity error occurs is set. 
     Thus, when a parity error occurs, after the data is written back from the primary cache memory to the secondary cache memory, the data is written from the secondary cache memory into the primary cache memory. Therefore, even if a parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is improved. Further, since an object to be prohibited from being replaced is narrowed to the entry, another entry which can be used in this way is not prohibited from being accessed. 
     Further, a write back operation is performed at the moment an error is detected by the error detection unit. Therefore, a period of time extending from when a parity error occurs to when the status before the parity error occurs in the primary cache memory can be shortened. 
     Further, a write back operation is performed at any timing after the error is detected by the error detection unit. Therefore, when the parity error occurs, the parity error does not adversely affect access to another entry pending. 
     The cache memory apparatus according to still another aspect of the present invention comprises a primary cache memory having a plurality of entries; an auxiliary memory having a plurality of entries whose bit fields are equal to those of entries in said primary cache memory; an error detection unit which detects an error in an entry of said primary cache memory; a secondary cache memory which holds data, a registration position information and a status information of data in said first cache memory; an auxiliary memory selection unit which, when an error is detected in an entry of said primary cache memory, makes a corresponding entry in said auxiliary memory valid in place of the entry of said primary cache memory in which the error has occurred; a write back unit which, when an error is detected in an entry of said primary cache memory, writes back the data held in that particular entry of said primary cache memory to an entry of said secondary cache memory; and a write unit which writes the data which is written back in an entry in said auxiliary memory upon completion of the write back operation by said write back unit. 
     According to the present invention of the above aspect, when an error in the entry of the primary cache memory is detected by the error detection unit, an auxiliary memory is selected by the auxiliary memory selection unit in place of the entry. The data held in the entry is written back to the entry of the secondary cache memory by the write back unit. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the data which is written back is written in the entry in the auxiliary memory by the write unit. 
     Thus, when a parity error occurs in the entry of the primary cache memory, the auxiliary memory is used as a backup in place of the entry. Therefore, the cache memory apparatus can be operated as if no parity error occurs. 
     The present invention according to still another aspect provides a computer readable recording medium on which a program for controlling a cache memory is recorded thereon, which program causes a computer to execute an error detection step of detecting an error in an entry of a way of a primary cache memory, which primary cache memory having at least one way, and which way having at least one entry; a replace prohibition step of, when an error is detected in an entry of a way in the error detection step, prohibiting that particular way from being replaced; a write back step of, when an error is detected in an entry of a way in the error detection step, writing back the data held in that particular entry of the way in said primary cache memory to an entry of a secondary cache memory, which secondary cache memory holds data, registration position information and status information of data in said primary cache memory; a release step of releasing the prohibition of replacement of that particular way of said primary cache memory upon completion of the write back operation in the write back step; and a write step of, when the entry of said secondary cache memory is accessed, writing the data which is written back in the entry in said primary cache memory. 
     According to the above invention, when a parity error occurs in the entry of the primary cache memory, the way including the entry in which the error is detected is prohibited by the replace prohibition step from being replaced, and the data held in the entry is written back to the entry of the secondary cache memory by the write back step. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the prohibition of replacement is released in the release step, and the data which is written back is written in the entry of the primary cache memory in the write step, so that a status before the parity error occurs is set. 
     Thus, when a parity error occurs, data is written back from the primary cache memory to the secondary cache memory and then written from the secondary cache memory in the primary cache memory. For this reason, even if the parity error occurs, the data can be normally read from the secondary cache memory. Therefore, even if a parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is improved. 
     The present invention according to still another aspect provides a computer readable recording medium on which a program for controlling a cache memory is recorded thereon, which program causes a computer to execute an error detection step of detecting an error in an entry of a way of a primary cache memory, which primary cache memory having at least one way, and which way having at least one entry; a replace prohibition step of, when an error is detected in an entry of a way in the error detection step, prohibiting that particular entry from being replaced; a write back step of, when an error is detected in an entry of a way in the error detection step, writing back the data held in that particular entry of the way in said primary cache memory to an entry of a secondary cache memory, which secondary cache memory holds data, registration position information and status information of data in said primary cache memory; a release step of releasing the prohibition of replacement of that particular entry of said primary cache memory upon completion of the write back operation in the write back step; and a write step of, when the entry of said secondary cache memory is accessed, writing the data which is written back in the entry in said primary cache memory. 
     According to the above invention, when a parity error occurs in the entry of the primary cache memory, the entry in which the error is detected is prohibited by the replace prohibition step from being replaced, and the data held in the entry is written back to the entry of the secondary cache memory by the write back step. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the prohibition of replacement is released by the release step, and the data which is written back is written in the entry of the primary cache memory by the write step, so that a status before the parity error occurs is set. 
     Thus, when a parity error occurs, data is written back from the primary cache memory to the secondary cache memory and then written from the secondary cache memory in the primary cache memory. For this reason, even if the parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is improved. Therefore, since an object to be prohibited from being replaced is narrowed to the entry, another entry which can be used in this way is not prohibited from being accessed. 
     The present invention according to still another aspect provides a computer readable recording medium on which a program for controlling a cache memory is recorded thereon, which program causes a computer to execute an error detection step of detecting an error in an entry of a primary cache memory, which primary cache memory having a plurality of entries; an auxiliary memory selection step of, when an error is detected in the error detection step, making an auxiliary memory valid in place of the entry of said primary cache memory in which the error has occurred, which auxiliary memory having a plurality of entries whose bit fields are equal to those of entries in said primary cache memory; a write back step of, when an error is detected in the error detection step, writing back the data held in that particular entry in said primary cache memory to an entry of a secondary cache memory, which secondary cache memory holds data, a registration position information and a status information of data in said first cache memory; and a write step of writing the data which is written back in an entry in said auxiliary memory upon completion of the write back operation in the write back step. 
     According to the above invention, when an error in the entry of the primary cache memory is detected in the error detection step, an auxiliary memory is selected in the auxiliary memory selection step in place of the entry. The data held in the entry is written back to the entry of the secondary cache memory in the write back step. In this manner, data obtained before the parity error occurs is held in the secondary cache memory. Upon completion of the write back operation, the data which is written back is written in the entry in the auxiliary memory in the write step. 
     Thus, when a parity error occurs in the entry of the primary cache memory, the auxiliary memory is used as a backup in place of the entry. Therefore, the cache memory apparatus can be operated as if no parity error occurs. 
     The cache memory apparatus according to still another aspect of the present invention comprises a primary cache memory having at least one way; an error detection unit for detecting errors in entries constituting the way of the primary cache memory; a secondary cache memory for storing registration position information and status information of the data in the primary cache memory; an access prohibition unit for prohibiting an access to the primary cache memory when an error is detected by the error detection unit; a write-back unit for accessing every entry of the secondary cache memory in which the data corresponding to an entry where an error occurs may be present when the error is detected and writing back the data stored in a concerned entry of the primary cache memory to an entry of the secondary cache memory in accordance with the registration position information and register status information; a restoration unit for restoring an entry in which an error is detected to a state free from error after the write-back is completed when the status information for the entry in which the above error is detected is an error and invalid; and a release unit for releasing prohibition of an access to the primary cache memory after the write-back is completed. 
     According to the above invention, when an error occurs in an entry of the primary cache memory, an access to the primary cache memory is prohibited. Therefore, an access does not occur after the error occurs. In this case, though the data in an entry in which the error occurs is lost, the registration position information and status information of the data in the primary cache memory and data are stored in the secondary cache memory. Then, every entry of the secondary cache memory in which the data corresponding to the entry in which an error occurs may be present is accessed and thereafter, data is written back from the primary cache memory to the secondary cache memory. 
     Then, when the status information for the entry in which an error is detected is an error and invalid, the entry in which an error is detected after write-back is completed is restored to a state free from error. Then, after the write-back is completed, prohibition of an access to the primary cache memory is released by the release unit. 
     Thus, according to the above invention, when an error occurs in an entry of the primary cache memory, an access to the primary cache memory is prohibited and the entry is restored to a state free from error by the restoration unit after writing back. Therefore, it is possible to avoid a trouble of detecting another error while eliminating the above error and moreover, avoid system down and improve the reliability of the apparatus. 
     The cache memory apparatus according to still another aspect of the present invention comprises a primary memory having at least one way; multi-hit error detection unit for detecting multi-hit errors in entries constituting the way of the primary cache memory; a secondary cache memory for storing registration position information and status information of the data in the primary cache memory; an access prohibition unit for prohibiting an access to the primary cache memory when a multi-hit error is detected by the multi-hit error detection unit; a write-back unit for accessing every entry of the secondary cache memory in which the data corresponding to an entry where a multi-hit error occurs may be present when the multi-hit error is detected and writing back the data stored in a concerned entry of the primary cache memory to an entry of the secondary cache memory in accordance with the registration position information and status information; a restoration unit for restoring an entry in which a multi-hit error is detected to a state free from multi-hit error after the write-back is completed when the status information for the entry in which the multi-hit error is detected is a multi-hit error and invalid; and a release unit for releasing prohibition of an access to the primary cache memory after the write-back is completed. 
     Thus, according to the above invention, when a multi-hit error occurs in an entry of the primary cache memory, an access to the primary cache memory is prohibited and write-back is performed so as to restore the entry to a state free from multi-hit error by the restoration unit. Therefore, it is possible to avoid a trouble of detecting another error while eliminating the above multi-hit errors, avoid system down, and improve the reliability of the apparatus. 
    
    
     Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram showing the configuration of a first embodiment according to the present invention. 
     FIG. 2A to FIG. 2J are diagrams showing various data structures in first and second embodiments. 
     FIG. 3 is a block diagram showing the configuration of a replace way selection circuit  106  shown in FIG.  1 . 
     FIG. 4 is a block diagram showing the configuration of an empty way selection circuit  106   a  shown in FIG.  3 . 
     FIG. 5 is a truth table of a priority selector  106   c  shown in FIG.  4 . 
     FIG. 6 is a block diagram showing the configuration of an ejection way selection circuit  106   f  shown in FIG.  3 . 
     FIG. 7 is a table showing the order of bit priority in priority selectors  106   h  to  106   k  shown in FIG.  6 . 
     FIG. 8 is a flow chart for explaining the operation of the first embodiment. 
     FIG. 9 is a diagram for explaining an operation performed in the first embodiment when a parity error occurs. 
     FIG. 10 is a diagram for explaining a recovery process in the first embodiment. 
     FIG. 11 is a diagram for explaining a completion process of an interrupt routine in the first embodiment. 
     FIG. 12 is a diagram for explaining an operation after the operation returns to a normal operation in the first embodiment. 
     FIG. 13 is a diagram for explaining an operation in the first embodiment when a parity error occurs. 
     FIG. 14 is a diagram for explaining an operation in the first embodiment when a parity error occurs. 
     FIG. 15 is a flow chart for explaining the operation of a modification of the first embodiment. 
     FIG. 16 is a block diagram showing the configuration of a second embodiment according to the present invention. 
     FIG. 17 is a flow chart for explaining the operation of the second embodiment. 
     FIG. 18 is a block diagram showing a configuration of the third embodiment of the present invention; 
     FIG. 19A to FIG. 19E are illustration showing various data structures of the third embodiment; 
     FIG. 20 is a block diagram showing a configuration of the parity-error elimination control circuit  324  shown in FIG. 18; 
     FIG. 21 is a flowchart for explaining operations of the third embodiment; 
     FIG. 22 is an illustration for explaining operations of the third embodiment when a parity error occurs; 
     FIG. 23 is an illustration for explaining operations of the third embodiment for eliminating a parity error; 
     FIG. 24 is a flowchart for explaining operations of the fourth embodiment of the present invention; 
     FIG. 25 is an illustration for explaining operations of the fourth embodiment when a multi-hit error occurs; 
     FIG. 26 is an illustration for explaining operations of the fourth embodiment for eliminating a multi-hit error; 
     FIG. 27 is a block diagram showing a modification of the first to fourth embodiments; 
     FIG. 28 is a block diagram showing a configuration of a conventional cache memory apparatus; 
     FIG. 29 is a flowchart for explaining write-back in a cache memory apparatus; and 
     FIG. 30 is an illustration for explaining operations a conventional cache memory apparatus. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Two preferred embodiments of a cache memory apparatus according to the present invention and a computer readable recording medium, on which a program for controlling the cache memory is recorded thereon, according to the present invention are explained below with reference to the accompanying drawings. 
     FIG. 1 is a block diagram showing the configuration of a cache memory apparatus according to the first embodiment of to the present invention. The cache memory apparatus shown in FIG. 1 comprises a multiple cache memory (primary cache memory  102  and secondary cache memory  110 ) to eliminate a difference in the processing speed between a CPU  101  and a main memory device  112  in the same manner as in the prior art. The CPU  101  accesses the primary cache memory  102 , the secondary cache memory  110 , or the main memory device  112  to read/write data. The main memory device  112  is a hard disk drive, for example, and has, as characteristics, a large capacity and an access time which is longer than that of the primary cache memory  102  or the secondary cache memory  110 . All data used in the CPU  101  are stored in the main memory device  112 . 
     The primary cache memory  102  and the secondary cache memory  110  are SRAMs, for example. The primary cache memory  102  and the secondary cache memory  110  have, as characteristics, access times which are shorter than the access time of the main memory device  112 . The primary cache memory  102  also has, as characteristics, an access time which is shorter than the access time of the secondary cache memory  110 . More specifically, of the primary cache memory  102 , the secondary cache memory  110 , and the main memory device  112 , the primary cache memory  102  has the shortest access time, the secondary cache memory  110  has an access time which is second shortest, and the main memory device  112  has the longest access time. Regarding the memory capacity, the memory capacity of the main memory device  112  is largest, the memory capacity of the secondary cache memory  110  is second largest, and the memory capacity of the primary cache memory  102  is smallest. 
     The primary cache memory  102  stores a part of the data stored in the main memory device  112 , and is a memory using a 4-way set associative method as shown in FIG.  9 . The primary cache memory  102  is constituted by a primary tag RAM  102   a  and a primary data RAM  102   b  in the same manner as the primary cache memory  13  (see FIG.  21 ). The primary tag RAM  102   a  has a capacity of 4 ways×256×64 bytes. A tag information shown in FIG. 2A is held in the entries of the primary tag RAM  102   a , respectively. In FIG. 2A, a status STATUS is information representing the status of data held in the primary data RAM  102   b , and this status STATUS denotes one of M (Modified), C (Clean), and I (Invalid) shown in FIG.  2 B. Status M denotes that the data is valid and that the data is updated one. Further, when the status is M it denotes that the data are not equal to data held in a secondary data RAM  110   b  corresponding to the data. In this case, the data held in the primary data RAM  102   b  must be written back to the secondary data RAM  110   b.    
     Status C denotes that the data held in the primary data RAM  102   b is valid and that the data is not updated one. Further, when the status is C it denotes that the data is equal to data held in the secondary data RAM  110   b  corresponding to the data. Therefore, a write back operation need not be performed. Status I denotes that the corresponding entry is unused and that the data held in the primary data RAM  102   b  is invalid one. 
     Referring again to FIG. 2A, a parity bit SP is an odd-number parity bit added to the status STATUS, and is used to check whether a parity error occurs in the status STATUS or not by the odd-number parity check method. Address ADR is an address of data held in the primary data RAM  102   b . A parity bit AP is an odd-number parity bit added to the address ADR, and is used to check whether a parity error occurs in the address ADR by the odd-number parity check method. 
     A model of the primary cache memory  102  is shown in FIG.  9 . As shown in FIG. 9, the primary cache memory  102  holds data a, b, c, and d or the like and addresses A, B, C, and D or the like (corresponding to the address ADR in FIG. 2A) corresponding to the data a, b, c, and d in the same manner as the primary cache memory  13  (see FIG.  21 ). FIG. 9 shows only the address ADR of the tag information shown in FIG.  2 A. The primary tag RAM  102   a  and the primary data RAM  102   b  are managed such that each of the primary tag RAM  102   a  and the primary data RAM  102   b  is divided into ways  0  to  3 . The ways of the primary tag RAM  102   a  and the ways of the primary data RAM  102   b  correspond to each other in a one-to-one relationship. For example, address A held in an entry constituting way  0  in the primary tag RAM  102   a  and data a held in an entry of way  0  in the primary data RAM  102   b  correspond to each other in a one-to-one relationship. 
     Referring again to FIG. 1, a tag parity error detection circuit  103  is a circuit for detecting a parity error of tag information in the accessed primary tag RAM  102   a . More specifically, when a parity error is detected in the status STATUS or the address ADR shown in FIG. 2A, the tag parity error detection circuit  103  makes a parity error signal active, and the tag parity error detection circuit  103  outputs the way number of an entry in which a parity error occurs and the information of the corresponding address to a tag parity error log register  104  and a primary cache hit determination circuit  105 . The tag parity error log register  104  is a register for holding information related to the error shown in FIG. 2C when a parity error is detected by the tag parity error detection circuit  103 . 
     In FIG. 2C, a mode MODE is a flag representing the mode of the apparatus. When the mode is a parity error mode, “1” is set. When the mode is a normal operation mode, “0” is set. A way WAY is the number of a way having an entry in which a parity error occurs in the primary tag RAM  102   a , and the address ADR is the address of the entry in which the parity error occurs. FIG. 9 shows, as an example, the address ADR (address: 0101) and the way WAY (way:  3 ). When the mode changes from the parity error mode to the normal operation mode, the tag parity error log register  104  is cleared under the control of the CPU  101 . 
     Referring again to FIG. 1, the primary cache hit determination circuit  105  is a circuit for checking whether an address related to a read request from the CPU  101  exists in the primary tag RAM  102   a  or not. When the address exists in the primary tag RAM  102   a , the primary cache hit determination circuit  105  makes a cache hit signal related to the way active. The primary cache hit determination circuit  105  accesses an entry in which a parity error occurs because of the tag parity error detection circuit  103  and an entry on an (error) way WAY held in the tag parity error log register  104 , the primary cache hit determination circuit  105  suppresses the cache hit signal from being output. When cache hit of a way WAY n  is represented by HIT n , the cache hit signal is expressed by the following theoretical equation: 
     
       
         HIT n =(READ·ADR_MATCH n ·(MCI_C n +MCI_M n )+WRITE·ADR_MATCH n ·MCI_M n )·#PE_WAY n ·#(ADR_PE n +MCI_PE n ) 
       
     
     where “#” represents negation and the other symbols have meaning as follows. 
     
       
         
           
               
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 READ 
                 : 
                 cache read 
               
               
                   
                 WRITE 
                 : 
                 cache write 
               
               
                   
                 ADR_MATCH 
                 : 
                 address of WAY n  is matched 
               
               
                   
                 MCI_C n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is C 
               
               
                   
                 MCI_M n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is M 
               
               
                   
                 ADR_PE n   
                 : 
                 address ADR (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is parity error 
               
               
                   
                 MCI_PE n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is parity error 
               
               
                   
                 PE_WAY n   
                 : 
                 number of way WAY (error) held in 
               
               
                   
                   
                   
                 tag parity error log register 104 
               
               
                   
                   
               
               
                   
                 n = 0, 1, 2, 3  
               
            
           
         
       
     
     A replace way selection circuit  106  is a circuit in which, when a new address, data, or the like are written in the entry of a way of the primary cache memory  102  shown in FIG. 9, the corresponding way (called a replace way) is selected. In the replace way selection circuit  106 , a random method for selecting a replace way from a plurality of ways at random is employed. In the replace way selection circuit  106 , a known LRU (Least Recently Used) algorithm is used as another selection method, so that the way of the entry which is accessed at the oldest time may be selected as the replace way. 
     When a plurality of ways include unused ways (empty ways), the replace way selection circuit  106  selects a replace way of the empty ways. When the plurality of ways do not include empty ways, the replace way selection circuit  106  selects a replace way from the plurality of ways at random by the random method. Further, the replace way selection circuit  106  is designed to select a replace way from ways other than a way (called an error way) of an entry in which a parity error occurs. 
     FIG. 3 is a block diagram showing a detailed configuration of the replace way selection circuit  106 . In FIG. 3, an empty way selection circuit  106   a  detects empty ways from a plurality of ways in the primary cache memory  102  and selects one of the empty ways. When the empty way selection circuit  106   a  detects the empty way it outputs an empty way detection signal and outputs the number of the selected empty way as an empty way signal. 
     FIG. 4 is a block diagram showing a detailed configuration of the empty way selection circuit  106   a . The empty way selection circuit  106   a  shown in FIG. 4 is constituted by a NOR circuit  106   b , a priority selector  106   c , an OR circuit  106   d , and an encoder  106   e . To the NOR circuit  106   b , a PRE_VALID_WAY signal, a VALID_WAY signal, and a PE_WAY signal each having a 4-bit configuration are input. The PRE_VALID_WAY signal is a signal representing the number of the way access of which is pending in the primary cache memory  102 . The VALID_WAY signal is a signal representing the number of the way including an entry in which data being valid in the primary cache memory  102  is held. The PE_WAY signal is a signal representing the number of an error way in the primary cache memory  102 . In each of the PRE_VALID_WAY signal, the VALID_WAY signal, and the PE_WAY signal, a bit, corresponding to the way number, of the four bits is “1”. 
     The priority selector  106   c , as shown in FIG. 5, outputs an output signal OUTPUT the most significant bit of which is “1” of bits of “1” in an input signal INPUT from the NOR circuit  106   b , so that one replace way is selected from empty ways. Returning to FIG. 4, the OR circuit  106   d  calculates OR of the input signal INPUT (see FIG. 5) from the NOR circuit  106   b , so that an empty way detection signal is output. The encoder  106   e  converts the output signal OUTPUT (see FIG. 5) from the priority selector  106   c  into a 2-bit empty way signal. The empty way signal represents the number of the selected empty way. 
     Referring again to FIG. 3, an ejection way selection circuit  106   f  is a circuit for selecting one way as an ejection way from a plurality of ways when all the ways in the primary cache memory  102  are in use. FIG. 6 is a block diagram showing a detailed configuration of the ejection way selection circuit  106   f . As shown in FIG. 6, to an AND circuit  106   g , signals obtained by inverting the VALID_WAY signal and the PE_WAY signal each having a 4-bit configuration are input. Output signal from the AND circuit  106   g  is a signal representing the number of a way which can be ejected. Priority selectors  106   h  to  106   k  select one way from ways which can be ejected according to the order of bit priority shown in FIG.  7 . For example, the priority selector  106   h  outputs a signal in which only one bit is made active according to the order of priority, i.e., the third bit, the second bit, the first bit, and the  0 th bit, from output signals (4 bits) from the AND circuit  106   g.    
     In the priority selectors  106   h  to  106   k , as shown in FIG. 7, the order of bit priority is set such that the numbers of the bits which are made active in the same order of priority do not overlap. Four types of signals are generated in the priority selectors  106   h  to  106   k . In the four types of signals, an active bit corresponds to the number of an ejection way. Returning to FIG. 6, encoders  106   l  to  106   o  convert output signals from the priority selectors  106   h  to  106   k  into 2-bit ejection way signals. The ejection way signal represents the number of an ejection way. 
     A selector  106   p  selects one of ejection way signals from the encoders  106   l  to  106   o  at random on the basis of a 2-bit selector signal and outputs the selected ejection way signal. A 2-bit D-FF  106   q  and an adder  106   r  constitute a circuit for generating the select signal. In this circuit, a 2-bit select signal incremented by one by the adder  106   r  is input to the 2-bit D-FF  106   q  at the leading edge of a clock signal CLK, and held data is output as a select signal. Therefore, a select signal incremented by one each time the clock signal rises is input to the selector  106   p . The selector  106   p  selects an ejection way signal corresponding to the select signal from the ejection way signals from the encoders  106   l  to  106   o  each time the select signal is incremented by one. 
     Referring again FIG. 3, a selector  106   s  selects one empty way signal out of the empty way signals output by the empty way selection circuit  106   a  and the ejection way signals from the ejection way selection circuit  106   f  on the basis of the following conditions, and outputs the selected signal as a replace way signal. The conditions are: 
     (1) When an empty way detection signal is input by the empty way selection circuit  106   a , an empty way signal is selected. 
     (2) When an empty way detection signal is not input by the empty way selection circuit  106   a , an ejection way signal is selected. 
     Referring again to FIG. 1, when cache miss is determined in the primary cache hit determination circuit  105 , a secondary cache access control circuit  107  performs control to access the secondary cache memory  110  on the basis of the replace way signal from the replace way selection circuit  106 , an address to be accessed, and the like. The secondary cache memory  110  stores part of data stored in the main memory device  112 , and is a memory using the direct mapping method explained in FIG.  9 . The secondary cache memory  110  has and having a capacity of 16-k entries×64 kbytes. The secondary cache memory  110  is constituted by a secondary tag RAM  110   a  and a secondary data RAM  110   b  in the same manner as the secondary cache memory  14  (see FIG.  21 ). Tag information shown in FIG. 2F is held in the secondary tag RAM  110   a.    
     In FIG. 2F, a status STATUS is information representing the status of data held in the secondary data RAM  110   b , and is one of M (Modified), O (Owned), E (Exclusive), S (Shared), and I (Invalid) shown in FIG.  2 G. Status M denotes a status in which another CPU (not shown) does not hold the data in the secondary data RAM  110   b  and that the data is updated one. Status O denotes a status in which another CPU holds the data in the secondary data RAM  110   b  and that the data is updated one. Status E denotes a status in which another CPU does not hold the data in the secondary data RAM  110   b  and that the data is not updated one. Status S denotes a status in which another CPU holds data in the secondary data RAM  110   b . Status I denotes a status in which the data is invalid one. 
     An INCL bit is a bit representing whether data held in the secondary data RAM  110   b  exists in the primary data RAM  102   b  of the primary cache memory  102  or not. The INCL bit is set to be “1” when the data exists, and the INCL bit is set to be “0” when the data does not exist. A way WAY represents the number of a way of the primary data RAM  102   b  when data held in the secondary data RAM  110   b  is held in the way. An address ADR represents data held in the secondary data RAM  110   b . A parity bit AP is an odd-number parity bit added to the address ADR. FIG. 9 typically shows the secondary cache memory  110  described above. As shown in FIG. 9, in the secondary tag RAM  110   a , addresses A, B, and D (corresponding to the address ADR in FIG. 2F) of data a′, b′, and d′ or the like, the INCL bit, the way WAY, and the like are held. In FIG. 9, information other than the status STATUS of the tag information shown in FIG. 2F is shown. 
     Referring again to FIG. 1, the secondary cache control register  108  is a register in which an instruction (INDEX value) for normally recovering the primary cache memory  102  in which a parity error occurs is set according to the content of the secondary data RAM  110   b . In the secondary cache control register  108 , an INDEX value shown in FIG. 2D is set. The INDEX value is a value for designating an address in the secondary cache memory  110 . When the secondary cache memory  110  is accessed (snooped) by the secondary cache access control circuit  107 , by the secondary cache control register  108 , and another CPU, an arbitration circuit  109  performs access arbitration to give an access right to one of the secondary cache access control circuit  107 , the secondary cache control register  108 , and the CPU. A secondary cache hit determination circuit  111  is a circuit for checking whether an address related to a read request from the CPU  101  exists in the secondary data RAM  110   b . When the address exists in the secondary data RAM  110   b , the secondary cache hit determination circuit  111  makes a cache hit signal related to the way active. 
     The main memory device  112  is a DRAM memory, a hard disk drive or the like for storing all data used in the CPU  101 . A primary cache access control circuit  113  is a circuit for performing control to access the primary cache memory  102 . A primary cache control register  114  is a register in which an instruction (way WAY and INDEX value) for normally recovering the primary cache memory  102  in which a parity error occurs is set. In the primary cache control register  114 , a way WAY and an INDEX value shown in FIG. 2E are set. The way WAY represents the number of the way in the primary cache memory  102 , and the INDEX value is a value for designating the address in the primary tag RAM  102   a.    
     The operation of the first embodiment will be explained here with reference to FIG. 9 to FIG. 14, and the flow chart shown in FIG.  8 . In this case, in the primary tag RAM  102   a  shown in FIG. 9, addresses A to D are held in the addresses of ways  0  to  3 , respectively. Data a to dare held in the primary data RAM  102   b  to correspond to address A to D, respectively. In FIG. 9, the addresses A, B, and D, data a′, b′, and d′ (all of which are old data), INCL bit=“1”, “1”, and “1”, and way WAY=“0”, “1”, and “3” are held in the secondary cache memory  110 . 
     When the CPU  101  outputs a read request for requesting that data e of an address E shown in FIG. 9 should be read, access (p 1  in FIG. 9) to an entry of the primary tag RAM  102   a  is started in step SB 1 . In the next step SB 2 , it is checked whether a parity error is detected by the tag parity error detection circuit  103 . In this case, if it is determined that a parity error has occurred at the address D in way  3  of the primary tag RAM  102   a  shown in FIG. 9 (p 2  in FIG.  9 ), the check result in step SB 2  shall be “Yes”, and an interrupt routine for canceling the parity error is started (p 3  in FIG.  9 ). If no parity error is detected, the check result in step SB 2  shall be “No”. In step SB 3 , as in the conventional cache memory apparatus described above, a normal process in which data is read from the primary cache memory  102 , the secondary cache memory  110 , or the main memory device  112  is performed. 
     When the check result in step SB 2  becomes “Yes”, the mode changes from the normal operation mode to a parity error mode, the processes in steps SB 4  to SB 8  and the processes in step SB 9  to SB 12  are performed in parallel to each other. More specifically, in step SB 4 , the CPU  101  is requested to perform a synchronous trap in synchronism with the change to the parity error mode. In step SB 9 , the numbers of the address D (0101) in which the parity error shown in FIG. 9 has occurred and the number of error way  3  are written in the tag parity error log register  104 . 
     In this manner, in the next step SB 10 , the primary cache hit determination circuit  105  performs control for determining all accesses to entries in which parity errors occur as cache miss. In step SB 11 , the primary cache hit determination circuit  105  determines all accesses to the error way  3  as cache miss. In the next step SB 12 , the replace way selection circuit  106  excludes the error way  3  from ways to be replaced, so that the error way  3  is prohibited from being replaced (p 4  in FIG.  10 ). In the next step SB 13 , it is checked whether the tag parity error log register  104  is cleared or not. If the check result is “No”, the CPU shifts the process to step SB 11 . 
     On the other hand, in step SB 5 , the CPU  101  reads the address D (0101) at which a parity error occurs and the number of the error way  3  are read from the tag parity error log register  104  shown in FIG. 10, and then shifts the process to step SB 6 . In step SB 6 , on the basis of the address D (0101) read in step SB 5 , the CPU  101  calculates the addresses of entries of the secondary cache memory  110  which may use the entry in which the parity error occurs as an INDEX value (instruction). The CPU  101  sequentially sets the addresses in the secondary cache control register  108 . 
     In this manner, in the secondary cache memory  110  shown in FIG. 10, the entry of the address A is accessed for the first time (p 5  in FIG.  10 ). In this case, since the way WAY is “0”, and is different from the error way  3 , this entry is excluded. Similarly, the entry of the address B is accessed f or the second time. However, this entry has a way WAY of “1” which is different from the error way  3 , therefore it is excluded. When the entry of the address D is accessed for the nth time, the way WAY “3” of this entry is equal to the error way  3 , and the INCL bit is “1”. The following process is then performed according to the entry. More specifically, it is requested that data d held in the entry of the error way  3  of the primary data RAM  102   b  show in FIG. 10 should be written back to the secondary data RAM  110   b  (p 6  in FIG.  10 ). 
     The data d held in the entry of the way  3  in the primary data RAM  102   b  shown in FIG. 10 is written back (p 7  in FIG. 10) to the entry corresponding to the address D in the secondary cache memory  110 . More specifically, in this case, the data d′ (old data) held in the entry corresponding to the address D in the secondary cache memory  110  is updated to the data d (latest data). Therefore, the address D and the data d held in the primary cache memory  102  before the parity error occurs are held in the secondary cache memory  110  (see FIG.  11 ). 
     Upon completion of the write back operation, in the secondary tag RAM  110   a , the INCL bit corresponding to the address D is set to be “0” (see FIG.  11 ). In this manner, the address D and the data d held in the secondary cache memory  110  are not also held in the entries of any ways of the primary cache memory  102 . 
     In step SB 7 , the CPU  101  sets “3” as the way WAY shown in FIG.  2 E and sets a value representing the address of the entry as the INDEX value in the primary cache control register  114 . The way WAY  3  is an error way in the primary cache memory  102  shown in FIG. 10, and the INDEX value is a value representing the address of the entry in which the data d is held. In the primary tag RAM  102   a , the status STATUS show in FIG. 2A is set to be “1” (invalid). In this manner, an address held in the entry marked by “x” in the primary tag RAM  102   a  shown in FIG. 11 is set as an invalid address, and data held in the entry marked by “x” in the primary data RAM  102   b  is set as invalid data. Therefore, the entry marked by “x” is in an unused state. 
     In the next step SB 8 , the tag parity error log register  104  is cleared by access performed by the CPU  101  (p 8  in FIG.  11 ). In this manner, in the primary cache hit determination circuit  105 , control for determining access to the error way  3  in the primary cache memory  102  and an entry in which a parity error occurs as cache miss is released. In the replace way selection circuit  106 , prohibition of replace of the error way  3  in the primary cache memory  102  is released (p 9  in FIG.  11 ). When the tag parity error log register  104  is cleared, the check result in step SB 13  becomes “Yes”. The series of interrupt routines are completed, and the normal operation is performed. 
     In the normal operation, an operation performed when the CPU  101  accesses the address D shown in FIG. 12 will be described below with reference to the flow chart shown in FIG.  20 . In step SA 1  shown in FIG. 20, the CPU  101  outputs a read request which requests that the data d of the address D shown in FIG. 12 should be read (p 10  in FIG.  12 ). In this case, in the step SA 2 , the primary cache hit determination circuit  105  accesses the primary cache memory  102  and compares the address D with the address held in the primary tag RAM  102   a  shown in FIG.  12 . 
     In step SA 3 , the primary cache hit determination circuit  105  checks whether the address D exists in the primary tag RAM  102   a  or not, i.e., whether cache hit is established or not. In this case, since the address D does not exist in the primary tag RAM  102   a , the primary cache hit determination circuit  105  determines this state as cache miss (p 11  in FIG.  12 ), and sets the check result in step SA 3  as “No”. 
     In step SA 5 , the secondary cache memory  110  is accessed (p 10  in FIG.  12 ). In step SA 6 , it is checked whether the secondary tag RAM  110   a  has an INCL bit set “1” or not. If the secondary tag RAM  110   a  has an INCL bit of “1”, the write back operation described above is performed in step SA 7 . In the next step SA 8 , the secondary cache hit determination circuit  111  checks whether the address D exists in the secondary tag RAM  110   a  or not, i.e., whether cache hit is established or not. In this case, since the address D exists in the secondary tag RAM  110   a , the secondary cache hit determination circuit  111  sets the check result in step SA 8  as “Yes”. In the next step SA 9 , the data d corresponding to the address D is read from the secondary data RAM  110   b . The read data d and the address D are moved from the secondary cache memory  110  into the primary cache memory  102  (p 12  in FIG.  12 ). 
     This operation is performed for the following reason. That is, when there is data which exists in the secondary cache memory  110  and does not exist in the primary cache memory  102 , the data is moved from the secondary cache memory  110  into the primary cache memory  102  to shorten the access time for the data for the next time. In this case, the address D is moved in the entry of the error way  3  in the primary tag RAM  102   a  shown in FIG. 12, and the data d is moved in the entry of the way  3  in the primary data RAM  102   b . In this manner, the status of the primary cache memory  102  is returned to the status before the parity error in the way  3  occurs. 
     Here, an operation performed when access is performed in a period from when the recovery process shown in FIG. 10 is started to when the interrupt routine shown in FIG. 11 is completed after the parity error occurs in the primary cache memory  102  will be described below with reference to FIG. 13, FIG. 14, and FIG.  20 . FIG. 13 explains a case in which normal access is performed although the address E is accessed after a parity error occurs. Similarly, FIG. 14 explains a case in which a normal access is performed although the address D is accessed after a parity error occurs. 
     First, the case in which the address E is accessed will be described below with reference to FIG.  13  and FIG.  20 . In step SA 1  shown in FIG. 20, the CPU  101  outputs a read request which requests that the data e of the address E shown in FIG. 13 should be read (p 13  in FIG.  13 ). In this case, in the step SA 2 , the primary cache hit determination circuit  105  accesses the primary cache memory  102  and compares the address E with the address held in the primary tag RAM  102   a  shown in FIG.  13 . 
     In step SA 3 , the primary cache hit determination circuit  105  checks whether the address E exists in the primary tag RAM  102   a  or not, i.e., whether cache hit is established or not. In this case, since the address E does not exist in the primary tag RAM  102   a , the primary cache hit determination circuit  105  determines this state as cache miss (p 14  in FIG.  13 ), and sets the check result in step SA 3  as “No”. 
     In step SA 5 , the secondary cache memory  110  is accessed (p 13  in FIG.  13 ). In step SA 6 , it is checked whether the secondary tag RAM  110   a  has an INCL bit set “1” or not. If the check result is “Yes”, it is considered that, for example, a way  1  in the primary cache memory  102  is selected as a replace way in the replace way selection circuit  106 . In this case, attention must be given to the following. That is, since the way  3  is set as a replace prohibition way in the primary cache memory  102 , one way is selected as a replace way from three ways, i.e., ways  0  to  2  other than the way  3  in the replace way selection circuit  106 . Since the INCL bit of an address B in the secondary cache memory  110  is “1”, data b′ (old data) of the address B is written back in step SA 7  (p 15  in FIG.  13 ). 
     More specifically, in step SA 7 , with reference to the address B existing in the way  1  of the primary tag RAM  102   a , the data b (latest data) existing in the primary data RAM  102   b  is written back to the region corresponding to the address B in the secondary data RAM  110   b  (p 15  in FIG.  13 ). In this manner, the data b′ (old data) of the address B in the secondary data RAM  110   b  is updated into the data b (latest data). 
     In the next step SA 8 , the secondary cache hit determination circuit  111  checks whether the address E exists in the secondary tag RAM  110   a  or not, i.e., whether cache hit is established or not. In this case, since the address E exists in the secondary tag RAM  110   a , the secondary cache hit determination circuit  111  sets the check result in step SA 8  as “Yes”. In the next step SA 9 , the data e corresponding to the address E is read from the secondary data RAM  110   b . The read data e and the address E are moved from the secondary cache memory  110  into the primary cache memory  102  (p 16  in FIG.  13 ). In this case, the address E is moved in the entry of the way  1  in the primary tag RAM  102   a  shown in FIG. 13, and the data e is moved in the entry of the way  2  in the primary data RAM  102   b . In this manner, in the first embodiment, even if a parity error occurs with respect to the way  3  in the primary cache memory  102 , access to the address E is not adversely affected in any way. 
     A case in which the address D is accessed will be described below with reference to FIG.  14  and FIG.  20 . In step SA 1  shown in FIG. 20, the CPU  101  outputs a read request which requests that the data d of the address D shown in FIG. 14 should be read (p 17  in FIG.  14 ). In this case, in the step SA 2 , the primary cache hit determination circuit  105  compares the address D with the address held in the primary tag RAM  102   a  shown in FIG.  14 . In the next step SA 3 , the primary cache hit determination circuit  105  checks whether the address D exists in the primary tag RAM  102   a  or not, i.e., whether cache hit is established or not. In this case, since the address D does not exist in the primary tag RAM  102   a , the primary cache hit determination circuit  105  determines this state as cache miss (p 18  in FIG.  14 ), and sets the check result in step SA 3  as “No”. 
     In step SA 5 , the secondary cache memory  110  is accessed (p 17  in FIG.  14 ). In step SA 6 , it is checked whether the secondary tag RAM  110   a  has an INCL bit set “1” or not. In this case, in the replace way selection circuit  106 , as in the case shown in FIG. 13, it is considered that, as a replace way, a way  1  in the primary cache memory  102  is selected as a way to be replaced from ways  0  to  2 . Since the INCL bit of an address B in the secondary cache memory  110  is “1”, data b′ (old data) of the address B is written back in step SA 7  (p 19  in FIG.  14 ). 
     More specifically, in step SA 7 , with reference to the address B existing in the way  1  of the primary tag RAM  102   a , the data b (latest data) existing in the primary data RAM  102   b  is written back to the region corresponding to the address B in the secondary data RAM  110   b  (p 19  in FIG.  14 ). In this manner, the data b′ (old data) of the address B in the secondary data RAM  110   b  is updated into the data b (latest data). 
     In the next step SA 8 , the secondary cache hit determination circuit  111  checks whether the address D exists in the secondary tag RAM  110   a  or not, i.e., whether cache hit is established or not. In this case, since the address D exists in the secondary tag RAM  110   a , the secondary cache hit determination circuit  111  sets the check result in step SA 8  as “Yes”. In the next step SA 9 , since the way WAY of the entry of the address D in the secondary cache memory  110  is “3”, and the INCL bit is “1”, the following process is performed to the entry. That is, it is requested that the data d held in the entry of the way  3  of the primary data RAM  102   b  should be written back to the secondary data RAM  110   b  (p 20  in FIG.  14 ). 
     Data d held in the entry of the way  3  in the primary data RAM  102   b  shown in FIG. 14 is written back to the entry corresponding to the address D in the secondary cache memory  110  (p 21  in FIG.  14 ). More specifically, in this case, the data d′ (old data) held in the entry corresponding to the address D in the secondary cache memory  110  is updated into the data d (latest data). Therefore, the address D and the data d held in the primary cache memory  102  before the parity error occurs are held in the secondary cache memory  110 . The data d corresponding to the address D is read from the secondary data RAM  110   b.    
     The read data d and the address D of the data d are moved from the secondary cache memory  110  into the way  1  (way to be replaced) of the primary cache memory  102  (p 22  in FIG.  14 ), and the way WAY related to the address D in the secondary cache memory  110  is changed from “3” to “1”. In this case, the address D is moved in the entry of the way  1  in the primary tag RAM  102   a  shown in FIG. 14, and the data d is moved in the entry of the way  1  in the primary data RAM  102   b . In this manner, in the first embodiment, even if a parity error occurs with respect to the way  3  in the primary cache memory  102 , access to the address D is not adversely affected in any way. 
     As described above, according to the first embodiment, when a parity error occurs in the primary cache memory  102 , the data corresponding this address is written back to the secondary cache memory  110 , and the address and the data corresponding the secondary cache memory  110  are moved in the primary cache memory  102 . Accordingly, even if a parity error occurs, the data corresponding the address can be normally read. Furthermore, since a way in which a parity error has occurred is prohibited from being replaced in the primary cache memory  102 , the entry of such way is not accessed. Thus, even if a parity error occurs in the primary cache memory  102 , system down can be avoided, and the reliability of the apparatus is greatly improved. 
     In the first embodiment, when a parity error occurs at the address D of the primary tag RAM  102   a  shown in FIG. 9, the mode is changed from the normal operation mode to the parity error mode, and the way  3  is prohibited from being replaced (see FIG. 10) to perform the recovery process. However, the recovery process may be performed by the method of a modification (to be described below) of the first embodiment. In the modification of the first embodiment, when the status of the entry of the address D in the primary tag RAM  102   a , i.e., the status STATUS shown in FIG. 2A is I (invalid), the entry is recovered without changing the mode to the parity error mode. 
     FIG. 15 is a flow chart for explaining a main operation of the modification of the first embodiment. In step SC shown in FIG. 15, the CPU  101  outputs a read request. When such a read request is output, in the step SC 2 , the tag parity error detection circuit  103  checks whether a parity error in the primary tag RAM  102   a  is detected or not. In this case, it is assumed that a parity error is detected in the entry of the address D of the primary tag RAM  102   a  shown in FIG. 9, therefore the check result in step SC 2  becomes “Yes”. In the next step SC 3 , it is checked whether the status STATUS shown in FIG. 2A related to the entry in which the parity error has occurred is set to be I (invalid) or not. More specifically, in the primary cache memory  102  shown in FIG. 9, it is checked whether the entry of the primary tag RAM  102   a  corresponding to the address D is invalid or not. In this case, when the status STATUS is M or C, i.e., when the status STATUS is valid, the check result in step SC 3  is set to be “No”, a parity error mode process is executed in step SC 4 . This parity error mode process is the same as the processes in the steps SA 4  to SB 13  described above (see FIG.  8 ). 
     On the other hand, in the primary cache memory  102 , when the status STATUS is I (invalid), the parity error occurring in the primary tag RAM  102   a  is regarded as cache miss, and the check result in step SC 3  is set to be “Yes”. In the next step SC 8 , the secondary cache memory  110  is accessed. In the subsequent step SC 9 , the secondary cache hit determination circuit  111  checks whether the address exists in the secondary tag RAM  110   a  or not, i.e., whether cache hit is established or not. When the check result is “Yes”, in the next step SC 10 , the data corresponding to the address is read from the secondary cache memory  110  (secondary data RAM  110   b ). As in the operation described above, the address and the data are moved from the secondary cache memory  110  into the primary cache memory  102 , e.g., the entry of the way  3 , so that the status is returned to the status before the parity error occurs. 
     On the other hand, when the check result in step SC 2  is “No”, after the primary cache memory  102  is accessed in the next step SC 5 , it is checked in step SC 6  whether the address exists in the primary tag RAM  102   a  or not, i.e., whether cache hit is established or not. When the check result is “No”, the processes in the steps subsequent to the step SC 8  described above are performed. When the check result in step SC 6  is “Yes”, the data corresponding to the address is read from the primary cache memory  102 . 
     On the other hand, when the check result in step SC 9  is “No”, after the main memory device  112  is accessed in step SC 11 , the data corresponding the address is read from the main memory device  112  in step SC 12 . 
     As described above, according to the modification of the first embodiment, when a parity error occurs in the primary cache memory  102 , and the entry in which the parity error has occurred is made invalid, this state is regarded as cache miss to set such a status that the way of the entry is permitted to be replaced. For this reason, the entry is recovered without changing the mode to the parity error mode. 
     In the first embodiment, a case is explained in which when it is determined in step SB 2  shown in FIG. 8 that a parity error has occurred, in synchronism with this, the mode is changed into the parity error mode, and the recovery process is immediately performed. However, the recovery process may be performed in a synchronism with occurrence of the parity error. More specifically, if there is another access which is pending when a parity error has occurred, the recovery process is performed after the access is completed. Thus, the access is not adversely affected. 
     Further, in the first embodiment, a case is explained in which when a parity error occurs in the primary cache memory  102 , a way including an entry in which a parity error has occurred is prohibited from being replaced. However, the entire way need not be prohibited from being replaced. Only the entry may be prohibited from being replaced. In this case, the functions of the primary cache hit determination circuit  105  and the replace way selection circuit  106  may be changed as described below. That is, the primary cache hit determination circuit  105  suppresses outputting of a cache hit signal related to only the entry in which the parity error occurs. In this case, when cache hit of a way WAY n  is represented by HIT n , the cache hit signal is expressed by the following theoretical equation: 
     
       
         HIT n =(READ·ADR_MATCH n ·(MCI_C n +MCI_M n )+WRITE·ADR_MATCH n ·MCI_M n )·#(ADR_PE n +MCI_PE n ) 
       
     
     where “#” represents negation and the other symbols have meanings as following. 
     
       
         
           
               
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 READ 
                 : 
                 cache read 
               
               
                   
                 WRITE 
                 : 
                 cache write 
               
               
                   
                 ADR_MATCH 
                 : 
                 address of WAY n  is matched 
               
               
                   
                 MCI_C n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is C 
               
               
                   
                 MCI_M n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is M 
               
               
                   
                 ADR_PE n   
                 : 
                 address ADR (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is parity error 
               
               
                   
                 MCI_PE n   
                 : 
                 status STATUS (see FIG. 2A) of 
               
               
                   
                   
                   
                 entry of WAY n  is parity error 
               
               
                   
                   
               
               
                   
                 n = 0, 1, 2, 3  
               
            
           
         
       
     
     In the replace way selection circuit  106 , in place of the PE_WAY signal (see FIG.  4  and FIG. 6) from the tag parity error log register  104 , a parity error signal from the tag parity error detection circuit  103  is used, so that an object to be prohibited from being replaced is reduced to an entry. In this case, the object to be prohibited from being replaced after a parity error has occurred is reduced from a way to an entry, another entry which can be used in the way is not prohibited from being accessed. 
     FIG. 16 is a block diagram showing the configuration of the second embodiment according to the present invention. The cache memory apparatus comprises a multiple cache memory (primary cache memory  202  and secondary cache memory  208 ) to eliminate a difference in the processing speed between a CPU  201  and a main memory device  210  in the same manner as in the first embodiment. The CPU  201  accesses the primary cache memory  202 , the secondary cache memory  208 , or the main memory device  210  to read/write data. 
     The CPU  201 , the primary cache memory  202 , the secondary cache memory  208 , and the main memory device  210  correspond to the CPU  101 , the primary cache memory  102 , the secondary cache memory  110 , and the main memory device  112  shown in FIG.  1 . Although the primary cache memory  102  shown in FIG. 1 is a memory using a 4-way set associative method, the primary cache memory  202  shown in FIG. 16 is a memory using a direct mapping method. The primary cache memory  202  is constituted by a so primary tag RAM  202   a  and a primary data RAM  202   b . The primary tag RAM  202   a  has a capacity of 256 entries×64 bytes. Tag information shown in FIG. 2H is held in each entry. In FIG. 2H, the status STATUS is information representing the status of data held in the secondary data RAM  202   b , and is one of M (Modified), C (Clean), and I (Invalid) shown in FIG.  2 B. 
     The address ADR is the address of the data held in the primary data RAM  202   b . A parity bit AP is an odd-number parity added to an address ADR, and is used by an odd-number parity check method to check whether a parity error occurs at the address ADR. 
     On the other hand, the secondary cache memory  208  stores part of data stored in the main memory device  210 , and is a memory using the direct mapping method as in the primary cache memory  202  and having a capacity of 16-k entries×64 kbytes. The secondary cache memory  208  constituted by a secondary tag RAM  208   a  and a secondary data RAM  208   b . Tag information shown in FIG. 2I is held in the secondary tag RAM  208   a.    
     In FIG. 2I, an INCL bit is a bit representing whether data held in the secondary data RAM  208   b  exists in the primary data RAM  202   b  of the primary cache memory  202  or not. The INCL bit is set to be “1” when the data exists, and the INCL bit is set to be “0” when the data does not exist. A status STATUS is information representing the status of data held in the secondary data RAM  208   b , and is one of M (Modified), O (Owned), E (Exclusive), S (Shared), and I (Invalid) shown in FIG.  2 G. The address ADR represents the address of data held in the secondary data RAM  208   b.    
     Referring again FIG. 16, an auxiliary register  203  is a register for holding data of one entry in the primary cache memory  202 . When a parity error occurs in the primary cache memory  202 , the auxiliary register  203  is used in place of the entry in which the parity error occurs. Tag information shown in FIG. 2H is held in the auxiliary register  203  as in the primary cache memory  202 . In the auxiliary register  203 , the status STATUS shown in FIG. 2H is set to be I. 
     A tag parity error detection circuit  206  is a circuit for detecting a parity error of the tag information in the primary tag RAM  202   a . More specifically, the tag parity error detection circuit  206  detects a parity error of the address ADR by an odd-number parity check method using the parity bit AP shown in FIG. 2H. A tag parity error log register  207  is a register for holding information related to an error shown in FIG. 2J when a parity error is detected by the tag parity error detection circuit  206 . In FIG. 2J, when the parity error occurs, “1” is set in a flag FLAG, and an index value INDEX represents the address of an entry in which a parity error occurs. 
     When the tag parity error detection circuit  206  detects a parity error, the tag parity error detection circuit  206  sets the flag FLAG to be “1”, and sets the index value INDEX as an address. When a parity error occurs, the tag parity error detection circuit  206  outputs tag information in which the status STATUS related to the entry and shown in FIG. 2H is corrected into I to the primary cache access control circuit  204 . This is because cache hit is prevented in access to an entry in which a parity error occurs. 
     The primary cache access control circuit  204  checks whether an address related toga read request from the CPU  201  exists in the primary tag RAM  202   a  or recognizes tag information input by the tag parity error detection circuit  206  when a parity error occurs to control access to the primary cache memory  202 . The details of the operation of the primary cache access control circuit  204  will be described later. The selection circuit  205  performs switching control between the auxiliary register  203  and the primary cache memory  202 . More specifically, the selection circuit  205  performs switching control from the primary cache memory  202  to the auxiliary register  203  when the flag FLAG shown in FIG. 2J in the tag parity error log register  207  is “1” and when the address of a read request from the CPU  201  is equal to the index value INDEX in FIG.  2 J. The secondary cache access control circuit  209  performs access control to the secondary cache memory  208 , control related to the write back operation, and the like. The details of the operation of the secondary cache access control circuit  209  will be described later. 
     Operation of the second embodiment will be explained here with reference to the flow chart shown in FIG.  17 . When a parity error occurs in the entry of the primary cache memory  202  shown in FIG. 16, the parity error is detected by the tag parity error detection circuit  206 . Therefore, the tag parity error detection circuit  206  sets the flag FLAG of the tag parity error log register  207  shown in FIG. 2J to be “1”, and makes the index value INDEX equal to the address of the entry in which the parity error has occurred. In addition, the tag parity error detection circuit  206  outputs tag information in which the status STATUS related to the entry and shown in FIG. 2H is corrected into I to the primary cache access control circuit  204 . 
     In this manner, when a read request is output from the CPU  201  in step SD 1  shown in FIG. 17 while a parity error occurs, in step SD 2 , the primary cache access control circuit  204  checks whether the flag FLAG shown in FIG. 2J is “1” in tag information from the tag parity error detection circuit  206  or not. In this case, the primary cache access control circuit  204  sets the check result in step SD 2  to be “Yes”, and shifts the process to step SD 3 . In step SD 3 , the primary cache access control circuit  204  checks whether the address which is requested to be read from the CPU  201  is equal to the index value INDEX (see FIG. 2J) related to the address at which the parity error has occurred. When the index value INDEX is equal to the address, the primary cache access control circuit  204  sets the check result in step SD 3  to be “Yes” and shifts the process to step SD 4 . In this case, a switching operation to the auxiliary register  203  is performed by the selection circuit  205 . When the check result in step SD 3  is “No”, the process in step SD 5  is executed. 
     In step SD 4 , the primary cache access control circuit  204  reads the tag information shown in FIG. 2H from the auxiliary register  203 , and shifts the process to step SD 8 . In step SD 8 , on the basis of the tag information, the primary cache access control circuit  204  checks whether cache hit is established or not. In this case, since the status STATUS shown in FIG. 2H is set to be I (invalid), cache miss is established. Therefore, the primary cache access control circuit  204  sets the check result in step SD 8  to be “No”, and shifts the process to step SD 9 . The primary cache access control circuit  204  outputs an access request to the secondary cache access control circuit  209  to perform control for accessing the secondary cache memory  208 . 
     In step SD 10 , the secondary cache access control circuit  209  accesses the secondary cache memory  208  to check whether the INCL bit related to the address and shown in FIG. 2I is “1” or not, i.e., whether the data related to the address exists in the primary cache memory  202  or not. In this case, it is assumed that the INCL bit is “1”, the secondary cache access control circuit  209  sets the check result to be “Yes”, and shifts the process to step SD 11 . In step SD 11 , the secondary cache access control circuit  209  requests the primary cache access control circuit  204  to perform a write back operation. 
     In this manner, the data of the address held in the primary data RAM  202   b  of the primary cache memory  202  is written back to the primary cache memory  202 . Furthermore, the secondary cache access control circuit  209  performs control such that the data is held in the auxiliary register  203 . Thus, data related to an entry in which a parity error has occurred in the primary cache memory  202  is held in the auxiliary register  203 . It is needless to say that, in the second embodiment, the data of the address held in the primary data RAM  202   b  of the primary cache memory  202  may be written back to the main memory device  210 , and the data may be held in the auxiliary register  203 . 
     In the next step SD 12 , the secondary cache access control circuit  209  checks whether an address related to an access request from the CPU  201  exists in the secondary tag RAM  208   a  or not, i.e., whether cache hit is established or not. In this case, since the check result is “Yes”, the data of the address is read from the secondary cache memory  208  in step SD 13 . 
     When a read request is output from the CPU  201  in step SD 1  while the parity error does not occur, it is checked in step SD 2  whether the flag FLAG shown in FIG. 2J is “1” or not in the tag information from the tag parity error detection circuit  206 . In this case, since the parity error does not occur, the primary cache access control circuit  204  sets the check result in step SD 2  to be “No”, and shifts the process to step SD 5 . In step SD 5 , the primary cache access control circuit  204  accesses the primary cache memory  202  to read the tag information from the primary tag RAM  202   a . In step SD 6 , it is checked whether a parity error is detected by the tag parity error detection circuit  206 . When the check result is “No”, the processes in steps subsequent to the step SD 8  are performed. 
     When a parity error is detected, in step SD 7 , the tag parity error detection circuit  206  sets the flag FLAG of the tag parity error log register  207  shown in FIG. 2J to be “1” and makes the index value INDEX equal to the address of the entry in which the parity error occurs. Further, the tag parity error detection circuit  206  outputs tag information in which the status STATUS related to the entry and shown in FIG. 2H is corrected into I to the primary cache access control circuit  204 . Subsequently, the operation which has already been explained above is performed. 
     When the check result in step SD 12  is “No”, the main memory device  210  is accessed in step SD 14 , and the data of the address is read from the main memory device  210  in step SD 15 . 
     As described above, according to the second embodiment, when a parity error occurs in the entry of the primary cache memory  202 , the auxiliary register  203  is used as a backup in place of the entry. Resultantly, the apparatus can be operated as if a parity error has not occurred. Thus, because of the provision of the auxiliary register  203 , even if a parity error occurs in the primary cache memory  202 , system down is avoided, and the reliability of the apparatus is improved. The configuration of the second embodiment can be realized by adding a simple circuit (i.e. the auxiliary register  203 ) to an existing circuit. 
     FIG. 18 is a block diagram showing a configuration of a third embodiment of the present invention. The cache memory apparatus shown in FIG. 18 is an apparatus provided with a multiple cache memory (primary cache memory  312  and secondary cache memory  322 ) to cover the speed difference between CPU  300  and main memory  330  as same as the prior art described above. The CPU  300  reads/writes data by accessing the primary cache memory  312 , secondary cache memory  322 , or main memory  330 . 
     The main memory  330  uses, for example, a DRAM memory and has a large capacity and a characteristic that the access time is longer than those of the primary cache memory  312  and secondary cache memory  322 . All data used for the CPU  300  is stored in the main memory  330 . 
     In a primary cache section  310 , the primary cache memory  312  uses, for example, an SRAM having a characteristic that the access time is shorter than that of the main memory  330 . Moreover, the primary cache memory  312  has a characteristic that the access time is shorter than that of the secondary cache memory  322 . 
     That is, among the primary cache memory  312 , secondary cache memory  322 , and main memory  330 , the primary cache memory  312  has the shortest access time, the secondary cache memory  322  has the second shortest access time, and the main memory  330  has the longest access time. Moreover, from the viewpoint of a storage capacity, the main memory  330  has the largest storage capacity, the secondary cache memory  322  has the second largest storage capacity, and the primary cache memory  312  has the smallest storage capacity. 
     The primary cache memory  312  stores some of the data stored in the main memory  330 , which is a four-way set-associative memory as shown in FIG.  22 . The primary cache memory  312  is constituted of a primary tag RAM  312   a  and a primary data RAM  312   b . The primary tag RAM  312   a  has a capacity of  4  ways×256×64 bytes and the tag information shown in FIG. 19A is stored in each entry. 
     In FIG. 19A, a state STATUS is information showing a state of the data stored in the primary data RAM  312   b  and corresponds to any one of legends M (Modified), C (Clean), and I (Invalid) shown in FIG.  19 B. Legend M denotes that the above data is valid and updated. Moreover, the state STATUS of M denotes that the above data does not match with the data stored in the secondary data RAM  322   b  corresponding to the above data. In this case, it is necessary to write back the data stored in the primary data RAM  312   b  to the secondary data RAM  322   b.    
     Legend C denotes that the data stored in the primary data RAM  312   b  is valid and it is not updated. Moreover, when the state STATUS is C, write-back is unnecessary because the above data matches with the data stored in the secondary data RAM  322   b  corresponding to the above data. Legend I denotes that a concerned entry is not used and the data stored in the primary data RAM  312   b  is invalid. 
     In FIG. 19A, a parity bit SP is an odd parity bit to be added to a state STATUS and is used to determine whether a parity error occurs in the state STATUS in accordance with the odd-parity checking mode. Address ADR is an address of the data stored in the primary data RAM  312   b . Parity bit AP is an odd parity bit to be added to the address ADR and is used to determine whether a parity error occurs in the address ADR in accordance with the odd-parity checking mode. 
     FIG. 22 schematically illustrates the above primary cache memory  312 . As shown in FIG. 22, the primary cache memory  312  stores data values a, b, c, and d and addresses A, B, C, and D {corresponding to the address ADR in FIG.  19 A} corresponding to the data values a, b, c, and d similarly to the case of the primary cache memory  13  (refer to FIG.  30 ). Moreover, FIG. 22 illustrates only the address ADR out of the tag information shown in FIG.  19 A. 
     Moreover, the primary tag RAM  312   a  and primary data RAM  312   b  are controlled by being divided into ways  0  to  3  and the way of the primary tag RAM  312   a  corresponds to the way of the primary data RAM  312   b  one to one. For example, an address A stored in an entry constituting a way  0  of the primary tag RAM  312   a  corresponds to data a stored in an entry of a way  0  of the primary data RAM  312   b  one to one. 
     In FIG. 18, a parity-error detection circuit  314  detects a parity error of tag information in the primary tag RAM  312   a . Specifically, when a parity error is detected in either of the state STATUS and address ADR shown in FIG. 19A in accordance with the odd-parity checking mode, the parity-error detection circuit  314  makes a parity error signal active and outputs a way number of an entry in which the parity error occurs and the information for a concerned address to a parity-error log register  315 . The parity-error log register  315  serves as a register for storing the information for the error shown in FIG. 19C when a parity error is detected by the parity-error detection circuit  314 . 
     In the case of the parity-error log register  315  shown in FIG. 19C, error-information storing sections WAY 0  to WAY 3  correspond to ways  0  to  3  of the primary cache memory  312  show in FIG. 23 one to one. A value “0” or “1” is set to each of these error-information storing sections WAY 0  to WAY 3 . The value “0” denotes that no parity error occurs in a concerned way and “1” denotes that a parity error occurs in a concerned way. Moreover, the information showing an entry in a way in which a parity error occurs is stored in INDEX. 
     In FIG. 18, a CPU interface circuit  311  is a circuit for establishing an interface between the CPU  300  with each portion of the primary cache section  310 . A primary cache access control circuit  313  is a circuit for controlling an access to the primary cache memory  312 . A secondary cache interface circuit  316  is a circuit for establishing a communication interface between each portion of the primary cache section  310  and a secondary cache section  320 . 
     In the secondary cache section  320 , a secondary cache memory  322  is a direct-mapping memory storing some of the data stored in the main memory  330  and has a capacity of 16k entries×64 bytes as shown in FIG.  22 . The secondary cache memory  322  comprises a secondary tag RAM  322   a  and a secondary data RAM  322   b  similarly to the case of a secondary cache memory  14  (refer to FIG.  30 ). The tag information shown in FIG. 19D is stored in the secondary tag RAM  322   a.    
     In FIG. 19D, a state STATUS is the information showing a state of the data stored in the secondary data RAM  322   b  and corresponds to any one of legends M (Modified), O (Owned), E (Exclusive), S (Shared), and I (Invalid) shown in FIG.  19 E. Legend M denotes a state in which not-illustrated other CPU does not store the above data in the secondary data RAM  322   b  but concerned data is updated. 
     Legend O denotes a state in which other CPU stores the above data in the secondary data RAM  322   b  and concerned data is updated. Legend E denotes a state in which other CPU does not store the above data in the secondary data RAM  322   b  but concerned data is not updated. Legend S denotes a state in which other CPU does not store the above data in the secondary data RAM  322   b . Legend I denotes a state in which the above data is invalid. 
     INCL bit is a bit showing whether the data stored in the secondary data RAM  322   b  is present in the primary data RAM  312   b  of the primary cache memory  312 . When the data is present, the INCL bit is set to “1”. When the data is not present, the INCL bit is set to “0”. When the data stored in the secondary data RAM  322   b  is stored in a way of the primary data RAM  312   b , a way WAY denotes the way number of the way WAY. Address ADR denotes the address of the data stored n the secondary data RAM  322   b.    
     Parity bit AP is an odd parity bit to be added to the address ADR. FIG. 22 schematically illustrates the above secondary cache memory  322 . As shown in FIG. 22, addresses A, B, F, and D {corresponding to the address ADR in FIG.  19 D} of data values a′, b′, f′, and d′, INCL bit, and way WAY are stored in the secondary tag RAM  322   a . Moreover, FIG. 22 illustrates information excluding a state STATUS out of the tag information shown in FIG.  19 D. 
     In FIG. 18, the primary cache interface circuit  321  is a circuit for establishing a communication interface between each portion of the secondary cache section  320  and the primary cache section  310 . A secondary cache access control circuit  323  is a circuit for controlling an access to the secondary cache memory  322 . A parity-error elimination control circuit  324  is a circuit for accepting a parity-error elimination request of the primary cache memory  312  and eliminating a parity error. 
     FIG. 20 is a block diagram showing a configuration of the parity-error elimination control circuit  324 . The parity-error elimination control circuit  324  shown in FIG. 20 is constituted of a write-back request processing circuit  324   a , an end determination circuit  324   b , a secondary cache access request circuit  324   c , an index register  324   d , and an index counter  324   e.    
     A parity-error elimination request signal S 1  is a signal output from the primary cache access control circuit  313  when a parity error is detected by the parity-error detection circuit  314  and also a signal for requesting parity-error elimination. Parity-error INDEX data D 1  is data corresponding to INDEX shown in FIG. 19C, which is output from the secondary cache interface circuit  316  simultaneously when the parity-error elimination request signal S 1  is output. 
     A write-back completed signal S 2  is a signal output from the secondary cache access control circuit  323  when write-back to be mentioned later is completed. Secondary tag data D 2  is data to be read from the secondary tag RAM  322   a  when write-back is executed. The write-back request processing circuit  324   a  outputs a write-back unnecessary signal S 3  to an end determination circuit  324   b  when write-back is unnecessary. The write-back request processing circuit  324   a  outputs a write-back request signal S 7  to the primary cache access control circuit  313  when write-back is necessary. 
     The end determination circuit  324   b  outputs a next-INDEX processing request signal S 4  to the secondary cache access request circuit  324   c  and index counter  324   e  and moreover outputs a parity-error elimination completed signal S 6  to the secondary cache interface circuit  316 . The secondary cache access request circuit  324   c  output s secondary cache access request signal S 5  to the secondary cache access control circuit  323 . The index register  324   d  outputs INDEX data D 3  to the secondary cache access control circuit  323 . In FIG. 18, the main-memory interface circuit  325  is a circuit for establishing a communication interface between each portion of the secondary cache section  320  and the main memory  330 . 
     Then, operations of the above-described third embodiment are described below by referring to the flow chart shown in FIG.  21 . In this case, it is assumed that addresses A to D are stored in entries of the ways  0  to  3  of the primary tag RAM  312   a  shown in FIG.  22  and data values a to d are stored in the primary data RAM  312   b  corresponding to these addresses A to D. Moreover, it is assumed that the ways  0 ,  1  and  3  are valid but the way  2  is invalid in the primary tag RAM  312   a . Furthermore, it is assumed that the value of [13:6] bit of the addresses A to D of the primary tag RAM  312   a  is set to  100  and the value  100  corresponds to an entry of INDEX  100  of the primary cache memory  312 . 
     Moreover, in FIG. 22, it is assumed that addresses A, B, and D, data values a′, b′, and d′ (these are old data values), INCL bit=“1”, “1”, and “1”, ways WAY=“0”, “1”, and “3” are stored in the second cache memory  322 . 
     When a read request for requesting that the data value e of the address E shown in FIG. 22 should be read is output from the CPU  300  shown in FIG. 18, an access to a concerned entry of the primary tag RAM  312   a  is started in step SE 1  shown in FIG.  21 . In this case, an entry corresponding to INDEX= 100  of the primary tag RAM  312   a  is accessed (( 1 ) in FIG.  22 ). 
     In the next step SE 2 , it is determined whether a parity error is detected by the parity-error detection circuit  314 . When the determination result is “No”, normal processing is executed in step SE 10  that data is read from the primary cache memory  312 , secondary cache memory  322 , or main memory  330 . 
     In this case, when it is assumed that a parity error occurs in the address D of the way  3  of the primary tag RAM  312   a  shown in FIG. 22 (( 2 ) in FIG.  22 ), the determination result in step SE 2  is assumed to be “Yes”. In step SE 3 , “1” is set to an error-information storing section WAY 3  of the parity-error log register  315  and  100  is set to INDEX by the parity-error detection circuit  314  (( 3 ) in FIG.  22 ). In this case, when a parity error simultaneously occurs in a plurality of ways of the primary tag RAM  312   a , “1” is stored in each of a plurality of error-information storing sections of the parity-error log register  315  corresponding to a plurality of parity errors and information showing an entry is set to INDEX. 
     In and after step SE 4 , operations when parity errors are eliminated shown in FIG. 23 are executed. That is, in step SE 4 , an access to the primary cache memory  312  from the CPU  300  is prohibited in accordance with the control by the primary cache access control circuit  313 . Moreover, the primary cache access control circuit  313  outputs the parity-error elimination request signal S 1  to the parity-error elimination control circuit  324  through the primary cache interface circuit  321 . 
     In step SE 5 , the parity-error elimination control circuit  324  calculates an entry (INDEX) of the secondary cache memory  322  to be written back. In the case of the example shown in FIG. 23, because the parity-error log register  315  of the parity-error elimination control circuit  324  has an INDEX value “100”, an entry of the secondary cache memory  322  has an address  100 . The number of INDEXes of this entry reaches 64 such as 100, 100+256, 100+256×2, . . . , 100+256×32, . . . , and 100+256×63. 
     In step SE 6 , the write-back processing is applied to the entry of the secondary cache memory  322  calculated in step SE 5 . In the case of the write-back processing, no data is written back because there is no data in a concerned entry of the primary cache memory  312  when INCL bit of the secondary cache memory  322  is set to “0”. However, when the INCL bit is set to “11”, write-back is requested to the primary cache memory  312  because there is data in the concerned entry of the primary cache memory  312 . In this case, the data for the concerned entry from the primary cache memory  312  is written back to a concerned entry of the secondary cache memory  322 . 
     In step SE 7 , it is determined whether write-back to all entries is completed, that is, write-back to 100+256*63 entries is completed in the secondary cache memory  322 . In this case, a determined result is set to “No”. Therefore, processings in and after step SE 5  are repeated. Then, when a determined result in step SE 7  becomes “Yes”, a way set to “1” in the parity-error log register  315  is initialized into a state free from error in step SE 8  (( 1 ) in FIG.  23 ). The above initialization is performed to correct an error state when a parity error occurs in STATUS and the STATUS changes from a state I to a state M (or C). In step SE 9 , the parity-error log register  315  is cleared (( 2 ) in FIG.  23 ). Moreover, prohibition of an access to the primary cache memory  312  is released (( 3 ) in FIG.  23 ). 
     As described above, when an error occurs in an entry of the primary cache memory  312 , the third embodiment prohibits an access to the primary cache memory  312  to perform write-back and then, restores the entry to a state free from error by the parity-error elimination control circuit  324 . Therefore, it is possible to avoid a trouble that other error is detected while eliminating the error and system down, and improve the reliability of an apparatus. 
     Moreover, the third embodiment makes it possible to store an error correction code in the primary tag RAM  312   a  in addition to a parity error and correct an error by the error correction code when the error occurs in the primary tag RAM  312   a . When an error that cannot be corrected occurs, the same operation as the case of the third embodiment is performed. Moreover, in the case of the third embodiment, it is permitted to set the parity-error log register  315  every way. 
     The third embodiment is also able to correspond to a case in which a multi-hit error that errors simultaneously occur in a plurality of ways occurs. Hereafter, the above case is described as the fourth embodiment. The fourth embodiment is described by using the configuration of the third embodiment shown in FIG.  18 . 
     FIG. 24 is a flowchart for explaining operations of the fourth embodiment. In this case, it is assumed that entry addresses A to D are stored in ways  0  to  3  of a primary tag RAM  312   a  shown in FIG.  25  and data values a to d are stored in a primary data RAM  312   b  corresponding to the addresses A to D. Moreover, in the case of the primary tag RAM  312   a , it is assumed that the ways  0 ,  1 , and  3  are valid and the way  2  is invalid. It is assumed that the value of [13:6] bits of the addresses A to D of the primary tag RAM  312   a  is set to 100 and this value 100 corresponds to the entry of INDEX  100  of a primary cache memory  312 . 
     Moreover, in FIG. 25, it is assumed that addresses A, B, and D, data values a′, b′, and d′ (these are old data values), INCL bit=“1”, “1” and “1”, and way WAY=“0”, and “1” and “3” are stored in a secondary cache memory  322 . 
     When a read request for reading data value e of the address E shown in FIG. 25 is output from the CPU  300  shown in FIG. 18, an access to a concerned entry of the primary tag RAM  312   a  is started in step SF 1  shown in FIG.  24 . In this case, an entry corresponding to INDEX= 100  of the primary tag RAM  312   a  is accessed (( 1 ) in FIG.  25 ). 
     In the next step SF 2 , it is determined whether a multi-hit error is detected by the parity-error detection circuit  314 . When the determined result is “No”, normal processing that data is read from the primary cache memory  312 , secondary cache memory  322 , or main memory  330  is executed in step SF 10 . 
     In this case, when it is assumed that a multi-hit error that parity errors simultaneously occur in addresses B and D in the way  3  of the primary tag RAM  312   a  shown in FIG. 25 (( 2 ) in FIG.  25 ), a determined result in step SF 2  is set to “Yes”. In step SF 3 , “1” is set to error-information storing sections WAY 1  and WAY 3  of the parity-error log register  315  and  100  is set to INDEX of the register  315  by the parity-error detection circuit  314 . 
     In and after step SF 4 , operations for eliminating parity errors shown in FIG. 26 are executed. That is, in step SF 4 , an access to a primary cache memory  312  from the CPU  300  is prohibited in accordance with the control by the primary cache access control circuit  313 . Moreover, the secondary cache access control circuit  323  outputs a parity-error elimination request signal S 1  to a parity-error elimination control circuit  324  through the primary cache interface circuit  321 . 
     In step SF 5 , the parity-error elimination control circuit  324  calculates an entry (INDEX) of the secondary cache memory  322  to be written back. In the case of the example shown in FIG. 26, because the parity-error log register  315  of the parity-error elimination control circuit  324  has an INDEX value “100”, an entry of the secondary cache memory  322  has an address  100 . The number of INDEXes of this entry reaches the total of 64 such as 100, 100+256, 100+256*2, . . . , 100*256*32, . . . , and 100+256*63. 
     In step SF 6 , processing for write-back to the entry of the secondary cache memory  322  calculated in step SF 5  is executed. In the case of the write-back processing, write-back is not performed because there is no data in a concerned entry of the primary cache memory  312  when INCL bit of the secondary cache memory  322  is set to “0”. However, when the INCL bit is set to “11”, a write-back request is issued to the primary cache memory  312  because there is data in the concerned entry of the primary cache memory  312 . In this case, the data of a concerned entry from the primary cache memory  312  is written back to a concerned entry of the secondary cache memory  322 . 
     In step SF 7 , it is determined whether write-back to all entries is completed, that is, write-back to 100+256*63 entries is completed in the secondary cache memory  322 . In this case, a determined result is set to “No”. Thereafter, processings in and after step SF 5  are repeated. Then, when a determined result in step SF 7  becomes “Yes”, a way set to “1” in the parity-error log register  315  is initialized into a state free from error in step SF 8  (( 1 ) in FIG.  26 ). In step SF 9 , the parity-error log register  315  is cleared (( 2 ) in FIG.  26 ). Moreover, prohibition of an access to the primary cache memory  312  is released (( 3 ) in FIG.  26 ). 
     As described above, according to the fourth embodiment, when a multi-hit error occurs in an entry of the primary cache memory  312 , an access to the primary cache memory  312  is prohibited to perform write-back and then, the entry is restored to a state free from error by the parity-error elimination control circuit  324 . Therefore, it is possible to avoid a trouble that other error is detected while eliminating the error, avoid system down, and improve the reliability of an apparatus. 
     The first to fourth embodiments of the present invention are described above in detail. However, a specific configuration is not restricted to the embodiments. Modifications not deviating from the gist of the present invention are included in the present invention. For example, in the case of the first to fourth embodiments, it is also permitted to execute cache memory control by recording a cache memory control program for realizing functions of the above cache memory apparatus in a computer-readable recording medium  500  shown in FIG. 27, making a computer  400  shown in FIG. 27 read the cache memory control program recorded in the recording medium  500  and executing the program. 
     The computer  400  shown in FIG. 27 is constituted of a CPU  401  for executing the above cache memory control program, an input unit  402  including a keyboard and a mouse, a ROM (Read Only Memory)  403  for storing various data values, a primary cache memory  404  for storing data, a secondary cache memory  405  and a main memory  406 , a reader  407  for reading the cache memory control program from the recording medium  500 , an output unit  408  including a display and a printer, and a bus BU for connecting various sections of the apparatus. 
     The above primary cache memory  404 , secondary cache memory  405 , and main memory  406  correspond to the primary cache memory  102 , secondary cache memory  110 , and main memory  112  (refer to FIG. 1) of the first embodiment, the primary cache memory.  202 , secondary cache memory  208 , and main memory  210  (refer to FIG. 16) of the second embodiment, and the primary cache memory  312 , secondary cache memory  322 , and main memory  330  of the third and fourth embodiments. 
     The CPU  401  controls the primary cache memory  404 , secondary cache memory  405 , and main memory  406  by reading a cache memory control program from the recording medium  500  via the reader  407  and then, executing the program. The recording medium  500  includes not only a portable recording medium such as an optical disk, floppy disk, or hard disk but also a transmission medium for temporarily storing data such as a network. 
     In the case of the cache memory according to any one of the first to fourth aspects described above, it is also permitted to stop functions of the replacement prohibition unit and the release unit when the status information for the above entry in which an error is detected is invalid. 
     According to the present invention, when the status information for an entry in which an error is detected in a primary cache memory is invalid, functions of a replace prohibition unit and a release unit are stopped. Therefore, it is possible to return only functions of a write-back unit and a write unit of a primary cache memory to sates before a parity error occurs. 
     As described above, according to one aspect of the present invention, when a parity error occurs, data is written back from the primary cache memory to the secondary cache memory, and the data is written from the second cache memory into the primary cache memory. Accordingly, even if a parity error occurs, the data can be normally read from the secondary cache memory. Therefore, even if a parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is greatly improved. 
     Further, according to another aspect of the present invention, when a parity error occurs, data is written back from the primary cache memory to the secondary cache memory, and the data is written from the secondary cache memory into the primary cache memory. Accordingly, even if a parity error occurs in the primary cache memory, system down is avoided, and the reliability of the apparatus is greatly improved. In addition, since an object to be prohibited from being replaced is narrowed to an entry, the advantage that another entry which can be used in the corresponding way is not prohibited from being accessed can be achieved. 
     Further, according to still another aspect of the present invention, a write back operation is performed at the moment an error is detected by the error detection unit. Therefore, a period of time extending from when a parity error occurs to when the status of the primary cache memory is returned to the status before the parity error occurs can be advantageously shortened. 
     Further, according to still another aspect of the present invention, a write back operation is performed at any time after an error is detected by the error detection unit. Therefore, the advantage that, when a parity error occurs, the parity error does not adversely affect another entry pending can be achieved. 
     Further, according to still another aspect of the present invention, when a parity error occurs in an entry of the primary cache memory, an auxiliary memory is used as a backup in place of the entry. Resultantly, the cache memory apparatus can be advantageously operated as if a parity error has not occurred. 
     Furthermore, according to still another aspect of the present invention, when an error occurs in an entry of a primary cache memory, it is prohibited to access the primary cache memory and write-back is performed and thereafter, the entry is restored to a state free from error. Therefore, it is possible to avoid a trouble that other error is detected while eliminating the error, avoid system-down, and improve the reliability of an apparatus. 
     Although the invention has been described with respect to a specific embodiment for a complete and clear disclosure, the appended claims are not to be thus limited but are to be construed as embodying all modifications and alternative constructions that may occur to one skilled in the art which fairly fall within the basic teaching herein set forth.