Patent Publication Number: US-7718527-B2

Title: Method for forming cobalt tungsten cap layers

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     The present invention is related to U.S. patent application Ser. No. 12/242,900, entitled “METHOD FOR FORMING COBALT NITRIDE CAP LAYERS”, filed on Sep. 30, 2008, the entire contents of which is hereby incorporated by reference. 
     FIELD OF THE INVENTION 
     The present invention relates to semiconductor processing and semiconductor devices, and more particularly, to a method of integrating cobalt tungsten films into the manufacturing of semiconductor devices. 
     BACKGROUND OF THE INVENTION 
     An integrated circuit contains various semiconductor devices and a plurality of conducting metal paths that provide electrical power to the semiconductor devices and allow these semiconductor devices to share and exchange information. Within the integrated circuit, metal layers are stacked on top of one another using intermetal or interlayer dielectric layers that insulate the metal layers from each other. Normally, each metal layer must form an electrical contact to at least one additional metal layer. Such electrical contact is achieved by etching a hole (i.e., a via) in the interlayer dielectric that separates the metal layers, and filling the resulting via with a metal to create an interconnect. A “via” normally refers to any recessed feature such as a hole, line or other similar feature formed within a dielectric layer that, when filled with metal, provides an electrical connection through the dielectric layer to a conductive layer underlying the dielectric layer. Similarly, recessed features connecting two or more vias are normally referred to as trenches. 
     The use of copper (Cu) metal in multilayer metallization schemes for manufacturing integrated circuits has created several problems that require solutions. For example, high mobility of Cu atoms in dielectric materials and Si can result in migration of Cu atoms into those materials, thereby forming electrical defects that can destroy an integrated circuit. Therefore, Cu metal layers, Cu filled trenches, and Cu filled vias are normally encapsulated with a barrier layer to prevent Cu atoms from diffusing into the dielectric materials. Barrier layers are normally deposited on trench and via sidewalls and bottoms prior to Cu deposition, and may include materials that are preferably non-reactive and immiscible in Cu, can provide good adhesion to the dielectrics materials and can offer low electrical resistivity. 
     The electrical current density in an integrated circuit&#39;s interconnects significantly increases for each successive technology node. Because electromigration (EM) and stress migration (SM) lifetimes are inversely proportional to current density, EM and SM have fast become critical challenges. EM lifetime in Cu dual damascene interconnect structures is strongly dependent on atomic Cu transport at the interfaces of bulk Cu metal and surrounding materials (e.g., capping layer) which is directly correlated to adhesion at these interfaces. New capping materials that provide better adhesion and better EM lifetime have been studied extensively. For example, a cobalt-tungsten-phosphorus (CoWP) layer has been selectively deposited on bulk Cu metal using an electroless plating technique. The interface of CoWP and bulk Cu metal has superior adhesion strength that yields longer EM lifetime. However, maintaining acceptable deposition selectivity on bulk Cu metal, especially for tight pitch Cu wiring, and maintaining good film uniformity, has affected acceptance of this complex process. Furthermore, wet process steps using acidic solution may be detrimental to the use of CoWP. 
     Therefore, new methods are required for depositing metal-containing cap layers that provide good adhesion to Cu, improved EM and SM properties of bulk Cu metal, and provide good chemical resistance to wet processing steps. Furthermore, these methods should provide good selectivity for metal-containing cap layer deposition on metal surfaces compared to dielectric surfaces. 
     SUMMARY OF THE INVENTION 
     Embodiments of the invention provide a method for integrating cobalt tungsten cap layers into manufacturing of semiconductor devices to improve electromigration and stress migration in Cu metallization. The cobalt metal element provides enhanced adhesion properties to Cu metal and the tungsten element provides enhanced diffusion barrier properties against Cu metal diffusion into dielectric materials. 
     According to one embodiment of the invention, the method includes providing a patterned substrate containing a recessed feature formed in a low dielectric constant (low-k) dielectric material and a first metallization layer at the bottom on the recessed feature, forming a first cobalt tungsten cap layer on the first metallization layer using a first cobalt precursor gas and a first tungsten precursor gas, depositing a barrier layer in the recessed feature, including on the low-k dielectric material and on the first cobalt tungsten cap layer; and filling the recessed feature with Cu metal. According to another embodiment of the invention, the method further includes, following the filling, forming a substantially planar surface with Cu paths and low-k dielectric regions, and forming a second cobalt tungsten cap layer on the Cu paths. 
     According to an embodiment of the invention, the method includes providing a patterned substrate having a substantially planar surface with Cu paths and low-k dielectric regions, and forming a cobalt tungsten cap layer on the Cu paths by exposing the patterned substrate to a deposition gas comprising a cobalt precursor gas and a tungsten precursor gas. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete appreciation of the invention and many of the attendant advantages thereof will become readily apparent with reference to the following detailed description, particularly when considered in conjunction with the accompanying drawings, in which: 
         FIGS. 1A-1F  show schematic cross-sectional views of integration of cobalt tungsten cap layers in a dual damascene interconnect structure according to embodiments of the invention; 
         FIGS. 2A-2C  schematically show cross-sectional views of additional interconnect structures according to embodiments of the invention; 
         FIGS. 3A-3D  show simplified schematic cross-sectional views of cobalt tungsten cap layers on a first metallization layer according to embodiments of the invention; 
         FIGS. 4A-4D  show simplified schematic cross-sectional views of cobalt tungsten cap layers on a Cu path according to embodiments of the invention; and 
         FIG. 5  depicts a schematic view of a processing system for forming cobalt tungsten films according to embodiments of the invention. 
     
    
    
     DETAILED DESCRIPTION OF SEVERAL EMBODIMENTS 
     Embodiments of the invention provide a method for integrating cobalt tungsten (CoW) cap layers into Cu metallization of semiconductor devices to improve electromigration (EM) and stress migration (SM) in the devices and provide good chemical resistance to wet processing steps. The method can provide selectivity for cobalt tungsten cap layer deposition on metal surfaces such as Cu paths relative to dielectric surfaces between the Cu paths that results in improved margin for line-to-line breakdown and electrical leakage performance. 
     One skilled in the relevant art will recognize that the various embodiments may be practiced without one or more of the specific details, or with other replacement and/or additional methods, materials, or component. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of various embodiments of the invention. Similarly, for purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the invention. Furthermore, it is understood that the various embodiments shown in the figures are illustrative representations and are not necessary drawn to scale. 
     Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention, but do not denote that they are present in every embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. 
     Embodiments of the invention provide a method for selective deposition of cobalt tungsten films on metal surfaces (e.g., Cu metal) on patterned substrates containing low-k materials. The patterned substrates can contain high-aspect-ratio recessed features in a low-k dielectric material that are at least substantially filled with Cu metal, thus forming Cu paths in the recessed features. According to one embodiment of the invention, a recessed feature can include a dual damascene interconnect structure containing a trench and a via formed in the patterned low-k dielectric material. The via can have an aspect ratio (depth/width) greater than or equal to about 2:1, for example 3:1, 4:1, 5:1, 6:1, 12:1, 15:1, or higher. The via can have widths of about 200 nm or less, for example 150 nm, 100 nm, 65 nm, 45 nm, 32 nm, 20 nm, or lower. However, embodiments of the invention are not limited to these aspect ratios or via widths, as other aspect ratios or via widths may be utilized. 
       FIGS. 1A-1E  show schematic cross-sectional views of integration of cobalt tungsten films in a dual damascene interconnect structure according to embodiments of the invention.  FIG. 1A  shows a schematic cross-sectional view of a patterned substrate containing a dual damascene interconnect structure  100  according to an embodiment of the invention. The dual damascene interconnect structure  100  can be formed using standard lithography and etching methods known to those skilled in the art. It will be understood that embodiments of the invention may also be applied to simpler or more complicated dual damascene interconnect structures and other types of recessed features formed in low-k dielectric materials. 
     In  FIG. 1A , the dual damascene interconnect structure  100  comprises a recessed feature  150  containing a trench  152  and a via  154  etched in a low-k dielectric material  104 . Furthermore, the dual damascene interconnect structure  100  contains a first metallization layer  102  (e.g., Cu metal, tungsten (W) metal, or aluminum (Al) metal) at the bottom of the via  154 . The low-k dielectric material  104  contains a dielectric material having a lower dielectric constant than SiO 2  (k˜3.9). The low-k dielectric material can include BLACK DIAMOND® II (BDII) SiCOH material, commercially available from Applied Materials of Santa Clara, Calif. Other low-k dielectric materials that may be used include fluorinated silicon glass (FSG), carbon doped oxide, a polymer, a SiCOH-containing low-k material (e.g., F—SiCOH), a non-porous low-k material, a porous low-k material, a low-k material deposited by chemical vapor deposition (CVD), or a spin-on dielectric (SOD) low-k material. In addition to BD II, other carbon-containing materials are commercially available, including Silk® and Cyclotene® (benzocyclobutene) available from Dow Chemical. Other suitable low-k dielectric material may be used. Although not shown, the interconnect structure  100  may contain additional layers, for example a trench etch stop layer, a via etch stop layer between dielectric materials  101  and  104 , and a barrier layer separating the first metallization layer  102  from the dielectric materials  101  and  104 . 
     According to one embodiment of the invention, the patterned substrate depicted in  FIG. 1A  may be treated with a thermally excited (non-plasma) or plasma excited process gas containing H 2 , NH 3 , N 2 , NH(CH 3 ) 2 , N 2 H 4 , N 2 H 3 CH 3 , or SiH 4 , or a combination thereof. 
     According to one embodiment, the patterned substrate may be treated with NH x  (x≦3) radicals and H radicals formed in a plasma processing chamber from a process gas comprising NH 3 . In one example, the plasma processing chamber may be process chamber  10  of processing system  1  depicted in  FIG. 5 . The treating can be performed at a substrate temperature below 500° C., for example between 150° C. and 400° C., and may further include a noble gas such as argon (Ar). In one example, pure NH 3  may be used. In one example, a 10:1 NH 3 /Ar mixture may be used. In one example, the process gas pressure in the plasma processing chamber is greater than 1 Torr, for example 2 Torr, 3 Torr, or greater than 3 Torr. In one example, plasma is generated in the plasma processing chamber by applying radio frequency (RF) power of less than 100 W to a substrate holder configured to support the substrate (wafer). The RF power can, for example, include 90, 80, 70, 60, 50, or even less than 50 Watts (W). In one example, according to embodiments of the invention, during the treating, plasma conditions may be selected such that exposure of the substrate to ions formed in the plasma is suppressed. This may be achieved using low plasma power and high process gas pressure that exposes the substrate to NH x  (x≦3) radicals and H radicals, but suppresses exposure of the substrate to ions formed in the plasma. 
     Following the treating of the patterned substrate, a first cobalt tungsten cap layer  112  may be formed on the first metallization layer  102  as shown in  FIG. 1B . The first cobalt tungsten cap layer  112  may be formed in a vapor deposition process selected from CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD). The first cobalt tungsten cap layer  112  may be formed using a cobalt precursor gas and a tungsten precursor gas. According to one embodiment, the first cobalt precursor gas can contain a cobalt carbonyl precursor gas (e.g., Co 2 (O) 8 , Co 4 (CO) 12 ) and the first tungsten precursor gas can contain a tungsten carbonyl precursor gas (e.g., W(CO) 6 ). In addition, a reducing gas may be used to aid in the deposition process. Alternately, other deposition processes may be utilized to deposit the first cobalt tungsten cap layer  112 . 
     According to some embodiments of the invention, the first cobalt tungsten cap layer  112  may contain a substantially homogeneous mixture of cobalt and tungsten, a graded cobalt tungsten mixture, or alternating cobalt and tungsten layers, or a combination thereof. Examples of a first cobalt tungsten cap layer  112  are depicted in  FIGS. 3A-3D . 
       FIGS. 3A-3D  show simplified schematic cross-sectional views of cobalt tungsten cap layers on a first metallization layer according to embodiments of the invention.  FIG. 3A  shows a schematic cross-sectional view of a first cobalt tungsten cap layer  112   a  on a first metallization layer  102  according to one embodiment. The first cobalt tungsten cap layer  112   a  can contain a substantially homogeneous cobalt tungsten mixture. The first cobalt tungsten cap layer  112   a  may be deposited by simultaneously exposing the first metallization layer  102  to a first cobalt precursor gas and a first tungsten precursor gas in a deposition process. 
       FIG. 3B  shows a schematic cross-sectional view of a first cobalt tungsten cap layer  112   b  on a first metallization layer  102  according to another embodiment. The first cobalt tungsten cap layer  112   b  may contain a cobalt metal layer  112   b   1  on the first metallization layer  102  and a tungsten metal layer  112   b   2  on the cobalt metal layer  112   b   1 . The cobalt metal layer  112   b   1  may be formed by exposing the first metallization layer  102  to a first cobalt precursor gas, and subsequently, the tungsten metal layer  112   b   2  may be deposited by exposing the cobalt metal layer  112   b   1  to a first tungsten precursor gas. According to other embodiments, the first cobalt tungsten cap layer  112   b  may contain additional alternating cobalt metal layers  112   b   1  and tungsten metal layers  112   b   2 . 
     According to one embodiment, the first cobalt tungsten cap layer  112   b  may contain a cobalt metal layer  112   b   1  on the first metallization layer  102  and a cobalt-rich cobalt tungsten layer  112   b   2  on the cobalt metal layer  112   b   1 . The cobalt-rich cobalt tungsten layer  112   b   2  can have a tungsten content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance cobalt. 
     According to one embodiment, the first cobalt tungsten cap layer  112   b  may contain a cobalt metal layer  112   b   1  on the first metallization layer  102  and a tungsten-rich cobalt tungsten layer  112   b   2  on the cobalt metal layer  112   b   1 . The tungsten-rich cobalt tungsten layer  112   b   2  can have a cobalt content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance tungsten. 
       FIG. 3C  shows a schematic cross-sectional view of a first cobalt tungsten cap layer  112   c  on a first metallization layer  102  according to another embodiment. The first cobalt tungsten cap layer  112   c  may contain a tungsten metal layer  112   c   1  on the first metallization layer  102  and a cobalt metal layer  112   c   2  on the tungsten metal layer  112   c   1 . The tungsten metal layer  112   c   1  may be formed by exposing the first metallization layer  102  to a tungsten precursor gas, and subsequently, the cobalt metal layer  112   c   2  may be deposited by exposing the tungsten metal layer  112   c   1  to a cobalt precursor gas. According to other embodiments, the first cobalt tungsten cap layer  112   c  may contain additional alternating tungsten metal layers  112   c   1  and cobalt metal layers  112   c   2 . 
     According to one embodiment, the first cobalt tungsten cap layer  112   c  may contain a tungsten metal layer  112   c   1  on the first metallization layer  102  and a cobalt-rich cobalt tungsten layer  112   c   2  on the tungsten metal layer  112   c   1 . The cobalt-rich cobalt tungsten layer  112   c   2  can have a tungsten content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance cobalt. 
     According to one embodiment, the first cobalt tungsten cap layer  112   c  may contain a tungsten metal layer  112   c   1  on the first metallization layer  102  and a tungsten-rich cobalt tungsten layer  112   c   2  on the tungsten metal layer  112   c   1 . The tungsten-rich cobalt tungsten layer  112   c   2  can have a cobalt content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance tungsten. 
       FIG. 3D  shows a schematic cross-sectional view of a first cobalt tungsten cap layer  112   d  on a first metallization layer  102  according to still another embodiment. The first cobalt tungsten cap layer  112   d  may have a varying cobalt/tungsten ratio from an external surface of the first cobalt tungsten cap layer  112   d  to an interface between the first cobalt tungsten cap layer  112   d  and the first metallization layer  102 . In some examples, the cobalt/tungsten ratio may increase or decrease from a first cobalt/tungsten ratio at an external surface of the first cobalt tungsten cap layer  112   d  to a second cobalt/tungsten ratio at an interface between the first cobalt tungsten cap layer  112   d  and the first metallization layer  102 . For example, the first cobalt tungsten cap layer  112   d  may be deposited by varying a ratio of a flow rate of the first cobalt precursor gas to a flow rate of the first tungsten precursor gas in a first deposition gas from a first ratio to a second ratio different than the first ratio. 
     According to other embodiments, the first cobalt tungsten cap layer  112  depicted in  FIG. 1B  may contain any combinations of the first cobalt tungsten cap layers  112   a - 112   d  depicted in  FIGS. 3A-3D . For example, the first cobalt tungsten cap layer  112  may contain the first cobalt tungsten cap layers  112   a  and  112   d  in any order on the first metallization layer  102 . 
     According to embodiments of the invention, the first cobalt tungsten cap layer  112  in  FIG. 1B  and the first cobalt tungsten cap layers  112   a - 112   d  in  FIGS. 3A-3D  may consist essentially of cobalt and tungsten. 
     Referring back to  FIG. 1B , according to one embodiment, the first cobalt tungsten cap layer  112  may be nitrided by exposing the first cobalt tungsten cap layer  112  to a first nitriding gas. The first nitriding gas can contain a thermally excited or plasma excited first nitriding gas selected from NH 3 , N 2 , N 2 +H 2 , NH(CH 3 ) 2 , N 2 H 4 , or N 2 H 3 CH 3 , or a combination thereof. 
     According to one embodiment of the invention, the first cobalt tungsten cap layer  112  may be selectively deposited on the first metallization layer  102  as depicted in  FIG. 1B . Selective deposition of the first cobalt tungsten cap layer  112  on the first metallization layer  102  relative to the low-k dielectric material  104  is enabled by a lack of or low concentration of metal precursor (e.g., cobalt or tungsten precursor) adsorption sites on the low-k dielectric material  104  compared to on the first metallization layer  102 . This leads to a short incubation time for deposition of the first cobalt tungsten cap layer  112  on the first metallization layer  102  relative to the low-k dielectric material  104 . 
     In one example, an average thickness of the first cobalt tungsten cap layer  112  can be between 5 angstrom (angstrom=10 −10  m) and 50 angstrom, for example about 5, 10, 15, 20, 30, 40, or 50 angstrom. In some examples, the first cobalt tungsten cap layer  112  may have an average thickness between 2 and 5 angstrom. However, embodiments of the invention are not limited to those thicknesses and a first cobalt tungsten cap layer  112  that is thicker than 50 angstrom may be formed and utilized. According to one embodiment, a surface coverage of the first cobalt tungsten cap layer  112  on the first metallization layer  102  may be incomplete with gaps that expose the first metallization layer  102 . According to one embodiment, the treating of the patterned substrate and the subsequent deposition of the first cobalt tungsten film may be performed in the same process chamber. Alternately, the treating and subsequent cobalt tungsten film deposition may be performed in different process chambers. 
       FIG. 1C  schematically shows a barrier layer  118  is formed in the recessed feature  150  and a planarized Cu path  122  formed on the barrier layer  118  in the recessed feature  150 . The planarized Cu path  122  can be formed by filling the recessed feature  150  with bulk Cu metal and removing excess Cu metal using a planarizing process, for example a chemical mechanical polishing (CMP) process. The planarization process further removes the barrier layer  118  from the low-k dielectric regions  114  of the low-k dielectric material  104  as schematically shown in  FIG. 1C . Bulk Cu metal deposition processes are well known to one of ordinary skill in the art of circuit fabrication and can, for example, include an electrochemical plating process or an electroless plating process. Furthermore, CMP processes are well known to one of ordinary skill in the art. Although only a single Cu path  122  is depicted in  FIG. 1C , those skilled in the art will readily recognize that semiconductor devices contain a plurality of Cu paths  122 . 
     The barrier layer  118  can, for example, contain a Ta-containing material (e.g., Ta, TaC, TaN, or TaCN, or a combination thereof), a Ti-containing material (e.g., Ti, TiN, or TiCN, or a combination thereof), or a W-containing material (e.g., W, WN, or a combination thereof). In one example, the barrier layer  118  may contain TaCN deposited in a plasma enhanced atomic layer deposition (PEALD) system using alternating exposures of tertiary amyl imido-tris-dimethylamido tantalum (Ta(NC(CH 3 ) 2 C 2 H 5 )(N(CH 3 ) 2 ) 3 ) and H 2 . In another example, the barrier layer  118  may contain a ruthenium (Ru) metal layer formed on a Ta-containing layer or on a Ti-containing layer, e.g., Ru/TaN, Ru/TaCN, Ru/TiN, or Ru/TiCN. In yet another example, the barrier layer  118  may contain a mixture of Ru and a Ta-containing material or a mixture of Ru and a Ti-containing material, e.g., RuTaN, RuTaCN, RuTiN, or RuTiCN. In still another example, the barrier layer  118  may contain a cobalt metal layer formed on a Ta-containing layer or on a Ti-containing layer, e.g., Co/TaN, Co/TaCN, Co/TiN, or Co/TiCN. In yet another example, the barrier layer  118  may contain a mixture of Co and a Ta-containing material or a mixture of Co and a Ti-containing material, e.g., CoTaN, CoTaCN, CoTiN, or CoTiCN. 
     Still referring to  FIG. 1C , the low-k dielectric regions  114  contain residues  117  and a copper oxide layer  115  formed on the Cu path  122 . The residues  117  and the copper oxide layer  115  may be formed by a CMP process. The residues  117  may include benzotriazine (BTA) that is a chemical agent commonly used in a CMP process. According to another embodiment, the residues  117 , the copper oxide layer  115 , or both the residues  117  and the copper oxide layer  115  may be absent from the interconnect structure  100  in  FIG. 1C . 
     According to one embodiment of the invention, following formation of the dual damascene interconnect structure  100  in  FIG. 1C , the planarized bulk Cu path  122  and the low-k dielectric regions  114  may be treated with thermally excited or plasma excited process gas containing H 2 , NH 3 , N 2 , NH(CH 3 ) 2 , N 2 H 4 , N 2 H 3 CH 3 , or SiH 4 , or a combination thereof. The treating is effective in removing the residues  117  and the copper oxide layer  115  from the patterned substrate, as depicted in  FIG. 1D . 
     According to one embodiment, the patterned substrate in  FIG. 1C  may be treated with NH x  (x≦3) radicals and H radicals formed from a process gas comprising NH 3 . In one example, the plasma processing chamber may be process chamber  10  of processing system  1  depicted in  FIG. 5 . The treating can be performed at a substrate temperature below 500° C., for example between 150° C. and 400° C., and may further include a noble gas such as argon (Ar). In one example, pure NH 3  may be used. In one example, a 10:1 NH 3 /Ar mixture may be used. In one example, the process gas pressure in the plasma processing chamber is greater than 1 Torr, for example 2 Torr, 3 Torr, or greater than 3 Torr. In one example, plasma is generated in the plasma processing chamber by applying RF power of less than 100 W to a substrate holder configured to support the substrate (wafer). The RF power can, for example, include 90, 80, 70, 60, 50, or even less than 50 W. According to embodiments of the invention, during the treating, plasma conditions may be selected such that exposure of the substrate to ions formed in the plasma is suppressed. This may be achieved using low plasma power and high process gas pressure that exposes the substrate to NH x  (x≦3) radicals and H radicals, but suppresses exposure of the substrate to ions formed in the plasma. 
     Following the treating, a second cobalt tungsten cap layer  124  may be formed on the Cu path  122  as shown in  FIG. 1E . The second cobalt tungsten cap layer  124  may be formed in a vapor deposition process selected from CVD), PECVD, ALD, or PEALD. The second cobalt tungsten cap layer  124  may be formed using a second cobalt precursor gas and a second tungsten precursor gas. According to one embodiment, the second cobalt precursor gas can contain a cobalt carbonyl precursor gas (e.g., CO 2 (CO) 8 , CO 4 (CO) 12 ) and the first tungsten precursor gas can contain a tungsten carbonyl precursor gas (e.g., W(CO) 6 ). In addition, a reducing gas may be used to aid in the deposition process. Alternately, other deposition processes may be utilized to deposit the second cobalt tungsten cap layer  124 . 
     According to some embodiments of the invention, the second cobalt tungsten cap layer  124  may contain a substantially homogeneous mixture of cobalt and tungsten, a graded cobalt tungsten mixture, or alternating cobalt and tungsten layers, or a combination thereof. Examples of a second cobalt tungsten cap layer  124  are depicted in  FIGS. 4A-4D . 
       FIGS. 4A-4D  show simplified schematic cross-sectional views of cobalt tungsten cap layers on Cu paths according to embodiments of the invention.  FIG. 4A  shows a schematic cross-sectional view of a second cobalt tungsten cap layer  124   a  on Cu path  122  according to one embodiment. The second cobalt tungsten cap layer  124   a  can contain a substantially homogeneous cobalt tungsten mixture. The second cobalt tungsten cap layer  124   a  may be deposited by simultaneously exposing the Cu path  122  to a second cobalt precursor gas and a second tungsten precursor gas in a deposition process. 
       FIG. 4B  shows a schematic cross-sectional view of a second cobalt tungsten cap layer  124   b  on Cu path  122  according to another embodiment. The second cobalt tungsten cap layer  124   b  may contain a cobalt metal layer  124   b   1  on the Cu path  122  and a tungsten metal layer  124   b   2  on the cobalt metal layer  124   b   1 . The cobalt metal layer  124   b   1  may be formed by exposing the Cu path  122  to a second cobalt precursor gas, and subsequently, the tungsten metal layer  124   b   2  may be deposited by exposing the cobalt metal layer  124   b   1  to a second tungsten precursor gas. According to other embodiments, the second cobalt tungsten cap layer  124   b  may contain additional alternating cobalt metal layers  124   b   1  and tungsten metal layers  124   b   2 . 
     According to one embodiment, the second cobalt tungsten cap layer  124   b  may contain a cobalt metal layer  124   b   1  on the Cu path  122  and a cobalt-rich cobalt tungsten layer  124   b   2  on the cobalt metal layer  124   b   1 . The cobalt-rich cobalt tungsten layer  124   b   2  can have a tungsten content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance cobalt. 
     According to one embodiment, the second cobalt tungsten cap layer  124   b  may contain a cobalt metal layer  124   b   1  on the Cu path  122  and a tungsten-rich cobalt tungsten layer  124   b   2  on the cobalt metal layer  124   b   1 . The tungsten-rich cobalt tungsten layer  124   b   2  can have a cobalt content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance tungsten. 
       FIG. 4C  shows a schematic cross-sectional view of a second cobalt tungsten cap layer  124   c  on a Cu path  122  according to another embodiment. The second cobalt tungsten cap layer  124   c  may contain a tungsten metal layer  124   c   1  on the Cu path  122  and a cobalt metal layer  124   c   2  on the tungsten metal layer  124   c   1 . The tungsten metal layer  124   c   1  may be formed by exposing the Cu path  122  to a second tungsten precursor gas, and subsequently, the cobalt metal layer  124   c   2  may be deposited by exposing the tungsten metal layer  124 C 1  to a second cobalt precursor gas. According to other embodiments, the second cobalt tungsten cap layer  124   c  may contain additional alternating tungsten metal layers  124   c   1  and cobalt metal layers  124   c   2 . 
     According to one embodiment, the second cobalt tungsten cap layer  124   c  may contain a tungsten metal layer  124   c   1  on the Cu path  122  and a cobalt-rich cobalt tungsten metal layer  124   c   2  on the tungsten metal layer  124   c   1 . The cobalt-rich cobalt tungsten layer  124   c   2  can have a tungsten content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance cobalt. 
     According to one embodiment, the second cobalt tungsten cap layer  124   c  may contain a tungsten metal layer  124   c   1  on the Cu path  122  and a tungsten-rich cobalt tungsten metal layer  124   c   2  on the tungsten metal layer  124   c   1 . The tungsten-rich cobalt tungsten layer  124   c   2  can have a cobalt content less than 50, 40, 30, 20, 10, or 5 atomic percent, and balance tungsten. 
       FIG. 4D  shows a schematic cross-sectional view of a second cobalt tungsten cap layer  124   d  on a Cu path  122  according to still another embodiment. The second cobalt tungsten cap layer  124   d  may have a varying cobalt/tungsten ratio from an external surface of the second cobalt tungsten cap layer  124   d  to an interface between the second cobalt tungsten cap layer  124   d  and the Cu path  122 . In some examples, the cobalt/tungsten ratio may increase or decrease from a first cobalt/tungsten ratio at an external surface of the second cobalt tungsten cap layer  124   d  to a second cobalt/tungsten ratio at an interface between the second cobalt tungsten cap layer  124   d  and the Cu path  122 . For example, the second cobalt tungsten cap layer  124   d  may be deposited by varying a ratio of a flow rate of the second cobalt precursor gas to a flow rate of the second tungsten precursor gas in a second deposition gas from a first ratio to a second ratio different than the first ratio. 
     According to other embodiments, the second cobalt tungsten cap layer  124  depicted in  FIG. 1E  may contain any combinations of the second cobalt tungsten cap layers  124   a - 124   d  depicted in  FIGS. 4A-4D . For example, the second cobalt tungsten cap layer  124  may contain the second cobalt tungsten cap layers  124   a  and  124   d  in any order on the Cu path  122 . 
     According to embodiments of the invention, the second cobalt tungsten cap layer  124  in  FIG. 1E  and the second cobalt tungsten cap layers  124   a - 124   d  in  FIGS. 4A-4D  may consist essentially of cobalt and tungsten. 
     Referring back to  FIG. 1E , according to one embodiment, the second cobalt tungsten cap layer  124  may be nitrided by exposing the second cobalt tungsten cap layer  124  to a second nitriding gas. The second nitriding gas can contain a thermally excited or plasma excited second nitriding gas selected from NH 3 , N 2 , N 2 +H 2 , NH(CH 3 ) 2 , N 2 H 4 , or N 2 H 3 CH 3 , or a combination thereof. 
     According to one embodiment of the invention, the second cobalt tungsten cap layer  124  may be selectively deposited on the Cu path  122  as depicted in  FIG. 1E . Selective deposition of the second cobalt tungsten cap layer  124  on the Cu path  122  relative to the low-k dielectric material  104  is enabled by a lack of or low concentration of metal precursor (e.g., cobalt or tungsten precursor) adsorption sites on the low-k dielectric material  104  compared to on the Cu path  122 . This leads to a short incubation time for deposition of the second cobalt tungsten cap layer  124  on the Cu path  122  first relative to the low-k dielectric material  104 . 
     In one example, an average thickness of the second cobalt tungsten cap layer  124  can be between 5 angstrom and 50 angstrom, for example about 5, 10, 15, 20, 30, 40, or 50 angstrom. In some examples, the second cobalt tungsten cap layer  124  may have an average thickness between 2 and 5 angstrom. However, embodiments of the invention are not limited to those thicknesses and the second cobalt tungsten cap layer  124  that is thicker than 50 angstrom may be formed and utilized. According to one embodiment, a surface coverage of the second cobalt tungsten cap layer  124  on the Cu path  122  may be incomplete with gaps that expose the Cu path  122 . According to one embodiment, the treating of the Cu path  122  and the subsequent deposition of the second cobalt tungsten cap layer  124  may be performed in the same process chamber. Alternately, the treating and subsequent cobalt tungsten film deposition may be performed in different process chambers. 
     Following selective deposition of the second cobalt tungsten cap layer  124  on the Cu path  122 , the partially manufactured semiconductor device depicted in  FIG. 1E  is further processed.  FIG. 1F  shows a conformal cap layer  126  deposited on the second cobalt tungsten cap layer  124  and on the low-k dielectric regions  114 . The conformal cap layer  126  can, for example, contain silicon nitride or silicon carbon nitride. According to one embodiment of the invention, prior to depositing the cap layer  126 , the second cobalt tungsten cap layer  124  and the low-k dielectric regions  114  may be treated in a plasma process or in a non-plasma process at a substrate temperature between 150° C. and 400° C. in the presence of H 2 , N 2 , or NH 3 , or a combination thereof. In one example, the second cobalt tungsten cap layer  124  and the low-k dielectric regions  114  may be treated with NH x  (x≦3) radicals and H radicals as described above. 
     According to other embodiments of the invention, the first cobalt tungsten cap layer  112  may be omitted from the dual damascene interconnect structure  100  depicted in  FIGS. 1B-1F . 
     A dual damascene opening is illustrated in the exemplary embodiments of  FIGS. 1A-1F , but embodiments of the invention may be applied to other types of openings and recessed features found in integrated circuit design. In one example,  FIG. 2A  schematically shows a cross-sectional view of a via interconnect structure according to one embodiment of the invention. The interconnect structure  200  contains a via  210  within a dielectric material  218  over a metallization layer  222  in a dielectric material  214 . The interconnect structure  200  further contains a diffusion barrier  220  around the metallization layer  222 , an etch stop layer  216 , and a substrate  212 . The dielectric material  218  can, for example, contain one or more of the low-k dielectric materials described above in reference to the low-k dielectric material  104  in  FIG. 1A . 
     In another example,  FIG. 2B  schematically shows a cross-sectional view of a trench interconnect structure according to one embodiment of the invention. The trench interconnect structure  201  contains a trench  211  within dielectric material  218  and an etch stop layer  216 . In yet another example,  FIG. 2C  schematically shows a cross-sectional view of a trench interconnect structure according to another embodiment of the invention. The trench interconnect structure  202  contains a trench  213  within dielectric material  218 . 
     As will be appreciated by those skilled in the art, embodiments of the invention can be readily applied to the interconnect structures depicted in  FIGS. 2A-2C . For example, a first cobalt tungsten cap layer may be deposited over the metallization layer  222  in the via  210 , and the via  210  filled with Cu metal. After the filling, planarization of the Cu metal, and optional treating of the planarized Cu metal, a second cobalt tungsten cap layer may be deposited on the planarized Cu metal. In other examples, the trenches  211  and  213  may be filled with Cu metal and planarized, optionally treated, and a cobalt tungsten cap layer deposited on the planarized Cu metal. 
       FIG. 5  depicts a schematic view of a processing system for processing a substrate in accordance with embodiments of the invention. As those skilled in the art will readily recognize, the processing system  1  can be utilized to perform various deposition processes, substrate treating processes, and substrate nitriding processes. The deposition processes can include chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD). The processing system  1  includes a process chamber  10  having a substrate holder  20  configured to support a substrate  25  upon which a cobalt tungsten cap layer is to be formed. The process chamber  10  further contains an upper assembly  30  coupled to a first process material supply system  40 , a second process material supply system  42 , a third process material supply system  44 , and a purge gas supply system  46 . Additionally, the processing system  1  includes a first power source  50  coupled to the process chamber  10  and configured to optionally generate plasma in the process chamber  10 , and a substrate temperature control system  60  coupled to substrate holder  20  and configured to elevate and control the temperature of the substrate  25 . 
     The processing system  1  may be configured to process 200 mm substrates (wafers), 300 mm substrates, or larger-sized substrates. In fact, it is contemplated that the processing system  1  may be configured to process substrates, wafers, or flat panel displays regardless of their size, as would be appreciated by those skilled in the art. Therefore, while aspects of the invention will be described in connection with the processing of a semiconductor substrate, the invention is not limited solely thereto. 
     The first process material supply system  40 , the second process material supply system  42 , and the third process material supply system  44  are configured to simultaneously or sequentially introduce a first process material, a second process material, or a third process material to the process chamber  10 . Sequential introduction of the first process material, the second process material, and the third process material can be cyclical, or it may be acyclical with variable time periods between introduction of the first, second, and third process materials. 
     The first process material can, for example, contain a cobalt precursor gas. The cobalt precursor gas can contain Co 2 (O) 8 , Co 4 (CO) 12 , CoCp(CO) 2 , Co(CO) 3 (NO), CO 2 (CO) 6 (HCC t Bu), Co(acac) 2 , Co(Cp) 2 , Co(Me 5  Cp) 2 ), Co(EtCp) 2 , cobalt(II) hexafluoroacetylacetonate hydrate, cobalt tris(2,2,6,6-tetramethyl-3,5-heptanedionate), cobalt(III) acetylacetonate, bis(N,N′-diisopropylacetamidinato) cobalt, or tricarbonyl allyl cobalt, or a combination of two or more thereof. For instance, the cobalt precursor gas can originate as a solid phase, a liquid phase, or a gaseous phase, and it may be delivered to process chamber  10  in a gaseous phase in a first or second deposition gas with or without the use of a carrier gas. 
     The second process material can, for example, contain a tungsten precursor gas. In one example, the tungsten precursor gas can contain a tungsten carbonyl precursor gas, for example W(CO) 6 . In another example, the tungsten precursor gas can contain a tungsten halide precursor gas, for example, WX 6  where X═F, Cl, or Br. 
     The third process material can, for example, contain a reducing gas, a nitriding gas, or a combination thereof, that may be delivered to process chamber  10  with or without the use of a carrier gas. The reducing gas may contain H 2  and may be exposed to the substrate  25  as thermally excited H 2  (non-plasma excited H 2 ) or plasma excited H 2 . The nitriding gas may contain NH 3 , NH 3 , N 2 , NH(CH 3 ) 2 , N 2 H 4 , or N 2 H 3 CH 3 , or a combination of two or more thereof, and may be exposed to the substrate  25  as thermally excited or plasma excited nitriding gas. 
     Additionally, the purge gas supply system  46  can be configured to introduce a purge gas to process chamber  10 . For example, the introduction of purge gas may occur between introduction of the first process material and the second process material, between the second process material and the third process material, or following the introduction of the third process material. The purge gas can comprise an inert gas, such as a noble gas (i.e., helium, neon, argon, xenon, krypton), N 2 , or H 2 . 
     Still referring to  FIG. 5 , the processing system  1  includes a plasma generation system  51  configured to generate a plasma in the process chamber  10  during formation of the cobalt tungsten film, for example during introduction of the first, second, or third process materials into the process chamber  10 . Furthermore the plasma generation system  51  may generate a plasma in the process chamber during introduction of the third process material into the process chamber  10  in a nitriding process. The plasma generation system can include the first power source  50  coupled to the process chamber  10 , and configured to couple power to gases in the process chamber  10 . The first power source  50  may be a variable power source and may include a radio frequency (RF) generator and an impedance match network, and may further include an electrode through which RF power is coupled to the plasma in process chamber  10 . The electrode can be formed in the upper assembly  30 , and it can be configured to oppose the substrate holder  20 . The impedance match network can be configured to optimize the transfer of RF power from the RF generator to the plasma by matching the output impedance of the match network with the input impedance of the process chamber  10 , including the electrode, and plasma. For instance, the impedance match network serves to improve the transfer of RF power to plasma in the process chamber  10  by reducing the reflected power. Match network topologies (e.g. L-type, π-type, T-type, etc.) and automatic control methods are well known to those skilled in the art. 
     Alternatively, the first power source  50  may include a RF generator an impedance match network, and an antenna, such as an inductive coil, through which RF power is coupled to plasma in process chamber  10 . The antenna can, for example, include a helical or solenoidal coil, such as in an inductively coupled plasma source or helicon source, or it can, for example, include a flat coil as in a transformer coupled plasma source. 
     Alternatively, the first power source  50  may include a microwave frequency generator, and may further include a microwave antenna and microwave window through which microwave power is coupled to plasma in process chamber  10 . The coupling of microwave power can be accomplished using electron cyclotron resonance (ECR) technology, or it may be employed using surface wave plasma technology, such as a slotted plane antenna (SPA), as described in U.S. Pat. No. 5,024,716, the contents of which are herein incorporated by reference in its entirety. 
     According to one embodiment of the invention, the processing system  1  includes a substrate bias generation system  53  configured to optionally generate or assist in generating a plasma (through substrate holder biasing) during at least a portion of deposition of a cobalt tungsten cap layer, during substrate treating processes, and during substrate nitriding processes. The substrate bias generation system  53  can include a substrate power source  52  coupled to the process chamber  10 , and configured to couple power to substrate  25 . The substrate power source  52  may include a RF generator and an impedance match network, and may further include an electrode through which RF power is coupled to substrate  25 . The electrode can be formed in substrate holder  20 . For instance, substrate holder  20  can be electrically biased at a RF voltage via the transmission of RF power from a RF generator (not shown) through an impedance match network (not shown) to substrate holder  20 . A typical frequency for the RF bias can range from about 0.1 MHz to about 100 MHz, and can be 13.56 MHz. RF bias systems for plasma processing are well known to those skilled in the art. Alternatively, RF power is applied to the substrate holder electrode at multiple frequencies. In one example, the substrate power source  52  may generate plasma in the process chamber  10  through biasing of the substrate holder  20  while the upper assembly  30  is grounded. 
     Although the plasma generation system  51  and the substrate bias generation system  53  are illustrated in  FIG. 5  as separate entities, they may indeed comprise one or more power sources coupled to substrate holder  20 . 
     According to an embodiment of the invention, the processing system  1  may contain an inductive couple plasma (ICP) source (not shown) to generate a plasma in the process chamber  10 . 
     Still referring to  FIG. 5 , processing system  1  includes substrate temperature control system  60  coupled to the substrate holder  20  and configured to elevate and control the temperature of substrate  25 . Substrate temperature control system  60  comprises temperature control elements, such as a cooling system including a re-circulating coolant flow that receives heat from substrate holder  20  and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system to the substrate holder  20 . Additionally, the temperature control elements can include heating/cooling elements, such as resistive heating elements, or thermo-electric heaters/coolers, which can be included in the substrate holder  20 , as well as the chamber wall of the process chamber  10  and any other component within the processing system  1 . 
     In order to improve the thermal transfer between substrate  25  and substrate holder  20 , the substrate holder  20  can include a mechanical clamping system, or an electrical clamping system, such as an electrostatic clamping system, to affix substrate  25  to an upper surface of substrate holder  20 . Furthermore, substrate holder  20  can further include a substrate backside gas delivery system configured to introduce gas to the back-side of substrate  25  in order to improve the gas-gap thermal conductance between substrate  25  and substrate holder  20 . Such a system can be utilized when temperature control of the substrate  25  is required at elevated or reduced temperatures. For example, the substrate backside gas system can comprise a two-zone gas distribution system, wherein the helium gas gap pressure can be independently varied between the center and the edge of substrate  25 . 
     Furthermore, the process chamber  10  is further coupled to a pressure control system  32 , including a vacuum pumping system  34  and a valve  36 , through a duct  38 , wherein the pressure control system  32  is configured to controllably evacuate the process chamber  10  to a pressure suitable for forming a cobalt tungsten cap layer on substrate  25 , treating the substrate  25 , or performing a nitriding process, and suitable for use of the first, second, and third process materials. The vacuum pumping system  34  can include a turbo-molecular vacuum pump (TMP) or a cryogenic pump capable of a pumping speed up to about 5000 liters per second (and greater) and valve  36  can include a gate valve for throttling the chamber pressure. In conventional processing systems, a 300 to 5000 liter per second TMP is generally employed. Moreover, a device for monitoring chamber pressure (not shown) can be coupled to the process chamber  10 . The pressure measuring device can, for example, be a capacitance manometer. 
     The processing system  1  includes a controller  70  that can be used to configure any number of processing elements of the processing system  1 , and the controller  70  can collect, provide, process, store, and display data from processing elements. The controller  70  can comprise a number of applications for controlling one or more of the processing elements. For example, controller  70  can include a graphic user interface (GUI) component (not shown) that can provide easy to use interfaces that enable a user to monitor and/or control one or more processing elements. Alternatively, or in addition, controller  70  can be coupled to one or more additional controllers/computers (not shown), and controller  70  can obtain setup and/or configuration information from an additional controller/computer. 
     The controller  70  can comprise a microprocessor, memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs of the processing elements of the processing system  1  as well as monitor outputs from the processing system  1 . For example, a program stored in the memory may be utilized to activate the inputs to the aforementioned components of the processing system  1  according to a process recipe in order to perform a deposition process, a treating process, or a nitriding process. 
     The controller  70  may be implemented as a general purpose computer system that performs a portion or all of the microprocessor based processing steps of embodiments of the invention in response to a processor executing one or more sequences of one or more instructions contained in a memory. Such instructions may be read into the controller memory from another computer readable medium, such as a hard disk or a removable media drive. One or more processors in a multi-processing arrangement may also be employed as the controller microprocessor to execute the sequences of instructions contained in main memory. In alternative embodiments, hard-wired circuitry may be used in place of or in combination with software instructions. Thus, embodiments are not limited to any specific combination of hardware circuitry and software. 
     The controller  70  includes at least one computer readable medium or memory, such as the controller memory, for holding instructions programmed according to the teachings of the invention and for containing data structures, tables, records, or other data that may be necessary to implement the present invention. Examples of computer readable media are compact discs, hard disks, floppy disks, tape, magneto-optical disks, PROMs (EPROM, EEPROM, flash EPROM), DRAM, SRAM, SDRAM, or any other magnetic medium, compact discs (e.g., CD-ROM), or any other optical medium, punch cards, paper tape, or other physical medium with patterns of holes, a carrier wave (described below), or any other medium from which a computer can read. 
     Stored on any one or on a combination of computer readable media, the present invention includes software for controlling the controller  70 , for driving a device or devices for implementing embodiments the invention, and/or for enabling the controller to interact with a human user. Such software may include, but is not limited to, device drivers, operating systems, development tools, and applications software. Such computer readable media further includes the computer program product of the present invention for performing all or a portion (if processing is distributed) of the processing performed in implementing embodiments of the invention. 
     The computer code devices of the present invention may be any interpretable or executable code mechanism, including but not limited to scripts, interpretable programs, dynamic link libraries (DLLs), Java classes, and complete executable programs. Moreover, parts of the processing of the present invention may be distributed for better performance, reliability, and/or cost. 
     The term “computer readable medium” as used herein refers to any medium that participates in providing instructions to the processor of the controller  70  for execution. A computer readable medium may take many forms, including but not limited to, non-volatile media, volatile media, and transmission media. Non-volatile media includes, for example, optical, magnetic disks, and magneto-optical disks, such as the hard disk or the removable media drive. Volatile media includes dynamic memory, such as the main memory. Moreover, various forms of computer readable media may be involved in carrying out one or more sequences of one or more instructions to processor of controller for execution. For example, the instructions may initially be carried on a magnetic disk of a remote computer. The remote computer can load the instructions for implementing all or a portion of the present invention remotely into a dynamic memory and send the instructions over a network to the controller  70 . 
     The controller  70  may be locally located relative to the processing system  1 , or it may be remotely located relative to the processing system  1 . For example, the controller  70  may exchange data with the processing system  1  using at least one of a direct connection, an intranet, the Internet and a wireless connection. The controller  70  may be coupled to an intranet at, for example, a customer site (i.e., a device maker, etc.), or it may be coupled to an intranet at, for example, a vendor site (i.e., an equipment manufacturer). Additionally, for example, the controller  70  may be coupled to the Internet. Furthermore, another computer (i.e., controller, server, etc.) may access, for example, the controller  70  to exchange data via at least one of a direct connection, an intranet, and the Internet. As also would be appreciated by those skilled in the art, the controller  70  may exchange data with the processing system  1  via a wireless connection. 
     A plurality of embodiments for integrating cobalt tungsten deposition and cobalt tungsten cap layers into manufacturing of semiconductor devices to improve EM and SM in Cu metallization has been disclosed in various embodiments. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms that are used for descriptive purposes only and are not to be construed as limiting. For example, the term “on” as used herein (including in the claims) does not require that a film “on” a patterned substrate is directly on and in immediate contact with the substrate; there may be a second film or other structure between the film and the substrate. 
     Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.