Patent Publication Number: US-11024510-B2

Title: Pattern forming method and method of manufacturing semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2019-170980, filed Sep. 20, 2019, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a pattern forming method and a method of manufacturing a semiconductor device. 
     BACKGROUND 
     It is often required to form a fine pattern on a semiconductor substrate in order to achieve high integration in a semiconductor device. One method of forming the fine pattern on a semiconductor substrate is a nano-imprinting method. 
     In the nano-imprinting method, a template (also sometimes referred to as a mold or imprint mold) having a fine pattern therein or thereon is brought into contact with a resist material applied to a surface of a layer to be processed/patterned. By such imprinting/molding, a finely patterned resist layer can be formed. The fine pattern can then be transferred into the underlying layer by etching using the patterned resist layer as an etch mask or the like. 
     With nano-imprinting methods, a thin, residual resist layer generally remains in the recessed regions of the imprinted pattern. It is generally required to remove this thin resist layer by etching. Problems may arise in that such removal of the residual resist layer can result in a thickness loss in the projecting/protruding regions of the imprinted resist pattern, and as the residual resist layer is reduced/removed, a dimension of the imprinted pattern may be changed by the removal process. Particularly, such a problem becomes more important when the pattern being imprinted is finer (e.g., narrower feature dimensions). 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIGS. 1-5  depict schematic cross-sectional views for explaining aspects of a method of manufacturing a semiconductor device according to a first embodiment. 
         FIG. 6  is a schematic diagram of a reactive ion etching device used in a method of manufacturing a semiconductor device according to a first embodiment. 
         FIGS. 7-10  depict schematic cross-sectional views for explaining additional aspect of a method of manufacturing a semiconductor device according to a first embodiment. 
         FIGS. 11-13  depict schematic cross-sectional views for explaining aspects of a method of manufacturing a semiconductor device according to a comparative example. 
         FIGS. 14-21  depict schematic cross-sectional views for explaining aspects of a method of manufacturing a semiconductor device according to a second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a pattern forming method includes forming an organic layer on a first layer. The organic layer includes a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region, located between the first region and the second region, that has a third thickness less than the first thickness and the second thickness and a third width. A second layer containing silicon oxide is formed on a surface of the organic layer in a process chamber of a reactive ion etching device. The third region is then etched in the process chamber using the second layer as a mask. 
     Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following description, the same or similar members and the like will be denoted by the same reference numerals, and members that have been once described will not be described as appropriate. 
     Qualitative and quantitative analyses of a chemical composition of a materials and/or components used in a pattern forming method and a method of manufacturing a semiconductor device in the present specification may be conducted by, for example, secondary ion mass spectrometry (SIMS) and energy dispersive X-ray spectroscopy (EDX). For measurements of thicknesses, distances, or other dimensions, a scanning electron microscope (SEM) or a transmission electron microscope (TEM) may be used. 
     Hereinafter, a pattern forming method and a method of manufacturing a semiconductor device according to example embodiments will be described with reference to the drawings. 
     First Embodiment 
     A pattern forming method according to a first embodiment includes forming, on a surface of a first layer, an organic layer which includes a first region having a first thickness and a first width, a second region having a second thickness and a second width, and a third region located between the first region and the second region and having a third thickness smaller than the first thickness and the second thickness and a third width, forming a second layer containing silicon oxide on a surface of the organic layer in a process chamber of a reactive ion etching device, and etching the third region using the second layer as a mask in the process chamber. 
     A method of manufacturing a semiconductor device according to the first embodiment includes forming a first layer on a semiconductor substrate and forming a pattern on the semiconductor substrate by using the pattern forming method. 
       FIGS. 1 to 5 and 7 to 10  are schematic cross-sectional views showing an example of a method of manufacturing a semiconductor device according to the first embodiment. FIG.  6  is a schematic diagram of a reactive ion etching device used in this example method of manufacturing a semiconductor device according to the first embodiment. 
     In the first embodiment, a case of forming a pattern by using a nano-imprinting method will be described as an example. In the first embodiment, a patterned metal layer for a line and space pattern is formed by using a nano-imprinting method and will be described as an example. 
     First, a semiconductor substrate  10  is prepared. The semiconductor substrate  10  is made of, for example, single crystal silicon. 
     Next, an insulating layer  12  is formed on the semiconductor substrate  10 . The insulating layer  12  is formed by using, for example, a chemical vapor deposition (CVD) method. The insulating layer  12  is made of, for example, silicon oxide or silicon nitride. 
     Next, a metal layer  14  is formed on the insulating layer  12 . The metal layer  14  is an example of a first layer. The metal layer  14  is a layer to be processed on which the pattern is formed. 
     The metal layer  14  is formed by using, for example, a CVD method. The metal layer  14  is made of, for example, tungsten, titanium nitride, or aluminum. 
     Next, as depicted in  FIG. 2 , a resist  16  is supplied to a surface of the metal layer  14 . The resist  16  is dispensed onto the surface of the metal layer  14  by using an ink jet method. The resist  16  can instead be applied onto the surface of the metal layer  14  by using a spin coat method or the like. 
     The resist  16  is initially liquid or substantially flowable. Resist  16  can be referred to as a nano-imprinting resist. The resist  16  comprises, for example, a photocurable resin, a thermosetting resin, or precursors of such materials. 
     Next, as depicted in  FIG. 3 , a template  18  (mold) having a pattern is brought into contact with the resist  16  on the surface of the metal layer  14 . For example, when the resist  16  contains a photocurable resin, a material of the template  18  is used for a light transmissive material. The template  18  is made of, for example, quartz glass. 
     The template  18  is brought into contact with the resist  16  on the surface of the metal layer  14 , such that the resist  16  is sucked up into a recess portion of the template  18  by capillary action. The pattern of the template  18  is transferred to the resist  16  to form a cured resist layer  20  on the surface of the metal layer  14  ( FIG. 4 ). The resist layer  20  is an example of an organic layer. 
     After the patterned and cured resist layer  20  is formed, the template  18  is separated from the resist layer  20 . 
       FIG. 5  shows a cross section parallel to a thickness direction of the resist layer  20 . The resist layer  20  includes a projected region  20   a  (first region), a projected region  20   b  (second region), a projected region  20   c , a recessed region  20   d  (third region), and a recessed region  20   e . The recessed region  20   d  is located between the projected region  20   a  and the projected region  20   b.    
     In the resist layer  20 , a plurality of projected regions including the projected region  20   a , the projected region  20   b , and the projected region  20   c  are arranged repeatedly. In addition, in the resist layer  20 , a plurality of recessed regions including the recessed region  20   d  and the recessed region  20   e  are arranged repeatedly. 
     The projected region  20   a  has a first thickness (t 1  in  FIG. 5 ) and a first width (w 1  in  FIG. 5 ). The recessed region  20   b  has a second thickness (t 2  in  FIG. 5 ) and a second width (w 2  in  FIG. 5 ). The recessed region  20   d  has a third thickness (t 3  in  FIG. 5 ) and a third width (w 3  in  FIG. 5 ). The third thickness t 3  is smaller than the first thickness t 1  and the second thickness t 2 . 
     The first thickness t 1  is the maximum value of a distance from the surface of the metal layer  14  to a (upper) surface of the projected region  20   a . In addition, the second thickness t 2  is the maximum value of a distance from the surface of the metal layer  14  to a surface of the projected region  20   b . In addition, the third thickness t 3  is the minimum value of a distance from the surface of the metal layer  14  to a surface of the recessed region  20   d.    
     A value obtained by dividing the difference between the first thickness t 1  and the third thickness t 3  (Δt=t 1 −t 3  in  FIG. 5 ) by the third width w 3  is referred to as the aspect ratio of the pattern of the resist layer  20 . The aspect ratio of the pattern of the resist layer  20  is in a range of, for example, 1 to 3. 
     The first width w 1 , the second width w 2 , and the third width w 3  are widths taken at a distance from the surface of the metal layer  14  equal to t 3 +Δt/2. 
     For example, the first thickness t 1  and the second thickness t 2  are equal. In addition, for example, the first width w 1  and the second width w 2  are equal. 
     The first thickness t 1  is in a range of, for example, 20 nm to 100 nm. The third thickness t 3  is in a range of, for example, 10 nm to 20 nm. 
     For example, a sum of the first width w 1  and the third width w 3  is in a range of 10 nm to 40 nm. That is, pitch of the projected regions repeatedly arranged is in a range of, for example, 10 nm to 40 nm. In other example, the pitch of the projected regions repeatedly arranged is in a range of, for example, 5 nm to 20 nm. 
     The first width w 1  is in a range of, for example, 5 nm to 20 nm. The third width w 3  is, for example, less than or equal to 40 nm. The third width w 3  is in a range of, for example, 5 nm to 20 nm. 
       FIG. 6  is a schematic diagram of a reactive ion etching device used in the method of manufacturing a semiconductor device according to the first embodiment. A reactive ion etching device  100  is a device using, for example, an inductively coupled plasma (ICP). 
     The reactive ion etching device  100  includes a process chamber  101 , a holder  102 , a source power supply  103 , a bias power supply  104 , an induction coil  105 , a first gas supply pipe  106 , a second gas supply pipe  107 , and a third gas supply pipe  108 . 
     The holder  102  is provided in the process chamber  101 . A substrate W (sample) is placed on the holder  102 . The holder  102  is, for example, an electrostatic chuck. 
     The source power supply  103  has a function of applying a first high frequency power to the induction coil  105 . The first high frequency power is applied to the induction coil  105 , such that a plasma is generated in the process chamber  101 . 
     The bias power supply  104  has a function of applying a second high frequency power to the holder  102 . 
     The first gas supply pipe  106  supplies first gas to the process chamber  101 . The second gas supply pipe  107  supplies second gas to the process chamber  101 . The third gas supply pipe  108  supplies third gas to the process chamber  101 . 
     The first gas contains, for example, silicon (Si). The first gas is, for example, silicon tetrachloride (SiCl 4 ) gas. The second gas contains, for example, oxygen (O). The second gas is, for example, oxygen (O 2 ) gas. The third gas is, for example, hydrogen bromide (HBr) gas. 
     For example, under some process conditions, the reactive ion etching device  100  deposits a film on a surface of the substrate W placed on the holder  102  using the plasma generated in the process chamber  101 . In addition, for example, under some process conditions, the reactive ion etching device  100  anisotropically etches the substrate W placed on the holder  102  using the plasma generated in the process chamber  101 . 
     After the resist layer  20  is formed, the semiconductor substrate  10  is introduced in the process chamber  101  of the reactive ion etching device  100 . The semiconductor substrate  10  is placed on the holder  102 . 
     In the process chamber  101 , a mask layer  22  (second layer) containing silicon oxide is formed on a surface of the resist layer  20  (see  FIG. 7 ). The mask layer  22  has, for example, silicon oxide as a main component. The mask layer  22  is primarily formed only on upper portions of the projected region  20   a ,  20   b ,  20   c  and need not be substantially formed on the recessed regions  20   d ,  20   e  or the side surfaces of the projected regions  20   a ,  20   b ,  20   c.    
     When the mask layer  22  is being formed in the process chamber  101  of the reactive ion etching device  100 , silicon tetrachloride (SiCl 4 ) gas is supplied from the first gas supply pipe  106  to the process chamber  101  and oxygen (O 2 ) gas is supplied from the second gas supply pipe  107  to the process chamber  101 , for example. Then, the process chamber  101  is held at a first pressure. Then, the first high frequency power is applied to the induction coil  105 , such that a plasma is generated in the process chamber  101 . The mask layer  22  containing silicon oxide is deposited on the surface of the resist layer  20  by a chemical vapor deposition method. 
     A plasma discharge time is in a range of, for example, two seconds to ten seconds. The plasma discharge time is a time when the first high frequency power is applied to the induction coil  105 . 
     The first pressure is in a range of, for example, 30 mTorr to 80 mTorr. The first high frequency power is, for example, 13 MHz and 250 W. 
     A fourth thickness of the mask layer  22  on the projected region  20   a  (t 4  in  FIG. 7 ) is greater than a fifth thickness of the mask layer  22  on the recessed region  20   d  (t 5  in  FIG. 7 ). The third thickness t 3  is, for example, between five and fifty times the fourth thickness t 4 . The fourth thickness is the maximum value of the thickness of the mask layer  22  on the projected region  20   a.    
     The fourth thickness t 4  is in a range of, for example, 2 nm to 10 nm. The fifth thickness t 5  is, for example, greater than 0 nm and less than or equal to 2 nm. 
     After the resist layer  20  has been formed, the recessed region  20   d  of the resist layer  20  is etched using the mask layer  22  as a mask in the process chamber  101  of the reactive ion etching device  100  ( FIG. 8 ). The recessed region  20   d  of the resist layer  20  is selectively etched with respect to the projected region  20   a  due to differential thicknesses of the mask layer  22  present in region. 
     When the recessed region  20   d  of the resist layer  20  is etched in the process chamber  101 , oxygen (O 2 ) gas is supplied from the second gas supply pipe  107  to the process chamber  101  and hydrogen bromide (HBr) gas is supplied from the third gas supply pipe  108  to the process chamber  101 , for example. Then, the process chamber  101  is held at a second pressure. Then, the second high frequency power is applied to the induction coil  105 , such that a plasma is generated in the process chamber  101 . Then, a third high frequency power is applied to the holder  102  to etch the recessed region  20   d.    
     The second pressure is in a range of, for example, 5 mTorr to 30 mTorr. The second high frequency power is, for example, 13 MHz and 350 W. In addition, the third high frequency power is, for example, 13 MHz and 100 W. 
     The first pressure is generally higher than the second pressure. The first pressure is, for example, between two times and ten times the second pressure. 
     Next, the metal layer  14  is etched using the remaining portions of the mask layer  22  and the resist layer  20  as a mask ( FIG. 9 ). The metal layer  14  is patterned by etching in this example. The etching of the metal layer  14  is performed in this example using a reactive ion etching device that is different from the reactive ion etching device  100  which is used for etches of the recessed region  20   d  of the resist layer  20 . 
     When the metal layer  14  is etched, the mask layer  22  on the projected region  20   a  can be completely removed by the etching, such that the first thickness t 1  of the projected region  20   a  is reduced, for example. 
     Next, the resist layer  20  remaining on the patterned metal layer  14  is removed ( FIG. 10 ). 
     A pattern of the metal layer  14  is formed on the semiconductor substrate  10  by the above method of manufacturing a semiconductor device. 
     Hereinafter, operations and effects of the method of manufacturing a semiconductor device according to the first embodiment will be described. 
       FIGS. 11 to 13  are schematic cross-sectional views showing the method of manufacturing a semiconductor device according to a comparative example. The method of manufacturing a semiconductor device according to the comparative example is different from the method of manufacturing a semiconductor device according to the first embodiment in that the mask layer  22  is not formed on the surface of the resist layer  20 . 
       FIG. 11  is a cross-sectional view showing a state in which the patterned resist layer  20  is on the surface of the metal layer  14 .  FIG. 11  is similar to the cross-sectional view in  FIG. 5  of the method of manufacturing a semiconductor device according to the first embodiment. 
     In the resist layer  20  formed by the nano-imprinting method, the recessed region  20   d  having the thickness smaller than that of the projected region  20   a  is formed between the projected region  20   a  and the projected region  20   b . If the recessed region  20   d  is not present on the resist layer  20 , for example, since a projected portion of the template  18  and the surface of the metal layer  14  are adsorbed, the template  18  is hard to be separated from the resist layer  20 . 
     The patterned resist layer  20  is formed on the surface of the metal layer  14 , and then the recessed region  20   d  is removed ( FIG. 12 ). For example, the recessed region  20   d  is removed by reactive ion etching using oxygen (O 2 ) gas and hydrogen bromide (HBr) gas. Since the projected region  20   a  is etched at the same time as recessed region  20   d , the first thickness t 1  of the projected region  20   a  is reduced. 
     Next, the metal layer  14  is etched using just the remaining resist layer  20  as a mask ( FIG. 13 ). The metal layer  14  is patterned by etching. If the first thickness t 1  of the projected region  20   a  before metal etching is small then, for example, the projected region  20   a  disappears during the etching of the metal layer  14  and thus during the etching of the metal layer  14  of a portion initially under the projected region  20   a  may be undesirably etched and thus the remaining portion of the metal layer  14  intended to remain as apart of a line pattern is thinned and/or etched in an unintended manner. Therefore, a problem that the thickness of the metal layer  14  after patterning becomes too small, the width of the metal layer  14  becomes too narrow, or even that the metal layer  14  disappears completely, may arise. 
     The problem becomes significant, for example, when the pattern is finer. For example, the problem becomes significant when a line and space pitch less than or equal to 40 nm. 
     When the pattern is finer, it is hard to make the third thickness t 3  of the recessed region  20   d  small in terms of separation of the template  18  from the resist layer  20 . In addition, when the pattern is finer, it is hard to make the first thickness t 1  of the projected region  20   a  larger. When the first thickness t 1  is increased after the first width w 1  of the projected region  20   a  is reduced, the projected region  20   a  is formed to be longer in the thickness direction. Therefore, when the template  18  is being separated from the resist layer  20 , the projected region  20   a  may be peeled off from the semiconductor substrate  10  together with the template  18 . 
     For this reason, when the pattern becomes finer, the first thickness t 1  of the projected region  20   a  is typically reduced while the third thickness t 3  of the recessed region  20   d  is substantially maintained. Accordingly, as the pattern becomes finer, the first thickness t 1  of the remaining projected region  20   a  etching the recessed region  20   d  will also be reduced. Thus, the first thickness t 1  of the projected region  20   a  before etching of the metal layer  14  may be insufficient, thus the thickness of the metal layer  14  after patterning may be reduced, or the metal layer  14  disappears. 
     In the method of manufacturing a semiconductor device according to the first embodiment, the mask layer  22  containing silicon oxide is formed on the surface of the resist layer  20  before removing the recessed region  20   d , as shown in  FIG. 7 . Therefore, as shown in  FIG. 8 , when the recessed region  20   d  is removed, the projected region  20   a  is not significantly etched, and the first thickness t 1  of the projected region  20   a  does not substantially change even after the recessed region  20   d  is removed. Accordingly, the first thickness t 1  of the projected region  20   a  is not insufficient before the metal layer  14  is etched. Thus, problems with the thickness of the metal layer  14  being reduced, the width of the metal layer  14  being reduced, or the metal layer  14  disappearing, may not arise. 
     There is a case in which the mask layer  22  is also initially present on the recessed region  20   d  when the recessed region  20   d  is being removed. However, as shown in  FIG. 7 , the fifth thickness t 5  of the mask layer  22  on the recessed region  20   d  is smaller than the fourth thickness t 4  of the mask layer  22  on the projected region  20   a . Therefore, the mask layer  22  on the recessed region  20   d  can be completely removed by etching when the recessed region  20   d  is removed while still leaving a portion of the mask layer  22  on the projected region  20   a.    
     In the method of manufacturing a semiconductor device according to the first embodiment, the mask layer  22  is formed in the same process chamber  101  which is used for the etching of the recessed region  20   d . The deposition of the mask layer  22  on the surface of the resist layer  20  and the etching of the recessed region  20   d  of the resist layer  20  are thus performed in the same process chamber  101 , back-to-back, thereby shortening the manufacturing time of the semiconductor device. In addition, since the deposition of the mask layer  22  and the etching of the recessed region  20   d  are performed in the same process chamber  101 , generation of defects caused by taking the semiconductor substrate  10  out of the process chamber  101  can be avoided. Therefore, the yield of the semiconductor devices is improved. 
     The fourth thickness t 4  of the mask layer  22  on the projected region  20   a  is preferably five times or more the fifth thickness t 5  of the mask layer  22  on the recessed region  20   d , and more preferably ten times or more. By increasing the relative thickness of the fourth thickness t 4 , it is possible to more surely keep the mask layer  22  on the projected region  20   a  when the recessed region  20   d  is removed by etching. 
     The fifth thickness t 5  of the mask layer  22  on the recessed region  20   d  is preferably less than or equal to 2 nm. 
     The fourth thickness t 4  of the mask layer  22  on the projected region  20   a  is preferably greater than or equal to 2 nm. 
     The fourth thickness t 4  of the mask layer  22  provided on the projected region  20   a  is preferably less than or equal to 10 nm. By keeping to this thickness or less, it is possible to limit the fifth thickness t 5  of the mask layer  22  formed on the recessed region  20   d  to a manageable amount. 
     The aspect ratio of the pattern of the resist layer  20  is preferably greater than or equal to 1, more preferably greater than or equal to 1.5, and still more preferably greater than or equal to 2. When the aspect ratio of the pattern of the resist layer  20  is increased, depositing speed of the mask layer  22  on the recessed region  20   d  during the forming the mask layer  22  is decreased as compared with a depositing speed of the mask layer  22  on the projected region  20   a.    
     The fifth thickness t 5  of the mask layer  22  provided on the recessed region  20   d  is preferably greater than or equal to 0 and more preferably greater than or equal to 0.5 nm. In this range, the mask layer  22  on the recessed region  20   d  tends to re-adhere on a side surface of the projected region  20   a  by being sputtered during etch processing and thus functions as a side wall protective film, when the recessed region  20   d  is being removed. Therefore, the etching of the side surface of the projected region  20   a  is limited when the recessed region  20   d  is being removed. Thus, reduction in the first width w 1  of the projected region  20   a  is limited when the recessed region  20   d  is being removed. 
     It is preferable that the first pressure in the process chamber  101  at the time of forming the mask layer  22  is higher than the second pressure in the process chamber  101  at the time of etching the recessed region  20   d.    
     As the first pressure when the mask layer  22  is deposited by a vapor phase growth method becomes higher, a depositing speed of the mask layer  22  becomes faster. By shortening deposition time of the mask layer  22 , it is possible to limit the increase in the fifth thickness t 5  of the mask layer  22  on the recessed region  20   d.    
     In addition, when the second pressure in the process chamber  101  during the etching the recessed region  20   d  becomes lower, etching of the side surface of the projected region  20   a  is reduced. Thus, reductions in the first width w 1  of the projected region  20   a  is prevented. 
     If increase in the fifth thickness t 5  of the mask layer  22  on the recessed region  20   d  is prevented, then the mask layer  22  on the recessed region  20   d  can be more surely removed and a reduction in the first width w 1  of the projected region  20   a  can be prevented. As such, it is preferable that the first pressure be higher than the second pressure. For example, the first pressure is preferably two times or more greater than the second pressure. And more preferably the first pressure is three times or more greater than the second pressure. 
     The sum of the first width w 1  and the third width w 3  is preferably less than or equal to 40 nm. That is, pitch of the projected regions repeatedly arranged is, for example, preferably less than or equal to 40 nm. 
     It is preferable that the reactive ion etching device  100  used in the formation of the mask layer  22  is a device using an inductively coupled plasma. The device using the inductively coupled plasma can stabilize and generate a high-density plasma. Therefore, it is possible to form a mask layer  22  having a small thickness. 
     Hereinafter, according to the pattern forming method and the method of manufacturing a semiconductor device of the first embodiment, it is possible to form a fine pattern. 
     Second Embodiment 
     In a pattern forming method according to a second embodiment, the organic layer includes a fourth region having a sixth thickness less than a first thickness and a fourth width greater than a third width. A second layer formed on the fourth region is removed before etching of the third region, which is different in this regard from the pattern forming method of the first embodiment. In other regards, the second embodiment is similar to the first embodiment and repeated description of such similar aspects may be omitted from the following description of the second embodiment. 
       FIGS. 14 to 21  are schematic cross-sectional views showing an example of the method of manufacturing a semiconductor device according to the second embodiment. 
     In the second embodiment, the case of forming a pattern by using a nano-imprinting method will be described as one possible example. In the second embodiment, a metal layer having a line and space pattern region and a wide space region is formed using a nano-imprinting method, but this just one possible example. 
     First, a semiconductor substrate  10  is prepared. The semiconductor substrate  10  is made of, for example, single crystal silicon. 
     Next, an insulating layer  12  is formed on the semiconductor substrate  10 . The insulating layer  12  is formed by using, for example, a chemical vapor deposition (CVD) method. The insulating layer  12  is made of, for example, silicon oxide or silicon nitride. 
     Next, a metal layer  14  is formed on the insulating layer  12 . The metal layer  14  is an example of a first layer. The metal layer  14  is the layer to be processed/patterned, which will remain in the final manufactured device, for example. 
     The metal layer  14  is formed by using, for example, a CVD method. The metal layer  14  is made of, for example, tungsten, titanium nitride, or aluminum. 
     Next, as depicted in  FIG. 14 , the resist layer  20  is formed on the surface of the metal layer  14  in a nano-imprinting method, which is substantially same as that described in the first embodiment. 
       FIG. 14  shows a cross section parallel to a thickness direction of the resist layer  20 . The resist layer  20  includes a projected region  20   a  (first region), a projected region  20   b  (second region), a projected region  20   g , a recessed region  20   d  (third region), a recessed region  20   e , and a wide region  20   f  (fourth region). The recessed region  20   d  is located between the projected region  20   a  and the projected region  20   b . The wide region  20   f  is located between the projected region  20   a  and the projected region  20   g.    
     The projected region  20   a  has a first thickness (t 1  in  FIG. 14 ) and a first width (w 1  in  FIG. 14 ). The projected region  20   b  has a second thickness (t 2  in  FIG. 14 ) and a second width (w 2  in  FIG. 14 ). The recessed region  20   d  has a third thickness (t 3  in  FIG. 14 ) and a third width (w 3  in  FIG. 14 ). The wide region  20   f  has a sixth thickness (t 6  in  FIG. 14 ) and a fourth width (w 4  in  FIG. 14 ). The second thickness t 2  and the fifth thickness t 5  are smaller than the first thickness t 1 . In general,  FIG. 14  depicts a dense pattern region (e.g., the region in which projected regions  20   a  and  20   b  are located) and a sparse pattern region (e.g., the region in which projected region  20   g  is located). 
     The aspect ratio of the pattern of the resist layer  20  is in a range of, for example, 1 to 3. 
     The first thickness t 1  is in a range of, for example, 20 nm to 100 nm. The third thickness t 3  is in a range of, for example, 10 nm to 20 nm. The sixth thickness t 6  is in a range of, for example, 10 nm to 20 nm. 
     A sum of the first width w 1  and the third width w 3  is in a range of, for example, 10 nm to 40 nm. That is, pitch of the projected regions repeatedly arranged is in a range of, for example, 10 nm to 40 nm. In some examples, pitch of the projected regions repeatedly arranged is in a range of, for example, 5 nm to 20 nm. 
     The first width w 1  is in a range of, for example, 5 nm to 20 nm. The third width w 3  is in a range of, for example, 5 nm to 20 nm. The fourth width w 4  is in a range of, for example, 50 nm to 100 μm. 
     In the process chamber  101  of the reactive ion etching device  100  (shown in  FIG. 6 ), a mask layer  22  containing silicon oxide is formed on a surface of the resist layer  20 , as depicted in  FIG. 15 . The mask layer  22  uses, for example, silicon oxide as a main component. The mask layer  22  is formed on the projected region  20   a , the projected region  20   b , the projected region  20   g , and the wide region  20   f , and need not necessarily be formed on the recessed region  20   d  depending of selected processing conditions and the like. 
     A fourth thickness of the mask layer  22  on the projected region  20   a  (t 4  in  FIG. 15 ) and a seventh thickness of the mask layer  22  on the wide region  20   f  (t 7  in  FIG. 15 ) are both greater than a fifth thickness of the mask layer  22  on the recessed region  20   d  (t 5  in  FIG. 15 ). The fourth thickness t 4  and the seventh thickness t 7  are, for example, between five times and fifty times greater than the fifth thickness t 5 . 
     The fourth thickness t 4  is in a range of, for example, 2 nm to 10 nm. The fifth thickness t 5  is, greater than 0 nm but less than or equal to 2 nm. The seventh thickness t 7  is in a range of, for example, 2 nm to 10 nm. 
     After the resist layer  20  and mask layer  22  are formed, a photoresist layer  30  having the open/uncovered region corresponding in position to the wide region  20   f  is formed, as depicted in  FIG. 16 . The photoresist layer  30  can be formed by known photolithographic methods. 
     Next, the mask layer  22  on the wide region  20   f  is removed in a processing using the photoresist layer  30  as a mask, as depicted in  FIG. 17 . The mask layer  22  can be removed by, for example, known wet etching methods. 
     Next, the photoresist layer  30  is removed, as depicted in  FIG. 18 . 
     Next, the recessed region  20   d  and the wide region  20   f  of the resist layer  20  are then etched in the process chamber  101  of the reactive ion etching device  100  ( FIG. 19 ). The recessed region  20   d  and the wide region  20   f  of the resist layer  20  are etched leaving the projected regions  20   a ,  20   b , and  20   g  (or at least substantial portions thereof). 
     Next, the metal layer  14  is etched using the mask layer  22  and the resist layer  20  as a mask, as depicted in  FIG. 20 . The metal layer  14  is patterned by this etching. For example, the etching of the metal layer  14  is performed using a reactive ion etching device that is different from the reactive ion etching device  100 . 
     In general, when the metal layer  14  is etched, the mask layer  22  on the projected regions  20   a ,  20   b , and  20   g  will be completely removed by the etching process, such that the first thickness t 1  of the projected region  20   a  may be somewhat reduced, for example. 
     Next, any resist layer  20  remaining on the patterned metal layer  14  is removed, as depicted in  FIG. 21 . 
     Thus, it is possible to form a fine pattern including a pattern having a wide space therein, for example, a pattern with a mixed pattern density of sparse and dense features or the like. 
     The case in which the second layer (which is the layer to be processed) is a metal layer and the pattern is formed directly thereon is described as an example in the first and second embodiments. However, for example, it is possible to use an insulating layer as the second layer and have the pattern formed on the insulating layer and transferred thereto. 
     The case of forming the line and space pattern is described as an example in the first and second embodiments. However, the present disclosure is not limited thereto and is possible to apply the present disclosure to the case of forming contact holes or the like. 
     A case in which a pattern including a projected region and a recessed region was formed on the organic layer by using a nano-imprinting method was described as an example in the first and second embodiments. However, it is possible to also apply the teachings of the present disclosure to a case in which such a pattern is formed in the organic layer by using self-assembly of a block copolymer or the like. 
     In addition, the first and second embodiments are described in conjunction with the manufacturing of a semiconductor device, but the present disclosure is not limited to the manufacture of semiconductor device. For example, it is possible to also apply the present disclosure to the case of manufacturing many other products such as a high-density recording medium and a liquid crystal display device, or, in general, any product requiring fine patterning or the like. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the present disclosure. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the present disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the present disclosure.