Patent Publication Number: US-7592678-B2

Title: CMOS transistors with dual high-k gate dielectric and methods of manufacture thereof

Description:
This is a continuation in part of U.S. patent application Ser. No. 10/870,616, entitled “CMOS Transistor With Dual High-k Gate Dielectric and Method of Manufacture Thereof,” filed on Jun. 17, 2004, which is incorporated herein by reference. 

   TECHNICAL FIELD 
   The present invention relates generally to semiconductor devices, and more particularly to structures for and methods of manufacturing complimentary metal oxide semiconductor (CMOS) transistor devices. 
   BACKGROUND 
   Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating (or dielectric) layers, conductive layers and semiconductive layers of material over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon. 
   A transistor is an element that is utilized extensively in semiconductor devices. There may be millions of transistors on a single integrated circuit (IC), for example. A common type of transistor used in semiconductor device fabrication is a metal oxide semiconductor field effect transistor (MOSFET). 
   Early MOSFET processes used one type of doping to create either positive or negative channel transistors. More recent designs, referred to as complimentary metal oxide semiconductor (CMOS) devices, use both positive and negative channel devices in complimentary configurations. While this requires more manufacturing steps and more transistors, CMOS devices are advantageous because they utilize less power, and the devices may be made smaller and faster. 
   The gate dielectric for MOSFET devices has in the past typically comprised silicon dioxide, which has a dielectric constant of about 3.9. However, as devices are scaled down in size, using silicon dioxide for a gate dielectric becomes a problem because of gate leakage current, which can degrade device performance. Therefore, there is a trend in the industry towards the development of the use of high dielectric constant (k) materials for use as the gate dielectric in MOSFET devices. The term “high k materials” as used herein refers to a dielectric material having a dielectric constant of about 4.0 or greater. 
   High k gate dielectric development has been identified as one of the future challenges in the 2002 edition of International Technology Roadmap for Semiconductors (ITRS), incorporated herein by reference, which identifies the technological challenges and needs facing the semiconductor industry over the next 15 years. For low power logic (for portable electronic applications, for example), it is important to use devices having low leakage current, in order to extend battery life. Gate leakage current must be controlled in low power applications, as well as sub-threshold leakage, junction leakage, and band-to-band tunneling. 
   To fully realize the benefits of transistor scaling, the gate oxide thickness needs to be scaled down to less than 2 nm. However, the resulting gate leakage current makes the use of such thin oxides impractical in many device applications where low standby power consumption is required. For this reason, the gate oxide dielectric material will eventually be replaced by an alternative dielectric material that has a higher dielectric constant. However, device performance using high k dielectric materials tends to suffer from trapped charge in the dielectric layer, which deteriorates the mobility, making the drive current lower than in transistors having silicon dioxide gate oxides, thus reducing the speed and performance of transistors having high k gate dielectric materials. 
   Another problem with using a high-k dielectric material as the gate electrode of a CMOS transistor is referred to in the art as a “Fermi-pinning” effect, which occurs at the interface of the gate electrode and gate dielectric material. Fermi-pinning is a problem that occurs in CMOS devices having both poly-silicon and metal gates. The Fermi-pinning effect causes a threshold voltage shift and low mobility, due to the increased charge caused by the Fermi-pinning effect. Fermi-pinning causes an assymmetric turn-on threshold voltage V t  for the two transistors of a CMOS device, which is undesirable. 
   In prior art CMOS transistor designs, the gate dielectric material for the CMOS was typically SiO 2  and the gate electrode was polysilicon. A symmetric threshold voltage V t  for the PMOS device and the NMOS device of a prior art CMOS device was easily achievable using SiO 2  as a gate dielectric material. For the PMOS device, the gate electrode was P-type, which was typically achieved by using polysilicon doped with B as the PMOS gate electrode material, as examples. For the NMOS device, the gate electrode was N-type, which was typically achieved by using polysilicon doped with P as the NMOS gate electrode material, as examples. 
   However, when attempts are made to use hafnium-based dielectric materials, a high k dielectric material, for the gate dielectric material of a CMOS device, problems arise. For the NMOS device, polysilicon doped with P may be used as the material for the gate electrode, and an N-type gate is achievable, which is desired. However, for the PMOS device, if polysilicon doped with B, for example, is used for the gate electrode material, the hafnium-based gate electrode material interacts with adjacent materials, caused by Fermi-pinning, resulting in an N-type gate, which is ineffective for the PMOS device. An N-type gate on the PMOS transistor is undesirable: the PMOS device gate should be P-type to optimize the CMOS device performance and achieve a symmetric V tp  and V tn . Thus, a CMOS device having an N-type gate electrode for the PMOS transistor has an asymmetric V tn  and V tp , due to the Fermi-pinning effect of the high k dielectric material. Efforts have been made to improve the quality of high-k dielectric films and resolve the Fermi-pinning problems, but the efforts have resulted in little success. 
   In electronics, the “work function” is the energy (usually measured in electron volts) needed to remove an electron from the Fermi level to a point an infinite distance away outside the surface. Work function is a material property of any material, whether the material is a conductor, semiconductor, or dielectric. The work function of a metal is fixed and cannot be changed unless the material composition is changed, for example. The work function of a semiconductor can be changed by doping the semiconductor material. For example, undoped polysilicon has a work function of about 4.5 eV, whereas polysilicon doped with boron has a work function of about 5.0 eV. The work function of a semiconductor or conductor directly affects the threshold voltage of a transistor when the material is used as a gate electrode. 
   In prior art CMOS devices utilizing SiO 2  as the gate dielectric material, the work function can be changed or tuned by doping the polysilicon used for the gate electrode material. However, the Fermi-pinning caused by the use of high k gate dielectric materials as the gate dielectric pins or fixes the work function, so that doping the polysilicon gate material does not change the work function. Thus, a symmetric V t  for the NMOS and PMOS transistors of a CMOS device having a high k material for the gate dielectric cannot be achieved by doping polysilicon gate material, as in SiO 2  gate dielectric CMOS devices. 
   Thus, what is needed in the art is a CMOS transistor device design and method of manufacturing thereof that has a high-k gate dielectric and a symmetric V t  for the p channel metal oxide semiconductor (PMOS) and n channel metal oxide semiconductor (NMOS) transistors of the CMOS device. 
   SUMMARY OF THE INVENTION 
   These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by preferred embodiments of the present invention which provide a CMOS transistor device design and method of manufacture thereof having a substantially symmetric threshold voltage V t  for the PMOS and NMOS transistors. A different gate dielectric material is used for the PMOS transistor than for the NMOS transistor. Advantageously, the novel invention uses the Fermi-pinning effect to achieve a symmetric V t , by disposing a Fermi-pinning material immediately beneath the gate of the PMOS transistor. 
   In accordance with a preferred embodiment of the present invention, a semiconductor device includes a workpiece, a first transistor formed in a first region of the workpiece, and a second transistor formed in a second region of the workpiece. The first transistor comprises a first gate dielectric including a first element comprising Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb. The second transistor comprises a second gate dielectric including a second element comprising Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Al, the second element being different than the first element. 
   In accordance with another preferred embodiment of the present invention, a method of manufacturing a semiconductor device includes providing a workpiece, the workpiece comprising a first region and a second region, and forming a first transistor in the first region of the workpiece. The first transistor comprises a first gate dielectric including a first element comprising Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb. The method includes forming a second transistor in the second region of the workpiece, the second transistor comprising a second gate dielectric including a second element comprising Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Al, the second element being different than the first element. 
   Advantages of preferred embodiments of the present invention include providing a method of fabricating a CMOS device and structure thereof wherein the PMOS transistor and NMOS transistor have a symmetric V t . The threshold voltage V t  is decreased compared to prior art CMOS devices, and the flat band voltage is easier to tune. Embodiments of the invention may utilize high-k dielectric materials as the gate dielectric, using polysilicon, metal or FUSI gate electrodes. The metal gate electrodes may comprise either single metal or dual-work function metals, e.g., the gate electrode for the PMOS and NMOS transistor may be the same material or different materials. 
   The foregoing has outlined rather broadly the features and technical advantages of embodiments of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of embodiments of the invention will be described hereinafter, which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1 through 9  show cross-sectional views of a semiconductor device at various stages of manufacturing in accordance with a preferred embodiment of the present invention, wherein a CMOS device comprises a PMOS transistor having a first gate dielectric material and an NMOS transistor having a second gate dielectric material, wherein the first gate dielectric material and the second gate dielectric material comprise different materials; 
       FIG. 10  shows an another preferred embodiment of the present invention, wherein the PMOS transistor gate dielectric comprises a first layer and a second layer, wherein the second layer is adjacent and abuts the PMOS transistor gate electrode, and wherein the second layer comprises a Fermi-pinning material; 
       FIGS. 11 through 16  show cross-sectional views of a method of forming a CMOS device having different gate dielectric materials for the PMOS transistor and NMOS transistor in accordance with another preferred embodiment of the present invention at various stages of manufacturing; and 
       FIGS. 17 and 18  show cross-sectional views of a method of forming a CMOS device having different gate dielectric materials for the PMOS transistor and NMOS transistor in accordance with yet another preferred embodiment of the present invention at various stages of manufacturing. 
   

   Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. 
   DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
   The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
   High-k gate dielectric materials generally yield orders of magnitude lower gate leakage current than SiO 2  gate dielectric materials with the same effective oxide thickness (EOT). For low standby power (LSTP) applications, the use of a high-k material for a gate dielectric is a potential solution in the roadmap for the advanced technology nodes. Using high-k materials for gate dielectrics in CMOS devices has resulted in good EOT, lower gate leakage (J g ), mobility and hysteresis parameters, but the devices suffer from lack of V t  controllability. In order to make high-k materials as gate dielectric materials useful in CMOS applications, it is desirable that the CMOS device should be manufactured such that V tn  and V tp  are symmetrical; e.g., V tn =0.3 V and V tp =−0.3 V, as examples. 
   Attempts to use a high-k dielectric material such as HfO 2  have been problematic. In particular, attempts have been made to use HfO 2 , which is a high-k dielectric material having a dielectric constant of about 25, as the gate dielectric for both the PMOS and NMOS FETs of a CMOS device. The work function of a polysilicon gate using a HfO 2  gate dielectric has been found to be pinned, as a result of Fermi-pinning, at a point close to the conduction band of polysilicon, causing the polysilicon gate to function as N-type polysilicon, even for the polysilicon gate doped with p-type dopant, for the PMOS device. Therefore, the threshold voltage V tp  of the PMOS device was much higher than expected; e.g., V tp  was −1.2 V while V tn  was 0.4 V, which is very asymmetric. The Fermi-pinning effect is suspected to be related to the Hf—Si bond at the gate electrode-gate dielectric interface, which is almost impossible to avoid with a polysilicon-HfO 2  gate stack structure. Therefore, the Fermi-pinning effect makes the use of polysilicon as a gate electrode incompatible with Hf-based high-k gate dielectric materials in CMOS devices. Fully silicided polysilicon (FUSI) gates have also exhibited Fermi-pinning effects and are undesirable for use as gate electrode materials when a high-k dielectric such as hafnium is used for a gate dielectric. 
   Embodiments of the present invention derive technical advantages by disposing a thin layer of a Fermi-pinning material such as Al 2 O 3  adjacent and abutting a gate electrode of a PMOS device, disposed over a high-k dielectric material such as HfO 2 , while using single layer of high-k dielectric material as the gate dielectric for the NMOS device. By doing so, polysilicon or FUSI may be used as the gate electrode while still achieving a symmetric V tp  and V tn  for the CMOS device. In the PMOS portion, a polysilicon-Al 2 O 3  interface sets the work function in the p-type regime, and in the NMOS portion, a polysilicon-Hf interface sets the work function in the n-type regime. 
   The present invention will be described with respect to preferred embodiments in a specific context, namely a CMOS transistor. Embodiments of the present invention may also be applied, however, to other semiconductor device applications where two or more transistors are required. Note that in the drawings shown, only one PMOS device and one NMOS device are shown; however, there may be many PMOS and NMOS devices formed during each of the manufacturing processes described herein. 
     FIGS. 1 through 9  show cross-sectional views of a semiconductor device  100  at various stages of manufacturing in accordance with a preferred embodiment of the present invention. With reference now to  FIG. 1 , there is shown a semiconductor device  100  in a cross-sectional view including a workpiece  102 . The workpiece  102  may include a semiconductor substrate comprising silicon or other semiconductor materials covered by an insulating layer, for example. The workpiece  102  may also include other active components or circuits, not shown. The workpiece  102  may comprise silicon oxide over single-crystal silicon, for example. The workpiece  102  may include other conductive layers or other semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece  102  may also comprise bulk Si, SiGe, Ge, SiC, or a silicon-on-insulator (SOI) substrate, as examples. 
   The workpiece  102  includes a first region  104  and a second region  106 . The first region  104  comprises a region where a first transistor comprising a PMOS device or PMOSFET (as indicated by the “P” in  FIG. 1 ), as examples, will be formed. The second region  106  comprises a region where a second transistor comprising an NMOS device or NMOSFET (as indicated by the “N” in  FIG. 1 ) will be formed, as examples. The PMOS device and NMOS device are not shown in  FIG. 1 : see  FIGS. 8 and 9  at  136  and  138 , respectively. 
   The first region  104  and the second region  106  may be separated by an optional shallow trench isolation (STI) region  108  formed in the workpiece  102 , as shown. The first region  104  may be lightly doped with N type dopants, and the second region  106  may be lightly doped with P type dopants. In general, the workpiece  102  is doped with N or P type dopants depending on whether the junctions of the transistor to be formed will be P or N type, respectively. 
   The workpiece  102  is preferably cleaned using a pre-gate clean process to remove any contaminant or native oxide from the top surface of the workpiece  102 . The pre-gate treatment may comprise a HF, HCl or ozone based cleaning treatment, as examples, although the pre-gate treatment may alternatively comprise other chemistries. 
   A hard mask  112  is deposited over the workpiece  102 , as shown in  FIG. 2 . The hard mask  112  preferably comprises a first layer  114  and a second layer  116  disposed over the first layer  114 , as shown. Alternatively, the hard mask  112  may comprise a single layer of an oxide or a nitride material, for example. In the embodiment shown in  FIG. 2 , the first layer  114  of the hard mask  112  preferably comprises about 300 Angstroms of an oxide material such as tetraethoxysilate (TEOS), although alternatively, the first layer  114  may comprise other insulating materials deposited in other dimensions, for example. The first layer  114  may be deposited by plasma-enhanced chemical vapor deposition (PECVD) or by other deposition techniques, as examples. The second layer  116  preferably comprises about 1500 Angstroms of a nitride material such as Si x N y , for example, although alternatively, the second layer  116  may comprise other insulating materials deposited in other dimensions, for example. The second layer  114  may be deposited by PECVD or by other deposition techniques, as examples. 
   A first layer of photoresist  118  is deposited over the second layer  116  of the hard mask  112 , as shown in  FIG. 2 . The first layer of photoresist  118  may patterned with a mask using traditional lithography techniques, although alternatively, the first layer of photoresist  118  may be directly patterned using electron beam lithography (EBL) or other direct etching technique, as examples. 
   The first layer of photoresist  118  is used to pattern at least the second layer  116  of the hard mask  112 , as shown in  FIG. 3 . For example, exposed portions of the second layer  116  in the second region  106  may be etched using the first layer of photoresist  118  remaining over the first region  104  as a mask. The etch process may be designed to stop when the first layer  114  of the hard mask  112  is reached. The first layer of photoresist  118  is then stripped or removed, and the second layer  116  is then used as a mask to pattern the first layer  114 . Alternatively, the first layer of photoresist  118  may be used as a mask to etch both the second layer  116  and the first layer  114  of the hard mask  112 , for example. The first layer of photoresist  118  is then stripped, as shown in  FIG. 3 . 
   A first gate dielectric material  120  is deposited over the patterned hard mask  112  and exposed portions of the workpiece  102 , as shown in  FIG. 3 . The first gate dielectric material  120  preferably comprises a high-k dielectric material having a dielectric constant of about 4.0 or greater, in one embodiment. The first gate dielectric material  120  preferably comprises HfO 2 , HfSiO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , SiO 2 , nitrides thereof, Si x N y , SiON, or combinations thereof, as examples, although alternatively, the first gate dielectric material  120  may comprise other high k insulating materials or other dielectric materials. The first gate dielectric material  120  may comprise a single layer of material, or alternatively, the first gate dielectric material  120  may comprise two or more layers. In one embodiment, one or more of these materials can be included in the first gate dielectric material  120  in different combinations or in stacked layers. The first gate dielectric material  120  may be deposited by chemical vapor deposition (CVD), atomic layer deposition (ALD), metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), or jet vapor deposition (JVD), as examples, although alternatively, the first gate dielectric material  120  may be deposited using other suitable deposition techniques. The first gate dielectric material  120  preferably comprises a thickness of about 10 Å to about 60 Å in one embodiment, although alternatively, the first gate dielectric material  120  may comprise other dimensions, such as about 80 Å or less, as an example. 
   In some embodiments, the first gate dielectric material  120  preferably comprises a first element comprising Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, or Yb. The first element may comprise an element from Column IIIb of the Periodic Table, or a Lanthanoid from the Periodic Table, as examples. In one embodiment, the first gate dielectric material  120  preferably comprises a La-containing insulating material, for example. The first gate dielectric material  120  preferably comprises a first material such as the first element combined with a second material, such as Hf, Zr, Ta, Ti, Al, or Si, and also combined with either O, N, or both O and N. In another embodiment, the first gate dielectric material  120  preferably comprises a first material comprising a first element, a second material comprising Hf, Zr, Ta, Ti, Al, or Si, and also either O, N, or both O and N, and further comprising a third material, such as Ti, Sr, or Sc. As examples, the first gate dielectric material  120  may comprise LaHfO or LaHfTiO, although alternatively, the first gate dielectric material  120  may comprise other La-containing insulating materials or first element-containing materials. 
   Advantageously, if the first transistor  138  (see  FIG. 9 ) to be formed in the first region  104  comprises an NMOS transistor, if the first gate dielectric material  120  comprises La, then the La shifts the flatband voltage V FB  of the NMOS transistor, allowing tunability of the threshold voltage V t . The other types of first elements of the first gate dielectric material  120  described herein also are preferably adapted to tune the V t  of the NMOS transistor, for example. 
   A first gate material  122  is deposited over the first gate dielectric material  120 , also shown in  FIG. 3 . The first gate material  122  preferably comprises a conductor, such as a metal or polysilicon, although alternatively, other conductive and semiconductive materials may be used for the first gate material  122 . In the embodiment shown in  FIGS. 1 through 9 , the first gate material  122  preferably comprises polysilicon or other semiconductor materials. However, the first gate material  122  may alternatively comprise TiN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, NiSi x , CoSi x , TiSi x , Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi, TaCN, a fully silicided gate material (FUSI), other metals, and/or combinations thereof, as examples. If the gate material  122  comprises FUSI, for example, polysilicon may be deposited over the gate dielectric material  120 , and a metal such as nickel may be deposited over the polysilicon, although other metals may be used. The workpiece  102  may then be heated to about 600 or 700 degrees C. to form a single layer of nickel silicide. 
   The first gate material  122  may comprise a plurality of stacked gate materials, such as a metal underlayer with a polysilicon cap layer disposed over the metal underlayer, or a combination of a plurality of metal layers that form a gate electrode stack. The first gate material  122  may be deposited using CVD, PVD, ALD, or other deposition techniques, as examples. The first gate material  122  preferably comprises a thickness of about 1,500 Å, although alternatively, the first gate material  122  may comprise about 1,000 Å to about 2,000 Å, or other dimensions, for example. 
   If the first gate material  122  comprises a semiconductive material, such as in the embodiment shown in  FIGS. 1 through 9 , preferably, the first gate material  122  is N-doped, by doping the first gate material  122  with N type dopants such as phosphorous or antimony, for example. Doping the first gate material  122  makes the semiconductive material conductive or more conductive. 
   A second layer of photoresist  124  is deposited over the first gate material  122 , as shown in  FIG. 3 . The second layer of photoresist  124  may patterned using a mask using traditional lithography techniques to remove the second layer of photoresist  124  from over the first region  104  of the workpiece  102 , as shown, although alternatively, the second layer of photoresist  124  may be directly patterned. 
   The second layer of photoresist  124  is used as a mask to pattern the first gate material  122  and the first gate dielectric material  120 , and to remove the hard mask  112  from the first region  104  of the workpiece  102 , as shown in  FIG. 4 . For example, exposed portions of the first gate material  122 , first gate dielectric material  120 , and hard mask  112  may be etched away from the first region  104  of the workpiece  102  using the second layer of photoresist  124  as a mask. The second layer of photoresist  124  is then stripped or removed from over the second region  106  of the workpiece  102 . Any excess first gate material  122  and first gate dielectric material  120  may be removed from over the optional STI region  108  proximate the interface of the first region  104  and second region  106  using a chemical-mechanical polish (CMP) process or an etch process, for example, leaving the structure shown in  FIG. 4 . The exposed surface of the workpiece  102  may be cleaned using a pre-gate clean process. 
   Next, a second gate dielectric material  126  is deposited over exposed portions of the workpiece  102  in the first region  104  and over the patterned first gate material  122  and first gate dielectric material  120  in the second region  106 , as shown in  FIG. 5 . The second gate dielectric material  126  preferably comprises a different material than the first gate dielectric material  126  in one embodiment of the present invention. The second gate dielectric material preferably comprises a high-k dielectric material having a dielectric constant of about 4.0 or greater, in one embodiment. The second gate dielectric material  126  preferably comprises HfO 2 , HfSiO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , nitrides thereof, Si x N y , SiON, SiO 2 , or combinations thereof, as examples, although alternatively, the second gate dielectric material  126  may comprise other high k insulating materials or other dielectric materials. 
   The second gate dielectric material  126  may comprise a single layer of material, or alternatively, the second gate dielectric material  126  may comprise two or more layers, wherein the top layer comprises a Fermi-pinning material, which will be described further herein with reference to  FIG. 10 . In one embodiment, one or more of these materials can be included in the second gate dielectric material  126  in different combinations or in stacked layers. The second gate dielectric material  126  may be deposited by CVD, ALD, MOCVD, PVD, or JVD, as examples, although alternatively, the second gate dielectric material  126  may be deposited using other suitable deposition techniques. The second gate dielectric material  126  preferably comprises a thickness of about 10 Å to about 60 Å in one embodiment, although alternatively, the second gate dielectric material  126  may comprise other dimensions, such as about 80 Å or less, as an example. The second gate dielectric material  126  preferably comprises a Fermi-pinning material such as an aluminum-containing material disposed at the top surface thereof. 
   In some embodiments, the second gate dielectric material  126  preferably comprises an insulating material comprising a second element, the second element being different than the first element of the first gate dielectric material  120 , for example. The second element in these embodiments preferably comprises Sc, Y, Lu, Lr, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, or Al, as examples. The second element may comprise an element from Column IIIb of the Periodic Table, a Lanthanoid from the Periodic table, Al or an Al-containing material, as examples. In one embodiment, e.g., when the second transistor  136  comprises a PMOS transistor (see  FIG. 9 ) the second gate dielectric material  126  preferably comprises a Y-containing insulating material or an Al-containing insulating material, for example. These materials are particularly beneficial for tuning or shifting the V FB  and thus provide tunability of the V t  of the PMOS transistor  136 , for example. The other types of second elements described herein are also preferably adapted to provide the ability to tune the V t  of the PMOS transistor  136  by varying the amount of the second element in the second gate dielectric material  126 , for example. 
   In some embodiments, the second gate dielectric material  126  preferably comprises a first material such as Y or Al combined with a second material, such as Hf, Zr, Ta, Ti, Al, or Si, and also combined with either O, N, or both O and N, as example, as another example. In another embodiment, the second gate dielectric material  126  preferably comprises a first material comprising Y or Al, a second material comprising Hf, Zr, Ta, Ti, Al, or Si, and also either O, N, or both O and N, and further comprising a third material, such as Ti, Sr, or Sc. As examples, the second gate dielectric material  126  may comprise YHfO, YHfTiO, or AlO, although alternatively, the second gate dielectric material  126  may comprise other materials. 
   Next, a second gate material  128  is deposited over the second gate dielectric material  126 , also shown in  FIG. 5 . The second gate material  128  preferably comprises a conductor, such as a metal or polysilicon, although alternatively, other conductive and semiconductive materials may be used for the second gate material  128 . In the embodiment shown in  FIGS. 1-9 , the second gate material  128  preferably comprises polysilicon or other semiconductor materials. However, the second gate material  128  may alternatively comprise TiN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, NiSi x , CoSi x , TiSi x , Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi, TaCN, fully silicided gate material (FUSI), and/or combinations thereof, as examples. The second gate material  128  may comprise a plurality of stacked gate materials, such as a metal underlayer with a polysilicon cap layer disposed over the metal underlayer, or a combination of a plurality of metal layers that form a gate electrode stack. The second gate material  128  may be deposited using CVD, PVD, ALD, or other deposition techniques, as examples. The second gate material  128  preferably comprises a thickness of about 1,500 Å, although alternatively, the second gate material  128  may comprise about 1,000 Å to about 2,000 Å, or other dimensions, for example. The second gate material  128  may comprise the same material as the first gate material  122 , or alternatively, the second gate material  128  may comprise a different material than the first gate material  122 , for example. 
   If the second gate material  128  comprises a semiconductive material, such as in the embodiment shown in  FIGS. 1 through 9 , preferably, the second gate material  128  is P-doped, by doping the second material  128  with a P type dopant such as boron, as an example. Doping the second gate material  128  makes the semiconductive material conductive or more conductive. 
   A third layer of photoresist  130  is deposited over the second gate material  128 , as shown in  FIG. 5 . The third layer of photoresist  130  may be patterned using a mask by traditional lithography techniques to remove the third layer of photoresist  130  from the second region  106  of the workpiece  102 , as shown, although alternatively, the third layer of photoresist  130  may be directly patterned. 
   The third layer of photoresist  130  is then used as a mask to pattern the second gate material  128  and second gate dielectric material  126 , as shown in  FIG. 6 . For example, exposed portions of the second gate material  128  and second gate dielectric material  126  may be etched away from the second region  106  of the workpiece  102  using the third layer of photoresist  130  as a mask. The third layer of photoresist  130  is then stripped or removed from over the first region  104  of the workpiece  102 . 
   Any excess second gate material  128  and second gate dielectric material  126  (e.g., as shown at peak  132 ) may be removed from over the optional STI region  108  proximate the interface of the first region  104  and second region  106  using a chemical-mechanical polish (CMP) process or an etch process, for example (not shown), leaving the structure shown in  FIG. 7 . 
   Preferably using a single lithography step, e.g., using a single layer of photoresist and using a single mask to pattern the photoresist, the first gate material  120 , the first gate dielectric material  122 , the second gate material  126 , and the second gate dielectric material  128  are simultaneously patterned with a desired pattern for a CMOS device, leaving the structure shown in  FIG. 8 , wherein a PMOS transistor  136  is formed in the first region  104 , and an NMOS transistor  138  is formed in the second region  106 . 
   Referring again to  FIG. 7 , note that while a vertical portion  160  of the second gate dielectric material  126  formed on the sidewall of the first gate material  122  is left remaining in the structure shown in  FIG. 7 , this is not problematic, because portion  160  is etched away or removed when the PMOS and NMOS transistors  136  and  138  are formed, as shown in  FIG. 8 . 
   Manufacturing of the CMOS device  100  is then continued to complete the fabrication of the CMOS device  100 . For example, spacers  134  may be formed on the sidewalls of the gate electrode materials  128  and  122 , and on the sidewalls of the gate dielectric materials  126  and  120 , forming the structure shown in  FIG. 9 . Source and drain regions S 1  and D 1 , and S 2  and D 2  may be formed in exposed surfaces of the PMOS transistor  136  and the NMOS transistor  138 , respectively. For example, the source and drain regions S 1  and D 1  may be doped with P type dopants to form p-n-p junctions in the PMOS transistor  136 . Likewise, the source and drain regions S 2  and D 2  may be doped with N type dopants to form n-p-n junctions in the NMOS transistor  138 . 
   One or more insulating materials (not shown) may be deposited over the PMOS transistor  136  and NMOS transistor  138 , and contacts may be formed in the insulating materials in order to make electrical contact with the gates, sources and/or drains. Additional metallization and insulating layers may be formed and patterned over the top surface of the insulating material and contacts. A passivation layer (not shown) may be deposited over the insulating layers or the PMOS transistor  136  and NMOS transistor  138 . Bond pads (also not shown) may be formed over contacts, and the semiconductor device  100  may then be singulated or separated into individual die. The bond pads may be connected to leads of an integrated circuit package (not shown) or other die, for example, in order to provide electrical contact to the transistors  136  and  138  of the semiconductor device  100 . 
   Thus, a novel semiconductor CMOS device  100  comprising a PMOS transistor  136  and an NMOS transistor  138  is formed, as shown in  FIG. 9 , wherein the gate dielectric GD 1  of the PMOS transistor  136  comprises a different material from the material of the gate dielectric GD 2  of the NMOS transistor  138 . The gate dielectric GD 1  of the PMOS transistor  136  preferably comprises a Fermi-pinning material abutting the gate G 1 . The PMOS transistor  136  includes a source S 1  and a drain D 1  separated by a first channel region C 1 . A gate dielectric GD 1  is disposed over the first channel region C 1 , and a gate G 1  is disposed over the gate dielectric GD 1 . The NMOS transistor  138  includes a source S 2  and a drain D 2  separated by a channel region C 2 . A gate dielectric GD 2  is disposed over the channel region C 2 , and a gate G 2  is disposed over the gate dielectric GD 2 . A spacer  134  comprising an oxide or nitride, as examples, may be formed on the sidewalls of the gates G 1  and G 2 , and gate dielectrics GD 1  and GD 2 , as shown. 
   Advantageously, in the embodiments where the first gate dielectric material  120  comprises a La-containing insulating material and the second gate dielectric material  126  comprises a Y-containing insulating material, the concentrations of the La and Y in the first gate dielectric material  120  and second gate dielectric material  126  may be varied to achieve a substantially symmetric V t . For example, the first gate dielectric material  120  may comprise about 5 to 95% La and about 95 to 5% of another element, such as Hf, Zr, Ta, Ti, Al, or Si. The higher the amount of La in the first gate dielectric material  120 , the higher the V tn  of the NMOS transistor  138 . The La in the gate dielectric material  120  shifts the flatband voltage V FB  of the NMOS transistor  138 , which shifts the threshold voltage V t  of the NMOS transistor  138  (V tn ). Similarly, the second gate dielectric material  126  may comprise about 5 to 95% Y or Al and about 95 to 5% of another element, such as Hf, Zr, Ta, Ti, Al, or Si. The higher the amount of Y or Al in the second gate dielectric material  126 , the higher the V tp  of the PMOS transistor  136 . The Y or Al in the gate dielectric material  126  shifts the flatband voltage V FB  of the PMOS transistor  136 , which shifts the threshold voltage V t  of the PMOS transistor  136  (V tp ). Because La and Y (or Al) are adapted to shift the flatband voltages of the NMOS transistor  138  and PMOS transistor  136 , respectively, the threshold voltages of the PMOS transistor  136  and NMOS transistor  138  may be tuned to be symmetric in accordance with embodiments of the present invention. If the first element of the first gate dielectric material  120  and the second element of the second gate dielectric material  126  comprise other materials, the percentage of the first and second element may similarly be varied to tune the CMOS device to have symmetric V t &#39;s. 
   The gate and gate dielectric materials for either the PMOS transistor  136  or the NMOS transistor  138  may be deposited first, in accordance with embodiments of the present invention. For example, in the embodiment described herein, the NMOS transistor  138  gate dielectric and gate materials are deposited first. Alternatively, the PMOS transistor  136  gate dielectric and gate materials may be deposited first. 
   Another preferred embodiment of the present invention is shown in  FIG. 10 . Like numerals are used for the various elements that were described in  FIGS. 1 through 9 . To avoid repetition, each reference number shown in  FIG. 10  is not described again in detail herein. Rather, similar materials x02, x04, x06, x08, etc . . . are preferably used for the various material layers shown as were described for  FIGS. 1 through 9 , where x=1 in  FIGS. 1 through 9  and x=2 in  FIG. 10 . As an example, the preferred and alternative materials and dimensions described for the first and second gate dielectric materials  120  and  126  (GD 2  and GD 1 , respectively) in the description for  FIGS. 1 through 9  are preferably also used for the gate dielectric materials GD 1  and GD 2  of  FIG. 10 . 
   In this embodiment, the PMOS device  204  is shown in the right side of the figure, and the NMOS device  206  is shown on the left side. The gate dielectric GD 1  in this embodiment comprises at least two insulating layers: a first insulating layer  250  and a second insulating layer  252  disposed over the first insulating layer  250 . The first insulating layer  250  preferably comprises a high-k dielectric material, and may comprise HfO 2 , HfSiO x , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , nitrides thereof, Si x N y , SiON, SiO 2 , or combinations thereof, as examples, although alternatively, the first insulating layer  250  may comprise other high k insulating materials or other dielectric materials, such as La or other materials listed for the first element in  FIGS. 1-9 . The first insulating layer  250  preferably comprises a thickness of about 80 Angstroms or less, for example. The second insulating layer  250  preferably comprises about 10 to 60 Angstroms of a Fermi-pinning material. For example, the second insulating layer  250  preferably comprises an aluminum-containing material such as aluminum oxide (Al x O y  or Al 2 O 3 ) or nitrides thereof, such as Al x O y N 1-x-y , as examples, although alternatively, the second insulating layer  250  may comprise other materials that induce Fermi-pinning of the gate dielectric GD 1  to the gate electrode G 1  of the PMOS device  236 , such as a Y-containing insulating material or other materials listed for the second element in  FIGS. 1-9 . The second insulating layer  250  may be deposited or may be formed by implanting a Fermi-pinning material such as aluminum, for example. 
   This embodiment also shows other optional elements that may be included in the CMOS device  200 . Before forming spacers  234  over the sidewalls of the gate dielectric GD 1  and GD 2  and gates G 1  and G 2 , an optional thin insulator  248  may be formed over the top surface of the sources S 1  and S 2  and drains D 1  and D 2 , the sidewalls of the gate dielectrics GD 1  and GD 2 , and gates G 1  and G 2 , as shown. The spacers  234  are then formed over the thin insulator  248 . The thin insulator  248  may comprise an oxide, and the spacers  234  may comprise a nitride, although alternatively, other materials may be used for the thin insulator  248  and the spacers  234 , for example. 
   The sources S 1  and S 2  or the drains D 1  and D 2 , or the gates G 1  and G 2 , may include an optional silicide material  244  and  246 , respectively, formed at a top surface thereof (often referred to as a salicide because the formation of the silicide may be self-aligning). The silicide  244  and  246  may comprise about 100 Å to 300 Å of TiSi x , CoSi x , or NiSi x , although the silicide  244  and  246  may alternatively comprise other materials and thicknesses, as examples. The sources S 1  and S 2  and drains D 1  and D 2  may include lightly doped areas and deeper implantation regions, as shown. 
   The novel CMOS device of embodiments of the present invention described herein having a PMOS transistor and an NMOS transistor that have gate dielectrics comprising different materials may be manufactured using other methods. Two examples of such other methods are shown  FIGS. 11 through 16 , and  FIGS. 17 and 18 , respectively. Again, like numerals are used for the various elements that were described in  FIGS. 1 through 9  and  10 , and to avoid repetition, each reference number shown in  FIGS. 11 through 16 , and  FIGS. 17 and 18  is not described again in detail herein. Rather, similar materials x02, x04, x06, x08, etc . . . are preferably used for the various material layers shown as were described for  FIGS. 1 through 9 , where x=1 in  FIGS. 1 through 9 , x=2 in  FIG. 10 , x=3 in  FIGS. 11 through 16 , and x=4 in  FIGS. 17 and 18 . 
     FIGS. 11 through 16  show cross-sectional views of a method of forming a CMOS device having different gate dielectric materials for the PMOS transistor and NMOS transistor in accordance with another preferred embodiment of the present invention at various stages of manufacturing. In this embodiment, starting with a workpiece such as  102  shown in  FIG. 1 , the second gate dielectric material  326  is deposited over the entire top surface of the workpiece  302 . The second gate material  328  is then deposited over the entire surface of the second gate dielectric material  326 , as shown. If the second gate material  328  comprises polysilicon, the polysilicon may be implanted with a P-type dopant, for example. The second gate material  328  and the second gate dielectric material  326  are then removed from over the second region  306  of the workpiece, as shown in  FIGS. 12 and 13 . 
   For example, a hard mask  312  may be formed over the second gate material  328 . A layer of photoresist  318  may be deposited over the hard mask  312 , and the photoresist  318  may be removed from over the second region  306  using lithography techniques, for example, as shown in  FIG. 11 . The hard mask  312  may comprise about 300 Angstroms of TEOS, for example, although alternatively, the hard mask  312  may comprise other materials and dimensions. The photoresist  318  may be used as a mask to pattern the hard mask  312  and second gate material  328  to remove layers  312  and  328  from over the second region  306  of the workpiece  302 , and the photoresist  318  may be stripped or ashed, as shown in  FIG. 12 . The second gate dielectric material  326  may then be etched, using sputter and/or wet etch techniques, for example, to remove layer  326  from over the second region  306  of the workpiece  302 , using the hard mask  312  as a mask, leaving the structure shown in  FIG. 13 , for example. The hard mask  312  may be consumed or removed during the etching of the second gate dielectric material  326 , or alternatively, any excess hard mask  312  remaining over the second region  306  of the workpiece may be removed. 
   Next, the first gate dielectric material  320  and the first gate material  322  are deposited over the second region  306  of the workpiece  302  and over the second gate material  328  over the first region  304  of the workpiece  302 , as shown in  FIG. 14 . The first gate dielectric material  320  and the first gate material  322  are then removed from over the first region  304  of the workpiece. For example, a layer of photoresist  324  may be deposited over the workpiece  302 , and the photoresist  324  may be patterned to remove the photoresist  324  from over the first region  304  of the workpiece  302 , as shown in  FIG. 14 . The photoresist  324  is then used as a mask while the first gate material  322  and the first gate dielectric material  320  are moved from the first region  304  of the workpiece. The photoresist  324  is then removed, as shown in  FIG. 15 , and the top surface of the first gate material  322  and the second gate material  328  are then planarized, e.g., using CMP or an etch process, for example, leaving the structure shown in  FIG. 16 . 
   While a vertical portion  362  of the first gate dielectric material  320  formed on the sidewall of the second gate material  322  is left remaining in the structure shown in  FIG. 16 , this is not problematic, because portion  362  will be etched away when the PMOS and NMOS transistors are formed, as shown in  FIGS. 8 through 10 . 
   The embodiment shown in  FIGS. 11 through 16  is advantageous in that one less lithography mask is required, compared to the embodiment shown in  FIGS. 1 through 9 . 
     FIGS. 17 and 18  show cross-sectional views of a method of forming a CMOS device having different gate dielectric materials for the PMOS transistor and NMOS transistor in accordance with yet another preferred embodiment of the present invention. In this embodiment, advantageously, a single layer of gate dielectric material  466  and a single layer of gate material  468  are deposited over the top surface of the workpiece  402 . The single layer of gate dielectric material  466  and the single layer of gate material  468  may comprise one type of material, or may alternatively comprise one or more material layers, for example. The single layer of gate dielectric material  466  is also referred to herein as an insulating layer  466 , and the single layer of gate material  468  is also referred to herein as a conductive layer  468 , for example. 
   The gate dielectric material  466  preferably comprises HfO 2 , HfSiO x , Al 2 O 3 , ZrO 2 , ZrSiO x , Ta 2 O 5 , La 2 O 3 , nitrides thereof, Si x N y , SiON, SiO 2 , or combinations thereof, for example, although alternatively, the gate dielectric material  466  may comprise other materials. The gate dielectric material  466  may comprise a thickness of a few hundred Angstroms or less, for example. 
   The gate material  468  may comprise a semiconductor material or a metal, for example. For example, the gate material  468  may comprise polysilicon, other semiconductor materials, TiN, HfN, TaN, W, Al, Ru, RuN, RuSiN, RuTa, TaSiN, TiSiN, NiSi x , CoSi x , TiSi x , Ir, Y, Pt, Ti, PtTi, Pd, Re, Rh, (borides, phosphides, or antimonides of Ti), Hf, Zr, TiAlN, Mo, MoN, ZrSiN, ZrN, HfN, HfSiN, WN, Ni, Pr, VN, TiW, LaN, LaSiN, WSiN, WSi, TaCN, fully silicided gate material (FUSI), and/or combinations thereof, as examples. 
   A material  464  is implanted into the gate material  468 , changing the first gate material of the first transistor (e.g., the PMOS “P” transistor). At least a portion  470  of the first gate dielectric material is also implanted with the material  464 , e.g., at  470 . 
   In one embodiment, the gate dielectric material  466  preferably comprises SiO 2 , SiON, HfO 2 , HfON, HfSiO, or HfSiON, and implanting the material  464  comprises implanting the first element, for example. The material  464  is preferably implanted into the first gate material  468  and also into at least a top portion of the first gate material  466 , e.g., at  470 . 
   In this embodiment, in the first region  404  where a PMOS transistor will be formed, a Fermi-pinning material  464  may be or may not be implanted. In one embodiment, the Fermi-pinning material  464  is implanted in the first region  404  but not in the second region  406 , as shown. For example, the gate material  468  may be covered with photoresist  424  or an insulating material during the implantation process, as shown. Implanting the material  464  may comprise implanting aluminum, for example, although alternatively, the implanted material  464  may comprise other materials. 
   Preferably, the material  464  is implanted into at least the conductive layer  468  over the first region  404  of the workpiece  402 , as shown. For example, the Fermi-pinning material  464  is preferably also implanted into a top surface  470  of the insulating layer  466 . 
   Because the material  464  is implanted into the first region  404  and not the second region  406  in some embodiments, the gate material and gate dielectric material for the first region  404  and second region  406  are now advantageously different, producing the novel CMOS device having different gate dielectric materials and symmetric V t  for a PMOS transistor and NMOS transistor, as shown in  FIGS. 9 and 10 . A different material may be implanted into the second region  406 , such as the second element of the second gate dielectric material, for example. Either the first element, the second element, or both may be implanted into the first gate dielectric material and the second gate dielectric material, for example. 
   Note that optionally, the gate material  468  in the first region  404  may be doped with a P-type dopant while the second region  406  is masked. Similarly, and the gate material  468  in the second region  406  may optionally be doped with an N-type dopant  472  while the first region  404  is masked, as shown in  FIG. 18 . 
   The structure shown in  FIG. 18  illustrates that the single conductive layer  468 , after implanting the material  464 , forms a first gate material  422  in the second region  406  and a second gate material  428  in the first region  404 . Likewise, the single insulating layer  466  forms a first gate dielectric material  420  in the second region  406  and a second gate dielectric material comprising a first insulating layer  450  and a second insulating layer  452  in the first region  404 . The device  400  is then patterned and the manufacturing process is continued to produce the novel CMOS device shown in a cross-sectional view in  FIG. 10 . 
   The embodiment shown in  FIGS. 17 and 18  is advantageous in that the number of lithography masks required to manufacture the device  400  is further reduced. 
   Advantages of embodiments of the invention include providing methods of fabricating a CMOS device  100 ,  200 ,  300 ,  400  and structures thereof wherein the PMOS transistor  136 ,  236  and the NMOS transistor  138 ,  238  have a substantially symmetric V t . For example, V tn  may be about +0.2 to +5 V), and V tp  may be the substantially the same negative value, e.g., about −0.2 to −5 V). The threshold voltages V t  may alternatively comprise other voltage levels, for example. Work function symmetry is achieved by using a different dielectric material GD 1  and GD 2  for the PMOS transistor  136 / 236  and the NMOS transistor  138 / 238 , respectively. The threshold voltage V t  is decreased compared to prior art CMOS devices, and the flat band voltage is easier to tune. Embodiments of the invention may utilize high-k dielectric materials as the gate dielectric GD 1 /GD 2 , using polysilicon, metal or FUSI gate electrodes G 1 /G 2 . The metal gate electrodes G 1 /G 2  may comprise either single metal or dual-work function metals, e.g., the gate electrode G 1 /G 2  for the PMOS and NMOS transistors may be the same material or different materials. In one embodiment, wherein the top layer of the gate dielectric of the PMOS transistor  136 / 236  comprises an aluminum-containing material, the fact that Si—Al pins to p-type and Si—Hf pins to n-type is utilized, to take advantage of the Fermi-pinning effect rather than trying to solve the Fermi-pinning effect or work around it by changing the material of the gate electrode. In another embodiment, the concentration of the first element, such as La, in the NMOS transistor gate dielectric, and the concentration of the second element, such as Y or Al, in the PMOS transistor gate dielectric, may be varied to tune the CMOS transistors so that the threshold voltages V t  are symmetric. 
   Although embodiments of the present invention and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that many of the features, functions, processes, and materials described herein may be varied while remaining within the scope of the present invention. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure of the present invention, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present invention. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.