Patent Publication Number: US-2023135902-A1

Title: Semiconductor memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation Application of U.S. Application No. 17/200,701, filed Mar. 12, 2021, which is based upon and claims the benefit of priority from Japanese Patent Application No. 2020-123692, filed Jul. 20, 2020, the entire contents of both of which are incorporated herein by reference. 
    
    
     FIELD 
     Embodiments described herein relate generally to a semiconductor memory device. 
     BACKGROUND 
     A NAND flash memory is known as a semiconductor memory device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram showing an example of a configuration of a memory system including a semiconductor memory device according to a first embodiment; 
         FIG.  2    is a block diagram of the semiconductor memory device according to the first embodiment; 
         FIG.  3    is a circuit diagram of a memory cell array included in the semiconductor memory device according to the first embodiment; 
         FIG.  4    is a cross-sectional view showing an example of a structure of the memory cell array in the semiconductor memory device according to the first embodiment; 
         FIG.  5    is a diagram for explaining a threshold voltage that may be taken by a dummy cell transistor in the semiconductor memory device according to the first embodiment; 
         FIG.  6    is a diagram showing an example of a state of the threshold voltage set for the dummy cell transistor of the semiconductor memory device according to the first embodiment; 
         FIG.  7    is a timing chart showing a voltage of each wiring in reading operation (operation example 1-1) using the semiconductor memory device according to the first embodiment; 
         FIG.  8    is a diagram for explaining the electrical connection between each string unit and a bit line and between each string unit and a source line in the reading operation (operation example 1-1) using the semiconductor memory device according to the first embodiment; 
         FIG.  9    is a timing chart showing a voltage of each wiring in reading operation (operation example 1-2) using the semiconductor memory device according to the first embodiment; 
         FIG.  10    is a diagram for explaining the electrical connection between each string unit and a bit line and between each string unit and a source line in the reading operation (operation example 1-2) using the semiconductor memory device according to the first embodiment; 
         FIG.  11    is a circuit diagram of a memory cell array included in a semiconductor memory device according to a second embodiment; 
         FIG.  12    is a cross-sectional view showing an example of a structure of the memory cell array in the semiconductor memory device according to the second embodiment; 
         FIG.  13    is a diagram showing an example of a state of a threshold voltage set for a dummy cell transistor of the semiconductor memory device according to the second embodiment; 
         FIG.  14    is a timing chart showing a voltage of each wiring in reading operation (operation example 2-1) using the semiconductor memory device according to the second embodiment; 
         FIG.  15    is a diagram for explaining the electrical connection between each string unit and a bit line and between each string unit and a source line in the reading operation (operation example 2-1) using the semiconductor memory device according to the second embodiment; 
         FIG.  16    is a timing chart showing a voltage of each wiring in the reading operation (operation example 2-2) using the semiconductor memory device according to the second embodiment; 
         FIG.  17    is a diagram for explaining the electrical connection between each string unit and a bit line and between each string unit and a source line in the reading operation (operation example 2-2) using the semiconductor memory device according to the second embodiment; 
         FIG.  18    is a timing chart showing a voltage of each wiring in reading operation (operation example 2-3) using the semiconductor memory device according to the second embodiment; and 
         FIG.  19    is a diagram for explaining the electrical connection between each string unit and a bit line and between each string unit and a source line in the reading operation (operation example 2-3) using the semiconductor memory device according to the second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor memory device includes a first memory string including a first memory cell transistor, a second memory cell transistor, and a first select element that connects the first memory cell transistor and the second memory cell transistor in series, a second memory string including a third memory cell transistor, a fourth memory cell transistor, and a second select element that connects the third memory cell transistor and the fourth memory cell transistor in series, a first wiring connected to a gate of each of the first memory cell transistor and the third memory cell transistor, a second wiring connected to a gate of each of the second memory cell transistor and the fourth memory cell transistor, a third wiring connected to a first end of each of the first memory string and the second memory string, a fourth wiring connected to a second end of each of the first memory string and the second memory string, and a control circuit. The control circuit is configured to set the second select element to an off state while setting the first select element to an on state when reading data of the first memory string. 
     Hereinafter, embodiments will be described with reference to the drawings. In the description hereinafter, common reference numerals are attached to common parts. 
     1. First Embodiment 
     The semiconductor memory device according to the first embodiment will be described. Note that, hereinafter, a NAND flash memory will be described as an example of the semiconductor memory device. 
     1.1 Configuration 
     1.1.1 Overall Configuration of Memory System 
     First, a configuration example of a memory system will be described with reference to  FIG.  1   .  FIG.  1    is a block diagram showing an example of the configuration of a memory system  3  including a NAND flash memory  1  according to the first embodiment. 
     The memory system  3  communicates with, for example, an external host device  4 . The memory system  3  stores data from the host device  4  and reads out the data to the host device  4 . The memory system  3  is, for example, a solid state drive (SSD), an SDTM card, or the like. 
     The memory system  3  includes a memory controller  2   and the NAND flash memory  1 . 
     The memory controller  2  receives an instruction from the host device  4  and controls the NAND flash memory  1  based on the received instruction. Specifically, the memory controller  2  writes in the NAND flash memory  1  the data instructed to write by the host device  4 , and reads out from the NAND flash memory  1  the data instructed to read by the host device  4  and transmits the data to the host device  4 . 
     The NAND flash memory  1  includes a plurality of memory cell transistors, each of which stores data in a non-volatile manner. The NAND flash memory  1  is connected to the memory controller  2  by a NAND bus. 
     The NAND bus transmits and receives, via an individual signal line, each of a chip enable signal/CE, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal/WE, a read enable signal/RE, a write protect signal/WP, a ready/busy signal/RB, and an input/output signal I/O &lt;7:0&gt; according to a NAND interface. The signal/CE is a signal for enabling the NAND flash memory  1 . The signal CLE notifies the NAND flash memory  1  that the signal I/O &lt;7:0&gt; flowing through the NAND flash memory  1  is a command while the signal CLE is at the “H (High)” level. The signal ALE notifies the NAND flash memory  1  that the signal I/O &lt;7:0&gt; flowing through the NAND flash memory  1  is an address while the signal ALE is at the “H” level. The signal/WE instructs the NAND flash memory  1  to capture the signal I/O &lt;7:0&gt; flowing through the NAND flash memory  1  while the signal/WE is at the “L (Low)” level. The signal/RE instructs the NAND flash memory  1  to output the signal I/O &lt;7:0&gt;. The signal/WP instructs the NAND flash memory  1  to prohibit data writing and erasing. The signal/RB indicates whether the NAND flash memory  1  is in a ready state (a state of accepting an external instruction) or a busy state (a state of not accepting an external instruction). The signal I/O &lt;7:0&gt; is, for example, an 8-bit signal. 
     The signal I/O &lt;7:0&gt; is sent and received between the NAND flash memory  1  and the memory controller  2 , and includes a command CMD, an address ADD, and data DAT. The data DAT includes write data and read data. 
     Examples of the host device  4  that uses the memory system  3  described above include a digital camera, a personal computer, and the like. 
     1.1.2 Configuration of memory controller 
     The configuration of the memory controller  2  will be described still with reference to  FIG.  1   . 
     As shown in  FIG.  1   , the memory controller  2  includes a central processing unit (CPU)  21 , a built-in memory  22 , a buffer memory  23 , a NAND interface circuit (NAND I/F)  24 , and a host interface circuit (host I/F)  25 . The memory controller  2  is configured as, for example, a system-on-a-chip (SoC). 
     The CPU  21  controls the operation of the entire memory controller  2 . For example, the CPU  21  issues, to the NAND flash memory  1 , a read instruction based on the NAND interface in response to a data read instruction received from the host device  4 . This operation is similarly performed in the case of writing and erasing. Further, the CPU  21  has a function of executing various operations on the data read from the NAND flash memory  1 . 
     The built-in memory  22  is, for example, a semiconductor memory such as a dynamic random access memory (DRAM), and is used as a work area of the CPU  21 . The built-in memory  22  stores firmware for managing the NAND flash memory  1 , various management tables, and the like. 
     The buffer memory  23  temporarily stores the read data received from the NAND flash memory  1  by the memory controller  2 , the write data received from the host device  4 , and the like. 
     The NAND interface circuit  24  is connected to the NAND flash memory  1  via the NAND bus and controls communication with the NAND flash memory  1 . The NAND interface circuit  24  transmits the command CMD, the address ADD, and the write data to the NAND flash memory  1  according to an instruction of the CPU  21 . Further, the NAND interface circuit  24  receives the read data from the NAND flash memory  1 . 
     The host interface circuit  25  is connected to the host device  4  via a host bus and controls communication between the memory controller  2  and the host device  4 . The host interface circuit  25  transfers, for example, an instruction and data received from the host device  4  to the CPU  21  and buffer memory  23 , respectively. 
     1.1.3 Configuration of NAND flash memory 
     Next, a configuration example of the NAND flash memory  1  according to the first embodiment will be described with reference to  FIG.  2   .  FIG.  2    is a block diagram showing an example of the configuration of the NAND flash memory  1  according to the first embodiment. 
     The NAND flash memory  1  includes a memory cell array  10 , a row decoder  20 , a sense amplifier  30 , and a control circuit  40 . 
     The memory cell array  10  includes a plurality of blocks BLK (BLK 0 , BLK 1 , BLK 2 ,...) including a non-volatile memory cell transistor associated with a row and a column. Each of the blocks BLK includes, for example, four string units SU (SU 0  to SU 3 ). Then, each of the string units SU includes a plurality of NAND strings NS. The number of blocks in the memory cell array  10  and the number of string units in the block are optional. Details of the memory cell array  10  will be described later. 
     The row decoder  20  decodes a row address, selects one of the blocks BLK based on the decoding result, and further selects one of the string units SU. Then, a required voltage is output to the block BLK. The row address is provided by, for example, the memory controller  2  that controls the NAND flash memory  1 . 
     During data reading operation, the sense amplifier  30  senses a threshold voltage of the memory cell transistor for which reading operation is to be performed in the memory cell array  10 . Then, a sense result is output to the memory controller  2  as read data. At the time of data writing operation, write data received from the external memory controller  2  is transferred to the memory cell array  10 . 
     The control circuit  40  controls the operation of the entire NAND flash memory  1 . 
     1.1.4 Configuration of memory cell array 
     Next, the configuration of the memory cell array  10  will be described with reference to  FIG.  3   .  FIG.  3    is a circuit diagram of the memory cell array  10  included in the NAND flash memory  1  according to the first embodiment. The example of  FIG.  3    shows one of the blocks BLK in the memory cell array  10 , but the configuration of the other blocks BLK is also the same. As described above, the block BLK includes, for example, four of the string units SU, and each of the string units SU includes a plurality of the NAND strings NS. 
     Each of the NAND strings NS includes 16 memory cell transistors MT (MT 0  to MT 15 ), two select transistors ST 1  and ST 2 , and four dummy cell transistors DT (DTU, DTL 0 , DTL 1 , and DTL 2 ). Note that, in the description hereinafter, two of the select transistors ST 1  and ST 2  in the string unit SUi (i is an integer of 0 or more and 3 or less) are referred to as select transistors ST 1 _ i  and ST 2 _ i , respectively, and four of the dummy cell transistors DTU, DTL 0 , DTL 1 , and DTL 2  in the string unit SUi are referred to as dummy cell transistors DTU_i, DTL 0 _ i , DTL 1 _ i , and DTL 2 _ i , respectively. 
     The memory cell transistor MT includes a control gate and a charge storage layer, and stores data in a non-volatile manner. 
     The source of the dummy cell transistor DTL 0  is connected to the drain of the select transistor ST 2 . The drain of the dummy cell transistor DTL 0  is connected to the source of the dummy cell transistor DTL 1 . 
     The memory cell transistors MT 0  to MT 7  are connected in series between the dummy cell transistor DTL 1  and the dummy cell transistor DTL 2  in this order. The source of the memory cell transistor MT 0  on one end side of this series connection is connected to the drain of the dummy cell transistor DTL 1 , and the drain of the memory cell transistor MT 7  on the other end side is connected to the source of the dummy cell transistor DTL 2 . 
     The drain of the dummy cell transistor DTL 2  is connected to the source of the dummy cell transistor DTU. 
     The memory cell transistors MT 8  to MT 15  are connected in series between the dummy cell transistor DTU and the select transistor ST 1  in this order. The source of the memory cell transistor MT 8  on one end side of this series connection is connected to the drain of the dummy cell transistor DTU, and the drain of the memory cell transistor MT 15  on the other end side is connected to the source of the select transistor ST 1 . 
     Note that, in the example shown in the first embodiment, the case where each of the NAND strings NS includes 16 memory cell transistors MT is shown. However, the number of the NAND strings NS may be 8, 24, 32, 48, 64, 96, 128, or the like, and is not limited. 
     The gate of the select transistor ST 1  in each of the string units SU 0  to SU 3  is connected to select gate lines SGD 0  to SGD 3 , respectively. In contrast, the gate of the select transistor ST 2  in each of the string units SU 0  to SU 3  is common-connected to, for example, a select gate line SGS. However, the gate of the select transistor ST 2  may be connected to a different select gate line for each of the string units SU. 
     Further, the control gates of the memory cell transistors MT 0  to MT 15  in the same block BLK are common-connected to word lines WL 0  to WL 15 , respectively. 
     Further, the control gates of the dummy cell transistors DTU, DTL 0 , DTL 1 , and DTL 2  in the same block BLK are common-connected to dummy word lines DWLU, DWLL 0 , DWLL 1 , and DWLL 2 , respectively. However, the gates of the dummy cell transistors DTU, and DTL 0  to DTL 2  may be connected to different dummy word lines for each of the string units SU. Note that, in description hereinafter, the dummy word lines DWLU and DWLL 0  to DWLL 2  are also collectively referred to as a dummy word line DWL. 
     Further, the drain of the select transistor ST 1  of each of the NAND strings NS in the string unit SU is connected to a different bit line BL (BL 0  to BL(k-1), where k is a natural number of two or more). Further, the bit line BL common-connects one of the NAND string NS in each of the string units SU between a plurality of the blocks BLK. Furthermore, the sources of a plurality of the select transistors ST 2  are common-connected to a source line CELSRC. 
     That is, the string unit SU is a set of the NAND strings NS connected to different ones of the bit lines BL and connected to the same select gate line SGD. Further, the block BLK is a set of a plurality of the string units SU having a common word line WL. Then, the memory cell array  10  is a set of a plurality of the blocks BLK having a common bit line BL. 
     Data erasure is performed collectively for the memory cell transistors MT in the same block BLK, for example. In contrast, data reading and writing may be collectively performed for a plurality of the memory cell transistors MT common-connected to one of the word lines WL in one of the string units SU of one of the blocks BLK. Such a set of the memory cell transistors MT sharing the word line WL in one of the string units SU is referred to as, for example, a memory cell unit MU. That is, the memory cell unit MU is a set of the memory cell transistors MT for which writing or reading operation may be executed collectively. 
     The unit of a data string of one-bit data stored in each of a plurality of the memory cell transistors MT in the memory cell unit MU is defined as a “page”. One memory cell transistor MT can store, for example, two-bit data. This two-bit data is called a lower bit and an upper bit from the lower bit. In this case, data of two pages is stored in the memory cell unit MU, and a set of lower bits stored by each of the memory cell transistors MT in the memory cell unit MU is called a lower page, and a set of upper bits is called an upper page. 
     1.1.5 Structure of memory cell array 
     A structure of the memory cell array  10  of the NAND flash memory  1  according to the first embodiment will be described with reference to  FIG.  4   .  FIG.  4    is a cross-sectional view of the structure of the memory cell array  10 . 
     Note that, in the drawings referred to below, the X axis corresponds to an extending direction of the word line WL, the Y axis corresponds to an extending direction of the bit line BL, and the Z axis corresponds to a vertical direction with respect to a surface of a semiconductor substrate on which the NAND flash memory  1  is formed. 
     The NAND flash memory  1  includes a semiconductor substrate  100  and conductive layers  103  to  106 . The conductive layer  104  includes one of each of conductive layers  104 L 0 ,  104 L 1 ,  104 L 2 , and  104 U. The conductive layer  105  includes eight of each of conductive layers  105 L and  105 U. 
     The semiconductor substrate  100  includes a P-type well region  101  provided near the surface of the semiconductor substrate  100 . 
     An insulating layer  102  is provided on the P-type well region  101 . The conductive layer  103  is stacked on the insulating layer  102 . The conductive layer  103  is formed in a plate shape extending along an XY plane, for example. The conductive layer  103  is used as the select gate line SGS. The conductive layer  103  contains, for example, tungsten. 
     An insulating layer  111  is provided on the conductive layer  103 . The conductive layer  104 L 0 , an insulating layer  112 , and the conductive layer  104 L 1  are stacked in this order on the insulating layer  111 . The conductive layers  104 L 0  and  104 L 1  are formed in a plate shape extending along the XY plane, for example. The conductive layers  104 L 0  and  104 L 1  are used as the dummy word lines DWLL 0  and DWLL 1 , respectively. The conductive layers  104 L 0  and  104 L 1  contain, for example, tungsten. 
     An insulating layer  113 L is provided on the conductive layer  104 L 1 . On the insulating layer  113 L, eight conductive layers  105 L and eight insulating layers  114 L are stacked in the order of the conductive layer  105 L, the insulating layer  114 L,..., the conductive layer  105 L, and the insulating layer  114 L. The conductive layer  105 L is formed in a plate shape extending along the XY plane, for example. The eight stacked conductive layers  105 L are used as the word lines WL 0  to WL 7  in order from the P-type well region  101  side. The conductive layer  105 L contains, for example, tungsten. 
     The conductive layer  104 L 2 , an insulating layer  115 , and the conductive layer  104 U are stacked in this order on the uppermost insulating layer  114 L. The conductive layers  104 L 2  and  104 U are formed in a plate shape extending along the XY plane, for example. The conductive layers  104 L 2  and  104 U are used as the dummy word lines DWLL 2  and DWLU, respectively. The conductive layers  104 L 2  and  104 U contain, for example, tungsten. 
     An insulating layer  113 U is provided on the conductive layer  104 U. On the insulating layer  113 U, eight conductive layers  105 U and eight insulating layers  114 U are stacked in the order of the conductive layer  105 U, the insulating layer  114 U,..., the conductive layer  105 U, and the insulating layer  114 U. The conductive layer  105 U is formed in a plate shape extending along the XY plane, for example. The eight stacked conductive layers  105 U are used as the word lines WL 8  to WL 15  in order from the P-type well region  101  side. The conductive layer  105 U contains, for example, tungsten. 
     The conductive layer  106  and an insulating layer  116  are stacked in this order on the uppermost insulating layer  114 U. The conductive layer  106  is formed in a plate shape extending along the XY plane, for example. The stacked conductive layer  106  is used as the select gate line SGD. The conductive layer  106  contains, for example, tungsten. The conductive layer  106  is electrically disconnected for each of the string units SU by, for example, a slit SHE. 
     A conductive layer  107  is provided on the insulating layer  116 . The conductive layer  107  is formed in a line shape extending in the Y direction, for example, and is used as the bit line BL. That is, a plurality of the conductive layers  107  are arranged along the X direction in a region (not shown). The conductive layer  107  contains, for example, copper. 
     In the NAND flash memory  1 , a memory pillar MP is provided so as to extend along the Z direction and penetrates the conductive layers  103  to  106 . Further, each of the memory pillars MP has a first portion formed in a hole LMH on a lower layer and a second portion formed in a hole UMH on an upper layer. 
     Specifically, the first portion corresponding to the hole LMH penetrates the conductive layers  103 ,  104 L 0  to  104 L 2 , and  105 L, and has a bottom portion in contact with the P-type well region  101 . The second portion corresponding to the hole UMH is provided above the first portion corresponding to the hole LMH and penetrates the conductive layers  104 U,  105 U, and  106 . A layer including a boundary portion between the first portion and the second portion of the memory pillar MP, that is, a wiring layer provided with the insulating layer  115  is also called a bonding layer. 
     Each of the memory pillars MP includes, for example, a semiconductor layer  121 , a block insulating film  122 , an insulating film  123 , and a tunnel insulating film  124 . For example, each of the semiconductor layer  121 , the block insulating film  122 , the insulating film  123 , and the tunnel insulating film  124  is continuously provided between the first portion and the second portion of the memory pillar MP. 
     The semiconductor layer  121  is provided, for example, by extending along the Z direction. Specifically, an upper end of the semiconductor layer  121  is included in an upper layer than the conductive layer  106 , and a lower end of the semiconductor layer  121  is in contact with the P-type well region  101 . The tunnel insulating film  124  covers a side surface of the semiconductor layer  121 . The insulating film  123  covers a side surface of the tunnel insulating film  124 . The block insulating film  122  covers a side surface of the insulating film  123 . 
     The insulating film  123  includes, for example, an insulating film having a trap level (for example, a SiN film). Note that the insulating film  123  may include a semiconductor film (for example, a silicon film). In a case where the insulating film  123  includes the semiconductor film, the semiconductor films are separated from each other for each of the memory cell transistors MT. 
     The semiconductor layer  121  includes, for example, amorphous silicon or polysilicon. The semiconductor layer  121  may include, for example, a columnar insulator (silicon oxide or the like) and a semiconductor region covering a side surface of the columnar insulator. 
     Note that the semiconductor layer  121  may have a tapered cross-sectional shape in, for example, each of the first portion and the second portion of the memory pillar MP due to the manufacturing process of the memory cell array  10 . In this case, the dimension (diameter) of a lower part of the first portion and the second portion in the X direction (and the Y direction) is smaller than the dimension (diameter) of an upper part of the first portion and the second portion in the X direction (and the Y direction), respectively. 
     In the structure of the memory pillar MP described above, a portion where the memory pillar MP and the conductive layer  103  intersect functions as the select transistor ST 2 . Further, each of a portion where the memory pillar MP and the conductive layer  105 L intersect and a portion where the memory pillar MP and the conductive layer  105 U intersect functions as the memory cell transistor MT. Further, a portion where the memory pillar MP and the conductive layer  104 L 0  intersect, a portion where the memory pillar MP and the conductive layer  104 L 1  intersect, a portion where the memory pillar MP and the conductive layer  104 L 2  intersect, and a portion where the memory pillar MP and the conductive layer  104 U intersect function as the dummy cell transistors DTL 0 , DTL 1 , DTL 2 , and DTU, respectively. Further, a portion where the memory pillar MP and the conductive layer  106  intersect functions as the select transistor ST 1 . Further, the semiconductor layer  121  functions as a channel of each of the memory cell transistors MT 0  to MT 15 , the dummy cell transistors DTL 0  to DTL 2 , and the DTU, and the select transistors ST 1  and ST 2 . Further, the insulating film  123  functions as a charge storage layer of the memory cell transistor MT and the dummy cell transistor DT. 
     A columnar contact CV is provided on the semiconductor layer  121  in the memory pillar MP. The contact CV is in contact with one of the conductive layers  107 , that is, one of the bit lines BL on an upper surface of the contact CV. 
     Note that the structure shown in  FIG.  4    is just an example, and other structures can be appropriately applied. For example, a conductor (not shown) that functions as the source line CELSRC may be further provided above the semiconductor substrate  100  shown in  FIG.  4   . 
     1.1.6 Threshold voltage of dummy cell transistor 
     The threshold voltage of the dummy cell transistor DT of the NAND flash memory  1  according to the first embodiment will be described with reference to  FIG.  5   .  FIG.  5    is a diagram for explaining the threshold voltage that the dummy cell transistor DT may take. 
     The dummy cell transistor DT may take four states having different threshold voltages, for example. Hereinafter, these four states are referred to as an “S0” state, an “S1” state, an “S2” state, and an “S3” state in ascending order of the threshold voltage. 
     The threshold voltage of the dummy cell transistor DT that takes the “S0” state is smaller than a voltage VS0. In this manner, the dummy cell transistor DT that takes the “S0” state is set to an on state by application of the voltage VS0 or higher to a corresponding dummy word line. 
     The threshold voltage of the dummy cell transistor DT that takes the “S1” state is the voltage VS0 or higher, and lower than a voltage VS1 (where VS1 &gt; VS0). In this manner, the dummy cell transistor DT that takes the “S1” state is set to an on state by application of the voltage VS1 or higher to a corresponding dummy word line. 
     The threshold voltage of the dummy cell transistor DT that takes the “S2” state is the voltage VS1 or higher, and lower than a voltage VS2 (where VS2 &gt; VS1). In this manner, the dummy cell transistor DT that takes the “S2” state is set to an on state by application of the voltage VS2 or higher to a corresponding dummy word line. 
     The threshold voltage of the dummy cell transistor DT that takes the “S3” state is the voltage VS2 or higher, and lower than a voltage VS3 (where VS3 &gt; VS2). In this manner, the dummy cell transistor DT that takes the “S3” state is set to an on state by application of the voltage VS3 or higher to a corresponding dummy word line. 
     In the first embodiment, the state of the threshold voltage of the dummy cell transistor DT is preset to one of the “S0” state to the “S3” state, for example, before the product is shipped. 
       FIG.  6    is a diagram showing an example of the state of the threshold voltage set to the dummy cell transistor DT. 
     In  FIG.  6   , the dummy cell transistor DT identified in a matrix by the string unit SU designated in the column direction and the dummy word line DWL designated in the row direction, and the state of the threshold voltage set to the dummy cell transistor DT are shown in a format of “(sign of dummy cell transistor)/(state of threshold voltage)”. 
     Dummy cell transistors DTU_ 0  to DTU_ 3  are set to, for example, the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. In this case, dummy cell transistors DTL 2 _ 0  to DTL 2 _ 3  are set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. Note that the dummy cell transistors DTU_ 0   to DTU_ 3  may be set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. In this case, the dummy cell transistors DTL 2 _ 0  to DTL 2 _ 3  are set to the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. 
     Dummy cell transistors DTL 1 _ 0  to DTL 1 _ 3  are set to, for example, the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. In this case, dummy cell transistors DTL 0 _ 0  to DTL 0 _ 3  are set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. Note that the dummy cell transistors DTL 1 _ 0  to DTL 1 _ 3  may be set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. In this case, the dummy cell transistors DTL 0 _ 0  to DTL 0 _ 3  are set to the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. 
     1.2 Reading operation 
     Next, an example of the reading operation according to the first embodiment will be described. 
     In the present embodiment, the dummy cell transistor DT is used as a select transistor for controlling the electrical connection between the string unit SU and the bit line BL or the source line CELSRC. More specifically, the NAND flash memory  1  according to the first embodiment controls voltage applied to the gate of the dummy cell transistor DT, so as to apply voltage to the first portion or the second portion of the memory pillar MP in the non-selection string unit SU while setting the other portion to a floating state. 
     Note that, in the description below, in order to simplify the description, a case where one-bit data is read in one time of the reading operation will be described. 
     1.2.1 Example of reading operation 
     Regarding the reading operation according to the first embodiment, description will be made by exemplifying a case where the reading operation of the memory cell transistor MT 0  of the string unit SU 1  is executed (operation example 1-1) and a case where the reading operation of the memory cell transistor MT 8  of the string unit SU 1  is executed (operation example 1-2). 
     Note that, in description below, the memory cell transistor MT for which the reading operation is to be performed is referred to as a selected memory cell transistor MT. Further, the word line WL corresponding to the selected memory cell transistor MT will be referred to as a selected word line WL. 
     1.2.1.1 Operation example 1-1 
     The operation example 1-1 of the reading operation according to the first embodiment will be described. 
       FIG.  7    is a timing chart showing a voltage of each wiring during the reading operation. 
     In  FIG.  7   , as described above, as the operation example 1-1, a case where data is read from the memory cell transistor MT 0  included in the first portion of the memory pillar MP of the string unit SU 1  is shown. 
     As shown in  FIG.  7   , first, at time t1, the row decoder  20  applies a voltage VSGD to the select gate line SGD 1  and applies a voltage VSS to the select gate lines SGD 0 , SGD 2 , and SGD 3 . In this manner, a select transistor ST 1 _ 1  of the string unit SU 1  is in an on state, and select transistors ST 1 _ 0 , ST 1 _ 2 , and ST 1 _ 3  of the string units SU 0 , SU 2 , and SU 3  are in an off state. Further, the row decoder  20  applies a voltage equivalent to, for example, the voltage VSGD to the select gate line SGS to set the select transistor ST 2  to an on state. The voltage VSGD is a voltage applied to the select gate lines SGD and SGS during the data reading operation to set the corresponding select transistors ST 1  and ST 2  to an on state. 
     Further, the row decoder  20  applies the voltage VS1 to the dummy word line DWLU. In this manner, the dummy cell transistors DTU_ 0  and DTU_ 1  are in an on state, and the dummy cell transistors DTU_ 2  and DTU_ 3  are in an off state. 
     Further, the row decoder  20  applies a voltage VS2 to the dummy word line DWLL 2 . In this manner, the dummy cell transistors DTL 2 _ 1  to DTL 2 _ 3  are in an on state, and the dummy cell transistor DTL 2 _ 0  is in an off state. 
     Further, the row decoder  20  applies a voltage VS3 to the dummy word lines DWLL 0  and DWLL 1 . In this manner, the dummy cell transistors DTL 0  and DTL 1  of all the string units SU are in an on state. 
     Further, the row decoder  20  applies a voltage VREAD to the non-selected word lines WL 1  to WL 15  and applies a voltage VCGRV to the selected word line WL 0 . The voltage VREAD is a voltage that is applied to the non-selected word line WL during the data reading operation to set the corresponding memory cell transistor MT to an on state. Further, the voltage VCGRV is a voltage corresponding to the threshold voltage of the memory cell transistor MT for which the reading operation is to be performed. The voltage VCGRV and the voltage VREAD are in a relationship of VCGRV &lt; VREAD. For example, in a case where the threshold voltage of the memory cell transistor MT for which the reading operation is to be performed is higher than the voltage VCGRV, the memory cell transistor MT is in an off state, and in a case where the threshold voltage is equal to or less than the voltage VCGRV, the memory cell transistor MT is in an on state. 
     At time t2, the sense amplifier  30  sets the voltage of the bit line BL to a voltage VBL. 
     The sense amplifier  30  senses and amplifies the cell current flowing through the bit line BL after the voltage of the selected word line WL 0  is stabilized at the voltage VCGRV, and reads out data. 
     At time t3, the row decoder  20  applies the voltage VSS to all the dummy word lines DWL, all the word lines WL, and all the select gate lines SGD. Further, the sense amplifier  30  applies the voltage VSS to the bit line BL. 
     As described above, data is read from the memory cell transistor MT 0  of the selected string unit SU 1 . 
       FIG.  8    is a diagram for explaining the electrical connection between each string unit SU and the bit line BL and between each string unit SU and the source line CELSRC during the reading operation shown in  FIG.  7   . In  FIG.  8   , the select transistor ST 1  and the dummy cell transistor DT, which are in an off state during the reading operation, are marked with “x”. 
     As shown in  FIG.  8   , in the selected string unit SU 1 , all the dummy cell transistors DT(DTU_ 1 , DTL 2 _ 1 , DTL 1 _ 1 , and DTL 0 _ 1  each corresponding to the dummy word lines DWLU, DWLL 2 , DWLL 1 , and DWLL 0 ) are in an on state, so that the memory pillar MP can function as a current path between the bit line BL and the source line CELSRC. 
     In contrast, in the non-selected string units SU 0 , SU 2 , and SU 3 , both the dummy cell transistors DTL 0  and DTL 1  are in an on state, and any one of the dummy cell transistors DTL 2  and DTU is in an off state. For this reason, a channel of the memory cell transistors MT 0  to MT 7 (corresponding to the conductive layer  105 L) located below the dummy cell transistors DTL 2  and DTU in the memory pillar MP is electrically connected to the source line CELSRC. In contrast, in the memory pillar MP, a channel of the memory cell transistors MT 8  to MT 15  located above the dummy cell transistors DTL 2  and DTU (the region enclosed by the alternate long and short dash line in  FIG.  8   ) is in a floating state, in which the channel is electrically insulated from the bit line BL and the source line CELSRC. 
     Note that, although the case where the memory cell transistor MT 0  is selected is described in  FIGS.  7  and  8   , the reading operation equivalent to that in the above description can be applied to the case where the memory cell transistors MT 1  to MT 7  located below the dummy cell transistors DTL 2  and DTU are selected. 
     1.2.1.2 Operation example 1-2 
     Next, the operation example 1-2 of the reading operation according to the first embodiment will be described. 
       FIG.  9    is a timing chart showing a voltage of each wiring during the reading operation. 
     In  FIG.  9   , as described above, as the operation example 1-2, a case where data is read from the memory cell transistor MT 8  included in the second portion of the memory pillar MP of the string unit SU 1  is shown. 
     Hereinafter, description of the same operation as the operation example 1-1 will be omitted, and operation different from the operation example 1-1 will be mainly described. 
     As shown in  FIG.  9   , at time t1, the row decoder  20  applies the voltage VSGD to the select gate lines SGD 0  to SGD 3  of all the string units SU. In this manner, the select transistors ST 1  of all the string units SU 0  to SU 3  are in an on state. 
     Further, the row decoder  20  applies the voltage VS1 to the dummy word lines DWLU and DWLL 1 . In this manner, the dummy cell transistors DTU_ 0 , DTU_ 1 , DTL 1 _ 0 , and DTL 1 _ 1  are in an on state, and the dummy cell transistors DTU_ 2 , DTU_ 3 , DTL 1 _ 2 , and DTL 1 _ 3  are in an off state. 
     Further, the row decoder  20  applies the voltage VS2 to the dummy word lines DWLL 2  and DWLL 0 . In this manner, the dummy cell transistors DTL 2 _ 1  to DTL 2 _ 3  and DTL 0 _ 1  to DTL 0 _ 3  are in an on state, and the dummy cell transistors DTL 2 _ 0  and DTL 0 _ 0  are in an off state. 
     Further, the row decoder  20  applies the voltage VREAD to the non-selected word lines WL 0  to WL 7  and WL 9  to WL 15 , and applies the voltage VCGRV to the selected word line WL 8 . 
     The operation at time t2 and t3 is equivalent to that in the operation example 1-1, and will be omitted from the description. 
     As described above, data is read from the memory cell transistor MT 8  of the selected string unit SU 1 . 
       FIG.  10    is a diagram for explaining the electrical connection between each string unit SU and the bit line BL and between each string unit SU and the source line CELSRC during the reading operation shown in  FIG.  9   . In  FIG.  10   , the select transistor ST 1  and the dummy cell transistor DT, which are in an off state during the reading operation, are marked with “x”. 
     As shown in  FIG.  10   , in the selected string unit SU 1 , all the dummy cell transistors DT are in an on state, so that the memory pillar MP can function as a current path between the bit line BL and the source line CELSRC. 
     In contrast, in the non-selected string units SU 0 , SU 2 , and SU 3 , any one of the dummy cell transistors DTL 0  and DTL 1  and any one of the dummy cell transistors DTL 2  and DTU are in an off state. For this reason, a channel of the memory cell transistors MT 8  to MT 15  located above the dummy cell transistors DTL 2  and DTU in the memory pillar MP is electrically connected to the bit line BL. In contrast, in the memory pillar MP, a channel of the memory cell transistors MT 0  to MT 7  located below the dummy cell transistors DTL 2  and DTU (the region enclosed by the alternate long and short dash line in  FIG.  10   ) is in a floating state, in which the channel is electrically insulated from the bit line BL and the source line CELSRC. 
     Note that, although the case where the memory cell transistor MT 8  is selected is described in  FIGS.  9  and  10   , the reading operation equivalent to that in the above description can be applied to the case where the memory cell transistors MT 9  to MT 15  located above the dummy cell transistors DTL 2  and DTU are selected. 
     1.2.2 Other operation examples 
     In the operation example 1-1 and the operation example 1-2 described above, the case where the reading operation of the memory cell transistor MT included in the string unit SU 1  is executed is shown as an example. 
     Hereinafter, operation in a case where the threshold voltage of the memory cell transistor MT included in a first portion of the string unit SUi (i is an integer of 0 or more and 3 or less) is read, which is a generic concept of the operation example 1-1, and in a case where the threshold voltage of the memory cell transistor MT included in a second portion of the string unit SUi is read, which is a generic concept of the operation example 1-2, will be described. 
     1.2.2.1 Reading operation of memory cell transistor included in first portion 
     First, a case where the reading operation of the memory cell transistor MT included in the first portion of the memory pillar MP of the string unit SUi is executed will be described. Note that, since control of the voltage applied to the word line WL, the dummy word lines DWLL 0  and DWLL 1 , the bit line BL, and the select gate line SGS is the same as that in the operation example 1-1, control of the dummy word lines DWLU and DWLL 2  and the select gate line SGD will be mainly described. 
     The row decoder  20  applies the voltage VSGD to the select gate line SGD of the selected string unit SUi, and maintains application of the voltage VSS to the select gate line SGD of a non-selected string unit SUj1 (j1 is an integer 0 or more and 3 or less, different from i). 
     Further, the row decoder  20  applies a voltage VSi to the dummy word line DWLU. In this manner, a dummy cell transistor DTU_ j   2  (j2 is an integer of 0 or more and i or less) is in an on state, and a dummy cell transistor DTU_ j   3  (j3 is an integer larger than i and 3 or less) is in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTU are in an on state. 
     Further, the row decoder  20  applies a voltage VS(3-i) to the dummy word line DWLL 2 . In this manner, a dummy cell transistor DTL 2 _ j   4  (j4 is an integer of i or more and 3 or less) is in an on state, and a dummy cell transistor DTL 2 _ j   5  (j5 is an integer smaller than i and 0 or more) is in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTL 2  are in an on state. 
     By the above operation, in the non-selected string unit SUj1, both the dummy cell transistors DTL 0  and DTL 1  can be set to an on state, and any one of the dummy cell transistors DTL 2  and DTU can be set to an off state. 
     1.2.2.2 Reading operation of memory cell transistor included in second portion 
     Next, a case where the reading operation of the memory cell transistor MT included in the second portion of the memory pillar MP of the string unit SUi is executed will be described. Note that, since control of the voltage applied to the word line WL, the bit line BL, and the select gate lines SGD and SGS is the same as that in the operation example 1-2, control of the dummy word line DWL will be mainly described. 
     The row decoder  20  applies the voltage VSi to the dummy word lines DWLU and DWLL 1 . In this manner, dummy cell transistors DTU_ j   6  and DTL 1 _ j   6  (j6 is an integer of 0 or more and i or less) are in an on state, and dummy cell transistors DTU_ j   7  and DTL l _ j   7  (j7 is an integer larger than i and 3 or less) are in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTU and DTL 1  are in an on state. 
     Further, the row decoder  20  applies the voltage VS(3-i) to the dummy word lines DWLL 2  and DWLL 0 . In this manner, dummy cell transistors DTL 2 _ j   8  and DTL 0 _ j   8  (j8 is an integer of i or more and 3 or less) are in an on state, and dummy cell transistors DTL 2 _ j   9  and DTL 0 _ j   9  (j9 is an integer less than i and 0 or more) are in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTL 2  and DTL 0  are in an on state. 
     By the above operation, in the non-selected string unit SUj1, any one of the dummy cell transistors DTL 0  and DTL 1  and any one of the dummy cell transistors DTL 2  and DTU are in an off state. 
     1.3 Effect of first embodiment 
     According to the first embodiment, the characteristics of the reading operation of the semiconductor memory device can be improved. An effect of the first embodiment will be described below. 
     As described above, in the first embodiment, each of the memory pillars MP includes the dummy cell transistors DTL 0  to DTL 2  included in the first portion and the dummy cell transistor DTU included in the second portion. In the first embodiment, each of the threshold voltages of the dummy cell transistors DTL 0  to DTL 2  and DTU is preset to a predetermined state different between each of the string units SU before the reading operation. In this manner, the NAND flash memory  1  of the first embodiment can make at least one channel connected to the non-selected word line WL in a floating state in the non-selected string unit SU during the reading operation. For this reason, it is not necessary to charge the memory cell transistor MT in a floating state via the bit line BL or the source line CELSRC, and it is possible to suppress an increase in the charging capacity of the bit line BL or the source line CELSRC. Therefore, the charging speed can be improved and an increase in the charging current can be suppressed. 
     Further, during the reading operation, the NAND flash memory  1  of the first embodiment can electrically connect, in the non-selected string unit SU, channels of the memory cell transistor MT connected to the selected word line WL and the memory cell transistor MT connected to the non-selected word line WL adjacent to the selected word line WL to the bit line BL or the source line CELSRC. In this manner, it is possible to prevent a fluctuation of the threshold voltage due to an unintended voltage difference between the gate and the source of the memory cell transistor MT in the non-selected string unit SU. For this reason, the characteristics of the reading operation of the semiconductor memory device can be improved. 
     Note that, in the above description, the case of the reading operation is described as an example. However, the present embodiment is not limited to this, and can be also applied to the verify operation during the writing operation. 
     2. Second Embodiment 
     Next, a NAND flash memory  1  according to a second embodiment will be described. The second embodiment further includes two dummy cell transistors DTMO and DTM 1  and a memory cell transistor MT sandwiched between the two dummy cell transistors DTMO and DTM 1  in addition to the configuration of the first embodiment. In description below, the same configuration and operation as those of the first embodiment will be omitted from the description, and a configuration and operation different from those of the first embodiment will be mainly described. 
     2.1 Configuration 
     A configuration of the NAND flash memory  1  according to the second embodiment will be described. 
     2.1.1 Configuration of Memory Cell Array 
     A configuration of a memory cell array  10  according to the second embodiment will be described with reference to  FIG.  11   .  FIG.  11    is a circuit diagram of the memory cell array  10  included in the NAND flash memory  1   according to the second embodiment. 
     In the memory cell array  10  according to the second embodiment, each of NAND strings NS includes 24 memory cell transistors MT (MT 0  to MT 23 ), two select transistors ST 1  and ST 2 , and six dummy cell transistors DT (DTU, DTM 0 , DTM 1 , and DTL 0  to DTL 2 ). Note that, in description below, two of the dummy cell transistors DTM 1  and DTMO in a string unit SUi (i is an integer of 0 or more and 3 or less) are also referred to as dummy cell transistors DTM 1 _ i  and DTM 0 _ i , respectively. 
     Configurations of the dummy cell transistors DTL 0  to DTL 2  and the memory cell transistors MT 0  to MT 7  are the same as those of the NAND flash memory  1  according to the first embodiment. 
     The drain of the dummy cell transistor DTL 2  is connected to the source of the dummy cell transistor DTMO. 
     The memory cell transistors MT 8  to MT 15  are connected in series between the dummy cell transistor DTMO and the dummy cell transistor DTM 1  in this order. The source of the memory cell transistor MT 8  on one end side of this series connection is connected to the drain of the dummy cell transistor DTM 0 , and the drain of the memory cell transistor MT 15  on the other end side is connected to the source of the dummy cell transistor DTM 1 . 
     The drain of the dummy cell transistor DTM 1  is connected to the source of the dummy cell transistor DTU. 
     The control gates of the dummy cell transistors DTM 1   and DTMO in the same block BLK are common-connected to dummy word lines DWLM 1  and DWLM 0 , respectively. However, the gates of the dummy cell transistors DTM 1  and DTMO may be connected to different dummy word lines for each of the string units SU. 
     Note that, in description hereinafter, the dummy word lines DWLM 1  and DWLM 0 , together with dummy word lines DWLU and DWLL 2  to DWLL 0 , are also collectively referred to as a dummy word line DWL. 
     Configurations of the dummy cell transistor DTU, the memory cell transistors MT 16  to MT 23 , and the select transistor ST 1  are equivalent to those in the NAND flash memory  1  according to the first embodiment except that the memory cell transistors MT 16  to MT 23  are provided instead of the memory cell transistors MT 8  to MT 15 . 
     2.1.2 Structure of Memory Cell Array 
     A configuration of the memory cell array  10  according to the second embodiment will be described with reference to  FIG.  12   .  FIG.  12    is a cross-sectional view showing an example of the structure of the memory cell array  10  in the NAND flash memory  1  according to the second embodiment. 
     In the NAND flash memory  1  according to the second embodiment, a conductive layer  104  includes one of each of conductive layers  104 L 0 ,  104 L 1 ,  104 L 2 ,  104 M 0 ,  104 M 1 , and  104 U. Further, a conductive layer  105  includes eight of each of conductive layers  105 L,  105 M, and  105 U. 
     An insulating layer  102 , a conductive layer  103 , the conductive layers  104 L 0  and  104 L 1 , the conductive layer  105 L, and the conductive layer  104 L 2  are stacked on the P-type well region  101  in the same manner as in the first embodiment. 
     An insulating layer  115 LM and the conductive layer  104 M 0  are stacked in this order on the conductive layer  104 L 2 . The conductive layer  104 M 0  is formed in a plate shape extending along the XY plane, for example. The stacked conductive layer  104 M 0  is used as a dummy word line DWLM 0 . The conductive layer  104 M 0  contains, for example, tungsten. 
     An insulating layer  113 M is provided on the conductive layer  104 M 0 . On the insulating layer  113 M, eight conductive layers  105 M and eight insulating layers  114 M are stacked in the order of the conductive layer  105 M, the insulating layer  114 M, the conductive layer  105 M,..., and the insulating layer  114 M. The eight stacked conductive layers  105 M are used as word lines WL 8  to WL 15  in order from a P-type well region  101  side. The conductive layer  105 M contains, for example, tungsten. 
     The conductive layer  104 M 1  and an insulating layer  115 MU are stacked in this order on the uppermost insulating layer  114 M. The conductive layer  104 M 1  is formed in a plate shape extending along the XY plane, for example. The stacked conductive layer  104 M 1  is used as a dummy word line DWLM 1 . The conductive layer  104 M 1   contains, for example, tungsten. 
     The conductive layer  104 U, the conductive layer  105 U, a conductive layer  106 , an insulating layer  116 , and a conductive layer  107  are stacked on the insulating layer  115 MU in the same manner as in the first embodiment. Note that, in the second embodiment, the eight stacked conductive layers  105 U are each used as word lines WL 16  to WL 23  in order from the P-type well region  101  side. 
     In the NAND flash memory  1  according to the second embodiment, a memory pillar MP penetrates the conductive layers  103  to  106 . Further, each of the memory pillars MP has a first portion formed in a hole LMH on a lower layer, a second portion formed in a hole UMH on an upper layer, and a third portion formed in a hole MMH on a middle layer. 
     The first portion and the second portion have the equivalent structure to those of the first embodiment. The third portion is provided above the first portion and below the second portion and penetrates the conductive layers  104 M 0 ,  105 M, and  104 M 1 . A layer including a boundary portion between the first portion and the third portion of the memory pillar MP, and a layer including a boundary portion between the second portion and the third portion, that is, a wiring layer provided with the insulating layer  115 LM and a wiring layer provided with the layer  115 MU are also called a bonding layer. 
     Each of a semiconductor layer  121 , a block insulating film  122 , an insulating film  123 , and a tunnel insulating film  124  is continuously provided between the first portion and the third portion of the memory pillar MP and the second portion and the third portion thereof. 
     2.1.3 Threshold Voltage of Dummy Cell Transistor 
     Next, a state of a threshold voltage taken by each dummy cell transistor DT of the NAND flash memory  1  according to the second embodiment will be described with reference to  FIG.  13   . 
     In the second embodiment, the state of the threshold voltage of the dummy cell transistor DT is preset to one of an “S0” state to an “S3” state, for example, before the product is shipped. 
       FIG.  13    is a diagram showing an example of the state of the threshold voltage set to the dummy cell transistor DT. 
     In  FIG.  13   , the dummy cell transistor DT identified in a matrix by the string unit SU designated in the column direction and the dummy word line DWL designated in the row direction, and the state of the threshold voltage set to the dummy cell transistor DT are shown in a format of “(sign of dummy cell transistor)/(state of threshold voltage)”. 
     Note that, since the state of the threshold voltage of the dummy cell transistors DTU and DTL 2  to DTL 0  is the same as that of the first embodiment, only the state of the threshold voltage of the dummy cell transistors DTMO and DTM 1  will be described in description below. 
     Dummy cell transistors DTM 1 _ 0  to DTM 1 _ 3  are set to, for example, the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. In this case, dummy cell transistors DTM 0 _ 0  to DTM 0 _ 3  are set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. Note that the dummy cell transistors DTM 1 _ 0  to DTM 1 _ 3  may be set to the “S3” state, the “S2” state, the “S1” state, and the “S0” state, respectively. In this case, the dummy cell transistors DTM 0 _ 0  to DTM 0 _ 3  are set to the “S0” state, the “S1” state, the “S2” state, and the “S3” state, respectively. 
     2.2 Reading Operation 
     Next, reading operation according to the second embodiment will be described by taking as an example a case where the reading operation of the memory cell transistor MT of a string unit SU 1  is executed. Hereinafter, description of operation which is the same as the reading operation according to the first embodiment will be omitted, and operation different from the reading operation according to the first embodiment will be mainly described. 
     Next, regarding the reading operation according to the second embodiment, description will be made by exemplifying a case where the reading operation of the memory cell transistor MT 0  of the string unit SU 1  is executed (operation example 2-1), a case where the reading operation of the memory cell transistor MT 8  of the string unit SU 1  is executed (operation example 2-2), and a case where the reading operation of the memory cell transistor MT 16  of the string unit SU 1  is executed (operation example 2-3) . 
     2.2.1 Operation Example 2-1 
     The operation example 2-1 of the reading operation according to the second embodiment will be described. 
       FIG.  14    is a timing chart showing a voltage of each wiring during the reading operation. 
     In  FIG.  14   , as described above, as the operation example 2-1, a case where data is read from the memory cell transistor MT 0  included in the first portion of the memory pillar MP of the string unit SU 1  is shown. 
     As shown in  FIG.  14   , first, at time t1, a row decoder  20  applies a voltage VSGD to a select gate line SGD 1  and applies a voltage VSS to select gate lines SGD 0 , SGD 2 , and SGD 3 . In this manner, a select transistor ST 1 _ 1  of the string unit SU 1  is in an on state, and select transistors ST 1 _ 0 , ST 1 _ 2 , and ST 1 _ 3  of the string units SU 0 , SU 2 , and SU 3  are in an off state. Further, the row decoder  20  applies a voltage equivalent to, for example, the voltage VSGD to the select gate line SGS to set the select transistor ST 2  to an on state. 
     Further, the row decoder  20  applies a voltage VS1 to the dummy word line DWLM 0 . In this manner, the dummy cell transistors DTM 0 _ 0  and DTMO_ 1  are in an on state, and the dummy cell transistors DTM 0 _ 2  and DTM 0 _ 3  are in an off state. 
     Further, the row decoder  20  applies a voltage VS2 to the dummy word line DWLL 2 . In this manner, the dummy cell transistors DTL 2 _ 1  to DTL 2 _ 3  are in an on state, and the dummy cell transistor DTL 2 _ 0  is in an off state. 
     Further, the row decoder  20  applies a voltage VS3 to the dummy word lines DWLU, DWLM 1 , DWLL 1 , and DWLL 0 . In this manner, all the dummy cell transistors DTU, DTM 1 , DTL 1 , and DTL 0  are in an on state. 
     Further, the row decoder  20  applies a voltage VREAD to non-selected word lines WL 1  to WL 23  and applies a voltage VCGRV to a selected word line WL 0 . 
     The operation at time t2 and t3 is equivalent to that in the first embodiment, and will be omitted from the description. 
     As described above, data is read from the memory cell transistor MT 0  of the selected string unit SU 1 . 
       FIG.  15    is a diagram for explaining the electrical connection between each string unit SU and a bit line BL and between each string unit and a source line CELSRC during the reading operation shown in  FIG.  14   . In  FIG.  15   , the select transistor ST 1  and the dummy cell transistor DT, which are in an off state during the reading operation, are marked with “x”. 
     As shown in  FIG.  15   , in the selected string unit SU 1 , all the dummy cell transistors DT(DTU_ 1 , DTM 1 _ 1 , DTM 0 _ 1 , DTL 2 _ 1 , DTL 1 _ 1 , and DTL 0 _ 1  each corresponding to the dummy word lines DWLU, DWLM 1 , DWLM 0 , DWLL 2 , DWLL 1 , and DWLL 0 ) are in an on state, so that the memory pillar MP can function as a current path between the bit line BL and the source line CELSRC. 
     In contrast, in non-selected string units SU 0 , SU 2 , and SU 3 , all the dummy cell transistors DTL 0 , DTL 1 , DTM 1 , and DTU are in an on state, and any one of the dummy cell transistors DTL 2  and DTMO is in an off state. For this reason, a channel of the memory cell transistors MT 0  to MT 7  located below the dummy cell transistors DTL 2  and DTMO in the memory pillar MP is electrically connected to the source line CELSRC. In contrast, in the memory pillar MP, a channel of the memory cell transistors MT 8  to MT 23  located above the dummy cell transistors DTL 2  and DTMO (the region enclosed by the alternate long and short dash line in  FIG.  15   ) is in a floating state, in which the channel is electrically insulated from the bit line BL and the source line CELSRC. 
     Note that, although the case where the memory cell transistor MT 0  is selected is described in  FIGS.  14  and  15   , the reading operation equivalent to that in the above description can be applied to the case where the memory cell transistors MT 1  to MT 7  located below the dummy cell transistors DTL 2  and DTMO are selected. 
     2.2.2 Operation Example 2-2 
     The operation example 2-2 of the reading operation according to the second embodiment will be described. 
       FIG.  16    is a timing chart showing a voltage of each wiring during the reading operation. 
     In  FIG.  16   , as described above, as the operation example 2-2, a case where data is read from the memory cell transistor MT 8  included in the third portion of the memory pillar MP of the string unit SU 1  is shown. 
     Hereinafter, description of the same operation as the operation example 2-1 will be omitted, and operation different from the operation example 2-1 will be mainly described. 
     As shown in  FIG.  16   , at time t1, the row decoder  20  applies a voltage equivalent to that of operation example 2-1 to the select gate lines SGD and SGS. 
     Further, the row decoder  20  applies the voltage VS1 to the dummy word line DWLU. In this manner, the dummy cell transistors DTU_ 0  and DTU_ 1  are in an on state, and the dummy cell transistors DTU_ 2  and DTU_ 3  are in an off state. 
     Further, the row decoder  20  applies a voltage VS2 to the dummy word line DWLM 1 . In this manner, the dummy cell transistors DTM 1 _ 1  to DTM 1 _ 3  are in an on state, and the dummy cell transistor DTM 1 _ 0  is in an off state. 
     Further, the row decoder  20  applies a voltage VS3 to the dummy word lines DWLM 0  and DWLL 2  to DWLL 0 . In this manner, all the dummy cell transistors DTMO and DTL 2  to DTL 0  are in an on state. 
     Further, the row decoder  20  applies the voltage VREAD to the non-selected word lines WL 0  to WL 7  and WL 9  to WL 23 , and applies the voltage VCGRV to the selected word line WL 8 . 
     The operation at time t2 and t3 is equivalent to that in the operation example 2-1, and will be omitted from the description. 
     As described above, data is read from the memory cell transistor MT 8  of the selected string unit SU 1 . 
       FIG.  17    is a diagram for explaining the electrical connection between each string unit SU and the bit line BL and between each string unit and the source line CELSRC during the reading operation shown in  FIG.  16   . In  FIG.  17   , the select transistor ST 1  and the dummy cell transistor DT, which are in an off state during the reading operation, are marked with “x”. 
     As shown in  FIG.  17   , in the selected string unit SU 1 , all the dummy cell transistors DT are in an on state, so that the memory pillar MP can function as a current path between the bit line BL and the source line CELSRC. 
     In contrast, in the non-selected string units SU 0 , SU 2 , and SU 3 , all the dummy cell transistors DTL 0 , DTL 1 , DTL 2 , and DTMO are in an on state, and any one of the dummy cell transistors DTU and DTM 1  is in an off state. For this reason, a channel of the memory cell transistors MT 0  to MT 15  located below the dummy cell transistors DTU and DTM 1  in the memory pillar MP is electrically connected to the source line CELSRC. In contrast, in the memory pillar MP, a channel of the memory cell transistors MT 16  to MT 23  located above the dummy cell transistors DTU and DTM 1  (the region enclosed by the alternate long and short dash line in  FIG.  17   ) is in a floating state, in which the channel is electrically insulated from the bit line BL and the source line CELSRC. 
     Note that, although the case where the memory cell transistor MT 8  is selected is described in  FIGS.  16  and  17   , the reading operation equivalent to that in the above description can be applied to the case where the memory cell transistors MT 9  to MT 15  located below the dummy cell transistors DTU and DTM 1  and above the dummy cell transistor DTMO are selected. 
     2.2.3 Operation Example 2-3 
     Operation example 2-3 of the reading operation according to the second embodiment will be described. 
       FIG.  18    is a timing chart showing a voltage of each wiring during the reading operation. 
     In  FIG.  18   , as described above, as the operation example 2-3, a case where data is read from the memory cell transistor MT 16  included in the second portion of the memory pillar MP of the string unit SU 1  is shown. 
     Hereinafter, description of the same operation as the operation example 2-1 and the operation example 2-2 will be omitted, and operation different from the operation example 2-1 and the operation example 2-2 will be mainly described. 
     As shown in  FIG.  18   , at time t1, the row decoder  20  applies the voltage VSGD to the select gate lines SGD 0  to SGD 3  of all the string units SU. In this manner, the select transistors ST 1  of all the string units SU 0  to SU 3  are in an on state. 
     Further, the row decoder  20  applies the voltage VS1 to the dummy word lines DWLU and DWLL 1 . In this manner, the dummy cell transistors DTU_ 0 , DTU_ 1 , DTL 1 _ 0 , and DTL 1 _ 1  are in an on state, and the dummy cell transistors DTU_ 2 , DTU_ 3 , DTL 1 _ 2 , and DTL 1 _ 3  are in an off state. 
     Further, the row decoder  20  applies the voltage VS2 to the dummy word lines DWLM 1  and DWLL 0 . In this manner, the dummy cell transistors DTM 1 _ 1  to DTM 1 _ 3  and DTL 0 _ 1  to DTL 0 _ 3  are in an on state, and the dummy cell transistors DTM 1 _ 0  and DTLO_ 3  are in an off state. 
     Further, the row decoder  20  applies the voltage VS3 to the dummy word lines DWLM 0  and DWLL 2 . In this manner, all the dummy cell transistors DTMO and DTL 2  are in an on state. 
     Further, the row decoder  20  applies the voltage VREAD to the non-selected word lines WL 0  to WL 15  and WL 17  to WL 23 , and applies the voltage VCGRV to the selected word line WL 16 . 
     The operation at time t2 and t3 is equivalent to that in the operation example 2-1 and the operation example 2-2, and will be omitted from the description. 
     As described above, data is read from the memory cell transistor MT 16  of the selected string unit SU 1 . 
       FIG.  19    is a diagram for explaining the electrical connection between each string unit SU and the bit line BL and between each string unit and the source line CELSRC during the reading operation shown in  FIG.  18   . In  FIG.  19   , the select transistor ST 1  and the dummy cell transistor DT, which are in an off state during the reading operation, are marked with “x”. 
     As shown in  FIG.  19   , in the selected string unit SU 1 , all the dummy cell transistors DT are in an on state, so that the memory pillar MP can function as a current path between the bit line BL and the source line CELSRC. 
     In contrast, in the non-selected string units SU 0 , SU 2 , and SU 3 , all the dummy cell transistors DTMO and DTL 2  are in an on state, and any one of the dummy cell transistors DTU and DTM 1  and any one of the dummy cell transistors DTL 1  and DTL 0  are in an off state. For this reason, a channel of the memory cell transistors MT 16  to MT 23  located above the dummy cell transistors DTU and DTM 1  in the memory pillar MP is electrically connected to the bit line BL. In contrast, in the memory pillar MP, a channel of the memory cell transistors MT 0  to MT 15  located below the dummy cell transistors DTU and DTM 1  (the region enclosed by the alternate long and short dash line in  FIG.  19   ) is in a floating state, in which the channel is electrically insulated from the bit line BL and the source line CELSRC. 
     Note that, although the case where the memory cell transistor MT 16  is selected is described in  FIGS.  18  and  19   , the reading operation equivalent to that in the above description can be applied to the case where the memory cell transistors MT 17  to MT 23  located above the dummy cell transistors DTU and DTM 1  are selected. 
     2.2.4 Other Operation Examples 
     In the operation example 2-1, the operation example 2-2, and the operation example 2-3 described above, the case where the reading operation of the memory cell transistor MT included in the string unit SU 1  is executed is shown as an example. 
     Hereinafter, operation in a case where the threshold voltage of the memory cell transistor MT included in a first portion of the string unit SUi (i is an integer of 0 or more and 3 or less) is read, which is a generic concept of the operation example 2-1, in a case where the threshold voltage of the memory cell transistor MT included in a third portion of the string unit SUi is read, which is a generic concept of the operation example 2-2, and in a case where the threshold voltage of the memory cell transistor MT included in a second portion of the string unit SUi is read, which is a generic concept of the operation example 2-3, will be described. 
     2.2.4.1 Reading operation of memory cell transistor included in first portion 
     First, a case where the reading operation of the memory cell transistor MT included in the first portion of the memory pillar MP of the string unit SUi is executed will be described. Note that, since control of the voltage applied to the word line WL, the dummy word lines DWLU, DWLM 1 , DWLL 1 , and DWLL 0 , the bit line BL, and the select gate line SGS is the same as that in the operation example 2-1, control of the dummy word lines DWLM 0  and DWLL 2  and the select gate line SGD will be mainly described. 
     The row decoder  20  applies the voltage VSGD to the select gate line SGD of the selected string unit SUi, and maintains application of the voltage VSS to the select gate line SGD in a non-selected string unit SUj10 ( j   10  is an integer 0 or more and 3 or less, different from i). 
     Further, the row decoder  20  applies a voltage VSi to the dummy word line DWLM 0 . In this manner, a dummy cell transistor DTM 0 _ j   11  ( j   11  is an integer of 0 or more and i or less) is in an on state, and a dummy cell transistor DTM 0 _ j   12  ( j   12  is an integer larger than i and 3 or less) is in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTMO are in an on state. 
     Further, the row decoder  20  applies a voltage VS(3-i) to the dummy word line DWLL 2 . In this manner, a dummy cell transistor DTL 2 _ j   13  ( j   13  is an integer of i or more and 3 or less) is in an on state, and a dummy cell transistor DTL 2 _ j   14  ( j   14  is an integer smaller than i and 0 or more) is in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTL 2  are in an on state. 
     By the above operation, in the non-selected string unit SUj10, all the dummy cell transistors DTL 0 , DTL 1 , DTM 1 , and DTU can be set to an on state, and any one of the dummy cell transistors DTL 2  and DTMO can be set to an off state. 
     2.2.4.2 Reading Operation of Memory Cell Transistor Included in Third Portion 
     Next, a case where the reading operation of the memory cell transistor MT included in the third portion of the memory pillar MP of the string unit SUi is executed will be described. Note that, since control of the voltage applied to the word line WL, the dummy word lines DWLM 0  and DWLL 2  to DWLL 0 , the bit line BL, and the select gate line SGS is the same as that in the operation example 2-2, control of the dummy word lines DWLU and DWLM 1  and the select gate line SGD will be mainly described. 
     The row decoder  20  applies the voltage VSGD to the select gate line SGD of the selected string unit SUi, and maintains application of the voltage VSS to the select gate line SGD in a non-selected string unit SUj10. 
     Further, the row decoder  20  applies a voltage VSi to the dummy word line DWLU. In this manner, a dummy cell transistor DTU_ j   15  ( j   15  is an integer of 0 or more and i or less) is in an on state, and a dummy cell transistor DTU_ j   16  ( j   16  is an integer larger than i and 3 or less) is in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTU are in an on state. 
     Further, the row decoder  20  applies a voltage VS(3-i) to the dummy word line DWLM 1 . In this manner, a dummy cell transistor DTM 1 _ j   17  ( j   17  is an integer of i or more and 3 or less) is in an on state, and a dummy cell transistor DTM 1 _ j   18  ( j   18  is an integer smaller than i and 0 or more) is in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTM 1  are in an on state. 
     By the above operation, in the non-selected string unit SUj10, all the dummy cell transistors DTL 0 , DTL 1 , DTL 2 , and DTM 0  can be set to an on state, and any one of the dummy cell transistors DTM 1  and DTU can be set to an off state. 
     Note that, in the reading operation of the memory cell transistor MT included in the third portion, operation below may be performed instead of the above reading operation. Hereinafter, since control of the voltage applied to the word line WL, the bit line BL, and the select gate line SGS is the same as the reading operation, control of the dummy word line DW and the select gate line SGD will be mainly described. 
     The row decoder  20  applies the voltage VSGD to the select gate lines SGD 0  to SGD 3  of all the string units SU. In this manner, the select transistors ST 1  of all the string units SU 0  to SU 3  are in an on state. 
     Further, the row decoder  20  applies the voltage VSi to the dummy word lines DWLM 0  and DWLL 1 . In this manner, dummy cell transistors DTM 0 _ j   19  and DTL 1 _ j   19  ( j   19  is an integer of 0 or more and i or less) is in an on state, and dummy cell transistors DTM 0 _ j   20  and DTL 1 _ j   20  ( j   20  is an integer larger than i and 3 or less) is in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTM 0  and DTL 1  are in an on state. 
     Further, the row decoder  20  applies the voltage VS (3-i) to the dummy word lines DWLL 0  and DWLL 2 . In this manner, dummy cell transistors DTL 0 _ j   21  and DTL 2 _ j   21  ( j   21  is an integer of i or more and 3 or less) are in an on state, and dummy cell transistors DTL 0 _ j   22  and DTL 2 _ j   22  ( j   22  is an integer less than i and 0 or more) are in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTL 0  and DTL 2  are in an on state. 
     Further, the row decoder  20  applies the voltage VS3 to the dummy word lines DWLM 1  and DWLU. In this manner, all the dummy cell transistors DTM 1  and DTU are in an on state. 
     By the above operation, in the non-selected string unit SUj10, both the dummy cell transistors DTU and DTM 1  can be set to an on state, and any one of the dummy cell transistors DTM 0  and DTL 2  and any one of the dummy cell transistors DTL 1  and DTL 0  can be set to an off state. 
     2.2.4.3 Reading Operation of Memory Cell Transistor Included in Second Portion 
     Next, a case where the reading operation of the memory cell transistor MT included in the second portion of the memory pillar MP of the string unit SUi is executed will be described. Note that, since control of the voltage applied to the word line WL, the dummy word lines DWLM 0  and DWLL 2 , the bit line BL, and the select gate lines SGD and SGS is the same as that in the operation example 2-3, control of the dummy word lines DWLU, DWLM 1 , DWLL 1 , and DWL 0  will be mainly described. 
     The row decoder  20  applies the voltage VSi to the dummy word lines DWLU and DWLL 1 . In this manner, dummy cell transistors DTU_ j   23  and DTL 1 _ j   23  ( j   23  is an integer of 0 or more and i or less) are in an on state, and dummy cell transistors DTU_ j   24  and DTL 1 _ j   24  ( j   24  is an integer larger than i and 3 or less) are in an off state. Note that, in a case where i is 3, all of the dummy cell transistors DTU and DTL 1  are in an on state. 
     Further, the row decoder  20  applies the voltage VS (3-i) to the dummy word lines DWLM 1  and DWLL 0 . In this manner, dummy cell transistors DTM 1 _ j   25  and DTL 0 _ j   25  ( j   25  is an integer of i or more and 3 or less) are in an on state, and dummy cell transistors DTM 1 _ j   26  and DTL 0 _ j   26  ( j   26  is an integer less than i and 0 or more) are in an off state. Note that, in a case where i is 0, all of the dummy cell transistors DTM 1  and DTL 0  are in an on state. 
     By the above operation, in the non-selected string unit SUj10, both the dummy cell transistors DTMO and DTL 2  can be set to an on state, and any one of the dummy cell transistors DTM 1  and DTU and any one of the dummy cell transistors DTL 1  and DTL 0  can be set to an off state. 
     2.3 Effect of Second Embodiment 
     In the second embodiment, each of the memory pillars MP includes the dummy cell transistors DTL 0  to DTL 2  included in the first portion, the dummy cell transistors DTMO and DTM 1  included in the third portion, and the dummy cell transistor DTU included in the second portion. In the second embodiment, each of the threshold voltages of the dummy cell transistors DTL 0  to DTL 2 , DTM 0 , DTM 1 , and DTU is preset to a predetermined state different between each of the string units SU before the reading operation. In this manner, the same effect as that of the first embodiment can be obtained. 
     3. Others 
     In the first embodiment and the second embodiment, the case where the dummy cell transistor DT is set to four states (“S0” state, “S1” state, “S2” state, and “S3” state) with different threshold voltages is described. However, the present embodiment is not limited to this. A dummy cell transistor DT is set to an optional number, such as two or eight states depending on the number of string units SU. 
     Specifically, in a case where a NAND flash memory  1  includes two string units SU 0  and SU 1  and each of the string units SU has a structure equivalent to that of the string unit SU in the first embodiment or the second embodiment, the dummy cell transistor DT is set to any of two states with different threshold voltages (for example, an “S0” state and an “S1” state in the ascending order of the threshold voltage). The threshold voltage of the dummy cell transistor DT of the string units SU 0  and SU 1  can be set to be equivalent to the threshold voltage of the dummy cell transistor DT of the string units SU 0  and SU 1  in the first embodiment or the second embodiment, for example. 
     Further, in a case where a NAND flash memory  1  includes eight string units SU 0  to SU 7  and each of the string units SU has a structure equivalent to that of the string unit SU in the first embodiment or the second embodiment, the dummy cell transistor DT is set to any of eight states with different threshold voltages (for example, an “S0” state to an “S7” state in the ascending order of the threshold voltage). A dummy cell transistor DTU of each of the string units SU 0  to SU 7  can be set to, for example, the “S0” state to the “S7” state. In this case, a dummy cell transistor DTM 1  of each of the string units SU 0  to SU 7  is set to the “S7” state to the “S0” state. Further, the respective dummy cell transistor DTMO of each of the string units SU 0  to SU 7  can be set to, for example, the “S0” state to the “S7” state. In this case, a dummy cell transistor DTL 2  of each of the string units SU 0  to SU 7  is set to the “S7” state to the “S0” state. Further, a dummy cell transistor DTL 1  of each of the string units SU 0  to SU 7  can be set to, for example, the “S0” state to the “S7” state. In this case, a dummy cell transistor DTL 0  of each of the string units SU 0  to SU 7  is set to the “S7” state to the “S0” state. 
     Further, in the description of the first embodiment and the second embodiment, the case where the dummy cell transistor DT is used as the select transistor for controlling the electrical connection of the channel included in the memory pillar MP of the string unit SU is described. However, the present embodiment is not limited to this. For example, as the select transistor, the memory cell transistor MT may be used instead of the dummy cell transistor DT. 
     Further, in the NAND flash memory  1  according to the first embodiment and the second embodiment, the example where the electrical connection between two adjacent portions of the first to third portions of the memory pillar MP and the electrical connection between the first portion and the source line CELSRC are controlled by the dummy cell transistor DT that is common-connected in the block BLK is shown. However, the present embodiment is not limited to these. For example, the NAND flash memory  1  may control the electrical connection between the first portion and the second portion in the first embodiment for each of the string units SU by a select element provided one for each of the string units SU. Further, the NAND flash memory  1  may control the electrical connection between the first portion and the third portion in the second embodiment for each of the string units SU by a select element provided one for each of the string units SU. Further, the NAND flash memory  1  may control the electrical connection between the second portion and the third portion in the second embodiment for each of the string units SU by a select element provided one for each of the string units SU. Further, the NAND flash memory  1  may control the electrical connection between the first portion and the source line CELSRC in the first embodiment and the second embodiment for each of the string units SU by a select element provided one for each of the string units SU. That is, the NAND flash memory  1  only needs to be configured so that a channel of at least one of the memory cell transistors MT is in a floating state in the non-selected string unit SU during the reading operation. 
     Further, in the first embodiment and the second embodiment, the case where the memory pillar MP includes two layers (two tiers) of the first portion and the second portion, and the case where the memory pillar MP includes three layers (three tiers) of the first portion, the second portion, and the third portion are shown. However, the present embodiment is not limited to these. The NAND flash memory  1  may include the memory pillar MP of, for example, one layer (one tier) or four layers (four tiers) or more. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit.