Patent Publication Number: US-8970641-B2

Title: Display device

Description:
This application claims the benefit of Korean Patent Application No. 2010-00136609, filed on Dec. 28, 2010, which is hereby incorporated by reference as if fully set forth herein. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a display device, and more particularly, to a display device that reduces a data transmission frequency, thereby minimizing generation of electromagnetic interference (EMI) and noise and realizing high resolution. 
     2. Discussion of the Related Art 
     Generally, a liquid crystal display is one of the flat panel display devices that display images using liquid crystals. A liquid crystal display has advantages in that the liquid crystal display is thinner and lighter and has lower driving voltage and power consumption than the other display devices. For this reason, the liquid crystal display has been widely used over the whole range of industry. 
     It is required for such a liquid crystal display to transmit a large amount of data at high speed and display high-resolution images so as to satisfy user demands for high-quality images. For this reason, the liquid crystal display transmits display data using a high-speed clock with the result that a frequency of the liquid crystal display is increased, and therefore, noise due to EMI may be generated. In particular, in a mobile liquid crystal display using a mobile industry processor interface (MIPI) to transmit data at high speed, noise is excessively generated. 
     Also, a reference clock signal necessary to transmit data so as to realize a high resolution of WVGA (wide video graphic array) on a mobile display at 60 Hz must have a frequency of 25 MHz (=480 (horizontal resolution)×864 (vertical resolution)×60 Hz (frame frequency)). However, a rated range of the clock necessary to transmit data to the mobile industry processor interface is 12.3 MHz to 20 MHz. For this reason, a mobile liquid crystal display using the mobile industry processor interface has a problem in that it is not possible to realize a high resolution of WVGA. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art. 
     An object of the present invention is to provide a display device that reduces a data transmission frequency, thereby minimizing generation of EMI noise and realizing high resolution. 
     Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings. 
     To achieve these objects and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, a display device includes a display panel to display images, a gate driver to drive gate lines of the display panel, a data driver to drive data lines of the display panel, a timing controller to control the gate driver and the data driver and to arrange and supply display data to the data driver, and N (N is a natural number greater than 1) data ports to transmit the display data while being synchronized with N low-speed clock signals having a lower frequency than a clock signal necessary to transmit the display data in the timing controller. 
     Specifically, the timing controller may include a clock conversion unit to generate the first and second low-speed clock signals having a frequency equivalent to half that of the clock signal necessary to transmit the display data, a data division unit to divide the display data into first and second display data, a color management unit to convert the first and second display data based on color management data, and an average picture level/pixel processing algorithm unit to adjust brightness components of the first and second display data and to arrange and transmit the first and second display data to the data driver. 
     Meanwhile, first and second data ports may be formed between the data division unit and the color management unit and between the color management unit and average picture level/pixel processing algorithm unit, respectively, the first data port may transmit the first display data while being synchronized with the first low-speed clock signal, and the second data port may transmit the second display data while being synchronized with the second low-speed clock signal. 
     The first low-speed clock signal may have a phase identical to or reverse to that of the second low-speed clock signal. 
     Meanwhile, the data division unit may divide the display data into the first display data including first to m/2-th display data and the second display data including (m/2)+1-th to m-th display data. Alternatively, the data division unit may divide the display data into the first display data including odd display data and the second display data including even display data. 
     It is to be understood that both the foregoing general description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the invention and together with the description serve to explain the principle of the invention. In the drawings: 
         FIG. 1  is a block diagram showing a liquid crystal display device according to the present invention; 
         FIG. 2  is a block diagram showing a timing controller shown in  FIG. 1  in detail; 
         FIGS. 3A and 3B  are view showing an embodiment of first and second display data supplied through first and second data ports shown in  FIG. 2 ; 
         FIGS. 4A and 4B  are view showing another embodiment of the first and second display data supplied through the first and second data ports shown in  FIG. 2 ; and 
         FIG. 5  is a view illustrating an average picture level (APL)/pixel processing algorithm (PPA) unit shown in  FIG. 2  in detail. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 1  is a block diagram showing a mobile liquid crystal display device using a mobile industry processor interface (MIPI) according to the present invention. 
     The liquid crystal display device shown in  FIG. 1  includes a liquid crystal panel  102  to display images, a gate driver  108  and a data driver  106  to drive the liquid crystal panel  102 , and a timing controller  104  to control the gate driver  108  and the data driver  106 . 
     The liquid crystal panel  102  includes a matrix of liquid crystal cells Clc and thin film transistors TFT connected to gate lines GL 1  to GLn and data lines DL 1  to DLm to drive the respective liquid crystal cells Clc. The thin film transistors TFT of the liquid crystal panel  102  are turned on by gate-on voltage from the gate lines GL. As a result, data signals of the data lines DL are supplied to the liquid crystal cells Clc, and voltage equivalent to the difference between common voltage Vcom and the data signals is applied to the liquid crystal cells Clc. Also, the thin film transistors TFT are turned off by gate-off voltage. As a result, voltage applied to the liquid crystal cells Clc is maintained. The liquid crystal cells Clc drives liquid crystals based on the applied voltage to adjust light transmissivity so that images are displayed on the liquid crystal panel  102 . 
     The gate driver  108  sequentially supplies gate-on voltage to the gate lines GL in response to a gate control signal GCS from the timing controller  104 . In addition, the gate driver  108  supplies gate-off voltages to the gate lines GL for a period where the gate-on voltages are not supplied. 
     The data driver  106  converts digital data signals into analog voltage using data control signal DCS from the timing controller  104  and gamma voltage, and supplies the converted analog voltage to the data lines DL. 
     The timing controller  104  generates a gate control signal GCS and a data control signal DCS using a plurality of synchronizing signals input through a host (not shown) and supplies the generated signals to the gate driver  108  and the data driver  106 . Also, the timing controller  104  arranges display data input from the host and supplies the arranged display data to the data driver  106 . 
     As shown in  FIG. 2 , the timing controller  104  includes first to third interface units  112 ,  114  and  126 , first and second data processing units  120  and  130 , a control signal generation unit  118 , and a clock conversion unit  116 . 
     The clock conversion unit  116  generates first and second low-speed clock signals LCLK 1  and LCLK 2  having a lower speed than a reference clock signal CLK necessary to transmit data using the clock signal CLK. For example, since a reference clock signal CLK necessary to transmit data has a frequency of 25 MHz to realize a high resolution of WVGA (wide video graphic array) on a mobile display at 60 Hz, the first and second low-speed clock signals LCLK 1  and LCLK 2  have a frequency of 12.5 MHz. 
     The clock conversion unit  116  includes a phase locked loop (PLL) circuit to generate the first and second low-speed clock signals LCLK 1  and LCLK 2 . The phase locked loop circuit locks the phase of an input signal to generate a fixed clock frequency. The phase locked loop circuit includes a phase detector, a low pass filter, an error amplifier and a voltage controlled oscillator. The phase locked loop circuit detects a phase difference between an input signal and an output signal, filters a high-frequency component of the detected phase difference signal to calculate direct current voltage equivalent to the phase difference, and applies the direct current voltage to an input of the voltage controlled oscillator so that the output frequency of the voltage controlled oscillator is automatically adjusted to compensate for deviated phase. 
     As described above, the phase locked loop circuit serves to correctly vary the frequency of a clock. Consequently, the clock conversion unit  116  including the phase locked loop circuit generates the first and second low-speed clock signals LCLK 1  and LCLK 2  having a frequency equivalent to half that of the reference clock signal CLK. 
     The first interface unit  112  is a display pixel interface DPI to receive command data including a timing synchronizing signal used to display such display data, such as parallel data bits DB, data enable DE, a vertical synchronizing signal VSYNC, a horizontal synchronizing signal HSYNC and a dot clock signal DCLK, from the host. 
     Command data supplied to the first interface unit  112  are supplied to a color management unit  122  through a port while being synchronized with a high-speed clock signal HCLK having a frequency lower than that of the reference clock signal CLK necessary to transmit data and higher than that of the first and second low-speed clock signals LCLK 1  and LCLK 2 . For example, the high-speed clock signal HCLK has a frequency of 17 MHz to realize the timing controller  104  in low power consumption mode. 
     The second interface unit  114  is a display bus interface to receive command data including a synchronizing signal related to a mode to display such display data, such as parallel data bits DB, a chip select signal, a register select signal, a read signal RD and a write signal WR, from the host. Also, the second interface unit  114  transmits the command data to a frame memory  132  and receives transmission state or command data information from the frame memory  132 . The command data supplied to the second interface unit  114  are supplied to the frame memory  132  in the first data processing unit  130  through a port while being synchronized with a high-speed clock signal HCLK. 
     The third interface unit  126  is a display serial interface to receive display data from the host in a series mode and to transmit the received display data to the frame memory  132 . Also, the third interface unit  126  receives transmission state or display data information from the frame memory  132 . 
     The first data processing unit  130  stores the display data from the third interface unit  126 , divides the display data into first and second display data, and supplies the first and second display data to the second data processing unit  120 . The first data processing unit  130  includes a frame memory  132  and a data division unit  134 . 
     The frame memory  132  buffers the display data from the third interface unit  126  per frame and supplies the buffered display data to the data division unit  134 . 
     As shown in  FIG. 3A  or  3 B, the data division unit  134  divides the display data from the frame memory  132  into first and second display data and supplies the first and second display data to the second data processing unit  120 . 
     Specifically, the data division unit  134  divides m display data into first display data including first to m/2-th display data and second display data including (m/2)+1-th to m-th display data. As shown in  FIGS. 3A and 3B , the first display data are transmitted to the second data processing unit  120  through a first data port DPT 1  while being synchronized with a rising edge of the first low-speed clock signal LCLK 1  from the clock conversion unit  116 . The second display data are transmitted to the second data processing unit  120  through a second data port DPT 2  while being synchronized with a rising edge of the second low-speed clock signal LCLK 2 . At this time, the second low-speed clock signal LCLK 2  has a phase identical to that of the first low-speed clock signal LCLK 1  as shown in  FIG. 3A  or reverse to that of the first low-speed clock signal LCLK 1  as shown in  FIG. 3B . 
     As described above, the data division unit  134  divides display data into first display data including first to m/2-th display data and second display data including (m/2)+1-th to m-th display data. Alternatively, as shown in  FIGS. 4A and 4B , the data division unit  134  may divide display data into first display data including odd display data and second display data including even display data. 
     The second data processing unit  120  receives the command data from the first interface unit  112 . Also, the second data processing unit  120  receives the first and second display data from the data division unit  134  through the first and second data buses DPT 1  and DPT 2 , arranges the display data so to be suitable for the data driver  106  and supplies the arranged display data to the date driver  106 . The second data processing unit  120  includes a color management unit  122  and an average picture level (APL)/pixel processing algorithm (PPA) unit  124 . 
     The color management unit  122  removes discordance between colors of the first and second display data realized through the liquid crystal panel  102  and colors realized through an output apparatus, such as a scanner or a printer, through mapping of a color region, thereby achieving color matching. That is, the color management unit  122  converts the first and second display data input through the first and second data buses DPT 1  and DPT 2  based on color management data included in the command data. The converted first and second display data are transmitted to the APL/PAA unit  124  through the first and second data buses DPT 1  and DPT 2 . 
     Specifically, as shown in  FIGS. 3A and 3B , the first display data are transmitted to the APL/PAA unit  124  through the first data port DPT 1  while being synchronized with a rising edge of the first low-speed clock signal LCLK 1 . The second display data are transmitted to the APL/PAA unit  124  through the second data port DPT 2  while being synchronized with a rising edge of the second low-speed clock signal LCLK 2 . At this time, the second low-speed clock signal LCLK 2  has a phase identical to that of the first low-speed clock signal LCLK 1  as shown in  FIG. 3A  or reverse to that of the first low-speed clock signal LCLK 1  as shown in  FIG. 3B . 
     As shown in  FIG. 5 , the APL/PAA unit  124  extracts average brightness values of red and blue color data R 1 , R 2 , B 1  and B 2  of the first display data including red, green and blue color data R 1 , G 1  and B 1  and the second display data including red, green and blue color data R 2 , G 2  and B 2  to calculate APL. The red and blue color data R 1 , R 2 , B 1  and B 2  are modulated based on the calculated APL. The modulated red and blue color data R′ and B′ and the green data G 1  and G 2  of the first and second display data are mixed, rearranged, and transmitted to the data driver  106 . 
     The control signal generation unit  118  generates a data control signal DCS and a gate control signal GCS using synchronizing signals DE, HSYNC, VSYNC and DCLK from the command data and supplies the generated data and gate control signals to the data driver  106  and the gate drive  108 , respectively. 
     In the present invention, as described above, the first display data are transmitted through the first data port DPT 1  while being synchronized with the first low-speed clock signal LCLK 1 , and the second display data are transmitted through the second data port DPT 2  while being synchronized with the second low-speed clock signal LCLK 2 , between the data division unit  134  and the color management unit  122  and between the color management unit  122  and the APL/PPA unit  124 , respectively. Consequently, a transmission frequency of the display data and the low-speed clock signal is reduced, and therefore, it is possible to reduce EMI and noise. In addition, it is possible to transmit data at high speed, thereby realizing high resolution. 
     Meanwhile, in the present invention, the timing controller  104  and the data driver  106  may be realized as one chip. Although the liquid crystal display device has been described as an example in the above, the present invention may be applied to an organic electroluminescent display device, a plasma display device or an electrophoretic display device. 
     As is apparent from the above description, in the display device according to the present invention, display data are divided into N data, and clock signals are divided into N low-speed clock signals in response to the divided display data and are supplied. That is, first display data are transmitted through a first data port while being synchronized with a first low-speed clock signal, and second display data are transmitted through a second data port while being synchronized with a second low-speed clock signal. Consequently, it is possible to reduce a transmission frequency of the display data and the low-speed clock signals, thereby reducing EMI and noise. Also, it is possible to transmit data at high speed, thereby realizing high resolution. 
     It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the inventions. Thus, it is intended that the present invention covers the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.