Patent Publication Number: US-6660600-B2

Title: Methods of forming integrated circuitry, methods of forming elevated source/drain regions of a field effect transistor, and methods of forming field effect transistors

Description:
RELATED PATENT DATA 
     This patent resulted from a continuation application of U.S. patent application Ser. No. 09/771,449, filed on Jan. 26, 2001, now U.S. Pat. No. 6,444,529 which resulted from a continuation application of U.S. Pat. No. 6,211,026, issued Apr. 3, 2001. 
    
    
     TECHNICAL FIELD 
     This invention relates to methods of forming integrated circuitry, to methods of forming elevated source/drain regions of a field effect transistor, and to methods of forming field effect transistors. 
     BACKGROUND OF THE INVENTION 
     As integrated circuitry device dimensions continue to shrink, problems such as short channel effects, source-drain punchthrough, and hot electron susceptibility become ever present, particularly in the deep sub-half-micron regime. These effects have, in the past, been addressed by additional masking levels and through the incorporation of lightly doped drain (LDD) engineering. 
     This invention arose out of concerns associated with providing improved integrated circuitry devices while reducing problems associated with short channel effects, source-drain punchthrough, and hot electron susceptibility, particularly in the deep sub-half-micron regime. 
     SUMMARY OF THE INVENTION 
     Methods of forming integrated circuitry, methods of forming elevated source/drain regions, and methods of forming field effect transistors are described. In one embodiment, a transistor gate line is formed over a semiconductive substrate. A layer comprising undoped semiconductive material is formed laterally proximate the transistor gate line and joins with semiconductive material of the substrate and comprises elevated source/drain material for a transistor of the line. Subsequently, conductivity-modifying impurity is provided into the elevated source/drain material. In another embodiment, a common step is utilized to provide conductivity enhancing impurity into both elevated source/drain material and material of the gate line. In another embodiment, the undoped semiconductive layer is first patterned and etched to provide elevated source/drain regions prior to provision of the conductivity-modifying impurity. In another embodiment, the semiconductive material is first patterned, with conductivity-modifying impurity being subsequently provided into selected portions of the semiconductive material. Undoped semiconductive portions are subsequently removed selectively relative to doped semiconductive material portions. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     Preferred embodiments of the invention are described below with reference to the following accompanying drawings. 
     FIG. 1 is a diagrammatic side sectional view of a semiconductor wafer fragment in process in accordance with one embodiment of the present invention. 
     FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  1 . 
     FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  2 . 
     FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  3 . 
     FIG. 5 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  4 . 
     FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  5 . 
     FIG. 7 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  6 . 
     FIG. 8 is a view of the FIG. 1 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  7 . 
     FIG. 9 is a diagrammatic side sectional view of a semiconductor wafer fragment in process in accordance with another embodiment of the present invention. 
     FIG. 10 is a view of the FIG. 9 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  9 . 
     FIG. 11 is a view of the FIG. 9 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  10 . 
     FIG. 12 is a view of the FIG. 9 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  11 . 
     FIG. 13 is a diagrammatic side sectional view of a semiconductor wafer fragment in process in accordance with another embodiment of the present invention. 
     FIG. 14 is a view of the FIG. 13 wafer fragment at a processing step which is different from that which is shown in FIG.  13 . 
     FIG. 15 is a view of the FIG. 13 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  14 . 
     FIG. 16 is a view of the FIG. 13 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  15 . 
     FIG. 17 is a view of the FIG. 13 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  16 . 
     FIG. 18 is a diagrammatic side sectional view of a semiconductor wafer fragment in process in accordance with another embodiment of the present invention. 
     FIG. 19 is a view of the FIG. 18 wafer fragment at a processing step which is subsequent to that which is shown in FIG.  18 . 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8). 
     Referring to FIG. 1, a semiconductor wafer fragment in process is shown generally at  30  and includes a semiconductive substrate  32 . In the context of this document, the term “semiconductive substrate” is defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. 
     Isolation regions  34  are formed within substrate  32  and comprise an oxide material. A plurality of lines, e.g. transistor gate lines are formed over the substrate with exemplary gate lines being shown at  36 ,  38  respectively. Gate lines  36 ,  38  include a gate oxide layer  40 , a layer of semiconductive material  42 , and insulative material caps  44 . In this example, layer  42  comprises undoped semiconductive gate line material, with undoped polysilicon being an exemplary material. In the context of this document, “undoped” will be understood to include those materials which, as deposited or formed, do not include meaningful amounts of p-type or n-type materials. An exemplary material for insulative caps  44  is silicon dioxide. For purposes of the ongoing discussion, layer  42  constitutes a layer of first-formed semiconductive material. 
     Gate lines  36 ,  38  constitute a pair of spaced-apart gate lines which, in a preferred embodiment, comprise a portion of dynamic random access memory (DRAM) circuitry. Sidewall spacers  46  are formed over transistor gate lines  36 ,  38  and can comprise nitride and/or oxide materials. Source/drain diffusion regions  48 ,  50 , and  52  are formed within and received by substrate  32 . 
     Referring to FIG. 2, a material layer  54  is formed over substrate  32 , and preferably comprises an undoped semiconductive material. Layer  54  constitutes a second-formed layer of semiconductive material which is formed laterally proximate gate lines  36 ,  38  and joins with semiconductive material of substrate  32  laterally proximate each gate line, e.g. diffusion regions  48 ,  50 , and  52 . As formed, layer  54  constitutes elevated source/drain material for gate lines  36 ,  38 . An exemplary material for layer  54  is undoped polysilicon which can be formed to an elevational thickness of around 4,000 Angstrom. 
     Referring to FIG. 3, material of layer  54  is removed to isolate remaining material relative to the conductive lines. In this example, layer  54  is planarized, as by chemical-mechanical polishing, to provide a generally planar outer surface  56 . Planarization can be made to stop on or proximate insulative caps  44 . Alternately, layer  54  can be etched back, with such etching stopping on or proximate the insulative caps. Although not specifically shown, further portions of layer  54  can be removed to recess the material relative to gate lines  36 ,  38 . 
     At this point in processing, insulative caps  44  can be etched away or otherwise removed from over semiconductive material  42  to expose an outer surface thereof for purposes which will become evident below. Such a construction is shown in FIG.  6 . 
     Referring to FIG. 4, a patterned masking layer  58  is formed over substrate  32  and over portions of the undoped semiconductive material of layer  54 . Exemplary material for layer  58  is photoresist. 
     Referring to FIG. 5, unmasked elevated source/drain material portions are removed to provide individual elevated source/drain regions  60 ,  62 , and  64 . In this example, such material is removed prior to provision of conductivity-modifying or conductivity-enhancing impurity thereinto. In one embodiment, the unmasked portions are etched, preferably through an anisotropic dry etch, which is sufficient to provide the elevated source/drain regions. 
     Referring to FIG. 6, a patterned masking layer  66  is formed over substrate  32 . In one embodiment, conductivity-modifying or conductivity-enhancing impurity is provided into the elevated source/drain material of regions  60 ,  62 , and  64 . In one embodiment, the insulative caps  44  are preferably removed and provision of the impurity comprises also providing the impurity into the exposed, undoped semiconductive gate line material  42 . Accordingly, such can constitute in a common step, providing impurity into both the lines and source/drain regions proximate thereto to form highest conductive portions of the source/drain regions and render the undoped semiconductive material of the line conductive. Alternately considered, this embodiment can constitute contemporaneously providing impurity into exposed undoped semiconductive gate line material  42 , as well as material comprising regions  60 ,  62 , and  64 . Provision of impurity can take place to a concentration of 10 20  cm −3 . 
     In one embodiment, material of both the elevated source/drain regions  60 - 64 , and semiconductive gate material  42  is commonly doped in different steps. Such different steps can provide different impurity doses at different energy levels. In one embodiment, the semiconductive material is doped with a first dose of impurity which is provided at a first energy level, and then a second dose of impurity which is provided at a second energy level. The first dose is preferably substantially the same as the second dose, with an exemplary dose being 5×10 12  atoms/cm 2 . Preferably, the second energy level is less than the first energy level, with an exemplary first energy level being 85 keV and an exemplary second energy level being 35 keV. Such will result in concentrations of implanted impurities which vary within the semiconductive material. 
     In another embodiment, a first region of elevated source/drain material is masked (with patterned masking layer  66  and not specifically shown) while a second region of elevated source/drain material (e.g. regions  60 ,  62 , and  64 ) is doped with an impurity of a second type. In this example, masking layer  66  can be used to open up n-channel active areas, as well as gate regions to allow implantation of the undoped polysilicon over not only the active areas, but the polysilicon gate regions as well. Exemplary material for such doping include arsenic and/or phosphorous. In accordance with this embodiment, masking layer  66  is subsequently removed, and a second region of elevated source/drain material is masked, e.g. with masking layer  68 , while a first region of elevated source/drain material (not specifically shown but disposed within masking layer openings which are substantially similar to the opening defined by previous masking layer  66 ) is provided with an impurity of a first type. In this example, masking layer  68  can be used to open up p-channel active areas, as well as gate regions to allow implantation of the undoped polysilicon over not only the active areas, but the polysilicon gate regions as well. Exemplary materials include boron and BF 2 . 
     Referring to FIGS. 7 and 8, a refractory metal layer  70  (FIG. 7) is formed over substrate  32 . Exemplary materials include titanium and cobalt. In one embodiment, refractory metal layer  70  is formed over silicon-containing material of transistor gate lines  36 ,  38  and exposed to annealing conditions which are effective to render it into a conductive gate line silicide  72  (FIG.  8 ). In another embodiment, refractory metal layer  70  constitutes a common refractory metal layer which is formed over both exposed silicon-containing material of transistor gate lines  36 ,  38 , and the elevated source/drain material comprising regions  60 ,  62 , and  64 . Subsequently, layer  70  is exposed to annealing conditions which are sufficient to render it into both the gate line silicide  72  and a source/drain material silicide  74  (FIG.  8 ). 
     Referring to FIG. 8, and alternately considered, a gate line silicide layer  72  is formed over exposed material of gate lines  36 ,  38  respectively. Elevated source/drain region silicide layers  74  are formed over elevated source/drain material comprising portions of the source/drain regions. In a preferred embodiment, the silicide layers are contemporaneously provided over the illustrated materials. 
     Referring to FIG. 9, a semiconductor wafer fragment in accordance with an alternate embodiment of the present invention is shown generally at  30   a  and includes a semiconductive substrate  32 . Like numerals from the above-described embodiment have been utilized where appropriate, with differences being indicated by the suffix “a” or with different numerals. 
     A material layer  54  is formed over substrate  32  and processed as described above, which can include the planarization thereof. A patterned masking layer  76  is formed over the substrate including portions of undoped semiconductive material  54 . Masking layer  76  defines a masking layer opening  78  which is disposed over only a portion of undoped semiconductive material of layer  54 . Accordingly, material elevationally below masking layer  76  constitutes covered portions of layer  54 , while exposed portions of layer  54  comprise elevated source/drain material regions for the field effect transistors. A semiconductive outer surface of gates lines  36 ,  38  is exposed through masking layer opening  78  (as the insulative caps thereover were previously removed). 
     Conductivity-modifying or conductivity-enhancing impurity is provided, preferably contemporaneously, into exposed semiconductive material  42  and exposed or unmasked portions of layer  54 . Such impurity can be provided in the concentration mentioned above. Such materials can be doped as described above utilizing the first and second doses provided at the first and second energy levels, respectively. Accordingly, material of layer  54  disposed elevationally below masking layer  76  remains substantially undoped laterally outward of doped elevated source/drain regions  60 ,  62 , and  64 . After the provision of the impurity, the masking layer can be stripped. 
     Referring to FIG. 10, the undoped source/drain material portions are removed to provide elevated source/drain regions  60 ,  62 , and  64 . In a preferred embodiment, the removal of such material takes place through an etch which is effective to remove elevated source/drain material containing less impurity than elevated source/drain material containing more impurity. In the illustrated example, a wet etch is conducted which selectively removes undoped semiconductive material relative to the doped semiconductive material. By selectively is meant removing of one layer relative to another layer in a ratio of 5:1 or greater. An exemplary wet etch comprises two percent by volume tetramethyl ammonium hydroxide (TMAH) in water. Etch chemistries could, of course, be changed to achieve higher etch selectivity to doped versus undoped polysilicon. Accordingly, removal of the elevated source/drain material portions in this embodiment takes place after provision of the doping impurity and constitutes removing previously-masked portions of the semiconductive material layer to provide the elevated source/drain regions which comprise the previously-unmasked portions. 
     Subsequently, the substrate can be annealed such that both n+ and p+ plugs or source/drain regions, and n+ gate/p+ gate material is annealed at the same time. 
     Referring to FIGS. 11 and 12, a refractory metal layer  70  is formed over substrate  32 . Exemplary materials include titanium and cobalt. In one embodiment, refractory metal layer  70  is formed over silicon-containing material of transistor gate lines  36 ,  38  and exposed to annealing conditions which are effective to render it into a conductive gate line silicide  72  (FIG.  12 ). In another embodiment, refractory metal layer  70  constitutes a common refractory metal layer which is formed over both exposed silicon-containing material of transistor gate lines  36 ,  38 , and the elevated source/drain material comprising regions  60 ,  62 , and  64 . Subsequently, layer  70  is exposed to annealing conditions which are sufficient to render it into both the gate line silicide  72  and a source/drain material silicide  74  (FIG.  12 ). 
     Referring to FIG. 12, and alternately considered, a gate line silicide layer  72  is formed over exposed material of gate lines  36 ,  38  respectively. Elevated source/drain region silicide layers  74  are formed over elevated source/drain material comprising portions of the source/drain regions. In a preferred embodiment, the silicide layers are contemporaneously provided over the illustrated materials. In this example, silicide layers  72 ,  74  are provided after provision of the impurity and the subsequent wet etching of the undoped semiconductive material. 
     Referring to FIG. 13, a semiconductor wafer fragment in process in accordance with another embodiment of the invention is shown generally at  30   b  and includes a semiconductive substrate  32 . Like numerals from the above described embodiment have been utilized where appropriate with differences being indicated by the suffix “b” or with different numerals. 
     In this example, a pair of spaced-apart conductive lines  36   b ,  38   b  are formed over substrate  32  and include a gate oxide layer  40 , a doped semiconductive material layer  42   b , e.g. polysilicon, a silicide layer  80 , e.g. tungsten silicide, and an insulative cap  82  comprising a material such as nitride. Layer  42   b  is preferably in-situ doped polysilicon. 
     Referring to FIG. 14, a material layer  54  is formed over substrate  32 , and preferably comprises an undoped semiconductive material. Layer  54  constitutes a second-formed layer of semiconductive material which is formed laterally proximate gate lines  36 ,  38  and joins with semiconductive material of substrate  32  laterally proximate each gate line, e.g. diffusion regions  48 ,  50 , and  52 . As formed, layer  54  constitutes elevated source/drain material for gate lines  36   b ,  38   b . An exemplary material for layer  54  is undoped polysilicon which can be formed to an elevational thickness of around 4,000 Angstrom. 
     Material of layer  54  can be removed, as described above, to isolate remaining material relative to the conductive lines. In this example, layer  54  is planarized, as by chemical-mechanical polishing, to provide a generally planar outer surface  56 . Planarization can be made to stop on or proximate insulative caps  82 . Alternately, layer  54  can be etched back, with such etching stopping on or proximate the insulative caps. Although not specifically shown, further portions of layer  54  can be removed to recess the material relative to gate lines  36   b ,  38   b.    
     Referring to FIG. 15, a patterned masking layer  58  is formed over substrate  32  and over portions of the undoped semiconductive material of layer  54 . Exemplary material for layer  58  is photoresist. 
     Referring to FIG. 16, unmasked elevated source/drain material portions are removed to provide individual elevated source/drain regions  60 ,  62 , and  64 . In this example, such material is removed prior to provision of conductivity-modifying or conductivity-enhancing impurity thereinto. In one embodiment, the unmasked portions are etched, preferably through an anisotropic dry etch, which is sufficient to provide the elevated source/drain regions. 
     Referring to FIG. 17, a patterned masking layer  66  is formed over substrate  32 . In one embodiment, conductivity-modifying or conductivity-enhancing impurity is provided into the elevated source/drain material of regions  60 ,  62 , and  64 . Such impurity can be provided in the concentration mentioned above. 
     In one embodiment, material of the elevated source/drain regions  60 - 64  is doped in different steps. Such different steps can provide different impurity doses at different energy levels. In one embodiment, the semiconductive material is doped with a first dose of impurity which is provided at a first energy level, and then a second dose of impurity which is provided at a second energy level. The first dose is preferably substantially the same as the second dose, with an exemplary dose being 5×10 12  atoms/cm 2 . Preferably, the second energy level is less than the first energy level, with an exemplary first energy level being 85 keV and an exemplary second energy level being 35 keV. Such will result in concentrations of implanted impurities which vary within the semiconductive material. 
     In another embodiment, a first region of elevated source/drain material is masked (with patterned masking layer  66  and not specifically shown) while a second region of elevated source/drain material (e.g. regions  60 ,  62 , and  64 ) is doped with an impurity of a second type. In this example, masking layer  66  can be used to open up n-channel active areas to allow implantation of the undoped polysilicon thereover. Exemplary material for such doping include arsenic and/or phosphorous. In accordance with this embodiment, masking layer  66  is subsequently removed, and a second region of elevated source/drain material is masked, e.g. with masking layer  68 , while a first region of elevated source/drain material (not specifically shown but disposed within masking layer openings which are substantially similar to the opening defined by previous masking layer  66 ) is provided with an impurity of a first type. In this example, masking layer  68  can be used to open up p-channel active areas to allow implantation of the undoped polysilicon thereover. Exemplary materials include boron and BF 2 . 
     Subsequent processing, with respect to the formation of the elevated source/drain region silicide can take place as described in connection with FIGS. 7 and 8. 
     Referring to FIG. 18, a semiconductor wafer fragment in accordance with an alternate embodiment of the present invention is shown generally at  30   c  and includes a semiconductive substrate  32 . Like numerals from the above-described embodiment have been utilized where appropriate, with differences being indicated by the suffix “c” or with different numerals. 
     A material layer  54  is formed over substrate  32  and processed as described above, which can include the planarization thereof. A patterned masking layer  76  is formed over the substrate including portions of undoped semiconductive material  54 . Masking layer  76  defines a masking layer opening  78  which is disposed over only a portion of undoped semiconductive material of layer  54 . Accordingly, material elevationally below masking layer  76  constitutes covered portions of layer  54 , while exposed portions of layer  54  comprise elevated source/drain material regions for the field effect transistors. 
     Conductivity-modifying or conductivity-enhancing impurity is provided into exposed or unmasked portions of layer  54 . Such impurity can be provided in the concentration mentioned above. Such materials can be doped as described above utilizing the first and second doses provided at the first and second energy levels, respectively. Accordingly, material of layer  54  disposed elevationally below masking layer  76  remains substantially undoped laterally outward of doped elevated source/drain regions  60 ,  62 , and  64 . After the provision of the impurity, the masking layer can be stripped. 
     Referring to FIG. 19, the undoped source/drain material portions are removed to provide elevated source/drain regions  60 ,  62 , and  64 . In a preferred embodiment, the removal of such material takes place through an etch which is effective to remove elevated source/drain material containing less impurity than elevated source/drain material containing more impurity. In the illustrated example, a wet etch is conducted which selectively removes undoped semiconductive material relative to the doped semiconductive material. An exemplary wet etch comprises two percent by volume tetramethyl ammonium hydroxide (TMAH) in water. Etch chemistries could, of course, be changed to achieve higher etch selectivity to doped versus undoped polysilicon. Accordingly, removal of the elevated source/drain material portions in this embodiment takes place after provision of the doping impurity and constitutes removing previously-masked portions of the semiconductive material layer to provide the elevated source/drain regions which comprise the previously-unmasked portions. 
     Subsequently, the substrate can be annealed such that both n+ and p+ plugs or source/drain regions is annealed at the same time. 
     Subsequent processing, with respect to the formation of the elevated source/drain region silicide can take place as described in connection with FIGS. 11 and 12. 
     Advantages of the present invention include improved CMOS formation techniques which use plugs or elevated source/drain regions over the p+/n+ active areas followed by a salicide process for sheet resistance reductions which improves robustness in the finished device. In addition, requirements of self-aligned contact etching in the previous DRAM processing flows can be reduced. Specifically, traditional formation of DRAM cells requires the use of a self-aligned contact etch through, for example, BPSG, to form DRAM cell capacitors. Various invented methods do not require such a self-aligned contact etch to form DRAM cell capacitors. The invented methods can also achieve n-channel and p-channel devices with elevated source/drain regions for better short channel characteristics without the use of additional masking steps. Moreover, realization of p+ polysilicon flows for p-type MOSFETs can be achieved without the use of any additional masks. 
     In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.