Patent Publication Number: US-8981848-B2

Title: Programmable delay circuitry

Description:
RELATED APPLICATION 
     The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/316,229, filed Dec. 9, 2011, entitled “PSEUDO-ENVELOPE FOLLOWER POWER MANAGEMENT SYSTEM WITH HIGH FREQUENCY RIPPLE CURRENT COMPENSATION,” now U.S. Pat. No. 8,633,766, which claims priority to U.S. Provisional Patent Applications No. 61/421,348, filed Dec. 9, 2010; No. 61/421,475, filed Dec. 9, 2010; and No. 61/469,276, filed Mar. 30, 2011. 
     The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, entitled “PSEUDO-ENVELOPE FOLLOWING POWER MANAGEMENT SYSTEM,” now U.S. Pat. No. 8,493,141, which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010. 
     The present application claims priority to and is a continuation-in-part of U.S. patent application Ser. No. 13/218,400, filed Aug. 25, 2011, entitled “BOOST CHARGE-PUMP WITH FRACTIONAL RATIO AND OFFSET LOOP FOR SUPPLY MODULATION,” now U.S. Pat. No. 8,519,788, which claims priority to U.S. Provisional Patent Application No. 61/376,877, filed Aug. 25, 2010. U.S. patent application Ser. No. 13/218,400 is a continuation-in-part of U.S. patent application Ser. No. 13/089,917, filed Apr. 19, 2011, which claims priority to U.S. Provisional Patent Application No. 61/325,659, filed Apr. 19, 2010. 
     All of the applications listed above are hereby incorporated herein by reference in their entireties. 
    
    
     FIELD OF THE DISCLOSURE 
     The embodiments described herein relate to a power management system for delivering current to a linear RF power amplifier. More particularly, the embodiments relate to the use of a pseudo-envelope tracker in a power management system of mobile communications equipment. 
     BACKGROUND 
     Next-generation mobile devices are morphing from voice-centric telephones to message and multimedia-based “smart” phones that offer attractive new features. As an example, smart phones offer robust multimedia features such as web-browsing, audio and video playback and streaming, email access and a rich gaming environment. But even as manufacturers race to deliver ever more feature rich mobile devices, the challenge of powering them looms large. 
     In particular, the impressive growth of high bandwidth applications for radio frequency (RF) hand-held devices has led to increased demand for efficient power saving techniques to increase battery life. Because the power amplifier of the mobile device consumes a large percentage of the overall power budget of the mobile device, various power management systems have been proposed to increase the overall power efficiency of the power amplifier. 
     As an example, some power management systems may use a V RAMP  power control voltage to control the voltage presented on a power amplifier collector of a linear RF power amplifier. As another example, other power management schemes may use a buck converter power supply and a class AB amplifier in tandem to provide power to the linear RF power amplifier. 
     Even so, there remains a need to further improve the power efficiency of mobile devices to provide extended battery life. As a result, there is a need to improve the power management system of mobile devices. 
     SUMMARY 
     Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay. 
     In one embodiment of the programmable delay circuitry, the correction start voltage circuit helps stabilize the variable time delay by reducing disturbances in a voltage across the variable delay capacitor when certain transistor elements in the programmable delay circuitry transition to be in a conducting state. Further, the correction start voltage circuit may improve accuracy of the variable time delay by reducing transition times of certain transistor elements in the programmable delay circuitry. 
     In one embodiment of the programmable delay circuitry, the programmable delay circuitry further includes a voltage divider circuit and a bias current and mirror circuit. The voltage divider circuit is coupled to the bias current and mirror circuit. The bias current and mirror circuit is coupled to the variable delay circuitry. The voltage divider circuit and the bias current and mirror circuit are configured to reduce changes in the variable time delay due to changes in a voltage level of a circuit supply voltage, which is provided to the programmable delay circuitry. 
     Those skilled in the art will appreciate the scope of the disclosure and realize additional aspects thereof after reading the following detailed description in association with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1A  depicts an embodiment of a pseudo-envelope follower power management system for managing power supplied to a linear RF power amplifier. 
         FIG. 1B  depicts an embodiment of a pseudo-envelope follower power management system for managing power supplied to a linear RF power amplifier. 
         FIG. 2A  depicts an embodiment of the pseudo-envelope follower power management system of  FIG. 1A  in further detail. 
         FIG. 2B  depicts an embodiment of the pseudo-envelope follower power management system of  FIG. 1B  in further detail. 
         FIG. 3A  depicts an embodiment of programmable delay circuitry. 
         FIG. 3B  depicts another embodiment of the programmable delay circuitry. 
         FIG. 4  depicts a further embodiment of the programmable delay circuitry. 
         FIG. 5A  depicts an embodiment of a parallel amplifier output impedance compensation circuit including a digital V RAMP  pre-distortion filter circuit. 
         FIG. 5B  depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit. 
         FIG. 5C  depicts another embodiment of a parallel amplifier output impedance compensation circuit including an analog V RAMP  pre-distortion filter circuit. 
         FIG. 5D  depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit. 
         FIG. 5E  depicts an alternative embodiment of a parallel amplifier output impedance compensation circuit. 
         FIG. 6  depicts embodiments of the digital V RAMP  pre-distortion filter and a V RAMP  digital-to-analog (D/A) circuit. 
         FIG. 7  depicts an example embodiment of a variable delay capacitor. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a current to a power amplifier supply output via an inductor. The parallel amplifier generates a power amplifier supply voltage at the power amplifier supply output based on a compensated V RAMP  signal. The parallel amplifier output impedance compensation circuit compensates for a non-ideal output impedance of the parallel amplifier by providing the compensated V RAMP  signal based on a combination of a V RAMP  signal and a high frequency ripple compensation signal. The high frequency ripple compensation signal is based on a difference between the V RAMP  signal and an estimated switching voltage output, which is provided by the switch mode power supply converter. 
     In one embodiment of the parallel amplifier output impedance compensation circuit, the combination of the V RAMP  signal and the high frequency ripple compensation signal is based on pre-filtering the V RAMP  signal to equalize the overall frequency response of the switch mode power supply converter and the parallel amplifier to provide a proper transfer function of the switch mode power supply converter and the parallel amplifier. 
       FIGS. 1A and 2A  depict an example embodiment of a pseudo-envelope follower power management system  10 A including a multi-level charge pump buck converter  12 , a parallel amplifier circuit  14 , a power inductor  16 , a coupling circuit  18 , and a bypass capacitor  19 . The bypass capacitor  19  has a bypass capacitor capacitance, C BYPASS . The multi-level charge pump buck converter  12  and the parallel amplifier circuit  14  may be configured to operate in tandem to generate a power amplifier supply voltage, V CC , at a power amplifier supply output  28  of the pseudo-envelope follower power management system  10 A for a linear RF power amplifier  22 . The power amplifier supply output  28  provides an output current, I OUT , to the linear RF power amplifier  22 . The linear RF power amplifier  22  may include a power amplifier input, P IN , which is configured to receive a modulated RF signal, and a power amplifier output, P OUT , coupled to an output load, Z LOAD . As an example, the output load, Z LOAD , may be an antenna. 
     The multi-level charge pump buck converter  12  may include a supply input  24 , which is configured to receive a direct current (DC) voltage, V BAT , from a battery  20 , and a switching voltage output  26 , which is configured to provide a switching voltage, V SW . The switching voltage output  26  may be coupled to the power amplifier supply output  28  by the power inductor  16 , where the power inductor  16  couples to the bypass capacitor  19  to form an output filter  29  for the switching voltage output  26  of the multi-level charge pump buck converter  12 . The power inductor  16  provides an inductor current, I SW     —     OUT , to the power amplifier supply output  28 . The parallel amplifier circuit  14  may include a parallel amplifier supply input  30 , which is configured to receive the DC voltage, V BAT , from the battery  20 , a parallel amplifier output  32 A, a first control input  34 , which is configured to receive a V RAMP  signal, and a second control input configured to receive the power amplifier supply voltage, V CC . The parallel amplifier output  32 A of the parallel amplifier circuit  14  may be coupled to the power amplifier supply voltage V CC , by the coupling circuit  18 . A parallel amplifier output voltage, V PARA     —     AMP , is provided by the parallel amplifier circuit  14  via the parallel amplifier output  32 A. 
     As an example, the parallel amplifier circuit  14  may generate the parallel amplifier output voltage, V PARA     —     AMP , based on the difference between the V RAMP  signal and the power amplifier supply voltage, V CC . Thus, the V RAMP  signal may represent either an analog or digital signal that contains the required supply modulation information for a power amplifier collector of the linear RF power amplifier  22 . Typically, the V RAMP  signal is provided to the parallel amplifier circuit  14  as a differential analog signal to provide common mode rejection against any noise or spurs that could appear on this signal. The V RAMP  signal may be a time domain signal, V RAMP (t), generated by a transceiver or modem and used to transmit radio frequency (RF) signals. For example, the V RAMP  signal may be generated by a digital baseband processing portion of the transceiver or modem, where the digital V RAMP  signal, V RAMP     —     DIGITAL , is digital-to-analog converted to form the V RAMP  signal in the analog domain. In some embodiments, the “analog” V RAMP  signal is a differential signal. The transceiver or a modem may generate the V RAMP  signal based upon a known RF modulation Amp(t)*cos(2*pi*f RF *t+Phase(t)). The V RAMP  signal may represent the target voltage for the power amplifier supply voltage, V CC , to be generated at the power amplifier supply output  28  of the pseudo-envelope follower power management system  10 A, where the pseudo-envelope follower power management system  10 A provides the power amplifier supply voltage, V CC , to the linear RF power amplifier  22 . Also the V RAMP  signal may be generated from a detector coupled to the linear RF power amplifier  22 . 
     For example, the parallel amplifier circuit  14  includes the parallel amplifier output  32 A that provides the parallel amplifier output voltage, V PARA     —     AMP , to the coupling circuit  18 . The parallel amplifier output  32 A sources a parallel amplifier circuit output current, I PAWA     —     OUT , to the coupling circuit  18 . The parallel amplifier circuit  14 , depicted in  FIG. 1A  and  FIG. 1B , may provide a parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , to the multi-level charge pump buck converter  12  as an estimate of the parallel amplifier circuit output current I PAWA     —     OUT , of the parallel amplifier circuit  14 . Thus, the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , represents an estimate of the parallel amplifier circuit output current I PAWA     —     OUT , provided by the parallel amplifier circuit  14  as a feedback signal to the multi-level charge pump buck converter  12 . Based on the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , the multi-level charge pump buck converter  12  may be configured to control the switching voltage, V SW , provided at the switching voltage output  26  of the multi-level charge pump buck converter  12 . 
     In some embodiments of the pseudo-envelope follower power management system  10 A, depicted in  FIG. 1A , and the pseudo-envelope follower power management system  10 B, depicted in  FIG. 1B , the coupling circuit  18  may be an offset capacitor, C OFFSET . An offset voltage, V OFFSET , may be developed across the coupling circuit  18 . In other alternative embodiments, the coupling circuit  18  may be a wire trace such that the offset voltage, V OFFSET , between the parallel amplifier output voltage, V PARA     —     AMP , and the power amplifier supply voltage, V CC , is zero volts. In still other embodiments, the coupling circuit  18  may be a transformer. 
     A pseudo-envelope follower power management system  10 A, depicted in  FIG. 2A , is an example embodiment of the pseudo-envelope follower power management system  10  depicted in  FIG. 1A . Unlike the pseudo-envelope follower power management system  10  depicted in  FIG. 1A , the pseudo-envelope follower power management system  10 A depicted in  FIG. 2A  includes an embodiment of the multi-level charge pump buck converter  12 A and a parallel amplifier circuit  14 A having parallel amplifier circuitry  32 . The parallel amplifier circuitry  32  includes a parallel amplifier  35  and a parallel amplifier sense circuit  36 . The parallel amplifier circuit  14 A further includes a parallel amplifier output impedance compensation circuit  37  configured to receive the V RAMP  signal and provide a compensated V RAMP  signal, V RAMP     —     C , to an input to the parallel amplifier  35 . The compensated V RAMP  signal, V RAMP     —     C , is a function of the V RAMP  signal. The parallel amplifier  35  generates a parallel amplifier output current, I PARA     —     AMP , to produce a parallel amplifier output voltage, V PARA     —     AMP , at the parallel amplifier output  32 A based on the difference between the compensated V RAMP  signal, V RAMP     —     C  and the power amplifier supply voltage, V CC , generated at power amplifier supply output  28 . The parallel amplifier sense circuit  36  generates a scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , which is a fractional representation of the parallel amplifier output current, I PARA     —     AMP , generated by the parallel amplifier  35 . Alternatively, in those embodiments of the parallel amplifier circuit  14  that do not include the parallel amplifier output impedance compensation circuit  37 , the parallel amplifier  35  generates the parallel amplifier output current, I PARA     —     AMP , to produce the parallel amplifier output voltage, V PARA     —     AMP , based on the difference between the V RAMP  signal and the power amplifier supply voltage, V CC . 
     The parallel amplifier circuit  14 A may further include an open loop assist circuit  39  configured to receive a feed forward control signal  38 , V SWITCHER , the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , and the V RAMP  signal. In response to the feed forward control signal  38 , V SWITCHER , the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , and the V RAMP  signal; the open loop assist circuit  39  may be configured to generate an open loop assist current, I ASSIST . The open loop assist current, I ASSIST , may be provided to the parallel amplifier output  32 A. The parallel amplifier output current, I PARA     —     AMP , generated by the parallel amplifier  35  and the open loop assist circuit current, I ASSIST , generated by the open loop assist circuit  39 , may be combined to form the parallel amplifier circuit output current, I PAWA     —     OUT , of the parallel amplifier circuit  14 A. The parallel amplifier circuit  14 A may further include a V OFFSET  loop circuit  41  configured to generate a threshold offset current  42 , I THRESHOLD     —     OFFSET . The threshold offset current  42 , I THRESHOLD     —     OFFSET , may be provided from the parallel amplifier circuit  14 A as a feedback signal to the multi-level charge pump buck converter  12 A. The V OFFSET  loop circuit  41  may be configured to provide a threshold offset current  42 , I THRESHOLD     —     OFFSET , as an estimate of the magnitude of the offset voltage, V OFFSET , appearing across the coupling circuit  18 . In those cases where the coupling circuit is a wire trace such that the offset voltage, V OFFSET , is always zero volts, the parallel amplifier circuit  14 A may not provide the threshold offset current  42 , I THRESHOLD     —     OFFSET , to the multi-level charge pump buck converter  12 A. 
     Another example is the pseudo-envelope follower power management system  10 B depicted in  FIG. 2B , which is similar to the embodiment of the pseudo-envelope follower power management system  10 B depicted in  FIG. 1B . The pseudo-envelope follower power management system  10 B is operationally and functionally similar in form and function to the pseudo-envelope follower power management system  10 A is depicted in  FIG. 2A . However, unlike the pseudo-envelope follower power management system  10 A depicted in  FIG. 2A , the pseudo-envelope follower power management system  10 B depicted in  FIG. 2B  includes a multi-level charge pump buck converter  12 B configured to generate an estimated switching voltage output  38 B, V SW     —     EST , and a parallel amplifier circuit  14 B configured to receive the estimated switching voltage output  38 B, V SW     —     EST , instead of the feed forward control signal  38 , V SWITCHER . Consequentially, as depicted in  FIG. 2B , the open loop assist circuit  39  of the parallel amplifier circuit  14 B is configured to use only the estimated switching voltage output  38 B, V SW     —     EST , instead of the feed forward control signal  38 , V SWITCHER . The estimated switching voltage output  38 B, V SW     —     EST , provides an indication of the switching voltage, V SW . 
     The generation of the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , depicted in  FIGS. 1A and 1B  will now be described with continuing reference to the embodiment of the parallel amplifier circuit  14 A, depicted in  FIG. 2A , and the embodiment of the parallel amplifier circuit  14 B depicted in  FIG. 2B . Embodiments of the parallel amplifier circuit  14 A and the parallel amplifier circuit  14 B, depicted in  FIGS. 2A and 2B , may provide the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , where the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , includes a scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , and a scaled open loop assist circuit output current estimate, I ASSIST     —     SENSE . The scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , is a scaled estimate of the parallel amplifier output current, I PARA     —     AMP , generated by the parallel amplifier sense circuit  36  of the parallel amplifier circuitry  32 . In some alternative embodiments, the parallel amplifier  35  may generate the scaled estimate of the parallel amplifier output current, I PARA     —     AMP     —     SENSE , directly. The scaled open loop assist circuit current estimate, I ASSIST     —     SENSE , is a scaled estimate of the open loop assist circuit current, I ASSIST , generated by the open loop assist circuit  39 . In other alternative embodiments of the parallel amplifier circuit  14  depicted in  FIG. 1A  and  FIG. 1B , the parallel amplifier circuit  14  does not include the open loop assist circuit  39 . In those embodiments of the parallel amplifier circuit  14  depicted in  FIG. 1A  and  FIG. 1B  that do not include the open loop assist circuit  39 , the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , may only be based on the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE . 
     Returning to  FIGS. 1A and 1B , the pseudo-envelope follower power management systems  10 A and  10 B may further include a control bus  44  coupled to a controller  50 . The control bus  44  may be coupled to a control bus interface  46  of the multi-level charge pump buck converter  12  and a control bus interface  48  of the parallel amplifier circuit  14 . The controller  50  may include various logical blocks, modules, and circuits. The controller  50  may be implemented or performed with a processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices. As an example, a combination of computing devices may include a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration. The controller may further include or be embodied in hardware and in computer executable instructions that are stored in memory, and may reside, for example, in Random Access Memory (RAM), flash memory, Read Only Memory (ROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), registers, hard disk, a removable disk, a CD-ROM, or any other form of computer readable medium known in the art. An exemplary storage medium may be coupled to the processor such that a processor can read information from, and write information to, the storage medium. In the alternative, the storage medium or a portion of the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. 
       FIGS. 2A and 2B  depict a pseudo-envelope follower power management system  10 A and a pseudo-envelope follower power management system  10 B, respectively, that include embodiments of the multi-level charge pump buck converter  12 A and the multi-level charge pump buck converter  12 B. As depicted in  FIGS. 2A and 2B , some embodiments of the multi-level charge pump buck converter  12  of  FIGS. 1A and 1B  may include an FLL circuit  54  configured to interoperate with a switcher control circuit  52 . Alternatively, some embodiments of the multi-level charge pump buck converter  12 A and the multi-level charge pump buck converter  12 B may not include an FLL circuit  54  or be configured to operate with the FLL circuit  54  being disabled. 
     As further depicted in  FIGS. 2A and 2B , some embodiments of the switcher control circuit  52  may be configured to control the operation of a multi-level charge pump circuit  56  and a switching circuit  58  to generate the switching voltage, V SW , on the switching voltage output  26  of the multi-level charge pump buck converter  12 A or the multi-level charge pump buck converter  12 B, respectively. For example, the switcher control circuit  52  may use a charge pump mode control signal  60  to configure the operation of the multi-level charge pump circuit  56  to provide a charge pump output  64  to the switching circuit  58 . Alternatively, the switcher control circuit  52  may generate a series switch control signal  66  to configure the switching circuit  58  to provide the switching voltage, V SW , substantially equal to the DC voltage, V BAT , from the battery  20  via a first switching element coupled between the supply input  24  and the switching voltage output  26 . As another example, the switcher control circuit  52  may configure the switching circuit  58  to provide the switching voltage, V SW , through a second switching element coupled to ground such that the switching voltage, V SW , is substantially equal to ground. 
     In addition, the parallel amplifier circuit  14 A, depicted in  FIG. 2A , and the parallel amplifier circuit  14 B, depicted in  FIG. 2B , may be configured to provide the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , and the threshold offset current  42 , I THRESHOLD     —     OFFSET , to the switcher control circuit  52  in order to control the operation of the switcher control circuit  52 . As discussed in detail below, some embodiments of the switcher control circuit  52  may be configured to receive and use the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , the threshold offset current  42 , I THRESHOLD     —     OFFSET , and/or a combination thereof to control the operation of the switcher control circuit  52 . 
     For example, the switcher control circuit  52  may use the parallel amplifier circuit output current estimate  40 , I PAWA     —     OUT     —     EST , the threshold offset current  42 , I THRESHOLD     —     OFFSET , and/or a combination thereof to determine the magnitude of the voltage provided by the switching voltage, V SW , from the multi-level charge pump circuit  56 . 
       FIG. 3A  depicts an embodiment of programmable delay circuitry  432 A, where the embodiment of the programmable delay circuitry  432 A includes both fixed delay circuitry  635  and variable delay circuitry  640 A. The fixed delay circuitry  635  includes an input stage  642  including an input node  642 A, a first PFET  644 , PFET 1 , a first NFET  646 , NFET 1 , a first fixed current source  648 , a second fixed current source  650 , and a first fixed delay capacitor  652 . The first fixed delay capacitor  652  has a first fixed delay capacitance, C DELAY1 . The input node  642 A of the input stage  642  is configured to receive an input voltage, V IN , having a digital logic level signal, where the digital logic level signal is to be delayed by the programmable delay circuitry  432 A. The input stage  642  is formed by coupling the gate of the first PFET  644 , PFET 1 , and the gate of the first NFET  646 , NFET 1 , to the input node  642 A. The first fixed current source  648  is coupled between a circuit supply voltage, V DD , and the source of the first PFET  644 , PFET 1 . The second fixed current source  650  is coupled between the source of the first NFET  646 , NFET 1 , and ground. The first fixed delay capacitor  652  is coupled between ground and the drain of the first PFET  644 , PFET 1 , and the drain of the first NFET  646 , NFET 1 . During normal operation, when the input voltage, V IN , at the input node  642 A is sufficiently low such that the input voltage, V IN  is substantially equal to a logic low threshold voltage, the first PFET  644 , PFET 1 , is configured to be in a conducting state and the first NFET  646 , NFET 1 , is configured to be in a non-conducting state. When the first PFET  644 , PFET 1 , is turned on, the first fixed current source  648  sources a fixed bias current, I BIAS , to the first fixed delay capacitor  652  with a first fixed capacitor current, I C1 . Assuming that most of the first fixed bias current, I BIAS , from the first fixed current source  648  is used to charge the first fixed delay capacitor  652 , the first fixed capacitor current, I C1 , is substantially equal to the fixed bias current, I BIAS , provided from the first fixed current source  648  through first PFET  644 , PFET 1 . As the first fixed delay capacitor  652  is charged, a first delay voltage, V D1 , continues to increase and eventually rises above a voltage level that is greater than a logic high threshold voltage that may trigger an action by the variable delay circuitry  640 A. 
     Otherwise, when the input voltage, V IN , at the input node  642 A is sufficiently high such that the input voltage, V IN  is substantially equal to a logic high threshold voltage, the first PFET  644 , PFET 1 , is configured to be in a non-conducting state and the first NFET  646 , NFET 1 , is configured to be in a conducting state. When the first NFET  646 , NFET 1 , is turned on, the second fixed current source  650  sinks a fixed bias current, I BIAS , from the first fixed delay capacitor  652  to generate the first fixed capacitor current, I C1 , of opposite magnitude than when the first fixed delay capacitor  652  is being charged by the first fixed current source  648 . Assuming that most of the fixed bias current, I BIAS , sunk through the first NFET  646 , NFET 1  by the second fixed current source  650  is used to discharge the first fixed delay capacitor  652 , the magnitude of the first fixed capacitor current, I C1 , is substantially equal to the magnitude of the fixed bias current, I BIAS , sunk by the second fixed current source  650  through the first NFET  646 , NFET 1 . As the first fixed delay capacitor  652  is discharged, the first delay voltage, V D1 , continues to decrease and eventually falls below a voltage level that is less than a logic low threshold voltage that may trigger an action by the variable delay circuitry  640 A. 
     Because the first fixed current source  648  and the second fixed current source  650  each source and sink, respectively, a current equal to the fixed bias current, I BIAS , the first fixed delay capacitor  652  is charged and discharged at the same rate. The first fixed delay time associated with the fixed delay circuitry  635  is due to the generation of the first delay voltage, V D1 . Because the current sourced by the first fixed current source  648  and sunk by the second fixed current source  650  are substantially equal, the rise time and fall time of the first delay voltage, V D1 , are substantially equal. Effectively, the first fixed delay time is due to the time required to propagate the digital logic state represented by the input voltage, V IN , through the fixed delay circuitry  635  and provide the first delay voltage, V D1 , that represents a digital logic state to an input stage  654  of the variable delay circuitry  640 A. 
     The variable delay circuitry  640 A includes the input stage  654  having an input node  654 A coupled to the drain of the first PFET  644 , PFET 1 , the drain of the first NFET  646 , NFET 1 , and the first fixed delay capacitor  652 . The variable delay circuitry  640 A further includes a second PFET  656 , PFET 2 , a second NFET  658 , NFET 2 , a first variable current source  660 , a second variable current source  662 , and a second fixed delay capacitor  664 . The second fixed delay capacitor  664  has a second delay capacitance, C DELAY2 . 
     The input stage  654  of the variable delay circuitry  640 A is formed by coupling the gate of the second PFET  656 , PFET 2 , and the gate of the second NFET  658 , NFET 2 , to the input node  654 A. The variable delay circuitry  640 A is further formed by coupling the first variable current source  660  between the circuit supply voltage, V DD , and the source of the second PFET  656 , PFET 2 , such that the first variable current source  660  may provide a variable bias current, I BIAS     —     VAR , to the source of the second PFET  656 , PFET 2  when the second PFET  656 , PFET 2 , is in a conducting state. In addition, the second variable current source  662  is coupled between the source of the second NFET  658 , NFET 2 , and ground such that the second variable current source  662  may sink a variable bias current, I BIAS     —     VAR , from the source of the second NFET  658 , NFET 2 , when the second NFET  658 , NFET 2 , is in a conducting state. The second fixed delay capacitor  664  is coupled between ground and the drain of the second PFET  656 , PFET 2 , and the drain of the second NFET  658 , NFET 2 . 
     In addition, the variable delay circuitry  640 A further includes an output buffer stage  666  that includes a third PFET  668 , PFET 3  operably coupled to a third NFET  670 , NFET 3  to form an input node  666 A. The output buffer stage  666  includes an input node  666 A formed by coupling the gate of the third PFET  668 , PFET 3 , to the gate of the third NFET  670 , NFET 3 . The source of the third PFET  668 , PFET 3 , is coupled to the circuit supply voltage, V DD . The source of the third NFET  670 , NFET 3 , is coupled to ground. The output buffer stage  666  further includes an output buffer stage output  672  that corresponds to the output of the programmable delay circuitry  432 A. The output buffer stage output  672  may be formed by coupling the drain of the third PFET  668 , PFET 3 , to the drain of the third NFET  670 , NFET 3 . The output buffer stage  666  is configured to generate an output voltage, V OUT , at the output buffer stage output  672 . Generally, the output voltage, V OUT , generated by the output buffer stage  666  at the output buffer stage output  672  will represent either a digital logic high state or a digital logic low state. For example, when the output voltage, V OUT , is substantially equal to the circuit supply voltage, V DD , the output voltage, V OUT , represents a digital logic high state. When the output voltage, V OUT , is substantially equal to the ground voltage, the output voltage, V OUT , represents a digital logic low state. 
     During operation of the variable delay circuitry  640 A, a second delay voltage, V D2 , increases as the second fixed delay capacitor  664  is charged and decreases as the second fixed delay capacitor  664  is discharged. When the second delay voltage, V D2 , is sufficiently low such that the second delay voltage, V D2 , is substantially equal to or below a logic low threshold voltage, the third PFET  668 , PFET 3 , is configured to be in a conducting state and the third NFET  670 , NFET 3  is configured to be in a non-conducting state. In this case, when the third PFET  668 , PFET 3 , is turned on, the output buffer stage output  672  is coupled to the circuit supply voltage, V DD , via the third PFET  668 , PFET 3 . As a result, the output voltage, V OUT , at the output buffer stage output  672  is substantially equal to the circuit supply voltage, V DD , and the output voltage, V OUT , represents a digital logic high state. 
     However, when the second delay voltage, V D2 , is sufficiently high such that the second delay voltage, V D2 , is substantially equal to or above a logic high threshold voltage, the third PFET  668 , PFET 3 , is configured to be in a non-conducting state and the third NFET  670 , NFET 3  is configured to be in a conducting state. In this case, the third NFET  670 , NFET 3 , is turned on and the output buffer stage output  672  is coupled to ground via the third NFET  670 , NFET 3 . As a result, the output voltage, V OUT , at the output buffer stage output  672  is substantially equal to the ground voltage, and the output voltage, V OUT , represents a digital logic low state. 
     During normal operation, when the first delay voltage, V D1 , at the input node  654 A is sufficiently low to be equal to or lower than a logic low threshold voltage, the second PFET  656 , PFET 2 , is configured to be in a conducting state and the second NFET  658 , NFET 2 , is configured to be in a non-conducting state. Accordingly, when the second PFET  656 , PFET 2 , is turned on, the first variable current source  660  sources the variable bias current, I BIAS     —     VAR , through the second PFET  656 , PFET 2 , to charge the second fixed delay capacitor  664  with a second fixed capacitor current, I C2 . Assuming that most of the variable bias current, I BIAS     —     VAR , from the first variable current source  660  is used to charge the second fixed delay capacitor  664 , the second fixed capacitor current, I C2  is substantially equal to the variable bias current, I BIAS     —     VAR , provided by the first variable current source  660 . As the second fixed delay capacitor  664  is charged by the variable bias current, I BIAS     —     VAR , the magnitude of the second delay voltage, V D2 , continues to increase and eventually rises above a voltage level that is greater than the logic high threshold voltage that may trigger an action by the output buffer stage  666 . For example, once the second delay voltage, V D2 , reaches or exceeds the logic high threshold voltage, the output buffer stage  666  will trigger so as to generate an output voltage, V OUT  that represents a digital logic low state. 
     Otherwise, during normal operation, when the first delay voltage, V D1 , at the input node  654 A is sufficiently high to be equal to exceed a logic high threshold voltage, the second PFET  656 , PFET 2 , is configured to be in a non-conducting state and the second NFET  658 , NFET 2 , is configured to be in a conducting state. Accordingly, when the second NFET  658 , NFET 2 , is turned on, the second variable current source  662  sinks the variable bias current, I BIAS     —     VAR , through the second NFET  658 , NFET 2 , to discharge the second fixed delay capacitor  664  with the second fixed capacitor current, I C2 , by removing charge from the second fixed delay capacitor  664 . Assuming that most of the variable bias current, I BIAS     —     VAR , sunk by the second variable current source  662  is used to discharge the second fixed delay capacitor  664 , the magnitude of the second fixed capacitor current, I C2 , that removes charge from the second fixed delay capacitor  664  is substantially equal to the variable bias current, I BIAS     —     VAR , sunk by the second variable current source  662 . As the second fixed delay capacitor  664  is discharged by the variable bias current, I BIAS     —     VAR , the magnitude of the second delay voltage, V D2 , continues to decrease or eventually fall below a voltage level that is less than the logic low threshold voltage that may trigger an action by the output buffer stage  666 . For example, once the second delay voltage, V D2 , reaches or falls below the logic low threshold voltage, the output buffer stage  666  will trigger, and the output buffer stage  666  will generate an output voltage, V OUT , that represents a digital logic high state. 
     The variable delay time provided by the variable delay circuitry  640 A is created by the time period required to charge and discharge the second fixed delay capacitor  664  with the variable bias current, I BIAS     —     VAR , where the variable bias current, I BIAS     —     VAR , varies in magnitude. As depicted in  FIG. 3A , the first variable current source  660  and the second variable current source  662  are each configured to respectively source and sink currents that are both equal to the variable bias current, I BIAS     —     VAR . As a result, the variable delay time of the variable delay circuitry  640 A is symmetrically divided into equal parts. However, in some embodiments, the first variable current source  660  and the second variable current source  662  may source and sink different magnitudes of current. Depending upon the magnitude of the variable bias current, I BIAS     —     VAR , the time to charge and discharge the second fixed delay capacitor  664  such that the magnitude of the second delay voltage, V D2 , changes logic state represented by the output voltage, V OUT , at the output buffer stage output  672  may change. 
     The controller  50  ( FIG. 1A ) may be configured to control the programmable delay circuitry  432 A. Accordingly, although not depicted in  FIG. 3A , in some embodiments of the programmable delay circuitry  432 A, the controller  50  may be further configured to control the first variable current source  660  and the second variable current source  662  to set the magnitude of the variable bias current, I BIAS     —     VAR , and thereby the variable delay time provided by the variable delay circuitry  640 A. 
       FIG. 3B  depicts programmable delay circuitry  432 B, which is another embodiment of the programmable delay circuitry. The embodiment of the programmable delay circuitry  432 B, depicted in  FIG. 3B , is similar to the programmable delay circuitry  432 A, depicted in  FIG. 3A , except the embodiment of the variable delay circuitry  640 A, depicted in  FIG. 3A , is replaced by variable delay circuitry  640 B, depicted in  FIG. 3B . 
     As depicted in  FIG. 3B , the programmable delay circuitry  432 B is similar to the programmable delay circuitry  432 A, depicted in  FIG. 3A , except the first variable current source  660 , the second variable current source  662 , and the second fixed delay capacitor  664  are replaced, respectively, with a third fixed current source  674 , a fourth fixed current source  678 , and a variable delay capacitor  680 . In addition, for the sake of clarity, and not by way of limitation, the voltage across the variable delay capacitor  680  is a third delay voltage, V D3 . The variable delay capacitor  680  having a variable delay capacitance C DELAY     —     VAR , where the capacitance value of the variable delay capacitance C DELAY     —     VAR , may be programmatically configured. 
     As discussed relative to the programmable delay circuitry  432 A, the operational parameters of the programmable delay circuitry  432 B may be configured by the controller  50  ( FIG. 1A ). For example, the variable delay capacitor  680  may be a capacitor array or a varactor under the control of the controller  50 . Accordingly, as will be described, the controller  50  may be configured to increase the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  680  in order to increase the delay time provided by the programmable delay circuitry  432 B. Likewise, the controller  50  may be configured to decrease the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  680  to decrease the delay time provided by the programmable delay circuitry  432 B. 
     Continuing with the description of the programmable delay circuitry  432 B, depicted in  FIG. 3B , the function and operation of the fixed delay circuitry  638  of the programmable delay circuitry  432 B, and thereby the fixed delay time provided by the fixed delay circuitry  638 , are substantially the same in the programmable delay circuitry  432 B, depicted in  FIG. 3B . Accordingly, description of the fixed delay circuitry  638  is omitted. 
     As discussed above, the variable delay circuitry  640 B is similar to the variable delay circuitry  640 A except that the variable delay circuitry  640 B replaces the first variable current source  660 , the second variable current source  662 , and the second fixed delay capacitor  664  of the variable delay circuitry  640 A, with the third fixed current source  674 , the fourth fixed current source  678 , and the variable delay capacitor  680 , respectively. Thus, the variable delay circuitry  640 B includes the input stage  654  having the input node  654 A, the second PFET  656 , PFET 2 , the second NFET  658 , NFET 2 , the third fixed current source  674 , the fourth fixed current source  678 , and the variable delay capacitor  680  having a variable delay capacitance, C DELAY     —     VAR , where the controller  50  (not shown) may be configured to change the capacitance value of the variable delay capacitance, C DELAY     —     VAR . 
     Similar to the variable delay circuitry  640 A, the variable delay circuitry  640 B also includes the output buffer stage  666  that includes the third PFET  668 , PFET 3 , and the third NFET  670 , NFET 3 . The output buffer stage  666  includes the input node  666 A formed by coupling the gate of the third PFET  668 , PFET 3 , to the gate of the third NFET  670 , NFET 3 . The source of the third PFET  668 , PFET 3 , is coupled to the circuit supply voltage, V DD . The source of the third NFET  670 , NFET 3 , is coupled to ground. The output buffer stage output  672  of the output buffer stage  666 , which is also the output of the programmable delay circuitry  432 B, is formed by coupling the drain of the third PFET  668 , PFET 3 , to the drain of the third NFET  670 , NFET 3 . The output buffer stage  666  is configured to generate an output voltage, V OUT , at the output buffer stage output  672 . For example, as will be discussed, a third delay voltage, V D3 , across the variable delay capacitor  680  increases and decreases at a rate that depends on the capacitance value of the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  680  and the magnitude of a variable capacitance current, I C     —     VAR , that charges and discharges the variable delay capacitor  680 . When the third delay voltage, V D3 , across the variable delay capacitor  680  is sufficiently low such that the third delay voltage, V D3  is substantially equal to a logic low threshold voltage, the third PFET  668 , PFET 3 , is configured to be in a conducting state and the third NFET  670 , NFET 3 , is configured to be in a non-conducting state. In this case, when the third PFET  668 , PFET 3 , is turned on, the output buffer stage output  672  is coupled to the circuit supply voltage, V DD . As a result, the output voltage, V OUT , at the output buffer stage output  672  is substantially equal to the circuit supply voltage, V DD , when the third PFET  668 , PFET 3 , is in the conducting state. However, when the third delay voltage, V D3 , across the variable delay capacitor  680  is sufficiently high such that the third delay voltage, V D3  is substantially equal to a logic high threshold voltage, the third NFET  670 , NFET 3 , is configured to be in a conducting state and the third PFET  668 , PFET 3 , is configured to be in a non-conducting state. In this case, when the third NFET  670 , NFET 3 , is turned on, the output buffer stage output  672  is coupled to ground. As a result, the output voltage, V OUT , at the output buffer stage output  672  is substantially equal to the ground voltage when the third NFET  670 , NFET 3 , is turned on. In this way, the output voltage, V OUT , at the output buffer stage output  672  toggles between a digital logic high state and a logic log state. 
     Continuing with the description of the variable delay circuitry  640 B, depicted in  FIG. 3B , the variable delay circuitry  640 B includes an input stage  654  having an input node  654 A configured to receive the signal generated by the charging and discharging of the first fixed delay capacitor  652 , where the first fixed delay capacitor  652  has a capacitance value substantially equal to the first fixed delay capacitance, C DELAY1 . The voltage generated across the first fixed delay capacitor  652  is substantially equal to the first delay voltage, V D1 . The input stage  654  is formed by coupling the gate of the second PFET  656 , PFET 2 , and the gate of the second NFET  658 , NFET, to the input node  654 A. The third fixed current source  674  is coupled between the circuit supply voltage, V DD , and the source of the second PFET  656 , PFET 2 . The fourth fixed current source  678  is coupled between the source of the second NFET  658 , NFET 2 , and ground. The variable delay capacitor  680  is coupled between ground and the drain of the second PFET  656 , PFET 2 , and the drain of the second NFET  658 , NFET 2 . 
     During normal operation, when the first delay voltage, V D1 , at the input node  654 A is sufficiently low, the second PFET  656 , PFET 2 , is configured to be in a conducting state. At the same time, when the first delay voltage, V D1 , at the input node  654 A is sufficiently low to turn on the second PFET  656 , PFET 2 , the second NFET  658 , NFET 2 , is configured to be in a non-conducting state. When the second PFET  656 , PFET 2 , is turned on, the third fixed current source  674  sources a second fixed bias current, I BIAS2 , to charge the variable delay capacitor  680 . The second fixed bias current, I BIAS2 , charges the variable delay capacitor  680  with a variable capacitance current, I C     —     VAR . The rate of change in the third delay voltage, V D3 , across the variable delay capacitor  680  depends upon the capacitance value of the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  680  and the magnitude of the variable capacitance current, I-C_VAR. Assuming that most of the second fixed bias current, I BIAS2 , from the third fixed current source  674  is used to charge the variable delay capacitor  680 , the variable capacitance current, I C     —     VAR , is substantially equal to the second fixed bias current, I BIAS2 . As the variable delay capacitor  680  is charged by the second fixed bias current, I BIAS2 , the magnitude of the third delay voltage, V D3 , increases. As described above, after the third delay voltage, V D3 , increases to a logic high threshold voltage, the third PFET  668 , PFET 3 , is turned off and the third NFET  670 , NFET 3 , is turned on, which changes the output voltage, V OUT , at the output buffer stage output  672  to be substantially equal to ground. 
     Otherwise, when the first delay voltage, V D1 , at the input node  654 A is sufficiently high, the second NFET  658 , NFET 2 , is configured to be in a conducting state and the fourth fixed current source  678  is permitted to sink a second fixed bias current, I BIAS2 , in order to discharge the variable delay capacitor  680 . At the same time, when the first delay voltage, V D1 , at the input node  654 A is sufficiently low to turn on the second NFET  658 , NFET 2 , the second PFET  656 , PFET 2 , is configured to be in a non-conducting state. When the second NFET  658 , NFET 2 , is turned on, the fourth fixed current source  678  sinks the second fixed bias current, I BIAS2 , to discharge the variable delay capacitor  680  with a current substantially equal to I C     —     VAR . The rate of change in the third delay voltage, V D3 , across the variable delay capacitor  680  depends upon the capacitance value of the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  680  and the magnitude of the variable capacitance current, I- C     —     VAR . Assuming that most of the second fixed bias current, I BIAS2 , from the fourth fixed current source  678  is used to discharge the variable delay capacitor  680 , the variable capacitance current, I C     —     VAR , is substantially equal to the second fixed bias current, I BIAS2 . As the variable delay capacitor  680  is discharged by the second fixed bias current, I BIAS2 , the magnitude of the third delay voltage, V D3 , decreases. As described above, after the third delay voltage, V D3 , decreases to a logic low threshold voltage, the third NFET  670 , NFET 3 , is turned off and the third PFET  668 , PFET 3 , is turned on, which changes the output voltage, V OUT , at the output buffer stage output  672  to be substantially equal to the circuit supply voltage, V DD . 
     The variable delay time provided by the variable delay circuitry  640 B is created by the time period required to charge and discharge the variable delay capacitor  680 , which depends upon the capacitance value of the variable delay capacitance, C DELAY     —     VAR , and the magnitude of the second fixed bias current, I BIAS2 . Because the variable delay capacitor  680  is either charged or discharged using a current substantially equal to the second fixed bias current, I BIAS2 , either sourced by the third fixed current source  674  or sunk by the fourth fixed current source  678 , the variable time period required for the third delay voltage, V D3 , to increase to the logic high threshold voltage or decrease to the logic high threshold voltage used to trigger the operation of the output buffer stage  666  is dependent upon the variable delay capacitance, C DELAY     —     VAR  of the variable delay capacitor  680 . 
     As previously discussed, the controller  50  ( FIG. 1A ) may be configured to control the programmable delay circuitry  432 B. Accordingly, although not depicted in  FIG. 3B , in some embodiments of the programmable delay circuitry  432 B, the controller  50  may be further configured to control the variable delay capacitance, C DELAY     —     VAR  of the variable delay capacitor  680  in order to change the delay time provided by the programmable delay circuitry  432 B. Assuming that the third fixed current source  674  and the fourth fixed current source  678  respectively source and sink the second fixed bias current, I BIAS2 , where the second fixed bias current, I BIAS2 , is constant, the variable delay capacitor current, I C     —     VAR , will likewise be constant. Consequently, the variable delay time provided by the variable delay circuitry  640 B when charging the variable delay capacitor  680  is substantially equal to the variable delay time provided by the variable delay circuitry  640 B when discharging the variable delay capacitor  680 . In alternative embodiments of the variable delay circuitry  640 B, the third fixed current source  674  and the fourth fixed current source  678  could be configured to source and sink different magnitudes of current. In this case, the variable delay time of the variable delay circuitry  640 B would have a charging period and a discharging period, where the charging period would not equal the discharging period. 
     Programmable Delay Circuitry 
     Programmable delay circuitry, which includes an input buffer circuit and variable delay circuitry, is disclosed. The variable delay circuitry includes an input stage, a correction start voltage circuit, and a variable delay capacitor. The input buffer circuit is coupled to the input stage, the correction start voltage circuit is coupled to the input stage, and the variable delay capacitor is coupled to the input stage. The programmable delay circuitry is configured to provide a fixed time delay and a variable time delay. 
     In one embodiment of the programmable delay circuitry, the correction start voltage circuit helps stabilize the variable time delay by reducing disturbances in a voltage across the variable delay capacitor when certain transistor elements in the programmable delay circuitry transition to be in a conducting state. Further, the correction start voltage circuit may improve accuracy of the variable time delay by reducing transition times of certain transistor elements in the programmable delay circuitry. 
     In one embodiment of the programmable delay circuitry, the programmable delay circuitry further includes a voltage divider circuit and a bias current and mirror circuit. The voltage divider circuit is coupled to the bias current and mirror circuit. The bias current and mirror circuit is coupled to the variable delay circuitry. The voltage divider circuit and the bias current and mirror circuit are configured to reduce changes in the variable time delay due to changes in a voltage level of a circuit supply voltage, which is provided to the programmable delay circuitry. 
       FIG. 4  depicts programmable delay circuitry  432 C, which is another embodiment of the programmable delay circuitry. Although the controller  50  ( FIG. 1A ) is not depicted in  FIG. 4 , it will be understood that the controller  50  ( FIG. 1A ), may be configured to control, configure, align, or change the parameter values and functions of the various circuits and elements to be described as being part of or related to the embodiment of the programmable delay circuitry  432 C, depicted in  FIG. 4 . 
     The programmable delay circuitry  432 C depicted in  FIG. 4  is configured to delay a single digital logic level signal. It will be understood that alternate embodiments may include multiple embodiments of the programmable delay circuitry  432 C arranged in parallel to provide a delay signal path for each of the multiple digital logic level signals to be delayed. 
     In addition, total delay time provided by the programmable delay circuitry  432 C may include a fixed delay time and a variable delay time, where the variable delay time may be configured based on the programmable delay parameter(s), as discussed above. In addition, the fixed delay time may be sub-divided and distributed between an input buffer circuit  682  and variable delay circuitry  684 . 
     As depicted in  FIG. 4 , the programmable delay circuitry  432 C includes an input buffer circuit  682 , a variable delay circuitry  684 , a voltage divider circuit  686 , and a bias current and mirror circuit  688 . The input buffer circuit  682  may include a first input buffer circuit  690  having a first input buffer input  690 A configured to receive an input voltage, V IN , where the input voltage, V IN , is a digital logic level signal. The digital logic signal may have either a digital logic high state or a digital logic low state. The digital logic signal may have either a digital logic high state or a digital logic low state. The first input buffer circuit  690  may include a first PFET  692 , PFET 1 , and a first NFET  694 , NFET 1 . The gate of the first PFET  692 , PFET 1 , and the gate of the first NFET  694 , NFET 1 , may be coupled to form the first input buffer input  690 A of the first input buffer circuit  690 . The source of the first PFET  692 , PFET 1 , may be coupled to the circuit supply voltage, V DD . The source of the first NFET  694 , NFET 1 , may be coupled to ground. The drain of the first PFET  692 , PFET 1 , and the drain of the first NFET  694 , NFET 1 , may be coupled to form a first input buffer output at a first voltage node  696 . 
     The input buffer circuit  682  may further include a second input buffer circuit  698  operably coupled to the first input buffer output at the first voltage node  696 . The second input buffer circuit  698  may include a second PFET  700 , PFET 2 , and a second NFET  702 , NFET 2 . The gate of the second PFET  700 , PFET 2 , and the gate of the second NFET  702 , NFET 2 , may be coupled to the drain of the first PFET  692 , PFET 1 , and the drain of the first NFET  694 , NFET 2 , at the first voltage node  696 . The source of the second PFET  700 , PFET 2 , may be coupled to the circuit supply voltage, V DD . The source of the second NFET  702 , NFET 2 , may be coupled to ground. The drain of the second PFET  700 , PFET 2 , and the drain of the second NFET  702 , NFET 2 , may be coupled to form a second input buffer output at a second voltage node  704 . 
     During operation of the first input buffer circuit  690 , when the input voltage, V IN , at the first input buffer input  690 A is sufficiently low such that the input voltage, V IN  is substantially equal to or less than a logic low threshold voltage, the first PFET  692 , PFET 1 , is configured to be in a conducting state and couples the circuit supply voltage, V DD , to the first voltage node  696 . As a result, the voltage level at the first voltage node  696  is substantially equal to the circuit supply voltage, V DD , and the first input buffer circuit  690  provides an output voltage level representative of a digital logic high state at the first voltage node  696 . In addition, the first NFET  694 , NFET 1 , is configured to be in a non-conducting state when the input voltage, V IN , at the first input buffer input  690 A is sufficiently low such that the input voltage, V IN  is substantially equal to or less than the logic low threshold voltage. 
     However, when the input voltage, V IN , at the first input buffer input  690 A is sufficiently high such that the input voltage, V IN  is substantially equal to or greater than a logic high threshold voltage, the first NFET  694 , NFET 1 , is configured to be in a conducting state and couples the first voltage node  696  to ground. As a result, the voltage level at the first voltage node  696  is substantially equal to ground, and the first input buffer circuit  690  provides an output voltage level representative of a digital logic low state at the first voltage node  696 . In addition, the first PFET  692 , PFET 1 , is configured to be in a non-conducting state when the input voltage, V IN , at the first input buffer input  690 A is sufficiently high such that the input voltage, V IN  is substantially equal to or greater than the logic high threshold voltage. 
     In a similar fashion, the operation of the second input buffer circuit  698  is dependent on the voltage level at the first voltage node  696 , which is coupled to the first input buffer output of the first input buffer circuit  690 . Accordingly, when the first input buffer circuit  690  provides a digital logic low state at the first voltage node  696  such that the voltage level at the first voltage node  696  is substantially equal to or less than the logic low threshold voltage, the second PFET  700 , PFET 2 , is configured to be in a conducting state and couples the circuit supply voltage, V DD , to the second voltage node  704 . As a result, the voltage level at the second input buffer circuit  698  is substantially equal to the circuit supply voltage, V DD , and the second input buffer circuit  698  provides a digital logic high state at the second voltage node  704 . In addition, the second NFET  702 , NFET 2 , is configured to be in a non-conducting state when the first input buffer circuit  690  provides an output voltage level representative of a digital logic low state at the first voltage node  696 . 
     However, in a similar fashion as the operation of the first input buffer circuit  690 , when the first input buffer circuit  690  provides a digital logic high state at the first voltage node  696  such that the voltage level at the first voltage node  696  is substantially equal to or higher than the logic low threshold voltage, the second NFET  702 , NFET 2 , is configured to be in a conducting state and couples the second voltage node  704  to ground. As a result, the voltage level at the second input buffer circuit  698  is substantially equal to the ground voltage, and the second input buffer circuit  698  provides a digital logic low state at the second voltage node  704 . In addition, the second PFET  700 , PFET 2 , is configured to be in a non-conducting state when the first input buffer circuit  690  provides an output voltage level representative of a digital logic high state at the first voltage node  696   
     It will be appreciated that the propagation time of the digital logic level signal, represented by the input voltage, V IN , through the input buffer circuit may be considered as a first portion of a fixed delay provided by the programmable delay circuitry  432 C and is a function of the switching time of the transistors. The first portion of the fixed delay time provided by the input buffer circuit  682  depends upon the switching time of the respective first input buffer circuit  690  and the second input buffer circuit  698 . In some alternative embodiments of the programmable delay circuitry  432 C, additional input buffer circuits, (not depicted in  FIG. 4 ), may be added to the input buffer circuit  682  to increase the first portion of the fixed delay provided by the input buffer circuit  682 . In addition to providing a first portion of the fixed delay time through the programmable delay circuitry  432 C, the combination of the first input buffer circuit  690  and the second input buffer circuit  698 , may also provide the further benefit of isolating analog characteristics of the input voltage, V IN , that represents the digital logic level signal from the variable delay circuitry. In some embodiments of the programmable delay circuitry  432 C, the number of input buffer circuits used to provide isolation between the input voltage, V IN , and the variable delay circuitry  684  may result in improved controllability of the variable delay provided by the variable delay circuitry  684 . 
     The variable delay circuitry  684  includes an input stage  706  including a third PFET  708 , PFET 3 , a third NFET  710 , NFET 3 , a fourth PFET  714 , PFET 4 , a fourth NFET  716 , NFET 4 , a fifth PFET  718 , PFET 5 , and a fifth NFET  720 , NFET 5 . As will be explained, a portion of the input stage  706  of the variable delay circuitry  684  may include a correction start voltage circuit  712  that is formed by the interconnections of the third PFET  708 , PFET 3  and the third NFET  710 , NFET 3 , to the fourth PFET  714 , PFET 4 , and the fourth NFET  716 , NFET 4 . The variable delay circuitry  684  further includes a variable delay capacitor  722 . In some embodiments, the variable delay capacitor  722  may be configured as a programmable capacitor array. 
     As depicted in  FIG. 4 , the variable delay capacitor  722  may be coupled between a third voltage node  724  and ground. The variable delay capacitor  722  is configured to have a variable delay capacitance, C DELAY     —     VAR . In addition, although not depicted in  FIG. 4 , the controller  50  ( FIG. 1A ) may be configured to govern or set various parameters to adjust the capacitance value of the variable delay capacitance, C DELAY     —     VAR , in order to adjust the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684 . For example, in some embodiments of the programmable delay circuitry  432 C, the variable delay capacitor  722  may be configured to couple to the controller  50  (not shown), where the controller  50  is configured to control the capacitance value of the variable delay capacitance, C DELAY     —     VAR . In some embodiments of the programmable delay circuitry  432 C, the variable delay capacitor  722  may be configured to increase as the value of a binary capacitor control word, CNTR_CD, increases, as described relative to  FIG. 7 . 
     For example, in some embodiments of the variable delay circuitry  684 , the variable delay capacitor  722  may be configured as a programmable capacitor array. The programmable capacitor array may include multiple capacitors, where each of the capacitors is arranged in series with a switch element. Each switch element may have a switch state (open or closed) that may be controlled by the controller  50  such that the effective capacitance of the programmable capacitor array has a desired effective capacitance. In some embodiments, the programmable capacitor array may be a linear capacitor array, where each of the capacitors has the same value. In other embodiments, the programmable capacitor array may be a binary weighted capacitor array. The controller  50  may adjust the effective capacitance of the programmable capacitor array by controlling the switch state (open or closed) of each switch to combine different combinations of the multiple capacitors in parallel. Alternatively, the variable delay capacitor  722  may be a programmable varactor configured to be controlled by the controller  50 . Depending on the topology and type of programmable capacitor, for example, the controller  50  may govern the effective capacitance of the programmable varactor by changing the distance between the two parallel plates that form the varactor or a voltage applied across the terminals of the varactor. 
     The variable delay circuitry  684  may further include an output buffer stage  726 . By way of example, and not by way of limitation, the output buffer stage  726  depicted in  FIG. 4  includes only one level of output buffering. Thus, as depicted in  FIG. 4 , the output buffer stage  726  includes a sixth PFET  728 , PFET 6 , and a sixth NFET  730 , NFET 6 , operably coupled to form an output buffer having an output buffer output  732 . The output buffer output  732  is formed by coupling the drain of the sixth PFET  728 , PFET 6 , to the drain of the sixth NFET  730 , NFET 6 . The source of the sixth PFET  728 , PFET 6 , is coupled to the circuit supply voltage, V DD . The source of the sixth NFET  730 , NFET 6  is coupled to ground. 
     However, similar to the input buffer circuit, some alternative embodiments of the variable delay circuitry  684  may include an embodiment of the output buffer stage  726  that includes multiple levels of output buffering in order to provide additional isolation between the interior circuitry of the variable delay circuitry  684  and the digital logic level signal to be generated by the programmable delay circuitry  432 C. For example, some alternative embodiments of the variable delay circuitry  684  may include additional output buffering to improve the drive level at the output of the programmable delay circuitry  432 C. 
     The operation of the output buffer stage  726  depends upon the voltage level at the third voltage node  724 . When the voltage level at the third voltage node  724  is equal to or less than the logic low threshold voltage such that the sixth PFET  728 , PFET 6 , is turned on and in the saturation state, the output buffer output  732  is effectively coupled to the circuit supply voltage, V DD , through the sixth PFET  728 , PFET 6 . Simultaneously, the sixth NFET  730 , NFET 6 , is configured to be turned off when the sixth PFET  728 , PFET 6  is turned on. As a result, the output buffer stage  726  provides an output voltage, V OUT , substantially equal to the circuit supply voltage, V DD , which represents a digital logic high state. Thus, when the voltage level at the third voltage node  724  is equal to or less than the logic low threshold voltage such that the sixth PFET  728 , PFET 6  is turned, the output buffer stage  726  is triggered to transition from a digital logic low state to a digital logic low state at the output buffer output  732 . 
     However, when the voltage level at the third voltage node  724  is equal to or greater than the logic high threshold voltage, such that the sixth NFET  730 , NFET 6 , is turned on and in the saturation state, the output buffer output  732  is effectively coupled to the ground through the sixth NFET  730 , NFET 6 . Simultaneously, the sixth PFET  728 , PFET 6 , is configured to be turned off when the sixth NFET  730 , NFET 6  is turned on. As a result, the output buffer stage  726  provides an output voltage, V OUT , substantially equal to ground, which represents a digital logic low state. Thus, when the voltage level at the third voltage node  724  is equal to or greater than the logic high threshold voltage such that the sixth PFET  728 , PFET 6 , is turned, the output buffer stage  726  is triggered to transition from a digital logic high state to a digital logic low state at the output buffer output  732 . 
     The time period during which the digital logic level signal, represented by the voltage level at the third voltage node  724 , propagates through the output buffer stage  726  may be a second portion of the fixed delay time provided by the programmable delay circuitry  432 C. The second portion of the fixed delay time provided by the output buffer stage  726  depends on the switching time of the output buffer stage  726 . Some alternative embodiments of the variable delay circuitry  684  may include additional output buffering. Accordingly, the propagation time through the output buffer stage of the variable delay circuitry  684  may be increased by addition of additional output buffering. Thus, the fixed delay time of the programmable delay circuitry  432 C includes the first portion of the fixed delay time of the input buffer circuit  682  and the second portion of the fixed delay time of the output buffer stage  726 . 
     Returning to the description of the variable delay circuitry  684  depicted in  FIG. 4 , to form the input stage  706  of the variable delay circuitry  684 , the gate of the fourth PFET  714 , PFET 4 , and the gate of the fourth NFET  716 , NFET 4 , are coupled to the second input buffer output at the second voltage node  704 . The source of the fourth PFET  714 , PFET 4 , is coupled to the drain of the fifth PFET  718 , PFET 5 . The source of the fifth PFET  718 , PFET 5 , is coupled to the circuit supply voltage, V DD . The source of the fourth NFET  716 , NFET 4 , is coupled to the drain of the fifth NFET  720 , NFET 5 . The source of the fifth NFET  720 , NFET 5 , is coupled to ground. As will be described with respect to the operation of the voltage divider circuit  686  and the bias current and mirror circuit  688 , the bias current and mirror circuit  688  is configured to generate a first gate voltage on the gate of the fifth PFET  718 , PFET 5 , such that the fifth PFET  718 , PFET 5 , is configured to provide a first bias current, I BIAS     —     1 , when the fourth PFET  714 , PFET 4 , is turned on. Similarly, the bias current and mirror circuit  688  is further configured to generate a second gate voltage on the gate of the fifth NFET  720 , NFET 5 , such that the fifth NFET  720 , NFET 5 , is configured to sink a second bias current, I BIAS     —     2 , when the fourth NFET  716 , NFET 4 , is turned on. The drain of the fourth PFET  714 , PFET 4 , is coupled to the drain of the fourth NFET  716 , NFET 4 , to provide an input stage output at the third voltage node  724 . The variable delay capacitor  722  is coupled between the third voltage node  724  and ground. As a result, the variable delay capacitor  722  is coupled to the drain of the fourth PFET  714 , PFET 4 , the drain of the fourth NFET  716 , NFET 4 , the gate of the sixth PFET  728 , PFET 6 , and the gate of the sixth NFET  730 , NFET 6 . The fourth PFET  714 , PFET 4 , and the fourth NFET  716 , NFET 4 , are configured such that when the fourth PFET  714 , PFET 4 , is in a conducting mode of operation (ON), the fourth NFET  716 , NFET 4 , is in a non-conducting mode (OFF). Likewise, the fourth PFET  714 , PFET 4 , and the fourth NFET  716 , NFET 4 , are configured such that when the fourth NFET  716 , NFET 4 , is in a conducting mode (ON) of operation, the fourth PFET  714 , PFET 4 , is in a non-conducting mode (OFF). 
     Accordingly, the fixed delay time of the programmable delay circuitry  432 C may further include a third portion of the fixed delay time, where the third portion of the fixed delay time is associated with the switching time of the fourth PFET  714 , PFET 4 , and the switching time of the fourth NFET  716 , NFET 4 . 
     As a result, when the voltage level on the second voltage node  704  is substantially equal to or less than the logic low threshold voltage such that the fourth PFET  714 , PFET 4 , is in the conducting mode of operation (ON), the first bias current, I BIAS     —     1 , passes through the fourth PFET  714 , PFET 4 , pushes charge into the variable delay capacitor  722  to charge the variable delay capacitor  722 . As the variable delay capacitor  722  is charged, the voltage across the variable delay capacitor  722 , which is substantially equal to the voltage level on the third voltage node  724 , increases. However, when the voltage level on the second voltage node  704  is substantially equal to or greater than the logic high threshold voltage such that the fourth NFET  716 , NFET 4 , is in the conducting mode of operation (ON), the second bias current, I BIAS     —     2 , sunk by the fifth NFET  720 , NFET 5 , passes through the fourth NFET  716 , NFET 4 , and pulls charge from the variable delay capacitor  722  to discharge the variable delay capacitor  722 . As a result, the voltage across the variable delay capacitor  722 , which is substantially equal to the voltage level on the third voltage node  724 , falls. 
     The correction start voltage circuit  712  is formed by coupling the gate of the third PFET  708 , PFET 3  and the gate of the third NFET  710 , NFET 3 , to the second voltage node  704 , such that the gates of the third PFET  708 , PFET 3 , the third NFET  710 , NFET 3 , the fourth PFET  714 , PFET 4 , and the fourth NFET  716 , NFET 4 , are coupled. The source of the third PFET  708 , PFET 3 , is coupled to the circuit supply voltage, V DD . The drain of the third PFET  708 , PFET 3 , is coupled to the source of the fourth NFET  716 , NFET 4 , and the drain of the fifth NFET  720 , NFET 5 . The source of the third NFET  710 , NFET 3 , is coupled to ground. The drain of the third NFET  710 , NFET 3 , is coupled to the source of the fourth PFET  714 , PFET 4 , and the drain of the fifth PFET  718 , PFET 5 . 
     The correction start voltage circuit  712  is configured to provide a first known voltage level at the source of the fourth PFET  714 , PFET 4 , while the fourth PFET  714 , PFET 4 , is in the non-conducting state such that the voltage level present at the source of the fourth PFET  714 , PFET 4 , is at the first known voltage level at the moment the fourth PFET  714 , PFET 4  transitions from the non-conducting state to the conducting state. In order to provide the first known voltage level at the source of the fourth PFET  714 , PFET 4 , while the fourth PFET  714 , PFET 4 , is in the non-conducting state, the third NFET  710 , NFET 3 , is configured to be turned on when the while the fourth PFET  714 , PFET 4 , is in the non-conducting state. As a result, the source of the fourth PFET  714 , PFET 4 , is coupled to ground through the third NFET  710 , NFET 3 . In the embodiment of the correction start voltage circuit  712  depicted in  FIG. 4 , the first known voltage is substantially equal to ground. However, in alternative embodiments, the source of the third NFET  710 , NFET 3  may be coupled to a voltage level other than ground such that the first known voltage is not substantially equal to ground. As an example, in some embodiments, the correction start voltage circuit  712  may be configured such that the first known voltage is substantially equal to one half the circuit supply voltage, V DD /2. 
     In some embodiments of the correction start voltage circuit  712 , the parasitic capacitance of the source of the fourth PFET  714 , PFET 4 , the parasitic capacitance of the drain of the fifth PFET  718 , PFET 5 , and/or a combination thereof is configured such that the voltage level present on the source of the fourth PFET  714 , PFET 4 , remains at the first known voltage level momentarily at the moment the fourth PFET  714 , PFET 4  transitions from the non-conducting state to the conducting state. In other embodiments of the correction start voltage circuit  712 , the parasitic capacitance of the drain of the third NFET  710 , NFET 3 , may also be configured to improve the ability of the correction start voltage circuit  712  to provide the first known voltage on the source of the fourth PFET  714 , PFET 4 , momentarily at the moment the fourth PFET  714 , PFET 4 , transitions from the non-conducting state to the conducting state. In addition, the third NFET  710 , NFET 3  may be further configured to turn off just prior to or coincidentally with the fourth PFET  714 , PFET 4 , transitioning from the non-conducting state to the conducting state. Otherwise, after the charge present in the parasitic capacitance(s) is discharged, the voltage level on the source of the fourth PFET  714 , PFET 4 , is determined by the operational state of the fourth PFET  714 , PFET 4 , and the first bias current, I BIAS     —     1 , provided by the fifth PFET  718 , PFET 5 . 
     In a similar fashion, the correction start voltage circuit  712  is configured to provide a second known voltage level at the source of the fourth NFET  716 , NFET 4 , while the fourth NFET  716 , NFET 4 , is in the non-conducting state such that the voltage level present at the source of the fourth NFET  716 , NFET 4 , is at the second known voltage level at the moment the fourth NFET  716 , NFET 4  transitions from the non-conducting state to the conducting state. In order to provide the second known voltage level at the source of the fourth NFET  716 , NFET 4 , while the fourth NFET  716 , NFET 4 , is in the non-conducting state, the third PFET  708 , PFET 3 , is configured to be turned on when the fourth NFET  716 , NFET 4 , is in the non-conducting state. As a result, the source of the fourth NFET  716 , NFET 4 , is coupled through the third PFET  708 , PFET 3 , to the circuit supply voltage V DD . As a result, in the embodiment of the correction start voltage circuit  712  depicted in  FIG. 4 , the second known voltage is substantially equal to the circuit supply voltage, V DD . However, in alternative embodiments, the source of the third PFET  708 , PFET 3 .may be coupled to a voltage level other than the circuit supply voltage, V DD , such that the second known voltage is not substantially equal to the circuit supply voltage, V DD . As an example, in some embodiments, the correction start voltage circuit  712  may be configured such that the second known voltage is substantially equal to one half the circuit supply voltage, V DD /2. 
     In some embodiments of the correction start voltage circuit  712 , the parasitic capacitance of the source of the fourth NFET  716 , NFET 4 , the parasitic capacitance of the drain of the fifth NFET  720 , NFET 5 , and/or a combination thereof is configured such that the voltage level present on the source of the fourth NFET  716 , NFET 4 , remains at the second known voltage level momentarily at the moment the fourth NFET  716 , NFET 4  transitions from the non-conducting state to the conducting state. In other embodiments of the correction start voltage circuit  712 , the parasitic capacitance of the drain of the third PFET  708 , PFET 3 , may also be configured to improve the ability of the correction start voltage circuit  712  to provide the second known voltage on the source of the fourth NFET  716 , NFET 4 , momentarily at the moment the fourth NFET  716 , NFET 4 , transitions from the non-conducting state to the conducting state. In addition, the third PFET  708 , PFET 3  may be further configured to turn off just prior to or coincidentally with the fourth NFET  716 , NFET 4 , transitioning from the non-conducting state to the conducting state. Otherwise, after the charge present in the parasitic capacitance(s) is discharged, the voltage level on the source of the fourth NFET  716 , NFET 4 , is determined by the operational state of the fourth NFET  716 , NFET 4 , and the second bias current, I BIAS     —     2 , sunk by the fifth NFET  720 , NFET 5 . 
     Advantageously, because the correction start voltage circuit  712  is configured to ensure the voltage level on the source of the fourth PFET  714 , PFET 4 , is substantially equal to the first known voltage when the fourth PFET  714 , PFET 4 , is in the non-conducting state and the voltage level on the source of the fourth NFET  716 , NFET 4 , is substantially equal to the second known voltage when the fourth NFET  716 , NFET 4 , is in the non-conducting state, the initial change in the voltage level at the third voltage node  724  that occurs as a result of charge stored in the capacitances associated with the source of the fourth PFET  714 , PFET 4 , or the charge stored in the capacitances associated with the source of the fourth NFET  716 , NFET 4 , (referred to as a state transition voltage charge) is predictable and substantially consistent. As a result, the state transition voltage charge may be controlled such that the voltage across the variable delay capacitor  722  is not substantially disturbed when either the fourth PFET  714 , PFET 4 , or the fourth NFET  716 , NFET 4 , transitions to be in the conducting state. 
     For example, as previously described, when the second input buffer circuit  698  provides a digital logic high state, the second input buffer circuit  698  provides an output voltage at the second voltage node  704  substantially equal to the circuit supply voltage, V DD . In this case, the gate of the fourth NFET  716 , NFET 4 , is greater than the logic high threshold level. As a result, the fourth NFET  716 , NFET 4 , turns on and discharges the variable delay capacitor  722  until the voltage level at the third voltage node  724  is substantially equal to ground. In addition, the third NFET  710 , NFET 3 , of the correction start voltage circuit  712  is configured to turn on and couple the source of the fourth PFET  714 , PFET 4 , to ground such that the charge stored on the source of the fourth PFET  714 , PFET- 4 , is at a voltage level substantially equal to ground. As a result, the charge stored on the source of the fourth PFET  714 , PFET 4 , minimally affects the charging period, ΔT CHARGING     —     PERIOD , of the variable delay circuitry  684 , where the charging period, ΔT CHARGING     —     PERIOD , is a period of time during which the variable delay capacitor  722  is being charged until the third voltage node  724  is equal to or exceeds the logic high threshold voltage of the output buffer stage  726 . 
     Similarly, when the second input buffer circuit  698  provides a digital logic low state, the second input buffer provides an output voltage at the second voltage node  704  substantially equal to ground. In this case, the gate of the fourth PFET  714 , PFET 4 , is less than the logic low threshold level. As a result, the fourth PFET  714 , PFET 4 , turns on and charges the variable delay capacitor  722  until the voltage level at the third voltage node  724  is substantially equal to the circuit supply voltage, V DD . In addition, the third PFET  708 , PFET 3 , of the correction start voltage circuit  712  is configured to turn on and couple the source of the fourth NFET  716 , NFET 4 , to the circuit supply voltage, V DD , such that the charge stored on the source of the fourth NFET  716 , NFET 4 , is at a voltage level substantially equal to ground. As a result, the charge stored on the source of the fourth NFET  716 , NFET 4 , minimally affects the charging period, ΔT CHARGING     —     PERIOD , of the variable delay circuitry  684 , where the charging period, ΔT CHARGING     —     PERIOD , is a period of time during which the variable delay capacitor  722  is being discharged until the third voltage node  724  is equal to or less than the logic low threshold voltage of the output buffer stage  726 . 
     Otherwise, if the correction start voltage circuit  712  is not present, the source of the fourth PFET  714 , PFET 4 , and the source of the fourth NFET  716 , NFET 4 , will each tend to float to an undetermined voltage level when either the fourth PFET  714 , PFET 4 , or the fourth NFET  716 , NFET 4 , are in the non-conducting state. As a result, state transition voltage change is unpredictable. 
     The operation of the output buffer stage  726  depends upon the voltage level at the third voltage node  724 . When the voltage level at the third voltage node  724  is equal to or less than the logic low threshold voltage such that the sixth PFET  728 , PFET 6  is turned on and in the saturation state, the output buffer output  732  is effectively coupled to the circuit supply voltage, V DD , through the sixth PFET  728 , PFET 6 . Simultaneously, the sixth NFET  730 , NFET 6 , is configured to be turned off when the sixth PFET  728 , PFET 6  is turned on. As a result, the output buffer stage  726  provides an output voltage, V OUT , substantially equal to the circuit supply voltage, V DD , which represents a digital logic high state. 
     However, when the voltage level at the third voltage node  724  is equal to or greater than the logic high threshold voltage such that the sixth NFET  730 , NFET 6  is turned on and in the saturation state, the output buffer output  732  is effectively coupled to the ground through the sixth NFET  730 , NFET 6 . Simultaneously, the sixth PFET  728 , PFET 6 , is configured to be turned off when the sixth NFET  730 , NFET 6  is turned on. As a result, the output buffer stage  726  provides an output voltage, V OUT , substantially equal to ground, which represents a digital logic low state. 
     The variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684  is a function of a charging period, ΔT CHARGING     —     PERIOD  and a discharging period, ΔT DISCHARGING     —     PERIOD , of the variable delay capacitor  722 . The charging period, ΔT CHARGING     —     PERIOD , is a period of time during which the variable delay capacitor  722  is being charged until the third voltage node  724  is equal to or exceeds the logic high threshold voltage. During the charging period, ΔT CHARGING     —     PERIOD , the change in the voltage across the variable delay capacitor  722 , necessary to change the digital logic state at the input of the output buffer stage  726 , is the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING . The discharging period, ΔT DISCHARGING     —     PERIOD , is a period of time during which the variable delay capacitor  722  is being charged until the third voltage node  724  is equal to or exceeds the logic high threshold voltage. During the discharging period, ΔT DISCHARGING     —     PERIOD , the change in the voltage across the variable delay capacitor  722 , necessary to change the digital logic state at the input of the output buffer stage  726 , is the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING . 
     The average variable delay time, T AVERAGE     —     VARIABLE     —     DELAY , provided by the variable delay circuitry  684  is provided by equation (1): 
     
       
         
           
             
               
                 
                   
                     T 
                     
                       AVERAGE_VARIABLE 
                       ⁢ 
                       _DELAY 
                     
                   
                   = 
                   
                     
                       
                         
                           T 
                           CHARGING_PERIOD 
                         
                         + 
                         
                           T 
                           DISCHARGING_PERIOD 
                         
                       
                       2 
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     The charging period, ΔT CHARGING     —     PERIOD , of the variable delay capacitor  722  is dependent upon the capacitance value of the variable delay capacitance, C DELAY     —     VAR , and the magnitude of the variable delay capacitor current, I C     —     VAR , where the magnitude of the variable delay capacitor current, I C     —     VAR , is substantially equal to the first bias current, I BIAS     —     1  during the charging period, ΔT CHARGING     —     PERIOD . Similarly, the discharging period, ΔT DISCHARGING     —     PERIOD , of the variable delay capacitor  722  is dependent upon the capacitance value of the variable delay capacitance, C DELAY     —     VAR , and the magnitude of the variable delay capacitor current, I C     —     VAR , where the magnitude of the variable delay capacitor current, I C     —     VAR , is substantially equal to the second bias current, I- BIAS     —     2  during the discharging period, ΔT DISCHARGING     —     PERIOD . 
     During the charging period, ΔT CHARGING     —     PERIOD , the variable delay capacitor current, I C     —     VAR , is given by equation (2): 
     
       
         
           
             
               
                 
                   
                     I 
                     C_VAR 
                   
                   = 
                   
                     
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         V 
                         
                           DELAY_VAR 
                           ⁢ 
                           _CAP 
                           ⁢ 
                           _CHARGING 
                         
                       
                       × 
                       
                         C 
                         DELAY_VAR 
                       
                     
                     
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         T 
                         CHARGING_PERIOD 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
           
         
       
     
     Similarly, during the discharging period, ΔT DISCHARGING     —     PERIOD , the variable delay capacitor current, I C     —     VAR , is given by equation (3) as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     C_VAR 
                   
                   = 
                   
                     
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         V 
                         
                           DELAY_VAR 
                           ⁢ 
                           _CAP 
                           ⁢ 
                           _DISCHARGING 
                         
                       
                       × 
                       
                         C 
                         DELAY_VAR 
                       
                     
                     
                       Δ 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         T 
                         DISCHARGING_PERIOD 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     Assuming the variable delay capacitor current, I C     —     VAR , is substantially equal to the first bias current, I BIAS     —     1 , provided by the fifth PFET  718 , PFET 5 , during the charging period, ΔT CHARGING     —     PERIOD , the charging period, ΔT CHARGING     —     PERIOD , is given by equation (4) as follows: 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       T 
                       CHARGING_PERIOD 
                     
                   
                   = 
                   
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           V 
                           
                             DELAY_VAR 
                             ⁢ 
                             _CAP 
                             ⁢ 
                             _CHARGING 
                           
                         
                         × 
                         
                           C 
                           DELAY_VAR 
                         
                       
                       
                         I 
                         
                           BIAS_ 
                           ⁢ 
                           1 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Likewise, assuming the magnitude of the variable delay capacitor current, I C     —     VAR , is substantially equal to the second bias current, I BIAS     —     2 , sunk by the fifth NFET  720 , NFET 5 , during the discharging period, ΔT DISCHARGING     —     PERIOD , the discharging period, ΔT DISCHARGING     —     PERIOD , is given by equation (5): 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       T 
                       DISCHARGING_PERIOD 
                     
                   
                   = 
                   
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           V 
                           
                             DELAY_VAR 
                             ⁢ 
                             _CAP 
                             ⁢ 
                             _DISCHARGING 
                           
                         
                         × 
                         
                           C 
                           DELAY_VAR 
                         
                       
                       
                         I 
                         
                           
                             BIAS 
                             ⁢ 
                             _ 
                           
                           ⁢ 
                           2 
                         
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
           
         
       
     
     In some embodiments of the programmable delay circuitry  432 C the channel width of the fifth PFET  718 , PFET 5 , and the channel width of the fifth NFET  720 , NFET 5 , are configured such that the first bias current, I BIAS     —     1 , is substantially equal to the second bias current, I BIAS     —     2 , where the magnitude of the first bias current, I BIAS     —     1 , and the magnitude of the second bias current, I BIAS     —     2 , are substantially equal to a bias current, I BIAS . 
     Some embodiments of the output buffer stage  726  may be configured such that the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , is substantially equal to the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING . For example, in some embodiments, the output buffer stage  726  logic low threshold voltage and a logic high threshold are configured such that the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , is substantially equal to the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING . In the case where the magnitude of the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , is substantially equal to the magnitude of the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING , such that the magnitude of the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , and the magnitude of the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING , are substantially equal to a transition voltage change, Δ DELAY     —     VAR     —     CAP     —     TRANSITION , the variable delay time, T VARIABLE     —     DELAY     —     TIME , of the variable delay circuitry  684  is given by equation (6): 
     
       
         
           
             
               
                 
                   
                     Δ 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       T 
                       
                         
                           VARIABLE 
                           ⁢ 
                           _ 
                           ⁢ 
                           DELAY 
                         
                         ⁢ 
                         _TIME 
                       
                     
                   
                   = 
                   
                     
                       
                         Δ 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           V 
                           
                             DELAY_VAR 
                             ⁢ 
                             _CAP 
                             ⁢ 
                             _TRANSITION 
                           
                         
                         × 
                         
                           C 
                           DELAY_VAR 
                         
                       
                       
                         I 
                         BIAS 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     In other embodiments of the programmable delay circuitry  432 C, the channel width of the fifth PFET  718 , PFET 5 , and the channel width of the fifth NFET  720 , NFET 5 , may be configured such that the first bias current, I BIAS     —     1 , is not substantially equal to the second bias current, I BIAS     —     2 . In this case, the charging period, ΔT CHARGING     —     PERIOD , and the discharging period, ΔT DISHARGING     —     PERIOD , may not be substantially equal. As an example, in some embodiments, the charging period, ΔT CHARGING     —     PERIOD , is longer than the discharging period, ΔT DISHARGING     —     PERIOD . In other embodiments, the charging period, ΔT CHARGING     —     PERIOD , is less than the discharging period, ΔT DISHARGING     —     PERIOD . 
     As an alternative embodiment, the logic low threshold voltage and the logic high threshold of the output buffer stage  726  may be configured such the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , is substantially equal to the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING . 
     In addition, as discussed above, in some embodiments of the programmable delay circuitry  432 C, the controller  50  ( FIG. 1A ) may be coupled to the variable delay capacitor  722 . The controller  50  may be configured to control the capacitance value of the variable delay capacitance, C DELAY     —     VAR , based on a binary capacitor control word, CNTR_CD, such that as the value of the binary capacitor control word, CNTR_CD increases, the variable delay capacitance, C DELAY     —     VAR , linearly increases or decreases in a substantially linear fashion. In some alternative embodiments of the variable delay capacitor  722 , the variable delay capacitance, C DELAY     —     VAR , has a minimum capacitance value, C DELAY     —     VAR     —     MIN , that corresponds to the minimum delay provided by charging and discharging of the variable delay capacitor  722  of the variable delay circuitry  684 . As an example, the minimum capacitance value, C DELAY     —     VAR     —     MIN , of the variable delay capacitor  722  may be provided by a fixed capacitance (not depicted) in parallel with a programmable binary capacitor array. An example of a programmable binary capacitor array is depicted in  FIG. 7 . 
     Furthermore, as discussed above, in some embodiments of the programmable delay circuitry  432 C, the controller  50  ( FIG. 1A ), may be configured to control the capacitance value of the variable delay capacitance, C DELAY     —     VAR , based on a binary capacitor control word, CNTR_CD, such that as the value of the binary capacitor control word, CNTR_CD increases, the variable delay capacitance, C DELAY     —     VAR , linearly increases or decreases in a substantially linear fashion. As a result, the variable delay circuitry  684  may be configured such that the variable delay time, T VARIABLE     —     DELAY     —     TIME , increases in a substantially linear fashion as the variable delay capacitance, C DELAY     —     VAR , increases in a substantially linear fashion. In addition, the delay step size, Δ VARIABLE     —     DELAY     —     TIME , of the variable delay circuitry  684  between any two adjacent values of the variable delay capacitance, C DELAY     —     VAR , may be substantially equal. 
     Because the first input buffer circuit  690 , the second input buffer circuit  698 , the input stage  706  of the variable delay circuitry  684 , the correction start voltage circuit  712 , and the output buffer stage  726  are substantially symmetric in construction, the first input buffer circuit  690 , the second input buffer circuit  698 , the input stage  706  of the variable delay circuitry  684 , the correction start voltage circuit  712 , and the output buffer stage  726  may be configured such that the logic low threshold voltage and the logic high threshold voltage tend to proportionally track the circuit supply voltage, V DD . As a result, the magnitude of the charging voltage change, Δ DELAY     —     VAR     —     CAP     —     CHARGING , and the magnitude of the discharging voltage change, Δ DELAY     —     VAR     —     CAP     —     DISCHARGING , will also tend to proportionally track the circuit supply voltage, V DD . However, the variations in the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684  due to changes in the voltage level of the circuit supply voltage, V DD , may be minimized by configuring the programmable delay circuitry  432 C such that the magnitude of the first bias current, I BIAS     —     1 , and the magnitude of the second bias current, I BIAS     —     2 , change proportionally with respect to a change in the voltage level of the circuit supply voltage, V DD . 
     As an example, the voltage divider circuit  686  and bias current and mirror circuit  688  may be configured such that the first bias current, I BIAS     —     1 , provided by the fifth PFET  718 , PFET 5 , and the second bias current, I BIAS     —     2 , sunk by the fifth NFET  720 , NFET 5 , are related to the voltage level of the circuit supply voltage, V DD , such that the variations in the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684  due to changes in the voltage level of the circuit supply voltage, V DD , may be minimized. 
     The bias current and mirror circuit  688  includes a seventh PFET  734 , PFET 7 , a seventh NFET  736 , NFET 7 , an eighth PFET  738 , PFET 8 , an eighth NFET  740 , PFET 9 , a bias reference current setting resistor  744 , and a bias resistor  746 . The bias reference current setting resistor  744  has a bias reference current setting resistance, R 3 . The bias resistor  746  has a bias resistance, R 4 . 
     The source of the seventh PFET  734 , PFET 7 , is coupled to the circuit supply voltage, V DD . The gate of the seventh PFET  734 , PFET 7 , is coupled to the source of the seventh PFET  734 , PFET 7 , and the drain of the eighth NFET  740 , NFET 8 . In addition, the gate and drain of the seventh PFET  734 , PFET 7 , is coupled to the gate of the fifth PFET  718 , PFET 5 . 
     The gate and drain of the seventh PFET  734 , PFET 7 , is coupled to the drain of the eighth NFET  740 , NFET 8 , The source of the eighth NFET  740 , NFET 8 , is coupled to the drain of the seventh NFET  736 , NFET 7 . The sources of the eighth NFET  740 , NFET 8 , and the seventh NFET  736 , NFET 7 , are coupled to ground. The gate of the seventh NFET  736 , NFET 7 , is coupled to the drain and gate of the ninth NFET  742 , NFET 9 . In addition, the gate of the seventh NFET  736 , NFET 7 , and the gate and drain of the ninth NFET  742 , NFET 9 , are coupled to the gate of the fifth NFET  720 , NFET 5 , of the variable delay circuitry  684 . 
     The bias reference current setting resistor  744  is coupled between the circuit supply voltage, V DD , and the source of the eighth PFET  738 , PFET 8 . The bias resistor  746  is coupled between the drain of the eighth PFET  738 , PFET 8 , and the drain and gate of the ninth NFET  742 , NFET 9 , and the gate of the seventh NFET  736 , NFET 7 . 
     The voltage divider circuit  686  includes a first voltage divider resistor  748 , a tenth PFET  750 , PFET 10 , an eleventh PFET  752 , PFET 11 , and a second voltage divider resistor  754 . The first voltage divider resistor  748  has a first voltage divider resistance, R 1 . The second voltage divider resistor  754  has a second voltage divider resistance, R 2 . The first voltage divider resistance, R 1 , of the first voltage divider resistor  748  is substantially equal to the second voltage divider resistance, R 2 , of the second voltage divider resistor  754 . 
     The first voltage divider resistor  748  is coupled between the circuit supply voltage, V DD , and the source of the tenth PFET  750 , PFET 10 . The gate of the tenth PFET  750 , PFET 10 , is coupled to the drain of the tenth PFET  750 , PFET 10  and the source of the eleventh PFET  752 , PFET 11 . The gate of the eleventh PFET  752 , PFET 11 , is coupled to the drain of the eleventh PFET  752 , PFET 11 . The second voltage divider resistor  754  is coupled between the drain of the eleventh PFET  752 , PFET 11 , and ground. Because the gate of the tenth PFET  750 , PFET 10 , is coupled to the drain of the tenth PFET  750 , PFET 10 , and the gate of the eleventh PFET  752 , PFET 11 , is coupled to the drain of the eleventh PFET  752 , PFET 11 , both the tenth PFET  750 , PFET 10 , and the eleventh PFET  752 , PFET 11 , are biased to be on in a saturation mode of operation. The source-to-drain voltage across the tenth PFET  750 , PFET 10 , and the source-to-drain voltage across the eleventh PFET  752 , PFET 11 , are substantially equal. Because the first voltage divider resistance, R 1 , of the first voltage divider resistor  748  is substantially equal to the second voltage divider resistance, R 2 , of the second voltage divider resistor  754 , the voltage divider circuit  686  may be configured to set a bias voltage substantially equal to one-half of the circuit supply voltage, V DD , on the drain of the tenth PFET  750 , PFET 10 , and the source of the eleventh PFET  752 , PFET 11 . 
     The operation of the bias current and mirror circuit  688  is now explained with reference to the voltage divider circuit  686 . The bias current and mirror circuit  688  is coupled to the voltage divider circuit  686  by coupling the gate of the eighth PFET  738 , PFET 8 , to the gate and drain of the eleventh PFET  752 , PFET 11 . The eighth PFET  738 , PFET 8 , of the bias current and mirror circuit  688  and the eleventh PFET  752 , PFET 11 , of the voltage divider circuit  686  are configured such that the gate-to-source voltage of the eighth PFET  738 , PFET 8 , is substantially equal to the gate-to-source voltage of the eleventh PFET  752 , PFET 11 . As a result, the voltage on the source of the eighth PFET  738 , PFET 8 , is substantially equal to the voltage on the source of the eleventh PFET  752 , PFET 11 . As discussed above with respect to the operation of the voltage divider circuit  686 , the voltage on the source of the eleventh PFET  752 , PFET 11 , is substantially equal to V DD /2. Accordingly, the voltage on the source of the eighth PFET  738 , PFET 8 , is also substantially equal to V DD /2. The current through the bias reference current setting resistor  744 , which is the bias reference current, I BIAS     —     REF , is provided by equation (7) as follows: 
     
       
         
           
             
               
                 
                   
                     I 
                     BIAS_REF 
                   
                   = 
                   
                     
                       
                         
                           V 
                           DD 
                         
                         - 
                         
                           
                             V 
                             DD 
                           
                           2 
                         
                       
                       
                         R 
                         3 
                       
                     
                     = 
                     
                       
                         V 
                         DD 
                       
                       
                         2 
                         × 
                         
                           R 
                           3 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     Accordingly, the drain-to-source current of the ninth NFET  742 , NFET 9 , is substantially equal to I BIAS     —     REF . Because the gate and drain of the ninth NFET  742 , NFET 9 , are coupled to the gate of the seventh NFET  736 , NFET 7 , and the gate of the fifth NFET  720 , NFET 5 , the source- to-drain current flowing through the ninth NFET  742 , NFET 9 , is mirrored such that the drain-to-source current flowing through the seventh NFET  736 , NFET 7 , and the drain-to-source current flowing through the fifth NFET  720 , NFET 5 , are proportional to the drain-to-source current flowing through the ninth NFET  742 , NFET 9 . Furthermore, the source-to-drain current flowing through the seventh PFET  734 , PFET 7 , is substantially equal to the drain-to-source current flowing through the seventh NFET  736 , NFET 7 . Because the gate-to-source voltage of the fifth PFET  718 , PFET 5 , is substantially equal to the gate voltage of the seventh PFET  734 , PFET 7 , the source-to-drain current of the seventh PFET  734 , PFET 7 , is proportional to the bias reference current, I BIAS     —     REF , where the bias reference current setting resistance, R 3 , of the bias reference current setting resistor  744  sets the bias reference current, I BIAS     —     REF . As a result, the first bias current, I BIAS     —     1 , proportionally tracks the circuit supply voltage, V DD . Similarly, the second bias current, I BIAS     —     2 , proportionally tracks the circuit supply voltage, V DD . 
     Accordingly, the bias reference current setting resistance, R 3 , resistance value may be configured to minimize the sensitivity of the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684  to a change in the voltage level of the circuit supply voltage, V DD . In addition, in some embodiments, the channel width ratios of the channel width of the ninth NFET  742 , NFET 9 , to each of the channel widths of the seventh PFET  734 , PFET 7 , the seventh NFET  736 , NFET 7 , the fifth PFET  718 , PFET 5  and the fifth NFET  720 , NFET 5 , may be configured to minimize the sensitivity of the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the variable delay circuitry  684  due to changes in the voltage level of the circuit supply voltage, V DD . 
       FIG. 7  depicts an example embodiment of the variable delay capacitor  722 , depicted in  FIG. 4 , as variable delay capacitor  722 A. The variable delay capacitor  722 A may be configured as a programmable capacitor array  758 . The programmable capacitor array  758  may be coupled to the controller  50  via a variable capacitance control bus  760 , CNTR_CD (5:1). The variable delay capacitor  722 A has a variable delay capacitance, C DELAY     —     VAR . The controller  50  may be configured to control the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  722 A by configuring the programmable capacitor array  758 . 
     The variable capacitance control bus  760 , CNTR_CD (5:1), may include a first capacitor control signal  762 , CNTR_CD 1 , a second capacitor control signal  764 , CNTR_CD 2 , a third capacitor control signal  766 , CNTR_CD 3 , a fourth capacitor control signal  768 , CNTR_CD 4 , and a fifth capacitor control signal  770 , CNTR_CD 5 . 
     The programmable capacitor array  758  may include a first array capacitor  772 , a second array capacitor  774 , a third array capacitor  776 , a fourth array capacitor  778 , and a fifth array capacitor  780 . The first array capacitor  772  may have a capacitance substantially equal to a first array capacitor capacitance, C D1 . The second array capacitor  774  may have a capacitance substantially equal to a second array capacitor capacitance, C D2 . The third array capacitor  776  may have a capacitance substantially equal to a third array capacitor capacitance, C D3 . The fourth array capacitor  778  may have a capacitance substantially equal to a fourth array capacitor capacitance, C D4 . The fifth array capacitor  780  may have a capacitance substantially equal to a fifth array capacitor capacitance, C D5 . 
     In addition, the programmable capacitor array  758  may further include a first switch element  782 , NFET 11 , a second switch element  784 , NFET 12 , a third switch element  786 , NFET 13 , a fourth switch element  788 , NFET 14 , and a fifth switch element  790 , NFET 15 . In  FIG. 7 , by way of example and not by way of limitation, the first switch element  782 , NFET 11 , the second switch element  784 , NFET 12 , the third switch element  786 , NFET 13 , the fourth switch element  788 , NFET 14 , and the fifth switch element  790 , NFET 15  are each depicted as NFET devices. 
     The programmable capacitor array  758  includes a first programmable capacitance  792 , a second programmable capacitance  794 , a third programmable capacitance  796 , a fourth programmable capacitance  798 , and a fifth programmable capacitance  800 . The first programmable capacitance  792  may be formed by coupling the first array capacitor  772  between the third voltage node  724  and the drain of the first switch element  782 , NFET 11 , where the source of the first switch element  782 , NFET 11 , is coupled to ground and the gate of the first switch element  782 , NFET 11 , is coupled to the first capacitor control signal  762 , CNTR_CD 1 , of the variable capacitance control bus  760 , CNTR_CD (5:1). The second programmable capacitance  794  may be formed by coupling the second array capacitor  774  between the third voltage node  724  and the drain of the second switch element  784 , NFET 12 , where the source of the second switch element  784 , NFET 12 , is coupled to ground and the gate of second switch element  784 , NFET 12 , is coupled to the second capacitor control signal  764 , CNTR_CD 2 , of the variable capacitance control bus  760 , CNTR_CD (5:1). The third programmable capacitance  796  may be formed by coupling the third array capacitor  776  between the third voltage node  724  and the drain of the third switch element  786 , NFET 13 , where the source of the third switch element  786 , NFET 13 , is coupled to ground and the gate of third switch element  786 , NFET 13 , is coupled to the third capacitor control signal  766 , CNTR_CD 3 , of the variable capacitance control bus  760 , CNTR_CD (5:1). The fourth programmable capacitance  798  may be formed by coupling the fourth array capacitor  778  between the third voltage node  724  and the drain of the fourth switch element  788 , NFET 14 , where the source of the fourth switch element  788 , NFET 14 , is coupled to ground and the gate of the fourth switch element  788 , NFET 14 , is coupled to the fourth capacitor control signal  768 , CNTR_CD 4 , of the variable capacitance control bus  760 , CNTR_CD (5:1). The fifth programmable capacitance  800  may be formed by coupling the fifth array capacitor  780  between the third voltage node  724  and the drain of the fifth switch element  790 , NFET 15 , where the source of the fifth switch element  790 , NFET 15 , is coupled to ground and the gate of the fifth switch element  790 , NFET 15 , is coupled to the fifth capacitor control signal  770 , CNTR_CD 5 , of the variable capacitance control bus  760 , CNTR_CD (5:1). 
     As an example, in some embodiments, the variable delay capacitor  722 A is configured such that the programmable capacitor array  758  is a linearly programmable capacitor array. The variable delay capacitor  722 A may be configured to be a linearly programmable capacitor array by configuring the first array capacitor capacitance, C D1 , the second array capacitor capacitance, C D2 , the third array capacitor capacitance, C D3 , the fourth array capacitor capacitance, C D4 , and the fifth array capacitor capacitance, C D5 , to have the same capacitance value. 
     As an alternative example, in some embodiments of the variable delay capacitor  722 A, the programmable capacitor array  758  may be configured as a binary weighted programmable capacitor array. The binary weighted programmable capacitor array may be configured such that the second array capacitor capacitance, C D2 , has substantially twice the capacitance as the first array capacitor capacitance, C D1 , the third array capacitor capacitance, C D3 , has substantially twice the capacitance as the second array capacitor capacitance, C D2 , the fourth array capacitor capacitance, C D4 , has substantially twice the capacitance as the third array capacitor capacitance, C D3 , and the fifth array capacitor capacitance, C D5 , has substantially twice the capacitance as the fourth array capacitor capacitance, C D4 . 
     The controller  50  may be configured to selectively control the variable capacitance control bus  760 , CNTR_CD (5:1), to set the capacitance value of the variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  722 A. The first capacitor control signal  762 , CNTR_CD 1 , the second capacitor control signal  764 , CNTR_CD 2 , the third capacitor control signal  766 , CNTR_CD 3 , the fourth capacitor control signal  768 , CNTR_CD 4 , and the fifth capacitor control signal  770 , CNTR_CD 5 , may form a binary capacitor control word, CNTR_CD, where 0≧CNTR_CD≧31. 
     Accordingly, the programmable capacitor array  758  may be configured such that as the value of the binary capacitor control word, CNTR_CD increases from 0 to 31, the effective capacitance of the programmable capacitor array  758  changes linearly. 
     Accordingly, returning to  FIG. 4 , in those embodiments of the programmable delay circuitry  432 C that include an embodiment of the variable delay capacitor  722 A, depicted in  FIG. 7 , the delay step size, Δ VARIABLE     —     DELAY     —     TIME , of the variable delay circuitry  684  between any two adjacent values of the variable delay capacitance, C DELAY     —     VAR , may be a function of the granularity of the effective capacitance of the binary capacitor control word, CNTR_CD changes, and the number of array capacitors present in the binary weighted programmable capacitor array. In some embodiments of the programmable delay circuitry  432 C, the variable delay circuitry  684  may be configured such that the average delay step size, Δ VARIABLE     —     DELAY     —     TIME , of the variable delay time, T VARIABLE     —     DELAY     —     TIME , is about 136 picoseconds. In other embodiments of the programmable delay circuitry  432 C, the variable delay circuitry  684  may be configured such that the average delay step size, Δ VARIABLE     —     DELAY     —     TIME , of the variable delay time, T VARIABLE     —     DELAY     —     TIME , is about 100 picoseconds. 
     Illustratively, by way of example, and not by limitation, in some embodiments of the programmable capacitor array  758  used to provide the variable delay capacitance, C DELAY     —     VAR , of the variable delay circuitry  684 , the first array capacitor capacitance, C D1 , of the first array capacitor  772  may have a capacitance of around 18.25 pF. The second array capacitor capacitance, C D2 , of the second array capacitor  774  may have a capacitance of around 30.93 pF. The third array capacitor capacitance, C D3 , of the third array capacitor  776  may have a capacitance of around 61.86 pF. The fourth array capacitor capacitance, C D4 , of the fourth array capacitor  778  may have a capacitance of around 123.72 pF. The fifth array capacitor capacitance, C D5 , of the fifth array capacitor  780  may have a capacitance of around 247.45 pF. 
     The variable delay capacitance, C DELAY     —     VAR , of the variable delay capacitor  722 , depicted in  FIG. 4 , may be configured by the controller  50  by incrementally changing the variable delay time, T VARIABLE     —     DELAY     —     TIME , provided by the programmable delay circuitry  432 C, depicted in  FIG. 4 , in steps substantially equal to the average delay step size, Δ VARIABLE     —     DELAY     —     TIME . For example, for the case where the average delay step size, Δ VARIABLE     —     DELAY     —     TIME , is substantially equal to 136 picoseconds, the high frequency ripple compensation current  416 , I COR , may be aligned to within an accuracy of less than 136 picoseconds. The precision of the average temporal alignment may be based upon the granularity of the capacitance values of the capacitors of the binary capacitor array. 
     Output Impedance Compensation of a Pseudo-Envelope Follower Power Management System 
     A switch mode power supply converter, a parallel amplifier, and a parallel amplifier output impedance compensation circuit are disclosed. The switch mode power supply converter provides a switching voltage and generates an estimated switching voltage output, which is indicative of the switching voltage. The parallel amplifier generates a power amplifier supply voltage at a power amplifier supply output based on a compensated V RAMP  signal. The parallel amplifier output impedance compensation circuit provides the compensated V RAMP  signal based on a combination of a V RAMP  signal and a high frequency ripple compensation signal. The high frequency ripple compensation signal is based on a difference between the V RAMP  signal and the estimated switching voltage output. 
     In one embodiment of the parallel amplifier output impedance compensation circuit, the parallel amplifier output impedance compensation circuit compensates for a non-ideal output impedance of the parallel amplifier by providing the compensated V RAMP  signal based on the combination of the V RAMP  signal and a high frequency ripple compensation signal. In one embodiment of the parallel amplifier output impedance compensation circuit, the combination of the V RAMP  signal and the high frequency ripple compensation signal is based on pre-filtering the V RAMP  signal to equalize the overall frequency response of the switch mode power supply converter and the parallel amplifier to provide a proper transfer function of the switch mode power supply converter and the parallel amplifier. 
       FIG. 5A  depicts an example embodiment of a pseudo-envelope follower power management system  10 PA that is similar in form and function to the pseudo-envelope follower power management system  10 B, depicted in  FIG. 2B . However, unlike the pseudo-envelope follower power management system  10 B, depicted in  FIG. 2B , the pseudo-envelope follower power management system  10 PA may include a switch mode power supply converter  802  instead of the multi-level charge pump buck converter  12 B. The switch mode power supply converter  802  may include a switcher control circuit  804  and programmable delay circuitry  806 . In addition, unlike the pseudo-envelope follower power management system  10 B, depicted in  FIG. 2B , the pseudo-envelope follower power management system  10 PA includes a parallel amplifier circuit  14 PA. 
     The switch mode power supply converter  802  depicted in  FIGS. 5A-5E  may be either a multi-level charge pump buck converter or a buck converter. The switch mode power supply converter  802  uses the switcher control circuit  804  in combination with the programmable delay circuitry  806  to generate a delayed estimated switching voltage output,  38 D, V SW     —     EST     —     DELAYED . The controller  50  may configure the delay provided by the programmable delay circuitry  806  to temporally shift the delayed estimated switching voltage output,  38 D, V SW     —     EST     —     DELAYED , with respect to the estimated switching voltage output  38 B, V SW     —     EST . Accordingly, the controller  50  may temporally align the generation of the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , with respect to the V RAMP  signal to improve performance of the circuitry and systems to be described. 
     In addition, some embodiments of the switch mode power supply converter  802  may include an FLL circuit (not depicted) similar to the FLL circuit  54  ( FIG. 2A ). Likewise, as a non-limiting example, the switch mode power supply converter  802  may be configured as a multi-level charge pump buck converter. Alternatively, as another non-limiting example, the switch mode power supply converter  802  may be configured as a buck converter. 
     Similar to the generation of the estimated switching voltage output  38 B, V SW     —     EST , by the switcher control circuit  52  of the multi-level charge pump buck converter  12 B, depicted in  FIG. 2B , the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , provides an indication of the switching voltage, V SW , to be generated at the switching voltage output  26  based on the state of the switcher control circuit  804 , except the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , may be delayed by an alignment period, T ALIGNMENT  to compensate for delays in either the switch mode power supply converter  802 , the parallel amplifier circuit  14 PA, or both. 
     The programmable delay circuitry  806  of the switch mode power supply converter  802  may be configured by the controller  50  to provide the alignment period, T ALIGNMENT , in order to generate the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED . As a non-limiting example, the programmable delay circuitry  806  may be similar in form and function to the programmable delay circuitry  432 A, depicted in  FIG. 3A , the programmable delay circuitry  432 B, depicted in  FIG. 3B , or the programmable delay circuitry  432 C, depicted in  FIG. 4 . 
     The controller  50  may configure the switch mode power supply converter  802  to scale the magnitude of the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , such that the magnitude of the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , tracks variations in the supply input  24 , (V BAT ). 
     The pseudo-envelope follower power management system  10 PA further includes a V RAMP  digital-to-analog (D/A) circuit  808  and a parallel amplifier circuit  14 PA that is similar in form and function to the parallel amplifier circuit  14 B, depicted in  FIG. 2B . However, unlike the parallel amplifier circuit  14 B, the parallel amplifier circuit  14 PA may be further configured to receive both the estimated switching voltage output  38 B, V SW     —     EST , and the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , generated by the switch mode power supply converter  802 . In addition, the V RAMP  digital-to-analog (D/A) circuit  808  may be configured to receive a digital V RAMP  signal  810 , V RAMP     —     DIGITAL , from a baseband portion of a transceiver or modem (not depicted). The V RAMP  digital-to-analog (D/A) circuit  808  converts the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , to provide a version of the V RAMP  signal in the analog domain. The version of the V RAMP  signal may be either a differential or a single ended signal. The V RAMP  digital-to-analog (D/A) circuit  808  provides the V RAMP  signal to the first control input  34  of the parallel amplifier circuit  14 PA. 
     The pseudo-envelope follower power management system  10 PA includes a parallel amplifier output impedance compensation circuit  37 B configured to generate a compensated V RAMP  signal, V RAMP     —     C , for use by the parallel amplifier  35  in lieu of the V RAMP  signal in order to reduce the high frequency ripple voltages generated in the parallel amplifier output voltage, V- PARA     —     AMP , by the parallel amplifier  35  at the parallel amplifier output  32 A due to the non-ideal output impedance characteristics of the parallel amplifier  35 . For example, one of the non-ideal output impedance characteristics of the parallel amplifier  35  is that the parallel amplifier  35  has an output impedance response that is inductive and increases approximately +6 dB/octave near and around the switching frequency of the switch mode power supply converter  802 . Thus, for example, the output impedance of the parallel amplifier  35  may be characterized as having a parallel amplifier inductance, L CORR . 
     Returning to  FIG. 5A , in addition, the parallel amplifier output impedance compensation circuit  37 B includes a digital V RAMP  pre-distortion filter circuit  812 . The frequency response of the digital V RAMP  pre-distortion filter circuit  812  may be configured to equalize the response of the pseudo-envelope follower power management system  10 PA. As an example, the digital V RAMP  pre-distortion filter circuit  812  may be configured to pre-distort the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , in order to compensate for different combinations of the power inductor inductance of the power inductor  16  and the bypass capacitance, C BYPASS , of the bypass capacitor  19 , the transfer function of the parallel amplifier  35 , the power amplifier associated inductance, L PA , (not shown), and the power amplifier filter associated capacitance, C PA , (not shown), and/or some combination thereof. 
     For example, the power amplifier associated inductance, L PA , (not shown) includes any parasitic inductance or filter inductance added between the power amplifier supply voltage, V CC , controlled by the parallel amplifier circuit  14 PA, and the power amplifier collector  22 A of a linear RF power amplifier  22 . The power amplifier filter associated capacitance, C PA , (not shown) includes any parasitic capacitance of a load line between the power amplifier supply voltage, V CC , controlled by the parallel amplifier circuit  14 PA and any added decoupling capacitance related to a power amplifier decoupling capacitor (not shown) coupled to the power amplifier collector  22 A. The power amplifier associated inductance, L PA , and the power amplifier filter associated capacitance, C PA , (not shown) may be determined at the time of calibration of an electronic device that includes the pseudo-envelope follower power management system  10 PA. The power amplifier associated inductance, L PA , (not shown) in combination with the power amplifier filter associated capacitance, C PA , (not shown) may form a power amplifier low pass filter (not shown) such that the frequency response of the combination of the power amplifier low pass filter and the pseudo-envelope follower power management system  10 PA is not substantially flat through the operating frequency range of the linear RF power amplifier  22 . Accordingly, the frequency response of the digital V RAMP  pre-distortion filter circuit  812  may be configured to compensate the frequency response of the pseudo-envelope follower power management system  10 PA such that the overall frequency response, as measured between the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , and the power amplifier collector  22 A, is substantially flat through the operating frequency range of the linear RF power amplifier  22 . 
     As depicted in  FIG. 5A , in some embodiments of the parallel amplifier output impedance compensation circuit  37 B, the digital V RAMP  pre-distortion filter circuit  812  is located in a digital baseband processing portion of a transceiver or modem of a communication device (not shown). The digital V RAMP  pre-distortion filter circuit  812  is in communication with the parallel amplifier circuit  14 PA, and provides a pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED . In some alternative embodiments of the pseudo-envelope follower power management system  10 PA, (not shown), the digital V RAMP  pre-distortion filter circuit  812  may be included in the parallel amplifier circuit  14 PA. 
     Accordingly, unlike the parallel amplifier circuit  14 B, depicted in  FIG. 2B , the parallel amplifier circuit  14 PA, depicted in  FIG. 5A , includes a portion of a parallel amplifier output impedance compensation circuit  37 B that is in communication with a digital V RAMP  pre-distortion filter circuit  812 . Whereas the embodiment of the parallel amplifier output impedance compensation circuit  37 , depicted in  FIG. 2B , is depicted as receiving an analog V RAMP  signal, the digital V RAMP  pre-distortion filter circuit  812  of the parallel amplifier output impedance compensation circuit  37 B is configured to receive a digital V RAMP  signal  810 , V RAMP     —     DIGITAL , from the baseband portion of a transceiver or modem. The digital V RAMP  pre-distortion filter circuit  812  provides a pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED . As will be discussed, the digital V RAMP  pre-distortion filter circuit  812  filters the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , to generate the pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED , to equalize the overall frequency response of the pseudo-envelope follower power management system  10 PA. 
       FIG. 6  is described with continuing reference to  FIG. 5A .  FIG. 6  depicts an embodiment of the V RAMP  digital-to-analog (D/A) circuit  808  and the digital V RAMP  pre-distortion filter circuit  812 . As depicted in  FIG. 6 , the V RAMP  digital-to-analog (D/A) circuit  808  may include a digital delay circuit  808 A, a first digital-to-analog (D/A) converter circuit  808 B, and an anti-aliasing filter  808 C. The V RAMP  digital-to-analog (D/A) circuit  808  may be coupled to the control bus  44  from the controller  50  (not depicted), and configured to receive the digital V RAMP  signal  810 , V RAMP     —     DIGITAL . Via the control bus  44 , the controller  50  may configure the operation of the digital delay circuit  808 A, the first digital-to-analog (D/A) converter circuit  808 B, and the anti-aliasing filter  808 C. The V RAMP  digital-to-analog (D/A) circuit  808  may be configured to generate the V RAMP  signal in the analog domain. For example, in some embodiments, the V RAMP  digital-to-analog (D/A) circuit  808  may generate a differential analog version of the V RAMP  signal. The digital delay circuit  808 A may be configured to receive the digital V RAMP  signal  810 , V RAMP     —     DIGITAL . The digital delay circuit  808 A may be a programmable tapped delay line configured to delay the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , such that the generated V RAMP  signal is temporally aligned with the pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED . The digital delay circuit provides the delayed version of the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , to the first digital-to-analog (D/A) converter circuit  808 B. The first digital-to-analog (D/A) converter circuit  808 B converts the delayed version of the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , into an analog representation of the V RAMP  signal, which is anti-aliasing filtered by the anti-aliasing filter  808 C to generate the V RAMP  signal. 
     The digital V RAMP  pre-distortion filter circuit  812  may include a pre-filter circuit  812 A, a second digital-to-analog converter (D/A) circuit  812 B, and an anti-aliasing filter  812 C. The pre-filter circuit  812 A may be configured to be either an infinite impulse response (IIR) filter or a finite impulse response (FIR) filter configured to receive the digital V RAMP  signal  810 , V RAMP     —     DIGITAL . The pre-filter circuit  812 A may be configured by the controller  50  to control the frequency response of the pre-filter circuit  812 A. The pre-filter circuit  812 A may include one or more coefficients that may be configured by the controller  50  to shape the frequency response of the pre-filter circuit  812 A. 
     As an example, in the case where the pre-filter circuit  812 A is configured to be an infinite impulse response (IIR) filter, the pre-filter circuit  812 A may include feed forward filter coefficients and feedback filter coefficients. Likewise, the pre-filter circuit  812 A may be configured to be a multiple order filter. For example, in some embodiments of the digital V RAMP  pre-distortion filter circuit  812 , the pre-filter circuit  812 A may be configured to be a first order filter. In alternative embodiments of the digital V RAMP  pre-distortion filter circuit  812 , the pre-filter circuit  812 A may be a filter having two or more orders. As a result, the digital V RAMP  pre-distortion filter circuit  812  may permit the controller to have additional degrees of control of the pre-distortion of the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , which is used to provide a pre-distorted V RAMP  signal. As an example, the controller  50  may configure the feed forward coefficients and the feedback coefficients of the digital V RAMP  pre-distortion filter circuit  812  to provide frequency peaking to compensate for the low pass filter effect of the combination of the power amplifier associated inductance, L PA , (not shown), and the power amplifier filter associated capacitance, C PA , (not shown), as described above. 
     As an alternative case, in some embodiments the pre-filter circuit  812 A may be a finite impulse response (FIR) filter having multiple weighting coefficients. The controller  50  may configure each of the weighting coefficients to configure the frequency response of the digital V RAMP  pre-distortion filter circuit  812  to pre-distort the digital V RAMP  signal, V RAMP     —     DIGITAL , to also equalize the overall frequency response of the pseudo-envelope follower power management system  10 PA. In addition, the digital V RAMP  pre-distortion filter circuit  812  may be further configured to compensate for the power amplifier associated inductance, L PA , (not shown), and the power amplifier filter associated capacitance, C PA , (not shown), such that the overall frequency response, as measured between the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , and the power amplifier collector  22 A, is substantially flat through the operating frequency range of the linear RF power amplifier  22 . 
     The output of the pre-filter circuit  812 A is digital to analog converted by the second digital-to-analog converter (D/A) circuit  812 B, where the output of the second digital-to-analog converter (D/A) circuit  812 B is anti-alias filtered by the anti-aliasing filter  812 C to provide the pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED . The frequency response of the pre-filter circuit  812 A may be configured to equalize the overall transfer function response between the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , and the power amplifier collector  22 A. As an example, the amount or shape of the equalization provided by the frequency response of the pre-filter circuit  812 A, and thus the digital V RAMP  pre-distortion filter circuit  812 , may depend upon the bypass capacitance, C BYPASS , of the bypass capacitor  19 , the power amplifier associated inductance, L PA , (not shown), the power amplifier filter associated capacitance, C PA , (not shown), the frequency response of the parallel amplifier  35 , and/or a combination thereof. 
     In addition, the controller  50  may adjust the frequency response of the pre-filter circuit  812 A by modifying the one or more coefficients of the pre-filter circuit  812 A to equalize the relative transfer function response between the power amplifier supply voltage V CC , and the digital V RAMP  signal  810 , V RAMP     —     DIGITAL . The controller  50  adjusts the frequency response of the pre-filter circuit  812 A such that the frequency response of the overall transfer function response between the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , and the power amplifier collector  22 A is substantially flattened through a desired frequency range. Illustratively, in some embodiments, the controller  50  may configure the equalization or frequency response of the pre-filter circuit  812 A such that the frequency response of the overall transfer function response the digital V RAMP  signal  810 , V RAMP     —     DIGITAL , and the power amplifier collector  22 A is substantially flattened out to around 20 MHz. 
     As an example, where the pre-filter circuit  812 A is configured as an IIR filter, the pre-filter circuit  812 A is configured to operate at a clock rate of about 312 MHz. Illustratively, for the case where the bypass capacitance, C BYPASS , of the bypass capacitor  19  is approximately 2 nF, the controller  50  may configure the frequency response of the pre-filter circuit  812 A to have a pole at approximately 14.5 MHz and a zero at approximately 20 MHz. 
     In addition, in some embodiments of the digital V RAMP  pre-distortion filter circuit  812 , the controller  50  may configure the equalization or frequency response provided by the pre-filter circuit  812 A as a function of the operational bandwidth of the linear RF power amplifier  22  needed to provide the wide-band modulation corresponding to a specific LTE band number. As an example, in a case where the LTE band has a 15 MHz bandwidth, the controller  50  may configure the digital V RAMP  pre-distortion filter circuit  812  to provide additional V RAMP  pre-distortion such that the radio frequency signal generated by the linear RF power amplifier falls within the spectrum mask requirements for an LTE  15  MHz test case. 
     Returning to  FIG. 5A , the parallel amplifier output impedance compensation circuit  37 B may further include an estimated switching voltage output selection switch  816 , S 1 , having a first input  816 A configured to receive the estimated switching voltage output  38 B, V SW     —     EST , a second input  816 B configured to receive the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , and an estimated switching voltage output selection switch output  816 C. The controller  50  may configure the estimated switching voltage output selection switch  816 , S 1 , to provide either the estimated switching voltage output  38 B, V SW     —     EST , or the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as an estimated switching voltage input signal  820 , V SW     —     I , at the estimated switching voltage output selection switch output  816 C. 
     The parallel amplifier output impedance compensation circuit  37 B further includes a first subtracting circuit  822 , a Z OUT  compensation high pass filter  824 , a G CORR  scalar circuit  826 , a second subtracting circuit  828 , a tune circuit  830 , and a summing circuit  832 . The first subtracting circuit  822  includes a positive terminal configured to receive the V RAMP  signal provided to the first control input  34  of the parallel amplifier circuit  14 PA and a negative terminal configured to receive the estimated switching voltage input signal  820 , V SW     —     I . The first subtracting circuit  822  subtracts the estimated switching voltage input signal  820 , V SW     —     I , from the V RAMP  signal to generate an expected difference signal  834 , which is provided to the Z OUT  compensation high pass filter  824 . The expected difference signal  834  represents the difference between the target voltage level of the power amplifier supply voltage V CC , to be generated at the power amplifier supply output  28  in response to the V RAMP  signal and the switching voltage, V SW , to be provided at the switching voltage output  26  of the switch mode power supply converter  802  at the time when the parallel amplifier  35  generates the parallel amplifier output voltage, V PARA     —     AMP , at the parallel amplifier output  32 A. 
     A frequency response of the Z OUT  compensation high pass filter  824  may be configurable. As an example, the Z OUT  compensation high pass filter  824  may include programmable time constants. The Z OUT  compensation high pass filter  824  may include resistor arrays or capacitor arrays that may be configurable by the controller  50  to set the value of programmable time constants. For example, the resistor arrays may be binary weighted resistor arrays similar to the binary weighted resistor arrays previously described. The capacitor arrays may be binary weighted capacitor arrays similar to the binary weighted capacitor arrays previously described. The controller  50  may configure the programmable time constants of the Z OUT  compensation high pass filter  824  to obtain a desired high pass filter response. In addition, the controller  50  may configure the programmable time constants of the Z OUT  compensation high pass filter  824  to obtain a desired high pass filter response as a function of the operational bandwidth or the wide-bandwidth modulation associated with the LTE band number for which the linear RF power amplifier  22  is configured to operate. 
     Illustratively, in some embodiments, the Z OUT  compensation high pass filter  824  may have a programmable time constant set to 40 nanoseconds. For example, the programmable time constant may be obtained by the controller  50  configuring the resistance of a programmable resistor to be substantially equal to 4K ohms and the capacitance of a programmable capacitor to be substantially equal to 10 pF. In this scenario, the high pass cutoff frequency, f HPC , of the example Z OUT  compensation high pass filter  824  may be approximately equal to 4 MHz. In some embodiments, the Z OUT  compensation high pass filter  824  may be a multiple-order high pass filter having multiple programmable time constants. In the case where the Z OUT  compensation high pass filter  824  is a multiple-order high pass filter, the controller  50  may be configured to set multiple programmable time constants to obtain a desired high pass frequency response from the Z OUT  compensation high pass filter  824 . As an example, the Z OUT  compensation high pass filter  824  may be a second order high pass filter having a first time constant and a second time constant corresponding to a first high pass cutoff frequency, f HPC1 , and a second high pass cutoff frequency, f HPC2 . In this case, the controller  50  may configure the first time constant and the second time constant of the Z OUT  compensation high pass filter  824  to obtain a desired high pass frequency response. In other embodiments, the Z OUT  compensation high pass filter  824  may be configured as an active filter. 
     When the controller  50  configures the estimated switching voltage output selection switch  816 , S 1 , to provide the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as the estimated switching voltage input signal  820 , V SW     —     I , the controller  50  may configure the programmable delay circuitry  806  to provide a delay substantially equal to an alignment period, T ALIGNMENT , in order to time align the indication of the switching voltage output, V SW , represented by the estimated switching voltage input signal  820 , V SW     —     I , with the V RAMP  signal. The expected difference signal  834  is provided to the Z OUT  compensation high pass filter  824 . The Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834  to generate an estimated high frequency ripple signal  836 . The high pass filtering of the Z OUT  compensation high pass filter  824  substantially extracts only the high frequency content of the expected difference signal  834 , where the high frequency content of the expected difference signal  834  represents a scaled derivative of the ripple current in the inductor current, I SW     —     OUT , of the power inductor  16  generated by the switch mode power supply converter  802  due to the changes in the switching voltage, V SW , associated with the estimated switching voltage input signal  820 , V SW     —     I . Thus, the estimated high frequency ripple signal  836  represents an estimated high frequency ripple current at the power amplifier supply output  28  that may cause the parallel amplifier  35  to generate high frequency ripple voltages in the parallel amplifier output voltage, V PARA     —     AMP , at the parallel amplifier output  32 A. The delay period provided by the programmable delay circuitry  806  may be configured by the controller  50  to temporally align the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , with the V RAMP  signal to improve the accuracy of the estimated high frequency ripple signal  836 . 
     In contrast, the controller  50  may configure the estimated switching voltage output selection switch  816 , S 1 , to provide the estimated switching voltage output  38 B, V SW     —     EST , as the estimated switching voltage input signal  820 , V SW     —     I , to the Z OUT  compensation high pass filter  824 . In this case, the Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834  to generate the estimated high frequency ripple signal  836 . The estimated high frequency ripple signal  836  substantially corresponds to a scaled derivative of a switcher ripple current in the inductor current, I SW     —     OUT , of the power inductor  16  based on the estimated switching voltage output  38 B, V SW     —     EST . However, because the generation of the estimated switching voltage output  38 B, V SW     —     EST , cannot be temporally aligned by adjusting a delay period provided by the programmable delay circuitry  806 , the controller  50  may not configure the programmable delay circuitry  806  to minimize the peak-to-peak ripple voltages on the power amplifier supply voltage, V CC , by improving the temporal alignment of the estimated switching voltage output  38 B, V SW     —     EST , with respect to the V RAMP  signal. 
     As previously discussed, the Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834  generated based on the estimated switching voltage output  38 B, V SW     —     EST , to generate the estimated high frequency ripple signal  836 . The pass band of the Z OUT  compensation high pass filter  824  extracts only the high frequency content of the estimated switching voltage input signal  820 , V SW     —     I , where the expected difference signal  834  represents the expected difference between the switching voltage output, V SW , and the target voltage level of the power amplifier supply voltage, V CC , based on the V RAMP  signal. 
     Because the Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834 , the direct current content of the expected difference signal  834  is not present in the estimated high frequency ripple signal  836 . The G CORR  scalar circuit  826  scales the estimated high frequency ripple signal  836  based on a scaling factor, G CORR , to generate a high frequency ripple compensation signal  838 . 
     The high frequency ripple compensation signal  838  is added to the pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED , by the summing circuit  832  to generate the compensated V RAMP  signal, V RAMP     —     C . The high frequency ripple compensation signal  838  is added to the pre-filtered V RAMP  signal  814 , V RAMP     —     PRE-FILTERED , to compensate for the non-ideal output impedance of the parallel amplifier  35 . The compensated V RAMP  signal, V RAMP     —     C , is provided as an input to the parallel amplifier  35 . The parallel amplifier  35  generates the parallel amplifier output voltage, V PARA     —     AMP , based on the difference between the compensated V RAMP  signal, V RAMP     —     C , and the power amplifier supply voltage, V CC . 
     Generation of the scaling factor, G CORR , will now be discussed. The second subtracting circuit  828  is configured to subtract the power amplifier supply voltage, V CC , from the V RAMP  signal to provide a G CORR  feedback signal  840  that is received by the tune circuit  830 . In some embodiments of the parallel amplifier output impedance compensation circuit  37 B, the tune circuit  830  may be configured to dynamically provide the scaling factor, G CORR , to the G CORR  scalar circuit  826  based on the G CORR  feedback signal  840 . As an example, the controller  50  may configure the tune circuit  830  to provide a different value of the scaling factor, G CORR , on a block-by-block transmission basis dependent upon the operational mode of the linear RF power amplifier  22 . For example, the tune circuit  830  may be configured by the controller  50  during a calibration procedure to develop at least one G CORR  curve. In other embodiments, the tune circuit  830  may have multiple G CORR  curves that may be used to provide a scaling factor, G CORR , based on the G CORR  feedback signal  840  and the operational mode of the linear RF power amplifier  22 . As an example, the controller  50  may configure the tune circuit  830  to use a particular one of the G CORR  curves depending on the configuration and/or operational mode of the pseudo-envelope follower power management system  10 PA, the parallel amplifier  35 , or a combination thereof. Each G CORR  curve may include several coefficients or values for the scaling factor, G CORR , that correspond to the magnitude of the G CORR  feedback signal  840 . In some embodiments, the controller  50  may select a G CORR  curve to be used on a block-by-block transmission basis depending on the operational mode of the linear RF power amplifier  22 . 
     For example, the controller  50  may select a first G CORR  curve to be used by the tune circuit  830  when the linear RF power amplifier  22  is in a first operational mode. The controller  50  may select a second G CORR  curve to be used by the tune circuit  830  when the linear RF power amplifier  22  is in a second operational mode. In still other embodiments of the parallel amplifier output impedance compensation circuit  37 B, the tune circuit  830  may only have one G CORR  curve to be used by the tune circuit  830  to provide the scaling factor, G CORR , to the G CORR  scalar circuit  826  based on the G CORR  feedback signal  840 . 
     As an example, in some embodiments of the parallel amplifier output impedance compensation circuit  37 B, the scaling factor, G CORR , is tuned by the tune circuit  830  based on a built-in calibration sequence that occurs at power start-up. As an example, the controller  50  may configure the switch mode power supply converter  802  to operate with a switching frequency that is a fixed frequency to create a switcher ripple current in the inductor current, I SW     —     OUT , of the power inductor  16  at a frequency of concern for the pseudo-envelope follower power management system  10 PA. In those cases where the switch mode power supply converter  802  is configured as a multi-level charge pump buck converter, the controller  50  may configure the switch mode power supply converter  802  to operate in a “bang-bang mode” of operation. When operating in the “bang-bang mode” of operation, the controller  50  configures the switcher control circuit  804  such that the switch mode power supply converter  802  operates in a fashion similar to a buck converter. Thus, when operating in the “bang-bang mode” of operation, the switch mode power supply converter  802  the switcher control circuit  804  does not permit the switch mode power supply converter  802  to provide a boosted output voltage at the switching voltage output  26 . 
     As a non-limiting example, to tune the scaling factor, G CORR , the controller  50  may configure the switch mode power supply converter  802  to operate at a calibration frequency with a fixed duty cycle in order to create a switcher ripple current at the calibration frequency. For example, the controller  50  may set the calibration frequency to 10 MHz. The V RAMP  signal is set to a constant value in order to create a constant output value for the power amplifier supply voltage, V CC , at the power amplifier supply output  28 . As discussed previously, the controller  50  may configure the switch mode power supply converter  802  to operate in a “bang-bang mode” of operation. The direct current voltage present at the power amplifier supply voltage, V CC , will be primarily set by the duty cycle of the switch mode power supply converter  802 . The DC voltage may be mainly set by the duty cycle on the switching voltage output  26  of the switch mode power supply converter  802 . The tune circuit  830  determines the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC , based on the G CORR  feedback signal  840 . Based on the magnitude of the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC , the tune circuit  830  adjusts the value of the scaling factor, G CORR , until the peak-to-peak ripple voltage on the G CORR  feedback signal  840  is minimized. In some embodiments, to adjust the value of the scaling factor, G CORR , based on the G CORR  feedback signal  840 , the controller  50  may determine the degree of adjustment to provide based on the estimated power inductor inductance parameter, L EST , the estimated bypass capacitance parameter, C BYPASS     —     EST , and the estimated power amplifier transconductance parameter, K_I OUT     —     EST , as previously described. Based on the scaling factor, G CORR , that provides the minimum peak-peak ripple voltage on the power amplifier supply voltage, V CC , the tune circuit  830  selects the scaling factor, G CORR , to be provided to the G CORR  scalar circuit  826 . In some embodiments, the controller  50  may configure the switch mode power supply converter  802  to operate at various calibration frequencies to develop one or more G CORR  curves, where each G CORR  curve corresponds to an operational mode of the linear RF power amplifier  22 . 
     The determination of the scaling factor, G CORR , and/or the development of the G CORR  curves is substantially orthogonal to the temporal alignment of the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED . Thus, following calibration of the tune circuit  830  to provide the scaling factor, G CORR , appropriate for the operational mode of the linear RF power amplifier  22 , the controller  50  may be further configured to adjust the alignment period, T ALIGNMENT , associated with the programmable delay circuitry  806  to temporally align the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , in order to further minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC . Thus, after the controller  50  completes the calibration of the tune circuit  830  to minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC , the controller  50  may configure the programmable delay circuitry  806  to iteratively adjust the alignment period, T ALIGNMENT , provided by the programmable delay circuitry  806  to further minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC . In some embodiments, the controller  50  may determine the alignment period, to be provided by the programmable delay circuitry  806 , for different operational modes of the linear RF power amplifier  22 . 
       FIG. 5B  depicts another example embodiment of a pseudo-envelope follower power management system  10 PB that is similar in form and function to the pseudo-envelope follower power management system  10 PA, depicted in  FIG. 5A . However, unlike the pseudo-envelope follower power management system  10 PA, the pseudo-envelope follower power management system  10 PB includes a parallel amplifier output impedance compensation circuit  37 C that is divided between a parallel amplifier circuit  14 PB and the digital baseband processing portion of a transceiver or modem. The example embodiment of the parallel amplifier output impedance compensation circuit  37 C is similar in form and function to the parallel amplifier output impedance compensation circuit  37 B, depicted in  FIG. 5A , except the scaling factor, G CORR , is provided by a G CORR  function circuit  842  instead of the tune circuit  830 , depicted in  FIG. 5A . 
     The G CORR  function circuit  842  is configured to receive the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , generated by the parallel amplifier sense circuit  36  of the parallel amplifier circuitry  32 . The value of the scaling factor, G CORR , may be based on a G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), where the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), characterizes values of the scaling factor, G CORR , as a function of the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE . In some embodiments, the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), may be a polynomial function. In other embodiments, the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), may be a linear function. For example, the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), may have G CORR  scaling function coefficients that may be configurable by the controller  50  via the control bus  44 . As a non-limiting example, equation (8) provides an example of the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), having two G CORR  scaling function coefficients. For example, the G CORR  scaling function coefficients may include a first G CORR  scaling function coefficient, G CORR (0), and a second G CORR  scaling function coefficient, G CORR (1), where the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), is a linear function characterized by equation (8) as follows:
 
 G   CORR ( I   PARA     —     AMP     —     SENSE )= G   CORR (0)+ G   CORR (1)× I   PARA     —     AMP     —     SENSE   (8)
 
     The first G CORR  scaling function coefficient, G CORR (0), may represent a scaling factor that is independent of the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , and the second G CORR  scaling function coefficient, G CORR (1), represents a first order coefficient of the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), that captures the dependency of the scaling factor, G CORR , on the change of value of the parallel amplifier inductance, L CORR , as a function of the parallel amplifier output current, I PARA     —     AMP . For example, in some embodiments, the second G CORR  scaling function coefficient, G CORR (1) may be based on the parallel amplifier inductance estimate parameter, L CORR     —     EST , where the parallel amplifier inductance estimate parameter, L CORR     —     EST , is an estimated inductance of the parallel amplifier  35  between the frequencies 10 MHz and 30 MHz. 
     In addition, because the parallel amplifier output current, I PARA     —     AMP , may change depending upon the operational mode of the linear RF power amplifier  22 , the values of the first G CORR  scaling function coefficient, G CORR (0), and the value of the second G CORR  scaling function coefficient, G CORR (1), may be calibrated for each mode of operation of the linear RF power amplifier  22 . As an example, the G CORR  function circuit  842  may include a first set of G CORR  scaling function coefficients that correspond to a first LTE band number and a second set of G CORR  scaling function coefficients that correspond to a second LTE band number. In other words, the controller  50  may configure the G CORR  function circuit  842  to adaptively determine the G CORR  scaling function coefficients to be used to characterize the G CORR  scaling function, G CORR (I PARA     —     AMP     —     SENSE ), based upon the operational mode of the pseudo-envelope follower power management system  10 PB and/or the band of operation at which the linear RF power amplifier  22  is transmitting. 
     In some alternative embodiments, the G CORR  function circuit  842  may be configured by the controller  50  to provide a fixed value of the scaling factor, G CORR , as depicted in equation (9) as follows: 
                     G   CORR     =       L   CORR_EST       L   EST               (   9   )               
where the estimated power inductor inductance parameter, L EST , represents the measured or estimated inductance of the power inductor  16  between a specific range of frequencies and the parallel amplifier inductance estimate parameter, L CORR     —     EST , estimates the inductance of the parallel amplifier  35  between a specific range of frequencies, as discussed above.
 
       FIG. 5C  depicts an example embodiment of a pseudo-envelope follower power management system  10 PC that is similar in form and function to the pseudo-envelope follower power management system  10 PA, depicted in  FIG. 5A . However, unlike the pseudo-envelope follower power management system  10 PA, depicted in  FIG. 5A , the pseudo-envelope follower power management system  10 PC includes a parallel amplifier circuit  14 PC that includes a parallel amplifier output impedance compensation circuit  37 D. Unlike the parallel amplifier output impedance compensation circuit  37 B of the pseudo-envelope follower power management system  10 PA, depicted in  FIG. 5A , the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , includes an analog V RAMP  pre-distortion filter circuit  844  configured to receive the V RAMP  signal in the analog domain. Similar to the digital V RAMP  pre-distortion filter circuit  812 , depicted in  FIG. 5A , the analog V RAMP  pre-distortion filter circuit  844  pre-distorts the V RAMP  signal in the frequency domain to generate an analog pre-filtered V RAMP  signal  814 A, V RAMP     —     ANALOG     —     PRE-FILTERED . The controller  50  may configure the analog V RAMP  pre-distortion filter circuit  844  to filter the V RAMP  signal such that the analog pre-filtered V RAMP  signal  814 A, V RAMP     —     ANALOG     —     PRE-FILTERED , may be used to equalize the response of the pseudo-envelope follower power management system  10 PC and compensate for the bypass capacitance, C BYPASS , of the bypass capacitor  19 , the power amplifier associated inductance, L PA , (not shown), the power amplifier filter associated capacitance, C PA , (not shown), and the frequency response of the transfer function of the parallel amplifier  35 . 
     As a non-limiting example, the analog V RAMP  pre-distortion filter circuit  844  may include programmable time constants that may be configured by the controller  50 . The controller  50  may configure the frequency response of the analog V RAMP  pre-distortion filter circuit  844  to equalize the response of the pseudo-envelope follower power management system  10 PA by adjusting the value of the programmable time constants. 
     In some embodiments of the parallel amplifier circuit  14 PC, the analog V RAMP  pre-distortion filter circuit  844  may be configured to compensate for the transfer function of the parallel amplifier  35  in conjunction with the power amplifier filter associated capacitance, C PA , the power amplifier associated inductance, L PA , (not shown), and the bypass capacitance, C BYPASS , of the bypass capacitor  19 . For example, the controller  50  may configure the analog V RAMP  pre-distortion filter circuit  844  to provide frequency peaking to compensate for the low pass filter response due to the combination of the power amplifier associated inductance, L PA , (not shown) and the power amplifier filter associated capacitance, C PA , (not shown) associated with the linear RF power amplifier  22 . In some embodiments, the Laplace transfer function of the analog V RAMP  pre-distortion filter circuit  844  may be represented by equation (10), as follows: 
                       H   ⁡     (   s   )         Analog   ⁢           ⁢   Pre   ⁢     -     ⁢   Distortion   ⁢           ⁢   Filter   ⁢           ⁢   Circuit       =       (     1   +       τ   ZERO_PRE     ⁢   s       )       (     1   +       τ   POLE_PRE     ⁢   s       )               (   10   )               
where, τ ZERO     —     PRE  is a first time constant associated with a real-zero in the Laplace transfer function of the analog V RAMP  pre-distortion filter circuit  844 , and τ POLE     —     PRE  is a second time constant associated with real-pole in the Laplace transfer function of the analog V RAMP  pre-distortion filter circuit  844 . The first time constant, τ ZERO     —     PRE , and the second time constant, τ POLE     —     PRE , may be configured by the controller  50  to pre-distort the V RAMP  signal prior to adding the high frequency ripple compensation signal  838  to compensate for the non-ideal parallel amplifier output impedance of the parallel amplifier  35 . The controller  50  may configure the first time constant, τ ZERO     —     PRE , and the second time constant, τ POLE     —     PRE , of the analog V RAMP  pre-distortion filter circuit  844  based on the RF modulation bandwidth of the linear RF power amplifier  22  associated with a wide-bandwidth modulation of a mode of operation of a communication device that includes the pseudo-envelope follower power management system  10 PC. As an example, the controller  50  may configure the first time constant, τ ZERO     —     PRE , and the second time constant, τ POLE     —     PRE , to provide peaking of the V RAMP  signal in order to flatten the overall modulation frequency response of the pseudo-envelope follower power management system  10 PC based on the wide-bandwidth modulation of a mode of operation of a communication device.
 
     As another example, the controller  50  may configure the analog V RAMP  pre-distortion filter circuit  844  to pre-distort the frequency response of the V RAMP  signal such that the overall transfer function between the first control input  34 , which receives the V RAMP  signal, and the power amplifier collector  22 A of the linear RF power amplifier  22  is substantially flat through the operating frequency range of the linear RF power amplifier  22 . As a non-limiting example, the controller  50  may configure the first time constant, τ ZERO     —     PRE , to place a real-zero at around 11 MHz and the second time constant, τ POLE     —     PRE , to locate a real-pole at around 20 MHz. Accordingly, the analog V RAMP  pre-distortion filter circuit  844  may be configured to provide a peaking response in order to compensate for the frequency response of the pseudo-envelope follower power management system  10 PC and the low pass filter effects of the combination of the power amplifier associated inductance, L PA , (not shown), and the power amplifier filter associated capacitance, C PA , (not shown). 
     Otherwise, similar to the parallel amplifier output impedance compensation circuit  37 B, depicted in  FIG. 5A , the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , may include an estimated switching voltage output selection switch  816 , S 1 , having a first input  816 A configured to receive the estimated switching voltage output  38 B, V SW     —     EST , a second input  816 B configured to receive the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , and an estimated switching voltage output selection switch output  816 C. The controller  50  may configure the estimated switching voltage output selection switch  816 , S 1 , to provide either the estimated switching voltage output  38 B, V SW     —     EST , or the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as an estimated switching voltage input signal  820 , V SW     —     I , at the estimated switching voltage output selection switch output  816 C. 
     The parallel amplifier output impedance compensation circuit  37 D also includes the first subtracting circuit  822 , the Z OUT  compensation high pass filter  824 , the G CORR  scalar circuit  826 , the second subtracting circuit  828 , the tune circuit  830 , and the summing circuit  832 . The first subtracting circuit  822  is configured to subtract the estimated switching voltage input signal  820 , V SW     —     I , from the V RAMP  signal to generate an expected difference signal  834 , which is provided to the Z OUT  compensation high pass filter  824 . As discussed previously, the controller  50  may configure the programmable time constants associated with the Z OUT  compensation high pass filter  824  to high pass filter the expected difference signal  834  in order to generate an estimated high frequency ripple signal  836 . 
     Alternatively, the controller  50  may configure the estimated switching voltage output selection switch  816 , S 1 , to provide the estimated switching voltage output  38 B, V SW     —     EST , as the estimated switching voltage input signal  820 , V SW     —     1 , to the Z OUT  compensation high pass filter  824 . In this case, the Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834  to generate the estimated high frequency ripple signal  836 . As such, the estimated high frequency ripple signal  836  substantially corresponds to a scaled derivative of a switcher ripple current in the inductor current, I SW     —     OUT , of the power inductor  16  based on the estimated switching voltage output  38 B, V SW     —     EST . Similar to the parallel amplifier output impedance compensation circuit  37 B, when the controller  50  configures the estimated switching voltage output selection switch  816 , S 1 , to provide the estimated switching voltage output  38 B, V SW     —     EST , as the estimated switching voltage input signal  820 , V SW     —     I , the controller  50  does not have the ability to adjust temporal alignment of the estimated switching voltage output  38 B, V SW     —     EST , with the V RAMP  signal in order to minimize the peak-to-peak ripple voltage on the power amplifier supply voltage, V CC , due to the non-ideal output impedance of the parallel amplifier  35 . 
     In contrast, when the controller  50  configures the estimated switching voltage output selection switch  816 , S 1 , to provide the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as the estimated switching voltage input signal  820 , V SW     —     I , the controller  50  may adjust the delay provided by the programmable delay circuitry  806  to temporally align the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , with the V RAMP  signal. 
     The Z OUT  compensation high pass filter  824  high pass filters the expected difference signal  834  to generate an estimated high frequency ripple signal  836  that may be scaled by the G CORR  scalar circuit  826  to create the high frequency ripple compensation signal  838 . The high frequency ripple compensation signal  838  is added to the analog pre-filtered V RAMP  signal  814 A, V RAMP     —     ANALOG     —     PRE-FILTERED , to form the compensated V RAMP  signal, V RAMP     —     C . The compensated V RAMP  signal, V RAMP     —     C , is provided as an input to the parallel amplifier  35 . The parallel amplifier  35  generates the parallel amplifier output voltage, V PARA     —     AMP , based on the difference between the compensated V RAMP  signal, V RAMP     —     C , and the power amplifier supply voltage, V CC , at the power amplifier supply output  28 . 
     The operation, configuration, and calibration of the tune circuit  830  of the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , is substantially similar to the operation of the tune circuit  830  previously described with respect to the embodiment of the parallel amplifier output impedance compensation circuit  37 B, depicted in  FIG. 5A . As such, a detailed description of the operation of the tune circuit  830  herein is omitted. 
       FIG. 5D  depicts an example embodiment of a pseudo-envelope follower power management system  10 PD that is similar to the pseudo-envelope follower power management system  10 PC, depicted in  FIG. 5C . However, the pseudo-envelope follower power management system  10 PD includes a parallel amplifier circuit  14 PD. The parallel amplifier circuit  14 PD includes a parallel amplifier output impedance compensation circuit  37 E configured to provide the compensated V RAMP  signal, V RAMP     —     C  to the parallel amplifier  35 . Similar to the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , the parallel amplifier output impedance compensation circuit  37 E includes an analog V RAMP  pre-distortion filter circuit  844  configured to receive the V RAMP  signal in the analog domain. In addition, as previously described with respect to the analog V RAMP  pre-distortion filter circuit  844 , the controller  50  may configure the frequency response of the analog V RAMP  pre-distortion filter circuit  844  to pre-distort the received the V RAMP  signal. 
     Illustratively, as described before, the first time constant, τ ZERO     —     PRE , and second time constant, τ POLE     —     PRE , may be adjusted by the controller  50  to provide peaking of the V RAMP  signal in order to equalize the overall frequency response between the first control input  34 , which received the V RAMP  signal, and the power amplifier collector  22 A of a linear RF power amplifier  22 . The controller  50  may configure the frequency response of the analog V RAMP  pre-distortion filter circuit  844  to equalize the response of the pseudo-envelope follower power management system  10 PD by adjusting the value of the programmable time constants of the analog V RAMP  pre-distortion filter circuit  844 , as previously described. In addition, similar to the parallel amplifier output impedance compensation circuit  37 D, the controller  50  may configure the analog V RAMP  pre-distortion filter circuit  844  of the parallel amplifier output impedance compensation circuit  37 E to pre-distort the frequency response of the V RAMP  signal such that the overall transfer function between the first control input  34 , which received the V RAMP  signal, and the power amplifier collector  22 A of the linear RF power amplifier  22  is substantially flat through the operating frequency range of the linear RF power amplifier  22 . For example, as described above, the controller  50  may configure the analog V RAMP  pre-distortion filter circuit  844  to provide frequency peaking to compensate for the low pass filter response due to the combination of the power amplifier associated inductance, L PA , (not shown) and the power amplifier filter associated capacitance, C PA , (not shown) associated with the linear RF power amplifier  22 . 
     However, unlike the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 5D , is configured to provide a high frequency ripple compensation signal  838  to generate the compensated V RAMP  signal, V RAMP     —     C , in a fashion that is similar to the parallel amplifier output impedance compensation circuit  37 C, depicted in  FIG. 5B , where the scaling factor, G CORR , is provided by the G CORR  function circuit  842 . Thus, similar to the parallel amplifier output impedance compensation circuit  37 C, depicted in  FIG. 5B , the parallel amplifier output impedance compensation circuit  37 E includes a G CORR  function circuit  842  configured to provide the scaling factor, G CORR , to the G CORR  scalar circuit  826 . The form and function of the G CORR  function circuit  842  of the parallel amplifier output impedance compensation circuit  37 E is similar to the operation of the G CORR  function circuit  842  of parallel amplifier output impedance compensation circuit  37 C, depicted in  FIG. 5B . 
     Accordingly, the parallel amplifier output impedance compensation circuit  37 E, may include an estimated switching voltage output selection switch  816 , S 1 , having a first input  816 A configured to receive the estimated switching voltage output  38 B, V SW     —     EST , a second input  816 B configured to receive the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , and an estimated switching voltage output selection switch output  816 C. The controller  50  may configure the estimated switching voltage output selection switch  816 . S 1 , to provide either the estimated switching voltage output  38 B, V SW     —     EST , or the second input configured to receive the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as an estimated switching voltage input signal  820 , V SW     —     I , at the estimated switching voltage output selection switch output  816 C. As discussed above, if the controller  50  configures the estimated switching voltage output selection switch  816 , S 1 , to provide the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , the controller  50  may configure the delay provided by the programmable delay circuitry  806  to temporally optimize the relationship between the estimated switching voltage input signal  820 , V SW     —     I , and the V RAMP  signal to minimize the high frequency voltage ripple generated as a result of the non-ideal output impedance characteristics of the parallel amplifier  35 . 
     Similar to the parallel amplifier output impedance compensation circuit  37 C, the parallel amplifier output impedance compensation circuit  37 E also includes the first subtracting circuit  822 , the Z OUT  compensation high pass filter  824 , the G CORR  scalar circuit  826 , and the summing circuit  832 . The first subtracting circuit  822  is configured to subtract the estimated switching voltage input signal  820 , V SW     —     I , from the V RAMP  signal to generate an expected difference signal  834 , which is provided to the Z OUT  compensation high pass filter  824 . Similar to the operation of the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , the controller  50  may configure the programmable time constants associated with the Z OUT  compensation high pass filter  824  to high pass filter the expected difference signal  834  in order to generate an estimated high frequency ripple signal  836 , which is scaled by the G CORR  scalar circuit  826  to create the high frequency ripple compensation signal  838 . 
     Unlike the parallel amplifier output impedance compensation circuit  37 D, depicted in  FIG. 5C , the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 5D , provides the scaling factor, G CORR , to the G CORR  scalar circuit  826  from the G CORR  function circuit  842 . The G CORR  function circuit  842  of the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 5D , is similar in form and function to the G CORR  function circuit  842  of the parallel amplifier output impedance compensation circuit  37 C, depicted in  FIG. 5B . For example, the G CORR  function circuit  842  of the parallel amplifier output impedance compensation circuit  37 E may be configured to receive the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , generated by the parallel amplifier sense circuit  36  of the parallel amplifier circuitry  32 . In some embodiments of the parallel amplifier output impedance compensation circuit  37 E, the G CORR  function circuit  842  provides the scaling factor, G CORR , to the G CORR  scalar circuit  826  as a function of the scaled parallel amplifier output current estimate, I PARA     —     AMP     —     SENSE , as previously described with respect to the parallel amplifier output impedance compensation circuit  37 C, depicted in  FIG. 5B . Alternatively, in some embodiments of the parallel amplifier output impedance compensation circuit  37 E, the G CORR  function circuit  842  may be configured by the controller  50  to provide the scaling factor, G CORR , based on the ratio of the parallel amplifier inductance estimate parameter, L CORR     —     EST , to the estimated power inductor inductance parameter, L EST , of the pseudo-envelope follower power management system  10 PD, as described in equation (9), which is described above. 
     Alternatively, in some embodiments of the parallel amplifier output impedance compensation circuit  37 E, the controller  50  characterizes the G CORR  function circuit  842  during either calibration of the pseudo-envelope follower power management system  10 PD as described relative to the parallel amplifier output impedance compensation circuit  37 C depicted in  FIG. 5B , the details of which are omitted here for the sake of brevity. 
       FIG. 5E  depicts an example embodiment of a pseudo-envelope follower power management system  10 PE that is similar to the pseudo-envelope follower power management system  10 PD, depicted in  FIG. 5D . However, the pseudo-envelope follower power management system  10 PE includes a parallel amplifier circuit  14 PE. The parallel amplifier circuit  14 PE includes a parallel amplifier output impedance compensation circuit  37 F that is similar to the parallel amplifier output impedance compensation circuit  37 E. However, unlike the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 5D , the parallel amplifier output impedance compensation circuit  37 F, depicted in  FIG. 5E , applies a parallel amplifier output impedance correction signal  838 A to the V RAMP  signal prior to applying equalization of the input signal provided to the parallel amplifier  35 . 
     Similar to the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 5D , the parallel amplifier output impedance compensation circuit  37 E, depicted in  FIG. 34F , may include an estimated switching voltage output selection switch  816 , S 1 , having a first input  816 A configured to receive the estimated switching voltage output  38 B, V SW     —     EST , a second input  816 B configured to receive the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED . The controller  50  may configure the estimated switching voltage output selection switch  816 , S 1 , to provide either the estimated switching voltage output  38 B, V SW     —     EST , or the delayed estimated switching voltage output  38 D, V SW     —     EST     —     DELAYED , as the estimated switching voltage input signal  820 , V SW     —     I , to the first subtracting circuit  822 . The first subtracting circuit  822  is configured to subtract the estimated switching voltage input signal  820 , V SW     —     1 , from the V RAMP  signal to generate an expected difference signal  834 , which is provided to the Z OUT  compensation high pass filter  824 . As previously described, the controller  50  may configure the programmable time constants associated with the Z OUT  compensation high pass filter  824  to high pass filter the expected difference signal  834  in order to generate an estimated high frequency ripple signal  836 . The estimated high frequency ripple signal  836  is then scaled by the G CORR  scalar circuit  826  based on the scaling factor, G CORR , received from the G CORR  function circuit  842  to generate the high frequency ripple compensation signal  838 . The operation and configuration of the G CORR  function circuit  842 , depicted in  FIG. 5E , is similar in form and function as the G CORR  function circuit  842 , previously described and depicted in  FIG. 5B  and  FIG. 5D , and therefore a detailed description of the calibration, function and operation of the G CORR  function circuit  842  is hereby omitted. 
     Unlike the previously described embodiments of the parallel amplifier output impedance compensation circuits  37 B-E, depicted in  FIG. 5A-D , the parallel amplifier output impedance compensation circuit  37 F, depicted in  FIG. 5E , includes a pre-distortion subtraction circuit  846  configured to subtract the high frequency ripple compensation signal  838  from the V RAMP  signal prior to pre-distorting the V RAMP  signal to form a non-filtered parallel amplifier output impedance compensated signal  848 . The non-filtered parallel amplifier output impedance compensated signal  848  represents a V RAMP  signal that has been compensated to take into consideration the non-ideal output impedance characteristics of the parallel amplifier  35 . The parallel amplifier output impedance compensation circuit  37 F further includes a V RAMP  post-distortion filter circuit  850  configured to filter the non-filtered parallel amplifier output impedance compensated signal  848  to generate the compensated V RAMP  signal, V RAMP     —     C . 
     The V RAMP  post-distortion filter circuit  850  may have a Laplace transfer function similar to the transfer function described by equation (11), as follows: 
                       H   ⁡     (   s   )           V   RAMP     ⁢   Post   ⁢     -     ⁢   Distortion   ⁢           ⁢   Filter   ⁢           ⁢   Circuit       =       (     1   +       τ   ZERO_POST     ⁢   s       )       (     1   +       τ   POLE_POST     ⁢   s       )               (   11   )               
where, τ ZERO     —     POST , is a first post distortion time constant associated with zero in the V RAMP  post-distortion filter circuit  850  and, τ POLE     —     POST , is a second post distortion time constant associated with pole of the V RAMP  post-distortion filter circuit  850 . The first post distortion time constant, τ ZERO     —     POST , and the second post distortion time constant, τ POLE     —     POST , may be configured to distort the non-filtered parallel amplifier output impedance compensated signal  848  to equalize the overall modulation frequency response of the pseudo-envelope follower power management system  10 PE. As an example, similar to the analog V RAMP  pre-distortion filter circuit  844 , depicted in  FIG. 5C  and  FIG. 5D , the controller  50  may be configured to adjust the first post distortion time constant, τ ZERO     —     POST , and the second post distortion time constant, τ POLE     —     POST , to provide peaking of the non-filtered parallel amplifier output impedance compensation signal  848  in order to equalize the overall modulation frequency response of the pseudo-envelope follower power management system  10 PE, depicted in  FIG. 5E , as well as the low pass filtering characteristics of the combination of the power amplifier associated inductance, L PA , (not shown), and the power amplifier filter associated capacitance, C PA , (not shown). The controller  50  may configure the first post distortion time constant, τ ZERO     —     POST , and the second post distortion time constant, τ POLE     —     POST , such that the transfer function of the V RAMP  post distortion filter circuit  850  is based on the RF modulation bandwidth of the linear RF power amplifier  22  associated with a wide-bandwidth modulation of a mode of operation of an electronic device or mobile terminal that includes the pseudo-envelope follower power management system  10 PE. As an example, the controller  50  may configure the first post distortion time constant, τ ZERO     —     PRE , and the second post distortion time constant, τ POLE     —     POST , to provide peaking of the non-filtered parallel amplifier output impedance compensation signal  848  in order to flatten the overall modulation frequency response of the pseudo-envelope follower power management system  10 PE based on the wide-bandwidth modulation of a mode of operation of electronic device or mobile terminal.
 
     Those skilled in the art will recognize improvements and modifications to the embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.