Patent Publication Number: US-2023141221-A1

Title: Volatile memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority from Korean Patent Application No. 10-2021-0153886 filed on Nov. 10, 2021 in the Korean Intellectual Property Office, and all the benefits accruing therefrom under 35 U.S.C. § 119, the contents of which in its entirety are herein incorporated by reference. 
     BACKGROUND 
     Some example embodiments relate to a volatile memory device, and more particularly, to a volatile memory device having an open bit line structure. 
     A semiconductor memory device for storing data may be broadly divided into a volatile memory device and a non-volatile memory device. Ina volatile memory device, such as a dynamic random access memory (DRAM) in which data is stored by charging or discharging a cell capacitor, stored data is maintained while power is applied to the volatile memory device, but the stored data is lost when power is cut off. Meanwhile, a non-volatile memory device may store data even when power is cut off. The volatile memory device is mainly used as a main memory of a computer and the like, and the non-volatile memory device is used as a massive memory for storing programs and data in a wide range of application devices, such as computers and portable communication devices. 
     The volatile memory device may have an open bit line structure or a folded bit line structure. A sense amplifier of the volatile memory device having the above-mentioned structures may have a pair of bit lines corresponding to each other. The volatile memory device having the open bit line structure may include an unnecessary mat according to characteristics of the structure thereof. 
     SUMMARY 
     Some example embodiments provide a memory device such as a volatile memory device capable of having a reduced area. 
     Alternatively or additionally, some example embodiments provide a memory device such as a volatile memory device capable of having an increased cell density. 
     However, aspects of example embodiments are not restricted to those set forth herein. The above and other aspects of example embodiments will become more apparent to one of ordinary skill in the art by referencing the detailed description given below. 
     According to some example embodiments, there is provided a volatile memory device capable of having a reduced area. The volatile memory device comprises a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier, a first normal mat between the first sense amplifier and the second sense amplifier and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, and a first reference mat on the first normal mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier and a second complementary bit line connected to the second sense amplifier. 
     According some example embodiments, there is provided a memory device such as a volatile memory device comprising a first sense amplifier, a second sense amplifier and a third sense amplifier that are sequentially spaced apart from the first sense amplifier in a first direction, a first mat between the first sense amplifier and the second sense amplifier, and including a first bit line connected to the first sense amplifier and a second bit line connected to the second sense amplifier, a second mat on the first mat between the first sense amplifier and the second sense amplifier, and including a first complementary bit line connected to the first sense amplifier, and a third mat between the second sense amplifier and the third sense amplifier, and including a second complementary bit line connected to the second sense amplifier. 
     According to some example embodiments, there is provided a memory device such as a volatile memory device comprising a plurality of memory banks, a row decoder having a first memory bank of the plurality of memory banks, the first row decoder extending in a first direction, a column decoder extending in a second direction orthogonal to the first direction, a bank memory array arranged in the second direction from the row decoder and arranged in the first direction from the column decoder, and a first sense amplifier at a first edge portion of the bank memory array in a third direction opposite to the first direction, wherein the bank memory array includes a first normal mat spaced apart from the first sense amplifier in the first direction and including a first bit line connected to the first sense amplifier, and a first reference mat spaced apart from the first normal matin the third direction, and including a first complementary bit line connected to the first sense amplifier. 
     According to some example embodiments, there is provided a memory device such as a volatile memory device comprising a first sense amplifier, a second sense amplifier spaced apart from the first sense amplifier in a first direction, a first bit line connected to the first sense amplifier between the first sense amplifier and the second sense amplifier and extending in the first direction, a first metal line connected to the first sense amplifier and extending in a second direction intersecting the first direction, a first complementary bit line spaced apart from the first bit line in the second direction and connected to the first sense amplifier through the first metal line, a second bit line connected to the second sense amplifier between the first sense amplifier and the second sense amplifier and extending in the second direction, and a plurality of word lines extending in a third direction intersecting the first direction and the second direction between the first sense amplifier and the second sense amplifier and connected to the first bit line, the first complementary bit line, and the second bit line. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects and features will become more apparent by describing in detail various example embodiments thereof with reference to the attached drawings, in which: 
         FIG.  1    is a block diagram illustrating a memory system according to some example embodiments. 
         FIG.  2    is a block diagram of the memory device of  FIG.  1   . 
         FIG.  3    is a plan view of a memory device according to some example embodiments. 
         FIGS.  4  and  5    are enlarged views of the second memory bank of  FIG.  3   . 
         FIG.  6    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  7    is a circuit diagram of a sense amplifier and a plurality of memory cells of  FIG.  6   . 
         FIG.  8    is a top view of a first normal mat of a first layer of  FIG.  6   . 
         FIG.  9    is a top view of a first reference mat of a second layer of  FIG.  6   . 
         FIG.  10    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  11    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  12    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  13    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  14    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  15    is a three-dimensional view of the memory device according to some example embodiments. 
         FIG.  16    is a block diagram illustrating a memory system according to some example embodiments. 
         FIG.  17    is a diagram of a semiconductor package according to some example embodiments. 
         FIG.  18    is a diagram illustrating an example of implementation of a semiconductor package according to some example embodiments. 
         FIG.  19    is a diagram of a semiconductor package according to some example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF VARIOUS EXAMPLE EMBODIMENTS 
     Hereinafter, example embodiments will be described with reference to the attached drawings. 
       FIG.  1    is a block diagram illustrating a memory system according to some example embodiments. 
     Referring to  FIG.  1   , the memory system may include a host device  20  and a memory storage device  1 . The memory storage device  1  may include a memory device  100  and a memory controller  10 . 
     The memory controller  10  may control an overall operation of the memory device  100 . For example, the memory controller  10  may control data exchange between the external host device  20  and the memory device  100 . For example, the memory controller  10  may control the memory device  100  according to a request from the host device  20 , and may write data and/or read data through such control. 
     The memory controller  10  and the memory device  100  may communicate through a memory interface MEM  1 /F. Alternatively or additionally, the memory controller  10  and the external host device  20  may communicate through a host interface. For example, the memory controller  10  may mediate a signal between the memory device  100  and the host device  20 . The memory controller  10  may control the operation of the memory device  100  by applying a command CMD for controlling the memory device  100  to the memory device  100 . Here, the memory device  100  may include dynamic memory cells. For example, the memory device  100  may include one or more of a dynamic random access memory (DRAM), a double data rate 4 (DDR4) synchronous DRAM (SDRAM), a low power DDR4 (LPDDR4) SDRAM, or an LPDDR5 SDRAM. However, example embodiments are not limited thereto, and the memory device  100  may include a non-volatile memory device. However, in various example embodiments, the memory device  100  will be described as a volatile memory device. 
     The memory controller  10  may transmit a clock signal CLK, a command CMD, an address ADDR, and the like to the memory device  100 . The memory controller  10  may provide data DQ to the memory device  100  and receive data DQ from the memory device  100 . The memory device  100  may include a memory cell array  200  in which the data DQ is stored, a control logic circuit  110 , a data input/output buffer  195 , and the like. 
       FIG.  2    is a block diagram of the memory device of  FIG.  1   . 
     Referring to  FIG.  2   , the memory device  100  may include a control logic circuit  110 , an address register  120 , a bank control logic circuit  130 , a row address multiplexer  140 , a refresh counter  145 , a column address latch  150 , a row decoder  160 , a column decoder  170 , a memory cell array  200 , a sense amplifier  300 , an input/output gating circuit  190 , an ECC engine  191 , a data input/output buffer  195 , and the like. 
     The memory cell array  200  may include a plurality of bank arrays. The row decoder  160  may be connected to the plurality of bank arrays. The column decoder  170  may be connected to the plurality of bank arrays. The sense amplifier  300  may be respectively connected to the plurality of bank arrays. The memory cell array  200  may include a plurality of word lines, a plurality of bit lines, and a plurality of memory cells formed at intersections of the word lines and the bit lines. 
     The address register  120  may receive an address ADDR from the memory controller  10 . The address ADDR may include a bank address BANK_ADDR, a row address ROW_ADDR, a column address COL_ADDR, and/or the like. The address register  120  may provide the bank address BANK_ADDR to the bank control logic circuit  130 . The address register  120  may provide the row address ROW_ADDR to the row address multiplexer  140 . The address register  120  may provide the column address COL_ADDR to the column address latch  150 . 
     The bank control logic circuit  130  may generate a bank control signal in response to the bank address BANK_ADDR. The bank row decoder  160  may be activated in response to the bank control signal. Alternatively or additionally, the column decoder  170  may be activated in response to the bank control signal corresponding to the bank address BANK_ADDR. 
     The mw address multiplexer  140  may receive a row address ROW_ADDR from the address register  120 , and may receive a refresh row address REF_ADDR from the refresh counter  145 . The row address multiplexer  140  may select one of the row address ROW_ADDR and the refresh row address REF_ADDR and output the selected one as a row address RA. The row address RA may be transmitted to the row decoder  160 . 
     The refresh counter  145  may sequentially output the refresh row address REF_ADDR according to the control of the control logic circuit  110 . 
     The row decoder  160  activated by the bank control logic circuit  130  may decode the row address RA output from the row address multiplexer  140  to activate a word line corresponding to the row address RA. For example, the row decoder  160  may apply a word line driving voltage to the word line corresponding to the row address RA. 
     The column address latch  150  may receive the column address COL_ADDR from the address register  120  and temporarily store the received column address COL_ADDR. The column address latch  150  may gradually increase the received column address COL_ADDR in or during a burst mode. The column address latch  150  may provide the temporarily stored column address COL_ADDR or the gradually increased column address COL_ADDR to the column decoder  170 . 
     Among the column decoders  170 , the column decoder  170  activated by the bank control logic circuit  130  may activate the sense amplifier  300  corresponding to the bank address BANK_ADDR and the column address COL_ADDR through the corresponding input/output gating circuit  190 . 
     The input/output gating circuit  190  may include a circuit for gating input/output data, input data mask logic, read data latches for storing data output from the memory cell array  200 , and write drivers for writing data into the memory cell array  200 . 
     A codeword CW read from the bank array of the memory cell array  200  may be sensed by the sense amplifier  300  corresponding to the bank array. Alternatively or additionally, the codeword CW may be stored in the read data latch. The ECC engine  191  may perform ECC decoding on the codeword CW stored in the read data latch, and the data DQ on which the ECC decoding is performed may be provided to the memory controller  10  through the data input/output buffer  195 . 
     The data input/output buffer  195  may provide the data DQ to the ECC engine  191  based on the clock signal CLK in or during a write operation. The data input/output buffer  195  may provide the data DQ provided from the ECC engine  191  to the memory controller  10  based on the clock signal CLK in a read operation. 
     The memory cell array  200  may be connected to the sense amplifier  300 , and the row decoder  160  and the column decoder  170  may be connected to the memory cell array  200  and the sense amplifier  300 . In this case, the plurality of bit lines included in the memory cell array  200  may be connected to the sense amplifier  300  in an open bit line structure. This will be described in more detail. 
       FIG.  3    is a plan view of a memory device according to some example embodiments. 
     Referring to  FIG.  3   , the memory device  100  may include a plurality of bank memory arrays BMA 1  to BMA 16 , a row decoder  160 , a column decoder  170 , and a peripheral circuit region PERI. 
     In some example embodiments, the memory device  100  may be disposed on a plane extending in a first direction X and a second direction Y. For example, the memory device  100  may extend in the first direction X and the second direction Y. In some example embodiments, the memory device  100  may have a rectangular shape when viewed from the top. 
     The memory device  100  may include sixteen bank memory arrays BMA 1  to BMA 16 . Here, the sixteen bank memory arrays BMA 1  to BMA 16  may process 1 Gb of data. However, example embodiments are not limited thereto, and the memory device  100  may include a different number of bank memory arrays BMA 1  to BMA 16 . The bank memory arrays BMA 1  to BMA 16  may be regularly arranged. For example, the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth bank memory arrays BMA 1 , BMA 3 , BMA 5 , BMA 7 , BMA 9 , BMA 11 , BMA 13 , and BMA 15  may be sequentially arranged along a direction opposite to the second direction Y. and the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth bank memory arrays BMA 2 , BMA 4 , BMA 6 , BMA 8 , BMA 10 , BMA 12 , BMA 14 , and BMA 16  may be sequentially arranged along a direction opposite to the second direction Y. Alternatively or additionally, the second, fourth, sixth, eighth, tenth, twelfth, fourteenth, and sixteenth bank memory arrays BMA 2 , BMA 4 , BMA 6 , BMA 8 , BMA 10 , BMA 12 , BMA 14 , and BMA 16  may be spaced apart in the first direction X from the first, third, fifth, seventh, ninth, eleventh, thirteenth, and fifteenth bank memory arrays BMA 1 , BMA 3 , BMA 5 , BMA 7 , BMA 9 , BMA 11 , BMA 13 , and BMA 15 . 
     The row decoder  160  may extend in the first direction X and may be disposed between the plurality of bank memory arrays BMA 1  to BMA 16 . For example, the row decoder  160  may be disposed between the first bank memory array BMA 1  and the third bank memory array BMA 3 . The column decoder  170  may extend in the second direction Y, and may be disposed at one side of the plurality of bank memory arrays BMA 1  to BMA 16 . For example, the column decoder  170  may be disposed in the first direction X from the first bank memory array BMA 1 . Alternatively or additionally, the row decoder  160  may intersect the column decoder  170 . Alternatively or additionally, the plurality of bank memory arrays BMA 1  to BMA 16  may be surrounded by the row decoder  160  and the column decoder  170 . 
     The peripheral circuit region PERI may be disposed in a portion of the memory device  100  except for the plurality of bank memory arrays BMA 1  to BMA 16 , the row decoder  160 , and the column decoder  170 . Here, the peripheral circuit region PERI may include the control logic circuit  110 , the address register  120 , the bank control logic circuit  130 , the row address multiplexer  140 , the refresh counter  145 , the column address latch  150 , the input/output gating circuit  190 , the ECC engine  191 , and the data input/output buffer  195  of  FIG.  2   . 
     Here, one of the bank memory arrays BMA 1  to BMA 16  may include the memory cell array  200  and a part of the sense amplifier  300 , but example embodiments are not limited thereto. One of the bank memory arrays BMA 1  to BMA 16  may include a first edge portion EDG 1  and a second edge portion EDG 2 . For example, the second bank memory array BMA 2  may include a first edge portion EDG 1  in a direction opposite to the first direction X and a second edge portion EDG 2  in the first direction X. 
     The memory bank may be defined by one of the bank memory arrays BMA 1  to BMA 16 , one row decoder  160 , and one column decoder  170 . For example, a second memory bank BNK 2  may be defined by the second bank memory array BMA 2 , the row decoder  160 , and the column decoder  170 . Here, the memory bank may correspond to a storage unit indicating one bank address. 
       FIGS.  4  and  5    are enlarged views of the second memory bank of  FIG.  3   . 
     Referring to  FIGS.  4  and  5   , the second memory bank BNK 2  may include a row decoder  160 , a column decoder  170 , and a second bank memory array BMA 2  surrounded by the row decoder  160  and the column decoder  170 . Here, the second bank memory array BMA 2  may include a plurality of sense amplifiers SA 1  to SA(2m) and a plurality of mats MAT 1  to MATm. 
     The plurality of mats MAT 1  to MATm may be disposed between the plurality of sense amplifiers SA 1  to SA(2m). For example, the first mat MAT 1  may be disposed between the first sense amplifier SA 1  and the second sense amplifier SA 2 . Alternatively or additionally, the m-th mat MATm may be disposed between the (2m−1)-th sense amplifier SA(2m−1) and the (2m)-th sense amplifier SA(2m). As used herein, a mat may include a cell array in which each cell is connected to a word line and a bit line. The mat may also include column and/or word line drivers connected to the word lines. For example, a mat may be or may include one or more subarrays of cells. The plurality of mats MAT 1  to MATm and the plurality of sense amplifiers SA 1  to SA(2m) may extend in the second direction Y. 
     Each of the sense amplifiers SA 1  to SA(2m) may include a plurality of sub sense amplifiers arranged in the second direction Y. For example, the first sense amplifier SA 1  may include first sub sense amplifiers SA 11  to SAn 1  arranged in the second direction Y. Alternatively or additionally, the second sense amplifier SA 2  may include second sub sense amplifiers SA 12  to SAn 2 , the third sense amplifier SA 3  may include third sub sense amplifiers SA 13  to SAn 3 , and the fourth sense amplifier SA 4  may include fourth sub sense amplifiers SA 14  to SAn 4 . Alternatively or additionally, the (2m−1)-th sense amplifier SA(2m−1) may include (2m−1)-th sub sense amplifiers SA 1 (2m−1) to SAn(2m−1)), and the (2m)-th sense amplifier SA(2m) may include (2m)-th sub sense amplifiers SA 1 (2m) to SAn(2m). 
     Each of the mats MAT 1  to MATm may include a plurality of sub-memory arrays arranged in the second direction Y. For example, the first mat MAT 1  may include first sub-memory arrays SMA 11  to SMAn 1  arranged in the second direction Y, the second mat MAT 2  may include second sub-memory arrays SMA 21  to SMAn 2 , and the m-th mat MATm may include m-th sub-memory arrays SMA 1   m  to SMAnm. 
     In some example embodiments, the plurality of mats MAT 1  to MATm and the plurality of sense amplifiers SA 1  to SA(2m) may be formed in units of memory. For example, the first mat MAT 1 , the first sense amplifier SA 1 , and the second sense amplifier SA 2  may be formed in units of single memory. For example, the first and second sense amplifiers SA 1  and SA 2  may perform a write or read operation on memory cells included in the first mat MAT 1 . The first and second sense amplifiers SA 1  and SA 2  may be connected to the bit lines BL included in the first mat MAT 1  and read a voltage applied thereto, or apply a voltage to the bit lines BL. 
     Alternatively or additionally, a word line WL included in the first mat MAT 1  may be connected to the column decoder  170  or the peripheral circuit region PER 1 , and the column decoder  170  may select a memory cell by applying a voltage to the word line WL. Here, the bit line BL and the word line WL may intersect each other. The memory cell may be formed between the bit line BL and the word line WL. 
     Alternatively or additionally, in some example embodiments, the plurality of sub-memory arrays SMA 11  to SMAnm and the plurality of sub sense amplifiers SA 11  to SAn(2m) may be formed in units of memory. For example, the first sub-memory array SMA 11 , the first sub sense amplifier SA 11 , and the second sub sense amplifier SA 12  may be formed in units of single memory. For example, the first sub sense amplifier SA 11  and the second sub sense amplifier SA 12  may perform a write and/or read operation on memory cells included in the first sub-memory array SMA 11 . 
     In some example embodiments, the first sense amplifier SA 1  may be disposed on the first edge portion EDG 1 , and the (2m)-th sense amplifier SA(2m) may be disposed on the second edge portion EDG 2 . For example, the first sense amplifier SA 1  may be positioned in a region closest to the column decoder  170  in the second bank memory array BMA 2 , and the (2m)-th sense amplifier SA(2m) may be positioned in a region farthest from the column decoder  170  in the second bank memory array BMA 2 . Hereinafter, the sense amplifiers SA 1  to SA(2m) and the mats MAT 1  to MATm will be described in more detail with reference to  FIGS.  6  to  9   .  FIGS.  6  to  9    describe the first sense amplifier SA 1 , the second sense amplifier SA 2 , and the first mat MAT 1 , but the description may be equally applied to other sense amplifiers SA 3  to SA(2m) and mats MAT 2  to MATm. 
       FIG.  6    is a three-dimensional view of the memory device according to some example embodiments.  FIG.  7    is a circuit diagram of a sense amplifier and a plurality of memory cells of  FIG.  6   .  FIG.  8    is a top view of a first normal mat of a first layer of  FIG.  6   .  FIG.  9    is a top view of a first reference mat of a second layer of  FIG.  6   . 
     Referring to  FIG.  6   , the memory device  100  may include the first sense amplifier SA 1 , the second sense amplifier SA 2 , and the first mat MAT 1 . Here, the first sense amplifier SA 1  may include the plurality of first sub sense amplifiers SA 11  to SAn 1  described with reference to  FIG.  4   , and the second sense amplifier SA 2  may include a plurality of second sub sense amplifiers SA 12  to SAn 2 . Alternatively or additionally, the first mat MAT 1  may include a plurality of first sub-memory arrays SMA 11  to SMAn 1 . Alternatively or additionally, the first mat MAT 1  may include a first normal mat NMAT 1  and a first reference mat RMAT 1 . 
     The first sense amplifier SA 1  may extend in the second direction Y, and the second sense amplifier SA 2  may extend in the second direction Y. Alternatively or additionally, the second sense amplifier SA 2  may be disposed to be spaced apart from the first sense amplifier SA 1  in the first direction X. Although the first and second sense amplifiers SA 1  and SA 2  in  FIG.  6    are expressed as a rectangular parallelepiped, such a shape is merely an example, and example embodiments are not limited thereto. The first sense amplifier SA 1  may be disposed at the first edge portion EDG 1 . For example, the first sense amplifier SA 1  may extend along the first edge portion EDG 1 . 
     The first normal mat NMAT 1  of the first mat MAT 1  may be disposed between the first sense amplifier SA 1  and the second sense amplifier SA 2 . For example, the first normal mat NMAT 1  may be disposed on the same plane as the first and second sense amplifiers SA 1  and SA 2 . For example, the first normal mat NMAT 1  may be disposed on a substrate on which the first and second sense amplifiers SA 1  and SA 2  are positioned. Although the first normal mat NMAT 1  is expressed as a rectangular parallelepiped, example embodiments am not limited thereto. 
     The first reference mat RMAT 1  of the first mat MAT 1  may be disposed above the first normal mat NMAT 1 . For example, the first reference mat RMAT 1  may be disposed to be spaced apart from the first normal mat NMAT 1  in a third direction Z. Here, the third direction Z may correspond to a direction intersecting both the first direction X and the second direction Y. The first reference mat RMAT 1  may be positioned above the first normal mat NMAT 1 , the first sense amplifier SA 1 , and the second sense amplifier SA 2 . For example, the first normal mat NMAT 1 , the first sense amplifier SA 1 , and the second sense amplifier SA 2  may be disposed on a first layer of the bank memory array, and the first reference mat RMAT 1  may be disposed on a second layer of the bank memory array. The first reference mat RMAT 1  may be positioned on a different substrate from the substrate on which the first normal mat NMAT 1 , the first sense amplifier SA 1 , and the second sense amplifier SA 2  are disposed. 
     The first normal mat NMAT 1  may include first to n-th bit lines BL 11  to BL 1   n  and first to n-th bit lines BL 21  to BL 2   n . The first to n-th bit lines BL 11  to BL 1   n  may be connected to the first sense amplifier SA 1 , and the first to n-th bit lines BL 21  to BL 2   n  may be connected to the second sense amplifier SA 2 . The first to n-th bit lines BL 11  to BL 1   n  and the first to n-th bit lines BL 21  to BL 2   n  may extend in the first direction X. 
     The first to n-th bit lines BL 11  to BL 1   n  and the first to n-th bit lines BL 21  to BL 2   n  may be spaced apart from each other in the second direction Y. For example, the first to n-th bit lines BL 11  to BL 1   n  may be spaced apart from each other in the second direction Y, and the first to n-th bit lines BL 21  to BL 2   n  may also be spaced apart from each other in the second direction Y. The first to n-th bit lines BL 11  to BL 1   n  and the first to n-th bit lines BL 21  to BL 2   n  may be alternately disposed or arranged. For example, the first bit line BL 11  may be disposed to be spaced apart from the first bit line BL 2   l  in the second direction Y. and the n-th bit line BL 1   n  may be disposed to be spaced apart from the n-th bit line BL 2   n  in the second direction Y. 
     Although not illustrated in  FIG.  6   , the first normal mat NMAT 1  may include a plurality of word lines intersecting the first to n-th bit lines BL 11  to BL 1   n  and the first to n-th bit lines BL 21  to BL 2   n . In addition, the plurality of memory cells may be connected between the first to n-th bit lines BL 11  to BL 1   n  and the first to n-th bit lines BL 21  to BL 2   n , and the plurality of word lines. 
     The first reference mat RMAT 1  may include first to n-th complementary bit lines BLB 11  to BLB 1   n  and first to n-th complementary (or barred) bit lines BLB 21  to BLB 2   n . The first to n-th complementary bit lines BLB 11  to BLB 1   n  may be connected to the first sense amplifier SA 1 , and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may be connected to the second sense amplifier SA 2 . The first to n-th complementary bit lines BLB 11  to BLB 1   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may extend in the first direction X. 
     The first to n-th complementary bit lines BLB 11  to BLB 1   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may be spaced apart from each other in the second direction Y. Alternatively or additionally, the first to n-th complementary bit lines BLB 11  to BLB 1   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may be alternately disposed. 
     Although not illustrated in  FIG.  6   , the first reference mat RMAT 1  may include a plurality of word lines intersecting the first to n-th complementary bit lines BLB 11  to BLB 1   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n . Alternatively or additionally, the plurality of memory cells may be connected between the first to n-th complementary bit lines BLB 11  to BLB 1   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n , and the plurality of word lines. 
     First to n-th metal lines ML 1  to ML 1   n  may extend in the third direction Z. The first to n-th metal lines ML 11  to ML 1   n  may connect the first sense amplifier SA 1  and the first to n-th complementary bit lines BLB 1  to BLB 1   n . For example, the first to n-th metal lines ML 11  to ML 1   n  may connect the first sense amplifier SA 1  and the first reference mat RMAT 1 . The first sense amplifier SA 1  and the first reference mat RMAT 1  may be three-dimensionally connected through the first to n-th metal lines ML 11  to ML 1   n . Accordingly, the memory device  100  including the first normal mat NMAT 1  and the first reference mat RMAT 1  may have a plurality of stack memory structure, such as a two-stack memory structure. 
     The first sense amplifier SA 1  may be connected to all of the first to n-th bit lines BLi 1  to BL 1   n  included in the first normal mat NMAT 1  and the first to n-th complementary bit lines BLB 11  to BLB 1   n  included in the first reference mat RMAT 1 . Here, the first to n-th bit lines BL 11  to BL 1   n  may correspond to the first to n-th complementary bit lines BLB 11  to BLB 1   n . For example, the first sense amplifier SA 1  may perform a write operation or a read operation on the memory cells connected to the first to n-th bit lines BL 11  to BL 1   n  by using the sensed results from the first to n-th complementary bit lines BLB 11  to BLB 1   n.    
     The first to n-th bit lines BL 11  to BL 1   n  and the first to n-th complementary bit lines BLB 11  to BLB 1   n  connected to the first sense amplifier SA 1  may have an open bit line structure, and may not have a folded bit line structure. An open bit line structure may provide improvement in sensing margins. 
     In addition, the second sense amplifier SA 2  may be connected to all of the first to n-th bit lines BL 21  to BL 2   n  included in the first normal mat NMAT 1  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  included in the first reference mat RMAT 1 . Here, the first to n-th bit lines BL 21  to BL 2   n  may correspond to the first to n-th complementary bit lines BLB 21  to BLB 2   n . For example, the second sense amplifier SA 2  may perform a write operation and/or a read operation on the memory cells connected to the first to n-th bit lines BL 21  to BL 2   n  by using the sensed results from the first to n-th complementary bit lines BLB 21  to BLB 2   n.    
     The first to n-th bit lines BL 21  to BL 2   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  connected to the second sense amplifier SA 2  may have an open bit line structure. 
     Referring to  FIG.  7   , the first sub sense amplifier SA 11  may be connected to both the first bit line BL 11  and the first complementary bit line BLB 11 . Here, the first sub sense amplifier SA 11  may be included in the first sense amplifier SAL, the first bit line BL 11  may be included in the first normal mat NMAT 1 , and the first complementary bit line BLB 11  may be included in the first reference mat RMAT 1 . 
     A first memory cell MC 1  may be connected to both the first bit line BL 11  and a first word line WL 1 , and may be positioned at an intersection of the first bit line BL 11  and the first word line WL 1 . The first memory cell MC 1  may include a first transistor TR 1  and a storage element such as a first capacitor C 1  and/or a first memristor. The first memory cell MC 1  may be a one transistor, one capacitor (“1T1C”) memory cell; however, example embodiments are not limited thereto. The first memory cell MC 1  may perform a read and/or write operation by the first capacitor C 1  being charged and/or discharged by the first sub sense amplifier SA 11 . A first memory cell MC 1 ′ may be connected to both the first complementary bit line BLB 11  and a first word line WL 1 ′, and may be positioned at an intersection of the first complementary bit line BLB 11  and the first word line WL 1 ′. The first memory cell MC 1 ′ may include a first transistor TR 1 ′ and a first capacitor C 1 ′. The first memory cell MC 1 ′ may correspond to a memory cell referred to when the first sub sense amplifier SA 11  performs the read or write operation on the first memory cell MC 1 . For example, the first memory cell MC 1 ′ may correspond to a complementary relationship to the first memory cell MC 1 . In addition, the first complementary bit line BLB 11  may correspond to a complementary relationship to the first bit line BL 11 . Here, the first memory cell MC 1 ′ may be positioned to be spaced apart from the first memory cell MC 1  in the third direction Z. 
     Referring to  FIGS.  6 ,  8 , and  9   , the first sense amplifier SA 1  may be positioned at the first edge portion EDG 1 . The first sense amplifier SA 1  may be disposed adjacent to the column decoder  170  and may extend along the column decoder  170 . The first to n-th bit lines BL 11  to BL 1   n  and the first to n-th complementary bit lines BLB 11  to BLB 1   n  connected to the first sense amplifier SA 1  may extend in the first direction X in parallel to each other. The first to n-th bit lines BL 21  to BL 2   n  and the first to n-th complementary bit lines BLB 21  to BLB 2   n  connected to the second sense amplifier SA 2  may extend in the first direction X in parallel to each other. The first to n-th complementary bit lines BLB 11  to BLB 1   n  may overlap the first to n-th bit lines BL 11  to BL 1   n , and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may overlap the first to n-th bit lines BL 21  to BL 2   n , but example embodiment are not limited thereto. 
     A memory device having an existing open bit line structure has bit lines and complementary bit lines that are connected to the sense amplifier and extend in the first direction X and a direction opposite to the first direction X. In this case, a portion corresponding to an outer portion of the bank memory array, such as the first edge portion EDG 1 , may correspond to a dummy mat including bit lines or complementary bit lines that are not matched. For example, the memory device having the existing open bit line structure may have the dummy mat at the first edge portion EDG 1  or the second edge portion EDG 2 . 
     However, the memory device  100  according to various example embodiments may include the first to n-th bit lines BL 11  to BL 1   n  connected to the first sense amplifier SA 1  and extending in the first direction X, and may include the first to n-th complementary bit lines BLB 11  to BLB 1   n  connected through the first to n-th metal lines ML 11  to ML 1   n  extending in the third direction Z. and extending in the first direction X. Accordingly, the memory device  100  according to various example embodiments has a multi-stack, or two-stack structure including the first normal mat NMAT 1  and the first reference mat RMAT 1 , and thus does not have a dummy mat. For example, the memory device  100  including the first and second sense amplifiers SA 1  and SA 2  and the first normal mat NMAT 1  disposed on the first layer, and the first reference mat RMAT 1  disposed on the second layer does not have the dummy mat, thereby making it possible to reduce consumption of an unnecessary area. Accordingly, an area occupied by the memory device  100  in a memory chip may be further reduced. 
     Alternatively or additionally, since the memory device  100  has the two-stack structure of the first normal mat NMAT 1  and the first reference mat RMAT 1 , more memory cells may be disposed in the same area. Accordingly, the memory device  100  having an increased cell density than a conventional cell density may be provided. 
       FIG.  10    is a three-dimensional view of the memory device according to some example embodiments. 
     Referring to  FIG.  10   , the memory device  100  may further include a third sense amplifier SA 3 , a fourth sense amplifier SA 4 , a fifth sense amplifier SA 5 , a second normal mat NMAT 2 , and a second reference mat RMAT 2 . Here, the third sense amplifier SA 3 , the fourth sense amplifier SA 4 , the fifth sense amplifier SA 5 , the second normal mat NMAT 2 , and the second reference mat RMAT 2  may be disposed to be spaced apart from the first sense amplifier SA 1 , the second sense amplifier SA 2 , the first normal mat NMAT 1 , and the first reference mat RMAT 1  in the first direction X. The second mat MAT 2  of  FIG.  4    may include the second normal mat NMAT 2  and the second reference mat RMAT 2  of  FIG.  10   . For example, the second mat MAT 2  may have a two-stack structure like the first mat MAT 1 . 
     The third sense amplifier SA 3  may be spaced apart from the second sense amplifier SA 2  in the first direction X. The fourth sense amplifier SA 4  may be spaced apart from the third sense amplifier SA 3  in the first direction X. The fifth sense amplifier SA 5  may be spaced apart from the fourth sense amplifier SA 4  in the first direction X. The second normal mat NMAT 2  may be disposed between the third sense amplifier SA 3  and the fourth sense amplifier SA 4 . In addition, the second reference mat RMAT 2  may be spaced apart from the second normal mat NMAT 2  in the third direction Z. For example, the second reference mat RMAT 2  may be positioned above the second normal mat NMAT 2 . 
     The third to fifth sense amplifiers SA 3  to SA 5  and the second normal mat NMAT 2  may be disposed on a first layer on which the first normal mat NMAT 1  is positioned, and the second reference mat RMAT 2  may be disposed on a second layer on which the first reference mat RMAT 1  is positioned. 
     The second normal mat NMAT 2  may include first to n-th bit lines BL 31  to BL 3   n  and first to n-th bit lines BL 41  to BL 4   n  extending in the first direction X. . The second normal mat NMAT 2  may include word lines intersecting the first to n-th bit lines BL 31  to BL 3   n  and the first to n-th bit lines BL 41  to BL 4   n.    
     The second reference mat RMAT 2  may include first to n-th complementary bit lines BLB 31  to BLB 3   n  and first to n-th complementary bit lines BLB 41  to BLB 4   n  extending in the first direction X. In addition, the second reference mat RMAT 2  may include word lines intersecting the first to n-th complementary bit lines BLB 31  to BLB 3   n  and the first to n-th complementary bit lines BLB 41  to BLB 4   n.    
     First to n-th metal lines ML 31  to ML 3   n  may extend in the third direction Z, and may connect the first to n-th bit lines BL 31  to BL 3   n  and the first to n-th complementary bit lines BLB 31  to BLB 3   n . First to n-th metal lines ML 41  to ML 4   n  may extend in the third direction Z, and may connect the first to n-th bit lines BL 41  to BL 4   n  and the first to n-th complementary bit lines BLB 41  to BLB 4   n.    
     The first to n-th bit lines BL 31  to BL 3   n  may correspond to the first to n-th complementary bit lines BLB 31  to BLB 3   n , and the first to n-th bit lines BL 41  to BL 4   n  may correspond to the first to n-th complementary bit lines BLB 41  to BLB 4   n . Since the memory device  100  of  FIG.  10    includes the first mat MAT 1  and the second mat MAT 2  corresponding to two stacks, the area thereof may be further reduced and the cell density thereof may be increased. 
       FIG.  1 I  is a three-dimensional view of the memory device according to some example embodiments. 
     Referring to  FIG.  11   , the memory device  100  may include a first normal mat NMAT 1 , a first reference mat RMAT 1 , a first sense amplifier SA 1 ′, and a second sense amplifier SA 2 ′. Here, the first normal mat NMAT 1  may be positioned on the first layer, and the first sense amplifier SA 1 ′, the second sense amplifier SA 2 ′, and the first reference mat RMAT 1  may be positioned on the second layer. 
     The first reference mat RMAT 1  may be positioned above the first normal mat NMAT 1 . For example, the first reference mat RMAT 1  may be spaced apart from the first normal mat NMAT 1  in the third direction Z. The first reference mat RMAT 1  may be disposed between the first sense amplifier SA 1 ′ and the second sense amplifier SA 2 ′. 
     The first to n-th complementary bit lines BLB 11  to BLB 1   n  included in the first reference mat RMAT 1  may be connected or directly connected to the first sense amplifier SA 1 ′, and the first to n-th complementary bit lines BLB 21  to BLB 2   n  may be directly connected to the second sense amplifier SA 2 ′. The first to n-th bit lines BL 11  to BL 1   n  included in the first normal mat NMAT 1  may be connected to the first sense amplifier SA 1 ′ through first to n-th metal lines ML 11 ′ to ML 1   n ′. Here, the first to n-th metal lines ML 11 ′ to ML 1   n ′ may extend in the third direction Z. The first to n-th bit lines BL 21  to BL 2   n  included in the first normal mat NMAT 1  may be connected to the second sense amplifier SA 2 ′ through first to n-th metal lines ML 21 ′ to ML 2   n ′. Here, the first to n-th metal lines ML 21 ′ to ML 2   n ′ may extend in the third direction Z. 
       FIG.  12    is a three-dimensional view of the memory device according to some example embodiments. 
     Referring to  FIG.  12   , the memory device  100  may include a first normal mat NMAT 1 , a first reference mat RMAT 1 , a first sense amplifier SA 1 ′, and a second sense amplifier SA 2 . Here, the first normal mat NMAT 1  and the second sense amplifier SA 2  may be positioned on the first layer, and the first sense amplifier SA 1 ′ and the first reference mat RMAT 1  may be positioned on the second layer. 
     The first to n-th complementary bit lines BLB 11  to BLB 1   n  included in the first reference mat RMAT 1  may be directly connected to the first sense amplifier SA 1 ′. The first to n-th bit lines BL 21  to BL 2   n  included in the first normal mat NMAT 1  may be directly connected to the second sense amplifier SA 2 . The first to n-th complementary bit lines BLB 21  to BLB 2   n  included in the first reference mat RMAT 1  may be connected to the second sense amplifier SA 2  through the first to n-th metal lines ML 21  to ML 2   n . Here, the first to n-th metal lines ML 21  to ML 2   n  may extend in the third direction Z. The first to n-th bit lines BL 11  to BL 1   n  included in the first normal mat NMAT 1  may be connected to the first sense amplifier SA 1 ′ through first to n-th metal lines ML 11 ′ to ML 1   n ′. Here, the first to n-th metal lines ML 11 ′ to ML 1   n ′ may extend in the third direction Z. 
       FIG.  13    is a three-dimensional view of the memory device according to some example embodiments. 
     Referring to  FIG.  13   , the memory device  100  may include a first sense amplifier SA 1  disposed at a first edge portion EDG 1 , and a first normal mat NMAT 1 ′, a second sense amplifier SA 2 ″, a second mat MAT 2 ′, and a fourth sense amplifier SA 4 ″ sequentially arranged in the first direction X from the first edge portion EDG 1 . In addition, the memory device  100  may include a first reference mat RMAT 1 ′ disposed above the first normal mat NMAT 1 ′. The memory device  100  may include a third sense amplifier SA 3 ″, a third mat MAT 3 ′, and a fifth sense amplifier SA 5  sequentially arranged in the first direction X from the first reference mat RMAT 1 ′. 
     The first normal mat NMAT 1 ′ may include first to n-th bit lines BL 11  to BL 1   n  connected to the first sense amplifier SA 1  and first to n-th bit lines BL 21  to BL 2   n  connected to the second sense amplifier SA 2 ″. The second mat MAT 2 ′ may include first to n-th complementary bit lines BLB 2   l  to BLB 2   n  connected to the second sense amplifier SA 2 ″ and first to n-th bit lines BL 41  to BL 4   n  connected to the fourth sense amplifier SA 4 ″. 
     The first reference mat RMAT 1 ′ may include first to n-th complementary bit lines BLB 11  to BLB 1   n  connected to the first sense amplifier SA 1  and first to n-th bit lines BL 31  to BL 3   n  connected to the third sense amplifier SA 3 ″ through the first to n-th metal lines ML 11  to ML 1   n . The third mat MAT 3 ′ may include first to n-th complementary bit lines BLB 31  to BLB 3   n  connected to the third sense amplifier SA 3 ″ and first to n-th bit lines BL 51  to BL 5   n  connected to the fifth sense amplifier SA 5 ″. 
     Here, the first sense amplifier SA 1  may perform a read or write operation on the memory cells connected to the first to n-th bit lines BL 11  to BL 1   n  by using the first to n-th complementary bit lines BLB 11  to BLB 1   n . The second sense amplifier SA 2 ″ may perform a read or write operation on the memory cells connected to the first to n-th bit lines BL 21  to BL 2   n  by using the first to n-th complementary bit lines BLB 21  to BLB 2   n . The third sense amplifier SA 3 ″ may perform a read or write operation on the memory cells connected to the first to n-th complementary bit lines BL 31  to BL 3   n  by using the first to n-th complementary bit lines BLB 31  to BLB 3   n.    
     For example, the first to n-th bit lines BL 11  to BL 1   n  and the first to n-th complementary bit lines BLB 11  to BLB 1   n  connected to the first sense amplifier SA 1  corresponding to the first edge portion EDG 1  may be vertically connected through the first to n-th metal lines ML 11  to ML 1   n , and each bit line and each complementary bit line may be disposed in two stacks. Accordingly, the dummy mat corresponding to the first edge portion EDG 1  is removed, so that the memory device  100  having a smaller area may be provided. In addition, mats corresponding to portions other than the first edge portion EDG 1  or the second edge portion EDG 2  are also disposed in two stacks in an open bit line structure, so that the memory device  100  having an increased cell density may be provided. 
     Hereinafter, the memory device  100  according to some other example embodiments will be described with reference to  FIG.  14   . 
       FIG.  14    is a three-dimensional view of the memory device according to some example embodiments. For convenience of explanation, portions overlapping those described above with reference to  FIGS.  1  to  9    will be briefly described or a description thereof will be omitted. 
     Referring to  FIG.  14   , the memory device  100  may further include a third sense amplifier SA 3 , a fourth sense amplifier SA 4 , a second normal mat NMAT 2 , and a second reference mat RMAT 2 . Here, the third sense amplifier SA 3 , the fourth sense amplifier SA 4 , the second normal mat NMAT 2 , and the second reference mat RMAT 2  may be disposed above the first sense amplifier SA 1 , the second sense amplifier SA 2 , the first normal mat NMAT 1 , and the first reference mat RMAT 1 . 
     For example, the first sense amplifier SA 1 , the second sense amplifier SA 2 , and the first normal mat NMAT 1  may be disposed on a first layer, the first reference mat RMAT 1  may be disposed on a second layer, the third sense amplifier SA 3 , the fourth sense amplifier SA 4 , and the second normal mat NMAT 2  may be disposed on a third layer, and the second reference mat RMAT 2  may be disposed on a fourth layer. For example, the memory device  100  may have a four-stack memory structure. 
     The second normal mat NMAT 2  may include first to n-th bit lines BL 31  to BL 3   n  connected to the third sense amplifier SA 3 , and may include first to n-th bit lines BL 41  to BL 4   n  connected to the fourth sense amplifier SA 4 . The second reference mat RMAT 2  may include first to n-th complementary bit lines BLB 31  to BLB 3   n  connected to the third sense amplifier SA 3  through the first to n-th metal lines ML 31  to ML 3   n , and may include first to n-th complementary bit lines BLB 41  to BLB 4   n  connected to the fourth sense amplifier SA 4  through the first to n-th metal lines ML 41  to ML 4   n.    
     The third mat MAT 3  may include a third normal mat NMAT 3  and a third reference mat RMAT 3 . The third mat MAT 3  may be disposed to be spaced apart from the first mat MAT 1  in the first direction X. The fourth mat MAT 4  may include a fourth normal mat NMAT 4  and a fourth reference mat RMAT 4 . The fourth mat MAT 4  may be disposed to be spaced apart from the second mat MAT 2  in the first direction X. In addition, the fourth mat MAT 4  may be disposed to be spaced apart from the third mat MAT 3  in the third direction Z. 
     In the third direction Z, the first normal mat NMAT 1 , the first reference mat RMAT 1 , the second normal mat NMAT 2 , and the second reference mat RMAT 2  are sequentially arranged, and the third normal mat NMAT 3 , the third reference mat RMAT 3 , the fourth normal mat NMAT 4 , and the fourth reference mat RMAT 4  are sequentially arranged, thereby making it possible to provide a four-stack memory device  100  having improved cell density. 
     Hereinafter, the memory device  100  according to some other example embodiments will be described with reference to  FIG.  15   . 
       FIG.  15    is a three-dimensional view of the memory device according to some example embodiments. For convenience of explanation, portions overlapping those described above with reference to  FIGS.  1  to  9  and  13    will be briefly described or a description thereof will be omitted. 
     Referring to  FIG.  15   , the memory device  100  may further include a sixth sense amplifier SA 6 , a seventh sense amplifier SA 7 ″′, an eighth sense amplifier SA 8 ″, a ninth sense amplifier SA 9 ″, a tenth sense amplifier SA 10 ″, a second normal mat NMAT 2 ′, a second reference mat RMAT 2 ′, a fourth mat MAT 4 ′, and a fifth mat MAT 5 ′. 
     Here, the sixth sense amplifier SA 6 , the seventh sense amplifier SA 7 ″, the eighth sense amplifier SA 8 ″, the ninth sense amplifier SA 9 ″, the tenth sense amplifier SA 10 ″, the second normal mat NMAT 2 ′, the second reference mat RMAT 2 ′, the fourth mat MAT 4 ′, and the fifth mat MAT 5 ′ may be disposed above the first sense amplifier SA 1 , the second to fifth sense amplifiers SA 2 ″ to SA 5 ″, the first normal mat NMAT 1 ′, the first reference mat RMAT 1 ′, the second mat MAT 2 ′, and the third mat MAT 3 ′. That is, the memory device  100  having a four-stack memory structure may be provided. 
     The second normal mat NMAT 2 ′ may include first to n-th bit lines BL 61  to BL 6   n  connected to the sixth sense amplifier SA 6  and first to n-th bit lines BL 71  to BL 7   n  connected to the seventh sense amplifier SA 7 ″. The second reference mat RMAT 2 ′ may include first to n-th complementary bit lines BLB 61  to BLB 6   n  connected to the sixth sense amplifier SA 6  through the first to n-th metal lines ML 11 ′ to ML 1   n ′, and may include first to n-th bit lines BL 81  to BL 8   n  connected to the eighth sense amplifier SA 8 ″. 
     The fourth mat MAT 4 ′ may include first to n-th complementary bit lines BLB 71  to BLB 7   n  connected to the seventh sense amplifier SA 7 ″ and first to n-th bit lines BL 91  to BL 9   n  connected to the ninth sense amplifier SA 9 ″. The fifth mat MAT 5 ′ may include first to n-th complementary bit lines BLB 81  to BLB 8   n  connected to the eighth sense amplifier SA 8 ″ and first to n-th complementary bit lines BL 101  to BL 10   n  connected to the tenth sense amplifier SA 10 ″. 
     Accordingly, the memory device  100  having an increased cell density by having the bit lines and the complementary bit lines vertically connected to the first edge portion EDG 1  and having the 4-stack memory structure may be provided. 
       FIG.  16    is a block diagram illustrating a memory system according to some example embodiments. 
     Referring to  FIG.  16   , a host device  20  may include a memory controller  10 . That is, unlike the memory system described with reference to  FIG.  1    in which the memory controller  10  is positioned outside the host device  20 , the host device  20  according to example embodiments may include the memory controller  10 . The host device  20  may control the memory device  100  through the memory controller  10 . Here, the host device  20  may communicate with the memory device  100  based on one or more of the standards such as double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), wide I/O, high bandwidth memory (HBM), hybrid memory cube (HMC), or compute eXpress link (CXL). 
       FIG.  17    is a diagram of a semiconductor package according to some example embodiments. 
     Referring to  FIG.  17   , a semiconductor package  1000  may include a stacked memory device  1100 , a system on chip  1200 , an interposer  1300 , and a package substrate  1400 . The stacked memory device  1100  may include a buffer die  1110  and core dies  1120  to  1150 . 
     Each of the core dies  1120  to  1150  may include a memory cell array. The core dies  1120  to  1150  may include the memory device  100  described with reference to  FIGS.  1  to  16   . The buffer die  1110  may include a physical layer  1111  and a direct access area (DAB)  1112 . The physical layer  1111  may be electrically connected to a physical layer  1210  of the system on chip  1200  through the interposer  1300 . The stacked memory device  1100  may receive signals from the system on chip  1200  or transmit signals to the system on chip  1200  through the physical layer  1111 . 
     The direct access area  1112  may provide an access path capable of testing the stacked memory device  1100  without passing through the system on chip  1200 . The direct access area  1112  may include conductive means (e.g., ports or pins) that may directly communicate with an external test device. The test signal and data received through the direct access area  1112  may be transmitted to the core dies  1120  to  1150  through or by through silicon vias (TSVs). For testing of the core dies  1120  to  1150 , data read from the core dies  1120  to  1150  may be transmitted to the test device through the TSVs and the direct access area  1112 . Accordingly, a direct access test for the core dies  1120  to  1150  may be performed. 
     The buffer die  1110  and the core dies  1120  to  1150  may be electrically connected to each other through TSVs  1101  and bumps  1102 . The buffer die  1110  may receive signals provided to each channel through the bumps  1102  allocated for each channel from the system on chip  1200 . For example, the bumps  1102  may be micro-bumps. 
     The system on chip  1200  may execute applications supported by the semiconductor package  1000  by using the stacked memory device  1100 . For example, the system on chip  1200  may execute specialized operations by including at least one processor of a central processing unit (CPU), an application processor (AP), a graphic processing unit (GPU), a neural processing unit (NPU), a tensor processing unit (TPU), a vision processing unit (VPU), an image signal processor (ISP), and a digital signal processor (DSP). 
     The system on chip  1200  may include a physical layer  1210  and a memory controller  1220 . The physical layer  1210  may include input/output circuits for transmitting and receiving signals to and from the physical layer  1111  of the stacked memory device  1100 . The system on chip  1200  may provide various signals to the physical layer  1111  through the physical layer  1210 . The signals provided to the physical layer  1111  may be transmitted to the core dies  1120  to  1150  through interface circuits of the physical layer  1111  and the TSVs  1101 . 
     The memory controller  1220  may control an overall operation of the stacked memory device  1100 . The memory controller  1220  may transmit signals for controlling the stacked memory device  1100  to the stacked memory device  1100  through the physical layer  1210 . 
     The memory controller  1220  may correspond to the memory controller  10  of  FIG.  1   . 
     The interposer  1300  may connect the stacked memory device  1100 ) and the system on chip  1200 . The interposer  1300  may connect the physical layer  1111  of the stacked memory device  1100  and the physical layer  1210  of the system on chip  1200  and provide physical paths formed using conductive materials. Accordingly, the stacked memory device  1100  and the system on chip  1200  may be stacked on the interposer  1300  to transmit and receive signals to and from each other. 
     Bumps  1103  may be attached to an upper portion of the package substrate  1400 , and solder balls  1104  may be attached to a lower portion of the package substrate  1400 . For example, the bumps  1103  may be flip-chip bumps. The interposer  1300  may be stacked on the package substrate  1400  through bumps  1103 . The semiconductor package  1000  may transmit and receive signals to and from other external packages or semiconductor devices through the solder balls  1104 . For example, the package substrate  1400  may be a printed circuit board (PCB). 
       FIG.  18    is a diagram illustrating an example of implementation of a semiconductor package according to some example embodiments. 
     Referring to  FIG.  18   , a semiconductor package  2000  may include a plurality of stacked memory devices  2100  and a system on chip  2200 . The stacked memory devices  2100  and the system on chip  2200  may be stacked on an interposer  2300 , and the interposer  2300  may be stacked on a package substrate  2400 . The semiconductor package  2000  may transmit and receive signals to and from other external packages or semiconductor devices through solder balls  2001  attached to a lower portion of the package substrate  2400 . 
     Each of the stacked memory devices  2100  may be implemented based on the high bandwidth memory (HBM) standard. However, example embodiments are not limited thereto, and each of the stacked memory devices  2100  may be implemented based on one or more of the GDDR, HMC, or Wide I/O standard. Each of, or at least some of, the stacked memory devices  2100  may correspond to the stacked memory device  1100  of  FIG.  17   . 
     The system on chip  2200  may include at least one processor such as a CPU, an AP, a GPU, or an NPU and a plurality of memory controllers for controlling the plurality of stacked memory devices  2100 . The system on chip  2200  may transmit and receive signals to and from a corresponding stacked memory device through the memory controller. The system on chip  2200  may correspond to the system on chip  1200  of  FIG.  17   . 
       FIG.  19    is a diagram of a semiconductor package according to some example embodiments. 
     Referring to  FIG.  19   , a semiconductor package  3000  may include a stacked memory device  3100 , a host die  3200 , and a package substrate  3300 . The stacked memory device  3100  may include a buffer die  3110  and core dies  3120  to  3150 . The buffer die  3110  may include a physical layer  3111  for communicating with the host die  3200 , and each of the core dies  3120  to  3150  may include a memory cell array. 
     The host die  3200  may include a physical layer  3210  for communicating with the stacked memory device  3100  and a memory controller  3220  for controlling an overall operation of the stacked memory device  3100 . In addition, the host die  3200  may include a processor for controlling an overall operation of the semiconductor package  3000  and executing an application supported by the semiconductor package  3000 . For example, the host die  3200  may include at least one processor such as a CPU, an AP, a GPU, or an NPU. 
     The stacked memory device  3100  may be disposed above the host die  3200  based on TSVs  3001  and vertically stacked above the host die  3200 . Accordingly, the buffer die  3110 , the core dies  3120  to  3150 , and the host die  3200  may be electrically connected to each other through the TSVs  3001  and the bumps  3002  without an interposer. For example, the bumps  3002  may be micro-bumps. 
     Bumps  3003  may be attached to an upper portion of the package substrate  3300 , and solder balls  3004  may be attached to a lower portion of the package substrate  33 . For example, the bumps  3003  may be flip-chip bumps. The host die  3200  may be stacked on the package substrate  3300  through the bumps  3003 . The semiconductor package  3000  may transmit and receive signals to and from other external packages or semiconductor devices through the solder balls  3004 . 
     Example embodiments have been described hereinabove with reference to the accompanying drawings, but it will be understood by one of ordinary skill in the art to which the present disclosure pertains that various modifications and alterations may be made without departing from the technical spirit or essential feature of the present disclosure. Furthermore example embodiments are not necessarily mutually exclusive. For example, some example embodiments may include one or more features described with reference to one or more figures, and may also include one or more other features described with reference to one or more other figures. Therefore, it is to be understood that the example embodiments described above are illustrative rather than being restrictive in all aspects.