Patent Publication Number: US-9887166-B2

Title: Integrated circuit assemblies with reinforcement frames, and methods of manufacture

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 14/288,064, filed May 27, 2014, incorporated herein by reference, which is a continuation-in-part of U.S. patent application Ser. No. 14/214,365, filed 14 Mar. 2014 by Shen et al., titled “INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE”, incorporated herein by reference, which claims priority of U.S. provisional application No. 61/952,066 filed on Mar. 12, 2014, titled “INTEGRATED CIRCUITS PROTECTED BY SUBSTRATES WITH CAVITIES, AND METHODS OF MANUFACTURE”, incorporated herein by reference. 
    
    
     BACKGROUND 
     This document relates to integrated circuits, and more particularly to assemblies having dies that include semiconductor integrated circuits. 
     In fabrication of integrated circuits, one or more circuits are manufactured in a semiconductor wafer and are then separated into “dies” (also called “chips”) in a process called “singulation” or “dicing”. The dies, such as shown at  110  in  FIG. 1 , are attached to a wiring substrate (“WS”, e.g. printed wiring board)  120  which has conductive lines  130  connecting the dies to each other and to other elements of the system. More particularly, the dies have contact pads  110 C connected to the dies&#39; circuits (not shown), and these contact pads are attached to contact pads  120 C of WS  120 . Pads  120 C are interconnected by conductive lines  130 . The attachment of pads  110 C to pads  120 C is performed by connections  140  which may include solder, conductive epoxy, or other types. 
     Encapsulant  150  (e.g. epoxy with silica or other particles) protects the dies  110  and the connections  140  from moisture and other contaminants, ultraviolet light, alpha particles, and possibly other harmful elements. The encapsulant also strengthens the die-to-WS attachment against mechanical stresses, and the encapsulant helps conduct heat away from the dies (to an optional heat sink  160  or directly to the ambient (e.g. air)). However, the encapsulant can cause warpage if the encapsulant&#39;s thermal expansion coefficient (CTE) does not match the CTE of the dies or the WS. 
     The wiring substrate can be an interposer, i.e. an intermediate substrate used to accommodate a mismatch between die fabrication technology and printed wiring substrates (PWS). More particularly, the die&#39;s contact pads  110 C can be placed much closer to each other (at a smaller pitch) than PWS pads  120 C. Therefore ( FIG. 2 ), an intermediate substrate  120 . 1  can be used between the dies  120  and the PWS (shown at  120 . 2 ). Interposer  120 . 1  includes a substrate  120 . 1 S (e.g. semiconductor or other material), a redistribution layer (RDL)  210 .T on top of substrate  120 . 1 S, and another redistribution layer  210 .B on the bottom of substrate  120 . 1 S. Each RDL  210 .T,  210 .B includes interconnect lines  216  insulated from each other and from substrate  120 . 1 S by the RDL&#39;s dielectric  220 . Lines  216  are connected to contact pads  120 . 1 C.T on top of the interposer and contact pads  120 . 1 C.B on the bottom. Lines  216  of RDL  210 .T are connected to lines  216  of RDL  210 .B by conductive (e.g. metallized) through-vias  224 . Pads  120 . 1 C.T are attached to the dies&#39; pads  110 C by connections  140 . 1  as in  FIG. 1 . Pads  120 . 1 C.B are attached to pads  120 . 2 C of PWS  120 . 2  by connections  140 . 2 . Pads  120 . 1 C.B are at a larger pitch than pads  120 . 1 C.T, to accommodate the pitch of the PWS contacts  120 . 2 C. 
     The interposer substrate  120 . 1 S should be as thin as possible to shorten the signal paths between dies  110  and PWS  120 . 2  and thus make the system faster and less power hungry. Also, if the interposer is thin, fabrication of metallized vias  224  is facilitated. However, thin interposers are hard to handle: they are brittle, easily warped, and do not absorb or dissipate heat during fabrication. Therefore, a typical fabrication process attaches the interposer to a temporary substrate (“support wafer”) during fabrication. The support wafer is later removed. Attaching and detaching temporary support wafers is burdensome, and should be avoided if possible. See U.S. Pat. No. 6,958,285 issued Oct. 25, 2005 to Siniaguine. 
     It is desirable to provide improved protection of dies from mechanical stresses, heat, and harmful elements, and improved accommodations for thin interposers. 
     SUMMARY 
     This section summarizes some of the exemplary implementations of the invention. 
     In some embodiments, the dies are protected by a reinforcement frame which is a separate substrate attached to a wiring substrate. The dies are located in openings in the reinforcement frame. Each opening may be a cavity, a through-hole, or both (i.e. a cavity with one or more through-holes). In some cavity embodiments, the reinforcement frame is similar to cap wafers used to protect MEMS components (Micro-Electro-Mechanical Structures); see K. Zoschke et al., “Hermetic Wafer Level Packaging of MEMS Components Using Through Silicon Via and Wafer to Wafer Bonding Technologies” (2013 Electronic Components &amp; Technology Conference, IEEE, pages 1500-1507); see also U.S. Pat. No. 6,958,285 issued Oct. 25, 2005 to Siniaguine. However, in some embodiments, the reinforcement frame improves heat dissipation from the dies, and may reduce or eliminate the need for encapsulant. In some embodiments (e.g. those with through-holes), reinforcement frames allow much flexibility for fabrication sequences and intermediate testing during manufacturing. A reinforcement frame may or may not have its own circuitry connected to the dies or to the wiring substrate. 
     In some embodiments, an opening contains multiple dies. 
     The invention is not limited to the features and advantages described above, and includes other features described below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1 and 2  illustrate vertical cross-sections of assemblies including integrated circuits and constructed according to prior art. 
         FIGS. 3A, 3B, 3C, 3D, 3E, 4A, 4B, 4C, 5A, 5B, 5C, 5D, 5E . 1  illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below. 
         FIGS. 5E . 2  and  5 E. 3  are bottom views of horizontal cross sections according to some embodiments as set forth in detail below. 
         FIGS. 6.1, 6.2, 7, 8A, 8B, 8C, 9A, 9B, 9C, 9D, 10, 11, 12, 13A, 13B  illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below. 
         FIG. 14  is a flowchart of a design and manufacturing method for manufacturing of assemblies according to some embodiments as set forth in detail below. 
         FIGS. 15A, 15B, 16, 17, 18, 19, 20.1  illustrate vertical cross-sections of structures according to some embodiments as set forth in detail below. 
         FIGS. 20.2, 21  are top views of assemblies according to some embodiments as set forth in detail below. 
         FIG. 22.1  illustrates a vertical cross-section of assemblies according to some embodiments as set forth in detail below. 
         FIG. 22.2  is a top view of assemblies according to some embodiments as set forth in detail below. 
         FIG. 23  is a flowchart of a manufacturing method for manufacturing of assemblies according to some embodiments as set forth in detail below. 
         FIGS. 24, 25, 26  illustrate vertical cross-sections of assemblies according to some embodiments as set forth in detail below. 
     
    
    
     DESCRIPTION OF SOME EMBODIMENTS 
     The embodiments described in this section illustrate but do not limit the invention. In particular, the invention is not limited to particular materials, processes, dimensions, or other particulars except as defined by the appended claims. 
       FIG. 3A  shows the beginning stages of fabrication of an interposer  120 . 1  according to some embodiments of the present invention. The interposer substrate  120 . 1 S is initially chosen to be sufficiently thick to provide easy handling and adequate heat dissipation in fabrication. In some embodiments, substrate  120 . 1 S is a monocrystalline silicon wafer of a 200 mm or 300 mm diameter and a thickness of 650 micron or more. These materials and dimensions are exemplary and do not limit the invention. For example, substrate  120 . 1 S can be made of other semiconductor materials (e.g. gallium arsenide), or glass, or sapphire, or metal, or possibly other materials. Possible materials include NbTaN and LiTaN. The substrate will later be thinned; for example, in case of silicon, the final thickness could be 5 to 50 microns. Again, these dimensions are not limiting. 
     Substrate  120 . 1 S is patterned to form blind vias  224 B ( FIG. 3B ). “Blind” means that the vias do not go through substrate  120 . 1 S. This can be done, for example, as follows for silicon substrates. First, optional layer  310  ( FIG. 3A ) is formed on substrate  120 . 1 S to protect the substrate and/or improve the adhesion of subsequently formed photoresist  320 . For example, layer  310  can be silicon dioxide formed by thermal oxidation, chemical vapor deposition (CVD), or sputtering. Then photoresist  320  is deposited and photolithographically patterned to define the vias. Layer  310  and substrate  120 . 1 S are etched in areas exposed by resist  320  to form the blind vias. The via depth is equal or slightly greater than the final depth of substrate  120 . 1 S, e.g. 5 to 51 microns for some silicon-substrate embodiments. The vias can be formed by a dry etch, e.g. dry reactive ion etching (DRIE). An exemplary diameter of each via can be 60 microns or less, but other dimensions are possible. The vias can be vertical (as shown) or may have sloped sidewalls. As noted above, the particular dimensions, processes and other features are illustrative and not limiting. For example, the vias can be laser-drilled or made by some other process. 
     The vias are then metallized. If substrate  120 . 1 S is silicon, this can be done as follows. Photoresist  320  and protective layer  310  are removed, and a dielectric layer  324  ( FIG. 3C ) is formed on the entire top surface of substrate  120 . 1 S. Dielectric  324  lines the via surfaces. In some embodiments, dielectric  324  is formed by thermal oxidation of the silicon substrate or by CVD or physical vapor deposition (PVD). Dielectric  324  will electrically insulate the substrate from subsequently formed metal in vias  224 B. The dielectric thickness depends on the desired process parameters, and is 1 micron in an exemplary thermal-oxide embodiment (a thermal oxide is silicon dioxide formed by thermal oxidation). Other dimensions and materials can be used instead. Dielectric  324  can be omitted if substrate  120 . 1 S is itself dielectric. 
     Then metal  224 M ( FIG. 3D ) is formed in vias  224 B over the dielectric  324 . In the embodiment shown, metal  224 M fills up the vias, but in other embodiments the metal is a liner on the via surfaces. In an exemplary embodiment, metal  224 M is electroplated copper. For example, a barrier layer (metal or dielectric, not shown separately) is formed first on dielectric  324  to aid in copper adhesion and prevent copper diffusion into the dielectric  324  or substrate  120 . 1 S. Suitable barrier layers may include a layer of titanium-tungsten (see Kosenko et al., US pre-grant patent publication 2012/0228778 published Sep. 13, 2012, incorporated herein by reference), and/or nickel containing layers (Uzoh et al., US 2013/0014978 published Jan. 17, 2013, incorporated herein by reference). Then a seed layer, e.g. copper, is formed on the barrier layer by physical vapor deposition (e.g. PVD, possibly sputtering). Then copper is electroplated on the seed layer to fill the vias  224 B and cover the whole substrate  120 . 1 S. The copper is then removed from the areas between the vias by chemical mechanical polishing (CMP). Optionally, the CMP may also remove the barrier layer (if present) from these areas, and may stop on dielectric  324 . As a result, the copper and the barrier layer remain only in and over the vias  224 B. 
     For ease of description, we will refer to vias  224  as “metallized”, but non-metal conductive materials can also be used (e.g. doped polysilicon). 
     If layer  224 M does not fill the vias but is only a liner on the via surfaces, some other material (not shown) can be formed on layer  224 M as a filler to fill the vias and provide a planar top surface for the wafer. This filler material can be polyimide deposited by spin coating for example. 
     Optionally, RDL  210 .T ( FIG. 3E ) is formed on top of substrate  120 . 1 S to provide contact pads  120 . 1 C.T at desired locations. RDL  210 .T can be formed by prior art techniques described above in connection with  FIGS. 1 and 2  for example. RDL  210 .T is omitted if the contact pads  120 . 1 C.T are provided by the top areas of metal  224 M. In such a case, if substrate  120 . 1 S is not dielectric, then a dielectric layer can be formed on the substrate and photolithographically patterned to expose the contact pads  120 . 1 C.T. 
     Interposer  120 . 1  may include transistors, resistors, capacitors, and other devices (not shown) in substrate  120 . 1 S and redistribution layer  210 .T. These devices can be formed before, during and/or after the fabrication of vias  224  and RDL  210 .T using the process steps described above and/or additional process steps. Such fabrication techniques are well known. See e.g. the aforementioned U.S. Pat. No. 6,958,285 and pre-grant patent publication 2012/0228778, both incorporated herein by reference. 
     Dies  110  are attached to contact pads  120 . 1 C.T by connections  140 . 1 , using possibly prior art methods described above in relation to  FIGS. 1 and 2  or by other methods (e.g. diffusion bonding; in this case the connections  140 . 1  are not additional elements but are part of contact pads  110 C and/or  120 . 1 C.T). 
     Optionally, an encapsulant (not shown) can be formed under the dies (as underfill) and/or around the dies (to completely or partially cover the dies&#39; sidewalls), and perhaps above the dies (to completely cover the dies&#39; top and sidewall surfaces), possibly by prior art techniques (e.g. including molding and/or capillary action for underfill). The encapsulant can be any suitable material (e.g. epoxy with silica or other particles). No encapsulant is used in some embodiments. Other embodiments use an encapsulant, but the requirements for the encapsulant are relaxed because the dies will be protected by a reinforcement frame in the form of an additional, protective substrate  410  ( FIG. 5A ) as described below. In some embodiments, the encapsulant is provided only underneath the dies (as underfill), i.e. only between the dies and substrate  120 . 1 S (around the connections  140 . 1 ). 
       FIGS. 4A-4C  illustrate fabrication of protective substrate  410 . Many variations are possible. Substrate  410  should be sufficiently rigid to facilitate subsequent handling of the assembly as explained below. In the embodiment shown, substrate  410  includes monocrystalline silicon substrate  410 S of a thickness 650 microns or higher. Other materials (e.g. glass, metal, polymer plastic, and others) and thicknesses are possible, based on any factors that may be important (including the availability of materials and processes). One possible factor is reducing the mismatch of the coefficients of thermal expansion (CTE) between substrates  410  and  120 . 1 S: if substrate  120 . 1 S is silicon, then substrate  410 S could be silicon or another material with a similar CTE. Another factor is reducing the CTE mismatch between substrate  410  and dies  110  (especially if the dies may physically contact the substrate  410  or may be attached to substrate  410 ). In some embodiments, substrate  410 S will not have any circuitry, but if circuitry is desired in or on substrate  410 S then this may affect the choice of material. The circuitry can be fabricated before, and/or during, and/or after the steps described below. 
     Another possible factor is high thermal conductivity to enable the substrate  410  to act as a heat sink. For example, metal may be appropriate. 
     Openings  414  ( FIG. 4C ) are cavities formed in substrate  410  to match the size and position of dies  110 . An exemplary process is as follows (this process is appropriate for a silicon substrate  410 S, and may be inappropriate for other materials; known processes can be used for silicon or other materials). First, an auxiliary layer  420  ( FIG. 4A ) is formed to cover the substrate  410 S for protection or for improved adhesion of subsequently formed photoresist  430 . Resist  430  is then deposited and patterned photolithographically to define the cavities  414 . Auxiliary layer  420  exposed by the resist openings is etched away. Then ( FIG. 4B ) substrate  410 S is etched in these openings to form cavities  414  with sloped, upward-expanding sidewalls (e.g. by a wet etch). The cavity depth depends on the thickness of dies  110  and connections  140 . 1  as explained below. Non-sloped (vertical) sidewalls can also be obtained, by an anisotropic dry etch for example. Retrograde sidewalls or other sidewall profiles are also possible. 
     Then photoresist  430  is removed ( FIG. 4C ). In the example shown, auxiliary layer  420  is also removed, but in other embodiments layer  420  remains in the final structure. 
     As shown in  FIG. 5A , substrate  410  is attached to interposer  120 . 1  so that one or more dies  110  fit into a corresponding cavity  414 . More particularly, legs  410 L of protective substrate  410  are attached to the top surface of interposer  120 . 1  (e.g. to RDL  210 .T if the RDL is present; legs  410 L are those portion(s) of protective substrate  410  that surround the cavities). The substrate-to-interposer attachment is shown as direct bonding, but other types of attachments (e.g. by adhesive) can also be used as described further below. The entire assembly is marked with numeral  504 . 
     In  FIG. 5A , the dies&#39; top surfaces physically contact the top surfaces of cavities  414 . In some embodiments, each die&#39;s top surface is bonded to the cavity top surface (directly or in some other way, e.g. by adhesive). This bonding increases the bonding strength between the two substrates and improves the thermal conductivity of the thermal path from the dies to the protective substrate. In other embodiments, the dies are not bonded to substrate  410 , and may be spaced from substrate  410 . Air or thermal interface material (TIM, possibly gel-like) may at least partially fill the space between the dies and the cavities&#39; top surfaces; for example, TIM could physically contact the dies and the cavity top surfaces to improve heat conduction away from the dies. 
     In other embodiments, the dies are not bonded to the cavities&#39; top surfaces, and thus the dies&#39; top surfaces can slide laterally along the cavities&#39; top surfaces in thermal movement. This may reduce the thermal stresses, e.g. if the die-interposer CTE matching is better than the matching between the interposer and protective substrate  410 . 
     As noted above, in some embodiments the dies are underfilled and/or encapsulated from above by a suitable protective material (not shown in  FIG. 5A ), e.g. the same material as in  FIG. 1 . In case of encapsulation from above, the cured encapsulant may be a solid material (possibly thermosetting) physically contacting the top surfaces of cavities  414 . The encapsulant may or may not be bonded to the cavity surfaces as described above, with benefits similar to those described above for the no-encapsulant embodiments. 
     To ensure physical contact between the dies (or the encapsulant) and the cavities, the top surfaces of the dies (or encapsulant) should have uniform height. To improve the height uniformity, the dies (or encapsulant) can be polished before joining of substrate  410  to interposer  120 . 1 . Suitable polishing processes include lapping, grinding, and chemical mechanical polishing (CMP). Also, before inserting the dies into cavities, the cavity surfaces and/or the dies can be provided with a suitable temperature interface material (TIM, not shown here but shown at  525  in  FIGS. 5E . 2  and  5 E. 3  discussed below) to improve the thermal transfer between the dies and substrate  410 . TIM&#39;s thermal conductivity can usually be higher than that of air. Exemplary TIMs are those that exist in semisolid, gel-like (grease-like) state throughout the range of expected operating temperatures (e.g. 0° C. to 200° C. for some assemblies) or at least when the temperatures are high to make die cooling particularly desirable (20° C. to 200° C. for some assemblies). The gel-like materials fill free spaces between the dies and substrate  410  to provide a thermally conductive path away from the dies. An exemplary TIM material is a thermal grease available from Arctic Silver, Inc. (having an office in California, USA); the grease&#39;s thermal conductivity is 1 W/mK. 
     After the bonding of substrate  410  to interposer  120 . 1 , the interposer is thinned from the bottom to expose the metal  224 M ( FIG. 5B ). The thinning involves partial removal of substrate  120 . 1 S and dielectric  324  (if the dielectric is present). The thinning may be performed by known techniques (e.g. mechanical grinding or lapping of substrate  120 . 1 S followed by dry or wet, masked or unmasked etch of substrate  120 . 1 S and dielectric  324 ; the substrate and the dielectric are etched simultaneously in some embodiments.) In some embodiments, dielectric  324  protrudes out of substrate  120 . 1 S around metal  224 M at the end of the thinning operation, and metal  224 M protrudes out of the dielectric. See for example the aforementioned U.S. Pat. No. 6,958,285. As noted above, the invention is not limited to particular processes. 
     Advantageously, interposer  120 . 1  is kept flat by substrate  410 , so the handling of the assembly  504  is facilitated. Substrate  410  also improves mechanical integrity (e.g. increases rigidity and weight) to further facilitate handling of the assembly. Also, substrate  410  helps absorb and dissipate the heat generated during this and subsequent fabrication stages and in subsequent operation of assembly  504 . The final thickness of substrate  120 . 1 S can therefore be very low, e.g. 50 microns or even 5 microns or less. Hence, blind vias  224 B ( FIG. 3B ) can be shallow. The shallow depth facilitates fabrication of the metallized vias (i.e. facilitates the via etch and subsequent deposition of dielectric and metal into the vias). The shallow depth also shortens the signal paths through the vias. Moreover, if the vias are shallow, each via can be narrower while still allowing reliable dielectric and metal deposition. The via pitch can therefore be reduced. 
     If desired, protective substrate  410  can be thinned from the top (this is not shown in  FIG. 5B ). The combined thickness of substrates  120 . 1 S and  410  is defined by desired properties, such as rigidity, resistance to warpage, heat dissipation, and assembly size. In some embodiments, substrate  410  is thinned to remove the substrate portions over the dies  110  and to leave only the legs  410 L, thus obtaining a structure of a type described below in relation to  FIG. 20.1 . 
     Subsequent process steps depend on the particular application. In some embodiments ( FIG. 5C ), RDL  210 .B is formed on the bottom of substrate  120 . 1 S, possibly using prior art techniques (as in  FIG. 2  for example). The RDL provides contact pads  120 . 1 C.B and connects them to metal  224 M. (If the RDL is omitted, the contact pads are provided by metal  224 M). If desired, the assembly  504  can be diced into stacks  504 S ( FIG. 5D ). Then the stacks (or the entire assembly  504  if dicing is omitted) are attached to other structures, such as wiring substrate  120 . 2  (e.g. a printed wiring substrate) in  FIG. 5E . 1 . In the example of  FIG. 5E . 1 , a stack  504 S is attached to PWS  120 . 2 , and more particularly the stack&#39;s contacts  120 . 1 C.B are attached to PWS contacts  120 . 2 C, possibly by the same techniques as in  FIG. 1 or 2 . Conductive lines  130  of PWS  120 . 2  connect the contact pads  120 . 2 C to each other or other elements. These details are not limiting. 
       FIG. 5E . 2  shows a possible bottom view of the horizontal cross section along the line  5 E. 2 - 5 E. 2  in  FIG. 5E . 1 . In the example of  FIG. 5E . 2 , the dies are surrounded by temperature interface material (TIM)  525 . The legs  410 L form a region completely surrounding each cavity, and the interposer area bonded to the legs also completely surrounds each cavity. 
       FIG. 5E . 3  shows another possible bottom view of the same horizontal cross section, also with TIM  525 . In this example, the legs  410 L are provided only on two opposite sides of each cavity (left and right sides) but are not provided above and below. Each cavity  414  is a horizontal groove in substrate  410 S, containing multiple dies (a groove may also have only one die). The groove may run through the entire substrate. Other cavity shapes are also possible. 
     As noted above, protective substrate  410  and interposer  120 . 1  can be bonded by adhesive, and  FIG. 6.1  illustrates such bonding by adhesive  610 . Adhesive  610  is provided on legs  140 L or the corresponding areas of interposer  120 . 1  or both. The structure is shown at the stage of  FIG. 5A  (before interposer thinning). In some embodiments, the adhesive is elastic, with a low elasticity modulus (e.g. silicone rubber with elasticity modulus of 50 MPa), to help absorb any mismatches in the thermal expansion of dies  110  and/or substrate  410  and/or interposer  120 . 1  (e.g. so that the pressure from the expanding dies  110  would not damage the protective substrate  410  or the dies). In some embodiments, this is beneficial if the dies&#39; CTE is equal to or greater than the CTE of protective substrate  410  or substrate  410 S. The adhesive&#39;s elasticity also absorbs the height non-uniformity of the top surfaces of dies  110  or the top surfaces of cavities  414 . Also, to absorb the dies expansion, the adhesive may have a CTE equal to or greater than the dies&#39; CTE. Exemplary adhesives are epoxy-based underfills. 
     In some embodiments, adhesive  610  is a punched adhesive tape. 
       FIG. 6.2  illustrates a similar embodiment where the adhesive is not present in areas  610 G in which the structure will be diced. 
       FIG. 7  shows a similar embodiment, but the adhesive  610  covers the whole bottom surface of protective substrate  410 S. The adhesive bonds the dies&#39; (or encapsulant&#39;s) top surfaces to the top surfaces of the cavities. The adhesive&#39;s CTE can be equal to, or greater than, or less than, the dies&#39; CTE. 
       FIGS. 8A-8C  illustrate the use of separate bonding layers  810 ,  820  to directly bond the protective substrate  410  to interposer  120 . 1 . In some embodiments, the bonding layers are silicon dioxide, but other materials can also be used (e.g. metals for eutectic bonding). Referring to  FIG. 8A , the dies are attached to interposer  120 . 1  as in  FIG. 3E ; the dies are then optionally underfilled and/or encapsulated from above (in  FIG. 8A , encapsulant  150  encapsulates and underfills the dies). Bonding layer  810 , e.g. silicon dioxide or metal, is formed to cover the interposer and the dies (and the encapsulant if present), by any suitable techniques (e.g. sputtering). 
     Referring to  FIG. 8B , the protective substrate  410  is provided with cavities as in  FIG. 4C . Then a bonding layer  820 , e.g. silicon dioxide or metal, is formed to cover the substrate surface by any suitable techniques (e.g. sputtering, or thermal oxidation if substrate  410 S is silicon). 
     Referring to  FIG. 8C , the interposer is joined to substrate  410  so that the layers  810 ,  820  physically contact each other. The structure is then heated to bond the layer  820  to layer  810  where the two layers meet, i.e. at legs  410 L and at the cavities&#39; top surfaces. In some embodiments however, before the bonding, the layer  820  is removed at the cavities&#39; top surfaces not to bond the dies to the cavities&#39; top surfaces. 
     Subsequent processing of the structures of  FIGS. 6.1-8A  (interposer thinning, possible dicing, etc.) can be as described above for other embodiments. 
     The process step sequences described above are not limiting; for example, the vias  224  can be formed after the interposer thinning.  FIGS. 9A-9D  illustrate an exemplary process. Interposer  120 . 1  is fabricated essentially as in  FIG. 3E or 6.1 or 6.2 or 8A , but without vias  224  (the vias will be formed later). In particular, dielectric  324  is a flat layer on interposer substrate  120 . 1 S. Then contact pads  910  are formed on substrate  120 . 1 S at the locations of future vias  224 . RDL  210 .T is optionally fabricated on top of the interposer to connect the contact pads  910  to pads  120 . 1 C.T on top of the interposer. (Alternatively, the pads  120 . 1 C.T can be provided by pads  910 .) Dies  110  are attached to pads  120 . 1 C.T, and optionally underfilled and encapsulated. Bonding layer  810  (as shown) is optionally deposited as in  FIG. 8A  for bonding to the protective substrate (alternatively, the bonding can be by an adhesive as in  FIG. 6.1 or 6.2 or 7 , or by a direct bonding process as described above in relation to  FIG. 5A ). 
     Interposer  120 . 1  with the dies attached is then bonded to protective substrate  410  ( FIG. 9B ) as in any embodiment described above. Then the interposer is thinned (FIG.  9 C). The dies will be protected by substrate  410  during subsequent steps. Substrate  410  can be thinned at any desired stage. 
     Then metallized vias  224  are formed from the interposer bottom. An exemplary process is as follows: 
     1. Dielectric  920  (e.g. silicon dioxide or silicon nitride) is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate  120 . 1 S. 
     2. Vias (through-holes) are formed (by a masked etching or laser drilling or some other process) from the bottom through dielectric  920  and substrate  120 . 1 S. The vias terminate at contact pads  910 . 
     3. Dielectric  930  (e.g. silicon dioxide or silicon nitride) is deposited (e.g. by sputtering or CVD) to cover the bottom surface of interposer substrate  120 . 1 S and to line the vias. Dielectric  930  covers the contact pads  910  from the bottom. 
     4. Dielectric  930  is etched to expose the contact pads  910 . This can be a masked etch. Alternatively, a blanket anisotropic (vertical) etch can be used to remove the dielectric  930  from over at least a portion of each contact pad  910  while leaving the dielectric on the via sidewalls. The vertical etch may or may not remove dielectric  930  outside the vias. 
     5. A conductive material  224 M (e.g. metal) is formed in the vias, possibly by the same techniques as described above (e.g. copper electroplating). The conductive material is not present outside the vias (e.g. it can be polished away by CMP). The conductive material may fill the vias or just line the via surfaces. The conductive material in each via physically contacts the corresponding pad  910 . 
     Subsequent processing steps can be as described above in connection with  FIGS. 5C-5E . 3 . In particular, the bottom RDL  210 .B ( FIG. 5C ) and connections  140 . 2  can be formed as described above. The structure can be diced if desired ( FIG. 5D ), and attached to another structure (e.g. PWS  120 . 2  in  FIG. 5E . 1 ). 
     Vias  224  are optional, and further the substrate  120 . 1  can be any wiring substrate, such as shown at  120  in  FIG. 10 . This figure illustrates an embodiment using an adhesive  610  to bond the protective substrate  410  to WS  120  at legs  410 L and at the cavity top surfaces, but any other bonding method described above can be used. No underfill or other encapsulant is shown, but underfill with or without encapsulation of the entire die can be present. 
     In some embodiments, vias  224  are formed partly before and partly after the interposer thinning. For example, in some embodiments, the interposer is processed to the stage of  FIG. 3C  (dielectric  324  is formed, possibly by a high temperature process such as thermal oxidation of silicon), but instead of metal the vias are filled with a temporary filling, e.g. polyimide. Then other processing steps are performed as described above in relation to  FIGS. 3E-5B , and in particular the temporary filling is exposed at the interposer bottom when the interposer is thinned. The temporary filling is removed, and metal or other conductive material  224 M is placed in the vias as described above in relation to  FIG. 9D . This may be advantageous if there is a need to avoid early deposition of metal into the vias (at the stage of  FIG. 3D ) due to incompatibility with subsequent processing steps, and at the same time it is undesirable to delay deposition of dielectric  324  to the stage of  FIG. 9D  (if dielectric  324  is formed by a high temperature process for example). Other variations are possible. 
     The techniques described above in connection with  FIGS. 5A-10  can be used to attach any number of separate protective substrates  410  to the same interposer  120 . 1  or WS  120 ; different protective substrates  410  can be attached to the same side of a substrate  120 . 1  or  120 , with different dies in different cavities of the same or different protective substrates  410 ; see  FIG. 16  described in more detail below. Other protective substrates  410  can be attached to the opposite side of substrate  120 . 1  or  120 . Some of the dies may have no protective substrate  410  to protect them. Each substrate  120 . 1 S or  410 S can be a wafer, and the two substrates can be of the same size in a given assembly  504 ; but different sizes are also possible in the same assembly. 
     The dies can be stacked one above another in the same cavity (see  FIG. 11  showing the structure at the same fabrication stage as  FIG. 6.1 ), with only the top die of each stack physically contacting the corresponding cavity&#39;s top surface (a stack may have multiple dies attached to the top surface of a lower die; one or more of the multiple dies may have their top surfaces contacting the cavity&#39;s top surface). The dies in each stack may have their respective circuits interconnected through their contact pads  110 C and respective connections  140  (which can be of any type described above). In  FIG. 11 , substrates  120 . 1 S,  410 S are bonded together by adhesive  610  on legs  410 L as in  FIG. 6.1 , but the other bonding methods described above can also be used. Stacked dies can also be used with other variations described above, e.g. when the protective substrate is bonded directly to the PWS. A die stack can be replaced by any integrated-circuit package. 
     In some embodiments, substrate  410 S has circuitry, possibly connected to the circuitry in the dies and/or the interposer  120 . 1 S or the PWS. See  FIG. 12 , showing the top dies connected to substrate  410 S by structures  1210 ; each structure  1210  includes a contact pad in substrate  410 S, a corresponding contact pad on a top die  110 , and a connection (e.g. solder or any other type described above) bonding the two contact pads to each other. In the example of  FIG. 12 , encapsulant  150  underfills and completely surrounds each die, contacting the cavities&#39; top surfaces. As noted above, encapsulation and/or underfilling are optional. 
     The invention is not limited to the embodiments described above or below. For example, the vias  224  can be formed after the RDLs, and can be etched through one or both of the RDLs. Different features described above or below can be combined. For example, in  FIGS. 13A and 13B  described below, the substrate  410  is bonded to interposer  120 . 1  by adhesive  610 , but other bonding methods described above can be used. Also, in  FIGS. 13A and 13B , the vias  224  are formed before the interposer thinning, but they can be made after the interposer thinning as in  FIGS. 9C-9D . The particulars displayed are for illustration purposes only and not to limit the invention. 
     A cavity  414  may include dies, stacks, or other packages of different heights (e.g. as in  FIG. 13A ), and the heights of the shorter modules may be increased to improve the mechanical strength and/or thermal dissipation—see  FIG. 13B .  FIGS. 13A and 13B  shown assemblies at the stage of  FIG. 11  (before interposer thinning). Each cavity  414  includes two modules  1310 . 1 ,  1310 . 2 ; module  1310 . 1  contains a stack of two dies, and module  1310 . 2  includes a single die (a module may be any die or assembly including a stack or other package). The die  110  of module  1310 . 2  could be made thinner ( FIG. 13A ), but the cavity depth Cd has to accommodate the module  1310 . 1 , so the thickness of die  110  of module  1310 . 2  is increased ( FIG. 13B ) to take advantage of the high Cd value. 
       FIG. 14  is a flowchart of a process that can be used to determine each die&#39;s thickness at the design stage. At step  1410 , the minimal thickness of each module  1310  is determined. (Tmin may include the height of connections  140  which interconnect different dies in the same module and/or connections  140  which connect the module to the interposer; further, if the top of any module are to be connected to protective substrate  410  (as in  FIG. 12 ), then in some embodiments Tmin includes the height of the corresponding connections.) In the example of  FIG. 13B , Tmin is larger for module  1310 . 1  than for module  1310 . 2 . 
     At step  1420 , the maximum Tmin value is determined (this value is denoted by M in  FIG. 14 ). In the example of  FIG. 13B , M is the Tmin value for module  1310 . 1 . 
     At step  1430 , the M value is used to determine the cavity depth Cd. For example, Cd may be set to the M value plus a value determined based on the available manufacturing tolerances (i.e. possible manufacturing errors) and/or desired heat dissipation capabilities and/or the bonding technology (e.g. the thickness of layer  610  or  810  or  820 ), and/or possibly other parameters. 
     At step  1440 , for each module whose Tmin is less than the maximum value (M), the module&#39;s thickness is increased as desired. In the example of  FIG. 13B , for module  1310 . 2 , the Tmin value is less than M, so the thickness of the die of module  1310 . 2  is increased if this would facilitate the die fabrication or improve the die&#39;s heat dissipation or if other benefits would exist in increasing the die thickness. At step  1450 , the dies are manufactured to using the thickness parameters obtained in steps  1410 - 1440 , the cavities are made to the thickness obtained at step  1430 , the protective substrate  410  and the dies are attached to the interposer using any method described above. 
     Steps  1420 ,  1430 ,  1440  are performed automatically in some embodiments, for example by a computer comprising computer processor(s) executing software instructions stored in a computer storage (e.g. memory) or by some other circuitry. 
     Further, as shown in  FIG. 15A , a cavity  414  may have a varying depth: the cavity can be less deep over shorter modules (like  1310 . 2 ) than taller modules (like  1310 . 1 ). Advantageously, in some embodiments, the thermal resistance is reduced between the shorter modules and the top cavity surface. For example, in some embodiments, the modules have different heights, but the gap between each module&#39;s top surface and the overlying cavity surface is the same, and/or has the same thermal resistance. Apart from the thermal resistance considerations, if the top surface of any module is connected to wafer  410  as in  FIG. 12 , the gap between the top surface of the module&#39;s top die and the overlying cavity surface is made equal to the desired height of the connections. 
     In some embodiments, a cavity with varying depths is provided even for modules of the same height. 
     Also ( FIG. 15B ), different cavities may have different depths in the same reinforcement frame. The different depths may be chosen to accommodate different module heights, and/or for other reasons. For example, a module generating more heat may be placed into a shallow cavity to reduce the thermal resistance between the module and the reinforcement frame, but another module generating less heat may be placed into a deeper cavity to increase the tolerance to the module&#39;s height variations. 
     As noted above, multiple protective substrates  410  can be attached to the same interposer. An example is shown in  FIG. 16 : each reinforcement frame  410  has one or more cavities and covers one or more dies  110  (throughout the examples above and below, a die  110  can be replaced by any type of module  1310  as described above in connection with  FIG. 13B ). In all the other respects, the structure of  FIG. 16  can be as in any embodiment described above. In particular, the dies could be encapsulated and/or underfilled, and could be separated from the top cavity surface by air or other gas or TIM grease or other material, or the dies could physically contact the cavity top surface or could contact a solid material (e.g. TIM) which may contact the cavity top surface. Other variations described above can also be present in the structure of the type of  FIG. 16  (for example, the reinforcement frames can be bonded to the interposer by adhesive such as  610  (e.g. punched adhesive tape or other types) that may or may not be present between the frames; other bonding techniques can also be used). 
     This type of structure can provide multiple advantages. In particular, the interposer areas between the frames  410  are accessible and can be used for test pads  1610 : the test pads can be connected to other contact pads in RDL  210 .T and/or to metallized vias  224 M. The test pads facilitate testing of the assembly before and/or after dicing (dicing is omitted in some embodiments). In some embodiments, test pads are located on dicing lines, i.e. a test pad can be cut through during dicing, and can thus be destroyed or can merely be divided into multiple test pads which can be used for testing each die after dicing. 
     Also, thermal stresses that may be present before dicing are lower than for a wafer-size (continuous) reinforcement frame. 
     Further, since each frame  410  covers less than all the dies  110 , each frame  410  is easier to align when it is placed on the interposer (because each frame has to be aligned with just the modules covered by the frame). Also, the interposer may have alignment marks (not shown) in the top surface between the positions of frames  410 , to facilitate the alignment of each frame. 
       FIG. 17  illustrates an exemplary die that obtained from the structure of  FIG. 16  after the interposer thinning and formation of bottom RDL  210 .B and connections  140 . 2  as in  FIG. 5D . (As noted above, different features can be combined in any suitable manner, and in particular the connections  140 . 2  and/or RDL  210 .B can be omitted.) In  FIG. 17 , the dicing lines are placed between the frames  410  so the frames  410  are not diced. Dicing is therefore simplified. 
     For alignment purposes, a reinforcement frame  410  may have protrusions or slots that mate with the slots or protrusions on the interposer. See  FIGS. 18 and 19  showing the structure at the stage of  FIG. 17 . In  FIG. 18 , reinforcement frame  410  has protrusions  1810  that mate with slots on the interposer (protrusions  1810  may extend into the interposer substrate  120 . 1  or just into the RDL  210 .T). In  FIG. 19 , frame  410  has slots that mate with interposer protrusions  1910  (the interposer protrusions can be extensions of the interposer substrate or can be part of RDL  210 .T). Such alignment features can be combined (the protrusions can be present on both the interposer and frame  410 , with mating slots on frame  410  and the interposer). Such alignment features can be present in any embodiment described above, including the embodiments with a single frame  410  (see  FIG. 5C ). 
     As noted above, openings  410  can be cavities as shown above, or can be through-holes, or can be cavities with through-holes.  FIGS. 20.1, 20.2  show respectively a vertical cross section and a top view of a through-hole embodiment; the vertical cross section of  FIG. 20.1  is marked as “ 20 . 1 ” in  FIG. 20.2 . This embodiment is similar to  FIG. 17 , but opening  414  is a through-hole in frame  410 ; frame  410  laterally surrounds the dies. The through-hole facilitates frame alignment and attachment to the interposer (since the die area is visible and accessible during frame placement and attachment). Also, test pads  1610  can be placed inside through-hole  414  (at the top of RDL  210 .T or dies  110  for example); the test pads can be connected to each other and/or other circuitry in the dies and the interposer, and are accessible via through-hole  414 . 
     Similar to  FIG. 16 , in embodiments in which an opening  414  is a through-hole, each frame  410  can be provided as a separate structure before attachment to the interposer as in. The advantages include those described above in relation to  FIG. 16 . Alternatively, the frames  410  can be part of a single wafer as in  FIG. 5A ; see  FIG. 21  showing an exemplary top view of a portion of a wafer-size frame  410  with four holes  414 ; the frame and the interposer will be diced along dicing lines  2110 . As in other schemes above, dicing is omitted in some embodiments. 
     While a through-hole-type frame  410  (such as in  FIGS. 20.1, 20.2 ) is not as strong as a cavity-type frame (such as in  FIG. 5D ), through-hole-type frames can have advantages. In particular, as noted above, they allow for more locations of test pads  1610 , and they can be easier to align and bond to the interposer. Also, they may have less mechanical stress. Further, they can support heat sinks bonded directly to the dies: see e.g. heat sink (heat spreader)  160  in  FIGS. 22.1  (vertical cross section) and  22 . 2  (top view): these figures show the same structure and the same views as  FIGS. 20.1, 20.2  but with heat sink  160  supported on two opposite sides of frame  410 . The heat sink can be supported by all the sides of frame  410 , or by three sides, or in some other way (of note, through hole  414  may have more than four sides and does not have to be rectangular in top view, e.g. the through-hole can be circular or any other shape). In  FIGS. 22.1 and 22.2 , the heat sink is bonded to dies  110  by a bonding layer  2230 . Layer  2230  can be adhesive and/or TIM and/or metal and/or other type of layer suitable for bonding. The heat sink can be bonded to less than all dies  110 . Layer  2230  can be omitted if direct bonding is used. This bonding is optional: instead or in addition, the heat sink can be bonded to frame  410  by a bonding layer or by direct bonding. A heat sink may overlie, and be supported by, multiple through-holes in the same or multiple reinforcement frames; such a heat sink may be bonded to multiple reinforcement frames and/or multiple dies in the same or different through-holes. 
     The through-hole scheme increases manufacturing flexibility in that the dies  110  and frames  410  can be attached to interposer  120 . 1  in any order. An exemplary manufacturing sequence is illustrated in the flowchart of  FIG. 23 . In this embodiment, step  2310  illustrates manufacturing of the interposer  120  (i.e.  120 . 1 ), the frame or frames  410 , and the modules  1310  (e.g. dies  110 ). The interposer may or may not include metallized vias  224 M (the vias can be formed later as described above in relation to  FIG. 9D ). At step  2320 , the frame or frames  410  are attached to the interposer. At step  2330 , the dies  110  (or the modules) are attached to the interposer and underfilled and/or encapsulated on all sides (laterally, above and below), as in  FIG. 1  for example. (The dies can be manufactured after step  2320 , or can be manufactured and attached before step  2320 .) At step  2340 , the interposer is thinned. At step  2350 , metallized vias  224 M are formed in the interposer (as noted above, some or all of these vias could be formed at step  2310  and revealed on the interposer backside at step  2340 ). At step  2360 , the assembly is tested (using test pads  1610 ). At step  2370 , one or more heat sinks  160  are attached over holes  414 . At step  1374 , encapsulant (such as  150  in  FIG. 1 ) can be dispensed to encapsulate the dies above the interposer. The encapsulant is optional, and encapsulation can precede heat sink attachment or can be performed after heat sink attachment if the heat sinks do not completely cover the holes  414 . Alternatively, some encapsulation (or at least underfilling of dies  110 ) can be performed before heat sink attachment (instead of or in addition to step  2330  underfilling), and additional encapsulation can be performed after heat sink attachment. Of note, the amount of encapsulant can be controlled based on the interposer warpage. The type of encapsulant can also be controlled based on the warpage. For example, if the interposer bows upward, i.e. the middle portion is higher than the edges, and the encapsulant induces compressive stress, then more encapsulant can be dispensed to counteract the warpage, and/or the encapsulant material can be chosen to provide more compressive stress to counteract the warpage. Encapsulation at these late stages, including possibly after heat sink attachment, allows the encapsulant material and amount to be chosen based on the warpage measurements performed on the assembly immediately before encapsulation. 
     Dicing is performed at step  2380 . If needed (step  2384 ), each die (i.e. each stack)  504 S obtained at step  2380  is attached to another substrate, e.g. PWS  120 . 2  (this is shown in  FIG. 24  for the assembly of  FIG. 22.1 ; the process of  FIG. 23  can also be performed with other types of assemblies discussed above). Then, as indicated by step  2390 , the entire die  504 S, including the interposer, can be encapsulated. For example, in  FIG. 24 , encapsulant layers  150 . 1  (underfill) and  150 . 2  (e.g. epoxy) have been dispensed and cured to encapsulate (cover) the die  504 S from below and on the sides to protect the die or simply to reduce warpage: the stresses induced by the encapsulant may counteract other warping stresses in the assembly and/or in the PWS. In some embodiments, the warpage is reduced to below 100 microns. In the example of  FIG. 24 , the encapsulant does not reach the top of die  504 S but only covers the die from below and on the sides part way to heat sink  160 . Encapsulant  150 . 2  also fills the cavity containing the dies  110 . Part of encapsulant  150 . 2  may have been formed at step  2330  and/or  2374  as described above. In other embodiments, the encapsulant may rise to any level above or below the level shown in  FIG. 24 ; for example, the encapsulant may completely cover the heat sink on the sides and the top, as shown for example in  FIGS. 25-26 . 
     Many variations are possible.  FIG. 25  illustrates the same assembly as in  FIG. 24  but the die  504 S is as in  FIG. 20.1  (no heat sink  160 ). Also, in this example, encapsulant layer  150 . 2  completely covers the die  504 S, but the encapsulant can be formed to a lower level (e.g. as in  FIG. 24 ), if appropriate for warpage compensation or for any other purpose. The encapsulant can be formed as described above for  FIG. 24 . 
       FIG. 26  illustrates the same assembly but the die  504 S is as in  FIG. 17 . Again, encapsulant layer  150 . 2  completely covers the die  504 S, but the encapsulant can be formed to a lower level. Other types of dies  504 S can be used. 
     Some aspects of some embodiments are described by the following clauses: 
     Clause 1 describes a manufacture comprising: 
     a first substrate (e.g. interposer  120  or  120 . 1 , or interposer substrate  120 . 1 S) comprising one or more first contact pads (e.g. top contact pads  120 . 1 C.T); 
     a plurality of modules (e.g. dies  110  or other assemblies/packages, e.g. modules  1310 ) attached to the first substrate, at least one module comprising a semiconductor integrated circuit, the module comprising one or more contact pads each of which is attached to a respective first contact pad (of note, there could also be dummy modules, e.g. dummy dies, if the assembly was initially designed to accommodate more modules than needed for a particular embodiment); 
     a reinforcement frame (e.g.  410  or  410 S) comprising one or more cavities, the reinforcement frame being attached to the first substrate, wherein at least part of each module is located in a corresponding cavity in the reinforcement frame (see e.g.  FIG. 13A ), wherein at least two modules have different heights and are at least partially located in the same cavity in the reinforcement frame. 
     Of note, the term “cavity” as used herein covers a cavity with a through-hole. However, the term “cavity” as used herein has a depth which is a parameter that limits the height of modules that can be placed in the cavity. Thus, if an opening  414  has vertical walls and no “roof” (as in  FIG. 20.1  for example), then the opening is not a cavity because the opening does not limit the height of any module that can be placed in the opening. 
     Clause 2 describes a manufacture comprising: 
     a first substrate (e.g. interposer  120  or  120 . 1 , or interposer substrate  120 . 1 S) comprising one or more first contact pads; 
     a plurality of modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; 
     a reinforcement frame comprising one or more cavities, the reinforcement frame being attached to the first substrate, wherein at least part of each module is located in a corresponding cavity in the reinforcement frame (of note, multiple modules may be located in the same cavity); 
     wherein the plurality of modules comprises a first module and a second module that are at least partially located in the same cavity which is deeper over the first module than over the second module (as in  FIG. 15A  for example). 
     Clause 3 describes a manufacture comprising: 
     a first substrate comprising one or more first contact pads; 
     a plurality of modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; 
     a reinforcement frame comprising a plurality of cavities, the reinforcement frame being attached to the first substrate, wherein at least part of each module is located in a corresponding cavity in the reinforcement frame; 
     wherein the plurality of modules comprises a first module and a second module taller than the first module, and the cavity corresponding to the second module is deeper than the cavity corresponding to the first module (as in  FIG. 15B  for example). 
     Clause 4 describes a method (e.g. as in  FIG. 14 ) for designing a manufacture comprising a plurality of modules attached to a first substrate and covered by a reinforcement frame comprising a first cavity which covers the plurality of modules, each module comprising a semiconductor integrated circuit (as in  FIG. 13B  for example), the method comprising: 
     (a) determining a minimum thickness Tmin for each module; 
     (b) determining a maximum value M of the minimum thicknesses of the modules; 
     (c) determining a depth of the first cavity by a process using the maximum value M; 
     (d) if any module&#39;s minimum thickness Tmin is less than M, then determining, for at least one module whose minimum thickness Tmin is less than M, if the module&#39;s thickness is to be increased, and if the module&#39;s thickness is to be increased than increasing the module&#39;s thickness. 
     Clause 5 describes the method of clause 4 further comprising manufacturing the modules based on the modules&#39; thicknesses. 
     Clause 6 describes the method of clause 4 or 5 wherein at least one module&#39;s thickness is increased in operation (d), and increasing the module&#39;s thickness comprises increasing a thickness of at least one semiconductor integrated circuit in the module. 
     Clause 7 describes a manufacture comprising: 
     a first substrate comprising a first side and one or more first contact pads at the first side; 
     one or more modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; and 
     a plurality of reinforcement frames attached to the first substrate (as in  FIG. 16  for example), each reinforcement frame comprising one or more openings, at least part of each module being located in a corresponding opening in a corresponding reinforcement frame. 
     In some embodiments, at least one opening is a cylindrical through-hole. “Cylindrical” is not limited to “circular”; for example, in  FIG. 22.2 , through-hole  414  may be rectangular in top view, or elliptic, or of any other shape. Also, “cylindrical” is not limited to a “right cylinder”; in other words, the walls of through-hole  414  do not have to be vertical, but may be at some other (non-90°) angle to reinforcement frame  410  or interposer  120 . 1 . 
     Clause 8 describes the manufacture of clause 7 wherein the reinforcement frames are spaced from each other. 
     Clause 9 describes the manufacture of clause 7 or 8 wherein the first substrate comprises one or more test pads (e.g.  1610 ) for testing the manufacture which are located outside of the reinforcement frames. 
     Clause 10 describes the manufacture of clause 9 wherein at least one test pad is located between at least two reinforcement frames. 
     Clause 11 describes a method for manufacturing a manufacture, the method comprising: 
     obtaining a first substrate comprising a first side and one or more first contact pads at the first side; 
     obtaining one or more modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; and 
     attaching a plurality of reinforcement frames to the first substrate, each reinforcement frame comprising one or more openings, at least part of each module being located in a corresponding opening in a corresponding reinforcement frame. See  FIG. 16  for example. 
     Clause 12 describes the method of clause 11 wherein the reinforcement frames are spaced from each other. 
     Clause 13 describes the method of clause 11 or 12 further comprising dicing the first substrate between at least two reinforcement frames to form a plurality of dies, each reinforcement frame being in one of the dies.  FIG. 17  shows one such die in one embodiment. 
     Clause 14 describes the method of clause 11, 12 or 13 wherein the first substrate comprises one or more test pads for testing the manufacture which are located outside of the reinforcement frames. 
     Clause 15 describes the method of clause 14 wherein at least one test pad is located between at least two reinforcement frames. 
     Clause 16 describes a manufacture comprising: 
     a first substrate comprising a first side and one or more first contact pads at the first side; 
     one or more modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; and 
     one or more reinforcement frames attached to the first substrate, each reinforcement frame comprising one or more openings, at least part of each module being located in a corresponding opening in a corresponding reinforcement frame; 
     wherein the first substrate comprises a portion laterally surrounding the one or more reinforcement frames. For example, in  FIG. 17 , the interposer comprises a portion (including test pad  1610 ) laterally surrounding the reinforcement frame  410 . 
     Clause 17 describes the manufacture of clause 16 wherein the portion laterally surrounding the one or more reinforcement frames comprises one or more test pads for testing the manufacture. 
     Clause 18 describes the manufacture of clause 17 wherein at least one test pad is electrically connected to at least one module (e.g. by interconnect lines in RDL  210 .T in  FIG. 17 ). 
     Clause 19 describes a manufacture comprising: 
     a first substrate comprising a first side and one or more first contact pads at the first side; 
     one or more modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; and 
     one or more reinforcement frames attached to the first substrate, each reinforcement frame comprising one or more openings, at least part of each module being located in a corresponding opening in a corresponding reinforcement frame; 
     wherein in at least one reinforcement frame, at least one opening comprises a through-hole. See  FIG. 20.1  for example. Of note, the through-hole sidewalls do not need to be vertical, and the opening may be a cavity with a through-hole (possibly multiple through-holes). 
     Clause 20 describes the manufacture of clause 19 wherein the manufacture comprises one or more test pads for testing the manufacture which are accessible through the through-hole and are laterally surrounded by the at least one reinforcement frame. See e.g. test pads  1610  in  FIG. 20.1 . 
     Clause 21 describes the manufacture of clause 20 wherein at least one test pad is part of the first substrate (e.g. as the test pad  1610  which is part of RDL  210 .T in  FIG. 20.1 ). 
     Clause 22 describes the manufacture of clause 20 or 21 wherein at least one test pad is part of a module at least partially located in the at least one opening (e.g. the test pad on top of die  110  in  FIG. 20.1 ). 
     Clause 23 describes a method for making a manufacture (e.g. as in  FIG. 23 ), the method comprising: 
     obtaining a first substrate comprising a first side and one or more first contact pads at the first side; 
     obtaining one or more modules attached to the first substrate, each module comprising a semiconductor integrated circuit, each module comprising one or more contact pads each of which is attached to a respective first contact pad; and 
     attaching one or more reinforcement frames to the first substrate, each reinforcement frame comprising one or more openings, at least part of each module being located in a corresponding opening in a corresponding reinforcement frame; 
     wherein in at least one reinforcement frame, at least one opening comprises a through-hole. 
     Clause 24 describes the method of clause 23 wherein the at least one reinforcement frame is attached to the first substrate before at least part of at least one module partially located in the through-hole. 
     Clause 25 describes the manufacture of clause 19 further comprising one or more heat sinks (e.g.  160 ) each of which overlies one or more through-holes in one or more reinforcement frames, wherein at least one heat sink overlying at least one through-hole in at least one reinforcement frame is attached to the reinforcement frame and/or to at least one module at least partially located in the through-hole, each heat sink having a higher thermal conductivity than each reinforcement frame. 
     Clause 26 describes the manufacture of claim  25  wherein at least one heat sink overlying at least one through-hole in at least one reinforcement frame is attached to the reinforcement frame. 
     Clause 27 describes the manufacture of claim  25  wherein at least one heat sink overlying at least one through-hole is attached to at least one module at least partially located in the through-hole. 
     Clause 28 describes the manufacture of claim  19  wherein the first substrate comprises a first alignment feature, and at least one reinforcement frame comprises a second alignment feature, and one of the first and second alignment features is a recess, and the other one of the first and second alignment features is a protrusion having no electrical functionality and at least partially located in the recess. 
     The invention is not limited to the examples above. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.