Patent Publication Number: US-7901984-B2

Title: Integrated circuit micro-module

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation-in-Part of and claims priority to U.S. patent application Ser. No. 12/390,349, entitled “Integrated Circuit Micro-Module,” filed Feb. 20, 2009, which is hereby incorporated by reference in its entirety for all purposes. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to the packaging of integrated circuits (ICs). More particularly, the present invention relates to integrated circuit micro-modules. 
     BACKGROUND OF THE INVENTION 
     There are a number of conventional processes for packaging integrated circuit (IC) dice. Some packaging techniques contemplate the creation of electronic modules that incorporate multiple electronic devices (e.g. integrated circuits, passive components such as inductors, capacitor, resisters or ferromagnetic materials, etc.) into a single package. Packages that incorporate more than one integrated circuit die are often referred to as multi-chip modules. Some multi-chip modules include a substrate or interposer that supports various components, while others utilize a lead frame, die or other structure to support various other package components. 
     A few multi-chip module packaging techniques have sought to integrate multiple interconnect layers into the package using, for example, laminated films or multiple stacked chip carriers. While existing arrangements and methods for packaging electronic modules work well, there are continuing efforts to develop improved packaging techniques that provide cost effective approaches for meeting the needs of a variety of different packaging applications. 
     SUMMARY OF THE INVENTION 
     Various apparatuses and methods for forming integrated circuit packages are described. One aspect of the invention pertains to a method for forming a microsystem and one or more passive devices in the microsystem. Layers of epoxy are sequentially deposited over a substrate to form multiple planarized layers of epoxy over the substrate. The epoxy layers are deposited by spin coating. At least some of the epoxy layers are photolithographically patterned after they are deposited and before the next epoxy layer is deposited. An integrated circuit having multiple I/O bond pads is placed on an associated epoxy layer. At least one conductive interconnect layer is formed over an associated epoxy layer. A passive component is formed within at least one of the epoxy layers. The passive component is electrically coupled with the integrated circuit via at least one of the interconnect layers. Multiple external package contacts are formed. The integrated circuit is electrically connected to the external package contacts at least partly through one or more of the conductive interconnect layers. The above operations can be performed on a wafer level to form multiple microsystems substantially concurrently. 
     One or more passive components can be positioned in a wide variety of locations within a microsystem. Passive components can be formed to serve various purposes. For example, the passive component may be a resistor, a capacitor, an inductor, a magnetic core, a MEMS device, a sensor, a photovoltaic cell or any other suitable device. 
     Various techniques can be employed to form passive devices. For example, each passive component can be formed substantially concurrently with other portions of the microsystem, such as another passive component and/or one or more of the interconnect layers. In some embodiments, thin film resistors may be formed by sputtering a metal over an epoxy layer. Inductor windings may be formed by sputtering or electroplating metal layers over at least one of the epoxy layers. Capacitors may be formed by sandwiching a thin dielectric layer between metal plates deposited over epoxy layers. Magnetic cores for inductors or sensors may be formed by sputtering or electroplating ferromagnetic material over an epoxy layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention and the advantages thereof may best be understood by reference to the following description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  illustrates a diagrammatic cross-sectional view of a package containing multiple integrated circuits and interconnect layers in accordance with an embodiment of the present invention. 
         FIG. 2  is a process flow diagram illustrating a wafer level process for packaging integrated circuits in accordance with an embodiment of the present invention. 
         FIGS. 3A-3L  illustrate diagrammatic cross-sectional views of selected steps in the process of  FIG. 2 . 
         FIGS. 4A-4E  illustrate diagrammatic cross-sectional views of packages in accordance with various alternative embodiments of the present invention. 
         FIGS. 5A-5H  illustrate selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. 
         FIGS. 6A-6C  illustrate selected steps in a wafer level process for packaging integrated circuits in accordance with another embodiment of the present invention. 
         FIGS. 7A-7C  illustrate selected steps in a wafer level process for packaging integrated circuits in accordance with yet another embodiment of the present invention. 
     
    
    
     In the drawings, like reference numerals are sometimes used to designate like structural elements. It should also be appreciated that the depictions in the figures are diagrammatic and not to scale. 
     DETAILED DESCRIPTION OF EXAMPLE EMBODIMENTS 
     In one aspect, the present invention relates generally to integrated circuit (IC) packages and more specifically to IC micro-module technology. The present invention involves a micro-module made of multiple layers of a dielectric that is preferably photo-imageable and readily planarized. The micro-module may contain a variety of components including one or more integrated circuits, interconnect layers, heat sinks, conductive vias, passive devices, MEMS devices, sensors, thermal pipes etc. The various components can be arranged and stacked within the micro-module in a wide variety of different ways. The layers and components of the micro-module can be deposited and processed using various conventional wafer level processing techniques, such as spin coating, lithography and/or electroplating. Another aspect of the present invention relates to wafer level manufacturing techniques and structures that integrate multiple active and/or passive components into a single, cost-effective, high-performance package. 
       FIG. 1  illustrates a package according to one embodiment of the present invention. In the illustrated embodiment, a multi-tiered package  100  includes a substrate  102 , a heat sink  104 , a plurality of stacked dielectric layers  106 , integrated circuits  114 , passive components (not shown), interconnect layers  122 , vias  125  and external contact pads  120 . The heat sink  104  is formed over the substrate  102  and the dielectric layers  106  are stacked on top of the heat sink. Interconnect layers are interspersed as needed between adjacent dielectric layers  106 . The integrated circuits are embedded within stacked layers of an dielectric  106 , and may be electrically connected to other components (e.g., other ICs, passive components, external contact pads  120 , etc. by appropriate traces in the interconnect layers  122  and vias  125 . In the illustrated embodiment, one of the integrated circuits ( 114   a ) is effectively mounted on the heat sink  104  to provide good heat dissipation. 
     The dielectric layers  106  may be made from any suitable dielectric material. In various preferred embodiments, the dielectric layers  106  are made from a material that is readily planarized and/or photo-imageable. In a particular preferred embodiment, the layers are made from photo-imageable SU-8 (a planarizing epoxy), although other suitable materials may be used as well. In some designs the dielectric used for layers  106  is highly viscous when initially applied, and is subsequently partially or fully cured during a photolithographic process. The layers  106  may be applied using a variety of suitable techniques, including spin coating. The thickness of the various dielectric layers can vary widely in accordance with the needs of a particular application and the different layers do not need to have the same thickness (although they may have the same thickness). 
     The integrated circuits  114  within package  100  can be arranged in a wide variety of ways and may be placed at almost any location within the package. By way of example, different integrated circuits  114  may be positioned in different photo-imageable layers and/or within the same layer. In various embodiments, the integrated circuits  114  can be stacked, positioned side-by-side, placed in close proximity to one another and/or be separated by a substantial distance relative to the overall size of package  100 . Integrated circuits positioned in different layers may be positioned directly or partially over one another or they may be separated such that they do not overlie one another. Integrated circuits  114  can also have a variety of different form factors, architectures and configurations. For example, they may take the form of relatively bare dice (e.g., unpackaged dice, flip chips etc.), partially and/or fully packaged dice (e.g., BGAs, LGAs, QFNs, etc.) 
     The electrical interconnects within the package  100  may be arranged in a wide variety of different ways as well. The embodiment illustrated in  FIG. 1  includes two interconnect (trace) layers  122   a  and  122   b . More or fewer interconnect layers are possible in different implementations. Each interconnect layer typically has at least one (but typically many) traces  123  that are used to help route electrical signals between different components of the package. The interconnect layers  122  are generally formed on top of an associated one of the planarized dielectric layers  106 . The trace layer is then buried or covered by the next dielectric layer. Thus, the interconnect layers generally extend in planes that are parallel with and embedded within the dielectric layers. 
     Since the interconnect layers (and potentially other components of the package) are formed on top of a dielectric layer, it is desirable for the dielectric layers  106  to have a very flat and hard surface upon which other components (e.g. traces, passive components, etc.) may be formed or discrete components (e.g. ICs) may be mounted. SU8 is particularly well suited for this application because it readily self-planarizes when applied using conventional spin-on coating techniques and it is very hard when cured. Indeed, spun on SU8 can be used to form a hard flat surface that does not require any additional planarizing (e.g., chemical mechanical polishing) before a high quality interconnect layer is formed thereon using conventional sputtering/electroplating techniques. Dielectric materials that can be applied in this manner to form a very flat surface are referred to herein as planarizing dielectrics. 
     Electrically conductive vias  125  are provided to electrically connect components (e.g., ICs/traces/contacts/passive components, etc.) that reside at different layers of the package. The vias  125  are arranged to extend through an associated dielectric layer  106 . By way of example, the vias  125  may be used to couple traces from two different interconnect layers together; a die or another component to an interconnect layer; a contact to a trace, die or other component, etc. As will be described in more detail below, metalized vias may be formed at the same time that an associated interconnect layer  122  is deposited by filling via openings that were earlier formed in an associated dielectric layer  106 . 
     Package  100  can include many other types of devices than the ones illustrated in  FIG. 1 . In the illustrated embodiment, only several integrated circuits and interconnect layers are shown. Package  100 , however, can also contain almost any number of active and/or passive devices. Examples of such active and/or passive devices includes resistors, capacitors, magnetic cores, MEMS devices, sensors, cells (e.g., encapsulated lithium or others), integrated thin film battery structures, inductors, etc. These devices can be positioned and/or stacked in various locations within package  100 . The components may take the form of prefabricated discrete components or may be formed in-situ. One advantage of the lithography-based process used to create package  100  is that these and other components can be formed in-situ during the layered formation of the package. That is, while prefabricated, discrete components can be placed in almost any position within package  100 , components can also be fabricated directly onto any photo-imageable layer  106  using any suitable technique, such as conventional sputtering and/or electroplating. Due to the nature of this fabrication process, superior matching, precision and control can be achieved and low stress packaging is possible over various die and/or substrate sizes, including medium and large ones. 
     The substrate  102  may be made of any suitable material, including silicon, glass, steel, G10-FR4, any other FR4 family epoxy, etc. In some embodiments, the substrate is used only as a carrier during fabrication and is accordingly removed before the package is completed. In other embodiments, the substrate remains an integral part of the package. If desired, the substrate  102  may be thinned after assembly by backgrinding or other suitable techniques. In still other embodiments, the substrate may be omitted entirely. 
     In some embodiments, the substrate  102  can integrate one or more sensors (not shown.) This approach enables the integration of sensor components without the packaging and reliability concerns often associated with the sensor&#39;s requirements to be exposed to the environment. Sensors can be mounted on either side of the substrate  102  and can be embedded or exposed to the environment through etched windows or micro-channels. Examples of suitable sensors include but are not limited to biosensors, sensors for gas, chemical, electromagnetic, acceleration, vibration, temperature, humidity etc. 
     One approach is to integrate a sensing element into the backside of the substrate  102 . The sensing element can be built inside a deep cavity in the substrate  102  that has been etched from the backside of the substrate  102 . For example the sensing element may be a capacitor made from electroplated Cu fingers. The capacitor can be connected with contact pads on the frontside of the substrate  102  through micro-vias. Package  100  can be formed over these contact pads such that the capacitor is electrically coupled with at least some of the electrical devices and interconnect layers within package  100 . The sensing element inside the cavity that is created on the backside of the wafer can be filled with the gas sensitive material and can be automatically exposed to the environment, while the active circuitry on the frontside of substrate  102  can be protected by conventional encapsulation techniques, such as those discussed below in connection with  FIG. 5E . 
     Package  100  also includes a system for dissipating internally generated heat, which can include thermal pipes and heat sinks, such as heat sink  104 . Such a system can play an important role in the performance of the package  100 , because packages with high power densities and multiple embedded devices may need to have good heat dissipation to function properly. The thermal pipes and heat sinks are generally formed at substantially the same time and using the same techniques as the interconnect layers  122 . Such thermal pipes can penetrate and/or wind through one or more interconnect layers and/or photoimageable layers. Any single, continuous thermal pipe, trace and/or via can branch off into multiple other traces and/or vias at almost any point and can extend in more than one direction, such as laterally and/or vertically within the package. The thermal pipes can thermally couple virtually any device within the package  100  with one or more heat dissipation pads and/or heat sinks located on the exterior of the package  100 . 
     The heat sink  104  can have a variety of different architectures. In the illustrated embodiment heat sink  104  forms a layer having a footprint that substantially matches the footprint of the photo-imageable layers of package  100 . Alternatively, the package  100  could include one or more heat sinks whose dimensions at least partly match those of an overlying or underlying active device, such as an integrated circuit. In the illustrated embodiment, the heat sink takes the form of a layer or sheet  104  formed over the substrate and forms a base for the dielectric layers  106 . If desired, integrated circuits  104  can be mounted directly on the heat sink layer as illustrated by integrated circuit  114 ( a ). Alternatively, thermally conductive vias (not shown) may be used to improve the thermal path between a buried integrated circuit and the heat sink as illustrated by integrated circuit  114 ( b ). In some embodiments, the heat sink(s) or heat sink layer(s) are exposed on a top or bottom surface of the package. In others, a substrate or other layer may cover the heat sink(s) or heat sink layers such that the heat sinks function as heat spreaders. The heat sink(s)  104  may be made of a variety of suitable conductive materials, such as copper and may be formed in the same manner as the interconnect layers. 
     Various embodiments of the package  100  can incorporate a variety of other features as well. For example, package  100  can incorporate high voltage (HV) isolation and an embedded inductive galvanic capability. It can feature wireless interfaces e.g., RF antennas for wireless system  10 , EM power scavenging, RF shielding for EMI sensitive application, etc. In various embodiments, package  100  can include power management subsystems e.g., superchargers, integrated photovoltaic switches etc. The package  100  could be formed on a wafer and encapsulated e.g., as shown in  FIG. 5E . Sensing surfaces and materials can be integrated into other processing steps for the package  100  and the wafer e.g., as discussed above and in connection with  FIGS. 5A-5H ,  6 A- 6 C and  7 A- 7 C. 
     Referring next to  FIG. 2 , a wafer level method  200  for forming integrated circuit package  100  according to an embodiment of the present invention will be described. The steps of method  200  are illustrated in  FIGS. 3A-3L . The steps of method  200  may be repeated and/or performed out of the illustrated order. It should be noted that the process depicted in method  200  may be used to concurrently form many structures other than those shown in  FIGS. 3A-3L . 
     Initially, in step  202  of  FIG. 2 , an optional conductive layer  104  of  FIG. 3A  is formed over a substrate  102  using any of a variety of suitable techniques. By way of example, sputtering of a seed layer followed by conventional electroplating works well. Of course other suitable conductive layer formation techniques may be used as well. The conductive layer  104  functions as a heat sink and may be made of various materials, such as copper or other appropriate metals or metal layer stacks. The substrate  102  may be a wafer and can be made of a variety of suitable materials, such as silicon, G10-FR4, steel, glass, plastic, etc. 
     In  FIG. 3B , a layer of planarizing, photo-imageable epoxy  106   a  is deposited over the heat sink  104  (step  204  of  FIG. 2 ). This can be done using a variety of techniques, such as spin coating, spray coating or sheet lamination. In the illustrated embodiment, the epoxy layer  106   a  is SU-8, although other appropriate dielectric materials may be used. SU-8 is well suited for applications using conventional spin-on coating techniques. 
     SU-8 has various advantageous properties. It is a highly viscous, photo-imageable, chemically inert polymer that can solidify when exposed to UV radiation, for example, during a photolithographic process. SU-8 provides greater mechanical strength relative to some other known photoresists, is resistant to overpolishing and is mechanically and thermally stable at temperatures up to at least 300° C. It planarizes easily and evenly using spin coating relative to certain other photo-imageable materials such as BCB, which allows it to be readily used as a base upon which interconnects or passive components may be fabricated, and upon which integrated circuits or other passive components may be mounted. It can readily be used to create dielectric layers with thicknesses in the range of 1 um to 250 um and both thinner and thicker layers are possible. In particular embodiments, openings can be formed in SU-8 having high aspect ratios (e.g. approximately 5:1 or greater) which facilitates the formation of components such as conductive vias or other structures with high aspect ratios. By way of example, aspect ratios of 7:1 are readily obtainable. Relative to many other materials, superior control, precision and matching can be achieved with SU-8 layers, which can result in higher densities and improved performance. Other suitable dielectric materials with one or more of the above characteristics may also be used in place of SU-8. 
     In step  206  of  FIG. 2 , epoxy layer  106   a  is patterned using conventional photolithographic techniques. In one embodiment, a mask is used to selectively expose portions of the epoxy layer  106   a . The exposure can be followed by a baking operation. These operations can cause the exposed portions of the epoxy layer  106   a  to crosslink. During the photolithographic process, exposed portions of epoxy layer  106   a  may be cured, partially cured (e.g., B-staged) or otherwise altered or hardened relative to the unexposed portions to facilitate later removal of unexposed portions of the epoxy. 
     In step  208  of  FIG. 2  and  FIG. 3C , unexposed portions of the epoxy layer  106   a  are removed to form one or more openings  306  in the epoxy layer  106   a . This removal process can be performed in a variety of ways. For example, the epoxy layer  106   a  can be developed in a developer solution, resulting in the dissolution of the unexposed portions of the layer  106   a . A hard bake can be performed after the developing operation. 
     In step  210  of  FIG. 2  and  FIG. 3D , an integrated circuit  114   a  is placed in opening  306  and mounted on the heat sink  104 . The integrated circuit  114   a  may be configured in a variety of ways. For example, the integrated circuit  114   a  may be a bare or flip chip die, could have a BGA, LGA and/or other suitable pinout configuration. In the illustrated embodiment, the thickness of the integrated circuit  114   a  is greater than the thickness of the epoxy layer  106   a  in which it is initially embedded, although in other embodiments, the die may be substantially the same thickness, or thinner than the epoxy layer in which it is initially embedded. The active face of the integrated circuit  114   a  may face up or down. In particular embodiments, the integrated circuit  114   a  may be attached and thermally coupled to heat sink  104  using an adhesive. 
     After the integrated circuit  114   a  has been positioned in opening  306  and attached to the heat sink, a second layer of epoxy  106   b  is applied over the integrated circuit  114   a  and the epoxy layer  106   a  (step  204  of  FIG. 2 ) as illustrated in  FIG. 3E . Like the first epoxy layer  106   a , the second epoxy layer  106   b  may be deposited using any suitable method, such as spin coating. In the illustrated embodiment, epoxy layer  106   b  is directly over, immediately adjacent to and/or in direct contact with integrated circuit  114   a  and epoxy layer  106   a , although other arrangements are possible. The epoxy layer  106   b  may completely or partially cover the active surface of integrated circuit  114   a.    
     After epoxy layer  106   b  has been applied, it is patterned and developed using any suitable techniques (steps  206  and  208 ), which would typically be the same techniques used to pattern the first epoxy layer  106   a . In the illustrated embodiment, via openings  312  are formed over integrated circuit  114   a  to expose I/O bond pads (not shown) on the active surface of integrated circuit  114   a . The resulting structure is illustrated in  FIG. 3F . 
     After any appropriate via openings  312  have been formed, a seed layer  319  is deposited over openings  312  and epoxy layer  106   b , as shown in  FIG. 3G . The seed layer  319  can be made of various suitable materials, including a stack of sequentially applied sublayers (e.g., Ti, Cu and Ti) and can be deposited using a variety of processes (e.g., by sputtering a thin metal layer on the exposed surfaces.) A feature of the described approach is that the sputtered seed layer tends to coat all exposed surfaces including the sidewalls and bottoms of via openings  312 . The deposition of seed layer  319  can also be limited to just a portion of the exposed surfaces. 
     In  FIG. 3H , a photoresist  315  is applied over the seed layer  319 . The photoresist  315 , which can be positive or negative, covers seed layer  319  and fills openings  312 . In  FIG. 3I , the photoresist is patterned and developed to form open regions  317  that expose the seed layer  319 . The open areas are patterned to reflect the desired layout of the interconnect layer, including any desired conductive traces and heat pipes, and any vias desired in the underlying epoxy layer  106 ( b ). After the desired open areas have been formed, the exposed portions of the seed layer are then electroplated to form the desired interconnect layer structures. In some embodiments, a portion of the seed layer (e.g., Ti) is etched prior to electroplating. During electroplating, a voltage is applied to seed layer  319  to facilitate the electroplating of a conductive material, such as copper, into the open regions  317 . After the interconnect layer has been formed, the photoresist  315  and the seed layer  319  in the field is then stripped. 
     As a result, interconnect layer  122   a  is formed over the epoxy layer  106   b , as illustrated in  FIG. 3J  (step  212 ). The aforementioned electroplating served to fill the via opening with metal thereby forming metal vias  313  in the spaces formerly defined by the via openings. The metal vias  313  may be arranged to electrically couple the I/O pads of the integrated circuit  114   a  with corresponding traces  316  of interconnect layer  122   a . Because seed layer  319  has been deposited on both the sidewalls and bottoms of openings  312 , the conductive material accumulates substantially concurrently on the sidewalls and the bottoms, resulting in the faster filling of openings  312  than if the seed layer were coated only on the bottom of openings  312 . 
     Although not shown in epoxy layers  106   a  and  106   b , other vias can also be formed all the way through one or more epoxy layers to couple components (e.g. traces, passive devices, external contact pads, ICs, etc. together). In still other arrangements conductive vias may be formed between a surface of a bottom (or other) surface of an integrated circuit and the heat sink layer  104  to provide a good thermal conduction path to the heat sink even when the metallization is not used for its current carrying capabilities. In general, interconnect layer  122   a  can have any number of associated traces and metal vias and these conductors can be routed in any manner appropriate for electrically coupling their associated package components. 
     It is noted that a particular sputtering/electro-deposition process has been described that is well suited for forming traces over and vias within an associated epoxy layer  106  at substantially the same time. However, it should be appreciated that a variety of other conventional or newly developed processes may be used to form the vias and traces either separately or together. 
     After the interconnect layer  122   a  has been formed, steps  204 ,  206 ,  208 ,  210  and/or  212  can generally be repeated in any order that is appropriate to form additional epoxy layers, interconnect layers, and to place or form appropriate components therein or thereon to form a particular package  100  such as the package illustrated in  FIG. 3K . By way of example, in the illustrated embodiment additional epoxy layers  106   c - 106   f  are applied over layer  106   b  (effectively by repeating step  204  as appropriate). Integrated circuits  114   b  and  114   c  are embedded within epoxy layers  106   d  and  106   e  (steps  206 ,  208  and  210 ). Another interconnect layer  122   b  is formed within top epoxy layer  106   f  (steps  206 ,  208  and  212 ) and so on. 
     It should be appreciated that integrated circuits and interconnect layers in package  100  may be arranged in a variety of ways, depending on the needs of a particular application. For example, in the illustrated embodiment, the active faces of some integrated circuits are stacked directly over one another (e.g., integrated circuits  114   a  and  114   b ). Some integrated circuits are embedded within the same epoxy layer or layers (e.g., integrated circuits  114   b  and  114   c .) Integrated circuits may be embedded in epoxy layers that are distinct from epoxy layers in which interconnect layers are embedded (e.g., interconnect layer  318   a  and electrical circuits  114   a  and  114   b ). (“Distinct” epoxy layers means layers where each layer is deposited in a single, cohesive coat in a sequence with the other layers, as is the case with epoxy layers  106   a - 106   e .) Integrated circuits may be stacked over and/or situated in close proximity to one another. Integrated circuits may also be electrically coupled via electrical interconnect layers, vias and/or traces that extend substantially beyond the immediate vicinity or profile of any single integrated circuit (e.g., integrated circuits  114   b  and  114   c ). 
     In step  214  of  FIG. 2  and  FIG. 3L , optional external contact pads  120  can be added to a top surface of package  100 . The external contact pads  120  may be placed on other surfaces and formed in a variety of ways. For example, top epoxy layer  106   f  may be patterned and developed using the techniques described above to expose portions of electrical interconnect layer  122   b . Any suitable metal, such as copper, may be electroplated into the holes on epoxy layer  106   f  to form conductive vias and external contact pads  120 . As a result, at least some of the external contact pads  120  can be electrically coupled with electrical interconnect layers  122   a - 122   b  and/or integrated circuits  114   a - 114   c.    
     The features of package  100  may be modified in a variety of ways. For example, it could contain more or fewer integrated circuits and/or interconnect layers. It could also contain multiple additional components, such as sensors, MEMS devices, resistors, capacitors, thin film battery structures, photovoltaic cells, RF wireless antennas and/or inductors. In some embodiments, substrate  102  is background away or otherwise discarded. Substrate  102  may have any suitable thickness. By way of example, thicknesses in the range of approximately 100 to 250 um work well for many applications. The thickness of the package  100  may vary widely. By way of example, thicknesses in the range of 0.5 to 1 mm work well in many applications. The thickness of electrical interconnect layers  122   a  and  122   b  may also widely vary with the needs of a particular application. By way of example, thicknesses of approximately 50 microns are believed to work well in many applications. 
       FIG. 4A  is a cross-sectional view of another embodiment of the present invention. Similar to package  100  of  FIG. 1 , package  400  of  FIG. 4A  includes integrated circuits  401  and  403 , epoxy layers  410  and multiple interconnect layers. Package  400  also includes some additional optional features that are not shown in package  100 . 
     For example, package  400  features an integrated circuit  401  that is thermally coupled with a heat sink  402 . In the illustrated embodiment, some of the dimensions of heat sink  402  are substantially similar to those of the thermally coupled device. In particular embodiments, heat sink  402  may be larger or smaller than its underlying device. Heat sink  402  may be positioned on and/or be in direct contact with a top or bottom surface of the integrated circuit  401 . It may have direct access to an external surface of package  400  (as is the case in the illustrated embodiment), or be connected to the external surface via one or more thermal vias. Heat sink  402  can be thermally coupled with a conductive layer, such as layer  104  of  FIG. 1 . In a preferred embodiment in which the epoxy layers  410  are made of SU-8, having a heat sink  402  directly below integrated circuit  401  can be particularly helpful, since heat does not conduct well through SU-8. 
     Package  400  also features various passive components, such as inductors  406  and  408 , resistor  404  and capacitor  407 . These passive components may be situated in any epoxy layer or location within package  400 . They may be formed using a variety of suitable techniques, depending on the needs of a particular application. For example, inductor windings  412  and inductor cores  410   a  and  410   b  can be formed by depositing conductive material and ferromagnetic material, respectively, over at least one of the epoxy layers  410 . Thin-film resistors may be formed by sputtering or applying any suitable resistive material, such as silicon chromium, nickel chromium and/or silicon carbide chrome, over one of the epoxy layers  410 . Capacitors can be formed by sandwiching a thin dielectric layer between metal plates deposited over one or more epoxy layers. Prefabricated resistors, inductors and capacitors may be placed on one or more epoxy layers  410  as well. Conductive, ferromagnetic and other materials can be deposited using any suitable method known in the art, such as electroplating or sputtering. 
     Package  400  also includes optional BGA-type contact pads  411  on frontside surface  416 . Because of the location of the contact pads  410 , substrate  414  can be made of various materials, such as G10-FR4, steel or glass. In particular embodiments where the contact pads are on the backside surface  418 , the substrate  414  can be made of silicon and feature through vias that enable electrical connections with the contact pads. In another embodiment, the substrate is primarily used as a building platform to form the package  400  and is ultimately ground off. 
       FIG. 4B  illustrates another embodiment of the present invention, which has many of the features illustrated in  FIG. 4A . This embodiment includes additional components, including precision trim-able capacitor  430  and resistor  432 , micro-relay  434 , low cost configurable, precision passive feedback network  436 , FR-4 mount  438 , and photovoltaic cell  440 . Cell  440  could be covered with a layer of transparent material, such as transparent SU-8. In other embodiments, photovoltaic cell  440  could be replaced by a windowed gas sensor, a wireless phased antenna array, a heat sink or another suitable component. Package  400  can include many additional structures, including a power inductor array, a RF capable antenna, thermal pipes and external pads for dissipating heat from the interior of the package  100 . 
       FIGS. 4C and 4D  illustrate two other embodiments having thermal pipes.  FIG. 4B  illustrates a package  479  that includes an integrated circuit  486  embedded in multiple layers of planarizing, photoimageable epoxy  480 . Metal interconnects  484  are coupled with bond pads (not shown) on the active surface of the integrated circuit  486 . The backside of the integrated circuit  486  is mounted onto a thermal pipe  488 , which includes thermal trace  488   a  and thermal vias  488   b . Thermal pipe  488  is made of any suitable material that conducts heat well, such as copper. As indicated by the dotted line  489 , heat from the integrated circuit  486  is routed through the backside of the integrated circuit  486 , around thermal trace  488   a  and up through thermal vias  488   b , so that the heat is ventilated through the external top surface of the package  479 . The embodiment illustrated in  FIG. 4B  can be fabricated using various techniques, such as the ones discussed in connection with  FIGS. 3A-3K . 
       FIG. 4D  illustrates another embodiment of the present invention. The embodiment includes an integrated circuit  114   a  whose bottom surface is thermally coupled with thermal pipes  470 . Thermal pipes  470  are made from a thermally conductive material, such as copper, and transmit heat from the integrated circuit  114   a  to external heat ventilation sites  472  of package  100 . Heat dissipation can pose a problem for packages with multiple integrated devices and high power densities. Thermal pipes  470 , which can be coupled with one or more devices within package  100 , allow internally generated heat to be transported to one or more external surfaces of package  100 . In  FIG. 4C , for example, heat is conducted away from the integrated circuit  114   a  to heat ventilation sites  472  on the top, bottom and multiple side surfaces of package  100 , although heat ventilation sites can be located on almost any location on the exterior of the package  100 . 
     Heat sinks can also be mounted on the top, bottom, side and/or almost any external surface of the package  100 . In the illustrated embodiment, for example, heat spreader  101 , which is on the bottom surface of package  100 , is thermally coupled with thermal pipes  470  and dissipates heat over the entire bottom surface area of package  100 . In one embodiment, all of the thermal pipes in the package  100 , which are thermally coupled with multiple embedded integrated circuits, are also coupled with heat spreader  101 . In a variation on this embodiment, some of the thermal pipes are also coupled with a heat sink located on the top surface of the package  100 . Thermal pipes  470  can be formed using processes similar to those used to fabricate interconnect layers  122 . They can be coupled with multiple passive and/or active devices within package  100  and can extend in almost any direction within package  100 . In the illustrated embodiment, for example, thermal pipes  470  extend both parallel and perpendicular to some of the planes formed by the photoimageable layers  106 . As shown in  FIG. 4C , thermal pipes  470  can include thermal traces  470   b  and  470   d  and/or vias  470   a  and  470   c  that penetrate one or more interconnect layers  122  and/or photoimageable layers  106 . The thermal pipes  470  can be configured to dissipate heat, conduct electrical signals, or both. In one embodiment, an interconnect layer for transmitting electrical signals and a thermal pipe that is not suitable for transmitting electrical signals are embedded within the same epoxy layer. 
     Another embodiment of the present invention is illustrated in  FIG. 4E . Package arrangement  450  includes a microsystem  452  formed on the top surface  460  of substrate  456 . Microsystem  452  may include multiple dielectric layers, interconnect layers, active and/or passive components and can have any of the features described in connection with package  100  of  FIG. 1  and/or package  400  of  FIG. 4A . Microsystem  452  and top surface  460  of substrate  465  are encapsulated in molding material  464 , which may be made of any suitable material, such as a thermosetting plastic. Multiple metallic vias  458  electrically couple external pads (not shown) on the bottom of microsystem  452  with the bottom surface  461  of substrate  456 . The vias  458  terminate at optional solder balls  462 , which can be made from various conductive materials. Solder balls  462  may be mounted on, for example, a printed circuit board to enable electrical connections between microsystem  452  and various external components. 
       FIGS. 5A-5J  illustrate cross-sectional views of a wafer level process for building a package similar to arrangement  450  of  FIG. 4D .  FIG. 5A  depicts a wafer  500  with a top surface  502  and a bottom surface  504 . Only a small portion of wafer  500  is shown. The dotted vertical lines indicate projected scribe lines  508 . In the illustrated embodiment, substrate  500  can be made of a variety of suitable materials, such as silicon. 
     In  FIG. 5B , the top surface  502  of wafer  500  is etched to form holes  506 . This etching process may be performed using a variety of techniques, such as plasma etching. Afterwards, metal is deposited into the holes to form an electrical system. This deposition may be performed using any suitable method, such as electroplating. For example, a seed layer (not shown) may be deposited over top surface  502  of wafer  500 . The seed layer may then be electroplated with a metal such as copper. The electroplating process can produce metal vias  510  and contact pads  512  on the top surface  502  of wafer  500 . 
     In  FIG. 5D , microsystems  513  are formed on the top surface  502  of wafer  500  using steps similar to those described in connection with FIGS.  2  and  3 A- 3 L. In the illustrated embodiment, microsystems  513  do not have external contact pads formed on their top surfaces  515 , as the top surfaces  515  will be overmolded in a later operation. In another embodiment, external contact pads are formed on top surfaces  515  to enable wafer level functional testing prior to overmolding. Microsystems  513  have external contact regions on their bottom surfaces  517 , which are aligned with the contact pads  512  on the top surface  502  of wafer  500 . This facilitates an electrical connection between the metal vias  510  and the interconnect layers within the microsystems  513 . 
     In  FIG. 5E , a suitable molding material  520  is applied over the microsystems  513  and the top surface  502  of the wafer  500 . The molding process can be performed using a variety of suitable techniques and materials. As a result, a molded wafer structure  522  is formed. In some designs, the molding material  520  completely covers and encapsulates microsystems  513  and/or the entire top surface  502 . The application of molding material  520  may provide additional mechanical support for microsystems  513 , which may be useful when microsystems  513  are large. 
       FIG. 5F  depicts molded wafer structure  522  after the bottom surface  504  of wafer  500  has been partially removed using any of a range of suitable techniques, such as backgrinding. As a result, portions of metal vias  510  are exposed. In  FIG. 5G , solder balls  524  are applied to the exposed portions of metal vias  510 . In  FIG. 5H , the molded wafer structure  522  is then singulated along projected scribe lines  508  to create individual package arrangements  526 . The singulation process can be performed using a variety of appropriate methods, such as sawing or laser cutting. 
       FIGS. 6A-6C  illustrate cross-sectional views of a wafer level process for building a package according to another embodiment of the present invention.  FIG. 6A  shows a substrate  600  prefabricated with through holes  602 .  FIG. 6B  illustrates the deposition of metal into the holes  602  to form metal vias  604 . The deposition of metal can be performed using any suitable technique, such as electroplating. In some embodiments, the substrate  600  comes prefabricated with through holes  602  and/or metal vias  604 , thus eliminating one or more processing steps. In  FIG. 6C , microsystems  606  are formed over the metal vias  604  and the substrate  600  using any of the aforementioned techniques. Afterward, solder bumping and singulation can be performed, as shown in  FIGS. 5G and 5H . The illustrated embodiment can include various features like those described in connection with  FIGS. 5A-5H . 
       FIGS. 7A-7C  illustrate cross-sectional views of a wafer level process for building a package according to another embodiment of the present invention. Initially, a substrate  700  is provided. Copper pads  702  are then formed over the top surface of the substrate  700 . In  FIG. 7B , microsystems  704  are formed over copper pads  702  and substrate  700  using any of the aforementioned techniques. The microsystems  704  and the top surface of the substrate  700  are then encapsulated in a suitable molding material  706 . The substrate  700  is then entirely ground away or otherwise removed in  FIG. 7C . Afterward, solder bumps can be attached to copper pads  702 . The illustrated embodiment can include various features like those described in connection with  FIGS. 5A-5H . 
     Although only a few embodiments of the invention have been described in detail, it should be appreciated that the invention may be implemented in many other forms without departing from the spirit or scope of the invention. Therefore, the present embodiments should be considered as illustrative and not restrictive and the invention is not limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.