Patent Publication Number: US-11386939-B2

Title: Read data FIFO control circuit

Description:
BACKGROUND 
     In a memory device such as a DRAM including a plurality of memory banks, a so-called “pipeline operation” is performed in which operations of the memory banks overlap with each other to realize a high-speed operation. Meanwhile, an output circuit is shared by the memory banks. Therefore, a FIFO circuit is provided at a previous stage of the output circuit to enable data output from the memory banks to be sequentially output without collision. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing an overall configuration of a semiconductor device according to the present disclosure. 
         FIG. 2  is a block diagram illustrating a configuration of main parts of the semiconductor device according to the present disclosure. 
         FIG. 3  is a block diagram illustrating a configuration of an FIFO circuit shown in  FIG. 2 . 
         FIG. 4  is a circuit diagram of a data amplifier. 
         FIG. 5  and  FIG. 6  are timing diagrams for explaining an operation of the semiconductor device according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments of the present invention will be explained below in detail with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings that show, by way of illustration, specific aspects and embodiments in which the present invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present invention. Other embodiments may be utilized, and structural, logical and electrical changes may be made without departing from the scope of the present invention. The various embodiments disclosed herein are not necessary mutually exclusive, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments. 
     A FIFO circuit placed between a plurality of memory banks and an output circuit includes a plurality of data registers storing a plurality of read data corresponding to a plurality of read commands to the memory banks, respectively. Input and output of read data to and from the data registers is controlled by point values. Specifically, control is executed such that one of the data registers indicated by an input point value generated in response to a read command is indicated by a same output point value as the input point value also at a time of output to enable a read data to be output from the data register. For example, when a read data that is read from a first memory bank is stored into a first data register indicated by a first input point value, it is necessary to generate a first output point value same as the first input point value after a predetermined latency count and to output the read data from the first data register indicated by the first output point value. If the point values differ, a read data that is read from another memory bank having been previously accessed is output instead of the read data that is read from the first memory bank and correct read control cannot be executed. Normally, a read command is input to an activated memory bank (a plurality of memory cells are in a selected state). However, there is also a case where an illegal read command is input to a non-activated memory bank (no memory cells are in a selected state) and it is important to perform designing to prevent the point values from differing also in this case. 
     A semiconductor device shown in  FIG. 1  includes a memory cell array  10 , an access control circuit  12  that performs an access operation to the memory cell array  10 , and a data control circuit  14  that externally outputs read data D 1  read from the memory cell array  10  and that supplies write data DQ externally input to the memory cell array  10 . The memory cell array  10  is divided into k+1 memory banks  20  to  2   k.  Nonexclusive accesses can be performed to different memory banks. The access control circuit  12  generates an internal command signal ICMD on the basis of a chip select signal CS and an external command signal CMD, which are externally supplied, and performs a read access or a write access to the memory banks  20  to  2   k  on the basis of the internal command signal ICMD. When a read access is performed, an internal read data D 1  is output from a selected one of the memory banks  20  to  2   k.  The internal read data D 1  is asynchronous with a clock signal ICLK. The data control circuit  14  receives the internal read data D 1  and outputs an external read data DQ synchronous with the clock signal ICLK to outside the semiconductor device. 
     As shown in  FIG. 2 , when the internal command signal ICMD is supplied to a read command decoder  31 , the read command decoder  31  supplies a read command RCMD to a selected one of the memory banks  20  to  2   k.  In response thereto, the selected one of the memory banks  20  to  2   k  performs a read operation and outputs a data stored at an indicated address as the internal read data D 1 . At this time, the selected one of the memory banks  20  to  2   k  activates a timing signal DSEL synchronously with the internal read data D 1 . The internal read data D 1  is supplied to a FIFO circuit  40 . The FIFO circuit  40  is included in the data control circuit  14  shown in  FIG. 1 . 
     As shown in  FIG. 3 , the FIFO circuit  40  has m+1 registers being registers  50  to  5   m.  The internal read data D 1  is supplied in common to the registers  50  to  5   m  and the internal read data D 1  is overwritten to one of the registers  50  to  5   m  indicated by an input point value DSEL&lt;i&gt;(in) (i=0 to m). The internal read data D 1  stored into one of the registers  50  to  5   m  indicated by an output point value OSEL&lt;i&gt;(out) (i=0 to m) is output as the external read data DQ. The input point value DSEL&lt;i&gt;(in) and the output point value OSEL&lt;i&gt;(out) are generated by decoders  40  and  42  shown in  FIG. 2 , respectively. The decoder  41  decodes a count value CDSEL&lt;n: 0 &gt; of a counter  43  to generate the input point value DSEL&lt;i&gt;(in) and outputs the input point value DSEL&lt;i&gt;(in) to the FIFO circuit  40  synchronously with the timing signal DSEL. The decoder  42  decodes a count value COSELP&lt;n: 0 &gt; of a counter  44  to generate the output point value OSEL&lt;i&gt;(out) and outputs the output point value OSEL&lt;i&gt;(out) to the FIFO circuit  40  synchronously with a timing signal OSEL. 
     The timing signal OSEL is generated by delaying the read command RCMD through a latency control circuit  32 . The latency control circuit  32  includes a shift register circuit and outputs the timing signal OSEL at a timing when the internal clock signal ICLK has been activated a predetermined number of times after the read command RCMD is generated. The timing signal OSEL indicates a timing when the internal read data D 1  is output from the selected one of the memory banks  20  to  2   n  after the read command RCMD is activated, and is synchronous with the internal clock signal ICLK. While a timing of actually outputting the internal read data D 1  is indicated by the timing signal DSEL, the timing signal DSEL is asynchronous with the internal clock signal ICLK. The latency control circuit  32  activates an active judge signal AJ(out) immediately before outputting the timing signal OSEL. The active judge signal AJ(out) is supplied to a FIFO circuit  33 . The FIFO circuit  33  is a circuit that retains a bank active signal BACT, and uses a read command RCMD(in) as an increment signal for the input point value and uses the active judge signal AJ(out) as the output point value. The bank active signal BACT is a signal indicating whether the read command RCMD is issued to one of the memory banks  20  to  2   k  in an active state. When the read command RCMD is issued to one of the memory banks  20  to  2   n  in an inactive state, the read operation is not actually performed. Therefore, the active judge signal AJ output from the FIFO circuit  33  indicates whether the timing signal OSEL corresponding thereto is valid. When the active judge signal AJ synchronous with a certain timing signal OSEL is in a non-activated state (a low level), a count signal OSEL_AJ output from a NAND gate circuit  34  that receives the timing signal OSEL and the active judge signal AJ is fixed to a high level. Accordingly the count value of the counter  44  is not updated even when the timing signal OSEL is activated. When such an illegal access is performed, the timing signal DSEL is not output from the memory banks  20  to  2   k  and therefore no difference occurs between the count value of the counter  43  and the count value of the counter  44 . 
     As shown in  FIG. 4 , the internal read data D 1  is output in response to activation of a data amplifier enable signal DAE. A read data D 0  read from a memory cell array in the memory banks  20  to  2   k  is supplied to a data amplifier  60 . The data amplifier  60  has a configuration in which P-channel MOS transistors P 1  and P 2  and N-channel MOS transistors N 1  and N 2  are cross-coupled. A power supply potential VPERI is supplied to sources of the transistors P 1  and P 2 . A source of the transistor N 1  is connected to an output node of an inverter circuit  63  via an N-channel MOS transistor N 3  and a source of the transistor N 2  is connected to the output node of the inverter circuit  63  via an N-channel MOS transistor N 4 . Gate electrodes of the transistors N 3  and N 4  are connected to global I/O lines GIOT and GIOB supplied with read data D 0 T and D 0 B, respectively. The data amplifier enable signal DAE is supplied to the inverter circuit  63 . With this configuration, when the data amplifier enable signal DAE changes to a high level, the data amplifier  60  is activated and a read data D 2  is output from the data amplifier  60 . The read data D 2  is subjected to error correction processing by an error correction circuit  61  and is thereafter supplied as the internal read data D 1  to the FIFO circuit  40 . The data amplifier enable signal DAE is also supplied to a replica circuit  62 . The replica circuit  62  provides a delay amount same as that of the error correction circuit  61  to the data amplifier enable signal DAB to generate the timing signal DSEL. Accordingly, a timing when the timing signal DSEL is activated matches an output timing of the internal read data D 1 . When the data amplifier enable signal DAE changes to a low level, P-channel MOS transistors P 3  to P 6  are turned on to inactivate the data amplifier  60 . 
     An operation of the semiconductor device according to the present disclosure is explained next with reference to  FIGS. 5 and 6 . In an example shown in  FIG. 5 , a chip select signal CS is activated and a read command RD is issued at each of times t 11  to t 15 . The read commands RD issued at the times t 11  to t 15  are all valid read commands RD. That is, the read commands RD are issued to memory banks in an active state. Accordingly, the bank active signal BACT is kept at a high level. In the example shown in  FIG. 5 , the read commands RD issued at the times t 11  to t 15  indicate bank addresses BA 0 , BA 1 , BA 7 , BA 0 , and BA 1 , respectively. When a read command RD is issued, the read command decoder  31  shown in  FIG. 2  generates a read command RCMD. In the example shown in  FIG. 5 , because the read commands RD issued at the times t 11  to t 15  are all valid read commands RD, the corresponding memory banks start a read operation in response to the read commands RCMD, respectively. When the read operation is completed, the timing signal DSEL and the read data D 1  are output from each of the corresponding memory banks. The timing signal DSEL is supplied to the counter  43  shown in  FIG. 2 , whereby the count value CDSEL&lt;n: 0 &gt; of the counter  43  is incremented. In the example shown in  FIG. 5 , the count value CDSEL&lt;n: 0 &gt; of the counter  43  is incremented to &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt; in this order. The decoder  41  decodes the count values CDSEL&lt;n: 0 &gt; of &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt; and activates the input point value DSEL&lt;i&gt;(in) synchronously with the timing signals DSEL. Therefore, in the example shown in  FIG. 5 , the input point value DSEL&lt;i&gt;(in) is activated in the order of &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt;. 
     The read commands RCMD are provided with a predetermined delay by the latency control circuit  32  and are output as the timing signals OSEL from the latency control circuit  32 . In the examples shown in  FIGS. 5 and 6 , a read latency is 10 (RL=10). A timing when the timing signal OSEL is activated is slightly delayed from a timing when the timing signal DSEL is activated. Because the bank active signal BACT is kept at a high level in the example shown in  FIG. 5 , the active judge signal AJ is also kept at a high level. Accordingly each time the timing signal OSEL is activated, the count signal OSEL_AJ is also activated, whereby the count value COSELP&lt;n: 0 &gt; of the counter  44  is sequentially incremented. In the example shown in  FIG. 5 , the count value COSELP&lt;n: 0 &gt; of the counter  44  is incremented to &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt; in this order. The decoder  42  decodes the count value COSELP&lt;n: 0 &gt; of &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt; and activates the output point value OSEL&lt;i&gt;(out) synchronously with the timing signals OSEL. Therefore, in the example shown in  FIG. 5 , the output point value OSEL&lt;i&gt;(out) is activated in the order of &lt;i&gt;, &lt;i+1&gt;, &lt;i+2&gt;, &lt;i+3&gt;, and &lt;i+4&gt;. 
     Accordingly, the read data D 1  output from the memory banks  20  to  2   n  are sequentially stored into the registers included in the FIFO circuit  40  and are sequentially selected to be output as the read data DQ. 
     In the example shown in  FIG. 6 , the chip select signal CS is activated and the read command RD is issued at each of times t 21  to t 25 . However, the read commands RD issued at the times t 23  and t 25  are both illegal read commands RD. That is, the read commands RD are issued to memory banks in an inactive state at the times t 23  and t 25 . Accordingly the bank active signal BACT changes to a low level at the times t 23  and t 25 . In this way, because the read commands RD issued at the times t 23  and t 25  are illegal read commands RD in the example shown in  FIG. 6 , read operations in response to these read commands RD are not performed and the timing signals DSEL and the read data D 1  in response to these read commands RD are not output. Therefore, the count value CDSEL&lt;n: 0 &gt; of the counter  43  is not incremented in response to the illegal read commands RD. Accordingly, the count value CDSEL&lt;n: 0 &gt; of the counter  43  is incremented to &lt;i&gt;, &lt;i+1&gt;, and &lt;i+2&gt; in this order and the decoder  41  activates the input point value DSEL&lt;i&gt;(in) in the order of &lt;i&gt;, &lt;i+1&gt;, and &lt;i+2&gt; synchronously with the timing signals DSEL. 
     Meanwhile, the read command RCMD is provided with a predetermined delay by the latency control circuit  32  and is output as the timing signal OSEL from the latency control circuit  32 , regardless of whether the read command RD is illegal. That is, even if the read command RD is illegal, the timing signal OSEL is activated after the predetermined latency is elapsed. However, when an illegal read command RD is issued, the bank active signal BACT changes to a low level and is accumulated in the FIFO circuit  33 . Because the bank active signal BACT accumulated in the FIFO circuit  33  is output as the active judge signal AJ after the predetermined latency is elapsed, the count signal OSEL_AJ is not activated even when the timing signal OSEL is activated in response to the illegal read command RD. Accordingly, the count value COSELP&lt;n: 0 &gt; of the counter  44  is incremented in response to correct read commands RD. That is, the count value COSELP&lt;n: 0 &gt; of the counter  44  is incremented to &lt;i&gt;, &lt;i+1&gt;, and &lt;i+2&gt; in this order and the decoder  42  activates the output point value OSEL&lt;i&gt;(out) in the order of &lt;i&gt;, &lt;i+1&gt;, and &lt;i+2&gt; synchronously with the timing signals OSEL. 
     Accordingly, even in a case where an illegal read command RD is issued, the difference between the count value CDSEL&lt;n: 0 &gt; of the counter  43  and the count value COSELP&lt;n: 0 &gt; of the counter  44  is always kept constant. 
     As described above, the semiconductor device according to the present disclosure generates the input point value DSEL&lt;i&gt;(in) using the timing signal DSEL output from the memory banks  20  to  2   n.  Accordingly, a FIFO circuit for managing the read command RCMD is not required unlike in a case of generating the input point value DSEL&lt;i&gt;(in) using the read command RCMD. Meanwhile, the FIFO circuit  33  for managing the bank active signal BACT is required. However, the FIFO circuit  33  for managing the bank active signal BACT is a circuit that merely manages one bit of the bank active signal BACT and is thus sufficiently smaller in the circuit scale than a FIFO circuit for managing the read command RCMD. 
     Although this invention has been disclosed in the context of certain preferred embodiments and examples, it will be understood by those skilled in the art that the inventions extend beyond the specifically disclosed embodiments to other alternative embodiments and/or uses of the inventions and obvious modifications and equivalents thereof. In addition, other modifications which are within the scope of this invention will be readily apparent to those of skill in the art based on this disclosure. It is also contemplated that various combination or sub-combination of the specific features and aspects of the embodiments may be made and still fall within the scope of the inventions. It should be understood that various features and aspects of the disclosed embodiments can be combined with or substituted for one another in order to form varying mode of the disclosed invention. Thus, it is intended that the scope of at least some of the present invention herein disclosed should not be limited by the particular disclosed embodiments described above.