Patent Publication Number: US-5022047-A

Title: Spread spectrum correlator

Description:
BACKGROUND OF THE INVENTION 
     This invention relates to spread spectrum communications, and more particularly to a non-code synchronous spread spectrum communications system. 
     DESCRIPTION OF THE PRIOR ART 
     A spread spectrum system is one in which the signal is spread over a band much wider than the maximum bandwidth required to transmit the information being sent. Techniques for direct sequence spread spectrum modulation have been developed for several years to ensure secure communications. Modulation is achieved by mixing the information to be sent with a periodic pseudo-noise (PN) code. The result is a sin(X)/X signal with a very wide bandwidth, as compared to the information, and low spectral density. This spectral density reduces the signal&#39;s sensitivity to in-band interference and jamming, as well as reducing interference with other radio sensitive equipment. Among the other advantages inherent to a spread spectrum system are selective addressing capabilities, code division multiplexing for multiple access, and highly accurate ranging capabilities. 
     Due to the encoded nature of the signal, demodulation is a more involved process than with traditional communications systems, and involves a reference code, identical to that transmitted, synchronized to the received code. The difficulty with this process is that there is no indication of the degree of non-synchronization between received and reference codes until a very high degree of synchronization is achieved. Additionally, mismatches between transmit and receive oscillators used to generate PN codes tend to cause drift in the synchronization between transmitter and receiver 
     A prior art communications system using two pseudo-random waveforms and two correlators for designating a MARK or a SPACE, is disclosed in U.S. Pat. No. 4,247,942, to Hauer, issued Jan. 27, 1981, which is incorporated herein by reference. Hauer discloses in a communication system, a first delay line having multiple spaced taps for supplying successive input pulses to the delay line. In response to each input impulse, variously delayed pulses appear at the taps of the delay line, which are used to generate pulses representing a MARK or a SPACE. His disclosure includes synchronous detectors, and means for supplying the carrier-transmitted pulses to the detectors. 
     None of the prior art teaches or suggests an apparatus for acquiring a spread spectrum signal using one correlator, nor an apparatus having an acquisition time of a spread spectrum signal equal to the time duration of one data bit on every data bit. Further, none of the prior art teaches dual threshold detection in a single correlator such that a first data symbol and a second data symbol can be determined with equal accuracy in one correlator, nor the use of a plurality of such dual threshold detection correlators to achieve a doubling of the data rate for each additional dual threshold detection correlator without increasing the code rate or the signal acquisition time. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     An object of the invention is to provide an apparatus for acquiring a spread spectrum signal using one correlator which is direct, inexpensive, and simple to use. 
     Another object of the invention is to provide an apparatus for acquiring a spread spectrum signal that has a dual threshold detection capability in one correlator for determining the occurrence of a first data symbol or a second data symbol. 
     A still further object of the invention is to provide an apparatus for detecting a spread spectrum signal without the use of a synchronous reference code. 
     An additional object of the invention is to provide an apparatus which will acquire a spread spectrum signal on each data bit received at the rate the data is transmitted with no time loss due to code synchronization and without use of any code synchronization preambles. 
     A further object of the invention is to provide the ability to use a plurality of dual threshold detection correlators (DTDCs). 
     Another object of the invention is to provide a plurality of DTDCs such that the transmitted and received data symbol rate can be increased without increasing the transmitted and received code bit rate, nor increasing the bandwidth of the frequency spectrum which is utilized. 
     An additional object of the present invention is that for the plurality of DTDCs, the transmitted and received data symbol rate can be increased by a factor of two while the required number of correlators in the receiver increases by an increment of one. 
     An additional object of the present invention is that for the plurality of DTDCs, the time for acquiring the spread spectrum signal remains constant even as the transmitted and received data symbol rate increases. 
     According to the present invention, as embodied and broadly described herein, an apparatus for decoding a received spread spectrum signal, which includes a data signal modulated with a PN code, is provided, comprising threshold setting means, first reference-sequence-storage means, receive-sequence-storage means, first correlating means, and comparison means. The first correlating means may include first chip-comparison means and first summer means. The present invention may additionally include second reference-sequence-storage means, and second correlating means. The second correlating means may include second chip-comparison means and second summer means. 
     The threshold setting means may set the threshold for a match equal to or less than the total number of chips per code being acquired. The threshold setting means may analyze the pattern and application of the data to be transmitted and/or received using the spread spectrum signal, the noise environment, and the amount of error correction used with the data signal In response to this analysis, the threshold setting means generates a threshold level. The threshold setting means may be used to predetermine each threshold for a specific device, application, or operating environment, or it may be coupled to the spread spectrum receiver and used to set and adjust one or more threshold levels as the application or operating environment changes. 
     For the case of one correlator having a dual threshold capability, the first reference-sequence-storage means stores a first pseudo-noise signal, and the receive-sequence-storage means stores the received spread spectrum signal. The first chip-comparison means, which is coupled to the first reference-sequence-storage means and the receive-sequence-storage means, compares each chip of the received spread spectrum signal with each respective chip of the first pseudo-noise signal to generate a first plurality of chip-comparison signals. The first summer means, which is coupled to the first chip-comparison means, adds the first plurality of chip-comparison signals and thereby generates a first correlation signal. For a digital correlator implementation, in response to the first correlation signal being greater than the upper-threshold level, the comparison means generates a first data-symbol signal. In response to the first correlation signal being less than the lower-threshold level, the comparison means generates a second data-symbol signal. 
     For an analog correlator implementation, in response to the first correlation signal being greater than an analog-threshold level, the comparison means generates a first data-symbol-correlation signal. In response to the first inverse-correlation signal being greater than the analog-threshold level, the comparison means generates a second data-symbol-correlation signal. 
     For the case of two correlators, each having a dual threshold capability, the first reference-sequence-storage means stores a first pseudo-noise signal, the second reference-sequence-storage means stores a second pseudo-noise signal, and the receive-sequence-storage means stores the received spread spectrum signal The first chip-comparison means is coupled to the first reference-sequence-storage means and the receive register means. In response to the received spread spectrum signal, the first chip-comparison means compares each chip of the received spread spectrum signal with each respective chip of the first pseudo-noise signal and thereby generates a first plurality of chip-comparison signals. The first summer means is coupled to the first chip-comparison means. In response to the first plurality of chip-comparison signals from the first chip-comparison means, the first summer means adds the first plurality of chip-comparison signals and thereby generates a first correlation signal. 
     The second chip-comparison means is coupled to the second reference-sequence-storage means and the receive-sequence-storage means. In response to the received spread spectrum signal, the second chip-comparison means compares each chip of the received spread spectrum signal with each respective chip of the second pseudo-noise signal and thereby generates a second plurality of chip-comparison signals. The second summer means is coupled to the second chip-comparison means. In response to the second plurality of chip-comparison signals, the second summer means adds the second plurality of chip-comparison signals and thereby generates a second correlation signal. 
     The comparison means is coupled to the first summer means and the second summer means. The comparison means for the digital correlator implementation includes upper- and lower-threshold levels for each reference-sequence-storage means. In response to the first correlation signal being greater than the upper-threshold level, the comparison means generates a first data-symbol signal. In response to the first correlation signal being less than the lower-threshold level, the comparison means generates a second data-symbol signal. In response to the second correlation signal being less than the lower-threshold level, the comparison means generates a third data-symbol signal. In response to the second correlation signal being greater than the upper-threshold level, the comparison means generates a fourth data-symbol signal. 
     The comparison means for the analog correlator implementation includes first and second threshold levels, which may be equivalent for each reference-sequence-storage means. In response to the first correlation signal being greater than the first threshold level, the comparison means generates a first data-symbol signal. In response to the first inverted correlation signal being greater than the second threshold level, the comparison means generates a second data-symbol signal. In response to the second inverse correlation signal being greater than the second threshold level, the comparison means generates a third data-symbol signal. In response to the second correlation signal being greater than the first threshold level, the comparison means generates a fourth data-symbol signal. 
     Statistically, the accuracy of detection depends, in part, upon the threshold level settings, which may be a function of several variables: The total number of matched chips to the total number of chips on a per data symbol basis, the error rate and the degree of forward error correction on the input signal, and whether the data stream to be processed is continuous, cyclically repetitive, patterned, episodic, pulsed or random. 
     The present invention may further include a plurality of reference-sequence-storage means for storing a plurality of pseudo-noise signals with means for correlating the received spread spectrum signal with the plurality of pseudo-noise signals. The correlating means would thereby generate a plurality of correlation signals, depending on the particular received spread spectrum signal. Likewise, the comparison means would be responsive to the plurality of correlation signals for generating one of a plurality of data-symbol signals in response to the correlation signals crossing a particular threshold level in one of the DTDC reference-sequence-storage means. 
     Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate a preferred embodiment of the invention, and together with the description serve to explain the principles of the invention. 
     FIG. 1 is a block diagram for a particular embodiment of a transmitter according to the present invention; 
     FIG. 2 is a timing diagram for a particular signal according to the present invention; 
     FIG. 3 illustrates one embodiment of a receiver according to the present invention; 
     FIG. 4 is a block diagram of a second embodiment of a transmitter according to the present invention; 
     FIG. 5 is a block diagram of a second embodiment of a receiver according to the present invention; and 
     FIG. 6 illustrates an analog embodiment of the present invention as exemplified by a SAW correlator. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. 
     The present invention includes an apparatus for transmitting and decoding a received spread spectrum signal having a data signal modulated with a PN code to produce a spread spectrum signal. As illustratively shown in FIG. 1, a transmitter is shown including a code clock generator 21, code selector 28, code generator 22, code clock divider 23, pulse generator 24, data generator 25, modulo 2 adder 26, carrier 29, and phase shift keyed (PSK) modulator and RF transmitter 27. The code clock generator 21 generates a clock signal which is fed to the code generator 22 and to the clock divider 23. Using clock divider 23, the code and the data of the transmitter 27 are synchronized, with the code clock frequency being a multiple equal to the code length, L, of the data clock frequency thereby allowing one data bit per PN code sequence of length L. The data clock signal from code clock divider 23 is fed to the pulse generator 24 and to the data generator 25. The data generator 25 is the source of the data signal to be transmitted over the communications system. The output signal of the pulse generator 24 is fed to the code generator 22 which thereby generates a PN code chosen by code selector 28. The PN code, which is recursive, is then fed out of to the data fed from the data generator 25. The output of the the code generator 22 and modulo 2 added with modulo 2 adder 26 modulo adder 26 is the data signal modulated with the PN code, which is phase shift keyed modulated with a carrier 29 in PSK modulator and RF transmitter 27. 
     An example of the timing of the code and clock signals of FIG. 1 is shown in FIG. 2. The timing diagram illustrates a code clock signal, a data clock signal which is the code clock signal divided by the length of code, L, pulse generator reset signal, and the code signal, the data signal, and the encoded data signal. The code signal, when modulo 2 added with the data signal produces the encoded data signal and when modulated by an RF carrier produces a spread spectrum signal. The transmitted spread spectrum signal may be received by the receiver illustrated in FIG. 3. 
     While FIG. 3 illustrates a particular embodiment of one dual threshold detection correlator receiver of the present invention, the present invention in general includes an apparatus for decoding a received spread spectrum signal having a data signal modulated with a PN code. The apparatus comprises threshold means, first reference-sequence-storage means, receive-sequence-storage means, first correlating means, and comparison means. The first correlating means may include first chip-comparison means and first summer means. With reference to FIG. 3, the first reference-sequence-storage means may be embodied as reference registers 33, the receive-sequence-storage means may be embodied as receive registers 39, the first chip-comparison means may be embodied as first adders 40, the first summer means may be embodied as first summer 41, and the comparison means may be embodied as first and second symbol comparators 42, 43. The threshold setting means may be embodied as threshold setter device 45. The first adders 40 are coupled to the first reference registers 33 and the receive registers 39. First summer 41 is coupled to first adders 40. 
     In the exemplary arrangement shown in FIG. 3, a count control 30 may be coupled to a code clock generator 31 which is connected to a code generator 32 and reference registers 33. The code generator 32 is also connected to the reference registers 33. A code selection circuit 34 is coupled to code generator 32. The count control 30 controls the length of the particular pseudo-noise signal chosen by code selection circuit 34 to be detected by the receiver, and outputs signals to the code clock generator 31 which causes the code generator 32 to output a code of length L to first reference registers 33. Count control 30 triggers code clock generator 31 which thereby triggers code generator 32 and first reference registers 33. Code generator 32 outputs the particular pseudo-noise signal to first reference registers 33 as determined by a code selection circuit 34. The code selection circuit 34 can provide signals to the code generator 32 which enable it to scan through a plurality of pseudo noise codes. In operation, a single code can be loaded into the first reference registers 33 or, in a scanning mode, the first reference registers 33 can be periodically loaded with constantly varying codes until a match to a received code occurs. 
     Also shown in FIG. 3 is RF and IF amplifiers 35, coupled to a product detector 36 which is coupled to a local oscillator 37 and a low pass filter 38. The low pass filter 38 is coupled to receive registers 39 and clock recovery circuit 46. 
     For the case of one correlator having a dual threshold capability, the first reference registers 33 stores a first pseudo-noise signal, and the receive registers 39 stores the received spread spectrum signal. The first adders 40 compares each chip of the received spread spectrum signal with each respective chip of the first pseudo-noise signal to generate a first plurality of chip-comparison signals. The first summer 41 adds the first plurality of chip-comparison signals and thereby generates a first correlation signal. In response to the first correlation signal being greater than the upper-threshold level, the comparator 42 generates a first data-symbol signal. In response to the first correlation signal being less than the lower-threshold level, the comparator 42 generates a second data-symbol signal. 
     In operation a received spread spectrum signal having a data signal modulated with the PN code would be stored in receive registers 39 and the entire length, L, of a first pseudo-noise signal would be stored in first reference registers 33. Each chip of the received spread spectrum signal is modulo 2 added by each respective chip of the first reference pseudo-noise signal by first adders 40. This modulo addition of the two signals would thereby generate a first plurality of chip-comparison signals which would be transferred from first adders 40 to first summer 41. The first summer 41 adds the first plurality of signals to generate a first correlation signal. 
     The first symbol comparator 42 and second symbol comparator 43 are coupled to the first summer 41. The comparators 42, 43 have an upper-threshold level and a lower-threshold level. In response to the first correlation signal being greater than the upper-threshold level, the first symbol comparator 42 generates a first data-symbol-correlation signal. In response to the first correlation signal being less than the lower-threshold level, the second symbol-comparator 43 generates a second data-symbol-correlation signal. Data generator 47 thereby generates first or second data symbols, per the first or second data-symbol-correlation signal, respectively. The first and second data-symbol signals may be, respectively, 1-bit and 0-bit data signals. 
     The present invention can further include using two or more, up to N, different recursive sequences, with an example using two as illustrated in FIG. 4. In this particular case, a first code generator 52 and a second code generator 53 each generate a difference recursive sequence as chosen by code selector 62 for generating a spread spectrum code signal. Code clock generator 51 feeds code clock to code generator A 52 and code generator 53 as well as divider 54. Divide by L/2 feeds a clock signal, which has a period equal to twice that of a code sequence of length L, to divide 2 56, two stage shift registers 58, and data generator 55. Thus, two data bits per code length L are generated by data generator 55 and stored in parallel in two stage shift registers 58. Divider 56 feeds a clock signal per once code segment of length L to sampler 57 and pulse generator 59 which resets code generator A 52 and code generator 53. Sampler 57 outputs two signals to selector 60, which determine which of four code segments (code A, inverse code A, code B, inverse code B) which it revives from code generator A 52 and code generator B 53. The modulated code is then transferred from selector 60 to PSK modulator and RF transmitter 61 where it is PSK modulated with an RF carrier 63 in the transmitter. Transmitting a spread spectrum signal using the circuitry of FIG. 4 has an advantage in that as shown in FIG. 5, as a particular embodiment of the present invention, a receiver can be implemented using only two correlators for detecting four possible spread spectrum received codes. The particular codes are actually two spread spectrum PN codes, with 180° phase reversals. 
     Thus, the present invention can further include second reference-sequence-storage means, second chip-comparison means, and second summer means. The second reference-sequence-storage means may be embodied as the second reference registers 73, the second chip-comparison means may be embodied as second adders 80, and the second summer may be embodied as second summer 81. The second reference-registers 73 stores a second pseudo-noise signal. The second adders 80 are coupled to the second reference-registers 73 and the receive registers 39. 
     For the case of two correlators as illustratively shown in FIG. 5, each having a dual threshold capability, the first adders 40 compares each chip of the received spread spectrum signal with each respective chip of the first pseudo-noise signal and thereby generates a first plurality of chip-comparison signals. The first summer 41 is coupled to the first adders 40. In response to the first plurality of chip-comparison signals from the first adders 40, the first summer 41 adds the first plurality of chip-comparison signals and thereby generates a first correlation signal. 
     The second adders 80 are coupled to the second reference registers 73 and the receive registers 39. In response to the received spread spectrum signal, the second adders 80 compares each chip of the received spread spectrum signal with each respective chip of the second pseudo-noise signal and thereby generates a second plurality of chip-comparison signals. The second summer 81 is coupled to the second adder 80. In response to the second plurality of chip-comparison signals, the second summer 81 adds the second plurality of chip-comparison signals and thereby generates a second correlation signal. 
     In this particular embodiment, the comparison means is embodied as comparison circuit 97. The comparison circuit 97 has upper- and lower-threshold levels. The comparison circuitry 97 is coupled to the first summer 41 and the second summer 81. In response to the first correlation signal from the first summer 41 being greater than its upper-threshold level the comparison circuitry 97 generates a first data-symbol-correlation signal. In response to the first correlation signal from summer 41 being less than its lower-threshold level, the comparison circuitry 97 generates a second data-symbol-correlation signal. In response to the second correlation signal from second summer 81 being greater than its upper-threshold level, comparison circuitry 97 generates a third data-symbol-correlation signal. In response to the second correlation signal from second summer 81 being less than its lower-threshold level, the comparison circuitry 97 generates a fourth data-symbol signal. Data generator 98 then generates the data symbol corresponding to the received data-symbol-correlation signal. The first, second, third, and fourth data-symbol signals may represent, for example, data bits 00, 01, 10, and 11. 
     While the present invention has disclosed using either a first correlator as shown in FIG. 3 or a first and second correlator as shown in FIG. 5, the present invention may be extended to using a plurality of correlators where the decoding decodes a plurality of data-symbol signals. 
     By using a plurality of DTDCs in the receiver, a code of length L can be used to transmit and receive a number of data symbols equal to twice the number of DTDCs in the receiver. Another advantage of using a plurality of DTDCs is that while the transmitted and received data symbol rate doubles with each additional DTDC, the code length, L, the aggregate code chip rate, and the bandwidth of the frequency spectrum used, all remain fixed. Moreover, the time to acquire the spread spectrum signal remains fixed, and the system remains inexpensive and simple. The code selection circuit can provide signals to the code generators which enable them to scan through a plurality of pseudo noise codes. In operation, single code sets can be loaded into the reference registers or, in a scanning mode, the reference registers can be periodically loaded with constantly varying codes until a match to a received code occurs. 
     In the system provided by this invention, a pseudo-noise signal may include a PN code segment having L bits produced with a clock rate equivalent to Lx(R d  /S d ), where R d  is the clock rate of the data to be modulated, and S d  is the number of data bits per code segment of length L. For example, if the data rate to be transmitted for one data bit is 100 kHz, and the code length, L, is 100, then the code rate, R c , is equivalent to Lx(R d  /S d )=(100)×(100 kHz/1)=10 MHz. For two data bits per code, the data rate rises to 200 kHz, but the code rate, R c   =(100)×(200 kHz /2)=10 MHz. Thus, the data rate can increase without a like increase in the code rate. The number of data symbols produced per code segment of length L is 2 S  d where S d  =the number of data bits per code segment. 
     In the transmitter, the beginning of a code segment of length L is synchronously aligned with each data set, defined by the number of data bits per code segment, which may produce 2 S  d data symbols. For example, if two data bits per code segment are to be transmitted, then the 2 S  d=4 data symbols, which may be represented by 00, 01, 10, 11. If data symbol one is to be transmitted, then code one may be sent. If data symbol two is to be transmitted then the inverse of code one may be sent. The same process follows for data symbol three, which could use code two&#39;s inverse, and data symbol four, which could use the normal code two. In the receiver, reference code one and code two segments equivalent to those in the transmitter are loaded into the storage elements of the two correlators and held stationary. The received signal is then passed through the correlator, and when the correlator score from correlator one exceeds its threshold value T, a first data-symbol-correlation signal is produced. If the correlation score is less than its L-T, then a second data-symbol-correlation signal is produced. The same result follows for the third data symbol, when the second correlator score is less than its L-T, and the fourth data symbol when the second correlator score is greater than its T. 
     A second preferred embodiment of the present invention may use analog devices such as surface-acoustic-wave (SAW) devices or charge-coupled devices The surface-acoustic-wave devices, as an example of analog devices, include reference-sequence-storage devices and receive-sequence-storage devices. The surface-acoustic-wave devices additionally may include the adders 40 and summers 41, and function as a complete self-contained correlator unit. Additionally, a plurality of sets of reference-sequence-storage devices may be constructed on one particular surface-acoustic-wave device along with the receive-sequence-storage devices to form a very compact means for decoding a plurality of pseudo-noise signals. 
     A delay line matched filter or SAW correlator is a passive device designed to recognize a specific sequence of code chips, as does a digital correlator, but accomplishes this through a correlation of phase shifts in an RF signal, rather than voltage levels at baseband, and can therefore avoid many of the problems inherent in a digital correlator, such as a high noise or interference/jamming environment. 
     Each delay element within the correlator has a delay equal to the period of the transmitted code clock such that each element corresponds to only one chip at any one time. As the received signal propagates down the delay line, the phase structure of each element is added in or out of phase with the propagated PN encoded wave, and the outputs of all the elements are then summed to arrive at a total correlation value. When all the phase shift structures of the elements match the phase shifts of the propagated wave, then the maximum sum and correlation is achieved. 
     In order to achieve the desired correlation, the correct reference code must be &#34;loaded&#34; onto the SAW device. The present discussion is for a BPSK device, however, the invention extends and includes any PSK such as MSK, QPSK, etc. Assuming a bi-phase shift keyed signal, phase reversals would occur at each one/zero transition of the PN code. This is usually accomplished in one of two ways. The first is through a programmable correlator which can output all phases in each element. As illustratively shown in FIG. 6, for a bi-phase shift keyed device a count controller 101 controls a code clock generator 102 which sends L clock signals to a code generator 104 and reference registers 105. Code generator 104 then produces a unique code as determined by code selector 103 and loads it into reference registers 105. Once the code is stored in reference registers 105, the zero/one pattern is loaded into delay line correlator 106, with the contents of register A(2) connected to element T(2), and so on to element A(L). The correlator is then programmed so that all the outputs of the elements corresponding to a first data symbol are connected to summing devices 108, 110 and all outputs of the elements corresponding to a second data symbol are connected to summing devices 109, 111. In this example, the first data symbol is embodied as a first phase symbol, and the second data symbol is embodied as a second phase symbol. 
     In non-programmable devices, these phase shifts are programmed at the time of construction through transducers placed in each element to produce an elemental phase match and cannot be changed by the user, thus only one code sequence can be correlated. Inverted and non-inverted phase elements are then summed together just as in the programmable device. 
     When a signal with a PN code, PSK modulation, and RF frequency equivalent to that in the SAW correlator is received, then the received signal is amplified (and maybe down-converted, although down conversion to an IF frequency is not preferred unless necessary) and fed to delay line correlator 106. As the wave propagates across the surface of the correlator, the energy in each delay element increases by a factor determined by the phase of the reference elements versus the received signal phase. 
     The output of the delay elements which are in phase with the first phase are summed in summers 108, 110, while those elements which are 180° out of phase with the first phase are summed in summers 109, 111. When a non-inverted code segment, PSK modulated signal with the same PN code phase shifts as those referenced in the correlator propagates through the device and the first code chip reaches the end of the delay line, all the phase shifts of the received signal match those of the elements comprising the correlator, and a first phase maximum energy is obtained. The output of inverted first phase summer 109 is inverted by phase inverter 112 and summed in phase with the output of first phase summer 108 in summer 114. If the output of summer 114 exceeds the threshold set in threshold detector 116 by threshold setter 118, a first data symbol correlation signal is generated by threshold detector 116 and fed to data generator 119, which produces a first data symbol signal. 
     When an inverted code segment, PSK modulated signal with the same non-inverted PN code phase shifts as those referenced in the correlator propagates through the device and the first code chip reaches the end of the delay line, all the phase shifts of the received signal match those of the elements comprising the correlator, and an inverted first phase maximum energy is obtained. The output of the first phase summer 110 is inverted by phase inverter 113 and summed in phase with the output of inverted first phase summer 111 in summer 115. If the output of summer 115 exceeds the threshold set in threshold detector 117 by threshold setter 118, a second data symbol correlation signal is generated by threshold detector 117 and fed to data generator 119, which produces a second data symbol signal. 
     A difference between the method and apparatus of this invention and those used in the prior art is that the correlation pulse is used to directly derive the data symbols, while other systems may use the pulse for synchronizing a much longer reference code signal to the incoming received code signal. 
     A difference between SAW devices and digital correlators is in the frequency bands in which they are used. The SAW devices are usually employed at IF, but they can be used at RF. The digital correlators are usually used at baseband. Another difference is that SAW devices perform phase shift comparisons while the digital correlators perform voltage level comparisons. Further, the SAW devices sum the outputs differently from that of digital correlators. Also, when the present invention is realized with a SAW correlator, no receive code clock is required to correlate the PN code. The present invention, using a SAW correlator, may be realized using fewer components. 
     The present invention further includes methods using a correlator for decoding a received PSK spread spectrum signal, which includes a data signal modulated with a PN code, and modulated with an RF carrier to produce a spread spectrum RF signal. The first method comprises of steps, using the digital correlator, of setting upper- and lower-threshold levels using a threshold setting means, storing a pseudo-noise signal in a reference-sequence-storage means, storing the received spread spectrum signal in receive-sequence-storage means, correlating the received spread spectrum signal with the pseudo-noise signal to generate a correlation signal, comparing the correlation signal to an upper-threshold level and a lower-threshold level, and generating a first data symbol in response to the correlation signal being greater than the upper-threshold level, and generating a second data symbol in response to the correlation signal being less than the lower-threshold level. 
     The second method comprises, using an analog correlator as exemplified by a SAW correlator, of setting two threshold levels, which may be equivalent, using a threshold setting means, storing a pseudo-noise signal in a reference-sequence-storage means, storing the received spread spectrum signal in receive-sequence-storage means, correlating the received spread spectrum signal with the pseudo-noise signal to generate two correlation signals, comparing the first correlation signal to a first threshold level and comparing an inverse correlation signal to a second threshold level, and generating a first data symbol in response to the first correlation signal being greater than the first threshold level, and generating a second data symbol in response to the inverse correlation signal being greater than the second threshold level. 
     It will be apparent to those skilled in the art that various modifications can be made to the apparatus for decoding a received spread spectrum signal, which includes a data signal modulated with spread spectrum, of the instant invention without departing from the scope or spirit of the invention, and it is intended that the present invention cover modifications and variations of the apparatus provided they come within the scope of the appended claims and their equivalents.