Patent Publication Number: US-11663366-B2

Title: Side-channel attack mitigation for secure devices with embedded sensors

Description:
This application is a continuation of pending U.S. patent application Ser. No. 16/687,959, filed on Nov. 19, 2019 and entitled “Side-Channel Attack Mitigation For Secure Devices With Embedded Sensors”, which are expressly incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The technical field relates to integrated circuits with cryptographic circuits and embedded sensors including wireless internet-of-things (IoT) devices. 
     BACKGROUND 
     Integrated circuits (ICs) that operate as internet-of-things (IoT) devices can include cryptographic functions in addition to other functions. For example, an IoT device may have a radio to allow wireless communications. IoT devices may also include sensors, actuators, and/or other circuitry that allow the IoT device to perform one or more functions within the environment within which the IoT devices are deployed. For example, IoT devices can be used to provide a system of autonomous interconnected computing, sensing, and/or actuating devices within an environment such as a home or business. Further, the IoT devices can each have a unique identifier and have the ability to transmit and/or receive data over a network including the IoT devices. 
     IoT devices face significant privacy and security challenges. To deal with these privacy and security challenges, IoT devices often include cryptographic (crypto) circuits that are integrated on the same IC with other operational circuitry. For example, many IoT devices store one or more secret keys and perform cryptographic operations with these keys. Further, prior solutions have created trusted memory zones within an integrated circuit where secret keys are stored and crypto operations are performed, and these trusted zones are separate from non-trusted memory zones where application code is stored and other circuitry performs non-crypto operations. 
     If the secret keys are compromised, however, multiple attacks become possible. For example, an attacker can take over control of the device and direct it to act in a way that causes financial, physical, or other harm to people or infrastructures associated with the environment within which the devices are deployed. Further, an attacker with the keys can also impersonate the device within a network to gain access to private or confidential data on the network or stored within other connected devices. 
     A variety of indirect side-channel techniques have been used by attackers to determine secret keys being used within cryptographic circuits on IoT devices or other secure IC devices. For example, many IoT devices are implemented as system-on-a-chip (SoC) integrated circuits including cryptographic circuits integrated with embedded radios, microcontrollers, and other circuits. Such embedded IC devices are vulnerable to side-channel attacks. Side-channel attacks sidestep the mathematical properties of the cryptographic system by focusing on information gained from the physical operation of the embedded IC device. For example, attackers can extract secret keys from microcontrollers by measuring power consumption or electromagnetic radiation while the device is performing cryptographic operations. These side-channel attacks, however, require direct physical access to the device. As such, the scope of these traditional side-channel attacks is limited to small numbers of embedded devices where direct physical access is available to the attackers. 
     For IoT devices with embedded sensors, however, a new class of side-channel attack exists that does not require physical access to the device. The attack relies on the operation of integrated sensors and related ADC circuits on the device to collect side-channel information. In particular, this attack relies upon leakage of crypto information between the cryptographic circuits and the integrated sensors and/or ADCs such that operation of the cryptographic circuits including the secret keys can be determined from results generated by the sensor and/or ADC circuits. This side-channel attack does not require that the attacker have physical access and take over the device. Rather, this side-channel attack can be initiated remotely by the attacker by sending legitimate commands to the device. For example, the attacker can send a command to obtain a sensor reading and another command that triggers usage of a secret key within cryptographic circuits. The overlapping operation of the sensor and cryptographic operations can cause exploitable side-channel information about the secret key to leak into the sensor related data. Thus, with such IoT devices including embedded sensors, a side-channel attack can be made that exploits side-channel information without having physical access to the device. Further, this new class of attack can easily scale by orders of magnitude, potentially compromising a large number of devices. 
       FIG.  1 A  (Prior Art) is a block diagram of an example embodiment  100  for a prior integrated circuit  102  that can be compromised using a side-channel attack based upon overlapping operation of one or more sensors  112  and related ADC circuits  108  with cryptographic circuit  106 . The integrated circuit  102  also includes a controller  104 , memory  110 , a radio  116 , and power supply circuit  118 . The radio  116  includes transmit circuits and receive circuits, and the radio  116  is coupled to an antenna  115  and communicates wirelessly with a network  125 . The one or more embedded sensors  112  detect environmental inputs  114  such as temperature, pressure, ambient light, mechanical actuators, and/or other environmental inputs that are desired to be detected by the integrated circuit  102 . ADC circuits  108  convert analog inputs from the embedded sensors  112  into digital data that is provided to the controller  104 . The cryptographic circuit  106  performs one or more cryptographic operations using one or more secret keys  107 . For one embodiment, the secret keys  107  are stored within trusted memory associated with the cryptographic circuit  106 . The memory  110  is used to facilitate operations of the integrated circuit  102  and can store data and/or code for the controller  104 , the cryptographic circuit  106 , and/or other circuit blocks within the integrated circuit  102 . The power supply circuit  118  receives power from an external voltage supply and provides internal supply voltages to the circuit blocks within the integrated circuit  102 . It is also noted that the integrated circuit  102  could also have a network interface circuit instead of or in addition to the radio  116  that provides a network connection to the network  125 . 
     An attacker, as represented by the external device  120 , can compromise the security of the cryptographic circuit  106  by determining the secret keys  107  through side-channel attacks based upon overlapping operation with the sensors  112  and/or the ADC circuits  108 . The attacking device  120  communicates commands  122  through the network  125  to the integrated circuit  102 . These commands  122  include sensor-related commands to cause the controller  104  to activate one or more of the sensors  112  to collect sensor readings and to generate digital sensor data through ADC circuits  108 . The commands  122  also include crypto-related commands to cause the controller  104  to activate the cryptographic circuit  106  to perform cryptographic operations using one or more of the secret keys  107 . The overlapping operation of the sensors  112  and/or the ADC circuits  108  with the cryptographic circuit  106  causes crypto information  124  to leak into the supply voltages being generated and provided by the power supply circuit  118  to the sensors  112  and/or the ADC circuits  108 . This crypto information  124  can then be detected by the attacking device  120  through the sensor data reported by the controller  104  through the network  125  in response to the sensor-related commands within commands  122 . 
       FIG.  1 B  (Prior Art) is a flow diagram of an example embodiment  150  where an attacking device  120  compromises the security of cryptographic circuit  106  through a side-channel attack based upon the overlapping operation with the sensors  112  and/or the ADC circuits  108 . As indicated by arrow  122 A, the attacking device  120  sends commands for sensor operations and cryptographic operations to the integrated circuit  102  that are received by controller  104 . The controller  104  then activates a sensor operation with respect to one of a sensor  112  as represented by arrow  152 . The controller  104  also activates as crypto operation with respect to cryptographic circuit  106  as indicated by arrow  154 . The sensor  112  performs a detection cycle  156  and generates a sensor signal that is sent to ADC circuits  108  as indicated by arrow  158 . The ADC circuits  108  performs a conversion cycle  160  to convert the sensed signal to digital data that is communicated to the controller  104  as indicated by arrow  162 . This digital data is then returned as requested data to the attacking device  120  as indicated by arrow  122 B. The cryptographic circuit  106  performs a crypto cycle  164  using secret keys  107  that overlaps with the operation of the sensor  112  and/or the ADC circuits  108 , and the cryptographic circuit  106  communicates resulting cryptographic data to the controller  104  as indicated by arrow  166 . As described above, this overlapping operation causes crypto information  124  to leak into the operation of the sensor  112  and/or the ADC circuits  108  thereby affecting the sensed signal and/or the digital data generated by those circuits. This crypto information  124  can then be detected by the attacking device  120  from the digital data that is communicated back by the controller  104 . Over time and multiple such command cycles, the attacking device  120  can determine the secret keys  107  and thereby compromise the integrated circuit  102  and/or the network  125 . 
     SUMMARY OF THE INVENTION 
     Systems and methods are disclosed for side-channel attack mitigation for secure devices with embedded sensors. Embodiments include cryptographic circuits having isolated operation with respect to embedded sensor operations to mitigate side-channel attacks. A cryptographic circuit, one or more sensors, and analog-to-digital converter (ADC) circuits are integrated into an integrated circuit along with the cryptographic circuit. For one embodiment, a sensed signal is output with an embedded sensor, and the sensed signal is converted to digital data using an ADC circuit. Further, cryptographic data is generated using one or more secret keys and a cryptographic circuit. As described herein, the generation of the cryptographic data has isolated operation with respect to the operation of the sensor to output the sensed signal and the operation of the ADC circuit to convert the sensed signal to digital data. The isolated operation mitigates side-channel attacks. For one embodiment, this isolated operation is achieved using a power supply circuit, a clock circuit, and/or a reset circuit for the cryptographic circuit that are electrically isolated from similar circuits for the sensor and ADC circuit. For one embodiment, the isolated operation is achieved using time-division multiplex operations for the cryptographic circuit with respect to the sensor and ADC circuit. Other features and variations can also be implemented, and related systems and methods can be utilized as well. 
     For one embodiment, an integrated circuit having side-channel attack mitigation is disclosed including a sensor having a sensed signal as an output, an analog-to-digital converter (ADC) circuit coupled to receive the sensed signal and to output digital data representing the sensed signal, and a cryptographic circuit having cryptographic data as an output based upon one or more secret keys, where operation of the cryptographic circuit is isolated with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. 
     In additional embodiments, the integrated circuit also includes a radio configured to communicate with a network to transmit the digital data representing the sensed signal. In further additional embodiments, the integrated circuit also includes a network interface circuit configured to communicate with a network to transmit the digital data representing the sensed signal. 
     In additional embodiments, the operation of the cryptographic circuit is electrically isolated with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the integrated circuit also includes a first power supply circuit coupled to distribute a supply voltage to the cryptographic circuit and a second power supply circuit coupled to distribute supply voltages to the sensor and the ADC circuit, and the first power supply circuit is electrically isolated from the second power supply circuit. In further embodiments, the first power supply circuit includes a shunt regulator. In still further embodiments, the integrated circuit includes a first clock circuit and a first reset circuit coupled to the cryptographic circuit and includes a second clock circuit and a second reset circuit coupled to the sensor and the ADC circuit, where the first clock circuit and the first reset circuit are electrically isolated from the second clock circuit and the second reset circuit. 
     In additional embodiments, the operation of the cryptographic circuit is isolated in time with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the integrated circuit also includes a controller coupled to the sensor, the ADC circuit, and the cryptographic circuit; and the controller is configured to cause time-division multiplex operation for the cryptographic circuit with respect to the sensor and the ADC circuit based upon commands received from an external device for sensor operations and cryptographic operations. In still further embodiments, the controller is configured to activate the cryptographic operations only after the sensor operations have completed. 
     For one embodiment, an internet-of-things (IoT) device is disclosed including a radio coupled to an antenna to communicate with a network, a sensor having a sensed signal as an output, an analog-to-digital converter (ADC) circuit coupled to receive the sensed signal and to output digital data representing the sensed signal, a cryptographic circuit having cryptographic data as an output based upon one or more secret keys, and a controller. The controller is coupled to the sensor, the ADC circuit, and the cryptographic circuit; and the controller is configured to receive commands from an external device through the network for sensor operations and cryptographic operations. The radio, the sensor, the ADC circuit, the cryptographic circuit, and the controller are integrated within an integrated circuit; and operation of the cryptographic circuit is isolated with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. 
     In additional embodiments, the operation of the cryptographic circuit is electrically isolated with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the IoT device includes a first power supply circuit coupled to distribute a supply voltage to the cryptographic circuit and a second power supply circuit coupled to distribute supply voltages the sensor and the ADC circuit, and the first power supply circuit are electrically isolated from the second power supply circuit. In still further embodiments, the IoT device includes a first clock circuit and a first reset circuit coupled to the cryptographic circuit and includes a second clock circuit and a second reset circuit coupled to the sensor and the ADC circuit, where the first clock circuit and the first reset circuit are electrically isolated from the second clock circuit and the second reset circuit. 
     In additional embodiments, the operation of the cryptographic circuit is isolated in time with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the controller is configured to cause time-division multiplex operation for the cryptographic circuit with respect to the sensor and the ADC circuit based upon the commands for sensor operations and cryptographic operations. 
     For one embodiment, a method to mitigate side-channel attacks is disclosed including outputting a sensed signal with a sensor integrated within an integrated circuit, converting the sensed signal to digital data using an analog-to-digital converter (ADC) circuit integrated within the integrated circuit, generating cryptographic data using one or more secret keys and a cryptographic circuit integrated within the integrated circuit, and isolating the generating with respect to the outputting and the converting to mitigate side-channel attacks. 
     In additional embodiments, the method also includes communicating with a network using at least one of a radio integrated within the integrated circuit or a network interface circuit to transmit the digital data representing the sensed signal. 
     In additional embodiments, the isolating includes electrically isolating operation of the cryptographic circuit with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the electrically isolating includes distributing a supply voltage to the cryptographic circuit using a first power supply circuit and distributing supply voltages to the sensor and the ADC circuit using a second power supply circuit coupled, where the first power supply circuit is electrically isolated from the second power supply circuit. In still further embodiments, the electrically isolating also includes supplying a first clock signal to the cryptographic circuit using a first clock circuit, supplying a first reset signal to the cryptographic circuit using a first reset circuit, supplying a second clock signal to the sensor and the ADC circuit using a second clock circuit, and supplying a second reset signal to the sensor and the ADC circuit using a second reset circuit, where the first clock circuit and the first reset circuit are electrically isolated from the second clock circuit and the second reset circuit. 
     In additional embodiments, the isolating includes isolating in time operation of the cryptographic circuit with respect to operation of the sensor and operation of the ADC circuit to mitigate side-channel attacks. In further embodiments, the isolating in time includes receiving, with a controller integrated within the integrated circuit, commands from an external device for sensor operations and cryptographic operations and causing, with the controller, time-division multiplex operation for the cryptographic circuit with respect to the sensor and the ADC circuit based upon the commands. In further embodiments, the method includes activating the cryptographic operations only after the sensor operations have completed. 
     Other features and variations can also be implemented, and related systems and methods can be utilized, as well. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       It is noted that the appended drawings illustrate only example embodiments of the invention and are, therefore, not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments. 
         FIG.  1 A  (Prior Art) is a block diagram of an example embodiment for a prior integrated circuit that can be compromised using a side-channel attack based upon overlapping operation of one or more sensors and related ADC circuits with cryptographic circuits. 
         FIG.  1 B  (Prior Art) is a flow diagram of an example embodiment where an attacking device compromises the security of cryptographic circuits through a side-channel attack based upon overlapping operation with sensors and/or ADC circuits. 
         FIG.  2    is a process diagram of an example embodiment where cryptographic circuits have isolated operations with respect to sensor and ADC circuit operations to mitigate side-channel attacks. 
         FIG.  3    is a block diagram of an example embodiment for an integrated circuit that electrically isolates the operation of cryptographic circuits from the operation of one or more integrated sensors and related ADC circuits thereby preventing or helping to eliminate side-channel attacks. 
         FIG.  4    is a block diagram of example embodiments for separate and electrically isolated power supply circuits as shown in the embodiment of  FIG.  3   . 
         FIG.  5    is a block diagram of an example embodiment where additional circuits, such as clock and reset circuits, for the cryptographic circuits are electrically isolated within the integrated circuit. 
         FIG.  6    is a flow diagram of an example embodiment where operation of the cryptographic circuits is isolated in time with respect to the operation of the sensors and the ADC circuits through time-division multiplex operation. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     Systems and methods are disclosed for side-channel attack mitigation for secure devices with embedded sensors. Disclosed embodiments include cryptographic circuits integrated with one or more sensors and related analog-to-digital converter (ADC) circuits. As described herein, the cryptographic circuits have isolated operation with respect to the sensors and ADC circuits so that attackers cannot obtain side-channel information due to leakage of crypto information during operation of the cryptographic circuits. Various features can be implemented for the embodiments described herein, and related systems and methods can be utilized as well. 
     As described herein, disclosed embodiments prevent an attacker from leveraging integrated on-chip sensors and related ADC circuits to measure side-channel information that can potentially reveal secret keys used in cryptographic operations. As such, the disclosed embodiments prevent side-channel attacks from being launched remotely through commands directed to network-connected devices having embedded sensors. As described herein, the disclosed embodiments isolate operation of the cryptographic circuits from operation of the integrated sensors and ADC circuits. This isolated operation can be implemented as electrical isolation, logical isolation, or other isolation and/or combinations of these isolation techniques. For example, electrical isolation can be achieved by using a power supply circuit for the cryptographic circuits that is dedicated, unequal, and separate from a power supply circuit used for the sensors converters and ADCs. Clock and/or reset circuits can similarly be electrically isolated. For one embodiment, a decoupled voltage regulator is used to power sensors and related ADCs and a separate, dedicated shunt regulator is used to power the cryptographic circuits. Logical isolation can be achieved, for example, by time-division multiplexing the operations of the cryptographic circuit with respect to the operation of the sensors and ADC circuits. Other variations can also be implemented while still taking advantage of the isolation techniques described herein. 
       FIG.  2    is a process diagram of an example embodiment  200  where cryptographic circuits have isolated operations with respect to sensor and ADC circuit operations to mitigate side-channel attacks. In block  201 , a sensed signal is output with a sensor integrated within an integrated circuit. In block  203 , the sensed signal is converted to digital data using an analog-to-digital converter (ADC) circuit integrated within the integrated circuit. In block  205 , cryptographic data is generated using one or more secret keys and a cryptographic circuit integrated within the integrated circuit. As represented by block  207 , the generation of the cryptographic data has isolated operation with respect to the operation of the sensor to output the sensed signal and operation of the ADC circuit to convert the sensed signal to digital data. This isolated operation mitigates side-channel attacks. It is noted that different and/or additional functions can also be implemented while still taking advantage of the isolation techniques described herein. 
       FIG.  3    is a block diagram of an example embodiment  300  for an integrated circuit  210  that electrically isolates the operation of cryptographic circuit  106  from the operation of one or more integrated sensors  112  and related ADC circuits  108  thereby preventing or helping to eliminate side-channel attacks. As with integrated circuit  102  of  FIG.  1 A  (Prior Art), the integrated circuit  210  also includes a controller  104 , memory  110 , and a radio  116 . The radio  116  includes transmit circuits and receive circuits, and the radio  116  is coupled to an antenna  115  and communicates wirelessly with a network  125 . The one or more embedded sensors  112  detect environmental inputs  114  such as temperature, pressure, ambient light, mechanical actuators, and/or other environmental inputs that are desired to be detected by the integrated circuit  210 . ADC circuits  108  convert analog inputs from the embedded sensors  112  into digital data that is provided to the controller  104 . The cryptographic circuit  106  performs one or more cryptographic operations using one or more secret keys  107 . For one embodiment, the secret keys  107  are stored within trusted memory associated with the cryptographic circuit  106 . The memory  110  is used to facilitate operations of the integrated circuit  210  and can store data and/or code for the controller  104 , the cryptographic circuit  106 , and/or other circuit blocks within the integrated circuit  210 . It is also noted that the integrated circuit  210  could also have a network interface circuit instead of or in addition to the radio  116  that provides a network connection to the network  125 . 
     In contrast with integrated circuit  102  of  FIG.  1 A  (Prior Art), integrated circuit  210  includes a power supply circuit  202  that is dedicated to the cryptographic circuit  106  and separate from the power supply circuit  204  for the sensors  112  and the related ADC circuits  108 . The power supply circuit  202  receives power from an external voltage supply and provides a supply voltage to the cryptographic circuit  106 . The power supply circuit  204  receives power from an external voltage supply and provides supply voltages to the sensors  112  and the ADC circuits  108 . The power supply circuit  204  can also provide supply voltages to other circuit blocks such as the radio  116 , the controller  104 , and the memory  110 . 
     Because the power supply circuit  202  is electrically isolated from power supply circuit  204 , an attacker, as represented by device  120 , is not able to compromise the security of the cryptographic circuit  106  through side-channel attacks based upon power supply leakage from overlapping operation of the sensors  112  and/or the ADC circuits  108 . As described above with respect to  FIG.  1 A  (Prior art), the attacking device  120  attempts such an attack by communicating commands  122  through the network  125  to the integrated circuit  102 . These commands  122  include sensor-related commands attempting to cause the controller  104  to activate one or more of the sensors  112  to collect sensor readings and to generate digital sensor data through ADC circuits  108 . The commands  122  also include crypto-related commands attempting to cause the controller  104  to activate the cryptographic circuit  106  to perform cryptographic operations using one or more of the secret keys  107 . For the embodiment of  FIG.  3   , however, the overlapping operation of the sensors  112  and/or the ADC circuits  108  with the cryptographic circuit  106  does not cause crypto information to leak into the supply voltages being generated and provided by the power supply circuits  202 / 204  because power supply circuit  202  is electrically isolated from the power supply circuit  204 . Thus, as indicated by arrow  206 , no crypto information can be detected by the attacking device  120  through the sensor data reported by the controller  104  through the network  125  in response to the sensor-related commands within commands  122 . 
       FIG.  4    is a block diagram of an example embodiment  400  for the separate and electrically isolated power supply circuits  202  and  204  of  FIG.  3   . The power supply circuit  202  receives an external supply voltage  402 . A voltage regulator  404  for the power supply circuit  202  receives this external supply voltage  402  and generates a regulated voltage  405 . This regulated voltage  405  is then received by supply distribution circuits  406 , and the supply distribution circuits  406  distribute supply voltage  407  to the cryptographic circuit  106 . Similarly, a voltage regulator  408  for the power supply circuit  204  receives the external supply voltage  402  and generates a regulated voltage  409 . This regulated voltage  409  is then received by supply distribution circuits  410 , and the supply distribution circuits  410  distribute supply voltages  411  to the sensors  112 , the ADC circuits  108 , and/or other circuit blocks within the integrated circuit  210 . Because the power supply circuit  202  is electrically isolated from the power supply circuit  204 , leakage of crypto information does not occur due to overlapping operation of the cryptographic circuit  106  with the sensors  112  and the ADC circuit  108 . 
     For one embodiment, the voltage regulator  404  for the power supply circuit  202  that distributes a supply voltage  407  to the cryptographic circuit  106  can be implemented as a shunt regulator. Although shunt regulators are often undesirable in IoT devices due to higher (but constant) current consumption, their limited use as the voltage regulators for the crypto power supply circuit  202  makes them a viable option for the embodiments described herein. Other regulator circuits could also be used while still taking advantage of the isolation techniques described herein. 
       FIG.  5    is a block diagram of an example embodiment  500  where additional circuits for the cryptographic circuit  106  are electrically isolated within the integrated circuit  210 . For the example embodiment  500 , a clock circuit  502  and a reset circuit  504  are also electrically isolated within a first circuit region  510 . The clock circuit  502  generates one or more clock signals  503 , and the reset circuit  504  generates one or more reset signals  505 . The clock and reset signals  503 / 505  are output to the cryptographic circuit  106  along with the power supply voltage  407  from the power supply circuit  202 . This first circuit region  510  is electrically isolated from the second circuit region  520 . A clock circuit  506  and a reset circuit  508  are included within the second circuit region  520  along with the powers supply circuit  204 . The clock circuit  506  generates one or more clock signals  507 , and the reset circuit  508  generates one or more reset signals  509 . The clock and reset signals  507 / 509  are output along with the power supply voltages  411  to the sensors  112 , the ADC circuits  108 , and/or other circuit blocks within the integrated circuit  210 . In addition to or separate from the circuits shown in embodiment  500 , other digital or analog circuits that provide signals to the cryptographic circuit  106  can also be electrically isolated to help eliminate side-channel attacks based upon the leakage of crypto information into the operation of the sensors  112  and/or ADC circuits  108 . Other variations can also be implemented. 
     As described above, in addition or instead of the electrical isolation of circuits provided by the embodiments of  FIGS.  3 - 5   , logical isolation can also be used to prevent leakage of crypto information into the operation of the sensors  112  and/or ADC circuits  108 . This logical isolation can be implemented, for example, by time-division multiplexing the operation of the cryptographic circuit  106  with respect to the operation of the sensors  112  and the ADC circuits  108 . 
       FIG.  6    is a flow diagram of an example embodiment  600  where operation of the cryptographic circuit  106  is isolated in time with respect to the operation of the sensors  112  and the ADC circuits  108  through time-division multiplex operation. Due to this time-division multiplex operation, an attacking device  120  is not able to compromise the security of cryptographic circuit  106  through a side-channel attack based upon the overlapping operation with the sensors  112  and/or the ADC circuits  108 . As indicated by arrow  122 A, the attacking device  120  sends commands for sensor operations and crypto operations to the integrated circuit  102  that are received by controller  104 . In contrast to the embodiment of  FIG.  1 B  (Prior Art), however, the controller  104  does not activate overlapping operation of the cryptographic circuit  106  with the sensors  112  and the ADC circuits  108 . Rather, time-division multiplex operations are used. For the example embodiment  600 , the controller  104  first activates a sensor operation with respect to one of a sensor  112  as represented by arrow  152 . The sensor  112  performs a detection cycle  156  and generates a sensor signal that is sent to ADC circuits  108  as indicated by arrow  158 . The ADC circuits  108  perform a conversion cycle  160  to generate digital data that is communicated to the controller  104  as indicated by arrow  162 . This digital data is then returned as requested data to the attacking device  120  as indicated by arrow  122 B. After completion of the sensor operation, the controller activates a crypto operation with respect to cryptographic circuit  106  as indicated by arrow  154 . The cryptographic circuit  106  performs a crypto cycle  164  using secret keys  107 , and this crypto cycle does not overlap with the operation of the sensor  112  and/or the ADC circuits  108 . The cryptographic circuit  106  communicates resulting crypto data to the controller  104  as indicated by arrow  166 . It is also noted that the crypto operation can also be activated first followed by the sensor operation. As such, the crypto operation is only activated after the sensor operation has completed, or the sensor operation is only activated after the crypto operation has completed. 
     Because there is no overlapping operation between the cryptographic circuit  106  with respect to the sensors  112  and the ADC circuits  108 , crypto information does not leak into the operation of the sensor  112  and/or the ADC circuits  108 . As indicated by arrow  206 , therefore, no crypto information can then be detected by the attacking device  120  from the digital data that is communicated back by the controller  104 . It is further noted that circuits related to the operation of the cryptographic circuit  106 , such as clock circuit  502  and reset circuit  504  in  FIG.  5   , can also be controlled and activated using time-division multiplex operations so that their operations do not overlap with operations of the sensors  112  and ADC circuits  108 . Other variations could also be implemented while still taking advantage of time-division multiplex operation described herein. 
     It is noted that the functional blocks, devices, and/or circuitry described herein can be implemented using hardware, software, or a combination of hardware and software. For one embodiment, one or more programmable integrated circuits are programmed to provide the functionality described herein. For example, one or more processors (e.g., microprocessor, microcontroller, central processing unit, etc.), programmable logic devices (e.g., complex programmable logic device (CPLD)), field programmable gate array (FPGA), etc.), and/or other programmable integrated circuits can be programmed with software or other programming instructions to implement the functionality of a proscribed plasma process recipe. It is further noted that the software or other programming instructions can be stored in one or more non-transitory computer-readable mediums (e.g., memory storage devices, FLASH memory, DRAM memory, reprogrammable storage devices, hard drives, floppy disks, DVDs, CD-ROMs, etc.), and the software or other programming instructions when executed by the programmable integrated circuits cause the programmable integrated circuits to perform the processes, functions, and/or capabilities described herein. Other variations could also be implemented. 
     Further modifications and alternative embodiments of this invention will be apparent to those skilled in the art in view of this description. It will be recognized, therefore, that the present invention is not limited by these example arrangements. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the manner of carrying out the invention. It is to be understood that the forms of the invention herein shown and described are to be taken as the presently preferred embodiments. Various changes may be made in the implementations and architectures. For example, equivalent elements may be substituted for those illustrated and described herein, and certain features of the invention may be utilized independently of the use of other features, all as would be apparent to one skilled in the art after having the benefit of this description of the invention.