Patent Publication Number: US-8115701-B2

Title: Sustain device for plasma panel

Description:
This application claims the benefit, under 35 U.S.C §365 of International Application PCT/EP2006/060953, filed Mar. 22, 2006, which was published in accordance with PCT Article 21 (2) on Oct. 12, 2006 in English and which claims the benefit of French patent application No. 0550882, filed Apr. 4, 2005 and French patent application No. 0551210, filed May 10, 2005. 
     The present invention concerns a device for generating a rectangular sustain voltage between the line scanning electrodes and the line common electrodes of luminous cells in a plasma panel. 
     Conventionally, a plasma display panel has a plurality of cells arranged in rows and columns. In the coplanar technology currently employed, each cell has three electrodes:
         one electrode called the “column electrode” used mainly for addressing the cells; the column electrodes of all the cells in the panel are connected to a column driver circuit; and   two row electrodes, one of which is called a “line scanning electrode” and used to individually address each row of cells, while the other one is called a “line common electrode”; all the line scanning electrodes are connected, on one side of the panel, to a row driver circuit and the line common electrodes are interconnected on the other side of the panel.       

     In this type of panel, the addressing of a cell involves applying a specific high-voltage signal between its line scanning electrode and its column electrode to modify its charge state. At the end of the addressing operation, the cell can have two charge states: a first state called “excited” which will enable it to be lit during the cell sustain phase to follow and a second state in which it will remain off. The sustain phase of the cells that follows the addressing phase is a period during which high-voltage rectangular signals are applied to the line scanning electrodes and the line common electrodes. During this phase, the cells excited beforehand light up. 
     To generate such voltage signals, the display panel has power amplifiers. The panel includes in particular a column amplifier to generate the addressing signal to apply to the column electrode of the cells and a sustain amplifier to generate the sustain signal applied to the line scanning electrode and the line common electrode of the cells. 
     These amplifiers have in common the need to generate signals having high-voltage transitions at high frequency on a very high capacitive load equal to the equivalent capacitance of all the cells in the panel or to the capacitance of a large number of them. 
     The sustain operation of the cells therefore involves an enormous transfer of energy between the amplifier and the panel cells, and this must be recovered. The same applies to the operation for addressing columns of cells. 
     To this end, a sustain amplifier with energy recovery, called a “Weber” amplifier, named after its inventor, was developed.  FIG. 1  represents the architecture of the power electronics of a plasma panel from its mains power supply to the plasma panel. The first power stage  1  is an AC/DC converter with power factor correction. This stage is connected to the mains supply. Its role is to adapt the current from the mains so that it has a sinusoidal waveform that is synchronous with the voltage waveform. This stage is well known to the person skilled in the art. It includes a diode bridge D 1  to D 4  to convert sinusoidal voltage to a DC voltage, an inductor L 1  with a switch T 1  in series with it connected to the terminals of the diode bridge to drive the current as described while adjusting the value of the DC voltage at the output, a rectifier diode D 5  and a high-value electrolytic capacitor Cc at its output terminals. The next stage is a DC/DC converter  2  responsible for delivering a high-value regulated voltage for the sustain operation of the plasma panel cells. The regulated voltage is delivered to the row sustain amplifier of the plasma panel. As represented in  FIG. 1 , this row sustain amplifier actually includes two identical amplifiers, one of them 11 intended to supply the line scanning electrode Y of the cells via a row driver circuit  12  and the other 13 intended to supply their line common electrodes Z. The plasma panel cells are represented in the figure by their equivalent capacitance Cp. This equivalent capacitance is in practice made up of the capacitance Cp 1  present between the line scanning electrodes Y and the line common electrodes Z of the panel, the capacitance Cp 2  present between the line scanning electrodes Y and the column electrodes of the panel and lastly the capacitance Cp 3  present between the line common electrodes Z and the column electrodes of the panel. An addressing voltage generator  15  is also provided to produce the appropriate voltages to apply to the electrodes of the cells in order to address them. The row driver circuit  12  is for selecting the voltage to apply to the Y electrode of the cells. Likewise, a column driver circuit  14  selects the voltage to apply to the column electrode of the cells. 
     The amplifier  11  intended to supply the Y electrodes conventionally includes switches M 1  and M 2 , connected in a half-bridge structure, placed in series between a supply terminal receiving the very high sustain voltage VS delivered by the DC/DC converter  2  and a reference terminal (connected here to ground GND). These switches are controlled so as to generate on the Y electrode of the panel cells a rectangular signal alternating between the voltage VS and the potential present on the reference terminal. As represented in the figure, these switches are generally MOS transistors with their diodes in anti-parallel. To recover and re-inject the capacitive energy and produce soft switching between the voltage VS and ground, the amplifier  11  includes a resonant inductor L placed in series with a switching module MC and a storage capacitor C 1 . These three components are connected between the Y electrode and the reference potential. The switching module includes two current conduction paths arranged in parallel, each allowing current to flow in one direction. The first current path includes a switch M 3  placed in series with a diode D 3  to allow the current to flow towards the storage capacitor C 1  when the switch M 3  is closed and thus to produce the falling edge of the output signal of the amplifier. The second current path includes a switch M 4  placed in series with a diode D 4  to allow the current to flow towards the resonant inductor L when the switch M 4  is closed and thus to produce the rising edge of the output signal. 
     As regards the amplifier  13 , it includes the same components as the amplifier  11  which are connected in the same way between the line common electrode Z and the reference terminal. To differentiate hereafter in the present description between the components of the amplifier  11  and those of the amplifier  13 , the components M 1 , M 2 , L, MC, M 3 , M 4 , D 3 , D 4  and C 1  of the amplifier  11  are labelled M 1 ′, M 2 ′, L′, MC′, M 3 ′, M 4 ′, D 3 ′, D 4 ′ and C 1 ′ in the amplifier  13 . 
       FIG. 2  represents the sustain voltage signals to be generated on the Y and Z electrodes and the resulting voltage across the terminals of the panel cells according to a well-known operating mode to achieve good sustaining of electrical discharges in the cells. According to this operating mode, the transitions of the voltage generated on the Y electrode are synchronized with those of the voltage generated on the Z electrode in order that the voltage across the terminals of the panel cells alternates continuously between +VS and −VS. This operating mode is given only by way of example to understand how the Weber circuit operates. Of course, there are other operating modes, in particular a mode in which the voltage transitions on the Y electrode of the cells are offset with respect to those on the Z electrode. 
     To obtain one or other of the voltage signals shown in  FIG. 2 , the amplifiers  11  and  13  are controlled as illustrated in  FIG. 3 . This figure represents more specifically the voltages for controlling switches M 1  to M 4 , the resulting output voltage of the amplifier and the current iL flowing through the resonant inductor L. In this figure, it is considered that, in the initial state, the switches M 2 , M 3  and M 4  are open and the switch M 1  is closed. The voltage on the Y electrode is therefore equal to VS. After opening of the switch M 1  then closure of the switch M 3 , the voltage on the Y electrode starts to fall. During this phase, the resonant circuit formed by the inductor L and the equivalent capacitance Cp is closed by the diode D 3 , the switch M 3  and the storage capacitor C 1  with the following initial conditions:
         the current iL through the inductor L is 0,   the voltage on the Y electrode is equal to VS, and   the voltage across the storage capacitor terminals is equal to VS/2.       

     Since the value of the storage capacitor C 1  is much greater than that of the capacitance Cp, the voltage across its terminals can be considered to be constant and equal to VS/2. As the current through the inductor L increases, the output of the amplifier and the voltage across the terminals of the capacitance Cp decreases according to a sinusoidal segment until the voltage on the Y electrode reaches VS/2 (point where the current iL stops increasing). This first phase corresponds to a transfer of energy from the capacitance Cp to the inductor L. A transfer in the opposite direction occurs during the next phase: during that phase, the current iL decreases and the voltage on the Y electrode continues to decrease according to another sinusoidal segment until it reaches 0 volts (the reference potential). The diode D 3  prevents the current from flowing in the other direction. Closure of the switch M 2  then enables the voltage on the Y electrode to be held at 0 volts. The transition from 0 volts to VS of the voltage on the Y electrode is achieved in the same way by the closure of the switch M 4 . 
     During the transition phases of the voltage across the terminals of the cells, significant energy transfers take place between the inductor L and the capacitance Cp. High charge currents and currents related to the electrical discharges in the plasma gas of the cells at the ends of transitions flow through the amplifier. These currents have very high values, in the order of several tens of amperes, over very short time intervals of about 1 microsecond. To this end, the storage capacitors C 1 , C 1 ′ and Cc must be connected perfectly to the other components of the amplifiers and to the panel in order to reduce the parasitic inductances and to not modify the waveforms of the voltages applied to the electrodes of the cells and the overall behaviour of the panel in terms light emission. 
     The invention proposes a novel plasma panel sustain circuit architecture without a DC/DC converter at the output of the AC/DC converter with power factor correction, the aim being to supply the power as close as possible to the panel cells. 
     The invention concerns a device for generating a rectangular sustain voltage between the line scanning electrodes and the line common electrodes of luminous cells in a plasma panel, said voltage being produced by applying a first rectangular sustain voltage signal to the line scanning electrode of the cells and a second rectangular sustain voltage signal to the line common electrode of the cells, 
     characterized in that it includes a first sustain amplifier connected to the line scanning electrode of the cells to produce the transitions of the first sustain voltage signal, a second sustain amplifier connected to the line common electrode of the cells to produce the transitions of the second sustain voltage signal and an insulated voltage supply circuit connected to the line scanning electrodes and to the line common electrodes of the cells in order to hold the end-of-transition voltage on said line scanning electrodes and said line common electrodes. 
     The insulated voltage supply circuit includes a transformer, the secondary of which is connected via a first end to the line scanning electrode of the cells and via a second end to the line common electrode of the cells, and a device capable of delivering to the primary of said transformer, in addition to the signal transitions, voltages corresponding to the end-of-transition voltages divided by the transformation ratio of the transformer. 
    
    
     
       The invention will be better understood on reading the following description, given by way of non-limiting example and with reference to the accompanying drawings in which: 
         FIG. 1 , already described, is a circuit diagram of the power electronics of a plasma panel of the prior art, 
         FIG. 2 , already described, shows timing diagrams illustrating the voltage signals generated by sustain amplifiers in the circuit of  FIG. 1  according to a known operating mode of the amplifier, 
         FIG. 3 , already described, shows control signals illustrating the operating mode of each of the sustain amplifiers in the circuit of  FIG. 1 ; 
         FIG. 4  shows a circuit diagram of the power electronics of a plasma panel according to a first embodiment of the invention; 
         FIG. 5  shows a circuit diagram of the power electronics of a plasma panel according to a second embodiment of the invention; and 
         FIG. 6  shows timing diagrams illustrating the operation of the circuit of  FIG. 5 . 
     
    
    
     According to the invention, the DC/DC converter  2  is replaced by an insulation transformer Trf with a full-bridge structure connected to the transformer primary. The full bridge is fed by the output of the AC/DC converter with power factor correction  1  and the transformer secondary is connected directly to the outputs of the sustain amplifiers  11  and  13 . 
     The full-bridge structure is made up of four switches M 5  to M 8 , the switches M 5  and M 8  being placed in series between the two output terminals of the AC/DC converter  1  as are the switches M 6  and M 7 . The primary winding of the transformer Trf is connected between the middle points of the bridge and, as indicated above, the secondary winding of the transformer Trf is connected directly to the outputs of the sustain amplifiers  11  and  13 . 
     Advantageously, diodes D 5  to D 8  and D 5 ′ to D 8 ′ are added to the full bridge structure to manage the reverse recovery effects of the MOSFET intrinsic diodes of the switches M 5  to M 8  as it will be described further. 
     Insulation transistors M 10  and M 11  are connected between the output of the amplifier  11  and the row circuit driver  12 . A storage capacitor Cs having a capacitance much greater than Cp is placed in parallel with the half-bridge circuits M 1 , M 2  and M 1 ′, M 2 ′. 
     During the sustain operations, the Y electrode of the cells is connected to the output of the amplifier  11  and their column electrodes are connected to ground. The insulation transistors M 10  and M 11  are conducting. During these operations, the voltage VS is the sustain voltage of the cells, in the order of 200 volts. 
     During the transitions of the sustain signal applied to the cells, the switches M 5  to M 8  are in a high-impedance state. Except for parasitic capacitances and inductances, the connection of the secondary of the transformer Trf to the amplifiers  11  and  13  has no effect on the operation of the amplifiers and may be considered as open. Generation of signals VY and VZ applied to the electrodes Y and Z respectively of the cells is managed by the switches M 1  to M 4  and M 1 ′ to M 4 ′. The capacitance Cp seen from the Y electrode is actually different to that seen from the Z electrode. For example, in the case of a synchronized transition mode as that illustrated in  FIG. 2 , the capacitance Cp is equal to:
         for the Y electrode, the equivalent capacitance of capacitances Cp 2  and       

                 Cp   ⁢           ⁢   1     2     ,         
and
         for the Z electrode, the equivalent capacitance of capacitances Cp 3  and       

     
       
         
           
             
               
                 Cp 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 1 
               
               2 
             
             . 
           
         
       
     
     On the line scanning electrode Y side, the switches M 1  to M 4  manage the resonance of the inductor L with the panel capacitance Cp seen from the Y electrode as illustrated in  FIG. 3 . Likewise, on the line common electrode Z side, the switches M 1 ′ to M 4 ′ manage the resonance of the inductor L′ with the panel capacitance Cp seen from the Z electrode. The energy required to compensate for the losses in the energy recovery circuits and the losses brought about by the electrical discharges is supplied by the storage capacitor Cs. 
     As soon as the transitions have terminated and during the voltage plateaus, the switches M 5  and M 7 , or M 6  and M 8 , are made conducting depending on whether the voltage to be delivered at the output of the sustain amplifiers  11  and  13  is negative or positive. The AC/DC converter  1  delivers the voltage V PFC . It is to be noted that the switching of the MOSFET transistors M 5  to M 8  is performed at zero voltage and therefore without switching losses since the voltage +VS or −VS at the transformer secondary has been reached beforehand by the output of the amplifiers  11  and  13  and brought back at the primary to +V PFC  or −V PFC  by the transformer Trf. The switches M 1  and M 2 ′ are also made conducting during this phase such that the capacitor Cs is recharged to the voltage VS. In the present case, the leakage inductance of the transformer Trf contributes to limiting the current between the AC/DC converter and the capacitor Cs when it is recharging. This effect of current limitation is compensated by using a transformation ratio n of the transformer Trf greater than VS/V PFC . This leakage current grows during the plateaus of the voltage applied to cells during the sustain phase. At the opening of the switches M 5  and M 7  (respectively M 6  and M 8 ) which correspond to the beginning of a transition, this current will flow through the intrinsic diodes of the switches M 6  and M 8  (respectively M 5  and M 7 ). The reverse recovery effects of the MOSFET intrinsic diodes of the switches requires to shunt the current by diodes D 5  to D 8  and to stop the current flowing in the Switches by the diodes D 5 ′ to D 8 ′. 
     The voltage VS is advantageously regulated for compensating the power variations due the variations of the picture load in the panel by modulating the power amounts transferred from the voltage V PFC  to the voltage VS as described before. A classical Pulse Width Modulation (PWM) method applied to the conduction time of the switches M 5  and M 7  (or M 6  and M 8 ) can be used within the plateau phases. However, as these conduction times are very short and consequently uneasy to control, a regulation mode using constant conduction times is preferably used. In this mode called burst mode, the power transferred during the plateau phases is always maximum but the presence or deletion of these conduction events is controlled as a function of the voltage Vs. 
     This structure also provides for simplifying the generation of other voltages, for example for the addressing voltage generator, by multiplying the number of windings on the secondary of the transformer Trf and by providing means of rectification, filtering and regulation to adjust the voltage to the desired value. 
     During the addressing phases, the insulation transistors M 10  and M 11  are in a high-impedance state, thus insulating the addressing voltage generator  15  from the sustain amplifiers  11  and  13 . The output of the transformer is held at zero by closing the transistors M 7  and M 8  or M 5  and M 6 . 
     A second embodiment of the device of the invention is proposed with reference to  FIG. 5 . The energy recovery circuit, i.e. the switching module MC or MC′ and the inductor L or L′, is removed in the each of the sustain amplifiers  11  and  13  and a high-value inductor L 2   2  operating in saturated mode possibly with a conventional low-value inductor L 2   1  in series is connected between the outputs of the two amplifiers  11  and  13 . L 2  denotes the series inductance. Its value is much higher than that of the inductor L or L′ in the Weber circuit: 100 to 1000 times higher. 
     In saturated mode, an inductor behaves like an inductor in air (without magnetic material). The inductor L 2   2  acts in the present case like an automatic switch. Before saturation, very little current flows through it and, after saturation, a high current flows through it. From now on in the description, L 2  denotes both the inductive element L 2  and the value of this inductance. 
     In non-saturated mode, the inductor L 2  acts like an inductance of value L 2   2  (L 2   1  being very low compared with L 2   2 ) and in saturated mode like an inductance of value L 2   1  (L 2   2  is close to 0). Operation in non-saturated or saturated mode depends on the current iL 2  through L 2 . 
     Operation of the amplifier in  FIG. 5  is illustrated with reference to  FIG. 6 .  FIG. 6  shows the control signals for the transistors M 1 , M 2 , M 1 ′ and M 2 ′, the voltage signal generated by the amplifiers  11  and  13  and the current iL 2  through the inductors L 2   1  and L 2   2 . 
     The operating half-period of the current iL 2  is divided into four consecutive operating phases numbered  1  to  4 . 
     During phase  1 , the switches M 1  and M 2 ′ are closed and the switches M 2  and M 1 ′ are open. The output voltage of the amplifier  11  is equal to VS. Furthermore, being in a plateau phase of the electrode voltages, the transistors M 6  and M 8  are closed as in the previous embodiment. They ensure that the capacitor Cs is adequately charged from the source of power supplied by the AC/DC converter  1  and its output V PFC . The output voltage of the amplifier  13  is equal to 0. The current flowing through the non-saturated inductor L 2  is controlled by the higher-value inductor L 2   2 . Thus, the current flowing through the amplifiers  11  and  13  is much lower, which will result in reducing the conduction losses. The voltage across the terminals of the inductor L 2  is substantially found across the terminals of the inductor L 2   2 . 
     At the start of phase  2 , the inductor L 2   2  saturates. The circuit is then controlled by the inductor L 2   1 . The current iL 2  increases linearly as long as the switches M 1  and M 2 ′ remain closed. 
     Phase  3  then starts when all the switches M 1 , M 2 , M 1 ′ and M 2 ′ are open. Moreover, being in a transition phase of the electrode voltages, the transistors M 5  to M 8  are open as in the previous embodiment. The inductor L 2   1  then resonates with the capacitance Cp. The output voltage of the amplifier  11  starts to fall and that of the amplifier  13  starts to rise, both according to a sinusoidal segment. In the middle of phase  3 , the voltage across the terminals of the inductor L 2  is cancelled out before being reversed and the current flowing through it has its maximum amplitude before decreasing. At the end of this phase, the output voltage of the amplifier  11  reaches 0 volts (reference potential) and that of the amplifier  13  reaches VS. 
     At the start of phase  4 , the current through the inductor L 2  continues to fall linearly regardless of whether the switches M 2  and M 1 ′ are in the open or closed state, because of their intrinsic diode (start of the greyed area). M 2  and M 1 ′ must be closed before current becomes zero (end of the greyed area). At the end of this phase  4 , the inductor L 2   2  is no longer saturated. A phase that is symmetric to phase  1  then begins. 
     The choice of the inductor L 2   2  is essential. Suitable magnetic material must be chosen and the number of turns required must be calculated. The number of turns of L 2   2  can be defined as follows: 
     During each operating phase, for example during phase  1  in  FIG. 6 , 
     
       
         
           
             
               V 
               
                 L 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   2 
                   2 
                 
               
             
             = 
             
               n 
               · 
               
                 A 
                 e 
               
               · 
               
                 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   B 
                 
                 
                   Δ 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     t 
                     
                       ph 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                 
               
             
           
         
       
     
     where:
         A e  is the effective cross-sectional area of the magnetic material;   ΔB is the variation in magnetic induction during this phase;   Δt ph1  is the duration of phase  1 .       

     During this phase, the voltage across the terminals of L 2   2  is equal to VS and the magnetic induction varies between +B sat  and −B sat  (or vice versa), giving: 
     
       
         
           
             
               
                 
                   
                     
                       
                         VS 
                         = 
                           
                         ⁢ 
                         
                           
                             n 
                             · 
                             
                               A 
                               e 
                             
                             · 
                             
                               
                                 2 
                                 · 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   B 
                                   sat 
                                 
                               
                               
                                 Δ 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 
                                   t 
                                   
                                     ph 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                   
                                 
                               
                             
                           
                           ⁢ 
                           
                               
                           
                           → 
                         
                       
                     
                   
                   
                     
                       
                         n 
                         = 
                           
                         ⁢ 
                         
                           
                             
                               VS 
                               · 
                               Δ 
                             
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             
                               t 
                               
                                 ph 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                           
                             2 
                             · 
                             
                               B 
                               sat 
                             
                             · 
                             
                               A 
                               e 
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     B sat  and A e  depend only on the magnetic material used. The number of turns of the inductor L 2   2  is thus calculated using equation (1). When choosing the material, it must be ensured that the magnetization cycle is sufficiently rectangular in order that the saturation is not “soft” and that the current iL 2  at the saturation points is low (in order to reduce the intensity of effective current). In addition, the area of this cycle must be small to prevent losses known as hysteresis losses. 
     Advantageously, the inductors L 2   1  and L 2   2  are produced in the same coil provided that the number of turns of the coil and the effective cross-sectional area of the magnetic material are adjusted as a consequence. For example, if the number of turns n calculated as described above is not suitable for the coil L 2   1  which corresponds to the inductance of the inductor L 2  when in saturated mode, it is possible to add a supplementary coil in series with L 2 . But it is also possible to re-adjust the number of turns n and the cross-sectional area A e . 
     For example, if the number of turns n calculated for phase  1  is too large for the next phases, it is sufficient to reduce this number and consequently to increase the cross-sectional area A e  so that equation 1 is still satisfied. 
     For example, if the number of turns calculated for phase  1  is 10 and if L 2   1  is four times too high for phases  2 ,  3  and  4 , it is sufficient to divide the number of turns n by 2 and to multiply the cross-sectional area A e  by 2.