Patent Publication Number: US-8541908-B2

Title: Powered device capable of working in continuation in case of power failure

Description:
BACKGROUND 
     1. Technical Field 
     The disclosure relates to power over Ethernet (PoE) technology and, particularly, to a powered device (PD). 
     2. Description of Related Art 
     Generally, Ethernet switches, routers, hubs, and other Ethernet powered devices (PDs) can be connected to a local power supply for continuous power. In addition, the PD can be connected to power sourcing equipment (PSE) which includes a backup battery for temporary power, which uses power over Ethernet (PoE) technology during failure of the local power supply. 
     PoE technology, as proposed by the Institute of Electrical and Electronics Engineers (IEEE), must comply with the IEEE 802.3af standard. Currently, when the PD is powered by the local power supply, the PSE typically functions in an idle mode. In the idle mode, the PSE continues detecting if any functioning PD is loaded thereto every two seconds, and classifies the power of the functioning PD, if detected. Then, the PSE is switched to a normal mode for a normal power supply. Accordingly, it can take as long as four seconds to resume normal power supply from the PSE. During the delay, communication via the PD is unavoidably interrupted. 
     Therefore, it is desirable to provide a protection circuit and a PD, which can overcome the limitations described. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a functional block diagram of one embodiment of a powered device (PD) connected to a local power source and a power sourcing equipment. 
         FIG. 2  is a circuit diagram of one embodiment of the PD, such as, for example, that of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , one embodiment of a power over Ethernet (PoE) system  100  includes power sourcing equipment (PSE)  10 , a local power source  20 , and a powered device (PD)  30 . The PD  30  includes a first conversion circuit  310 , a first diode D 1 , a second conversion circuit  320 , a second diode D 2 , a power switch control circuit  330 , a power switch  340 , and a constant current source (e.g., a current sink)  350 . 
     The first conversion circuit  310  includes a first input  312  and a first output  314 . The first conversion circuit  310  is configured for converting a voltage input to the first input  312  into a rated working voltage Vr of the PD  30  and outputting the rated working voltage Vr via the first output  314  to power the PD  30 . The positive terminal of the first diode D 1  is connected to the local power source  20  and the negative terminal thereof is connected to the first input  312 . The local power source  20  provides a power input with a first input voltage Vin 1  to the first diode D 1 . 
     The second conversion circuit  320  includes a second input  322  and a second output  324 . The second conversion circuit  320  is configured for converting a voltage input to the second input  322  into a second input voltage Vin 2  and outputting the second input voltage Vin 2  via the second output  324 . The second input  322  is connected to the PSE  10 . The PSE  10  provides a power input having a predetermined voltage Vp to the second input  322 . In detail, the PSE  10  is connected to the second input  322  through a media dependent interface (MDI) and an RJ-45 connector. The positive terminal of the second diode D 2  is connected to the second output  324  and the negative terminal thereof is connected to the first input  312 . 
     The first input voltage Vin 1  is higher than the second input voltage Vin 2 . Therefore, when the local power source  20  is functional, the first diode D 1  is forward biased and the second diode D 2  is reverse biased. Electrical connection between the local power source  20  and the first input  312  is established while the electrical path from the second output  324  to the first input  312  is blocked by the reverse-biased second diode D 2 . The PD  30  is powered by the local power source  20  rather than the PSE  10 . 
     In one embodiment, the rated working voltage Vr may be about 3.3V, the first input voltage Vin 1  may be about 12V, the second input voltage Vin 2  may be about 10V, and the predetermined voltage Vp may be about 48V. 
     The power switch control circuit  330  includes a power terminal  332  and a control terminal  334 . The power terminal  332  is connected to the local power source  20 . The power switch control circuit  330  is configured for outputting a connection control signal when the power terminal  332  obtains a high level input from the local power source  20  (i.e., the local power source  20  works properly), or outputting a disconnection control signal when the power terminal  332  gets a low level input from the local power source  20  (i.e., the local power source  20  fails). 
     The power switch  340  includes two connection terminals  342  and an enable terminal  344 . The two connecting ends  342  are respectively connected to the second output  324  and the constant current source  350 . The enable terminal  344  is connected to the control terminal  334 . The power switch  340  enables power transmission between the two connection terminals  342  so that the constant current source  350  can draw power, that is current from the PSE  10  when the enable terminal  344  receives the connection control signal, or disables power transmission between the two connection terminals  342  when the enable terminal  344  receives the disconnection control signal. 
     According to the IEEE 802.3af standard, to maintain a PSE in a normal mode (one in which the PSE can provide normal power supply), the PD(s) is required to present a maintain power signal (MPS) to the PSE  10 . The MPS can be, for example, draw of at least 10 mA direct current from the PSE by the PD. Thus, as long as the constant current source  350  draws at least 10 mA direct current, the PSE  10  is maintained in normal mode, in which power is provided to the PD  30  in continuation from the PSE  10  once the power local source  20  is down. That is, when the local power source  20  fails (e.g., an interrupted operation), the first diode D 1  becomes reverse-biased, and the second diode D 2  becomes forward-biased. Interrupted service to the PD  30  is enabled. 
     To reduce power consumption of PSE  10 , the constant current source  350  draws as small as possible exceeding 10 mA direct current from the PSE  10 . In this embodiment, the constant current source  350  draws slightly more than 10 mA direct current from the PSE  10 . 
     After the failure of the local power source  20 , the power terminal  332  of the power switch control circuit  330  receives the low level input. Accordingly, the control terminal  334  outputs the disconnection control signal. The power switch  340  disables power transmission between the two connection terminals  342  since the enable terminal  344  receives the disconnection control signal from the control terminal  334 . The constant current source  350  no longer draws power from the PSE  10 . This also helps to reduce the power consumption of the PSE  10 . To simplify the circuit of the PD  30  and reduce cost thereof, in alternative embodiments, the power switch control circuit  330  and power switch  340  can be omitted, whereby the constant current source  350  is directly connected to the second output  324 . 
     Referring to  FIG. 2 , the power switch control circuit  330  includes a voltage regulator chip U (e.g., 78D05L). The voltage regulator chip U includes an input Vin, an output Vout, and a ground terminal GND. The voltage regulator chip U is configured for converting the first voltage input Vin 1  input thereto by the input Vin into an enable signal Vsw and outputting the enable signal Vsw via the output Vout. The input Vin of the voltage regulator chip U is the power terminal  332  of the power switch control circuit  330 . The output Vout of the voltage regulator chip U is the control terminal  334  of the power switch control circuit  330 . When the enable signal Vsw is high, such as about 5V, the enable signal Vsw is the connection control signal. When the enable signal Vsw is low, such as about 0V, the enable signal Vsw is the disconnection control signal. In particular, the power switch control circuits  330  may also include two bypass capacitors C. The input Vin and the output Vout of the voltage regulator chip U are connected to ground by the two bypass capacitors C respectively. 
     The power switch  340  includes a first npn transistor Q 1 , a third resistor R 3 , a fourth resistor R 4 , a bypass capacitor C, a second npn transistor Q 2 , a fifth resistor R 5 , and a third npn transistor Q 3 . The base of the first npn transistor Q 1  is the enable terminal  344  and is connected to the output Vout of the voltage regulator chip U. The collector of the first npn transistor Q 1  is connected to the PSE  10  through the third resistor R 3 . The emitter of the first npn transistor Q 1  is grounded. The base of the second npn transistor Q 2  is connected to the collector of the first npn transistor Q 1  through the fourth resistor R 4  and is also connected to ground via the bypass capacitor C. The collector of the second npn transistor Q 2  is connected to the base of the third npn transistor Q 3 . The emitter of the second npn transistor Q 2  is grounded. The collector of the third npn transistor Q 3  is one of the connection terminals  342  of the power switch  340 , connected to the PSE  10 . The emitter of the third npn transistor Q 3  is another connection terminal  342 , connected to the constant current source  350 . In operation, when the enable signal Vsw is high, that is the connection control signal, the first npn transistor Q 1  turns on, the second npn transistor Q 2  turns off, and the third npn transistor Q 3  turns on. That is, the two connection terminals  342  of the power switch  340  are connected. When the enable signal Vsw is low, that is the disconnection control signal, the first npn transistor Q 1  turns off, the second npn transistor Q 2  turns on, and the third npn transistor Q 3  turns off. That is, the two connection terminals  342  of the power switch  340  are disconnected. 
     The constant current source  350  is a current negative feedback circuit, which includes a sixth resistor R 6 , a fourth npn transistor Q 4 , a fifth npn transistor Q 5 , and a seventh resistor R 7 . The collector of the fourth npn transistor Q 4  is connected to one of the connection terminals  342  of the power switch  340 , that is the emitter of the third npn transistor Q 3 . The base of the fourth npn transistor Q 4  is also connected to the connection terminal  342  of the power switch  340  via the sixth resistor R 6 . The emitter of the fourth npn transistor Q 4  is connected to ground through a seventh resistor R 7 . The collector of the fifth npn transistor Q 5  is connected to the base of the fourth npn transistor Q 4 . The base of the fifth npn transistor Q 5  is connected to the emitter of the fourth npn transistor Q 4 . The emitter of the fifth npn transistor Q 5  is grounded. In operation, when the current through the seventh resistor R 7  increases, the voltage of the base of the fifth npn transistor Q 5  increases accordingly. The current through the sixth resistor R 6  increases due to the current amplification effect of the fifth npn transistor Q 5 , resulting in a smaller voltage of the base of the fourth npn transistor Q 4 . As such, the current through the base of the fourth npn transistor Q 4  decreases. The current through the collector of the fourth npn transistor Q 4  decreases due to the current amplification effect of the fourth npn transistor Q 4 . Consequently, the current through the seventh resistor R 7  decreases. The opposite happens when the current through the seventh resistor R 7  increases. That is, the current through the seventh resistor R 7  is locked. 
     While various exemplary and preferred embodiments have been described, it is to be understood that the disclosure is not limited thereto. To the contrary, various modifications and similar arrangements (as would be apparent to those skilled in the art) are intended to also be covered. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.