Patent Publication Number: US-2022238058-A1

Title: Display device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 16/532,411, filed Aug. 5, 2019, which claims priority to and the benefit of Korean Patent Application No. 10-2018-0120765, filed Oct. 10, 2018, the entire content of both of which is incorporated herein by reference. 
    
    
     BACKGROUND 
     1. Field 
     The present disclosure generally relates to a display device. 
     2. Description of the Related Art 
     With the development of information technologies, the importance of a display device, which is a connection medium between a user and information, increases. Accordingly, display devices such as liquid crystal display devices and organic light emitting display devices are increasingly used. 
     An organic light emitting display device includes a plurality of pixels, and displays an image frame by allowing organic light emitting diodes of the plurality of pixels to emit lights so as to correspond to a plurality of grayscale values constituting the image frame. 
     In general, in the organic light emitting display device, grayscale voltages are set to exhibit a luminance according to a gamma curve more suitable for a white color light radiated when pixels of different colors emit lights with the same grayscale value. 
     Therefore, when a mixed color light or a single color light is radiated instead of the white color light, using the set grayscale voltages, the luminance of the mixed color light or the single color light does not exactly correspond to the above-described gamma curve. In addition, there exists a lateral leakage problem in that, when the single color light is radiated, holes of driving current flowing in a corresponding pixel are leaked to an adjacent pixel having a small resistance through a P-doped Hole Injection Layer (PHIL) that is a layer shared by the organic light emitting diodes, and therefore, the corresponding pixel does not emit light with a desired luminance. 
     SUMMARY 
     Embodiments provide a display device capable of exhibiting a desired luminance not only when a white color light is radiated but also when a single color light or a mixed color light is radiated. 
     According to an aspect of the present disclosure, there is provided a display device including: a target pixel; observation target pixels located adjacent to the target pixel; and a grayscale corrector configured to convert an input grayscale value corresponding to the target pixel with reference to observation target grayscale values corresponding to the observation target pixels, wherein the grayscale corrector includes: a light emitting pixel counter configured to provide a number of light emitting pixels by counting a number of observation target grayscale values that exceed a reference value; and a grayscale converter configured to provide a converted grayscale value by converting the input grayscale value, based on the number of light emitting pixels. 
     The grayscale corrector may further include a single color offset provider configured to provide single color offset values. When the number of light emitting pixels is 0, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the single color offset values to the input grayscale value. 
     The grayscale corrector may further include a mixed color offset provider configured to provide mixed color offset values. When the number of light emitting pixels is greater than 0 and is less than the number of observation target pixels, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the mixed color offset values to the input grayscale value. 
     When the number of light emitting pixels is equal to the number of observation target pixels, the grayscale converter may determine the input grayscale value as the converted grayscale value. 
     The single color offset provider may include: a reference offset provider configured to receive an input maximum luminance value, and to provide reference offset values corresponding to the input maximum luminance value; and a total offset generator configured to generate single color offset values by interpolating the reference offset values. 
     The reference offset provider may include a preset determiner configured to store, in advance, preset offset values corresponding to preset maximum luminance values, and to determine whether the input maximum luminance value corresponds to any one of the preset maximum luminance values. When the input maximum luminance value corresponds to any one of the preset maximum luminance values, the preset determiner may provide the corresponding preset offset values as the reference offset values. 
     When the input maximum luminance value does not correspond to any one of the preset maximum luminance values, the preset determiner may provide the preset offset values corresponding to at least two preset maximum luminance values. The reference offset provider may further include a reference offset generator configured to generate the reference offset values by interpolating the preset offset values corresponding to the at least two preset maximum luminance values. 
     The preset maximum luminance values may include a maximum value and a minimum value of a receivable input maximum luminance value. 
     The preset maximum luminance values may further include a first intermediate maximum luminance value. When the input maximum luminance value is between the maximum value and the first intermediate maximum luminance value, a grayscale voltage corresponding to the converted grayscale value may be adjusted corresponding to the input maximum luminance value, so that the luminance of the target pixel is controlled. 
     When the input maximum luminance value is between the minimum value and the first intermediate maximum luminance value, an emission period of the target pixel may be adjusted corresponding to the input maximum luminance value, so that the luminance of the target pixel is controlled. 
     The preset maximum luminance values may further include a second intermediate maximum luminance value that is between the first intermediate maximum luminance value and the minimum value. 
     The target pixel may be a pixel that emits light of a first color with a luminance corresponding to the converted grayscale value, and at least some of the observation target pixels may be pixels that emit light of a second color different from the first color. 
     At least some of the observation target pixels may be pixels that emit light of a third color different from the first color and the second color. 
     The grayscale corrector may further include a single color offset provider configured to provide single color offset values. When the number of light emitting pixels is 0, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the single color offset values to the input grayscale value. 
     The grayscale corrector may further include a mixed color offset provider configured to provide mixed color offset values. When the number of light emitting pixels is greater than 0 and is less than the number of observation target pixels, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the mixed color offset values to the input grayscale value. 
     When the number of light emitting pixels is equal to the number of observation target pixels, the grayscale converter may determine the input grayscale value as the converted grayscale value. 
     At least some of the observation target pixels may be pixels that emit light of the first color. 
     The grayscale corrector may further include a single color offset provider configured to provide single color offset values. When the number of light emitting pixels corresponding to the second color and the third color is 0, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the single color offset values to the input grayscale value. 
     The grayscale corrector may further include a mixed color offset provider configured to provide mixed color offset values. When the number of light emitting pixels corresponding to the second color and the third color is not 0 and is less than the number of observation target pixels corresponding to the second color and the third color, the grayscale converter may generate the converted grayscale value by adding a corresponding offset value from among the mixed color offset values to the input grayscale value. 
     When the number of light emitting pixels corresponding to the second color and the third color is equal to the number of observation target pixels corresponding to the second color and the third color, the grayscale converter may determine the input grayscale value as the converted grayscale value. 
     According to another aspect of the present disclosure, there is provided a display device including: a first pixel configured to emit light of a first color; a second pixel configured to emit light of a second color different from the first color; a third pixel configured to emit light of a third color different from the first color and the second color; and a grayscale corrector configured to convert input grayscale values corresponding to the first, second, and third pixels to converted grayscale values, wherein the first, second, and third pixels are configured to emit lights, based on the converted grayscale values, wherein a first luminance of the first pixel in a first case where the first pixel, the second pixel, and the third pixel emit lights is different from a second luminance of the first pixel in a second case where only the first pixel emits light and the second and third pixels do not emit light, wherein an input grayscale value corresponding to the first pixel in the first case is equal to that corresponding to the first pixel in the second case, and a converted grayscale value corresponding to the first luminance is different from that corresponding to the second luminance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. 
       In the drawing figures, dimensions may be exaggerated for clarity of illustration. It will be understood that when an element is referred to as being “between” two elements, it may be the only element between the two elements, or one or more intervening elements may also be present. Like reference numerals refer to like elements throughout. 
         FIG. 1  is a diagram illustrating a display device according to an embodiment of the present disclosure. 
         FIG. 2  is a diagram illustrating an exemplary pixel of the display device of  FIG. 1 . 
         FIG. 3  is a diagram illustrating an exemplary driving method of the pixel of  FIG. 2 . 
         FIG. 4  is a diagram illustrating a display device according to another embodiment of the present disclosure. 
         FIG. 5  is a diagram illustrating an exemplary pixel of the display device of  FIG. 4 . 
         FIG. 6  is a diagram illustrating an exemplary driving method of the pixel of  FIG. 5 . 
         FIG. 7  is a diagram illustrating a grayscale voltage generator according to an embodiment of the present disclosure. 
         FIG. 8  is a diagram illustrating an exemplary portion of the grayscale voltage generator of  FIG. 7 . 
         FIGS. 9-10  are diagrams illustrating a case where pixels emit a white color light according to a maximum luminance value. 
         FIGS. 11-14  are diagrams illustrating a case where the pixels emit a single color light. 
         FIG. 15  is a diagram illustrating a grayscale corrector according to an embodiment of the present disclosure. 
         FIGS. 16-18  are diagrams illustrating a single color offset provider of  FIG. 15 . 
         FIG. 19  is a diagram illustrating a configuration of an exemplary offset value. 
         FIG. 20  is a diagram illustrating an effect obtained by applying a single offset value. 
         FIGS. 21-22  are diagrams illustrating a reference offset provider of  FIG. 16 . 
         FIGS. 23-27  are diagrams illustrating a mixed color offset provider of  FIG. 15 . 
         FIGS. 28-31  are diagrams illustrating a tuning process performed by considering a mixed color light. 
         FIGS. 32-34  are diagrams illustrating a case where the range of observation target pixels is differently set. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, exemplary embodiments are described in detail with reference to the accompanying drawings so that those skilled in the art may practice the present disclosure. The present disclosure may be implemented in various different forms and is not limited to the exemplary embodiments described in the present specification. 
     A part irrelevant to the description may be omitted to clearly describe the present disclosure, and the same or similar constituent elements may be designated by the same reference numerals throughout the specification. Therefore, the same reference numerals may be used in different drawings to identify the same or similar elements. 
     In addition, the size and thickness of each component illustrated in the drawings may be arbitrarily shown for better understanding and ease of description, but the present disclosure is not limited thereto. Thicknesses of several portions and regions may have been exaggerated for clear expressions. 
     It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. 
     As used herein, the term “substantially,” “about,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. 
     The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein, such as, for example, an external controller, a timing controller, a data driver, a scan driver, a grayscale voltage generator, a grayscale corrector, and an emission driver, may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware known to those of ordinary skill in the art. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of ordinary skill in the art should recognize that the functionality of various computing/electronic devices may be combined or integrated into a single computing/electronic device, or the functionality of a particular computing/electronic device may be distributed across one or more other computing/electronic devices without departing from the spirit and scope of the present disclosure. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein. 
       FIG. 1  is a diagram illustrating a display device according to an embodiment of the present disclosure. 
     Referring to  FIG. 1 , the display device  10  according to the embodiment of the present disclosure may include a timing controller  11 , a data driver  12 , a scan driver  13 , pixels  14  in a display region, a grayscale voltage generator  15 , and a grayscale corrector  16 . 
     The timing controller  11  may receive input grayscale values with respect to an image frame and control signals, which are provided from an external controller. The grayscale corrector  16  may provide converted grayscale values by correcting the input grayscale values. 
     The timing controller  11  may provide the data driver  12  with the converted grayscale values and the control signals. Also, the timing controller  11  may provide the scan driver  13  with a clock signal, a scan start signal, and the like. 
     The data driver  12  may generate data voltages to be provided to data lines DL 1 , DL 2 , DL 3 , . . . , and DLn, using the converted grayscale values and the control signals, which are received from the timing controller  11 . For example, the data driver  12  may sample converted grayscale values, using the clock signal, and apply data voltages corresponding to the converted grayscale values to the data lines DL 1  to DLn in units of pixel rows. Here, n may be a natural number. The data voltages may correspond to grayscale voltages RV 0  to RV 255 , GV 0  to GV 255 , and BV 0  to BV 255  provided from the grayscale voltage generator  15 . 
     The scan driver  13  may generate scan signals to be provided to scan lines SL 1 , SL 2 , SL 3 , . . . , and SLm by receiving the clock signal, the scan start signal, and the like from the timing controller  11 . For example, the scan driver  13  may sequentially provide the scan signals having a turn-on level pulse to the scan line SL 1  to SLm. For example, the scan driver  13  may be configured in the form of a shift register, and generate the scan signals in a manner that sequentially transfers the scan start signal provided in the form of a turn-on level pulse to a next stage circuit under the control of the clock signal. Here, m may be a natural number. 
     The pixels  14  may include pixels RPij. Each pixel RPij may be connected to a corresponding scan line and a corresponding data line. Here, i and j may be natural numbers. The pixel RPij may refer to a pixel in which a scan transistor is connected to an ith scan line and a jth data line. 
     The pixels  14  may include pixels for emitting light of a first color, pixels for emitting light of a second color, and pixels for emitting light of a third color. The first color, the second color, and the third color may be colors different from one another. For example, the first color may be one color from among red, green, and blue, the second color may be one color except the first color from among red, green, and blue, and the third color may be the other color except the first color and the second color from among red, green, and blue. In addition, magenta, cyan, and yellow instead of red, green, and blue may be used as the first to third colors. However, for convenience of description, a case where red, green, and blue are used as the first to third colors, and magenta, cyan, and yellow are respectively expressed as a combination of red and blue, a combination of green and blue, and a combination of red and green is described in this embodiment. 
     Hereinafter, a case where the pixels  14  are arranged in a diamond Pentile® form is assumed and described. Pentile® is a registered trademark of Samsung Display Co., Ltd., Yongin-si, Republic of Korea. However, even if the pixels  14  were arranged in another suitable arrangement form, e.g., a form such as an RGB-stripe, an S-stripe, a read RGB, or a normal Pentile®, those skilled in the art after reviewing the present disclosure would know how to appropriately set a target pixel and observation target pixels, which will be described later, so as to implement embodiments of the present disclosure. 
     Hereinafter, the positions of the pixels  14  may be described based on the position of a light emitting diode of each of the pixels  14 . That is, the position of a pixel circuit connected to the light emitting diode of each of the pixels  14  may not correspond to the position of the light emitting diode, and the pixel circuit may be appropriately disposed in the display device  10 . 
     The grayscale voltage generator  15  may receive an input maximum luminance value DBVI from the timing controller  11 , and provide grayscale voltages RV 0  to RV 255  of the pixels of the first color, which correspond to the input maximum luminance value DBVI, grayscale voltages GV 0  to GV 255  of the pixels of the second color, which correspond to the input maximum luminance value DBVI, and grayscale voltages BV 0  to BV 255  of the pixels of the third color, which correspond to the input maximum luminance value DBVI. Hereinafter, a case where a total of 256 grayscale levels (i.e., gray levels) from grayscale level 0 (minimum grayscale level) to grayscale level 255 (maximum grayscale level) exist will be described for convenience of description. However, when a grayscale value is expressed exceeding 8 bits, a greater number of grayscale levels may exist. The minimum grayscale level may be the darkest grayscale level, and the maximum grayscale level may be the brightest grayscale level. 
     A maximum luminance value may be a luminance value of lights emitted from pixels, corresponding to the maximum grayscale level. For example, the maximum luminance value may be a luminance value of a white color light generated when a pixel of the first color, which constitutes one dot, emits light corresponding to the grayscale level 255, a pixel of the second color, which constitutes one dot, emits light corresponding to the grayscale level 255, and a pixel of the third color, which constitutes one dot, emits light corresponding to the grayscale level 255. The unit of a luminance value may be a nit. 
     Therefore, the pixels may display a partially (spatially) dark or bright image frame, but the maximum brightness of the image frame is limited to the maximum luminance value. The maximum luminance value may be manually set by a manipulation of a user with respect to the display device  10 , or be automatically set by an algorithm linked with an illumination sensor, etc. The set maximum luminance value is expressed as an input maximum luminance value. 
     The maximum luminance value may be changed depending on products. However, for example, the maximum value of the maximum luminance value may be 1200 nit, and the minimum value of the maximum luminance value may be 4 nits. When the input maximum luminance DBVI is changed even though grayscale values are the same, the grayscale corrector  16  provides different grayscale voltages RV 0  to RV 255 , GV 0  to GV 255 , and BV 0  to BV 255 , and therefore, the light emitting luminance of a pixel is changed. 
     The grayscale corrector  16  may correct an input grayscale value to a converted grayscale value as described above. The grayscale corrector  16  will be described in detail later with reference to drawings from  FIG. 15 . 
     In the above-described embodiment, a case where the grayscale corrector  16  is a component separate from the timing controller  11  is illustrated. In some embodiments, a portion or the whole of the grayscale corrector  16  may be integrally configured with the timing controller  11 . For example, a portion or the whole of the grayscale corrector  16  along with the timing controller  11  may be configured in the form of an integrated circuit. In some embodiments, a portion or the whole of the grayscale corrector  16  may be implemented in a software manner in the timing controller  11 . 
     In another embodiment, a portion or the whole of the grayscale corrector  16  along with the data driver  12  may be configured in the form of an integrated circuit. In some embodiments, a portion or the whole of the grayscale corrector  16  may be implemented in a software manner in the timing controller  11 . In an embodiment, the timing controller  11  may first provide input grayscale values to the data driver  12 , and the grayscale corrector  16  or the data driver  12  may autonomously correct the input grayscale values to converted grayscale values. 
     In still another embodiment, a portion or the whole of the grayscale corrector  16  along with the external controller may be configured in the form of an integrated circuit. In some embodiments, a portion or the whole of the grayscale corrector  16  may be implemented in a software manner in the external controller. In an embodiment, the timing controller  11  may directly receive converted grayscale values provided from the external controller. 
       FIG. 2  is a diagram illustrating an exemplary pixel of the display device of  FIG. 1 .  FIG. 3  is a diagram illustrating an exemplary driving method of the pixel of  FIG. 2 . 
     The pixel RPij may be a pixel for emitting light of the first color. Pixels for emitting light of the second color or the third color include components that are substantially identical to those of the pixel RPij, except for a light emitting diode R_LD 1 , and therefore, overlapping descriptions may be omitted. 
     The pixel RPij may include a plurality of transistors T 1  and T 2 , a storage capacitor Cst 1 , and the light emitting diode R_LD 1 . While the pixel RPij (or other pixels such as the pixel RPij′ of  FIG. 4 ) having a single light emitting diode R_LD 1  (or R_LD 2 ) is primarily being referred to herein as a pixel, the pixel RPij may alternately be referred to as a subpixel of a pixel including a plurality of subpixels. In such a pixel including a plurality of subpixels, each of the subpixels may be configured to emit light of a color, such as, for example, red, green, blue, or white. Further, such a pixel may include two or more subpixels that are configured to emit a same color while including only one subpixel per each of other colors. 
     In this embodiment, a case where the transistors are implemented with P-type transistors, e.g., a PMOS transistors, is illustrated, but those skilled in the art would know how to implement a pixel circuit having the same function, using N-type transistors, e.g., NMOS transistors, based on the teachings of the present disclosure. 
     A gate electrode of the transistor T 2  is connected to a scan line SLi, one electrode of the transistor T 2  is connected to a data line DLj, and the other electrode of the transistor T 2  is connected to a gate electrode of the transistor T 1 . The transistor T 2  may be referred to as a switching transistor, a scan transistor or the like. 
     The gate electrode of the transistor T 1  is connected to the other electrode of the transistor T 2 , one electrode of the transistor T 1  is connected to a first power voltage line ELVDD, and the other electrode of the transistor T 1  is connected to an anode of the light emitting diode R_LD 1 . The transistor T 1  may be referred to as a driving transistor. 
     The storage capacitor Cst 1  is interposed between the one electrode and the gate electrode of the transistor T 1 , and is configured to apply voltage between the one electrode and the gate electrode of the transistor T 1 . 
     The anode of the light emitting diode R_LD 1  is connected to the other electrode of the transistor T 1 , and a cathode of the light emitting diode R_LD 1  may be connected to a second power voltage line ELVSS. The light emitting diode R_LD 1  may be an element (or a device) that emits light having a wavelength corresponding to the first color. The light emitting diode R_LD 1  may correspond to an organic light emitting diode, a nano light emitting diode, etc. 
     When a turn-on level (low level) scan signal is supplied (i.e., applied) to the gate electrode of the transistor T 2  through the scan line SLi, the transistor T 2  connects (e.g., electrically connects) the data line DLj and one electrode of the storage capacitor Cst 1 . Therefore, a voltage value corresponding to the difference between a data voltage DATAij applied to the data line DLj and a voltage of the first power voltage line ELVDD is written in the storage capacitor Cst 1 . The data voltage DATAij may correspond (or may substantially correspond) to one of the grayscale voltages RV 0  to RV 255 . 
     The transistor T 1  allows a driving current determined according to the voltage value written in the storage capacitor Cst 1  to flow from the first power voltage line ELVDD to the second power voltage line ELVSS. The light emitting diode R_LD 1  emits light with a luminance corresponding to a magnitude of the driving current. 
       FIG. 4  is a diagram illustrating a display device according to another embodiment of the present disclosure. 
     The display device  10 ′ of  FIG. 4  may include components substantially identical to those of the display device  10  of  FIG. 1 , except for an emission driver  17  and pixels  14 ′ in a display region. Therefore, descriptions of overlapping components may be omitted. 
     The emission driver  17  may receive a clock signal, an emission stop signal, etc., and may generate emission signals to be provided to emission lines EL 1 , EL 2 , EL 3 , . . . , and ELo. For example, the emission driver  17  may sequentially provide the emission signals having a turn-off level pulse to the emission lines EL 1  to ELo. For example, the emission driver  17  may be configured in the form of a shift register, and may generate the emission signals in a manner that sequentially transfers the emission stop signal provided in the form of a turn-off level pulse to a next stage circuit under the control of the clock signal. Here, o may be a natural number. 
     The pixels  14 ′ may include pixels RPij′. Each pixel RPij′ may be connected to a corresponding data line, a corresponding scan line, and a corresponding emission line. 
       FIG. 5  is a diagram illustrating an exemplary pixel of the display device of  FIG. 4 . 
     Referring to  FIG. 5 , the pixel RPij′ may include transistors M 1 , M 2 , M 3 , M 4 , M 5 , M 6 , and M 7 , a storage capacitor Cst 2 , and a light emitting diode R_LD 2 . 
     One electrode of the storage capacitor Cst 2  is connected to a first power voltage line ELVDD, and the other electrode of the storage capacitor Cst 2  is connected to a gate electrode of the transistor M 1 . 
     One electrode of the transistor M 1  is connected to the other electrode (i.e., an electrode other than an electrode connected to the first power voltage line ELVDD or a gate electrode) of the transistor M 5 , the other electrode of the transistor M 1  is connected to one electrode of the transistor M 6 , and the gate electrode of the transistor M 1  is connected to the other electrode of the storage capacitor Cst 2 . The transistor M 1  may be referred to as a driving transistor. The transistor M 1  determines an amount of driving current flowing between the first power voltage line ELVDD and a second power voltage line ELVSS according to a potential difference between the gate electrode and a source electrode. 
     One electrode of the transistor M 2  is connected to a data line DLj, the other electrode of the transistor M 2  is connected to the one electrode of the transistor M 1 , and a gate electrode of the transistor M 2  is connected to a current scan line SLi. The transistor M 2  may be referred to as a switching transistor, a scan transistor or the like. The transistor M 2  allows a data voltage of the data line DLj to be input to the pixel RPij′ when a turn-on level scan signal is applied to the current scan line SLi. 
     One electrode of the transistor M 3  is connected to the other electrode of the transistor M 1 , the other electrode of the transistor M 3  is connected to the gate electrode of the transistor M 1 , and a gate electrode of the transistor M 3  is connected to the current scan line SLi. The transistor M 3  connects the transistor M 1  in a diode form when a turn-on level scan signal is applied to the current scan line SLi. 
     One electrode of the transistor M 4  is connected to the gate electrode of the transistor M 1 , the other electrode of the transistor M 4  is connected to an initialization voltage line VINT, and a gate electrode of the transistor M 4  is connected to a previous scan line SL(i−1). In another embodiment, the gate electrode of the transistor M 4  may be connected to another scan line. The transistor M 4  transfers an initialization voltage to the gate electrode of the transistor M 1  when a turn-on level scan signal is applied to the previous scan line SL(i−1), to initialize a charge quantity of the gate electrode of the transistor M 1 . 
     One electrode of the transistor M 5  is connected to the first power voltage line ELVDD, the other electrode of the transistor M 5  is connected to the one electrode of the transistor M 1 , and the gate electrode of the transistor M 5  is connected to an emission line ELi. The one electrode of the transistor M 6  is connected to the other electrode of the transistor M 1 , the other electrode of the transistor M 6  is connected to an anode of the light emitting diode R_LD 2 , and a gate electrode of the transistor M 6  is connected to the emission line ELi. Each of the transistors M 5  and M 6  may be referred to as an emission transistor. Each of the transistors M 5  and M 6  allows the light emitting diode R_LD 2  to emit light by forming a driving current path between the first power voltage line ELVDD and the second power voltage line ELVSS when a turn-on level emission signal is applied to the emission line ELi. 
     One electrode of the transistor M 7  is connected to the anode of the light emitting diode R_LD 2 , the other electrode of the seventh transistor M 7  is connected to the initialization voltage line VINT, and a gate electrode of the transistor M 7  is connected to the current scan line SLi. In another embodiment, the gate electrode of the transistor M 7  may be connected to another scan line. For example, the gate electrode of the transistor M 7  may be connected to the previous scan line SL(i−1), a previous scan line before the previous scan line SL(i−1), a next scan line (i+1)th scan line), or a next scan line after the (i+1)th scan line. The transistor M 7  transfers the initialization voltage to the anode of the light emitting diode R_LD 2  when a turn-on level scan signal is applied to the current scan line SLi, to initialization a charge quantity accumulated in the light emitting diode R_LD 2 . 
     The anode of the light emitting diode R_LD 2  is connected to the other electrode of the transistor M 6 , and a cathode of the light emitting diode R_LD 2  is connected to the second power voltage line ELVSS. 
       FIG. 6  is a diagram illustrating an exemplary driving method of the pixel of  FIG. 5 . 
     First, a turn-on level (low-level) scan signal is applied to the previous scan line SL(i−1). Because the transistor M 4  is in a turn-on state, the initialization voltage is applied to the gate electrode of the transistor M 1  such that the charge quantity of the gate electrode of the transistor M 1  is initialized. Because a turn-off level emission signal is applied to the emission line ELi, the transistors M 5  and M 6  are in a turn-off state, and unnecessary emission of the light emitting diode R_LD 2  in the process of applying the initialization voltage is prevented or reduced. 
     Next, a data voltage DATAij of a current pixel row is applied to the data line DLj, and a turn-on level scan signal is applied to the current scan line SLi. Accordingly, the transistors M 2 , M 1 , and M 3  are in a conduction state, and the data line DLj and the gate electrode of the transistor M 1  are electrically connected. Thus, the data voltage DATAij is applied to the other electrode of the storage capacitor Cst 2 , and the storage capacitor Cst 2  accumulates a charge quantity corresponding to the difference between the voltage of the first power voltage line ELVDD and the data voltage DATAij. 
     Because the transistor M 7  is in the turn-on state, the anode of the light emitting diode R_LD 2  and the initialization voltage line VINT are electrically connected, and the light emitting diode R_LD 2  is precharged or initialized to a charge quantity corresponding to the difference between the initialization voltage and the voltage of the second power voltage line ELVSS. 
     Subsequently, when a turn-on level emission signal is applied to the emission line ELi, the transistors M 5  and M 6  are in the conduction state, and the amount of driving current flowing through the transistor M 1  is adjusted depending on a charge quantity accumulated in the storage capacitor Cst 2 , so that the driving current flows through the light emitting diode R_LD 2 . The light emitting diode R_LD 2  emits light until before a turn-off level emission signal is applied to the emission line ELi. 
       FIG. 7  is a diagram illustrating a grayscale voltage generator according to an embodiment of the present disclosure. 
     The grayscale voltage generator may include a first grayscale voltage generator  151 , a second grayscale voltage generator  152 , and a third grayscale voltage generator  153 . 
     The first grayscale voltage generator  151  may receive an input maximum luminance value DBVI, and provide grayscale voltages RV 0  to RV 255  with respect to pixels of the first color, which correspond to the input maximum luminance value DBVI. 
     The second grayscale voltage generator  152  may receive the input maximum luminance value DBVI, and provide grayscale voltages GV 0  to GV 255  with respect to pixels of the second color, which correspond to the input maximum luminance value DBVI. 
     The third grayscale voltage generator  153  may receive the input maximum luminance value DBVI, and provide grayscale voltages BV 0  to BV 255  with respect to pixels of the third color, which correspond to the input maximum luminance value DBVI. 
       FIG. 8  is a diagram illustrating an exemplary portion of the grayscale voltage generator of  FIG. 7 . 
     Referring to  FIG. 8 , the first grayscale voltage generator  151  may include a select value provider  1511 , a grayscale voltage output unit  1512 , resistor strings RS 1  to RS 11 , multiplexers MX 1  to MX 12 , and resistors R 1  to R 10 . 
     The second grayscale voltage generator  152  and the third grayscale voltage generator  153  may include components substantially identical to those of the first grayscale voltage generator  151 , and therefore, overlapping descriptions may be omitted. 
     The select value provider  1511  may provide select values with respect to the multiplexers MX 1  to MX 12  according to the input maximum luminance value DBVI. 
     The select values according to the input maximum luminance value DBVI may be stored in advance in a memory element, e.g., an element such as a register. 
     The resistor string RS 1  may generate intermediate voltages between a first reference voltage VH and a second reference voltage VL. The multiplexer MX 1  may output a third reference voltage VT by selecting one of the intermediate voltages provided from the resistor string RS 1  according to a select value. The multiplexer MX 2  may output grayscale voltage  255  RV 255  by selecting one of the intermediate voltages provided from the resistor string RS 1  according to a select value. 
     The resistor string RS 11  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  255  RV 255 . The multiplexer MX 12  may output grayscale voltage  203  RV 203  by selecting one of the intermediate voltages provided from the resistor string RS 11  according to a select value. 
     The resistor string RS 10  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  203  RV 203 . The multiplexer MX 11  may output grayscale voltage  151  RV 151  by selecting one of the intermediate voltages provided from the resistor string RS 10  according to a select value. 
     The resistor string RS 9  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  151  RV 151 . The multiplexer MX 10  may output grayscale voltage  87  RV 87  by selecting one of the intermediate voltages provided from the resistor string RS 9  according to a select value. 
     The resistor string RS 8  may generate intermediate voltages between the third reference voltage VT and the grayscale voltages  87  RV 87 . The multiplexer MX 9  may output grayscale voltage  51  RV 51  by selecting one of the intermediate voltages provided from the resistor string RS 8  according to a select value. 
     The resistor string RS 7  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  51  RV 51 . The multiplexer MX 8  may output grayscale voltage  35  RV 35  by selecting one of the intermediate voltages provided from the resistor string RS 7  according to a select value. 
     The resistor string RS 6  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  35  RV 35 . The multiplexer MX 7  may output grayscale voltage  23  RV 23  by selecting one of the intermediate voltages provided from the resistor string RS 6  according to a select value. 
     The resistor string RS 5  may generate intermediate voltages between the third reference voltage VT and the grayscale voltage  23  RV 23 . The multiplexer MX 6  may output grayscale voltage  11  RV 11  by selecting one of the intermediate voltages provided from the resistor string RS 5  according to a select value. 
     The resistor string RS 4  may generate intermediate voltages between the first reference voltage VH and the grayscale voltage  11  RV 11 . The multiplexer MX 5  may output grayscale voltage  7  RV 7  by selecting one of the intermediate voltages provided from the resistor string RS 4  according to a select value. 
     The resistor string RS 3  may generate intermediate voltages between the first reference voltage VH and the grayscale voltage  7  RV 7 . The multiplexer MX 4  may output grayscale voltage  1  RV 1  by selecting one of the intermediate voltages provided from the resistor string RS 3  according to a select value. 
     The resistor string RS 2  may generate intermediate voltages between the first reference voltage VH and the grayscale voltage  1  RV 1 . The multiplexer MX 3  may output grayscale voltage  0  RV 0  by selecting one of the intermediate voltages provided from the resistor string RS 2  according to a select value. 
     The above-described grayscale levels 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 may be referred to as reference grayscale levels. In addition, the grayscale voltages RV 0 , RV 1 , RV 7 , RV 11 , RV 23 , RV 35 , RV 51 , RV 87 , RV 151 , RV 203 , and RV 255  generated from the multiplexers MX 2  to MX 12  may be referred to as reference grayscale voltages. The number of reference grayscale levels and grayscale numbers corresponding to the reference grayscale levels may be differently set depending on products. Hereinafter, for convenience of description, the grayscale levels 0, 1, 7, 11, 23, 35, 51, 87, 151, 203, and 255 are described as reference grayscale levels. 
     The grayscale voltage output unit  1512  may generate all grayscale voltages RV 0  to RV 255  by dividing the reference grayscale voltages RV 0 , RV 1 , RV 7 , RV 11 , RV 23 , RV 35 , RV 51 , RV 87 , RV 151 , RV 203 , and RV 255 . For example, the grayscale voltage output unit  1512  may generate grayscale voltages RV 2  to RV 6  by dividing reference grayscale voltages RV 1  and RV 7 . 
       FIGS. 9-10  are diagrams illustrating a case where pixels emit a white color light according to a maximum luminance value. 
     Referring to  FIG. 9 , an arrangement example of the pixels  14  is partially illustrated. As described above,  FIG. 9  is illustrated based on the positions of light emitting diodes of the pixels  14 , and scan lines SL 1  to SL 7  and data lines DL 1  to DL 7  are illustrated to describe an electrical connection of the pixels  14 . 
     First pixels RP 22  to RP 66  may be pixels emitting lights of the first color. Second pixels GP 11  to GP 77  may be pixels emitting lights of the second color. The third pixels BP 24  to BP 64  may be pixels emitting lights of the third color. 
     In some embodiments, data voltages corresponding to grayscale voltages may be alternately applied to data lines DL 1 , DL 3 , DL 5 , and DL 7  of a first group and data lines DL 2 , DL 4 , and DL 6  of a second group. 
     For example, data voltages corresponding to the second color may be applied to the data lines DL 1 , DL 3 , DL 5 , and DL 7  of the first group. When a turn-on level scan signal is applied to a scan line SL 1 , the corresponding data voltages are written in pixels GP 11 , GP 13 , GP 15 , and GP 17 . When a turn-on level scan signal is applied to a scan line SL 3 , the corresponding data voltages are written in pixels GP 31 , GP 33 , GP 35 , and GP 37 . When a turn-on level scan signal is applied to a scan line SL 5 , the corresponding data voltages are written in pixels GP 51 , PG 53  GP 55 , and GP 57 . When a turn-on level scan signal is applied to a scan line SL 7 , the corresponding data voltages are written in pixels GP 71 , GP 73 , GP 75 , and GP 77 . 
     In addition, data voltages corresponding to the first color or the third color may be applied to the data lines DL 2 , DL 4 , and DL 6  of the second group. When a turn-on level scan signal is applied to a scan line SL 2 , the corresponding data voltages are written in pixels RP 22 , BP 24 , and RP 26 . When a turn-on level scan signal is applied to a scan line SL 4 , the corresponding data voltages are written in pixels BP 42 , RP 44 , and BP 46 . When a turn-on level scan signal is applied to a scan line SL 6 , the corresponding data voltages are written in pixels RP 62 , BP 64 , and RP 66 . 
       FIG. 10  illustrates a white color light curves WC 1 , WC 2 , . . . , WC(k−1), and WCk of output luminance with respect to input grayscale value. Here, k may be a natural number. 
     Maximum luminance values of the white color light curves WC 1  to WCk may be different from each other. For example, the maximum luminance value (e.g., 4 nits) of the white color light curve WC 1  may be the lowest, and the maximum luminance value (e.g., 1200 nit) of the white color light curve WCk may be the highest. 
     In order to generate a white color light, it is assumed that the pixels  14  of all colors receive data voltages with respect to the same grayscale. 
     Imaginary dots illustrated on the white color light curves WC 1  to WCk of  FIG. 10  may correspond to the above-described select values stored in advance in the select value provider  1511 . When the number of select values increases, more accurate white color light curves can be directly expressed. However, additional physical elements such as multiplexers and registers, which correspond to the increased select values, may be required, and hence a limitation exists. Therefore, select values with respect to the above-described reference grayscale voltages may be stored in advance and used, and other grayscale voltages may be divided and generated. In addition, for the same reason, select values with respect to some maximum luminance values (e.g., reference maximum luminance values) between 4 nit and 1200 nit may be stored in advance and used, and select values with respect to other maximum luminance values may be interpolated and generated. 
     The select values stored in advance may be set for every individual product through multi-time programming (MTP). That is, the select values may be set through repetitive measurement to be stored in a product such that a white color light with a desired luminance with respect to input grayscale values is emitted. 
     That is, the select values stored in advance may be values set based on a white color light. As described above, when a mixed color light or a single color light is emitted using the set grayscale voltages, the luminance of the mixed color light or the single color light does not accurately correspond to a desired gamma curve. The gamma curve may correspond to a white color light curve. 
       FIGS. 11-14  are diagrams illustrating a case where the pixels emit a single color light. 
     Referring to  FIG. 11 , a case where the first pixels RP 22  to RP 66  emit light, and the second pixels GP 11  to GP 77  and the third pixels BP 24  to BP 64  do not emit lights is illustrated. That is, in  FIG. 11 , the pixels  14  emit a single color light of the first color. 
     Emission and non-emission may be distinguished according to an input grayscale value. That is, a pixel provided with an input grayscale value exceeding a reference value may be classified as an emission pixel, and a pixel provided with an input grayscale value equal to or less than the reference value may be classified as a non-emission pixel. For example, the reference value may be set to grayscale level 0. In another embodiment, the reference value may be set to a low grayscale level. 
     In this embodiment, a target pixel and observation target pixels may be defined so as to distinguish a single color, a mixed color, and a white color for each unit area of an image frame. For example, the pixel RP 44  located at the center of a unit area ORA 1  may be a target pixel, and the pixels GP 33 , GP 35 , GP 53 , and GP 55  adjacent to the target pixel RP 44  may be observation target pixels. For example, the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  may be set as pixels most adjacent (i.e., closest or nearest) to the target pixel RP 44 . Whether the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  are most adjacent to the target pixel RP 44  may be determined according to a distance between a center of the target pixel RP 44  and centers of the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55 . 
     When the unit area ORA 1  emits light of one of the first to third colors, the unit area ORA 1  may emit a single color light. In  FIG. 11 , only the target pixel RP 44  emits light in the unit area ORA 1 , and thus the unit area ORA 1  emits a single color light of the first color. 
     When all the pixels GP 33 , GP 35 , RP 44 , GP 53 , and GP 55  included in the unit area ORA 1  emit light, the unit area ORA 1  may emit a white color light. Input grayscale values of the pixels GP 33 , GP 35 , RP 44 , GP 53 , and GP 55  may be the same or be different within an allowable range. 
     When the unit area ORA 1  emits light different from the single color light or the white color light, the unit area ORA 1  may emit a mixed color light. The mixed color light will be described later with reference to  FIGS. 23-25 . 
     When the size of the unit area ORA 1  decreases, less computing resources for distinguishing between a single color, a mixed color, and a white color are used or required. When the size of the unit area ORA 1  increases, the single color, the mixed color, and the white color can be more accurately (e.g., accurately) distinguished. Hereinafter, for convenience of description, a case where the unit area ORA 1  includes five pixels is assumed and described. 
     Referring to  FIG. 12 , a case where the second pixels GP 11  to GP 77  emit light, and the first pixels RP 22  to RP 55  and the third pixels BP 24  to BP 64  do not emit light is illustrated. That is, in  FIG. 12 , the pixels  14  emit a single color light of the second color. 
     A unit area OGA 1  may include a target pixel GP 33  and observation target pixels RP 22 , BP 24 , BP 42 , and RP 44 . In  FIG. 12 , the unit area OGA 1  emits a single color light of the second color. 
     Referring to  FIG. 13 , a case where the third pixels BP 24  to BP 64  emit light, and the second pixels GP 11  to GP 77  and the first pixels RP 22  to RP 66  do not emit light is illustrated. That is, in  FIG. 13 , the pixels  14  emit a single color light of the third color. 
     A unit area OBA 1  may include a target pixel BP 24  and observation target pixels GP 13 , GP 15 , GP 33 , and GP 35 . In  FIG. 13 , the unit area OBA 1  may emit a single color light of the third color. 
     Referring to  FIG. 14 , a white color light curve WC, a first single color light curve RWC, a second single color light curve GWC, and a third single color light curve BWC at an arbitrary maximum luminance value are illustrated. 
     As described above, when a single color light instead of a white color light is emitted using set grayscale voltages, the luminance of the single color light does not accurately correspond to a desired gamma curve. The gamma curve may correspond to the white color light curve WC. In addition, an expression of low-grayscale levels may be unclear because the luminance difference between low grayscale levels may be insufficient. 
     The gamma curve may generally follow the following Equation 1. 
         y=ax   GM   +b   Equation 1
 
     Here, x is a grayscale value, y is a luminance value, a and b are arbitrary constants, and GM is a gamma value. 
     Hereinafter, for convenience of description, the constants a and b are neglected, and shapes of the curves are described using the gamma value GM. When the gamma value corresponds to 1, a straight line is drawn instead of a curve. When the gamma value is greater than 1, the curve protrudes adjacent to (e.g., towards) the x-axis. 
     Therefore, a gamma value of the first single color light curve RWC may be greater than that of the white color light curve WC. In addition, a gamma value of the second single color light curve GWC may be greater than that of the white color light curve WC and be less than that of the first single color light curve RWC. In addition, a gamma value of the third single color light curve BWC may be less than that of the white color light curve WC. For example, the first color may be red, the second color may be green, and the third color may be blue. 
     Therefore, although the same input grayscale value is expressed when a single color light is emitted and when a white color light is emitted, the select values of the select value provider  1511  may be different from each other. However, as described above, when the select values of the select value provider  1511  are directly increased, additional physical elements such as multiplexers may be required, which is not preferable. 
     Thus, in this embodiment, there is used a method of checking whether unit areas emit a single color light, a mixed color light or a white color light, and for correcting an input grayscale value to a converted grayscale value in some cases. When the method is used, it may be unnecessary to modify the existing grayscale voltage generator  15 , and hence products can be easily configured. 
     By using the case of  FIG. 14  as an example, the gamma value of the first single color light curve RWC is adjusted by correcting the input grayscale value. Therefore, the gamma value of the first single color light curve RWC may be adjusted such that the first single color curve RWC is similar to the white color light curve WC. For example, the gamma value of the first single color light curve RWC may be adjusted to decrease. 
     Similarly, the gamma value of the second single color light curve GWC is adjusted by correcting the input grayscale value. Therefore, the gamma value of the second single color light curve GWC may be adjusted such that the second single color curve GWC is similar to the white color light curve WC. For example, the gamma value of the second single color light curve GWC may be adjusted to decrease. A decrement of the gamma value of the second single color light curve GWC may be less than that of the gamma value of the first single color light curve RWC. 
     Similarly, the gamma value of the third single color light curve BWC is adjusted by correcting the input grayscale value. Therefore, the gamma value of the third single color light curve BWC may be adjusted such that the third single color curve BWC is similar to the white color light curve WC. For example, the gamma value of the third single color light curve BWC may be adjusted to increase. 
     According to the above-described embodiments, luminances of single color lights can be more accurately (e.g., accurately) expressed according to a desired gamma curve. Further, low-grayscale expression may be clearer. 
       FIG. 15  is a diagram illustrating a grayscale corrector according to an embodiment of the present disclosure. 
     Referring to  FIG. 15 , in some embodiments, the grayscale corrector  16  may selectively include a light emitting pixel counter  164 , a grayscale converter  165 , single color offset providers  1611 ,  1621 , and  1631 , and mixed color offset providers  1612 ,  1622 , and  1632 . 
     The grayscale corrector  16  may convert an input grayscale value provided corresponding to a target pixel with reference to observation target grayscale values provided corresponding to observation target pixels. For example, the grayscale corrector  16  may provide converted grayscale values PX 1 G′, PX 2 G′, . . . by converting input grayscale values PX 1 G, PX 2 G, . . . provided corresponding to the pixels  14 . Hereinafter, each of the input grayscale values PX 1 G, PX 2 G, . . . is expressed as an input grayscale value when it is referred to as a grayscale value of a target pixel, and is expressed as an observation target grayscale value when it is referred to as a grayscale value of an observation target pixel. 
     The light emitting pixel counter  164  may provide a number of light emitting pixels by counting a number of observation target grayscale values that exceed a reference value. For example, the light emitting pixel counter  164  may provide numbers PX 1 N, PX 2 N, . . . of light emitting pixels in a unit area in which each of the pixels  14  is used as a target pixel, using the input grayscale values PX 1 G, PX 2 G, . . . . 
     For example, referring to  FIG. 11 , the observation target grayscale values of the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  in the unit area ORA 1  may be grayscale levels that are equal to or less than grayscale level 0 or the reference value. Accordingly, the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  may all be determined that they are in a non-emission state. Therefore, the light emitting pixel counter  165  may determine the number of light emitting pixels with respect to the target pixel RP 44  as  0 . 
     Referring to  FIG. 23  in advance, the observation target grayscale value of the observation target pixel GP 33  in the unit area ORA 1  may exceed the reference value. In addition, the observation target grayscale values of the observation target pixels GP 35 , GP 53 , and GP 55  may be grayscale levels that are equal to or less than the grayscale level 0 or the reference value. Accordingly, the observation target pixel GP 33  may be determined that it is in an emission state, and the observation target pixels GP 35 , GP 53 , and GP 55  may be determined that they are in the non-emission state. Therefore, the light emitting pixel counter  164  may determine the number of light emitting pixels with respect to the target pixel RP 44  as  1 . 
     Referring to  FIG. 24  in advance, the observation target grayscale values of the observation target pixels GP 33  and GP 35  in the unit area ORA 1  may exceed the reference value. In addition, the observation target grayscale values of the observation target pixels GP 53  and GP 55  may be grayscale levels that are equal to or less than the grayscale level 0 or the reference value. Accordingly, the observation target pixels GP 33  and GP 35  may be determined that they are in the emission state, and the observation target pixels GP 53  and GP 55  may be determined that they are in the non-emission state. Therefore, the light emitting pixel counter  164  may determine the number of light emitting pixels with respect to the target pixel RP 44  as 2. 
     Referring to  FIG. 25  in advance, the observation target grayscale values of the observation target pixels GP 33 , GP 35 , and GP 53  in the unit area ORA 1  may exceed the reference value. In addition, the observation target grayscale value of the observation target pixel GP 55  may be a grayscale level that is equal to or less than the grayscale level 0 or the reference value. Accordingly, the observation target pixels GP 33 , GP 35 , and GP 53  may be determined that they are in the emission state, and the observation target pixel GP 55  may be determined that it is in the non-emission state. Therefore, the light emitting pixel counter  164  may determine the number of light emitting pixels with respect to the target pixel RP 44  as 3. 
     Referring to  FIG. 9 , the observation target grayscale values of the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  in the unit area ORA 1  may exceed the reference value. Accordingly, the observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  may be determined that they are in the emission state. Therefore, the light emitting pixel counter  164  may determine the number of light emitting pixels with respect to the target pixel RP 44  as 4. 
     The target pixels GP 33  and BP 24  and the unit areas OGA 1  and OBA 1  of  FIGS. 12 and 13  may be similarly described, and therefore, overlapping descriptions may be omitted. 
     The grayscale converter  165  may provide a converted grayscale value by converting an input grayscale value, based on the number of light emitting pixels. For example, the grayscale converter  165  may generate the converted grayscale values PX 1 G′, PX 2 G′, . . . by adding, to the input grayscale values PX 1 G, PX 2 G, . . . , a corresponding offset value from among single color offset values RSO 0  to RSO 255 , GSO 0  to GSO 255 , and BSO 0  to BSO 255  and mixed color offset values RMOa 0  to RMOa 255 , RMOb 0  to RMOb 255 , RMOc 0  to RMOc 255 , GMOa 0  to GMOa 255 , GMOb 0  to GMOb 255 , GMOc 0  to GMOc 255 , BMOa 0  to BMOa 255 , BMOb 0  to BMOb 255 , and BMOc 0  to BMOc 255 , based on the numbers PX 1 N, PX 2 N, . . . of light emitting pixels with respect to the target pixels. 
     The first single color offset provider  1611  may provide first single color offset values RSO 0  to RSO 255 . The first single color offset values RSO 0  to RSO 255  may be single color offset values with respect to the first color, and be changed depending on the input maximum luminance value DBVI. 
     The second single color offset provider  1621  may provide second single color offset values GSO 0  to GSO 255 . The second single color offset values GSO 0  to GSO 255  may be single color offset values with respect to the second color, and be changed depending on the input maximum luminance value DBVI. 
     The third single color offset provider  1631  may provide third single color offset values BSO 0  to BSO 255 . The third single color offset values BSO 0  to BSO 255  may be single color offset values with respect to the third color, and be changed depending on the input maximum luminance value DBVI. 
     When the number of light emitting pixels is 0, the grayscale converter  165  may generate a converted grayscale value by adding a corresponding offset value from among the single color offset values RSO 0  to RSO 255 , GSO 0  to GSO 255 , and BSO 0  to BSO 255  to the input grayscale value. 
     For example, in  FIG. 11 , the number of light emitting pixels with respect to the target pixel RP 44  is 0, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel RP 44  by adding a corresponding offset value from among the first single color offset values RSO 0  to RSO 255  to the input grayscale value of the target pixel RP 44 . 
     For example, in  FIG. 12 , the number of light emitting pixels with respect to the target pixel GP 33  is 0, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel GP 33  by adding a corresponding offset value from among the second single color offset values GSO 0  to GSO 255  to the input grayscale value of the target pixel GP 33 . 
     For example, in  FIG. 13 , the number of light emitting pixels with respect to the target pixel BP 24  is 0, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel BP 24  by adding a corresponding offset value from among the second single color offset values BSO 0  to BSO 255  to the input grayscale value of the target pixel BP 24 . 
     Returning now to  FIG. 15 , the first mixed color offset provider  1612  may provide first mixed color offset values RMOa 0  to RMOa 255 , RMOb 0  to RMOb 255 , and RMOc 0  to RMOc 255 . The first mixed color offset values RMOa 0  to RMOc 255  may be mixed color offset values with respect to the first color. 
     The second mixed color offset provider  1622  may provide second mixed color offset values GMOa 0  to GMOa 255 , GMOb 0  to GMOb 255 , and GMOc 0  to GMOc 255 . The second mixed color offset values GMOa 0  to GMOc 255  may be mixed color offset values with respect to the second color. 
     The third mixed color offset provider  1632  may provide third mixed color offset values BMOa 0  to BMOa 255 , BMOb 0  to BMOb 255 , and BMOc 0  to BMOc 255 . The third mixed color offset values BMOa 0  to BMOc 255  may be mixed color offset values with respect to the third color. 
     When the number of light emitting pixels is greater than 0 and is less than the number of observation target pixels, the grayscale converter  165  may generate a converted grayscale value by adding a corresponding offset value from among the mixed color offset values RMOa 0  to BMOc 255  to the input grayscale value. 
     For example, in  FIG. 23 , the number of light emitting pixels with respect to the target pixel RP 44  is 1, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel RP 44  by adding a corresponding offset value from among the first mixed color offset values RMOa 0  to RMOa 255  to the input grayscale value of the target pixel RP 44 . 
     For example, in  FIG. 24 , the number of light emitting pixels with respect to the target pixel RP 44  is 2, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel RP 44  by adding a corresponding offset value from among the first mixed color offset values RMOb 0  to RMOb 255  to the input grayscale value of the target pixel RP 44 . 
     For example, in  FIG. 25 , the number of light emitting pixels with respect to the target pixel RP 44  is 3, and hence the grayscale converter  165  may generate a converted grayscale value with respect to the target pixel RP 44  by adding a corresponding offset value from among the first mixed color offset values RMOc 0  to RMOc 255  to the input grayscale value of the target pixel RP 44 . 
     The aforementioned description may be substantially identically applied even when the grayscale converter  165  uses the second and third mixed color offset values GMOa 0  to BMOc 255 , and therefore, overlapping descriptions may be omitted. 
     When the number of light emitting pixels is equal to the number of observation target pixels, the grayscale converter  165  may determine an input grayscale value as the converted grayscale value. 
     For example, referring to  FIG. 9 , the number of observation target pixels GP 33 , GP 35 , GP 53 , and GP 55  with respect to the target pixel RP 44  is 4, and the number of light emitting pixels is also 4. Hence, an offset value may not be added to the input grayscale value of the target pixel RP 44 . In other words, an offset value 0 may be added to the input grayscale value of the target pixel RP 44 . That is, the input grayscale value of the target pixel RP 44  and the converted grayscale value may be equal to each other. 
     Substantially identical description may be applied to the target pixels of the second color and the second color, and therefore, overlapping descriptions may be omitted. 
       FIGS. 16-18  are diagrams illustrating the single color offset provider of  FIG. 15 . 
     In some embodiments, the first single color offset provider  1611  may include a first reference offset provider  16111  and a first total offset provider  16112 . Substantially identical description may be applied to the second and third single color offset providers  1621  and  1631 , and therefore, overlapping descriptions may be omitted. 
     The first reference offset provider  16111  may receive the input maximum luminance value DBVI, and provide first reference offset values RRO 1 , RRO 2 , RRO 3 , RRO 4 , RRO 5 , RRO 6 , RRO 7 , RRO 8 , and RRO 9  corresponding to the input maximum luminance value DBVI. 
     When the number of light emitting pixels is equal to the number of observation target pixels, a converted grayscale value equal to the input grayscale value may be output by the grayscale converter  165  as described above. The relationship of converted grayscale values with respect to input grayscale values may follow a white color grayscale line RWL. 
     When the number of light emitting pixels is 0, a converted grayscale value different from the input grayscale value may be output by the grayscale converter  165  as described above. That is, the converted grayscale value may be generated by adding a corresponding offset value corresponding to the first single color offset values RSO 0  to RSO 255  to the input grayscale value. The relationship of converted grayscale values with respect to input grayscale values may follow a first single color grayscale line RSL. 
     For example, when the input grayscale value is 1, a first single color offset value RSO 1  that is 0 may be added such that the converted grayscale value becomes 1. Also, when the input grayscale value is 7, a first single color offset value RSO 7  that is 17 is added such that the converted grayscale value becomes 24. Also, when the input grayscale value is 11, a first single color offset value RS 011  that is 53 is added such that the converted grayscale value becomes 64. Also, when the input grayscale value is 23, a first single color offset value RS 023  that is 47 is added such that the converted grayscale value becomes 70. Also, when the input grayscale value is 35, a first single color offset value RS 035  that is 40 is added such that the converted grayscale value becomes 76. Also, when the input grayscale value is 51, a first single color offset value RS 051  that is 32 is added such that the converted grayscale value becomes 83. Also, when the input grayscale value is 87, a first single color offset value RS 087  that is 20 is added such that the converted grayscale value becomes 107. Also, when the input grayscale value is 151, a first single color offset value RS 0151  that is 5 is added such that the converted grayscale value becomes 156. Also, when the input grayscale value is 203, a first single color offset value RS 0203  that is 3 is added such that the converted grayscale value becomes 206. When the input grayscale value is 255, the converted grayscale value may be 255. When the input grayscale value is 0, the converted grayscale value may be 0. 
     The first single color offset values RSO 1 , RSO 7 , RS 011 , RS 023 , RS 035 , RS 051 , RS 087 , RS 0151 , and RS 0203  may correspond to the first reference offset values RRO 1 , RRO 2 , RRO 3 , RRO 4 , RRO 5 , RRO 6 , RRO 7 , RRO 8 , and RRO 9 . 
     The first total offset generator  16112  may generate first single color offset values RSO 0  to RSO 255  by interpolating the first reference offset values RRO 1  to RRO 9 . The existing methods such as linear interpolation, polynomial interpolation, and exponential interpolation may be used as the interpolation method. Hereinafter, description of the interpolation method will be omitted. 
     For example, referring to  FIG. 18 , the first total offset generator  16112  may generate a first single color offset value RSO 8  corresponding to the grayscale value 8, a first single color offset value RSO 9  corresponding to the grayscale value 9, and a first single color offset value RS 010  corresponding to the grayscale value 10 by interpolating a first reference offset value RRO 2  corresponding to the grayscale  7  and a first reference offset value RRO 3  corresponding to the grayscale value 11. 
     Thus, according to this embodiment, it is unnecessary to store all the first offset values RSO 0  to RSO 255  in advance, so that cost for a memory device can be reduced. 
       FIG. 19  is a diagram illustrating a configuration of an exemplary offset value. 
     Referring to  FIG. 19 , the offset value RSO may include a sign bit SBT, an offset integer bit OIBT, and an offset decimal bit ODBT. 
     The sign bit SBT may express whether the offset value RSO is a positive number or a negative number. For example, referring to  FIG. 14 , it is necessary to decrease gamma values of the first single color light curve RWC and the second single color light curve GWC, and therefore, the offset value RSO may be a positive number. However, it is necessary to increase a gamma value of the third single color light curve BWC, and therefore, the offset value RSO may be a negative number. For example, the offset value RSO may be a positive number when the sign bit SBT is 0, and be a negative number when the sign bit SBT is 1. On the contrary, the offset value RSO may be a positive number when the sign bit SBT is 1, and be a negative number when the sign bit SBT is 0. 
     In the case of  FIG. 18 , the interpolated converted grayscale values 24, 44, 54, and 64 may be expressed with only integers. However, in some cases, the interpolated converted grayscale values may be expressed with integers and decimals (e.g., real numbers). For example, referring to  FIG. 17 , 63 input grayscale values corresponding to between 87 and 151 may be corrected to converted grayscale values between 107 and 156. Because the number of integers between 107 and 156 is 48, it is necessary to express a minimal of 15 converted grayscale values with integers and decimals. Therefore, the offset value RSO requires the offset integer bit OIBT and the offset decimal bit ODBT. 
     When the offset value RSO has a decimal value, the corrected converted grayscale value cannot express a corresponding luminance with only one of the grayscale voltages RV 0  to RV 255  (see  FIG. 8 ). The display device  10  can express a luminance corresponding to a converted grayscale value having a decimal value by spatially dithering a target pixel and adjacent pixels. 
       FIG. 20  is a diagram illustrating an effect obtained by applying a single offset value. 
     A first single color light curve RWC represents luminance in a case where the pixels  14  emit light of a first single color due to input grayscale values that are not corrected. 
     A first single color light correction curve RSC represents luminance in a case where the pixels  14  emit light of the first single color due to corrected input grayscale values, i.e., converted grayscale values. 
     For example, the display device  10  according to the embodiment of the present disclosure may include a first pixel emitting light of a first color, a second pixel emitting light of a second color different from the first color, a third pixel emitting light of a third color different from the first color and the second color, and a grayscale corrector  16  for converting input grayscale values provided corresponding to the first to third pixels into converted grayscale values. The first to third pixels may emit light, based on the converted grayscale values. 
     A first luminance of the first pixel in a first case where the first pixel, the second pixel, and the third pixel emit lights may be different from a second luminance of the first pixel in a second case where only the first pixel emits light and the second and third pixels do not emit lights. 
     An input grayscale value provided corresponding to the first pixel in the first case may be equal to that provided corresponding to the first pixel in the second case, and a converted grayscale value corresponding to the first luminance may be different from that corresponding to the second luminance. 
     That is, as for the same input grayscale values, the first luminance in the first case may follow the first single color light curve RWC, and the second luminance in the second case may follow the first single color light correction curve RSC. 
     A gamma value of the first single color light correction curve RSC may be less than that of the first single color light curve RWC. Accordingly, the luminance of first single color light can be accurately expressed according to a desired gamma curve. Further, low-grayscale expression can be clearer. 
     A substantially identical embodiment may be applied to a second single color light and a third single color light, and therefore, overlapping description may be omitted. 
       FIGS. 21-22  are diagrams illustrating the reference offset provider of  FIG. 16 . 
     In some embodiments, the first reference offset provider  16111  may include a first preset determiner  161111  and a first reference offset generator  161112 . 
     The first preset determiner  161111  may store, in advance, first preset offset values corresponding to preset maximum luminance values, and determine whether an input maximum luminance value DBVI corresponds to any one of the preset maximum luminance values. 
     For example, the preset maximum luminance values may include a maximum value (e.g., 1200 nit) and a minimum value (e.g., 4 nit) of a receivable input maximum luminance value DBVI. 
     Also, the preset maximum luminance values may further include a first intermediate maximum luminance value (e.g., 100 nit). When the input maximum luminance value is a value between the maximum value and the first intermediate maximum luminance value, a grayscale voltage corresponding to a converted grayscale value is adjusted corresponding to the input maximum luminance value DBVI, so that the luminance of a target pixel may be controlled. For example, the luminance of the target pixel in a section between 1200 nit and 100 nit may rely on a grayscale voltage control method. In addition, when the input maximum luminance value DBVI is a value between the minimum value and the first intermediate maximum luminance value, the emission period of the target pixel is adjusted corresponding to the input maximum luminance value DBVI, so that the luminance of the target pixel can be controlled. For example, the luminance of the target pixel in a section between 100 nit and 4 nit may rely on a duty ratio control method. 
     Also, the preset maximum luminance values may further include a second intermediate maximum luminance value (e.g., 30 nit) that is a value between the first intermediate maximum luminance value and the minimum value. 
     The above-described four preset maximum luminance values (i.e., 1200 nit, 100 nit, 30 nit, and 4 nit) are merely illustrative, and other preset maximum luminance values may be set depending on products. 
     When the input maximum luminance value DBVI corresponds to any one of the preset maximum luminance values, the first preset determiner  161111  may provide corresponding first preset offset values DBVP 1  as the first reference offset values RRO 1  to RRO 9 . For example, first preset offset values DBVP 1  with respect to each of the 1200 nit, the 100 nit, the 30 nit, and the 4 nit may be stored in advance. Therefore, when the input maximum luminance value DBVI corresponds to one of the 1200 nit, the 100 nit, the 30 nit, and the 4 nit, the first reference offset values RRO 1  to RRO 9  may be provided without passing through the first reference offset generator  161112 . 
     When the input maximum luminance value DBVI does not correspond to any one of the preset maximum luminance values, the first preset determiner  161111  may provide first preset offset values corresponding to at least two preset maximum luminance values. 
     For example, when the input maximum luminance value DBVI is 17 nit, the first preset determiner  161111  may provide first preset offset values DBVP 1  corresponding to the 4 nit and first preset offset values DBVP 2  corresponding to the 30 nit. 
     The first reference offset provider  161112  may generate the first reference offset values RRO 1  to RRO 9  by interpolating first preset offset values DBVP 1  and DBVP 2  corresponding to at least two preset maximum luminance values. 
     Referring to  FIG. 22 , a process of determining magnitudes of first reference offset values DBVG corresponding to 17 nit by interpolating first preset offset values DBVP 1  corresponding to the 4 nit and first preset offset values DBVP 2  corresponding to the 30 nit is expressed using a graph. 
     Thus, according to this embodiment, it is unnecessary to store offset values in advance with respect to all receivable input maximum luminance values DBVI, so that cost of a memory device, etc. can be reduced. 
       FIGS. 23-27  are diagrams illustrating the mixed color offset provider of  FIG. 15 . 
     Hereinafter, the first mixed color offset provider  1612  with respect to the first color is described as an example, and descriptions overlapping with those of the second mixed color offset provider  1622  and the third mixed color offset provider  1632  to which substantially identical contents may be applied may be omitted. 
     As described above,  FIG. 23  illustrates a case where the number of light emitting pixels in the unit area ORA 1  is 1. The grayscale converter  165  may use first mixed color offset values RMOa 0  to RMOa 255  corresponding to a first mixed color grayscale line RMLa. 
     In addition,  FIG. 24  illustrates a case where the number of light emitting pixels in the unit area ORA 1  is 2. The grayscale converter  165  may use first mixed color offset values RMOb 0  to RMOb 255  corresponding to a first mixed color grayscale line RMLb. 
     In addition,  FIG. 25  illustrates a case where the number of light emitting pixels in the unit area ORA 1  is 3. The grayscale converter  165  may use first mixed color offset values RMOc 0  to RMOc 255  corresponding to a first mixed color grayscale line RMLc. 
     The first mixed color offset provider  1612  may generate the first mixed color offset values RMOa 0  to RMOc 255  by interpolating the first single color offset values RSO 0  to RSO 255  provided thereto. In another embodiment, the first mixed color offset provider  1612  may autonomously generate the first mixed color offset values RMOa 0  to RMOc 255  or store the first mixed color offset values RMOa 0  to RMOc 255  in advance, independently from the first single color offset provider  1611 . 
     Referring to  FIG. 27 , there are illustrated a first mixed color light curve RMCa corresponding to the first mixed color grayscale line RMLa, a second mixed color light curve RMCb corresponding to the first mixed color grayscale line RMLb, and a third mixed color light curve RMCc corresponding to the first mixed color grayscale line RMLc. 
     Therefore, the first mixed color light curve may be similar to the first single color light correction curve RSC when the number of light emitting pixels decreases, and be similar to the first single color light curve RWC when the number of light emitting pixels increases. 
       FIGS. 28-31  are diagrams illustrating a tuning process performed by considering a mixed color light. 
     In this embodiment, a case where the first color is red, the second color is green, and the third color is blue is assumed. The red, green, and blue may be expressed as primary colors. Magenta corresponding to a secondary color may be expressed with a combination of red and blue. Cyan corresponding to a secondary color may be expressed with a combination of green and blue. Yellow corresponding to a secondary color may be expressed with a combination of red and green. 
     Referring to  FIG. 28 , because the red pixels RP 22  to RP 66  and the blue pixels BP 24  to BP 64  are in the emission state, and the green pixels GP 11  to GP 77  are in the non-emission state, the pixels  14  display an image frame of a magenta color. In  FIGS. 28-31 , magenta is described as an example. A similar tuning method may be applied to cyan and yellow, and therefore, overlapping descriptions may be omitted. 
     According to the above-described embodiments, because the number of light emitting pixels in the unit area ORA 1  is 0, one of the first single color light offset values RSO 0  to RSO 255  may be applied to a target pixel RP 44 . In addition, because the number of light emitting pixels in the unit area OBA 1  is 0, one of the third single color light offset values BSO 0  to BSO 255  may be applied to a target pixel BP 24 . 
     Therefore, referring to  FIGS. 29 and 30 , the first single color light curve RWC may be corrected to a first single color light correction curve RSC of which gamma value is substantially equal to that of the white color light curve WC, and the third single color light curve BWC may be corrected to a third single color light correction curve BSC of which gamma value is substantially equal to that of the white color light curve WC. However, due to this, a magenta color light curve MGTC may be unintentionally over-corrected to a curve MGTC′. 
     Therefore, according to this embodiment, gamma values of a first single color light correction curve RSC′ and a third single color light correction curve BSC′ are corrected greater than the gamma value of the white color light curve WC, so that a magenta color light correction curve MGTC″ of which gamma value is more similar than that of the white color light curve WC may be generated. For example, as can be seen in  FIG. 31 , when each of the gamma values of the first single color light correction curve RSC′ and the third single color light correction curve BSC′ is adjusted to 2.4, the magenta color light correction curve MGTC″ having a gamma value of 2.1 may be generated. 
     Thus, the first to third single color offset values RSO 0  to RSO 255 , GSO 0  to GSO 255 , and BSO 0  to BSO 255  can be adjusted suitable for a color sensitive to eyes of a user according to products. 
       FIGS. 32-34  are diagrams illustrating a case where the range of observation target pixels is differently set. 
     In the embodiments described so far, a case where the number of observation target pixels is 4 in each of the unit areas ORA 1 , OGA 1 , and OBA 1  has been described. 
     However, in this embodiment, it shows that the number of observation target pixels may be 8 by applying expanded unit areas ORA 2 , OGA 2 , and OBA 2 . Similarly, the unit areas may be set such that the number of observation target pixels exceeds 8. 
     In this embodiment, single color offset providers  1611 ,  1621 , and  1631  and mixed color offset providers  1612 ,  1622 , and  1632  may be configured substantially identical to those described in  FIG. 15 , and therefore, overlapping descriptions may be omitted. 
     As for a unit area ORA 2  with respect to the first color and the unit area OBA 2  with respect to the third color, a light emitting pixel counter  164  and a grayscale converter  165  may be configured substantially identical to those of  FIG. 15 , and therefore, overlapping descriptions may be omitted. 
     However, referring to a unit area OGA 2  with respect to the second color, when the unit area OGA 2  emits a second single color light, observation target pixels GP 13 , GP 31 , GP 35 , and GP 53  of the second color are also in the emission state, and hence the light emitting pixel counter  164  and the grayscale converter  165  may be differently configured. 
     For example, when the number of light emitting pixels corresponding to the first color and the third color is 0, the grayscale converter  165  may generate a converted grayscale value by adding a corresponding offset value from among the second single color offset values GSO 0  to GSO 255  to an input grayscale value. 
     That is, in this embodiment, the light emitting pixel counter  164  may distinguish and count colors (e.g., the first color and the third color) different from at least the second color. In addition, the grayscale converter  165  may apply offset values, using the number of light emitting pixels, which is distinguished and counted for each color. 
     When the number of light emitting pixels corresponding to the first color and the third color is not 0 and is less than the number of observation target pixels corresponding to the first color and the second color, the grayscale converter  165  may generate a converted grayscale value by adding a corresponding offset value from among the second mixed color offset values GMOa 0  to GMOa 255 , GMOb 0  to GMOb 255 , and GMOc 0  to GMOc 255  to the input grayscale value. 
     When the number of light emitting pixels corresponding to the first color and the second color is equal to the number of observation target pixels corresponding to the first color and the second color, the grayscale converter  156  may determine the input grayscale value as the converted grayscale value. 
     Therefore, according to this embodiment, the number of observation target pixels may become 8 by applying the expanded unit areas ORA 2 , OGA 2 , and OBA 2 . Similarly, the unit areas may be set such that the number of observation target pixels exceeds 8. 
     According to the present disclosure, the display device can exhibit a desired luminance not only when a white color light is radiated but also when a single color light or a mixed color light is radiated. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims and their equivalents.