Patent Publication Number: US-2009236317-A1

Title: Anti-reflection etching of silicon surfaces catalyzed with ionic metal solutions

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The application is related to co-pending U.S. patent application Ser. No. 12/053,372, entitled “Nanoparticle-Based Etching of Silicon Surfaces,” identified by Docket No. NREL 07-10, which is incorporated herein by reference in its entirety. 
    
    
     CONTRACTUAL ORIGIN 
     The United States Government has rights in this invention under Contract No. DE-AC36-99GO10337 between the United States Department of Energy and the National Renewable Energy Laboratory, a Division of the Midwest Research Institute. 
    
    
     BACKGROUND 
     Despite numerous attempts at making better solar cells with new and exotic materials, the photovoltaics market is still dominated by early or first generation solar cells that are typically silicon wafer-based solar cells. Most solar cell manufacturers are equipped to produce silicon wafer-based solar cells, and research continues to design silicon-based solar cells that can achieve higher conversion efficiencies without an exorbitant increase in production costs, e.g., the aim of research often is to achieve the lowest cost per watt solar cell design that is suitable for commercial production. In addition to use in solar cells, silicon wafers, other silicon layers on substrates, and objects having silicon surfaces are used in numerous other applications such as in electronic devices, telecommunication devices, computers, and even in biological or medical applications, and these applications have also driven research to methods of fabricating silicon wafers and silicon surfaces with particular qualities or characteristics such as a rough, textured, or nanostructured surface. 
     The performance of solar cells and other optoelectronic devices is directly related to optical losses caused by high reflectivity. Flat silicon surfaces such as those found on an untreated silicon wafer have a high natural reflectivity across the entire range of the solar spectrum that could otherwise be converted to electrical energy by the silicon photovoltaic device. To produce high efficiency solar cells, researchers have sought ways to minimize reflection losses. One common approach has been to provide anti-reflection coatings (ARCs) that typically are selected based on interference. For example, quarter wavelength transparent layers of materials such as SiO x , TiO x , ZnO, ITO, or Si 3 N 4  are used as ARCs on silicon surfaces. In some cases, ARCs from oxidized silicon may be formed by electrochemical etching. All such ARC coatings are resonant structures and perform well only in a limited spectral range and for specific angles of incidence while the solar spectrum spans a wide range of wavelengths and the incident angle varies during the day. The typical results achieved with simple one-layer ARCs have been a reduction of the surface reflection to about 8 to 15 percent. With more difficult two-layer ARC coatings, the reflectivity can be reduced to about 4 percent, but this kind of coating is expensive to apply and is not effective when placed under glass in photovoltaic modules. 
     Researchers have shown that efficient suppression of reflection in a broad spectral range can be achieved by deep surface texturing. In this regard, etching can be used on a smooth or polished silicon surface to produce rough surfaces with bumps and pits having typical sizes of several or even ten micrometers, and these rough surfaces exhibit reduced reflectivity due to its reflection and absorption characteristics. In one example, anisotropic etching of silicon in KOH/C 2 H 5 OH mixtures produces densely packed pyramids that appear black. However, such etching has been typically limited to single crystalline silicon with &lt;(1,0,0,&gt;) surface orientation, and solar cell design is made more complex by the large penetration pyramids. This texturing also has reflectivity that increases rapidly with the angle of light incidence. 
     More recently, researchers determined that a fine surface texturing on the nanometer scale may be utilized to control reflectivity of silicon surfaces. Specifically, a textured surface with features smaller than the wavelength of light is an effective medium for controlling reflectivity, and testing with regard to solar cell applications has shown that a fine texture that is only about 300 to 500 nanometers in depth and provides a gradual grading of the silicon density and of the index of refraction from the surface to the bulk that is adequate to suppress reflectivity of a silicon surface in the usable spectral range of photon energies above the band gap. Such a textured surface may be thought of a subwavelength structured surface that behaves itself as an anti-reflective surface, with the gradually tapered density of the anti-reflective surface suppressing reflection over a wide spectral bandwidth and over a large incidence angle of the incoming light. One group of researchers has developed a method of nanoscale texturing of silicon surfaces that utilizes wet chemical etching to reduce optical losses due to surface reflection to below 5 percent at all solar wavelengths for crystalline silicon. 
     Briefly, the texturing of the silicon surfaces involves black etching in a three step process. First, a discontinuous gold (Au) layer with a thickness of about 1 to 2 nanometers is deposited by thermal evaporation or other deposition techniques. This initial metal coating is made up of Au clusters or islands that in later steps provide a catalytic action or function. Second, a wet chemical etching of the silicon material is performed using all aqueous solution of hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ). This solution etches clean or non-coated portions of the silicon surface very slowly but near or about the periphery of the Au islands a texture with a depth of up to 500 nanometers forms very quickly, such as at an etch rate of about 330 nanometers per minute (which indicated that catalytic action to these researchers of the Au clusters or islands). Third, since gold is a detrimental impurity in silicon surfaces, the remaining gold is removed from the textured silicon surface such as by room temperature etching in an aqueous solution of iodine and potassium iodide. The researchers indicated that this multi-step process including deposition of a metallic or catalytic layer may be performed on different silicon surfaces including morphologies such as crystalline, multicrystalline, and amorphous as well as differing doping such as n-type, p-type, and intrinsic doping. The amount of absorbed light was increased with this black etch treatment and results showed reflectivity of as little as 2 to 5 percent in the high light absorption ranges of the silicon samples. 
     While such etching processes produce highly non-reflective or “black” silicon surface, there are a number of drawbacks that may hinder wide adoption of such processes. The deposition of gold may be cost prohibitive (e.g., undesirably increase the production cost or price of solar cells or other optoelectronic devices). The costs include material costs associated with deposition of the thin layers of pure gold and also include high capital equipment costs associated with purchase, operation, and maintenance of vacuum deposition and other equipment used in the metallic deposition steps of the process. The process also requires two or more steps to provide the etching or texturing, which increases manufacturing complexity and fabrication times. Hence, there is an unmet demand for inexpensive, less complex (e.g., processes with fewer steps and less equipment), and efficient techniques for providing etching silicon surfaces including ways to facilitate black etching of silicon wafers. 
     The foregoing examples of the related art and limitations related therewith are intended to be illustrative and not exclusive. Other limitations of the related art will become apparent to those of skill in the art upon a reading of the specification and a study of the drawings. 
     SUMMARY 
     The following embodiments and aspects thereof are described and illustrated in conjunction with systems, tools and methods that are meant to be exemplary and illustrative, not limiting in scope. In various embodiments, one or more of the above-described problems have been reduced or eliminated, while other embodiments are directed to other improvements. 
     Prior silicon etching research has shown techniques for producing highly non-reflective or “black” silicon surfaces, but these techniques have generally called for evaporating or depositing a thin layer of expensive metals or islands of such metals, such as a 1 to 3 nanometer (nm) layer of gold, upon the silicon surfaces. Then, etching would be performed in a separate step such as by placing the coated silicon surface in an aqueous solution of hydrofluoric acid (HF) and hydrogen peroxide (H 2 O 2 ) to texture the surface to make a density gradient at the surface with length scales that are less than the wavelength of light. Other techniques have involved providing nanoparticles of catalytic metals such as gold or silver as a coating layer or in a suspension that is added to the etching solution along with the HF and H 2 O 2 . Such techniques have helped eliminate complex deposition steps but still may still be too costly as they specify the use of evaporated gold or other relatively expensive metal nanoparticles as a catalyst for the etching process. 
     An embodiment of the etching process described represents a unique process as it eliminates the need for deposition of gold or other metals on a silicon surface and the use of gold or other catalytic metal nanoparticles while still providing a black etching process that is extremely effective in achieving reduced reflectance, is less expensive to implement and perform, and, in some cases, is more controllable. More particularly, the etching process provides molecular or ionic species containing a catalytic metal, such as gold, silver, a transition metal, or the like, in the etching solution along with oxidant-etchant solution components such as an etching agent and an oxidizing agent. The catalytic metal molecule or ion acts to catalyze the reaction cause in part by the oxidant-etchant solution (e.g., HF and H 2 O 2 ), and the resulting etching is very uniform and produces a rapid formation of a non-reflective or black surface layer on the silicon surface. During the etching, stirring or agitation is also performed to facilitate the texturing, e.g., ultrasonic agitation or sonication is used to stir the etching solution. 
     In one exemplary, but not limiting, implementation of an etching process, catalytic quantities (e.g., between about 70 and 400 μM) of chorauric acid (HAuCl 4 ) in aqueous solution are mixed, such as 1:1 or in other useful ratios, with a oxidant-etchant solution (e.g., 5 to 10% of an etching agent such as HF and 15 to 30% of an oxidizing agent such as H 2 O 2 , with one experiment using about 6% HF and 18% to 2 7 % H 2 O 2 ). The chorauric acid in this implementation is the source of the catalytic metal molecule or ionic species or the ionic metal solution (or, more simply, the “catalytic solution”). A silicon wafer or a substrate with a silicon surface is placed in the etching solution containing the ionic metal solution and the oxidant-etchant solution, and the etching solution is agitated or stirred for an etch period (e.g., up to about 4 minutes or more using ultrasonic agitation, such as 125 W in a total solution of 10 ml for a 1 square inch wafer). The result of such etching is a textured surface with extremely low reflectivity across the broad spectrum of wavelengths useful for solar energy applications. The silicon etching may be used on a variety of surface types such as &lt;(1,0,0&gt;), &lt;(1,1,1&gt;), &lt;(3,1,1&gt;), and other surfaces of silicon, and on multi-crystalline wafers with grains that may expose silicon surfaces to the etching solution. Post etching treatment may be performed with a stripping solution (e.g., I 2 /KI or the like) to remove residual catalytic metals such as gold from the surface, and this typically has not detrimentally affected reflectivity. 
     In one exemplary, but not limiting, embodiment, a method is provided for texturing a silicon surface. The method includes positioning a substrate, such as a silicon wafer, with a silicon surface into a vessel. The vessel is filled with a volume of an etching solution to cover the silicon surface. The etching solution includes a catalytic solution and a oxidant-etchant solution, e.g., an aqueous solution of HF and H 2 O 2 . The catalytic solution may generally be any solution that provides a source of metal-containing molecules or ionic species of catalytic metals (such as a transition metal or the like). The method continues with etching the silicon surface by agitating the etching solution in the vessel such as with ultrasonic agitation for a relatively short time period such as less than about 4 minutes with 30 to 90 seconds being adequate to achieve a desired surface roughening in some cases. During the etching step, the catalytic solution in the presence of the oxidant-etchant solution provides or releases a plurality of metal particles. In some cases, the catalytic solution is a dilute solution of  HAuCl4  and the metal particles are gold particles and/or nanoparticles. In other cases, the catalytic solution comprises a dilute solution of AgF and the metal particles are silver particles and/or nanoparticles. In other cases, the molecules or ionic species may effect the catalysis directly. In other cases, the metal particles are transition metal particles, and, in some applications, the etching is performed until the etched silicon surface has a reflectivity of less than about 10 percent in a wavelength range of about 350 to 1000 nanometers. 
     In addition to the exemplary aspects and embodiments described above, further aspects and embodiments will become apparent by reference to the drawings and by study of the following descriptions. 
    
    
     
       BRIEF DESCRIPTION OF THE DETAILED DRAWINGS 
       Exemplary embodiments are illustrated in referenced figures of the drawings. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than limiting. 
         FIG. 1  illustrates in schematic and/or functional block form an etching system for use in texturing silicon surfaces using catalytic solutions, with catalytic metal molecules or ionic species of catalytic material, and a oxidant-etchant solution; 
         FIG. 2  illustrates a silicon wafer or substrate after etching with an etching solution including catalytic and oxidant-etchant solutions showing a textured silicon surface with a plurality of etched tunnels or pits; 
         FIG. 3  is a flow chart of an exemplary texturing or etching process using catalytic solution combined with a oxidant-etchant solution to texture a silicon surface; 
         FIG. 4  is a sectional view of a solar cell fabricated with a silicon layer textured with catalytic metals such as with the system of  FIG. 1  and/or the process of  FIG. 3 ; and 
         FIGS. 5-7  are graphs illustrating reduced reflectance levels achieved in experiments or tests performed on silicon surfaces using etching solutions produced from a volume of catalytic solution and a volume of oxidant-etchant solution. 
     
    
    
     DESCRIPTION 
     The following provides a description of exemplary methods and systems for etching or texturing silicon surfaces such as to create a surface of tapered density to significantly reduce reflectivity (e.g., to create an anti-reflective surface on a silicon wafer that may be used in a solar cell). Generally, the etching methods include positioning a silicon surface in a volume of etching solution that is made up of a oxidant-etchant solution (e.g., an aqueous solution of an etching agent and an oxidizing agent such as HF and H 2 O 2 ) and a source of a molecule or ionic species that contains a catalytic metal (e.g., an acid such as chorauric acid in aqueous solution to provide gold in the etching solution or AgF in aqueous solution to provide silver and so on). The bath or volume of etching solution is stirred or agitated for a period of time (or an etch time) to achieve a desired amount/depth of texturing of the silicon surface, which may be thought of as forming a non-reflective layer or textured layer on the silicon surface. The gold or other metal catalyst is then cleaned or stripped from the silicon surface, and then the silicon surface or a wafer or substrate with such surface may be used to fabricate a device such as a solar cell, a biomedical device, an optoelectrical component, or the like. 
     The etching method described herein provides a solution-based approach to etching silicon that may use inexpensive chemicals (e.g., a reaction based on catalytic quantities of ionic or molecular-compound forms of gold, platinum, silver, or other catalytic metals in a oxidant-etchant solution is very inexpensive to create). The etching method is “one-step” rather than multi-step in the sense that etching occurs in the presence of the oxidant-etchant solution and the metal ionic or molecular solution as these experience ultrasonic or other agitation. The etching method is advantageous in part because of its simplicity and speed, with etch times being relatively short and not requiring deposition/coating pre-etching. The etching method is also desirable as it produces textured silicon surfaces with low reflectivity over a broad spectrum, and these non-reflective layers or textured silicon surfaces have a wide acceptance angle of anti-reflection. Further, the etching method(s) is applicable to nearly all surfaces of silicon including multi-crystalline silicon. As will be seen, the resulting silicon surfaces are likely to be highly desirable in the photovoltaic or solar cell industry. For example, the etching method, with HAuCl 4  provided as or as part of the catalytic solution, has been used to provide on &lt;1,0,0&gt;crystal silicon wafers reflectivity ranging from about 0.3% at a wavelength of 400 nm to about 2.5% at a wavelength of 1000 nm, with most of the usable solar spectrum below 1% reflectivity. When the catalytic solution included AgF, the etching solution technique was able to obtain reflection of less than about 5% on 100 crystal silicon wafers. 
     As will become clear, numerous catalytic solutions or sources of catalytic metals may be used to practice the etching process. One embodiment uses a catalytic solution chosen to provide molecular or ionic species of gold (e.g., chorauric acid (HAuCl 4 ) in aqueous solution) while another exemplary embodiment uses a catalytic solution (e.g., a solution with AgF) to provide molecular or ionic species of silver. Generally, the molecular or ionic species or a catalytic solution containing such catalysts is mixed with an etchant such as HF or the like and also with an oxidizing agent such as H 2 O 2  or the like. In other embodiments, the catalytic solution may be chosen to provide molecules and/or ionic species of other metals such as transition and/or noble metals in the etching solution such as platinum or the like, and this may be useful in further reducing the cost of etching and may be desirable as some of these metals may be less deleterious impurities in silicon than gold. 
     Generally, the silicon surface is a polished surface, but in some cases, the etching techniques may be performed in combination with other anti-reflection techniques. For example, the silicon surface may be an anisotropically pyramid-textured Si &lt;1,0,0&gt;surface (or other textured Si surface) that is then treated with a one step etching process by placing the Si &lt;1,0,0&gt;surface (or a substrate/wafer/device with the Si surface/layer) in an etching solution including a catalytic solution (with a metal-containing molecule or an ionic species of a catalytic metal), an etching agent, and an oxidizing agent. Used independently or with other surfacing processes, the etching solution is stirred or agitated for a period of time (e.g., a predetermined etch time) such as with ultrasonic agitation or sonication. 
     The following description stresses the use of catalytic solutions in etching silicon surfaces for use in controlling (i.e., reducing or minimizing) reflectance, but the etching techniques described herein may be used for texturing silicon for nearly any application in which it is desirable to provide a silicon surface with a particular surface roughness or non-smooth topology such as optoelectronic devices, biomedical device, and the like. The description begins with a general overview of the etching process with reference to  FIGS. 1-3 . Then with reference to  FIG. 4 , the description provides an example of one device, i.e., a solar cell, that can be formed with a silicon substrate or wafer with an antireflective surface created by the explained texturing methods. Next, the description provides a discussion of exemplary recipes (e.g., proportions of and particular types of catalytic solutions and the catalytic metals these solutions may provide, etching agents, oxidizing agents, silicon surfaces, agitation methods, etching times, and the like), processes, and the like to achieve useful results particularly with an eye toward reducing or nearly eliminating reflectance to increase efficiency of a solar cell (e.g., increase photon absorption in photovoltaic devices of silicon). 
       FIG. 1  illustrates a texturing or etching system  100  of one embodiment. The system  100  includes a source of or quantity of wafers, substrates, or devices  110  with silicon surfaces. These may be Si wafers that are to be used in solar cells, optoelectronics, or other products. The silicon surface  116  on silicon sample  112  may be mono-crystalline, multi-crystalline, amorphous, or the like, and the type of doping may be varied such as to be n or p-type doping of varying levels (such as from about 0.25 ohm-cm to about 50 ohm-cm or the like). The wafer, substrate, or device  110  may have one silicon surface or two or more such surfaces that will be etched during operation of system  100 . The system  100  does not require a metal deposition station, but, instead, the system  100  includes an etching assembly  120  with a wet etching vessel or container  122 . During operation, one or more of the Si wafers  110  or Si layers on substrate  112  are placed into the vessel  122  before or after adding a volume of an etching solution  124 . In  FIG. 1 , a single substrate  112  is shown in the vessel with an exposed silicon surface  116  but, of course, a plurality of such surfaces  116  may be etched concurrently. 
     The assembly  120  includes a mechanism  126  for agitating or stirring the solution  124  initially and/or during etching. The mechanism  126  may be a mechanical or magnetic-based stirring device while in some cased enhanced or more repeatable results are achieved with an ultrasonic agitator for stirring/agitating reactants or solutions such as etching solution  124  by sonication. The assembly  120  may include a heater  128  to maintain or raise the temperature of the etching solution  124  within one or more desired temperature ranges to facilitate etching of surface  116 . A temperature gauge or thermometer  130  may be provided to monitor the temperature of the solution (and, optionally, provide control feedback signals to heater  128 ), and a timer  134  may be provided to provide a visual and/or audio indicator to an operator of the assembly  120  regarding an etching or stripping step. 
     The system  100  further includes a catalytic solution  140  that provides a supply or source of a catalytic metal such as a metal containing molecule or ionic species of a catalytic metal. This source provides a quantity of catalyst for the etching solution  124  such as a quantity of a transition or noble metal such as gold, silver, platinum, palladium, copper, nickel, cobalt, and the like. Good results are typically achieved with solutions containing HAuCl 4 , AgF, and the similar acids or materials that release metal-containing molecules or ionic species of such metals when mixed with the oxidant-etchant solution in the etching solution  124  in vessel  122 . Generally, this catalytic solution with a metal catalyst is added to the vessel  122  to make up a portion of the etching solution  124 , but, in other cases, the solution (or other source of metal-containing molecules or an ionic species of a catalytic metal)  140  is first added to the oxidant-etchant solution  146  (or to one of its components  142 ,  144 ) prior to insertion into the vessel  122  with the Si substrate  112 . Specific, catalytic solutions and their makeup are discussed in further detail below. 
     To achieve etching of the silicon surface  116 , the system  100  includes a source of an etching agent  142  and of an oxidizing agent  144 . These are chosen specifically for texturing/etching of silicon, and the etching agent  142  may be HF, NH 4 F, or a similar etchant. The oxidizing agent may be H 2 O 2  or another agent such as one that has its decomposition catalyzed by the metal provided by catalytic solution  140 . For example, the oxidizing agent  144  may include H 2 O 2 , O 3 , CO 2 , K 2 Cr 2 O 7 , CrO 3 , KIO 3 , KBrO 3 , NaNO 3 , HNO 3 , KMnO 4 , or the like or a mixture thereof. These agents (or solutions thereof)  142 ,  144  may be added separately to the vessel  122  to form the etching solution  124  along with the catalytic solution  140  or, as shown, a oxidant-etchant solution  146  may be formed first by combining the etching agent  142  and the oxidizing agent  144  and then putting this solution in the vessel  122 . The assembly  120  is then operated such as by agitation via mechanism  126  and heating by heater  128  for a time period (“etch time”) to texture the surface  116 . After the etch time elapses, the solution  124  is removed (or substrate  112  is moved to another container or vessel for metal stripping), and remaining metal catalyst is removed as it is likely to present an undesirable impurity in silicon. To this end, the system  100  includes a source of a metal stripping solution  150  that is added to the vessel  122 , and the stripping solution may be stirred or agitated (and, optionally, heated with heater  128 ) by mechanism  126  until all or substantially all of the metal from material  140  is removed from surface  116 . The substrate or wafer  112  may then be used as is or as a component or layer of a larger device such as a solar cell or photovoltaic device, an optoelectric device, a biomedical device, or the like. 
       FIG. 2  illustrates a silicon wafer  200  after treatment of an etching process as described herein. As shown, the wafer  200  includes an upper surface or Si surface  210  that has been exposed to an etching solution for a period of time or an etch time. The Si surface  210  has nanoscale roughening that significantly reduces reflectivity. Significantly, the use of catalytic solutions as described herein is believed to act to produce nanoparticles of gold, silver, or other metal that in situ or in the etching solution (such as 2 to 30 nm gold particles, 2 to 30 nm silver particles, or the like depending on the makeup of the catalytic solution) causes the surface  210  to have a plurality of pits or tunnels  214  where etching has occurred much more rapidly due to the presence of a nanoparticle (not shown in  FIG. 2 ). Other mechanisms may be fully or partially responsible for the etching results achieved with the use of the catalytic solutions in combination with the oxidant-etchant solution. Regardless of the acting mechanism(s), each tunnel  214  includes an opening  216  at the surface  210  with a diameter, Diam Tunnel , and a depth, D Tunnel , that is typically less (e.g., up to about 99.91% less or the like) than the thickness, T wafer , of the wafer  200 , about 300 micrometers. For example, the tunnel diameters, Diam Tunnel , may be somewhat larger than the particle size such as about 21 to about 23 nm when 5 to 10 nm nanoparticles are present in the etching solution. The tunnel depths, D Tunnel , may be selected to provide a desired physical characteristic (e.g., an interference with reflection) and in the case of controlling reflectance by the silicon later  210  be between about 50 and about 300 nm (e.g., with one test showing tunnels in the 250 to 280 nm depth range) with a desired depth being selectable or-controlled by controlling time and temperature for a particular etching solution. As can be seen from  FIG. 2 , the etching processes involving catalytic solutions that provide a source of catalytic metal (and, in some cases, nanoparticles of such metals) are effective in providing a nanoscale roughness or structure with tapered density that is desirable for reducing reflectivity. 
       FIG. 3  illustrates one embodiment of a solutions-based etching or texturing process or method  300  for processing a silicon surface to obtain a desired characteristic such as, but not limited to, a tapered surface that reduces reflectance or creates a black surface. The process  300  begins at  305  such as with planning or selecting the type of silicon surface to be textured, e.g., a silicon wafer or a substrate or device with a silicon layer and a silicon surface, a particular crystalline surface or makeup, and a particular type of doping. Step  305  may also include choosing a recipe or step-by-step design for the texturing or etching of the silicon surface, and this may include choosing a catalytic metal and sources of molecules or ionic species of such as a metal, an etching agent for the silicon surface (e.g., HF or the like) and an oxidizing agent (e.g., H 2 O 2 , O 3 , CO 2 , K 2 Cr 2 O 7 , or the like), the ratio of each of these to provide in the oxidant-etchant solution that includes these two ingredients, the type and amount of agitation/stirring, the desired depth of surface penetration to provide with the etching, and the time and temperature for etching (which, of course, will vary based on the prior decisions/parameters). 
     The texturing/etching method  300  continues at  310  with the wafer(s) (or substrates/devices) with the silicon surface being chosen and then positioned into a reaction or etching vessel. At  320 , a oxidant-etchant solution is formed by combining or mixing the chosen etching and oxidizing agents (or solutions thereof), but, in some embodiments, this step is not performed and these two agents are simply added to the vessel concurrently or nearly so. The method  300  continues with the performance of steps  330  and  340 , which may be performed concurrently or nearly so such as within a preset time period (e.g., less than about 5 minutes or more typically less than about 2 minutes between performance of each step) with either being performed first. At  330 , the oxidant-etchant solution is added or input into the vessel with the silicon surface, and at  340 , a catalytic solution is added to the vessel (such as an acid or an aqueous solution of an acid that acts as a source of molecules containing (or ionic species of) gold, silver, platinum, palladium, copper, cobalt, nickel, another noble or transition metal, or another catalytic metal/material). In some cases, the particles are provided “dry” or in similar form while in other cases metal-containing molecules (or materials that provide such molecules or ionic species in the presence of the oxidant-etchant solution) are contained in deionized water or aqueous solution (or other appropriate medium) and a volume of such solution is added to the vessel at  340 . 
     At  350 , the method  300  includes mixing or agitating the etching solution in the vessel such as with mechanical mixing devices or, more typically, with ultrasonic mixing technologies or sonication. At  360 , the method  300  may optionally include heating the solution in the vessel to a predetermined temperature range (or adding heat to maintain the initial temperatures of the oxidant-etchant solution in a desired temperature range) chosen to hasten etching processes. At  365 , the method  300  may include illuminating the etching solution and/or the wafer or silicon surface with light to facilitate or drive the etching reactions/processes. For example, particular silicon surfaces, such as deeply n-doped surfaces, may benefit from being illuminated under a high-intensity light, which may reduce the etching time (such as to 8 minutes or less in some cases and enhance reflectivity results such as to less than about 5% reflectance where 20 to 30% was achieved without providing intense lighting). At  370 , the method  300  involves determining whether a preset etch time has elapsed (e.g., a time determined previously through testing to provide a desired depth or amount of etching based on the silicon surface type, the catalytic metal, and the oxidant-etchant solution composition). If not, the method  300  continues at  350 . 
     If the etch time has elapsed, at  370 , the method  300  includes removing the etch solution from the vessel or removing the Si wafer(s) from the vessel at  376 . At  380 , the catalytic metal is removed from the now textured silicon surface such as with use of a stripping solution selected based on the composition of the catalytic solution (e.g., a differing stripping solution may be used for gold, for silver, for platinum, and the like). At  388 , the method  300  may include further processing of the textured wafer to fabricate a device that makes use of the textured/etched silicon surface such as a solar cell, a biomedical device, an optoelectrical device, a consumer electronic device, or the like. At  390 , the method  300  is ended (or repeated by returning to step  305  where the same method may be repeated or changed such as to use one of the differing “recipes” described herein). 
     As discussed above, one reason it may be desirable to etch a silicon surface according to the processes described herein is to form a silicon substrate for use in forming a silicon-based solar cell with little or no total reflectance (e.g., without the need for application of an ARC or further processing). It will be understood that nearly any type of solar cell design may make use of the etching processes, and the description is intended to be broad enough to cover a wide variety of solar cells with varying design. However, at this time, it may be useful to at least describe one useful solar cell arrangement and to follow this with a brief discussion of one useful fabrication technique, and these descriptions may then be used to fabricate solar cells and other devices with silicon surfaces textured as described herein. 
       FIG. 4  illustrates a relatively simple solar cell  400 . As shown, the exemplary solar cell  400  includes a silicon substrate  410  with at least an upper surface that has been textured or roughened with a catalytic nanomaterial-based etching process (such as using the system  100  of  FIG. 1  or the method  300  of  FIG. 3 ) as described herein. The reflectance of the substrate may be controlled to be under about 20 percent, more typically less than about 10 percent, and in many cases in the range of about 0.3 to 2.5 percent or up to about 5 percent or more by such techniques. The substrate  410  may be, for example, a Boron-doped, p-type silicon surface or nearly any other silicon surface useful in solar cells. In such a case, the cell  400  may further include an n-type emitter layer  420  may be provided on the textured or upper surface of the silicon substrate  410 . A plurality of electrical contacts (e.g., silver or other contact material)  430  may be positioned on the emlitter layer  420 , and the cell  400  may further include additional layers/components to provide a desired functionality such as a back surface field layer  440  (e.g., an aluminum or similar metal layer) and a contact layer  450  (e.g., an aluminum or similar material layer). The silicon substrate  410  with an etched surface may take many forms such as an edge-defined film fed grown (EFG) silicon wafer, string ribbon silicon, float zone (FZ) silicon, Czochralski (CZ) grown silicon, cast multi-crystalline silicon (mc-Si), a monocrystalline silicon, epitaxially grown silicon layer, or another silicon structure or type. 
     In some cases, formation of a solar cell from a textured/etched silicon wafer may involve the following or other processes known to those skilled in the art. Formation of an emitter may involve the diffusion of phosphorus or similar material through the etched surface (e.g., from a spin-on dopant). The doping source may be removed by further etching in concentrated HF or the like, and the result of the diffusion may be the formation of n-type regions. Surface passivation may be provided by oxidizing (e.g., with O 2 ) and annealing (eg., with N 2 ), which may provide a dry oxide layer with an annealed interface to the silicon to reduce the surface recombination at the heavily doped emitters. A back contact may then be formed by removing the passivating oxide from the back surface of the silicon wafer or substrate and then applying a layer of aluminum or other similar metal and a silver or similar metal onto these back surfaces such as by vacuum evaporation or the like. Next, a front contract grid may be formed such as by opening an array of slits in the passivating oxide on the front or textured surface side of the wafer/substrate and then covering these slits with Ti or the like such as by vacuum evaporation and lift-off of photoresist. The solar cell may be further processed or be assembled with other cells to make solar modules, which in turn may be linked to form photovoltaic arrays. Of course, this is just one simplified method of fabricating a solar cell and it may be modified to form a cell with a black etched surface described herein or other techniques well known in the industry may be used in its place. 
     The inventors have performed numerous experiments with differing catalytic nanomaterials, oxidant-etchant solutions, and silicon surface types/dopings and have also tested resulting surfaces for reflectivity. The following discussion describes these experiments and the inventors findings as well as more general conclusions and extensions of their ideas. The process described herein is generally a wet-chemical method that is particularly well suited for producing silicon surfaces that exhibit nearly complete suppression of reflectivity in the wavelength range of 350 to 1000 nm. The processes described herein are believed useful with mainly silic on substrates such as single-crystal p-type Czochralski, {&lt;1,0,0,&gt;and &lt;1,1,1,&gt;}, n and p-type Float Zone, intrinsic, n and p-doped amorphous, and p-doped multi-crystalline as well as other silicon surfaces. 
     In one set of experiments, the catalytic solution was a dilute (e.g., less than about 2 mM or, in some cases, less than about 1 mM) solutions of gold, silver, platinum, and other ions that may be presented in the form of HAuCl 4 , AgF, and the like. This catalytic solution is added to the oxidant-etchant solution and these solutions combine under agitation to form an etch solution that etches a silicon surface. The etch time was significantly reduced relative to prior etching techniques such as less than about 4 minutes (e.g., 2 to 4 minutes or a similar time frame) to obtain a minimum achievable reflectivity (e.g., less than about 3% such as 1 to 2% or even as low as 0.2 to 0.4% in some cases such as those using gold as the catalyst) and also to achieve a relatively uniform surface texture. Such etching results were found to be achievable for both multi-crystalline and single crystalline silicon wafers of all orientations. Further, amorphous silicon layers approximately 1 micrometer thick required only about 90 seconds to achieve minimum achievable reflectance. 
     Regarding agitation/stirring during the etching process, both magnetic stirring and ultrasonication (e.g., 125 W or the like) were utilized for solution mixing during the etching reactions. Magnetic stirring generally was found to yield wafers with a flatter reflectivity profile over the 350 to 1000 nm wavelength range. However, magnetic stirring may not yield wafers or silicon surfaces with the minimum achievable reflectivity in the middle of this wavelength range and may be ineffective for initiation of certain black etch procedures depending upon the catalytic nanomaterial utilized. Ultrasonication or ultrasonic agitation, hence, may be more useful in some applications. Generally, in the experiments/tests run by the inventors, polytetrafluoroethylene (PTFE) or Teflon® labware was used for the investigations, and the chemicals solutions used were clean room/reagent grade. 
     The oxidant-etchant solution generally includes an etching agent chosen for silicon and a silicon oxidizing agent whose decomposition can be catalyzed by the chosen catalytic metal. In one embodiment, HF is used as the etching agent while H 2 O 2  is the oxidizing agent with the balance of the etching solution volume being deionized water. The specific make up of the oxidant-etchant solution may vary widely to practice the described etching such as 5 to 15% w/w HF, 15 to 30% H 2 O 2  with the balance being DI H 2 O. In one case, a oxidant-etchant solution (sometimes referred herein to as a 2× strength oxidant-etchant solution) was formed with 6.25% w/w HF, 18.75% w/w H 2 O 2 , and balance DI H 2 O while in another case a oxidant-etchant solution with 26.25% H 2 O 2  and 6.25% HF was used and found effective when the wafers are deeply doped (e.g., n-doping may require longer etch times such as up to 60 minutes or more and/or higher etching solution temperatures such as up to about 950° C. or more). The final etching solution is somewhat more diluted due to the combination with the solution provided with the catalytic nanomaterial. For example, the etching solution may include equal volumes of the oxidant-etchant solution and the catalytic nanomaterial solution (e.g., a metal colloid solution), and in the above specific example, this would yield an etching solution of 3.125% w/w HF, 9.375% w/w H 2 O 2  and DI H 2 O to provide a volume ratio of 1:5:2 of HF:H 2 O 2 :DI H 2 O. 
     A wide variety of silicon wafers may be etched as described herein with some testing being performed on 1 square inch Czochralski wafers that were polished on one side. The wafers may be n-type or p-type with a wide range of doping (e.g., 0.25 ohm-cm to about 50 ohm-cm or the like). In particular embodiments, the resistivities of p-doped CZ, FZ, and multi-crystalline wafers (excluding tested undoped-pCZ&lt;1,1,1,&gt;wavers) were between about 1 and about 3 ohm-cm. Also, p-doped CZ&lt;3,1,1,&gt;wafers were tested that had a resistivity of about 0.5 ohm-cm. Further, tests were performed using p-doped CZ&lt;1,1,1,&gt;wafers with a resistivity in the range of about 0.2 to about 0.25 ohm-cm. In the following tests, the volume of the etching solution used was typically about 5 ml to about 15 ml per square inch of silicon wafer or silicon surface with 10 ml reactant per square inch of wafer being used in some cases, but, of course, the volume may be optimized or selected to suit the size/shape of the reactant vessel and size and number of the silicon wafers processed in each batch and based on other variables. 
     The stripping solution used to remove remaining nanoparticles after etch is complete may also vary to practice the process and is typically selected based on a number of factors such as to provide a chemistry suitable for the catalytic nanomaterial. When the nanoparticles were silver or gold, the stripping solution may be 25 g I 2 /100 g KI per liter of DI H 2 O or aqua regia or the like, and the stripping or metal removal time, agitation technique, and volume of stripping solution may be similar or even the same as used in the etching process. Reflectance measurements after etching and stripping may be performed in a number of ways such as with a Cary-5G UV-vis spectrometer that is equipped with a calibrated spherical reflectance or similar device. Real-time UV-visible reflectance spectrometry assays may be performed to obtain information about the progress of etching using devices such as an Ocean Optics&#39; fiber-optic pixel array UV-visible spectrometer. 
     With respect to time, the stability of the pre-mixed etching solution formed with HAuCl 4  solution may be relatively short such as about 2 minutes at room temperature, and after this time, gold nanoparticles may form such as by the in-situ reduction of Au 3+  by H 2 O 2 , rendering the pre-mixed etching solution inactive or less active with respect to achieving black etching. Hence, it may be desirable to combine the catalytic solution with the oxidant-etchant solution in the vessel in the presence of the silicon surfaces to be etched or forming the etching solution and then promptly placing this solution in the vessel containing the silicon wafer(s). One useful procedure entails placing the Si wafer in the HAuCl 4  solution prior to the addition of the 2× strength oxidant-etchant solution and then performing concurrent or subsequent ultrasonication such as for about 3 to 4 minutes or longer. In one implementation/experiment, the size of the resultant “Purple of Cassius” gold particles from catalytic solutions of 0.4 mM HAuCl 4 :2× strength black etch after 4-minute etching was determined by TEM to be less than about 10 nm. XPS spectroscopy revealed that the gold particles did not contain Au(I) ions, (e.g., from AuF) but only or mainly Au 0 . 
     One useful catalytic concentration of HAuCl 4  has been determined via iterative experiments to be about 0.0775 mM for p-CZ&lt;1,0,0&gt;wafers while about 0.155 mM was useful for p-doped CZ&lt;1,1,1&gt;and &lt;3,1,1&gt;wafers and about 0.31 mM was found desirable for p-multi-crystalline wafers. In some experiments, p-FZ wafers and un-doped p-CZ&lt;1,1,1&gt;, {*R 75 Ω-m} silicon surface were better etched with a catalytic solution containing a minimum HAuCl 4  of about 0.04 mM. Hence, wafers containing excess positive carriers and, in some cases, having a lower sheet resistance may be better or completely black etched or textured with ha higher HAuCl 4  concentration or amount provided in the etching solution. 
     Further, electrochemical experiments involving the placement of Au-plated alligator clips on the dry portions of test p-FZ wafers placed in a 10 nM black-etch reaction limiting concentration and a Pt-wire counter electrode revealed that a positively-charged Si surface enhances the black etch procedure while a negatively charged Si surface hinders it. This appears to support the concept that the etching processes described herein involve a mechanism involving a Silyl (Si 3   + ) transition-state at the crystal surface, which may be formed by the initial HF etch of thin (e.g., 7 to 20 Angstrom) SiO 2  films by the 2× strength oxidant-etchant solution in the presence of the catalytic solution. 
     The possibility of increasing the etching rate of the silicon surface by increasing temperature has been confirmed by the observation of a 4-fold rate increase with a 20° C. increase in reaction temperature when the etching process including heating of the etching solution. For example, in some implementations, etching was performed for about 30 to 60 seconds and texturing reached about the same degree of black-etch at 45° C. etching temperature compared with about 180 to 240 seconds or more provided for etching time with etching solutions maintained at room temperature (e.g., about 25° C.). 
     With the use of a catalytic solution including HAuCl 4 , perpendicular and cross-sectional SEM studies of mono-crystalline &lt;1,0,0,&gt;Si wafers tested have revealed a uniform surface morphology containing an average 20 to 25 nm diameter cylindrical etch tunnels (as shown in  FIG. 2 ) approximately 275 nm deep for the “standard” 3 to 4 minute etching process. Perpendicular and cross-sectional SEM studies of mono-crystalline &lt;1,1,1,&gt;Si wafers tested have revealed a uniform surface morphology containing few, if any, of the 20 to 25 nm diameter cylindrical etch tunnels obtained above, but instead, included a plurality of 35 to 50 μm diameter circular plates. These raised plates or islands were separated from each other and offset vertically from each other by about 0.6 to about 1.2 μm. However, to the eye, and based on testing with UV-vis reflectance spectroscopy, there is little or no difference in the “darkness” between the &lt;1,0,0&gt;and &lt;1,1,1&gt;black etched wafers. 
     Observations made for a p-CZ&lt;1,1,1&gt;Si sample used for the SEM results referred to in the above paragraph, which had been subject to the Gold removal (as AuI 3 ) with I 2 /KI solution as compared to the Gold-containing sample, show that a smoothing of the pancake-like features can be observed with the concomitant elimination of a few tunnel-like features. Initial indications from both stylus and optical profilometry on sonic p-CZ&lt;1,1,1&gt;Si samples that had been subjected to the I 2 /KI solution and had 12.4 nm of aluminum evaporated onto it, showed only flat surface morphology. Testing results generally indicate the etching processes described herein are effective in texturing a wide variety of silicon surfaces, and such texturing of a variety of surfaces likely will be advantageous in solar cell design and functionality. 
     In one specific experiment, a 4-minute etch was performed on a &lt;1,0,0&gt;p-CZ silicon wafer. The catalytic solution in this experiment was about 0.31 mM HAuCl 4  at a 50:50 volume ratio in the etch solution with 2× strength oxidant-etchant solution (e.g., HF and H 2 O 2 ). Real-time reflectivity measurements indicate that across a wide spectrum or wavelength range of 575 nm to 1160 nm that reflectance rapidly (e.g., less than about 50 seconds) dropped to less than 10% and by about 180 seconds had reached a minimum reflectance near zero (e.g., in the range of 0.2 to 1%). 
     In another experiment, an etch solution of about 5.0 ml/0.5 in 2  of p-CZ&lt;1,0,0&gt;silicon wafer was etched with sonication for about 4 minutes. In this case, the catalytic solution was 0.29 mM AgF to provide silver as the catalytic metal during etching. The etching solution also included an equal volume of 2× oxidant-etchant solution with HF and H 2 O 2 .  FIG. 5  illustrates a graph  500  illustrating the results with line  510 , while line  520  shows similar results after etching and removal of the remaining silver. In  FIG. 5 , the increase in reflectivity for wavelength above about 1100 nm is caused by a reflective background behind the silicon wafer during measurement. The kinetics of this sample wafer showed that after about 30 seconds reflectance was reduced to below 10% over wavelengths from about 575 nm to 1160 nm while minimum achievable reflectance in the range of about 0.1 to 1.5 was achieved in the range of about 130 to 240 seconds. When the catalytic solution was changed to 0.31 mM HAuCl 4 , the resulting reflectance was generally less than about 5% from 350 nm to 1000 nm with the typical value being less than about 1%. 
     Excellent results were also achieved in etching p-mc silicon with a catalytic solution of 0.31 mM HAuCl 4  combined with 2× strength of oxidant-etchant solution. Again, the etching solution was agitated for about 4 minutes and the gold was then removed. The etched or textured layer on the silicon surface showed reflectance of less than about 10 percent from 350 to 1000 nm wavelength light with an average of less than about 5 to 6%. 
       FIG. 6  illustrates a graph  600  with the results of etching of a single crystal silicon surface shown with line  610 . In  FIG. 6 , the increase in reflectivity for wavelength above about 1100 nm is caused by a reflective background behind the silicon wafer during measurement. In this experiment, the etching solution included equal volumes of 0.39 mM HAuCl 4  and of oxidant-etchant solution with 6.25% HF and 26.25% H 2 O 2  and etching proceeded for 4 minutes in this strong solution, following an aggressive surface oxide strip with 5% HF under sonication for 5 minutes. This strong black etching solution was often beneficial in texturing surfaces that were free of oxide. The results show, that reflectance of the surface was lowered to less than about 5% and down to about 1 or 2% in some portions of the 350 to 1000 nm spectrum. 
     Etching has also been completed on other silicon surfaces with catalytic solutions such as 0.31 mM HAuCl 4  or the like. For example, a black etch was performed for 3.5 minutes on a 0.67 micrometer n-doped amorphous silicon layer on a stainless steel substrate using the 0.31 mM HAuCl 4  catalytic solution combined equally with 1× strength oxidant-etchant solution of HF and H 2 O 2 . In this case, the reflectance was generally 5 to 10% less over the 350 to 1000 nm wavelength range, but reflectance still averaged about 40%. Better results were seen when a black etch was performed on a 1.0 micrometer non-doped amorphous silicon layer on a stainless steel substrate. In this test, etching was performed for 90 seconds with a 1:1 volumetric ratio of 0.31 mM HAuCl 4  and 2× strength oxidant-etchant solution. The reflectance was reduced about 15 to 25% across the 350 to 1000 nm spectrum to values ranging from about 18 to about 60%. Reasonable results were also achieved when a 2.45-minute black etch was performed on 1.0 micrometer non-doped amorphous silicon on a glass substrate with an etch solution having equal volumes of 0.31 mM HAuCl 4  and 2× strength oxidant-etchant solution. Testing of such an etched surface showed a significant reduction of reflectance at the lower end and higher end of the 350 to 1200 nm spectrum with less change from about 700 nm to about 800 nm, e.g., with reflectances ranging from about 15% to about 43%. Black etching as taught herein was also performed on a 1.0 p-doped amorphous silicon layer on a stainless steel substrate with similar etching solution as in the prior example. This texturing provided a reflectance reduction to about 25% to about 50% ranged in the 350 to 1000 nm spectrum. Excellent results were obtained in an experiment where an anistropically KOH/IPR etched p-FZ silicon wafer was black etched for 4 minutes with a 1:1 volumetric ratio etching solution of 0.39 mM HAuCl 4  and 2× strength oxidant-etchant solution followed by 5 minutes of gold removal from the etched surface. The tests show this surface generally has a reflectance in the range of about 1 to 3% or lower across the 350 to 1000 nm spectrum. 
       FIG. 7  illustrates a graph  700  providing results of an exemplary 8-minute black etch performed on a heavily n-diffused (e.g., POCl 3 @ 950° C. for 1 hour) p-FZ&lt;100&gt;silicon wafer. In this etching process, the etching solution included equal volumes of 0.4 nM HAuCl 4  and oxidant-etchant solution (with 26.25% H 2 O 2 ). As shown with line  710 , when tie etching was performed without adding light or illuminating the silicon surface and etching solution with high intensity light reflectance was only lowered to about 15% to about 27% in the useful 350 to 1000 nm spectrum. In contrast, when the etching method further included providing light sources at about 50 mm above the wafer, the etching results were much more desirable for using the silicon surface in a solar cell or similar application in which low reflectance is desired. As shown with line  720 , when the etching is carried out in the presence of a 6V flashlight/light source that is operated to direct light onto the wafer surface through the etch solution, the reflectance in the 350 to 1000 nm range is lowered to below about 5% (e.g., in the 2.5 to 4% range). Similarly, when the light source is a 3 W, 12 V LED the reflectance as shown with line  730  is reduced below 5% to the range of about 2 to about 4% over the 350 to 1000 nm wavelength range. Hence, in some implementations, light sources may be used to provide light (e.g., relatively high-intensity and/or directed light with a significant component of blue light that is considered to be useful) that can be directed onto the etched surface to act as a further driver of the etching process, and anti-reflection surfaces are better obtained by adding illumination when etching a silicon surface such as that found in a solar cell with a diffuse junction of n-emitter on a p-base wafer. 
     While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations additions, and sub-combinations thereof it is therefore intended that the following appended claims hereafter introduced are interpreted to include modifications, permutations, additions, and sub-combinations to the exemplary aspects and embodiments discussed above as are within their true spirit and scope. As will be understood from the above description, the catalytic etching of silicon based on catalytic molecular or ionic species is useful for eliminating previously used deposition process for creating metal clusters or islands. Expensive metallic nanoparticles are not employed though such nanoparticles may be created during the etching process and contribute to the catalytic process producing the surface texture. Further, the described etching process provides excellent control over silicon characteristics such as reduction of reflectance to facilitate use of textured silicon in solar cells with numerous tunnels being bored or formed fairly uniformly across the silicon surface (e.g., a single nanoparticle may act to catalyze a hole of about the diameter being created in the surface and then etching a very high aspect ratio tunnel or pit in the surface such as a hole diameter of 2 to 30 nm and a tunnel depth in the 200 to 300 nm range).