Patent Publication Number: US-11385668-B2

Title: Configurable offset compensation device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention is related to an offset compensation device, and more particularly to a configurable offset compensation device. 
     2. Description of the Prior Art 
     Since the differential signal has a better immunity against ambient noises, it is widely adopted in various circuits. However, in the actual manufacturing of differential amplifiers or other types of differential circuits, due to process deviations, the direct current (DC) voltage level is often shifted unexpectedly, causing offset voltages and/or offset currents at the terminals of the differential pair. Since the offset voltage and/or offset current at the terminals of the differential pair will interfere with the differential signal and cause distortion, additional voltage or current must be applied to compensate the offset and reduce the impact brought by the shift of the DC voltage level. 
     Furthermore, as the manufacturing technology grows, the size of electronic components becomes smaller and smaller. However, when the size of the electronic component becomes smaller, the influence of the same offset voltage and/or offset current on the differential circuit will also become more significant, and thus, the requirements for accurate compensation to the offset voltage and/or the offset current would be higher. 
     SUMMARY OF THE INVENTION 
     One embodiment of the present invention discloses an offset compensation device. The offset compensation device includes a first bias module and a second bias module. 
     The first bias module is coupled to a first bias node and includes a plurality of first current control circuits and a plurality of second current control circuits. Each of the plurality of first current control circuits generates a first reference current, and each of the plurality of second current control circuits generates a second reference current. The second bias module is coupled to a second bias node and includes a plurality of third current control circuits and a plurality of fourth current control circuits. Each of the plurality of third current control circuits generates a third reference current, and each of the plurality of fourth current control circuits generates a fourth reference current. 
     The plurality of first current control circuits and the plurality of second current control circuits are coupled in parallel and coupled to the first bias node. The plurality of third current control circuits and the plurality of fourth current control circuits are coupled in parallel and coupled to the second bias node. The second reference current is greater than the first reference current, and the fourth reference current is greater than the third reference current. 
     Another embodiment of the present invention discloses a method for operating an offset compensation device. The offset compensation device includes a first bias module and a second bias module. The first bias module includes a plurality of first current control circuits and a plurality of second current control circuits. The second bias module includes a plurality of third current control circuits and a plurality of fourth current control circuits. The plurality of first current control circuits and the plurality of second current control circuits are coupled in parallel and coupled to a first bias node, and the plurality of third current control circuits and the plurality of fourth current control circuits are coupled in parallel and coupled to a second bias node. 
     The method includes enabling a first number of second or fourth current control circuits according to an offset value for making a preliminary compensation to the offset value, and enabling a second number of first or third current control circuits according to the offset value after the preliminary compensation is made for making a further compensation to the offset value. 
     A second reference current generated by each of the second current control circuits is greater than a first reference current generated by each of the first current control circuits, and a fourth reference current generated by each of the fourth current control circuits is greater than a third reference current generated by each of the third current control circuits. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an offset compensation device according to one embodiment of the present invention. 
         FIG. 2  shows a flowchart of a method for operating the offset compensation device in  FIG. 1  according to one embodiment of the present invention. 
         FIG. 3  shows the relationship between the LO leakage of the mixer and the configuration of the current control circuits of the offset compensation device in  FIG. 1  according to one embodiment of the present invention. 
         FIG. 4  shows another offset compensation device according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  shows an offset compensation device  100  according to one embodiment of the present invention. In  FIG. 1 , the offset compensation device  100  can be used to compensate the offset current IOS between the two differential current terminals of a mixer M 1 . The offset compensation device  100  includes a first bias module  110  and a second bias module  120 . The first bias module  110  can be coupled to a first bias node N 1 , and the second bias module  120  can be coupled to a second bias node N 2 . 
     The first bias module  110  can include first current control circuits  1121  to  112 X and second current control circuits  1141  to  114 Y, where X and Y are positive integers. Each of the first current control circuits  1121  to  112 X can generate a first reference current Iref 1 , and each of the second current control circuits  1141  to  114 Y can generate a second reference current Iref 2 . The second bias module  120  can include third current control circuits  1221  to  122 X and fourth current control circuits  1241  to  124 Y. Each of the third current control circuits  1221  to  122 X can generate a third reference current Iref 3 , and each of the fourth current control circuits  1241  to  124 Y can generate a fourth reference current Iref 4 . 
     In the first bias module  110 , the first current control circuits  1121  to  112 X and the second current control circuits  1141  to  114 Y can be coupled to the first bias node N 1  and can be coupled in parallel. In the second bias module  120 , the third current control circuits  1221  to  122 X and the fourth current control circuits  1241  to  124 Y can be coupled to the second bias node N 2  and can be coupled in parallel. 
     In  FIG. 1 , the first current control circuit  1121  can include a reference current source CS 1  and a switch SW 1 . The reference current source CS 1  can generate the first reference current Iref 1 , and the switch SW 1  can be coupled in series with the reference current source CS 1 . In some embodiments, the switch SW 1  can be turned on to enable the first reference current source CS 1  and can be turned off to disable the first reference current source CS 1 . In some embodiments, the first current control circuits  1121  to  112 X, the second current control circuits  1141  to  114 Y, the third current control circuits  1221  to  122 X, and the fourth current control circuits  1241  to  124 Y can have the similar structures. That is, the offset compensation device  100  can control the switches SW 1  in the first current control circuits  1121  to  112 X, the switches SW 2  in the second current control circuits  1141  to  114 Y, the switches SW 3  in the third current control circuits  1221  to  122 X, and the switches SW 4  in the fourth current control circuits  1241  to  124 Y to enable or disable the reference current sources CS 1 , CS 2 , CS 3 , and CS 4 . Therefore, each of the first current control circuits  1121  to  112 X, the second current control circuits  1141  to  114 Y, the third current control circuits  1221  to  122 X, and the fourth current control circuits  1241  to  124 Y can be controlled independently. 
     Furthermore, in the present embodiment, the second reference current Iref 2  generated by the reference current source CS 2  can be greater than the first reference current Iref 1  generated by the reference current source CS 1 , and the fourth reference current Iref 4  generated by the reference current source CS 4  can be greater than the third reference current Iref 3  generated by the reference current source CS 3 . In addition, the first reference current Iref 1  can be equal to the third reference current Iref 3 , and the second reference current Iref 2  can be equal to the fourth reference current Iref 4 . 
     Furthermore, in  FIG. 1 , the first bias module  110  can further include a first primary current source  116 . The first primary current source  116  can be coupled in parallel with the first current control circuits  1121  to  112 X and the second current control circuits  1141  to  114 Y, and the first primary current source  116  can generate a first primary current Im 1 . Similarly, the second bias module  120  can further include a second primary current source  126 . The second primary current source  126  can be coupled in parallel with the third current control circuits  1221  to  122 X and the fourth current control circuits  1241  to  124 Y, and the second primary current source  126  can generate a second primary current Im 2 . The first primary current source  116  and the second primary current source  126  can be used to provide the default bias currents according to the system requirement even when the first current control circuits  1121  to  112 X, the second current control circuits  1141  to  114 Y, the third current control circuits  1221  to  122 X, and the fourth current control circuits  1241  to  124 Y are disabled. In some embodiments, the first primary current Im 1  can be equal to the second primary current Im 2 . 
     In some embodiments, the offset compensation device  100  can enable a proper number of second current control circuits  1141  to  114 Y or a proper number of fourth current control circuits  1241  to  124 Y according to the offset value to be compensated, that is, the offset IOS in the present embodiment. After the number of second current control circuits  1141  to  114 Y or the number of fourth current control circuits  1241  to  124 Y to be enabled is determined to make a preliminary compensation, according to the result of the preliminary compensation, the number of first current control circuits  1121  to  112 X or the number of third current control circuits  1221  to  122 X to be enabled can be determined to make a further compensation to the offset current IOS. 
     Since the offset compensation device  100  can use the second current control circuits  1141  to  114 Y or the fourth current control circuits  1241  to  124 Y to generate greater currents for making a preliminary compensation, and can use first current control circuits  1121  to  112 X or the third current control circuits  1221  to  122 X to generate smaller current for making a further compensation, the offset compensation device  100  can determine the numbers of current control circuits to be enabled for achieving the desired compensation result rapidly. Furthermore, by adopting this kind of configurable compensation structure, the offset compensation device  100  can reduce the total number of the current control circuits and, thus, the offset compensation device  100  can be implemented within a smaller circuit area. 
       FIG. 2  shows a flowchart of a method  200  for operating the offset compensation device  100  according to one embodiment of the present invention. The method  200  includes steps S 210  and S 220 . 
     S 210 : enable a corresponding number of second current control circuits  1141  to  114 Y or a corresponding number of fourth current control circuits  1241  to  124 Y according to the offset value to be compensated for making a preliminary compensation to the offset value; and 
     S 220 : enable a corresponding number of first current control circuits  1121  to  112 X or a corresponding number of third current control circuits  1221  to  122 X according to the desired bias value after the preliminary compensation is made for making a further compensation to the offset value. 
     Generally, the actual value of the offset current IOS is unknown before the offset current IOS is compensated. However, the value of the offset current can be roughly depicted by observing the offset current and/or the local oscillator (LO) leakage generated by the mixer M 1  under the original DC level condition. 
     In addition, according to the direction of the leakage current, the user can determine to increase the current at the first bias node N 1  by enabling the second current control circuits  1141  to  114 Y or to increase the current at the second bias node N 2  by enabling the fourth current control circuits  1241  to  124 Y for compensation. For the mixer M 1 , the current on the first node N 1  and the current on the second node N 2  are counterparts to each other. That is, increasing the current on the first bias node N 1  has the same effect as decreasing the current on the second bias node N 2 . Similarly, increasing the current on the second bias node N 2  has the same effect as decreasing the current on the first bias node N 1 . Therefore, in general, when any of the second current control circuits  1141  to  114 Y is determined to be enabled, all the fourth current control circuits  1241  to  124 Y may be disabled, avoiding the second reference current Iref 2  and the fourth reference current Iref 4  from canceling each other. Similarly, when any of the fourth current control circuits  1241  to  124 Y is determined to be enabled, all the second current control circuits  1141  to  114 Y may be disabled. 
     In step S 210 , after determining whether to enable the second current control circuits  1141  to  114 Y or the fourth current control circuits  1241  to  124 Y, the corresponding number of the second current control circuit  1141  to  114 Y or the corresponding number of the fourth current control circuit  1241  to  124 Y that should be enabled can be further determined. In some embodiments, the offset compensation device  100  can gradually increase the number of enabled second current control circuits  1141  to  114 Y to increase the current on the first bias node N 1  or gradually increase the number of enabled fourth current control circuits  1241  to  124 Y to increase the current on the second bias node N 2  for seeking the proper configurations of the current control circuits that can minimize the LO leakage. 
       FIG. 3  shows the relationship between the LO leakage of the mixer M 1  and the configuration of the current control circuits of the offset compensation device  100  according to one embodiment of the present invention. In  FIG. 3 , the actual value of the offset current IOS can be, for example, 280 μA, and the fourth reference current Iref 4  generated by each of the fourth current control circuits  1241  to  124 Y can be 100 μA. In this case, when the offset compensation device  100  gradually enables the fourth current control circuits  1241  to  1243 , part of the reference currents Iref 4  generated by the fourth current control circuits  1241  to  1243  will cancel out the offset current IOS. Therefore, the value of LO leakage will gradually decrease. However, when the offset compensation device  100  enables the fourth current control circuits  1241  to  1244 , it will over-compensate, which will increase the value of the LO leakage. In this case, the offset compensation device  100  can select to enable only three of the fourth current control circuits  1241  to  1243  as the most appropriate configuration in step S 210  to perform the preliminary compensation to the offset current IOS. 
     In step S 220 , the similar principle can be followed. That is, the offset compensation device  100  can gradually increase the number of enabled first current control circuits to increase the current on the first bias node N 1  or gradually increase the number of enabled third current control circuits to increase the current on the second bias node N 2  for making further compensation. 
     For the mixer M 1 , since the current on the first node N 1  and the current on the current on the second node N 2  are counterparts to each other. Therefore, when any of the first current control circuits  1121  to  112 X is determined to be enabled, all the third current control circuits  1221  to  122 X may be disabled, avoiding the first reference current Iref 1  and the third reference current Iref 3  from canceling each other. Similarly, when any of the third current control circuits  1221  to  122 X is determined to be enabled, all the first current control circuits  1121  to  112 X may be disabled. 
     In  FIG. 3 , the first reference current Iref 1  and the third reference current Iref 3  can be 25 μA. In this case, when there are more third current control circuits  1221  to  122 X being enabled, the LO leakage of the mixer M 1  will also increase. However, when the first current control circuit  1121  is enabled, the LO leakage of the mixer M 1  will have a minimal value, and the LO leakage of the mixer M 1  will increase when the first current control circuit  1122  is also enabled. In this case, the offset compensation device  100  can determine to enable the first current control circuit  1121  to complete the compensation for the offset current IOS in step S 220 . 
     Since the offset compensation device  100  can use the current control circuits that generate greater currents to make a preliminary compensation, and can use the current control circuits that generate smaller currents to make a further compensation according to the result of the preliminary compensation, the offset compensation device  100  can determine which current control circuits to be enabled and the numbers of enabled current control circuits rapidly to make the compensation. By adopting such configurable compensation structure, the offset compensation device  100  can reduce the total number of current control circuits and, thus, compensation can be completed within a smaller circuit area. 
     For example, if the system requires the offset compensation device  100  to provide  32  levels of different compensation currents, then X can be 7 and Y can be 3. In this case, the first bias module  110  and the second bias module  120  can each include 10 current control circuits. However, in prior art, if the reference currents generated by the current control circuits are all the same, each bias module would need 31 current control circuits for providing the  32  levels of different compensation currents. In contrast, the offset compensation device  100  can not only reduce the area, but also reduce the parasitic effects and maintain the compensation effect. 
     In the offset compensation device  100 , the first bias module  110  and the second bias module  120  can each include two different current control circuits for generating reference currents of different intensities. Therefore, the compensation can be achieved in two stages. However, in some other embodiments, according to the system requirement, the offset compensation device may include more different current control circuits for generating reference currents of different intensities and achieve the compensation with more stages. 
     Furthermore, due to the uncontrollable factors in the manufacturing process, the first reference currents Iref 1  generated by the first current control circuits  1121  to  112 X may not be completely equal. In this case, to ensure that the current can be increased smoothly when the number of enabled current control circuits increases, the first current control circuits  1121  to  112 X can have the same layout so that the variation of the reference current Iref 1  can be reduced. Also, the first current control circuits  1121  to  112 X can be enabled according to a fixed order so as to prevent that the current is not positively correlated to the number of enabled current control circuits when the enabled current control circuits are unfortunately the ones that generate smaller reference currents Iref 1 . Similarly, the other current control circuits can be operated with the same principle to reduce the current variation to influence the compensation result. 
     Furthermore, since the second reference currents Iref 2  generated by the second current control circuits  1141  to  114 Y may also be slightly different, the first bias module  110  may include more first current control circuits  1121  to  112 X so the total current generated by the first reference currents Iref 1  outputted by the first current control circuits  1121  to  112 X can be greater than the target value of the second reference current Iref 2 . For example, if the second reference current Iref 2  is targeted to be 100 μA and the first reference current Iref 1  is targeted to be 25 μA, then the first bias module  110  can include 5 first current control circuits  1121  to  1125 , that is, X can be 5. Consequently, when the second reference current Iref 2  generated by the second current control circuit  1141  is smaller than the target value, such as 75 μA, then the first bias module  110  can still provide a 200 μA current by enabling the second current control circuit  1141  and the five first current control circuits  1121  to  1125 , ensuring the current accuracy of each compensation stage. Similarly, the second bias module  120  can include more third current control circuits  1221  to  122 X so that the total current generated by the third reference currents Iref 3  outputted by the third current control circuits  1221  to  122 X can be greater than the target value of the fourth reference current Iref 4 . 
     In  FIG. 1 , the number X of the first current control circuits  1121  to  112 X can be the same as the number X of the third current control circuits  1221  to  122 X, and the number Y of the second current control circuits  1141  to  114 Y can be the same as the number Y of the fourth current control circuits  1241  to  124 Y. However, in some embodiments, according to the system requirements, the number of the first current control circuits can be different from the number of the third current control circuits. Also, the number of the second current control circuits can be different from the number of the fourth current control circuits. 
       FIG. 4  shows another offset compensation device  300  according to another embodiment. The offset compensation device  300  and the offset compensation device  100  can have similar structures, and can be operated by similar principles. However, the offset compensation device  300  can further include resistors R 1  and R 2 . 
     The resistor R 1  has a first terminal coupled to the first bias node N 1 , and a second terminal coupled to a system voltage terminal NV 1 . The resistor R 2  has a first terminal coupled to the second bias node N 2 , and a second terminal coupled to the system voltage terminal NV 1 . In this case, by adjusting the currents outputted by the first bias module  110  and the second bias module  120 , the voltages at the terminals of the resistors R 1  and R 2  can also be adjusted, thereby adjusting the voltages at the bias nodes N 1  and N 2 . Consequently, the offset compensation device  300  can be used to compensate the offset voltage VOS at the input terminals of the differential amplifier A 1 . In some embodiments, the method  200  can also be used to operate the offset compensation device  300  to compensate the offset voltage VOS. 
     In summary, the offset compensation devices and the methods for operating the offset compensation devices provided by the embodiments of the present invention can compensate the offset current or the offset voltage in multiple stages so that the compensation can be made rapidly while the number of current control circuits can be reduced, thereby reducing the circuit area and the parasitic effects. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.