Patent Publication Number: US-11379716-B2

Title: Method and electronic apparatus for adjusting a neural network

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to U.S. Provisional Application Ser. No. 62/628,311, filed on Feb. 9, 2018 and U.S. Provisional Application Ser. No. 62/672,596, filed May 17, 2018 and U.S. Provisional Application Ser. No. 62/727,570, filed Sep. 6, 2018, which are herein incorporated by reference. 
    
    
     BACKGROUND 
     Field of Invention 
     The disclosure relates to a machine learning method. More particularly, the disclosure relates to a method for adjusting a convolutional neural network. 
     Description of Related Art 
     Machine learning technologies are utilized in many applications, such as artificial intelligence (AI), data mining, auto-pilot, etc. There are various types of neural networks developed to solve different kinds of problems. Among these neural networks, a convolutional neural network (CNN) is one of the popular neural networks. The convolutional neural network is usually used to solve image-related problems, such as object recognition. 
     In a convolutional neural network, multiple convolution layers including a variety of filters are utilized to match or extract features from a source image by a series of convolution calculations. In addition, some pooling layers or activation layers are also included in the convolutional neural network to process the input image and recognize an object from the input image. 
     SUMMARY 
     The disclosure provides a method for adjusting a convolutional neural network. The convolutional neural network includes convolution layers in a sequential order. The method includes following operations. Receptive field widths of the convolution layers in a first model of the convolutional neural network are determined. Channel widths of the convolution layers in the first model are reduced into reduced channel widths according to the receptive field widths of the convolution layers and an input image width. A structure of a second model of the convolutional neural network is formed according to the reduced channel widths. The second model of the convolutional neural network is trained. 
     The disclosure also provides an electronic apparatus suitable for adjusting a convolution neural network. The electronic apparatus include a data storage and a processor. The data storage is configured to store a first model of the convolution neural network. The first model of the convolution neural network includes a plurality of convolution layers. The processor is coupled with the data storage. The processor is configured to determine receptive field widths of the convolution layers in the first model of the convolutional neural network. The processor is further configured to reduce channel widths of the convolution layers in the first model into reduced channel widths according to the receptive field widths of the convolution layers and an input image width. The processor is further configured to form a structure of a second model of the convolutional neural network according to the reduced channel widths. The processor is further configured to train the second model of the convolutional neural network. 
     It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure can be more fully understood by reading the following detailed description of the embodiment, with reference made to the accompanying drawings as follows: 
         FIG. 1  is a schematic diagram illustrating an electronic apparatus according to an embodiment of the disclosure. 
         FIG. 2  is a schematic diagram illustrating the first model of the convolution neural network according to an embodiment of the disclosure. 
         FIG. 3A  is a schematic diagram illustrating a convolution layers shown in 
         FIG. 2 . 
         FIG. 3B  is a schematic diagram illustrating another convolution layers shown in  FIG. 2 . 
         FIG. 3C  is a schematic diagram illustrating another convolution layers shown in  FIG. 2 . 
         FIG. 3D  is a schematic diagram illustrating another convolution layers shown in  FIG. 2 . 
         FIG. 3E  is a schematic diagram illustrating another convolution layers shown in  FIG. 2 . 
         FIG. 3F  is a schematic diagram illustrating another convolution layers shown in  FIG. 2 . 
         FIG. 4  is a schematic diagram illustrating a method for adjusting the convolutional neural network according to an embodiment of the disclosure. 
         FIG. 5A  is a schematic diagram illustrating a receptive field width corresponding to one convolution layer in  FIG. 2  and another receptive field width corresponding to another convolution layer in  FIG. 2  according to an embodiment of the disclosure. 
         FIG. 5B  is a schematic diagram illustrating a projection region on the input image corresponding to one feature point at the convolution output tensor according to an embodiment of the disclosure. 
         FIG. 6  is a schematic diagram illustrating the structure of the second model of the convolutional neural network with the reduced channel widths according to the embodiment. 
         FIG. 7  is a schematic diagram illustrating a first model with macroblocks according to an embodiment. 
         FIG. 8  is a schematic diagram illustrating a second model with macroblocks according to an embodiment. 
         FIG. 9  is a schematic diagram illustrating a second model with macroblocks according to another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     Reference is made to  FIG. 1 , which is a schematic diagram illustrating an electronic apparatus  100  according to an embodiment of the disclosure. The electronic apparatus  100  is suitable for adjusting a convolution neural network (CNN). 
     There are usually several convolution layers included in one convolution neural network. Each of the convolution layers may include several convolution filters for matching and identifying object-related features in images. If the convolution neural network includes more convolution filters in each convolution layers, it will be more precise in recognizing objects. At the same time, when the convolution neural network includes more convolution filters, a model size of the convolution neural network will increase correspondingly. When the model size of the convolution neural network is increased, it requires more time spent in training a model of the convolution neural network, more data storage space to store the model of the convolution neural network, and/or more computation time in recognizing an object. In an embodiment, the electronic apparatus  100  is utilized to reduce a model size of the convolution neural network by adjusting a structure of the model of the convolution neural network. 
     As shown in  FIG. 1 , the electronic apparatus  100  includes a data storage  120  and a processor  140 . The processor  140  is coupled with the data storage  120 . In an embodiment, the data storage can be implemented by a memory, a hard-disk, a cache, a non-transitory computer readable medium, a register, a data storage array or any equivalent data storage components. In an embodiment, the processor can be implemented by a central processing unit, a processing circuit, a graphic processing unit (GPU), an application-specific integrated circuit (ASIC) or any equivalent processing component. 
     In an embodiment, the data storage  120  stores a first model MD 1  of the convolution neural network. In an embodiment, the first model is a pre-trained model of the convolutional neural network. In an embodiment, the pre-trained model can be downloaded from a public convolution neural network library, such as ResNet, MobileNet, SqueezeNet, ShuffleNet, DenseNet, or alike. A structure of the pre-trained model (i.e., the first model MD 1 ) includes a specific amount of convolution layers, and the convolution layers have channel widths in default amounts. However, the first model MD 1  is not necessary downloaded from the public convolution neural network library. In another embodiment, the first model MD 1  can be trained by the processor  140  according to training data TD stored in the data storage  120 . 
     Reference is further made to  FIG. 2 , which is a schematic diagram illustrating the first model MD 1  of the convolution neural network according to an embodiment of the disclosure. In this embodiment, the first model MD 1  is assumed to include twelve convolution layers CL 0 , CL 1 , CL 2  . . . CL 11  in a sequential order. The convolution layer CL 0  is configured to receive and process an input image IMGin to generate a convolution output tensor CT 0 . The convolution output tensor CT 0  generated by the convolution layer CL 0  is received by the following convolution layer CL 1 , and the convolution layer CL 1  process the convolution output tensor CT 0  to generate another convolution output tensor CT 1 . The convolution output tensor CT 1  is received and processed by the following convolution layer CL 2  to generate another convolution output tensor CT 2 . Similarly, the convolution output tensors CT 3 -CT 11  are generated by the convolution layers CL 3 -CL 11  in the sequential order. In an embodiment, the input image IMGin as shown in  FIG. 2  can be provided by or included in the training data TD stored in the data storage  120 . 
     In the embodiment shown in  FIG. 2 , the first model MD 1  further includes two pooling layers PL 1  and PL 2 , a fully-connected layer FCL and an activation function layer AFL. In some embodiments, the activation function layer AFL may include a Softmax function layer, but the disclosure is not limited thereto. In some other embodiments, the activation function layer AFL may include a Softmin function layer, a Softmax2d function layer, a LogSoftmax function layer or an Adaptive Softmax (e.g., AdaptiveLogSoftmaxWithLoss) function layer. The pooling layers PL 1  and PL 2  are utilized to down-sample the convolution output tensors generated by the convolution layers, such that the first model MD 1  of the convolution neural network can integrate a local object feature into a high-level object feature. In this embodiment, each of the pooling layers PL 1  and PL 2  is configured to have a kernel size of 2×2 and a stride step equal to 2, but the disclosure is not limited thereto. In some other embodiments, the pooling layers can be configured to have a different kernel size and a different stride step. The fully-connected layer FCL and the activation function layer AFL are configured to link a result of the convolution output tensor CT 11  to one specific label LAB, such that the first model MD 1  is able to generate one label LAB corresponding to the input image IMGin. 
     In this embodiment, the first model MD 1  includes the convolution layers CL 0 -CL 11  with the channel widths in default amounts. For example, each of the convolution layers CL 0 -CL 3  has 16 different convolution filters for matching image features (i.e., the channel widths of output channels=16); each of the convolution layers CL 4 -CL 7  has 32 different convolution filters for matching image features (i.e., the channel widths of output channels=32); and, each of the convolution layers CL 8 -CL 11  has 64 different convolution filters for matching image features (i.e., the channel widths of output channels=64). As shown in  FIG. 2 , in the convolution layers CL 0 -CL 11 , the convolution layers around a beginning end (e.g., the convolution layers CL 0 -CL 3 ) adjacent to the input image IMGin has a lower channel width, and the convolution layers around a deeper end (e.g., the convolution layers CL 8 -CL 11 ) adjacent to a fully-connected layer FC of the first model MD 1  has a larger channel width. 
     A model size of the first model MD 1  is highly related to storage space required to store data in the convolution layers CL 0 -CL 11 . Reference is further made to  FIG. 3A , which is a schematic diagram illustrating the convolution layers CL 0  shown in  FIG. 2 . 
     As shown in  FIG. 3A , the convolution layer CL 0  (with the channel width equal to “16”) includes sixteen convolution filters F 1   a -F 16   a . The convolution filter F 1   a  is utilized to perform a convolution calculation with the input image IMGin to generate a convolution channel output CCH 1 . The convolution filter F 2   a  is utilized to perform a convolution calculation with the input image IMGin to generate a convolution channel output CCH 2 . The convolution filter F 3   a  is utilized to perform a convolution calculation with the input image IMGin to generate a convolution channel output CCH 3 . Similarly, the convolution filter F 16   a  is utilized to perform a convolution calculation with the input image IMGin to generate a convolution channel output CCH 16 . These convolution channel outputs CCH 1 -CCH 16  are integrated into the convolution output tensor CT 0 . 
     A storage size occupied by the convolution layer CL 0  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         total 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         amount 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameters 
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         data 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         bits 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         each 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameter 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         3 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         16 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     432 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     In the equation above, Cin means an amount of input channels to the convolution layer CL 0 , k means a width/height of each convolution filter (F 1   a -F 16   a ) in the convolution layer CL 0 , k is a positive integer ≥1, Cout means an amount of output channels from the convolution layer CL 0 , and DBits means how many data bits are carried in each pixel on one convolution filter. 
     It is noticed that the sizes of convolution filters F 1   a -F 16   a  in the embodiment shown in  FIG. 3A  are assumed to be 3×3 for demonstration. However, the sizes of the convolution filters F 1   a -F 16   a  are not limited to 3×3. In other embodiment, the convolution filters F 1   a -F 16   a  can be replaced by 2×2, 2×3, 3×4, 4×4 or other size configurations. In order to simplify the demonstration, the convolution filters in other convolution layer CL 1 -CL 11  are also assumed to be in size of 3×3, but the disclosure is not limited thereto. 
     Reference is further made to  FIG. 3B , which is a schematic diagram illustrating the convolution layers CL 1  shown in  FIG. 2 . As shown in  FIG. 3B , the convolution layer CL 1  also includes sixteen convolution filters F 1   b -F 16   b . The convolution filters F 1   b -F 16   b  are utilized to perform convolution calculation respectively on the convolution output tensor CT 0  to generate a convolution output tensor CT 1 . 
     A storage size occupied by the convolution layer CL 1  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         total 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         amount 
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                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameters 
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         data 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         bits 
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                         each 
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                         parameter 
                       
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                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         16 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         16 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     2304 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     In the embodiment shown in  FIG. 2 , a storage size occupied by the convolution layer CL 2  in the first model MD 1  and another storage size occupied by the convolution layer CL 3  in the first model MD 1  are similar to the storage size occupied by the convolution layer CL 1 . 
     Reference is further made to  FIG. 3C , which is a schematic diagram illustrating the convolution layers CL 4  shown in  FIG. 2 . As shown in  FIG. 3C , the convolution layer CL 4  (with a channel width of input channels equal to “16” and another channel width of the output channels equal to “32”) include thirty-two convolution filters F 1   c -F 32   c.    
     In this embodiment shown in  FIG. 2  and  FIG. 3C , a convolution output tensor CT 3  generated by the convolution layer CL 3  is down-sampled by the pooling layer PL 1  of the first model MD 1  into a sampled convolution output tensor CT 3   d . In this embodiment, the pooling layer PL 1  is utilized to merge 2×2 feature points in the convolution output tensor CT 3  into one feature point in the sampled convolution output tensor CT 3   d . In other words, the pooling layer PL 1  in the embodiment has a stride step equal to “2”, but the disclosure is not limited thereto. In this case, the sampled convolution output tensor CT 3   d  will be in dimensions at height=16, width=16 and channel=16. In other words, the dimensions of the sampled convolution output tensor CT 3   d =16×16×16. 
     The convolution filters F 1   c -F 32   c  are utilized to perform convolution calculation respectively on the sampled convolution output tensor CT 3   d  to generate a convolution output tensor CT 4 . 
     A storage size occupied by the convolution layer CL 4  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
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                         total 
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                         ⁢ 
                         amount 
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                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameters 
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         data 
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                         bits 
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                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         16 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         32 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     4608 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     Reference is further made to  FIG. 3D , which is a schematic diagram illustrating the convolution layers CL 5  shown in  FIG. 2 . As shown in  FIG. 3D , the convolution layer CL 5  (with a channel width of input channels equal to “32” and another channel width of the output channels equal to “32”) include thirty-two convolution filters F 1   d -F 32   d.    
     A storage size occupied by the convolution layer CL 5  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
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                         total 
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                         amount 
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                         of 
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                         ⁢ 
                         parameters 
                       
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                     × 
                     
                       ( 
                       
                         data 
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                         bits 
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                         each 
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                         parameter 
                       
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                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         32 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         32 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     9216 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     In the embodiment shown in  FIG. 2 , a storage size occupied by the convolution layer CL 6  in the first model MD 1  and another storage size occupied by the convolution layer CL 7  in the first model MD 1  are similar to the storage size occupied by the convolution layer CL 5 . 
     Reference is further made to  FIG. 3E , which is a schematic diagram illustrating the convolution layers CL 8  shown in  FIG. 2 . As shown in  FIG. 3E , the convolution layer CL 8  (a channel width of input channels equal to “32” and another channel width of the output channels equal to “64”) include sixty-four convolution filters F 1   e -F 64   e.    
     A storage size occupied by the convolution layer CL 8  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
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                         total 
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                         amount 
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                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameters 
                       
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                     × 
                     
                       ( 
                       
                         data 
                         ⁢ 
                         
                             
                         
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                         bits 
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                         each 
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                         parameter 
                       
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                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         32 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         64 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     18432 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     Reference is further made to  FIG. 3F , which is a schematic diagram illustrating the convolution layers CL 9  shown in  FIG. 2 . As shown in  FIG. 3F , the convolution layer CL 9  (with a channel width of input channels equal to “64” and another channel width of the output channels equal to “64”) include sixty-four convolution filters F 1   f -F 64   f.    
     A storage size occupied by the convolution layer CL 9  in the first model MD 1  can be calculated as: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         a 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         total 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         amount 
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                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameters 
                       
                       ) 
                     
                     × 
                     
                       ( 
                       
                         data 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         bits 
                         ⁢ 
                         
                             
                         
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                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         each 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         parameter 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         Cin 
                         × 
                         
                           k 
                           2 
                         
                         × 
                         Cout 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     
                       ( 
                       
                         64 
                         × 
                         
                           3 
                           2 
                         
                         × 
                         64 
                       
                       ) 
                     
                     × 
                     DBits 
                   
                 
               
             
             
               
                 
                   = 
                   
                     36864 
                     × 
                     
                       DBits 
                       . 
                     
                   
                 
               
             
           
         
       
     
     In the embodiment shown in  FIG. 2 , a storage size occupied by the convolution layer CL 10  in the first model MD 1  and another storage size occupied by the convolution layer CL 11  in the first model MD 1  are similar to the storage size occupied by the convolution layer CL 9 . 
     An embodiment of the disclosure, the electronic apparatus  100  adjusts a structure of the convolution layers CL 0 -CL 11  by reducing channel numbers of the convolution layers CL 0 -CL 11 , so as to reduce the model size of the first model MD 1  of the convolutional neural network. 
     Based on that the convolution layers CL 8 -CL 11  at the deeper end (adjacent to the fully-connected layer FCL) occupy more storage space compared to the convolution layers (e.g., CL 0 -CL 3 ) adjacent to the beginning end (adjacent to the input image IMGin), the electronic apparatus  100  utilize an adjustment method to reduce in a backward order opposite to the sequential order. In other words, the electronic apparatus  100  and the adjustment method will reduce the channel numbers of the convolution layers (e.g., CL 8 -CL 11 ) around the deeper end first before reducing the channel numbers of the convolution layers around the beginning end. 
     Reference is further made to  FIG. 4 , which is a schematic diagram illustrating a method  200  for adjusting the convolutional neural network according to an embodiment of the disclosure. As shown in  FIG. 1  and  FIG. 4 , the processor  140  of the electronic apparatus  100  is configured to execute the method  200  in  FIG. 4  to determine how to adjust the structure of the first model MD 1  of the convolutional neural network into a second model MD 2  of the convolutional neural network. The electronic apparatus  100  utilizes the method  200  to effectively reduce a model size of the second model MD 2  (compared to the first model MD 1 ) and also to retain the preciseness of the object recognition performed by the second model MD 2  of the convolutional neural network. Details about how to adjust the structure of the convolutional neural network are explained in following paragraphs. 
     As shown in  FIG. 4 , operation S 210  of the method  200  is executed to determine receptive field widths of the convolution layers CL 0 -CL 11  in the first model MD 1  of the convolutional neural network. Each of the convolution layers CL 0 -CL 11  may have a receptive field width different from another convolution layer. Reference is further made to  FIG. 5A , which is a schematic diagram illustrating a receptive field width RFW 0  corresponding to the convolution layer CL 0  in  FIG. 2  and another receptive field width RFW 1  corresponding to the convolution layer CL 1  in  FIG. 2  according to an embodiment of the disclosure. 
       FIG. 5A  shows a schematic view of one output channel layer of the convolution output tensor CT 0  generated by the convolution layer CL 0  and a schematic view of one output channel layer of the convolution output tensor CT 1  generated by the convolution layer CL 1  relative to the input image IMGin. 
     As shown in  FIG. 5A , a feature point FP 0  on the convolution output tensor CT 0  is calculated by convolution between one 3×3 convolution filter and a projection region R 0  on the input image IMGin. Therefore, the feature point FP 0  on the convolution output tensor CT 0  will be affected by the 3×3 projection region R 0 . In this case, the receptive field width RFW 0  of the convolution layer CL 0  is determined to be 3. 
     As shown in  FIG. 5A , another feature point FP 1  on the convolution output tensor CT 1  is calculated by convolution between one 3×3 convolution filter and a projection region R 1   a  on the convolution output tensor CT 0 . Because the convolution output tensor CT 0  is calculated by convolution between one 3×3 convolution filter and the input image IMGin in advance. Therefore, the feature point FP 1  on the convolution output tensor CT 1  will be affected by the 5×5 projection region R 1   b  on the input image IMGin. In this case, the receptive field width RFW 1  of the convolution layer CL 1  is determined to be 5. 
     Similarly, the receptive field width will be further accumulated in the following convolution layer CL 2 -CL 11 . A receptive field width of the convolution layer CL 2  is determined to be 7. A receptive field width of the convolution layer CL 3  is determined to be 9. After the pooling layer PL 1  and another convolution calculation at the convolution layer CL 4 , a receptive field width of the convolution layer CL 4  is determined to be 14. A receptive field width of the convolution layer CL 5  is determined to be 18. A receptive field width of the convolution layer CL 6  is determined to be 22. A receptive field width of the convolution layer CL 7  is determined to be 26. After the pooling layer PL 2  and another convolution calculation at the convolution layer CL 8 , a receptive field width of the convolution layer CL 8  is determined to be 36. A receptive field width of the convolution layer CL 9  is determined to be 44. A receptive field width of the convolution layer CL 10  is determined to be 52. A receptive field width of the convolution layer CL 11  is determined to be 60. The receptive field widths of the convolution layers CL 0 -CL 11  determined in S 210  are listed in the following TABLE 1. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
             
            
               
                 conv. layer 
                 CL0 
                 CL1 
                 CL2 
                 CL3 
                 CL4 
                 CL5 
                 CL6 
                 CL7 
               
               
                   
               
               
                 channel 
                 16 
                 16 
                 16 
                 16 
                 32 
                 32 
                 32 
                 32 
               
               
                 width 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 R.F. width 
                 3 
                 5 
                 7 
                 9 
                 14 
                 18 
                 22 
                 26 
               
               
                 classification 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 conv. layer 
                 CL8 
                 CL9 
                 CL10 
                 CL11 
               
               
                   
               
               
                 channel 
                 64 
                 64 
                 64 
                 64 
               
               
                 width 
                   
                   
                   
                   
               
               
                 R.F. width 
                 36 
                 44 
                 52 
                 60 
               
               
                 classification 
                 B 
                 E 
                 E 
                 E 
               
               
                   
                 (or E) 
               
               
                   
               
            
           
         
       
     
     Reference is further made to  FIG. 5B , which is a schematic diagram illustrating a projection region R 2  on the input image IMGin corresponding to one feature point FP 2  at the convolution output tensor CT 1  according to an embodiment of the disclosure. As shown in  FIG. 5B , the feature point FP 2  is affected by the projection region R 2  on the input image IMGin. However, as shown in  FIG. 5B , the projection region R 2  exceeds a boundary of the input image IMGin. The area of the projection region R 2  outside the boundary of the input image IMGin is called padding area PAD. The padding area PAD does not include real image data and is filled with inactive data, e.g., “0”, for the convolution calculation. In this case, the feature point FP 2  is calculated based on 80% of the real image data and 20% of the padding data. 
     A feature point calculated based on more padding data will be less effective in object recognition. A feature point calculated based on more real image data will be more effective in object recognition. 
     After operation S 210  of determining receptive field widths of the convolution layers CL 0 -CL 11 , the method  200  performs operation S 220  for reducing channel widths of the convolution layers in the first model MD 1  into reduced channel widths according to aforesaid receptive field widths of the convolution layers CL 0 -CL 11 , by comparing the receptive field widths of the convolution layers CL 0 -CL 11  with an input image width of the input image IMGin. 
     In an embodiment as shown in  FIG. 4 , the operation S 220  includes operations S 221 , S 222  and S 223 . 
     As shown in  FIG. 4 , operation S 221  of the method  200  is executed to classify each of the convolution layers CL 0 -CL 11  in the first model MD 1  into one of a base layer group and an enhancement layer group by comparing the receptive field widths of the convolution layers CL 0 -CL 11  in the first model MD 1  with an input image width of the input image IMGin. 
     In the embodiment, the input image IMGin is assumed to be 32×32. In other words, the input image width of the input image IMGin is equal to 32. 
     The convolution layers CL 0 -CL 11  are classified into the base layer group or the enhancement layer group by compared their receptive field widths (3, 5, 7, 9, 14, 18, 22, 26, 36, 44, 52 and 60) with the input image width “32”. As shown in TABLE 1, the receptive field widths (3, 5, 7, 9, 14, 18, 22 and 26) of the convolution layers CL 0 -CL 7  is lower than the input image width “32”, and the receptive field widths (36, 44, 52 and 60) of the convolution layers CL 8 -CL 11  is larger than the input image width “32”. 
     In an embodiment as shown in TABLE 1, the convolution layers CL 0 -CL 7  is classified into the base layer group because the receptive field widths (3, 5, 7, 9, 14, 18, 22 and 26) of the convolution layers CL 0 -CL 7  are compared to be lower than the input image width “32”, and the convolution layers CL 9 -CL 11  is classified into the enhancement layer group because the receptive field widths (44, 52 and 60) of the convolution layers CL 9 -CL 11  are compared to be larger than the input image width “32”. It is noticed that the receptive field width (36 in this embodiment) of the convolution layer CL 8  which is the first layer to exceed the input image width (32 in this embodiment) is still classified into the base layer group in this embodiment as shown in TABLE 1. However, this disclosure is not limited thereto. 
     In another embodiment, the convolution layers CL 0 -CL 7  (with receptive field widths lower than the input image width) are classified into the base layer group, and the convolution layers CL 8 -CL 11  (with receptive field widths exceeding the input image width) are classified into the enhancement layer group. 
     In the embodiment illustrated in TABLE 1, the input image width “32” is utilized to a threshold for the receptive field size of convolution layers to classify the base layer group and the enhancement layer group. In this case, the input image width is equal to the threshold for the receptive field size of convolution layers. However, the disclosure is not limited thereto. 
     In another embodiment, a threshold to classify the base layer group and the enhancement layer group can be configured at (X %*the input image width). In other words, the threshold is positively related to the input image width. 
     In an embodiment, X is a number between 0 and 100, but the disclosure is not limited thereto. In another embodiment, when the electronic apparatus  100  and the method  200  tend to elevate a prediction accuracy of the convolutional neural network to be trained, the X can be a number between 0 and 200. X affects a compression ratio in the method  200 . When X is configured to be lower, more convolution layers will be classified into the enhancement layer group, and fewer convolution layers will be classified into the base layer group, such that channel widths on more convolution layers will be reduced (in following operation S 223 ). When X is configured to be higher, more convolution layers will be classified into the base layer group, and fewer convolution layers will be classified into the enhancement layer group, such that channel widths on fewer convolution layers will be reduced (in following operation S 223 ). 
     In general, the convolution layers closer to the deeper end tend to be classified into the enhancement layer group, and the convolution layers closer to the beginning end tends to be classified into the base layer group. 
     As shown in  FIG. 4 , operation S 222  of the method  200  is executed to determine redundancy ratios of the convolution layers CL 0 -CL 11  in the first model MD 1  according to a partial calculation amount of the enhancement layer group relative to a total calculation amount of the base layer group and the enhancement layer group. 
     Some details related to how to calculate the redundancy ratios of the convolution layers CL 0 -CL 11  in S 222  are listed in the following TABLE 2. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
             
            
               
                 conv. layer 
                 CL0 
                 CL1 
                 CL2 
                 CL3 
                 CL4 
                 CL5 
                 CL6 
                 CL7 
               
               
                   
               
               
                 classification 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
               
               
                 flop counts 
                 FC0 
                 FC1 
                 FC2 
                 FC3 
                 FC4 
                 FC5 
                 FC6 
                 FC7 
               
               
                 Eff. Prob. 
                 35% 
                 52% 
                 40% 
                 36% 
                 42% 
                 56% 
                 48% 
                 51% 
               
               
                 Eff. flop cnts 
                 EFC0 
                 EFC1 
                 EFC2 
                 EFC3 
                 EFC4 
                 EFC5 
                 EFC6 
                 EFC7 
               
               
                 redundancy 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 ratio 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 conv. layer 
                 CL8 
                 CL9 
                 CL10 
                 CL11 
               
               
                   
               
               
                 classification 
                 B 
                 E 
                 E 
                 E 
               
               
                 flop counts 
                 FC8 
                 FC9 
                 FC10 
                 FC11 
               
               
                 Eff. Prob. 
                 39% 
                 41% 
                 57% 
                 52% 
               
               
                 Eff. flop cnts 
                 EFC8 
                 EFC9 
                 EFC10 
                 EFC11 
               
               
                 redundancy 
                 0 
                 0.13 
                 0.28 
                 0.4 
               
               
                 ratio 
               
               
                   
               
            
           
         
       
     
     Firstly, flop counts in convolution calculation at every convolution layers CL 0 -CL 11  are known and fixed number. A flop count FC 0  at the convolution layers CL 0  is decided by how many times of multiplication and adding are required at the convolution layer CL 0  to generate the convolution output tensor CT 0 . A flop count FC 1  at the convolution layers CL 1  is decided by how many times of multiplication and adding are required at the convolution layer CL 1  to generate the convolution output tensor CT 1 . Similar, flop counts FC 2 -FC 11  are decided by how many times of multiplication and adding are required at the convolution layers CL 2 -CL 11  to generate the convolution output tensors CT 2 -CT 11 . 
     In an embodiment, the first model MD 1  of the convolutional neural network further includes twelve activation layers (not shown in figures). Each of the activation layers are arranged after one of the convolution layers CL 0 -CL 11 . In one embodiment, the activation layers can be rectified linear units (ReLU). The rectified linear units are used to replace negative data into “0” and remain all positive data in the convolution output tensor CT 0 -CT 11  generated by each of the convolution layers CL 0 -CL 11 . In this embodiment, a convolution output tensor generated by each of the convolution layers is rectified by one of the activation layers into non-zero outputs and zero outputs. However, the activation layers are not limited to the rectified linear units (ReLU). In some embodiments, the activation layers may be selected from at least one or a combination of ELU, Sigmoid, Softplus, Tanh, or any equivalent activation layer. In operation S 222 , the processor  140  calculates an effective probability respectively for each of the convolution layers CL 0 -CL 11  according to a ratio of the non-zero outputs among all outputs in the convolution output tensor CT 0 -CT 11 . It is assumed that there are 35% non-zero outputs among all outputs in the convolution output tensor CT 0 . In this case, an effective flop count EFC 0  for the convolution layers CL 0  is calculated by a product between the original flop counts FC 0  and the effective probability “35%”. In other words, the effective flop count EFC 0 =FC 0 *35%. 
     It is assumed that there are 52%, 40% 36%, 42%, 56%, 48%, 51%, 39%, 41%, 57% and 52% non-zero outputs among all outputs in the convolution output tensor CT 1 , CT 2 , CT 3 , CT 4 , CT 5 , CT 6 , CT 7 , CT 8 , CT 9 , CT 10  and CT 11 . The effective flop count EFC 1  of the convolution layers CL 1  is calculated by a product between the original flop counts FC 1  and the corresponding effective probability “52%”, and the effective flop count EFC 2  of the convolution layers CL 2  is calculated by a product between the original flop counts FC 2  and the corresponding effective probability “40%”. 
     Based on aforesaid effective flop counts EFC 0 -EFC 8  of the convolution layers CL 0 -CL 8  in the base layer group and the effective flop counts EFC 9 -EFC 11  of the convolution layers CL 9 -CL 11  in the enhancement layer group, the processor  140  execute operation S 222  to determine the redundancy ratios of the convolution layers CL 0 -CL 11  in the first model MD 1 . 
     Firstly, a redundancy ratio of the convolution layer CL 11  is determined according to a partial calculation amount of the enhancement layer group relative to a total calculation amount, as:
 
(EFC9+EFC10+EFC11)/(EFC0+EFC1+EFC2 . . . EFC10+EFC11).
 
     In other words, a redundancy ratio of the convolution layer CL 11  is determined by the sum of the effective flop counts (EFC 9 -EFC 11 ) in the enhancement layer group divided by a sum of the effective flop counts in all convolution layer CL 0 -CL 11 . As shown in TABLE 2, the redundancy ratio of the convolution layer CL 11  is determined to be “0.4”. 
     Secondly, a redundancy ratio of the convolution layer CL 10 , according to a partial calculation amount of the enhancement layer group relative to a total calculation amount, as:
 
(EFC9+EFC10)/(EFC0+EFC1+EFC2 . . . EFC9+EFC10).
 
     In other words, a redundancy ratio of the convolution layer CL 10  is determined by the sum of the effective flop counts (EFC 9  and EFC 10 ) in the enhancement layer group of the convolution layers until the convolution layer CL 10  itself divided by a sum of the effective flop counts in all convolution layer CL 0 -CL 10  from the first one of the convolution layers until the convolution layer CL 10  itself. As shown in TABLE 2, the redundancy ratio of the convolution layer CL 10  is determined to be “0.28”. 
     Thirdly, a redundancy ratio of the convolution layer CL 9  is determined, according to a partial calculation amount of the enhancement layer group relative to a total calculation amount, as:
 
(EFC9)/(EFC0+EFC1+EFC2 . . . EFC8+EFC9).
 
     In other words, a redundancy ratio of the convolution layer CL 9  is determined by the effective flop count EFC 9  in the enhancement layer group of the convolution layers until the convolution layer CL 9  divided by a sum of the effective flop counts in all convolution layer CL 0 -CL 9  from the first one of the convolution layers until the convolution layer CL 9  itself. As shown in TABLE 2, the redundancy ratio of the convolution layer CL 9  is determined to be “0.13”. 
     Afterward, the redundancy ratios of the convolution layers CL 0 -CL 8  are determined to be zero, because there is no convolution layer classified into the enhancement layer group from CL 0  to CL 8 . 
     As shown in  FIG. 4 , operation S 223  of the method  200  is executed to reduce channel widths of the convolution layers CL 0 -CL 11  in the first model MD 1  according to the redundancy ratios into reduced channel widths. 
     Some details related to how to calculate the reduced channel widths of the convolution layers CL 0 -CL 11  in S 223  are listed in the following TABLE 3. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
             
            
               
                 conv. layer 
                 CL0 
                 CL1 
                 CL2 
                 CL3 
                 CL4 
                 CL5 
                 CL6 
                 CL7 
               
               
                   
               
               
                 channel 
                 16 
                 16 
                 16 
                 16 
                 32 
                 32 
                 32 
                 32 
               
               
                 width 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 redundancy 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 ratio 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 reduced 
                 16 
                 16 
                 16 
                 16 
                 32 
                 32 
                 32 
                 32 
               
               
                 channel 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                 width 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 conv. layer 
                 CL8 
                 CL9 
                 CL10 
                 CL11 
               
               
                   
               
               
                 channel 
                 64 
                 64 
                 64 
                 64 
               
               
                 width 
                   
                   
                   
                   
               
               
                 redundancy 
                 0 
                 0.13 
                 0.28 
                 0.4 
               
               
                 ratio 
                   
                   
                   
                   
               
               
                 reduced 
                 64 
                 57 
                 50 
                 46 
               
            
           
           
               
               
               
               
               
               
            
               
                 channel 
                   
                   
                   
                   
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 width 
                   
                   
                   
                   
                   
                   
                   
                   
               
               
                   
               
            
           
         
       
     
     In operation S 223 , the processor  140  is configured to calculate the reduced channel widths of the convolution layers CL 0 -CL 11  according to original channel widths in the first model MD 1  and the corresponding redundancy ratios of the convolution layers CL 0 -CL 11 . 
     In the embodiment shown in TABLE 3, a reduced channel width of the convolution layers CL 11  is calculated by: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         original 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         channel 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         width 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         CL 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         11 
                       
                       ) 
                     
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         + 
                         
                           redundancy 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           ratio 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           of 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           CL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           11 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     64 
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     1.4 
                   
                 
               
             
             
               
                 
                   = 
                   46. 
                 
               
             
           
         
       
     
     In the embodiment shown in TABLE 3, a reduced channel width of the convolution layers CL 10  is calculated by: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         original 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         channel 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         width 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         CL 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         10 
                       
                       ) 
                     
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         + 
                         
                           redundancy 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           ratio 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           of 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           CL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           10 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     64 
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     1.28 
                   
                 
               
             
             
               
                 
                   = 
                   50. 
                 
               
             
           
         
       
     
     In the embodiment shown in TABLE 3, a reduced channel width of the convolution layers CL 9  is calculated by: 
     
       
         
           
             
               
                 
                   
                     
                       ( 
                       
                         original 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         channel 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         width 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         of 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         CL 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         9 
                       
                       ) 
                     
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         + 
                         
                           redundancy 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           ratio 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           of 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           CL 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           9 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     64 
                     ⁢ 
                     
                       / 
                     
                     ⁢ 
                     1.13 
                   
                 
               
             
             
               
                 
                   = 
                   
                     56.637 
                     ≈ 
                     57. 
                   
                 
               
             
           
         
       
     
     In the embodiment shown in TABLE 3, the channel widths of the convolution layers CL 0 -CL 8  are not reduced because their redundancy ratios are determined to be zero. 
     In aforesaid embodiment, a channel width of a M th  convolution layer of the first model is reduced to a lower channel width compared to another channel width of a (M−1) th  convolution layer of the first model. M is a positive integer. For example, the reduced channel width of convolution layer CL 11  is configured to be “46”, which is lower than the reduce channel width “50” of convolution layer CL 10 . 
     In other words, the channel width in the M th  convolution layer is reduced with a higher proportion compared to the channel width in the (M−1) th  convolution layer. For example, the channel width of convolution layer CL 11  is reduced by 28.125% from 64 to 46; the channel width of convolution layer CL 10  is reduced by 21.875% from 64 to 50; and, the channel width of convolution layer CL 9  is reduced by 10.9375% from 64 to 57. The channel width of convolution layer CL 11  is reduced with a higher proportion (28.125%) compared to the convolution layer CL 10  (reduced by 21.875%). Similarly, the channel width of convolution layer CL 10  is reduced with a higher proportion (21.875%) compared to the convolution layer CL 9  (reduced by 10.9375%). 
     In aforesaid embodiment of the electronic apparatus  100  and the method  200 , a channel width of the convolution layer closer to the deeper end will be reduced more than another channel width of the convolution layer closer to the beginning end. The convolution layer (e.g., CL 9 -CL 11 ) closer to the deeper end will have a larger receptive field width, such that the corresponding convolution output tensors (CT 9 -CT 11 ) will include a larger portion of outputs affected by padding data (referring to the padding area PAD shown in  FIG. 5B ). Therefore, reducing the convolution filters on the convolution layer (e.g., CL 9 -CL 11 ) closer to the deeper end will induce minor influence to the preciseness of the object recognition compared to reducing the convolution filters on the convolution layer (e.g., CL 0 -CL 3 ) closer to the beginning end. On the other hand, because convolution filters on the convolution layer (e.g., CL 9 -CL 11 ) closer to the deeper end occupy more storage space, reducing the convolution filters on the convolution layer (e.g., CL 9 -CL 11 ) closer to the deeper end will help to reduce the model size of the convolution neutral network. 
     In operation S 250 , the processor  140  is configured to form a structure of the second model MD 2  of the convolutional neural network according to the reduced channel widths calculated in S 223  as shown in TABLE 3. Reference is further made to  FIG. 6 , which is a schematic diagram illustrating the structure of the second model MD 2  of the convolutional neural network with the reduced channel widths according to the embodiment shown in TABLE 3. As shown in  FIG. 6 , the second model MD 2  includes twelve convolution layers CL 0 , CL 1 , CL 2  . . . CL 11  in a sequential order. It is noticed that the channel widths of the convolution layers CL 9 -CL 11  are now reduced to 57, 50 and 46 in the second model MD 2 . 
     In operation S 260 , the processor  140  is configured to train the second model MD 2  of the convolutional neural network according to the training data TD stored in the stored in the data storage  120 . A model size of the second model MD 2  will be smaller than the model size of the first model MD 1  because the reduced channel widths at the convolution layers CL 9 -CL 11 . 
     In operation S 270 , the second model MD 2  of the convolutional neural network can be utilized by the processor  140  to process an incoming image IMGnew. In an embodiment, the second model MD 2  can be used by the processor  140  to recognize an incoming image IMGnew and generate a label IMGlab corresponding to the incoming image IMGnew as shown in  FIG. 1 . 
     However, the second model MD 2  is not limited to generate the label IMGlab corresponding to the incoming image IMGnew. In another embodiment, the second model MD 2  can be used by the processor  140  to detect an object (e.g., a human, a face, an animal, a vehicle or a building) within the incoming image IMGnew. In still another embodiment, the second model MD 2  can be used by the processor  140  to segment a foreground object (e.g., a human, a face, an animal, a vehicle or a building) from a background (e.g., a mountain view, a street view or an indoor decoration) of the incoming image IMGnew. 
     In aforesaid embodiments, the redundancy ratios in operation S 222  and the reduced channel widths in operation S 223  are determined respectively on each one of the convolution layers CL 0 -CL 11 . However, the disclosure is not limited thereto. In another embodiment, the convolution layers CL 0 -CL 11  can be grouped into several macroblocks and one redundancy ratio is determined to one of the macroblocks, so as to speed up and simplify the computation of the redundancy ratios and the reduced channel widths. 
     Reference is further made to  FIG. 7 ,  FIG. 8  and following TABLE 4.  FIG. 7  is a schematic diagram illustrating a first model MD 1  with macroblocks MB 0 -MB 2  according to an embodiment.  FIG. 8  is a schematic diagram illustrating a second model MD 2  with macroblocks MB 0 -MB 2  according to an embodiment. TABLE 4 shows some details in an embodiment related to how to calculate the reduced channel widths of the macroblocks MB 0 -MB 2 . 
     As shown in  FIG. 7 , the first model MD 1  of the convolutional neural network includes convolution layers CL 0 -CL 3 , a pooling layer PL 1 , convolution layers CL 4 -CL 7 , another pooling layer PL 2  and convolution layers CL 8 -CL 11  arranged in the sequential order. The convolution layers CL 0 -CL 3  are grouped into a macroblock MB 0 . The convolution layers CL 4 -CL 7  are grouped into another macroblock MB 1 . The convolution layers CL 8 -CL 11  are grouped into another macroblock MB 2 . 
     In this embodiment, operation S 223  in  FIG. 4  will reduce channel widths of the convolution layers in a macroblock if any one of the convolution layers in the macroblock is in the enhancement layer group. 
     Based the embodiments shown in TABLE 4, the convolution layers CL 0 -CL 3  in the macroblock MB 0  are all in the base layer group. The convolution layers CL 4 -CL 7  in the macroblock MB 1  are all in the base layer group. The channel widths of the macroblock MB 0  and the macroblock MB 1  will not be reduced. 
     The convolution layers CL 9 -CL 11  in the macroblock MB 2  are in the enhancement layer group. There, the channel widths of the macroblock MB 2  will be reduced to “46”. Details about how to calculate the reduced channel widths of the macroblock MB 2  can be referred to calculation of the reduced channel widths of the convolution layer CL 11  in the embodiment of TABLE 3. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
             
            
               
                 conv. layer 
                 CL0 
                 CL1 
                 CL2 
                 CL3 
                 CL4 
                 CL5 
                 CL6 
                 CL7 
               
               
                   
               
            
           
           
               
               
               
            
               
                 macro block 
                 MB0 
                 MB1 
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 classification 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
               
            
           
           
               
               
               
            
               
                 redundancy 
                 0 
                 0 
               
               
                 ratio 
                   
                   
               
               
                 reduced 
                 16 
                 32 
               
               
                 channel 
                   
                   
               
               
                 width 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 conv. layer 
                 CL8 
                 CL9 
                 CL10 
                 CL11 
               
               
                   
               
            
           
           
               
               
            
               
                 macro block 
                 MB2 
               
            
           
           
               
               
               
               
               
            
               
                 classification 
                 B 
                 E 
                 E 
                 E 
               
            
           
           
               
               
            
               
                 redundancy 
                 0.4 
               
               
                 ratio 
                   
               
               
                 reduced 
                 46 
               
               
                 channel 
                   
               
               
                 width 
               
               
                   
               
            
           
         
       
     
     Reference is further made to  FIG. 9  and following TABLE 5.  FIG. 9  is a schematic diagram illustrating a second model MD 2  with macroblocks MB 0 -MB 2  according to another embodiment. TABLE 5 shows some details in an embodiment related to how to calculate the reduced channel widths of the macroblocks MB 0 -MB 2  in  FIG. 9 . 
     In the embodiment shown in TABLE 5, it is assumed that the convolution layers CL 6 -CL 7  in the macroblock MB 1  are classified in the enhancement layer group, and the convolution layers CL 8 -CL 11  in the macroblock MB 2  are classified in the enhancement layer group. In addition, in the embodiment shown in TABLE 5, it is assumed that the convolution layers CL 0 -CL 3  in the macroblock MB 0  are classified in the base layer group, and the convolution layers CL 4 -CL 5  in the macroblock MB 1  are classified in the base layer group. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 5 
               
               
                   
               
             
            
               
                 conv. layer 
                 CL0 
                 CL1 
                 CL2 
                 CL3 
                 CL4 
                 CL5 
                 CL6 
                 CL7 
               
               
                   
               
            
           
           
               
               
               
            
               
                 macro block 
                 MB0 
                 MB1 
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 classification 
                 B 
                 B 
                 B 
                 B 
                 B 
                 B 
                 E 
                 E 
               
            
           
           
               
               
               
            
               
                 redundancy 
                 0 
                 0.15 
               
               
                 ratio 
                   
                   
               
               
                 reduced 
                 16 
                 28 
               
               
                 channel 
                   
                   
               
               
                 width 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 conv. layer 
                 CL8 
                 CL9 
                 CL10 
                 CL11 
               
               
                   
               
            
           
           
               
               
            
               
                 macro block 
                 MB2 
               
            
           
           
               
               
               
               
               
            
               
                 classification 
                 E 
                 E 
                 E 
                 E 
               
            
           
           
               
               
            
               
                 redundancy 
                 0.6 
               
               
                 ratio 
                   
               
               
                 reduced 
                 40 
               
               
                 channel 
                   
               
               
                 width 
               
               
                   
               
            
           
         
       
     
     In the embodiment shown in TABLE 5 and  FIG. 9 , when the channel widths in the macroblock MB 2  and the channel widths in the macroblock MB 1  are both reduced, the channel widths in the macroblock MB 2  are reduced with a higher proportion compared to the channel widths in the macroblock MB 1 . In the embodiment shown in TABLE 5, the channel widths in the macroblock MB 2  is reduced by 37.5% and the channel widths in the macroblock MB 1  is reduced by 12.5%. 
     In aforesaid embodiment of the electronic apparatus  100  and the method  200 , channel widths of the macroblock closer to the deeper end will be reduced more than channel widths of the macroblock closer to the beginning end. Therefore, reducing the convolution filters on the convolution layer in the macroblock closer to the deeper end will induce minor influence to the preciseness of the object recognition. On the other hand, reducing the convolution filters on the convolution layer of the macroblock closer to the deeper end will help to reduce the model size of the convolution neutral network. 
     Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.