Patent Publication Number: US-10788744-B2

Title: Extreme ultraviolet lithography mask blank manufacturing system and method of operation therefor

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a divisional of U.S. Non-Provisional application Ser. No. 14/139,415, filed Dec. 23, 2013, which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/778,402 filed Mar. 12, 2013, to each of which priority is claimed and each of which are incorporated herein by reference in their entireties. 
     The present application contains subject matter related to concurrently filed U.S. patent application Ser. No. 14/139,307. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto. 
     The present application contains subject matter related to concurrently filed U.S. patent application Ser. No. 14/139,371. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto. 
     The present application contains subject matter related to concurrently filed U.S. patent application Ser. No. 14/139,457. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto. 
     The present application contains subject matter related to concurrently filed U.S. patent application Ser. No. 14/139,507. The related application is assigned to Applied Materials, Inc. and the subject matter thereof is incorporated herein by reference thereto. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to extreme ultraviolet lithography blanks, and manufacturing and lithography systems for such extreme ultraviolet lithography blanks. 
     BACKGROUND 
     Extreme ultraviolet lithography (EUV, also known as soft x-ray projection lithography) is a contender to replace deep ultraviolet lithography for the manufacture of 0.13 micron, and smaller, minimum feature size semiconductor devices. 
     However, extreme ultraviolet light, which is generally in the 5 to 40 nanometer wavelength range, is strongly absorbed in virtually all materials. For that reason, extreme ultraviolet systems work by reflection rather than by transmission of light. Through the use of a series of mirrors, or lens elements, and a reflective element, or mask blank, coated with a non-reflective absorber mask pattern, the patterned actinic light is reflected onto a resist-coated semiconductor wafer. 
     The lens elements and mask blanks of extreme ultraviolet lithography systems are coated with reflective multilayer coatings of materials such as molybdenum and silicon. Reflection values of approximately 65% per lens element, or mask blank, have been obtained by using substrates that are coated with multilayer coatings that strongly reflect light essentially at a single wavelength within a extremely narrow ultraviolet bandpass; e.g., 12 to 14 nanometer bandpass for 13 nanometer ultraviolet light. 
     There are various classes of defects in semiconductor processing technology which cause problems. Opaque defects are typically caused by particles on top of the multilayer coatings or mask pattern which absorb light when it should be reflected. Clear defects are typically caused by pinholes in the mask pattern on top of the multilayer coatings through which light is reflected when it should be absorbed. And phase defects are typically caused by scratches and surface variations beneath the multilayer coatings which cause transitions in the phase of the reflected light. These phase transitions result in light wave interference effects which distort or alter the pattern that is to be exposed in the resist on the surface of the semiconductor wafer. Because of the shorter wavelengths of radiation which must be used for sub-0.13 micron minimum feature size, scratches and surface variations which were insignificant before now become intolerable. 
     While progress has been made in reducing or eliminating particle defects and work has been done on repair of opaque and clear defects in masks, to date nothing has been done to address the problem of phase defects. For deep ultraviolet lithography, surfaces are processed to maintain phase transitions below 60 degrees. Similar processing for extreme ultraviolet lithography is yet to be developed. 
     For an actinic wavelength of 13 nanometers, a 180 degree phase transition in the light reflected from the multilayer coating may occur for a scratch of as little as 3 nanometers in depth in the underlying surface. This depth gets shallower with shorter wavelengths. Similarly, at the same wavelength, surface variations more abrupt than one (1) nanometer rise over one hundred (100) nanometers run may cause similar phase transitions. These phase transitions can cause a phase defect at the surface of the semiconductor wafer and irreparably damage the semiconductor devices. 
     In the past, mask blanks for deep ultraviolet lithography have generally been of glass but silicon or ultra low thermal expansion materials have been proposed as alternatives for extreme ultraviolet lithography. Whether the blank is of glass, silicon, or ultra low thermal expansion material, the surface of the mask blank is made as smooth as possible by such processes a chemical mechanical polishing, magneto-rheological finishing, or ion beam polishing. The scratches that are left behind in such a process are sometimes referred to as “scratch-dig” marks, and their depth and width depend upon the size of the particles in the abrasive used to polish the mask blank. For visible and deep ultraviolet lithography, these scratches are too small to cause phase defects in the pattern on the semiconductor wafer. However, for extreme ultraviolet lithography, scratch-dig marks are a significant problem because they will appear as phase defects. 
     Due to the short illumination wavelengths required for EUV lithography the pattern masks used must be reflective mask instead of the transmissive masks used in current lithography. The reflective mask is made up of a precise stack of alternating thin layers of molybdenum and silicon, which creates a Bragg refractor or mirror. Because of the nature of the multilayer stack and the small feature size, any imperfections in the surface of the substrate on which the multilayer stack is deposited will be magnified and impact the final product. Imperfections on the scale of a few nanometers can show up as printable defects on the finished mask and need to be eliminated from the surface of the mask blank before deposition of the multilayer stack. 
     Typical masks used in optical lithography consist of a glass blank and a patterned chrome layer that blocks light transmission. In contrast in EUV lithography, the mask consists of a reflective layer and a patterned absorber layer. This architectural change is necessary due to the high absorbance of EUV light in most materials. 
     The reflector layer is a stack of 80 or more alternating layers of molybdenum and silicon. The precision for the layer thickness and smoothness of this stack is critical to achieve high reflectivity of the mask as well as line edge roughness, respectively. 
     Current technology employs glass polishing and cleaning processes to obtain a smooth substrate surface and ion beam deposition for the reflector layers. 
     This process flow does not meet the stringent defect specifications. The main causes of defects are pits and bumps in the glass substrate left behind by the polishing process as well as the subsequent cleaning. The ion beam deposition process further leaves particles embedded in and on top of the multilayer stack. 
     Thus, it is increasingly critical that answers be found to these problems and a system be developed that resolves these questions. In view of the ever-increasing commercial competitive pressures, along with growing consumer expectations, it is critical that answers be found for these problems. Additionally, the need to reduce costs, improve efficiencies and performance, and meet competitive pressures adds an even greater urgency to the critical necessity for finding answers to these problems. 
     Solutions to these problems have been long sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art. 
     SUMMARY 
     An embodiment of the present invention provides a processing system that includes: a vacuum chamber; a plurality of processing sub-systems attached around the vacuum chamber; and a wafer handling system in the vacuum chamber for moving a wafer among the plurality of processing systems without exiting from a vacuum. 
     An embodiment of the present invention provides a physical vapor deposition system for manufacturing an extreme ultraviolet blank comprising: a target comprising molybdenum, molybdenum alloy, or a combination thereof. 
     Certain embodiments of the invention have other steps or elements in addition to or in place of those mentioned above. The steps or element will become apparent to those skilled in the art from a reading of the following detailed description when taken with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a shown an integrated extreme ultraviolet (EUV) mask production system in accordance with an embodiment of the present invention. 
         FIG. 2  is the first multi-cathode source in accordance with an embodiment of the present invention. 
         FIG. 3  is a cross-section of the first multi-cathode source in accordance with an embodiment of the present invention. 
         FIG. 4  is the cross-section of the first multi-cathode source in operation in accordance with an embodiment of the present invention. 
         FIG. 5  is a mask blank which is square in shape and has a multi-layer stack in accordance with an embodiment of the present invention. 
         FIG. 6  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 7  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 8  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 9  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 10  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 11  is the mask blank in a supported position on a carrier in accordance with an embodiment of the present invention. 
         FIG. 12  is a method for making the mask blank with ultra-low defects. 
     
    
    
     DETAILED DESCRIPTION 
     The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be understood that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention. 
     In the following description, numerous specific details are given to provide a thorough understanding of the invention. However, it will be apparent that the invention may be practiced without these specific details. In order to avoid obscuring the present invention, some well-known circuits, system configurations, and process steps are not disclosed in detail. 
     The drawings showing embodiments of the system are semi-diagrammatic and not to scale and, particularly, some of the dimensions are for the clarity of presentation and are shown exaggerated in the drawing FIGs. Similarly, although the views in the drawings for ease of description generally show similar orientations, this depiction in the FIGs. is arbitrary for the most part. Generally, the invention can be operated in any orientation. 
     Where multiple embodiments are disclosed and described having some features in common, for clarity and ease of illustration, description, and comprehension thereof, similar and like features will be described with similar reference numerals. 
     For expository purposes, the term “horizontal” as used herein is defined as a plane parallel to the plane or surface of a mask blank, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “upper”, “over”, and “under”, are defined with respect to the horizontal plane, as shown in the figures. The term “on” indicates that there is direct contact between elements. 
     The term “processing” as used herein includes deposition of material or photoresist, patterning, exposure, development, etching, cleaning, and/or removal of the material or photoresist as required in forming a described structure. 
     Embodiments of the present invention use various established techniques for depositing silicon, silicon oxide, and related films of compatible thermal expansion coefficient by CVD, PVD, ALD, and flowable CVD to fill the pits and bury the defects. Once deposited, the films surface maybe smooth and flat enough for further multilayer stack deposition, or may then be smoothed further using a variety of established smoothing or polishing techniques, including CMP, annealing, or ion beam polishing. 
     Referring now to  FIG. 1 , therein is shown an integrated extreme ultraviolet (EUV) mask production system  100  in accordance with an embodiment of the present invention. The integrated EUV mask production system  100  is a processing system that processes wafers or blanks on a carrier and that includes a mask blank loading and carrier handling system  102  into which mask blanks  104  are loaded. 
     An airlock  106  provides access to a wafer handling vacuum chamber  108 . In the embodiment shown, the wafer handling vacuum chamber  108  contains two vacuum chambers, a first vacuum chamber  110  and a second vacuum chamber  112 . Within the first vacuum chamber  110  is a first wafer handling system  114  and in the second vacuum chamber  112  is a second wafer handling system  116 . 
     The wafer handling vacuum chamber  108  has a plurality of ports around its periphery for attachment of various other systems. The first vacuum chamber  110  has a degas system  118 , a first physical vapor deposition system  120 , a second physical vapor deposition system  122 , and a preclean system  124 . 
     The second vacuum chamber  112  has a first multi-cathode source  126 , a flowable chemical vapor deposition (FCVD) system  128 , a cure chamber  130 , and a second multi-cathode source  132  connected to it. The FCVD system  128  can deposit a planarization layer on a substrate, a blank, or a wafer  136  and the cure chamber can cure the planarization layer. The second multi-cathode source  132  can deposit a multi-layer stack of reflective material and other systems can deposit a capping layer. The planarization layer, the multi-layer stack, and the capping layer all become part of the wafer  136 . 
     The first wafer handling system  114  is capable of moving wafers, such as a wafer  134 , among the airlock  106  and to one or more of the various systems around the periphery of the first vacuum chamber  110  and through slit valves in a continuous vacuum. The second wafer handling system  116  is capable of moving wafers, such as a wafer  136 , around the second vacuum chamber  112  while maintaining the wafers in a continuous vacuum. The first wafer handling system  114 , such as a first processing sub-system, and the second wafer handling system  116 , such as a second processing sub-system, are capable of moving the wafer  136  selectively through one or all of the systems around the periphery of the first vacuum chamber  110  and the second vacuum chamber  112  to allow the various processes to be performed without having the wafer  136  exit from the vacuum until it is removed through the airlock  106 , such as an output. 
     Referring now to  FIG. 2 , therein is shown the first multi-cathode source  126  in accordance with an embodiment of the present invention. The first multi-cathode source  126  includes a base structure  200  with a cylindrical body portion  202  capped by a top adapter  204 . 
     The top adapter  204  has provisions for a number of cathode sources, such as cathode sources  206 ,  208 ,  210 ,  212 , and  214 , position around the top adapter  204 . 
     Referring now to  FIG. 3 , therein is shown a cross-section of the first multi-cathode source  126  in accordance with an embodiment of the present invention. The first multi-cathode source  126  has the base structure  200 , the cylindrical body portion  202 , and the top adapter  204 . 
     Within the base structure  200  is a rotating pedestal  300  upon which a wafer, such as the wafer  136 , can be secured. Above the rotating pedestal  300  is a covering ring  302  with an intermediate ring  304  above the covering ring  302 . A conical shield  306  is above the intermediate ring  304  and is surrounded by a conical adapter  308 . 
     A deposition area  310  for depositing material by physical vapor deposition (PVD) on the wafer  136  is surrounded by a rotating shield  312  to which a shroud  314  is affixed. Above the shroud  314  is one of a number of targets, such as a target  316 , the source of the deposition material, and a cathode  318 . 
     In an alternate embodiment, a number of individual shrouds  314  are each attached to an individual source and remain stationary as the rotating shield  312  rotates. 
     Referring now to  FIG. 4 , therein is shown the cross-section of the first multi-cathode source  126  in operation in accordance with an embodiment of the present invention. The cross-section of the first multi-cathode source  126  shows an off-angled conical deposition pattern  400  with the rotating pedestal  300  shown moved into position for a material deposition on a wafer  402  from the target  316 . 
     In operation, the rotating pedestal  300  with the wafer  136  is moved up into position where it is in view of the opening in the shroud  314  of  FIG. 3 . Depending on the design of the first multi-cathode source  126 , there can be multiple shrouds  314  attached to the top adapter  204  so each source has its own shroud, or with one should that rotates with the rotating shield  312 , or a single large rotating shield without the shroud. 
     The rotating shield  312  is then rotated among the various cathodes until the appropriate cathode  318  and target  316  are positioned to deposit material at an angle on the wafer  136  on the rotating pedestal  300 . 
     By rotating the pedestal  300 , the wafer  136  will receive a uniform deposition of target material on its surface. 
     Referring now to  FIG. 5 , therein is shown a mask blank  500  which is square in shape and has a multi-layer stack  502  in accordance with an embodiment of the present invention. 
     Referring now to  FIG. 6 , therein is shown the mask blank  500  in a supported position on a carrier  600  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing up and is supported on the carrier  600  on support pins  602  and is held in place laterally by retaining pins  604 . A wedge-shaped support  606  can also be used at the bottom edge of the mask blank  500 . 
     Referring now to  FIG. 7 , therein is shown the mask blank  500  in a supported position on a carrier  700  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing up and is supported on the carrier  700  on support pins  702  and is held in place laterally by retaining pins  704 . A wedge-shaped support  706  can also be used at the bottom edge of the mask blank  500 . 
     Referring now to  FIG. 8 , therein is shown the mask blank  500  in a supported position on a carrier  800  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing up and is supported on the carrier  800  on support pins  802  and is held in place laterally by retaining pins  804 . The carrier  800  is slightly thicker than the thickness of the support pins  802  and the thickness of the mask blank  500 . An edge exclusion cover mask  806  covers the edges of the mask blank  500  to prevent deposition of material in the edge areas of the multi-layer stack  502 . A wedge-shaped support  808  can also be used at the bottom edge of the mask blank  500 . 
     Referring now to  FIG. 9 , therein is shown the mask blank  500  in a supported position on a carrier  900  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing down and is supported on the carrier  900  on support pins  902  and is held in place laterally by retaining pins  904 . The bottom side of the carrier  900  has an opening  906  to allow for deposition from below. 
     Referring now to  FIG. 10 , therein is shown the mask blank  500  in a supported position on a carrier  1000  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing down and is supported on the carrier  1000  on support pins  1002  and is held in place laterally by retaining pins  1004 . The bottom side of the carrier  1000  has an opening  1006  to allow for deposition from below. 
     Referring now to  FIG. 11 , therein is shown the mask blank  500  in a supported position on a carrier  1100  in accordance with an embodiment of the present invention. The mask blank  500  has the multi-layer stack  502  facing down and is supported on the carrier  1100  on support pins  1102  and is held in place laterally by retaining pins  1104 . The bottom side of the carrier has an opening  1106  to allow for deposition from below. 
     Referring now to  FIG. 12 , therein is shown a method  1200  for making the EUV mask blank  500  of  FIG. 5  with ultra-low defects. The method  1200  begins with a mask blank being supplied to a vacuum in the EUV mask production system  100  of  FIG. 1 . 
     The mask blank is degassed and precleaned in a step  1202 . The planarization occurs in a step  1204 . The planarization layer is deposited by CVD and is cured in a step  1206 . The multi-layer deposition is performed by PVD in a step  1208  and the capping layer is applied in a step  1210 . The degassing, precleaning, planarization, multi-layer deposition, and capping layer application is all performed in the EUV mask production system  100  without removing the mask blank from the vacuum. 
     The integrated EUV mask production system  100  of  FIG. 1  can be used to make any type of lithographic blank, such as mask blanks and mirror blanks, as well as masks for a lithographic semiconductor manufacturing process. 
     Embodiments of the present invention provide an integrated tool concept for depositing the layer structure required on a EUV mask blank. These include smoothing layers to planarize defects on the glass blank (pits, scratches and particles in the few to tens of nm size range), the molybdenum and silicon multilayer stack deposition for the Bragg reflector, as well as the ruthenium capping layer (used to protect the molybdenum/silicon stack from oxidation). 
     By integrating these steps into one process tool, it has been found that it is possible to achieve better interface control as well as better defect performance by limiting the number of handling steps. 
     The substrate is placed on a carrier so that handling of the mask blank is minimized through multiple process steps. This will reduce the chance of handling-related particles on the substrate. 
     The use of a cluster tool also allows the integration of dry cleaning processes to improve substrate cleanliness and thus adhesion of the layer stack without breaking vacuum. 
     After loading the substrate into the integrated extreme ultraviolet (EUV) mask production system, the mask blank is first coated with a planarizing layer in a flowable CVD process, such as in the AMAT Eterna films, to fill pits and scratches on the substrate surface, as well as planarize any remaining small particles. 
     Next, the substrate is moved to the deposition chamber for the multi-layer deposition. The chamber integrates multiple targets so that the entire stack can be deposited in one chamber without the need to transfer the substrate. 
     The resulting system is straightforward, cost-effective, uncomplicated, highly versatile, and can be surprisingly and unobviously implemented by adapting known technologies, and are thus readily suited for efficiently and economically manufacturing EUV mask blanks. 
     Embodiments of the invention provide an atomically flat, low defect, smooth surface for an EUV mask blank. However, embodiments of the invention could also be used to manufacture other types of blanks, such as for mirrors. Over a glass substrate, embodiments of the invention can be used to form an EUV mirror. Further, embodiments of the invention can be applied to other atomically flat, low defect, smooth surface structures used in UV, DUV, e-beam, visible, infrared, ion-beam, x-ray, and other types of semiconductor lithography. Embodiments of the invention can also be to form various size structures that can range from wafer-scale to device level and even to larger area displays and solar applications. 
     Another important aspect of the present invention is that it valuably supports and services the historical trend of reducing costs, simplifying systems, and increasing performance. 
     These and other valuable aspects of the present invention consequently further the state of the technology to at least the next level. 
     While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the aforegoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations that fall within the scope of the included claims. All matters hithertofore set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.