Patent Publication Number: US-9900015-B2

Title: Temperature-compensated oscillator and device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation of U.S. patent application Ser. No. 14/518,161, filed on Oct. 20, 2014, which claims the priority under 35 U.S.C §119(a) from Korean Patent Application No. 10-2013-0130436 filed on Oct. 30, 2013, the disclosures of which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     1. Field 
     Embodiments of the inventive concept relate to an electronic circuit, and more particularly, to an oscillator to generate a clock signal and a device including the same. 
     2. Description of the Related Art 
     A ring oscillator is usually used to generate a reference clock signal. In order to minimize a frequency change with respect to a temperature change, a temperature-compensated current which is the same as a current generated in a band gap reference (BGR) circuit is usually used in a ring oscillator design. However, a circuit for generating the temperature-compensated current usually includes a single operational amplifier and a plurality of resistors, and therefore, it is hard to be implemented in a design for an ultra-low current (e.g., nano-current) operation such as a standby mode (or a stop mode). 
     An ultra-low current reference clock generator requires a stable frequency characteristic with respect to temperature change and a minimum operation current as well. However, it is hard to satisfy these requirements with a conventional design method that requires several resistance elements with a resistance ranging from several MΩ to several tens of MΩ. 
     SUMMARY 
     The present general inventive concept provides an oscillator to generate a stable oscillation signal with respect to a temperature change, and an electronic device having the same. 
     Additional features and utilities of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept. 
     The foregoing and/or other features and utilities of the present general inventive concept may be achieved by providing a temperature-compensated oscillator including an oscillation unit configured to generate an oscillation signal using an operating current and an operating voltage, a bias circuit configured to control the operating current so that a frequency of the oscillation signal increases as temperature increases, and a voltage generation unit configured to generate the operating voltage that varies with the temperature. The voltage generation unit compensates for a change in a frequency of the oscillation signal with respect to a change in the temperature complementarily with the bias circuit by controlling the operating voltage so that the frequency of the oscillation signal decreases as the temperature increases. 
     The oscillation unit may include an odd number of inverters connected in series in a ring shape and at least one current source of a first current source which is connected between a first operating voltage in the operating voltage and the inverters and is controlled by the bias circuit and a second current source which is connected to the inverters and a second operating voltage in the operating voltage and is controlled by the bias circuit. 
     The bias circuit may include a current source proportional to absolute temperature (PTAT) current source configured to generate the operating current that increases as the temperature increases. 
     The voltage generation unit may include an operating voltage generation transistor which is connected between a supply voltage and the first operating voltage and has a diode connection. 
     The voltage generation unit may further include an operating voltage generation transistor which is connected between a ground voltage and the second operating voltage and has a diode connection. 
     The voltage generation unit may further include a bulk voltage controller configured to control a bulk voltage of the operating voltage generation transistor in response to a digital control signal included of at least two bits. 
     The PTAT current source may include a first transistor having a gate and a drain connected in common to a first node, a fourth transistor having a gate and a drain connected in common to a third node, a fifth transistor having a gate connected to the third node and a drain connected to a fourth node, a sixth transistor having a source connected to the supply voltage, a gate connected to the fourth node, and a drain connected to the third node, a seventh transistor having a gate and a drain connected in common to the fourth node and a source connected to the supply voltage, and an eighth transistor having a gate connected to the fourth node, a source connected to the supply voltage, and a drain connected to the first node. 
     The first node may be connected to the second current source. 
     The PTAT current source may further include a second transistor having a gate connected to the first node and a drain connected to a second node and a third transistor having a gate and a drain connected in common to the second node and a source connected to the first operating voltage. The second node may be connected to the first current source. 
     The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a temperature-compensated oscillator including an oscillation unit configured to generate an oscillation signal using an odd number of inverters connected in series in a ring shape, a bias circuit configured to increase an operating current of each of the inverters as temperature increases, and at least one transistor of a first operating current generation transistor which is connected between a supply voltage and a first operating voltage and has a diode connection and a second operating current generation transistor which is connected between a ground voltage and a second operating voltage and has the diode connection. The temperature-compensated oscillator increases or decreases an operating voltage of the inverters according to an increase of the temperature. 
     The oscillation unit may include at least one current source of a first current source which is connected between the first operating voltage and the inverters and is controlled by the bias circuit and a second current source which is connected to the inverters and the second operating voltage and is controlled by the bias circuit. 
     The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing an electronic device including a temperature-compensated oscillator configured to generate an oscillation signal having an output frequency insensitive to a temperature change and a logic circuit configured to operate in response to the oscillation signal. The temperature-compensated oscillator includes an oscillation unit configured to generate the oscillation signal using an odd number of inverters connected in series in a ring shape, a bias circuit configured to increase an operating current of each of the inverters as temperature increases, and a voltage generation unit configured to increase an operating voltage put across both ends of each inverter as the temperature increases. 
     The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing a temperature-compensated oscillator usable with an electronic device, the oscillator including an oscillation unit having inverters as a ring oscillator to be supplied with an operating voltage and an operating current which are variable according to a temperature change and to output an oscillation signal such that a characteristic of the operating current and a characteristic of the operating voltage can be offset to maintain a frequency of the oscillation signal stable regardless of the temperature change. 
     The temperature-compensated oscillator may further include a bias circuit having transistors to generate the operating current to increase when a temperature increase, and a voltage generation unit to generate the operating voltage to be changed with the temperature. 
     The variable operating voltage and the variable operating current may be simultaneously applied to the corresponding inverters of the oscillation unit. 
     In the temperature-compensated oscillator, an association of the variable operating voltage and the variable operating current may reduce a variation of a frequency of the oscillation signal. 
     The oscillation unit may generate the oscillation signal with frequencies to be usable in corresponding different modes according to the operating voltage variable according to the temperature change and a further adjustment or the operating current variable according to the temperature change and a further adjustment. 
     The operating current may be supplied between the operating voltage and the corresponding inverters. 
     The oscillation signal may have a frequency with a variation within a range of about 2% with respect to a reference frequency in the temperature change between 20° C. and 80° C. 
     The foregoing and/or other features and utilities of the present general inventive concept may also be achieved by providing an electronic device including a temperature-compensated oscillator described above or hereinafter, and a logic circuit to receive the oscillation signal from the temperature-compensated oscillator to perform a function of the electronic device. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and/or other features and utilities of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which: 
         FIG. 1  is a schematic block diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 2  is a schematic circuit diagram illustrating an oscillation unit of  FIG. 1  according to an embodiment of the present general inventive concept; 
         FIG. 3  is an equivalent circuit diagram of the oscillation unit of  FIG. 2 ; 
         FIG. 4  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 5  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 6  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 7  is a circuit diagram illustrating a bias adjustment circuit usable with a bias circuit of  FIG. 4  according to an embodiment of the inventive concept; 
         FIG. 8  is a circuit diagram illustrating a bulk voltage control circuit usable with a voltage generation unit of  FIG. 5  according to an embodiment of the inventive concept; 
         FIG. 9  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 10  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 11  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 12  is a circuit diagram illustrating a temperature-compensated oscillator according to an embodiment of the inventive concept; 
         FIG. 13  is a graph illustrating a simulation result of an output frequency of a temperature-compensated oscillator according to an embodiment of the inventive concept and a simulation result of an output frequency of an oscillator according to a comparison example; and 
         FIG. 14  is a schematic block diagram illustrating an electronic device according to an embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the embodiments of the present general inventive concept, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the like elements throughout. The embodiments are described below in order to explain the present general inventive concept while referring to the figures. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present general inventive concept to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  is a schematic block diagram illustrating a temperature-compensated oscillator  1  according to an embodiment of the inventive concept.  FIG. 2  is a schematic circuit diagram illustrating an oscillation unit  100 A usable as an oscillation unit  100  of  FIG. 1  according to an embodiment of the present general inventive concept. Referring to  FIGS. 1 and 2 , the temperature-compensated oscillator  1  includes the oscillation unit  100 , a bias circuit  200 , and a voltage generation unit  300 . 
     The oscillation unit  100  generates an oscillation signal SO having an output frequency using first and second operating voltages VDD and VSS and an operating current I D . The oscillation signal SO is a reference clock signal and may be applied to a logic circuit (not illustrated) that operates in synchronization with the reference clock signal or a clock signal generated from the reference clock signal. The oscillation signal SO may be output to one or more components of an electronic device including the logic circuit so that a function of the electronic device can be performed according to the oscillation signal SO. 
     As illustrated in  FIG. 2 , the oscillation unit  100 A may be implemented as a ring oscillator that uses the first operating voltage VDD, the second operating voltage VSS, and an operating current I D , but the inventive concept is not limited thereto. The ring oscillator, i.e., the oscillation unit  100 A, may include an inverter chain  103  in which a plurality of (or the odd number of) inverters IV (IV 1  through IVn) (where “n” is an odd number) are connected in a ring shape. The oscillation unit  100 A may include one or more current sources. It is possible that the oscillation unit  100   a  may include at least two current sources  101  ( 101 - 1  through  101 - n ) and  102  ( 102 - 1  through  102 - n ) to provide the operating current I D  to the inverters IV (IV 1  through IVn). 
     Each of the first current sources  101  ( 101 - 1  through  101 - n ) is connected between the first operating voltage VDD and a corresponding one of the inverters IV (IV 1  through IVn). Each of the second current sources  102  ( 102 - 1  through  102 - n ) is connected between a corresponding one of the inverters IV (IV 1  through IVn) and the second operating voltage VSS. The first current sources  101  ( 101 - 1  through  101 - n ) and the second current sources  102  ( 102 - 1  through  102 - n ) are controlled by the bias circuit  200 . A ground voltage may be usable as the second operating voltage VSS. 
       FIG. 3  is an equivalent circuit diagram illustrating a block  110   n  of the oscillation unit  110 A of  FIG. 2 . Here, a ground voltage may be usable as the second operating voltage VSS. 
     Referring to  FIG. 3 , the block  110 - n  may be represented as an equivalent circuit including a single current source providing the operating current I D , a resistor R tot , a capacitor C tot , and a switch SW. Accordingly, a frequency f osc  of the oscillation signal SO output from the oscillation unit  100 A (hereinafter, referred to as an oscillation frequency f osc ) may be defined as Equation 1: 
     
       
         
           
             
               
                 
                   
                     f 
                     osc 
                   
                   = 
                   
                     
                       
                         I 
                         D 
                       
                       
                         n 
                         · 
                         
                           C 
                           tot 
                         
                         · 
                         VDD 
                       
                     
                     . 
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     As illustrated in Equation 1, the oscillation frequency f osc  is in inverse proportion to the first operating voltage VDD and is in proportion to the operating current I D . Accordingly, a frequency insensitive to temperature change, i.e., temperature-compensated oscillation frequency can be obtained by complementarily changing the operating current I D  and the first operating voltage VDD with respect to a temperature. For instance, when the operating current I D  is increased to increase the frequency of the oscillation signal SO with respect to the increase of the temperature and the first operating voltage VDD is increased to decrease the frequency of the oscillation signal SO with respect to the increase of the temperature, a temperature-compensated oscillation frequency can be obtained. 
     The bias circuit  200  controls the operating current I D  of the oscillation unit  100 . The bias circuit  200  may generate a bias current (IPTAT in  FIG. 4 ) that increases when a temperature increases. In addition, the bias circuit  200  may mirror the bias current IPTAT having a current source proportional to an absolute temperature (PTAT) characteristic as the operating current I D . The bias circuit  200  may be implemented as a current bias circuit, such as a beta multiplier, but the present general inventive concept is not limited thereto. It is possible that other type of a current circuit can be usable as the bias circuit  200 . 
     When the bias current IPTAT which increases as the temperature increases is mirrored as the operating current I D  of the oscillation unit  100 , the oscillation frequency f osc  output from the oscillation unit  100  also increases as the temperature increases. However, the oscillation frequency f osc  of the ring oscillator, i.e., the oscillation unit  100 , is in inverse proportion to the first operating voltage VDD of the inverter chain  103 , as described above. Assuming that the operating current I D  does not vary with a temperature change, the oscillation frequency f osc  is increased when the first operating voltage VDD of the inverter chain  103  decreases and is decreased when the first operating voltage VDD increases. 
     Using this characteristic, the voltage generation unit  300  generates the first operating voltage VDD and/or the second operating voltage VSS to compensate for the change in the oscillation frequency f osc  with respect to the temperature change complementarily with the bias circuit  200 . The voltage generation unit  300  generates the first operating voltage VDD and/or the second operating voltage VSS applied to the oscillation unit  100  using a supply voltage (VR in  FIG. 4 ). The first operating voltage VDD may be the same as or different from the supply voltage VR and the second operating voltage VSS may be the same as or different from the ground voltage. 
       FIG. 4  is a circuit diagram illustrating a temperature-compensated oscillator  1 A according to an embodiment of the inventive concept. Referring to  FIG. 4 , the temperature-compensated oscillator  1 A includes the oscillation unit  100 A, a bias circuit  200 A, and a voltage generation unit  300 A. The oscillation unit  100 A illustrated in  FIG. 4  may have the same structure as the oscillation unit  100 A illustrated in  FIG. 2  or may further include a capacitor  104  connected between the first operating voltage VDD and the ground voltage. The oscillation unit  100 A illustrated in  FIG. 4  is connected to the first operating voltage VDD and the ground voltage. 
     The voltage generation unit  300 A may include an operating voltage generation transistor  310  which is connected between the supply voltage VR and a node Nd and has a diode-connection. The operating voltage generation transistor  310  may be a diode-connected P-channel metal oxide semiconductor (PMOS) transistor or a bipolar junction transistor (BJT). 
     When a temperature increases, a gate-source voltage (Vgs) of the diode-connected PMOS transistor decreases, and therefore, the first operating voltage VDD increases. However, when temperature decreases, the Vgs of the diode-connected PMOS transistor increases, and therefore, the first operating voltage VDD decreases. Like the diode-connected PMOS transistor, a base-emitter voltage (Vbe) of the diode-connected BJT decreases when a temperature increases, and therefore, the first operating voltage VDD increases. When the first operating voltage VDD increases under the assumption that other conditions are constant, the oscillation frequency f osc  decreases, as described above. 
     The bias circuit  200 A includes a PTAT current source  210 A and a current mirror unit  220 A. The PTAT current source  210 A provides the bias current IPTAT that increases as the temperature increases. The current mirror unit  220 A is a circuit to mirror the bias current IPTAT as the operating current I D . 
     The current mirror unit  220 A may include first through third transistors M 1  through M 3 . The first and second transistors M 1  and M 2  may be N-channel metal oxide semiconductor (NMOS) transistors and the third transistor M 3  may be a PMOS transistor. A gate and a drain of the first transistor M 1  are connected in common to a first node N 1  and a source of the first transistor M 1  is connected to the ground voltage. A gate, a drain and a source of the second transistor M 2  are respectively connected to the first node N 1 , a second node N 2 , and the ground voltage. A gate and a drain of the third transistor M 3  are connected in common to the second node N 2  and a source of the third transistor M 3  is connected to the first operating voltage VDD. 
     The first node N 1  is connected to the second current sources  102  ( 102 - 1  through  102 - n ). The second node N 2  is connected to the first current sources  101  ( 101 - 1  through  101 - n ). 
     The PTAT current source  210 A is connected between the supply voltage VR and the first node N 1  to supply the bias current IPTAT to the first node N 1 . The PTAT current source  210 A includes fourth through eighth transistors M 4  through M 8  and a resistor R. The fourth and fifth transistors M 4  and M 5  may be NMOS transistors and the sixth through eighth transistors M 6 , M 7 , and M 8  may be PMOS transistors. 
     A gate and a drain of the fourth transistor M 4  are connected in common to a third node N 3  and a source of the fourth transistor M 4  is connected to the ground voltage. a gate and a drain of the fifth transistor M 5  are respectively connected to the third node N 3  and a fourth node N 4  and a source of the fifth transistor M 5  is connected to the ground voltage via the resistor R. A source, a gate and a drain of the sixth transistor M 6  are respectively connected to the supply voltage VR, the fourth node N 4 , and third node N 3 . A gate and a drain of the seventh transistor M 7  are connected in common to the fourth node N 4  and a source of the seventh transistor M 7  is connected to the supply voltage VR. A gate, a source and a drain of the eighth transistor M 8  are respectively connected to the fourth node N 4 , the supply voltage VR, and first node N 1 . 
       FIG. 5  is a circuit diagram illustrating a temperature-compensated oscillator  1 B according to an embodiment of the inventive concept. Referring to  FIG. 5 , the temperature-compensated oscillator  1 B includes an oscillation unit  100 B, the bias circuit  200 A, and the voltage generation unit  300 A. The bias circuit  200 A and the voltage generation unit  300 A may have the same construction as the bias circuit  200 A and the voltage generation unit  300 A illustrated in  FIG. 4 , and therefore, descriptions thereof will be omitted. 
     Like the oscillation unit  100 A illustrated in  FIGS. 2 and 4 , the oscillation unit  100 B may include the inverter chain  103  in which a plurality of (or the odd number of) the inverters IV (IV 1  through IVn) (where “n” is an odd number) are connected in a ring shape and the first and second current sources  101  ( 101 - 1  through  101 - n ) and  102  ( 102 - 1  through  102 - n ) providing the operating current I D  for the inverters IV (IV 1  through IVn). In the embodiment of  FIG. 5 , it is assumed that “n” is 5, but the inventive concept is not limited thereto. The oscillation unit  100 B may also include a buffer  105  that receives an input signal and an output signal of the last inverter IV 5  and outputs the oscillation signal SO. 
     The first current sources  101  ( 101 - 1  through  101 - n ) may be implemented using PMOS transistors. The PMOS transistors of the respective first current sources  101  ( 101 - 1  through  101 - n ) may be connected between the first operating voltage VDD and the respective inverters IV (IV 1  through IVn), and gates of the PMOS transistors may be connected to in common to the gate of the third transistor M 3 , i.e., the second node N 2  in the bias circuit  200 A. 
     The second current sources  102  ( 102 - 1  through  102 - n ) may be implemented using NMOS transistors. The NMOS transistors of the respective second current sources  102  ( 102 - 1  through  102 - n ) may be connected between the respective inverters IV (IV 1  through IVn) and the ground voltage and gates of the NMOS transistors may be connected to in common to the gate of the first and second transistors M 1  and M 2 , i.e., the first node N 1  in the bias circuit  200 A. 
     Therefore, a PTAT characteristic of the operating current I D  with respect to a temperature change and the complementary to an absolute temperature (CTAT) characteristic of the first operating voltage VDD of the inverter chain  103  are offset each other, so that an error in the oscillation frequency f osc  of the ring oscillator with respect to a temperature change is significantly reduced. 
       FIG. 6  is a circuit diagram illustrating a temperature-compensated oscillator  1 C according to an embodiment of the inventive concept. The temperature-compensated oscillator  1 C includes an oscillation unit  100 A′, a bias circuit  200 B, and a voltage generation unit  300 B. The oscillation unit  100 A′ may have a similar construction to the oscillation unit  100 A illustrated in  FIG. 4  but uses a different operating voltage. 
     The oscillation unit  100 A illustrated in  FIG. 4  operates using the first operating voltage VDD and the ground voltage, but the oscillation unit  100 A′ illustrated in  FIG. 6  operates using the supply voltage VR and the second operating voltage VSS. In other words, the oscillation unit  100 A illustrated in  FIG. 4  uses the ground voltage as the second operating voltage VSS and the oscillation unit  100 A′ illustrated in  FIG. 6  uses the supply voltage VR as the first operating voltage VDD. 
     The voltage generation unit  300 B may include an operating voltage generation transistor  320  which is connected between the ground voltage and a node Ns and has a diode-connection. The operating voltage generation transistor  320  may be a diode-connected NMOS transistor or a diode-connected BJT. 
     When a temperature increases, a gate-source voltage (Vgs) of the diode-connected NMOS transistor  320  decreases, and therefore, the second operating voltage VSS decreases. However, when a temperature decreases, the Vgs of the diode-connected NMOS transistor  320  increases, and therefore, the second operating voltage VSS increases. Like the diode-connected NMOS transistor, a base-emitter voltage (Vbe) of the diode-connected BJT decreases when a temperature increases, and therefore, the second operating voltage VSS decreases. 
     When the second operating voltage VSS decreases under the assumption that other conditions are constant, a voltage (e.g., VR-VSS) put across both ends of each of the inverters IV (IV 1  through IVn) increases, and therefore, the oscillation frequency f osc  decreases. In other words, when a temperature increases, the operating voltage of the oscillation unit  100 A′ is increased by the voltage generation unit  300 B, so that the oscillation frequency f osc  is decreased. However, the bias current IPTAT increases as a temperature increases, and therefore, the operating current I D  of the oscillation unit  100 A′ also increases with the temperature. As a result, the oscillation frequency f osc  is increased. 
     Accordingly, a PTAT characteristic of the operating current I D  with respect to a temperature change and the CTAT characteristic of the operating voltage (VDD-VSS) of the inverter chain  103  are offset each other, so that an error in the oscillation frequency f osc  of the ring oscillator with respect to a temperature change is significantly reduced. 
       FIG. 7  is a circuit diagram illustrating a bias adjustment circuit  230  usable with the PTAT current source  210 A of  FIG. 4  according to an embodiment of the inventive concept. Referring to  FIG. 7 , the PTAT current source  210 A includes the NMOS transistors M 4  and M 5 , the PMOS transistors M 6 , M 7 , and M 8 , and the resistor R. 
     The bias adjustment circuit  230  adjusts a bulk voltage level of at least one transistor (e.g., M 4 ) of the PTAT current source  210 A. The bias circuits  200 ,  200 A, and  200 B may also include the bias adjustment circuit  230  in addition to the PTAT current source  210 A and the current mirror unit  220 A. The bias adjustment circuit  230  includes a current source  240 , a transistor circuit  260  including at least two bias voltage control transistors  261 , and a switch circuit  250 . 
     The current source  240  is connected between the supply voltage VR and a bulk node NC 1 . Each of the bias voltage control transistors  261  may be implemented as a diode-connected NMOS transistor. 
     The switch circuit  250  includes a plurality of switches  251  which are connected between the respective bias voltage control transistors  261  and the bulk node NC 1  and closed and opened in response to switch control signals CB (CB[ 1 ] through CB[m]), respectively. As each of the switches  251  is selectively closed or opened, a corresponding one of the bias voltage control transistors  261  is selectively conducted. 
     A position of the switch circuit  250  and a position of the transistor circuit  260  may be changed. For instance, the bias voltage control transistors  261  may be connected to the bulk node NC 1  and the switches  251  may be placed between the bias voltage control transistors  261  and the ground voltage. 
     The bias voltage control transistors  261  are respectively connected to corresponding ones of the switches  251  in the present embodiment illustrated in  FIG. 7 , but the inventive concept is not limited thereto. For instance, a common switch may be provided for at least two bias voltage control transistors  261  or at least one bias voltage control transistor  261  may be connected without a switch. 
     The bias voltage control transistors  261  may be the same or different in size. A voltage level of the bulk node NC 1  is adjusted by the bias voltage control transistors  261  selectively conducted according to the switch control signals CB (CB[ 1 ] through CB[m]), i.e., the selective opening or closing of the corresponding switches  251 , so that the bulk voltage level of the transistor M 4  of the PTAT current source  210 A is adjusted. As a result, a level of the bias current IPTAT is adjusted, and therefore, the operating current I D  is also adjusted. Although the operating current and the operating voltage are variable to reduce a variation of the frequency of the oscillation signal SO according to the temperature change, the variable operating current I D , can be further adjusted such that the oscillation signal can have different frequencies corresponding to different modes. The different frequencies may be a high frequency to be usable in a normal mode and a lower frequency to be usable in a non-normal mode, that is, an ultra-low current mode, a standby mode or a sleep mode thereof. 
       FIG. 8  is a circuit diagram illustrating a bulk voltage control circuit  315  usable with the voltage generation unit  300 A illustrated in  FIG. 5  according to an embodiment of the inventive concept. Referring to  FIG. 8 , the bulk voltage control circuit  315  adjusts the bulk voltage level of the operating voltage generation transistor  310  of the voltage generation unit  300 A. 
     The bulk voltage control circuit  315  includes a current source  340 , a transistor circuit  350  including at least two bulk voltage control transistors  321 , and a switch circuit  330 . Each of the bulk voltage control transistors  321  may be implemented as a diode-connected PMOS transistor. The bulk voltage control transistors  321  are connected between the supply voltage VR and the switch circuit  330 . The switch circuit  330  includes a plurality of switches  331  which are connected between the respective bulk voltage control transistors  321  and a common node NC 2  and closed and opened in response to digital control signals CS (CS[ 1 ] through CS[k]), respectively. 
     The current source  340  is connected between the common node NC 2  and a potential, for example, the ground voltage. As each of the switches  331  is selectively closed or opened, a corresponding one of the bulk voltage control transistors  321  is selectively conducted. 
     A position of the switch circuit  330  and a position of the transistor circuit  350  may be changed. For instance, the switches  331  may be connected to the supply voltage VR and the bulk voltage control transistors  321  may be placed between the switches  331  and the common node NC 2 . 
     The bulk voltage control transistors  321  are respectively connected to corresponding ones of the switches  331  as illustrated in  FIG. 8 , but the inventive concept is not limited thereto. For instance, a common switch may be provided for at least two bulk voltage control transistors  321  or at least one bulk voltage control transistor  321  may be connected without a switch. 
     The bulk voltage control transistors  321  may be the same or different in size. A voltage level of a node NB is adjusted by the bulk voltage control transistors  321  selectively conducted according to the digital control signals CS (CS[ 1 ] through CS[k]), i.e., the selective opening or closing of the switches  331 , so that the bulk voltage level of the operating voltage generation transistor  310  of the voltage generation unit  300 A is adjusted. As a result, a level of the first operating voltage VDD generated by the voltage generation unit  300 A is adjusted. Although the operating current and the operating voltage are variable to reduce a variation of the frequency of the oscillation signal SO according to the temperature change, the variable operating voltage can be further adjusted such that the oscillation signal can have different frequencies corresponding to different modes. The different frequencies may be a high frequency to be usable in a normal mode and a lower frequency to be usable in a non-normal mode, that is, an ultra mode, a standby mode or a sleep mode thereof. 
       FIG. 9  is a circuit diagram illustrating a temperature-compensated oscillator  1 D according to an embodiment of the inventive concept. Referring to  FIG. 9 , the temperature-compensated oscillator  1 D includes the oscillation unit  100 B, a bias circuit  200 C, and the voltage generation unit  300 A. The voltage generation unit  300 A illustrated in  FIG. 9  may be the same as the voltage generation unit  300 A illustrated in  FIG. 4 , and therefore, a description thereof will be omitted. 
     The oscillation unit  100 B illustrated in  FIG. 9  includes the inverter chain  103  in which an odd number of the inverters IV 1  through IVn (where “n” is an odd number) and the first current sources  101  ( 101 - 1  through  101 - n ) but does not include the second current sources  102  ( 102 - 1  through  102 - n ) illustrated in the oscillation unit  100 A of  FIG. 4 . The bias circuit  200 C may have the same construction as the bias circuit  200 A illustrated in  FIG. 4  with the exception that a signal line for controlling the second current sources  102  ( 102 - 1  through  102 - n ) of  FIG. 4  is omitted from the bias circuit  200 C of  FIG. 9 . Since the oscillation unit  100 A illustrated in  FIG. 4  includes the second current sources  102  ( 102 - 1  through  102 - n ), the first node N 1  to which the gate and drain of the first transistor M 1  and the gate of the second transistor M 2  in the bias circuit  200 A are connected in common is connected to the second current sources  102  ( 102 - 1  through  102 - n ). However, since the oscillation unit  100 B illustrated in  FIG. 9  does not include the second current sources  102  ( 102 - 1  through  102 - n ), a line connecting the first node N 1  to the second current sources  102 - 1  through  102 - n  is not required, either. 
     The bias circuit  200 C generates the bias current IPTAT that increases as a temperature increases. Accordingly, the operating current I D , i.e., the mirrored current of the bias current IPTAT also increases as the temperature increases. 
     Meanwhile, the voltage generation unit  300 A generates the first operating voltage VDD that increases as the temperature increases. As described above, the oscillation frequency f osc  decreases when the first operating voltage VDD increases and the oscillation frequency f osc  increases when the operating current I D  increases. Accordingly, when the temperature increases, the decrease of the oscillation frequency f osc  due to the increase of the first operating voltage VDD and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may offset each other, so that the oscillation signal SO having the oscillation frequency f osc  insensitive to a temperature change is obtained. It is possible that a variation (decrease or increase) of the oscillation frequency f osc  due to a change (increase or decrease) of the first operating voltage VDD and a variation (increase or decrease) of the oscillation frequency f osc  due to a change (increase or decrease) of the operating current I D  may partially offset each other. It is also possible that the variation of the oscillation frequency f osc  of the oscillation signal SO is reduced at least due to a simultaneous change of the increase (or decrease) of the first operating voltage VDD and the increase (decrease) of the operating current I D  according to the temperature change. The association of the change (increase or decrease) of the first operating voltage VDD and the change (increase or decrease) of the operating current I D  according to the temperature change may affect (reduce) the variation of the oscillation frequency f osc  of the oscillation signal SO as described above or hereinafter. The oscillation frequency f osc  of the oscillation signal SO may be maintained stable or may be in a variation range, for example, about within 2% from a reference frequency in a case where a temperature change is between 20° C. and 80° C., for example. The reference frequency may be referred to as a center frequency of a middle portion of a temperate variation between a low temperature and a high temperature in which an oscillation is usable to provide an oscillation signal to an external unit or device. 
       FIG. 10  is a circuit diagram illustrating a temperature-compensated oscillator  1 E according to an embodiment of the inventive concept. Referring to  FIG. 10 , the temperature-compensated oscillator  1 E includes an oscillation unit  100 C, a bias circuit  200 D, and the voltage generation unit  300 A. The voltage generation unit  300 A illustrated in  FIG. 10  may be the same as the voltage generation unit  300 A illustrated in  FIG. 4 , and therefore, a description thereof will be omitted. 
     The oscillation unit  100 C illustrated in  FIG. 10  includes the inverter chain  103  in which an odd number of the inverters IV (IV 1  through IVn) (where “n” is an odd number) and the second current sources  102  ( 102 - 1  through  102 - n ) but does not include the first current sources  101  ( 101 - 1  through  101 - n ) of  FIG. 4 . 
     The bias circuit  200 D may include the first transistor M 1 , the fourth through eighth transistors M 4  through M 8 , and the resistor R. The first, fourth and fifth transistors M 1 , M 4 , and M 5  may be NMOS transistors and the sixth, seventh, and eighth transistors M 6 , M 7 , and M 8  may be PMOS transistors. 
     The gate and drain of the first transistor M 1  are connected in common to the first node N 1  and the source thereof is connected to the ground voltage. The first node N 1  is connected to the second current sources  102  ( 102 - 1  through  102 - n ). 
     The gate and drain of the fourth transistor M 4  are connected in common to the third node N 3  and the source thereof is connected to the ground voltage. The gate and drain of the fifth transistor M 5  are respectively connected to the third node N 3  and the fourth node N 4  and the source thereof is connected to the ground voltage via the resistor R. The source, gate and drain of the sixth transistor M 6  are respectively connected to the supply voltage VR, the fourth node N 4 , and the third node N 3 . The gate and drain of the seventh transistor M 7  are connected in common to the fourth node N 4  and the source thereof is connected to the supply voltage VR. The gate, source and drain of the eighth transistor M 8  are respectively connected to the fourth node N 4 , the supply voltage VR, and the first node N 1 . 
     The bias circuit  200 D having the above-described construction does not need to control the first current sources  101 - 1  through  101 - n  and thus not include the second and third transistors M 2  and M 3 , as compared to the bias circuit  200 A illustrated in  FIG. 4 . 
     The bias circuit  200 D generates the bias current IPTAT that increases as temperature increases. Accordingly, the operating current I D , i.e., the mirrored current of the bias current IPTAT also increases as temperature increases. Meanwhile, the voltage generation unit  300 A generates the first operating voltage VDD that increases as temperature increases. 
     As described above, the oscillation frequency f osc  decreases when the first operating voltage VDD increases and the oscillation frequency f osc  increases when the operating current I D  increases. Accordingly, when a temperature increases, the decrease of the oscillation frequency f osc  due to the increase of the first operating voltage VDD and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may offset each other, so that the oscillation signal SO having the oscillation frequency f osc  insensitive to a temperature change is obtained. It is possible that the decrease of the oscillation frequency f osc  due to the increase of the first operating voltage VDD and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may partially offset each other. It is also possible that a variation of the oscillation frequency f osc  of the oscillation signal SO is reduced at least due to a simultaneous change of the increase of the first operating voltage VDD and the increase of the operating current I D  according to the temperature change. The association of the increase of the first operating voltage VDD and the increase of the operating current I D  according to the temperature change may affect (reduce) a variation of the oscillation frequency f osc  of the oscillation signal SO as described above or hereinafter. 
       FIG. 11  is a circuit diagram illustrating a temperature-compensated oscillator  1 F according to an embodiment of the inventive concept. Referring to  FIG. 11 , the temperature-compensated oscillator  1 F includes the oscillation unit  100 B, a bias circuit  200 E, and the voltage generation unit  300 B. The voltage generation unit  300 B illustrated in  FIG. 11  may be the same as the voltage generation unit  300 B illustrated in  FIG. 6 , and therefore, a description thereof will be omitted. The oscillation unit  100 B illustrated in  FIG. 11  may be the same as the oscillation unit  100 B illustrated in  FIG. 9 , and therefore, a description thereof will be omitted. 
     The bias circuit  200 E may include the first transistor M 1 , the fourth through eighth transistors M 4  through M 8 , and the resistor R. The oscillation unit  100 B of  FIG. 11  does not include the second current sources  102  ( 102 - 1  through  102 - n ) of the oscillation unit  100 A′ of  FIG. 6 , and therefore, the bias circuit  200 E does not include the second and third transistors M 2  and M 3  of the bias circuit  200 B of  FIG. 6 . The first, fourth and fifth transistors M 1 , M 4 , and M 5  may be NMOS transistors and the sixth, seventh and eighth transistors M 6 , M 7 , and M 8  may be PMOS transistors. 
     The gate and drain of the eighth transistor M 8  are connected in common to the first node N 1  and the source thereof is connected to the first operating voltage VDD. The first node N 1  is connected to the first current sources  101  ( 101 - 1  through  101 - n ). 
     The gate and drain of the fourth transistor M 4  are connected in common to the third node N 3  and the source thereof is connected to the ground voltage. The gate and drain of the fifth transistor M 5  are respectively connected to the third node N 3  and the fourth node N 4  and the source thereof is connected to the ground voltage via the resistor R. The source, gate and drain of the sixth transistor M 6  are respectively connected to the supply voltage VR, the fourth node N 4 , and the third node N 3 . The gate and drain of the seventh transistor M 7  are connected in common to the fourth node N 4  and the source thereof is connected to the supply voltage VR. 
     The bias circuit  200 E generates the bias current IPTAT that increases as temperature increases. Accordingly, the operating current I D , i.e., the mirrored current of the bias current IPTAT also increases as a temperature increases. Meanwhile, the voltage generation unit  300 B generates the second operating voltage VSS that decreases as the temperature increases. 
     As described above, the oscillation frequency f osc  decreases when the second operating voltage VSS decreases and it increases when the operating current I D  increases. Accordingly, when the temperature increases, the decrease of the oscillation frequency f osc  due to the decrease of the second operating voltage VSS and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may offset each other, so that the oscillation signal SO having the oscillation frequency f osc  insensitive to a temperature change is obtained. It is possible that the decrease of the oscillation frequency f osc  due to the decrease of the second operating voltage VSS and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may partially offset each other. It is also possible that a variation of the oscillation frequency f osc  of the oscillation signal SO is reduced at least due to a simultaneous change of the decrease of the second operating voltage VSS and the increase of the operating current I D  according to the temperature change. The association of the decrease of the second operating voltage VSS and the increase of the operating current I D  according to the temperature change may affect (reduce) a variation of the oscillation frequency f osc  of the oscillation signal SO as described above or hereinafter. 
       FIG. 12  is a circuit diagram illustrating a temperature-compensated oscillator  1 G according to an embodiment of the inventive concept. Referring to  FIG. 12 , the temperature-compensated oscillator  1 G includes the oscillation unit  100 C, a bias circuit  200 F, and the voltage generation unit  300 B. The voltage generation unit  300 B illustrated in  FIG. 12  may be the same as the voltage generation unit  300 B illustrated in  FIG. 6 , and therefore, a description thereof will be omitted. The oscillation unit  1000  illustrated in  FIG. 12  may be the same as the oscillation unit  100 C illustrated in  FIG. 10 , and therefore, a description thereof will be omitted. 
     The bias circuit  200 F may have the same construction as the bias circuit  200 B illustrated in  FIG. 6 , with the exception that a signal line for controlling the first current sources  101  ( 101 - 1  through  101 - n ) of  FIG. 6  is omitted from the bias circuit  200 F of  FIG. 12  since the oscillation unit  100 C does not include the first current sources  101  ( 101 - 1  through  101 - n ). The second node N 2  to which the gate and drain of the second transistor M 2  are connected in common is connected to the second current sources  102  ( 102 - 1  through  102 - n ). 
     The gate and drain of the eighth transistor M 8  are connected in common to the first node N 1  and the source thereof is connected to the first operating voltage VDD. The gate, the drain and the source of the third transistor M 3  are respectively connect to the first node N 1 , the second node  2 , and the first operating voltage VDD. The gate and drain of the fourth transistor M 4  are connected in common to the third node N 3  and the source thereof is connected to the ground voltage. The gate and drain of the fifth transistor M 5  are respectively connected to the third node N 3  and the fourth node N 4  and the source thereof is connected to the ground voltage via the resistor R. The source, gate and drain of the sixth transistor M 6  are respectively connected to the supply voltage VR, the fourth node N 4 , and the third node N 3 . The gate and drain of the seventh transistor M 7  are connected in common to the fourth node N 4  and the source thereof is connected to the supply voltage VR. 
     The bias circuit  200 F generates the bias current IPTAT that increases as temperature increases. Accordingly, the operating current I D , i.e., the mirrored current of the bias current IPTAT also increases as temperature increases. Meanwhile, the voltage generation unit  300 B generates the second operating voltage VSS that decreases as temperature increases. 
     As described above, the oscillation frequency f osc  decreases when the second operating voltage VSS decreases and the oscillation frequency f osc  increases when the operating current I D  increases. Accordingly, when temperature increases, the decrease of the oscillation frequency f osc  due to the decrease of the second operating voltage VSS and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may offset each other, so that the oscillation signal SO having the oscillation frequency f osc  insensitive to temperature change is obtained. It is possible that the decrease of the oscillation frequency f osc  due to the decrease of the second operating voltage VSS and the increase of the oscillation frequency f osc  due to the increase of the operating current I D  may partially offset each other. It is also possible that a variation of the oscillation frequency f osc  of the oscillation signal SO is reduced at least due to a simultaneous change of the decrease of the second operating voltage VSS and the increase of the operating current to according to the temperature change. The association of the decrease of the second operating voltage VSS and the increase of the operating current I D  according to the temperature change may affect (reduce) a variation of the oscillation frequency f osc  of the oscillation signal SO as described above or hereinafter 
       FIG. 13  is a graph illustrating a simulation result of an output frequency of a temperature-compensated oscillator according to the embodiment of the inventive concept and a simulation result of an output frequency of an oscillator according to a comparison example. Referring to  FIG. 13 , a curve  410  illustrates the output frequency of the oscillator with respect to a temperature in the comparison example and a line  420  illustrates the output frequency of the oscillator with respect to a temperature in the embodiment of the inventive concept. The line  420  may be a curve. 
     As described above, the oscillator according to the present embodiment of the inventive concept includes a PTAT current source to provide an operating current increasing with the increase of a temperature and a voltage generation unit to control an operating voltage so that the output frequency is decreased. The oscillator according to the comparison example uses only the PTAT current source to provide an operating current increasing with the increase of temperature without the voltage generation unit. 
     As illustrated in  FIG. 13 , while the output frequency of the oscillator according to the comparison example has a variation of about ±12% with respect to a temperature, the output frequency of the oscillator according to the present embodiment of the inventive concept has a variation of only about ±2% with respect to a temperature and thus remarkably increase the accuracy of a frequency with respect to a temperature. 
     As described above, according to the embodiment of the inventive concept, the output frequency of an oscillator can be compensated using an operating current proportional to a temperature and a power supply voltage having a predetermined value with respect to the temperature (e.g., a voltage proportional or inverse proportional to the temperature) instead of using a temperature-compensated reference current only that is usually used as an operating current of a ring oscillator. Therefore, according to the embodiment of the inventive concept, a ring oscillator having a temperature-compensated oscillation frequency (e.g., 15 KHz can be embodied with a low operating current (e.g., 200 nA or less) using a small resistor (e.g., a single resistor having a resistance of 2 MΩ or less). 
       FIG. 14  is a schematic block diagram illustrating an electronic device  10  according to an embodiment of the inventive concept. Referring to  FIG. 14 , the electronic device  10  includes a temperature-compensated oscillator  1  and a logic circuit  2 . The temperature-compensated oscillator  1  may be one of the temperature-compensated oscillators  1  and  1 A through  1 G that have been described above with reference to  FIGS. 1 through 12  according to the embodiment of the inventive concept. 
     The logic circuit  2  uses the oscillation signal SO as a clock signal and may operate in synchronization with the oscillation signal SO or a clock signal generated from the oscillation signal SO. The logic circuit  2  may be a central processing unit (CPU), a graphics processing unit (GPU), a memory, or a communication circuit (e.g., a modem or a transceiver) to communicate with an external device, but the present general inventive concept is not limited thereto. The logic circuit  2  may be included in a functional unit  3  of the electronic device  10 . The functional unit  3  may include a user interface to communicate with a user to output data to the user or receive a user command from the user, and a video and/or audio uit to output an image and/or sound. The image may be displayed on a display unit (not illustrated). The display unit may be a touch panel as an output element and a user command input element. 
     The oscillation signal SO may be usable in components of the functional unit  3 . It is possible that the oscillation signal SO may be usable to operate the electronic device including the logic circuit  2  in different operating modes corresponding to different oscillation frequencies. The oscillation signal SO may be usable as at least one of the different oscillation frequencies or may be usable to generate (or to be converted into) at least one of the different oscillation frequencies to perform the corresponding operating mode. 
     The electronic device  10  may be a memory device, a cellular phone, a smart phone, a personal digital assistant (PDA), a wireless communication device, a digital camera, or a solid state drive (SSD), but the present general inventive concept is not limited thereto. 
     As described above, according to the embodiment of the inventive concept, the output frequency of an oscillator can be compensated using an operating current proportional to a temperature and a power supply voltage having a predetermined value with respect to the temperature instead of using a temperature-compensated reference current only that is usually used as an operating current of a ring oscillator. As a result, a stable frequency characteristic can be obtained with respect to a temperature change. In addition, a size of a resistance element required to implement a low-current oscillator is remarkably reduced, so that a size of the oscillator is reduced. The voltage generation unit compensates for a change in the frequency of the oscillation signal with respect to a change in the temperature complementarily with the bias circuit by controlling the operating voltage so that the frequency of the oscillation signal decreases as the temperature increases. 
     Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.