Patent Publication Number: US-7710093-B2

Title: Driver for a power converter and a method of driving a switch thereof

Description:
This application is a continuation of patent application Ser. No. 10/767,540, entitled “Driver for a Power Converter and a Method of Driving a Switch Thereof,” filed on Jan. 29, 2004, now U.S. Pat. No. 7,330,017, issued Feb. 12, 2008, which application is incorporated herein by reference. 

   TECHNICAL FIELD 
   The present invention is directed, in general, to power electronics and, more specifically, to a driver for a power converter, method of driving a switch thereof, and a power converter employing the same. 
   BACKGROUND 
   A switch mode power converter (also referred to as a “power converter”) is a power supply or power processing circuit that converts an input voltage waveform into a specified output voltage waveform. Controllers associated with the power converters manage an operation thereof by controlling the conduction periods of switches employed therein. Generally, the controllers are coupled between an input and output of the power converter in a feedback loop configuration (also referred to as a “control loop” or “closed control loop”). 
   Typically, the controller measures an output characteristic (e.g., an output voltage) of the power converter and based thereon modifies a duty cycle of the switches of the power converter. The duty cycle is a ratio represented by a conduction period of a switch to a switching period thereof. Thus, if a switch conducts for half of the switching period, the duty cycle for the switch would be 0.5 (or 50 percent). Additionally, as the needs for systems such as a microprocessor powered by the power converter dynamically change (e.g., as a computational load on the microprocessor changes), the controller should be configured to dynamically increase or decrease the duty cycle of the switches therein to maintain the output characteristic at a desired value. 
   In combination with the controller, a driver is often employed to provide a drive signal to the switches of the power converter as a function of a signal from the controller. Assuming that the switches of the power converter are metal oxide semiconductor field effect transistors (“MOSFETs”), the driver is referred to as a gate driver and provides a gate drive signal to a gate terminal (i.e., a control terminal) of the MOSFET to control an operation thereof. Providing a gate drive signal with a limited control voltage range (or “gate voltage limit”) for a MOSFET is of particular interest in the design and implementation of power converters. In an exemplary application, the power converters have the capability to convert an unregulated input voltage such as five volts to a lower, regulated, output voltage such as 2.5 volts to power a load. 
   As discussed above, the power converters are frequently employed to power loads having tight regulation characteristics such as a microprocessor with, for instance, five volts provided from a source of electrical power (e.g., a voltage source). To provide the voltage conversion and regulation functions, the power converters include active switches such as the MOSFETs that are coupled to the voltage source and periodically switch a reactive circuit element such as an inductor to the voltage source at a switching frequency that may be on the order of five megahertz. To maintain high power conversion efficiency and low cost, the MOSFETs employed for the switches in the power converters are generally configured with fine line structures and thin gate oxides. The aforementioned structures that form the MOSFETs, however, present new design challenges associated with the control signals such as a gate voltage adapted to control the conduction periods of the switches. 
   For instance, recently designed MOSFETs for the power converters can reliably sustain control signals of about 2.5 volts from the gate terminal to the source terminal, whereas MOSFETs of earlier designs were able to sustain control signals of 20 volts or more. Additionally, the power converters often employ a P-channel MOSFET as a main switch therein. Inasmuch as the P-channel MOSFET is generally coupled to the input voltage (e.g., nominal five volts) of the power converter, the gate voltage is desirably controlled to a value of the input voltage (again, five volts) to transition the switch to a non-conducting state. Conversely, the P-channel MOSFET is enabled to conduct at a gate voltage equal to the input voltage of five volts minus 2.5 volts, which represents about the maximum sustainable voltage from the gate terminal to the source terminal of the switch (also referred to as a “gate-to-source voltage limit” or the “gate voltage limit” of the switch). 
   It is relatively common to employ a driver for a P-channel MOSFET that includes a series-coupled, totem-pole arrangement of a P-channel and N-channel MOSFET with coupled gate terminals. In the environment of a power converter, the totem pole driver (as the driver is customarily designated) for the P-channel MOSFET is coupled to the source of electrical power for the power converter and the controller of the power converter. The drive signal is generated from a junction coupling the drain terminals of the P-channel and N-channel MOSFETs of the totem pole driver. When a signal from the controller to the totem pole driver is high, the drive signal is essentially grounded. When the signal from the controller to the totem pole driver is low, the drive signal is substantially equal to the input voltage of the power converter. In effect, the drive signal from the totem pole driver exhibits voltages over the entire voltage range of the source of electrical power for the power converter. Alternatively, the driver may be described as providing a drive signal referenced to ground when its output is low, and a drive signal referenced to the input voltage when its output is high. 
   When providing a drive signal to a P-channel MOSFET (or any switch for that matter) having a gate voltage limit of 2.5 volts, and in the environment of a power converter having a nominal input voltage of five volts, the extended voltage range present on the gate terminal of the switch may break down the integrity of the thin gate oxide of the switch. In other words, when the input voltage to the power converter which is translated into the drive signal to the switch under certain conditions as described above exceeds the gate voltage limit thereof, the switch may be damaged and fail. Thus, the totem pole driver and other presently available drivers are typically not practical for applications wherein the switch to be driven exhibits a smaller gate voltage limit from the gate terminal to the source terminal thereof. 
   Another level of complexity arises when the switch to be driven and the driver are referenced to different voltages. In the environment of the power converter described above, circuitry that embodies the driver may be coupled to ground and referenced to a ground potential and the switch to be driven may be referenced to, for instance, the input voltage of the power converter. As a result, the driver is referenced to a ground potential and the switch is referenced to an input voltage such as an unregulated five volt input voltage. Thus, in conjunction with the control voltage limit, the driver should be adapted to drive a switch referenced to another voltage level as described above and adaptively perform the necessary voltage translation to the another voltage level to provide the drive signal. 
   Accordingly, what is needed in the art is a driver for the power converters, and a method of driving a switch thereof, that takes into account a control voltage limit associated with a switch (i.e., the gate voltage limit for a MOSFET) of the power converter referenced to a voltage level different from the driver that overcomes the deficiencies in the prior art. 
   SUMMARY OF THE INVENTION 
   These and other problems are generally solved or circumvented, and technical advantages are generally achieved, by advantageous embodiments of the present invention which includes a driver having switching circuitry referenced to a voltage level and configured to provide a drive signal for a switch referenced to another voltage level and subject to a control voltage limit. In a related, but alternative embodiment, the driver is employable with a power converter couplable to a source of electrical power adapted to provide an input voltage thereto. The power converter includes a power train having a switch referenced to the input voltage and subject to a control voltage limit. The driver includes switching circuitry referenced to a voltage level different from the input voltage and configured to provide a drive signal for the switch within the control voltage limit of the switch. For instance, the switch may be a metal oxide semiconductor field effect transistor (“MOSFET”) having a gate terminal and a source terminal referenced to the input voltage of the power converter. The switching circuitry is therein configured to provide a gate drive signal for the MOSFET within a gate voltage limit thereof. 
   In another aspect and for use with a power converter couplable to a source of electrical power adapted to provide an input voltage thereto, the present invention provides a method of driving a switch of the power converter referenced to the input voltage and subject to a control voltage limit. The method includes providing a drive signal for the switch within the control voltage limit of the switch with switching circuitry referenced from a voltage level different from the input voltage. In this and other aspects of the present invention, the switching circuitry may include a plurality of driver switches couplable to ground wherein ones of the plurality of driver switches are couplable to the ground, the source of electrical power and a bias voltage source for providing a bias voltage. In accordance therewith, ones of the plurality of driver switches are configured to cooperate to provide the drive signal referenced to the input voltage and within the control voltage limit of the switch. Additionally, the switching circuitry may include at least one driver switch configured to enable a mode of operation wherein the drive signal for the switch is referenced to the voltage level of the switching circuitry. 
   In yet another aspect, the present invention provides a power converter couplable to a source of electrical power adapted to provide an input voltage thereto. The power converter includes a power train including a switch, referenced to the input voltage and subject to a control voltage limit, configured to conduct for a duty cycle and provide a regulated output characteristic at an output of the power converter. The power converter also includes a controller configured to provide a signal to control the duty cycle of the switch. The power converter still further includes a driver including switching circuitry referenced to a voltage level different from the input voltage and configured to provide a drive signal for the switch within the control voltage limit as a function of the signal from the controller. Additionally, the controller is configured to provide a complement of the signal to control the duty cycle of the switch. In accordance therewith, the driver is configured to provide the drive signal for the switch within the control voltage limit as a function of the complement of the signal from the controller. 
   The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIG. 1  illustrates a block diagram of an embodiment of a power converter constructed according to the principles of the present invention; 
       FIG. 2  illustrates a schematic diagram of an embodiment of a power train of a power converter constructed according to the principles of the present invention; 
       FIG. 3  illustrates a schematic diagram of a conventional totem pole driver; 
       FIG. 4  illustrates a schematic diagram of an embodiment of a driver constructed according to the principles of the present invention; 
       FIG. 5  illustrates waveform diagrams demonstrating an exemplary operation of the driver of  FIG. 4 ; 
       FIG. 6  illustrates a schematic diagram of another embodiment of a driver constructed according to the principles of the present invention; and 
       FIG. 7  illustrates waveform diagrams demonstrating an exemplary operation of the driver of  FIG. 6 . 
   

   Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the preferred embodiments and are not necessarily drawn to scale. 
   DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS 
   The making and using of the presently preferred embodiments are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention. 
   The present invention will be described with respect to preferred embodiments in a specific context, namely, a driver for a power converter, method of driving a switch thereof and a power converter employing the same. The principles of the present invention, however, may also be applied to all types of power supplies employing various conversion topologies that may benefit from a driver that takes into account a control voltage limit associated with a switch [e.g., the gate voltage limit for a metal oxide semiconductor field effect transistor (“MOSFET”)] of the power converter referenced to a voltage level different from the driver. 
   Referring initially to  FIG. 1 , illustrated is a block diagram of an embodiment of a power converter constructed according to the principles of the present invention. The power converter includes a power train  110 , a controller  120  and a driver  190 , and provides power to a system such as a microprocessor. The power train  110  may employ a buck converter topology as illustrated and described with respect to  FIG. 2  below. Of course, any number of converter topologies may benefit from the use of a driver  190  constructed according to the principles of the present invention and are well within the broad scope of the present invention. 
   The power train  110  receives an input voltage V in  at an input thereof as a power source and provides a regulated output characteristic (e.g., an output voltage) V out  to power a microprocessor or other load coupled to an output of the power converter. The controller  120  receives a digital word representing a desired characteristic such as a desired system voltage V system  from an internal or external source associated with the microprocessor, and the output voltage V out  of the power converter. In accordance with the aforementioned characteristics, the controller  120  provides a signal to control a duty cycle and a frequency of at least one switch of the power train  110  to regulate the output voltage V out  thereof. 
   The controller  120  includes a digital-to-analog converter (“DAC”)  130  that receives a reference voltage V REF  and transforms the desired system voltage V system  in the form of a digital word or format into an analog equivalent (i.e., an analog format). The reference voltage V REF  provides a reference for a calibration of the digital-to-analog conversion process associated with the DAC  130 . The analog format of the desired system voltage V system  is then amplified with a gain K, if necessary, by an operational amplifier  135 . A sparse analog-to-digital converter (“ADC”)  140  of the controller  120  employs the analog format of the desired system voltage V system  and the output voltage V out  to provide an error signal S E  to a duty cycle processor  150 . The error signal S E  typically is in the form of a series of binary error signals and represents a difference between the output voltage V out  of the power converter and the desired system voltage V system  in discrete steps. In an advantageous embodiment, a magnitude of the discrete steps of the error signal S E  is small when the difference is small and a magnitude of the discrete steps of the error signal S E  is larger when the difference is larger. 
   Thus, the sparse ADC  140  determines a difference between the output voltage V out  and the desired system voltage V system  and provides the error signal S E  therefrom. The duty cycle processor  150  then employs the error signal S E  to provide a digital duty cycle signal S D  (e.g., a four or an eight bit digital signal representing a duty cycle) to control a duty cycle of at least one switch of the power converter. An embodiment of a sparse ADC  140  and duty cycle processor  150  are disclosed in U.S. Patent Publication No. 2005/0169024, entitled “Controller for a Power Converter and a Method of Controlling a Switch Thereof,” to Dwarakanath, et al., now U.S. Pat. No. 7,038,438, issued May 2, 2006, which is incorporated herein by reference. 
   The duty cycle processor  150  is coupled to a modulator  180  [e.g., a pulse width modulator (“PWM”)] that converts the digital duty cycle signal S D  from the duty cycle processor  150  into a signal so that the driver  190  (e.g., a gate driver) can control at least one switch of the power converter. An operation of the duty cycle processor  150  is gated by a clock signal S CLK  provided by a clock generator  170 . The clock generator  170  also provides another clock signal S CK  for the sparse ADC  140 , which may be shifted in phase as compared to the clock signal S CLK  for the duty cycle processor  150 . A frequency of the clock signals S CLK , S CK  may be on the order of one thirty-second or one eighth of the switching frequency of the power converter. 
   The switching frequency of the modulator  180  is typically the same as the switching frequency of the power converter and is controlled by an oscillator (e.g., a ring oscillator)  160 . The ring oscillator  160  also provides a high frequency clock signal S CLK-OSC  to the clock generator  170 , which is divided down to produce the clock signals S CLK , S CK . In accordance with the aforementioned characteristics, a drive signal(s) (e.g., a gate drive signal) S DRV  is provided by the driver  190  to control a duty cycle and a frequency of at least one switch of the power converter to regulate the output voltage V out  thereof. 
   There are a number of design choices available for the modulator  180 . For instance, a digital counter may be clocked by the ring oscillator  160 . The modulator  180  reads the digital duty cycle signal S D  from the duty cycle processor  150  and generates a high signal during a portion of the counting cycle that corresponds to a period when a switch of the power converter is being controlled to conduct, and a low signal otherwise. At the end of the counting cycle, the counter resets to zero. The ring oscillator  160  generates a clock signal S CLK-OSC  that can facilitate fine duty cycle granularity or resolution by the modulator  180  thereby allowing accurate control, as necessary, of the output voltage V out  of the power converter. 
   Thus, the modulator  180  supplies a signal that is typically constructed to form a pulse width modulated signal S PWM  to control the duty cycle for at least one switch of the power converter. The modulator  180  can also supply a complement of the signal to control the duty cycle for at least one switch of the power converter (e.g., a complementary pulse width modulated signal S 1-PWM ). The pulse width modulated signal S PWM  and the complementary pulse width modulated signal S 1-PWM  are then fed to the driver  190 . Additionally, an embodiment of a modulator is disclosed in U.S. Patent Publication No. 2005/0168205, entitled “Controller for a Power Converter and Method of Controlling a Switch Thereof,” to Dwarakanath, et al., now U.S. Pat. No. 7,019,505, issued Mar. 28, 2006, which is incorporated herein by reference. 
   The driver  190  then provides the drive signal S DRV  to control at least one switch of the power converter to regulate the output voltage V out  thereof. As will become more apparent, the driver  190  is particularly adapted to take into account a control voltage limit associated with a switch of the power converter. Moreover, the driver  190  resolves a challenge wherein circuitry of the driver is referenced to a voltage level and the switch of the power converter to be driven is referenced to another voltage level. Additionally, the driver  190  may employ techniques to provide sufficient signal delays to prevent crosscurrents when controlling multiple switches in the power converter. While a particular type of controller  120  has been described in the environment of the power converter, those skilled in the art should understand that other controllers (including principally analog controllers) adapted to control at least one switch of the power converter are well within the broad scope of the present invention. 
   Turning now to  FIG. 2 , illustrated is a schematic diagram of an embodiment of a power train of a power converter constructed according to the principles of the present invention. While in the illustrated embodiment, the power train employs a buck converter topology, those skilled in the art should understand that other converter topologies such as a forward converter topology are well within the broad scope of the present invention. 
   The power train of the power converter receives an input voltage V in  (e.g., an unregulated input voltage) from a source of electrical power (represented by a battery) at an input thereof and provides a regulated output voltage V out  to power, for instance, a microprocessor at an output of the power converter. In keeping with the principles of a buck converter topology, the output voltage V out  is generally less than the input voltage V in  such that a switching operation of the power converter can regulate the output voltage V out . A main switch Q mn  (e.g., a P-channel MOSFET) is enabled to conduct for a primary interval (generally co-existent with a primary duty cycle “D” of the main switch Q mn ) and couples the input voltage V in  to an output filter inductor L out . During the primary interval, an inductor current I Lout  flowing through the output filter inductor L out  increases as a current flows from the input to the output of the power train. An AC component of the inductor current I Lout  is filtered by the output capacitor C out . 
   During a complementary interval (generally co-existent with a complementary duty cycle “1-D” of the main switch Q mn ), the main switch Q mn  is transitioned to a non-conducting state and an auxiliary switch Q aux  (e.g., a N-channel MOSFET) is enabled to conduct. The auxiliary switch Q aux  provides a path to maintain a continuity of the inductor current I Lout  flowing through the output filter inductor L out . During the complementary interval, the inductor current I Lout  through the output filter inductor L out  decreases. In general, the duty cycle of the main and auxiliary switches Q mn , Q aux  may be adjusted to maintain a regulation of the output voltage V out  of the power converter. Those skilled in the art should understand, however, that the conduction periods for the main and auxiliary switches Q mn , Q aux  may be separated by a small time interval to avoid cross conduction therebetween and beneficially to reduce the switching losses associated with the power converter. 
   As described above, the main and auxiliary switches Q mn , Q aux , in the illustrated embodiment, are embodied in P-channel and N-channel MOSFETs, respectively. Due to the design of the main switch Q mn  and operating conditions of the power converter, a driver employable to provide a drive signal to control the main switch Q mn  is subject to design challenges that a driver according to the present invention is adapted to overcome. Prior to introducing a driver according to the present invention, a conventional driver and the limitations associated therewith is hereinafter described. 
   Turning now to  FIG. 3 , illustrated is a schematic diagram of a conventional totem pole driver. As mentioned above, the totem pole driver typically includes first and second driver switches Q DR1 , Q DR2  embodied in a P-channel MOSFET and a N-channel MOSFET, respectively, with coupled gate terminals. In the environment of a power converter, the first driver switch Q DR1  is coupled to the source of electrical power for the power converter and the controller of the power converter. A drive signal S DRV  is generated from a junction coupling the drain terminals of the first and second driver switches Q DR1 , Q DR2  of the totem pole driver. When a signal (e.g., a pulse width modulated signal S PWM ) from the controller to the totem pole driver is high, the drive signal S DRV  is essentially grounded. When the signal S PWM  from the controller to the totem pole driver is low, the drive signal S DRV  is substantially equal to the input voltage V in  (e.g., an unregulated input voltage) of the power converter. In effect, the drive signal S DRV  from the totem pole driver exhibits voltages over the entire voltage range of the source of electrical power for the power converter. 
   When providing a drive signal to a switch such as a P-channel MOSFET having a control voltage limit (i.e., a gate voltage limit) of 2.5 volts, and in the environment of a power converter having a nominal input voltage V in  of five volts, the extended voltage range present on the gate terminal of the switch may break down the integrity of the thin gate oxide of the switch. In other words, when the input voltage V in  to the power converter which is translated into the drive signal S DRV  to the switch under certain conditions as described above exceeds the gate voltage limit thereof, the switch may be damaged and fail. Another layer of complexity arises when the first and second driver switches Q DR1 , Q DR2  are referenced to a voltage level (e.g., a ground potential) and the switch to be driven is referenced to another voltage (e.g., the input voltage V in  to the power converter). Colloquially, the switch of the power converter is referred to as a “floating” switch. Thus, the totem pole driver and other presently available drivers are typically not practical for applications wherein the switch to be driven exhibits a smaller control voltage limit (e.g., gate voltage limit) from the control terminal to another terminal (e.g., the gate terminal to the source terminal) thereof and is referenced to a voltage level different from the driver. 
   Turning now to  FIG. 4 , illustrated is a schematic diagram of an embodiment of a driver constructed according to the principles of the present invention. The driver is adapted to provide a drive signal S DRV  to control a switch having a control voltage limit. More specifically and in the illustrated embodiment, the driver is a gate driver that provides a gate drive signal S DRV  to, for instance, a P-channel MOSFET that exhibits a gate voltage limit (i.e., a gate-to-source voltage limit) of 2.5 volts. The gate driver receives a signal (e.g., a pulse width modulated signal S PWM ) from a controller (see, for instance, the controller  120  illustrated and described with respect to  FIG. 1 ) and a complement of the signal (e.g., a complementary pulse width modulated signal S 1-PWM ) from the controller. 
   The gate driver includes switching circuitry formed by a plurality of driver switches such as first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  coupled to a source of electrical power for the power converter and the controller of the power converter. The gate driver is also coupled to a bias voltage source that provides a bias voltage V bias , which may be internally or externally generated and may depend on an input voltage of the power converter. For purposes of the discussion herein, it is assumed that the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  have a low gate voltage limit and a higher voltage drain. Thus, the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  may exhibit a low gate voltage limit (e.g. 2.5 volts) and at the same time handle drain-to-source voltages above the gate voltage limit thereof (e.g., ten volts). 
   To simplify the discussion, it is also assumed that the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  exhibit a gate threshold voltage of about is 0.5 volts, which is consistent with a number of fine feature size, low voltage MOSFET designs. The gate threshold voltage provides a voltage level above or below which (depending on the type) the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  are enabled to conduct. 
   In the illustrated embodiment, the first and second driver switches Q DR1 , Q DR2  are N-channel MOSFETs and the third, fourth, fifth and sixth driver switches Q DR3 , Q DR4 , Q DR5 , Q DR6  are P-channel MOSFETs. The drain terminals of the second, third and fifth driver switches Q DR2 , Q DR3 , Q DR5  are coupled together at a first node n 1 . The drain terminals of the first, fourth and sixth driver switches Q DR1 , Q DR4 , Q DR6  are coupled together at a second node n 2 . While each of the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  are illustrated with gate, source and drain terminals, it is also common for each of the first, second, third, fourth, fifth and sixth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6  to include a body terminal. 
   The gate driver is coupled between an input voltage V in  (e.g., an unregulated input voltage at a nominal five volts) of the power converter and ground, with a potential difference therebetween for the purposes of this discussion of five volts. The source terminal of the third and sixth driver switches Q DR3 , Q DR6  are coupled to the input voltage V in . The bias voltage V bias , assumed for this discussion to be 2.5 volts with respect to the ground, is coupled to the gate terminal of the fourth and fifth driver switches Q DR4 , Q DR5 , and a return connection of the bias voltage source is coupled to the ground. The bias voltage source may or may not be derived from the source of electrical power that provides the input voltage V in , depending on the application for the gate driver. 
   When the pulse width modulated signal S PWM  provided to the second driver switch Q DR2  is high (i.e., when the pulse width modulated signal S PWM  is more positive than the gate threshold voltage of 0.5 volts), the first node n 1  that couples the drain terminals of the second and third driver switches Q DR2 , Q DR3  is pulled low by the second driver switch Q DR2 . The drain terminal of the fifth driver switch Q DR5  is also coupled to the first node n 1  and the gate terminal thereof is coupled to the bias voltage source. Thus, the source of the fifth driver switch Q DR5  is pulled down to three volts (i.e., one gate threshold voltage value more positive than the bias voltage V bias ). The gate drive signal S DRV  is therefore pulled down two volts below the input voltage V in , which is a sufficient voltage to enable a switch such as the main switch Q mn , a P-channel MOSFET, illustrated and described with respect to the power train of the power converter of  FIG. 2  to conduct. 
   When the complementary pulse width modulated signal S 1-PWM  provided to the first driver switch Q DR1  is more positive than the gate threshold voltage, the first driver switch Q DR1  is enabled to conduct and the second node n 2  is pulled down to substantially the ground voltage by an on-resistance of the first driver switch Q DR1 . The gate of the third driver switch Q DR3  is pulled down to about three volts (i.e., one gate threshold voltage value more positive than the bias voltage V bias ). Thus, the third driver switch Q DR3  is enabled to conduct and the drain thereof, coupled to first node n 1 , is pulled up substantially to the input voltage V in . The fifth driver switch Q DR5  is now enabled to conduct because the gate voltage is more than one gate threshold voltage more negative than the drain thereof, and the source of the fifth driver switch Q DR5  is pulled up substantially to the input voltage V in . Therefore, the gate drive signal S DRV  from the gate driver is also pulled up to substantially the input voltage V in , which is a sufficient voltage to transition a switch such as the main switch Q mn , a P-channel MOSFET, illustrated and described with respect to the power train of the power converter of  FIG. 2  to a non-conducting state. 
   Accordingly, a type of level shifting gate driver has been introduced with an improved level-shifting capability that can controllably raise the gate voltage of an exemplary switch (e.g., a P-channel MOSFET) to substantially the input voltage to transition the switch to a non-conducting state, and controllably reduce the gate voltage to a lower voltage to enable the switch to conduct. Inasmuch as the gate terminal of the fifth driver switch Q DR5  is coupled to the bias voltage source V bias , the fifth driver switch Q DR5  is transitioned to a non-conducting state when a voltage present on its source is less than the bias voltage V bias  plus its gate threshold voltage (treating the gate threshold voltage of a P-channel MOSFET as a positive number). If the gate driver properly applies the bias voltage V bias  (e.g., if the bias voltage V bias  is the input voltage V in  minus 2.5 volts and adjusted for the gate threshold voltage of the fifth driver switch Q DR5 ), the gate drive signal S DRV  will not decrease more than 2.5 volts below input voltage V in  thereby not exceeding the gate voltage limit of the switch to be driven. The bias voltage V bias , therefore, is preferably dependent on the input voltage V in . The gate terminal of the switch (again, a P-channel MOSFET) coupled to the gate driver will thus be protected by the gate driver and, in particular, by the fifth driver switch Q DR5 , which operatively provides a protective voltage limiting function. Finally, the gate driver is symmetrical and as the pulse width modulated signal S PWM  and complementary pulse width modulated signal S 1-PWM  alternate, the conduction states and voltages within the gate driver alternate accordingly. 
   Turning now to  FIG. 5 , illustrated are waveform diagrams demonstrating an exemplary operation of the gate driver of  FIG. 4 . At a time t 1 , the complementary pulse width modulated signal S 1-PWM  is at a voltage of 2.5 volts thereby enabling the first driver switch Q DR1  to conduct. Conversely, the pulse width modulated signal S PWM  is at zero volts at the time t 1 , which transitions the second driver switch Q DR2  to a non-conducting state. The gate drive signal S DRV  from the gate driver is maintained at five volts thereby causing the switch such as the main switch Q mn , a P-channel MOSFET as described above, to transition to a non-conducting state. 
   At a time t 2 , a polarity of the pulse width modulated signal S PWM  and the complementary pulse width modulated signal S 1-PWM  alternate thereby causing the second driver switch Q DR2  to transition to a conducting state and causing the first driver switch Q DR1  to transition to a non-conducting state. A short time later at a time t 3 , the gate drive signal S DRV  drops from five volts to 2.5 volts thereby enabling the main switch Q mn , a P-channel MOSFET as described above with a 2.5 volt gate voltage limit, to conduct. The brief delay period between time t 2  and time t 3  represents an intrinsic delay associated with the switching action of the gate driver and may be on the order of a nanosecond. Thereafter, at a time t 4 , the polarity of the pulse width modulated signal S PWM  and the complementary pulse width modulated signal S 1-PWM  alternate. Then, at a time t 5 , the gate drive signal S DRV  correspondingly changes with the brief delay between the time t 4  and the time t 5 , which again is expected to be on the order of a nanosecond. 
   The plurality of driver switches of the switching circuitry of the gate driver referenced to a voltage level (in this case, ground potential) cooperate to provide the gate drive signal S DRV  to a switch (e.g., the main switch Q mn , a P-channel MOSFET, of the power converter) referenced to another voltage level (in this case, the input voltage V in  of the power converter). Thus, in addition to providing a gate drive signal S DRV  within the gate voltage limit of the switch, the gate driver also performs a voltage translation between the gate driver referenced to a voltage level and the switch referenced to another voltage level. 
   Turning now to  FIG. 6 , illustrated is a schematic diagram of another embodiment of a driver constructed according to the principles of the present invention. The driver is adapted to provide a drive signal S DRV  to control a switch having a control voltage limit. More specifically and in the illustrated embodiment, the driver is a gate driver that provides a gate drive signal S DRV  to, for instance, a P-channel MOSFET that exhibits a gate voltage limit (i.e., a gate-to-source voltage limit) of 2.5 volts. The gate driver receives a signal (e.g., a pulse width modulated signal S PWM ) from a controller (see, for instance, the controller  120  illustrated and described with respect to  FIG. 1 ) and a complement of the signal (e.g., a complementary pulse width modulated signal S 1-PWM ) from the controller. 
   The gate driver includes switching circuitry formed by a plurality of driver switches such as first, second, third, fourth, fifth, sixth, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6 , Q DR7 , Q DR8  coupled to a source of electrical power for the power converter and the controller of the power converter. The gate driver is also coupled to a first bias voltage source that provides a first bias voltage V bias1 , which may be internally or externally generated and may depend on an input voltage of the power converter. For purposes of the discussion herein, it is assumed that the first, second, third, fourth, fifth, sixth, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6 , Q DR7 , Q DR8  have a low gate voltage limit and a higher voltage drain. Thus, the first, second, third, fourth, fifth, sixth, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6 , Q DR7 , Q DR8  may exhibit a low gate voltage limit (e.g. 2.5 volts) and at the same time handle drain-to-source voltages above the gate voltage limit thereof (e.g., ten volts). 
   To simplify the discussion, it is also assumed that the first, second, third, fourth, fifth, sixth, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6 , Q DR7 , Q DR8  exhibit a gate threshold voltage of about is 0.5 volts, which is consistent with a number of fine feature size, low voltage MOSFET designs. The gate threshold voltage provides a voltage level above or below which (depending on the type) the first, second, third, fourth, fifth, sixth, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR3 , Q DR4 , Q DR5 , Q DR6 , Q DR7 , Q DR8  are enabled to conduct. 
   In the illustrated embodiment, the first, second, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR7 , Q DR8  are N-channel MOSFETs and the third, fourth, fifth and sixth driver switches Q DR3 , Q DR4 , Q DR5 , Q DR6  are P-channel MOSFETs. The drain terminals of the second, third and fifth driver switches Q DR2 , Q DR3 , Q DR5  are coupled together at a first node n 1 . The drain terminals of the first, fourth and sixth driver switches Q DR1 , Q DR4 , Q DR6  are coupled together at a second node n 2 . While each of the first, second, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR7 , Q DR8  are illustrated with gate, source and drain terminals, it is also common for each of the first, second, seventh and eighth driver switches Q DR1 , Q DR2 , Q DR7 , Q DR8  to include a body terminal. 
   The gate driver is coupled between an input voltage V in  (e.g., an unregulated input voltage at a nominal five volts) of the power converter and ground, with a potential difference therebetween for the purposes of this discussion of five volts. The source terminal of the third and sixth driver switches Q DR3 , Q DR6  are coupled to the input voltage V in . The first bias voltage V bias1 , assumed for this discussion to be 2.5 volts with respect to the ground, is coupled to the gate terminal of the fourth and fifth driver switches Q DR4 , Q DR5 , and a return connection of the first bias voltage source is coupled to the ground. The first bias voltage source may or may not be derived from the source of electrical power that provides the input voltage V in , depending on the application for the gate driver. 
   As illustrated, the seventh and eighth driver switches Q DR7 , Q DR8  are parallel coupled to the fourth and fifth driver switches Q DR4 , Q DR5 , respectively. The seventh and eighth driver switches Q DR7 , Q DR8  include a higher voltage source and a higher voltage drain and typically exhibit a higher source-to-gate voltage handling (e.g., five volts) when the source is more positive than the gate and at the same time handle drain-to-source voltages above the low gate voltage limit thereof. The gate terminal of the seventh and eighth driver switches Q DR7 , Q DR8  are coupled together and to a second voltage bias source that provides a second bias voltage V bias2 , which may be internally or externally generated and may depend on an input voltage of the power converter. 
   The gate driver, in the illustrated embodiment, can operate in a couple of different modes of operation. For instance, when the input voltage V in  to the power converter is greater than an upper gate voltage limit for a main switch Q mn  such as a P-channel MOSFET (see, as an example, the power train of the power converter illustrated and described with respect to  FIG. 2 ) driven by the gate driver, then voltage protective features of the gate driver are enabled (see the description above with respect to the gate driver illustrated in  FIG. 4 ). In this mode of operation, the second bias voltage V bias2  provided to the gate terminals of the seventh and eighth driver switches Q DR7 , Q DR8  is at a ground potential. Since the source terminals of the seventh and eighth driver switches Q DR7 , Q DR8  are not coupled to a potential at or below the ground potential, the seventh and eighth driver switches Q DR7 , Q DR8  are not enabled to conduct as a consequence of the grounded gate terminals thereof. Thus, under the aforementioned circumstances, the seventh and eighth driver switches Q DR7 , Q DR8  have little effect on the operation of the gate driver. 
   In another operating mode for the gate driver (enabled by the seventh and eighth driver switches Q DR7 , Q DR8 ), the input voltage V in  to the power converter is not greater than an upper gate voltage limit for a main switch Q mn  such as a P-channel MOSFET (see, as an example, the power train of the power converter illustrated and described with respect to  FIG. 2 ) driven by the gate driver, then voltage protective features of the gate driver are not necessary. In this mode of operation, the clamping operation of the fifth driver switch Q DR5  on the gate drive signal S DRV  is inoperative. More specifically, the gate terminal of the seventh and eighth driver switches Q DR7 , Q DR8  are coupled to a suitably high potential such as the input voltage V in . As a result, the seventh and eighth driver switches Q DR7 , Q DR8  are enabled to conduct. Thus, the gate drive signal S DRV  is coupled to ground potential by an on resistance of the second and eighth driver switches Q DR2 , Q DR8  when the main switch Q mn , a P-channel MOSFET as discussed above, driven by the gate driver is enabled to conduct. The gate driver, therefore, selectively provides additional flexibility by altering a voltage applied to an input thereof, consequently accommodating an input voltage V in  above or below a gate voltage limit of a switch driven therefrom. 
   Turning now to  FIG. 7 , illustrated are waveform diagrams demonstrating an exemplary operation of the gate driver of  FIG. 6 . As mentioned above, the gate driver described with respect to  FIG. 7  can operate in a couple of different modes of operation. For instance, when the input voltage V in  to the power converter is greater than an upper gate voltage limit for a main switch Q mn  such as a P-channel MOSFET driven by the gate driver, then voltage protective features of the gate driver are enabled. Inasmuch as the operation under such conditions is analogous to the operation of the gate driver described with respect to  FIGS. 4 and 5  above, a detailed description thereof will not be forthcoming. In this mode of operation (see waveforms labeled S PWM , S 1-PWM , S DRVH ), the gate terminal of the seventh and eighth driver switches Q DR7 , Q DR8  are coupled to the second bias voltage V bias2 , which is sufficiently near ground potential that the seventh and eighth driver switches Q DR7 , Q DR8  are not enabled to conduct and hence the operating and associated waveforms are analogous to the waveforms of  FIG. 5 . 
   In another operating mode for the gate driver, the input voltage V in  to the power converter is not greater than an upper gate voltage limit for a main switch Q mn  such as a P-channel MOSFET driven by the gate driver, then voltage protective features of the gate driver are not necessary. In this mode of operation (see waveforms labeled S PWM , S 1-PWM , S DRVL ), the gate terminal of the seventh and eighth driver switches Q DR7 , Q DR8  are coupled to the second bias voltage V bias2 , which is a suitably high potential such as the input voltage V in . The seventh and eighth driver switches Q DR7 , Q DR8  are enabled to conduct, thereby disabling the voltage clamping operation of the fourth and fifth driver switches Q DR4 , Q DR5 . When the main switch Q mn  driven by the gate driver is enabled to conduct, the gate drive signal S DRVL is substantially zero volts between the time t 3  and the time t 5 . When the main switch Q mn  driven by the gate driver is transitioned to a non-conducting state, the gate drive signal S DRVL is held at or below the gate voltage limit of the main switch Q mn . The delay between the time t 2  and time t 3  and the delay between the time t 4  and time t 5  represents an intrinsic delay associated with the switching action of the gate driver and is again expected to be on the order of a nanosecond. 
   The plurality of driver switches of the switching circuitry of the gate driver referenced to a voltage level (in this case, ground potential) cooperate to provide the gate drive signal S DRV  to a switch (e.g., the main switch Q mn , a P-channel MOSFET, of the power converter) referenced to another voltage level (in this case, the input voltage V in  of the power converter). Thus, in addition to providing a gate drive signal S DRV  within the gate voltage limit of the switch, the gate driver also performs a voltage translation between the gate driver referenced to a voltage level and the switch referenced to another voltage level. Additionally, the seventh and eighth driver switches Q DR7 , Q DR8  are configured to enable a mode of operation wherein the gate drive signal S DRV  for the switch is referenced to the voltage level (in this case, the ground potential) of the gate driver. 
   Thus, a driver and related method of driving at least one switch of a power converter with readily attainable and quantifiable advantages has been introduced. Those skilled in the art should understand that the previously described embodiments of the driver, related method, and power converter employing the same are submitted for illustrative purposes only and that other embodiments capable of producing a drive signal for a switch referenced to different voltage levels and having a control voltage limit are well within the broad scope of the present invention. It is further recognized that multiple switches may be included in a power converter and ones of the switches may be referenced to the same ground potential as the driver (e.g., “freewheeling switches” that can be driven with customary drivers such as the totem pole driver described above). Thus, a driver according to the principles of the present invention and a customary driver may be included in the design of a power converter. 
   Additionally, in an advantageous embodiment, a power converter constructed accordingly to the principles of the present invention may be embodied in an integrated circuit. Alternatively, portions of the power converter such as the driver and the power train (or portions thereof) may also be embodied in an integrated circuit and still be within the broad scope of the present invention. In accordance therewith, selected switches or other devices of the power converter may be embodied in a semiconductor device as disclosed in U.S. Patent Publication No. 2005/0167756, entitled “Laterally Diffused Metal Oxide Semiconductor Device and Method of Forming the Same,” to Lotfi, et al., now U.S. Pat. No. 7,230,302, issued Jun. 12, 2007, which is incorporated herein by reference. The driver includes switching circuitry with a plurality of switches referenced to a different voltage that limit a drive signal to a switch within the control voltage limit thereof. As a result, the power converter can be employed in various applications including conditions wherein the switches are subject to a low gate voltage limit. 
   Additionally, exemplary embodiments of the present invention have been illustrated with reference to specific electronic components. Those skilled in the art are aware, however, that components may be substituted (not necessarily with components of the same type) to create desired conditions or accomplish desired results. For instance, multiple components may be substituted for a single component and vice-versa. The principles of the present invention may be applied to a wide variety of power converter topologies. While the driver has been described in the environment of a power converter, those skilled in the art should understand that the driver and related principles of the present invention may be applied in other environments or applications such as a power amplifier, motor controller, and a system to control an actuator in accordance with a stepper motor or other electromechanical device. 
   For a better understanding of digital control theory in power converters see “An Energy/Security Scalable Encryption Processor Using an Embedded Variable Voltage DC/DC Converter,” by John Goodman, Abram P. Dancy and Anantha P. Chandrakasan, IEEE Journal of Solid-State Circuits, Vol. 33, No. 11 (November 1998). For a better understanding of power converters, see “Modern DC-to-DC Switchmode Power Converter Circuits,” by Rudolph P. Severns and Gordon Bloom, Van Nostrand Reinhold Company, New York, N.Y. (1985) and “Principles of Power Electronics,” by J. G. Kassakian, M. F. Schlecht and G. C. Verghese, Addison-Wesley (1991). The aforementioned references are incorporated herein by reference in their entirety. 
   Although the present invention has been described in detail, those skilled in the art should understand that they can make various changes, substitutions and alterations herein without departing from the spirit and scope of the invention in its broadest form.