Patent Publication Number: US-7214619-B2

Title: Method for forming a barrier layer in an integrated circuit in a plasma with source and bias power frequencies applied through the workpiece

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application claims priority of U.S. Provisional Application Ser. No. 60/616,418 filed Oct. 5, 2004 entitled APPARATUS AND METHOD FOR METAL PLASMA VAPOR DEPOSITION AND RE-SPUTTER WITH SOURCE AND BIAS POWER FREQUENCIES APPLIED THROUGH THE WORKPIECE by Karl M. Brown, et al. and assigned to the present assignee. 

   BACKGROUND OF THE INVENTION 
   With recent technological advances in integrated circuit design, there are now as many as six to ten interconnect layers of a multilayer interconnect structure overlying the semiconductor transistors. Insulator layers separate the successive conductor layers. The conductor interconnect layers can have completely different conductor patterns and are connected to one another and to the transistor layer at different locations through vias extending vertically through the insulator layers. It is the formation of the vias with which the present invention is concerned. 
   To reduce resistive power losses in the integrated circuit, the interconnect layers and the vias typically employ aluminum and, more recently, copper as the principal conductor. The insulator layers are silicon dioxide, although more recently dielectric materials other than silicon dioxide having a lower dielectric constant are increasingly being employed. Because copper tends to diffuse over time through the insulator layer to cause catastrophic short circuiting, a barrier layer that blocks copper diffusion is placed between the copper material and the dielectric material wherever the two materials interface in the integrated circuit. The barrier layer is typically formed of an underlying tantalum nitride or titanium nitride layer contacting the insulator layer, an overlying pure (or nearly pure) tantalum (or titanium) layer and, finally, a copper seed layer over the pure tantalum (or titanium) layer. If the conductor is to be copper, then tantalum is preferred. The copper conductor is deposited on the copper seed layer. Such a barrier layer prevents migration or diffusion of copper atoms into the dielectric material. The tantalum and tantalum nitride (or titanium and titanium nitride) layers are poor conductors compared to copper. The formation of the barrier layer and of the copper conductors is carried out by physical vapor deposition. Other deposition processes may be employed for the metal fill step (copper deposition) such as chemical vapor deposition, plasma enhanced chemical vapor deposition or electroplating. 
   A problem arises in forming the vertically extending vias extending between the horizontal interconnect layers, as follows. Each vertical via opening is formed by etching a hole through an overlying horizontal insulator (silicon dioxide) layer so as to expose a portion of the copper conductor in the underlying horizontal interconnect layer. It is this exposed portion to which connection is to be made through the via. A barrier layer must be deposited on the interior surfaces of the via before the copper conductor can be formed in the via, to prevent copper migration as explained above. This barrier layer, in covering all interior surfaces of the via, covers the exposed portion of the underlying copper conductor. Since the barrier layer is an inferior conductor, it must be selectively removed from the underlying copper conductor (in an etch process) without removing the remainder of the barrier layer from the other interior surfaces of the via. This removal step has required interruption of the physical vapor deposition process in order to place the wafer in an etch chamber where the step of selectively removing the barrier layer from the underlying copper surface is carried out. The wafer is then returned to a physical vapor deposition reactor for formation of the copper conductor(s). 
   The interruption represented by the selective removal of the barrier layer entails a higher production cost and consumes production time. In recent years, a dual purpose reactor was developed capable of both physical vapor deposition of the barrier layer and selective removal of the barrier layer after the barrier layer formation step, without removing the wafer from the reactor. As a result, great savings in production cost and production time have been realized. This was accomplished by providing in the physical vapor deposition chamber a separate coil near the wafer. After barrier layer formation, the coil is used to form an inductively coupled plasma which selectively sputters the barrier layer from horizontal surfaces (i.e., the floor formed by the underlying copper conductor). Such selective sputtering (hereinafter referred to as “re-sputtering”) is achieved by applying RF bias power to the wafer to achieve an ion velocity distribution that is predominantly vertical. While this dual-purpose reactor works extremely well, it does entail some additional expense. For example, since the barrier layer deposition step involves sputtering a metal target and therefore deposits metal over all interior surfaces of the reactor chamber, the re-sputtering coil must be located inside the chamber so that no metallized surfaces shield the coil or otherwise prevent inductive coupling of RF power from the re-sputtering coil to the plasma. In order to avoid process contamination, the re-sputtering coil is formed of pure tantalum, adding cost. The coil is subject to very large temperature fluctuations during its lifetime, and must be changed periodically. RF power must be coupled to the re-sputtering coil through the vacuum seal of the reactor chamber and through an environment that periodically is completely filled with metal vapor. Therefore, an RF feedthrough must be employed that can tolerate the metal deposition, and whose exterior surfaces are textured to avoid excessive accumulation of deposited materials and flaking, and that can tolerate wide temperature excursions over its lifetime. 
   Another well-known dual-purpose reactor employs an external inductive coil overlying a portion of the ceiling not blocked by the metal sputter target. One problem is that the metal vapor deposition process can coat the ceiling with metal and thereby block inductive coupling from the coil antenna. A more significant problem is that the RF plasma produced by the coil produces a high proportion of metal ions from the target, so that the wafer bias cannot be optimized for etch selectivity to horizontal surfaces without impacting (de-optimizing) the flux of metal ions/vapor from the target. Therefore, the metal deposition process and the re-sputter process must be performed at separate times. 
   It should be noted that although such dual purpose reactors are capable of performing both the Ta/TaN barrier layer deposition step and the re-sputtering step, a different reactor is typically employed to perform the subsequent copper deposition step. This is because a high flux of copper ions on the wafer is desired, and the PVD reactor must be specially configured in order for the sputtered copper atoms to self-ionize in a very dense plasma at the copper target. Specifically, a very high D.C. power level (40–56 kWatts) is applied to the copper target and a specially configured magnetron is employed for a more concentrated plasma at the target. Because of the high density of copper ions near the target, it is placed very high above the wafer (390 mm), which limits the copper deposition rate to an acceptable threshold (as well as providing some beneficial collimation of copper neutrals). Typically, however, are large share of the copper ions are deposited on shields in the chamber and otherwise lost while traveling over this long distance. 
   In addition to the requirement for a copper PVD chamber and a barrier PVD chamber, a third chamber, an etch chamber, must be employed to carry out a pre-deposition cleaning process, since the copper PVD chamber and the barrier PVD/re-sputter chamber are not suitable for clean/etch processes. 
   Another problem is the tendency of the tantalum and/or tantalum nitride material deposited during formation of the barrier layer to deposit with non-uniform thickness along the via walls, and in particular to accumulate faster near the top corners of the vertical walls and thereby exhibit some tendency toward pinch-off. This makes it necessary to restrict the process window in order to ameliorate such problems. This problem is solved to some extent when, upon completion of the barrier layer deposition process, the re-sputtering process is performed, because the re-sputtering process tends to remove tantalum or tantalum nitride from the tops and corners of the via walls faster than elsewhere, while transferring tantalum (or tantalum nitride) material removed from the horizontal surfaces (floors) of the vias onto the lower portions of the via sidewalls. Nevertheless, it would be beneficial to avoid altogether the initial non-uniform tantalum or tantalum nitride deposition problem, to eliminate any risk of pinch-off, permitting some liberalization of the process window. 
   It would also be beneficial to avoid the necessity of the internal re-sputtering coil provided at least some of its benefits could be realized in a simpler manner. 
   The present invention provides benefits at least approaching those afforded by the internal re-sputtering coil without the need for such a coil. The present invention furthermore provides a way of ameliorating or avoiding non-uniform deposition of the barrier layer, and a way of avoiding or minimizing deposition of the barrier layer on the exposed copper conductor surface forming the floor of the via during formation of the barrier layer. 
   SUMMARY OF THE INVENTION 
   A barrier layer is formed in an integrated circuit by providing a metal target near a ceiling of the chamber and a wafer support pedestal facing the target near a floor of the chamber. A process gas is introduced into the vacuum chamber. A target-sputtering plasma is maintained at the target to produce a stream of principally neutral atoms flowing from the target toward the wafer for vapor deposition. A wafer-sputtering plasma is maintained near the wafer support pedestal to produce a stream of sputtering ions toward the wafer support pedestal for re-sputtering. The sputtering ions are accelerated across a plasma sheath at the wafer in a direction normal to a surface of the wafer to render the sputter etching highly selective for horizontal surfaces. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a cut-away side view of a plasma reactor embodying the invention. 
       FIG. 2  is an enlarged cut-away view of a wafer support pedestal in accordance with one aspect. 
       FIG. 3  is an enlarged cut-away view of a wafer support pedestal in accordance with another aspect. 
       FIG. 4  illustrates the use of two different plasma bias power frequencies in the reactor of  FIG. 1 . 
       FIG. 5  is a graph illustrating the combination of the different ion energy distributions of the different bias power frequencies in the embodiment of  FIG. 4 . 
       FIGS. 6A through 6E  are sequential cross-sectional views of a portion of an integrated circuit, in accordance with a process of the invention. 
       FIG. 7  is an enlarged cross-sectional view of a barrier layer formed in the process of  FIGS. 6A through 6E . 
       FIGS. 8A through 8C  illustrate the formation of a barrier layer in one embodiment of a process of the invention. 
       FIGS. 9A and 9B  illustrate the formation of a barrier layer in the preferred embodiment of a process of the invention. 
       FIG. 10  is a block flow diagram of a preferred process of the invention. 
       FIGS. 11A ,  11 B and  11 C are cross-sectional side views of an narrow opening through a dielectric layer, and depict deposition results in three respective modes of the reactor of  FIG. 1 , namely a conformal mode, a non-conformal mode and a punch-through mode, respectively. 
       FIG. 12  illustrates a plasma reactor in accordance with a first alternative embodiment. 
       FIG. 13  illustrates a plasma reactor in accordance with a second alternative embodiment. 
       FIG. 14  illustrates a plasma reactor in accordance with a third alternative embodiment. 
       FIG. 15  illustrates a plasma reactor in accordance with a fourth alternative embodiment. 
       FIG. 16  illustrates a plasma reactor in accordance with a fifth alternative embodiment. 
       FIG. 17  depicts a process in which the reactor of  FIG. 1  performs a pre-deposition cleaning process, a dielectric barrier layer deposition process and a metal barrier layer deposition process on the same wafer. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   A plasma reactor forms barrier layers (such as a tantalum/tantalum nitride film or titanium/titanium nitride film) for conductors (such as copper, for which the barrier should be tantalum/tantalum nitride) in trenches or through vias between successive interconnection layers of an integrated circuit. The plasma reactor is capable of both physical vapor deposition and of highly selective re-sputtering to remove barrier material from the exposed horizontal surfaces of the underlying conductor constituting the floor of the via. Significantly, the reactor accomplishes all this without an internal coil that had previously been required for a fully and precisely controllable re-sputtering step. Instead, a plasma is formed near the wafer to perform the re-sputtering step. For this purpose a process gas such as argon may be introduced and source power is applied to the wafer at an RF frequency effective for capacitively coupling energy to kinetic electrons to excite argon plasma ions near the wafer. The term “source power” as employed in this specification refers to RF power suitable for maintain an RF-coupled plasma by coupling power to kinetic electrons in the plasma. This is to be distinguished from use of the term “source” when referring to the D.C. excited metal sputtering target, which is the “source” of the metal atoms or ions in a metal deposition process. Typically, the source power frequency is a VHF frequency because of the low mass-to-charge ratio of electrons. The ions of the VHF-coupled plasma formed near the wafer are employed in the re-sputtering step. The selectivity of the re-sputtering step for horizontal surfaces is established by applying bias power to the wafer at an RF frequency effective for coupling energy to the ions (e.g., argon ions), which is typically an HF or LF frequency because of the high mass-to-charge ratio of the ions. This constricts the ion velocity distribution across the plasma sheath at the wafer surface to a small directional range about the chamber axis, typically a vertical direction, making the re-sputtering step highly selective for surfaces perpendicular to the chamber axis, typically horizontal surfaces. A significant feature is that the bias power controls the selectivity of the ion re-sputter or etch step without affecting the flux of metal atoms from the target toward the wafer. This is facilitated by a low power (2–5 kW) D.C. discharge plasma at the target surface which produces primarily neutral metal particles or atoms from the target that are unaffected by the bias power applied to the wafer. Thus, two different plasmas are employed, one being a D.C. discharge plasma at the target and the other being an RF (VHF) plasma at the wafer. Therefore, the target sputtering may be optimized without affecting the re-sputtering plasma at the wafer, while the bias voltage may be optimized without affecting the target sputtering. This feature is not possible in conventional ion physical vapor deposition reactors that employ RF coupled plasmas near the target to produce metal ions for the physical vapor deposition process. 
   An advantageous mode is provided that is unique to the present invention in which the physical vapor deposition and the re-sputtering can be performed simultaneously, and the selectivity of the re-sputter or etch process is adjusted without affecting the flux of metal atoms from the target. 
   The re-sputtering step tends to compensate for non-uniform deposition of the barrier layer material. Therefore, in one embodiment of the invention, the re-sputter step is performed simultaneously with the barrier deposition step. This is possible because a preferred embodiment of the invention produces two somewhat independent plasmas, namely a D.C. discharge plasma near the ceiling or target that is confined by a magnetron above the target and an RF plasma near the wafer surface to perform the re-sputtering. Thus, the plasma near the ceiling is optimized for sputtering the target while (simultaneously) the plasma at the wafer is optimized for re-sputtering and selectively etching the floor of each via. One advantage is that prominent non-uniformities in the deposited barrier layer film are reduced or are never formed, thereby reducing the risk of pinch-off or other problems in the vias. Another advantage of this embodiment is that throughout the entire barrier deposition/re-sputter process, accumulation of barrier material can be entirely avoided on the exposed horizontal surface of the underlying conductor forming the floor of the via. This is accomplished by adjusting the barrier material deposition rate (controlled largely by the tantalum target D.C. sputter voltage) relative to the re-sputter rate (controlled largely by the VHF plasma source power applied to the wafer.) 
   The invention can afford certain advantages depending upon it application. For example, a low power (2–5 kW) D.C. power level is employed to sputter the metal target for all deposition process, including copper, tantalum and titanium, because metal neutrals are desired. Therefore, the target height above the wafer and the magnetron design are the same in all these processes, so that the same chamber can perform any or all of them. The target height above the wafer can be relatively low, or between about 225 mm and 290 mm, for example. In addition, the VHF source power applicator and the HF bias power applicator can be used without a target to excite a plasma (such as argon plasma) to perform a pre-deposition clean process prior to each deposition process. Such a pre-clean process can be repeated prior to each and all of the deposition steps, including the barrier metal (tantalum) deposition step, the barrier dielectric (tantalum nitride) barrier deposition step, the copper seed layer deposition step and the copper conductor deposition step. 
   Reactor Apparatus: 
   Referring to  FIG. 1 , a reactor of a first embodiment of the invention includes a vacuum chamber defined by a cylindrical side wall  10 , a disk-shaped ceiling  12 , and a wafer support pedestal  14  for supporting a semiconductor wafer  16  to be processed. A target  18  of a metal (e.g., tantalum) to be deposited on the wafer  16  is mounted on the ceiling  12 . A process kit consisting of a cylindrical shield  20  surrounds the wafer  16  and the target  18 . A magnetron  22  of the conventional type overlies the target  18  on the external side of the ceiling  12 . A high voltage D.C. source  24  is coupled to the target  18 . A process gas injector  26  furnished process gas from a supply  28  into the interior of the chamber. A vacuum pump  30  maintains a desired sub-atmospheric pressure in the vacuum chamber. 
   The wafer pedestal  14  is coupled through an impedance match network  34  to a VHF plasma source power generator  36  and to an HF or LF plasma bias power generator  38 . The high voltage D.C. source maintains an upper plasma  40  near the target  18 . The VHF plasma source power generator  36  maintains a lower plasma  42  at or near the surface of the wafer  16 . The two plasmas  40 ,  42  may be maintained simultaneously or may be produced at different times. The upper plasma  40  is a D.C. discharge plasma that enables sputtering of the target  18  to produce mainly neutral metal atoms from the target  18  that deposit on the wafer, with some metal ions from the target  18 . The lower plasma  42  is a capacitively coupled RF plasma that promotes selective etching of horizontal surface on the wafer  16 . The two plasmas  40 ,  42  may be controlled independently, for separate control of the metal deposition process and the re-sputter process. The LF bias power applied to the wafer determines the selectivity of the re-sputter/etch process for horizontal surfaces. Plasma uniformity, particularly uniformity of the plasma  42  nearest the wafer, is controlled by an electromagnetic coil  43  wrapped around the cylindrical sidewall of the reactor chamber and supplied with D.C. current by a current source controller  45 . 
   Coupling of the VHF source power and HF or LF bias power to the wafer is illustrated in  FIG. 2 . The wafer support pedestal  14  can be an electrostatic chuck (ESC) for electrostatically holding the wafer  16  in place. In this case, the ESC or pedestal consists of an insulating layer  50  mounted on a conductive base  51  and an electrode  52  such as a conductive mesh buried inside the insulating layer  50 . The pedestal structure can extend downwardly in a coaxial arrangement consisting of a center conductor  54  connected to the electrode  52 , an insulating intermediate layer  56  and an outer conductor  58  connected to the conductive base  51 . The conductive base can be coupled to the bottom of the cylindrical shield  20  by conductive tabs  60  to provide a more continuous ground reference. The center conductor  54  is coupled to the RF power sources while the outer conductor  58  is grounded. The impedance match network  34  consists of a conventional impedance match circuit  64  coupled to the RF (VHF) plasma source power generator  36  and a conventional impedance match circuit  68  coupled to the RF (HF or LF) plasma bias power generator  38 . The output of the impedance match circuit  64  is connected through a high pass filter  65  to the wafer pedestal center conductor  54 , while the output of the impedance match circuit  68  is connected through a low pass filter  69  to the wafer pedestal center conductor  54 . In addition, a D.C. chuck voltage source  74  is connected to the wafer pedestal center conductor  54  and is isolated from RF power by an isolation capacitor  76 . The high pass filter  65  has a sufficiently high cut-off frequency to prevent HF or LF current from the RF generator  38  from reaching the VHF match circuit  64 , while the low pass filter has a sufficiently low cut-off frequency to prevent VHF current from the RF generator  36  from reaching the HF (or LF) match circuit  68 . 
     FIG. 3  illustrates another embodiment of the wafer support pedestal  14  in which the electrode  52  contacts the wafer, and there is no electrostatic chucking of the wafer. In this case, since the electrode  52  is potentially exposed to the plasma, the electrode  52  can be formed of the material to be deposited on the wafer, such as tantalum. 
     FIG. 4  illustrates an embodiment in which the bias power consists of both HF and LF frequencies (e.g., 13.56 MHz and 2 MHz, respectively, for example). For this purpose, there are two bias power RF generators, namely an HF bias power generator  38   a  and an LF bias power generator  38   b , the generators  38   a ,  38   b  being coupled through respective match circuits  68   a ,  68   b  to the wafer pedestal center conductor  54 . The VHF source power generator  36  is coupled through its impedance match circuit  64  and through the high pass filter  65  to the wafer pedestal center conductor  54 . One advantage of this embodiment is that the lower ion energy distribution of the HF bias and the higher ion energy distribution of the LF bias (both shown in  FIG. 5 ) can be combined to produce an ion energy distribution that peaks between the peaks of the LF and HF ion energy distributions. This peak can be shifted up or down in energy by adjusting the relative power levels of the LF and HF power generators  38   a ,  38   b.    
   The deposition rate of the target material (e.g., tantalum) is mainly determined by the power delivered by the D.C. voltage source to the target. The selectivity of the etch/re-sputter process (for horizontal surfaces) is determined by the bias power, while the rate of the etch/re-sputter process is mainly determined by the source power level. Therefore, there are three parameters that can be controlled independently of one another, namely metal deposition rate, etch selectivity for horizontal surfaces and etch rate. Since all these can be controlled independently of one another, the metal deposition and etch/re-sputter process may be performed simultaneously, if desired. 
   PVD/Re-Sputter Method: 
   The reactor of  FIG. 1  is particularly useful in the formation of metal contacts between successive interconnection layers of an integrated circuit. Typically, an integrated circuit includes an active semiconductor layer having thousands of transistors and many insulated interconnection layers stacked over the active semiconductor layer and providing complex interconnection circuits among the transistors. The connections between interconnection layers are formed through vias or vertical holes between the interconnection layers by filling the holes with a metal such as copper. In order to prevent failure by short circuiting due to diffusion of copper through insulating material, a barrier layer of tantalum and tantalum nitride is placed between the copper and the insulating material. It is in the deposition of the barrier layer within the via that the reactor of  FIG. 1  provides great advantage. 
     FIG. 6A  is an enlarged cross-sectional side view of a partially fabricated portion of an interconnection layer  100  in a stack of many interconnection layers overlying an active semiconductor layer (now shown).  FIG. 6B  is the corresponding top view. The interconnection layer  100  includes, among many conductors, a pair of parallel copper conductors  102 ,  104  embedded in an insulator (silicon dioxide) layer  106 . Each copper conductor  102 ,  104  is separated from the dielectric layer  106  by a barrier layer  108  that prevents diffusion of copper atoms into the dielectric layer  106 . Preferably, the barrier layer  108  includes a tantalum nitride layer contacting the insulator layer  106  and covered by a tantalum layer and a copper seed layer. The structure is best shown in the enlarged view of  FIG. 7 , which shows a tantalum nitride layer  110  covering the insulator layer  106 , a tantalum metal layer  112  overlying the tantalum nitride layer  110  and a copper seed layer  114  overlying the tantalum metal layer  112 . A copper conductor, such as the copper conductor  102 , overlies the copper seed layer  114 . The tantalum metal layer  112  establishes a high quality bond with the tantalum nitride layer  110 , while the copper seed layer establishes a high quality bond with the tantalum metal layer  112  on one side and the copper conductor  102  on the opposite side. 
   Before the next interconnection layer is formed on the top surface of the insulator layer  106 , a vertical opening or via  120  is opened through the insulator layer  106 , typically by etch processes ( FIGS. 6A and 6B ). The via  120  consists of a large opening  122  extending only partly through the insulator layer  106  and a pair of smaller openings  124  extending down to the respective copper conductors  102 ,  104 . Typically, the etching process that forms the two smaller openings  124  is carried out sufficiently to remove the exposed portion of the barrier layer  108  overlying each conductor  102 ,  104  ( FIG. 6A ). 
   The via  120  forms a vertical conductor when later filled with copper. However, before copper is deposited into the via  120 , a barrier layer  130  is deposited onto all surfaces in the via  120  and onto the top surface of the insulator layer  106  as shown in  FIG. 6C . The barrier layer  130  has the same structure as that described above with reference to  FIG. 7 , including a tantalum nitride layer  110 , a metal tantalum layer  112  and a copper seed layer  114 . In one embodiment of the invention, each sub-layer  110 ,  112 ,  114  of the barrier layer  120  is deposited in a separate step by providing the appropriate material for the metal target  18  (tantalum for the sub-layers  110 ,  112  and copper for the sub-layer  114 ). The target  18  is sputtered by introducing a process gas which is ionized in the vicinity of the target by the large D.C. sputtering voltage from the sputter voltage source  24 . In order to deposit the tantalum nitride sub-layer  110 , nitrogen is employed as the process gas, and the tantalum atoms combine with nitrogen atoms as they impact the wafer to form a tantalum nitride film. When depositing the metal tantalum layer  112  and, later, when depositing the copper seed layer  114 , the process gas is an inert or non-reactive gas, such as Argon. Thus, three deposition steps are carried out. First, using a tantalum sputtering target and nitrogen process gas, tantalum nitride is deposited. Second, using a tantalum target and argon process gas, metallic tantalum is deposited. Third, using a copper target and argon gas, a copper seed layer is deposited. 
   In one embodiment of the invention, no plasma RF (VHF) source power is applied to the wafer support pedestal  14 , although a modest level of plasma RF (HF or LF) bias power may be applied. In this way, metal is sputtered from the target  18  and deposited onto the wafer  16 . As a result, the barrier layer  130  is formed by carrying out the three deposition steps for the successive sub-layers  110 ,  112 ,  114 . The barrier layer  130  covers all exposed surfaces including the portions of the copper conductors  102 ,  104  exposed by the small openings  124 , as shown in  FIG. 6C . 
   After each of the three deposition steps have been completed, an etch/re-sputter step is carried out ( FIG. 6D ) in which the VHF plasma source power generator  36  and the HF (or LF) plasma bias power generator  38  deliver power to the wafer support pedestal  14 . This produces a plasma near the wafer that furnishes ions guided to the horizontal surfaces by the applied plasma bias power. These ions sputter the horizontal surfaces to remove films deposited thereon, such as the portion of the barrier layer  130  at the bottom of the small openings  124 . Within the small openings  124 , the close proximity of the vertical walls (or small diameter of the openings  124 ) promotes the re-deposition of atoms sputtered from the floor  124   a  of each opening  124  onto the vertical side wall. This uncovers the copper conductors, as desired, as illustrated in  FIG. 6D . In other areas where there is no vertical wall, such as the vast area of the top surface of the insulator layer  106 , the sputtered atoms re-deposit onto the horizontal surface, so that there is no net loss. 
   In a preferred embodiment, each of the three deposition process steps (corresponding to the three layers  110 ,  112 ,  114 ) is performed simultaneously with the etch and re-sputter process step. In this preferred embodiment, the sputter voltage source  24  delivers power to the target  18 , while simultaneously the VHF plasma source power generator  36  and the HF (or LF) plasma bias power generator  38  deliver power to the wafer support pedestal  14 . This produces a plasma near the wafer that furnishes ions guided to the horizontal surfaces by the applied plasma bias power while atoms from the target  18  are being deposited. Deposition of atoms from the target  18  on the horizontal surfaces such as the exposed portions of the copper conductors  102 ,  104  is avoided provided the etch rate on the horizontal surfaces rival the deposition rate of atoms from the target  18 . This condition is realized by an appropriate adjustment of the voltage of the D.C. sputter voltage source  24  (to adjust the deposition rate) and of the power level of the VHF source power generator  36 . The power level of the HF (or LF) bias power generator  38  is adjusted to achieve the desired degree of etch selectivity for horizontal surfaces. The result is that the barrier layer  130  is not formed over the horizontal floor of the via  120 , so that the process sequence skips the state illustrated in  FIG. 6C . 
   The next step ( FIG. 6E ) is to deposit a thick copper layer to form the next interconnect layer  200  and vertical conductors extending through the via  120  between the lower interconnect conductors  102 ,  104  and the upper interconnect layer  200 , as shown in  FIG. 6E . 
   The sequence illustrated in  FIGS. 8A through 8C  shows one advantage of the re-sputtering step of  FIG. 6D .  FIG. 8A  illustrates one of the small openings  124  prior to deposition of the barrier layer  130 .  FIG. 8B  shows how the barrier layer  130  is formed in cases where the re-sputtering step is not carried out simultaneously with the deposition step. Specifically, the barrier layer  130  tends to accumulate with greater thickness near the top edge of the small opening  124  and with smaller thickness near the bottom of the opening  124 . The re-sputtering step removes the excess material from the top edge and removes the material from the floor of the small opening and re-deposits it on the vertical side wall, so that the thickness distribution along the vertical side wall becomes more uniform, as indicated in  FIG. 8C . The problem is that the thicker accumulation of barrier material near the top edge of the small opening  124  may lead to pinch-off, so that the re-sputter step could have no beneficial effect, the device would fail. 
   This risk is avoided in the preferred method in which the re-sputter step ( FIG. 6D ) and the deposition step ( FIG. 6C ) are carried out simultaneously. In this preferred mode, the process begins with a newly formed small opening  124  in  FIG. 9A  and transitions directly to a uniform barrier layer  130  in  FIG. 9B . The simultaneous deposition/re-sputtering prevents the deposition process from forming significant non-uniformities in the barrier layer  130 . This eliminates the risk of the pinch-off effect illustrated in  FIG. 8B . 
     FIG. 10  is a block diagram illustrating the preferred process. In block  310  of  FIG. 10 , a deposition D.C. discharge plasma is generated around the target  18  (near the ceiling) to deposit atoms from the target onto the wafer. In block  312 , a re-sputter capacitively coupled RF plasma is generated near the wafer to produce ions to bombard the wafer to re-sputter the deposited atoms from the target  18 . In the step of block  314 , plasma RF bias power is applied to the wafer. The bias power is sufficient to render the sputtering highly selective for horizontal surfaces. In block  320 , the plasma source power applied to the wafer and the D.C. sputter voltage applied to the target are adjusted relative to one another so that the re-sputter rate is at least nearly as great as the sputter deposition rate. 
   One embodiment of the PVD/re-sputter reactor of the invention is capable of depositing three different type of layers by operating in three different modes, specifically, in mode (A), a highly conformal layer with uniform sidewall and horizontal surface coverage, in mode (B), a non-conformal layer with little or no sidewall coverage, and in mode (C), a “punch through” layer with good sidewall coverage and good horizontal surface coverage in a large field, but no coverage of bottom surfaces of high aspect ratio openings. The conformal layer of mode (A), illustrated in  FIG. 11A , is obtained by applying a relatively low level of D.C. power to the target (e.g., 5 kW), high VHF source power to the wafer (1 kW at 60 MHz) and a low level of HF bias power to the wafer (about 100 W at 13.56 MHz). The non-conformal layer of mode (B), illustrated in  FIG. 11B , is obtained under the same conditions except that the HF bias power level is reduced to zero. The “punch-through” layer of mode (C), illustrated in  FIG. 11C , is obtained by increasing the bias power to a high level (500 W at 13.56 MHz). The conformal mode is particularly useful for depositing the copper conductor layer. The non-conformal mode is particularly useful for covering the bottom or floor of a via with a low-resistance metal such as tantalum or titanium. The punch-through mode is the preferred mode for depositing the barrier layer (Ta and TaN) in a via. 
   In some cases, the plasma density distribution may differ between the three modes described above. In order to maintain more uniform plasma density distribution, the current source controller  45  may cause different levels of D.C. current to flow through the electromagnet coil  43  in different ones of the three modes. In any case, the current level furnished by the current controller  45  is preferably optimized to improve the radial plasma ion density uniformity in the process zone. 
   Each of the three modes described above with reference to  FIGS. 11A ,  11 B and  11 C may be implemented by a process controller  210  shown in  FIG. 1  whose outputs control the power level of the target high voltage D.C. supply  24 , the power level of the VHF plasma source power generator  36  and the power level of the HF or LF bias power generator  38 . The process controller  210  may be controlled by a user through a user interface  212 , allowing the user to program the controller to have the reactor of  FIG. 1  automatically transition between any of the operating states defined above for the conformal mode, the non-conformal mode and the punch through re-sputter mode. The process controller (or processor)  210  therefore has three states to which the user may set or program the processor  210  to enter into. One state is the conformal deposition mode in which the processor  210  sets the D.C. power level of the supply  24  to a low level, sets the power level of the VHF generator  36  to a high level and the HF/LF bias generator  36  to a low level. The another state is the non-conformal mode in which the processor  210  sets the D.C. power level of the supply  24  to a low level, sets the power level of the VHF generator  36  to a high level and the HF/LF bias generator  38  to zero (or nearly zero) level. The remaining state is the punch through state in which the processor  210  sets the D.C. power level of the supply  24  to a low level, sets the power level of the VHF generator  36  to a high level and the HF/LF bias generator  38  to a high level. 
   The processor  210  may also govern the electromagnet current source  45 , so that in each of the three modes ( FIGS. 11A ,  11 B,  11 C), the current level is optimized for a more uniform radial distribution of plasma ion density distribution. 
   The metal target  18  may assume a shape different from the disk shape illustrated in  FIG. 1 . For example, as shown in  FIG. 12 , a modified target  18 ′ having an annular shape may be employed, leaving a center portion  12   a  of the ceiling  12  exposed and an annular portion  12 ′ blocked by the target  18 ′. The overlying magnetron  22 ′ has a corresponding annular configuration. Optionally, VHF plasma source power may be applied to the ceiling center portion  12   a  by an additional VHF source power generator  66 ′ (dashed line in  FIG. 12 ). This may be in addition to or in lieu of the VHF source power generator  36  coupled to the wafer support pedestal  14 . However, it is preferred to couple VHF source power to the pedestal  14  rather than to the ceiling  12 . 
     FIG. 13  depicts another option, in which a coil antenna  400  may be placed over the ceiling center portion  12 ′ and coupled to an RF source power generator  410  through an impedance match circuit  415  to produce an inductively coupled plasma. A louvered shield  420  may cover the ceiling center portion  12   a  during metal deposition to avoid metal coverage of the ceiling center portion  12   a , so that the coil antenna  400  will not be shielded from the plasma. 
     FIG. 14  illustrates how the configuration of the coil antenna  400  and target  18 ′ may be reversed from that illustrated in  FIG. 13 . In  FIG. 14 , the coil antenna  400  is in an annular shape while the disk-shaped target  18  is located at the ceiling center portion  12   a . The reactor of  FIG. 14  may be modified as follows: The annular coil antenna  400  may be removed and the peripheral portion  12 ′ of the ceiling  12  may be conductive and coupled to the VHF plasma source power generator  410  through the impedance match circuit  415 , as indicated in dashed line in  FIG. 14 . 
     FIG. 15  illustrates another alternative embodiment in which the target  18  is configured in an inverted cup shape. As shown in  FIG. 16 , the cup shape may be of sufficient height to accommodate an array of magnets  450  along its side to enhance ion distribution. 
     FIG. 17  is a flow diagram of a process carried out in the PVD/re-sputter chamber of  FIG. 1 . In the step of block  1710 , a pre-clean process is performed by applying no power to the metal target, introducing an etchant precursor gas such as a fluorine-contain gas or a neutral gas such as argon, applying sufficient VHF plasma source power to the wafer from the VHF generator  36  and applying a small amount of HF bias power to the wafer from the HF generator  38 . In the following step of block  1720 , the dielectric film (e.g., TaN) of a barrier layer is deposited by introducing nitrogen gas and sputtering the metal target (e.g., tantalum) while re-sputtering by maintaining the VHF-driven argon plasma near the wafer and applying bias power to the wafer. In the next step (block  1730 ), the metal film of the barrier layer is deposited by stopping the supply of nitrogen gas, so that pure metal is deposited while the VHF-driven argon plasma performs re-sputtering. Thus, three successive processes may be performed in the PVD re-sputter reactor of  FIG. 1  without removing the wafer from the reactor. 
   While the invention has been described in detail with reference to preferred embodiments, it is understood that variations and modifications thereof may be made without departing from the true spirit and scope of the invention.