Patent Publication Number: US-8988049-B2

Title: Multiple switch power stage control tracking PCM signal input

Description:
BACKGROUND OF THE INVENTIONS 
     1. Technical Field 
     The present inventions relate to PCM to a set of digital PWM signals and, more particularly, relate to PCM to a set of digital PWM signals for multiple switch power stage control. 
     2. Description of the Related Art 
     Envelope Tracking is a method of powering the RF (radio frequency) power amplifier using a power signal which is a function of the RF signal envelope to improve power conversion efficiency of an RF envelope. As bandwidth of the RF signal increases for newer signals like 3G and 4G cellular standards, there is a move towards the use of digital circuitry to create the PWM (pulse width modulation) signals. The switching frequency of the PWM signal has to be significantly greater than the bandwidth of the RF signal envelope. As the bandwidth of the RF signal envelope goes into tens of MHz (megahertz) and higher the switching frequency of the PWM would get into the hundreds of MHz. The efficiency of a switching signal operating at such a high switching frequency is low due to the switching losses associated with the PWM power stage. As a result the efficiency of the envelope tracking RF power amplifier is reduced which is highly undesirable. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
       The details of the preferred embodiments will be more readily understood from the following detailed description when read in conjunction with the accompanying drawings wherein: 
         FIG. 1  illustrates a block diagram of the system where a Digital PCM Signal is used to produce an output voltage which powers an RF Power Amplifier according to embodiments of the present inventions; 
         FIG. 2  illustrates a schematic block diagram of PCM to Dual Digital PWM driving a power stage which provides envelope tracking to an RF Power Amplifier according to a embodiments of the present inventions; 
         FIG. 3  illustrates a schematic block diagram of PCM to Triple Digital PWM driving a power stage which provides envelope tracking to an RF Power Amplifier according to a embodiments of the present inventions; 
         FIG. 4  illustrates a schematic block diagram of PCM to Quad Digital PWM driving a power stage which provides envelope tracking to an RF Power Amplifier according to embodiments of the present inventions; 
         FIG. 5  illustrates a Block Diagram of PCM to Dual Digital PWM for Envelope Tracking according to embodiments of the present inventions; 
         FIG. 6  illustrates a Block Diagram of PCM to Triple Digital PWM for Envelope Tracking according to embodiments of the present inventions; 
         FIG. 7  illustrates a Block Diagram of PCM to Quad Digital PWM for Envelope Tracking according to embodiments of the present inventions; 
         FIG. 8  illustrates a State Space diagram of the Dual Digital PWM according to embodiments of the present inventions; 
         FIG. 9  illustrates a Timing Waveform of PCM to Dual Digital PWM for Envelope Tracking according to embodiments of the present inventions; 
         FIG. 10  illustrates a State Space diagram of the Triple Digital PWM according to embodiments of the present inventions; 
         FIG. 11  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between zero and one third according to embodiments of the present inventions; 
         FIG. 12  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between one third and two third according to embodiments of the present inventions; 
         FIG. 13  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between two third and one according to embodiments of the present inventions; 
         FIG. 14  illustrates a State Space diagram of the Quad Digital PWM according to embodiments of the present inventions; 
         FIG. 15  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between zero and one fourth according to embodiments of the present inventions; 
         FIG. 16  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between one fourth and half according to embodiments of the present inventions; 
         FIG. 17  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between half and three fourth according to embodiments of the present inventions; 
         FIG. 18  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between three fourth and one according to embodiments of the present inventions; 
         FIG. 19  illustrates a schematic diagram of a Dual Power Stage and Low Pass Filter according to according to embodiments of the present inventions; 
         FIG. 20  illustrates a Plot over time of Inductor Currents without Imbalance Correction for a dual power stage according to embodiments of the present inventions; 
         FIG. 21  illustrates a Plot over time of Inductor Currents with Imbalance Correction for a dual power stage according to embodiments of the present inventions; 
         FIG. 22  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum at 1 MHz for a dual power stage according to embodiments of the present inventions; 
         FIG. 23  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum at 9 MHz for a dual power stage according to embodiments of the present inventions; 
         FIG. 24  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum at 18 MHz for a dual power stag according to embodiments of the present inventions; 
         FIG. 25  illustrates a Tracking Plot over time LTE20 Envelope for a dual power stage according to embodiments of the present inventions; 
         FIG. 26  illustrates a Spectrum Plot over frequency of LTE20 Envelope Spectrum for a dual power stage according to embodiments of the present inventions; and 
         FIG. 27  illustrates a Flowchart of the system according to embodiments of the present inventions. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
       FIG. 1  illustrates a block diagram of the system where a Digital PCM Signal  101  is used to produce an output voltage which defines the power output needed from an RF Power Amplifier  112 . This power output from an RF Power Amplifier  112  tracks the Digital PCM Signal  101 . A plurality of N switches  106  control a switching power stage for the RF Power Amplifier  112  containing N inductors  108  and a filter  110 . For optimum efficiency and fidelity it is desired that each of the N switches  106 , also known as stages, share the output current and power equally. 
     Sampler  102  can be used to sample the Digital PCM Signal  101  based on a Sampling Clock  103  and produces output Sampled Digital PCM Signal  105 . The sampling frequency of the Sampler  102  is preferably at a sampling ratio of two times a number N of switches  106  times a switching frequency of the switches  106 . Alternatively the sampler  102  is unneeded when the Digital PCM Signals  101  already is delivered at this sampling ratio. 
     Single to N mapping unit  114  takes PCM signal input sampled at 2·N·F SW  and produces N digital PWM signals  117 . Since each PWM signal has two transitions in a switching period the mapping unit switches only one of the N digital PWM signals at a time. The N digital PWM signals  117  are the input to the Imbalance correction unit  104 . The switching of the Single to N mapping unit  114  switches to generate all the PWM signals at a same switching frequency F SW . When N is 2 the mapping unit switches one signal transition in each one-quarter of the PCM signal input. When N is 3 the mapping unit switches one signal transition in each one-sixth of the PCM signal input. When N is 4 the mapping unit switches one signal transition in each one-eighth of the PCM signal input. 
     Imbalance Correction Unit  104  produces output Duty Ratio Adjusted N Digital PWM Signals  107  for the switches  106 . The imbalance correction unit adjusts a duty ratio of the N digital PWM signals relative to one another based on differentially accumulating errors among the N digital PWM signals to prevent divergence of N digital PWM signals. The Imbalance Correction Unit  104  has an explicit control mechanism for substantially equal sharing of the currents among the inductors. The Imbalance Correction Unit  104  contains an accumulator that accumulates differences between the stages and forces equal sharing of current between the stages. The Imbalance Correction Unit  104  also helps cancel the switching frequency at the output of the system. 
     N Switches  106  have input Duty Ratio Adjusted Sampled Digital PWM Signals  107  and drive output Inductors  108  from a DC (direct current) source such as battery  109 . The N switches are each coupled to a corresponding one of the N digital balanced PWM signals. Since the N switches are controlled by the N digitally balanced PWM signals, both the mapping unit and thus the switches switch only one the N digital PWM signal at a time. 
     The PCM signal input arrives or is generated at a sampling frequency which is relatively high. It is desirable to support a high sampling frequency while keeping the switching frequency of the N digital PWM signals F SW  low. 
     The PCM signal input preferably arrives at the sampling frequency of the PCM signal input two times the integer number N times the switching frequency (2×N×F SW ). The integer number N is the number of digital PWM signals generated therefrom by the mapping unit. The integer number N is also the number of switches. A sampler would sample the PCM signal input at a sampling frequency two times the integer number N times the switching frequency (2×N×F SW ). The sampler could be used if the PCM signal input didn&#39;t arrive at the frequency of this sampling frequency. 
     The mapping unit thus switches each of the N digital PWM signals at the switching frequency that is the sampling frequency of the PCM signal input divided by a product of 2 times the integer number N. When N is 2 the mapping unit switches each of the 2 digital PWM signals at the switching frequency that is one-quarter of the sampling frequency of the PCM signal input. When N is 3 the mapping unit switches each of the 3 digital PWM signals at the switching frequency that is one-sixth of the sampling frequency of the PCM signal input. When N is 4 the mapping unit switches each of the 4 digital PWM signals at the switching frequency that is one-eighth of the sampling frequency of the PCM signal input. 
     A plurality of Inductors  108  are configured in parallel and each take input from a corresponding one of the plurality of N Switches  106 . The N Inductors  108  preferably produce a single output that is filtered by Filter  110 . The N inductances are in parallel, each of the N inductances coupled to a corresponding one of the N switches to produce a combined signal. Filter  110  is a low pass filter coupled to filter the combined signal and to remove out of band variants as will later be seen with reference to  FIGS. 22-24  and  FIG. 26 . Filter  110  takes input from N Inductors  108  and produces output V OUT    113  which powers the RF Power Amplifier  112 . RE Power Amplifier  112  has an input  111  and power supply V OUT    113  and produces output RF OUT    115 . 
     This invention introduces a way of reducing the switching frequency without reducing the performance of the system. It introduces a multiple PWM system where there are two or more digital PWM signals that are generated from a single PCM (pulse control modulation) input. The PCM input is upsampled to the product of two times the switching frequency and the number of PWM signals using digital interpolation filters. By using digital cancellation the switching frequency and intermodulation of the switching frequency and the frequencies in the envelope signal are cancelled. The lowest undesired frequency produced is the switching frequency times the number of PWM signals and the intermodulation of this frequency and the frequencies in the envelope signal. These frequencies are quite high and can be easily filtered using physically small passive L-C low pass filters. 
     A pair of digital PWM signals has edges at four times the switching frequency. However, the edges of the two digital PWM signals cross each other depending on the duty ratio of the PWM. The inventions introduce a method to map the PCM samples at four times the switching frequency to rising and falling edges of a pair of PWM signals in manner that preserves the linearity of the output signals. Further, there is no frequency content at the switching frequency or intermodulation between the switching frequency and the frequencies in the envelope signal. 
     The dual PWM signals are amplified by dual power stages and filtered by a passive L-C filter which also combines the square waves to produce a single output which powers the RF power amplifier. 
     For triple and quad cases the signals are amplified by triple or quad power stages and filtered by a passive L-C filter which also combines the square waves to produce a single output which powers the RF power amplifier. 
     In digital PWM generation a high speed quantization clock for example, at 6 GHz is counted to generate the PWM signal. The duty ratios of the PWM signal are quantized such that the PWM signal edge coincides with an edge of the high speed clock. The pair of digital PWM signals drive a pair of power stages which are combined using two inductors. 
     For optimum efficiency and fidelity of the output signal it is desired that the stages share the output current equally. However, the PWM duty ratios of the multiple stages are driven by consecutive PCM signal values and further quantized for generation of the duty ratios. The current in the inductors are set by the integrals of the PWM voltages. Thus it is possible and even likely that over a number of PWM cycles the current in the multiple stages will diverge from each other. In this invention a method is introduced to share the current between the multiple stages without sensing the current which would be costly and cumbersome. 
       FIG. 2  illustrates a schematic block diagram of PCM to Dual Digital PWM driving a Power Stage which provides Envelope Tracking to an RE Power Amplifier according to embodiments. PCM to Dual Digital PWM  202  takes input from PCM at 4E SW    201  and produces two output PWM 1  at F SW    203  and PWM 2  at E SW    205 . PWM 1  at F SW    203  is the gating signal for switch RA 1    204  and PWM 2  at F SW    205  is the gating signal for switch RA 2    206 . Switch RA 1    204  and RA 2    206  both connect to DC voltage source  109  and also connected to diodes D 1    208  and D 2    210 . When the switches are off the diodes connect the switching node to ground. Inductors L 1    212  and L 2    214  both are connected to the same Low Pass Filter  216 . The currents in the Inductors L 1    212  and L 2    214  are IL 1    207  and IL 2    209  respectively. Low Pass Filter produces output V OUT    113  which powers the RE Power Amplifier  112 . RF Power Amplifier  112  has input RF IN    111  and produces output RE OUT    115 . 
       FIG. 3  illustrates a schematic block diagram of PCM to Triple Digital PWM driving a Power Stage which provides Envelope Tracking to an RE Power Amplifier according to embodiments. PCM to Triple Digital PWM  302  takes input from PCM at 6F SW    301  and produces three output PWM 1  at F SW    303 , PWM 2  at F SW    305  and PWM 3  at F SW    307 . PWM 1  at F SW    303  is the gating signal for switch RA 1    304 , PWM 2  at F SW    305  is the gating signal for switch RA 2    306  and PWM 3  F SW    307  is the gating signal for switch RA 3    308 . Switch RA 1    304 , RA 2    306  and RA 3    308  are connect to DC voltage source  109  and also connected to diodes D 1    310 , D 2    312  and D 3    314 . When the switches are off the diodes connect the switching node to ground. Inductors L 1    316 , L 2    318  and L 3    320  are connected to the same V OUT    113  and capacitor C  322 . V OUT    113  which powers the RF Power Amplifier  112 . RE Power Amplifier  112  has input RF N    111  and produces output RF OUT    115 . 
       FIG. 4  illustrates a schematic block diagram of PCM to Quad Digital PWM driving a Power Stage which provides Envelope Tracking to an RF Power Amplifier according to embodiments. PCM to Quad Digital PWM  402  takes input from PCM at 8F SW    401  and produces four output PWM 1  at F SW    403 , PWM 2  at F SW    405 , PWM 3  at F SW    407  and PWM 4  at F SW    409  PWM 1  at F SW    403  is the gating signal for switch RA 1    404 , PWM 2  at F SW    405  is the gating signal for switch RA 2    406 , PWM 3  at F SW    407  is the gating signal for switch RA 3    408  and PWM 4  at F SW    409  is the gating signal for switch RA 4    410 . Switch RA 1    404 , RA 2    406 , RA 3    408  and RA 4    410  are connect to DC voltage source  109  and also connected to diodes D 1    412 , D 2    414 , D 3    416  and D 4   418 . When the switches are off the diodes connect the switching node to ground. Inductors L 1    420 , L 2    422 , L 3    424  and L 4    426  are connected to the same V OUT    113  and capacitor C  428 . V OUT    113  which powers the RF Power Amplifier  112 . RE Power Amplifier  112  has input RF N    111  and produces output RF OUT    115 . 
       FIG. 5  illustrates a Block Diagram of PCM to Dual Digital PWM for Envelope Tracking  500  according to embodiments. Noise Shaper  502  takes input from PCM at 4F SW    201  and produces output Corrected PCM at 4F SW    503 . Duty Ratio Quantizer  504  takes input from Corrected PCM at 4F SW    503  and produces output Duty Ratio at 4F SW    505 . Single to Dual Mapping Unit  506  takes input from Duty Ratio at 4F SW    505  and produces two outputs D 1  at 2F SW    507  and D 2  at 2F SW    509 . Imbalance Correction  508  takes two inputs from D 1  at 2F SW    507  and D 2  at 2F SW    509  and produces two corrected outputs DC 1  at 2F SW    511  and DC 2  at 2F SW    513 . Differential Error Accumulator  510  takes two input from DC 1  at 2F SW    511  and DC 2  at 2F SW    513  and produces output Imbalance Error  515 . Imbalance Quantizer  512  takes input from Imbalance Error  515  and produces two outputs Quantized Imbalance Error 1    517  and Quantized Imbalance Error 2    519 . The Quantized Imbalance Error 1    517  and Quantized Imbalance Error 2    519  are added to the D 1  at 2F SW    507  and D 2  at 2F SW    509  to produce 2F SW    511  and DC 2  at 2F SW    513 . Dual Counter  514  takes two inputs from DC 1  at 2F SW    511  and DC 2  at 2F SW    513  and produces two output PWM 1  at F SW    203  and PWM 2  at F SW    205 . PWM1 at FSW  203  and PWM2 at FSW  205  when applied to a dual power stage produce a combined output signal that is proportional to PCM at 4FSW  201 . 
       FIG. 6  illustrates a Block Diagram of PCM to Triple Digital PWM for Envelope Tracking  600  according to embodiments. Noise Shaper  602  takes input from PCM at 6F SW    301  and produces output Corrected PCM at 6F SW    603 . Duty Ratio Quantizer  604  takes input from Corrected PCM at 6F SW    603  and produces output Duty Ratio at 6F SW    605 . Duty Ratio at 6F SW    605  is input to Single to Triple Mapping Unit  606 . Single to Triple Mapping Unit  606  takes input from Duty Ratio at 6F SW    605  and produces three outputs D 1  at 2F SW    607 , D 2  at 2F SW    609  and D 3  at 2F SW    611 . D 1  at 2F SW    607 , D 2  at 2F SW    609  and D 3  at 2F SW    611  are takes input from Single to Triple Mapping Unit  606  and produces output Imbalance Correction  608 . Imbalance Correction  608  takes two input from D 1  at 2F SW    607 , D 2  at 2F SW    609  and D 3  at 2F SW    611  and produces three outputs corrected duty ratios DC 1  at 2F SW    613 , DC 2  at 2F SW    615  and DC 3  at 2F SW    617 . DC 1  at 2F SW    613 , DC 2  at 2F SW    615  and DC 3  at 2F SW    617  are takes input from Imbalance Correction  608  and produces output Triple Counter  614 . Imbalance Error Accumulator  610  takes three input from DC 1  at 2F SW    613 , DC 2  at 2F SW    615  and DC 3  at 2F SW    617  and produces output Imbalance Error  619 . Imbalance Error  619  takes input from Imbalance Error Accumulator  610  and produces output Imbalance Quantizer  612 . Imbalance Quantizer  612  takes input from Imbalance Error  619  and produce three outputs Quantized Imbalance Error 1    621 , Quantized Imbalance Error 2    623  and Quantized Imbalance Error 3    625 . Quantized Imbalance Error 1    621 , Quantized Imbalance Error 2    623  and Quantized Imbalance Error 3    625  takes input from Imbalance Quantizer  612  and going to Imbalance Correction  608 . Triple Counter  614  takes three input from DC 1  at 2F SW    613 , DC 2  at 2F SW    615  and DC 3  at 2F SW    617  and produces three output PWM 1  at F SW    303 , PWM 2  at F SW    305  and PWM 3  at F SW    307 . 
       FIG. 7  illustrates a Block Diagram of PCM to Quad Digital PWM for Envelope Tracking  700  according to embodiments. Noise Shaper  702  takes input from PCM at 8F SW    401  and produces output Corrected PCM at 8F SW    703 . Duty Ratio Quantizer  704  takes input from Corrected PCM at 8F SW    703  and produces output Duty Ratio at 8F SW    705 . Single to Quad Mapping Unit  706  takes input from Duty Ratio at 8F SW    705  and produces four outputs D 1  at 2F SW    707 , D 2  at 2F SW    709 , D 3  at 2F SW    711  and D 4  at 2F SW    713 . Imbalance Correction  708  takes inputs from D 1  at 2F SW    707 , D 2  at 2F SW    709 , D 3  at 2F SW    711  and D 4  at 2F SW    713  and produce four outputs DC 1  at 2F SW    715 , DC 2  at 2F SW    717 , DC 3  at 2F SW    719  and DC 4  at 2F SW    721 . Imbalance Error Accumulator  710  takes four inputs from DC 1  at 2F SW    715 , DC 2  at 2F SW    717 , DC 3  at 2F SW    719  and DC 4  at 2F SW    721  and produces output Imbalance Error  723 . Imbalance Quantizer  712  takes input from Imbalance Error  723  and produces four outputs Quantized Imbalance Error 1    725 , Quantized Imbalance Error 2    727 , Quantized Imbalance Error 3    729  and Quantized Imbalance Error 4    731 . Imbalance Error 1    725 , Quantized Imbalance Error 2    727 , Quantized Imbalance Error 3    729  and Quantized Imbalance Error 4    731  takes input from Imbalance Quantizer  712  and going to Quad Counter  714 . Quad Counter  714  takes four input from DC 1  at 2F SW    715 , DC 2  at 2F SW    717 , DC 3  at 2F SW    719  and DC 4  at 2F SW    721  and produces four outputs PWM 1  at F SW    403 , PWM 2  at F SW    405 , PWM 3  at F SW    407  and PWM 4  at F SW    409 . 
       FIG. 8  illustrates a State Space diagram of the Dual Digital PWM. There are four possible states: A  801  which corresponds to PWM 1  and PWM 2  equal to 00, B  802  which corresponds to PWM 1  and PWM 2  equal to 01, C  803  which corresponds to PWM 1  and PWM 2  equal to 10, D  804  which corresponds to PWM 1  and PWM 2  equal to 11. 
     When 0&lt;PCM&lt;1/2 the transitions follow the pattern CABACABACABA. 
     When 1/2&lt;PCM&lt;1 the transitions follow the pattern CDBDCDBDCDBD. The objectives of the State Space diagram are to generate PWM signals that maintain a fixed switching frequency F SW  over all possible duty ratios, while cancelling the switching frequency at the output voltage at the output of the switcher. Another objective of the system is to map a PCM signal sampled at four times the switching frequency to the pair of PWM signals. The system starts at state C or 10 at the beginning of the PWM cycle. Depending on the level of the PCM input the system goes to state A 00 or D 11. Independent of the PCM level the next state is state B 01. From state B 01 the system goes to A 00 or D 11 depending on the level of the PCM. The next state from this is state C 10 which completes the PWM cycle. Depending on the level of PCM being greater than or less than half the system follows the two switching patterns. 
       FIG. 9  illustrates a Timing diagram of the system. The PCM signal sampled at four times the switching frequency is mapped to four edges of the pair of PWM signals. As the duty ratio changes the PWM edges that map to the PCM samples change but the mapping works for the entire range of duty ratios. Even though the PWM signals vary vastly based on the level of the PCM signal in every PWM cycle there exists two points where PWM 1  equals PWM 2 . Further, there is one point in each PWM cycle where PWM 1 =1 and PWM 2 =0. Conversely there is another point in the PWM cycle where PWM 1 =0 and PWM 2 =1. In each quarter of the PWM cycle there is exactly one edge of one the two PWM signals but which PWM signal is dependent on the level of the PCM signal. For low PCM values, during first quarter Q 1  the first PCM sample of the cycle maps to PWM 1  going down from 1 to 0 while PWM 2  stays at 0. For high PCM values, during first quarter Q 1  the first PCM sample of the cycle maps to PWM 2  going from 0 to 1 while PWM 1  stays at 1. Thus the mapping of the PCM signal to PWM 1  or PWM 2  and rising or falling edge are variable depending on the level of the PCM signal. 
     The delay times are related to the PCM input in a linear fashion. This is also called Uniform Sampling. Uniform sampling has a residual nonlinearity. However, this invention has high linearity with Uniform Sampling because of the high sample rate. Uniform Sampling also eliminates any additional computation related to linearization which is also desirable. In  FIG. 8  the relationship between the times and the PCM values are given by the Table 1 Dual PWM Truth Table. They have also been summarized by the following equations.
 
 dt   11   =T   SW   PCM   11 /2
 
 dt   12   =T   SW (1−2 PCM   12 )/4
 
 dt   13   =T   SW   PCM   13 /2
 
 dt   14   =T   SW (1−2 PCM   14 )/4
 
 dt   21   =T   SW   PCM   21 /2
 
 dt   22   =T   SW (1−2 PCM   22 )/4
 
 dt   23   =T   SW (1 −PCM   23 )/2
 
 dt   24   =T   SW (2 PCM   24 −1)/4
 
 dt   31   =T   SW (1− PCM   31 )/2
 
 dt   32   =T   SW (2 PCM   32 −1)/4
 
 dt   33   =T   SW (1 −PCM   33 )/2
 
 dt   34   =T   SW (2 PCM   34 −1)/4
 
The relationship between the PCM value and the PWM transition times is formally given by the truth table given below.
 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Dual PWM Truth Table 
               
            
           
           
               
               
               
               
               
               
               
               
               
               
            
               
                   
                 PCM 
                 PWM 1   
                 PWM 2   
                 Start 
                 PWM 1   
                 PWM 2   
                 End 
                 Signal 
                 Signal 
               
               
                 Q 
                 value 
                 at start 
                 at start 
                 state 
                 at end 
                 at end 
                 state 
                 change 
                 Change time 
               
               
                   
               
               
                 Q 1   
                 &lt;0.5 
                 1 
                 0 
                 C 
                 0 
                 0 
                 A 
                 PWM 1   
                 (2pcm)Tsw/4 
               
               
                   
                 &gt;0.5 
                 1 
                 0 
                 C 
                 1 
                 1 
                 D 
                 PWM 2   
                 (2-2pcm)Tsw/4 
               
               
                 Q 2   
                 x 
                 0 
                 0 
                 A 
                 0 
                 1 
                 B 
                 PWM 2   
                 (1-2pcm)Tsw/4 
               
               
                   
                   
                 1 
                 1 
                 D 
                 0 
                 1 
                 B 
                 PWM 1   
                 (2pcm-1)Tsw/4 
               
               
                 Q 3   
                 &lt;0.5 
                 0 
                 1 
                 B 
                 0 
                 0 
                 A 
                 PWM 2   
                 (2pcm)Tsw/4 
               
               
                   
                 &gt;0.5 
                 0 
                 1 
                 B 
                 1 
                 1 
                 D 
                 PWM 1   
                 (2-2pcm)Tsw/4 
               
               
                 Q 4   
                 x 
                 0 
                 0 
                 A 
                 1 
                 0 
                 C 
                 PWM 1   
                 (1-2pcm)Tsw/4 
               
               
                   
                   
                 1 
                 1 
                 D 
                 1 
                 0 
                 C 
                 PWM 2   
                 (2pcm-1)Tsw/4 
               
               
                   
               
            
           
         
       
     
       FIG. 10  illustrates a State Space diagram of the Triple Digital PWM. There are eight possible states 1001 A 000, 1002 B 001, 1003 C 010, 1004 D 100, 1005E 011, 1006 F 101, 1007 G 110 and 1008 H 111 for PWM 1 , PWM 2  and PWM 3  respectively. 
     When 0&lt;PCM&lt;1/3 the transitions follow the pattern: 
     BACADABACADABACADA. 
     When 1/3&lt;PCM&lt;2/3 the transitions follow the pattern: 
     BECGDFBECGDFBECGDF. 
     When 2/3&lt;PCM&lt;1 the transitions follow the pattern: 
     HEHGHFHEHGHFHEHGHF. 
     The objectives of the State Space diagram is to generate PWM signals that maintain a fixed switching frequency F SW  over all possible duty ratios, cancel the switching frequency at the output voltage at the output of the switcher. Another objective of the system is to map a PCM signal sampled at six times the switching frequency to the three PWM signals. Depending on the level of PCM being between zero and a third, between a third and two third, between two third and one the system follows one of the three switching patterns. The PCM signal being band limited is typically smooth and transitions are between adjacent regions. The switching patterns in adjacent regions are chosen to have every other state being equal to allow easy transition between the three switching patterns if PCM crosses the one third or the two third value. 
       FIG. 11  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between zero and one third. 
       FIG. 12  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between one third and two third. 
       FIG. 13  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between two third and one. 
       FIG. 14  illustrates a State Space diagram of the Quad Digital PWM. There are 16 possible sates for the four PWM signals. The states are 1401 A 0000, 1402 B 0001, 1403 C 0010, 1404 D 0100, 1405 E 1000, 1406 F 0011, 1407 G 0101, 1408 H 0110, 1409 I 1001, 1410 J 1010, 1411K 1100, 1412 L 0111, 1413 M 1011, 1414 N 1101, 1415 O 1110 and 1418 P 1111. Of these states in one embodiment states G and J are avoided. 
     When 0&lt;PCM&lt;1/4 the transitions follow the pattern: 
     BACADAEABACADAEABACADAEA. 
     When 1/4&lt;PCM&lt;1/2 the transitions follow the pattern: 
     BFCHDKEIBFCHDKEIBFCHDKEI. 
     When 1/2&lt;PCM&lt;3/4 the transitions follow the pattern: 
     MFLHOKNIMFLHOKNIMFLHOKNI. 
     When 3/4&lt;PCM&lt;1 the transitions follow the pattern: 
     MPLPOPNPMPLPOPNPMPLPOPNP. 
     The objectives of the State Space diagram are to generate PWM signals that maintain a fixed switching frequency F SW  over all possible duty ratios, while cancelling the switching frequency at the output voltage at the output of the switcher. Another objective of the system is to map a PCM signal sampled at eight times the switching frequency to the four PWM signals. Depending on the level of PCM being between zero and a fourth, between a fourth and half, between half and three quarter, between three quarter and one the system follows one of the four switching patterns. The PCM signal being band limited is typically smooth and transitions are between adjacent regions. The switching patterns in adjacent regions are chosen such that every other state is equal to allow an easy transition between the four switching patterns if PCM crosses the fourth, half or the three quarter value. 
       FIGS. 8 ,  10  and  14  show the state space diagrams for the 2, 3 and 4 digital PWM signals respectively. In general, the mapping unit switches the N digital PWM signals in the integer number N of transitions between N plus 1 layers of 2 N  states. Further, the switching of the mapping unit is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances. Also the mapping unit switches signal transitions in like patterns with common states. 
     In the switching of the mapping unit, the transitions alternate between layers. In the switching of the mapping unit, every other transition returns to an adjacent state on a same layer within one of N ranges of values of the N digital PCM signals. 
       FIG. 15  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between zero and one fourth. 
       FIG. 16  illustrates a Timing Waveform of PCM to Triple Digital PWM for Envelope Tracking for the case that the PCM is limited between one fourth and half. 
       FIG. 17  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between half and three fourth. 
       FIG. 18  illustrates a Timing Waveform of PCM to Quad Digital PWM for Envelope Tracking for the case that the PCM is limited between three fourth and one. 
     Exemplary timing waveforms of PCM to 4 digital PWM signals are illustrated in  FIGS. 15 to 18 . In general the mapping unit switches such that a center of the pulses of the N digital PWM signals are equally spaced from one another. Further the mapping unit switches signal transitions in symmetrical patterns time offset by like phase differences between the N digital PWM signals. 
       FIG. 19  illustrates a schematic diagram of a dual Power Stage and Low Pass Filter according to embodiments. RA 1    204  and RA 2    206  are the high side switches connected to voltage source DC  109 . Switches RB 1    1902  and RB 2    1904  are the low side switches connected to ground and implement diode functionality. Inductors L 1    212  and L 2    214  connect the switching to the Capacitor C 1    1908 . The currents in the inductors L 1    212  and L 2    214  are IL 1    207  and IL 2    209  respectively. Inductor L 3    1906  takes combination of inputs of L 1    212 , L 2    214 , IL 1   207  and IL 1    209  and produces output V OUT    113 . Capacitor C 2    1910  is connected between the V OUT  node  113  and ground. 
       FIG. 20  shows the time domain plot of the Inductor Currents without Imbalance Correction. Note that the currents are starting to diverge. If the modulation signal has content at sub harmonics of the PWM switching frequency the inductor current can even change polarity. This would result in significantly worse efficiency and linearity of the power stage. 
       FIG. 21  shows the time domain plot of the Inductor Currents with Imbalance Correction. Note that the currents are controlled to converge in a manner keep their average values even though their instantaneous values are quite different. The ripple has opposite phase so that the switching frequency is cancelled almost entirely. 
       FIG. 22  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum. The single tone is at 1 MHz. There is also large content at dc. The switching frequency is chosen to be at 61.44 MHz. The lowest undesired spectral content is around twice the switching frequency. This is significantly easier to filter than having content at the switching frequency. 
       FIG. 23  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum. The single tone is at 9 MHz. There is also large content at dc. The switching frequency is chosen to be at 61.44 MHz. The lowest undesired spectral content is at twice the switching frequency mixed with 9 MHz and its harmonics. This is significantly easier to filter than having content at the switching frequency. We also see a small nonlinearity at 18 MHz which is about 50 dB lower than the desired signal at 9 MHz. 
       FIG. 24  illustrates a Spectrum Plot over frequency of Single Tone Large Signal Spectrum. The single tone is at 18 MHz. There is also large content at dc. The switching frequency is chosen to be at 61.44 MHz. The lowest undesired spectral content is at twice the switching frequency mixed with 18 MHz and its harmonics. This is significantly easier to filter than having content at the switching frequency. We also see a small nonlinearity at 36 MHz which is about 60 dB lower than the desired signal at 18 MHz. 
       FIG. 25  illustrates a Plot over time of Tracking of LTE20 Signal Spectrum. The signals shown are the reference and output voltage of the switcher normalized to unity. The small time delay through the LC filter has been compensated to illustrate the tracking accuracy better. 
       FIG. 26  illustrates a Plot over frequency spectrum of LTE20 Envelope. Note that the signal is high up to 18 MHz and then falls down gradually from that. There is a single spectral line at twice the switching frequency at 122.88 MHz. 
       FIG. 27  illustrates a Flowchart of the system according to embodiments of the present inventions to provide a power output that tracks a PCM signal input. The PCM signal input arrives at a sampling frequency in step  2701 . The sampling frequency of the PCM signal input is two times an integer number N times the switching frequency (2×N×F SW). Step  2703  generates the integer number of N digital PWM signals each switched at a same switching frequency by switching states of the N digital PWM signals one at a time based on a level of the PCM signal input. Step  2005  adjusts a duty ratio of the N digital PWM signals relative to one another based on differentially accumulating errors among the N digital PWM signals to prevent divergence of N digital PWM signals and produce N balanced digital PWM signals. Step  2709  switches the N digital balanced PWM signals adjusted in the step  2005  to switch power from a DC power source based on corresponding ones of N digital PWM signals. The switching in step  2709  is limited to switching between only those state combinations of the N digital PWM signals such that the switching frequency is cancelled in the combined signal from the N inductances. The switching in said step  2709  switches only one the N digital PWM signals at a time. Step  2715  inductively combines in parallel each of the signals switched in the step  2709 . Step  2721  low pass filters the combined signal inductively combined in the step  2715  to provide the power output tracking the PCM signal input. 
     Many of the signal processing techniques disclosed herein with reference to the accompanying drawings are preferably implemented on one or more digital signal processors (DSPs) or other microprocessors. Nevertheless, such techniques could instead be implemented wholly or partially as hardwired circuits. Further, it is appreciated by those of skill in the art that certain well known digital processing techniques are mathematically equivalent to one another and can be represented in different ways depending on choice of implementation. 
     Any letter designations such as (a) or (b) etc. used to label steps of any of the method claims herein are step headers applied for reading convenience and are not to be used in interpreting an order or process sequence of claimed method steps. Any method claims that recite a particular order or process sequence will do so using the words of their text, not the letter designations. 
     Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements. 
     Any trademarks listed herein are the property of their respective owners, and reference herein to such trademarks is generally intended to indicate the source of a particular product or service. 
     Although the inventions have been described and illustrated in the above description and drawings, it is understood that this description is by example only, and that numerous changes and modifications can be made by those skilled in the art without departing from the true spirit and scope of the inventions. Although the examples in the drawings depict only example constructions and embodiments, alternate embodiments are available given the teachings of the present patent disclosure.