Patent Publication Number: US-2013249095-A1

Title: Gallium arsenide devices with copper backside for direct die solder attach

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present disclosure generally relates to the field of semiconductor wafer processing technology. In particular, this disclosure relates to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits. 
     2. Description of the Related Art 
     The use of GaAs substrates in the design and construction of integrated circuits has proven to have desirable effects. For example, GaAs substrates have been useful in achieving greater performance in power amplifier circuits. Typically, a GaAs integrated circuit will be used as a component in a larger circuit device or design. In order to be integrated into the circuit design, the GaAs integrated circuit is mechanically and electrically coupled to a printed circuit board for the circuit device. In other cases, the GaAs integrated device is mounted to other electronic devices. 
     Current processes for mounting a GaAs integrated circuit to a printed circuit board typically involves attaching a singulated GaAs die to a contact pad formed on the printed circuit board. The GaAs integrated circuit usually includes a gold contact layer which is adapted to couple with a die attach pad on the printed circuit board. Depositing the gold layer is a time-consuming and relatively inefficient process. Also, gold is an expensive material, increasing the cost for GaAs integrated circuit products. Finally, gold has a relatively high dissolution rate in solder, and therefore is not able to be soldered to the die attach pad of the device&#39;s printed circuit board. As such, the contact side of the GaAs integrated circuit is typically adhered to the die attach pad using a conductive adhesive, such as epoxy. The use of conductive adhesive requires an additional manufacturing step, and also requires the use of larger pads to accommodate adhesive overflow. This requirement of excess dimensions limits the ability to further miniaturize components. However, even with these undesirable features, gold contact layer and conductive adhesive continue to be the standard material and procedure used for attaching GaAs integrated circuit dies to a substrate. 
     With increasing pressure to reduce the size of components in electronic devices, there is a need for reducing the required size of the die attach pad on a printed circuit board or other substrate. There is also a need for improved GaAs integrated circuits that employ less costly component materials and can be more efficiently manufactured. Furthermore, there is a need for improved processes and methods for manufacturing such GaAs integrated circuits. 
     SUMMARY OF THE INVENTION 
     Systems and methods for reducing the required size of die attach pads adapted to receive GaAs integrated circuit dies on printed circuit boards and other substrates are disclosed herein. The systems and methods are designed to effectively attach a singulated GaAs integrated circuit die to a die attach pad on a substrate, such as a printed circuit board, without using a conductive adhesive. The direct die attach systems and methods disclosed herein eliminate the need to use larger die attach pads to accommodate adhesive overflow and the like. 
     In one embodiment, an electronic circuit device incorporating a direct die attach system is provided. The device includes a GaAs integrated circuit die having a copper backside contact pad, a substrate having a die attach pad, and a solder layer. The solder layer is preferably disposed between the copper backside contact pad on the GaAs integrated circuit and the die attach pad on the substrate in a manner such that the solder layer attaches the integrated circuit die to the substrate. In one implementation, the device further includes a solder barrier layer that is disposed between the copper backside contact pad and the solder layer. The solder barrier layer may include nickel and/or a palladium flash layer. In another implementation, the copper backside contact pad is substantially the same size as the die attach pad. The substrate can be a printed circuit board or the like. 
     In another embodiment, a method for manufacturing a GaAs wafer assembly is disclosed. The method includes providing a GaAs wafer having a copper layer over the backside of the wafer. Next, a solder barrier layer is formed over the copper layer. A singulated die from the wafer is soldered to a die attach pad on a substrate. In some embodiments, forming the solder barrier layer comprises forming a nickel layer over the copper layer. In some embodiments, the method further includes forming a palladium flash over the copper layer. In some embodiments, the substrate can be a printed circuit board. In some embodiments, the surface area of the singulated die can be substantially equivalent to the surface area of the die attach pad. 
     Semiconductor integrated circuits can be made in accordance with the methods disclosed herein. In some embodiments, the integrated circuit is incorporated in a wireless telecommunication device. In some embodiments, the integrated circuit comprises a copper filled through wafer via. In some embodiments, the integrated circuit comprises a copper contact pad. 
     In yet another embodiment, an electronic circuit module incorporating a direct die attachment assembly is disclosed. The electronic circuit module includes a singulated GaAs integrated circuit having a copper contact pad, a printed circuit board having a die attach pad, and a solder layer. The die attach pad is sized to receive the singulated GaAs integrated circuit die. In one implementation, the copper contact pad is attached to the singulated GaAs integrated circuit die by the solder layer. In another implementation, the size of the die attach pad does not exceed the size of the singulated GaAs integrated circuit die by more than 150 microns in at least one direction. 
     For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an example of attaching a singulated GaAs die to a die attach pad on a substrate. 
         FIGS. 2A-2B  show an example sequence of attaching a GaAs die to a substrate using standard processes. 
         FIGS. 3A-3B  show an example sequence of attaching a GaAs die to a substrate using a direct die solder process. 
         FIG. 4  shows an example sequence of wafer processing for forming singulated GaAs dies for attachment to a substrate. 
         FIGS. 5A-5R  show examples of structures at various stages of the processing sequence of  FIG. 4 . 
         FIG. 6  is a block diagram representing the copper metallization process according to various aspects of the present invention. 
         FIGS. 7A-7D  show examples of structures at various stages of the processing sequence of  FIG. 6 . 
         FIG. 8  is a block diagram representing the direct die solder process according to various aspects of the present invention. 
         FIGS. 8A-8C  show examples of structures at various stages of the processing sequence of  FIG. 8 . 
         FIGS. 9A-9D  show an example sequence of singulating a GaAs integrated circuit die from a wafer. 
         FIG. 10  shows an example sequence of ball grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment. 
         FIGS. 11A-11H  show examples of structures at various stages of the processing sequence of  FIG. 10 . 
         FIG. 12  shows an example shows an example sequence of land grid array packaging of singulated GaAs integrated circuit dies, according to one embodiment. 
         FIGS. 13A-13G  show examples of structures at various stages of the processing sequence of  FIG. 12 . 
         FIG. 14  shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, according to one embodiment. 
         FIGS. 15A-15D  show examples of structures at various stages of the processing sequence of  FIG. 14 , according to one embodiment. 
         FIGS. 16A-16E  show examples of structures at various stages of the processing sequence of  FIG. 14 , according to another embodiment. 
         FIG. 17  illustrates a GaAs integrated circuit device made according to various methods of the present invention, mounted onto a printed circuit board. 
         FIG. 18  illustrates an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. 
     Various embodiments of the present disclosure relate to novel methods and systems for attaching a singulated GaAs die to a substrate such as a printed circuit board. As described in greater detail below, the methods and systems involve directly attaching a singulated GaAs die  101  to a die attach pad  102  on a substrate  103  as shown in  FIG. 1  without using conductive adhesive such as epoxy. The elimination of adhesive significantly reduces the need for forming a die attach pad with larger dimensions than the singulated die. In some embodiments, the die attach pad can be identically sized to the singulated die. The novel die attach methods and systems described herein reduce the footprint of the mounted die, thereby facilitating further module size reduction. 
       FIGS. 2A-2B  show an example sequence of attaching a GaAs die to a substrate using standard processes that incorporate the use of a conductive adhesive to attach the die to the substrate. As illustrated, a singulated GaAs die  201  is arranged to be attached to a substrate  205  by die attach pad  207  via a conductive adhesive such as epoxy. The substrate  205  is preferably a printed circuit board for an electronic device. Typically, the dimensions of the die attach pad  207  exceed the dimensions of the die  201  itself, in order to allow room for adhesive to spread laterally. The larger dimensions of the die attach pad  207  effectively expand the footprint of the device, and hinder efforts toward increased miniaturization. 
       FIGS. 3A-3B  show an example sequence of attaching a GaAs die to a substrate using a direct die attach method in accordance with various preferred embodiments of the present invention. In contrast to the sequence illustrated in  FIGS. 2A-2B , the die attach pad  307  has the same width as the singulated die  301 . This can be achieved by the use of direct die solder (DDS), as opposed to epoxy. Since solder is less prone to lateral flow during the attachment process, the die attach pad  307  can have the same footprint as the singulated die  301 . This advantageously reduces the footprint of the device, and allows for reduced component sizes. However, it is impractical to implement the sequence illustrated in  FIGS. 3A-3B  for conventional GaAs integrated circuits having a gold contact layer because of the difficulties in soldering gold due to gold&#39;s relative high dissolution rate in solder. Accordingly, in certain preferred embodiments described in greater detail below, the inventors have developed methods and systems for replacing gold with copper as backside contact for GaAs integrated circuits in order to implement the direct die attach methods described herein. 
     Provided herein are various methodologies and devices for processing GaAs wafers to form GaAs integrated circuits that are subsequently mounted to printed circuit boards or other devices using a direct die attach process. 
     In the description herein, various examples are described in the context of GaAs substrate wafers. It will be understood, however, that some or all of the features of the present disclosure can be implemented in processing of other types of semiconductor wafers. Further, some of the features can also be applied to situations involving non-semiconductor wafers. 
       FIG. 4  shows an example of a process  10  where a functional GaAs wafer is processed to form GaAs integrated circuit dies and the formed integrated circuit dies are singulated for assembly, which includes direct die attachment to a printed circuit board or other device without using a conductive adhesive. 
     In the process  10  of  FIG. 4 , a functional wafer is provided (block  11 ).  FIG. 5A  depicts a side view of such a wafer  30  having first and second sides. The first side can be a front side, and the second side a back side.  FIG. 5B  depicts an enlarged view of a portion  31  of the wafer  30 . The wafer  30  can include a substrate layer  32  (e.g., a GaAs substrate layer). The wafer  30  can further include a number of features formed on or in its front side. In the example shown, a transistor  33  and a metal pad  35  are depicted as being formed the front side. The example transistor  33  is depicted as having an emitter  34   b,  bases  34   a,    34   c,  and a collector  34   d.  Although not shown, the circuitry can also include formed passive components such as inductors, capacitors, and source, gate and drain for incorporation of planar field effect transistors (FETs) with heterojunction bipolar transistors (HBTs). Such structures can be formed by various processes performed on epitaxial layers that have been deposited on the substrate layer. 
     Referring to the process  10  of  FIG. 4 , the functional wafer of block  11  can be tested (block  12 ) in a number of ways prior to bonding. Such a pre-bonding test can include, for example, DC and RF tests associated with process control parameters. Upon such testing, the wafer can be bonded to a carrier (block  13 ).  FIG. 4C  shows an example assembly of the wafer  30  and a carrier  40  (above the wafer) that can result from the bonding step  13 . 
     Referring to the process  10  of  FIG. 4 , the wafer—now mounted to the carrier plate—can be thinned so as to yield a desired substrate thickness in blocks  14  and  15 . 
     Referring to the process  10  of  FIG. 4 , the thinned and stress-relieved wafer can undergo a through-wafer via formation process (block  16 ).  FIGS. 5D-5F  show different stages during the formation of a via  44 . Such a via is described herein as being formed from the back side of the substrate  32  and extending through the substrate  32  so as to end at the example metal pad  35 . It will be understood that one or more features described herein can also be implemented for other deep features that may not necessarily extend all the way through the substrate. Moreover, other features (whether or not they extend through the wafer) can be formed for purposes other than providing a pathway to a metal feature on the front side. 
     Referring to the process  10  of  FIG. 4 , a metal layer can be formed on the back surface of the substrate  32  in block  17 .  FIGS. 5G and 5H  show examples of adhesion/seed layers and a thicker metal layer. 
       FIG. 5G  shows that in certain implementations, an adhesion layer  45  such as a nickel vanadium (NiV) layer can be formed on surfaces of the substrate&#39;s back side and the via  44  by, for example, sputtering.  FIG. 5G  also shows that a seed layer  46  such as a thin gold layer can be formed on the adhesion layer  45  by, for example, sputtering. Such a seed layer facilitates formation of a thick metal layer  47  such as a thick gold layer shown in  FIG. 5H . In certain implementations, the thick gold layer can be formed by a plating technique. 
     The metal layer formed in the foregoing manner forms a back side metal plane that is electrically connected to the metal pad  35  on the front side. Such a connection can provide a robust electrical reference (e.g., ground potential) for the metal pad  35 . Such a connection can also provide an efficient pathway for conduction of heat between the back side metal plane and the metal pad  35 . 
     Referring to the process  10  of  FIG. 3 , the wafer having a metal layer formed on its back side can undergo a street formation process (block  18 ).  FIGS. 5I-5K  show different stages during the formation of a street  50 . Such a street is described herein as being formed from the back side of the wafer and extending through the metal layer  52  to facilitate subsequent singulation of dies. 
     To form a street  50  ( FIG. 5J ) through the metal layer  52 , techniques such as wet etching (with chemistry such as potassium iodide) can be utilized.  FIG. 5K  shows the formed street  50 , with the resist layer  48  removed. In the example back-side wafer process described in reference to  FIGS. 4 and 5 , the street ( 50 ) formation and removal of the resist ( 48 ) yields a wafer that no longer needs to be mounted to a carrier plate. Thus, referring to the process  10  of  FIG. 4 , the wafer is debonded or separated from the carrier plate in block  19 .  FIGS. 5L-5N  show different stages of the separation and cleaning of the wafer  30 . 
     Referring to the process  10  of  FIG. 4 , the debonded wafer of block  19  can be tested (block  20 ) in a number of ways prior to singulation. 
     Referring to the process  10  of  FIG. 4 , the tested wafer can be cut to yield a number of dies (block  21 ). In certain implementations, at least some of the streets ( 50 ) formed in block  18  can facilitate the cutting process.  FIG. 5O  shows cuts  61  being made along the streets  50  so as to separate an array of dies  60  into individual dies. Such a cutting process can be achieved by, for example, a diamond scribe and roller break, saw or a laser. 
     In the context of laser cutting,  FIG. 5P  shows an effect on the edges of adjacent dies  60  cut by a laser. As the laser makes the cut  61 , a rough edge feature  62  (commonly referred to as recast) typically forms. Presence of such a recast can increase the likelihood of formation of a crack therein and propagating into the functional part of the corresponding die. 
     Thus, referring to the process  10  in  FIG. 4 , a recast etch process using acid and/or base chemistry (e.g., similar to the examples described in reference to block  15 ) can be performed in block  22 . Such etching of the recast feature  62  and defects formed by the recast, increases the die strength and reduces the likelihood of die crack failures ( FIG. 5Q ). 
     Referring to the process  10  of  FIG. 4 , the recast etched dies ( FIG. 5R ) can be further inspected and subsequently attached to a printed circuit board or other substrate. In certain embodiments, the singulated dies  60  are preferably directly attached to a contact pad on a printed circuit board using solder. Since it is difficult to solder gold, the inventors have developed methodologies to use copper, instead of gold, as backside contact for GaAs integrated circuits in conjunction with the direct die solder approach in attaching the singulated dies to a substrate. 
     Copper Metallization 
     While metallization of backside contact of GaAs integrated circuits is typically performed using gold, other integrated circuit technologies, such as silicon-based technologies, use copper (Cu) for a contact layer. Cu has superior conductivity, may be applied more uniformly, and is less costly than gold. Further, Cu has a sufficiently low dissolution rate in solder, so allows the integrated circuit device to be soldered to its printed circuit board pad. Cu, however, readily oxidizes, which degrades electrical and mechanical characteristics. Accordingly, when used in silicon processes, the Cu is typically applied in thick layers, polished, and then capped with dielectric materials such as silicon nitride to avoid these oxidation effects. 
     Although Cu has been used successfully in silicon wafer technology, to the best of the inventors&#39; knowledge, Cu has not been successfully used in GaAs integrated circuit devices. A number of obstacles have hindered the effective use of copper in metallization of GaAs devices. For example, Cu is an unintentional source of impurity, and is often proven to be the leading cause of GaAs device failures. Cu rapidly diffuses into GaAs substrates, at a rate faster than the diffusion of gold into GaAs substrates, and faster than the diffusion of Cu into silicon substrates. Once Cu diffuses into source/gate/drain region of a field effect transistor (FET) or active areas of a heterojunction bipolar transistor (HBT), the device will degrade, and eventually fail electrically. Unlike gold, Cu can diffuse into GaAs and create deep energy levels in the GaAs band gap region. These deep levels will trap charges, which lead to degradation and failure of the GaAs devices. 
     Without wishing to be bound by theory, the inventors have determined that there are three mechanisms of Cu diffusion in GaAs. The first is bulk or lattice diffusion, which involves vacancies in the GaAs lattice and the exchange of Cu atoms between layers in the GaAs lattice. Bulk diffusion is highly temperature dependent. The second mechanism is the intermetallic compound formation between Cu and GaAs. The third mechanism is interstitial diffusion, in which Cu atoms move along defects, dislocations, or grain boundaries in GaAs. This third mechanism is of particular importance because during processing, the GaAs surface is often damaged. Consequently, there are voids, dislocations, and other defects present on the GaAs surface, which facilitate the movement of Cu atoms within the GaAs lattice structure. 
     Accordingly, the use of Cu typically results in the destruction or nonoperation of GaAs integrated circuits. Further, Cu readily oxidizes, and so is difficult to use as a contact material in GaAs integrated circuits without any protection. It is therefore necessary to modify the process outlined above in order to permit the use of Cu to form the metal layer lining the back side of the wafer and the surface of the vias. Certain aspects of the present invention are directed to novel process modifications and techniques which the inventors have developed to overcome at least some of the obstacles in using copper for backside metallization of GaAs integrated circuits. A backside metallization process developed for copper will be first described below. 
       FIG. 6  shows one embodiment of a modified via metallization process represented in Block  17  of  FIG. 4 , which is developed for copper metallization of a GaAs integrated circuit.  FIGS. 7A-7D  show examples of cross sectional diagrams of a section of a GaAs wafer formed in accordance the process shown in  FIG. 6 . 
     In the process  10  of  FIG. 6 , the via metallization process (block  17 ) begins with a pre-clean step (block  17   a ).  FIG. 7A  depicts the formed via  113  processed through the pre-clean step  17   a.  In various implementations, the pre-clean step removes residues and other contamination from the via  113  and back surface  103  of the substrate  102  and activates the surfaces for subsequent metal adhesion. 
     Referring to the process  10  of  FIG. 6 , a metal barrier and seed layer can be formed in the via  113  and on the back surface  103  of the substrate  102  in block  17   b.    FIG. 7B  shows an example of a seed layer  109  and a metal barrier layer  104  that can be formed in the via  113  and on the back surface  103  of the substrate  102 . 
     Referring to the process  10  of  FIG. 6 , a copper layer is formed in the via  113  and on the back surface  103  of the substrate  32  in block  17   c.    FIG. 7C  shows an example of a copper contact layer  106  that can be formed in the via  113  and on the back surface  103  of the substrate  102 . The copper contact layer  106  can replace some or all of the gold contact layer that is typically deposited in the via  113  and on the back surface  103 . As  FIG. 6  further shows, in some embodiments, an optional heat treatment step in block  17   d  can follow the copper deposition process. 
     In some implementations of the embodiment shown in  FIG. 6 , the via metallization process (blocks  17   a - 17   d ) is followed by street formation (block  18 ), and deposition of a protective layer deposition (block  18   a ) before debonding wafer from carrier. 
       FIGS. 7A-7D  show examples of cross sectional diagrams of a section of a GaAs wafer with a via formed in accordance with embodiments of the process  10  in  FIG. 3  is illustrated. Section  100  has via  113  extending through a GaAs substrate  102 . Referring to the process  10  of  FIG. 3 , the via  113  may be pre-cleaned (block  17   a ). The via  113  and back side  105  of the GaAs wafer  102  may be cleaned using, for example HCl and/or an O 2  plasma ash process. 
     Following cleaning, the via may be barrier layer followed by a seed layer may be deposited (block  17   b ). First a barrier layer  104  is deposited on the contact side  105  of the GaAs substrate  102 . In one example, the barrier layer  104  is a nickel vanadium (NiV) layer disposed at about  800  angstroms thickness. The NiV may be deposited using a physical vapor deposition process (commonly known as sputtering), or other known deposition process. The NiV provides an effective diffusion barrier between the GaAs substrate and the copper contact layer  106 , which will be applied later. Since copper is known to have an undesirable diffusion effect on GaAs, the NiV is deposited in a relatively thick layer. It will be appreciated that the thickness of the layer may be adjusted according to the needs of the particular application. For example, devices subjected to long-term use may require thicker layers, and the layer may be adjusted according to other material used, for example, in the seed layer  109 . 
     A seed layer  109  may then be deposited on the barrier layer  104 . Although the seed layer  109  may not always be necessary, it has been found that a seed layer facilitates better mechanical and electrical connection of the copper contact layer. The metal seed layer may be, for example, either a copper layer or a gold layer, and may be deposited at a thickness of about 700 angstroms using a physical vapor deposition process. If copper is used as the seed layer, then an activation process may need to be performed at a later time if the copper has been allowed to oxidize. 
     The via  113  may then be plated with copper (block  17   c ). The copper contact layer  106  is deposited on the seed layer  109 , if present. The copper contact layer  106  is deposited using an electroplating process. The copper is deposited at a relatively uniform thickness, such as about 6 μm. It will be appreciated that other types of processes and thicknesses may be used. Depending on the size of the via  113 , the copper may simply coat the walls, or may nearly fill the via. To facilitate faster production, a 6 μm coating of the copper contact layer  106  typically provides sufficient electrical conduction, while leaving a central opening in via  113 . 
     Following the copper plating, the GaAs wafer  102  is subjected to an optional heat treatment (block  17   d ). The metallization process can continue for 48 hours or more. Such a long process disadvantageously extends production time GaAs integrated circuit devices. Additionally, this slow process results in copper structure with significant defects, cracks, etc caused by the slow growth. Adding heat to the process both significantly accelerates the metallization process and increase the quality and uniformity of the copper grain structure. In typical PECVD processes, the heat treatment involves application of temperatures between 200 to 300° C. These temperatures may exceed the melting point for the adhesive used to bond the wafer to the carrier. Subjecting GaAs wafers mounted onto carriers to such high temperatures may therefore disadvantageously decrease the bonding strength of the carrier and wafer. Accordingly, in certain embodiments the GaAs device is subjected to a temperature of approximately 100° C. Once the GaAs has been subjected to heat treatment, the metallization (block  17 ) of via  113  is complete. In some embodiments, the metallization (block  17 ) of via  113  is complete without heat treatment. 
     Referring to the process  10  of  FIG. 6 , the GaAs wafer having a copper contact layer  106  formed on its back side  105  can undergo a street formation process (block  18 ). Such a street is described herein as being formed from the back side of the wafer and extending through the copper contact layer  106  to facilitate subsequent singulation of dies. It will be understood that one or more features described herein can also be implemented for other street-like features on or near the back surface of the wafer. Moreover, other street-like features can be formed for purposes other than to facilitate the singulation process. 
     The street can be formed as described above with respect to  FIGS. 4  and  FIGS. 5I-5K . An etch resist layer defining a street opening can be formed using standard photolithography. Next, the exposed street opening in the copper contact layer  106  may be etched using wet etching, although other etching processes are also possible. A pre-etching cleaning process (e.g., O 2  plasma ash) can be performed prior to the etching process. In various implementations, the thickness of the resist and how such a resist is applied to the back side of the wafer can be important considerations to prevent certain undesirable effects, such as via rings and undesired etching of via rim during the etch process. 
     After etching the street into copper contact layer  106 , the resist layer may be removed, using photoresist strip solvents such as NMP (N-methyl-2-pyrrolidone), applied using, for example, a batch spray tool. To remove residue of the resist material that may remain after the solvent strip process, a plasma ash (e.g., O 2 ) and/or aqueous wash process can be applied to the back side of the wafer. 
     Following street formation (block  18 ), a protective layer  108  may be deposited over the back side of the GaAs wafer (block  18   a ). Since copper is highly reactive with oxygen, a protective layer  108  is deposited over the copper contact layer  106 . In one example, the protective layer  108  is an organic solder preservative (OSP). The OSP may be applied using a bath process, or other known processes may be used. The OSP may be deposited at a thickness of about 700 angstroms. It will be appreciated that other thicknesses may be used depending upon application specific requirements and the particular materials used. For example, thicknesses in the range of about 100 angstroms to about 900 angstroms have been found to be effective, although other thicknesses may be alternatively used. 
     As described in more detail above, street formation (block  18 ) may be followed by debonding the wafer from the carrier (block  19 ), and testing the wafer following debonding (block  20 ). The resulting structure is shown in  FIG. 7D . 
     Direct Die Solder 
     Current processes for attaching a singulated die to a substrate rely on conductive adhesives such as epoxy. For example, a singulated GaAs die can be attached to a die attach pad on a printed circuit board (PCB) using epoxy. Due to the tendency of epoxy to spread during the attachment process, the size of the die attach pad on the PCB must typically exceed the size of the GaAs die by at least  150  microns in each direction. 
     Direct die solder (DDS) is a process that uses solder to attach a singulated die to a die attach pad, rather than epoxy. As solder has less tendency to spread laterally during this process, the need for a die attach pad with larger dimensions than the singulated die. Accordingly, using DDS a die attach pad can be used that is identically sized to the singulated die. This reduced the footprint of the mounted die, thereby facilitating further module size reduction. 
     An additional benefit of using DDS is that solder has higher thermal conductivity than epoxy. As the die heats up during operation, there is a need to transfer heat from the die to the PCB as efficiently as possible. The improved thermal conductivity afforded by solder can therefore improve operation of the die itself. Further, solder is typically less expensive than epoxy, allowing the manufacturer to achieve reduction in component costs. 
     However, DDS presents certain problems of its own. For example, solder typically reflows at approximately 260° C., depending on the exact composition of the solder. During the die attach process, the solder therefore must be heated at least to this temperature. At such high temperatures, however, contact metals may dissolve in the solder. For example, gold dissolves in solder at these temperatures. Copper likewise dissolves into solder and forms an intermetallic compound. While copper typically dissolves into solder at a slower rater than gold, the formation of the intermetallic compounds has deleterious effects on die performance. The resultant copper intermetallic compounds have five to ten times higher resistivity and brittleness. Additionally, over time the copper can be consumed by the solder, resulting in detachment of the copper contact layer from the die, resulting in device failure. 
     As noted above, the DDS process poses certain problems, particularly in regards to the interaction of the solder and the backside metal contact material. Accordingly, steps can be taken to protect the backside metal contact material from being damaged by the solder. 
     One such process it illustrated in  FIG. 8 .  FIG. 8  is a block diagram representing the direct die attach process according to various aspects of the present invention, with  FIGS. 8A-8C  showing examples of structures at various stages of the processing sequence of  FIG. 8 . 
     With reference to  FIG. 8A , the process  70  begins with a copper plated wafer (block  71 ), a section  400  of which is illustrated. The wafer section  400  includes a GaAs substrate  402 , seed layer  404 , barrier layer  409 , and copper contact layer  406 . The wafer section  400  with a copper contact layer can be fabricated as described above with respect to  FIGS. 6-7D . 
     As noted above, a direct copper contact layer may not amenable to use in DDS attachment processes. Referring to  FIG. 8B , the copper layer can be protected from intermixing with solder at elevated temperatures by use of an electroless nickel plating process (block  72 ). As a result, a nickel layer  410  can cover the copper contact layer  106  and provide an effective barrier between the copper and the solder. 
     Electroless nickel plating is an auto-catalytic chemical technique well known in the art. It may be used to deposit a layer of nickel  410  over the copper  406 . The thickness of the nickel layer can be controlled by adjusting the parameters of the electroless plating process, as is known in the art. The thickness of the nickel layer  410  can be selected to avoid stress on the wafer, which can disadvantageously lead to wafer bow or die crack. 
     For example, if the nickel layer  410  is too thick, it may impart undesirable stress on the wafer. Subject to too much stress, the wafer  400  may bow or crack. Accordingly, the nickel layer  110  must be sufficiently thick to provide an effective barrier between the copper layer  406  and the solder during attachment, without being so thick as to result in wafer bowing or cracking. 
     Exposed to atmosphere, nickel will readily oxidize. As shown in  FIG. 9C , a palladium flash  411  (block  73 ) can be applied over the nickel layer  410  and the copper layer  406 . The palladium flash  411  protects the nickel layer  410  from oxidation. 
     Once the copper layer  406  has been covered with nickel layer  410 , which in turn is coated with palladium flash  411 , the wafer can proceed as described above with respect to  FIGS. 4-5R . 
       FIG. 9A  illustrates a GaAs wafer  500  with a plurality of individual integrated circuits  551  formed in accordance with embodiments of the invention shown and described above with reference to  FIGS. 6 ,  7 A- 7 D,  8 , and  8 A- 8 C in which copper is used as a contact metal for the vias and back-side plane. As shown in  FIG. 9A , streets  552  have been formed in the regions between each integrated circuit  551  on the wafer  550 . As described above, street formation involves removing copper in the regions between the integrated circuits. 
     Following street formation, the wafer  550  is placed onto cutting tape  553 , with the backside of the GaAs wafer  550  adhering to the cutting tape  553  and frame in the manner shown in  FIGS. 9B and 9C . Next, the integrated circuit dies are singulated by cutting through the GaAs wafer along the pre-formed streets. A scribe may be applied to the streets in order to mechanically singulate the integrated circuit dies. Alternatively, a laser may be used to burn through the streets. Mechanical scribing is inexpensive, but typically less accurate than laser singulation, and may cause damage to the die. Laser singulation is more accurate and reduces damage, but at increased expense. 
     Once the integrated circuit dies have been singulated, the cutting tape is stretched apart. This stretching ensures that the dies have been singulated, as it results in widening the separation between each of the dies. The cutting tape may be stretched until the tape is visible between each of the dies.  FIG. 9C  illustrates stretched cutting tape in which some of the singulated dies have been removed. The dies may be removed from the cutting tape manually or by automated robotics. For example, an automated die-picking machine may select and remove individual dies through the use of vacuum pressure.  FIG. 9D  illustrates a singulated GaAs integrated circuit die, according to an embodiment of the present invention. 
     Once individual GaAs integrated circuit dies have been formed, they may be packaged for incorporation into larger electronic devices. Various types of packaging exist, some of which are described in more detail below. It will be understood that there exist myriad different types of packaging beyond those listed and described herein. Depending on the desired application, virtually any type of packaging may be used in accordance with the present invention. Four different packages are described in more detail below: ball grid array (BGA), land grid array (LGA), molded leadframe, and quad-flat no-leads (QFN). 
       FIG. 10  shows an example shows an example sequence of BGA packaging of singulated GaAs integrated circuit dies, according to one embodiment, with  FIGS. 11A-11H  showing examples of structures at various stages of the processing sequence of  FIG. 10 . With reference to  FIG. 11A , individual dies  551  are arranged (block  501 ), typically in an array, onto a laminate packaging substrate  555 . A single packaging substrate  555  such as that shown in  FIG. 11A  can include between 200 to 400 dies  551 , although the specific number may vary depending on the application. The packaging substrate  555  includes pre-formed lower contact pads  554  on its lower surface. As described in more detail below, a grid of solder balls  556  are formed on the lower contact pads  554 . On the top surface the packaging substrate has die attach pads  557 , onto which singulated dies  551  are mounted, and a plurality upper contact pads  558 . The singulated dies  551  are preferably soldered to the die attach pads  556 . As illustrated, the die attach pads  557  have a footprint substantially identical to that of the singulated dies  551 . The packaging substrate includes internal interconnections to electrically connect the upper contact pads  558  on the top surface to the lower contact pads  554  on the bottom surface. 
     The die attach pad  557  is typically flat and made of tin-lead, silver, or gold-plated copper. With reference to  FIGS. 11B and 11C , the individual dies  201  are attached to the die attach pads  207  (block  502 ) by applying solder paste to all die attach pads  557 . Solder paste is an adhesive mixture of flux and tiny solder particles. The solder paste may be deposited by the use of a screen printing process, or by jet-printing. After the solder paste has been applied, individual dies are placed onto the packaging substrate  555  by robotic pick-and-place machines. Individual dies  551  may be removed from the cutting tape and transferred directly to the packaging substrate, where they are positioned to align the die attach pads with the contacts of the individual dies. The solder paste connects the die attach pads  557  to the contacts of the individual dies  551 . To provide a more robust connection, the dies are subjected to heat treatment for solder reflow. The precise temperatures and times for this process will vary depending on the composition of the solder paste. Typical temperatures range from 100° to 260° C., with dwell times at peak temperatures ranging from 50 seconds to two minutes. This heat treatment causes the solder particles within the solder paste to melt. The solder is then allowed to cool, resulting in a robust electrical and mechanical connection between the packaging substrate and the individual dies. 
     With reference to  FIG. 11D , following attachment of the individual dies  551  to the packaging substrate  555 , electrical interconnection is formed between bonding pads on the integrated circuit and the upper contact pads  558  on the top surface of the packaging substrate  555  (block  503 ). This connection may be formed by wire bonding or flip-chip methods. Wire bonding involves arranging wires  559 , often made of copper, gold, or aluminum, between an upper contact pad  558  at one end, and a bonding pad on the integrated circuit die  551  at the other. The wire  559  is attached using some combination of heat, pressure, and ultrasonic energy to weld the wire  559  in place. Flip chip interconnection involves applying solder bumps to the bonding pads on the top surface of the integrated circuit. The integrated circuit is then inverted, and arranged such that the solder bumps align with contact pads. With the application of heat, the solder bumps melt and, following a cooling process, an electrical and mechanical connection may be formed between the bonding pads on the integrated circuit die and the contact pads on the packaging substrate. 
     With reference to  FIG. 11E , after electrical interconnection has been formed between the die and the packaging substrate, the entire packaging substrate is covered with a molding compound  560  (block  504 ). There are a wide variety of commercially available molding compounds. Typically, these are epoxy-based compounds. The packaging substrate  555  covered with the molding compound  560  is then cured in an oven. The temperature and duration of curing depends on the particular molding compound selected. As shown in  FIG. 11F , after the molding compound  560  has cured, the each die  551  on the packaging substrate  560  is totally encapsulated, including the electrical interconnections  559 , with only the bottom surface of the packaging substrate  555 , with its lower contact pads, exposed. At this stage, the packaging substrate  555  covered with cured molding compound  560  can be sawed (block  505 ), thereby singulating the packaged devices. Singulation may be performed mechanically, such as with a wafer saw. 
     Each packaged device is inverted at this stage, and then on top of each lower contact pad  554  on the packaging substrate, a small ball of solder paste is deposited, creating a grid of solder paste balls  556  (block  506 ). The BGA package may then be placed over solder pads on a PCB, with each solder paste ball  556  aligned to a solder pad. The solder pads are flat, and typically made of tin-lead, silver, or gold-plated copper.  FIG. 11E  illustrates a schematic cross-section of a singulated BGA packaged die, with  FIGS. 11G and 11H  illustrating the top and bottom perspective views of the same. 
       FIG. 12  shows an example shows an example sequence of LGA packaging of singulated GaAs integrated circuit dies, with  FIGS. 13A-13G  showing examples of structures at various stages of the processing sequence of  FIG. 12 . In many respects, LGA packaging is similar to BGA packaging. As shown in  FIG. 13A , individual dies  551  are arranged (block  401 ), typically in an array, onto a laminate packaging substrate  555 . The packaging substrate  555  includes pre-formed lower contact pads  554  on its lower surface. On the top surface the packaging substrate has die attach pads  557 , onto which singulated dies  551  are mounted, and a plurality upper contact pads  558 . As illustrated, by using the DDS process discussed above, the die attach pads  557  may have a footprint substantially identical to that of the singulated dies  551 . The packaging substrate includes internal interconnections to electrically connect the upper contact pads  558  on the top surface to the lower contact pads  554  on the bottom surface. 
     The die attach pad  557  is typically flat and made of tin-lead, silver, or gold-plated copper. With reference to  FIGS. 13B and 13C , the individual dies  551  are attached to the die attach pads  557  (block  402 ) by applying solder paste to all die attach pads  557 , similar to BGA packaging. After the solder paste has been applied, individual dies are placed onto the packaging substrate  555  by robotic pick-and-place machines. The solder paste connects the die attach pads  557  to the contacts of the individual dies  551 . To provide a more robust connection, the dies are subjected to heat treatment for solder reflow, as described in more detail above. 
     With reference to  FIG. 13D , following attachment of the individual dies  551  to the packaging substrate  555 , electrical interconnection is formed between bonding pads on the integrated circuit and the upper contact pads  558  on the top surface of the packaging substrate  555  (block  403 ). This connection may be formed by wire bonding or flip-chip methods, as described with respect to BGA packaging above. 
     With reference to  FIG. 13E , after electrical interconnection has been formed between the die and the packaging substrate, the entire packaging substrate is covered with a molding compound  560  (block  404 ). The packaging substrate  555  covered with the molding compound  560  is then cured in an oven. As shown in  FIG. 13F , after the molding compound  560  has cured, the each die  551  on the packaging substrate  560  is totally encapsulated, including the electrical interconnections  559 , with only the bottom surface of the packaging substrate  555 , with its lower contact pads, exposed. At this stage, the packaging substrate  555  covered with cured molding compound  560  can be sawed (block  405 ), thereby singulating the packaged devices. 
     It is at this stage that LGA packaging deviates from BGA packaging described above. In contrast to BGA, LGA does not involve placing small balls of solder paste onto the packaging substrate. Rather, the solder paste, or alternatively molten solder, is placed onto the PCB over the solder pads, and then the LGA packaged device is arranged such that the contact pads  554  are aligned over the solder pads (block  406 ). For mounting onto a PCB, the package may be placed over corresponding solder pads on the PCB, followed by heat treatment to induce solder reflow. The PCB is outfitted with pre-formed conductive solder pads, also known as PCB pads, arranged to correspond to contact pads  554  of the packaging substrate. In short, BGA involves applying solder paste to the packaging substrate  555 , whereas LGA involves applying solder paste to the PCB.  FIG. 13E  illustrates a schematic cross-section of a singulated BGA packaged die, with  FIG. 13G  illustrating a bottom perspective view of the same 
     After placement of the packaged device on the packaging substrate, BGA and LGA proceed similarly. The packaged device mounted onto a PCB is subjected to a heat treatment for solder reflow, followed by a cool down period. 
       FIG. 14  shows an example shows an example sequence of leadframe packaging of singulated GaAs integrated circuit dies, with  FIGS. 15A-15D  showing examples of structures at various stages of the processing sequence of  FIG. 14 . With reference to  FIG. 15A , individual singulated integrated circuit dies  551  are mounted onto a metallic leadframe  561  (block  601 ). The leadframe  561  includes a plurality of die attach regions  562 , and a plurality of leads  562 . The leadframe  561  is typically made of a thin sheet of copper or copper alloy. In some instances, the copper is plated with another metal, such as pure tin, silver, nickel, gold, or palladium. For high-throughput, the processing may be performed in batches, in which an array or strip of connected leadframes is provided. 
     The singulated dies  551  can be mounted onto the die attach regions  552  of the leadframe  561  by an adhesive or soldering process (block  601 ). The bond is typically formed between the backside metallization of the die and the metal surface of the leadframe. The bond can be formed using solder paste followed by a reflow process, as described above. Alternatively, molten solder can be placed directly onto the die attach pad, followed by placement of the die. Conductive epoxy adhesives may also be used in place of solder. 
     With reference to  FIG. 15B , After the die has been attached to the leadframe, wire bonding is then used to form electrical connections  566  between the die attach pads to the package leads (block  602 ). Next, a mechanical trimming operation separates the leads  563  from the die bonding platform on the lead frame  561  (block  603 ). Plastic or other molding compound  565  is then injection molded around the die  551  and leadframe  551  to form the typical black plastic body (block  604 ), similar to the molding processes described above with respect to LGA and BGA packaging. In typical leadframe packaging, however, the frame for injection molding is designed such that a portion of the leads  563  remains uncovered by the molding compound  565 . Following curing, the packaged device is presented with a portion of the leads  563  extending out from the cured molding compound, typically a black plastic.  FIG. 15C  illustrates a schematic cross-section of a singulated leadframe packaged die, with  FIG. 15D  illustrating a top perspective view of the same 
     The sequence illustrated in  FIG. 14  can also be applied to quad-flat no lead (QFN) packaging of singulated GaAs integrated circuit dies.  FIGS. 16A-16E  show examples of structures at various stages of the processing sequence. QFN packaging is similar to leadframe packaging, with some important distinctions. With reference to  FIG. 16A , QFN packaging also begins with a leadframe  561  comprising die attach regions  562  and a plurality of leads  563 . Singulated dies  551  are attached to the leadframe  301  in a manner similar to that described above with respect to standard leadframe packaging (block  701 ). As shown in  FIG. 16B , Wire bonding then follows, as described above, to connect the die  551  to the leadframe leads  563  with wires  566  (block  702 ). With QFN packaging, however, the leads  563  are not designed to extend out beyond the cured molding materials after singulation. Accordingly, there is no need for singulation prior to injection molding of the molding compound over the leadframe and die. Instead, a batch of connected mounted dies  551  can be covered with a molding compound, followed by a curing process (block  703 ). 
     Once the molding compound  565  has cured, the leadframes with mounted dies are singulated (block  704 ). Typically a diamond saw is used to cut through the hardened cured molding compound  565 . As the diamond saw cuts through the leads  563 , each side of the QFN package has exposed portions of the leadframe  561 . Unlike traditional leadframe packaging, however, the exposed portions are flush with the molding compound  565 . The leads  563  are also typically exposed on the lower surface of the QFN package.  FIG. 16C  illustrates a schematic cross-section of a singulated QFN packaged die, with  FIGS. 16D and 15E  illustrating top bottom and perspective views of the same. 
     Mounted Integrated Circuit Device 
       FIG. 17  illustrates one embodiment of a GaAs integrated circuit device  200 . The device  200  generally comprises a printed circuit board  212  connected to a GaAs integrated circuit  211 . The GaAs integrated circuit  211  has a backside  105  and a frontside  103 . The GaAs integrated circuit  211  includes a GaAs substrate  102 , a barrier layer  104 , a protective layer  108 , and a copper contact layer  106 . In some embodiments, the GaAs integrated circuit  211  may also include a seed layer  109  between the copper contact layer  106  and the barrier  104 . The seed layer  109  may serve to facilitate mechanical and electrical connection to the copper contact layer  106 , but is not always necessary. The printed circuit board includes a pad which is adapted to couple with the GaAs integrated circuit  211  at the backside  105 . The GaAs integrated circuit  211  is configured to be mounted on the printed circuit board  212  by the pad  216 . In one embodiment, the GaAs integrated circuit  211  is mounted to the pad  216  by a layer of solder  218  interposed between the backside  105  and the pad  216 . 
     The barrier layer  104  is formed on the lower surface  105  of the GaAs substrate  102  and serves to isolate the copper contact layer  106  from the GaAs substrate  102  to prevent copper diffusion. The copper contact layer  106  is formed on the backside  105  of the GaAs integrated circuit  211 . The copper contact layer  106  provides an electrical ground contact between the GaAs substrate  102  and the pad  216  on the printed circuit board  212 . In one embodiment, the layer of solder  218  is formed between the copper contact layer  106  and the pad  216  to securely mechanically attach the backside  105  of the GaAs integrated circuit  211  to the printed circuit board  212 . In one embodiment, the protective layer  108  is formed between the copper contact layer  106  and the solder  218  to prevent oxidation of the copper. The GaAs substrate  102  comprises a plurality of vias  25  which have been etched through the GaAs substrate  102  to form electrical connections between various integrated circuits disposed thereon. The vias  25  have sidewalls which will comprise the layers previously deposited on the GaAs substrate, as described in more detail above. 
       FIG. 18  illustrates a portion of an electronic device incorporating a GaAs integrated circuit device made according to various methods of the present invention. In some embodiments, the device can be a portable wireless device, such as a cellular phone. The device can include a battery configured to supply power to the device, a circuit board configured to provide support for and to interconnect various electronic components, and an antenna configured to receive and transmit wireless signals. The electronic device can include a number of additional components, such as a display processor, central processor, user interface processor, memory, etc. In other embodiments, the electronic device may be a component of a tablet computer, PDA, or other wireless device. 
     Terminology 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Detailed Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. 
     The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. 
     While certain embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.