Patent Publication Number: US-8536713-B2

Title: System in package with heat sink

Description:
CLAIM OF BENEFIT TO PRIOR APPLICATIONS 
     This Application is a continuation application of U.S. patent application Ser. No. 11/861,204, filed Sep. 25, 2007, now issued as U.S. Pat. No. 7,936,074. U.S. patent application Ser. No. 11/861,204 is a continuation application of U.S. patent application Ser. No. 11/081,842, filed Mar. 15, 2005, now issued as U.S. Pat. No. 7,301,242 U.S. patent application Ser. No. 11/081,842 claims benefit to U.S. Provisional Patent Application 60/625,263, filed Nov. 4, 2004, entitled “Method and Apparatus for a Programmable System in Package.” U.S. Pat. Nos. 7,936,074, 7,301,242, and U.S. Provisional Patent Application 60/625,263 are incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     The present invention is directed towards programmable system in package. 
     BACKGROUND OF THE INVENTION 
     The use of configurable integrated circuits (“IC&#39;s”) has dramatically increased in recent years. One example of a configurable IC is a field programmable gate array (“FPGA”). An FPGA is a field programmable IC that has an internal array of logic circuits (also called logic blocks) that are connected together through numerous interconnect circuits (also called interconnects) and that are surrounded by input/output blocks. Like some other configurable IC&#39;s, the logic circuits and the interconnect circuits of an FPGA are configurable (i.e., they can be configured to perform different functions and operations by receiving different configuration data). One benefit of configurable IC&#39;s is that they can be uniformly mass produced and then subsequently configured to perform different operations. 
     Recently, some have suggested implementing an FPGA within a system on chip (“SoC”). A SoC is an IC that includes all of the necessary hardware and electronic circuitry for a complete system. The SoC is typically a small piece of semiconducting material (e.g., silicon) on which several macroblocks are embedded. Some of these macroblocks can include a memory, a microprocessor, digital signal processor, etc. A characteristic of the SoC is that it requires all the macroblocks to be manufactured with one type of fabrication technology. This can be problematic since each macroblock may have a different optimal fabrication technology (e.g., a memory macroblock might be optimally manufactured at 90 nm, while an analog macroblock might be optimally manufactured at 180 nm). As such, in some instances, some of the macroblocks of a SoC might be manufactured sub-optimally. Another drawback of a SoC is that the design process is often extensive, cumbersome and expensive. 
     Therefore, there is a need in the art for a better method of fabricating a configurable IC that has configurable IC operations and non-configurable IC operations within the IC. 
     SUMMARY OF THE INVENTION 
     Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC&#39;s that are arranged within the single IC housing. At least one of the IC&#39;s is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC&#39;s in the PSiP. The first clock rate is faster than the clock rate of all of the other IC&#39;s in the PSiP in some embodiments. 
     Some embodiments provide a method for manufacturing a programmable system in package. The method divides a system into sets of operations. For each set of operations, the method identifies an integrated circuit (“IC”) for performing the set of operations. The method packages a set of identified IC&#39;s into a single IC package. The set of identified IC&#39;s includes at least one configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. 
     Other embodiments of the invention provide a method for selecting a set of IC&#39;s for a PSiP. The method defines a budget for implementing the PSiP. The method identifies sets of operations that the PSiP has to implement. For each particular set of operations, the method identifies an IC to implement the particular set of operations. When the method identifies a set of IC&#39;s for implementing the PSiP&#39;s sets of operations, the method determines whether the cost of the identified set of IC&#39;s is less than the budget. If so, the method selects the identified set of IC&#39;s. Otherwise, the method searches for another set of IC&#39;s to implement the PSiP&#39;s operations. In the set of IC&#39;s that the method eventually selects, there is at least one IC that is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during run time. 
     In some of the embodiments described above, the set of IC&#39;s may include digital and analog IC&#39;s. Furthermore, in some embodiments, the set of IC&#39;s may include IC&#39;s that are manufactured with different fabrication technologies. Moreover, different embodiments might package the set of IC&#39;s differently in a single package. Some embodiments might stack the set of IC&#39;s on top of each other into a single package. Some embodiments might place the set of IC&#39;s side by side into a single package. Some embodiments might stack some IC&#39;s while placing other IC&#39;s side by side in a single package. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The novel features of the invention are set forth in the appended claims. However, for purpose of explanation, several embodiments of the invention are set forth in the following figures. 
         FIG. 1  illustrates a PSiP with IC&#39;s that are stacked in a pyramid structure and includes a ball grid array. 
         FIG. 2  illustrates a PSiP with IC&#39;s that are stacked in a non-pyramid structure and includes a pin grid array. 
         FIG. 3  illustrates a PSiP with IC&#39;s that are placed side by side. 
         FIG. 4  illustrates a PSiP with IC&#39;s that are stacked and placed side by side. 
         FIG. 5  illustrates a reconfigurable IC that can perform the operations of a non configurable IC. 
         FIG. 6  illustrates a PSiP with a reconfigurable IC stacked on top of non configurable IC&#39;s. 
         FIG. 7  illustrates a PSiP with IC&#39;s that have different manufacturing processes. 
         FIG. 8  illustrates a PSiP with a heat sink in the PSiP. 
         FIG. 9  illustrates a PSiP with a heat sink embedded in the first IC of the PSiP. 
         FIG. 10  illustrates a process of manufacturing a PSiP. 
         FIG. 11  illustrates a method of identifying IC&#39;s for a PSiP. 
         FIG. 12  illustrates an example of a system for a PSiP divided into a set of operations. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     In the following description, numerous details are set forth for purpose of explanation. However, one of ordinary skill in the art will realize that the invention may be practiced without the use of these specific details. In other instances well-known structures and devices are shown in block diagram form in order not to obscure the description of the invention with unnecessary detail. 
     Some embodiments of the invention provide a programmable system in package (“PSiP”). The PSiP includes a single IC housing, a substrate and several IC&#39;s that are arranged within the single IC housing. At least one of the IC&#39;s is a configurable IC. In some embodiments, the configurable IC is a reconfigurable IC that can reconfigure more than once during “run time”. 
     As used in this document, run time means a period during which the PSiP continuously receives power (i.e., after the PSiP starts receiving power and before the PSiP stops receiving power). Also, in this document, the term “IC” refers to a semiconductor wafer on which a number of circuit elements (e.g., transistors, resistors, etc.) have been defined. 
     In some of these embodiments, the reconfigurable IC can be reconfigured at a first clock rate that is faster (i.e., larger) than the clock rates of one or more of the other IC&#39;s in the PSiP. The first clock rate is faster than the clock rate of all of the other IC&#39;s in the PSiP in some embodiments. 
     In some of the embodiments, the set of IC&#39;s may include digital and analog IC&#39;s. Furthermore, in some embodiments, the set of IC&#39;s may include IC&#39;s that are manufactured with different fabrication technologies. Moreover, different embodiments might package the set of IC&#39;s differently in a single package. Some embodiments might stack the set of IC&#39;s on top of each other into a single package. Some embodiments might place the set of IC&#39;s side by side into a single package. Some embodiments might stack some IC&#39;s while placing other IC&#39;s side by side in a single package. 
     I. Structure of PSiP with Configurable Ic 
     A. Stacked IC&#39;s 
       FIG. 1  illustrates an example of a PSiP that includes several IC&#39;s that are stacked. As shown in this figure, the PSiP  100  includes a substrate  105 , a ball grid array (“BGA”)  110 , a set of vias  115 , a first IC  120 , a second IC  125 , a third IC  130 , a fourth IC  135 , a first adhesive  140 , a second adhesive  145 , a third adhesive  150 , a fourth adhesive  155 , a first set of wire-bonding  160 , a second set of wire-bonding  165 , a third set of wire-bonding  170 , a fourth set of wire-bonding  175 , and a housing  180 . In some embodiments, at least one of the IC&#39;s  120 - 135  is a configurable IC, or a reconfigurable IC, as further described below. 
     As shown in  FIG. 1 , the substrate  105  serves as a base for creating the PSiP. In some embodiments, the substrate  105  is a non-conducting or insulating material that prevents outside electrical phenomena (e.g., current, voltage) from interfering with the internal IC&#39;s (e.g., first, second, third, fourth IC&#39;s) of the PSiP  100 . 
     As further shown in  FIG. 1 , the first IC  120  is located on top of the substrate  105 . A first adhesive  140  bonds the first IC  120  to the substrate  105 . The second IC  125  is located on top of the first IC  120 . The second adhesive  145  bonds the second IC  125  to the first IC  120 . The third IC  130  is located on top of the second IC  125 . The third adhesive  150  bonds the second IC  125  to the third IC  130 . The fourth IC  135  is located on top of the third IC  130 . The fourth adhesive  155  bonds the third IC  130  to the fourth IC  135 . As shown in this figure, the ICs  120 - 135  are stacked in a pyramid structure. That is, the ICs  120 - 135  are stacked bottom to top, from the largest IC to the smallest IC. However, other embodiments might stack the ICs  120 - 135  differently, such as shown in  FIG. 2 . 
     As further shown in  FIG. 1 , the first IC  120  is communicatively attached to the substrate  105  through the first set of wire-bonding  160 . Similarly, each of the IC&#39;s  125 - 135  is communicatively attached to the substrate  105  through a respective set of wire-bonding  165 ,  170 , or  175 . These sets of wire-bonding  160 - 175  allow the first, second, third and fourth IC&#39;s  120 - 135  to communicate with each other without having to go outside of the PSiP  100 . In some embodiments, the IC&#39;s  120 - 135  might be directly wire-bonded to each other in order to facilitate communication between these IC&#39;s. Instead of, or in conjunction with the sets of wire-bonding  160 - 175 , some embodiments might use other mechanisms to communicatively couple the IC&#39;s  120 - 135  to each other. Furthermore,  FIG. 1  illustrates the sets of wire-bonding  160 - 175  attached to the top surface of the IC&#39;s  120 - 135 . However, in other embodiments, the sets of wire-bonding  160 - 175  may be attached to another surface area (e.g. side surface area) of the IC&#39;s  120 - 135  of the PSiP  100 , such as shown in  FIG. 2 . 
     As further shown in  FIG. 1 , the substrate  105  includes the BGA  110  and the set of vias  115 . The BGA  110  is a set of solder balls that allows the PSiP  100  to be attached to a printed circuit board (“PCB”). Each via connects a solder ball in the BGA  110  on the bottom of the substrate  105 , to a conductor on the top of the substrate  105 . 
     The conductors on the top of the substrate  105  are electrically coupled to the IC&#39;s  120 - 135  through the sets of wire bonding  160 - 175 . Accordingly, the IC&#39;s  120 - 135  can send and receive signals to and from circuits outside of the PSiP  100  through the sets of wire bonding  160 - 175 , the conductors on the top of the substrate  105 , the set of vias  115 , and the BGA  110 . 
     Some embodiments place the BGA  110  in a concentric two-dimensional array at the bottom of the substrate. Other embodiments might place the BGA  110  in other arrangements (e.g., in a peripheral arrangement around the perimeter of the PSiP  100 ). In other embodiments, a PSiP  200  includes a pin grid array (“PGA”)  205 , as shown in  FIG. 2 . The PGA  205  performs the same function as the BGA  115  shown in  FIG. 1 . As such, in combination with the set of vias  115 , the PGA  205  provides an intermediate that allows the IC&#39;s  120 - 135  inside the PSiP  200  to communicate with other IC&#39;s outside the PSiP  200 . 
     As further shown in  FIG. 1 , the housing  180  encapsulates the substrate  105 , the BGA  110 , the set of vias  115 , the IC&#39;s  120 - 135 , the adhesives  140 - 155 , the sets of wire-bonding  160 - 175  to form the PSiP  100 . 
     In the figures mentioned above and below, the PSiPs are shown attached to a PCB facing up. However, one of ordinary skill in the art will realize that other PSiP structures can be used. For example, some embodiments might use a flip chip structure. In such instances, the PSiPs are flipped over and attached to the PCB facing down. 
     B. Side by Side IC&#39;s 
       FIG. 3  illustrates an example of a PSiP  300  that includes several IC&#39;s that are placed side by side to each other. As shown in this figure, the first, second, third and fourth IC&#39;s  120 - 135  are located on top of the substrate  105 . In some embodiments, at least one of the IC&#39;s  120 - 135  is a configurable IC or a reconfigurable IC, as further described below. 
     In the PSiP  300 , each IC is placed side by side to each other. A first adhesive  140  is placed between the first IC  120  and the substrate  105  to bond them together. Similarly, a second, third and fourth adhesive  145 - 155  are respectively placed between the second, third and fourth IC  125 - 135  and the substrate  105 . A first, second, third and fourth set of wire-bonding  160 - 175  are attached respectively to the first, second, third and fourth IC&#39;s  120 - 135 . These sets of wire-bonding  160 - 175  allow the IC&#39;s  120 - 135  (1) to communicate with each other without having to go outside of the PSiP, and (2) to communicate with IC&#39;s that are located outside of the PSiP  300 . 
     The PSiP  300  includes a BGA  110  and a set of vias  115 . As previously mentioned, the BGA  110  and the set of vias  115  allow the IC&#39;s  120 - 135  to communicate with IC&#39;s outside of the PSiP  300 . In contrast to the PSiP  100  with stacked IC&#39;s, which provides a PSiP that is narrow, the PSiP  300  that includes side by side IC&#39;s provides a PSiP that is thin. 
     iii. Combination of Stacked and Side by Side IC&#39;s 
       FIG. 4  illustrates an example of a PSiP  400  that includes a combination of stacked and side by side IC&#39;s. In such an embodiment, some IC&#39;s of the PSiP  400  are stacked on top of each other, while other IC&#39;s of the PSiP  400  are placed side by side to each other. As shown in this figure, a first, second and third IC  120 - 130  is placed on top of a substrate  105 . A first, second and third adhesive  140 - 150  respectively bond the first, second and third IC  120 - 130  to the substrate  105 . A fourth IC  135  is placed on top of the third IC  130 . A fourth adhesive  155  bonds the fourth IC  135  to the third IC  130 . In some embodiments, at least one of the IC&#39;s  120 - 135  is a configurable IC. Furthermore, the PSiP  400  includes a first, second, third and fourth set of wire-bonding  160 - 175  that are attached respectively to the first, second, third and fourth IC&#39;s  120 - 135 . As previously described, these sets of wire-bonding  160 - 175  allow the IC&#39;s  120 - 135  to communicate with each other. In other embodiments, the PSiP  400  further includes a BGA  110  and a set of vias  115  to allow the IC&#39;s  120 - 135  to communicate with IC&#39;s outside of the PSiP  400 . 
     II. PSiP with Reconfigurable IC&#39;s 
     In some embodiments, the configurable IC of the PSiP&#39;s described above is a reconfigurable IC that reconfigures more than once during runtime. In some embodiments, this reconfigurable IC might be a sub-cycle reconfigurable IC.  FIG. 5  conceptually illustrates an example of a sub-cycle reconfigurable IC. Specifically, in its top left hand corner, this figure illustrates a non-configurable IC  505  that operates at a clock speed of X MHz. As further illustrated in this figure, the operations performed by this non-configurable IC  505  can be partitioned into four sets of operations that are each performed at a clock speed of X MHz. 
       FIG. 5  then illustrates that these four sets of operations can be performed by one sub-cycle reconfigurable IC  530  that operates at 4× MHz. In some embodiments, four cycles of the 4× MHz clock correspond to four sub-cycles within a cycle of the X MHz clock. Accordingly, this figure illustrates the reconfigurable IC  530  reconfiguring four times during four cycles of the 4× MHz clock (i.e., during four sub-cycles of the X MHz clock). During each of these reconfigurations (i.e., during each sub-cycle), the reconfigurable IC  530  performs one of the identified four sets of operations. In other words, the faster operational speed of the reconfigurable IC  530  allows this IC to reconfigure four times during each cycle of the X MHz clock, in order to perform the four sets of operations sequentially at a 4× MHz rate instead of performing the four sets of operations in parallel at an X MHz rate. 
     In some embodiments, a reconfigurable IC  530  reconfigures at a clock speed that is comparatively faster than the clock speed of some or all other IC&#39;s within a PSiP.  FIG. 6  illustrates an example of such a PSiP. Specifically, this figure illustrates a PSiP  600  that includes a first, second, third and fourth IC  605 - 620 . The first, second and third IC&#39;s  605 - 615  are non configurable IC&#39;s. As shown in this figure, each of the first, second and third IC&#39;s  605 - 615  operates at a clock speed of Z MHz or less. The fourth IC  620  is a reconfigurable IC which operates at a clock speed of 4Z MHz. 
     As shown in  FIG. 6 , the clock speed of the reconfigurable IC  620  is comparatively faster than the clock speed of the first, second and third IC&#39;s  605 - 615 . In other embodiments, the clock speed of the reconfigurable IC  620  is comparatively faster than the clock speed of either the first, second or third IC  605 - 615 . 
     III. Mixed Fabrication Technology 
     As mentioned above, the IC&#39;s within a PSiP can perform many operations. Examples of operations include a processor operation, an analog operation, a memory operation, etc. In some embodiments, these IC&#39;s are manufactured using different fabrication technologies. For instance, an IC that performs memory operations might be manufactured using 90 nm fabrication technology, while an IC that performs a processor operation might be manufactured using 130 nm fabrication technology, and an IC that performs analog operations might be manufactured using 180 nm. 
       FIG. 7  conceptually illustrates a PSiP  700  that includes IC&#39;s with different fabrication technologies. The PSiP  700  includes a first, second, third and fourth IC  120 - 135  that are placed on top of the substrate  105 . At least one of the IC&#39;s  120 - 135  is a configurable IC. In this figure, the IC&#39;s  120 - 135  have different dimensions (e.g., width, height) to illustrate pictorially and conceptually that some of the IC&#39;s  120 - 135  are manufactured with different fabrication technologies. Irrespective of the conceptual illustration in  FIG. 7 , one of ordinary skill will realize that using different manufacturing fabrication technologies might not result in IC&#39;s with different dimensions. 
     IV. PSiP with Heat Sink 
     In some embodiments, a PSiP includes a heat sink.  FIG. 8  illustrates an example of such a PSiP. As shown in this figure, the PSiP  800  includes a first IC  805  and a configurable IC  810 . The configurable IC  810  is a reconfigurable IC in some embodiments. As shown in  FIG. 8 , the PSiP  800  also includes a heat sink  815  between the first IC  805  and the configurable IC  810 . The heat sink  815  helps dissipate heat from the configurable IC  810  in the PSiP  800 . 
       FIG. 9  illustrates another embodiment of a PSiP that includes a heat sink. As shown in this figure, the PSiP  900  includes a first IC  905  and a configurable IC  910 . The configurable IC  910  is a reconfigurable IC in some embodiments. As shown in  FIG. 9 , the first IC  905  includes (1) a center area  915  on which no circuits are defined, and (2) a periphery area  920  on which circuit elements (e.g., transistors, resistors, wires, etc.) are defined. The center area  915  serves as a heat sink on which configurable IC  910  is positioned. In other words, the center area  915  helps dissipate heat from the configurable IC  910  in the PSiP  900 . 
     Having described various PSiP that include a configurable or reconfigurable IC, a method of manufacturing a PSiP and selecting the IC&#39;s for the PSiP will now be described in detail. 
     V. Manufacturing PSiP 
       FIG. 10  conceptually illustrates a process  1000  for manufacturing a PSiP. As shown in this figure, the system requirements of the PSiP are initially identified (at  1005 ). That is, this operation identifies what performance objectives the PSiP has to achieve. After identifying (at  1005 ) the system requirements of the PSiP, sets of operations that are necessary for achieving the identified system requirements are identified at  1010 . For each set of operation identified at  1010 , a determination is made (at  1010 ) whether to implement the set of operations by using an existing IC or a new IC that will be specifically designed or configured to implement the set of operations. In some embodiments, at least one of the IC&#39;s identified at  1010  is a configurable IC. In some of these embodiments, this configurable IC is a reconfigurable IC that reconfigures more than once during run time. The operation at  1010  will be further described below by reference to  FIG. 11 . 
     After identifying new or existing IC&#39;s, a PSiP structure is identified (at  1015 ) for housing all the identified IC&#39;s. As described above, a PSiP can be structured in numerous ways. In some embodiments, a PSiP can include IC&#39;s that are stacked. In other embodiments, a PSiP can include IC&#39;s that are placed side by side. In yet other embodiments, a PSiP can include IC&#39;s that are placed side by side and stacked. 
     After defining (at  1015 ) the structure of the PSiP, a pre-fabrication analysis is performed (at  1020 ) to determine whether the designed PSiP is likely to satisfy the system requirements. If the designed PSiP fails this analysis, the process (1) returns back to  1010  to redefine the sets of operations and/or to modify the IC selection/design choices, and then (2) transitions to  1015  to define a PSiP structure for housing the IC&#39;s identified at  1010 . 
     When the PSiP design passes the pre-fabrication analysis at  1020 , the PSiP is manufactured (at  1025 ) based on the IC&#39;s identified in the last iteration of  1010  and the PSiP structure identified in the last iteration of  1015 . In some embodiments, the manufacturing process entails purchasing and/or configuring only existing IC&#39;s to produce the desired PSiP. In other embodiments, the manufacturing process entails manufacturing at least one new IC to produce the PSiP. 
     After manufacturing the PSiP, the manufactured PSiP is tested (at  1030 ) to determine whether the manufactured PSiP meets the system requirements that were identified (at  1005 ). If not, the process returns to  1010 , which was described above. When the manufactured PSiP passes the post-fabrication analysis at  1030 , then the process  1000  ends. 
     VI. Identifying Reconfigurable Ic&#39;s for PSiP 
       FIG. 11  conceptually illustrates a process  1100  for selecting and identifying IC&#39;s to be used in a PSiP. Some embodiments perform the process  1100  to implement the design operation  1010  in  FIG. 10 . As shown  FIG. 11 , an available budget for producing the PSiP is initially identified at  1105 . In some embodiments, this budget is predicted on producing a certain number of PSiP&#39;s. Also, in some embodiments, the identified budget accounts for all funds necessary (1) for designing, configuring and manufacturing new IC or IC&#39;s if such IC&#39;s are required by the PSiP, and (2) for acquiring and/or configuring an existing IC. In other embodiments, this amount also includes the cost of the PSiP packaging, assembling, and/or testing. 
     Once the available budget has been defined (at  1105 ), sets of operations are identified (at  1110 ) by dividing the system requirements of the PSiP into several operational blocks, where each operational block represents a set of operations that the PSiP has to perform.  FIG. 12  conceptually illustrates an example of dividing the system requirements for a PSiP into several operational blocks. In this example, the operational blocks include a processor operation block  1205 , a memory operation block  1210 , a digital signal processor operation block  1220 , an analog operation block  1225 , an analog/digital converter operation block  1230 , a digital/analog converter operation block  1235 , and a reconfigurable IC operation block  1240 . As mentioned above, each operational block includes a set of operations that the PSiP has to perform. For instance, the processor operation block  1205  may include a set of processing operations that the PSiP has to perform. 
     Once the sets of operations have been identified (at  1110 ) by dividing the system requirement of the PSiP into several operational blocks, one or more sets of operations (i.e., selects at least one or more operational blocks) are selected at  1115 . After selecting one or more sets of operations at  1115 , an IC that can perform the selected set or sets of operations is identified at  1120 . The identified IC might be an existing IC that can perform or can be configured to perform the set or sets of operations selected at  1115 . Alternatively, the identified IC might be an IC that has to be designed to perform, or has to be designed to be configured to perform, the selected set of operations. In at least one iteration through  1120 , the selected IC is a configurable IC. In some cases, the configurable IC is a reconfigurable IC that can reconfigured more than once at run time. 
     Different identified IC&#39;s perform the selected set or sets of operations differently. For instance, a non-configurable IC that is identified at  1120  might perform in parallel the operations in the set or sets of operations selected at  1115 . Alternatively, the IC identified at  1120  might be a configurable IC that can be configured to perform in parallel the operations in the set or sets of operations selected at  1115 . On the other hand, the IC identified at  1120  might be a reconfigurable IC that sequentially performs one or more sub-sets of the operations in the set(s) of operations selected at  1115  during different reconfiguration sub-cycles. 
     Once the IC is identified at  1120 , a determination is made (at  1125 ) as to whether the actual or estimated cost of the identified IC is less than the available budget. When the selected IC is a previously designed IC, the cost of the IC is the cost associated with purchasing, manufacturing, and/or configuring the previously designed IC. When the selected IC is an IC that has yet to be designed, the cost of the IC is the cost associated with designing, testing, manufacturing, and/or configuring the IC. Furthermore, in some embodiments, the cost of the IC accounts for costs associated with packaging and assembling the IC within the PSiP. In such embodiments, the process  1100  might perform the package-defining operation  1015  of the process  1000  of  FIG. 10 , or might simply account for the probable cost of such a packaging. 
     If the cost of the identified IC is not less than the available budget, the process  1100  proceeds back to  1120  to identify another IC for the selected set of operations. However, if the cost of the identified IC is less than the available budget, the process  1100  subtracts (at  1130 ) the cost of the identified IC from the available budget. 
     Once the cost of the identified IC has been subtracted from the available budget, a determination is made (at  1135 ) whether there is an additional set of operations that has not yet been associated with an IC. If so, the process  1100  (1) returns back to  1115  to select other set or sets of operations that have not yet been selected, and then (2) proceeds to  1120  to identify another IC for the newly selected set or sets of operations. 
     When it is determined (at  1135 ) that there is no additional set of operations, a determination is made (at  1140 ) whether the identified set of IC&#39;s is a good enough set of IC&#39;s for implementing the PSiP. For instance, when the identified set of IC&#39;s includes a reconfigurable IC, a determination might be made (at  1140 ) that the reconfigurable IC can perform additional operations in order to reduce the overall cost of the PSiP. Such additional operations would be operations that were previously identified for another IC. When a determination is made (at  1140 ) that the set of IC&#39;s is a good enough set, the process  1100  ends. 
     A PSiP, i.e., a SiP with a configurable or reconfigurable IC, has many advantages. A PSiP provides a simple solution for combining the often desirable configurable functionality of a configurable or reconfigurable IC with the functionalities commonly provided by other IC&#39;s. PSiP&#39;s are easier to design than the currently proposed SoC solutions that combine configurable functionality of configurable IC&#39;s with other IC functionalities. 
     Also, the IC&#39;s of a PSiP can be manufactured by different fabrication technologies. Hence, optimal fabrication processes can be used to manufacture the IC&#39;s of the PSiP. This is to be contrasted with the prior SoC solutions that require the use of one fabrication process for all the operational blocks on the SoC, which results in some of the operational blocks being manufactured by fabrication processes that are far from their optimal fabrication technology. 
     While the invention has been described with reference to numerous specific details, one of ordinary skill in the art will recognize that the invention can be embodied in other specific forms without departing from the spirit of the invention. For instance, some embodiments might first identify all the IC&#39;s for the PSiP and then determine whether the cost of all the IC&#39;s is less than the available budget. Furthermore, in some instances, some embodiments might identify an IC based on IC&#39;s that were previously identified. Additionally, some embodiments determine whether a set of IC&#39;s is optimized based on cost. As such, in some instances, a set of IC&#39;s is not optimized if the cost of the set of IC&#39;s can be further minimized. Thus, one of ordinary skill in the art would understand that the invention is not to be limited by the foregoing illustrative details, but rather is to be defined by the appended claims.