Patent Publication Number: US-6670683-B2

Title: Composite transistor having a slew-rate control

Description:
BACKGROUND OF THE INVENTION 
     1. Technical Field 
     The present invention relates to semiconductor devices in general, and in particular to metal oxide semiconductor (MOS) transistors. Still more particularly, the present invention relates to a MOS transistor having a slew-rate control. 
     2. Description of the Prior Art 
     Integrated circuit devices commonly employ output buffers for driving other external devices. In order to provide a high DC drive capability, at least two output transistors are typically placed in parallel within each output buffer of an integrated circuit device. When an output buffer is changing states, the switching current present within the output buffer becomes a major source of noise spikes on power buses, which may induce latch-up to other devices. Although such noise spikes can be lessened by reducing the size of output buffers, small output buffers are usually incapable of driving heavy loads that are frequently required of an output buffer. Hence, a slew rate control circuit is commonly provided to slow down an output buffer in a manner that will reduce the rate of change of output voltage and peak current value while maintaining the DC drive capability of the output buffer. Slew rate is defined as the rate of output transition in volts per unit time. Slew rate control is also very important in the settings of precision differential amplifier applications and delay line applications in which precision delay signals are introduced to a signal propagation. 
     Conventionally, a slew rate control circuit for an output buffer includes multiple delay elements placed between each pair of parallel output transistors within the output buffer. However, the inclusion of delay elements requires considerable amount of silicon area in which the output buffer is implemented. The area penalty becomes more costly as the output area becomes a size limiting factor for circuits that are manufactured in submicron technology. Consequently, it would be desirable to provide an improved apparatus for controlling the slew rate of an output buffer such that the above-described problems associated with the prior art slew rate control circuit can be alleviated. 
     SUMMARY OF THE INVENTION 
     In accordance with a preferred embodiment of the present invention, a transistor having a slew-rate control includes an elongated diffusion area and an elongated gate overlying the diffusion area. The elongated diffusion area has at least two diffusion regions, each having a threshold voltage that is different from each other. The elongated gate has a gate contact at only one side of the elongated diffusion area. 
     All objects, features, and advantages of the present invention will become apparent in the following detailed written description. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein: 
     FIG. 1 is a circuit diagram of an output buffer according to the prior art; 
     FIG. 2 a  is a circuit layout diagram of an output transistor, in accordance with a preferred embodiment of the present invention; 
     FIG. 2 b  is a graphical depiction of the output voltage characteristic of the output transistor from FIG. 2 a;    
     FIG. 3 a  is a circuit layout diagram of an output transistor, in accordance with a second embodiment of the present invention; 
     FIG. 3 b  is a graphical depiction of the output voltage characteristic of the output transistor from FIG. 3 a;    
     FIG. 4 a  is a circuit layout diagram of an output transistor, in accordance with a third embodiment of the present invention; 
     FIG. 4 b  is a graphical depiction of the output voltage characteristic of the output transistor from FIG. 4 a;  and 
     FIG. 5 is a high-level process flow diagram of a method for manufacturing the transistor from FIG. 2 a,  in accordance with a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT 
     Referring now to the drawings and in particular to FIG. 1, there is depicted a circuit diagram of an output buffer according to the prior art. As shown, an output buffer  10  includes an output transistor  11   a  and an output transistor  11   b  connected in parallel. In order to control the slew rate of output buffer  10 , several delay elements, such as inverters  12  and  13 , are placed between output transistors  11   a  and  11   b.  Because of the addition of inverters  12  and  13 , the silicon area required to implement output buffer  10  is larger than is necessary. 
     Thus, instead of using two output transistors connected in parallel to implement an output buffer, the present invention employs one output transistor with a built-in slew-rate control. There are two scenarios that should be considered. The first scenario relates to situations when the slew rate of a rising input signal is critical and must be controlled. The second scenario relates to situations when the slew rate of the falling edge of an input signal is critical and must be controlled. The first scenario is handled by an output transistor shown in FIG. 2 a,  and the second scenario is handled by an output transistor shown in FIG. 3 a.    
     With reference now to FIG. 2 a,  there is illustrated a circuit layout diagram of an output transistor having a slew-rate control, in accordance with a preferred embodiment of the present invention. As shown, an P-channel output transistor  20  includes an elongated polysilicon gate  21  and an elongated diffusion  22 . Polysilicon gate  21  is connected to other circuits via a gate contact  23 . The source and drain of diffusion  22  are connected to other circuits via diffusion contacts  24 ,  25 , respectively. Output transistor  20  is a “wide” device with a relatively short channel length. The aspect ratio of width-to-length for diffusion  22  is approximately 10:1. As a comparison, for a given integrated circuit device with multiple transistors including output transistor  20  that are manufactured by the 0.25 μm complementary-metal-oxide semiconductor (CMOS) technology, output transistor  20  has a channel width of approximately 2.25 μm and a channel length of approximately 0.15 μm, while other transistors have an average channel width of approximately 0.75 μm and an average channel length of approximately 0.15 μm. 
     Output transistor  20  has preferably two different threshold voltage (Vt) regions, namely, a low Vt (LVT) region and a high Vt (HVT) region, within diffusion  22  for achieving slew rate control. In FIG. 2 a,  the LVT region is located closer to gate contact  23  than the HVT region. The slew rate control of output transistor  20  is achieved by the percentage of gate width allocated to the LVT region and the HVT region. 
     Polysilicon gate  21  is also wide and narrow. Thus, a conducting channel will slowly form from the left side of diffusion  22  to the right side of diffusion  22  because of the delay for a voltage signal to travel across the resistance of polysilicon gate  21 . The resistance of polysilicon gate  21  can be further increased by adding squares of resistance between the LVT and HVT regions, and/or altering the doping of polysilicon gate  21 . The resistance of polysilicon gate  21  may also be controlled by selectively blocking the silicide formation in various regions of polysilicon gate  21 . In addition, although the channel length of polysilicon gate  21  is shown to be uniform in FIG. 2 a,  it is understood the channel length of polysilicon gate  21  can be longer in the LVT region than in the HVT region or vice versa such that shorter portion would appear as a “bottleneck” to the longer portion. 
     The output voltage characteristic of output transistor  20  is depicted in FIG. 2 b.  As shown, the output voltage of output transistor  20  ramps up slowly in the beginning when only the LVT region of diffusion  22  is turned on. The LVT region is turned on before the HVT region because the LVT region is closer to gate contact  23  than the HVT region, and the LVT region has a lower voltage threshold than the HVT region. Afterwards, the output voltage of output transistor  20  begins to increase at a faster ramp rate when the LVT and HVT regions are both turned on. In essence, the LVT region produces a slow initial ramp and then the HVT region produces a faster ramp to complete the transition of a signal. The time delay for turning on the HVT region of output transistor  20  can be controlled by adjusting the resistance of polysilicon gate  21 . 
     Referring now to FIG. 3 a,  there is illustrated a circuit layout diagram of an output transistor, in accordance with a second embodiment of the present invention. As shown, a P-channel output transistor  30  includes an elongated polysilicon gate  31  and an elongated diffusion  32 . Polysilicon gate  31  is connected to other circuits via a gate contact  33 . The source and drain of diffusion  32  are connected to other circuits via diffusion contacts  34 ,  35 , respectively. The difference between output transistor  30  and output transistor  20  (from FIG. 2) is that the HVT region of output transistor  30  is located closer to gate contact  33  than the HVT region of output transistor  20 . As a result, output transistor  30  has an output voltage characteristic that is different from that of output transistor  20 . 
     The output voltage characteristic of transistor  30  is depicted in FIG. 3 b.  As shown, the output voltage of output transistor  30  ramps down slowly in the beginning when only the HVT region is turned off. Afterwards, the output voltage of output transistor  30  begins to ramp down rapidly when the HVT and LVT regions are both turned off. The HVT region is located closer to gate contact  23  and is smaller than the LVT region so output transistor  30  initially discharges the load slowly. The LVT region turns on subsequently and sinks current more quickly to achieve the completion of the transition. The time delay for turning on the LVT region of output transistor  30  can be controlled by adjusting the resistance of polysilicon gate  31 . 
     With reference now to FIG. 4 a,  there is illustrated a circuit layout diagram of an output transistor having a slew-rate control, in accordance with a third embodiment of the present invention. As shown, a P-channel output transistor  40  includes an elongated polysilicon gate  41  and diffusions  42   a,    42   b.  Diffusion  42   a  is the LVT region, and diffusion  42   b  is the HVT region. Polysilicon gate  41  is connected to other circuits via a gate contact  43 . The source and drain of diffusions  42   a,    42   b  are connected to other circuits via diffusion contacts  44 ,  55 , respectively. The resistance of the middle segment of polysilicon gate  41  is R 2 , and the resistance of the remaining two segments of polysilicon gate  41  are R 1  and R 3 , where R 2 &gt;R 1 &gt;R 3 . 
     The output voltage characteristic of output transistor  40  is depicted in FIG. 4 b.  Similar to FIG. 3 b,  the output voltage of output transistor  40  ramps up slowly initially when only the HVT region is turned on. Afterwards, the output voltage of output transistor  40  begins to ramp up rapidly when the HVT and LVT regions are both turned on. The difference between FIG. 4 b  and FIG. 3 b  is that the initial ramp up time, t ramp , in FIG. 4 b  is longer than that of FIG. 3 b.    
     Referring now to FIG. 5, there is illustrated a high-level process flow diagram of a method for manufacturing a transistor having a slew-rate control, such as output transistor  20  from FIG. 2 a,  in accordance with a preferred embodiment of the present invention. After all active device regions have been isolated by silicon dioxide, as shown in block  51 , an ion implantation procedure is performed to define a well area, as depicted in block  52 . The ion implantation procedure can be performed by using N-type ions, such as Phosphorus, with a dose in the range of 1×10 12  atoms/cm 2  to 5×10 12  atoms/cm 2  and an energy of 15-50 KeV. After masking off an intended LVT region in the well area, as shown in block  53 , another ion implantation procedure is performed to define an HVT region in the well area, as depicted in block  54 . Such ion implantation procedure can be performed by using N-type ions with a dose in the range of 5×10 12  atoms/cm 2  to 10×10 12  atoms/cm 2  and an energy of 15-50 KeV. After stripping off the mask from the well area, as shown in block  55 , a gate oxide is grown over the well area, as depicted in block  56 . The thickness of the gate oxide is preferably 2 nm-5 nm. Next, a layer of polysilicon, approximately 150 nm-200 nm, is deposited over the gate oxide, as shown in block  57 . Finally, a gate is formed by etching the polysilicon, as depicted in block  58 . 
     As has been described, the present invention provides an output transistor having a slew-rate control. The output transistor of the present invention allows customized slew rate control on precision circuits to achieve specific functional responses. Such type of control is often required in order to sense signals, to customize arrays, or to produce delay lines accurately. Although P-channel transistors are used to illustrate the present invention, it is understood by those skilled in the art that the principle of the present invention can also be applicable to N-channel transistors using P-type dopants such as Boron. 
     While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.