Patent Publication Number: US-2003235944-A1

Title: Semiconductor device manufacturing method

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
       [0001] This application is based upon and claims priority of Japanese Patent Application No. 2002-180453, filed on Jun. 20, 2002, the contents being incorporated herein by reference.  
       BACKGROUND OF THE INVENTION  
       [0002] 1. Field of the Invention  
       [0003] The present invention relates to a semiconductor device manufacturing method and, more particularly, a semiconductor device manufacturing method having the step of forming a capacitor that employs ferroelectric substance.  
       [0004] 2. Description of the Prior Art  
       [0005] In the semiconductor memory, increase in the memory capacity and miniaturization of the device are required. In FeRAM, for the purpose of miniaturization, the memory cell using the stacked ferroelectric capacitor is required.  
       [0006] Next, a method of forming the ferroelectric capacitor is explained with reference to FIGS. 1A and 1B as follows.  
       [0007] First, as shown in FIG. 1A, a first metal film  103 , a ferroelectric film  104 , and a second metal film  105  are formed sequentially on an insulating film  102  that covers a semiconductor substrate  101 , and then a mask  106  having a capacitor planar shape is formed on the second metal film  105 .  
       [0008] Then, as shown in FIG. 1B, regions of the second metal film  105 , the ferroelectric film  104 , and the first metal film  103 , which are not covered with the mask  106 , are etched successively. Accordingly, an upper electrode  105   a  of a capacitor Q o  is formed from the second metal film  105  under the mask  106 , a dielectric film  104   a  of the capacitor Q o  is formed from the ferroelectric film  104 , and a lower electrode  103   a  of the capacitor Q o  is formed from the first metal film  103 .  
       [0009] In this case, the method of forming the stacked ferroelectric capacitor is set forth in Patent Application Publication (KOKAI) Hei 8-45905, for example.  
       [0010] In order to enhance an area efficiency of the capacitance of the capacitor Q o , respective planar surfaces of the lower electrode  103   a , the dielectric film  104   a , and the upper electrode  105   a  must be set as equal in size as possible by increasing a taper angle θ of a side surface of the capacitor Q o  to an upper surface of the insulating film  102  as large as possible.  
       [0011] In order to form side surfaces of the capacitor sharply, it is necessary that the etching by-product, which is generated in etching the first metal film  103 , the ferroelectric film  104 , and the second metal film  105 , should be hardly adhered onto the side surfaces of the capacitor Q o .  
       [0012] As the method of suppressing the adhesion of the etching by-product onto the side surfaces of the capacitor Q o , it is studied to etch films from the second metal film  105  to the first metal film  103  successively while keeping the semiconductor substrate  101  at the high temperature of 300 to 500° C.  
       [0013] However, if the resist is employed as the material of the mask  106 , such the resist is deteriorated in the midst of the etching and does not function as the mask  106 .  
       [0014] Therefore, the mask must be formed of the material with the heat resistance. As the mask with the heat resistance, employment of a hard mask that is made of a hard film such as a titanium film, a titanium nitride film, an aluminum film, or the like may be considered.  
       [0015] Next, steps of forming the hard mask and forming the capacitor by using the hard mask are explained with reference to FIGS. 2A to  2 D as follows.  
       [0016] First, as shown in FIG. 2A, the first metal film  103 , the ferroelectric film  104 , and the second metal film  105  are formed sequentially on the insulating film  102 . Then, a hard film  110  made of any of titanium, titanium nitride, and aluminum is formed on the second metal film  105 . Then, a resist pattern  111  having a capacitor planar shape is formed on the hard film  110 .  
       [0017] Then, as shown in FIG. 2B, the hard film  110  left under the resist pattern  111  is formed into a hard mask  110 M by etching the hard film  110  that is exposed from the resist pattern  111 .  
       [0018] Then, the resist pattern  111  is removed. Then, as shown in FIGS. 2C and 2D, regions of the second metal film  105 , the ferroelectric film  104 , and the first metal film  103 , which are not covered with the hard mask  110 M, are etched successively. Accordingly, the capacitor Q o  is formed under the hard mask  110 M.  
       [0019] In the event that any of titanium, titanium nitride, and aluminum is employed as the material of the hard mask  110 M, etching resistance of the hard mask  110 M is improved extremely by condition of which an oxygen gas is added into the etching gas. Therefore, there is no need to form the hard mask  110 M thick. In addition, in the event that the resist pattern  111  used to form the hard mask  110 M is made of the resist for excimer exposure, it is indispensable that, in order to enhance the pattern precision, the hard film  110  should be formed thin.  
       [0020] However, as shown in FIG. 2C, according to the experiment made by the inventors of the present invention, it was become apparent that, when the high-selectivity etching executed at the high temperature in the oxygen-added atmosphere is employed, the microloading effect is enhanced in the step of etching the ferroelectric film  104 , in particular the PZT film, by using the hard mask  110 M, so that the etching rate of the ferroelectric film  104  is lowered extremely in the narrow region between the capacitors Q o  and thus residue of the ferroelectric film  104  is generated around the hard mask  110 M.  
       [0021] If the etching of the first metal film  103  is carried out in the situation that the residue of PZT is present, the first metal film  103  is left like the island, as shown in FIG. 2D, since the residue of the ferroelectric film  104  functions substantially as the mask. As a result, it is possible that the pattern precision of the capacitor Q o  is lowered or the upper electrodes  105   a  of the neighboring capacitors Q o  are short-circuited by the conductive residue.  
       [0022] Therefore, it may be considered that the hard mask made of the material that does not cause the microloading effect in etching the ferroelectric film should employed. As such material, there are silicon oxide, silicon nitride, etc. In this case, since the silicon oxide film and the silicon nitride film have the low etching selectivity to the etching of the first metal film  103 , the ferroelectric film  104 , and the second metal film  105 , the film thickness must be formed thick in excess of 1 μm. In this case, it is set forth in Patent Application Publication (KOKAI) 2001-36024, for example, that the hard mask  110 M is made of silicon nitride.  
       [0023] In contrast, as set forth in Patent Application Publication (KOKAI) Hei 11-354510, the hard mask having the double-layered structure in which the silicon oxide film is formed on the titanium nitride film may be employed.  
       [0024] Next, steps of forming the capacitor by employing the hard mask having the double-layered structure will be explained with reference to FIGS. 3A to  3 C hereunder.  
       [0025] First, as shown in FIG. 3A, the first metal film  103 , the ferroelectric film  104 , and the second metal film  105  are formed sequentially on the insulating film  102 . Then, a titanium nitride film  110   a  and a silicon oxide film  110   b  are formed on the second metal film  105 . Then, the resist pattern  111  having the capacitor planar shape is formed on the silicon oxide film  110   b.    
       [0026] Then, as shown in FIG. 3B, the silicon oxide film  110   b  and the titanium nitride film  110   a  exposed from the resist pattern  111  are etched. Then, the silicon oxide film  110   b  and the titanium nitride film  110   a  left under the resist pattern  111  are used as the hard mask  110 M.  
       [0027] Then, the resist pattern  111  is removed. Then, as shown in FIG. 3C, regions of the second metal film  105 , the ferroelectric film  104 , and the first metal film  103 , which are not covered with the hard mask  110 M, are successively etched. Accordingly, the capacitor Q o  is formed under the hard mask  110 M.  
       [0028] In case the hard mask  110 M having the above-mentioned double-layered structure is employed, the microloading effect is suppressed and thus etching residue of the ferroelectric film  104  is hard to occur, and in addition at least the titanium nitride film  110   a  is left as the hard mask  110 M upon etching the first metal film  103  and thus the gradient of the side surfaces of the capacitor is set steeply.  
       [0029] However, when the hard mask having the structure shown in FIG. 3B is employed, not only the film forming step of forming the hard mask is increased but also the etching of the silicon oxide film is not suppressed if the oxygen is added in etching. Therefore, the silicon oxide film must be formed thick like about 1 μm, for example. Since it is difficult to pattern such silicon oxide film having a thick film thickness by using the resist for the excimer exposure, it is hard to form the hard mask with high precision.  
       [0030] As a result, the advantages of the hard mask having the double-layered structure are not sufficiently put into practical use.  
       SUMMARY OF THE INVENTION  
       [0031] It is an object of the present invention to provide a semiconductor device manufacturing method including the step that makes it possible to pattern a plurality of films constituting a capacitor with good precision by using hard masks.  
       [0032] According to one aspect of the present invention, there is provided a method of manufacturing a semiconductor device comprising the steps of: forming an insulating film over a semiconductor substrate; forming a first conductive film on the insulating film; forming a ferroelectric film on the first conductive film; forming a second conductive film on the ferroelectric film; forming a hard mask on the second conductive film; forming a capacitor upper electrode under the hard mask by etching the second conductive film in an area, which is exposed from the hard mask, at a first temperature by using a first etching gas; forming a capacitor dielectric film under the hard mask by etching the ferroelectric film in the area, which is exposed from the hard mask, at a second temperature by using a second etching gas; and forming a capacitor lower electrode under the hard mask by etching the first conductive film in the area, which is exposed from the hard mask, at a third temperature that is higher than the second temperature by using a third etching gas.  
       [0033] According to the present invention, in the step of forming the capacitor over the substrate, the substrate temperature at the time of etching of the ferroelectric film is set lower than the substrate temperature at the time of etching of the first conductive film when the first conductive film constituting the capacitor lower electrode, the ferroelectric film constituting the capacitor dielectric film, and the second conductive film constituting the capacitor upper electrode are etched sequentially by using the same hard mask. More particularly, the substrate temperature at the time of etching of the ferroelectric film is set to below 300° C., e.g., the atmospheric temperature whereas the substrate temperature at the time of etching of the first conductive film is set to more than 300° C.  
       [0034] According to this, the microloading effect is hard to occur because the substrate temperature is lowered when the ferroelectric film is to be etched by using the hard mask, and thus generation of the etching residue of the ferroelectric film is prevented. In this case, if the substrate temperature is set too low, it is possible that the taper angle of the side surface of the capacitor dielectric film becomes small, but the substrate temperature is set high when the first conductive film is to be etched subsequently. Therefore, since side walls of the capacitor dielectric film extruded from the hard mask is also etched at the time of etching of the first conductive film, the taper angle of the side surface of the capacitor dielectric film becomes steep finally.  
       [0035] The hard mask is formed by the material the etching resistance of which can be improved by adding the oxygen into the etching gas, for example, titanium, titanium nitride, or aluminum. Accordingly, the selective etching ratios of the first conductive film, the ferroelectric film, and the second conductive film to the hard mask is enhanced. Therefore, if the hard mask is formed thin, the first conductive film, the ferroelectric film, and the second conductive film are patterned with good precision. In addition, when the hard mask is formed thin, the patterning precision to form the hard mask is improved and also the patterning is facilitated.  
       [0036] By condition of which such hard mask is formed by a single layer, the mask forming step does not become complicated and thus reduction in throughput of the mask forming step is prevented. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0037]FIGS. 1A and 1B are sectional views of the capacitor forming step showing the first prior art;  
     [0038]FIGS. 2A to  2 D are sectional views of the capacitor forming step showing the second prior art;  
     [0039]FIGS. 3A to  3 C are sectional views of the capacitor forming step showing the third prior art;  
     [0040]FIGS. 4A to  4 K are sectional views showing semiconductor device forming steps according to an embodiment of the present invention;  
     [0041]FIG. 5 is a chart showing control states of the substrate temperature in the etching steps to form the capacitor according to the embodiment of the present invention;  
     [0042]FIG. 6 is a side view showing the capacitor formed according to the embodiment of the present invention; and  
     [0043]FIGS. 7A and 7B are schematic configurative views of the reaction chamber of the etching equipment employed in the embodiment of the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT  
     [0044] An embodiment of the present invention will be explained with reference to the drawings hereinafter.  
     [0045]FIGS. 4A to  4 K are sectional views showing semiconductor device manufacturing steps according to an embodiment of the present invention.  
     [0046] First, steps required until a sectional structure shown in FIG. 4A is formed are explained hereunder.  
     [0047] As shown in FIG. 4A, an element isolation insulating recess is formed around a transistor forming region of an n-type or p-type silicon (semiconductor) substrate  1  by the photolithography method, and then an element isolation insulating film  2  is formed by burying silicon oxide (SiO 2 ) in the element isolation insulating recess. The element isolation insulating film  2  having such structure is called STI (Shallow Trench Isolation). In this case, an insulating film formed by the LOCOS (Local Oxidation of Silicon) method may be employed as the element isolation insulating film.  
     [0048] Then, a p-well  1   a  is formed by introducing the p-type impurity into the transistor forming region of the silicon substrate  1 . Then, a silicon oxide film is formed as a gate insulating film  3  by thermally oxidizing a surface of the transistor forming region of the silicon substrate  1 .  
     [0049] Then, an amorphous silicon or polysilicon film and a tungsten silicide film are formed sequentially on the overall upper surface of the silicon substrate  1 . Then, gate electrodes  4   a ,  4   b  are formed by patterning the silicon film and the tungsten silicide film by virtue of the photolithography method.  
     [0050] In this case, two gate electrodes  4   a ,  4   b  are formed in parallel over one p-well  1   a . These gate electrodes  4   a ,  4   b  constitute a part of the word line.  
     [0051] Then, first to third n-type impurity diffusion regions  5   a  to  5   c  serving as the source/drain are formed by ion-implanting the n-type impurity into the p-well  1   a  on both sides of the gate electrodes  4   a ,  4   b.    
     [0052] Then, an insulating film, e.g., a silicon oxide (SiO 2 ) film is formed on the entire surface of the silicon substrate  1  by the CVD method. Then, insulating sidewall spacers  6  are left on portions on both sides of the gate electrodes  4   a ,  4   b  by etching back the insulating film.  
     [0053] Then, the n-type impurity is ion-implanted into the first to third n-type impurity diffusion regions  5   a  to  5   c  once again by using the gate electrodes  4   a ,  4   b  and the sidewall spacers  6  as a mask. Thus, the first to third n-type impurity diffusion regions  5   a  to  5   c  are formed as the LDD structure.  
     [0054] In this case, the second n-type impurity diffusion region  5   b  positioned between two gate electrodes  4   a ,  4   b  in one transistor forming region is connected electrically to the bit line, described later. The first and third n-type impurity diffusion regions  5   a ,  5   c  positioned on both end sides of the transistor forming region are connected electrically to the lower electrode of the capacitor, described later.  
     [0055] According to the above steps, a first MOS transistor T 1  having the gate electrode  4   a  and the first and second n-type impurity diffusion regions  5   a ,  5   b  with the LDD structure and a second MOS transistor T 2  having the gate electrode  4   b  and the second and third n-type impurity diffusion regions  5   b ,  5   c  with the LDD structure are formed on one p-well  1   a.    
     [0056] Then, a silicon oxide nitride (SiON) film of about 200 nm thickness is formed as a cover insulating film  7 , which covers the MOS transistors T 1 , T 2 , on the overall surface of the silicon substrate  1  by the plasma CVD method. Then, a silicon oxide (SiO 2 ) film of about 1.0 μm thickness is formed as a first interlayer insulating film  8  on the cover insulating film  7  by the plasma CVD method using the TEOS gas.  
     [0057] Then, as the densifying process of the first interlayer insulating film  8 , such first interlayer insulating film  8  is annealed at the temperature of 700° C. for 30 minute in the atmospheric-pressure nitrogen atmosphere, for example. Then, an upper surface of the first interlayer insulating film  8  is planarized by the CMP (Chemical Mechanical Polishing) method.  
     [0058] Next, steps required until a structure shown in FIG. 4B is formed will be explained hereunder.  
     [0059] First, first and second contact holes  8   a ,  8   b  are formed on the first and third n-type impurity diffusion regions  5   a ,  5   c  by patterning the cover insulating film  7  and the first interlayer insulating film  8  by virtue of the photolithography method.  
     [0060] Then, a Ti film of 30 nm thickness and a TiN film of 50 nm thickness are formed sequentially as a glue film on the upper surface of the first interlayer insulating film  8  and in the first and second contact holes  8   a ,  8   b  by the sputter method. Then, a W film is grown on the TiN film by the CVD method to bury insides of the first and second contact holes  8   a ,  8   b  perfectly.  
     [0061] Then, as shown in FIG. 4C, the W film, the TiN film, and the Ti film are polished by the CMP method to remove from the upper surface of the first interlayer insulating film  8 . The W film, the TiN film, and the Ti film left in the first and second contact holes  8   a ,  8   b  are used as first and second conductive plugs  11   a ,  11   c  respectively.  
     [0062] Next, steps required until a structure shown in FIG. 4D is formed will be explained hereunder.  
     [0063] First, an iridium (Ir) film, a platinum (Pt) film, a platinum oxide (PtO x ) film, an iridium oxide (IrO x ) film, or a strontium ruthenium oxide (SRO) film having a thickness of 300 nm, for example, is formed as a first conductive film  13  on the first and second conductive plugs  11   a ,  11   c  and the first interlayer insulating film  8 . As the first conductive film  13 , a multi-layered structure film selected from the Ir film, the Pt film, the PtO x  film, and the IrO x  film may be formed.  
     [0064] In this case, the first interlayer insulating film  8  is annealed to prevent the peeling-off of the film, for example, before or after the first conductive film  13  is formed. As the annealing method, RTA (Rapid Thermal Annealing) executed at 600 to 750° C. in the argon atmosphere, for example, is employed.  
     [0065] Then, a PZT film of 100 nm thickness, for example, is formed as a ferroelectric film  14  on the first conductive film  13  by the sputter method. As the method of forming the ferroelectric film  14 , there are the MOD (Metal Organic Deposition) method, the MOCVD (Metal Organic CVD) method, the sol-gel method, etc. in addition to this. Also, as the material of the ferroelectric film  14 , other PZT material such as PLCSZT, PLZT, etc., the Bi-layered structure compound material such as SrBi 2 Ta 2 O 9 , SrBi 2 (Ta,Nb) 2 O 9 , etc., and other metal oxide ferroelectric substance in addition to PZT.  
     [0066] Then, the ferroelectric film  14  is annealed in the oxygen atmosphere to crystallize. As such annealing, two-step RTA process having the first step executed at the substrate temperature of 600° C. for a time of 90 second in the mixed gas atmosphere consisting of argon and oxygen and the second step executed at the substrate temperature of 750° C. for a time of 60 second in the oxygen atmosphere, for example, is employed.  
     [0067] Then, an iridium oxide (IrO 2 ) film of 200 nm thickness, for example, is formed as a second conductive film  15  on the ferroelectric film  14  by the sputter method.  
     [0068] Then, a hard film  18  made of titanium nitride is formed on the second conductive film  15  to have a thickness of about 300 nm, for example. Material such as titanium, aluminum, or the like, the etching resistance of which is improved by the oxygen, as the hard film  18 , may be formed in place of the titanium nitride film, otherwise the structure in which these materials are formed as plural layers may be employed.  
     [0069] Then, resist  16  for excimer laser exposure is coated on the hard film  18 , and then the resist  16  is exposed by the excimer laser and then developed. Thus, the resist  16  is left over the first and second conductive plugs  11   a ,  11   c  to have a capacitor planar shape.  
     [0070] Then, as shown in FIG. 4E, the hard film  18  is etched by using the resist  16  as a mask, and thus the hard film  18  left under the resist  16  is used as a hard mask  18   a.    
     [0071] The etching of the hard film  18  made of titanium nitride is executed by using the inductively coupled (IPC) plasma etching equipment. As the etching conditions, for example, the silicon substrate  1  is put on the stage in the reaction chamber, BCl 3  and Cl 2  are introduced into the reaction chamber as the etching gas at flow rates of 40 ml/min. and 60 ml/min. respectively, the source power of 13.56 MHz is set to 250 W, the bias power of 400 kHz is set to 200 W, a degree of vacuum in the reaction chamber is set to 1 Pa, and the stage temperature is set to 25° C.  
     [0072] In this case, the bias power is a power of a high-frequency power supply, which is applied to the antenna coil provided to the top portion pf the reaction chamber of the IPC plasma etching equipment. Also, the source power is a power of a high-frequency power supply that is connected to the electrostatic chuck fitted to the stage in the reaction chamber.  
     [0073] After the hard mask  18   a  is formed, the silicon substrate is brought out from the IPC plasma etching equipment and then the resist  16  is removed.  
     [0074] Next, the second conductive film  15 , the ferroelectric film  14 , and the first conductive film  13  in the regions that are not covered with the hard mask  18   a  are etched continuously and sequentially.  
     [0075] First, as shown in FIG. 4F, the region of the second conductive film  15 , which is exposed from the hard mask  18   a , is etched at the high temperature. Thus, the second conductive film  15  left under the hard mask  18   a  is used as an upper electrode  15   a  of the capacitor Q. The etching of the second conductive film  15  is carried out by using the IPC plasma etching equipment. For example, the etching is carried out by putting the silicon substrate  1  on the stage in the reaction chamber, introducing HBr and O 2  into the reaction chamber as the etching gas at flow rates of 10 ml/min. and 40 ml/min. respectively, applying the source power of 800 W at 13.56 MHz, applying the bias power of 700 W at 400 kHz, setting a degree of vacuum in the reaction chamber to 0.4 Pa, and setting the stage temperature to 300 to 500° C., e.g., 400° C.  
     [0076] Then, as shown in FIG. 4G, the region of the ferroelectric film  14 , which is exposed from the hard mask  18   a  and the upper electrode  15   a , is etched in the state that the stage temperature is set lower than that in the etching of the second conductive film  15 . Thus, the ferroelectric film  14  left under the hard mask  18   a  is used as a dielectric film  14   a  of the capacitor Q. The etching of the ferroelectric film  14  may be carried out in the reaction chamber of the same IPC plasma etching equipment as the etching of the second conductive film  15  or may be carried out by using another IPC plasma etching equipment. As the etching conditions, for example, Cl 2 , Ar, O 2  and CF 4  are introduced into the reaction chamber as the etching gas at flow rates of 10 ml/min., 40 ml/min., 10 ml/min., and 12 ml/min. respectively, the source power of 13.56 MHz is set to 1400 W, the bias power of 400 kHz is set to 800 W, a degree of vacuum in the reaction chamber is set to 0.7 Pa, and the stage temperature is set within the range from the atmospheric temperature to below 300° C., e.g., 25° C. According to such conditions, generation of residue of the ferroelectric film  14  due to the microloading effect is prevented.  
     [0077] Further, as shown in FIG. 4H, the region of the first conductive film  13 , which is not covered with the hard mask  18   a , is etched in the state that the stage temperature is increased higher than that in the etching of the ferroelectric film  14 . Thus, the first conductive film  13  left under the hard mask  18   a  is used as a lower electrode  13   a  of the capacitor Q. The etching of the first conductive film  13  is carried out in the reaction chamber of the same IPC plasma etching equipment as the etching of the second conductive film  15 . The etching conditions are given such that, for example, HBr and O 2  are introduced into the reaction chamber as the etching gas at flow rates of 10 ml/min. and 40 ml/min. respectively, the source power of 13.56 MHz is set to 800 W, the bias power 400 kHz is set to of 700 W, a degree of vacuum in the reaction chamber is set to 0.4 Pa, and the stage temperature is set within the range of 300° C. to 500° C., e.g., 400° C.  
     [0078] After the etching of the first conductive film  13  is ended, the over-etching is carried out by about 60% in time.  
     [0079] In this case, a pressure in the atmosphere in which the first conductive film  13  and the second conductive film  15  are etched is set lower than that in the atmosphere in which the ferroelectric film  14  is etched.  
     [0080] As a result, the step of patterning the capacitor Q consisting of the lower electrode  13   a , the dielectric film  14   a , and the upper electrode  15   a  is ended. In this case, changes of the substrate temperature in respective etching steps of the second conductive film  15 , the ferroelectric film  14 , and the first conductive film  13  are shown in FIG. 5.  
     [0081] One lower electrode  13   a  is connected electrically to the first n-type impurity diffusion region  5   a  via the first conductive plug  11   a  over one p-well  1   a , while the other lower electrode  13   a  is connected electrically to the third n-type impurity diffusion region  5   c  via the second conductive plug  11   c . Also, a taper angle θ of the side surfaces of the capacitor Q is about 80 degree.  
     [0082] Then, the hard mask  18   a  is removed by the wet etching or the dry etching. As the etchant of the wet etching applied to the hard mask  18   a  made of titanium nitride, a mixed solution consisting of hydrogen peroxide and ammonia, for example, is employed.  
     [0083] In this case, when the upper portion of the hard mask is formed of silicon oxide, the first interlayer insulating film  8  is etched to remove the silicon oxide and thus a recess is formed in the region between the capacitors Q. However, in the present embodiment, since the hard mask is not formed of the silicon oxide, such problem is not caused.  
     [0084] Then, in order to recover the ferroelectric film  14  from the damage caused by the etching, the recover annealing is executed. The recover annealing in this case is executed at the substrate temperature of 650° C. for 60 minute in the oxygen atmosphere, for example.  
     [0085] Then, as shown in FIG. 4I, alumina of 50 nm thickness is formed as a capacitor protection insulating film  19  on the first interlayer insulating film  8  and the capacitor Q by the sputter. Then, the capacitor Q is annealed at 650° C. for 60 minute in the oxygen atmosphere. The capacitor protection insulating film  19  protects the capacitor Q from the process damage.  
     [0086] Then, a silicon oxide (SiO 2 ) film of about 1.0 μm thickness is formed as a second interlayer insulating film  20  on the capacitor protection insulating film  19  by the plasma CVD method using the TEOS gas. Then, an upper surface of the second interlayer insulating film  20  is planarized by the CMP method. In this example, a remaining film thickness of the second interlayer insulating film  20  after CMP is set to about 300 nm on the upper electrode  15   a  of the capacitor Q.  
     [0087] Next, steps required until a structure shown in FIG. 4J is formed is explained hereunder.  
     [0088] First, the second interlayer insulating film  20 , the capacitor protection insulating film  19 , and the cover insulating film  7  are etched by using a resist mask (not shown). Thus, a hole  20   a  is formed on the second n-type impurity diffusion region  5   b.    
     [0089] Then, a Ti film of 30 nm thickness and a TiN film of 50 nm thickness are formed sequentially as a glue film in the hole  20   a  and on the second interlayer insulating film  20  by the sputter method. Then, a W film is grown on the glue film by the CVD method to bury perfectly the inside of the hole  20   a.    
     [0090] Then, the W film, the TiN film, and the Ti film are polished by the CMP method to remove from the upper surface of the second interlayer insulating film  20 . Then, the W film and the glue film left in the hole  20   a  is used as a third conductive plug  21 . This third conductive plug  21  is connected electrically to the second n-type impurity diffusion region  5   a.    
     [0091] Next, steps required until a structure shown in FIG. 4K is formed are explained hereunder.  
     [0092] First, a SiON film is formed as a second oxidation preventing film (not shown) on the third conductive plug  21  and the second interlayer insulating film  20  by the CVD method. Then, the second oxidation preventing film (not shown), the second interlayer insulating film  20 , and the capacitor protection insulating film  19  are patterned by the photolithography method. Thus, contact holes  20   b  are formed on the upper electrode  15   a  of the capacitor Q.  
     [0093] The capacitor Q that is subjected to the damage caused by forming the contact holes  20   b  is recovered by the annealing. This annealing is executed at the temperature of 550° C. for 60 minute in the oxygen atmosphere, for example.  
     [0094] Then, the oxidation preventing film formed on the second interlayer insulating film  20  is removed by the etching-back, and also a surface of the third conductive plug  21  is exposed.  
     [0095] Then, a metal film is formed in the contact holes  20   b  on the upper electrodes  15   a  of the capacitors Q and on the second interlayer insulating film  20 . Then, first-layer metal wirings  22   a , which are connected the upper electrodes  15   a  via the contact holes  20   b , and a conductive pad  22   b , which is connected to the third conductive plug  21 , are formed by patterning the metal film. As the layered metal film, a multi-layered structure constructed by forming sequentially a Ti film of 60 nm thickness, a TiN film of 30 nm thickness, an Al—Cu film of 400 nm thickness, a Ti film of 5 nm thickness, and a TiN film of 70 nm thickness, for example, is employed.  
     [0096] In this case, as the method of patterning the metal film, the method of forming a reflection preventing film on the metal film, then coating resist on the reflection preventing film, then forming resist patterns having a wiring shape, etc. by exposing/developing the resist, and then etching the reflection preventing film and the metal film by using the resist patterns is employed.  
     [0097] Then, a third interlayer insulating film  23  is formed on the second interlayer insulating film  20 , the first-layer metal wirings  22   a , and the conductive pad  22   b . Then, a hole  23   a  is formed on the conductive pad  22   b  by patterning the third interlayer insulating film  23 . Then, a fourth conductive plug  24  made of the TiN film and the W film sequentially from the bottom is formed in the hole  23   a.    
     [0098] Then, a metal film is formed on the third interlayer insulating film  23 . Then, a bit line  25  connected to the fourth conductive plug  24  is formed by patterning this metal film by means of the photolithography method. The bit line  25  is connected electrically to the second n-type impurity diffusion region  5   b  via the fourth conductive plug  24 , the conductive pad  22   b , and the third conductive plug  21 . Subsequently to this, an insulating film for covering the second-layer wiring layer, etc. are formed. But their details will be omitted herein.  
     [0099] In the above embodiment, as shown in FIG. 5, the substrate temperature applied to the etching of the second conductive film  15  by using the hard masks  18   a  is set to the high temperature of more than 300° C. but less than 500° C. The substrate temperature applied to the etching of the ferroelectric film  14  by using the hard masks  18   a  is set to the low temperature of more than the atmospheric temperature but below 300° C. The substrate temperature applied to the etching of the first conductive film  13  by using the hard masks  18   a  is set to the high temperature of more than 300° C. but less than 500° C.  
     [0100] Since the oxygen gas is added to the etching gas in all etching times, the etching resistance of the hard masks  18   a  can be enhanced and also the selective etching ratios of the films  13 ,  14 ,  15  to the hard masks  18   a  is increased. For example, in the above etching conditions for forming the capacitor Q, the selective etching ratios of the first conductive film  13  and the second conductive film  15  to the TiN hard masks  18   a  become infinity respectively, and thus the hard masks  18   a  are seldom etched. Then, in the above etching conditions for forming the capacitor Q, the selective etching ratio of the PZT ferroelectric film  14  to the TiN hard masks  18   a  becomes about 2, and thus the hard masks  18   a  are never eliminated at the etching time of the ferroelectric film  14 .  
     [0101] Also, when the stage temperature is lowered at the time of etching of the ferroelectric film  14 , the microloading effect is difficult to occur and thus the etching residue of the ferroelectric substance is not generated around the capacitors Q.  
     [0102]FIG. 6 is a side view showing the capacitor that was formed actually by forming the hard masks  18   a  made of TiN and having a thickness of 300 nm on the second conductive film  15 , and then patterning the second conductive film  15 , the ferroelectric film  14 , and the first conductive film  13  under the above etching conditions. As shown in FIG. 6, the etching residue shown in FIG. 2D has not been generated on the first interlayer insulating film  8  around the capacitors Q.  
     [0103] In this case, FIG. 6 is depicted based on the microphotograph that picks up the image of the side surface of the capacitor, which was formed actually under the above etching conditions. In FIG. 6, edge portions of the hard mask  18   a  are thinner than the center portion thereof since they are etched in etching the ferroelectric film  14 .  
     [0104] By the way, in the step of forming the dielectric film  14   a  of the capacitor Q, since the ferroelectric film  14  is etched at the low temperature, a taper angle of the side surface of the dielectric film  14   a  does not become so steep. However, the side surface of the dielectric film  14   a  is etched during when the etching of the first conductive film  13  and in addition the over-etching of the first conductive film  13  are carried out at the high temperature respectively. Thus, finally the taper angle of the side surface of the capacitor Q containing the side surface of the dielectric film  14   a  becomes large and sharp.  
     [0105] Meanwhile, in the above embodiment, the stage temperature used in the etching of the second conductive film  15  is set to 300 to 500° C. But such etching may be carried out at the low temperature in the range of more than the atmospheric temperature but below 300° C. This is because, in the etching of the second conductive film  15  that is the initial stage of the capacitor Q forming step, the reaction product is hardly adhered onto the side surface of the upper electrode  15   a  and thus the taper angle of the side surface of the upper electrode  15   a  becomes large. In addition, in the step of forming the lower electrode  13   a , since the first conductive film  13  is etched at the high temperature, the portion of the upper electrode  15   a  extruded from the hard mask  18   a  is etched simultaneously at that time. Thus, the final taper angle of the side surface of the capacitor Q become steep.  
     [0106] The etching conditions of the second conductive film  15  when 25° C. is selected as the atmospheric temperature are given such that, for example, Cl 2 , Ar, and O 2  are introduced into the reaction chamber as the etching gas at flow rates of 10 ml/min., 40 ml/min., and 10 ml/min. respectively, the source power of 13.56 MHz is set to 1400 W, the bias power of 400 kHz is set to 800 W, and a degree of vacuum in the reaction chamber is set to 0.7 Pa.  
     [0107] In the meanwhile, as the method of executing the etching in two temperature ranges, any one of the method of executing the etching in one reaction chamber  31  by executing two types of temperature control, as shown in FIG. 7A, and the method of executing the etching by controlling separately the temperatures of wafer stages  41   a ,  41   b  in two reaction chambers  41 ,  42 , as shown in FIG. 7B, may be employed.  
     [0108] In case two types of temperature control is to be executed in the reaction chamber  31  of one etching equipment, the wafer stage  32  with a heating/cooling mechanism  33  may be employed or a lamp heating mechanism (not shown) may be provided, in order to implement two types of temperature control.  
     [0109] Also, in case the ferroelectric film  14  and the first metal film  13  are to be etched separately in respective reaction chambers  41 ,  42  of two etching equipments, the etching equipment in which two reaction chambers  41 ,  42  or more are connected via a vacuum transferring chamber  43  may be employed or two stand-alone equipments may be employed.  
     [0110] As described above, according to the present invention, in the step of forming the capacitor over the substrate, the substrate temperature at the time of etching the ferroelectric film is set lower than the substrate temperature at the time of etching the first conductive film when the first conductive film constituting the capacitor lower electrode, the ferroelectric film constituting the capacitor dielectric film, and the second conductive film constituting the capacitor upper electrode are to be etched sequentially by using the same hard masks. Therefore, the microloading effect is hard to occur when the ferroelectric film is etched by using the hard masks, and thus generation of the etching residue of the ferroelectric film can be prevented.