Patent Publication Number: US-7907015-B2

Title: Circuit for compensation of leakage current-induced offset in a single-ended op-amp

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of application Ser. No. 61/017,002 filed Dec. 27, 2007 which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to an electronic device including a operational amplifier. More specifically the present invention relates to an offset compensation circuit for Miller compensated single-ended operational amplifiers. 
     One of the most common architectures for integrated operational amplifiers (op-amp) is a single-ended two stage operational amplifier. Single-ended two (or more) stage op-amps need Miller compensation for stabilizing the op-amps. A Miller capacitance is coupled across the second stage from the op-amp output to an output of the first stage.  FIG. 1(   a ) shows a conventional Miller-compensated single-ended op-amp, with a simplified circuit diagram of this Miller compensation scheme being shown in  FIG. 1(   b ). The first stage ST 1  is a differential input stage having a transconductance gm. The second stage is coupled to a first output node of the differential input stage. In order to prevent the op-amp from oscillating or to achieve a specific settling behavior, a Miller capacitance C M  is coupled between the output node Vout of the second stage ST 2  and the output node V 1  of the differential amplifier input stage ST 1 . An integrated circuit including such an op-amp can be processed (i.e. manufactured) in a specific technology or process. Some processes offer capacitances consisting of two layers of polysilicon (i.e. poly-poly capacitance). These capacitances have good linearity, i.e. the capacitance with respect to the voltage across the capacitance is substantially constant, and only little parasitic effects, as for example parasitic diodes from a polysilicon layer to substrate or the like. However, other technologies do not provide poly-poly capacitors. Therefore, other layers must be used for capacitors. A typical choice is an n-well-poly capacitance consisting of an n-well layer (or region), which is an n-doped area in a p-substrate. Above the n-well region, a poly layer is arranged so as to form the two layer n-well-poly capacitance. However, this kind of capacitance is highly non-linear. Further, the n-well area is buried in the p-substrate and provides undesired parasitic elements, in particular a backward biased parasitic diode from the n-doped region to the p-substrate. The parasitic diode has a leakage current which is proportional to the diode area which is proportional to the capacitance value. The leakage current is drawn from the output node of the differential input stage. In order to compensate for the leakage current one branch of the differential input stage has to provide more current than the other branch, which results in an offset of the differential input stage, i.e. the op-amp has an offset. For a differential input stage having a transconductance gm, the offset voltage amounts to Voff=Ileak/gm, wherein Ileak is the leakage current provided by the Miller capacitance. As the leakage current depends on the area of the Miller capacitance, Voff=αC/gm=α/GBW, wherein α is technology dependent factor and GBW the gain-bandwidth product of the op-amp. Therefore, single-ended op-amps with n-well-poly capacitances as Miller compensation have an offset, which depends on the gain-bandwidth product GBW, temperature and the technology. The offset voltage Voff can hardly be removed by adapting the design of the op-amp (i.e. by dimensioning the components of the op-amp) as the GBW is given by the specification and can not be changed. Calibrating the op-amp is also almost impossible as the offset voltage is exponentially dependent on temperature. These considerations apply equally to a wide range of different op-amp architectures, such as nested or multipath Miller compensation op-amps, or so called Ahuja-compensation as described by B. K. Ahuja in “An improved frequency compensation technique for CMOS operational amplifiers, IEEE Journal of Solid-State Circuits, Volume 18, Issue 6, December 1983, pp. 629-633”. 
     SUMMARY OF THE INVENTION 
     It is a general object of the present invention to provide an offset compensation circuit and principle that overcomes the drawbacks of a leakage current induced by a component used for op-amp transfer function compensation. 
     This and other objects and features are provided, in accordance with an aspect of the present invention provides an electronic device including an operational amplifier, with the operational amplifier comprising a amplifier input stage coupled with a first output node to an amplifier output stage. Preferably, the amplifier input stage can be differential, but also other architectures for the input stage can be used. A compensation capacitance is provided, which is connected between an output node of the amplifier output stage and the first output node of the amplifier input stage, thereby operating as a compensator for stabilizing the operational amplifier. The compensation capacitance provides a parasitic diode drawing a first leakage current from the first output node of the amplifier input stage. A leakage current compensation circuit is coupled to the first output node of the amplifier input stage and coupled to a second output node of the amplifier input stage for drawing a first current from the first output node and a second current from the second output node. Further, the leakage current compensation circuit is adapted such that the second current is greater than the first current by an amount corresponding to the first leakage current. The operational amplifier has a input stage connected to the amplifier output stage by its first output node. A compensation capacitance, which can be a Miller capacitance, is then connected between the first output node of the input stage and the output node of the output stage of the amplifier. The compensation capacitance has the effect of stabilizing the operational amplifier by acting as a compensator, which prevents the operational amplifier from oscillating or can achieve a specific settling behavior. In fact, the compensation capacitance has a component that acts as a parasitic diode, which draws a first leakage current from the amplifier at its first output node. A circuit for compensating leakage current is then connected between the first input node of the amplifier input stage and a second output node of the differential amplifier input stage. This leakage current compensation circuit draws a first current from the first output node and also draws a second current from the second output node of the amplifier input stage. The difference between the second current and the first current is then made equal to the first leakage current, by adapting the leakage current compensation circuit accordingly. In this way, the first and second currents drawn by the leakage current compensation circuit compensates the first leakage current and the influences of both currents on the operational amplifier offset are cancelled out. A component of the offset of the operational amplifier is then cancelled, which is normally difficult to cancel. 
     The leakage current compensation circuit may comprise a diode element having a second leakage current which is a factor k smaller than the first leakage current and a first current mirror for amplifying the second leakage current by a factor k. The first current mirror amplifies the second leakage current from the diode element by k so that the second leakage current multiplied by a factor k by the first current mirror then compensates the first leakage current. 
     Advantageously, the diode element is formed by use of the same layers, which are used for the compensation capacitance and which include the parasitic diode. The diode element can also be implemented as a parasitic diode. The leakage current produced by the diode element is then subject to the same physical parameters, as for example temperature, as the parasitic diode of the compensation capacitance. Accordingly, the compensation of the leakage current becomes independent from parameters like temperature or internal voltage levels, and it becomes more resistant to parameter variations due to production spread. 
     The compensation capacitance can comprise two capacitors coupled in an anti-parallel arrangement for compensating a nonlinearity of a single capacitor. The two capacitors can be, for example, high density n-well-poly capacitors. Coupling the two capacitors in an antiparallel arrangement reduces the non-linearity of such n-well-poly capacitors, especially for a rail to rail output voltage. The parasitic diode of the compensation capacitance is then connected to the output of the transconductance gm and is provided between the well and the substrate 
     In one aspect of the invention, the first current mirror having a factor k is coupled to the first output node of the amplifier input stage and the leakage current compensation circuit further comprises a second current mirror having a factor k coupled to the second output node of the amplifier input stage. The diode element is then coupled to the first current mirror so as to reduce the first current by an amount corresponding to the first leakage current. The first current mirror sinks current from the first output node of the amplifier input stage and the second current mirror sinks current from the other side (the second output node) of the input stage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Further advantages and characteristics ensue from the description below of a preferred embodiment, with reference to the accompanying drawings, in which: 
         FIG. 1(   a ) is a simplified circuit diagram of a conventional Miller-compensated single-ended operational amplifier; 
         FIG. 1(   b ) is a simplified circuit diagram of a conventional Miller compensation scheme; and 
         FIG. 2  is a simplified circuit diagram of an electronic device including a single-ended operational amplifier according to the invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 2  shows a single-ended operational amplifier according to one aspect of the invention. The differential amplifier has a differential input stage provided with a node N 1 , which receives a current I 1  from an input current source, and is formed of a differential pair of PMOS transistors M 1  and M 2  having interconnected source terminals connected at the node N 1 . Gate terminals of the transistors M 1  and M 2  form the differential inputs of the amplifier. The drain terminal of the transistor M 1  is connected to the drain terminal of a diode-connected NMOS transistor M 3  and the drain terminal of the transistor M 2  is connected to a further NMOS transistor M 4 . An interconnection of the drain terminals of the transistors M 2  and M 4  forms a first output node V 1  of the differential amplifier input stage and an interconnection of the drain terminals of the transistors M 1  and M 3  forms a second output node V 3  of the differential amplifier input stage. The transistors M 3  and M 4  have interconnected gate terminals and source terminals both connected to ground. The first output node V 1  of the differential input stage is connected to the gate terminal of an NMOS transistor M 5 , which provides the amplifier output stage, along with a current source I 0 . The drain terminal of the transistor M 5  is connected to an amplifier output node Vout, as well as to the current source I 0 , with the source terminal of the transistor M 5  being connected to ground. A compensation capacitance circuit C M  is connected between the first output node V 1  of the differential input stage of the amplifier and the output node Vout of the amplifier output stage. The compensation capacitance circuit C M  is a so-called Miller capacitance and comprises an anti-parallel arrangement of capacitors C 1  and C 2 , which compensate for the non-linearity of a single capacitance. In other words, the capacitors C 1  and C 2  are connected in parallel in an anti-parallel configuration between the output node V 1  of the differential input stage and the amplifier output node Vout. In this example, the capacitors C 1  and C 2  are n-well poly capacitors. For such an anti-parallel arrangement of n-well polycapacitors a parasitic diode is always provided between the well and the substrate, represented here by the diode D connected between the differential stage output node V 1  and the substrate connection SUB. This leads to a leakage current from the compensation capacitance circuit C M , as explained with reference to  FIG. 1 . 
     A current leakage compensation circuit is provided for compensating for leakage current Ileak 1  that occurs from the compensation capacitance circuit C M . The first part of the current leakage compensation circuit is coupled to the first output node V 1  of the amplifier&#39;s differential input stage and is formed of a current mirror arrangement of two NMOS transistors M 6  and M 7 , as well as a diode D 2  connected to a node V 2  interconnecting the gate terminals of the transistors M 6  and M 7  and also to the substrate connection SUB. The drain terminal of the transistor M 7  is connected to the first output node V 1  of the input stage, with the transistor M 6  being diode-connected and having its drain terminal connected to a current source I 2 . Source terminals of the transistors M 6  and M 7  are both connected to ground. A second part of the current leakage compensation circuit is connected to the second output node V 3  of the differential input stage of the amplifier and is also formed of a current mirror arrangement of two NMOS transistors M 8  and M 9 . The drain terminal of the transistor M 9  is connected to the second output V 3  of the input stage and the transistor M 8  is diode-connected with its drain terminal being connected to a current source I 2 ′. Source terminals of the transistors M 8  and M 9  are connected to ground. Current mirror transistors M 6 , M 7 , M 8  and M 9  are configured such that the transistors M 7  and M 9  have an area a factor k times the transistors M 6  and M 8 . 
     In operation of the operational amplifier, the leakage current Ileak from the compensation capacitance circuit C M , including the anti-parallel arrangement of the capacitors C 1  and C 2 , flows through the diode D, as explained with reference to  FIG. 1 . The current mirror formed by the transistors M 6  and M 7  sinks an amount of current k*I 2  from the first output node V 1  of the differential input stage, under the condition that K*I 2 &lt;I 1 /2. By symmetry, this means that the current mirror formed by the transistors M 8  and M 9  also sinks an amount of current k*I 2  from the second output node V 3  on the other side of the input stage. At the same time, the diode D 2  sinks a leakage current Ileak 2  from the node V 2 . This means that the total current of the transistor M 7  (the total current drawn from the first output node V 1  of the input stage) is
 
 k *( I 2 −I leak2)=15  (1)
 
     under the condition that Ileak 2 &lt;I 2 . If the parasitic diode D is k times the size of the diode D 2 , then
 
V2=V1  (2)
 
and
 
 a·k*I leak2 =I leak  (3).
 
     In other words, the leakage current Ileak 2  from the diode D 2  is k times less than the leakage current Ileak from the parasitic diode D and is amplified by the current mirror M 6 , M 7  by a factor of k. V 2  can be made equal to V 1  if the transistors M 5  and M 6  as well as the current sources  10  and  12  are matched. As a result, the currents loading the input stage are
 
 I 3 =k*I 2  (4)
 
and
 
 I 4 =I 5 +I leak=k*I2 =I 3  (5),
 
     where I 4  is the current at the first output V 1  of the input stage and I 3  is the current at the second output V 3  of the input stage. So I 3  is greater than I 5  by an amount equal to the leakage current Ileak from the parasitic diode D. Since both currents I 3  and I 4  are symmetrical, the leakage current induced offset Ileak from the compensation capacitance circuit C M  is cancelled. 
     In an alternative embodiment, instead of connecting the diode D 2  to the node V 2 , it is also possible to achieve compensation of the leakage current Ileak by connecting the diode to the second output node V 3  of the input stage. However, this configuration increases the capacitance at the node V 3 , which may decrease the stability of the operational amplifier (whereas a capacitance at the node V 2  in the current mirror arrangement of transistors M 6  and M 7  does not affect the main feedback loop). Furthermore, using a current mirror with an amplification factor k&gt;1 means that the area of the diode D 2  is k times smaller than the parasitic diode D when the diode D 2  is connected to the node V 2 . However, if the diode D 2  is connected to V 3 , it must have the same area as the parasitic diode D. 
     In an integrated circuit, the physical layers used for the diode D and the diode D 2  can be the same. This allows the physical properties of the diodes to be matched to a large extent. The temperature behavior or the voltage dependence of the diodes may then qualitatively similar. The compensation mechanism is the substantially independent from other parameters and will provide good performance over a large parameter range. 
     The present invention is also applicable and advantageous for operational amplifiers using the Ahuja compensation cited in hereinabove. With an Ahuja compensation instead of a Miller compensation, it is possible to use a single capacitor. The aspects of the present invention set out hereinabove can equally be applied to this single capacitor. 
     Although the invention has been described hereinabove with reference to a specific embodiment, it is not limited to this embodiment and no doubt further alternatives will occur to the skilled person that lie within the scope of the invention as claimed. For example, although a specific operational amplifier circuit has been described above, the invention can also be implemented in other types of operational amplifier technology, e.g. folded-cascode, telescopic cascode, N/P input differential pair, and N/P output transistor, to name but a few. 
     Although the present invention has been described with reference to a specific embodiment, it is not limited to this embodiment and no doubt alternatives will occur to the skilled person that lie within the scope of the invention as claimed.