Patent Publication Number: US-2021185261-A1

Title: Imaging device and imaging method

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to an imaging device and an imaging method. 
     2. Description of the Related Art 
     In the related art, the luminance of an image output from an imaging device has been adjusted. The luminance is adjusted in accordance with, for example, the illuminance of a subject or the like. 
     The luminance can be adjusted by, for example, adjusting the amount of light that is incident on an imaging element. The amount of incident light can be adjusted by, for example, adjusting the diaphragm of a lens, adjusting the exposure time of a shutter, reducing light by using a neutral density (ND) filter, or the like. 
     The luminance can also be adjusted by, for example, adjusting the sensitivity of the imaging element. Adjustment of the sensitivity of the imaging element adjusts the amount of positive or negative charge to be read from the imaging element. The adjustment of the amount of charge adjusts the luminance of an output image. Japanese Unexamined Patent Application Publication No. 2007-104114 and Japanese Unexamined Patent Application Publication No. 2017-135704 describe an imaging element with an adjustable sensitivity. 
     In the imaging element in Japanese Unexamined Patent Application Publication No. 2007-104114 and Japanese Unexamined Patent Application Publication No. 2017-135704, a voltage is applied to a photoelectric conversion layer. By controlling the time range for the voltage application, the sensitivity of the imaging element is adjusted. 
     SUMMARY 
     In the related art, obtaining a high sensitivity while maintaining an image quality has not been sufficiently studied. The present disclosure provides a technique suitable for obtaining a high sensitivity while maintaining an image quality. 
     In one general aspect, the techniques disclosed here feature an imaging device including a pixel array. A first period, a third period, and a second period appear in this order in a first frame. During the first period, pixel signal readout is performed on a first row in the pixel array. During the second period, pixel signal readout is performed on a second row in the pixel array. Each of the first period and the second period is a high-sensitivity exposure period. The third period is a low-sensitivity exposure period. 
     The technique according to the present disclosure is suitable for obtaining a high sensitivity while maintaining an image quality. 
     It should be noted that general or specific embodiments may be implemented as a system, a method, an integrated circuit, a computer program, a storage medium, or any selective combination thereof. 
     Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically illustrates an imaging device; 
         FIG. 2  is a schematic cross-sectional view of a device structure of a unit pixel; 
         FIG. 3A  is a chart for describing the operation of the imaging device; 
         FIG. 3B  is an enlarged view of part of  FIG. 3A ; 
         FIG. 4  is a chart for describing control signals during a signal readout period; 
         FIG. 5A  is a chart for describing the operation of the imaging device; 
         FIG. 5B  is an enlarged view of part of  FIG. 5A ; 
         FIG. 6  illustrates a relationship between a voltage of a counter electrode and pixel signal readout; 
         FIG. 7  illustrates a relationship between the voltage of the counter electrode and pixel signal readout; 
         FIG. 8  illustrates a relationship between the voltage of the counter electrode and pixel signal readout; 
         FIG. 9  illustrates a relationship between a potential difference between a pixel electrode and the counter electrode and a standardized sensitivity; 
         FIG. 10  is a chart for describing the operation of the imaging device; 
         FIG. 11  is a chart for describing the operation of the imaging device; 
         FIG. 12  is a chart for describing the operation of the imaging device; 
         FIG. 13A  is a chart for describing the operation of the imaging device; 
         FIG. 13B  is an enlarged view of part of  FIG. 13A ; 
         FIG. 14  is a chart for describing the operation of the imaging device; 
         FIG. 15  schematically illustrates an imaging device; 
         FIG. 16A  is a chart for describing the operation of the imaging device; and 
         FIG. 16B  is a view including an enlarged view of part of  FIG. 16A . 
     
    
    
     DETAILED DESCRIPTION 
     Overview of Aspects of Present Disclosure 
     An imaging device according to a first aspect of the present disclosure is
         an imaging device including:   a pixel array,   in which a first period, a third period, and a second period appear in this order in a first frame,   in which, during the first period, pixel signal readout is performed on a first row in the pixel array,   in which, during the second period, pixel signal readout is performed on a second row in the pixel array,   in which each of the first period and the second period is a high-sensitivity exposure period, and   in which the third period is a low-sensitivity exposure period.       

     The technique according to the first aspect is suitable for obtaining a high sensitivity while maintaining an image quality. Note that no pixel signal readout may be performed on the rows in the pixel array during the third period. 
     According to a second aspect of the present disclosure, for example, in the imaging device according to the first aspect, a total period of the high-sensitivity exposure period is longer than or equal to a total period of the low-sensitivity exposure period in the first frame. 
     The technique according to the second aspect helps image capturing with a high sensitivity. 
     According to a third aspect of the present disclosure, for example, in the imaging device according to the first or second aspect, a fourth period, a sixth period, and a fifth period may appear in this order in a second frame, in which, during the fourth period, pixel signal readout is performed on a fourth row in the pixel array, in which, during the fifth period, pixel signal readout is performed on a fifth row in the pixel array, in which, during the sixth period, no pixel signal readout may be performed on the rows in the pixel array, in which each of the fourth period and the fifth period may be the low-sensitivity exposure period, and in which the sixth period may be the high-sensitivity exposure period. 
     The second frame according to the third aspect is suitable for image capturing with a low sensitivity. 
     According to a fourth aspect of the present disclosure, for example, the imaging device according to any one of the first to third aspects may further include a semiconductor substrate and a photoelectric converter. The photoelectric converter may include a photoelectric conversion layer, a first electrode, and a second electrode. The semiconductor substrate, the first electrode, the photoelectric conversion layer, and the second electrode may be stacked in this order. 
     The fourth aspect can form an imaging element with an easily adjustable sensitivity. 
     According to a fifth aspect of the present disclosure, for example, the imaging device according to the fourth aspect may have the following feature (i) and/or (ii): (i) the imaging device further includes a third electrode, the semiconductor substrate, the third electrode, the photoelectric conversion layer, and the second electrode are stacked in this order, and the imaging device controls the third electrode to have a different voltage during the high-sensitivity exposure period and during the low-sensitivity exposure period; and (ii) the imaging device controls the second electrode to have a different voltage during the high-sensitivity exposure period and during the low-sensitivity exposure period. 
     Control of the voltage(s) of the electrode(s) as in the fifth aspect enables adjustment of the sensitivity. 
     According to a sixth aspect of the present disclosure, for example, in the imaging device according to the fourth or fifth aspect, the imaging device may control a voltage of the second electrode to a first voltage during the high-sensitivity exposure period, the imaging device may perform first driving and second driving, the first driving using a first driving voltage as the first voltage, the second driving using a second driving voltage as the first voltage, and the first driving voltage and the second driving voltage may be different from each other. 
     The sixth aspect makes it easy to adjust the sensitivity. 
     According to a seventh aspect of the present disclosure, for example, the imaging device according to any one of the fourth to sixth aspects, may further include a third electrode, in which the semiconductor substrate, the third electrode, the photoelectric conversion layer, and the second electrode may be stacked in this order, in which the imaging device may control a voltage of the third electrode to a third voltage during the high-sensitivity exposure period, in which the imaging device may perform third driving and fourth driving, the third driving using a third driving voltage as the third voltage, the fourth driving using a fourth driving voltage as the third voltage, and in which the third driving voltage and the fourth driving voltage may be different from each other. 
     The seventh aspect makes it easy to adjust the sensitivity. 
     According to an eighth aspect of the present disclosure, for example, the imaging device according to any one of the first to third aspects may further include a semiconductor substrate and a photoelectric converter, in which the photoelectric converter may be an embedded photodiode that is embedded in the semiconductor substrate. 
     The eighth aspect can form an imaging element with an easily adjustable sensitivity. 
     According to a ninth aspect of the present disclosure, for example, the imaging device according to the eighth aspect may further include: a first transistor that resets the embedded photodiode; a charge accumulator that accumulates charge generated in the embedded photodiode; and a second transistor that transfers the charge from the embedded photodiode to the charge accumulator, in which the high-sensitivity exposure period may be a period from turning off of the first transistor until turning off of the second transistor, and in which the low-sensitivity exposure period may be a period from turning off of the second transistor until turning off of the first transistor. 
     The ninth aspect enables sensitivity adjustment on the basis of switching timing of the first transistor and the second transistor. 
     An imaging method according to a tenth aspect of the present disclosure is
         an imaging method using an imaging device including a pixel array   in which a first period, a third period, and a second period appear in this order in a first frame, the method including:   during the first period, performing pixel signal readout on a first row in the pixel array; and   during the second period, performing pixel signal readout on a second row in the pixel array,   in which each of the first period and the second period is a high-sensitivity exposure period, and   in which the third period is a low-sensitivity exposure period.       

     The technique according to the tenth aspect is suitable for obtaining a high sensitivity while maintaining an image quality. Note that no pixel signal readout may be performed on the rows in the pixel array during the third period. 
     An imaging device according to an eleventh aspect of the present disclosure includes:
         a signal line;   a plurality of pixels that generate pixel signals in accordance with amounts of incident light, respectively, and that sequentially output the pixel signals to the signal line; and   a voltage supply circuit that supplies a first voltage and a second voltage concurrently to each of the plurality of pixels, the first voltage and the second voltage being different from each other and being to be supplied alternately twice or more during a first frame period,   in which each of the plurality of pixels includes
           a photoelectric converter that converts light into an electric signal with a first sensitivity during a first period during which the first voltage is supplied and converts light into an electric signal with a second sensitivity during a second period during which the second voltage is supplied, the second sensitivity being higher than the first sensitivity, and   a first transistor that amplifies each of the electric signals and outputs a corresponding one of the pixel signals, and   
           in which the plurality of pixels output the pixel signals, respectively, to the signal line during the second period in the first frame period.       

     According to a twelfth aspect of the present disclosure, for example, in the imaging device according to the eleventh aspect, the plurality of pixels may not output the pixel signals, respectively, to the signal line during the first period in the first frame period. 
     According to a thirteenth aspect of the present disclosure, for example, in the imaging device according to the eleventh aspect, the photoelectric converter in each of the plurality of pixels may include a first electrode to be electrically connected to a gate of the first transistor, a second electrode facing the first electrode, and a photoelectric conversion layer between the first electrode and the second electrode, and in which the voltage supply circuit may alternately supply the first voltage and the second voltage to the second electrode in the photoelectric converter in each of the plurality of pixels. 
     According to a fourteenth aspect of the present disclosure, for example, in the imaging device according to the eleventh aspect, the photoelectric converter in each of the plurality of pixels may include a photoelectric conversion layer having a first surface and a second surface, the first surface and the second surface being opposite to each other, a first electrode located on the first surface, a third electrode located on the first surface, and a second electrode located on the second surface and facing the first electrode and the third electrode, in which the first electrode may be to be electrically connected to a gate of the first transistor, and in which the voltage supply circuit may alternately supply the first voltage and the second voltage to the third electrode in the photoelectric converter in each of the plurality of pixels. 
     According to a fifteenth aspect of the present disclosure, for example, in the imaging device according to the eleventh aspect, the photoelectric converter in each of the plurality of pixels may include a photodiode, in which each of the plurality of pixels may include a second transistor having one of a source and a drain to be electrically connected to the photodiode and the other of the source and the drain to be electrically connected to a gate of the first transistor, and a third transistor having one of a source and a drain to be electrically connected to the photodiode and the other of the source and the drain to be supplied with a predetermined voltage, and in which the voltage supply circuit may alternately supply the first voltage and the second voltage to a gate of the third transistor. 
     According to a sixteenth aspect of the present disclosure, for example, in the imaging device according to the fifteenth aspect, the voltage supply circuit may alternately supply a third voltage and a fourth voltage to a gate of the second transistor, the third voltage and the fourth voltage being different from each other. 
     According to a seventeenth aspect of the present disclosure, for example, in the imaging device according to any one of the eleventh to sixteenth aspects, a total duration of the second period in the first frame period may be longer than or equal to a total duration of the first period in the first frame period. 
     According to an eighteenth aspect of the present disclosure, for example, the imaging device according to any one of the eleventh to seventeenth aspects may further include: a first control circuit that causes the voltage supply circuit to supply the first voltage and the second voltage; and a second control circuit that causes the plurality of pixels to sequentially output the pixel signals, respectively, to the signal line. 
     According to a nineteenth aspect of the present disclosure is
         an imaging device including a pixel array,   in which a control mode of the imaging device includes a first mode in which a first frame is generated,   in which a duty ratio in the first mode is changed such that a state in which a first condition, a second condition, and a third condition are satisfied is maintained before and after the change.   The first frame herein is a frame in which a first period, a third period, and a second period appear in this order. Each of the first period and the second period is one of the high-sensitivity exposure period and the low-sensitivity exposure period. The third period is the other of the high-sensitivity exposure period and the low-sensitivity exposure period. The first condition is a condition that pixel signal readout is performed on a first row in the pixel array during the first period. The second condition is a condition that pixel signal readout is performed on a second row in the pixel array during the second period. The third condition is a condition that no pixel signal readout is performed in the rows in the pixel array during the third period. The duty ratio is a ratio of a total period of the high-sensitivity exposure period in the first frame to the first frame period.       

     The technique according to the nineteenth aspect is suitable for obtaining a high sensitivity while maintaining an image quality. The technique according to the nineteenth aspect is also suitable for obtaining a low sensitivity while maintaining the image quality. 
     According to a twentieth aspect of the present disclosure is
         an imaging method using an imaging device including a pixel array,   in which a control mode of the imaging device includes a first mode in which a first frame is generated, the method including:       

     changing a duty ratio in the first mode such that a state in which a first condition, a second condition, and a third condition are satisfied is maintained before and after the change.
         The first frame herein is a frame in which a first period, a third period, and a second period appear in this order. Each of the first period and the second period is one of the high-sensitivity exposure period and the low-sensitivity exposure period. The third period is the other of the high-sensitivity exposure period and the low-sensitivity exposure period. The first condition is a condition that pixel signal readout is performed on a first row in the pixel array during the first period. The second condition is a condition that pixel signal readout is performed on a second row in the pixel array during the second period. The third condition is a condition that no pixel signal readout is performed in the rows in the pixel array during the third period. The duty ratio is a ratio of a total period of the high-sensitivity exposure period in the first frame to the first frame period.       

     The technique according to the twentieth aspect is suitable for obtaining a high sensitivity while maintaining an image quality. The technique according to the twentieth aspect is also suitable for obtaining a low sensitivity while maintaining the image quality. 
     The term “high-sensitivity exposure period” and the term “low-sensitivity exposure period” are used herein. The high-sensitivity exposure period indicates a period during which a higher sensitivity is obtained than during the low-sensitivity exposure period. The low-sensitivity exposure period indicates a period during which a lower sensitivity is obtained than during the high-sensitivity exposure period. The sensitivity being low herein is a concept including the sensitivity being zero. The low-sensitivity exposure period is a concept including a period during which the sensitivity is zero. 
     Ordinals such as first, second, and third may be used herein. An element with an ordinal does not necessarily require the presence of an element of the same kind with a smaller ordinal. 
     Now, embodiments of the present disclosure will be described in detail with reference to the drawings. Note that the embodiments described below illustrate general or specific examples. Any numeric value, shape, material, structural element, arrangement and connection of structural elements, step, order of steps, and the like illustrated in the following embodiments are examples and do not intend to limit the present disclosure. Various embodiments described herein can be combined with each other without inconsistency. In addition, among structural elements in the following embodiments, those not described in the broadest independent claim are optional. Furthermore, in the following description, structural elements having substantially the same function are denoted by the same reference numerals and may not be repeatedly described. 
     First Embodiment 
     Circuit Configuration of Imaging Device 
       FIG. 1  illustrates an exemplary circuit configuration of an imaging device according to a first embodiment. An imaging device  100  illustrated in  FIG. 1  includes a pixel array PA including a plurality of unit pixels  10  that are arrayed two-dimensionally.  FIG. 1  schematically illustrates an example in which the unit pixels  10  are arranged in a matrix of two rows and two columns. It is needless to say that the number and arrangement of the unit pixels  10  in the imaging device  100  are not limited to those in the example illustrated in  FIG. 1 . 
     Each of the unit pixels  10  includes a photoelectric conversion section  13  and a signal detection circuit  14 . As will be described later with reference to a drawing, the photoelectric conversion section  13  includes a photoelectric conversion layer sandwiched between two electrodes facing each other and generates a signal by receiving incident light. The entirety of the photoelectric conversion section  13  does not need to be an element that is independent for each of the unit pixels  10 , and, for example, part of the photoelectric conversion section  13  may be formed across the plurality of unit pixels  10 . The signal detection circuit  14  is a circuit that detects the signal generated by the photoelectric conversion section  13 . In this example, the signal detection circuit  14  includes a signal detection transistor  24  and an address transistor  26 . Each of the signal detection transistor  24  and the address transistor  26  is typically a field-effect transistor (FET) and is an N-channel metal oxide semiconductor (MOS) transistor in this example. 
     As schematically illustrated in  FIG. 1 , a control terminal (gate in this example) of the signal detection transistor  24  has an electrical connection with the photoelectric conversion section  13 . Signal charge (holes or electrons) generated by the photoelectric conversion section  13  is accumulated in a charge accumulation section  41 . The charge accumulation section  41  spreads in a region including a region between the gate of the signal detection transistor  24  and the photoelectric conversion section  13 . The charge accumulation section  41  includes so-called floating diffusion. Details of the structure of the photoelectric conversion section  13  will be described later. 
     The imaging device  100  includes a driving section that drives the pixel array PA and acquires images at a plurality of timings. The driving section includes a voltage supply circuit  32 , a voltage supply circuit  35 , a reset voltage source  34 , a vertical scanning circuit  36 , column signal processing circuits  37 , a horizontal signal reading circuit  38 , and a pixel-driving-signal generating circuit  39 . 
     The photoelectric conversion section  13  in each of the unit pixels  10  further has a connection with a sensitivity control line  42 . In the configuration illustrated in  FIG. 1 , the sensitivity control line  42  is connected to the voltage supply circuit  32 . As will be described later in detail, the voltage supply circuit  32  supplies a voltage to a counter electrode  12  (see  FIG. 2 ), the voltage being different during a high-sensitivity exposure period and during a low-sensitivity exposure period. The voltage supplied to the counter electrode  12  may be different in frames. 
     As will be described later, the photoelectric conversion section  13  includes a pixel electrode  11  and a photoelectric conversion layer  15  in addition to the counter electrode  12 . In addition, in the configuration illustrated in  FIG. 1 , a shield electrode  17  has a connection with a sensitivity control line  45 . The sensitivity control line  45  is connected to the voltage supply circuit  35 . The voltage supply circuit  35  supplies a shield voltage to the shield electrode  17 . Typically, the shield electrode  17  and the pixel electrode  11  are electrically isolated from each other. In the example in  FIGS. 1 and 2 , the shield electrode  17  and the pixel electrode  11  are separated from each other. In this example, the shield electrode  17  and the pixel electrode  11  are in contact with a surface of the photoelectric conversion layer  15 , and the counter electrode  12  is in contact with the other surface of the photoelectric conversion layer  15 . 
     The shield voltage in the shield electrode  17  may be used to suppress crosstalk between the unit pixels  10 . For example, crosstalk may be suppressed by applying the shield voltage to the shield electrode  17 , the shield voltage being lower than a reset voltage Vr applied to the pixel electrode  11 . The shield voltage applied to the shield electrode  17  may be a negative voltage. 
     When viewed in the thickness direction of the pixel electrode  11 , that is, in a plan view, the shield electrode  17  may surround the pixel electrode  11 . More specifically, a plurality of through-holes may be provided in the shield electrode  17 , and each pixel electrode  11  may be included in a corresponding one of the through-holes. The shield electrode  17  may be a single electrode or may be constituted by a plurality of electrodes that are separated from one another. 
     Note that the sensitivity control line  45  and the voltage supply circuit  35  may be omitted, and the shield electrode  17  may be connected to ground of the imaging device  100 . Also in this manner, crosstalk may be suppressed. In addition, the shield electrode  17 , the sensitivity control line  45 , and the voltage supply circuit  35  may be omitted. The same applies to a second embodiment. 
     During “high-sensitivity exposure period” in the first embodiment, one of positive charge and negative charge (signal charge) generated through photoelectric conversion is accumulated in the charge accumulation section  41  with a relatively high sensitivity. That is, during “high-sensitivity exposure period”, light is converted into an electric signal with a relatively high sensitivity. In addition, during “low-sensitivity exposure period” in the first embodiment, one of positive charge and negative charge (signal charge) generated through photoelectric conversion is accumulated in the charge accumulation section  41  with a relatively low sensitivity. That is, during “low-sensitivity exposure period”, light is converted into an electric signal with a relatively low sensitivity. The sensitivity being low includes the sensitivity being zero. The same applies to the following second and third embodiments. 
     By controlling the potential of the counter electrode  12  with respect to the potential of the pixel electrode  11 , it is possible to collect, in the pixel electrode  11 , one of holes and electrons from hole-electron pairs generated in the photoelectric conversion layer  15  through photoelectric conversion. For example, in a case of using holes as signal charge, it is possible to selectively collect holes in the pixel electrode  11  by making the potential of the counter electrode  12  higher than that of the pixel electrode  11 . The amount of signal charge collected per unit time changes depending on the potential difference between the pixel electrode  11  and the counter electrode  12 . A case of using holes as signal charge will be described below. As a matter of course, electrons may also be used as signal charge. Each of the voltage supply circuit  32  and the voltage supply circuit  35  is not limited to a specific power source circuit and may be a circuit that generates a predetermined voltage or a circuit that converts a voltage supplied from another power source to a predetermined voltage. 
     Each of the unit pixels  10  has a connection with a power source line  40  that supplies a power source voltage VDD. As illustrated, an input terminal (typically, drain) of the signal detection transistor  24  is connected to the power source line  40 . By the power source line  40  serving as a source follower power source, the signal detection transistor  24  amplifies and outputs a signal generated by the photoelectric conversion section  13 . 
     An input terminal (drain in this example) of the address transistor  26  is connected to an output terminal (source in this example) of the signal detection transistor  24 . An output terminal (source in this example) of the address transistor  26  is connected to a vertical signal line  47 , which is one of a plurality of vertical signal lines  47  arranged for the respective columns of the pixel array PA. A control terminal (gate in this example) of the address transistor  26  is connected to an address control line  46 , and by controlling the potential of the address control line  46 , an output of the signal detection transistor  24  can be selectively read out to the corresponding vertical signal line  47 . 
     In the illustrated example, the address control line  46  is connected to the vertical scanning circuit (also referred to as “row scanning circuit”)  36 . By applying a predetermined voltage to the address control line  46 , the vertical scanning circuit  36  selects, in units of row, the plurality of unit pixels  10  arranged in each row. Thus, signal readout and reset of pixel electrodes  11 , which will be described later, are performed on the selected unit pixels  10 . 
     Furthermore, the pixel-driving-signal generating circuit  39  is connected to the vertical scanning circuit  36 . In the illustrated example, the pixel-driving-signal generating circuit  39  generates signals for driving the unit pixels  10  arranged in the respective rows of the pixel array PA. The generated pixel driving signals are supplied to the unit pixels  10  in the row selected by the vertical scanning circuit  36 . 
     The vertical signal lines  47  are main signal lines for transmitting pixel signals from the pixel array PA to peripheral circuits. The column signal processing circuits (also referred to as “row signal accumulating circuits”)  37  are connected to the vertical signal lines  47 . The column signal processing circuits  37  perform noise suppressing signal processing, analog-to-digital conversion (AD conversion), and the like. The noise suppressing signal processing is typified by correlated double sampling. As illustrated, the column signal processing circuits  37  are provided to correspond to the respective columns of the unit pixels  10  in the pixel array PA. The horizontal signal reading circuit (also referred to as “column scanning circuit”)  38  is connected to these column signal processing circuits  37 . The horizontal signal reading circuit  38  sequentially reads out signals from the plurality of column signal processing circuits  37  and outputs them to a horizontal common signal line  49 . 
     In the configuration illustrated in  FIG. 1 , each of the unit pixels  10  includes a reset transistor  28 . Similarly to the signal detection transistor  24  and the address transistor  26 , the reset transistor  28  may be, for example, an FET. The following description illustrates an example of applying an N-channel MOS transistor to the reset transistor  28  unless otherwise specified. As illustrated, the reset transistor  28  is connected between a reset voltage line  44  for supplying a reset voltage Vr and the charge accumulation section  41 . A control terminal (gate in this example) of the reset transistor  28  is connected to a reset control line  48 , and by controlling the potential of the reset control line  48 , the potential of the charge accumulation section  41  can be reset to the reset voltage Vr. In this example, the reset control line  48  is connected to the vertical scanning circuit  36 . Thus, by the vertical scanning circuit  36  applying a predetermined voltage to the reset control line  48 , the plurality of unit pixels  10  arranged in the respective rows can be reset in units of row. 
     In this example, the reset voltage line  44  for supplying the reset voltage Vr to the reset transistor  28  is connected to the reset voltage supply circuit (hereinafter simply referred to as “reset voltage source”)  34 . The reset voltage source  34  may have any configuration that can supply the predetermined reset voltage Vr to the reset voltage line  44  during the operation of the imaging device  100 , and is not limited to a specific power source circuit similarly to the voltage supply circuit  32  described above. Each of the voltage supply circuit  32 , the voltage supply circuit  35 , and the reset voltage source  34  may be part of a single voltage supply circuit or independent, separate voltage supply circuits. Note that the voltage supply circuit  32 , the voltage supply circuit  35 , and/or the reset voltage source  34  may be part of the vertical scanning circuit  36 . Alternatively, a sensitivity control voltage from the voltage supply circuit  32 , a sensitivity control voltage from the voltage supply circuit  35 , and/or the reset voltage Vr from the reset voltage source  34  may be supplied to the unit pixels  10  through the vertical scanning circuit  36 . 
     It is also possible to use the power source voltage VDD of the signal detection circuit  14  as the reset voltage Vr. In this case, a voltage supply circuit (not illustrated in  FIG. 1 ) that supplies the power source voltage to the unit pixels  10  and the reset voltage source  34  may be shared. In addition, since the power source line  40  and the reset voltage line  44  may be shared, wiring in the pixel array PA may be simplified. Note that the reset voltage Vr being a voltage different from the power source voltage VDD of the signal detection circuit  14  enables more flexible control of the imaging device  100 . 
     Device Structure of Unit Pixel 
       FIG. 2  schematically illustrates an exemplary device structure of a unit pixel  10 . In the structure illustrated in  FIG. 2 , the signal detection transistor  24 , the address transistor  26 , and the reset transistor  28  are formed on a semiconductor substrate  20 . The semiconductor substrate  20  is not limited to a substrate the entirety of which is a semiconductor. The semiconductor substrate  20  may also be an insulating substrate having a surface on which a semiconductor layer is formed and on which a sensitive region is to be formed. In this example, a P-type silicon (Si) substrate is used as the semiconductor substrate  20 . 
     The semiconductor substrate  20  includes impurity regions (N-type regions in this example)  26   s,    24   s,    24   d,    28   d,  and  28   s  and an element isolation region  20   t  for electric isolation between the unit pixels  10 . In this example, the element isolation region  20   t  is also provided between the impurity region  24   d  and the impurity region  28   d.  The element isolation region  20   t  is formed by, for example, implantation of acceptor ions under predetermined implantation conditions. 
     The impurity regions  26   s,    24   s,    24   d,    28   d,  and  28   s  are typically diffusion layers formed in the semiconductor substrate  20 . As schematically illustrated in  FIG. 2 , the signal detection transistor  24  includes the impurity region  24   s,  the impurity region  24   d,  and a gate electrode  24   g  (typically, a polysilicon electrode). The impurity region  24   s  serves as, for example, a source region of the signal detection transistor  24 . The impurity region  24   d  serves as, for example, a drain region of the signal detection transistor  24 . A channel region of the signal detection transistor  24  is formed between the impurity region  24   s  and the impurity region  24   d.    
     Similarly, the address transistor  26  includes the impurity region  26   s,  the impurity region  24   s,  and a gate electrode  26   g  (typically, a polysilicon electrode) connected to the address control line  46  (see  FIG. 1 ). In this example, the signal detection transistor  24  and the address transistor  26  are electrically connected to each other by sharing the impurity region  24   s.  The impurity region  26   s  serves as, for example, a source region of the address transistor  26 . The impurity region  26   s  has a connection with a vertical signal line  47  (see  FIG. 1 ) that is not illustrated in  FIG. 2 . The reset transistor  28  includes the impurity region  28   d,  the impurity region  28   s,  and a gate electrode  28   g  (typically, a polysilicon electrode) connected to the reset control line  48  (see  FIG. 1 ). The impurity region  28   s  serves as, for example, a source region of the reset transistor  28 . The impurity region  28   s  has a connection to the reset voltage line  44  (see  FIG. 1 ) that is not illustrated in  FIG. 2 . 
     On the semiconductor substrate  20 , an interlayer insulating layer  50  (typically, a silicon dioxide layer) is disposed to cover the signal detection transistor  24 , the address transistor  26 , and the reset transistor  28 . As illustrated, wiring layers  56  may be disposed in the interlayer insulating layer  50 . The wiring layers  56  are typically formed of a metal such as copper, and, for example, may partly include wiring such as the vertical signal line  47  described above. The number of insulating layers in the interlayer insulating layer  50  and the number of the wiring layers  56  disposed in the interlayer insulating layer  50  may be set to any numbers and are not limited to the numbers in the example illustrated in  FIG. 2 . 
     On the interlayer insulating layer  50 , the photoelectric conversion section  13  described above is disposed. In other words, in an embodiment of the present disclosure, the plurality of unit pixels  10  constituting the pixel array PA (see  FIG. 1 ) are formed on the semiconductor substrate  20 . The plurality of unit pixels  10  that are arrayed two-dimensionally on the semiconductor substrate  20  form a photosensitive region (pixel region). The distance between two adjacent unit pixels  10  (pixel pitch) may be, for example, about 2 μm. 
     The photoelectric conversion section  13  includes the pixel electrode  11 , the counter electrode  12 , and the photoelectric conversion layer  15  disposed therebetween. In this example, the counter electrode  12  and the photoelectric conversion layer  15  are formed across the plurality of unit pixels  10 . On the other hand, the pixel electrode  11  is provided for each of the unit pixels  10  and is spatially isolated from the pixel electrode  11  of another adjacent unit pixel  10  to be electrically isolated from the pixel electrode  11  of the other unit pixel  10 . 
     The counter electrode  12  is typically a transparent electrode formed of a transparent conductive material. The counter electrode  12  is disposed over a surface of the photoelectric conversion layer  15  on which light is incident. Thus, light passing though the counter electrode  12  is incident on the photoelectric conversion layer  15 . Note that the light detected by the imaging device  100  is not limited to light within the wavelength range of visible light (e.g., greater than or equal to 380 nm and less than or equal to 780 nm). The transparent material herein indicates a material that transmits at least part of light in a wavelength range to be detected, and does not need to transmit light in the entire wavelength range of visible light. Note that general electromagnetic waves including infrared rays and ultraviolet rays are expressed as “light” herein for convenience. For the counter electrode  12 , for example, it is possible to use a transparent conductive oxide (TCO) such as ITO, IZO, AZO, FTO, SnO 2 , TiO 2 , or ZnO 2 . 
     The photoelectric conversion layer  15  receives incident light and generates hole-electron pairs. The photoelectric conversion layer  15  is typically formed of an organic semiconductor material. Specific examples of the materials for forming the photoelectric conversion layer  15  will be described later. The photoelectric conversion layer  15  typically has a film-like shape. 
     As described with reference to  FIG. 1 , the counter electrode  12  has a connection with the sensitivity control line  42  connected to the voltage supply circuit  32 . The counter electrode  12  may be formed across the plurality of unit pixels  10 . In this manner, it is possible to apply a sensitivity control voltage with a desired value across the plurality of unit pixels  10  at once from the voltage supply circuit  32  through the sensitivity control line  42 . It is also possible to form the counter electrode  12  so as to apply the sensitivity control voltage according to the row in the pixel array PA at once. As long as the sensitivity control voltage with a desired value can be applied from the voltage supply circuit  32 , the counter electrode  12  may be provided to be isolated for each of the unit pixels  10 . Similarly, the photoelectric conversion layer  15  may be provided to be isolated for each of the unit pixels  10 . 
     By controlling the potential of the counter electrode  12  with respect to the potential of the pixel electrode  11 , it is possible to collect, in the pixel electrode  11 , one of holes and electrons from hole-electron pairs generated in the photoelectric conversion layer  15  through photoelectric conversion. For example, in a case of using holes as signal charge, it is possible to selectively collect holes in the pixel electrode  11  by making the potential of the counter electrode  12  higher than that of the pixel electrode  11 . The amount of signal charge collected per unit time changes depending on the potential difference between the pixel electrode  11  and the counter electrode  12 . A case of using holes as signal charge will be described below. As a matter of course, electrons may also be used as signal charge. 
     By an appropriate bias voltage being applied between the counter electrode  12  and the pixel electrode  11 , the pixel electrode  11  that faces the counter electrode  12  collects one of positive charge and negative charge generated through photoelectric conversion in the photoelectric conversion layer  15 . The pixel electrode  11  is formed of a metal such as aluminum or copper, a metal nitride, a polysilicon that becomes conductive by an impurity being doped thereto, or the like. 
     The pixel electrode  11  may be a light-blocking electrode. For example, by forming a TaN electrode with a thickness of 100 nm as the pixel electrode  11 , a sufficient light-blocking property can be obtained. By forming the pixel electrode  11  as a light-blocking electrode, light that passes through the photoelectric conversion layer  15  can be prevented from being incident on a channel region or an impurity region of a transistor (the signal detection transistor  24 , the address transistor  26 , and/or the reset transistor  28  in this example) formed on the semiconductor substrate  20 . A light-blocking film may be formed in the interlayer insulating layer  50  by using the wiring layers  56  described above. Prevention of light, by using such a light-blocking electrode or light-blocking film, from being incident on a channel region of a transistor formed on the semiconductor substrate  20  may prevent shift of transistor characteristics (e.g., variations in threshold voltage), for example. In addition, prevention of light from being incident on an impurity region formed in the semiconductor substrate  20  may prevent noise generated by unintended photoelectric conversion in the impurity region from being mixed. In this manner, prevention of light from being incident on the semiconductor substrate  20  contributes to improvement of reliability of the imaging device  100 . 
     As schematically illustrated in  FIG. 2 , the pixel electrode  11  is connected to the gate electrode  24   g  of the signal detection transistor  24  through a plug  52 , a wiring  53 , and a contact plug  54 . In other words, the gate of the signal detection transistor  24  has an electrical connection with the pixel electrode  11 . The plug  52  and the wiring  53  can be formed of, for example, a metal such as copper. The plug  52 , the wiring  53 , and the contact plug  54  form at least part of the charge accumulation section  41  (see  FIG. 1 ) between the signal detection transistor  24  and the photoelectric conversion section  13 . The wiring  53  may be part of the wiring layers  56 . In addition, the pixel electrode  11  is also connected to the impurity region  28   d  via the plug  52 , the wiring  53 , and a contact plug  55 . In the structure illustrated in  FIG. 2 , the gate electrode  24   g  of the signal detection transistor  24 , the plug  52 , the wiring  53 , the contact plugs  54  and  55 , and the impurity region  28   d  being one of the source region and the drain region of the reset transistor  28  serve as the charge accumulation section  41  that accumulates signal charge collected in the pixel electrode  11 . 
     Since the signal charge is collected in the pixel electrode  11 , a voltage in accordance with the amount of the signal charge accumulated in the charge accumulation section  41  is applied to the gate of the signal detection transistor  24 . The signal detection transistor  24  amplifies the voltage. The voltage amplified by the signal detection transistor  24  is selectively read as a signal voltage through the address transistor  26 . 
     Operation of Imaging Device 
     Referring to  FIGS. 3A and 3B , image acquisition using the high-sensitivity exposure period and the low-sensitivity exposure period will be described.  FIG. 3A  is a timing chart illustrating an example of the operation of the imaging device  100  according to the first embodiment.  FIG. 3B  is an enlarged view of part of  FIG. 3A . In  FIG. 3A , a graph (a) illustrates a timing of fall (or rise) of a vertical synchronization signal VD, a graph (b) illustrates a timing of fall (or rise) of a horizontal synchronization signal HD, a graph (c) illustrates an example of a temporal change of a voltage Vb to be applied from the voltage supply circuit  32  to the counter electrode  12  through the sensitivity control line  42 , and a graph (d) schematically illustrates a signal readout period, the high-sensitivity exposure period, and the low-sensitivity exposure period in the respective rows of the pixel array PA. The reference of the voltage Vb is, for example, a ground potential of the imaging device  100 . Although not illustrated in  FIGS. 3A and 3B , a predetermined voltage Vs is applied from the voltage supply circuit  35  to the shield electrode  17  through the sensitivity control line  45 . The voltage Vs is, for example, 0 V. 
     In the graph (d) in  FIG. 3A , the signal readout period in each row of the pixel array PA is illustrated in association with a sensitivity. Specifically, these are indicated by a horizontally long bar related to each row. A white rectangle in the upper half of each bar schematically represents the high-sensitivity exposure period in each row. A diagonally hatched part in the upper half of each bar schematically represents the low-sensitivity exposure period in each row. A dot-hatched rectangle in the lower half of each bar schematically represents the signal readout period in each row. 
     Now, an example of the operation of the imaging device  100  will be described. For simplicity, in this operation example, the number of rows of pixels included in the pixel array PA is 8 in total, from Row R 0  to Row R 7 . 
     To acquire an image, in each of the unit pixels  10  in the pixel array PA, the charge accumulation section  41  is reset, and a pixel signal accumulated therein after reset is read out. In the imaging device  100  according to this embodiment, during a single readout period, the pixel signal is read out, and the charge accumulation section  41  is reset in order to accumulate charge for the following frame period. For example, as illustrated in  FIG. 3A , on the basis of the vertical synchronization signal VD, signal readout starts for a plurality of pixels that belong to Row R 0 . Time t 0  is one of the start times. 
     As described above, the period represented by a single dot-hatched rectangle in the graph (d) in  FIG. 3A  is the signal readout period.  FIG. 4  illustrates an example of a timing chart of control signals during the signal readout period. In  FIG. 4 , a potential Vsel is the potential of the address control line  46  and may change between VL 1  being a low level and VH 1  being a high level. A potential Vrc is the potential of the reset control line  48  and may change between VL 2  being a low level and VH 2  being a high level. A potential VFD is the potential of the charge accumulation section  41 . The potential VFD is used as a pixel signal Vpsig when charge is accumulated in the charge accumulation section  41  and is used as a reset signal Vrsig when the charge accumulation section  41  is reset. 
     At time t 0 , the signal readout period starts. During the signal readout period, first, on the basis of the vertical synchronization signal VD, the potential Vsel of the address control line  46  in Row R 0  is switched from the low level to the high level. Thus, each address transistor  26  having the gate connected to the address control line  46  is turned on from the off state. Thus, the potential VFD of the charge accumulation section  41  is output to the corresponding vertical signal line  47 . Specifically, the pixel signal Vpsig is output to the vertical signal line  47 . The pixel signal Vpsig is a signal corresponding to the amount of charge accumulated in the charge accumulation section  41  during the previous one frame period. The pixel signal Vpsig is transmitted to the column signal processing circuit  37 . 
     In the example in  FIG. 3A , the signal readout period represented by the dot-hatched rectangle in the graph (d) includes a reset period in addition to the period for reading out the pixel signal Vpsig. The reset period is a period for resetting the potential of the charge accumulation section  41  of each of the unit pixels  10 . Specifically, in this example, after the above pixel readout has ended, the pixels that belong to Row R 0  are reset. Between the end of pixel readout and the reset of the pixels that belong to Row R 0 , for example, AD conversion of the pixel signal may be performed in the column signal processing circuit  37 . 
     The pixels that belong to Row R 0  are reset as follows. As illustrated in  FIG. 4 , the potential Vrc of the reset control line  48  in Row R 0  is switched from the low level to the high level. Thus, each reset transistor  28  having the gate connected to the reset control line  48  is turned on from the off state. Thus, the charge accumulation section  41  and the reset voltage line  44  are connected to each other, and the reset voltage Vr is supplied to the charge accumulation section  41 . Thus, the potential of the charge accumulation section  41  is reset to the reset voltage Vr. The reset voltage Vr herein is, for example, 0 V. 
     Subsequently, the potential Vrc of the reset control line  48  is switched from the high level to the low level. Thus, the reset transistor  28  is turned off from the on state. During the off state of the reset transistor  28 , the reset signal Vrsig is read out from each of the unit pixels  10  in Row R 0  through the corresponding vertical signal line  47 . The reset signal Vrsig is a signal corresponding to the value of the reset voltage Vr. The reset signal Vrsig is transmitted to the column signal processing circuit  37 . 
     After reading out the reset signal Vrsig, the potential Vsel of the address control line  46  is switched from the high level to the low level. Thus, the address transistor  26  is turned off from the on state. 
     As described above, the pixel signal Vpsig and the reset signal Vrsig that are read out are both transmitted to the column signal processing circuit  37 . By obtaining the difference between these signals, a fixed pattern noise can be removed. Specifically, the reset signal Vrsig corresponds to a noise component, and by subtracting the noise component from the pixel signal Vpsig, the noise is removed. 
     In this example, as schematically illustrated in  FIG. 3A , in accordance with the horizontal synchronization signal HD, signal readout and reset are sequentially performed on pixels that belong to Row R 0  to Row R 7  in units of row. In the following description, an interval between pulses of the horizontal synchronization signal HD, in other words, a period from selection of a certain row until selection of the next row, may be referred to as “ 1 H period”. 
     In this example, for example, a period H 0  from time t 0  to time t 1  corresponds to a  1 H period. A period H 1  from time t 1  to time t 2  also corresponds to a  1 H period. A period H 2  from time t 2  to time t 3  also corresponds to a  1 H period. A period H 3  from time t 3  to time t 4  also corresponds to a  1 H period. A period H 4  from time t 4  to time t 5  also corresponds to a  1 H period. A period H 5  from time t 5  to time t 6  also corresponds to a  1 H period. A period H 6  from time t 6  to time t 7  also corresponds to a  1 H period. A period H 7  from time t 7  to time t 8  also corresponds to a  1 H period. 
     During the period H 0 , readout from pixels that belong to Row R 0  is performed while accumulating charge in the charge accumulation section  41 . During the period H 1 , readout from pixels that belong to Row R 1  is performed while accumulating charge in the charge accumulation section  41 . During the period H 2 , readout from pixels that belong to Row R 2  is performed while accumulating charge in the charge accumulation section  41 . During the period H 3 , readout from pixels that belong to Row R 3  is performed while accumulating charge in the charge accumulation section  41 . During the period H 4 , readout from pixels that belong to Row R 4  is performed while accumulating charge in the charge accumulation section  41 . During the period H 5 , readout from pixels that belong to Row R 5  is performed while accumulating charge in the charge accumulation section  41 . During the period H 6 , readout from pixels that belong to Row R 6  is performed while accumulating charge in the charge accumulation section  41 . During the period H 7 , readout from pixels that belong to Row R 7  is performed while accumulating charge in the charge accumulation section  41 . Note that the expression “readout is performed during a period” is not to be limitedly interpreted as spending the entire period for readout. This expression includes spending part of the period for readout. In the example in  FIG. 3A , readout of pixels that belong to a row is performed during the high-sensitivity exposure period. 
     In this embodiment, the  1 H periods included in the first frame have an equal duration. However, these may have different durations. 
     In the example in  FIG. 3A , on the basis of the vertical synchronization signal VD, scanning is performed on eight rows from Row R 0  to Row R 7 . The scanning herein refers to readout of signals from pixels that belong to a row. 
     During readout from the pixels that belong to the period H 0 , the period H 1 , the period H 2 , the period H 3 , the period H 4 , the period H 5 , the period H 6 , and the period H 7 , a voltage V 1  is applied from the voltage supply circuit  32  to the counter electrode  12 . 
     Specifically, at time t 0 , the voltage Vb applied from the voltage supply circuit  32  to the counter electrode  12  is switched from a voltage V 2  to the voltage V 1 . Subsequently, at time tu 0 , the voltage Vb is switched from the voltage V 1  to the voltage V 2 . Subsequently, at time t 1 , the voltage Vb is switched from the voltage V 2  to the voltage V 1 . Subsequently, at time tu 1 , the voltage Vb is switched from the voltage V 1  to the voltage V 2 . Subsequently, at time t 2 , the voltage Vb is switched from the voltage V 2  to the voltage V 1 . Subsequently, at time tu 2 , the voltage Vb is switched from the voltage V 1  to the voltage V 2 . Subsequently, the voltage Vb is switched repeatedly in the above manner. 
     The voltage V 2  is typically a voltage with which the potential difference between the pixel electrode  11  and the counter electrode  12  becomes less than or equal to 0 V. This potential difference will be further described below. As described above, by turning on the reset transistor  28 , the reset voltage Vr can be supplied from the reset voltage source  34  to the charge accumulation section  41  through the reset voltage line  44  and the reset transistor  28 . By the reset voltage Vr being supplied to the charge accumulation section  41 , the voltage of the pixel electrode  11  is also reset to the voltage Vr. By setting the voltage V 2  to be equal to the voltage Vr, the above potential difference can be made 0 V when the voltage of the pixel electrode  11  is reset to the voltage Vr. As described above, the voltage Vr may be 0 V. 
     In a state where the bias voltage applied to the photoelectric conversion layer  15  is 0 V, most of charge generated in the photoelectric conversion layer  15  is eliminated. This is assumed to be because most of positive and negative charge generated by light irradiation is immediately eliminated due to recombination. On the other hand, signal charge accumulated in the charge accumulation section  41  during high-sensitivity exposure is not eliminated and is held until a reset operation of the pixel is performed. The signal charge is not discarded by switching between the low-sensitivity exposure state and the high-sensitivity exposure state. As a result, even if the high-sensitivity exposure period and the low-sensitivity exposure period are repeated, the signal charge accumulated during each high-sensitivity exposure is integrated. During the high-sensitivity exposure, in the above example, the bias voltage is 10 V. Note that when a positive bias voltage is applied to the photoelectric conversion layer  15  during the low-sensitivity exposure, signal charge is accumulated also during the low-sensitivity exposure. In such a case, signal charge accumulated during the low-sensitivity exposure, in addition to the high-sensitivity exposure, is integrated. 
     Example of Long High-Sensitivity Exposure Period 
     Another example of this embodiment is illustrated in  FIGS. 5A and 5B . In the example in  FIGS. 5A and 5B , each high-sensitivity exposure period is longer and each low-sensitivity exposure period is shorter than those in the example in  FIGS. 3A and 3B . In the example in  FIGS. 5A and 5B , a high sensitivity is more likely to be obtained than in the example in  FIGS. 3A and 3B . In the example in  FIGS. 5A and 5B , each readout period is shorter than the high-sensitivity exposure period including the period. 
     The technique of this embodiment described with reference to  FIGS. 3A and 3B ,  FIGS. 5A and 5B , and the like can be expressed as follows. The imaging device  100  includes the pixel array PA. A first period, a third period, and a second period appear in this order in a first frame. During the first period, pixel signal readout is performed on a first row in the pixel array PA. During the second period, pixel signal readout is performed on a second row in the pixel array PA. During the third period, no pixel signal readout is performed on the rows in the pixel array PA. Each of the first period and the second period is the high-sensitivity exposure period. The third period is the low-sensitivity exposure period. Note that the first row and the second row are rows different from each other. In the example in  FIG. 3A , the duration of the first frame period is the same as the duration from the start of pixel signal readout in a row until the start of the following pixel signal readout. The same applies to a second frame in  FIG. 13A , which will be described later. Specifically, in the example in  FIG. 3A , the duration of the first frame period is the duration of the period from time t 0  to time t 15 . The duration of the second frame period, which will be described later, is the duration of the period from time t 15  to time t 30 . In the example in  FIGS. 3A and 3B , the driving section sets the first period, the second period, and the third period and sets the timing for pixel signal readout. The driving section may also set a fourth period, a fifth period, and a sixth period, which will be described later. 
     Specifically, as illustrated in  FIG. 3B , in the example in  FIG. 3A , the period from time t 0  to time tu 0  may correspond to the first period, the period from time tu 0  to time t 1  may correspond to the third period, and the period from time t 1  to time tu 1  may correspond to the second period. Row R 0  may correspond to the first row. Row R 1  may correspond to the second row. The first period and the third period are adjacent to each other. The third period and the second period are adjacent to each other. 
     From a different perspective, in the example in  FIG. 3A , the period from t 1  to time tu 1  may correspond to the first period. This period is the high-sensitivity exposure period. The low-sensitivity exposure period subsequent to the first period may correspond to the third period. The high-sensitivity exposure period subsequent to the third period may correspond to the second period. Row R 1  may correspond to the first row. Row R 2  may correspond to the second row. Such different perspectives may be similarly possible in the other embodiments. 
     As illustrated in  FIG. 5B , in the example in  FIG. 5A , the period from time td 0  to time tu 0  may correspond to the first period, the period from time tu 0  to time td 1  may correspond to the third period, and the period from time td 1  to time tu 1  may correspond to the second period. Row R 0  may correspond to the first row. Row R 1  may correspond to the second row. The first period and the third period are adjacent to each other. The third period and the second period are adjacent to each other. 
     From a different perspective, in the example in  FIG. 5A , the period from td 1  to time tu 1  may correspond to the first period. This period is the high-sensitivity exposure period. The low-sensitivity exposure period subsequent to the first period may correspond to the third period. The high-sensitivity exposure period subsequent to the third period may correspond to the second period. Row R 1  may correspond to the first row. Row R 2  may correspond to the second row. 
     The technique of this embodiment is suitable for obtaining a high sensitivity while maintaining an image quality. Now, this point will be described. 
     The upper part in each of  FIGS. 6 to 8  illustrates a temporal change of the voltage Vb to be applied to the counter electrode  12 . Each rectangle in the lower part represents pixel signal readout. 
     In order to obtain an appropriate image quality, it is desirable that there be no rows on which pixel signal readout is performed in the pixel array PA during a period across the low-sensitivity exposure period and the high-sensitivity exposure period. In the example in  FIG. 6 , as in this embodiment, such a row is not present. Thus, in this light, the example in  FIG. 6  is advantageous in terms of obtaining an appropriate image quality. 
     However, according to the present inventors&#39; study, the example in  FIG. 6  has room for improvement in obtaining an appropriate image. Specifically, in the example in  FIG. 6 , pixel signal readout is performed during both the low-sensitivity exposure period and the high-sensitivity exposure period. In this case, an output level difference may be generated between a row in the pixel array PA in which pixel signal readout is performed during the low-sensitivity exposure period and a row in the pixel array PA in which pixel signal readout is performed during the high-sensitivity exposure period. In addition, the output level difference may generate a periodic lateral stripe in the image. 
     To prevent the periodic lateral stripe from being generated, pixel signal readout may be performed during one of the low-sensitivity exposure period and the high-sensitivity exposure period. The present inventors have studied during which period pixel signal readout is to be performed. Details of the study will be described below with reference to  FIGS. 7 and 8 . In  FIGS. 7 and 8 , a period Tg refers to a period during which pixel signal readout is performed. 
     In the example in  FIG. 8 , each of the first period and the second period is the high-sensitivity exposure period, and the third period is the low-sensitivity exposure period, Setting these periods in this manner is suitable for image capturing with a high sensitivity for the following reasons. 
     It is considered that the first period, the second period, and the third period are set in a manner opposite to the above, as illustrated in  FIG. 7 . In this case, if a short low-sensitivity exposure period and a long high-sensitivity exposure period are employed in order to make a sensitivity high, the period Tg is likely to stick out from the low-sensitivity exposure period. This is disadvantageous in terms of obtaining an appropriate image quality. On the other hand, in the example in  FIG. 8 , each of the first period and the second period is the high-sensitivity exposure period, and the third period is the low-sensitivity exposure period. In this case, if a short low-sensitivity exposure period and a long high-sensitivity exposure period are employed in order to make a sensitivity high, the period Tg is unlikely to stick out from the high-sensitivity exposure period. From the above, if each timing for pixel signal readout is fixed (i.e., if the frame rate is fixed), it is understood that image quality degradation due to the above stick-out is likely to be prevented while maintaining a high sensitivity in the example in  FIG. 8  compared with the example in  FIG. 7 . 
     The present disclosure does not exclude an embodiment of changing the timings for pixel signal readout. It is possible to make the interval between the timings for pixel signal readout longer. In this case, even if each of the first period and the second period is set as the low-sensitivity exposure period and the third period is set as the high-sensitivity exposure period as in  FIG. 7 , a high sensitivity can be obtained without the above stick-out. Specifically, by employing a long interval and fitting the long high-sensitivity exposure period within the long interval, a high sensitivity can be obtained without the above stick-out. However, if the interval is made longer, it is difficult to maintain the frame rate. Thus, even if the embodiment of changing timings for pixel signal readout is taken into account, the example in  FIG. 8  is advantageous over the example in  FIG. 7  in obtaining a high sensitivity while maintaining the image quality. 
     For the above reasons, the technique according to this embodiment is suitable for obtaining a high sensitivity while maintaining the image quality. 
     The first row and the second row may be or may not be adjacent to each other. 
     As described above, in this embodiment, the first period, the third period, and the second period appear in this order in the first frame. If the first period or the second period is defined as an X-th period, the X-th period and the third period may be repeated alternately in the first frame. The first frame may be constituted by this repetition alone. 
     As understood from the description above, according to this embodiment, a plurality of high-sensitivity exposure periods are dispersed in the first frame. Pieces of data obtained through image capturing during the respective high-sensitivity exposure periods are superposed to form an image. In this manner, the high-sensitivity exposure periods are unlikely to be concentrated at a specific area in the first frame period, and information over the entire frame period is likely to be obtained. Thus, compared with a case in which the high-sensitivity exposure periods are concentrated at one area in the first frame, it is likely to capture an appropriate image of a subject that changes over time. For example, it is likely to capture an appropriate image of a blinking subject such as a light emitting diode (LED). Specifically, if the high-sensitivity exposure periods are concentrated at one area, the subject may not emit light within the high-sensitivity exposure periods. In contrast, if the plurality of high-sensitivity exposure periods are dispersed, such a situation is unlikely to occur, and it is easy to capture an image of the blinking subject. 
     In the first frame, the total period of the high-sensitivity exposure period may be longer than or equal to the total period of the low-sensitivity exposure period. This helps image capturing with a high sensitivity. Note that this feature is also applicable to the other embodiments. However, the total period of the high-sensitivity exposure period may be shorter than the total period of the low-sensitivity exposure period. 
     The imaging device  100  may include a control mode for rolling shutter operation. The rolling shutter is a method for sequential pixel signal readout for each row in the pixel array PA. In addition, by rolling shutter, the high-sensitivity exposure period is sequentially set for each row in the pixel array PA. “First frame” in  FIG. 3A  may be a frame in which the imaging device  100  operates by rolling shutter. The same applies to the other figures. In addition, the same applies to “second frame” in  FIG. 10 , which will be described later. 
     In the example in  FIGS. 1 and 2 , the imaging device  100  includes the semiconductor substrate  20  and the photoelectric conversion section  13 . The photoelectric conversion section  13  includes the photoelectric conversion layer  15 , the pixel electrode (hereinafter also referred to as first electrode)  11 , and the counter electrode (hereinafter also referred to as second electrode)  12 . The semiconductor substrate  20 , the first electrode  11 , the photoelectric conversion layer  15 , and the second electrode  12  are stacked in this order. Such a stack structure may form an imaging element with an easily adjustable sensitivity. The first electrode  11  corresponds to the pixel electrode  11 . The second electrode  12  corresponds to the counter electrode  12 . Specifically, each of the first electrode  11  and the second electrode  12  is in contact with the photoelectric conversion layer  15 . 
     In the example in  FIGS. 1 and 2 , the imaging device  100  includes the voltage supply circuit  32 . During the high-sensitivity exposure period, the voltage supply circuit  32  controls the voltage Vb of the second electrode  12  to a first voltage. During the low-sensitivity exposure period, the voltage supply circuit  32  controls the voltage Vb of the second electrode  12  to a second voltage. The first voltage and the second voltage are different from each other. By controlling the voltage of the second electrode  12  in this manner, the sensitivity can be adjusted. The expression “to control the voltage of an electrode to the first voltage” or “to control the voltage of an electrode to the second voltage” indicates that a target voltage is the first voltage or the second voltage. This expression is not to be limitedly interpreted as the voltage Vb of the second electrode  12  reaching the first voltage or the second voltage instantly. This expression includes the voltage Vb of the second electrode  12  reaching the first voltage or the second voltage relatively slowly by being influenced by the time constant or the like. The same applies to the following expression “to control the voltage of an electrode to a third voltage” or “to control the voltage of an electrode to a fourth voltage”. In the example in  FIGS. 1 to 3 , the first voltage corresponds to the voltage V 1 , and the second voltage corresponds to the voltage V 2 . 
     In the example in  FIGS. 1 and 2 , the imaging device  100  collects holes in the pixel electrode  11 . Thus, the first voltage is higher than the second voltage. However, as described above, the imaging device  100  may also collect, instead of holes, electrons in the pixel electrode  11 . In this case, the first voltage may be lower than the second voltage. 
     The imaging device  100  may have an R component and a C component that may change the voltage of the second electrode  12  in accordance with the time constant determined by the R component and the C component from the start of the third period. The third period is, for example, longer than or equal to twice the time constant. In this manner, during the third period, even if the presence of the time constant is taken into account, the voltage of the second electrode  12  may be sufficiently close to an expected value. This is advantageous in terms of obtaining a desired sensitivity. The third period may be longer than or equal to three times the time constant. For example, the third period is longer than or equal to 20 μs. The third period is, for example, shorter than or equal to thirty times the time constant. For example, the third period is shorter than or equal to 300 μs. The R component is a resistance component. The C component is a capacitance component. 
     Similarly, the voltage of the second electrode  12  changes in accordance with the time constant from the start of the first period. The first period may be longer than or equal to twice or longer than or equal to three times the time constant. The first period may be longer than or equal to 20 μs. The first period may be shorter than or equal to thirty times the time constant. The first period may be shorter than or equal to 300 μs. 
     Similarly, the voltage of the second electrode  12  changes in accordance with the time constant from the start of the second period. The second period may be longer than or equal to twice or longer than or equal to three times the time constant. The second period may be longer than or equal to 20 μs. The second period may be shorter than or equal to thirty times the time constant. The second period may be shorter than or equal to 300 μs. 
     The above R component may include a resistance of the second electrode  12 . Specifically, the above R component may include the resistance of the second electrode  12  and a resistance of the photoelectric conversion layer  15 . More specifically, when a voltage supply source for the second electrode  12  is defined as a power source PS, a voltage output section in the power source PS for the second electrode  12  is defined as a first end, and the boundary between the photoelectric conversion layer  15  and the first electrode  11  is defined as a second end, the above R component may be a composite resistance of elements that constitute an electrical path from the first end to the second end. Note that the R component including a resistance R 1  of an element is a concept including a case in which the R component is the resistance R 1 . In addition, the R component including the resistance R 1  of an element is a concept including general cases in which the R component is a composite resistance of a plurality of resistances, such as a case in which the element having the resistance R 1  is connected in series to another element having a resistance R 2  and the R component is R 1 +R 2 , and a case in which this element is connected in parallel to another element having the resistance R 2  and the R component is R 1 R 2 /(R 1 +R 2 ). 
     The above C component may include a capacitance of the photoelectric conversion layer  15 . Specifically, the above C component may include a capacitance of the second electrode  12  and the capacitance of the photoelectric conversion layer  15 , More specifically, when the voltage supply source for the second electrode  12  is defined as the power source PS, the voltage output section in the power source PS for the second electrode  12  is defined as the first end, and the boundary between the photoelectric conversion layer  15  and the first electrode  11  is defined as the second end, the above C component may be a composite capacitance of elements that constitute an electrical path from the first end to the second end. Note that the C component including a capacitance C 1  of an element is a concept including a case in which the C component is the capacitance C 1 . In addition, the C component including the capacitance C 1  of an element is a concept including general cases in which the C component is a composite capacitance of a plurality of capacitances, such as a case in which the element having the capacitance C 1  is connected in parallel to another element having a capacitance C 2  and the C component is C 1 +C 2 , and a case in which this element is connected in series to another element having the capacitance C 2  and the C component is C 1 C 2 /(C 1 +C 2 ). 
     As described above, in this embodiment, during the first period, pixel signal readout is performed on the first row in the pixel array PA. During the second period, pixel signal readout is performed on the second row in the pixel array PA. During the third period, no pixel signal readout is performed on the rows in the pixel array PA. Each of the first period and the second period is the high-sensitivity exposure period, and the third period is the low-sensitivity exposure period. A duty ratio may be changed so as to maintain this configuration. The duty ratio may be changed so as to maintain, in addition to this configuration, other features of this embodiment. The duty ratio herein refers to a ratio of the total period of the high-sensitivity exposure period in the first frame to the first frame period. Changing the duty ratio can adjust the sensitivity. 
     Specifically, by changing the duty ratio, electronic neutral density (ND) control is performed. The electronic ND control refers to electric control on the sensitivity of an imaging element. The electronic ND control may also be performed by adjusting the value of the potential difference between the pixel electrode  11  and the counter electrode  12  during the high-sensitivity exposure period. Now, these two types of electronic ND control will be described. 
     First, electronic ND control by adjusting the value of the potential difference between the pixel electrode  11  and the counter electrode  12  will be described. 
     As understood from the description above, according to this embodiment, the potential of the counter electrode  12  with respect to the potential of the pixel electrode  11  can be controlled. Thus, from hole-electron pairs generated in the photoelectric conversion layer  15  through photoelectric conversion, one of holes and electrons can be collected in the pixel electrode  11 . The amount of signal charge collected per unit time changes depending on the potential difference between the pixel electrode  11  and the counter electrode  12 . By changing the potential difference, electronic ND control can be performed. 
       FIG. 9  illustrates an example of change in the light-receiving sensitivity of the photoelectric conversion layer  15  with respect to the potential difference between the pixel electrode  11  and the counter electrode  12 . In  FIG. 9 , the horizontal axis indicates the potential difference between the pixel electrode  11  and the counter electrode  12 , and the vertical axis indicates a standardized sensitivity of the photoelectric conversion layer  15 . The standardized sensitivity herein is a standardized value when the sensitivity obtained with the potential difference between the pixel electrode  11  and the counter electrode  12  being 10 V is 1.0. 
       FIG. 9  illustrates that the light-receiving sensitivity of the photoelectric conversion layer  15  can be adjusted by adjusting the potential difference between the pixel electrode  11  and the counter electrode  12 . Specifically, in  FIG. 9 , “ND 2 ” indicates a standardized sensitivity corresponding to an ND 2  filter that reduces the amount of light incident on an imaging element by half, “ND 4 ” indicates a standardized sensitivity corresponding to an ND 4  filter that reduces the amount of light incident on an imaging element to a quarter, and “ND 8 ” indicates a standardized sensitivity corresponding to an ND 8  filter that reduces the amount of light incident on an imaging element to one eighth. The standardized sensitivity corresponding to the ND 2  filter is a half of 1.0, which is 0.5. The standardized sensitivity corresponding to the ND 4  filter is a quarter of 1.0, which is 0.25. The standardized sensitivity corresponding to the ND 8  filter is one eighth of 1.0, which is 0.125. These standardized sensitivities can be adjusted by adjusting the potential difference between the pixel electrode  11  and the counter electrode  12  and adjusting an electric field applied to the photoelectric conversion layer  15 . 
     In the above manner, the potential difference corresponding to the light-receiving sensitivity corresponding to a desired ND function can be given between the pixel electrode  11  and the counter electrode  12 . Thus, the photoelectric conversion layer  15  can serve as an electronic ND filter, and electronic ND control can be performed. 
       FIG. 10  illustrates the example of electronic ND control by adjusting the value of the potential difference between the pixel electrode  11  and the counter electrode  12 . In the example in  FIG. 10 , the imaging device  100  controls the voltage Vb of the second electrode  12  to the voltage V 1 , which is the first voltage, during the high-sensitivity exposure period. The imaging device  100  performs first driving using a first driving voltage Vm as the voltage  11 , which is the first voltage, and second driving using a second driving voltage Vn as the voltage V 1 , which is the first voltage. The first driving voltage Vm and the second driving voltage Vn are different from each other. The example in  FIG. 10  can be implemented by the above-described stack structure. 
     Next, electronic ND control by changing the duty ratio will be described. 
     The potential difference between the pixel electrode  11  and the counter electrode  12  may be selected from two values: a relatively large first value and a relatively small second value. If the potential difference is selected in this manner, even if the first value and the second value are fixed, the sensitivity can be adjusted. By changing a ratio of the period of the first value to the sum of the period of the first value and the period of the second value, the sensitivity can be adjusted. 
     The first value may be, but not limited to, the potential difference by which the standardized sensitivity of the photoelectric conversion layer  15  becomes 1.0. This potential difference is 10 V in the above example. The second value may be the potential difference by which the standardized sensitivity of the photoelectric conversion layer  15  becomes 0.0. This potential difference is 0 V in the above example. 
     If the electronic ND control is performed by changing the duty ratio, an operation for forming the first frame illustrated in  FIG. 3A  and an operation for forming the first frame illustrated in  FIG. 5A  can be switched. In the first frame of the former case, each high-sensitivity exposure period is relatively short. In the first frame of the latter case, each high-sensitivity exposure period is relatively long. 
     In the example in  FIG. 9 , the light-receiving sensitivity of the photoelectric conversion layer  15  changes non-linearly with respect to the potential difference between the pixel electrode  11  and the counter electrode  12 . Even in such a case, with the electronic ND control by changing the duty ratio, the light-receiving sensitivity with respect to the duty ratio can change linearly. Thus, the sensitivity can be adjusted easily. However, also in such a case, the electronic ND control by adjusting the value of the potential difference between the pixel electrode  11  and the counter electrode  12  can be performed. For example, this control can be performed by using a storage that stores a function indicating the relation between the potential difference and the light-receiving sensitivity. 
     In the first frame, it is not necessary that the high-sensitivity exposure periods are evenly distributed. In the example in  FIG. 11 , unlike in the example in  FIG. 3A , a period Tx is the low-sensitivity exposure period. In other words, in the example in  FIG. 11 , compared with the example in  FIG. 3A , the pulse of the voltage Vb is intermitted during the period Tx. On the other hand, in the example in FIG.  12 , unlike in the example in  FIG. 3A , the entirety of a period Ty is the high-sensitivity exposure period. The embodiments in  FIG. 11  and  FIG. 12  are also included in the first embodiment. 
     Second Embodiment 
     Now, the second embodiment will be described. In the second embodiment, substantially the same details as those in the first embodiment may be omitted from description. 
       FIG. 13A  is a timing chart illustrating an example of the operation of an imaging device according to the second embodiment.  FIG. 13B  is an enlarged view of part of  FIG. 13A . As understood from comparison between  FIG. 5A  and  FIG. 13A , in the second embodiment, the second frame is formed in addition to the first frame illustrated in  FIG. 5A . 
     In the second frame in  FIG. 13A , as in the first frame, in accordance with the horizontal synchronization signal HD, signal readout and reset are sequentially performed on pixels that belong to Row R 0  to Row R 7  in units of row. 
     In the second frame in this example, a period H 15  from time t 15  to time t 16  corresponds to a  1 H period. A period H 16  from time t 16  to time t 17  also corresponds to a  1 H period. A period H 17  from time t 17  to time t 18  also corresponds to a  1 H period. A period H 18  from time t 18  to time t 19  also corresponds to a  1 H period. A period H 19  from time t 19  to time t 20  also corresponds to a  1 H period. A period H 20  from time t 20  to time t 21  also corresponds to a  1 H period. A period H 21  from time t 21  to time t 22  also corresponds to a  1 H period. A period H 22  from time t 22  to time t 23  also corresponds to a  1 H period. 
     During the period H 15 , readout from pixels that belong to Row R 0  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 16 , readout from pixels that belong to Row R 1  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 17 , readout from pixels that belong to Row R 2  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 18 , readout from pixels that belong to Row R 3  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 19 , readout from pixels that belong to Row R 4  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 20 , readout from pixels that belong to Row R 5  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 21 , readout from pixels that belong to Row R 6  is performed, and then charge is accumulated in the charge accumulation section  41 . During the period H 22 , readout from pixels that belong to Row R 7  is performed, and then charge is accumulated in the charge accumulation section  41 . 
     In this embodiment, the  1 H periods included in the second frame have an equal duration. However, these may have different durations. 
     During readout from the pixels that belong to the period H 15 , the period H 16 , the period H 17 , the period H 18 , the period H 19 , the period H 20 , the period H 21 , and the period H 22 , the voltage V 2  is applied from the voltage supply circuit  32  to the counter electrode  12 . Note that the predetermined voltage Vs is applied from the voltage supply circuit  35  to the shield electrode  17  as in the first embodiment. 
     Specifically, at time t 15 , the voltage Vb applied from the voltage supply circuit  32  to the counter electrode  12  is the voltage V 2 . At time td 15 , the voltage Vb is switched from the voltage V 2  to the voltage V 1 . Subsequently, at time t 16 , the voltage Vb is switched from the voltage V 1  to the voltage V 2 . Subsequently, at time td 16 , the voltage Vb is switched from the voltage V 2  to the voltage V 1 . Subsequently, at time t 17 , the voltage Vb is switched from the voltage V 1  to the voltage V 2 . Subsequently, at time td 17 , the voltage Vb is switched from the voltage V 2  to the voltage V 1 . Subsequently, the voltage Vb is switched repeatedly in the above manner. 
     The technique of this embodiment described with reference to  FIGS. 13A and 13B  and the like can be expressed as follows. A fourth period, a sixth period, and a fifth period appear in this order in the second frame. During the fourth period, pixel signal readout is performed on a fourth row in the pixel array PA. During the fifth period, pixel signal readout is performed on a fifth row in the pixel array PA. During the sixth period, no pixel signal readout is performed on the rows in the pixel array PA. Each of the fourth period and the fifth period is the low-sensitivity exposure period. The sixth period is the high-sensitivity exposure period. The second frame as above is suitable for image capturing with a low sensitivity. Note that the fourth row and the fifth row are rows different from each other. 
     Specifically, as illustrated in  FIG. 13B , in the example in  FIG. 13A , the period from time t 15  to time td 15  may correspond to the fourth period, the period from time td 15  to time t 16  may correspond to the sixth period, and the period from time t 16  to time td 16  may correspond to the fifth period. Row R 0  may correspond to the fourth row. Row R 1  may correspond to the fifth row. The fourth period and the sixth period are adjacent to each other. The sixth period and the fifth period are adjacent to each other. The imaging device  100  has a control mode that is either a first mode in which the first frame is formed or a second mode in which the second frame is formed. 
     The fourth row and the fifth row may be or may not be adjacent to each other. 
     From a different perspective, in the example in  FIG. 13A , the period from t 16  to time td 16  may correspond to the fourth period. This period is the low-sensitivity exposure period. The high-sensitivity exposure period subsequent to the fourth period may correspond to the sixth period. The low-sensitivity exposure period subsequent to the sixth period may correspond to the fifth period. Row R 1  may correspond to the fourth row. Row R 2  may correspond to the fifth row. 
     In the example in  FIG. 13A , the first mode is switched to the second mode at time t 15 . The period during which the first mode is implemented includes the period from time t 0  to time t 15 . During this period, the first frame is formed. The period during which the second mode is implemented includes the period from time t 15  to time t 30 . During this period, the second frame is formed. 
     In this example, the first mode and the second mode are switched on the basis of a set value of sensitivity (hereinafter also referred to as set sensitivity). The set value indicates a target value to be obtained by control. 
     In this example, the set sensitivity is a value that changes depending on the duty ratio and the set value of the potential difference (hereinafter also referred to as set potential difference) between the pixel electrode  11  and the counter electrode  12  during the high-sensitivity exposure period. 
     Specifically, the set sensitivity increases as the duty ratio increases. The set sensitivity increases as the set potential difference increases. More specifically, the set sensitivity increases in proportion to the duty ratio. The set sensitivity increases non-linearly with respect to the set potential difference. The non-linear increase can be known in advance through experiment or the like. 
     The non-linear increase will be further described. The light-receiving sensitivity of the photoelectric conversion layer  15  when the potential difference between the pixel electrode  11  and the counter electrode  12  is a certain value is standardized as 1. This sensitivity that is standardized is referred to as standardized sensitivity as in the example in  FIG. 9 . As in  FIG. 9 , the standardized sensitivity changes non-linearly with respect to the potential difference between the pixel electrode  11  and the counter electrode  12 . In the following description, the set value of the standardized sensitivity may be referred to as set standardized sensitivity. The above certain value (i.e., the potential difference by which the standardized sensitivity becomes 1) may be referred to as potential difference H. The potential difference by which the standardized sensitivity becomes 0 may be referred to as potential difference L. According to the description with reference to  FIG. 9 , the potential H may be 10 V, and the potential difference L is, for example, 0 V. 
     In a first example, when the set sensitivity is reduced to less than a switching threshold in the first mode, the first mode is switched to the second mode. When the set sensitivity increases to greater than or equal to the switching threshold in the second mode, the second mode is switched to the first mode. As the switching threshold in the first example, for example, a value greater than or equal to 0.3 and less than or equal to 0.7, specifically, 0.5 may be used. 
     In a second example, when the set sensitivity is reduced to less than a first threshold in the first mode, the first mode is switched to the second mode. When the set sensitivity increases to greater than or equal to a second threshold in the second mode, the second mode is switched to the first mode. The first threshold is smaller than the second threshold. As the first threshold in the second example, for example, a value greater than or equal to 0.25 and less than or equal to 0.41, specifically, 0.33 may be used. As the second threshold in the second example, for example, a value greater than or equal to 0.42 and less than or equal to 0.58, specifically, 0.5 may be used. 
     In a specific example, the set potential difference during the low-sensitivity exposure period is set to the potential difference L. Thus, the set standardized sensitivity during the low-sensitivity exposure period is zero. The set sensitivity is a product of the duty ratio and the set standardized sensitivity during the high-sensitivity exposure period. In this specific example, when the duty ratio is 1 (i.e., 100%) and the set standardized sensitivity during the high-sensitivity exposure period is 1 (i.e., 100%), the set sensitivity is 1 (i.e., 100%). The set sensitivity is 0 when the duty ratio is 0, and is also 0 when the set standardized sensitivity is 0. By combining this specific example and the above second example, 0.33 is used as the first threshold, 0.5 is used as the second threshold, and the set standardized sensitivity during the high-sensitivity exposure period is set to 1. In this case, by setting the ratio between the duration of the high-sensitivity exposure period and the duration of the low-sensitivity exposure period in the first mode to 1:2, the set sensitivity can be 0.33 in the first mode. 
     In the example in  FIG. 13A , in the second frame period, pixel signals read out from the pixels that belong to Row R 0  are signals in accordance with charge accumulated in the pixels during an interval period from pixel signal readout in the first frame until pixel signal readout in the second frame. This period is a charge accumulating period of the pixels in Row R 0 . The same applies to Row R 1  to Row R 7 . 
     In the example in  FIG. 13A , in the rows from Row R 0  to Row R 7 , the accumulating period of charge to be read by pixel signal readout in the second frame have an equal duration. However, in the rows from Row R 0  to Row R 7 , the total periods of the high-sensitivity exposure periods in the charge accumulating period have different durations. This is because the high-sensitivity exposure periods have different durations in the first frame and in the second frame. Specifically, each high-sensitivity exposure period in the first frame has a longer duration than each high-sensitivity exposure period in the second frame. In addition, although the number of the high-sensitivity exposure periods in the charge accumulating period in Row R 0  to Row R 7  is equal, the number of the high-sensitivity exposure periods in the first frame is larger as the row number is smaller. Thus, the total period of the high-sensitivity exposure periods in the charge accumulating period is longer as the row number is smaller. However, even with this difference, it is possible to prevent the sensitivity from becoming uneven according to the row in the pixel array PA on the same screen. 
     Specifically, for each row in the pixel array PA, a gain can be applied to output signals of pixels. More specifically, a gain in accordance with a ratio Tt/Ta can be applied to the output signals of pixels, the ratio Tt/Ta being a ratio of a total period Tt of the high-sensitivity exposure periods to an accumulating period Ta. Even more specifically, a gain in inverse proportion to the ratio Tt/Ta can be applied to the output signals of pixels. By applying such a gain, the output signals are corrected so as to prevent the sensitivity from becoming uneven according to the row. 
     In the example in  FIG. 13A , in a case where the ratio Tt/Ta in a certain row in the pixel array PA is rat1 and the ratio Tt/Ta in another row is rat2, a ratio of the gain to be applied to the output signals of pixels that belong to the certain row and the gain to be applied to the output signals of pixels that belong to the other row can be set to rat2:rat1. This can prevent the sensitivity in the certain row and the other row in the pixel array PA from becoming uneven. The effect of this prevention is likely to be produced if, in particular, the set standardized sensitivity during the high-sensitivity exposure period is fixed to a certain single value and the set standardized sensitivity during the low-sensitivity exposure period is fixed to another single value. However, this effect may also be produced to an extent even if these are not fixed. The ratio Tt/Ta herein is the ratio Tt/Ta of the total period Tt of the high-sensitivity exposure periods to the accumulating period Ta. The accumulating period Ta is an interval period between pixel signal readout and pixel signal readout in a row. 
     Third Embodiment 
     In the first and second embodiments, the sensitivity is modulated by changing the voltage Vb of the counter electrode  12 . However, the sensitivity may also be modulated by changing the voltage of the shield electrode  17 , while the voltage of the counter electrode  12  is maintained at a constant voltage. In the third embodiment, the sensitivity is modulated by changing the voltage of the shield electrode  17 . 
     Now, the third embodiment will be described with reference to  FIG. 14 . In the third embodiment, substantially the same details as those in the first embodiment may be omitted from description. Note that the technique of the third embodiment is applicable not only to the first embodiment but also to the other embodiments. 
     In the third embodiment, as illustrated in  FIG. 14 , the voltage supply circuit  32  constantly maintains the voltage Vb of the counter electrode  12  at the voltage V 1 . On the other hand, the voltage supply circuit  35  changes the voltage Vs of the shield electrode  17  between a voltage V 3  and a voltage V 4  through the sensitivity control line  45 . The voltage V 3  is a voltage higher than the voltage V 4 . The voltage V 4  is a voltage lower than the voltage V 3 . For example, the voltage V 3  is higher than the reset voltage Vr, and the voltage V 4  is lower than the reset voltage Vr. In addition, for example, the voltage V 3  and the voltage V 4  are lower than the voltage V 1 . The reference of the voltage Vs is, for example, the ground potential of the imaging device. The period during which the voltage Vs of the shield electrode  17  is set at the voltage V 3  corresponds to the high-sensitivity exposure period, and the period during which the voltage Vs of the shield electrode  17  is set at the voltage V 4  corresponds to the low-sensitivity exposure period. 
     In the example in  FIG. 14 , during readout from the pixels that belong to the period H 0 , the period H 1 , the period H 2 , the period H 3 , the period H 4 , the period H 5 , the period H 6 , and the period H 7 , the voltage V 3  is applied to the shield electrode  17 . 
     Specifically, at time t 0 , the voltage Vs applied to the shield electrode  17  is switched from the voltage V 4  to the voltage V 3 . At time tu 0  , the voltage Vs is switched from the voltage V 3  to the voltage V 4 . Subsequently, at time t 1 , the voltage Vs is switched from the voltage V 4  to the voltage V 3 . Subsequently, at time tu 1 , the voltage Vs is switched from the voltage V 3  to the voltage V 4 . Subsequently, at time t 2 , the voltage Vs is switched from the voltage V 4  to the voltage V 3 . Subsequently, at time tu 2 , the voltage Vs is switched from the voltage V 3  to the voltage V 4 . Subsequently, the voltage Vs is switched repeatedly in the above manner. 
     According to the third embodiment, substantially the same effects as those in the first embodiment are obtained. 
     Now, the principle of modulation of the sensitivity in the third embodiment will be described. The sensitivity is modulated by an electric field generated by the potential difference between the pixel electrode  11  and the counter electrode  12  and an electric field generated by the potential difference between the shield electrode  17  and the counter electrode  12 . 
     In the following situation, signal charge is holes, the voltage of the counter electrode  12  is higher than the voltage of the pixel electrode  11 , and an electric field from the counter electrode  12  toward the pixel electrode  11  is generated. If the voltage of the shield electrode  17  is high (e.g., higher than the voltage of the pixel electrode  11 ), the signal charge is unlikely to be captured in the shield electrode  17  and is likely to flow into the pixel electrode  11 . Thus, a high sensitivity is obtained. In contrast, if the voltage of the shield electrode  17  is low (e.g., lower than the voltage of the pixel electrode  11 ), signal charge is likely to be captured in the shield electrode  17  and is unlikely to flow into the pixel electrode  11 . Thus, a low sensitivity is obtained. In other words, in the former case, the photoelectric conversion layer  15  is likely to have an appropriate sensitivity in a broader area than in the latter case. For example, during the high-sensitivity exposure period, a magnitude relation in which the voltage of the counter electrode  12 &gt;the voltage of the shield electrode  17 &gt;the voltage of the pixel electrode  11  can be employed. During the low-sensitivity exposure period, a magnitude relation in which the voltage of the counter electrode  12 &gt;the voltage of the pixel electrode  11 &gt;the voltage of the shield electrode  17  can be employed. 
     In the following situation, signal charge is electrons, the voltage of the pixel electrode  11  is higher than the voltage of the counter electrode  12 , and an electric field from the pixel electrode  11  toward the counter electrode  12  is generated. If the voltage of the shield electrode  17  is low (e.g., lower than the voltage of the pixel electrode  11 ), the signal charge is unlikely to be captured in the shield electrode  17  and is likely to flow into the pixel electrode  11 . Thus, a high sensitivity is obtained. In contrast, if the voltage of the shield electrode  17  is high (e.g., higher than the voltage of the pixel electrode  11 ), signal charge is likely to be captured in the shield electrode  17  and is unlikely to flow into the pixel electrode  11 . Thus, a low sensitivity is obtained. In other words, in the former case, the photoelectric conversion layer  15  is likely to have an appropriate sensitivity in a broader area than in the latter case. For example, during the high-sensitivity exposure period, a magnitude relation in which the voltage of the counter electrode  12 &lt;the voltage of the shield electrode  17 &lt;the voltage of the pixel electrode  11  can be employed. During the low-sensitivity exposure period, a magnitude relation in which the voltage of the counter electrode  12 &lt;the voltage of the pixel electrode  11 &lt;the voltage of the shield electrode  17  can be employed. 
     For example, Japanese Unexamined Patent Application Publication No. 2017-005051 is to be referred to for details of modulation of the sensitivity by using the shield electrode  17 . 
     Both the voltage of the counter electrode  12  and the voltage of the shield electrode  17  can be changed. Also in this manner, the low-sensitivity exposure period and the high-sensitivity exposure period can be set. 
     In the third embodiment, the imaging device  100  includes the voltage supply circuit  35 . During the low-sensitivity exposure period, the voltage supply circuit  35  controls the voltage Vs of the shield electrode  17  to a fourth voltage. During the high-sensitivity exposure period, the voltage supply circuit  35  controls the voltage Vs of the shield electrode  17  to a third voltage. The third voltage and the fourth voltage are different from each other. By controlling the voltage of the first electrode  11  in this manner, the sensitivity can be adjusted. The third voltage corresponds to the voltage V 3 , and the fourth voltage corresponds to the voltage V 4 . 
     In the third example, the imaging device  100  collects holes in the pixel electrode  11 . Thus, the third voltage is higher than the fourth voltage. However, as described above, the imaging device  100  may also collect, instead of holes, electrons in the pixel electrode  11 . In this case, the third voltage may be lower than the fourth voltage. 
     The imaging device  100  may have an R component and a C component that may change the voltage of the shield electrode  17  in accordance with the time constant determined by the R component and the C component from the start of the third period. The third period is, for example, longer than or equal to twice the time constant. In this manner, during the third period, even if the presence of the time constant is taken into account, the voltage of the shield electrode  17  may be sufficiently close to an expected value. This is advantageous in terms of obtaining a desired sensitivity. The third period may be longer than or equal to three times the time constant. For example, the third period is longer than or equal to 20 μs. The third period is, for example, shorter than or equal to thirty times the time constant. For example, the third period is shorter than or equal to 300 μs. 
     Similarly, the voltage of the shield electrode  17  changes in accordance with the time constant from the start of the first period. The first period may be longer than or equal to twice or longer than or equal to three times the time constant. The first period may be longer than or equal to 20 μs. The first period may be shorter than or equal to thirty times the time constant. The first period may be shorter than or equal to 300 μs. 
     Similarly, the voltage of the shield electrode  17  changes in accordance with the time constant from the start of the second period. The second period may be longer than or equal to twice or longer than or equal to three times the time constant. The second period may be longer than or equal to 20 μs. The second period may be shorter than or equal to thirty times the time constant. The second period may be shorter than or equal to 300 μs. 
     The above R component may include a resistance of the first electrode  11 . Specifically, the above R component may include the resistance of the shield electrode  17  and a resistance of the photoelectric conversion layer  15 . More specifically, when a voltage supply source for the shield electrode  17  is defined as a power source PS, a voltage output section in the power source PS for the shield electrode  17  is defined as a first end, and the boundary between the photoelectric conversion layer  15  and the second electrode  12  is defined as a second end, the above R component may be a composite resistance of elements that constitute an electrical path from the first end to the second end. 
     The above C component may include a capacitance of the photoelectric conversion layer  15 . Specifically, the above C component may include a capacitance of the shield electrode  17  and the capacitance of the photoelectric conversion layer  15 . More specifically, when the voltage supply source for the shield electrode  17  is defined as the power source PS, the voltage output section in the power source PS for the shield electrode  17  is defined as the first end, and the boundary between the photoelectric conversion layer  15  and the second electrode  12  is defined as the second end, the above C component may be a composite capacitance of elements that constitute an electrical path from the first end to the second end. 
     The time constant that defines the manner of voltage change of the second electrode  12  described in the first embodiment can be referred to as second time constant. The R component and the C component that define the second time constant described in the first embodiment can be referred to as second R component and second C component, respectively. The time constant that defines the manner of voltage change of the shield electrode  17  described in the third embodiment can be referred to as third time constant. The R component and the C component that define the third time constant described in the third embodiment can be referred to as third R component and third C component, respectively. 
     As understood from the description above, the voltage supply circuit  35  supplies voltage to the shield electrode  17 . The voltage supply circuit  35  can set the voltage to different values during the high-sensitivity exposure period and during the low-sensitivity exposure period. In addition, the voltage supply circuit  35  can set the voltage to different values in frames. 
     The techniques of the first and third embodiments can be expressed together as follows. The imaging device has the following feature (i) and/or (ii), According to feature (i), the imaging device further includes the shield electrode (hereinafter also referred to as third electrode)  17 . The semiconductor substrate  20 , the third electrode  17 , the photoelectric conversion layer  15 , and the second electrode  12  are stacked in this order, and the third electrode  17  is controlled to different voltages during the high-sensitivity exposure period and during the low-sensitivity exposure period. According to feature (ii), the second electrode  12  is controlled to different voltages during the high-sensitivity exposure period and during the low-sensitivity exposure period. By controlling the voltage(s) of the electrode(s) in this manner, the sensitivity can be adjusted. The third electrode  17  corresponds to the shield electrode  17 . 
     Specifically, the techniques of the first and third embodiments can be expressed together as follows. The imaging device has the following feature (I) and/or (II). According to feature (I), the imaging device has feature (i) and the third time constant that changes the voltage of the third electrode in accordance with the third time constant, and the third period is longer than or equal to twice the third time constant. According to feature (II), the imaging device has feature (ii) and the second time constant that changes the voltage of the second electrode in accordance with the second time constant, and the third period is longer than or equal to twice the second time constant. In this manner, during the third period, even if the presence of the time constant is taken into account, the voltage(s) of the electrode(s) may be sufficiently close to an expected value. This is advantageous in terms of obtaining a desired sensitivity. 
     Electronic ND control may also be performed by adjusting the voltage Vs of the shield electrode  17 . That is, in this example, the imaging device further includes the shield electrode  17 . The semiconductor substrate  20 , the shield electrode  17 , the photoelectric conversion layer  15 , and the second electrode  12  are stacked in this order. The imaging device controls the voltage Vs of the shield electrode  17  to the voltage V 3 , which is the third voltage, during the high-sensitivity exposure period. The imaging device performs third driving using a third driving voltage as the voltage V 3 , which is the third voltage, and fourth driving using a fourth driving voltage as the voltage V 3 , which is the third voltage. The third driving voltage and the fourth driving voltage are different from each other. This example can be implemented by the above-described stack structure. 
     Fourth Embodiment 
     Now, a fourth embodiment will be described. In the fourth embodiment, substantially the same details as those in the first embodiment may be omitted from description. 
       FIG. 15  illustrates an exemplary circuit configuration of an imaging device according to the fourth embodiment. An imaging device  200  illustrated in  FIG. 15  includes a pixel array PA including a plurality of unit pixels  60  that are arrayed two-dimensionally.  FIG. 15  schematically illustrates an example in which the unit pixels  60  are arranged in a matrix of two rows and two columns. It is needless to say that the number and arrangement of the unit pixels  60  in the imaging device  200  are not limited to those in the example illustrated in  FIG. 15 . 
     Each of the unit pixels  60  includes a photoelectric conversion section  69 , a shutter gate transistor  61 , and a transfer transistor  62 . 
     In each of the unit pixels  60 , a readout circuit  65  is configured. The readout circuit  65  includes the address transistor  26 , the signal detection transistor  24 , and the reset transistor  28 . 
     In this embodiment, the photoelectric conversion section  69  is a photodiode. Specifically, the photoelectric conversion section  69  is an embedded photodiode embedded in a semiconductor substrate. The photoelectric conversion section  69  receives incident light and generates signal charge in accordance with the illuminance. The polarity of signal charge may be positive or negative. 
     The transfer transistor  62  switches whether signal charge generated by the photoelectric conversion section  69  is to be transferred to the readout circuit  65 . Typically, the transfer transistor  62  is an FET. The transfer transistor  62  herein is an N-channel MOS transistor. 
     A control signal line  81  is connected to a control terminal that is an input of the transfer transistor  62 . The control signal line  81  is connected to the vertical scanning circuit  36 . The transfer transistor  62  is turned on or off by controlling a voltage level of the control signal line  81 . The voltage level is controlled by the vertical scanning circuit  36 . By turning on the transfer transistor  62 , signal charge generated by the photoelectric conversion section  69  is transferred to the charge accumulation section  41 . The charge accumulation section  41  is provided in an area including the transfer transistor  62  and an area between a control terminal of the signal detection transistor  24  and the reset transistor  28 . 
     In the illustrated example, the control terminal of the transfer transistor  62  is a gate. The same applies to the signal detection transistor  24 , the address transistor  26 , and the shutter gate transistor  61 . 
     The readout circuit  65  detects an electric signal generated by the photoelectric conversion section  69  and transferred to the charge accumulation section  41 . As illustrated, the control terminal of the signal detection transistor  24  is connected to an output (one of source and drain) of the transfer transistor  62 . A source of the signal detection transistor  24  is connected to a vertical signal line  47  through the address transistor  26 . The address control line  46  is connected to the control terminal of the address transistor  26 . The address transistor  26  is turned on or off under control of the vertical scanning circuit  36  through the address control line  46 . 
     During the operation of the imaging device  200 , the signal detection transistor  24  amplifies and outputs the voltage applied to the control terminal thereof, that is, the voltage of the charge accumulation section  41 . The signal amplified by the signal detection transistor  24  is selectively read out as a signal voltage through the address transistor  26  and the vertical signal line  47 . 
     The shutter gate transistor  61  is a shutter gate transistor for the photoelectric conversion section  69 . The control terminal of the shutter gate transistor  61  is connected to a shutter gate control line  82  connected to the vertical scanning circuit  36 . Thus, the vertical scanning circuit  36  can turn on or off the shutter gate transistor  61 . By turning on the shutter gate transistor  61 , charge in the photoelectric conversion section  69  is reset, and while the shutter gate transistor  61  is in the on state, a photoelectric conversion operation of the photoelectric conversion section  69  can be stopped. While the shutter gate transistor  61  is in the off state, the photoelectric conversion section  69  is not reset, and a photoelectric conversion operation of the photoelectric conversion section  69  can be performed. 
       FIG. 16A  is part of a timing chart illustrating an example of the operation of the imaging device  200  according to the fourth embodiment. The chart below the block arrow in  FIG. 16B  is an enlarged view of part of  FIG. 16A . In the part above the block arrow in  FIG. 16B , part of  FIG. 3B  is illustrated again. 
     This timing chart example according to the fourth embodiment is obtained by replacing the graph (c) in  FIG. 3A  with graphs (c 1 ) and (c 2 ) in  FIG. 16A . 
     In  FIG. 16A , the graph (c 1 ) illustrates an example of a temporal change of a voltage Vtr of the control terminal of the transfer transistor  62 , and the graph (c 2 ) illustrates an example of a temporal change of a voltage Vrst of the control terminal of the shutter gate transistor  61 . 
     In the example in  FIG. 16A , the voltage Vtr changes between a voltage Vtr_on and a voltage Vtr_off, While the voltage Vtr is at the voltage Vtr_on, the transfer transistor  62  is maintained in the on state. While the voltage Vtr is at the voltage Vtr_off, the transfer transistor  62  is maintained in the off state. The voltage Vtr on is higher than the voltage Vtr_off. 
     The voltage Vrst changes between a voltage Vrst_on and a voltage Vrst_off. While the voltage Vrst is at the voltage Vrst_on, the shutter gate transistor  61  is maintained in the on state. While the voltage Vrst is at the voltage Vrst_off, the shutter gate transistor  61  is maintained in the off state. The voltage Vrst_on is higher than the voltage Vrst_off. 
     In the example in  FIG. 16A , as understood from comparison between  FIG. 16B  and  FIG. 3B , while the voltage Vb of the counter electrode  12  in  FIG. 3A  is at the voltage V 1 , the voltage Vtr is maintained at the voltage Vtr_on. During this period, the voltage Vrst is maintained at the voltage Vrst_off. While the voltage Vb of the counter electrode  12  in  FIG. 3A  is at the voltage V 2 , the voltage Vtr is maintained at the voltage Vtr_off. During this period, the voltage Vrst is maintained at the voltage Vrst_on. 
     With the voltage Vtr and the voltage Vrst illustrated in  FIG. 16A , as in a case where the voltage Vb according to the first embodiment illustrated in  FIG. 3A  is employed, the high-sensitivity exposure period and the low-sensitivity exposure period are generated. 
     Now, the low-sensitivity exposure period according to the fourth embodiment will be described. In the following situation, the voltage Vrst and the voltage Vtr are maintained at the voltage Vrst_on and the voltage Vtr_off, respectively, during the low-sensitivity exposure period. Ideally, in this situation, charge generated in the photoelectric conversion section  69  does not move to the charge accumulation section  41 , and the sensitivity is zero. Such a period during which the sensitivity is zero may correspond to the low-sensitivity exposure period according to the fourth embodiment. On the other hand, if intense light, such as sunlight, is incident on the photoelectric conversion section  69 , charge generated in the photoelectric conversion section  69  may flow out, and the flown-out charge may move to the charge accumulation section  41 . In addition, in the above case, light incident on the charge accumulation section  41  may be subjected to photoelectric conversion, and charge may be generated. The sensitivity generated in this manner is typically called parasitic light sensitivity. In the fourth embodiment, the period during which the parasitic light sensitivity is generated may also correspond to the low-sensitivity exposure period. 
     In the example in  FIG. 16A , the voltage Vrst is maintained at the voltage Vrst_off while the voltage Vtr is at the voltage Vtr_on, and is maintained at the voltage Vrst_on while the voltage Vtr is at the voltage Vtr_off. In other words, the shutter gate transistor  61  is turned on at timing when the transfer transistor  62  is turned off, and is turned off at timing when the transfer transistor  62  is turned on. That is, the voltage Vtr and the voltage Vrst are controlled such that the transfer transistor  62  and the shutter gate transistor  61  are complementarily turned on and off. 
     However, the voltage Vtr and the voltage Vrst are not necessarily controlled such that the transfer transistor  62  and the shutter gate transistor  61  are complementarily turned on and off. That is, the period during which the voltage Vtr is at the voltage Vtr_on does not necessarily correspond with the period during which the voltage Vrst is at the voltage Vrst_off. The period during which the voltage Vtr is at the voltage Vtr_off does not necessarily correspond with the period during which the voltage Vrst is at the voltage Vrst_on. The timing when the transfer transistor  62  is turned off does not necessarily correspond with the timing when the shutter gate transistor  61  is turned on. The timing when the transfer transistor  62  is turned on does not necessarily correspond with the timing when the shutter gate transistor  61  is turned off. 
     The technique of this embodiment can be expressed as follows. The imaging device  200  includes a semiconductor substrate and the photoelectric conversion section  69 . The photoelectric conversion section  69  is an embedded photodiode that is embedded in the semiconductor substrate. 
     Specifically, the imaging device  200  includes the shutter gate transistor (hereinafter also referred to as first transistor)  61 , the charge accumulation section  41 , and the transfer transistor (hereinafter also referred to as second transistor)  62 . The first transistor  61  resets the embedded photodiode. The charge accumulation section  41  accumulates charge generated by the embedded photodiode. The second transistor  62  transfers charge from the embedded photodiode to the charge accumulation section  41 . The high-sensitivity exposure period is a period from turning off of the first transistor  61  until turning off of the second transistor  62 . The low-sensitivity exposure period is a period from turning off of the second transistor  62  until turning off of the first transistor  61 . In the example in  FIG. 15 , the first transistor  61  corresponds to the shutter gate transistor  61 , and the second transistor  62  corresponds to the transfer transistor  62 . 
     First Reference Embodiment 
     The above-described change of the duty ratio an achieve both a low sensitivity and a high sensitivity. In addition, the change of the duty ratio can be combined with the technique advantageous in maintaining the image quality described in the above embodiments. This combination can lead to the following technique according to a first reference embodiment. 
     According to the first reference embodiment, the imaging device  100  includes the pixel array PA. The control mode of the imaging device  100  includes a first mode in which the first frame is generated. The duty ratio in the first mode is changed such that a state in which a first condition, a second condition, and a third condition are satisfied is maintained before and after the change. The first frame herein is a frame in which the first period, the third period, and the second period appear in this order. Each of the first period and the second period is one of the high-sensitivity exposure period and the low-sensitivity exposure period. The third period is the other of the high-sensitivity exposure period and the low-sensitivity exposure period. The first condition is a condition that pixel signal readout is performed on a first row in the pixel array PA during the first period. The second condition is a condition that pixel signal readout is performed on a second row in the pixel array PA during the second period. The third condition is a condition that no pixel signal readout is performed in the rows in the pixel array PA during the third period. The duty ratio is a ratio of the total period of the high-sensitivity exposure period in the first frame to the first frame period. 
     In the first reference embodiment, as understood from the first condition, the second condition, and the third condition, pixel signal readout is not performed during both the first period and the third period or both the second period and the third period. in this case, as understood from the description of the first embodiment, the image quality is likely to be maintained. Furthermore, in the reference embodiment, the duty ratio is changed such that the state in which the first condition, the second condition, and the third condition are satisfied is maintained. By changing the duty ratio, a high sensitivity can be obtained, and a low sensitivity can be obtained. 
     From the above reasons, the technique according to the first reference embodiment is suitable for obtaining a high sensitivity while maintaining the image quality. The technique according to the first reference embodiment is also suitable for obtaining a low sensitivity while maintaining the image quality. 
     For example, by changing the duty ratio, a P frame and a Q frame that correspond to the first frame and that have different duty ratios can be generated. For example, the first frame illustrated in  FIG. 3A  can be considered as the P frame. The first frame illustrated in  FIG. 5A  can be considered as the Q frame. 
     In the first frame illustrated in  FIG. 3A  and  FIG. 5A , each of the first period and the second period is the high-sensitivity exposure period, and the third period is the low-sensitivity exposure period. However, each of the first period and the second period may be the low-sensitivity exposure period, and the third period may be the high-sensitivity exposure period. 
     The technique of the first reference embodiment may be combined as appropriate with the technique of any other embodiments. 
     The imaging device according to any of embodiments of the present disclosure is applicable to various camera systems and sensor systems such as a digital still camera, a medical camera, a surveillance camera, an in-vehicle camera, a digital single-lens reflex camera, and a digital mirrorless single-lens camera.