Patent Publication Number: US-11392701-B2

Title: Information processing apparatus and method for controlling the same

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to an information processing apparatus and a method for controlling the same. 
     Description of the Related Art 
     Conventionally, as a boot code alteration detection method of an information apparatus such as an image processing apparatus (to be referred to as an MFP hereinafter) or the like, there is a method of verifying whether a boot code has been altered by causing a sub CPU to read out the boot code to be executed by a main CPU before the main CPU is activated. If the sub CPU detects that the boot code obtained from the readout has been altered, recovery will be performed by copying a master boot code onto the boot code detected to have been altered or error control will be performed to stop the operation of the sub CPU. For example, Japanese Patent Laid-Open No. 2017-33149 proposes a technique in which a CPU verifies designated software and will set the verified designated software as the software to be used by the processor at the time of activation, but will safely update software that has been detected to have been altered. 
     However, the conventional technique described above has the following problem. In general, for example, in a case in which another controller (for example, a function controller that controls functions of the apparatus) is included separately from a main CPU, the function controller will operate based on another CPU which is different from the main CPU. If a program code such as an activation code, an execution code, or the like of the other CPU is altered, the function control operation cannot be performed, and the reliability of the apparatus will degrade. 
     SUMMARY OF THE INVENTION 
     The present invention enables realization of secure activation of an apparatus by suitably verifying the safety of a program code which is to be executed by a controller different from a main CPU of the apparatus. 
     One aspect of the present invention provides an information processing apparatus comprising: a first controller that executes a first program code; a second controller that executes a second program code different from the first program code, and communication with the first controller; a storage device that stores the first program code to be executed by the first controller and the second program code to be executed by the second controller; and a verifier that verifies, before the first controller and the second controller execute respective program codes, the respective program codes, stored in the storage device. 
     Another aspect of the present invention provides an information processing apparatus comprising: a first controller that executes a first program code; a second controller that executes a second program code different from the first program code, and communication with the first controller; a first storage device that stores the first program code to be executed by the first controller; a second storage device that stores the second program code to be executed by the second controller; and a verifier that verifies, before the first controller and the second controller execute respective program codes stored in the first storage device and the second storage device, the respective program codes stored in the first storage device and the second storage device. 
     Still another aspect of the present invention provides an information processing apparatus comprising: a first controller that executes a first program code; a second controller that executes a second program code different from the first program code, and communication with the first controller; a first storage device that stores the first program code to be executed by the first controller; a second storage device that stores the second program code to be executed by the second controller; a first verifier that verifies the first program code stored in the first storage device before the first controller executes the first program code stored in the first storage device; and a second verifier that verifies the second program code stored in the second storage device before the second controller executes the second program code stored in the second storage device. 
     Yet still another aspect of the present invention provides a method for controlling an information processing apparatus that includes a first controller that executes a first program code, a second controller that executes a second program code different from the first program code, and communication with the first controller, and a storage device that stores the first program code to be executed by the first controller and the second program code to be executed by the second controller, the method comprising: verifying, before the first controller and the second controller execute respective program codes, the respective program codes, stored in the storage device. 
     Still yet another aspect of the present invention provides a method for controlling an information processing apparatus that includes a first controller that executes a first program code, a second controller that executes a second program code different from the first program code, and communication with the first controller, a first storage device that stores the first program code to be executed by the first controller, and a second storage device that stores the second program code to be executed by the second controller, the method comprising; verifying, before the first controller and the second controller execute respective program codes stored in the first storage device and the second storage device, respectively, the respective program codes stored in the first storage device and the second storage device. 
     Yet still another aspect of the present invention provides a method for controlling information processing apparatus that includes a first controller that executes a first program code, a second controller that executes a second program code different from the first program code, and communication with the first controller, a first storage device that stores the first program code to be executed by the first controller, and a second storage device that stores the second program code to be executed by the second controller, the method comprising: verifying the first program code stored in the first storage device before the first controller executes the first program code stored in the first storage device; and verifying the second program code stored in the second storage device before the second controller executes the second program code stored in the second storage device. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments (with reference to the attached drawings). 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing the arrangement of an MFP according to one embodiment; 
         FIG. 2  is a block diagram showing the arrangement of a main CPU according to one embodiment; 
         FIG. 3  is a block diagram showing the arrangement of a sub CPU according to one embodiment; 
         FIG. 4  is a block diagram showing the arrangement of an HDD controller according to one embodiment; 
         FIG. 5  is a view showing a memory map of a flash ROM according to one embodiment; 
         FIG. 6A  is a flowchart showing processing of the sub CPU according to one embodiment; 
         FIG. 6B  is a flowchart showing the processing of the sub CPU according to one embodiment; 
         FIG. 7  is a flowchart showing processing of a CPU of the HDD controller according to one embodiment; 
         FIG. 8  is a block diagram of an MFP of one embodiment; 
         FIG. 9  is a memory map of a flash ROM of a sub CPU according to one embodiment; 
         FIG. 10  is a flowchart showing processing of the sub CPU according to one embodiment; 
         FIG. 11  is a flowchart showing processing of a main CPU according to one embodiment; and 
         FIG. 12  is a timing chart showing the timings of reset signals according to one embodiment. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Hereinafter, embodiments will be described in detail with reference to the attached drawings. Note, the following embodiments are not intended to limit the scope of the claimed invention. Multiple features are described in the embodiments, but limitation is not made an invention that requires all such features, and multiple such features may be combined as appropriate. Furthermore, in the attached drawings, the same reference numerals are given to the same or similar configurations, and redundant description thereof is omitted. 
     Note that a multi-function peripheral (MFP) will be exemplified as an information processing apparatus according to an embodiment. However, the application range of the present invention is not limited to a multi-function peripheral. The present invention is applicable as long as it is an information processing apparatus. Note that, unless otherwise mentioned, the present invention is applicable, as a matter of course, to a single device or a system formed by a plurality of devices as long as the function of the present invention can be executed. 
     First Embodiment 
     &lt;Arrangement of Information Processing Apparatus&gt; 
     The first embodiment of the present invention will be described hereinafter. The arrangement of an MFP  1  according to this embodiment will be described with reference to  FIG. 1 . The MFP  1  mainly includes a main CPU  101 , a DRAM  102 , an operation unit  103 , a network OF  104 , a printer unit  105 , a scanner unit  106 , a FAX  107 , an image processor  111 , a flash ROM  112 , an operation unit OF  113 , and a sub CPU  115 . In addition, the MFP  1  includes a power supply controller  118 , a reset circuit  122 , an HDD controller  124 , and an HDD  125 . 
     The main CPU  101  is a first controller and controls the overall MFP  1 . The DRAM (Dynamic Random Access Memory)  102  stores program codes to be executed by the main CPU  101 , and functions as a work area for temporary data. 
     The operation unit  103  notifies, via the operation unit OF  113 , the main CPU  101  of an operation by a user. The network I/F  104  connects to a LAN  130  to control communication with an external device. The printer unit  105  is an image formation unit that prints image data on the surface of a paper sheet. The scanner unit  106  is a reading unit that optically reads an image on the surface of a paper sheet and converts the read image into an electrical signal to generate a scan image. The FAX  107  connects to a public line  110  to perform facsimile communication with an external device. 
     The HDD  125  is a non-volatile storage device, stores program codes to be executed by the main CPU  101  via the HDD controller  124 , and is used as a spooling area for a print job, a scan job, and the like. The HDD controller  124  is a second controller that controls a load (HDD). This HDD controller  124  functions as a bridge between the main CPU  101  and the HDD  125  by communicating with the main CPU  101  and controlling data input to and data output from the HDD  125  in accordance with a control command from the main CPU  101 . A program code (an HDD CPU BIOS FW  507 ) to be executed by a CPU (a CPU core  401 ) of the HDD controller  124  is stored in the flash ROM  112  and is a program that allows the HDD controller to function as a bridge between the main CPU  101  and the HDD  125 . That is, the HDD controller  124  transfers data transmitted by the main CPU  101  to the HDD  125  and transfers data read out from the HDD  125  to the main CPU  101 . The communication between the main CPU  101  and the HDD  125  is controlled by this function. This function is implemented when the CPU core  401  (to be described later) executes the HDD CPU BIOS FW  507 . Also, the HDD CPU BIOS FW  507  includes a program code for encrypting and decrypting data, and the CPU core  401  encrypts and decrypts data to be exchanged between the main CPU  101  and the HDD  125  in accordance with the program code. A reset signal  129  is output from a GPIO port of the sub CPU  115  and is connected to the HDD controller  124  for reset processing. Hence, the sub CPU  115  and the HDD controller  124  can be connected by a signal line for transmitting a reset signal. Note that although an HDD controller that performs the role of a bridge between the main CPU and the HDD will be exemplified as the second controller for controlling the load in this embodiment, the present invention is not limited to this, and it may be a controller for controlling another load. For example, it may be an engine controller for a printer, a scanner, or the like, a power supply controller, a network controller, or the like. 
     Communication is performed by connecting the modules to each other by a signal bus  109 . The FAX  107  and an external device are connected to each other by the public line  110 . The image processor  111  executes processing to convert a print job received via the network OF  104  into image data suitable for printing by the printer unit  105  and processing operations such as noise removal, color space conversion, rotation, compression, and the like on a scanned image read by the scanner unit  106 . The image processor also executes image processing on a scanned image stored in the HDD  125 . 
     The flash ROM (flash Read Only Memory)  112  is a first storage device and stores programs that include a boot code to be executed by the main CPU  101  and default setting values of the MFP  1 . The operation unit  103  and the signal bus  109  are connected to each other by the operation unit OF  113 . The main CPU  101 , the flash ROM  112  and the sub CPU  115  are connected to each other by a SPI (Serial Peripheral Interface) bus  114 . 
     The sub CPU  115  is a verifier that reads out the boot code from the flash ROM  112  to verify the corresponding program before the main CPU  101  is activated at the time of activation of the MFP  1 . Program verification according to this embodiment is an operation performed to verify whether a predetermined program code has changed due to intentional alteration or deterioration over time. Note that although the term “alteration” will be used in the description hereinafter for the sake of descriptive convenience, assume that the term “alteration” according to this embodiment also includes change due to deterioration over time in addition to the intentional alteration as described above. As a verification method, for example, public key information (a value obtained by performing public key encryption on a hash value) of a digital signature of a boot code will be stored in an OTP (One Time Programmable) memory area  304  (to be described later), in the sub CPU  115  at the time of manufacture. The sub CPU  115  decrypts the boot code which has been read out by using this public key information to perform verification. RSA  2048 , ECDSA, or the like can be used as the public key encryption method. Note that, as shown in  FIGS. 1 and 3 , the sub CPU  115  is a microcomputer independent of the main CPU  101 , and is a microcomputer that supports secure boot and stores its own boot code in a boot ROM  310 . Also, the incorporated OTP memory area  304  described above is an area that is not rewritable, and data stored in the OTP memory area  304  cannot be altered. 
     A reset signal  117  is output from the GPIO port of the sub CPU  115 , and a dedicated signal line is connected to a reset terminal of the main CPU  101 . The power supply controller  118  controls power supply to each module in the MFP  1 . A power supply line  119  is used to supply power to each module. A commercial AC power supply is supplied to a power supply line  120 . When the system is powered on, the reset circuit  122  shifts a sub CPU reset signal  123  from “Lo” level to “Hi” level after a predetermined delay time has elapsed. The sub CPU reset signal  123  is output from the reset circuit  122  and is connected to the reset terminal of the sub CPU  115 . When the sub CPU reset signal  123  shifts to “Hi” level, a reset state is canceled in the sub CPU  115 , and the activation of the sub CPU  115  is started. 
     &lt;Arrangement of Main CPU&gt; 
     The arrangement of the main CPU  101  according to this embodiment will be described with reference to  FIG. 2 . The main CPU  101  includes a CPU core  201  and an SPI master  202 . 
     The CPU core  201  is in charge of the basic functions of the CPU. The SPI master  202  connects to an external SPI device and performs data read and write. The SPI master  202  and the external SPI device are electrically connected to each other by an SPI bus  206 . Modules of the main CPU  101  are connected to each other by a signal bus  209 . The main CPU  101  is set in a reset state when the reset signal  117  output from the sub CPU  115  is at “Lo” level. On the other hand, the main CPU  101  is set to a reset canceled state when the reset signal  117  is at “Hi” level. When the reset signal  117  shifts from the reset state to the reset canceled state, the CPU core  201  first loads a main CPU BIOS  501  ( FIG. 5 ) stored in the flash ROM  112  to the DRAM  102  and executes the main CPU BIOS  501 . A detailed memory map of the flash ROM  112  will be described later with reference to  FIG. 5 . 
     &lt;Arrangement of Sub CPU) 
     The arrangement of the sub CPU  115  according to this embodiment will be described with reference to  FIG. 3 . The sub CPU  115  includes a CPU core  301 , an SPI master  302 , a GPIO  303 , the OTP memory area  304 , an SRAM  305 , an encryption processor  308 , the boot ROM  310 , and a Crypto RAM  311 . According to this embodiment, the sub CPU  115 , which supports secure boot, functions as a detector that detects an alteration by verifying the boot code (boot program) or the execution code (execution program) of each controller for controlling a load such as the main CPU  101 , the HDD controller  124 , or the like. These verification operations are performed before these controllers are activated, thus implementing secure boot. 
     The CPU core  301  is in charge of the basic functions of the CPU. The SPI master  302  connects to an external SPI device and performs data read and write. The GPIO (general-purpose input/output)  303  connects to an external device to perform data exchange. The OTP (One Time Programmable) memory area  304  is a memory area. In the OTP memory area  304 , a value obtained by encrypting the hash value of a sub CPU FW (firmware) by a public key and an address of tag indicating the start address of the sub CPU FW are written, at the time of manufacture, as verification information to be used in the verification. Once written, the data written in this area cannot be rewritten again. 
     The SRAM  305  is used as a work memory of the sub CPU  115 . The encryption processor  308  decrypts the hash value of the sub CPU FW from the value that has undergone public key encryption, and decrypts the hash value of the main CPU BIOS that has also undergone public key encryption. A signal bus  309  connects each module in the sub CPU. The boot ROM (Read Only Memory)  310  stores the boot code of the sub CPU  115 . The main CPU  101  is set in the reset state when the reset signal  117  is at “Lo” level. The main CPU  101  is set in the reset canceled state when the reset signal  117  is at “Hi” level. When the reset signal  117  shifts from the reset state to the reset canceled state, the CPU core  301  will first read out its own boot code from the boot ROM  310  and execute the boot code. The Crypto RAM  311  stores highly confidential data and the like to be used in the encryption processor  308 . 
     &lt;Anangement of HDD Controller&gt; 
     The arrangement of the HDD controller  124  according to the embodiment will be described next with reference to  FIG. 4 . The HDD controller  124  includes the CPU core  401 , an SPI master  402 , and transfer controllers  403  and  404 . 
     The CPU core  401  is in charge of the basic functions of the CPU for controlling the HDD controller  124 . The SPI master  402  connects to an external SPI device and performs data read and write. The transfer controllers  403  and  404  perform processing setting of the HDD  125  under the instruction of the CPU core  401 , and control data transfer to/from the HDD  125 . 
     In a readout operation of the HDD  125 , the CPU core  401  sets the settings in the transfer controller  404  for the read-access of the HDD  125 , and reads out the setting data from the HDD  125 . The data that has been read out is written to the DRAM  102  via a SATA interface bus  408 , the transfer controller  404 , an internal data bus  407  of the HDD controller  124 , the transfer controller  403 , and a data bus  405 . 
     In a write operation of the HDD  125 , the CPU core  401  sets the transfer controller  404  to write data on the HDD  125 . Subsequently, the write operation of the data transferred from the data bus  405  is performed on the HDD  125  via the transfer controller  403 , the internal data bus  407  of the HDD controller  124 , the transfer controller  404 , and the SATA interface bus  408 . 
     An SPI bus  406  electrically connects with an external SPI device. The modules of the HDD controller  124  are connected to each other by the internal data bus  407 . The HDD controller  124  is set to the reset state when the reset signal  129  is at “Lo” level. On the other hand, the HDD controller  124  is set to the reset canceled state when the reset signal  129  is at “Hi” level. When the reset signal  129  shifts from the reset state to the reset canceled state, the CPU core  401  first loads the HDD CPU BIOS FW  507  stored in the flash ROM  112  to the SPI master  402  and executes the HDD CPU BIOS FW. That is, the HDD CPU BIOS FW  507  is a program that allows the HDD controller  124  to function as a bridge between the main CPU  101  and the HDD  125 . 
     &lt;Memory Map&gt; 
     The memory map of the flash ROM  112  according to the embodiment will be described next with reference to  FIG. 5 . Note that the memory map to be described below is merely an example and is not intended to limit the present invention. That is, the stored information to be described below may be stored in a memory different from the flash ROM  112 . 
     The main CPU BIOS  501  stores codes (programs) to be executed by the main CPU  101 . A main CPU BIOS signature  502  stores an RSA signature value of the hash value of the main CPU BIOS  501 . A tag  503  stores the start address of a sub CPU FW  504 . The OTP memory area  304  stores the address of the tag  503  itself. 
     The sub CPU FW  504  stores codes to be executed by the sub CPU  115 . A FW signature  505  stores the sub CPU FW  504  or an ECDSA signature value of a specific part of the start address of the sub CPU FW  504 . A ROM-ID  506  stores the start address, the size, and the address of the BIOS signature of the main CPU BIOS  501 . The HDD CPU BIOS FW  507  stores the BIOS and the FW program code to be executed by the CPU core  401  of the HDD controller  124 . An HDD CPU BIOS FW signature  508  stores an RSA signature value of the hash value of the HDD CPU BIOS FW. 
     That is, the flash ROM  112  stores boot codes and execution codes to be executed by the main CPU  101  and the HDD controller  124 , and all of these codes have the potential to be altered. Hence, according to this embodiment, safer activation is implemented by using the sub CPU  115  supporting secure boot to verify the validity of a code to be executed by a corresponding controller before the execution of the code. The detailed processing of the sub CPU  115  will be described hereinafter. 
     &lt;Processing Procedure of Sub CPU  115 &gt; 
     The processing procedure of the sub CPU  115  according to this embodiment will be described next with reference to  FIGS. 6A, 6B, and 12 . The processing of the flowcharts shown in  FIGS. 6A and 6B  is started at a timing T 0  at which an MFP power supply  1201  is input in the timing chart shown in  FIG. 12 . 
     When the MFP  1  is powered on, in step S 701 , the CPU core  301  immediately reads out a code in the boot ROM  310  to the SRAM  305  and executes the code. The CPU core  301  loads, from the flash ROM  112  via the bus  114 , the sub CPU FW  504  and the FW signature  505  into the SRAM  305 . 
     Next, in step S 702 , the CPU core  301  causes the encryption processor  308  to decrypt the FW signature  505  by a public key in the OTP memory area  304  and obtain the correct hash value. Next, in step S 703 , the CPU core  301  causes the encryption processor  308  to calculate the hash value of the sub CPU FW  504 . Subsequently, in step S 704 , the CPU core  301  compares the hash value obtained in step S 502  with the hash value calculated in step S 703 . If the hash values do not match (NO), the processing ends. Otherwise (YES), the process advances to step S 705 , and the CPU core  301  loads the sub CPU FW  504  into the SRAM  305  and executes the sub CPU FW. 
     Next, in step S 706 , the CPU core  301  loads the ROM-ID  506  from the flash ROM  112  into the Crypto RAM  311 . Next, in step S 707 , the CPU core  301  obtains the address of the main CPU BIOS  501  and the address of the main CPU BIOS signature  502  from the ROM-ID  506 . 
     Next, in step S 708 , the CPU core  301  loads the main CPU BIOS signature  502  into the SRAM  305 . Next, in step S 709 , the CPU core  301  causes the encryption processor  308  to use the public key, which is attached to the sub CPU FW  504 , to decrypt the main CPU BIOS signature  502  and obtain the hash value. Subsequently, in step S 710 , the CPU core  301  loads the main CPU BIOS  501  into the SRAM  305 . In addition, in step S 711 , the CPU core  301  causes the encryption processor  308  to calculate the hash value of the main CPU BIOS  501 . 
     In step S 712 , the CPU core  301  compares the hash value obtained in step S 709  with the hash value obtained in step S 711 . If the hash values do not match (NO), the processing ends. Otherwise (YES), the process advances to step S 713 , and the CPU core  301  cancels the reset state by controlling the GPIO  303  to output the reset signal  117  at “Hi” level. At a timing T 1  of  1202  shown in  FIG. 12 , the reset signal  117  is canceled, and the main CPU  101  can be activated. 
     Next, in step S 714 , the CPU core  301  confirms whether there is a plurality of the ROM-IDs  506  obtained in step S 706 . If there are a plurality of ROM-IDs, the process advances to step S 715 . Otherwise, the processing ends. In step S 715 , the CPU core  301  obtains, from the flash ROM  112 , the address of the HDD CPU BIOS FW  507  and the address of the HDD CPU BIOS FW signature  508  which were not loaded in step S 707 . Next, in step S 716 , the CPU core  301  loads the HDD CPU BIOS FW signature  508  to the SRAM  305 . 
     Furthermore, in step S 717 , the CPU core  301  causes the encryption processor  308  to obtain a hash value by decrypting the HDD CPU BIOS FW signature  508  by using the public key attached to the sub CPU FW  504 . 
     Next, in step S 718 , the CPU core  301  loads the HDD CPU BIOS FW  507  to the SRAM  305 . Next, in step S 719 , the CPU core  301  causes the encryption processor  308  to calculate the hash value of the HDD CPU BIOS FW  507 . Subsequently, in step S 720 , the CPU core  301  compares the hash value obtained in step S 717  with the hash value obtained in step S 719 . If the hash values do not match (NO), the processing ends. Otherwise (YES), the process advances to step S 721 . In step S 721 , the CPU core  301  controls the GPIO  303  to output the reset signal  129  at “Hi” level. The reset signal  129  is canceled at a timing T 2  of  1203  shown in  FIG. 12 , and the CPU core  401  of the HDD controller  124  is activated. 
     &lt;Processing Procedure of HDD Controller&gt; 
     The processing procedure of the HDD controller  124  according to this embodiment will be described with reference to  FIG. 7 . After the reset signal  129  is canceled in step S 721  of  FIGS. 6A and 6B  described above, the processing of the CPU core  401  is started. 
     After the CPU core  401  has performed the BIOS verification and the reset state of the CPU core  401  has been canceled, the CPU core  401  immediately loads, in step S 801 , the HDD CPU BIOS FW  507  stored in the flash ROM  112 . The loading area in this case may be the DRAM  102  or a ROM (not shown) provided in the HDD controller  124 . Next, in step S 802 , the CPU core  401  executes the HDD CPU BIOS FW  507  that has been loaded, executes the initialization processing of inputs to/outputs from the CPU core  401 , and ends the processing. As a result, the HDD controller  124  is initialized and shifts to a state in which data exchange with the HDD  125  can be performed. 
     As described above, an information processing apparatus according to this embodiment includes a main CPU that executes processing in accordance with a program code and an HDD controller that controls communication with the main CPU and communication with a predetermined load in accordance with another predetermined program code. In addition, the information processing apparatus includes a flash ROM that stores program codes to be executed by the main CPU and the HDD controller. Furthermore, the information processing apparatus includes a sub CPU that verifies each program code stored in the flash ROM before the main CPU and the HDD controller execute their respective program codes. More specifically, the sub CPU first verifies the program code of the main CPU and cancels the reset signal to the main CPU, if an alteration is not detected, to activate the main CPU. Subsequently, the sub CPU verifies the program code of the HDD controller and cancels the reset signal output to the HDD controller if an alteration is not detected. As a result, according to this embodiment, the safety of a program code which is to be executed by a controller different from a main CPU can also be suitably verified, and secure activation of the apparatus can be implemented. 
     Note that the present invention is not limited to the above-described embodiment, and various modifications are possible. Although the above first embodiment described a case in which the code of the main CPU  101  and the code of the HDD controller  124  are stored in the same memory served by the flash ROM  112 , the respective codes may be stored in different memories as described below in the second embodiment. In such a case, the sub CPU  115  will verify codes stored in two memories. Note that in the second embodiment hereinafter will describe an example in which memories for storing codes to be executed by a plurality of CPUs will be arranged in correspondence with the plurality of CPUs, and sub CPUs for verifying the memories will be arranged in correspondence with the memories. 
     Second Embodiment 
     The second embodiment of the present invention will be described hereinafter. Although the above first embodiment described an example in which the sub CPU  115  integrally verifies the boot codes and the like of all of the controllers, boot code verification will be performed for each CPU of a plurality of CPUs in this embodiment. Note that unless otherwise mentioned, the present invention is applicable, as a matter of course, to a single device or a system formed by a plurality of devices as long as the function of the present invention can be executed. 
     &lt;Arrangement of Information Processing Apparatus&gt; 
     The arrangement of an MFP  1001  according to the embodiment will be described next with reference to  FIG. 8 . Note that the same reference numerals denote components and control processes similar to those of the above-described first embodiment hereinafter. 
     The MFP  1001  according to this embodiment includes, in addition to the components of the MFP  1  shown in  FIG. 1 , a sub CPU  1026  (second verifier) and a flash ROM  1027  (second storage device). When the system is powered on, a reset circuit  122  causes sub CPU reset signals  123  and  1023  to shift from “Lo” level to “Hi” level after a predetermined delay time has elapsed. The sub CPU reset signal  123  is output from the reset circuit  122  and is connected to the reset terminal of a sub CPU  115 . The reset state of the sub CPU  115  is canceled and activation is started when the sub CPU reset signal  123  is changed to “Hi” level. On the other hand, the sub CPU reset signal  1023  is connected to the reset terminal of the sub CPU  1026 . The reset state of the sub CPU  1026  is canceled and activation is started when the sub CPU reset signal  1023  is changed to “Hi” level. Note that the sub CPU  1026  has the same arrangement as the sub CPU  115 . That is, in this embodiment, a sub CPU that supports secure boot for verifying a boot code or an execution code is arranged in correspondence with each CPU (a main CPU  101  and an HDD controller  124 ). 
     The sub CPU  1026  verifies, at the activation of the MFP  1001 , whether an alteration has occurred by reading out a boot code from a flash ROM  1027 . As an alteration detection method, for example, public key information (a value obtained by performing public key encryption on a hash value) of a digital signature of a boot code will be stored in an OTP (One Time Programmable) memory area in the sub CPU  1026  at the time of production. The boot code that has been read out is decrypted by using this public key information to perform verification. RSA  2048 , ECDSA, or the like can be used as the public key encryption method. A reset signal  1029  is output from a GPIO port of the sub CPU  1026  and connected via a dedicated signal line to the HDD controller  124  for reset processing. The sub CPU  1026 , the flash ROM  1027 , and the HDD controller  124  are connected to each other by an SPI bus  1028 . 
     &lt;Memory Map&gt; 
     The memory map of the flash ROM  1027  will be described next with reference to  FIG. 9 . Note that the memory map to be described below is merely an example and is not intended to limit the present invention. That is, the stored information to be described below may be stored in a memory different from the flash ROM  1027 . In addition, the stored information to be described below is information to be stored in the flash ROM  1027  in place of a flash ROM  112 , that is, is information which will not be stored in the flash ROM  112 . 
     An HDD CPU BIOS FW  1101  stores a code to be executed by a CPU core  401  of the HDD controller  124 . An HDD CPU BIOS FW signature  1102  stores an RSA signature value of a hash value of the HDD CPU BIOS FW  1101 . A tag  1103  stores the start address of a sub CPU FW  1104 . The address of the tag  1103  itself is stored in an OTP memory area  304  of the sub CPU  1026  described in  FIG. 3 . 
     The sub CPU FW  1104  stores a code to be executed by the sub CPU  1026 . An FW signature  1105  stores the sub CPU FW  1104  or an ECDSA signature value of a specific part of the start address of the sub CPU FW  1104 . A ROM-ID  1106  stores the start address, the size, the address of the HDD CPU BIOS FW signature of the main HDD CPU BIOS FW  1101 . 
     &lt;Processing Procedure of Sub CPU  1026 &gt; 
     The processing procedure of the sub CPU  1026  according to the embodiment will be described next with reference to  FIG. 10 . 
     When the MFP  1001  is powered on, a CPU core  301  of the sub CPU  1026  immediately reads out, in step S 1201 , the code in a boot ROM  310  to a SRAM  305  and executes the code. The CPU core  301  loads the sub CPU FW  1104  from the flash ROM  1027  to the SRAM  305  via the SPI bus  1028 . Next, in step S 1202 , the CPU core  301  causes an encryption processor  308  to obtain the correct hash value by decrypting the FW signature  1105  by using a public key of the OTP memory area  304 . Furthermore, in step S 1203 , the CPU core  301  causes the encryption processor  308  to calculate the hash value of the sub CPU FW  1104 . 
     Next, in step S 1204 , the CPU core  301  compares the hash value obtained in step S 1202  with the hash value calculated in step S 1203 . If the hash values do not match (NO), the processing ends. Otherwise (YES), the process advances to step S 1205 , and the CPU core  301  loads the sub CPU FW  1104  to the SRAM  305  and executes the sub CPU FW  1104 . Next, in step S 1206 , the CPU core  301  loads the ROM-ID  1106  from the flash ROM  1027  to a Crypto RAM  311 . 
     Furthermore, in step S 1207 , the CPU core  301  obtains, from a ROM-ID  506 , the address of the HDD CPU BIOS FW  1101  and the address of the HDD CPU BIOS FW signature  1102 . 
     Next, in step S 1208 , the CPU core  301  loads the HDD CPU BIOS FW signature  1102  to the SRAM  305 . Next, in step S 1209 , the CPU core  301  causes the encryption processor  308  to obtain the hash value by decrypting the HDD CPU BIOS FW signature  1102  by using the public key attached to the sub CPU FW  1104 . 
     Next, in step S 1210 , the CPU core  301  loads the HDD CPU BIOS FW  1101  to the SRAM  305 . Next, in step S 1211 , the CPU core  301  causes the encryption processor  308  to calculate the hash value of the HDD CPU BIOS FW  1101 . Subsequently, in step S 1213 , the CPU core  301  compares the hash value obtained in step S 1209  with the hash value obtained in step S 1211 . If the hash values match (YES), the process advances to step S 1214 . The CPU core  301  controls a GPIO  303  to output the reset signal  1029  at “Hi” level, and ends the processing. Otherwise (NO), the processing ends directly. 
     As described above, an information processing apparatus according to this embodiment includes a main CPU that executes processing in accordance with a program code and an HDD controller that controls communication with the main CPU and communication with a predetermined load in accordance with another predetermined program code. The information processing apparatus also includes a first ROM that stores a program code to be executed by the main CPU and a second ROM that stores a program code to be executed by the HDD controller. In addition, the information processing apparatus includes a sub CPU that verifies the program code stored in the first ROM before the program code is executed by the main CPU. Furthermore, the information processing apparatus includes a sub CPU that verifies the program code stored in the second ROM before the program code is executed by the HDD controller. In this manner, according to this embodiment, the sub CPU  115  and the sub CPU  1026  are used separately to detect a boot code alteration in the ROMs of a CPU core  201  and the CPU core  401  which are components of the main CPU and the HDD controller, respectively. Subsequently, boot code alteration detection is executed for each individual CPU, and, as a result, notification as to whether an alteration occurred can be performed. 
     Third Embodiment 
     The third embodiment of the present invention will be described hereinafter. This embodiment will describe control performed based on the verification result of a code to be executed by an HDD controller  124 . Note that, unless otherwise mentioned, the present invention is applicable, as a matter of course, to a single device or a system formed by a plurality of devices as long as the function of the present invention can be executed. 
     &lt;Processing Procedure of Main CPU  101 &gt; 
     The processing procedure of a main CPU  101  of a case in which the verification result of the HDD controller  124  indicates a mismatch according to this embodiment will be described with reference to  FIG. 11 . 
     In step S 901 , a CPU core  201  of the main CPU  101  immediately loads, upon canceling the reset state, a main CPU BIOS  501  stored in a flash ROM  112  to a DRAM  102 . Next, in step S 902 , the CPU core  201  executes the main CPU BIOS  501 , and initialization processing of inputs to/outputs from the main CPU  101  is executed. 
     Next, in step S 903 , the CPU core  201  confirms the verification result of the HDD controller  124 . If the verification result indicates a mismatch, the process advances to step S 907 . The CPU core  201  instructs an operation unit OF  113  to perform an error display operation of an HDD  125 , the error of the HDD  125  is displayed on an operation unit  103 , and the processing ends. As a result, the error display operation can be performed on the MFP when the verification result of the HDD controller  124  indicates a mismatch. 
     On the other hand, if the HDD  125  can be activated, the process advances to step S 904 . The CPU core  201  loads an OS (Operating System) from the HDD  125  to the DRAM  102  and performs activation in step S 905 . Next, in step S 906 , the CPU core  201  executes initialization processing of a printer unit  105 , a scanner unit  106 , a FAX  107 , an image processor  111 , a network OF  104 , and the operation unit  103  to shift to a state that allows operation as an MFP, and the processing ends. 
     As described above, a main CPU according to this embodiment will cause an operation unit of an information processing apparatus to perform an error display operation when a sub CPU fails to verify a program code to be executed by an HDD controller. According to this embodiment, boot code alteration verification of each ROM is performed by the main CPU  101  and a CPU core  401  which is a component of the HDD controller  124 . As a result, if it is determined that the CPU core  401  as a component of the HDD controller  124  has been altered, activation will be performed in only the main CPU  101  that has been determined not to have any problems in the alteration determination, and error notification of the apparatus can be performed. 
     Other Embodiments 
     Embodiment(s) of the present invention can also be realized by a computer of a system or apparatus that reads out and executes computer executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be referred to more fully as ‘non-transitory computer-readable storage medium’) to perform the functions of one or more of the above-described embodiment(s) and/or that includes one or more circuits (e.g., application specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiment(s), and by a method performed by the computer of the system or apparatus by, for example, reading out and executing the computer executable instructions from the storage medium to perform the functions of one or more of the above-described embodiment(s) and/or controlling the one or more circuits to perform the functions of one or more of the above-described embodiment(s). The computer may comprise one or more processors (e.g., central processing unit (CPU), micro processing unit (MPU)) and may include a network of separate computers or separate processors to read out and execute the computer executable instructions. The computer executable instructions may be provided to the computer, for example, from a network or the storage medium. The storage medium may include, for example, one or more of a hard disk, a random-access memory (RAM), a read only memory (ROM), a storage of distributed computing systems, an optical disk (such as a compact disc (CD), digital versatile disc (DVD), or Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like. 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2019-080470 filed on Apr. 19, 2019, which is hereby incorporated by reference herein in its entirety.