Patent Publication Number: US-8982924-B2

Title: Architectures and methods for code combiners

Description:
STATEMENT OF GOVERNMENT INTEREST 
     This invention was made with government support under Contract No. FA8802-09-C-0001 awarded by the Department of the United States Air Force. The government has certain rights in the invention. 
    
    
     BACKGROUND 
     Code division multiple access (CDMA) modulation techniques are used in various communications fields to allow multiple access (i.e., multiple data signals to be transmitted on a single channel). According to CDMA, each data signal is modulated with a pseudo-random code having a wider bandwidth than the data signal. The result is a spread-spectrum user signal or code. Different data signals to be transmitted on the same channel may utilize different pseudo-random codes. A receiver of a particular data signal may either have or may derive the pseudo-random code with which its respective data signal was modulated. The receiver may utilize the appropriate pseudo-random code to demodulate the user signal or code and derive the original data signal. User signals or codes modulated by pseudo-random codes not known to the receiver will appear as noise. 
     It is often desirable to amplify a CDMA signal composed of many individual user signals or codes (e.g., to transmit the signal). For example, a global positioning system (GPS) satellite may transmit a combination of multiple GPS signals. Also, for example, a mobile telephone base station may transmit a combination of multiple CDMA signals corresponding to different conversations or other data transactions. In many applications, highly linearized power amplifiers (LPA&#39;s) may be used to amplify signals comprising a combination of codes. LPA&#39;s generate an output signal with minimal distortion, however, suffer from poor power efficiency. When a higher power efficiency is required, high-power nonlinear power amplifiers (HPA&#39;s) may be used. HPA&#39;s, however, generate a large number of distortion terms that are present, along with the input signal, at the amplifier output. In addition, there is some loss in the signal power as a component of the amplifier output power is used up by the distortion terms. It is possible to minimize the distortion terms and associated output power loss by configuring the HPA with a larger output power back-off. This, however, also reduces DC-RF power conversion efficiency. 
     It is known to reduce HPA distortion by pre-combining CDMA codes prior to amplification according to a majority logic scheme. A majority logic combiner counts the number of codes at its input that have a value of +1 and −1 during any chip period. The output is set to which ever value (e.g., +1 or −1) occurs in a majority of the signals. Where M is the number of codes to be combined, the output of a majority logic combiner at any time k may be equal to +1 if the number of codes that take the value +1 is greater than or equal to (M+1)/2 and is equal to −1 otherwise. For example, Table 1 below shows a chart illustrating the output (v 0 ) of a majority logic combiner operating on three input codes (c 1 , c 2 , c 3 ): 
                     TABLE 1               Majority Logic Combiner Output                                                                    c 1     −1   −1   −1   −1   +1   +1   +1   +1       c 2     −1   −1   +1   +1   −1   −1   +1   +1       c 3     −1   +1   −1   +1   −1   +1   −1   +1       v 0     −1   −1   −1   +1   −1   +1   +1   +1                    
The output (v 0 ) may be provided to an HPA amplifier. Note that in a majority logic combiner, M must be odd to avoid the occurrence of a tie.
 
     Majority logic combining may allow HPA amplifiers to operate more effectively, however, the majority logic combining process itself may introduce distortion terms, which can be amplified by the HPA, leading to signal degradation. 
     SUMMARY 
     Various embodiments are directed to signum code combiners that combine a plurality of codes and have three possible logical outputs, +1, −1 and 0. For example, the output of the signum combiner may be +1 if the sum of the input signals is greater than zero; −1 if the sum of the input signals is less than zero and zero if the sum of the input signals is equal to zero. Various embodiments are also directed to signum combiners have various additional features including, for example, successive signal insertion signum combiners, signum combiners with interlacing, and weighted coefficient signum combiners. Various embodiments may also be directed to modulators for modulating signum combiner outputs according to any suitable modulation scheme including, for example, binary phase shift keying (BPSK) modulation and quadrature phase shift keying (QPSK) modulation. 
    
    
     
       DRAWINGS 
       Various embodiments of the present invention are described here by way of example in conjunction with the following figures, wherein: 
         FIG. 1  illustrates one embodiment of an architecture for utilizing a cascaded set of signum combiners to combine code groups of differing power. 
         FIG. 2  illustrates a block diagram of one embodiment of a signum combiner with interlacing. 
         FIG. 3  illustrates a block diagram of one embodiment of a two-stage weighted coefficients signum combiner. 
         FIG. 4  illustrates a block diagram of one embodiment of a binary phase shift keying (BPSK) modulator for modulating the output of a signum combiner. 
         FIG. 5  shows a block diagram of one embodiment of a quadrature phase shift keying (PQSK) modulator. 
         FIG. 6  shows one embodiment of an example computing device. 
     
    
    
     DESCRIPTION 
     Various embodiments are directed to signum code combiners that may decrease distortion and increase power efficiency and increase the number of potential output levels from two to three. For example, a signum combiner may generate an output according to (1) and (2) below, where c i,k , for i=1 to M represents the value of M input codes during a period k. The period k may be a chip period or other period indicating one cycle of the input codes.
 
 v   i,k   =c   1,k   +c   2,k   + . . . +c   M,k   (1)
 
 v   0,k =sgn( v   i,k )  (2)
 
The signum function is given by (3);
 
                     sgn   ⁡     (   x   )       =     {           1   ;     x   &gt;   0                 0   ;     x   =   0                   -   1     ;     x   &lt;   0                       (   3   )               
In (1) and (2), v i,k  is the sum of the M input codes for a chip period k and v 0,k  is the output for the chip period k. According to various embodiments, the signum combiner given by (1) and (2) may accept an even or an odd number of input codes M. When the number of input codes M is an odd number, the output of the signum combiner may be identical to that of a majority logic combiner, with only two possible logical outputs (+1 and −1). Accordingly, the distortion and power efficiency properties may also be the same. When the number of input codes is even, three logical outputs (+1, 0, −1) may be possible and, as demonstrated below, improvements in distortion and power efficiency may be realized. Table 2 illustrates a signum combiner output where the number of input codes M is four:
 
     
       
         
           
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Signum Combiner (M = 4) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
               
            
               
                 C 1   
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 −1 
                 +1 
                 +1 
                 +1 
                 +1 
                 +1 
                 +1 
                 +1 
                 +1 
               
               
                 C 2   
                 −1 
                 −1 
                 −1 
                 −1 
                 +1 
                 +1 
                 +1 
                 +1 
                 −1 
                 −1 
                 −1 
                 −1 
                 +1 
                 +1 
                 +1 
                 +1 
               
               
                 C 3   
                 −1 
                 −1 
                 +1 
                 +1 
                 −1 
                 −1 
                 +1 
                 +1 
                 −1 
                 −1 
                 +1 
                 +1 
                 −1 
                 −1 
                 +1 
                 +1 
               
               
                 C 4   
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
                 −1 
                 +1 
               
               
                 V 0   
                 −1 
                 −1 
                 −1 
                  0  
                 −1 
                  0 
                  0  
                 +1 
                 −1 
                  0 
                  0 
                 +1 
                  0 
                 +1 
                 +1 
                 +1 
               
               
                   
               
            
           
         
       
     
     When the number of input codes is even, a signum combiner may enjoy a reduction in distortion and an increase in power efficiency relative to a majority logic combiner. Before finding the distortion characteristics of a signum combiner, however, an analysis of the distortion characteristics of a majority logic combiner is first derived for comparison purposes. 
     In general, the output of the majority logic code combiner will have some positive cross correlation with all of the input codes representing the signal component as well as a distortion term that has zero cross correlation with all of the input codes. The amplitudes and powers of the various components may be obtained by cross-correlating the output with the input codes and the distortion terms of various orders. For example, where the number of codes M is equal to three, the output will have only the components of the input codes and the third order distortion term. Table 3 below shows the logic relationships between the input codes (c 1 , c 2 , c 3 ), the output (X 2 =v 0 ); and the third order distortion term equal to the product of c 1 , c 2 , c 3  and v 0 . 
                     TABLE 3                  Logic relationships between the majority       logic combiner output and various terms                                                 X 1  =               c 1     c 2     c 3     c 1  c 2  c 3     X 2  = v 0      X 1 X 2                                               −1   −1   −1   −1   −1   1       1   −1   −1   1   −1   −1       −1   1   −1   1   −1   −1       1   1   −1   −1   1   −1       −1   −1   1   1   −1   −1       1   −1   1   −1   1   −1       −1   1   1   −1   1   −1       1   1   1   1   1   1                    
Table 3 shows values for a single chip period. For convenience, therefore, the time index k is omitted from the code sequence c j,k . Because the codes are assumed to be random, all eight possible combinations of the input code symbols (c 1 , c 2 , c 3 ) are assumed to be equally likely. Therefore, the normalized cross correlation between the output v 0  and various terms may be obtained by element wise multiplication of the corresponding elements, summing these terms and dividing by the norm square of any particular column, which in this case, is eight. Accordingly, the cross correlations, denoted by the symbol &lt; &gt;, are given below:
 
&lt; v   0   ,c   1 &gt;[1−1+1+1+1+1−1+1]/8=0.5  (4a)
 
&lt; v   0   ,c   2 &gt;=0.5;&lt; v   0   ,c   3 &gt;=0.5  (4b)
 
&lt; v   0   ,X   1 &gt;=[1−1−1−1−1−1−1+1]/8=−0.5  (4c)
 
     To derive a closed form expression for the more general case of M terms, it may be observed from Table 3 that: 
     (5) X 1 =1 if the number of 1&#39;s is either 1 or 3
         X 1 =−1 if the number of 1&#39;s is either 0 or 2       

     (6) X 2 =1 if the number of 1&#39;s is either 2 or 3
         X 2 =−1 if the number of 1&#39;s is either 0 or 1
 
Accordingly,
       

     (7) X 1 =1 &amp; X 2 =1 if the number of 1&#39;s is 3
         X 1 =−1 &amp; X 2 =−1 if the number of 1&#39;s is 0
 
Therefore, X 1 ·X 2 =1 if and only if the number of 1&#39;s is either 0 or 3. The number of code combinations for which the total number of 1&#39;s is equal to 0 and 3 is equal to:
       

                         (         3           0         )     =   1     ;     ⁢     
     ⁢   and           (   8   )                 (         3           3         )     =   1           (   9   )               
Thus, X 1 ·X 2 =1 for 2 of the 8 possible code combinations, and is otherwise equal to −1. From this, it may be inferred that E[X 1 ·X 2 ]=[(1)·(2)+(−1)·(6)]/8=−0.5, which is the same as obtained by more direct computations in (4c).
 
     In a more general case of M codes, the n th  order term may be given by:
 
( n  odd) X   1   =c   i     1     ·c   i     2      . . . c   i     n     (10)
 
The indices i 1 , i 2 , . . . i n  are all distinct and may take values between 1 and M. In this case, X 1 =+1 if the number of +1&#39;s within the subsequence c i     1   , c i     2   , . . . c i     n    is an odd integer and X 1 =−1 if the number of −1&#39;s in the subsequence c i     1   , c i     2   , . . . , c i      n    is an even integer. Similarly, X 2 =+1 if the number of +1&#39;s in the complete code sequence is greater than M/2 and X 2 =−1 if the number of 1&#39;s in the complete code sequence is less than M/2. With the order n of the term odd, the number of terms I 1  for which X 1 =1 and X 2 =1 is given by:
 
                           I   1     =       ⁢         (         n           1         )     ⁢       ∑     i   =       ⌈     M   /   2     ⌉     -   1         M   -   n       ⁢     (           M   -   n             i         )         +       (         n           3         )     ⁢       ∑     i   =       ⌈     M   /   2     ⌉     -   3         M   -   n       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n           n         )     ⁢       ∑     i   =       ⌈     M   /   2     ⌉     -   n         M   -   n       ⁢     (           M   -   n             i         )                     =       ⁢       ∑       k   =   1       k   :   odd       n     ⁢       (         n           k         )     ⁢       ∑     i   =       ⌈     M   /   2     ⌉     -   k         M   -   n       ⁢     (           M   -   n             i         )                         (   11   )               
In (11) and in all of the following equations,
 
               (         N           m         )     =       0   ⁢           ⁢   if   ⁢           ⁢   m     &lt;     0   ⁢           ⁢   or   ⁢           ⁢   m     &gt;     M   ⁢           ⁢   or   ⁢           ⁢   N     &lt;   0           
by convention and the notation ┌x┐ denotes the minimum integer that is greater than or equal to x for any real x. Similarly, the number of terms I 2  for which X 1 =−1 and X 2 =−1 is given by:
 
                           I   2     =       ⁢         (         n           0         )     ⁢       ∑     i   =   0       ⌊     M   /   2     ⌋       ⁢     (           M   -   n             i         )         +       (         n           2         )     ⁢       ∑     i   =   0         ⌊     M   /   2     ⌋     -   1       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n             n   -   1           )     ⁢       ∑     i   =   0         ⌊     M   /   2     ⌋     -     (     n   -   1     )         ⁢     (           M   -   n             i         )                     =       ⁢       ∑       k   =   0       k   :   even         n   -   1       ⁢       (         n           k         )     ⁢       ∑     i   =   0         ⌊     M   /   2     ⌋     -   k       ⁢     (           M   -   n             i         )                         (   12   )               
In (12) the notation └x┘ denotes the maximum integer that is less than or equal to x for any real x. As the total number of terms (e.g., possible sequences) is 2 M , the expected value of X 1 X 2  is given by:
 
     
       
         
           
             
               
                 
                   
                     
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                                     I 
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                                     I 
                                     2 
                                   
                                 
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                                 M 
                               
                             
                           
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                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   Or 
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
             
               
                 
                   
                     E 
                     ⁡ 
                     
                       [ 
                       
                         
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                           1 
                         
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                               1 
                             
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                         2 
                         M 
                       
                     
                     - 
                     1 
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     Equations (15a)-(15c) below illustrate an example realization of Equations (11)-(14) above for the case where M=5 and n=3. 
                     I   1     =           (         3           1         )     ⁢       ∑     i   =   2     2     ⁢     (         2           i         )         +       (         3           3         )     ⁢       ∑     i   =   0     2     ⁢     (         2           i         )           =   7             (     15   ⁢   a     )                 I   2     =           (         3           0         )     ⁢       ∑     i   =   0     2     ⁢     (         2           i         )         +       (         3           2         )     ⁢       ∑     i   =   0     0     ⁢     (         2           i         )           =   7             (     15   ⁢   b     )                 E   ⁡     [       X   1     ⁢     X   2       ]       =           2   ⁢     (   14   )       32     -   1     =       -   1     /   8               (     15   ⁢   c     )               
In (15a)-(15c), ┌M/2┐=3. The number of terms of order n of the type X 1  given by (10) at the output of the code combiner is given by
 
     
       
         
           
             
               t 
               n 
             
             = 
             
               
                 ( 
                 
                   
                     
                       M 
                     
                   
                   
                     
                       n 
                     
                   
                 
                 ) 
               
               . 
             
           
         
       
     
     Table 4 below provides the number of terms t n , the amplitude of the terms a n , and the total power P n  in all the terms of order n, for M taking odd integer values between 3 and 9. The terms corresponding to n=1, of course, are the signal terms while all the other terms are the distortion terms. 
                     TABLE 4               The number of distortion terms and their amplitudes and powers                                                        M = 3                           N   1   3                   t n     3   1                   a n     0.5   −0.5                   P n     0.75   0.25                   M = 5                           N   1   3   5               t n     5   10   1               a n     0.375   −0.125   0.375               P n     0.7031   0.1563   0.1406               M = 7                           N   1   3   5   7           t n     7   35   21   1           a n     0.3125   −0.0625   0.0625   −0.3125           P n     0.6836   0.1367   0.0820   0.0977           M = 9                           N   1   3   5   7   9       t n     9   84   126   36   1       a n     0.2734   −0.0391   0.0234   −0.0391   0.2734       P n     0.6729   0.1282   0.0692   0.0549   0.0748                    
Table 5 shows the signal power to distortion ratio γ in dB obtained by dividing P 1  of Table 4 by the sum of power in all the distortion terms present at the output and represented by P n  with n&gt;1.
 
     
       
         
           
               
             
               
                 TABLE 5 
               
             
            
               
                   
               
               
                 Performance of the Majority Logic Combiner 
               
            
           
           
               
               
               
               
               
            
               
                 M 
                 P s  (W) 
                 P t  (W) 
                 P L  (dB) 
                 γ (dB) 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 3 
                 0.75 
                 1.0 
                 1.25 
                 4.77 
               
               
                 5 
                 0.7031 
                 1.0 
                 1.53 
                 3.74 
               
               
                 7 
                 0. 6836 
                 1.0 
                 1.65 
                 3.34 
               
               
                 9 
                 0.6729 
                 1.0 
                 1.72 
                 3.13 
               
               
                   
               
            
           
         
       
     
     As illustrated by Table 5, for the existing majority logic combiners, the maximum amount of power P s  corresponding to the signal is 75% of the total power, with the maximum possible power to distortion ratio being 4.77 dB, this for the case where M=3. This ratio decreases further as the number of codes M is increased. Implicitly, the cross-correlation properties of the codes are modified due to the presence of the distortion terms, leading to the degradation of receiver acquisition and tracking performance. 
     With the distortion performance of the existing majority logic combiners as a baseline, the distortion of a signum combiner with an even number of input codes may be found in a manner similar to that described above with respect to the majority logic combiner. As with the analysis of the majority logic converter above, c i     1   , c i     2   , . . . , c i     n    may represent the input codes, X 2  may represent the output v 0  and X 1  may represent a distortion of term of order n (n odd). 
     Given (2) above, the output X 2  may be given by (16a)-(16c) below: 
     (16a) X 2 =1 if the number of 1&#39;s in the complete input sequence&gt;M/2 
     (16b) X 2 =−1 if the number of 1&#39;s in the complete input sequence&lt;M/2 
     (16c) X 2 =0 if the number of 1&#39;s in the complete input sequence=M/2 
     The distortion term X 1  may be given by (17):
 
 X 1 =c   i     1     ·c   i     2      . . . c   i     n     (17)
 
In (17), the indices i 1 , i 2 , . . . , i n  are all distinct and may take values between 1 and M. This is in view of the fact that the terms for which i 1 , i 2 , . . . , i n  are not all distinct may reduce to terms of lower order with distinct indices due to the property that c i,k   2 =1 for all code indices i and time k. Accordingly:
 
     (18) X 1 =1 if the number of 1&#39;s within the subsequence
     c i     1   , c i     2   , . . . , c i     n    is an odd integer   

     (19) X 1 =−1 if the number of 1&#39;s within the subsequence
     c i     1     , c   i     2     , . . . , c   i     n    is an even integer
 
Because the signum function has odd symmetry, only terms of odd order n may be present at the output. Accordingly, the number of terms for which X 1  and X 2 =1 is given by (20):
   

                           I   1     =       ⁢         (         n           1         )     ⁢       ∑     i   =     M   /   2         M   -   n       ⁢     (           M   -   n             i         )         +       (         n           3         )     ⁢       ∑     i   =       M   /   2     -   2         M   -   n       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n           n         )     ⁢       ∑     i   =       M   /   2     -   n   +   1         M   -   n       ⁢     (           M   -   n             i         )                       =       ⁢       ∑       k   =   1       k   :   odd       n     ⁢       (         n           k         )     ⁢       ∑     i   =     max   ⁡     (         M   1     -   k     ,   0     )           M   -   n       ⁢     (           M   -   n             i         )             ;                 (   20   )                 M   1     =       M   /   2     +   1                             
Similarly, the number of terms I 2  for which X 1 =−1 and X 2 =−1 is given by (20a):
 
                           I   2     =       ⁢         (         n           0         )     ⁢       ∑     i   =   0         M   /   2     -   1       ⁢     (           M   -   n             i         )         +       (         n           2         )     ⁢       ∑     i   =   0         M   /   2     -   3       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n             n   -   1           )     ⁢       ∑     i   =   0         M   /   2     -   n       ⁢     (           M   -   n             i         )                     =       ⁢       ∑       k   =   0       k   :   even       n     ⁢       (         n           k         )     ⁢       ∑     i   =   0         M   /   2     -   1   -   k       ⁢     (           M   -   n             i         )                         (     20   ⁢   a     )               
The number of terms I 3  for which X 1 =1 and X 2 =−1 is given by (21):
 
                           I   3     =       ⁢         (         n           1         )     ⁢       ∑     i   =   0         M   /   2     -   2       ⁢     (           M   -   n             i         )         +       (         n           3         )     ⁢       ∑     i   =   0         M   /   2     -   4       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n           n         )     ⁢       ∑     i   =   0         M   /   2     -   1   -   n       ⁢     (           M   -   n             i         )                     =       ⁢       ∑       k   =   1       k   :   odd       n     ⁢       (         n           k         )     ⁢       ∑     i   =   0         M   /   2     -   1   -   k       ⁢     (           M   -   n             i         )                         (   21   )               
Finally, the number of terms I 4  for which X 1 =−1 and X 2 =1 is given by (22):
 
                           I   4     =       ⁢         (         n           0         )     ⁢       ∑     i   =       M   /   2     +   1         M   -   n       ⁢     (           M   -   n             i         )         +       (         n           2         )     ⁢       ∑     i   =       M   /   2     +   1   -   2         M   -   n       ⁢     (           M   -   n             i         )         +   …   +                     ⁢       (         n             n   -   1           )     ⁢       ∑     i   =       M   /   2     -   n   +   2         M   -   n       ⁢     (           M   -   n             i         )                     =       ⁢       ∑       k   =   0       k   :   even         n   -   1       ⁢       (         n           k         )     ⁢       ∑     i   =       M   /   2     +   1   -   k         M   -   n       ⁢     (           M   -   n             i         )                         (   22   )               
The cross-correlation between X 1  and X 2  may be given by (23):
 
 E[X   1   X   2 ]={(1)·( I   1   +I   2 )+(−1)·( I   3   +I   4 )}/2 M   (23)
 
Equation (23) may be derived by observing that there are total of terms and for all the remaining terms not accounted for in I 1 , I 2 , I 3 , and I 4  the product X 1 X 2 =0. Table 6 shows the distortion terms and amplitudes thereof for one embodiment of a signum combiner for different values of M.
 
                     TABLE 6               The number of distortion terms and their amplitudes        and powers (M even)                  M = 4                                         n   1   3                               t n     4   4                       a n     0.375   −0.125                       P n     0.5625   0.0625                         M = 6                                         n   1   3   5                           t n     6   20   6                   a n     0.3125   −0.0625   0.0625                   P n     0.5859   0.0781   0.0234                         M = 8                                         n   1   3   5   7                       t n     8   56   56   8               a n     0.2734   −0.0391   0.0234   −0.0391               P n     0.5981   0.0854    0.0308    0.0122                         M = 10                                         n   1   3   5   7   9                   t n     10   120   252   120   10           a n     0.2461   −0.0273   0.0117    −0.0117   0.0273           P n     0.6056   0.897   0.0346    0.0165   0.0075                         M = 12                                         n   1   3   5   7   9   11               t n     12   220   792   792   220   12       a n     0.2256   −0.0205   0.0068    −0.0049   0.0068   −0.0205       P n     0.6107   0.0925   0.0370    0.0189    0.0103   0.0050                    
Table 7 shows the signum combiner signal power P s  equal to P 1  in Table 6, the total output power P t  equal to sum of P n  over n, the loss in power equal to P L =10 log(P t /P s ) dB and the signal to distortion ratio γ=10 log(P s /(P t −P s )) dB for various values of M.
 
     
       
         
           
               
             
               
                 TABLE 7 
               
             
            
               
                   
               
               
                 Performance of the Signum Combiner 
               
            
           
           
               
               
               
               
               
            
               
                 M 
                 P s  (W) 
                 P t  (W) 
                 P L  (dB) 
                 γ (dB) 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 4 
                 0.5625 
                 0.625 
                 0.46 
                 9.54 
               
               
                 6 
                 0.5859 
                 0.6875 
                 0.69 
                 7.61 
               
               
                 8 
                 0.5981 
                 0.7266 
                 0.84 
                 6.68 
               
               
                 10 
                 0.6056 
                 0.7539 
                 1.23 
                 6.11 
               
               
                 12 
                 0.6107 
                 0.7744 
                 1.11 
                 5.7 
               
               
                 16 
                 0.617 
                 0.8036 
                 1.14 
                 5.19 
               
               
                 32 
                 0.6268 
                 0.8601 
                 1.37 
                 4.29 
               
               
                 64 
                 0.6317 
                 0.9007 
                 1.54 
                 3.7 
               
               
                   
               
            
           
         
       
     
     A comparison of Table 7 with Table 5 above demonstrates that the signum combiner provides an improved signal to distortion ratio (SDR) and power efficiency over the majority logic combiner. For example, for M=4 codes, the signum combiner has an SDR γ of 9.54 dB. The majority logic combiner has an SDR γ of 4.77 dB when M=3 and an SDR γ of 3.74 dB for M=5. The average SDR γ of the majority logic combiner between the case where M=3 and the case where M=5 is 4.25 dB. Compared with the SDR γ for the signum combiner when M=4, this represents an improvement of more than 5 dB. Also, the power loss to distortion P L  of the signum combiner when M=4 is equal to 0.46 dB, compared with majority logic combiner&#39;s 1.39 dB average between the M=3 and M=5 cases. Similarly, the power efficiency, defined as the ratio of P s  and P t  is equal to 90% with M=4 for the sigma combiner compared to 72.5% average for M=3 and M=5 for the majority logic combiner. As the power conversion efficiency of the high-power non-linear amplifier (HPA) with both the majority logic and signum combiners is about same, the signum combiner may result in a very significant overall power efficiency improvement. For example, with a 60% conversion efficiency of the HPA, the overall efficiency of the sigma combiner may be 54% (0.9 0.6 100%) compared to 43.5% for the majority logic combiner. These advantages may be obtained with about 1 dB reduction in the signal power P s . However, as shown in the following, the signal power P s  can be increased at the cost of a nominal reduction in the SDR which still remains relatively high. 
     In addition to the mathematical analysis presented, the performance of a signum combiner was also obtained utilizing a computer simulation developed in the MATLAB software package available from THE MATHWORKS. According to the simulation, a signum combiner with an output given by Equation (2) above was input with M random codes of length 8192. The amplitudes of the signal terms, denoted by a 1  were obtained by correlating the combiner output with the various input codes. Fifty simulations were run. Table 8 illustrates the averages of the amplitudes for various codes over the fifty simulations. 
                     TABLE 8                  Coefficients of the various signal components at the        signum combiner output                     M   Signal coefficients (V)                                                                 4   0.375   0.374   0.375   0.376                               6   0.312   0.311   0.313   0.312   0.314   0.312                       8   0.272   0.274   0.277   0.273   0.272    0.272   0.273   0.275               10   0.247   0.243   0.245   0.247   0.247   0.245   0.246   0.248   0.244   0.246                    
Table 9 shows the overall performance in terms of combiner power loss P L  and the signal to distortion power ratio γ.
 
                     TABLE 9                  Performance of the Signum Combiner by Simulations                                         M   P s  (W)   P t  (W)   P L  (dB)   γ (dB)                                                 4   0.56   0.62   0.46   9.51           6   0.59   0.6879   0.68   7.65           8   0.60   0.73   0.83   6.78           10   0.60   0.75   0.95   6.12           12   0.61   0.77   1.02   5.77           16   0.61   0.80   1.15   5.20           32   0.63   0.86   1.35   4.36           64   0.63   0.90   1.52   3.76                    
Comparing the results of tables 6 and 8 shows that the signal amplitude estimate obtained by simulation is very close to that predicted by theory. Similarly the comparison of the Tables 7 and 9 show that the results in terms of combiner power loss P L  and the signal to distortion power ratio γ obtained by theory and simulations are very close.
 
     The various signum code combiners described herein may be implemented by any suitable hardware and/or software combination. Also, for example, different architectures may utilize signum combiners in different ways. For example,  FIG. 1  illustrates one embodiment of an architecture  100  for utilizing a cascaded set of signum combiners to combine code groups of differing power. According to various embodiments, the architecture  100  and generalized versions thereof may be referred to as successive signal insertion signum combiners. In the embodiment illustrated by the architecture  100 , three code groups are received: CG 1 , CG 2 , CG 3 . Codes within a common group may have the same power level. Also, for code CG 1  may have the highest power, with CG 2  having a power less than or equal that of CG 1  and CG 3  having a power less than or equal to CG 2 . Each of the code groups CG 1 , CG 2 , CG 3  may be provided as input to respective signum combiners  102 ,  104 ,  106 . The output of the signum combiner  102  corresponding to the highest power code group (CG 1 ) may be provided as input to a logic converter  108 . The output of the logic converter  108  may provide a magnitude of its input. For example, if the output of the signum combiner  102  is equal to +1 or −1, the output of the logic converter  108  may be 1. If the output of the signum combiner  102  is equal to 0, then the output of the logic converter  108  may be 0. The output of the logic converter  108  may be provided to the inhibit input of a tri-state gate  110 , whose input is connected to the output of the signum combiner  104  corresponding to the next highest power code group (CG 2 ). Accordingly, the output of the tri-state gate  110  may be equal to zero when the signum combination of the CG 1  codes is equal to +1 or −1 and may be equal to the signum combination of the CG 2  codes when the signum combination of the CG 1  codes is equal to zero. 
     An additional signum combiner  112  may receive as input a signal  112   a  that is the output of the signum combiner  102 , corresponding to CG 1 , and a signal  112   b  that is the output of the tri-state gate  110 . The output of the signum combiner  112  may be provided to a logic converter  114 , which may operate in a manner similar to that of converter  108 . The output of the logic converter may be provided to a tri-state gate  116 . The input of the tri-state gate  116  may be the output of the signum combiner  106  corresponding to the next highest power code group (CG 3 ). An additional signum combiner  118  may receive as input a signal  118   a  corresponding to the output of the combination of the CG 1  and CG 2  codes (e.g., the output of the signum combiner  112 ). In addition, the combiner  118  may receive an input  118   b  that may be equal to 0 when the combination of CG 1  and CG 2  is equal to +1 or −1 and may be equal to the combination of CG 3  when the combination of CG 1  and CG 2  is equal to zero. The output of the combiner  118  may be the output of the architecture  100 . 
     The cascaded architecture  100  illustrated in  FIG. 1  may be expanded for an arbitrary number of code groups CG i  where i=1 to N. The power of each code group CG i  may decrease as i increases. The number of codes in each code group CG i  may be given by M i . In the general case, each code group would be initially combined by a signum combiner, such as the combiners  102 ,  104 ,  106  of the architecture  100 . Code group CG 1  may be combined with code group CG 2  utilizing the logic converter and tri-state gate logic shown in the architecture  100 . The combination of groups CG 1  and CG 2  may then be combined with the code group CG 3 , also using the logic converter and tri-state gate logic shown in the architecture  100 . This pattern may continue until all of the code groups CG i  where i=1 to N are combined. For example, the combination of groups CG 1  through CG i-1  may be combined with the group CG i  until all code groups (i=1 to N) are combined. Table 10 below shows the theoretical performance of successive signal insertion signum combiners for different numbers of code groups (N) having different numbers of signals (M). 
                     TABLE 10                  Successive Signal Insertion Combiner Performance                                                             M   N   M 1     M 2     M 3     P s (W)    P t (W)   P L (dB)   γ(dB)    α 1 (V)    α 2 (V)    α 3 (V)               8   2   4   4       0.64   0.86   1.27   4.69   0.375   0.140           6   2   2   4       0.64   0.81   1.03   5.72   0.500   0.188           6   2   4   2       0.63   0.81   1.09   5.45   0.375   0.186           8   3   4   2   2   0.65   0.91   1.42   4.10   0.375   0.187    0.094                    
In Table 10, α i  denotes the amplitude of the codes in the code group i for i=1, 2, . . . , N. Comparison with the case of equal power (Table 9) shows some increase in signal power P s  and a reduction in the signal to distortion ratio (SDR).
 
       FIG. 2  illustrates a block diagram of one embodiment of a signum combiner  200  with interlacing. The example combiner  200  is configured to receive as input N groups of codes (CG i  where i=1 to N). According to various embodiments, the codes within each group CG i  may have equal power. Each group CG i  may be combined at a first level signum combiner (e.g.,  202 ,  204 ,  206 ) generating outputs s 1 , s 2 , . . . , s N . These outputs are, in turn, combined by a signum combiner  208  generating an output s 0 . The outputs s 1 , s 2 , . . . , s N  may also be input to an interlace circuit  210 . The interlace circuit, at each discrete time instance, may select one of its inputs in a random manner with respective probabilities p 1 , p 2 , . . . , p N  and makes its output equal to the input selected in this manner. The probabilities p 1 , p 2 , . . . , p N  of the interlace circuit  210  may or may not be the same and, according to various embodiments, need not be non-zero and their sum may be smaller than 1. The output s 0  of the combiner  208  may be converted to a two-level output by a logic converter  212 . An output of the logic converter  212  may be provided to the inhibit input of a tri-state gate  214 . The other input of the tri-state gate  214  may be provided to the output i 0  of the interlace circuit  210 . Thus the output of the tri-state gate  214  may be equal to i 0  when s 0  is zero and may be equal to zero otherwise. The output i 0G  of the tri-state gate  214  may be combined with s 0  by the signum combiner  216 , providing output v 0.    
     Table 11 shows the performance of the combiner  200  shown in  FIG. 2  for an example with M=6, N=2, M 1 =4 and M 2 =2 with α 1  and α 2  denoting the amplitude of the Group 1 and Group 2 signals, respectively. 
                     TABLE 11                  Performance of Signum Combiner with Interlacing       (M = 6, N = 2, M 1  = 4, M 2  = 2)                                             p 1     p 2     P s (W)    P t (W)   P L (dB)   γ(dB)    α 1 (V)    α 2 (V)                                                     0   0   0.55   0.66   0.75   7.24   0.281   0.343       0.5   0   0.57   0.73   1.09   5.42   0.327   0.263       0.8   0   0.61   0.78   1.11   5.35   0.357   0.214       1   0   0.63   0.81   1.08   5.46   0.375   0.187       0   0.5   0.58   0.73   1.04   5.65   0.236   0.421       0   0.8   0.61   0.78   1.07   5.53   0.207    0.469       0   1   0.64   0.81   1.03   5.72   0.189   0.499                    
As may be inferred from Table 11, for a wide range of power distribution (e.g., power ratio among signals of up to 8.4 dB) between the two groups of signals, the SDR may lie between about 5.5 dB and 7.2 dB. Also, it can be seen that the result of the last row of Table 11 is very close to the result obtained by the successive insertion signum combiner  100  for the case M 1 =2 and M 2 =4 (e.g., two strong and four weak signals). For the case of equal power among M=6 signals, the SDR may be 7.65 dB from Table 9. This shows a penalty in SDR of up to about 2 dB depending upon the desired power ratio. The worst case power loss P L  for the combiner  200  shown in  FIG. 11  may be about 1.1 dB. Except for the first two rows of Table 11, however, the total signal power P s  is higher than for the case of equal power allocation among the M signals.
 
     According to various embodiments, it may be desirable to combine codes while assigning different weights to different codes. For example, for codes c 1 , c 2 , . . . , c n , a weighted coefficients signum combiner output may be given by (23):
 
 v 0=sgn(β 1   c   1 +β 2   c   2 + . . . +β n   c   n )  (23)
 
In (23), β 1 , β 2 , β n  may be the combiner weighting coefficients.  FIG. 3  illustrates a block diagram of one embodiment of a two-stage weighted coefficients signum combiner  300 . The combiner  300  may receive as input a set of code groups CG i  where i=1 to N. Each group of signals CG i  may be combined by first-stage combiners  302 ,  304 ,  306  to generate outputs s i  for i=1 to N. The outputs s 1 , s 2 , . . . , s N  may be input to the second stage weighted signum combiner  308 , which may generate an overall output v O . Each input to the combiner  308  may be scaled by a weighting factor β i . According to various embodiments, the first stage combiners  302 ,  304 ,  306  may also weight or scale different codes from the respective code groups CG i  differently.
 
     Table 12 shows the performance of the two stage weighted coefficients signum combiner, with N=2 and the number of signals in the two groups equal to M 1 =4, M 2 =2. The first stage combiners  302 ,  304 ,  306  may have all of their weights equal to 1 with the combiner weights of the second stage combiner  308  given by β 1  and β 2 . 
                     TABLE 12                  Performance of Weighted Coefficients Signum Combiner       (M = 6, N = 2, M 1  = 4, M 2  = 2)                                             β 1     β 2     P s (W)   P t (W)   P L (dB)    γ(dB)    α 1 (V)    α 2 (V)               2   3   0.64   0.81   1.03   5.71   0.188   0.499       1   1   0.55   0.66   0.74   7.29   0.280   0.340       3   2   0.63   0.81   1.08   5.47   0.375    0.188                    
As can be seen from Table 12, the power of the CG 1  codes relative to the CG 2  codes may vary between −8.5 dB and 6.0 dB for the range of coefficients β 1  and β 2  shown in the table. The SDR may lie between 5.5 dB and 7.3 dB for this range of variation.
 
     It will be appreciated that modulating the output of a signum combiner may be different than modulating the output of a majority logic or other code combiner, at least because the output of the signum combiner has three possible states (e.g., −1, +1 and 0) as compared to the typical two states (−1, +1). According to various embodiments, however, the output of a signum combiner may be modulated according to any suitable modulation scheme. For example,  FIG. 4  illustrates a block diagram of one embodiment of a binary phase shift keying (BPSK) modulator  400  for modulating the output of a signum combiner. A signum combiner  402  may combine a series of codes c i , for i=1 to n. The combiner  402  may be any suitable type of signum combiner including, for example, a successive insertion signum combiner, such as  100 , an interlaced signum combiner, such as  200 , or one or multiple stage weighted coefficients signum combiner, such as  300 . 
     The output v 0 (t) of the combiner  402  may be may be input to a square-root raised cosine filter  404  for band limiting. The resulting band limited signal v 0f (t) may be input to a BPSK modulator  410 , which may modulate the band limited signal v 0f (t) with a carrier signal  412  to generate a modulated signal v m (t) output. The output v 0 (t) of the signum combiner may also be input to a three-to-two level logic converter  406 . The output of the logic converter  406  may be 1 if the input is non-zero and 0 otherwise. The output of the logic converter  406  may be provided to a delay adjust  408  with a delay equal to that introduced by the filter  404 . The output of the delay adjust may be provided to a switch  416  which may control the DC voltage (provided by supply  414 ) to a power amplifier  418 . When the logic converter output is 1 (e.g., when v 0 (t) is −1 or 1), the switch  416  may be closed, allowing the amplifier  418  to amplify the modulated signal v m (t), resulting in the transmission of an RF signal, v RF (t). When the logic converter output is zero (e.g., when v 0 (t) is 0), the switch  416  may be open, preventing amplification of the modulated signal v m (t) and, therefore, also preventing transmission. It will be appreciated that the power supply switch  416  may lead to some small distortion as it may block any signal caused by adjacent symbols during the period when the signum combiner output is zero. Nonetheless, the overall system may provide increased power efficiency, as set forth above. 
     According to various embodiments the band limiting filter  404  and power supply switch  416  may be omitted. When the filter  404  is omitted, the output v m (t) of the modulator  410  may be zero when the combiner  402  output v 0 (t) is also zero. For some power amplifiers  418 , such as class B and class C amplifiers, there may be no conduction and, therefore, no transmission when the input is equal to zero. Accordingly, in embodiments where the filter  404  is omitted the power supply switch  416  may not be necessary. 
       FIG. 5  shows a block diagram of one embodiment of a quadrature phase shift keying (PQSK) modulator  500 . The input to the modulator  500  may comprise a set of in-phase codes c i  for i=1 to n, and a set of quadrature codes d i  for i=1 to m. The in-phase codes c i  may be combined at an in-phase signum combiner  502 , which may be any suitable type of signum combiner including, for example, any one of the combiners  100 ,  200 ,  300  described herein. The result may be an in-phase combined signal v i (t). Similarly, the quadrature codes d i  may be combined at quadrature combiner  504  to generate output v q (t). According to various embodiments, the quadrature combiner  504  and the in-phase combiner  502  may be of the same type. Also, it will be appreciated that the number of in-phase modulation n may not be equal to the number of quadrature modulation codes m. 
     The output v i (t) of the in-phase combiner  502  may be provided to a logic converter  506  having an output LC 1  equal to 1 if the input is nonzero and equal to zero otherwise. Similarly, the quadruature signum combiner  504  output v q (t) may be input to the logic converter  508  having an output LC 2  equal to 1 if the input is nonzero and equal to zero otherwise. The logic converter outputs LC 1  and LC 2  may be input to logic gates  512 ,  514 ,  516  generating outputs L 1 , L 2  and L 3 , respectively. L 1  may be 1 if and only if LC 1  is equal to 1 and LC 2  is equal to zero. L 3  may be equal to 1 if and only if both of the inputs LC 1  and LC 2  are equal to zero. Similarly, L 2  may be equal to 1 if LC 1  is equal to zero and LC 2  is equal to 1. The logic outputs L 1 , L 2  and L 3  may all equal zero if both LC 1  and LC 2  are equal to one. 
     The logic output L 1  may be provided to and may control a multiplier switch  518 . The multiplier switch  518  may provide an output v I (t) that is equal to v i (t) when L 1  is zero and is equal to the inphase combiner output v i (t) multiplied by √{square root over (2)} if L 1  is 1. Accordingly, when v i (t) is non zero and v q (t) is zero, the combiner output v i (t) may be multiplied by √{square root over (2)}. Similarly a multiplier switch  520  may generate an output v Q (t) that is equal to v q (t) when L 2  is zero and equal to v q (t) multiplied by √{square root over (2)} when v q (t) is nonzero and v i (t) is zero (e.g., when L 2  is equal to one). 
     The outputs v I (t), v Q (t) of the multiplier switches  518 ,  520  may be input to the QPSK modulator  522 , generating the QPSK modulated signal v m (t) at the modulator output. The QPSK modulated signal v m (t) may be input to the power amplifier  524 , generating the amplified signal v a (t). When both the inphase and quadrature signum combiner outputs v i (t) and v q (t) are zero, the logic output L 3  is 1 and the power supply switch  526  is turned to the ground position, disconnecting the DC power supply  528  from the power amplifier  524 . Thus no DC power is supplied to the amplifier during the period when both v i (t) and v q (t) are zero resulting in zero output at the QPSK modulator output and ensuring high DC to AC power conversion efficiency. For the usual class B and C amplifier designs, there is no conduction with the amplifier input equal to 0 and thus the power supply switch may not be required. Again, when class B and/or C amplifier designs are used for the power amplifier  524 , there may not be any conduction when the input v m (t) is equal to zero, and this the power supply switch  526  may be omitted. 
     The multiplication of the signum combiner outputs v i (t) and v q (t) by √{square root over (2)} in a manner described herein may ensure that the QPSK modulated signal v m (t) is a constant envelope signal when the dc power supply is ON and is zero otherwise. This may maximize the DC to RF power conversion efficiency of the power amplifier  524 . Such a multiplication by √{square root over (2)} may also result in a further improvement in terms of the transmitted signal power P s . For example, with n=4 codes at the input of the in-phase combiner  502  and m=4 codes at the input of the quadrature combiner  504 , the coefficients of the various code components present in the signal v I (t) are equal to 0.433 compared to 0.375 for the signum combiner without such modification as given by Table 6. Multiplication by √{square root over (2)} does not result in any increase in the peak envelope power at the amplifier input which is equal to A c  √{square root over (2)} with or without the multiplication by √{square root over (2)}. The corresponding power levels are P s =0.7534 W and P t =0.8599 W as compared to P s =0.5625 W and P t =0.625 W from Table 6. The signal-to-noise ratio γ is equal to 8.50 dB compared to 9.54 dB thus resulting in about 1 dB degradation. However, the increase in the signal power P s  by 1.27 dB is desirable as the signal-to-noise ratio γ equal to 8.50 dB is relatively high especially compared to the traditional majority logic combiner with γ equal to 4.77 dB and 3.74 dB for the number of codes equal to three and four respectively as per the results of Table 5. 
     It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating other elements, for purposes of clarity. Those of ordinary skill in the art will recognize that these and other elements may be desirable. However, because such elements are well known in the art and because they do not facilitate a better understanding of the present invention, a discussion of such elements is not provided herein. 
     In general, it will be apparent to one of ordinary skill in the art that at least some of the embodiments described herein may be implemented in many different embodiments of software, firmware, and/or hardware. The software and firmware code may be executed by a computer or computing device comprising a processor (e.g., a DSP or any other similar processing circuit), for example, the computing device  600  described below. The processor may be in communication with memory or another computer readable medium comprising the software code. The software code or specialized control hardware that may be used to implement embodiments is not limiting. For example, embodiments described herein may be implemented in computer software using any suitable computer software language type, using, for example, conventional or object-oriented techniques. Such software may be stored on any type of suitable computer-readable medium or media, such as, for example, a magnetic or optical storage medium. According to various embodiments, the software may be firmware stored at an EEPROM and/or other non-volatile memory associated a DSP or other similar processing circuit. The operation and behavior of the embodiments may be described without specific reference to specific software code or specialized hardware components. The absence of such specific references is feasible, because it is clearly understood that artisans of ordinary skill would be able to design software and control hardware to implement the embodiments based on the present description with no more than reasonable effort and without undue experimentation. 
       FIG. 6  shows an example of a computing device  600  according to one embodiment. For the sake of clarity, the computing device  600  is illustrated and described here in the context of a single computing device. However, it is to be appreciated and understood that any number of suitably configured computing devices can be used to implement a described embodiment. For example, in at least some implementations, multiple communicatively linked computing devices may be used. One or more of these devices can be communicatively linked in any suitable way such as via one or more networks. One or more networks can include, without limitation: the Internet, one or more local area networks (LANs), one or more wide area networks (WANs) or any combination thereof. 
     In the example of  FIG. 6 , the computing device  600  comprises one or more processor circuits or processing units  602 , one or more memory circuits and/or storage circuit component(s)  604  and one or more input/output (I/O) circuit devices  606 . Additionally, the computing device  600  comprises a bus  608  that allows the various circuit components and devices to communicate with one another. The bus  608  represents one or more of any of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. The bus  608  may comprise wired and/or wireless buses. The processing unit  602  may be responsible for executing various software programs such as system programs, applications programs, and/or program modules/blocks to provide computing and processing operations for the computing device  600 . The processing unit  602  may be responsible for performing various voice and data communications operations for the computing device  600  such as transmitting and receiving voice and data information over one or more wired or wireless communications channels. Although the processing unit  602  of the computing device  600  is shown in the context of a single processor architecture, it may be appreciated that the computing device  600  may use any suitable processor architecture and/or any suitable number of processors in accordance with the described embodiments. In one embodiment, the processing unit  602  may be implemented using a single integrated processor. 
     The processing unit  602  may be implemented as a host central processing unit (CPU) using any suitable processor circuit or logic device (circuit), such as a as a general purpose processor. The processing unit  602  also may be implemented as a chip multiprocessor (CMP), dedicated processor, embedded processor, media processor, input/output (I/O) processor, co-processor, microprocessor, controller, microcontroller, application specific integrated circuit (ASIC), field programmable gate array (FPGA), programmable logic device (PLD), or other processing device in accordance with the described embodiments. 
     As shown, the processing unit  602  may be coupled to the memory and/or storage component(s)  604  through the bus  608 . The bus  608  may comprise any suitable interface and/or bus architecture for allowing the processing unit  602  to access the memory and/or storage component(s)  604 . Although the memory and/or storage component(s)  604  may be shown as being separate from the processing unit  602  for purposes of illustration, it is worthy to note that in various embodiments some portion or the entire memory and/or storage component(s)  604  may be included on the same integrated circuit as the processing unit  602 . Alternatively, some portion or the entire memory and/or storage component(s)  604  may be disposed on an integrated circuit or other medium (e.g., hard disk drive) external to the integrated circuit of the processing unit  602 . In various embodiments, the computing device  600  may comprise an expansion slot to support a multimedia and/or memory card, for example. The memory and/or storage component(s)  604  represent one or more computer-readable media. The memory and/or storage component(s)  604  may be implemented using any computer-readable media capable of storing data such as volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. The memory and/or storage component(s)  604  may comprise volatile media (e.g., random access memory (RAM)) and/or nonvolatile media (e.g., read only memory (ROM), Flash memory, optical disks, magnetic disks and the like). The memory and/or storage component(s)  604  may comprise fixed media (e.g., RAM, ROM, a fixed hard drive, etc.) as well as removable media (e.g., a Flash memory drive, a removable hard drive, an optical disk). Examples of computer-readable storage media may include, without limitation, RAM, dynamic RAM (DRAM), Double-Data-Rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory (e.g., NOR or NAND flash memory), content addressable memory (CAM), polymer memory (e.g., ferroelectric polymer memory), phase-change memory, ovonic memory, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, magnetic or optical cards, or any other type of media suitable for storing information. 
     The one or more I/O devices  606  allow a user to enter commands and information to the computing device  600 , and also allow information to be presented to the user and/or other components or devices. Examples of input devices include data ports, digital-to-analog converters (DAC&#39;s), analog to digital converters (ADC&#39;s), a keyboard, a cursor control device (e.g., a mouse), a microphone, a scanner and the like. Examples of output devices include data ports, DACs, ADCs, a display device (e.g., a monitor or projector, speakers, a printer, a network card). The computing device  600  may comprise an alphanumeric keypad coupled to the processing unit  602 . The keypad may comprise, for example, a QWERTY key layout and an integrated number dial pad. The computing device  600  may comprise a display coupled to the processing unit  602 . The display may comprise any suitable visual interface for displaying content to a user of the computing device  600 . In one embodiment, for example, the display may be implemented by a liquid crystal display (LCD) such as a touch-sensitive color (e.g., 76-bit color) thin-film transistor (TFT) LCD screen. The touch-sensitive LCD may be used with a stylus and/or a handwriting recognizer program. 
     The processing unit  602  may be arranged to provide processing or computing resources to the computing device  600 . For example, the processing unit  602  may be responsible for executing various software programs including system programs such as operating system (OS) and application programs. System programs generally may assist in the running of the computing device  600  and may be directly responsible for controlling, integrating, and managing the individual hardware components of the computer system. The OS may be implemented, for example, as a Microsoft® Windows OS, Symbian OS™, Embedix OS, Linux OS, Binary Run-time Environment for Wireless (BREW) OS, JavaOS, or other suitable OS in accordance with the described embodiments. The computing device  600  may comprise other system programs such as device drivers, programming tools, utility programs, software libraries, application programming interfaces (APIs), and so forth. 
     In various embodiments disclosed herein, a single component may be replaced by multiple components and multiple components may be replaced by a single component to perform a given function or functions. Except where such substitution would not be operative, such substitution is within the intended scope of the embodiments. 
     While various embodiments have been described herein, it should be apparent that various modifications, alterations, and adaptations to those embodiments may occur to persons skilled in the art with attainment of at least some of the advantages. The disclosed embodiments are therefore intended to include all such modifications, alterations, and adaptations without departing from the scope of the embodiments as set forth herein.