Patent Publication Number: US-9892484-B2

Title: Methods for checking dependencies of data units and apparatuses using the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of China Patent Application No. 201510788164.X, filed on Nov. 17, 2015, the entirety of which is incorporated by reference herein. 
     BACKGROUND 
     Technical Field 
     The present invention relates to 3D (three-dimensional) graphics, and in particular, it relates to methods for checking dependencies of data units and apparatuses using the same. 
     Description of the Related Art 
     In a 3D graphics pipeline, the rasterizer converts primitives into pixels and feeds these pixels into the pixel shader. The pixel shader determines the final pixel color to be written to the render target. The rasterizer generates primitives in order and tiles for each primitive. The data units (e.g. quads) are abstracted and packed to threads. One thread contains a predefined number of data units. The threads are kicked off into the pixel shader and run in parallel. The threads run in the pixel shader may be out of order. But, the pixel shader needs to output data units in the order generated by the rasterizer. The threads, when being executed, may be arbitrary access memory, such as read data, write data, etc. However, a read-after-write hazard may occur for the same data unit between threads. To avoid the aforementioned problem, it is desirable to provide methods for checking dependencies of data units and apparatuses using the same. 
     BRIEF SUMMARY 
     An embodiment of a method for checking dependencies of data units contains at least the following steps. A memory access request associated with a data unit is received from a first thread of a pixel shader. A processing status associated with the data unit is obtained from a window buffer. It is determined whether the data unit is being processed by a second thread. If so, a rejection procedure is performed to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM (Dynamic Random Access Memory). Otherwise, an acknowledgement procedure is performed to grant the first thread to access the attribute value associated with the data unit from/to the DRAM. 
     An embodiment of an apparatus for checking dependencies of data units is introduced, and it contains at least a window buffer and a window checker. The window checker, coupled to the window buffer, receives a memory access request associated with a data unit from a first thread of a pixel shader; obtains a processing status associated with the data unit from a window buffer; and determines whether the data unit is being processed by a second thread. If so, the window checker performing a rejection procedure to avoid the first thread gaining to access an attribute value associated with the data unit from/to a DRAM. Otherwise, the window checker performs an acknowledgement procedure to grant the first thread to access the attribute value associated with the data unit from/to the DRAM. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention can be fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
         FIG. 1  is the hardware architecture of an apparatus for checking dependencies of data units according to an embodiment of the invention; 
         FIG. 2  is a schematic diagram illustrating primitive conversions into a 2D image according to an embodiment of the invention; 
         FIG. 3  is a flowchart illustrating a method for processing pixels according to an embodiment of the invention; 
         FIG. 4  is a flowchart illustrating a method for checking dependencies of data units, performed by a window checker, according to an embodiment of the invention; 
         FIG. 5  is a flowchart illustrating a method for checking dependencies of data units, performed by a window releaser, according to an embodiment of the invention; and 
         FIG. 6  is a block diagram of an arbiter according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
     The present invention will be described with respect to particular embodiments and with reference to certain drawings, but the invention is not limited thereto and is only limited by the claims. Furthermore, it should be understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Use of ordinal terms such as “first”, “second”, “third”, etc., in the claims to modify a claim element does not by itself connote any priority, precedence, or order of one claim element over another or the temporal order in which acts of a method are performed, but are used merely as labels to distinguish one claim element having a certain name from another element having the same name (but for use of the ordinal term) to distinguish the claim elements. 
       FIG. 1  is the hardware architecture of an apparatus for checking dependencies of data units according to an embodiment of the invention. A DRAM (Dynamic Random Access Memory)  120  stores attribute values associated with pixels of a 2D (two-dimensional) image, such as coordinates, z-values, color values, etc. A pixel shader  110  needs to access the attribute values of the pixels of the DRAM  120  when performing particular operations, such as ROVs (Raster Ordered Views), pixel-value fusions between primitives. One operation typically includes tasks for reading attribute values from particular addresses of the DRAM  120 , computing the read values and writing the computation results back into the addresses of the DRAM  120 . It should be noted that, when a thread of the pixel shader  110  has read attribute values of particular addresses but the computation results haven&#39;t been written back, the attribute values of the addresses cannot be read by the other threads. Otherwise, a read-after-write hazard occurs.  FIG. 2  is a schematic diagram illustrating primitive conversions into a 2D image according to an embodiment of the invention. A raster generates primitives  210  and  230  sequentially and converts them into the 2D image in quads, where the primitives  210  and  230  are overlapped in the back-slashed area. When any pixel of the overlapped area is processed by the threads associated with the primitives  210  and  230  simultaneously, the pixel shader  110  has to guarantee that the thread associated with the primitive  230  starts to process the pixel until the thread associated with the primitive  210  has processed the pixel completely. 
       FIG. 3  is a flowchart illustrating a method for processing pixels according to an embodiment of the invention. The method is performed by a thread of the pixel shader  110 . The process begins with an acquisition of information regarding a data unit to be processed (step S 311 ). The data unit may be one or more pixels, quads, tiles or others. The acquired information contains at least the position at which the data unit is situated in the 2D image. The position of the 2D image may be (x,y) coordinates, a quad number, a tile number or a similar but different expression. To ensure that the access order between threads to the attribute values of the same pixel conforms to the production order of the associated primitives, a thread issues a memory access request for the data unit to a window checker  130  (step S 313 ). The memory access request contains at least the position at which the data unit is situated in the 2D image. Next, when receiving an acknowledgement from the window checker  130  (the “Yes” path of step S 315 ), the thread reads the attribute values associated with the data unit from the DRAM  120  (step S 331 ). When receiving a rejection from the window checker  130  (the “No” path of step S 315 ), the thread may re-issue a memory access request for the data unit to the window checker  130  after a predefined time period has elapsed (step S 313 ). In some embodiments, the thread may activate a timer for counting to the predefined time period after issuing a memory access request. When receiving an acknowledgement from the window checker  130  before the timer has expired (the “Yes” path of step S 315 ), the thread reads the attribute values associated with the data unit from the DRAM  120  (step S 331 ). After the timer has expired (the “No” path of step S 315 ), the thread re-issues the memory access request for the data unit to the window checker  130  (step S 313 ). After reading the required data (step S 331 ), the thread computes the attribute values of the data unit (step S 333 ), writes the computation results of the data unit back to the DRAM  120  (step S 335 ) and informs a window releaser  150  that the memory access for the data unit has completed (step S 337 ). Detailed operations of the window checker  130  and the window releaser  150  will be discussed in the following paragraphs. 
     A window buffer  160  stores a processing status of each data unit and may be implemented in a 1R1W-type SRAM (Static Random Access Memory). The window buffer  160  may contain a predefined quantity M of cells and each cell may contain a predefined quantity N of bits. Each bit indicates a processing status associated with a data unit, where logic “1” indicates that the data unit is being processed by a thread and logic “0” indicates that the data unit hasn&#39;t been processed by any thread. For example, to conform to the full capability of the pixel shader  110 , the window buffer  160  contains 256 cells and each cell contains 256 bits. The addressing information of the processing statuses associated the data units conform to their positions in the 2D image. In an example, bits  0  to  255  of cell  0  indicates the processing statuses associated with the pixels at coordinates (0, 0) to (0, 255) respectively, bits  0  to  255  of cell  1  indicates the processing statuses associated with the pixels at coordinates (1, 0) to (1, 255) respectively, and so on. In another example, bits  0  to  255  of cell  0  indicates the processing statuses associated with the quads or tiles  0  to  255  respectively, bits  0  to  255  of cell  1  indicates the processing statuses associated with the quads or tiles  256  to  511  respectively, and so on. In still another example, bits  0  to  3  of cell  0  indicates the processing statuses associated with the pixels  0  to  3  of the quad  0  respectively, bits  4  to  7  of cell  0  indicates the processing statuses associated with the pixels  0  to  3  of the quad  1  respectively, and so on. Although the embodiments describe the 1R1W-type SRAM as the window buffer  160 , those skilled in the art may implement the window buffer  160  in a 2R2W-type SRAM to yield better performance by the acceptable addition of a gate-count cost. 
       FIG. 4  is a flowchart illustrating a method for checking dependencies of data units, performed by the window checker  130 , according to an embodiment of the invention. The window checker  130  begins with a reception of the memory access request associated with the data unit from a thread (step S 411 ). The memory access request contains at least the position at which the data unit is situated in the 2D image. After calculating a cell index according to the position of the data unit (step S 413 ), the window checker  130  issues a request to an arbiter  140  for reading a designated cell (step S 431 ) and obtains the processing status of the data unit from the arbiter  140  (step S 433 ). The request for reading data from the designated cell, which is issued by the window checker  130 , contains the calculated cell index. It should be noted that the arbiter  140  may read the whole processing statuses of the cell at one time and reply with the processing statuses to the window checker  130 , and then the window checker  130  may obtain the processing status associated with the data unit from the replied data according to the position of the data unit. Assume that, for example, cell  0  stores processing statuses of quads  0  to  255  and the data unit is the quad  7 : The window checker  130  may obtain the bit  7  value of the replied 256 bits from the arbiter  140  according to the position of the data unit. The window checker  130  determines whether the data unit is being processed by another thread (step S 451 ). If so, a rejection procedure is performed to avoid the thread gaining to access the attribute value associated with the data unit from/to the DRAM  120  (steps S 471  to S 473 ). Otherwise, an acknowledgement procedure is performed to grant the thread to access the attribute value associated with the data unit from/to the DRAM  120  (steps S 491  to S 495 ). In step S 451 , for example, the corresponding bit value being logic “1” indicates that the data unit is being processed by another thread. The corresponding bit value being logic “0” indicates that the data unit has not been processed by any thread. In the rejection procedure, the window checker  130  replies with a rejection message to the thread (step S 471 ) and issues a request to the arbiter  140  for writing data into the designated cell so as to write the originally read processing statuses into the address corresponding to the cell index of the window buffer  160  (step S 473 ). The request for writing data into the designated cell issued by the window checker  130  contains the calculated cell index. In some embodiments, step S 471  may be omitted. In the acknowledgement procedure, the window checker  130  replies with an acknowledgement to the thread (step S 491 ), updates the bit value corresponding to the data unit to indicate that the data unit is being processed by the thread (step S 493 ) and issues a request to the arbiter  140  for writing data into the designated cell so as to write the updated processing statuses into the address corresponding to the cell index of the window buffer  160  (step S 495 ). In step S 495 , it should be noted that, in spite of the processing status associated with the data unit, the other processing statuses are maintained without any modification. To simplify the lock design of the arbiter  140 , the read and write requests are executed pair by pair. That is, after issuing a read request for a designated cell, the window checker  130  issues a write request for the cell. 
       FIG. 5  is a flowchart illustrating a method for checking dependencies of data units, performed by the window releaser  150 , according to an embodiment of the invention. The window releaser  150  begins with a reception of the memory-access completion notification associated with the data unit from a thread (step S 511 ). The memory-access completion notification contains at least the position at which the data unit is situated in the 2D image. After calculating a cell index according to the position of the data unit (step S 513 ), the window releaser  150  issues a request to an arbiter  140  for reading a designated cell (step S 531 ) updates the bit value of the data unit to indicate that the data unit has not been processed by any thread (step S 533 ) and issues a request to the arbiter  140  for writing data into the designated cell so as to write the updated processing statuses (step S 535 ). The requests for reading data from and writing data into the designated cell, which are issued by the window releaser  150 , contain the calculated cell index. It should be noted that the arbiter  140  may read the whole processing statuses of the cell at one time and reply with the processing statuses to the window releaser  150 , and then, the window releaser  150  may update the processing status associated with the data unit according to the position of the data unit. Assume that, for example, cell  0  stores processing statuses of quads  0  to  255  and the data unit is the quad  7 : The window releaser  150  may update the processing status of bit  7  according to the position of the data unit. In step S 535 , it should be noted that, despite the processing status associated with the data unit, the other processing statuses are maintained without any modification. To simplify the lock design of the arbiter  140 , the read and write requests are executed pair by pair. 
     In order to coordinate with the requests between the window checker  130  and the window releaser  150 , the arbiter  140  grants one request according to the following rules to avoid a read-after-write hazard in which a thread reads a data unit that has been processed by another thread but has yet to be written back.  FIG. 6  is a block diagram of an arbiter according to an embodiment of the invention. A register  630  records a lock flag and a cell index of the window checker  130 . The lock flag of the window checker  130  being “true” indicates that the window checker  130  has read the processing status of the designated cell (indicated by the cell index) of the window buffer  160  but hasn&#39;t written the (original or updated) processing status back. The lock flag of the window checker  130  being “false” indicates that the window checker  130  hasn&#39;t read new cell data from the window buffer  160 . The register  630  further records a lock flag and a cell index of the window releaser  150 . The lock flag of the window releaser  150  being “true” indicates that the window releaser  150  has read the processing status of the designated cell (indicated by the cell index) of the window buffer  160  but hasn&#39;t written the (original or updated) processing status back. The lock flag of the window releaser  150  being “false” indicates that the window releaser  150  hasn&#39;t read new cell data from the window buffer  160 . 
     When receiving a request (which may be a read or write request) from the window checker  130 , the control unit  610  stores a cell index of the request in the register  630 . Similarly, when receiving a request (which may be a read or write request) from the window releaser  150 , the control unit  610  stores a cell index of the request in the register  630 . The control unit  610  reads the aforementioned lock flags and cell indices and employs the following rules to select and process one of the requests issued by the window checker  130  and the window releaser  150 . In the first rule, when the lock flags of the window checker  130  and the window releaser  150  are “false” and the two cell indices are the same (indicating that the window checker  130  and the window releaser are asking to read processing statuses from the same cell), the control unit  610  selects and processes the read request issued by the window releaser  150 . That is, when conflict occurs, the priority of the window releaser  150  is higher than that of the window checker  130  to avoid the aforementioned read-after-write hazard. Specifically, the control unit  610  directs an access interface  620  to read processing statuses from the designated cell, replies with the read data to the window releaser  150 , and updates the lock flag of the window releaser  150  with “true”. In the second rule, when the lock flag of the window checker  130  is “true” and the lock flag of the window releaser  150  is “false” and the two cell indices are different (indicating that the window checker  130  asks to write processing statuses into one cell and the window releaser  150  asks to read processing statuses from another cell), the control unit  610  selects and processes the read request issued by the window releaser  150 . Specifically, the control unit  610  directs the access interface  620  to read processing statuses from the designated cell, replies with the read data to the window releaser  150  and updates the lock flag of the window releaser  150  with “true”. In the third rule, when the lock flag of the window checker  130  is “false” and the lock flag of the window releaser  150  is “true” and the two cell indices are different (indicating that the window checker  130  asks to read processing statuses from one cell and the window releaser  150  asks to write processing statuses into another cell), the control unit  610  selects and processes the read request issued by the window checker  130 . Specifically, the control unit  610  directs the access interface  620  to read processing statuses from the designated cell, replies with the read data to the window checker  130  and updates the lock flag of the window checker  130  with “true”. In the fourth rule, when the lock flag of the window checker  130  is “true” and the lock flag of the window releaser  150  is “false” and the two cell indices are the same (indicating that the window checker  130  asks to write processing statuses into one cell and the window releaser  150  asks to read processing statuses from the same cell), the control unit  610  selects and processes the write request issued by the window checker  130  to ensure that the read and write requests issued by the window checker  130  can be processed consecutively and will not be interrupted by the read request issued by the window releaser  150 . Specifically, the control unit  610  directs the access interface  620  to write processing statuses into the designated cell, replies with a data-write success message to the window checker  130  and updates the lock flag of the window checker  130  with “false”. In the fifth rule, when the lock flag of the window checker  130  is “false” and the lock flag of the window releaser  150  is “true” and the two cell indices are the same (indicating that the window checker  130  asks to read processing statuses from one cell and the window releaser  150  asks to write processing statuses into the same cell), the control unit  610  selects and processes the write request issued by the window releaser  150  to ensure that the read and write requests issued by the window releaser  150  can be processed consecutively and will not be interrupted by the read request issued by the window checker  130 . Specifically, the control unit  610  directs the access interface  620  to write processing statuses into the designated cell, replies with a data-write success message to the window releaser  150  and updates the lock flag of the window releaser  150  with “false”. In the sixth rule, when the lock flags of the window checker  130  and the window releaser  150  are “true” and the two cell indices are different (indicating that the window checker  130  and the window releaser ask to write processing statuses into different cell), the control unit  610  selects and processes the write request issued by the window releaser  150 . Specifically, the control unit  610  directs the access interface  620  to write processing statuses into the designated cell, replies with a data-write success message to the window releaser  150  and updates the lock flag of the window releaser  150  with “false”. 
     It should be noted that, as to any of the second, third and sixth rules without any conflict, the arbitration prioritizes the window checker  130 . That is, the control unit  610  selects and processes the request issued by the window checker  130 . Or, the arbitration may employ a round-robin principle to yield more balanced throughput. For example, the control unit  610  selects and processes the request issued by the window checker  130  when the request issued by the window releaser  150  was selected last time, and vice versa. 
     In some implementations, the designer may devise the window buffer  160  with registers for storing the aforementioned processing statuses and install numerous comparators to achieve functions similar to those taught by the embodiments of the invention. However, the implementations consume at least three times the gate-count cost of the embodiments of the invention. 
     Although the embodiments have been described in  FIGS. 1 and 6  as having specific elements, it should be noted that additional elements may be included to achieve better performance without departing from the spirit of the invention. While the process flows described in  FIGS. 3 to 5  include a number of operations that appear to occur in a specific order, it should be apparent that these processes can include more or fewer operations, which can be executed serially or in parallel, e.g., using parallel processors or a multi-threading environment. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.