Patent Publication Number: US-11647589-B2

Title: Wiring board

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims priority to Japanese Patent Application No. 2020-128108, filed on Jul. 29, 2020, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Certain aspects of the embodiments discussed herein are related to wiring boards, and methods for manufacturing the wiring boards. 
     BACKGROUND 
     As one example of the wiring board, Japanese Laid-Open Patent Publication No. 2019-220504 proposes an inductor built-in substrate having a magnetic resin embedded inside a through hole of a core substrate. 
     In the conventional wiring board including the magnetic resin, an interconnect layer directly connected to the through hole of the core substrate is inevitably thick, and it is difficult to form a fine pattern on the interconnect layer. In addition, the thicker the interconnect layer becomes, the more likely a thickness variation occurs. If the thickness variation occurs, an unetched portion may occur during patterning of the interconnect layer, thereby deteriorating the yield. 
     SUMMARY 
     Accordingly, it is an object in one aspect of the embodiments to provide a wiring board having a fine interconnect layer, and a method for manufacturing the wiring boards. 
     According to one aspect of the embodiments, a wiring board includes an insulating base including a first principal surface, a second principal surface opposite to the first principal surface, and a first through hole penetrating the insulating base from the first principal surface to the second principal surface; a functional material provided inside the first through hole; a first insulating layer covering the first principal surface, and a first surface of the functional material; a second insulating layer covering the second principal surface, and a second surface of functional material; a second through hole formed in the first insulating layer, the functional material, and the second insulating layer; a conductive layer formed on a wall surface of the second through hole. 
     The object and advantages of the embodiments will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a cross sectional view illustrating a structure of a wiring board according to a first embodiment. 
         FIG.  2    is a cross sectional view illustrating a conductive layer, a first interconnect layer, and a second interconnect layer according to the first embodiment. 
         FIG.  3 A ,  FIG.  3 B , and  FIG.  3 C  are cross sectional views (part  1 ) illustrating a method for manufacturing the wiring board according to the first embodiment. 
         FIG.  4 A ,  FIG.  4 B , and  FIG.  4 C  are cross sectional views (part  2 ) illustrating the method for manufacturing the wiring board according to the first embodiment. 
         FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C  are cross sectional views (part  3 ) illustrating the method for manufacturing the wiring board according to the first embodiment. 
         FIG.  6 A ,  FIG.  6 B , and  FIG.  6 C  are cross sectional views (part  4 ) illustrating the method for manufacturing the wiring board according to the first embodiment. 
         FIG.  7 A ,  FIG.  7 B , and  FIG.  7 C  are cross sectional views (part  5 ) illustrating the method for manufacturing the wiring board according to the first embodiment. 
         FIG.  8    is a cross sectional view illustrating the conductive layer, the first interconnect layer, and the second interconnect layer according to a second embodiment. 
         FIG.  9 A ,  FIG.  9 B , and  FIG.  9 C  are cross sectional views (part  1 ) illustrating the method for manufacturing the wiring board according to the second embodiment. 
         FIG.  10 A  and  FIG.  10 B  are cross sectional views (part  2 ) illustrating the method for manufacturing the wiring board according to the second embodiment. 
         FIG.  11    is a cross sectional view illustrating a magnetic material according to a third embodiment. 
         FIG.  12 A  and  FIG.  12 B  are cross sectional views (part  1 ) illustrating the method for manufacturing the wiring board according to a third embodiment. 
         FIG.  13 A  and  FIG.  13 B  are cross sectional views (part  2 ) illustrating the method for manufacturing the wiring board according to the third embodiment. 
         FIG.  14    is a cross sectional view illustrating the magnetic material according to a fourth embodiment. 
         FIG.  15    is a cross sectional view illustrating a semiconductor package according to a fifth embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Preferred embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, those constituent elements having substantially the same functions or structures are designated by the same reference numerals, and a repeated description of such constituent elements may be omitted. 
     A description will now be given of a wiring board according to each embodiment, and a method for manufacturing the wiring board according to each embodiment, by referring to the drawings. 
     First Embodiment 
     A first embodiment will be described. The first embodiment relates to the wiring board. 
     [Structure of Wiring Board] 
     First, a structure of the wiring board will be described.  FIG.  1    is a cross sectional view illustrating the structure of the wiring board according to the first embodiment. 
     As illustrated in  FIG.  1   , a wiring board  100  according to the first embodiment includes an insulating base  102 , as a support. The base  102  may be formed of an insulating material, such as a glass epoxy resin, a bismaleimide triazine (BT) resin, or the like. The base  102  includes a first principal surface  102 A, and a second principal surface  102 B opposite the first principal surface  102 A. A first through hole  111  is formed to penetrate the base  102  in a thickness direction of the base  102 , from the first principal surface  102 A to the second principal surface  102 B. For example, the first through hole  111  may have a diameter in a range of 350 μm to 450 μm. 
     A magnetic material  110  is provided inside the first through hole  111 . The magnetic material  110  includes, a resin, such as an epoxy resin or the like, and magnetic particles, such as iron fillers or the like, dispersed in the resin. The magnetic material  110  includes a first surface  110 A on the side closer to the first principal surface  102 A, and a second surface  110 B on the side closer to the second principal surface  102 B. In the first embodiment, the magnetic material  110  is thicker than the base  102 , and the magnetic material  110  protrudes from the first principal surface  102 A and the second principal surface  102 B. That is, a distance from a center C along the thickness direction of the base  102  to the first surface  110 A, is greater than a distance from the center C to the first principal surface  102 A. A distance from the center C to the second surface  110 B, is greater than a distance from the center C to the second principal surface  102 B. 
     A first insulating layer  121 , which covers the first principal surface  102 A and the first surface  110 A of the magnetic material  110 , is provided on the first principal surface  102 A and the first surface  110 A. A second insulating layer  122 , which covers the second principal surface  102 B and the second surface  110 B of the magnetic material  110 , is provided on the second principal surface  102 B and the second surface  110 B. For example, the first insulating layer  121  and the second insulating layer  122  are made of an epoxy film including a filler. For example, the first insulating layer  121  and the second insulating layer  122  may have thicknesses in a range of 30 μm and 60 μm. 
     A second through hole  112  is formed to penetrate the first insulating layer  121 , the magnetic material  110 , and the second insulating layer  122 , in the thickness direction of these layers. The second through hole  112  has a diameter smaller than the diameter of the first through hole  111 . For example, the second through hole  112  may have a diameter in a range of 150 μm to 250 μm. A conductive layer  140  is provided on a wall surface of the second through hole  112 . An insulative filler material  149  is provided to fill the inner side of the conductive layer  140  at the second through hole  112 . For example, the filler material  149  main include a resin. The filler material  149  may further include a filler. 
     A third through hole  113  is formed to penetrate the first insulating layer  121 , the base  102 , and the second insulating layer  122  in the thickness direction of these layers. The third through hole  113  is formed at a position separated from the magnetic material  110  in an in-plane direction which is perpendicular to the thickness direction of the base  102 . For example, the third through hole  113  may have a diameter in a range of 150 μm to 250 μm. The conductive layer  140  is also provided on a wall surface of the third through hole  113 . The filler material  149  is provided to fill the inner side of the conductive layer  140  at the third through hole  113 . 
     A first interconnect layer  141  is formed on a surface of the first insulating layer  121 , and a second interconnect layer  142  is formed on a surface of the second insulating layer  122 . The first interconnect layer  141  and the second interconnect layer  142  connect to the conductive layer  140 . That is, the first interconnect layer  141  and the second interconnect layer  142  are connected to each other via the conductive layer  140 . 
     A third insulating layer  123  is formed on the first insulating layer  121 . The third insulating layer  123  includes a via hole  161  which is formed to reach a connection portion of the first interconnect layer  141 . A third interconnect layer  143 , which connects to the first interconnect layer  141  via a via conductor inside the via hole  161 , is formed on the third insulating layer  123 . Further, a fifth insulating layer  125  is formed on the third insulating layer  123 . The fifth insulating layer  125  includes a via hole  163  which is formed to reach a connection portion of the third interconnect layer  143 . A fifth interconnect layer  145 , which connects to the third interconnect layer via a via conductor inside the via hole  163 , is formed on the fifth insulating layer  125 . 
     A solder resist layer  127  is formed on the fifth insulating layer  125 . The solder resist layer  127  includes an opening  165  which reaches a connection portion of the fifth interconnect layer  145 . A connection terminal  147 , which protrudes above the solder resist layer  127  via the opening, is famed on the connection portion of the fifth interconnect layer  145 . The connection terminal  147  may include a post, and a bump on top of the post. An electrode of a semiconductor chip is connected to the connection terminal  147 . 
     A fourth insulating layer  124  is formed on the second insulating layer  122 . The fourth insulating layer  124  includes a via hole  162  which is formed to reach a connection portion of the second interconnect layer  142 . A fourth interconnect layer  144 , which connects to the second interconnect layer  142  via a via conductor inside the via hole  162 , is formed on the fourth insulating layer  124 . Further, a sixth insulating layer  126  is formed on the fourth insulating layer  124 . The sixth insulating layer  126  includes a via hole  164  which is formed to reach a connection portion of the fourth interconnect layer  144 . A sixth interconnect layer  146 , which connects to the fourth interconnect layer  144  via a via conductor inside the via hole  164 , is formed on the sixth insulating layer  126 . 
     A solder resist layer  128  is formed on the sixth insulating layer  126 . The solder resist layer  128  includes an opening  166  which is formed to reach a connection portion of the sixth interconnect layer  146 . 
     Next, details of the conductive layer  140 , the first interconnect layer  141 , and the second interconnect layer  142  will be described.  FIG.  2    is a cross sectional view illustrating the conductive layer  140 , the first interconnect layer  141 , and the second interconnect layer  142  according to the first embodiment. 
     As illustrated in  FIG.  2   , the conductive layer  140  includes an electroless copper plating film  131 , and an electrolytic copper plating film  132 , which are laminated. The electroless copper plating film  131  is formed on a wall surface of the second through hole  112  and on a wall surface of the third through hole  113 . The electrolytic copper plating film  132  is formed on electroless copper plating film  131 . For example, the electroless copper plating film  131  may have a thickness in a range of 0.3 μm to 1.0 μm, and the electrolytic copper plating film  132  may have a thickness in a range of 10 μm to 50 μm. The filler material  149  fills the inner side of the electrolytic copper plating film  132  at the second through hole  112  and the third through hole  113 . The electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  respectively have surfaces coinciding with the surface of the first insulating layer  121 , and surfaces coinciding with the surface of the second insulating layer  122 . 
     The first interconnect layer  141  includes an electroless copper plating film  133 A, and an electrolytic copper plating film  134 A, which are laminated. The electroless copper plating film  133 A is formed on the surface (that is, the upper surface) of the first insulating layer  121 , and on the surfaces (that is, first end surfaces) of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the upper surface of the first insulating layer  121 . In other words, the first end surface (that is, the upper end surface) of the conductive layer  140  coincides with the upper surface of the first insulating layer  121 , opposite to the lower surface of the insulating layer  121  covering the first principal surface  102 A. The electrolytic copper plating film  134 A is formed on electroless copper plating film  133 A. For example, the electroless copper plating film  133 A may have a thickness in a range of 0.3 μm to 1.0 μm, and the electrolytic copper plating film  134 A may have a thickness in a range of 15 μm to 40 μm. 
     The second interconnect layer  142  includes an electroless copper plating film  133 B, and an electrolytic copper plating film  134 B, which are laminated. The electroless copper plating film  133 B is formed on the surface (that is, the lower surface) of the second insulating layer  122 , and on the surfaces (that is, second end surfaces) of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the lower surface of the second insulating layer  122 . In other words, the second end surface (that is, the lower end surface) of the conductive layer  140  coincides with the lower surface of the second insulating layer  122 , opposite to the upper surface of the second insulating layer  122  covering the second principal surface  102 B. The electrolytic copper plating film  134 B is formed on the electroless copper plating film  133 B. For example, the electroless copper plating film  133 B may have a thickness in a range of 0.3 μm to 1.0 μm, and the electrolytic copper plating film  134 B may have a thickness in a range of 15 μm to 40 μm. 
     In the first embodiment, the thickness of the first interconnect layer  141  is equal to the total thickness of the electroless copper plating film  133 A and the electrolytic copper plating film  134 A, and the thickness of the second interconnect layer  142  is equal to the total thickness of the electroless copper plating film  133 B and the electrolytic copper plating film  134 B. The electroless copper plating film  133 A is extremely thin compared to the electrolytic copper plating film  134 A, and the electroless copper plating film  133 B is extremely thin compared to the electrolytic copper plating film  134 B. Hence, the thickness of the first interconnect layer  141  is substantially the same as the thickness of the electrolytic copper plating film  134 A, and the thickness of the second interconnect layer  142  is substantially the same as the thickness of the electrolytic copper plating film  134 B. For example, the thicknesses of the first interconnect layer  141  and the second interconnect layer  142  may be in a range of approximately 15 μm to approximately 40 μm. For this reason, the first interconnect layer  141  and the second interconnect layer  142  can easily be subjected to a fine pattern lithography. That is, fine patterns can easily be formed in the first interconnect layer  141  and the second interconnect layer  142 . In addition, it is possible to reduce a variation (or inconsistency) in the thicknesses of the first interconnect layer  141  and the second interconnect layer  142 , and to reduce an unetched portion from occurring during the patterning, as will be described later in conjunction with  FIG.  7 B . Accordingly, it is possible to reduce deterioration of the yield caused by the unetched portion. 
     [Method for Manufacturing Wiring Board] 
     Next, a method for manufacturing the wiring board according to the first embodiment will be described.  FIG.  3    through  FIG.  7    are cross sectional views illustrating the method for manufacturing the wiring board according to the first embodiment. 
     First, as illustrated in  FIG.  3 A , a laminate  101 , including the insulating base  102 , the conductive film  103 A, and the conductive film  103 B, is prepared. The base  102  includes the first principal surface  102 A, and the second principal surface  102 B opposite to the first principal surface  102 A. The conductive film  103 A is provided on the first principal surface  102 A, and the conductive film  103 B is provided on the second principal surface  102 B. For example, the conductive films  103 A and  103 B are copper foils. The laminate  101  forms a large substrate from which a plurality of wiring boards  100  can be singulated. In other words, the laminate  101  includes a plurality of regions (or areas) where structures, respectively corresponding to the wiring board  100 , are formed. 
     Next, as illustrated in  FIG.  3 B , the first through hole  111  is formed to penetrate the laminate  101  in a thickness direction of the laminate  101 . The first through hole  111  penetrates the conductive film  103 A, the base  102 , and the conductive film  103 B in the thickness direction of these layers. For example, the first through hole  111  may be formed by drilling, laser beam machining, or the like. Thereafter, the wall of the first through hole  111  is subjected to a desmear process. The desmear process removes the resin residue (or smear). For example, the desmear process may be performed using a potassium permanganate solution. For example, the first through hole  111  may have a diameter in a range of 350 μm to 450 μm. 
     Thereafter, as illustrated in  FIG.  3 C , the magnetic material  110  is filled into the first through hole  111 . For example, the magnetic material  110  may be filled so as to protrude from the surfaces of each of the conductive films  103 A and  103 B, in order to avoid insufficient filling of the first through hole  111 . 
     Next, as illustrated in  FIG.  4 A , portions of the magnetic material  110  protruding from the surfaces of the conductive films  103 A and  103 B are removed by polishing. For example, the protruding portions of the magnetic material  110  may be removed by buffing or roll polishing. The magnetic material  110  after the polishing includes the first surface  110 A which coincides with the surface of the conductive film  103 A, and a surface  110 B which coincides with the surface of the conductive film  103 B. 
     Next, as illustrated in  FIG.  4 B , the conductive films  103 A and  103 B are removed. As a result, the first principal surface  102 A and the second principal surface  102 B are exposed. For example, the conductive films  103 A and  103 B may be removed by wet etching using an acidic solution. Examples of the acidic solution may include a hydrogen peroxide (H 2 O 2 ) solution, a sulfuric acid (H 2 SO 4 ) solution, or the like. 
     Next, as illustrated in  FIG.  4 C , the first insulating layer  121 , which covers the first principal surface  102 A and the first surface  110 A of the magnetic material  110 , is provided on the first principal surface  102 A and the first surface  110 A. The second insulating layer  122 , which covers the second principal surface  102 B and the second surface  110 B of the magnetic material  110 , is provided on the second principal surface  102 B and the second surface  110 B. An epoxy resin film including a filler may be adhered as the first insulating layer  121  and the second insulating layer  122 . For example, the first insulating layer  121  and the second insulating layer  122  may have thicknesses in a range of 30 μm and 60 μm. 
     Next, as illustrated in  FIG.  5 A , the third through hole  113  is formed to penetrate the first insulating layer  121 , the base  102 , and the second insulating layer  122  in the thickness direction of these layers. For example, the third through hole  113  may be famed by drilling, laser beam machining, or the like. Then, the desmear process is performed on the wall surface of the third through hole  113 . For example, the third through hole  113  may have a diameter in a range of 150 μm to 250 μm. 
     Thereafter, as illustrated in  FIG.  5 B , the second through hole  112  is formed to penetrate the first insulating layer  121 , the magnetic material  110 , and the second insulating layer  122  the thickness direction of these layers. The diameter of the second through hole  112  is smaller than the diameter of the first through hole  111 . For example, the second through hole  112  may be formed by drilling, laser beam machining, or the like. For example, the second through hole  112  may have a diameter in a range of 150 μm to 250 μm. Then, the wall surface of the second through hole  112  is cleaned with water. 
     Next, as illustrated in  FIG.  5 C , the electroless copper plating film  131  is formed on the surface of the first insulating layer  121 , the surface of the second insulating layer  122 , the wall surface of the second through hole  112 , and the wall surface of the third through hole  113 . Thereafter, the electrolytic copper plating film  132  is formed on the electroless copper plating film  131 , by electrolytic plating using the electroless copper plating film  131  as a plating feed line. For example, the electroless copper plating film  131  may have a thickness in a range of 0.3 μm to 1.0 μm, and the electrolytic copper plating film  132  may have a thickness in a range of 10 μm to 50 μm. 
     Next, as illustrated in  FIG.  6 A , the filler material  149  is filled into the second through hole  112  and the third through hole  113 . For example, the filler material  149  may be filled by screen printing. The filler material  149  is provided on the electrolytic copper plating film  132  inside the second through hole  112  and the third through hole  113 . Then, the filler material  149  is cured. If the filler material  149  includes a thermosetting resin, such as an epoxy resin or the like, the filler material  149  may be cured by a heat treatment. 
     Thereafter, as illustrated in  FIG.  6 B , the electrolytic copper plating film  132 , the electroless copper plating film  131 , and the filler material  149  are polished on the side closer to the first principal surface  102 A, until the surface of the first insulating layer  121  is exposed. In addition, the electrolytic copper plating film  132 , the electroless copper plating film  131 , and the filler material  149  are polished on the side closer to the second principal surface  102 B, until the surface of the second insulating layer  122  is exposed. As a result, the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  have surfaces which coincide with the surface of the first insulating layer  121 , and also have surfaces which coincide with the surface of the second insulating layer  122 . The electroless copper plating film  131  and electrolytic copper plating film  132 , after the polishing, are included in conductive layer  140 . For example, the electrolytic copper plating film  132 , the electroless copper plating film  131 , and the filler material  149  may be polished by a chemical mechanical polishing (CMP). The electrolytic copper plating film  132 , the electroless copper plating film  131 , and the filler material  149  may be polished as follows. First, portions of the electrolytic copper plating film  132  and the electroless copper plating film  131  on the surface of the first insulating layer  121 , and portions of the electrolytic copper plating film  132  and the electroless copper plating film  131  on the surface of the second insulating layer  122 , may be removed by wet etching. As a result, the surface of the first insulating layer  121 , and the surface of the second insulating layer  122 , are exposed. Then, portions of the filler material  149  protruding from the surface of the first insulating layer  121  and from the surface of the second insulating layer  122 , are removed by buffing or roll polishing. 
     Next, as illustrated in  FIG.  6 C , the electroless copper plating film  133 A is formed on the surface of the first insulating layer  121 , and on the surfaces of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the surface of the first insulating layer  121 . Similarly, the electroless copper plating film  133 B is formed on the surface of the second insulating layer  122 , and on the surfaces of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the surface of the second insulating layer  122 . Then, the electrolytic copper plating film  134 A is formed on the electroless copper plating film  133 A, by electrolytic plating using the electroless copper plating film  133 A as the plating feed line, and the electrolytic copper plating film  134 B is famed on the electroless copper plating film  133 B by electrolytic plating method using the electroless copper plating film  133 B as the plating feed line. For example, the electroless copper plating films  133 A and  133 B may have thicknesses in a range of 0.3 μm to 1.0 μm, and the electrolytic copper plating films  134 A and  134 B may have thicknesses in a range of 15 μm to 40 μm. 
     Thereafter, as illustrated in  FIG.  7 A , a resist layer  151 A, famed with a pattern of the first interconnect layer  141 , is formed on the electrolytic copper plating film  134 A, and a resist layer  151 B, formed with a pattern of the second interconnect layer  142 , is formed on the electrolytic copper plating film  134 B. The resist layers  151 A and  151 B may be a dry film or the like, for example, and the pattern may be formed in the resist layers  151 A and  151 B by exposure and development. 
     Next, as illustrated in  FIG.  7 B , the electrolytic copper plating film  134 A and the electroless copper plating film  133 A are wet etched, using the resist layer  151 A as a mask, and the electrolytic copper plating film  134 B and the electroless copper plating film  133 B are wet etched, using the resist layer  151 B as a mask. As a result, the first interconnect layer  141  and the second interconnect layer  142  are obtained. The first interconnect layer  141  includes the electroless copper plating film  133 A and the electrolytic copper plating film  134 A. The second interconnect layer  142  includes the electroless copper plating film  133 B and the electrolytic copper plating film  134 B. 
     Then, as illustrated in  FIG.  7 C , the resist layers  151 A and  151 B are removed. 
     Next, an uncured resin film is adhered on the first insulating layer  121 , so as to cover the first interconnect layer  141 , and an uncured resin film is adhered on the second insulating layer  122 , so as to cover the second interconnect layer  142 . Thereafter, these resin films are cured by a heat treatment, to form the third insulating layer  123  and the fourth insulating layer  124  illustrated in  FIG.  1   . The third insulating layer  123  and the fourth insulating layer  124  may be formed of an insulating resin, such as an epoxy resin, a polyimide resin, or the like. The third insulating layer  123  and the fourth insulating layer  124  may be formed by coating a liquid resin. Then, by subjecting the third insulating layer  123  and the fourth insulating layer  124  to a laser beam machining, the via hole  161  reaching the connection portion of the first interconnect layer  141  is formed in the third insulating layer  123 , and the via hole  162  reaching the connection portion of the second interconnect layer  142  is formed in the fourth insulating layer  124 , as illustrated in  FIG.  1   . 
     Next, the third interconnect layer  143 , which connects to the first interconnect layer  141  via the via conductor inside the via hole  161 , is famed on the third insulating layer  123 , and the fourth interconnect layer  144 , which connects to the second interconnect layer  142  via the via conductor inside the via hole  162 , is formed on the fourth insulating layer  124 , as illustrated in  FIG.  1   . 
     The third interconnect layer  143  and the fourth interconnect layer  144  may be formed by a semi-additive method. A more detailed description will be given on the method of forming the third interconnect layer  143 . First, a seed layer (not illustrated) made of copper or the like is formed on the third insulating layer  123 , and on the inner surface of the via hole  161 , by electroless plating or sputtering. Then, a plating resist layer (not illustrated), formed with an opening at the portion where the third interconnect layer  143  is to be formed, is formed on the seed layer. Further, a metal plating layer made of copper or the like is formed in the opening of the plating resist layer, by electrolytic plating using the seed layer as the plating feed line. Thereafter, the plating resist layer is removed. Then, the seed layer is removed by wet etching using the metal plated layer as a mask. In this manner, it is possible to form the third interconnect layer  143  including the seed layer and the metal plating layer. The fourth interconnect layer  144  may be formed in a similar manner to the third interconnect layer  143 . 
     After the third interconnect layer  143  and the fourth interconnect layer  144  are formed, the fifth insulating layer  125 , provided with the via hole  163  on the connection portion of the third interconnect layer  143 , is formed on the third insulating layer  123 , and the sixth insulating layer  126 , provided with the via hole  164  on the connection portion of the fourth interconnect layer  144 , is famed on the fourth insulating layer  124 , as illustrated in  FIG.  1   . The fifth insulating layer  125  and the sixth insulating layer  126  may be formed in a similar manner to the third insulating layer  123  and the fourth insulating layer  124 . 
     Further, the fifth interconnect layer  145 , which connects to the third interconnect layer  143  via the via conductor inside the via hole  163 , is famed on the fifth insulating layer  125 , and the sixth interconnect layer  146 , which connects to the fourth interconnect layer  144  via the via conductor inside the via hole  164 , is formed on the sixth insulating layer  126 , as illustrated in  FIG.  1   . The fifth interconnect layer  145  and the sixth interconnect layer  146  may be formed in a manner similar to the third interconnect layer  143  and the fourth interconnect layer  144 . 
     Next, a solder resist layer  127  is formed on the fifth insulating layer  125 , and a solder resist layer  128  is formed on the sixth insulating layer  126 , as illustrated in  FIG.  1   . Thereafter, the opening  165 , which reaches the connection portion of the fifth interconnect layer  145 , is formed in the solder resist layer  127 . In addition, an opening  166 , which reaches the connection portion of the sixth interconnect layer  146 , is formed in the solder resist layer  128 . 
     The solder resist layer  127  and the solder resist layer  128  are formed of an insulating resin, such as a photosensitive epoxy resin, a photosensitive acrylic resin, or the like. The solder resist layer  127  and the solder resist layer  128  may be formed by adhering a resin film, or by coating a liquid resin. The opening  165  and the opening  166  may be formed by exposure and development. An insulating resin, such as a non-photosensitive epoxy resin, a non-photosensitive polyimide resin, or the like, may be used for the solder resist layer  127  and the solder resist layer  128 . In this case, the opening  165  and the opening  166  may be formed by laser beam machining, blasting, or the like. 
     Next, the connection terminal  147 , which protrudes above the solder resist layer  127  via the opening  165 , is formed on the connection portion of the fifth interconnect layer  145 . The connection terminal  147  may include the post and the bump. 
     Next, the structure, which is subjected to the processes up to the forming of the connection terminal  147 , is cut along a predetermined cutting plane line by a slicer or the like. Hence, the structures respectively corresponding to the wiring board  100  are singulated from the large laminate  101 , and a plurality of wiring boards  100  according to the first embodiment are obtained. The wiring board  100  according to the first embodiment can be manufactured in this manner. 
     According to the method for manufacturing the wiring board described above, the first interconnect layer  141  and the second interconnect layer  142  can be made thin, and can easily be subjected to a fine pattern lithography. 
     The desmear process using a desmear liquid may be performed after formation of the via holes  161  through  164 . Because the surface of the magnetic material  110  is covered by the base  102 , the first insulating layer  121 , the second insulating layer  122 , and the conductive layer  140 , the magnetic material  110  is not exposed to the desmear liquid even if desmear process is performed. For this reason, it is possible to prevent the magnetic material  110  from being eroded by the desmear liquid. 
     In the method described method, the first interconnect layer  141  and the second interconnect layer  142  are formed by the subtractive method. However, the first interconnect layer  141  and the second interconnect layer  142  may be formed by the semi-additive method. When the first interconnect layer  141  and the second interconnect layer  142  are formed by the semi-additive method, the following processes may be performed. 
     That is, after polishing illustrated in  FIG.  6 B , the electroless copper plating film  133 A is formed on the surface of the first insulating layer  121 , and on the surfaces of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the surface of the first insulating layer  121 , as the seed layer. Similarly, the electroless copper plating film  133 B is formed on the surface of the second insulating layer  122 , and on the surfaces of the electroless copper plating film  131 , the electrolytic copper plating film  132 , and the filler material  149  coinciding with the surface of the second insulating layer  122 , as the seed layer. 
     Next, a plating resist layer (not illustrated), provided with an opening at the portion where the first interconnect layer  141  is to be formed, is formed on the electroless copper plating film  133 A. Then, the electrolytic copper plating film  134 A is formed in the opening of the plating resist layer, by electrolytic plating using the electroless copper plating film  133 A as the plating feed line. Similarly, a plating resist layer (not illustrated), provided with an opening at a portion where the second interconnect layer  142  is to be formed, is formed on the electroless copper plating film  133 B. Then, the electrolytic copper plating film  134 B is formed in the opening of the plating resist layer, by electrolytic plating using the electroless copper plating film  133 B as the plating feed line. Thereafter, the plating resist layers are removed. 
     Next, the electrolytic copper plating film  134 A is used as a mask, to remove a portion of the electroless copper plating film  133 A exposed from the electrolytic copper plating film  134 A, by wet etching. As a result, the first interconnect layer  141 , including the electroless copper plating film  133 A and the electrolytic copper plating film  134 A, is obtained. Similarly, the electrolytic copper plating film  134 B is used as a mask, to remove a portion of the electroless copper plating film  133 B exposed from the electrolytic copper plating film  134 B, by wet etching. As a result, the second interconnect layer  142 , including the electroless copper plating film  133 B and the electrolytic copper plating film  134 B, is obtained. 
     Second Embodiment 
     Next, a second embodiment will be described. The second embodiment differs from the first embodiment mainly in the structure of the conductive layer, the first interconnect layer, and the second interconnect layer. 
     [Structure of Wiring Board] 
     First, the structure of the wiring board will be described.  FIG.  8    is a cross sectional view illustrating the conductive layer  140 , the first interconnect layer  141 , and the second interconnect layer  142  according to the second embodiment. 
     As illustrated in  FIG.  8   , in the second embodiment, the conductive layer  140  includes portions of the electroless copper plating film  131  and the electrolytic copper plating film  132  formed on the surface of the first insulating layer  121  and the surface of the second insulating layer  122 . 
     The first interconnect layer  141  includes the electroless copper plating film  133 A, and the electrolytic copper plating film  134 A. The first interconnect layer  141  further includes portions of the electroless copper plating film  131  and the electrolytic copper plating film  132  which are on the outer side of the surface of the first insulating layer  121 . 
     The second interconnect layer  142  includes an electroless copper plating film  133 B, and the electrolytic copper plating film  134 B. The second interconnect layer  142  further includes portions of the electroless copper plating film  131  and the electrolytic copper plating film  132  which are on the outer side of the surface of the second insulating layer  122 . 
     The structure of other portions of the second embodiment are similar to those of the first embodiment. 
     Effects similar to those obtainable by the first embodiment can also be obtained by the second embodiment. 
     [Method for Manufacturing Wiring Board] 
     Next, the method for manufacturing the wiring board according to the second embodiment will be described.  FIG.  9 A  through  FIG.  10 B  are cross sectional views illustrating the method for manufacturing the wiring board according to the second embodiment. 
     First, the processes up to the filling of the filler material  149  is performed in a manner similar to those of the first embodiment, as illustrated in  FIG.  6 A . Then, as illustrated in  FIG.  9 A , the portions of the filler material  149 , protruding from the surfaces of the electrolytic copper plating film  132  on both sides of the base  102 , are removed by polishing. For example, the protruding portions of the filler material  149  can be removed by buffing or roll polishing. As a result, the filler material  149  has the surface which coincides with the surface of the electrolytic copper plating film  132  on the side closer to the first principal surface  102 A, and the surface which coincides with the surface of the electrolytic copper plating film  132  on the side closer to the second principal surface  102 B. Thereafter, a desmear process is performed on the surfaces of the electrolytic copper plating film  132 . 
     Then, as illustrated in  FIG.  9 B , the electroless copper plating film  133 A is formed on the surface of the electrolytic copper plating film  132 , and on the surface of the filler material  149  coinciding with the surface of the electrolytic copper plating film  132 , on the side closer to the first principal surface  102 A of the base  102 . Similarly, the electroless copper plating film  133 B is famed on the surface of the electrolytic copper plating film  132 , and on the surface of the filler material  149  coinciding with the surface of the electrolytic copper plating film  132 , on the side closer to the second principal surface  102 B of the base  102 . Furthermore, the electrolytic copper plating film  134 A is formed on the electroless copper plating film  133 A, by electrolytic plating using the electroless copper plating film  133 A as the plating feed line, and the electrolytic copper plating film  134 B is formed on the electroless copper plating film  133 B, by electrolytic plating using the electroless copper plating film  133 B as the plating feed line. 
     Thereafter, as illustrated in  FIG.  9 C , the resist layer  151 A is formed on the electrolytic copper plating film  134 A, and the resist layer  151 B is formed on the electrolytic copper plating film  134 B, similar to the first embodiment. 
     Next, as illustrated in  FIG.  10 A , the resist layer  151 A is used as a mask, to etch the electrolytic copper plating film  134 A, the electroless copper plating film  133 A, the electrolytic copper plating film  132 , and the electroless copper plating film  131 . In addition, the resist layer  151 B is used as a mask, to etch the electrolytic copper plating film  134 B, the electroless copper plating film  133 B, the electrolytic copper plating film  132 , and the electroless copper plating film  131 . As a result, the first interconnect layer  141  and the second interconnect layer  142  are obtained. 
     Then, as illustrated in  FIG.  10 B , the resist layer  151 A and the resist layer  151 B are removed. Thereafter, the processes of forming the third insulating layer  123  and the fourth insulating layer  124 , and subsequent processes, are performed similar to the first embodiment. 
     The wiring board according to the second embodiment can be manufactured in this manner. 
     Third Embodiment 
     Next, a third embodiment will be described. The third embodiment differs from the first embodiment mainly in the structure of the magnetic material. 
     [Structure of Wiring Board] 
     First, the structure of the wiring board will be described.  FIG.  11    is a cross sectional view illustrating the magnetic material  110  according to the third embodiment. 
     As illustrated in  FIG.  11   , in the third embodiment, the thickness of the magnetic material  110  is the same as the thickness of the base  102 . The first surface  110 A of the magnetic material  110  coincides with the first principal surface  102 A, and the second surface  110 B of the magnetic material  110  coincides with the second principal surface  102 B. That is, the distance from the center C along the thickness direction of the base  102  to the first surface  110 A, is equal to the distance from the center C to the first principal surface  102 A. In addition, the distance from the center C to the surface  110 B, is equal to the distance from the center C to the second principal surface  102 B. 
     The structure of other portions of the third embodiment are similar to those of the first embodiment. 
     Effects similar to those obtainable by the first embodiment can also be obtained by the third embodiment. 
     [Method for Manufacturing Wiring Board] 
     Next, the method for manufacturing the wiring board according to the third embodiment will be described.  FIG.  12 A  through  FIG.  13 B  are cross sectional views illustrating the method for manufacturing the wiring board according to the third embodiment. 
     First, as illustrated in  FIG.  12 A , the insulating base  102  without the conductive films  103 A and  103 B is prepared. The large substrate from which a plurality of wiring boards can be singulated, may be used as the base  102 . That is, the base  102  includes a plurality of regions (or areas) where structures, respectively corresponding to the wiring board  100 , are formed. 
     Next, as illustrated in  FIG.  12 B , the first through hole  111  is formed in the base  102 . For example, the first through hole  111  may be formed by drilling, laser beam machining, or the like. Thereafter, a desmear process is performed on the wall surface of the first through hole  111 . 
     Then, as illustrated in  FIG.  13 A , the magnetic material  110  is filled inside the first through hole  111 . 
     Next, as illustrated in  FIG.  13 B , the portions of the magnetic material  110 , protruding from the first principal surface  102 A and the second principal surface  102 B of the base  102 , are removed by polishing. For example, the protruding portions of the magnetic material  110  may be removed by buffing or roll polishing. The magnetic material  110 , after the polishing, includes the first surface  110 A coinciding with the first principal surface  102 A, ad the second surface  110 B coinciding with the second principal surface  102 B. Thereafter, the processes of forming the first insulating layer  121  and the second insulating layer  122 , and subsequent processes, are performed similar to the first embodiment. 
     The wiring board according to the third embodiment can be manufactured in this manner. 
     Fourth Embodiment 
     Next, a fourth embodiment will be described. The fourth embodiment differs from the second embodiment mainly in the structure of the magnetic material. 
     [Structure of Wiring Board] 
     First, the structure of the wiring board will be described.  FIG.  14    is a cross sectional view illustrating the magnetic material  110  according to the fourth embodiment. 
     As illustrated in  FIG.  14   , in the fourth embodiment, the thickness of the magnetic material  110  is the same as the thickness of the base  102 , similar to the third embodiment. The first surface  110 A of the magnetic material  110  coincides with the first principal surface  102 A, and the second surface  110 B of the magnetic material  110  coincides with the second principal surface  102 B. That is, the distance from the center C along the thickness direction of the base  102  to the first surface  110 A, is equal to the distance from the center C to the first principal surface  102 A. In addition, the distance from the center C to the second surface  110 B, is equal to the distance from the center C to the second principal surface  102 B. 
     The structure of other portions of the fourth embodiment are similar to those of the second embodiment. 
     Effects similar to those obtainable by the second embodiment can also be obtained by the third embodiment. 
     [Method for Manufacturing Wiring Board] 
     Next, the method for manufacturing the wiring board according to the fourth embodiment will be described. 
     First, the insulating base  102  without the conductive films  103 A and  103 B is prepared, similar to the third embodiment. Then, the processes from the formation of the first through hole  111  to the polishing of the magnetic material  110  are performed, similar to the third embodiment. Thereafter, the processes of forming the first insulating layer  121  and the second insulating layer  122 , and subsequent processes, are performed similar to the second embodiment. 
     The wiring board according to the fourth embodiment can be manufactured in this manner. 
     Fifth Embodiment 
     Next, a fifth embodiment will be described. The fifth embodiment relates to a semiconductor package.  FIG.  15    is a cross sectional view illustrating a semiconductor package  500  according to the fifth embodiment. 
     As illustrated in  FIG.  15   , the semiconductor package  500  according to the fifth embodiment includes the wiring board  100  according to the first embodiment, a semiconductor chip  300 , bumps  312 , and an underfill resin  330 . 
     The semiconductor chip  300  includes connection terminals  311  which connect to the connection terminals  147  via the bumps  312 . The connection terminals  311  are electrode pads, for example. Solder balls may be used for the bumps  312 , for example. Examples of the solder ball material include Pb-free solders, such as tin silver (SnAg) based alloys, tin zinc (SnZn) based alloys, tin copper (SnCu) based alloys, or the like, and lead-based solders such as lead tin (PbSn) based alloys or the like. The underfill resin  330 , such as an epoxy resin or the like, is filled in between the semiconductor chip  300  and the solder resist layer  127  of the wiring board  100 . 
     When manufacturing the semiconductor package  500 , the singulated wiring board  100  is prepared, and the bumps  312  are used to mount the semiconductor chip  300  onto the wiring board  100  by flip-chip bonding. After mounting the semiconductor chip  300  on the wiring board  100 , the underfill resin  330  is filled in between the semiconductor chip  300  and the solder resist layer  127 . 
     The semiconductor package  500  according to the fifth embodiment can be manufactured in this manner. 
     The wiring board according to one of the second, third, and fourth embodiments may be used in place of the wiring board  100  according to the first embodiment. 
     In the present disclosure, the magnetic material  110  is an example of a functional material, and the functional material is not limited to the magnetic material. 
     In the present disclosure, the material of the conductive layer is not limited to copper, and the conductive layer may include a plating film of other metals, such as nickel or the like. 
     Accordingly to each of the embodiments described above, it is possible to provide a wiring board having a fine interconnect layer, and a method for manufacturing the wiring boards. 
     Various aspects of the subject-matter described herein may be set out non-exhaustively in the following numbered clauses: 
     1. A method of manufacturing a wiring board, comprising: 
     forming a first through hole in an insulating base having a first principal surface and a second principal surface opposite to the first principal surface, the first through hole penetrating the insulating base from the principal surface to the second principal surface; 
     providing a functional material inside the first through hole; 
     forming a first insulating layer covering the first principal surface, and a first surface of the functional material on the side closer to the first principal surface; 
     forming a second insulating layer covering the second principal surface, and a second surface of the functional material on the side closer to the second principal surface; 
     forming a second through hole in the first insulating layer, the functional material, and the second insulating layer; 
     providing a conductive layer on a wall surface of the second through hole. 
     2. The method for manufacturing the wiring board according to clause 1, wherein the forming the conductive layer includes 
     forming an electroless plating film on a surface of the first insulating layer, a surface of the second insulating layer, and the wall surface of the second through hole, 
     forming an electrolytic plating film on the electroless plating film, 
     polishing the electrolytic plating film and the electroless plating film until the surface of the first insulating layer is exposed, and 
     polishing the electrolytic plating film and the electroless plating film until the surface of the second insulating layer is exposed. 
     3. The method for manufacturing the wiring board according to clause 1 or 2, further comprising: 
     forming a first interconnect layer on the first insulating layer, the first interconnect layer connecting to the conductive layer; and 
     forming a second interconnect layer on the second insulating layer, the second interconnect layer connecting to the conductive layer. 
     4. The method for manufacturing the wiring board according to any one of clauses 1 to 3, further comprising: 
     filling the second through hole with an insulating filler material on an inner side of the conductive layer. 
     5. The method for manufacturing the wiring board according to any one of clauses 1 to 4, wherein the functional material includes a magnetic material. 
     Although the embodiments are numbered with, for example, “first,” “second,” “third,” “fourth,” or “fifth,” the ordinal numbers do not imply priorities of the embodiments. Many other variations and modifications will be apparent to those skilled in the art. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiments of the present invention have been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.