Patent Publication Number: US-11664418-B2

Title: Semiconductor devices having gate isolation layers

Description:
CROSS-REFERENCE TO THE RELATED APPLICATION 
     Korean Patent Application No. 10-2021-0016530, filed on Feb. 5, 2021, in the Korean Intellectual Property Office, and entitled: “Semiconductor Devices Having Gate Isolation Layers,” is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Field 
     Exemplary embodiments of the disclosure relate to a semiconductor device having a gate isolation layer. 
     2. Description of the Related Art 
     In accordance with a tendency of semiconductor devices toward miniaturization, technology associated with a FinFET or a multi-bridge channel transistor, which has a three-dimensional structure, has been introduced in order to reduce a short channel effect. 
     SUMMARY 
     A semiconductor device according to exemplary embodiments of the disclosure may include active regions disposed on a substrate, a gate structure intersecting the active regions, a source/drain region disposed on the active regions while being disposed at a side surface of the gate structure, a gate spacer disposed between the gate structure and the source/drain region while contacting the side surface of the gate structure, a lower source/drain contact plug connected to the source/drain region, a gate isolation layer disposed on the gate spacer, an upper end of the gate isolation layer being disposed at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug while extending through the capping layer. 
     A semiconductor device according to exemplary embodiments of the disclosure may include active regions disposed on a substrate, channel layers disposed on the active regions while being vertically spaced apart from one another, a gate structure intersecting the active regions while surrounding the channel layers, the gate structure including a gate electrode, and a gate insulating layer between the channel layers and the gate electrode, a source/drain region disposed on the active regions while being disposed at a side surface of the gate structure, a gate spacer disposed between the gate structure and the source/drain region while contacting the side surface of the gate structure, an inner spacer disposed under the channel layers while contacting a side surface of the source/drain region, a lower source/drain contact plug disposed on the source/drain region, a gate isolation layer disposed on the gate spacer, an upper end of the gate isolation layer being disposed at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug and the gate isolation layer, and an upper source/drain contact plug connected to the lower source/drain contact plug while extending through the capping layer. 
     A semiconductor device according to exemplary embodiments of the disclosure may include active regions disposed on a substrate while extending in a first horizontal direction, the active regions being spaced apart from one another in a second horizontal direction intersecting the first horizontal direction, a gate structure intersecting the active regions while extending in the second horizontal direction, a source/drain region disposed on the active regions while being disposed at a side surface of the gate structure, a gate spacer disposed between the gate structure and the source/drain region while contacting the side surface of the gate structure, an interlayer insulating layer covering the source/drain region, a lower source/drain contact plug connected to the source/drain region while extending through the interlayer insulating layer, a gate isolation layer covering the gate spacer and the interlayer insulating layer, an upper end of the gate isolation layer being disposed at a higher level than an upper surface of the gate structure and an upper surface of the lower source/drain contact plug, a capping layer covering the gate structure, the lower source/drain contact plug and the gate isolation layer, an upper insulating layer covering the capping layer, and an upper source/drain contact plug connected to the lower source/drain contact plug while extending through the capping layer and the upper insulating layer. The upper surface of the gate structure may be disposed at a lower level than the upper surface of the lower source/drain contact plug. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings, in which: 
         FIG.  1    is a layout of a semiconductor device according to an example embodiment. 
         FIGS.  2 A and  2 B  are vertical cross-sectional views along lines I-I′, II-II′ III-III′ and IV-IV′ in  FIG.  1   . 
         FIG.  3    are enlarged views of contact plugs in the semiconductor device of  FIG.  2 A . 
         FIGS.  4 A to  16 B  are vertical cross-sectional views of stages in a method of manufacturing the semiconductor device shown in  FIGS.  2 A and  2 B . 
         FIGS.  17  to  19    are vertical cross-sectional views of contact plugs in semiconductor devices according to example embodiments. 
         FIGS.  20 A and  20 B  are vertical cross-sectional views of a semiconductor device according to an example embodiment. 
         FIGS.  21 A and  21 B  are vertical cross-sectional views of a semiconductor device according to an example embodiment. 
         FIG.  22    is an enlarged view of a contact plug in the semiconductor device shown in  FIG.  21 A . 
         FIGS.  23 A to  24 B  are vertical cross-sectional views of stages in a method of manufacturing the semiconductor device shown in  FIGS.  21 A and  21 B . 
         FIGS.  25  to  27    are vertical cross-sectional views of semiconductor devices according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is a layout of a semiconductor device according to an example embodiment.  FIGS.  2 A and  2 B  illustrate vertical cross-sectional views along lines I-I′, II-II′ III-III′ and IV-IV′ in  FIG.  1   , and  FIG.  3    illustrates enlarged views of portions of the semiconductor device in  FIG.  2 A . 
     Referring to  FIGS.  1  to  3   , a semiconductor device  100  may include a substrate  102 , an element isolation layer  110 , gate structures  120 , gate spacers  130 , source/drain regions SD, an interlayer insulating layer  140 , upper spacers  150 , lower source/drain contact plugs  160 , gate isolation layers  172 , an upper insulating layer  180 , gate contact plugs  181 , and upper source/drain contact plugs  184 . 
     The substrate  102  may include active regions AR extending in a first horizontal direction D 1  while being spaced apart from one another in a second horizontal direction D 2 . In an embodiment, the active regions AR may protrude upwards from an upper surface of the substrate  102 , and may have a fin shape. The substrate  102  may include a semiconductor material. For example, the substrate  102  may be a silicon substrate, a germanium substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate. The active regions AR may include the same material as the substrate  102 . 
     The element isolation layer  110  may be disposed on the upper surface of the substrate  102 , and may define the active regions AR. The element isolation layer  110  may cover the upper surface of the substrate  102 , and may partially cover side surfaces of the active regions AR. Upper surfaces of the active regions AR may be disposed at a higher level than an upper surface of the element isolation layer  110 . In an embodiment, the element isolation layer  110  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. 
     The gate structures  120  may extend in the second horizontal direction D 2  while being spaced apart from one another in the first horizontal direction D 1 . The gate structures  120  may intersect the active regions AR. Each gate structure  120  may include a gate insulating layer  122  and a gate electrode  124 . The gate insulating layer  122  may surround a lower surface and a side surface of the gate electrode  124 , and may extend in the second horizontal direction D 2 . The gate insulating layer  122  may cover the element isolation layer  110  and a portion of a corresponding one of the active regions AR protruding upward beyond the element isolation layer  110 . The gate electrode  124  may be disposed on the gate insulating layer  122 , and may extend in the second horizontal direction D 2 . The gate structure  120  may further include a metal layer disposed between the gate insulating layer  122  and the gate electrode  124 , to adjust a work function of the gate electrode  124 . 
     The gate insulating layer  122  may include a high-k dielectric material, e.g., hafnium oxide, hafnium oxynitride, etc. The gate electrode  124  may include at least one of, e.g., W, Al, Co, Ti, Ta, poly-Si, SiGe, or a metal alloy thereof. 
     The gate spacers  130  may be disposed at side surfaces of the gate structures  120 , and may extend in the second horizontal direction D 2 . For example, each pair of gate spacers  130  may be disposed to correspond to each of the gate structures  120 , such that the gate spacers  130  of the pair may face each other while contacting the gate insulating layer  122  of the corresponding gate structure  120  under the condition in which the gate electrode  124  of the corresponding gate structure  120  is interposed between the gate spacers  130 . As shown in  FIG.  3   , an upper surface of each gate spacer  130  may be an inclined surface, e.g., an entirety of the upper surface of each gate spacer  130  may curve downwardly to have a concave shape. For example, as further illustrated in  FIG.  3   , the height of the gate spacer  130  may be gradually reduced as the upper surface of the gate spacer  130  becomes nearer to a corresponding, e.g., adjacent, gate structure  120 . An upper end of the gate spacer  130  may be disposed at a higher level than an upper surface of the corresponding, e.g., adjacent, gate structure  120 . For example, an upper end of the upper surface of the gate spacer  130  may be disposed at the same level as an upper surface of a corresponding one of the lower source/drain contact plugs  160 , and a lower end of the upper surface of the gate spacer  130  may be disposed at the same level as the upper surface of the gate structure  120 , e.g., the upper surface of the gate spacer  130  may curve downwardly from the upper surface of the lower source/drain contact plugs  160  toward the upper surface of the gate structure  120 . In an embodiment, the gate spacer  130  may be constituted by one or more layers. The gate spacer  130  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. 
     The source/drain regions SD may be disposed on the active regions AR, and may be disposed at opposite sides of the gate structures  120 . Although a merged structure of the source/drain regions SD on the active regions AR spaced apart from one another in the second horizontal direction D 2  is shown in  FIG.  2 B , the exemplary embodiments of the disclosure are not limited thereto. In an embodiment, the source/drain regions SD may be spaced apart from one another in the second horizontal direction D 2 . The source/drain regions SD may be semiconductor layers epitaxially grown from the active regions AR. The source/drain regions SD may apply compressive stress or tensile stress to the active regions AR, and may include an n-type impurity or a p-type impurity. 
     The interlayer insulating layer  140  may cover the element isolation layer  110  and the source/drain regions SD. The interlayer insulating layer  140  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material, and may be constituted by one or more layers. The low-k dielectric material may include, e.g., undoped silicate glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma enhanced tetraethylorthosilicate (PETEOS), fluoride silicate glass (FSG), a high density plasma (HDP) oxide, or a combination thereof. 
     The upper spacers  150  may be disposed at the side surfaces of the gate structures  120 . For example, the upper spacers  150  may be disposed on the gate spacers  130 , respectively, while extending in the second horizontal direction D 2 . For example, as illustrated in  FIG.  3   , the upper spacers  150  may be on the inclined, e.g., curved, upper surface of the gate spacers  130 , respectively. As further illustrated in  FIG.  3   , each upper spacer  150  may include an upper surface  151   a  and a side surface  151   b . The upper surface  151   a  of the upper spacer  150  may be disposed at a higher level than the upper surface of a corresponding one of the gate structures  120 , and may be coplanar with an upper surface of a corresponding one of the lower source/drain contact plugs  160 . The side surface  151   b  of the upper spacer  150  may be an inclined, e.g., curved, surface, and a lower end of the side surface  151   b  of the upper spacer  150  may be disposed at the same level as the upper surface of the corresponding gate structure  120 . The upper spacers  150  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the upper spacers  150  may include silicon nitride. 
     Each of the lower source/drain contact plugs  160  may include a lower source/drain contact conductive layer  161  and a lower contact barrier layer  162 . The lower source/drain contact plugs  160  may extend through the interlayer insulating layer  140 , and may be connected to the source/drain regions SD, respectively. The lower source/drain contact plugs  160  may extend in the second horizontal direction D 2  along the source/drain regions SD, and may be electrically connected to the source/drain regions SD, respectively. In addition, the lower source/drain contact plugs  160  may be disposed at opposite sides of the gate structures  120  while contacting the gate spacers  130 . The lower contact barrier layer  162  may surround a side surface and a lower surface of the lower source/drain contact conductive layer  161 . The lower contact barrier layer  162  may contact corresponding ones of the gate spacers  130 , a corresponding one of the source/drain regions SD, and the interlayer insulating layer  140 . The source/drain region SD may include a silicide layer at a portion thereof contacting the lower source/drain contact plug  160 . The upper surface of the lower source/drain contact plug  160  may be disposed at the same level as an upper surface of the interlayer insulating layer  140 . As shown in  FIG.  3   , the upper surface of the lower source/drain contact plug  160  may be disposed at a higher level than the upper surface of the corresponding gate structure  120 . 
     The lower source/drain contact conductive layer  161  may include, e.g., W, Co, Ru, Mo, or a combination thereof. The lower contact barrier layer  162  may include, e.g., Ti, TiN, Ta, TaN, or a combination thereof. 
     Each of the gate isolation layers  172  may be disposed on a corresponding one of the gate spacers  130 , and may be disposed between corresponding ones of the gate structures  120  and the lower source/drain contact plugs  160 . For example, the gate isolation layer  172  may contact a corresponding one of the upper spacers  150  while extending in the second horizontal direction D 2 , e.g., each upper spacer  150  may be between a corresponding gate spacer  130  and a respective gate isolation layer  172 . The gate isolation layer  172  may electrically insulate the corresponding gate electrode  124  from a corresponding one of the upper source/drain contact plugs  184 , and may electrically insulate the corresponding lower source/drain contact plug  160  from a corresponding one of the gate contact plugs  181 . In addition, as shown in  FIG.  2 B , the gate isolation layer  172  may cover the upper surface of the interlayer insulating layer  140 . 
     As shown in  FIG.  3   , the gate isolation layer  172  may have a round cross-section, e.g., as viewed from a vertical cross-sectional view of  FIG.  3   . An upper end of the gate isolation layer  172  may be disposed at a higher level than the upper surface of the corresponding gate structure  120  and the corresponding lower source/drain contact plug  160 . For example, as further illustrated in  FIG.  3   , a topmost part of the gate isolation layer  172  may be at a higher level than the upper surface of the corresponding gate structure  120  and the upper surface of the lower source/drain contact plug  160  relative to the bottom of the substrate  102 . For example, the upper end of the gate isolation layer  172  may extend above each of the upper surface of the corresponding gate structure  120  and the upper surface of the lower source/drain contact plug  160 , e.g., so the curved surfaces of the gate isolation layer  172  may be above the corresponding gate structure  120  and the corresponding lower source/drain contact plug  160 . Although the gate isolation layer  172  is shown as being disposed only on the corresponding upper spacer  150 , the exemplary embodiments of the disclosure are not limited thereto. In an embodiment, the gate isolation layer  172  may partially cover the upper surface of the lower source/drain contact plug  160  or the gate structure  120 . 
     The gate isolation layer  172  may include, e.g., silicon oxide, silicon nitride, aluminum oxide, or a combination thereof. In an embodiment, the gate isolation layer  172  may include aluminum oxide. The maximum horizontal width of the gate isolation layer  172 , e.g., along the first horizontal direction D 1 , may be about 6 nm to about 10 nm, and the maximum vertical width of the gate isolation layer  172 , e.g., along a direction perpendicular to the first and second horizontal directions D 1  and D 2 , may be about 6 nm to about 10 nm. 
     The semiconductor device  100  may further include a capping layer  174 . The capping layer  174  may cover the gate isolation layers  172  while extending in a horizontal direction. For example, the capping layer  174  may be conformally disposed along upper surfaces of the gate structures  120 , the lower source/drain contact plugs  160 , and the gate isolation layers  172 . The capping layer  174  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the capping layer  174  may include silicon nitride. 
     The upper insulating layer  180  may cover an upper surface of the capping layer  174 . The upper insulating layer  180  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. 
     The gate contact plugs  181  may be disposed on the gate structures  120 , respectively. For example, the gate contact plugs  181  may be connected to the gate electrodes  124 , respectively, while extending through the capping layer  174  and the upper insulating layer  180 . The gate contact plugs  181  may be electrically connected to the gate structures  120 , but may not be electrically connected to the lower source/drain contact plugs  160 . Although a lower surface of each gate contact plug  181  is shown as being disposed at the same level as an upper surface of a corresponding one of the gate structures  120  in  FIG.  2 A , the exemplary embodiments of the disclosure are not limited thereto. In an embodiment, the gate contact plug  181  may partially extend through the gate structure  120 , and the lower surface of the gate contact plug  181  may be disposed at a lower level than the upper surface of the gate structure  120 . 
     The gate contact plug  181  may include a gate contact conductive layer  182  and a gate barrier layer  183 . The gate barrier layer  183  may surround a side surface and a lower surface of the gate contact conductive layer  182 . The gate barrier layer  183  may contact the gate structure  120 , the capping layer  174 , and the upper insulating layer  180 . In an embodiment, the gate contact plug  181  may be vertically misaligned from the gate structure  120 , and may contact a corresponding one of the gate isolation layers  172 . As shown in  FIG.  3   , the gate barrier layer  183  may contact the upper surface of the gate structure  120  and an upper surface of the corresponding gate isolation layer  172 . The gate contact plug  181  may be concave at a portion thereof contacting the gate isolation layer  172 . 
     The gate contact conductive layer  182  may include, e.g., W, Co, Ru, Mo, or a combination thereof. The gate barrier layer  183  may include, e.g., Ti, TiN, Ta, TaN, or a combination thereof. 
     The upper source/drain contact plugs  184  may be disposed on the lower source/drain contact plugs  160 , respectively. For example, each upper source/drain contact plug  184  may be connected to the lower source/drain contact conductive layer  161  of a corresponding one of the lower source/drain contact plugs  160  while extending through the capping layer  174  and the upper insulating layer  180 . The upper source/drain contact plugs  184  may be electrically connected to the lower source/drain contact plugs  160 , but may not be electrically connected to the gate structures  120 . 
     In an embodiment, the upper source/drain contact plugs  184  may be disposed on a part of the active regions AR. However, the gate contact plugs  181  may be disposed on the active regions AR different from the active regions AR on which the upper source/drain contact plugs  184  are disposed. As shown in  FIG.  1   , the upper source/drain contact plugs  184  may be misaligned with respect to the gate contact plugs  181  in the first horizontal direction D 1  and the second horizontal direction D 2 . 
     Although lower surfaces of the upper source/drain contact plugs  184  are shown as being disposed at the same level as upper surfaces of the lower source/drain contact plugs  160  in  FIG.  2 A , the exemplary embodiments of the disclosure are not limited thereto. In an embodiment, each upper source/drain contact plug  184  may partially extend through a corresponding one of the lower source/drain contact plugs  160 , and the lower surface of the upper source/drain contact plug  184  may be disposed at a lower level than the upper surface of the corresponding lower source/drain contact plug  160 . 
     The upper source/drain contact plug  184  may include an upper source/drain contact conductive layer  185  and an upper contact barrier layer  186 . The upper contact barrier layer  186  may surround a side surface and a lower surface of the upper source/drain contact conductive layer  185 . In an embodiment, the upper source/drain contact plug  184  may be vertically misaligned with the lower source/drain contact plug  160 , and may contact a corresponding one of the gate isolation layers  172 . As shown in  FIG.  3   , the upper contact barrier layer  186  may, e.g., directly, contact the upper surface of the lower source/drain contact plug  160  and the upper surface of the corresponding gate isolation layer  172 . The upper source/drain contact plug  184  may be concave at a portion thereof contacting the gate isolation layer  172 . 
     The upper source/drain contact conductive layer  185  may include the same material as the gate contact conductive layer  182 . The upper contact barrier layer  186  may include the same material as the gate barrier layer  183 . 
       FIGS.  4 A to  16 B  are vertical cross-sectional views illustrating stages in a method of manufacturing the semiconductor device shown in  FIGS.  2 A and  2 B . Description of configurations described previously with reference to  FIGS.  1  to  3    will not be repeated. 
     Referring to  FIGS.  4 A and  4 B , the substrate  102 , the active regions AR on the substrate  102 , the element isolation layer  110  covering lower portions of the active regions AR, the gate structures  120  intersecting the active regions AR, the gate spacers  130  contacting side surfaces of the gate structures  120 , the source/drain regions SD disposed on the active regions AR while contacting the gate spacers  130 , and the interlayer insulating layer  140  covering the source/drain regions SD may be provided. 
     Each gate structure  120  may include the gate insulating layer  122 , the gate electrode  124 , and a gate capping layer  126 . The gate capping layer  126  may be disposed on the gate insulating layer  122  and the gate electrode  124  while being disposed between adjacent ones of the gate spacers  130 . In an embodiment, the gate structures  120  may be formed through a replacement metal gate (RMG) process. For example, the gate structures  120  may be formed by forming the source/drain regions SD and an interlayer insulating layer  140  covering the source/drain regions SD, removing a dummy gate electrode among the gate spacers  130 , and depositing an insulating material, a conductive material, and a capping material among the gate spacers  130 . 
     Referring to  FIGS.  5 A and  5 B , the gate structures  120  and the gate spacers  130  may be recessed. That is, the gate capping layer  126  may be removed and, as such, the gate insulating layer  122  and the gate electrode  124  may be exposed. An upper surface of each gate spacer  310 , which is recessed, may not be flat. As described with reference to  FIG.  3   , the height of the gate spacer  130  may be gradually reduced as the upper surface of the gate spacer  130  becomes nearer to the corresponding gate structure  120 . The interlayer insulating layer  140  may not be removed, and may protrude upwards beyond the gate structures  120 . 
     An upper spacer  150   a  and an etch stop layer  152  may be formed on the recessed gate structures  120  and the interlayer insulating layer  140 . The upper spacer  150   a  may be formed by conformally depositing an insulating material along upper surfaces of the gate structures  120  and the interlayer insulating layer  140 , and anisotropically etching the insulating material such that the gate structures  120  are exposed. For example, the upper spacer  150   a  may be formed through an etch-back process. The upper spacer  150   a  may contact the upper surfaces of the gate spacers  130  while partially covering a side surface of the interlayer insulating layer  140 . In an embodiment, the upper spacer  150   a  may include, e.g., silicon nitride. 
     The etch stop layer  152  may be formed by conformally depositing an insulating material on the gate structures  120 , the interlayer insulating layer  140  and the upper spacer  150   a  after formation of the upper spacer  150   a . The etch stop layer  152  may cover the gate structures  120  and the interlayer insulating layer  140 . The etch stop layer  152  may include, e.g., silicon oxycarbide (SiOC) or silicon carbide (SiC). In an embodiment, the etch stop layer  152  may include silicon carbide. 
     Referring to  FIGS.  6 A and  6 B , an insulating layer  154  may be deposited on the etch stop layer  152 . The insulating layer  154  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In an embodiment, the insulating layer  154  may include silicon oxide. 
     Referring to  FIGS.  7 A and  7 B , a planarization process may be performed to expose the upper surface of the interlayer insulating layer  140 . The interlayer insulating layer  140  and the etch stop layer  152  may be partially removed by the planarization process. The planarized etch stop layer  152  may cover the upper surfaces of the gate structures  120  and a side surface of the upper spacer  150   a . The insulating layer  154  may be disposed on the etch stop layer  152 , and an upper surface of the insulating layer  154  may be coplanar with the upper surface of the interlayer insulating layer  140 . 
     Referring to  FIGS.  8 A and  8 B , portions of the interlayer insulating layer  140  among the gate structures  120  may be anisotropically etched. Etching of the interlayer insulating layer  140  may include forming a hard mask on the resultant structure of  FIGS.  7 A and  7 B , patterning the hard mask such that the interlayer insulating layer  140  is exposed, and etching the exposed interlayer insulating layer  140 . The etching process may include a dry etching process. In accordance with the etching process, the source/drain regions SD may be exposed. In an embodiment, upper portions of the source/drain regions SD may be partially removed. The upper spacer  150   a , the etch stop layer  152  and the insulating layer  154  may also be partially removed. The upper spacer  150   a  may protect the gate structures  120  during the etching process such that the gate structures  120  may be prevented from being etched. 
     Referring to  FIGS.  9 A and  9 B , a conductive material  160   a  and a barrier material  162   a  may be deposited on the resultant structure of  FIGS.  8 A and  8 B . The barrier material  162   a  may be conformally formed along surfaces of the source/drain regions SD, the gate structures  120 , the interlayer insulating layer  140 , the upper spacer  150   a , the etch stop layer  152 , and the insulating layer  154 . The conductive material  160   a  may be formed on the barrier material  162   a , and may fill a space among the gate structures  120 . The conductive material  160   a  may include, e.g., W, Co, Ru, Mo, or a combination thereof. The barrier material  162   a  may include, e.g., Ti, TiN, Ta, TaN, or a combination thereof. 
     Referring to  FIGS.  10 A and  10 B , a planarization process may be performed to remove the insulating layer  154 . The etch stop layer  152  may protect the gate structures  120  during the planarization process such that the gate structures  120  may be prevented from being etched. In the planarization process, the conductive material  160   a  and the barrier material  162   a  may be etched, thereby forming lower source/drain contact conductive layers  161  and lower contact barrier layers  162 . The lower source/drain contact conductive layers  161  and the lower contact barrier layers  162  may constitute the lower source/drain contact plugs  160 . The lower source/drain contact plugs  160  may be horizontally spaced apart from one another, and may be disposed at opposite sides of the gate structures  120 . Upper spacers  150  may be formed as the upper spacer  150   a  is etched through the planarization process. Upper surfaces of the lower source/drain contact plugs  160  may be coplanar with the upper surface of the interlayer insulating layer  140 , upper surfaces of the upper spacers  150 , and an upper surface of the etch stop layer  152 . 
     Referring to  FIGS.  11 A and  11 B , the etch stop layer  152  may be removed, thereby exposing the gate structures  120 . Removal of the etch stop layer  152  may include performing an ashing process. The etch stop layer  152  may be selectively removed, and the upper spacers  150  and the lower source/drain contact plugs  160  may not be etched. The upper surfaces of the gate structures  120  may be disposed at a lower level than the upper surfaces of the upper spacers  150  and the lower source/drain contact plugs  160 . 
     Referring to  FIGS.  12 A and  12 B , suppressants  170  may be selectively formed on the resultant structure of  FIGS.  11 A and  11 B . For example, the suppressants  170  may cover the gate structures  120  and the lower source/drain contact plugs  160 , but may not cover the interlayer insulating layer  140  and the upper spacers  150 . In an embodiment, the suppressants  170  may incompletely cover the gate structures  120  and the lower source/drain contact plugs  160  and, as such, the gate structures  120  and the lower source/drain contact plugs  160  may be partially exposed. In an embodiment, the suppressants  170  may include polymer. 
     Referring to  FIGS.  13 A and  13 B , the gate isolation layers  172  may be selectively formed on the upper spacers  150 . For example, the gate isolation layers  172  may be formed through upward growth thereof from surfaces of the upper spacers  150 , e.g., each gate isolation layer  172  may be grown from a corresponding upper spacer  150  to contact facing corners of a corresponding gate structure  120  and an adjacent lower source/drain contact plug  160 . The gate isolation layers  172  may have a round cross-section. In addition, the gate isolation layers  172  may be formed on the upper surface of the interlayer insulating layer  140 . In an embodiment, formation of the gate isolation layers  172  may include performing an atomic layer deposition (ALD) process. The gate isolation layers  172  may include, e.g., silicon oxide, silicon nitride, aluminum oxide, or a combination thereof. 
     Referring to  FIGS.  14 A and  14 B , the suppressants  170  may be selectively removed and, as such, the gate structures  120  and the lower source/drain contact plugs  160  may be exposed. In an embodiment, the suppressants  170  may remain on the upper surfaces of the gate structures  120  or the upper surfaces of the lower source/drain contact plugs  160  without being completely removed. 
     Referring to  FIGS.  15 A and  15 B , the capping layer  174  and the upper insulating layer  180  may be formed on the resultant structure of  FIGS.  14 A and  14 B . Formation of the capping layer  174  may include performing a chemical vapor deposition (CVD) process or an ALD process. The capping layer  174  may be conformally disposed along the upper surfaces of the gate structures  120  and the lower source/drain contact plugs  160  and upper surfaces of the gate isolation layers  172 . In an embodiment, the capping layer  174  may include silicon nitride. 
     The upper insulating layer  180  may be formed on the capping layer  174 . The upper insulating layer  180  may be deposited through, e.g., a CVD process or an ALD process. In an embodiment, the upper insulating layer  180  may include, e.g., silicon oxide, silicon nitride, silicon oxynitride, or a low-k dielectric material. 
     Referring to  FIGS.  16 A and  16 B , openings OP may be formed to expose the gate structures  120  and the lower source/drain contact plugs  160  therethrough. Formation of the openings OP may include anisotropically etching the capping layer  174  and the upper interlayer insulating layer  140 . In an embodiment, the gate structures  120  and the lower source/drain contact plugs  160  may be partially etched through the etching process. 
     In an embodiment, the openings OP may be vertically misaligned relative to the gate structures  120  or the lower source/drain contact plugs  160  due to process deviation or occurrence of misalignment. The gate isolation layers  172  may be exposed by the etching process. However, the gate isolation layers  172  may have dry etching resistance and, as such, may not be substantially removed by the etching process. Accordingly, the gate isolation layers  172  may prevent adjacent ones of the gate structures  120  and the lower source/drain contact plugs  160  from being simultaneously exposed through one opening OP, e.g., the gate isolation layer  172  may fill (e.g., seal) one bottom corner of each of the openings OP to prevent exposure of a corresponding one of the gate structure  120  or the lower source/drain contact plug  160 . For example, the openings OP, which expose the gate structures  120 , may not expose the lower source/drain contact plugs  160 , and the openings OP, which expose the lower source/drain contact plugs  160 , may not expose the gate structures  120 . 
     Referring back to  FIGS.  2 A and  2 B , gate contact plugs  181  contacting the gate structures  120  and upper source/drain contact plugs  184  contacting the lower source/drain contact plugs  160  may be formed in the openings OP. Each of the gate contact plugs  181  may include the gate contact conductive layer  182  and the gate barrier layer  183 , and each of the upper source/drain contact plugs  184  may include the upper source/drain contact conductive layer  185  and the upper contact barrier layer  186 . The gate contact plugs  181  and the upper source/drain contact plugs  184  may be formed by forming a barrier material and a conductive material in the openings OP and on the upper insulating layer  180 , and performing a planarization process such that the barrier material and the conductive material may be coplanar with the upper insulating layer  180 . The gate contact plugs  181  may be formed in the same formation process as the upper source/drain contact plugs  184  and, as such, the gate contact conductive layer  182  may include the same material as the upper source/drain contact conductive layer  185 , and the gate barrier layer  183  may include the same material as the upper contact barrier layer  186 . 
     The gate contact conductive layer  182  and the upper source/drain contact conductive layer  185  may include, e.g., W, Co, Ru, Mo, or a combination thereof. The gate barrier layer  183  and the upper contact barrier layer  186  may include, e.g., Ti, TiN, Ta, TaN, or a combination thereof. 
     Since the gate isolation layers  172  are not etched in the process of forming the openings OP, as described above, the gate contact plugs  181  may not be electrically connected to the lower source/drain contact plugs  160 , and the upper source/drain contact plugs  184  may not be electrically connected to the gate structures  120 , even when misalignment of the openings OP occurs. Accordingly, it may be possible to reduce failure, e.g., an electrical short circuit, which may occur when contact plugs are formed in a narrow space. As such, it may be possible to enhance the reliability of the semiconductor device  100  while enhancing the integration degree of the semiconductor device  100 . 
       FIGS.  17  to  19    are vertical cross-sectional views of semiconductor devices according to example embodiments. 
     Referring to  FIG.  17   , a semiconductor device  200  may include a gate isolation layer  272  contacting an upper surface of the gate spacer  130 . The upper spacers  150  of the semiconductor device  100  shown in  FIG.  3    may be omitted. 
     Referring to  FIG.  18   , a semiconductor device  300  may include a suppressant  170 . In a process of removing the suppressant  170 , as described with reference to  FIGS.  14 A and  14 B , the suppressant  170  may be incompletely removed. The remaining portion of the suppressant  170  may be disposed on an upper surface of the gate structure  120  or an upper surface of the lower source/drain contact plug  160 . For example, as shown in  FIG.  18   , the remaining portion of the suppressant  170  may be disposed between the gate structure  120  and the gate isolation layer  172 . 
     Referring to  FIG.  19   , a semiconductor device  400  may include gate isolation layers  472  disposed on the gate spacers  130 . The gate isolation layers  472  may partially cover the gate structure  120  and the lower source/drain contact plug  160 , but the exemplary embodiments are not limited thereto. The gate isolation layers  472  may partially cover at least one of the gate structure  120  and the lower source/drain contact plug  160 . 
       FIGS.  20 A and  20 B  are vertical cross-sectional views of a semiconductor device according to an example embodiment. 
     Referring to  FIGS.  20 A and  20 B , a semiconductor device  500  may include a multi-bridge-channel-transistor such as an MBCFET®. For example, the semiconductor device  500  may include channel layers  502  disposed on the active region AR while being vertically spaced apart from one another. As shown in  FIG.  20 B , the active region AR may be disposed under the gate electrode  124  while protruding from an upper surface of the substrate  102 , and the channel layers  502  may be vertically spaced apart from the active region AR while being surrounded by a gate insulating layer  522 . The gate insulating layer  522  may also cover an upper surface of the element isolation layer  110  and an upper surface of the active region AR while extending in a horizontal direction. The gate insulating layer  522  surrounding the channel layers  502  may be surrounded by the gate electrode  124 . As shown in  FIG.  20 A , the channel layers  502  may connect adjacent ones of the source/drain regions SD. 
     Although the channel layers  502  are shown as having the form of a nanosheet with a rectangular cross-section in  FIGS.  20 A and  20 B , the exemplary embodiments of the disclosure are not limited thereto. In an embodiment, the cross-section of the channel layers  502  may have a circular shape or an oval shape. In an embodiment, the channel layers  502  may include a group IV semiconductor, e.g., Si, G or SiGe, or a group III-V compound, e.g., InGaAs, InAs, GaSb, InSb, etc. 
     The semiconductor device  500  may further include inner spacers  523  disposed under the channel layers  502  while contacting opposite side surfaces of the source/drain regions SD. The inner spacers  523  may electrically insulate the gate electrodes  124  from the source/drain regions SD. In an embodiment, the inner spacers  523  may include silicon nitride. 
       FIGS.  21 A and  21 B  are vertical cross-sectional views of a semiconductor device according to an example embodiment.  FIG.  22    is an enlarged view of the semiconductor device  600  shown in  FIG.  21 A . 
     Referring to  FIGS.  21 A and  21 B , the semiconductor device  600  may include a gate structure  620  connected to the gate contact plug  181 , gate spacers  630  respectively disposed at opposite sides of the gate structure  620 , gate isolation layers  672  respectively disposed on the gate spacers  630 , and a capping layer  674  covering the gate structure  620 . The gate structure  620  may include a gate insulating layer  622  and a gate electrode  624 . 
     As shown in  FIG.  22   , an upper surface of the gate structure  620  may be disposed at the same level as an upper surface of the lower source/drain contact plug  160 . An upper surface of each gate spacer  630  may be flat, and may be coplanar with the upper surface of the gate structure  620 . Each gate isolation layer  672  may have an oval shape having a longer axis and a shorter axis. In an embodiment, the longer axis may extend in a vertical direction, and the shorter axis may extend in a horizontal direction. The capping layer  674  may be conformally disposed along the upper surface of the gate structure  620 , the upper surface of the lower source/drain contact plug  160 , and upper surfaces of the gate isolation layers  672 . 
       FIGS.  23 A to  24 B  are vertical cross-sectional views illustrating stages in a method of manufacturing the semiconductor device shown in  FIGS.  21 A and  21 B . 
     Referring to  FIGS.  23 A and  23 B , the gate structures  620  intersecting active regions AR and the lower source/drain contact plugs  160  disposed at opposite sides of the gate structures  620  may be provided. Formation of the gate structures  620  and the lower source/drain contact plugs  160  may include additionally performing a buffing CMP process after the planarization process described with reference to  FIGS.  10 A  and  10 B in order to remove the upper spacers  150  and the etch stop layer  152 . Upper surfaces of the planarized gate structures  620  may be coplanar with upper surfaces of the lower source/drain contact plugs  160 . In addition, an upper surface of the interlayer insulating layer  140  may be coplanar with the upper surfaces of the gate structures  620 . 
     Alternatively, formation of the gate structures  620  and the lower source/drain contact plugs  160  may include etching the interlayer insulating layer  140  shown in  FIGS.  4 A and  4 B , thereby forming openings exposing the source/drain regions SD, forming a barrier material and a conductive material filling the openings, and performing a planarization process such that the barrier material and the conductive material are coplanar with gate electrodes  624 . The gate capping layer  126  may be removed in the planarization process. 
     Referring to  FIGS.  24 A and  24 B , suppressants  170  may be selectively formed on the gate structures  620  and the lower source/drain contact plugs  160 . For example, the suppressants  170  may not cover the interlayer insulating layer  140  and the upper spacers  150 . After formation of the suppressants  170 , gate isolation layers  672  may be formed on the interlayer insulating layer  140  and the upper spacers  150 . In an embodiment, the gate isolation layers  672  may be formed through an ALD process. 
     Again referring to  FIGS.  21 A and  21 B , the capping layer  674  covering the lower source/drain contact plugs  160 , the gate structures  620 , and the gate isolation layers  672  may be formed, and an upper insulating layer  180  may be formed on the capping layer  674 . Thereafter, the gate contact plugs  181  and the upper source/drain contact plugs  184  may be formed to extend through the capping layer  674  and the upper insulating layer  180 . The gate contact plugs  181  may be connected to the gate structures  620 , and the upper source/drain contact plugs  184  may be connected to the lower source/drain contact plugs  160 . 
       FIGS.  25  to  27    are vertical cross-sectional views of semiconductor devices according to example embodiments. 
     Referring to  FIG.  25   , a semiconductor device  700  may include a gate isolation layer  772  contacting an upper surface of the gate spacer  630 . In an embodiment, the gate isolation layer  772  may have an oval shape having a longer axis and a shorter axis. The longer axis may extend in a horizontal direction, and the shorter axis may extend in a vertical direction. 
     Referring to  FIG.  26   , a semiconductor device  800  may include a gate isolation layer  872  contacting an upper surface of the gate spacer  630 . In an embodiment, the gate isolation layer  872  may have an oval shape having a longer axis and a shorter axis. The longer axis may extend in a vertical direction, and the shorter axis may extend in a horizontal direction. The semiconductor device  800  may further include suppressants  170  disposed on the gate structure  620  and the lower source/drain contact plug  160 . For example, the suppressants  170  may contact an upper surface of the gate structure  620  or the lower source/drain contact plug  160  while contacting the gate isolation layer  872 . The suppressants  170  may contact the capping layer  674  or the gate contact plug  181 . 
     Referring to  FIG.  27   , a semiconductor device  900  may include a gate isolation layer  972  contacting an upper surface of the gate spacer  630 . The gate isolation layer  972  may have an oval shape or a hemispherical shape with a longer axis extending in a horizontal direction. Although the gate isolation layer  972  is shown as partially covering the gate structure  620  and the lower source/drain contact plug  160  in  FIG.  27   , the exemplary embodiments are not limited thereto. In an embodiment, the gate isolation layer  972  may partially cover at least one of the gate structure  620  and the lower source/drain contact plug  160 . 
     By way of summation and review, exemplary embodiments provide a semiconductor device having a gate isolation layer on a gate spacer, thereby securing insulation among contact plugs and enhancing reliability of a device. That is, the semiconductor device includes a gate isolation layer with dry etching resistance on the gate spacer, so the gate isolation layer is not etched during an etching process for forming a gate contact plug and an upper source/drain contact plug. Therefore, the gate isolation layer is on the gate spacer between the gate electrode and the contact plugs to secure electrical insulation therebetween, thereby preventing or substantially minimizing an electrical short circuit therebetween. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.