Patent Publication Number: US-10320371-B2

Title: Method and apparatus for reducing impact of transistor random mismatch in circuits

Description:
PRIORITY APPLICATION 
     This application is a continuation of U.S. application Ser. No. 15/482,020, filed Apr. 7, 2017, which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     Random offsets resulting from transistor random mismatch can be found in analog circuits such as an operational amplifier, a comparator, a current mirror, an analog-to-digital converter, and a digital-to-analog converter. Such offsets can affect circuit performance to unacceptable levels. An example for reducing the random offsets is the auto zero method that uses a capacitor to store and cancel the random offset. However, this method is limited to application in certain circuits, and limits the speed of such circuits, as every operation needs an equilibration phase. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       In the drawings, which are not necessarily drawn to scale, like numerals may describe similar components in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present document. 
         FIG. 1  illustrates an embodiment of an electronic circuit including a system with an analog circuit and circuitry for reducing impact of transistor random mismatch in the analog circuit. 
         FIG. 2  illustrates an embodiment of the system of  FIG. 1 . 
         FIG. 3  illustrates another embodiment of the system of  FIG. 1 . 
         FIG. 4  illustrates an embodiment of a method for reducing impact of transistor random mismatch in a circuit. 
         FIG. 5  illustrates another embodiment of a method for reducing impact of transistor random mismatch in a circuit. 
         FIG. 6  illustrates an embodiment of a digital-to-analog converter (DAC) and comparator system including the system of  FIG. 1 . 
         FIG. 7  illustrates an embodiment of an analog-to-digital converter (ADC) system including the system of  FIG. 1 . 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention, and it is to be understood that the embodiments may be combined, or that other embodiments may be utilized and that structural, logical and electrical changes may be made without departing from the spirit and scope of the present invention. References to “an”, “one”, or “various” embodiments in this disclosure are not necessarily to the same embodiment, and such references contemplate more than one embodiment. The following detailed description provides examples, and the scope of the present invention is defined by the appended claims and their legal equivalents. 
     This document discusses, among other things, a system and method for reducing random offsets caused by transistor random mismatch in a circuit. In various embodiments, a digital means for such reducing random offsets can be implemented by hardware, software, or combination of hardware and software to support a fast operation in a high speed system or device. Examples of circuits implementing the present system can include, but are not limited to, an electronic circuit including a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and/or a comparator. While these examples are specifically discussed in this document, the present system and method can be applied to any circuit that includes one or more pairs of matching transistors to reduce random offsets resulting from transistor random mismatch. 
       FIG. 1  illustrates an embodiment of an electronic circuit  100  including a system  101  with an analog circuit  102  and a mismatch reduction circuit  108  for reducing impact of transistor random mismatch in analog circuit differential amplifier  102 . In various embodiments, electronic circuit  100  can include an ADC, a DAC, and/or a comparator. System  101  can be part of any of the ADC, the DAC, and/or the comparator for which random offsets caused by transistor random mismatch need to be addressed. In various embodiments, analog circuit  102  can include an operational amplifier, a comparator, or a current mirror. 
     Analog circuit  102  includes an input  104  and an output  106 . Input  104  can include a pair of differential input nodes, such as a positive (non-inverting) input node and a negative (inverting) input node. Output  106  can include a pair of complementary output nodes, such as a true output node and a complementary output node. Analog circuit  102  includes one or more pairs of matching transistors coupled between input  104  and output  106 . The transistors of each pair of matching transistors may have transistor random mismatch that results in random offsets seen at output  106 . Mismatch reduction circuit  108  is coupled to analog circuit  102  at its input  104  and output  106  to reduce the random offsets. Mismatch reduction circuit  108  includes an input  110  to receive an input signal and an output  112  to deliver an output signal. 
     In various embodiments, analog circuit  102  can include an operational amplifier, a comparator and/or a current mirror. System  101  may use such analog circuit  102  to process the input signal and use mismatch reduction circuit  108  to reduce the impact of transistor random mismatch on the signal processing to produce the output signal. 
       FIG. 2  illustrates an embodiment of a system  201 , which represents an example of system  101 . System  201  includes a current mirror  202  and a mismatch reduction circuit  208 . 
     Current mirror  202  represents an example of analog circuit  102  of  FIG. 1  and can include a pair of input nodes, a pair of output nodes, and one or more pairs of matching transistors. In the illustrated embodiment, the pair of input nodes include a first input node (IN 21 ) and a second input node (IN 22 ). The pair of output nodes include a first output node (OUT 21 ) and a second output node (OUT 22 ). A pair of matching transistors M 1  and M 2  may have transistor random mismatch resulting in random offsets at the output nodes. Input node IN 21  and output node OUT 21  are used when transistors M 1  and M 2  serve as current input and output transistors, respectively. Input node IN 22  and output node OUT 22  are used when transistors M 2  and M 1  serve as current input and output transistors, respectively. 
     Mismatch reduction circuit  208  represents an example of mismatch reduction circuit  108  of  FIG. 1  and include an input node IN 1 , an output node OUT 1 , a phase controller  220 , an input switch S-IN, an output switch S-OUT, and optionally a rest ADC or DAC output circuit  222 . 
     Phase controller  220  can time one or more pairs of even and odd phases (e.g., phase  0 , phase  1 , phase  2 , phase  3  . . . ). The even and odd phases can have a duration between 0.01 to 1000 microseconds. 
     Input switch S-IN is controlled by phase controller  220 . Input switch S-IN can connect input node IN 1  to input node IN 21  during each even phase of the one or more pairs of even and odd phases, and can connect input node IN 1  to input node IN 22  during each odd phase of the one or more pairs of even and odd phases. Alternatively, input switch S-IN can connect input node IN 1  to input node IN 21  during each odd phase of the one or more pairs of even and odd phases, and can connect input node IN 1  to input node IN 22  during each even phase of the one or more pairs of even and odd phases. 
     Output switch S-OUT is also controlled by phase controller  220 . Output switch S-OUT can connect output node OUT 21  to output node OUT 1  during each even phase of the one or more pairs of even and odd phases and connect output node OUT 22  to output node OUT 1  during each odd phase of the one or more pairs of even and odd phases. Alternatively, output switch S-OUT can connect output node OUT 21  to output node OUT 1  during each odd phase of the one or more pairs of even and odd phases and connect output node OUT 22  to output node OUT 1  during each even phase of the one or more pairs of even and odd phases. 
     Rest ADC or DAC circuit  222  (also referred to as an output circuit) can record (e.g., store at least temporary such as in a memory device) a digital code for each phase of the one or more pairs of even and odd phases, and can produce an averaged output signal being an average of the digital codes recorded for the one or more pairs of even and odd phases. In various embodiments, the number of pairs of even and odd phases used in calculating the average depends on the magnitude of the random offsets and/or their impact on the circuit performance. Such magnitude and/or impact may be estimated based on structure of the circuit. The averaging function can be achieved in mismatch reduction circuit  208  (as illustrated) or outside of mismatch reduction circuit  201 , and can be achieved by hardware circuits or software codes. 
       FIG. 3  illustrates another embodiment of a system  301 , which represents another example of system  101 . System  301  includes an op amp or comparator  302  and a mismatch reduction circuit  308 . 
     Op amp or comparator  302  represents another example of analog circuit  102  of  FIG. 1  and can include a pair of differential input nodes, a pair of complementary output nodes, and one or more pairs of matching transistors. In the illustrated embodiment, the pair of differential input nodes includes a positive (non-inverting) input node (IN+) and a negative (inverting) input node (IN−). The pair of complementary output nodes include a true output node (OUT) and a complementary output node (OUTF). Op amp or comparator  302  includes at least one pair of matching transistors, and can include multiple pairs of matching transistors, that may have transistor random mismatch resulting in random offsets at the true and/or complementary output nodes. 
     Mismatch reduction circuit  308  represents another example of mismatch reduction circuit  108  and includes a pair of first input node IN 1  and second input node IN 2 , a pair of first output node OUT 1  and second output node OUT 2 , a phase controller  220 , an input switch S-IN, an output switch S-OUT, and optionally a rest ADC or DAC circuit  322 . 
     Input switch S-IN is controlled by phase controller  220 . Input switch S-IN can connect first input node IN 1  to positive input node In+ and second input node IN 2  to negative input node IN− during each even phase of the one or more pairs of even and odd phases, and can connect first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during each odd phase of the one or more pairs of even and odd phases. Alternatively, input switch S-IN can connect first input node IN 1  to positive input node IN+ and second input node IN 2  to negative input node IN− during each odd phase of the one or more pairs of even and odd phases, and can connect first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during each even phase of the one or more pairs of even and odd phases. 
     Output switch S-OUT is also controlled by phase controller  220 . Output switch S-OUT can connect true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during each even phase of the one or more pairs of even and odd phases, and can connect complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during each odd phase of the one or more pairs of even and odd phases. Alternatively, output switch S-OUT can connect true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during each odd phase of the one or more pairs of even and odd phases, and can connect complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during each even phase of the one or more pairs of even and odd phases. 
     Rest ADC or DAC circuit  322  (also referred to as an output circuit) can record (e.g., store at least temporary such as in a memory device) a digital code for each phase of the one or more pairs of even and odd phases, and can produce an averaged output signal being an average of the digital codes recorded for the one or more pairs of even and odd phases. In various embodiments, the number of pairs of even and odd phases used in calculating the average depends on the magnitude of the random offsets and/or their impact on the circuit performance. Such magnitude and/or impact may be estimated based on structure of the circuit. The averaging function can be achieved in mismatch reduction circuit  308  (as illustrated) or outside of mismatch reduction circuit  301 , and can be achieved by hardware circuits or software codes. 
       FIG. 4  illustrates an embodiment of a method  430  for reducing impact of transistor random mismatch in a circuit. Method  430  can be applied in processing a signal using an electronic circuit including an ADC, a DAC, and/or a comparator. The electronic circuit includes one or multiple analog circuits having a pair of input nodes and a pair of output nodes. Method  430  can be performed, for example, using system  201  of  FIG. 2 . 
     At  431 , one or more pairs of even and odd phases are timed, such as by using phase controller  220 . At  432 , an input signal is transmitted to a first node (e.g., IN 21  in system  201 ) of the pair of input nodes during each even phase of the one or more pairs of even and odd phases. At  433 , an output signal (e.g., including a digital code) is received from a first node (e.g., OUT 21  in system  201 ) of the pair of output nodes during each even phase of the one or more pairs of even and odd phases. At  434 , the input signal is transmitted to a second node (e.g., IN 22  in system  201 ) of the pair of input nodes during each odd phase of the one or more pairs of even and odd phases. At  435 , the output signal is received from a second node (e.g., OUT 22 ) of the pair of output nodes during each odd phase of the one or more pairs of even and odd phases. Steps  432  and  434  can be performed, for example, using input switch S-IN in system  201 . Steps  433  and  435  can be performed, for example, using input switch S-OUT in system  201 . At  436 , a digital codes is received from the output signal during each even phase and received from the output signal during each odd phase, and is averaged to produce an averaged digital code. 
       FIG. 5  illustrates an embodiment of a method  540  for reducing impact of transistor random mismatch in a circuit. Method  540  can be applied in processing a signal using an electronic circuit including an ADC, a DAC, and/or a comparator. The electronic circuit includes at least one op amp or comparator circuit having a pair of differential input nodes and a pair of complementary output nodes. Method  540  can be performed, for example, using system  301  of  FIG. 3 . 
     At  541 , one or more pairs of even and odd phases are timed, such as by using phase controller  220 . At  542 , an input signal is transmitted to the pair of differential input nodes (e.g., IN+ and IN− in system  301 ) during each even phase of the one or more pairs of even and odd phases. The transmitted input signal is a differential signal between the first and second nodes of the pair of differential input nodes. At  543 , an output signal (e.g., including a digital code) is received from the pair of complementary output nodes (e.g., OUT and OUTF in system  301 ) during each even phase of the one or more pairs of even and odd phases. The received output signal is a differential signal between the first and second nodes of the pair of complementary output nodes. At  544 , the input signal is inverted and transmitted to the pair of differential input nodes during each odd phase of the one or more pairs of even and odd phases. At  545 , the output signal is received from the pair of complementary output nodes and inverted during each odd phase of the one or more pairs of even and odd phases. Steps  542  and  544  can be performed, for example, using input switch S-IN in system  301 . Steps  543  and  545  can be performed, for example, using input switch S-OUT in system  301 . At  546 , a digital code is received from the output signal during each even phase and received from the output signal during each odd phase, and is averaged to produce an output digital code. 
       FIG. 6  illustrates an embodiment of a DAC and comparator system  600  that includes system  101  (including its various examples as discussed in this document). The illustrated system includes a DAC  650  having a DAC input to receive a digital code and a DAC output to provide an analog signal, a comparator  652  having a first comparator input coupled to the DAC output to receive the analog signal, a second comparator input to receive a reference voltage signal VREF, and a comparator output. The degree of the impact of transistor random mismatch on output variation of system  600  depends on, and may be estimated from, the circuit structure of system  600 . In various embodiments, comparator  652  includes system  101  (including any of its examples as discussed in this document) to reduce the impact of transistor random mismatch on the output variation. 
     In one embodiment, system  600  is implemented in a high-speed circuit for clock duty cycle calibration. In a high-speed system (e.g., with main clock frequency at 500 MHz or above), clock duty cycle calibration is important to ensure reliable high-speed operation. A circuit including system  600  can provide for the clock duty cycle calibration. The circuit receives an external clock signal and converts it to an internal clock signal that goes to a clock tree. The circuit has several trim bits to calibrate the duty cycle of the clock signal, and operates like a DAC. Low pass filters and a comparator are connected to the clock tree to monitor the duty cycle of the clock signal. The comparator has transistor random mismatch that can impact the accuracy of the duty cycle calibration. System  101  (including any of its examples discussed in this document) can be included in the comparator to improve the calibration accuracy by reducing the random offsets. The digital codes used in each phase can be averaged by either hardware circuits or software codes. The averaged digital code can then be used for proper clock duty cycle trims to reduce the impact of transistor random mismatch in the comparator. 
       FIG. 7  illustrates an embodiment of an ADC system  700  that includes system  101  (including its various examples as discussed in this document). In the illustrated embodiment, system  700  includes an ADC  754  that includes system  101 . In another embodiment, ADC  754  can have an ADC output connected to a comparator that includes system  101 . The degree of the impact of transistor random mismatch on output variation of system  700  depends on, and may be estimated from, the circuit structure of system  700 . In various embodiments, system  700  includes system  101  (including any of its examples as discussed in this document) to reduce the impact of transistor random mismatch on the output variation. 
     Referring to both  FIGS. 6 and 7 , in one embodiment, transistor random mismatch has negligible impact on the output variation of system  600  or  700 . Comparator  652  includes system  301  of  FIG. 3 . Phase controller  220  times one pair of even and odd phases: phase  0  and phase  1 . Input switch S-IN connects first input node IN 1  to positive input node IN+ and second input node IN 2  to negative input node IN− during phase  0 , and connects first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during phase  1 . Alternatively, input switch S-IN connects first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during phase  0 , and connects first input node IN 1  to positive input node IN+ and second input node IN 2  to negative input node IN− during phase  1 . Output switch S-OUT connects true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during phase  0 , and connect complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during phase  1 . Alternatively, output switch S-OUT connects complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during phase  0 , and connects true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during phase  1 . Output circuit  322  record the signal at complementary output nodes OUT and OUTF for each of phases  0  and  1 , and produce an average of the signal recorded for phases  0  and  1 . 
     Referring to both  FIGS. 6 and 7 , in another embodiment, transistor random mismatch has significant impact on the output variation of system  600 . Comparator  652  includes system  301  of  FIG. 3 . Phase controller  220  times two pairs of even and odd phases: phase  0 , phase  1 , phase  2 , and phase  3 . Input switch S-IN connects first input node IN 1  to positive input node IN+ and second input node IN 2  to negative input node IN− during each of phases  0  and  2 , and connects first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during each of phases  1  and  3 . Alternatively, input switch S-IN connects first input node IN 1  to negative input node IN− and second input node IN 2  to positive input node IN+ during each of phases  0  and  2 , and connects first input node IN 1  to positive input node IN+ and second input node IN 2  to negative input node IN− during each of phases  1  and  3 . Output switch S-OUT connects true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during each of phases  0  and  2 , and connect complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during each of phases  1  and  3 . Alternatively, output switch S-OUT connects complementary output node OUTF to first output node OUT 1  and true output node OUT to second output node OUT 2  during each of phases  0  and  2 , and connects true output node OUT to first output node OUT 1  and complementary output node OUTF to second output node OUT 2  during each of phases  1  and  3 . Output circuit  322  record the signal at complementary output nodes OUT and OUTF for each of phases  0 ,  1 ,  2 , and  3 , and produce an average of the signal recorded for phases  0 ,  1 ,  2 , and  3 . 
     While system  301  is discussed above as a specific example, system  600  or  700  can include one or more systems such as systems  201  and/or  301 . In various embodiments, system  600  can include any DAC system with one or multiple critical matching devices in one or more op amps and/or one or more current mirrors, and system  700  can include any ADC system with one or multiple critical matching devices in one or more op amps and/or one or more current mirrors. 
     The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples”. Such examples can include elements in addition to those shown or described. However, the present inventors also contemplate examples in which only those elements shown or described are provided. Moreover, the present inventors also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein. 
     It will be understood that when an element is referred to as being “on,” “connected to” or “coupled with” another element, it can be directly on, connected, or coupled with the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly on,” “directly connected to” or “directly coupled with” another element, there are no intervening elements or layers present. If two elements are shown in the drawings with a line connecting them, the two elements can be either be coupled, or directly coupled, unless otherwise indicated. 
     The above description is intended to be illustrative, and not restrictive. For example, the above-described examples (or one or more aspects thereof) may be used in combination with each other. Other embodiments can be used, such as by one of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b), to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is essential to any claim. Rather, inventive subject matter may lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate embodiment, and it is contemplated that such embodiments can be combined with each other in various combinations or permutations. The scope of the invention should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.