Patent Publication Number: US-9898436-B2

Title: Data transmission system and transmission method thereof including connection and orientation detection

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 104115194, filed on May 13, 2015. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND 
     Field of the Invention 
     The invention is related to a data transmission system and a method thereof and more particularly, to a data transmission system and a method thereof capable of providing multi-direction connection to electronic apparatuses. 
     Description of Related Art 
     With the rapid development of information technologies, as well as the progress of various types of electronic apparatuses and a variety of functions equipped therewith, the electronic apparatuses have become more and more inseparable with people&#39;s life. Generally, a user can connect two electronic apparatuses with each other for information communication or data transmission to expand functions of the electronic apparatuses through various general purpose transmission interfaces (e.g., a universal serial bus (USB)) complying with a variety of specification standards, including Type A, Type B, Mini-B, Micro-A and Micro-B, and D-subminiature connectors complying with a variety of specification standards, including DA-15, DB-25, DC-37, DD-50 and DE-9, or other transmission interfaces with other specific specifications of the electronic apparatuses. 
     However, in the conventional connection interfaces, pin positions of the electronic apparatuses have to be corresponding to each other, for example, data pins or clock pins of the two electronic apparatuses have to be connected with each other, so as to implement the data transmission. Thus, in a general scenario, two electronic apparatuses have to be connected in a fixed direction (i.e., a forward direction) when performing the data transmission between each other, which cause inconvenience to the users. As such, even though more corresponding pins can be increased for the data transmission when the connection direction is a reverse direction; however, the increase of the pin count would result in higher manufacturing cost. 
     SUMMARY 
     The invention provides a data transmission system and a data transmission thereof, which can facilitate in connecting electronic apparatuses in a plurality of directions for perform operations. 
     According to an embodiment of the invention, a data transmission system including a first electronic apparatus and a second electronic apparatus is provided. The first electronic apparatus has a first connection interface with a first clock pin and a first data pin disposed thereon. The second electronic apparatus has a second connection interface with a second clock pin and a second data pin disposed thereon. In a connecting detection mode, the first electronic apparatus transmits a first detection signal to the first clock pin and drives the first data pin to a reference logic level. The second electronic apparatus transmits a second detection signal to the second clock pin and drives the second data pin to the reference logic level. The first electronic apparatus determines whether the first and the second electronic apparatuses are connected to each other according to whether at least one of signals on the first clock pin and on the first data pin is varied. 
     In an embodiment of the invention, when the first and the second electronic apparatuses are connected with each other, the first electronic apparatus determines connecting direction information of the first and the second electronic apparatuses according to whether the signal on the first data pin is maintained at the reference logic level. 
     According to an embodiment of the invention, a data transmission system including a first electronic apparatus and a second electronic apparatus is provided. The first electronic apparatus has first connection interface with a first clock pin and a first data pin disposed thereon. The second electronic apparatus has a second connection interface with a second clock pin and a second data pin disposed thereon. In a connecting detection mode, the first electronic apparatus drives the first clock pin to a first logic level and drives the first data pin to a second logic level. The second electronic apparatus drives the second clock pin and the second data pin to a second logic level. The first electronic apparatus receives the signal on the first clock pin to determine whether the first and the second electronic apparatuses are connected to each other by comparing whether the signal on the first clock pin is maintained at the first logic level. 
     According to an embodiment of the invention, a data transmission method adapted for data transmission between a first electronic apparatus and a second electronic apparatus is provided. The first electronic apparatus is disposed with a first clock pin and a first data pin. The second electronic apparatus is disposed with a second clock pin and a second data pin. The method includes: in a connecting detection mode, transmitting a first detection signal to the first clock pin to drive the first data pin to a reference logic level, and transmitting a second detection signal to the second clock pin to drive the second data pin to the reference logic level; and determining whether the first and the second electronic apparatuses are connected to each other according to whether at least one of signals on the first clock pin and on the first data pin is varied. 
     According to an embodiment of the invention, a data transmission method adapted for data transmission between a first electronic apparatus and a second electronic apparatus is provided. The first electronic apparatus is disposed with a first clock pin and a first data pin. The second electronic apparatus is disposed with a second clock pin and a second data pin. The method includes: in a connecting detection mode, respectively driving the first clock pin to a first logic level and driving the first data pin, the second clock pin and the second data pin to a second logic level; receiving the signal on the first clock pin; and determining whether the first and the second electronic apparatuses are connected to each other by comparing whether the signal on the first clock pin is maintained at the first logic level. 
     To sum up, in the data transmission system of the invention, when the electronic apparatuses are connected with each other, variation occurring in the signal (the voltage level) of each pin can be detected by means of the detection signal transmitted to each pin (e.g., the clock pin and the data pin). Accordingly, the connection direction between the electronic apparatuses can be determined, and functions of and signals output by the pins of the apparatuses can be correspondingly switched, such that data transmission can be successfully performed between the electronic apparatuses which are connected in either the forward direction or the reverse direction and the convenience in use can therefore be enhanced. 
     In order to make the aforementioned and other features and advantages of the present invention more comprehensible, several embodiments accompanied with figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and, together with the description, serve to explain the principles of the present invention. 
         FIG. 1  is a schematic diagram illustrating a data transmission system according to an embodiment of the invention. 
         FIG. 2  is a signal timing chart of implementing detection signals according to an embodiment of the invention. 
         FIG. 3  is a schematic diagram illustrating a data transmission system according to another embodiment of the invention. 
         FIG. 4  is a schematic diagram illustrating a part of circuits of the controller according to another embodiment of the invention. 
         FIG. 5  is a schematic diagram illustrating a data transmission system according to another embodiment of the invention. 
         FIG. 6  is a schematic diagram illustrating switching units according to an embodiment of the invention. 
         FIG. 7  is a flowchart illustrating a data transmission method according to an embodiment of the invention. 
         FIG. 8  is a flowchart illustrating a data transmission method according to an embodiment of the invention. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Referring to  FIG. 1 ,  FIG. 1  is a schematic diagram illustrating a data transmission system according to an embodiment of the invention. A data transmission system  100  includes an electronic apparatus  110  and an electronic apparatus  120 . The electronic apparatus  110  may be, for example, a notebook computer, a tablet computer, a smart phone, a personal digital assistant (PDA). The electronic apparatus  120  may be, for example, an electronic apparatus capable of being operated with the electronic apparatus  110  for functional expansion (e.g., a dock or a keyboard), or any electronic apparatus for data transmission with the electronic apparatus  110  through hardware connection, of which the type is not limited in the invention. 
     The electronic apparatus  110  has a connection interface  111 . The connection interface  111  has a clock pin CLK 1  and a data pin DAT 1  disposed thereon. The electronic apparatus  120  has a connection interface  121 . The connection interface  121  has a clock pin CLK 2  and a data pin DAT 2  disposed thereon. Positions where the clock pin CLK 1  and the data pin DAT 1  are disposed on the connection interface  111  and positions where the clock pin CLK 2  and the data pin DAT 2  are disposed on the connection interface  121  may be corresponding to each other, for example. In the embodiment of the invention, when the connection interface  111  of the electronic apparatus  110  and the connection interface  121  of the electronic apparatus  120  are connected with each other, a connecting state (in a forward direction or in a reverse direction) is determined by transmitting a detection signal to each pin, so as to correspondingly adjust a function and an output signal of each pin. 
     To be specific, in  FIG. 1 , when the electronic apparatus  110  and the electronic apparatus  120  are connected to each other, the data transmission system  100  may enter a connecting detection mode. In the connecting detection mode, the electronic apparatus  110  may transmit a detection signal SDT 1  to the clock pin CLK 1  and drive the data pin DAT 1  to a reference logic level LREF. The electronic apparatus  120  may transmit a detection signal SDT 2  to the clock pin CLK 2  and drive the data pin DAT 2  to the reference logic level LREF. Therein, the detection signal SDT 1  and the detection signal SDT 2  have different waveforms and frequencies, which may be pulse width modulation (PWM) signals having different duty cycles respectively, for example. In this case, the electronic apparatus  110  may determine whether the electronic apparatus  110  and the electronic apparatus  120  are connected with each other according to whether at least one of a signal on the clock pin CLK 1  and a signal on the data pin DAT 1  is varied or not. 
     Examples of determining whether the electronic apparatuses are connected with each other will be described with reference to  FIG. 1  and  FIG. 2 . Therein,  FIG. 2  is a signal timing chart of implementing detection signals according to an embodiment of the invention.  FIG. 2  illustrates the detection signal SDT 1  transmitted to the clock pin CLK 1  by the electronic apparatus  110 , the detection signal SDT 2  transmitted to the clock pin CLK 2  by the electronic apparatus  120  and a signal SCP on the clock pin CLK 1  of the electronic apparatus  110 . When the electronic apparatus  110  and the electronic apparatus  120  are not connected, the signal SCP on the clock pin CLK 1  is equal to the detection signal SDT 1  transmitted to the clock pin CLK 1  by the electronic apparatus  110 . When the clock pin CLK 1  of the electronic apparatus  110  and the clock pin CLK 2  of the electronic apparatus  120  are connected with each other (e.g., in a forward direction), as shown in  FIG. 2 , the signal SCP on the clock pin CLK 1  is varied due to being affected by the detection signal SDT 2  and becomes a signal having a waveform different from the detection signal SDT 1 . Thereby, it may be determined that the electronic apparatus  110  and the electronic apparatus  120  are connected with each other. 
     Additionally, when the data pin DAT 1  of the electronic apparatus  110  and the clock pin CLK 2  of the electronic apparatus  120  are connected with each other (e.g., in a reverse direction), whether the electronic apparatuses are connected with each other may be determined in another way by means of driving the data pins DAT 1  and DAT 2  to the reference logic level LREF. For instance, if it is assumed that the data pins DAT 1  and DAT 2  are pulled up to the reference logic level LREF (e.g., a high logic level) merely by a pull-up voltage, intensities for maintaining the data pins DAT 1  and DAT 2  at the reference logic level are low. In this circumstance, when the electronic apparatus  110  and the electronic apparatus  120  are connected in the reverse direction, the logic level of the signal SDP on the data pin DAT 1  is changed (which are not maintained at the high logic levels, for example) due to being affected by the detection signal SDT 2 . Thereby, it may be determined that the electronic apparatus  110  and the electronic apparatus  120  are connected with each other. 
     However, if it is assumed that the data pins DAT 1  and DAT 2  are driven to the reference logic level LREF (e.g., a low logic level) through controllers built in the electronic apparatuses  110  and  120 , the intensities for maintaining the data pins DAT 1  and DAT 2  at the reference logic level are high. In this circumstance, when the electronic apparatus  110  and the electronic apparatus  120  are connected in the reverse direction, the logic levels of the signal SDP on the data pin DAT 1  are not changed (which are still maintained at the low logic levels, for example) due to being affected by the detection signal SDT 2 . Therefore, the electronic apparatus  110  has to detect the signal SCP on the clock pin CLK 1 . In this case, the signals SCP are affected by the reference logic level LREF with the high intensity on the data pin DAT 2  and tend toward being equal. Thereby, it may be determined that the electronic apparatus  110  and the electronic apparatus  120  are connected with each other. 
     In the present embodiment, connecting direction information of the electronic apparatuses  110  and  120  may also be determined according to signal variation on the data pin DAT 1  or the clock pin CLK 1 . The connecting direction information includes, for example, a forward connection state and a reverse connection state. In a scenario where the electronic apparatus  110  and the electronic apparatus  120  are determined as being connected with each other, if it is assumed that the data pins DAT 1  and DAT 2  are pulled up to the reference logic level LREF (e.g., high logic level) merely by the pull-up voltage, the electronic apparatus  110  may receive the signal SDP on the data pin DAT 1  and determine the connecting direction information of the electronic apparatuses  110  and  120  according to whether the signal SDP is maintained at the reference logic level LREF. For instance, when the connecting direction information is the forward connection state, the clock pin CLK 1  and the clock pin CLK 2  are connected with each other, the data pin DAT 1  is connected with the data pin DAT 2  which is also pulled up to the reference logic level LREF by the pull-up voltage in the same way. Thereby, the signal SDP on the data pin DAT 1  may be maintained at the high logic level. When the connecting direction information is the reverse connection state, the clock pin CLK 1  and the data pin DAT 2  are connected with each other, and the data pin DAT 1  and the clock pin CLK 2  are connected with each other. Because the intensity for maintaining the signal SDP on the data pin DAT 1  at the reference logic level LREF is low, the signal SDP may not be maintained at the high logic level due to being affected by the clock pin CLK 2  (e.g., the detection signal SDT 2 ). Thereby, the connecting direction information of the electronic apparatuses  110  and  120  may be determined through the data pin DAT 1 . 
     In the same condition, the electronic apparatus  110  may also determine the connecting direction information of the electronic apparatuses  110  and  120  according to whether the signal on the clock pin CLK 1  is equal to the detection signal SDT 1 . For instance, when the connecting direction information is the forward connection state, the signal SCP on the clock pin CLK 1  is interfered by the detection signal SDT 2  and is not equal to the detection signal SDT 1 . On the contrary, when the connecting direction information is the reverse connection state, because the intensity for maintaining the signal on the data pin DAT 2  at the reference logic level LREF is low, the waveform of the signal SCP on the clock pin CLK 1  is not changed due to being affected by the detection signal SDT 2  and is still equal to the detection signal SDT 1 . Thereby, the connecting direction information of the electronic apparatuses  110  and  120  may be determined through the clock pin CLK 1 . 
     On other hand, if it is assumed that the data pins DAT 1  and DAT 2  are driven to the reference logic level LREF (e.g., the low logic level) through the controllers built in the electronic apparatus  110  and the electronic apparatus  120 , the electronic apparatus  110  may determine the connecting direction information of the electronic apparatuses  110  and  120  by determining whether the signal on the clock pin CLK 1  is equal to the reference logic level LREF. For instance, when the connecting direction information is the forward connection state, the clock pin CLK 1  and the clock pin CLK 2  are connected with each other, the data pin DAT 1  and the data pin DAT 2  are connected with each other. Thus, the signal SCP on the clock pin CLK 1  is not affected by the signal on the data pin DAT 2  and is not equal to the reference logic level LREF. When the connecting direction information is the reverse connection state, the clock pin CLK 1  and the data pin DAT 2  are connected with each other, the data pin DAT 1  and the clock pin CLK 2  are connected with each other. Because the intensity for maintaining the signal on the data pin DAT 2  at the reference logic level LREF is high, the signal SCP on the clock pin CLK 1  in this case is affected by the signal on the data pin DAT 2  and is equal to the reference logic level LREF. Thereby, the connecting direction information of the electronic apparatuses  110  and  120  may be determined through the clock pin CLK 1 . 
     After the connection direction of the electronic apparatus  110  and the electronic apparatus  120  is determined, the electronic apparatus  110  (or the electronic apparatus  120 ) may determine whether to switch the functions of and the signals output by the clock pin CLK 1  and the data pin DAT 1  (or the clock pin CLK 2  and the data pin DAT 2 ) according to the detected connecting direction information, and thereby, a clock signal and a data signal may be output from the appropriate pin positions according to the current connection direction, such that the data transmission system  100  may start to perform the data transmission (i.e., enter the communication mode). For instance, during the connection in the forward direction, the clock signal is output from the clock pin CLK 1  to the clock pin CLK 2 , and the data signal is output from the data pin DAT 1  to the data pin DAT 2 . During the connection in the reverse direction, the functions of the clock pin CLK 1  and the data pin DAT 1  may be interchanged, such that the data signal is output from the clock pin CLK 1  to the data pin DAT 2 , and the clock signal is output from the data pin DAT 1  to the clock pin CLK 2 . Therefore, the data transmission can be successfully performed between the electronic apparatus  110  and the electronic apparatus  120  which are connected in either the forward direction or the reverse direction, so as to enhance the convenience in use. 
     It should be noted that within a testing period after the data transmission system  100  of the invention enters the communication mode, if a poor rate of the transmission between the electronic apparatus  110  and the electronic apparatus  120  is over a preset threshold, the electronic apparatus  110  (or the electronic apparatus  120 ) may change the functions of and the signals output by the clock pins and the data pins as default states, i.e., the electronic apparatus  110  is changed to transmit the clock signal to the clock pin CLK 1  and transmit the data signal to data pin DAT 1  to avoid data transmission failure caused by mistakenly determined connection direction. 
     Referring to  FIG. 3  hereinafter,  FIG. 3  is a schematic diagram illustrating a data transmission system according to another embodiment of the invention. A data transmission system  300  includes an electronic apparatus  310  and an electronic apparatus  320 . The electronic apparatus  310  has a connection interface  311 . The connection interface  311  has a clock pin CLK 1  and a data pin DAT 1  disposed thereon. The electronic apparatus  320  has a connection interface  321 . The connection interface  321  has a clock pin CLK 2  and a data pin DAT 2  disposed thereon. Positions where the clock pin CLK 1  and the data pin DAT 1  are disposed on the connection interface  311  and positions where the clock pin CLK 2  and the data pin DAT 2  are disposed on the connection interface  321  may be corresponding to each other, for example. In the meantime, functions of part of the elements are the same as or similar to the functions of the corresponding elements in the embodiments above and thus, details thereof will not be repeatedly described. 
     In the present embodiment, referring to  FIG. 3 , the electronic apparatus  310  and the electronic apparatus  320  respectively include a controller  312  and a controller  322 . The controller  312  and the controller  322  are, for example, central processing units (CPUs) with single core or multiple cores, other general purpose or specific purpose programmable microprocessors, digital signal processors (DSPs), programmable controllers, and so on. In  FIG. 3 , the controller  312  includes a clock output terminal C_OUT 1  and a data output terminal D_OUT 1 . The clock output terminal C_OUT 1  is coupled to the clock pin CLK 1 , and the data output terminal D_OUT 1  is coupled to the data pin DAT 1 . The controller  312  may transmit signals to the clock pin CLK 1  and the data pin DAT 1  respectively through the clock output terminal C_OUT 1  and the data output terminal D_OUT 1 . 
     Meanwhile, the controller  322  includes a clock output terminal C_OUT 2  and a data output terminal D_OUT 2 . The clock output terminal C_OUT 2  is coupled to the clock pin CLK 2 , and the data output terminal D_OUT 2  is coupled to the data pin DAT 2 . The controller  322  may transmit signals to the clock pin CLK 2  and the data pin DAT 2  respectively through the clock output terminal C_OUT 2  and the data output terminal D_OUT 2 . 
     In  FIG. 3 , the electronic apparatus  310  further includes pull-up resistors R 1  and R 2 . The pull-up resistor R 1  is serially connected between the clock pin CLK 1  and the pull-up voltage VPU. The pull-up resistor R 2  is serially connected between the data pin DAT 1  and the pull-up voltage VPU. The electronic apparatus  320  also further includes pull-up resistors R 3  and R 4 . The pull-up resistor R 3  is serially connected between the clock pin CLK 2  and the pull-up voltage VPU. The pull-up resistor R 4  is serially connected between the data pin DAT 2  and the pull-up voltage VPU. 
     Referring to  FIG. 3 , in the present embodiment, the clock pin CLK 1 , the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  may be connected with output terminals of open drain buffers (not shown), such that each pin forms an open drain circuit. In operation, when the electronic apparatus  310  and the electronic apparatus  320  are connected with each other, the data transmission system  300  may enter a connecting detection mode. In the connecting detection mode, the controller  312  may transmit a detection signal SDT 1  to the clock pin CLK 1 . The controller  322  may transmit a detection signal SDT 2  to the clock pin CLK 2 . Therein, the detection signal SDT 1  and the detection signal SDT 2  have different waveforms and frequencies. In this case, the controller  312  may determine whether the electronic apparatus  310  and the electronic apparatus  320  are connected with each other according to whether at least one of the signal SCP on the clock pin CLK 1    the signal SDP on the data pin DAT 1  is varied. 
     For instance,  FIG. 4  is a schematic diagram illustrating a part of circuits of the controller according to another embodiment of the invention. Referring to both  FIG. 3  and  FIG. 4 , the controller  312  may further include a buffer  400  and a detecting unit  410 . The buffer  400  has an input terminal, an output terminal and an enable terminal. The input terminal of the buffer  400  is coupled to clock output terminal C_OUT 1  transmitting the detection signal SDT 1 . The output terminal of the buffer  400  is coupled to the clock pin CLK 1  and the pull-up resistor R 1 . And, the buffer  400  may determine whether to output the detection signal SDT 1  to the clock pin CLK 1  based on the control of the enable terminal (e.g., based on an enable signal SE coupled to the enable terminal). 
     Additionally, the buffer  400  may be enabled according to the enable signal SE to generate a low logic level of the detection signal SDT 1 . Meanwhile, the buffer  400  may further be disabled according to the enable signal SE and generate a high logic level part of the detection signal SDT 1  through the pull-up resistor R 1  pulling up the detection signal SDT 1 . 
     The detecting unit  410  is coupled to the input terminal and the output terminal of the buffer  400 . The detecting unit  410  may detect the signal SCP on the clock pin CLK 1  and the detection signal SDT 1  to provide a detection result to the controller  312 . Accordingly, the controller  312  may compare the detection signal SDT 1  and the signal SCP to determine whether the electronic apparatus  310  and the electronic apparatus  320  are connected with each other. 
     Continuously referring to  FIG. 3 , when the electronic apparatus  310  and the electronic apparatus  320  are connected with each other, in an embodiment, the data pins DAT 1  and DAT 2  are pulled up to the reference logic level LREF (e.g., the high logic level) merely by the pull-up voltage VPU. That is, the data pins DAT 1  and DAT 2  are driven in a condition that the controllers  312  and  322  do not transmit the signals. Because intensities for the signals to maintain the data pins DAT 1  and DAT 2  at the reference logic level LREF are weak, the electronic apparatus  310  may receive the signal SDP on the data pin DAT 1  and detect whether the signal SDP is maintained at the high logic level to determine connecting direction information of the electronic apparatus  310  and the electronic apparatus  320 . 
     To be specific, the controller  312  may compare the signal on the data pin DAT 1 . When the signal SDP on the data pin DAT 1  is maintained at the high logic level, the controller  312  may determine that the data pin DAT 1  is connected with the data pin DAT 2  which is also pulled up to the high logic level in the same way. Thus, the connecting direction information is the forward connection state. Otherwise, when the signal on the data pin DAT 1  Is not maintained at the high logic level, the controller  312  may determine that the data pin DAT 1  is connected with the clock pin CLK 2  due to being affected by the detection signal SDT 2 , for example, and thus, the connecting direction information is the reverse connection state. 
     In another embodiment, the data pins DAT 1  and DAT 2  are driven to the reference logic level LREF (e.g., the low logic level) through the controllers built in the electronic apparatus  110  and the electronic apparatus  120 . In this condition, the controllers  312  and  322  may respectively provide detection signals SDT 3  and SDT 4  to the data pins DAT 1  and DAT 2  to drive each of the data pins DAT 1  and DAT 2  to the reference logic level LREF. In this case, because the intensities of the signals for maintaining the data pins DAT 1  and DAT 2  at the reference logic level LREF are high, the electronic apparatus  310  may receive the signal SCP on the clock pin CLK 1  and compare whether the signal SCP is equal to the reference logic level LREF due to being affected by the data pin DAT 2  to determine the connecting direction information of the electronic apparatus  310  and the electronic apparatus  320 . 
     To be specific, the controller  312  may compare the signal SCP on the clock pin CLK 1 . When the signal SCP on the clock pin CLK 1  is not affected by the signal on the data pin DAT 2  and is not equal to the reference logic level LREF, the controller  312  may determine that the clock pin CLK 1  is connected with the clock pin CLK 2 , and the connecting direction information is the forward connection state. Otherwise, when the signal SCP on the clock pin CLK 1  is equal to the reference logic level LREF due to being affected by the signal on the data pin DAT 2 , the controller  312  may determine that the clock pin CLK 1  is connected with the clock pin DAT 2 , and the connecting direction information is the reverse connection state. 
     Accordingly, after the connection direction of the electronic apparatus  310  and the electronic apparatus  320  is determined, the electronic apparatus  310  (or the electronic apparatus  320 ) may determine whether to switch the functions of and the signals output by the e clock pin CLK 1  and the data pin DAT 1  (or the clock pin CLK 2  and the data pin DAT 2 ) according to the detected connecting direction information, and thereby, a clock signal and a data signal may be output from the appropriate pin positions according to the current connection direction, such that the data transmission system  300  may start to perform the data transmission (i.e., enter the communication mode). 
     Referring to  FIG. 5  hereinafter,  FIG. 5  is a schematic diagram illustrating a data transmission system according to another embodiment of the invention. A data transmission system  500  includes an electronic apparatus  510  and an electronic apparatus  520 . The electronic apparatus  510  has a connection interface  511 . The connection interface  511  has a clock pin CLK 1  and a data pin DAT 1  disposed thereon. The electronic apparatus  520  has a connection interface  521 . The connection interface  521  has a clock pin CLK 2  and a data pin DAT 2  disposed thereon. Positions where the clock pin CLK 1  and the data pin DAT 1  are disposed on the connection interface  511  and positions where the clock pin CLK 2  and the data pin DAT 2  are disposed on the connection interface  521    clock pin CLK 1 , data pin DAT 1    clock pin CLK 2 , data pin DAT 2  may be corresponding to each other, for example. In the meantime, functions of part of the elements are the same as or similar to the functions of the corresponding elements in the embodiments above and thus, details thereof will not be repeatedly described. 
     In  FIG. 5 , the electronic apparatus  510  further includes a controller  512 . The controller  512  includes a clock output terminal C_OUT 1  and a data output terminal D_OUT 1 . The clock output terminal C_OUT 1  is coupled to the clock pin CLK 1 , and the data output terminal D_OUT 1  is coupled to the data pin DAT 1 . The controller  512  may transmit signals to the clock pin CLK 1  and the data pin DAT 1  respectively through the clock output terminal C_OUT 1  and the data output terminal D_OUT 1 . 
     Meanwhile, the electronic apparatus  520  also includes a controller  522 . The controller  522  includes a clock output terminal C_OUT 2  and a data output terminal D_OUT 2 . The clock output terminal C_OUT 2  is coupled to the clock pin CLK 2 , data output terminal D_OUT 2  is coupled to data pin DAT 2 . The controller  522  may also transmit signals to the clock pin CLK 2  and the data pin DAT 2  respectively through the clock output terminal C_OUT 2  and the data output terminal D_OUT 2 . 
     In addition, electronic apparatus  510  further includes a ground resistor R 5  and a pull-up resistor R 6 . The ground resistor R 5  is serially connected between the clock pin CLK 1  and a reference ground voltage GND. The pull-up resistor R 6  is serially connected between the data pin DAT 1  and a pull-up voltage VPU. In the present embodiment, referring to  FIG. 5 , the ground resistor R 5  and the pull-up resistor R 6  are disposed inside the controller  512  of the electronic apparatus  510  and serially connected with the clock pin CLK 1  and the data pin DAT 1  respectively through the clock output terminal C_OUT 1  and the data output terminal D_OUT 1 . It should be noted that the disposition of the ground resistor R 5  and the pull-up resistor R 6  is not limited in the present embodiments of the invention, and the ground resistor R 5  and the pull-up resistor R 6  may be disposed outside the controller  512  in another embodiment. 
     The electronic apparatus  520  further includes a pull-up resistor R 7  and a pull-up resistor R 8 . The pull-up resistor R 7  is serially connected between the clock pin CLK 2  and the pull-up voltage VPU. The pull-up resistor R 8  is serially connected between the data pin DAT 2  and the pull-up voltage VPU. In the present embodiment, a resistance of the ground resistor R 5  is, for example, greater than that of the pull-up resistor R 7  and that of the pull-up resistor R 8 . 
     
       
         
           
               
               
               
             
               
                   
                 TABLE (1) 
               
             
            
               
                   
                   
               
               
                   
                 Electronic apparatus 510 
                 Electronic apparatus 520 
               
            
           
           
               
               
               
               
               
            
               
                 Step 
                 CLK1 
                 DAT1 
                 CLK2 
                 DAT2 
               
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 1 
                 GPI 
                 L 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
               
               
                 2 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
               
               
                 3 
                 GPO 
                 L 
                 GPI 
                 H 
                 GPI 
                 L 
                 GPI 
                 H 
               
               
                 4 
                 GPO 
                 L 
                 GPI 
                 L 
                 GPI 
                 L 
                 GPO 
                 L 
               
               
                 5 
                 GPI 
                 H 
                 GPI 
                 L 
                 GPI 
                 H 
                 GPO 
                 L 
               
               
                   
               
            
           
         
       
     
     Table (1) illustrates input/output states and voltage levels of the clock pin CLK 1 , the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  respectively during the process of detecting whether the electronic apparatus  510  and the electronic apparatus  520  are connected with each other and connecting direction information thereof when the electronic apparatus  510  and the electronic apparatus  520  of the present embodiment are connected in the forward direction, where “H” represents the high logic level, and “L” represents the low logic level. In the present embodiment, the clock pin CLK 1 , the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  may be, for example, general purpose input output (GPIO) pins, and thus, the controller  512  of the electronic apparatus  510  and the controller  522  of the electronic apparatus  520  may arbitrarily set the clock pin CLK 1 , the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  as a general purpose input (GPI) or a general purpose output (GPO) type. Operations performed by the elements illustrated in  FIG. 5  will be described with reference to Table (1) hereinafter. 
     Referring to both  FIG. 5  and Table (1), in step 1 of Table (1), the clock pin CLK 1 , data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  are set as the GPI type. And, the clock pin CLK 1  is set at the low logic level L according to the reference ground voltage GND, while the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  are set at the high logic level H according to the pull-up voltage VPU. 
     Then, when the electronic apparatus  510  and the electronic apparatus  520  are connected with each other, in step 2 of Table (1), the controller  512  may determine whether the electronic apparatus  510  and the electronic apparatus  520  are connected with each other by comparing whether the signal on the clock pin CLK 1  is maintained at the low logic level L dropped by the reference ground voltage GND. In step 2 of Table (1), when the electronic apparatus  510  detects that the level of the clock pin CLK 1  is changed to the high logic level H, it represents that the level of the clock pin CLK 1  is changed due to being and connected with and affected by the clock pin CLK 2  or the data pin DAT 2 , so as to determine that the electronic apparatus  510  and the electronic apparatus  520  are connected with each other. 
     Then, when the electronic apparatus  510  and the electronic apparatus  520  are connected with each other, in step 3 of Table (1), the controller  512  of the electronic apparatus  510  may set the clock pin CLK 1  as the GPO type. And, the controller  512  may transmit a detection signal SDT 5  at the low logic level L to the clock pin CLK 1  to drop the clock pin CLK 1  to the low logic level L. The controller  522  of the electronic apparatus  520  may then determine the connecting direction information of the electronic apparatus  510  and the electronic apparatus  520  according to whether the pin (which is changed to the low logic level L) receiving the detection signal SDT 5  is the clock pin CLK 2  or the data pin DAT 2 . 
     To be specific, the controller  522  may detect whether signals (levels) on the clock pin CLK 2  and the data pin DAT 2  are equal to the detection signal SDT 5  (i.e., the low logic level L). When the signal on the clock pin CLK 2  is equal to the detection signal SDT 5 , the connecting direction information is determined as the forward connection state. When the signal on the data pin DAT 2  is equal to the detection signal SDT 5 , the connecting direction information is determined as the reverse connection state. In step 3 of the Table (1), the clock pin CLK 2  is changed to the low logic level L, such that the controller  522  may acquire that the connecting direction information is the forward connection state. 
     Afterwards, in step 4 of Table (1), the controller  522  of the electronic apparatus  520  may set the data pin DAT 2  as the GPO type and transmit a detection signal SDT 6  at the low logic level L to the data pin DAT 2  to adjust the data pin DAT 2  from the high logic level H to the low logic level L, such that the electronic apparatus  520  may be ready for entering the communication mode. Accordingly, in step 4 of Table (1), the data pin DAT 1  of the electronic apparatus  510  is correspondingly changed to the low logic level L due to being connected with the data pin DAT 2 . 
     Then, in step 5 of Table (1), the controller  512  of the electronic apparatus  510  detects that the data pin DAT 1  is changed to the low logic level L and sets the clock pin CLK 1  as the GPI type, such that the electronic apparatus  510  may be ready for entering the communication mode. In this case, the electronic apparatus  510  and the electronic apparatus  520  are connected with each other in the forward direction and thus, do not have to switch the functions of and the signals output by the clock pin CLK 1  and the data pin DAT 1  (or the clock pin CLK 2  and the data pin DAT 2 ). 
     Lastly, the data transmission between the electronic apparatus  510  and the electronic apparatus  520  may start by means of adjusting the clock pin CLK 1  of the electronic apparatus  510  and the clock pin CLK 2  of the electronic apparatus  520  to the high logic level H. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE (2) 
               
             
            
               
                   
                   
               
               
                   
                 Electronic apparatus 510 
                 Electronic apparatus 520 
               
            
           
           
               
               
               
               
               
            
               
                 Step 
                 CLK1 
                 DAT1 
                 CLK2 
                 DAT2 
               
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 1 
                 GPI 
                 L 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
               
               
                 2 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 H 
               
               
                 3 
                 GPO 
                 L 
                 GPI 
                 H 
                 GPI 
                 H 
                 GPI 
                 L 
               
               
                 4 
                 GPO 
                 L 
                 GPI 
                 L 
                 GPO 
                 L 
                 GPI 
                 L 
               
               
                 5 
                 GPI 
                 H 
                 GPI 
                 L 
                 GPO 
                 L 
                 GPI 
                 H 
               
               
                   
               
            
           
         
       
     
     Table (2) illustrates the input/output states and the voltage levels of the clock pin CLK 1 , the data pin DAT 1 , the clock pin CLK 2  and the data pin DAT 2  respectively during the process of detecting whether the electronic apparatus  510  and the electronic apparatus  520  are connected with each other and connecting direction information thereof when the electronic apparatus  510  and the electronic apparatus  520  of the present embodiment are connected in the reverse direction. Details with respect to steps 1 and 2 of Table (2) are the same as or similar to steps 1 and 2 of Table (1) and thus, will not be repeatedly described. 
     Being different from Table (1) above, in step 3 of Table (2), the data pin DAT 2  is changed to the low logic level L, such that the controller  522  may acquire that the connecting direction information is the reverse connection state. 
     Then, in step 4 of Table (2), the controller  522  of the electronic apparatus  520  may set the clock pin CLK 2  as the GPO type and transmit a detection signal SDT 7  at the low logic level L to the clock pin CLK 2  to adjust the clock pin CLK 2  from the high logic level H to the low logic level L, such that the electronic apparatus  520  may be ready for entering the communication mode. Accordingly, in step 4 of Table (2), the data pin DAT 1  of the electronic apparatus  510  is correspondingly changed to the low logic level due to being connected with the clock pin CLK 2 . 
     Then, in step 5 of Table (2), the controller  512  of the electronic apparatus  510  detects that the data pin DAT 1  is changed to the low logic level L and sets the clock pin CLK 1  as the GPI type, such that the electronic apparatus  510  may be ready for entering the communication mode. In this case, the electronic apparatus  510  and the electronic apparatus  520  are connected with each other in the reverse direction, and thus, one of the electronic apparatus  510  and the electronic apparatus  520  has to switch the functions of and the signals output by the clock pin CLK 1  and the data pin DAT 1  or the clock pin CLK 2  and the data pin DAT 2 . 
     Lastly, the data transmission between the electronic apparatus  510  and the electronic apparatus  520  may start by means of adjusting the clock pin CLK 1  of the electronic apparatus  510  and the clock pin CLK 2  of the electronic apparatus  520  to the high logic level H. 
     Additionally, in part of the embodiments, a switching unit may be disposed in each electronic apparatus for switching the output signals.  FIG. 6  is a schematic diagram illustrating switching units according to an embodiment of the invention. A switching unit  600  includes switches SW 1  to SW 4 . The switches SW 1  to SW 4  may be, for example, N-type or P-type metal-oxide-semidrive or field-effect transistors (MOSFETs), and the embodiments of the invention are not limited thereto. Each of the switches SW 1  to SW 4  has a first terminal, a second terminal and a control terminal and determines whether to turn on the first terminal and the second terminal according to a voltage applied to the control terminal. With the structure of the switching unit  600 , the first terminal of the switch SW 1  is coupled to the clock output terminal C_OUT 1  of the electronic apparatus, the second terminal of the switch SW 1  is coupled to the clock pin CLK 1 , and the control terminal of the switch SW 1  is coupled to a control signal SCT 1 . The first terminal of the switch SW 2  is coupled to the data output terminal D_OUT 1  of the electronic apparatus, the second terminal of the switch SW 2  is coupled to the clock pin CLK 1 , and the control terminal of the switch SW 2  is coupled to the control signal SCT 2 . The first terminal of the switch SW 3  is coupled to the clock output terminal C_OUT 1 , the second terminal of the switch SW 3  is coupled to data pin DAT 1 , and the control terminal of the switch SW 3  is coupled to a control signal SCT 2 . The first terminal of the switch SW 4  is coupled to the data output terminal D_OUT 1 , the second terminal of the switch SW 4  is coupled to the data pin DAT 1 , the control terminal of the switch SW 4  is coupled to the control signal SCT 1 . The control signals SCT 1  and SCT 2  may be generated according to the connecting direction information between the electronic apparatuses, so as to adaptively switch between the turned-on switches. 
       FIG. 7  is a flowchart illustrating a data transmission method according to an embodiment of the invention. The data transmission method of the present embodiment is applicable to the data transmission system illustrated in  FIG. 1 . Referring to  FIG. 1  and  FIG. 7 , in step S 710 , in a connecting detection mode, the electronic apparatus  110  transmits a detection signal SDT 1  to the clock pin CLK 1  and drives the data pin DAT 1  to a reference logic level LREF, and the electronic apparatus  120  transmits a detection signal SDT 2  to the clock pin CLK 2  and drives the data pin DAT 2  to the reference logic level LREF. In the meantime, in step S 720 , the electronic apparatus  110  determines whether the electronic apparatus  110  and the electronic apparatus  120  are connected with each other according to whether at least one of a signal on the clock pin CLK 1  and a signal on the data pin DAT 1  is varied. 
     Additionally, after step S 720 , when the electronic apparatus  110  and the electronic apparatus  120  are connected with each other, the electronic apparatus  110  determines whether the signal SDP on the data pin DAT 1  or the signal SCP on the clock pin CLK 1  is equal to the corresponding reference logic level, so as to determine connecting direction information of the electronic apparatus  110  and the electronic apparatus  120 . 
       FIG. 8  is a flowchart illustrating a data transmission method according to an embodiment of the invention. The data transmission method of the present embodiment is applicable to the data transmission system illustrated in  FIG. 1 . Referring to  FIG. 1  and  FIG. 8 , in step S 810 , in a connecting detection mode, the electronic apparatus  110  drops the clock pin CLK 1  to a low logic level (i.e., a first logic level) and drives the data pin DAT 1  to the high logic level (second logic level), and the electronic apparatus  120  drives the clock pin CLK 2  and the data pin DAT 2  to a high logic level. Then, in step S 820 , the electronic apparatus  110  receives a signal on the clock pin CLK 1 . Meanwhile, in step S 830 , the electronic apparatus  110  compares whether the signal on the clock pin CLK 1  is maintained at the low logic level, so as to determine whether the electronic apparatus  110  and the electronic apparatus  120  are connected with each other. 
     Additionally, after step S 830 , when the electronic apparatus  110  and the electronic apparatus  120  are connected with each other, the electronic apparatus  110  also transmits the detection signal SDT 5  to the clock pin CLK 1 . And, the electronic apparatus  120  determines the connecting direction information of the electronic apparatus  110  and the electronic apparatus  120  according to whether the pin receiving the detection signal SDT 5  is the clock pin CLK 2  or the data pin DAT 2 . 
     To summarize, in the invention, two electronic apparatuses when being connected with each other can transmit the detection signals of the pins (e.g., the clock pin and the data pin) that are connected with each other and can determine the connecting state and the connection direction between the electronic apparatuses according to the signal (i.e., the voltage level) of each pin. In this way, the functions of and the signals output by the pins of the apparatuses can be adaptively switched according to the determination result, such that the data transmission can be successfully performed between the electronic apparatuses which are connected in either the forward direction or the reverse direction, so as to enhance the convenience in use. 
     Although the invention has been described with reference to the above embodiments, it will be apparent to one of the ordinary skill in the art that modifications to the described embodiment may be made without departing from the spirit of the invention. Accordingly, the scope of the invention will be defined by the attached claims not by the above detailed descriptions.