Patent Publication Number: US-10324786-B2

Title: Method for managing data stored in flash memory and associated memory device and controller

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of the co-pending U.S. application Ser. No. 13/950,301 (filed on Jul. 25, 2013), which claims the benefit of U.S. provisional application 61/675,355 (filed on Jul. 25, 2012). The entire content of the related applications is incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The disclosed embodiments of the present invention relate to a flash memory, and more particularly, to a method for managing data stored in a flash memory and related memory apparatus and controller. 
     2. Description of the Prior Art 
     A flash memory can be used to store data through electrical erase and write/program, and is widely applied in the field of memory cards, solid-state drives, portable multi-media players, etc. Because the flash memory is a non-volatile memory, there is no need for extra power to maintain what is stored in the flash memory. In addition, the flash memory provides high speed data access and excellent vibration resistance, which explains its popularity. 
     The flash memories can be classified into two categories: NOR flash memories and NAND flash memories. For the later, the erase time and program time is shorter, and the die size of each memory cell is smaller. Thus, compared with the NOR flash memory, the NAND flash memory permits higher storage density and lower cost per bit. Generally speaking, the flash memory consists of memory cell arrays, wherein each memory cell is implemented using a floating-gate transistor in practice, and the threshold voltage of the memory cell is configured by properly controlling charge number at a floating gate of the floating-gate transistor to thereby store a single-bit data or a multi-bit data. Therefore, when one or more predetermined control gate voltages are imposed at the control gate of the floating-gate transistor, a conduction status of the floating-gate transistor will indicate one or more binary digits stored in the floating-gate transistor. 
     However, due to certain reasons, the original charge number of the flash memory may be affected/disturbed. For instance, the disturbance may come from retention disturbance, and a number of charges stored in the flash memory may changes due to high temperature. Hence, threshold voltage distribution of memory cells of the flash memory may change by the effect of retention time and/or temperature, and the data read from the memory cells may be erroneous since the threshold voltage distribution may be different from the original threshold voltage. 
     SUMMARY OF THE INVENTION 
     Therefore, one of the objectives of the present invention is to provide a method for managing data stored in a flash memory and related memory apparatus and controller, to avoid severe distortion of the data stored in memory cells. 
     According to an embodiment of the present invention, a method for managing data stored in a flash memory is disclosed. Where, the flash memory comprises a plurality of blocks, the method comprises: providing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks; detecting quality of a first block of the plurality of blocks to generate a first detection result, where the first block is the programmed block that has an earliest write time; and determining whether to move contents of the first block to a blank block, and delete the contents of the first block according to the first detection result. 
     According to another embodiment of the present invention, a memory apparatus is disclosed. The memory apparatus comprises a flash memory and a controller. The flash memory comprises a plurality of blocks. The controller comprises a memory for storing a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks. Where the controller detects quality of a first block of the plurality of blocks to generate a first detection result, where the first block is the programmed block that has an earliest write time; and determines whether to move contents of the first block to a blank block, and delete the contents of the first block according to the first detection result. 
     According to yet another embodiment of the present invention, a controller of a flash memory is disclosed. Where the controller is arranged for accessing a flash memory, the flash memory comprises a plurality of blocks, and the controller comprises a memory and a micro processor. The memory is arranged for storing a program code and a program list, where the program list records information about programmed blocks of the plurality of blocks and sequence of write times of the programmed blocks. The micro processor is arranged for executing the program code to control access of the flash memory and manage the plurality of blocks. Where the micro processor detects quality of a first block of the plurality of blocks to generate a first detection result, where the first block is the programmed block that has an earliest write time; and determines whether to move contents of the first block to a blank block, and delete the contents of the first block according to the first detection result. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a memory apparatus according to an embodiment of the present invention. 
         FIG. 2  is a diagram illustrating a program list according to an embodiment of the present invention. 
         FIG. 3  is flowchart illustrating a method for managing data stored in the flash memory according to an embodiment of the present invention. 
         FIG. 4  is diagram illustrating the step of moving contents of a block which has an earliest write time in the updated program list to a blank block. 
     
    
    
     DETAILED DESCRIPTION 
     Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is electrically connected to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections. 
     Please refer to  FIG. 1 , which is a diagram illustrating a memory apparatus  100  according to an embodiment of the present invention. The memory apparatus  100  of the present invention is particularly a portable memory apparatus (e.g. a memory card complying with SD/MMC, CF, MS or XD standard). The memory apparatus  100  includes a flash memory  120  and a controller. The controller may be a memory controller  110  arranged for accessing the flash memory  120 . According to this embodiment, the memory controller  110  includes a micro processor  112 , a memory  112 M, a control logic  114 , a buffer memory  116  and an interface logic  118 . The memory  112 M is used for storing a program code  112 C, and the micro processor  112  is used for executing the program code  112 C to control access of the flash memory  120 . 
     In a typical case, the flash memory  120  includes a plurality of blocks, and the controller (e.g. the memory controller  110  which executes the program code  112 C through the micro processor  112 ) performs processes, including copying data, erasing data, merging data, etc., upon the flash memory  120 , where the erase process is a block based process. In addition, a block records a specific number of pages, wherein the write process performed by the controller (e.g. the memory controller  110  which executes the program code  112 C through the micro processor  112 ) upon the flash memory  120  is a page based process. 
     In practice, the memory controller  110  may utilize its internal components to perform a variety of processes. For instance, the memory controller  110  utilizes the control logic  114  to control the access of the flash memory  120  (particularly, the access of at least one block or at least one page), or utilizes the buffer memory  116  to perform the desired buffering process, or utilizes the interface logic  118  to communicate with a host device. 
     In addition, the memory  112 M has a program list  112 P stored therein, where the program list  112 P records information about programmed blocks of the plurality of blocks and sequence of write times (relative write times) of the programmed blocks. For instance, please refer to  FIG. 2 , which is a diagram illustrating a program list  200  according to an embodiment of the present invention. As depicted in  FIG. 2 , it is assumed that the flash memory  120  has total N blocks B 1 -BN, where block B 2 -B 4 , B 7 -B 11  and B 14  are programmed previously, and sequence of write times thereof is B 14 , B 2 -B 4 , B 7 -B 11 . Hence, the program list  200  may sequentially record blocks B 14 , B 2 -B 4 , B 7 -B 11  on behalf of the sequence of write times of the programmed blocks. However, it should be noted that contents of the program list  200  depicted in  FIG. 2  are for illustrative purposes only, and not limitations of the present invention. In other embodiments of the present invention, it may be replaced by a different recording manner to record information about programmed blocks of a plurality of blocks and sequence of write times (relative write times) of the programmed blocks. 
     Please refer to  FIGS. 1-3  together.  FIG. 3  is a flowchart illustrating a method for managing data stored in the flash memory  120  according to an embodiment of the present invention. The method is described as follows. 
     In step  300 , the flow starts. In step  302 , when the memory controller  110  is in an idle status (i.e. the memory controller  110  is not receiving and executing any commands), the micro processor  112  detects quality of a block according to the program list  112 P, and accordingly generates a detection result, where the block is a programmed block that has the earliest write time. Taking the program list  200  shown in  FIG. 2  for example, the micro processor  112  performs the quality detection in respect of the block B 14 . Specifically speaking, the micro processor  112  generates the detection result by reading at least a portion of contents of the block B 14  (e.g. at least a portion of pages) and a bit error rate or bit error amount obtained during the decoding process. Alternatively, the micro processor  112  may generate the detection result by detecting a threshold voltage shifting status of at least a portion of memory cells included in the block B 14 , where each memory cell may be implemented by a floating-gate transistor. 
     Next, in step  304 , the micro processor  112  determines whether the quality of the block indicated by the detection result satisfies a criterion. If the quality of the block indicated by the detection result does satisfy the criterion, the flow will enter step  306 ; otherwise, step  308  will be performed. In details, considering a case where the micro processor  112  generates the detection result by detecting the bit error rate orbit error amount of at least a portion of contents of the block B 14  (step  302 ), when the detection result indicates that the bit error rate or the bit error amount of the at least a portion of contents of the block B 14  is higher than a threshold (step  304 ), the flow will enter step  308 . When the detection result indicates the bit error rate or the bit error amount of the at least a portion of contents of the block B 14  is lower than the threshold, the flow will enter step  306 . Furthermore, considering another case where the micro processor  112  generates the detection result by detecting the threshold voltage shifting status of at least a portion of memory cells included in the block B 14  (step  302 ), when the detection result indicates the threshold voltage shifting status of the at least a portion of memory cells included in the block B 14  does not satisfy a criterion (step  304 ), the flow will enter step  308 . When the detection result indicates the threshold voltage shifting status of the at least a portion of memory cells included in the block B 14  does satisfy the criterion, the flow will enter step  306 . 
     In step  306 , since the quality of the block B 14  meets the criterion, the micro processor  112  therefore keeps the data in the block B 14  intact. That is to say, the content of the block B 14  is allowed to remain unchanged for extending memory life. Besides, since the block B 14  is the programmed block that has the earliest write time, other blocks B 2 -B 4  and B 7 -B 11  having relatively later write time are unlikely to have data distortion issues caused by excessive retention time at this moment. Therefore, it is needless for the micro processor  112  to perform detection and determination process upon other blocks, and step  310  can be entered directly to end the flow. 
     In step  308 , since the quality of the block B 14  does not meet the criterion, the micro processor  112  moves all contents of the block B 14  to a blank/empty block, deletes the contents of the block B 14 , and updates the contents of the program list  200 . For instance, referring to  FIG. 4 , if the entire contents of the block B 14  are moved to the block B 15 , then the records associated with the block B 14  in the program list  200  will be deleted, and the contents of the block B 14  will be deleted. Moreover, a built-in backup block list  410  (which is arranged for recording which blocks in the flash memory  120  are blank) of the program code  112 C will become a blank block. The program list  200  will further append a record pertain to the block B 15  to its end. In addition, in the course of moving the entire contents of the block B 14  to the block B 15 , decoding and error correction operations are performed upon the data by the memory controller  110 . Therefore, the data moved to the block B 15  has better quality. 
     After step  308  is completed, the flow goes back to step  302  to detect quality of the block B 2  to generate a detection result, wherein the block B 2  is the programmed block that has the earliest write time recorded in the updated program list  200 . Next, the aforementioned process is repeated. 
     In summary, the method for managing data stored in a flash memory and related memory apparatus and controller utilize an idle period of the memory controller to move contents of a programmed block that has the earliest write time (i.e. longest retention time) and poor quality to a different block. In this way, the undesired situation of threshold voltage distribution variation and data distortion in a block with long retention time can be prevented. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.