Patent Publication Number: US-6211023-B1

Title: Method for fabricating a metal-oxide semiconductor transistor

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to semiconductor fabrication, and more particularly to a method for fabricating a metal-oxide semiconductor (MOS) transistor, using an improved ion implantation process. 
     2. Description of Related Art 
     A semiconductor device always includes several MOS transistors, which are fabricated in high integration so as to form an integrated circuit (IC) device. The MOS transistors are the fundamental elements of the IC device. Its properties, such as operation speed, determine the performance of the IC device. 
     FIGS. 1A-1C are cross-sectional views, schematically illustrating a conventional fabrication process of a MOS transistor. In FIG. 1A, a field oxide layer (FOX)  12  serving as an isolation structure is formed on a semiconductor substrate  10 . An area of the substrate  10  other than the FOX layer  12  is called an active area, where an MOS transistor  14  is formed. The MOS transistor  14  includes a gate oxide layer  20 , a gate  22 , and a lightly doped region  16 , in which the gate oxide layer  20  and the gate  22  forms together as a gate structure  19 . Conventionally, in order to prevent a punch through effect from occurring on the junction, an anti-punch-through implantation is usually performed to form a halo doped region  18  below the lightly doped region  16  by a higher ion energy beam. The dopant type of the halo doped region  18  is opposite to the dopant type doped in the interchangeable source/drain region. A dopant conventionally may be viewed as a substance, such as boron, added in small amounts to a pure semiconductor material to alter its conductive properties for use in transistors and diodes. 
     In FIG. 1B, a thin conformal silicon dioxide layer (not shown) is formed over the substrate  10 , and a silicon nitride layer (not shown) is formed on the silicon dioxide layer. An etching back process is performed to remove the silicon nitride layer and the silicon dioxide layer, all of which respectively leave a silicon dioxide remains  24 , or called a liner oxide layer  24 , and a silicon nitride remains  26  and form together on each side of the gate structure  19  to serve as a sidewall spacer. As seen in FIG. 1B, the liner oxide layer  24  extends over the lightly doped region  16 . This extension may be throught of as an extension of gate oxide layer  20  that overlaps the lightly doped region  16 . 
     In FIG. 1C, using the FOX layer  12 , the gate structure  19  as a mask, an ion implantation process with a higher dosage density is performed to dope an exposed area of the substrate  10  at the lightly doped region  16 . After an annealing process, a heavily doped region  28  abutting the lightly doped region  16  and the halo doped region  18  is formed. All of the lightly doped region  16 , the heavily doped region  28  and the halo doped region  18  serve together as an interchangeable region of the transistor  14 . 
     In the above descriptions, for a design of a sub-micron IC device, in order to prevent the punch through effect from occurring on the junction, which is the interchangeable source/drain region, the anti-punch-through implantation is usually performed to form the halo doped region  18  below the lightly doped region  16 . 
     Moreover, in order to increase an direct-current (DC) operation speed of the MOS transistor  14  of FIG. 1A, the heavily doped region  28  is necessary to be formed. However, a depletion region usually exists at an interface of the interchangeable source/drain region and the substrate due to, for example, a depletion of electron-holes for P-type substrate. This depletion region behaves like an capacitor and contributes a junction capacitance. The junction capacitance is larger if the depletion region is larger. The depletion region is larger if the dopant density is larger or junction contact area is larger. A higher dopant density also needs a higher dopant density in the halo doped region in order to reduce a short channel effect. Since the heavily doped region  28  carries higher dopant density, it results in a higher junction capacitance. It is natural for an AC circuit that the junction capacitance can reduce an alternative-current (AC) operation speed. In addition, the gate oxide layer also induces an oxide capacitor, which is coupled with the junction capacitor in series. The oxide capacitor increases the junction capacitance and causes a slower AC operation speed. 
     Furthermore, if the junction capacitance is reduced through a reduction of the junction contact area, the junction depth is usually reduced. This causes a difficult control on the margin of junction. 
     SUMMARY OF THE INVENTION 
     It is therefore an objective of the present invention to provide an improved method for forming an interchangeable source/drain region. The improved method includes a formation of a low dopant density region below the interchangeable source/drain region so as to reduce a junction capacitance. An AC operation speed is further increased. 
     It is another an objective of the present invention to provide an improved method for forming an interchangeable source/drain region. The improved method includes a formation of a low dopant density region below the interchangeable source/drain region so as to allow a thicker junction depth to be formed. Thus a margin of the junction can be more easily controlled. 
     It is still another an objective of the present invention to provide an improved method for forming a spacer on each sidewall of a gate structure. The improved method includes forming a thin liner spacer instead so as to reduce a lateral extension length of the interchangeable source/drain region. The overlap region between the gate structure and the interchangeable source/drain region is therefore reduced so that a less overlapping capacitance can be obtained. An AC operation speed is further increased. 
     In accordance with the foregoing and other objectives of the present invention, an improved method for fabrication a MOS transistor is provided. The improved method is suitable for a semiconductor substrate having a gate structure. The improved method includes forming a liner spacer on each side of the gate structure. Using the gate structure and the liner spacer as a mask, an ion implantation process with very high beam energy is performed to form a low dopant density region deep inside the substrate. The dopant is a first-type dopant, which is opposite to the substrate. A lightly doped region with the first-type dopant is formed in the low dopant density region on the top portion preferably by ion implantation. An anti-punch-through region having a second-type dopant with a sufficient dopant density is formed between the low dopant density region and the lightly doped region. The second-type dopant is opposite to the first-type dopant so as to prevent a punch-through effect from occurring. A sidewall spacer is formed on the liner spacer, which is on each side of the gate structure. Using the gate structure and the spacers as a mask, an ion implantation process is performed to form a heavily doped region in the substrate on the top portion of the low dopant density region. The heavily doped region is doped with the first-type dopant and has a dopant density higher than the low dopant density region and the lightly doped region. Thus, the junction of the MOS transistor of the invention includes an interchangeable source/drain region, which includes the lightly doped region and the heavily doped region, the anti-punch-through region, and the low dopant density region below these three regions to separate these three regions from the substrate. 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     The invention can be more fully understood by reading the following detailed description of the preferred embodiment, with reference made to the accompanying drawings as follows: 
     FIGS. 1A-1C are cross-sectional views of a MOS transistor, schematically illustrating a conventional fabrication process of the MOS transistor; and 
     FIGS. 2A-2F are cross-section views of a MOS transistor, schematically illustrating an improved fabrication process of the MOS transistor, according to a preferred embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENT 
     FIGS. 2A-2F are cross-section views of a MOS transistor, schematically illustrating an improved fabrication process of the MOS transistor, according to a preferred embodiment of the invention. In FIG. 2A, a semiconductor substrate  100  having several isolation structures, such as field oxide (FOX) layers  120 , is provided. A gate structure  130  including a gate oxide layer  140  and a gate  160  on the substrate between the FOX layers  120 . A silicon oxide layer (not shown) including, conformal to the substrate top surface, is formed preferably by chemical vapor deposition (CVD) to at least cover the gate structure. An etching back process is performed to remove the silicon oxide layer so that a remains of the silicon oxide layer forms a liner spacer  170  on each side of the gate structure  130 . The silicon oxide layer preferably includes silicon dioxide. 
     In FIG. 2B, a first ion implantation process is performed, using the gate structure  130  as a mask, to form a low dopant density region  175  deep inside the substrate  100 . The dopant is a first-type, which is opposite DY complementary to the substrate  100 . For example, if the substrate is a P-type substrate, the first-type dopant is an N-type dopant. If the substrate is an N-type substrate, the first-type dopant is a P-type dopant. The dopant type of the substrate  100  is also called a second-type dopant in this description. The dopant density of the low dopant density region  175  is about 10 13  ions/cm 2 . The ion beam energy is sufficiently high so as to obtain a greater depth. 
     In FIG. 2C, using the gate structure  130  as a mask, a second ion implantation process is performed to form a lightly doped region  188  on the top of the low dopant density region  175  in the substrate  100 . The doped dopant is the first-type dopant with a medium dopant density of about 10 14  ion/cm 2 . The lightly doped region  188  serves as a lightly doped drain (LDD) structure when an interchangeable source/drain region is formed later. 
     In FIG. 2D, a third ion implantation process is performed with a proper energy and the second-type dopant with a sufficient dopant density to form an anti-punch-through region  220  between the low dopant density region  175  and the lightly doped region  188 . The purpose of the anti-punch-through region  220  is to prevent a punch-through effect from occurring. As stated in connection  15  with FIG. 2B, the second-type dopant is opposite to the first-type dopant. 
     In FIG. 2E, an insulating layer (not shown) including, for example, silicon oxide or silicon nitride is formed over the substrate  100  by, example, CVD. An etching back process is performed to remove the insulating layer so that a remains of the insulating layer forms a sidewall spacer  260  on the liner spacer  170 , which is on each side of the gate structure  130 . 
     In FIG. 2F, an fourth ion implantation process is performed to form a heavily doped region  280  in the substrate  100  abutting the lightly doped region  188 , the anti-punch-through region  220  and the low dopant density region  1765 . After an annealing process, the heavily doped region  280  is completely formed. The heavily doped region serving a main body of the interchangeable source/drain region of the MOS transistor includes the first-type dopant with a dopant density of about 10 15  ions/cm 2 , which is higher than those of the lightly doped region  188  and the low dopant density region  175 . A junction structure of the MOS transistor includes the interchangeable source/drain region, which includes the lightly doped region  188  and the heavily doped region  280 , the anti-punch-through region  220 , and the low dopant density region  175  below these three regions  188 ,  220 ,  280  to separate them from the substrate  100 . 
     In the invention, the low dopant density region  175  can reduce the junction capacitance of a depletion region (not shown) between the junction structure and the substrate due to a proper distribution of the dopant density gradient. The liner spacer  170 , which is different from the liner oxide layer  24  of FIG. 1B, can reduce the extension of the gate oxide layer  140  so that the overlapping region between the lightly doped region  188  and the gate structure  130  is reduced. A capacitance effect from the overlapping region is reduced. In a total improvement, the junction capacitance is reduced so that the AC operation speed is increased. 
     Moreover, the low dopant density region  175  is formed in a greater depth. This allows a greater depth of the interchangeable source/drain region to be formed without increasing junction capacitance. A shallow junction structure is conventionally taken so as to decrease the short channel effect. Because the depth of the interchangeable source/drain region of the invention is not necessary to be as shallow as a conventional one, a subsequent fabrication process, such as a self-aligned silicide (Salicide) process, can be easier without a worry about the Salicide being formed over-through the margin of the interchangeable source/drain margin to have an undesired contact to the substrate  100 . 
     In conclusion, the method for fabricating a MOS transistor of the invention has several characteristic as follows: 
     1. The low dopant density region  175  with a lower dopant density is formed on each side of the gate structure  130  below the interchangeable source/drain region so as to form a proper dopant density gradient, which can reduce a size of the depletion region, resulting in a smaller junction capacitance. 
     2. The liner spacer  170  provides a smaller overlapping region between the gate structure  130  and the interchangeable source/drain region so as to reduce the gate oxide capacitance effect. The junction capacitance is further reduced. 
     3. Due to the property of the low dopant density region  175 , the junction capacitance is effectively reduced so that a shallow junction structure is not necessary. A greater depth of the junction structure of the interchangeable source/drain region is very helpful for the subsequent fabrication process, such as a Salicide process. There is no worry about the junction structure being broken through by the Salicide structure to causes an undesired contact to the substrate  100 . 
     The invention has been described using an exemplary preferred embodiment. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiment. On the contrary, it is intended to cover various modifications and similar arrangement. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.