Patent Publication Number: US-11652117-B2

Title: Image sensing device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This patent document claims the priority and benefits of Korean patent application No. 10-2020-0013094, filed on Feb. 4, 2020, which is hereby incorporated in its entirety by reference. 
     TECHNICAL FIELD 
     The technology and implementations disclosed in this patent document generally relate to an image sensing device. 
     BACKGROUND 
     An image sensor is a semiconductor device for converting an optical image into electrical signals. In recent times, with the increasing development of computer industries and communication industries, demand for high-quality and high-performance image sensors is rapidly increasing in various fields, for example, digital cameras, camcorders, personal communication systems (PCSs), game consoles, surveillance cameras, medical micro-cameras, robots, etc. 
     Image sensing devices may be broadly classified into CCD (Charge Coupled Device)-based image sensors and CMOS (Complementary Metal Oxide Semiconductor)-based image sensors. The CMOS image sensors have simpler and more convenient driving schemes, and thus may be preferred in some applications. Also, CMOS image sensors may integrate a signal processing circuit into a single chip, making it easy to miniaturize CMOS image sensors for implementation in a product with the added benefits of consuming very low power. CMOS image sensors can be fabricated using CMOS fabrication technology, which results in low manufacturing costs. CMOS image sensors have been widely used and designed to implement high-resolution images while CMOS image sensors have been intensively researched. 
     In addition, as the image resolution of the CMOS image sensor gradually increases, each pixel is gradually reduced in size in a manner that the number of pixels can increase without increasing the chip size. 
     SUMMARY 
     Various embodiments of the disclosed technology relate to an image sensing device having a high dynamic range, which can acquire low-illuminance and high-illuminance characteristics by adjusting a conversion gain. 
     Various embodiments of the disclosed technology relate to an image sensing device having a new layout structure capable of adjusting a conversion gain in a shared pixel structure configured to share floating diffusion (FD) regions. 
     In accordance with an embodiment of the disclosed technology, an image sensing device may include a first unit pixel including a first photoelectric conversion element configured to generate photocharges in response to incident light, and a first floating diffusion region configured to receive photocharges generated by the first photoelectric conversion element, a second unit pixel including a second photoelectric conversion element configured to generate photocharges in response to incident light, and a second floating diffusion region configured to receive photocharges generated by the second photoelectric conversion element, a third unit pixel including a third photoelectric conversion element configured to generate photocharges in response to incident light, and a third floating diffusion region configured to receive photocharges generated by the third photoelectric conversion element, and a fourth unit pixel including a fourth photoelectric conversion element configured to generate photocharges in response to incident light, and a fourth floating diffusion region configured to receive photocharges generated by the fourth photoelectric conversion element. The first to fourth unit pixels may be isolated from each other by a first device isolation structure. The first to fourth floating diffusion regions may be coupled to a common floating diffusion node through conductive lines. At least one unit pixel among the first to fourth unit pixels may include a conversion gain transistor coupled to the common floating diffusion node and configured to adjust capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor. 
     In accordance with another embodiment of the disclosed technology, an image sensing device may include a plurality of pixel groups arranged in a first direction and a second direction perpendicular to the first direction. Each pixel group may include unit pixels that are isolated from one another by a first device isolation structure. Each of the unit pixels may include a photoelectric conversion element configured to generate photocharges by performing photoelectric conversion of incident light, a floating diffusion region configured to receive the photocharges, and a transfer transistor configured to transmit the photocharges generated by the photoelectric conversion element to the floating diffusion region. The floating diffusion regions of the unit pixels may be coupled to a common floating diffusion node through conductive lines. At least one of the unit pixels may include a conversion gain transistor configured to adjust capacitance of the common floating diffusion node in response to a gain control signal provided to the conversion gain transistor. 
     It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the disclosure as claimed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and beneficial aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings. 
         FIG.  1    is an example of a block diagram illustrating an image sensing device based on some implementations of the disclosed technology. 
         FIG.  2    is an example of a schematic diagram illustrating a layout structure of a pixel group (PXG) shown in  FIG.  1    based on some implementations of the disclosed technology. 
         FIG.  3    is an example of an equivalent circuit diagram illustrating an equivalent circuit corresponding to the pixel group (PXG) shown in  FIG.  1    based on some implementations of the disclosed technology. 
         FIG.  4 A  is an example of a schematic diagram illustrating a layout structure of a unit pixel (PX 1 ) contained in the pixel group (PXG) shown in  FIG.  2    based on some implementations of the disclosed technology. 
         FIG.  4 B  is an example of a schematic diagram illustrating a layout structure of a unit pixel (PX 2 ) contained in the pixel group (PXG) shown in  FIG.  2    based on some implementations of the disclosed technology. 
         FIG.  4 C  is an example of a schematic diagram illustrating a layout structure of a unit pixel (PX 3 ) contained in the pixel group (PXG) shown in  FIG.  2    based on some implementations of the disclosed technology. 
         FIG.  4 D  is an example of a schematic diagram illustrating a layout structure of a unit pixel (PX 4 ) contained in the pixel group (PXG) shown in  FIG.  2    based on some implementations of the disclosed technology. 
         FIG.  5    is a cross-sectional view illustrating an example of a unit pixel taken along the line A-A′ shown in  FIG.  4 C  based on some implementations of the disclosed technology. 
     
    
    
     DETAILED DESCRIPTION 
     This patent document provides implementations and examples of an image sensing device and the disclosed features may be implemented to substantially address one or more issues due to limitations and disadvantages of various image sensing devices. Some implementations of the disclosed technology may suggest designs of an image sensing device having a high dynamic range, which can acquire low-illuminance and high-illuminance characteristics by adjusting a conversion gain. Some implementations of the disclosed technology may be used to provide designs of an image sensing device having a new layout structure capable of adjusting a conversion gain in a shared pixel structure in which floating diffusion (FD) regions are shared. For example, the disclosed technology provides various implementations of an image sensing device which can improve operational characteristics thereof, and also provides various implementations of an image sensing device which can adjust a conversion gain without increasing the size of pixels within a shared structure in which a plurality of pixels shares floating diffusion (FD) regions. 
     Reference will now be made in detail to certain embodiments, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or similar parts. In the following description, a detailed description of related known configurations or functions incorporated herein will be omitted to avoid obscuring the subject matter. 
       FIG.  1    is a block diagram illustrating an example of an image sensing device  100  based on some implementations of the disclosed technology. 
     Referring to  FIG.  1   , the image sensing device  100  may include a pixel array  110 , a row decoder  120 , a correlated double sampler (CDS) circuit  130 , an analog-to-digital converter (ADC) circuit  140 , an output buffer  150 , a column decoder  160 , and a timing controller  170 . In this case, the above-mentioned constituent elements of the image sensing device  100  are disclosed only for illustrative purposes, and at least some elements may be added to or omitted from the image sensing device  100  as necessary. 
     The pixel array  110  may include a plurality of pixel groups (PXGs) consecutively and repeatedly arranged in a matrix shape. Each pixel group (PXG) may include a plurality of unit pixels to convert incident light received from outside into an electrical signal. Each unit pixel may include a photosensing pixel to generate photocharges by converting incident light into an electrical signal. The unit pixels contained in each pixel group (PXG) may be shared pixels in which floating diffusion (FD) regions respectively formed in the unit pixels are coupled to each other through conductive lines. Each of the unit pixels may receive a drive signal including a selection signal, a reset signal, a transmission signal, and a gain control signal, etc. from the row decoder  120  through row lines, and may be driven by the drive signal. 
     The row decoder  120  may drive the pixel array  110  upon receiving a control signal from the timing controller  170 . In particular, the row decoder  120  may select at least one row line from among a plurality of row lines of the pixel array  110 . In order to select at least one row line from among the plurality of row lines, the row decoder  120  may generate a row selection signal. The row decoder  120  may sequentially enable the pixel reset signal and the transmission signal for pixels corresponding to the at least one selected row line. Therefore, an analog reference signal and an analog image signal may be generated by each of the pixels contained in the selected row line, such that the analog reference signals and the analog image signals generated by the respective pixels contained in the selected row line can be sequentially transferred to the correlated double sampler (CDS) circuit  130 . In this case, the reference signal and the image signal generated by each pixel may be generically called a pixel signal as necessary. 
     The correlated double sampler (CDS) circuit  130  may sequentially sample and hold the reference signal and the image signal that are transferred from the pixel array  110  to the plurality of column lines. That is, the correlated double sampler (CDS) circuit  130  may sample and hold levels of the reference signal and the image signal that correspond to each column of the pixel array  110 . 
     The correlated double sampler (CDS) circuit  130  may transmit a correlated double sampling (CDS) signal corresponding to the reference signal and the image signal for each column to the ADC circuit  140  upon receiving a control signal from the timing controller  170 . 
     The ADC circuit  140  may receive the CDS signal for each column from the CDS circuit  130 , may convert the received CDS signal into a digital signal, and may thus output the digital signal. The ADC circuit  140  may perform counting and calculation operations based on the CDS signal for each column and a ramp signal received from the timing controller  170 , such that the ADC circuit  140  may generate digital image data from which noise (for example, unique reset noise for each pixel) corresponding to each column is removed. 
     The ADC circuit  140  may include a plurality of column counters corresponding to respective columns of the pixel array  110 , and may convert the CDS signal for each column into a digital signal using the column counters. In accordance with another embodiment, the ADC circuit  140  may include a single global counter, and may convert a CDS signal corresponding to each column into a digital signal using a global code received from the global counter. 
     The output buffer  150  may receive image data for each column output from the ADC circuit  140 , may capture the received image data, and may output the captured image data. The output buffer  150  may temporarily store image data that is output from the ADC circuit  140  upon receiving a control signal from the timing controller  170 . The output buffer  150  may operate as an interface configured to compensate for a difference in transmission speed (or in processing speed) between the image sensor  100  and another device coupled to the image sensor  100 . 
     The column decoder  160  may select a column of the output buffer  150  upon receiving a control signal from the timing controller  170 , and the image data temporarily stored in the selected column of the output buffer  150  may be sequentially output. In more detail, the column decoder  160  may receive an address signal from the timing controller  170 , may generate a column selection signal based on the received address signal, and may select a column of the output buffer  150 , such that the column decoder  160  may control image data from the selected column of the output buffer  150  to be output as an output signal SO. 
     The timing controller  170  may control the row decoder  120 , the ADC circuit  140 , the output buffer  150 , and the column decoder  160 . 
     The timing controller  170  may transmit a clock signal needed for the constituent elements of the image sensor  100 , a control signal needed for timing control, and address signals needed for selection of a row or column to the row decoder  120 , the column decoder  160 , the ADC circuit  140 , and the output buffer  150 . In accordance with the embodiment, the timing controller  170  may include a logic control circuit, a phase locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, etc. 
       FIG.  2    is an example of a schematic diagram illustrating a layout structure of the pixel group (PXG) shown in  FIG.  1    based on some implementations of the disclosed technology. 
     Referring to  FIG.  2   , each pixel group (PXG) may include 4 unit pixels PX 1  to PX 4 . The unit pixels PX 1  to PX 4  may be arranged contiguous or adjacent to one another in a first direction (X-axis direction) and a second direction (Y-axis direction) perpendicular to the first direction. For example, the unit pixels PX 1 ˜PX 4  may be arranged in a (2×2) matrix shape. 
     Each of the unit pixels PX 1  to PX 4  may be an isolated pixel that is physically isolated from contiguous or adjacent unit pixels by a device isolation structure ISO 1 . For example, each of the unit pixels PX 1  to PX 4  is includes its own photoelectric conversion element PD 1  to PD 4 , a single floating diffusion (FD) region FD 1  to FD 4 , or transistors. Thus, any two of the unit pixels do not share photoelectric conversion elements PD 1  to PD 4 , floating diffusion (FD) regions FD 1  to FD 4 , and transistors (TX 1  to TX 4 , DX 1  to DX 3 , SX 1  to SX 3 , RX, CGX). 
     In some implementations, the device isolation structure ISO 1  may include a trench-shaped isolation structure in which a substrate is etched to a predetermined depth and an insulation material fills the etched region. For example, the device isolation structure ISO 1  may include a Deep Trench Isolation (DTI) structure, a Shallow Trench Isolation (STI) structure, or a combination thereof. 
     Electrical connection between elements contained in different unit pixels may be achieved through a conductive line (e.g., a metal line) formed over the substrate. 
     Each of the unit pixels PX 1  to PX 4  may include a Back Side Illumination (BSI) structure or a Front Side Illumination (FSI) structure. 
     Each of the unit pixels PX 1  to PX 4  may include a single photoelectric conversion element (any one of PD 1  to PD 4 ), a single floating diffusion (FD) region (any one of FD 1  to FD 4 ), and three transistors. As the example shown in  FIG.  2   , the types of the transistors included in some unit pixels contained in the pixel group (PXG) can be different from those included in other unit pixels. In  FIG.  2   , 3 unit pixels PX 1 , PX 2 , and PX 4  contained in the pixel group (PXG) may include three transistors including a transfer transistor (any one of TX 1 , TX 2 , and TX 4 ), a source follower transistor (any one of DX 1 , DX 2 , and DX 4 ), and a selection transistor (any one of SX 1 , SX 2 , and SX 4 ). The unit pixel PX 3  contained in the pixel group (PXG) may include a transfer transistor TX 3 , a reset transistor RX, and a conversion gain transistor CGX. 
     In the implementation above, four unit pixels PX 1  to PX 4  include total 12 transistors including 4 transfer transistors, 3 source follower transistors, 3 selection transistors, a single reset transistor, and a single conversion gain transistor, and each of the unit pixels PX 1  to PX 4  may include 3 transistors. 
     As an example, 4 transfer transistors may be formed in the unit pixels PX 1  to PX 4 , respectively. 3 source follower transistors may be formed in three unit pixels PX 1 , PX 2  and PX 4 , respectively. 3 selection transistors may be formed in three unit pixels PX 1 , PX 2  and PX 4 , respectively. A single reset transistor and a single conversion gain transistor may be formed in the remaining unit pixel PX 3  in which the source follower transistor and the selection transistor are not formed. 
     The photoelectric conversion elements PD 1  to PD 4  may be respectively formed in the corresponding unit pixels PX 1  to PX 4  on a one to one basis. The photoelectric conversion elements PD 1  to PD 4  may generate photocharges by performing photoelectric conversion of incident light. Each unit pixel includes a photoelectric conversion element which includes, for example, a photodiode, a photogate, a phototransistor, a photoconductor, or some other photosensing structures capable of generating photocharges. 
     The floating diffusion (FD) regions FD 1  to FD 4  may receive photocharges generated by the photoelectric conversion elements PD 1  to PD 4  through the transfer transistors TX 1  to TX 4 , and may temporarily store the received photocharges. The floating diffusion (FD) regions FD 1  to FD 4  may be electrically coupled to each other through conductive lines. Thus, the unit pixels PX 1  to PX 4  contained in the pixel group (PXG) may be configured to share the floating diffusion (FD) regions FD 1  to FD 4  and have a 4-shared pixel structure. 
     The length of the conductive lines that electrically couple the floating diffusion (FD) regions to one another depends on the arrangement of the floating diffusion (FD) regions connected through the conductive lines. In order to minimize the length of conductive lines by which the floating diffusion (FD) regions FD 1  to FD 4  are coupled to each other, the floating diffusion (FD) regions may be positioned as close as possible in the pixel group (PXG). For example, the floating diffusion (FD) regions FD 1  to FD 4  may be located closest to each other within the pixel group (PXG). For example, the floating diffusion (FD) regions FD 1  to FD 4  may be arranged around corner regions of the corresponding unit pixels PX 1  to PX 4  such that the floating diffusion regions FD 1  to FD 4  can meet around the center portion of the pixel group (PXG). 
     In the unit pixels (PX 1  to PX 4 ), the transfer transistors TX 1  to TX 4  may be arranged contiguous or adjacent to the floating diffusion (FD) regions FD 1  to FD 4  in the first direction. In the unit pixels PX 1 , PX 2 , and PX 4 , the source follower transistors DX 1  to DX 3  may be arranged contiguous or adjacent to the floating diffusion (FD) regions FD 1 , FD 2 , and FD 4  in the second direction, and the selection transistors SX 1  to SX 3  may be arranged contiguous or adjacent to the source follower transistors DX 1  to DX 3  in the first direction. In the unit pixel PX 3 , the conversion gain transistor CGX may be arranged contiguous or adjacent to the floating diffusion (FD) region FD 3  in the second direction, and the reset transistor RX may be arranged contiguous or adjacent to the conversion gain transistor CGX in the first direction. 
     The unit pixels PX 1  to PX 4  may include tap regions T 1  to T 4 , respectively. The tap regions T 1  to T 4  may be located at one side of the transfer transistors TX 1  to TX 4  in the first direction. Thus, the tap regions T 1  to T 4  may be respectively located opposite to the floating diffusion (FD) regions FD 1  to FD 4 . Here, each of the tap regions T 1  to T 4  may apply a bias voltage to a well region of the substrate. 
     As described above, the unit pixels PX 1 , PX 2 , and PX 4  may include the same constituent elements. In this case, the constituent elements contained in the unit pixel PX 1  and the constituent elements contained in the unit pixel PX 2  may be arranged symmetrical to each other with respect to a boundary region between the unit pixel PX 1  and the unit pixel PX 2 . In addition, the constituent elements contained in the unit pixel PX 2  and the constituent elements contained in the unit pixel PX 4  may be arranged symmetrical to each other with respect to a boundary region between the unit pixel PX 2  and the unit pixel PX 4 . 
     Although  FIG.  2    illustrates an exemplary case in which the reset transistor RX and the conversion gain transistor CGX are formed in the unit pixel PX 3  for convenience of description, such implementation is provided as one example only and other implementations are also possible. For example, the reset transistor RX and the conversion gain transistor CGX may be formed in any one of the unit pixels PX 1 , PX 2 , and PX 4 , and the selection transistor and the source follower transistor may be formed in the unit pixel PX 3 . 
       FIG.  3    is an example of an equivalent circuit diagram illustrating an equivalent circuit corresponding to the pixel group (PXG) shown in  FIG.  1    based on some implementations of the disclosed technology. 
     Referring to  FIG.  3   , the pixel group (PXG) may include photoelectric conversion elements PD 1  to PD 4 , floating diffusion regions FD 1  to FD 4 , transfer transistors TX 1  to TX 4 , source follower transistors DX 1  to DX 3 , selection transistors SX 1  to SX 3 , a reset transistor RX, a conversion gain transistor CGX, and a conversion gain capacitor C. 
     Each of the photoelectric conversion elements PD 1  to PD 4  may perform photoelectric conversion of incident light, and may thus generate photocharges corresponding to the amount of incident light. Each of the photoelectric conversion elements PD 1  to PD 4  may be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. 
     The transfer transistors TX 1  to TX 4  may be coupled to the photoelectric conversion elements PD 1  to PD 4  and the floating diffusion regions FD 1  to FD 4 . In some implementations, the transfer transistor TX 1  may be coupled to the photoelectric conversion element PD 1  and the floating diffusion region FD 1 , the transfer transistor TX 2  may be coupled to the photoelectric conversion element PD 2  and the floating diffusion region FD 2 , the transfer transistor TX 3  may be coupled to the photoelectric conversion element PD 3  and the floating diffusion region FD 3 , and the transfer transistor TX 4  may be coupled to the photoelectric conversion element PD 4  and the floating diffusion region FD 4 . Thus, one terminal of each transfer transistor TX 1  to TX 4  may be coupled to the photoelectric conversion element PD 1  to PD 4  in the same unit pixel, and the other terminal of each transfer transistor TX 1  to TX 4  may be coupled to the floating diffusion region FD 1  to FD 4  in the same unit pixel. The transfer transistors TX 1  to TX 4  may be turned on or off in response to transmission signals TS 1  to TS 4  applied to gate terminals thereof, such that the transfer transistors TX 1  to TX 4  may transmit photocharges generated by the photoelectric conversion elements PD 1  to PD 4  to the corresponding floating diffusion regions FD 1  to FD 4 . 
     The floating diffusion regions FD 1  to FD 4  may be electrically and commonly coupled to each other through conductive lines, resulting in formation of a common floating diffusion (CFD) node. The common floating diffusion (CFD) node may be modeled as a single junction capacitor coupled in parallel to the floating diffusion regions FD 1  to FD 4 . Capacitance of the common floating diffusion (CFD) node may be denoted by the sum of capacitances of the floating diffusion regions FD 1  to FD 4 . The common floating diffusion (CFD) node may receive photocharges of the photoelectric conversion elements PD 1  to PD 4  through the transfer transistors TX 1  to TX 4 , and may temporarily store the received photocharges. 
     The source follower transistors DX 1  to DX 3  may be coupled to a power-supply voltage (VDD) node and the selection transistors SX 1  to SX 3  corresponding thereto. In some implementations, one terminal of the source follower transistor DX 1  may be coupled to the power-supply voltage (VDD) node and the other terminal of the source follower transistor DX 1  may be coupled to the selection transistor SX 1  belonging to the same unit pixel, one terminal of the source follower transistor DX 2  may be coupled to the power-supply voltage (VDD) node and the other terminal of the source follower transistor DX 2  may be coupled to the selection transistor SX 2  belonging to the same unit pixel, and one terminal of the source follower transistor DX 3  may be coupled to the power-supply voltage (VDD) node and the other terminal of the source follower transistor DX 3  may be coupled to the selection transistor SX 3  belonging to the same unit pixel. The source follower transistors DX 1  to DX 3  may be coupled to the common floating diffusion (CFD) node through gate terminals thereof, may generate a signal corresponding to the magnitude of an electric potential of the common floating diffusion (CFD) node, and may output the generated signal to the corresponding selection transistors SX 1  to SX 3 . Thus, each of the source follower transistors DX 1  to DX 3  may amplify a potential change of the common floating diffusion (CFD) node, and may output the amplified potential to the selection transistors SX 1  to SX 3 . 
     The selection transistors SX 1  to SX 3  may be respectively coupled to the source follower transistors DX 1  to DX 3  corresponding thereto, and each of the selection transistors SX 1  to SX 3  may be coupled to an output node (OUT). The selection transistors SX 1  to SX 3  may be turned on or off in response to the row selection signal (RSS) applied to gate terminals thereof, such that the selection transistors SX 1  to SX 3  may transmit output signals of the source follower transistors DX 1  to DX 3  to the output node (OUT). The output node (OUT) may be coupled to column lines. The selection transistors SX 1  to SX 3  according to the present embodiment may be commonly coupled to the single output node (OUT), and may receive the same row selection signal (RSS) through gate terminals thereof, such that the selection transistors SX 1  to SX 3  may operate as a single transistor having a relatively large channel width. 
     The reset transistor RX and the conversion gain transistor CGX may be coupled in series between the power-supply voltage (VDD) node and the common floating diffusion (CFD) node. The conversion gain capacitor (C) for adjusting capacitance of the common floating diffusion (CFD) node may be coupled to a common node of the reset transistor RX and the conversion gain transistor CGX. The reset transistor RX may be turned on or off in response to the reset signal (RS) applied to a gate terminal thereof, such that the reset transistor RX may reset the common floating diffusion (CFD) node to a power-supply voltage (VDD) level. The conversion gain transistor CGX may enable the conversion gain capacitor (C) to be selectively coupled in parallel to the common floating diffusion (CFD) node in response to the gain control signal GCS applied to a gate terminal thereof, such that the conversion gain transistor CGX can adjust capacitance of the common floating diffusion (CFD) node. The gain control signal GCS may be received from the row decoder  120 . 
       FIGS.  4 A to  4 D  are schematic diagrams illustrating layout structures of unit pixels PX 1  to PX 4  contained in the pixel group (PXG) shown in  FIG.  2    based on some implementations of the disclosed technology. 
     In the substrate, a region in which unit pixels are formed may be defined by a device isolation structure ISO 1 . The device isolation structure ISO 1  may be formed in a boundary region of contiguous or adjacent unit pixels, such that the device isolation structure ISO 1  may physically isolate the contiguous or adjacent unit pixels from each other. The device isolation structure ISO 1  may include a DTI structure and/or a combination structure of the DTI structure and the STI structure. For example, the substrate in which photoelectric conversion elements of the unit pixel are formed may include a first surface upon which light is incident and a second surface that faces the first surface and includes pixel transistors TX 1 , DX 1 , and SX 1 . The device isolation structure ISO 1  may include a Front Deep Trench Isolation (FDTI) structure in which a trench formed by etching the substrate to a predetermined depth in the direction from the second surface to the first surface is filled with an insulation material. 
     The unit pixel PX 1  may include active regions ACT 11  and ACT 12  that are defined by a device isolation structure ISO 21 . The active region ACT 11  may include a selection transistor SX 1 , a source follower transistor DX 1 , and a transfer transistor TX 1 . For example, the selection transistor SX 1 , the source follower transistor DX 1 , and the transfer transistor TX 1  may be formed to share the same active region ACT 11 . A tap region T 1  may be formed in the active region ACT 12 . The device isolation structure ISO 21  may be formed to have a shallow trench isolation (STI) structure in which a trench formed by etching the substrate to a predetermined depth is filled with an insulation material. 
     The selection transistor SX 1  may include a selection gate SG 1  formed over the active region ACT 11 . In the active region ACT 11 , the active region at one side of the selection gate SG 1  may be coupled to the output node OUT through conductive lines, and the active region at the other side of the selection gate SG 1  may be coupled to the source follower transistor DX 1 . The selection gate SG 1  may receive the row selection signal RSS through conductive lines. 
     The source follower transistor DX 1  may include a drive gate DG 1  formed over the active region ACT 11 . In the active region ACT 11 , the active region at one side of the drive gate DG 1  may be coupled to the power-supply voltage (VDD) node through conductive lines, and the active region at the other side of the drive gate DG 1  may be coupled to the selection transistor SX 1 . In this case, the selection transistor SX 1  and the source follower transistor DX 1  may not be electrically coupled to each other through conductive lines, and may be electrically coupled to each other by sharing the active region ACT 11 . The drive gate DG 1  may be coupled to the common floating diffusion (CFD) node through conductive lines. 
     The transfer transistor TX 1  may include a transfer gate TG 1  formed over the active region ACT 11 . The transfer transistor TX 1  may be a transistor in which the photoelectric conversion element PD 1  and the floating diffusion (FD) region FD 1  are used as source/drain regions. In this case, the transfer gate TG 1  may be buried to a predetermined depth in the substrate, and may be formed in a recess gate shape that forms a vertical channel region between the photoelectric conversion element PD 1  and the floating diffusion (FD) region FD 1  in response to the transmission signal TS 1 . 
     The transfer gate TG 1  may be formed in the active region ACT 11 . Thus, in the active region ACT 11 , the floating diffusion (FD) region FD 1  may be formed at one side of the transfer gate TG 1 , and the selection transistor SX 1  and the source follower transistor DX 1  may be coupled to the other side of the transfer gate TG 1 . For example, the active region ACT 11  may be formed in a T-shaped structure in which three branches are commonly coupled to each other and each of the three branches is bent. Each of the selection gate SG 1 , the drive gate DG 1 , and the transfer gate TG 1  may be formed at the center portion of each branch. In this case, in the active region ACT 11 , whereas a specific region in which the transfer transistor TX 1  is formed is physically coupled to another region in which the selection transistor SX 1  and the source follower transistor SX 1  are formed, through the active region ACT 11 , it should be noted that the specific region is not electrically coupled to the above another region. For example, impurities for forming the source/drain regions of the transistor may not be implanted into the center portion of the unit pixel PX 1  from among the active region ACT 11 . As a result, although the transfer gate TG 1  is turned on, the floating diffusion (FD) region FD 1  may not be electrically coupled to the selection transistor SX 1  or the source follower transistor DX 1 . 
     The transfer gate TG 1  may receive the transmission signal TS 1  through conductive lines. The floating diffusion (FD) region FD 1  may be coupled to the common floating diffusion (CFD) node through conductive lines. 
     The tap region T 1  may be used to apply a bias voltage to the well region of the substrate, and may be formed in the active region ACT 12  that is isolated from the active region ACT 11  by the device isolation structure ISO 21 . The active region ACT 12  may be formed in an island shape at the corner region of the unit pixel PX 1 . The tap region T 1  may be coupled to a bias voltage (BV) node through conductive lines. 
     The unit pixel PX 2  may be arranged contiguous or adjacent to the unit pixel PX 1  in the first direction. The unit pixel PX 2  may include active regions ACT 21  and ACT 22  defined by a device isolation structure ISO 22 . The active region ACT 21  may include a selection transistor SX 2 , a source follower transistor DX 2 , and a transfer transistor TX 2 . For example, the selection transistor SX 2 , the source follower transistor DX 2 , and the transfer transistor TX 2  may be formed to share the same active region ACT 21 . The active region ACT 22  may include a tap region T 2 . 
     The unit pixel PX 2  may include a layout structure that is symmetrical to the unit pixel PX 1  in the first direction with respect to a boundary region between the unit pixel PX 2  and the unit pixel PX 1 . For example, the active regions ACT 21  and ACT 22  of the unit pixel PX 2  may be respectively arranged symmetrical to the active regions ACT 11  and ACT 12  of the unit pixel PX 1  in the first direction. The gates SG 2 , DG 2 , and TG 2  of the unit pixel PX 2  may be formed over the active region ACT 21  in a manner that the gates SG 2 , DG 2 , and TG 2  of the unit pixel PX 2  are arranged symmetrical to the gates SG 1 , DG 1 , and TG 1  of the unit pixel PX 1  in the first direction. The transistors SX 2 , DX 2 , and TX 2  of the unit pixel PX 2  may be identical in structure to the transistors SX 1 , DX 1 , and TX 1  of the unit pixel PX 1 , and may also be identical in function to the transistors SX 1 , DX 1 , and TX 1  of the unit pixel PX 2 . 
     The tap region T 2  of the unit pixel PX 2  may be arranged symmetrical to the tap region T 1  of the unit pixel PX 1  in the first direction. The tap region T 2  may be formed in the active region ACT 22  that is isolated from the active region ACT 21  by the device isolation structure ISO 22 . The active region ACT 22  may be formed in the island shape at the corner region of the unit pixel PX 2 . The tap region T 2  may be coupled to the bias voltage (BV) node through conductive lines. 
     The unit pixel PX 3  may be arranged contiguous or adjacent to the unit pixel PX 1  in the second direction. The unit pixel PX 3  may include active regions ACT 31  and ACT 32  that are defined by a device isolation structure ISO 23 . The active region ACT 31  may include a transfer transistor TX 3 , a reset transistor RX, and a conversion gain transistor CGX. For example, the transfer transistor TX 3 , the reset transistor RX, and the conversion gain transistor CGX may be formed to share the same active region ACT 31 . The active region ACT 32  may include a tap region T 3 . 
     The transfer transistor TX 3  may include a transfer gate TG 3  formed in the active region ACT 31 . The transfer gate TG 3  may include a recess gate that forms a vertical channel region between the photoelectric conversion element PD 3  and the floating diffusion (FD) region FD 3  in response to a transmission signal TS 3 . 
     In the active region ACT 31 , the floating diffusion (FD) region FD 3  may be formed at one side of the transfer gate TG 3 , and the other side of the transfer gate TG 3  may be coupled to the reset transistor RX and the conversion gain transistor CGX. The transfer gate TG 3  may receive the transmission signal TS 3  through conductive lines. The floating diffusion (FD) region FD 3  may be coupled to the common floating diffusion (CFD) node through conductive lines. 
     The reset transistor RX may include a reset gate RG formed over the active region ACT 31 . In the active region ACT 31 , the active region at one side of the reset gate RG may be coupled to the power-supply voltage (VDD) node through conductive lines, and the active region at the other side of the reset gate RG may be coupled to the conversion gain transistor CGX and the conversion gain capacitor (C). In this case, the reset transistor RX may be coupled to the conversion gain transistor CGX by sharing the active region ACT 31  with the conversion gain transistor CGX, and may be coupled to the conversion gain capacitor (C) through conductive lines. The reset gate RG may receive the reset signal (RS) through conductive lines. 
     The conversion gain transistor CGX may include a conversion gate CG formed over the active region ACT 31 . In the active region ACT 31 , the floating diffusion (FD) region FD 3  may be formed at one side of the conversion gate CG, and the other side of the conversion gate CG may be coupled to the reset transistor RX and the conversion gate capacitor (C). In this case, the conversion gain transistor CGX may be coupled to the reset transistor RX by sharing the active region ACT 31  with the reset transistor RX, and may be coupled to the conversion gain capacitor (C) through conductive lines. The conversion gate CG may receive a gain control signal (GCS) through conductive lines. 
     An impurity region VSS coupled to the conversion gain capacitor (C) may be partially formed in the center portion of the unit pixel PX 3  from among the active region ACT 31 . For example, the impurity region VSS may be used to ground one terminal of the conversion gain capacitor (C). 
     The tap region T 3  may be arranged symmetrical to the tap region T 1  of the unit pixel PX 1  in the second direction. The tap region T 3  may be formed in the active region ACT 32  that is isolated from the active region ACT 31  by the device isolation structure ISO 23 . The active region ACT 32  may be formed in an island shape at the corner region of the unit pixel PX 3 . The tap region T 3  may be coupled to the bias voltage (BV) node through conductive lines. 
     The unit pixel PX 4  may be arranged contiguous or adjacent to the unit pixel PX 3  in the first direction, and may also be arranged contiguous or adjacent to the unit pixel PX 2  in the second direction. The unit pixel PX 4  may include active regions ACT 41  and ACT 42  defined by a device isolation structure ISO 24 . The active region ACT 41  may include a selection transistor SX 3 , a source follower transistor DX 3 , and a transfer transistor TX 4 . For example, the selection transistor SX 3 , the source follower transistor DX 3 , and the transfer transistor TX 4  may be formed to share the same active region ACT 41 . The active region ACT 42  may include a tap region T 4 . 
     The unit pixel PX 4  may include a layout structure that is symmetrical to the unit pixel PX 2  in the second direction with respect to a boundary region between the unit pixel PX 4  and the unit pixel PX 2 . For example, the active regions ACT 41  and ACT 42  may be arranged symmetrical to the active regions ACT 21  and ACT 22  of the unit pixel PX 2  in the second direction. The gates SG 3 , DG 3 , and TG 4  of the unit pixel PX 4  may be formed over the active region ACT 41  in a manner that the gates SG 3 , DG 3 , and TG 4  of the unit pixel PX 4  are arranged symmetrical to the gates SG 2 , DG 2 , and TG 2  of the unit pixel PX 2  in the second direction. That is, the transistors SX 3 , DX 3 , and TX 4  of the unit pixel PX 4  may be arranged symmetrical to the transistors SX 2 , DX 2 , and TX 2  of the unit pixel PX 2  in the second direction. The transistors SX 3 , DX 3 , and TX 4  of the unit pixel PX 4  may be identical in structure to the transistors SX 2 , DX 2 , and TX 2  of the unit pixel PX 2 , and may also be identical in function to the transistors SX 2 , DX 2 , and TX 2  of the unit pixel PX 2 . 
     The tap region T 4  may be arranged symmetrical to the tap region T 2  of the unit pixel PX 2  in the second direction. The tap region T 4  may be formed in the active region ACT 42  that is isolated from the active region ACT 41  by the device isolation structure ISO 24 . The active region ACT 42  may be formed in an island shape at the corner region of the unit pixel PX 4 . The tap region T 4  may be coupled to the bias voltage (BV) node through conductive lines. 
       FIG.  5    is a cross-sectional view illustrating an example of the unit pixel taken along the line A-A′ shown in  FIG.  4 C . In more detail,  FIG.  5    exemplarily illustrates a method for forming the conversion gain capacitor. 
     Referring to  FIG.  5   , the conversion gain capacitor (C) may be formed over the active region ACT 31  in the unit pixel PX 3 . For example, the conversion gain capacitor (C) may include a Metal-Insulator-Metal (MIM) capacitor in which an insulation material is formed between two metal plates MP 0  and MP 1  over the active region ACT 31 . 
     In this case, the metal plate MP 0  may correspond to a lower electrode of the conversion gain capacitor (C), and may be formed simultaneously with formation of conductive lines of the metal layer M 0 . The metal plate MP 1  may correspond to an upper electrode of the conversion gain capacitor (C), and may be formed simultaneously with formation of conductive lines of the metal layer M 1 . The metal plate MP 0  may be coupled to the impurity region VSS, and the metal plate MP 1  may be coupled to an impurity region CAP formed between the conversion gate CG and the reset gate RG. 
     Although  FIG.  5    illustrates an exemplary case in which the conversion gain capacitor (C) for minimizing the length of conductive lines through which the conversion gain capacitor (C) is coupled to the conversion gate transistor CGX is formed in the unit pixel PX 3  for convenience of description, other implementations are also possible. For example, the conversion gain capacitor (C) may be formed anywhere in a redundant space where the conductive lines are not formed within the pixel group (PXG). 
     Although  FIG.  5    exemplarily illustrates only one conversion gain capacitor (C) for convenience of description, the number of the conversion gain capacitor is not limited  1 . In some implementations, several conversion gain capacitors can also be coupled in parallel to each other. 
     As is apparent from the above description, the image sensing device based on some implementations of the disclosed technology can improve operational characteristics thereof. 
     The image sensing device based on some implementations of the disclosed technology can adjust a conversion gain without increasing the size of pixels within a shared structure in which a plurality of pixels shares floating diffusion (FD) regions. 
     Those skilled in the art will appreciate that the embodiments may be carried out in other specific ways than those set forth herein. The above embodiments are therefore to be construed in all aspects as illustrative and not restrictive. In addition, those skilled in the art will understand that claims that are not explicitly cited in each other in the appended claims may be presented in combination as an embodiment or included as a new claim by a subsequent amendment after the application is filed. 
     Although a number of illustrative embodiments have been described, it should be understood that modifications to the disclosed embodiments and other embodiments may be made based on the disclosure of this patent document.