Patent Publication Number: US-9844127-B2

Title: High voltage switching circuit

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation in part of U.S. patent application Ser. No. 14/935,859, filed Nov. 9, 2015, which is a continuation in part of U.S. patent application Ser. No. 14/622,879, filed Feb. 15, 2015, which is a continuation in part of U.S. patent application Ser. No. 14/616,884, filed Feb. 9, 2015, which is a continuation in part of U.S. patent application Ser. No. 14/594,262, filed Jan. 12, 2015, which in turn claims priority to U.S. Provisional Patent Application Ser. No. 61/925,974, filed Jan. 10, 2014. U.S. patent application Ser. No. 14/616,884, filed Feb. 9, 2015, also claims priority to U.S. Provisional Patent Application Ser. No. 61/940,139, filed Feb. 14, 2014. U.S. patent application Ser. No. 14/622,879, filed Feb. 15, 2015, also claims priority to U.S. Provisional Patent Application Ser. No. 61/940,165, filed Feb. 14, 2014. U.S. patent application Ser. No. 14/935,859, filed Nov. 9, 2015, also claims priority to U.S. Provisional Patent Application Ser. No. 62/077,753, filed Nov. 10, 2014. The present application also claims priority to U.S. Provisional Patent Application Ser. No. 62/077,750, filed Nov. 10, 2014. The disclosures of these references are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     PiN or NiP diodes are frequently used in RF applications as RF switches. PiN/NiP diodes have the characteristic that their conduction can be changed by applying appropriate bias voltage. When used as a switch, the diode can be turned ‘OFF’ by applying a reverse bias voltage across it that is of sufficient amplitude to prevent the RF signal from passing through the diode. Similarly, a forward bias can be applied across the diode to turn it ‘ON’ and make it conduct. The current generated by the forward bias determines the amount of conduction allowed. Since the reverse bias has to be of sufficient amplitude to block an RF signal, the reverse bias voltage is usually a high voltage, whereas the forward bias voltage is a low voltage. 
     For a typical PiN/NiP diode, the driver circuit for the bias voltage must be able to switch from reverse bias to forward bias in order to turn the PiN/NiP diode ‘ON’. There are several methods of driving the PiN/NiP diodes, which generally include the use of mechanical relays, MOSFETs, IGBTs, and the like, to alternatively apply one of the reverse bias and the forward bias to the PiN/NiP diode. For example in a driver circuit that uses MOSFETs, one for each of the reverse bias and the forward bias, the MOSFETs may be switched ‘on’ or ‘off’ by applying voltage between their respective gate and source connections. When the high voltage side MOSFET turns ‘on’, the source connection of this MOSFET needs to go to the high voltage potential. To keep the high voltage side MOSFET turned ‘on’, the gate of this MOSFET must go to a potential higher than the high voltage potential of the source plus the gate threshold voltage. This condition of maintaining the high voltage MOSFET turned ‘on’ requires the circuit driving the gate to float above the source, which can be a problem since it necessitates the use of complex circuitry to drive the high voltage side MOSFET. 
     Gate driver circuits become even more complex when used as part of PiN/NiP diode driver circuitry, in uses when the PiN/NiP diode needs to be turned ‘ON’ or ‘OFF’ for a considerable duration. Typically, gate driver circuits are designed for high frequency, high speed switching applications, where the MOSFETs are being switched at frequencies typically in the kHz range. When such circuits are used to drive PiN/NiP diodes, specialized circuitry must be used to enable their use for low frequency switching. For these reasons, PiN/NiP driver circuits are generally complex and expensive, and less complex and expensive PiN/NiP driver circuits are desirable. The same is true for other high voltage switching applications in which high speed switching is desirable alongside low frequency switching. 
     BRIEF SUMMARY 
     The present invention is directed toward a high voltage control circuit for an electronic switch, the control circuit being able to switch between a high voltage source and a low voltage source on a common output at high speed to control the state of the electronic switch. 
     In one aspect, the invention may be a switching circuit including: an electronic switch including one or more diodes for switching a capacitor within an electronic variable capacitor array (EVC); a first power switch receiving a common input signal and a first voltage input and configured to switchably connect the first voltage input to a common output in response to the common input signal; and a second power switch receiving the common input signal and a second voltage input and configured to switchably connect the second voltage input to the common output in response to the common input signal, wherein: the second voltage input is opposite in polarity to the first voltage input, and the first power switch and the second power switch are configured to asynchronously connect the first voltage input and the second voltage input, respectively, to the common output in response to the common input signal, the one or more diodes of the electronic switch being switched according to the first voltage input or the second voltage input being connected to the common output. 
     In another aspect, the invention may be a switching circuit including: an electronic switch including one or more diodes for switching a capacitor within an electronic variable capacitor array (EVC); a first power switch receiving a common input signal and a first voltage input and configured to switchably connect the first voltage input to a common output in response to the common input signal; and a second power switch receiving the common input signal and a second voltage input and configured to switchably connect the second voltage input to the common output in response to the common input signal, wherein: the second voltage input is about three orders of magnitude or more less than the first voltage input, and the first power switch and the second power switch are configured to asynchronously connect the first voltage input and the second voltage input, respectively, to the common output in response to the common input signal, the one or more diodes of the electronic switch being switched according to the first voltage input or the second voltage input being connected to the common output. 
     In yet another aspect, the invention may be an RF impedance matching network including: an RF input configured to operably couple to an RF source, the RF source having a fixed RF source impedance; an RF output configured to operably couple to a plasma chamber, the plasma chamber having a variable plasma impedance; a series electronically variable capacitor (“series EVC”) having a series variable capacitance and including a first plurality of capacitors, the series EVC electrically coupled in series between the RF input and the RF output; a shunt electronically variable capacitor (“shunt EVC”) having a shunt variable capacitance and including a second plurality of capacitors, the shunt EVC electrically coupled in parallel between a ground and one of the RF input and the RF output; an inductor electrically coupled in series between the RF input and the RF output; and a control circuit operatively coupled to the series EVC and to the shunt EVC to control the series variable capacitance and the shunt variable capacitance, wherein the control circuit is configured to: determine the variable plasma impedance of the plasma chamber; determine a series capacitance value for the series variable capacitance and a shunt capacitance value for the shunt variable capacitance; and generate a control signal to alter at least one of the series variable capacitance and the shunt variable capacitance to the series capacitance value and the shunt capacitance value, respectively, the control signal including a common input signal; wherein the alteration of the at least one of the series variable capacitance and the shunt variable capacitance is caused by at least one of a plurality of switching circuits, wherein each of the plurality of switching circuits is configured to switch one capacitor of the first plurality of capacitors and the second plurality of capacitors such that each of the first plurality of capacitors and the second plurality of capacitors is configured to be switched, each switching circuit including: an electronic switch electrically coupled to the one capacitor, the electronic switch including one or more diodes for switching the one capacitor of the first plurality of capacitors and the second plurality of capacitors; and a driver circuit having a common output electrically coupled to the electronic switch, the driver circuit including: a first power switch receiving the common input signal and a first voltage and configured to switchably provide the first voltage to the common output in response to the common input signal, the first power switch including a plurality of optocoupler phototransistors connected in series; and a second power switch receiving the common input signal and a second voltage and configured to switchably provide the second voltage to the common output in response to the common input signal, wherein: the second voltage is opposite in polarity to the first voltage; the first power switch and the second power switch are configured to asynchronously provide the first voltage and the second voltage, respectively, to the common output in response to the common input signal, the electronic switch being switched according to the first voltage or the second voltage being provided to the common output; and when the plurality of optocoupler phototransistors of the first power switch are switched off, a voltage drop from the first voltage to the second voltage occurs across the plurality of optocoupler phototransistors. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing summary, as well as the following detailed description of the exemplary embodiments, will be better understood when read in conjunction with the appended drawings. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities shown in the following figures: 
         FIG. 1  is a schematic representation of an embodiment of an RF impedance matching network using EVCs incorporated into a semiconductor wafer fabrication system; 
         FIG. 2A  illustrates an EVC for use in an RF impedance matching network; 
         FIG. 2B  is a schematic representation of an embodiment of an electronic circuit for providing a variable capacitance. 
         FIG. 2C  is a schematic representation of an embodiment of an EVC having three capacitor arrays. 
         FIG. 3A  illustrates a first switching circuit for use with an EVC, the switching circuit including a single diode as an electronic switch; 
         FIG. 3B  schematically illustrates a first multiple-diode arrangement which may be used as an electronic switch in the switching circuit of  FIG. 3A ; 
         FIG. 3C  schematically illustrates a second multiple-diode arrangement which may be used as an electronic switch in the switching circuit of  FIG. 3A ; 
         FIG. 4  is a graphical representation showing the timing capabilities of a driver circuit to switch to high voltage on the common output; 
         FIG. 5  is a graphical representation showing the timing capabilities of a driver circuit to switch to low voltage on the common output; 
         FIG. 6A  illustrates a second switching circuit for use with an EVC; 
         FIG. 6B  illustrates a third switching circuit for use with an EVC; 
         FIG. 7  is a graph showing the capacitance range of an EVC; 
         FIG. 8  is a graph showing the stable delivered power and the low reflected power that an impedance matching network including EVCs may provide during tuning; 
         FIG. 9  is a graphical representation showing the reflected RF power profile through an RF impedance matching network using EVCs and showing the voltage supplied to the driver circuit for the EVCs; and 
         FIG. 10  is a flow chart showing an embodiment of a process for matching an impedance. 
     
    
    
     DETAILED DESCRIPTION 
     The description of illustrative embodiments according to principles of the present invention is intended to be read in connection with the accompanying drawings, which are to be considered part of the entire written description. In the description of embodiments of the invention disclosed herein, where circuits are shown and described, one of skill in the art will recognize that for the sake of clarity, not all desirable or useful peripheral circuits and/or components are shown in the figures or described in the description. Moreover, the features and benefits of the invention are illustrated by reference to the disclosed embodiments. Accordingly, the invention expressly should not be limited to such disclosed embodiments illustrating some possible non-limiting combinations of features that may exist alone or in other combinations of features; the scope of the invention being defined by the claims appended hereto. 
     As used throughout, ranges are used as shorthand for describing each and every value that is within the range. Any value within the range can be selected as the terminus of the range. In addition, all references cited herein are hereby incorporated by reference in their entireties. In the event of a conflict in a definition in the present disclosure and that of a cited reference, the present disclosure controls. 
     Turning in detail to the drawings,  FIG. 1  illustrates an RF impedance matching network  11  having an RF input  13  connected to an RF source  15  and an RF output  17  connected to a plasma chamber  19 . An RF input sensor  21  is connected between the RF impedance matching network  11  and the RF source  15  so that the RF signal output from the RF source  15  may be monitored. An RF output sensor  49  is connected between the RF impedance matching network  11  and the plasma chamber  19  so that the RF output from the impedance matching network, and the plasma impedance presented by the plasma chamber  19 , may be monitored. Certain embodiments may include only one of the input sensor  21  and the output sensor  49 . The functioning of these sensors  21 ,  49  are described in greater detail below. 
     The RF impedance matching network  11  serves to help maximize the amount of RF power transferred from the RF source  15  to the plasma chamber  19  by matching the impedance at the RF input  13  to the fixed impedance of the RF source  15 . The matching network  11  can consist of a single module within a single housing designed for electrical connection to the RF source  15  and plasma chamber  19 . In other embodiments, the components of the matching network  11  can be located in different housings, some components can be outside of the housing, and/or some components can share a housing with a component outside the matching network. 
     As is known in the art, the plasma within a plasma chamber  19  typically undergoes certain fluctuations outside of operational control so that the impedance presented by the plasma chamber  19  is a variable impedance. Since the variable impedance of the plasma chamber  19  cannot be fully controlled, and an impedance matching network may be used to create an impedance match between the plasma chamber  19  and the RF source  15 . Moreover, the impedance of the RF source  15  may be fixed at a set value by the design of the particular RF source  15 . Although the fixed impedance of an RF source  15  may undergo minor fluctuations during use, due to, for example, temperature or other environmental variations, the impedance of the RF source  15  is still considered a fixed impedance for purposes of impedance matching because the fluctuations do not significantly vary the fixed impedance from the originally set impedance value. Other types of RF source  15  may be designed so that the impedance of the RF source  15  may be set at the time of, or during, use. The impedance of such types of RF sources  15  is still considered fixed because it may be controlled by a user (or at least controlled by a programmable controller) and the set value of the impedance may be known at any time during operation, thus making the set value effectively a fixed impedance. 
     The RF source  15  may be an RF generator of a type that is well-known in the art, and generates an RF signal at an appropriate frequency and power for the process performed within the plasma chamber  19 . The RF source  15  may be electrically connected to the RF input  13  of the RF impedance matching network  11  using a coaxial cable, which for impedance matching purposes would have the same fixed impedance as the RF source  15 . 
     The plasma chamber  19  includes a first electrode  23  and a second electrode  25 , and in processes that are well known in the art, the first and second electrodes  23 ,  25 , in conjunction with appropriate control systems (not shown) and the plasma in the plasma chamber, enable one or both of deposition of materials onto a substrate  27  and etching of materials from the substrate  27 . 
     The RF impedance matching network  11  includes a series variable capacitor  31 , a shunt variable capacitor  33 , and a series inductor  35  configured as one form an ‘L’ type matching network. In particular, the shunt variable capacitor  33  is shown shunting to ground  40  between the series variable capacitor  31  and the series inductor  35 , and one of skill in the art will recognize that the RF impedance matching network  11  may be configured with the shunt variable capacitor  33  shunting to ground  40  at the RF input  13  or at the RF output  17 . Alternatively, the RF impedance matching network  11  may be configured in other matching network configurations, such as a ‘T’ type configuration or a ‘Π’ type configuration. In certain embodiments, the variable capacitors and the switching circuit described below may be included in any configuration appropriate for an RF impedance matching network. 
     Each of the series variable capacitor  31  and the shunt variable capacitor  33  may be an electronic variable capacitor (EVC), as described in U.S. Pat. No. 7,251,121. The series variable capacitor  31  is coupled in series between the RF input  13  and the RF output  17  (which is also in parallel between the RF source  15  and the plasma chamber  19 ). The shunt variable capacitor  33  is coupled in parallel between the RF input  13  and ground  40 . In other configurations, the shunt variable capacitor  33  may be coupled in parallel between the RF output  19  and ground  40 . Other configurations may also be implemented without departing from the functionality of an RF matching network. 
     The series variable capacitor  31  is connected to a series RF choke and filter circuit  37  and to a series driver circuit  39 . Similarly, the shunt variable capacitor  33  is connected to a shunt RF choke and filter circuit  41  and to a shunt driver circuit  43 . Each of the series and shunt driver circuits  39 ,  43  are connected to a control circuit  45 , which is configured with an appropriate processor and/or signal generating circuitry to provide an input signal for controlling the series and shunt driver circuits  39 ,  43 . A power supply  47  is connected to each of the RF input sensor  21 , the series driver circuit  39 , the shunt driver circuit  43 , and the control circuit  45  to provide operational power, at the designed currents and voltages, to each of these components. The voltage levels provided by the power supply  47 , and thus the voltage levels employed by each of the RF input sensor  21 , the series driver circuit  39 , the shunt driver circuit  43 , and the control circuit  45  to perform the respective designated tasks, is a matter of design choice. In other embodiments, a variety of electronic components can be used to enable the control circuit  45  to send instructions to the variable capacitors. Further, while the driver circuit and RF choke and filter are shown as separate from the control circuit  45 , these components can also be considered as forming part of the control circuit  45 . 
     In the exemplified embodiment, the control circuit  45  includes a processor. The processor may be any type of properly programmed processing device, such as a computer or microprocessor, configured for executing computer program instructions (e.g., code). The processor may be embodied in computer and/or server hardware of any suitable type (e.g., desktop, laptop, notebook, tablets, cellular phones, etc.) and may include all the usual ancillary components necessary to form a functional data processing device including without limitation a bus, software and data storage such as volatile and non-volatile memory, input/output devices, graphical user interfaces (GUIs), removable data storage, and wired and/or wireless communication interface devices including Wi-Fi, Bluetooth, LAN, etc. The processor of the exemplified embodiment is configured with specific algorithms to enable matching network to perform the functions described herein. 
     With the combination of the series variable capacitor  31  and the shunt variable capacitor  33 , the combined impedances of the RF impedance matching network  11  and the plasma chamber  19  may be controlled, using the control circuit  45 , the series driver circuit  39 , the shunt driver circuit  43 , to match, or at least to substantially match, the fixed impedance of the RF source  15 . 
     The control circuit  45  is the brains of the RF impedance matching network  11 , as it receives multiple inputs, from sources such as the RF input sensor  21  and the series and shunt variable capacitors  31 ,  33 , makes the calculations necessary to determine changes to the series and shunt variable capacitors  31 ,  33 , and delivers commands to the series and shunt variable capacitors  31 ,  33  to create the impedance match. The control circuit  45  is of the type of control circuit that is commonly used in semiconductor fabrication processes, and therefore known to those of skill in the art. Any differences in the control circuit  45 , as compared to control circuits of the prior art, arise in programming differences to account for the speeds at which the RF impedance matching network  11  is able to perform switching of the variable capacitors  31 ,  33  and impedance matching. 
     Each of the series and shunt RF choke and filter circuits  37 ,  41  are configured so that DC signals may pass between the series and shunt driver circuits  39 ,  43  and the respective series and shunt variable capacitors  31 ,  33 , while at the same time the RF signal from the RF source  15  is blocked to prevent the RF signal from leaking into the outputs of the series and shunt driver circuits  39 ,  43  and the output of the control circuit  45 . The series and shunt RF choke and filter circuits  37 ,  41  are of a type known to those of skill in the art. 
     The series and shunt variable capacitors  31 ,  33  may each be an electronically variable capacitor  51  such as is depicted in  FIG. 2A . The electronically variable capacitor  51  includes a plurality of discrete capacitors  53 , each of which has an electrode on opposite sides thereof, such as is typical of discrete capacitors that are available on the market. 
     Each discrete capacitor  53  has its individual bottom electrode  55  electrically connected to a common bottom electrode  57 . The individual top electrode  59  of each discrete capacitor  53  is electrically connected to the individual top electrode  59  of adjacent discrete capacitors  53  through an electronic switch  61  that may be activated to electrically connect the adjacent top electrodes  59 . Thus, the individual top electrodes  59  of each discrete capacitor  53  may be electrically connected to the top electrodes  59  of one or more adjacent discrete capacitors  53 . The electronic switch  61  is selected and/or designed to be capable of switching the voltage and current of the RF signal. For example, the electronic switch  61  may be a PiN/NiP diode, or a circuit based on a PiN/NiP diode. In certain embodiments, a PiN/NiP diode may be directly coupled to a surface of the electronically variable capacitor  51 , with the surface being, by way of example, the substrate  60  on which the top electrode  59  is formed or the top electrode  59  itself. Alternatively, the electronic switch  61  may be any other type of appropriate switch, such as a micro electro mechanical (MEM) switch, a solid state relay, a field effect transistor, and the like. One embodiment of the electronic switch  61 , in combination with a driver circuit, is discussed in greater detail below. 
     In the configuration of the electronically variable capacitor  51  shown, each individual top electrode  59  may be electrically connected to between two to four adjacent top electrodes  59 , with each connection being independently regulated by a separate electronic switch  61 . The RF signal input  63  is electrically connected to one of the individual top electrodes  59 , and the RF signal output  65  is electrically connected to the common bottom electrode  57 . Thus, the electronic circuit through which the RF signal passes may include one, some, or all of the discrete capacitors  53  by a process of independently activating one or more of the electronic switches  61  coupled to adjacent ones of the individual top electrodes  59 . 
     In other embodiments, the electronically variable capacitor  51  may be configured to have any layout for the individual top electrodes  59 , to thereby increase or decrease the number of possible electrical connections between adjacent top electrodes  59 . In still other embodiments, the electronically variable capacitor  51  may have an integrated dielectric disposed between the bottom electrode  57  and a plurality of top electrodes  59 . 
     The electronic switch  61  that is used to connect pairs of adjacent top electrodes  59  may be a PiN/NiP diode-based switch, although other types of electronic switches may be used, such as a Micro Electro Mechanical (MEM) switch, a solid state relay, a field effect transistor, and the like. Each electronic switch  61  is switched by appropriate driver circuitry. For example, each of the series and  651  shunt driver circuits  39 ,  43  of  FIG. 1  may include several discrete driving circuits, with each discrete driving circuit configured to switch one of the electronic switches  61 . 
       FIG. 2B  shows an electronic circuit  650  for providing a variable capacitance according to one embodiment. The circuit  650  utilizes an EVC  651  that includes two capacitor arrays  651   a ,  651   b . The first capacitor array  651   a  has a first plurality of discrete capacitors, each having a first capacitance value. The second capacitor array  651   b  has a second plurality of discrete capacitors, each having a second capacitance value. The first capacitance value is different from the second capacitance value such that the EVC  651  can provide coarse and fine control of the capacitance produced by the EVC  651 . The first capacitor array and the second capacitor array are coupled in parallel between a signal input  613  and a signal output  630 . The capacitor arrays  651   a ,  651   b  and their discrete capacitors may be arranged in manner similar to that shown in  FIG. 2A , or in an alternative manner. 
     The first and second capacitance values can be any values sufficient to provide the desired overall capacitance values for the EVC  651 . In one embodiment, the second capacitance value is less than or equal to one-half (½) of the first capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (⅓) of the first capacitance value. In yet another embodiment, the second capacitance value is less than or equal to one-fourth (¼) of the first capacitance value. 
     The electronic circuit  650  further includes a control circuit  645 . The control circuit  645  is operably coupled to the first capacitor array  651   a  and to the second capacitor array  651   b  by a command input  629 , the command input  629  being operably coupled to the first capacitor array  651   a  and to the second capacitor array  651   b . In the exemplified embodiment, the command input  629  has a direct electrical connection to the capacitor arrays  651   a ,  651   b , though in other embodiments this connection can be indirect. The coupling of the control circuit  645  to the capacitor arrays  651   a ,  651   b  will be discussed in further detail below. 
     The control circuit  645  is configured to alter the variable capacitance of the EVC  651  by controlling on and off states of (a) each discrete capacitor of the first plurality of discrete capacitors and (b) each discrete capacitor of the second plurality of discrete capacitors. The control circuit  645  can have features similar to those described with respect to control circuit  45  of  FIG. 1 . For example, the control circuit  645  can receive inputs from the capacitor arrays  651   a ,  651   b , make calculations to determine changes to capacitor arrays  651   a ,  651   b , and delivers commands to the capacitor arrays  651   a ,  651   b  for altering the capacitance of the EVC  651 . 
     Similar to the EVC  51  discussed with respect to  FIG. 2A , the EVC  651  of  FIGS. 2B and 2C  can include a plurality of electronic switches. Each electronic switch can be configured to activate and deactivate one or more discrete capacitors. 
     As with the control circuit  45  of  FIG. 1 , the control circuit  645  can also be connected to a driver circuit  639  and an RF choke and filter circuit  637 . The control circuit  645 , driver circuit  639 , and RF choke and filter circuit  637  can have capabilities similar to those discussed with regard to  FIG. 1 . In the exemplified embodiment, the driver circuit  639  is operatively coupled between the control circuit  645  and the first and second capacitor arrays  651   a ,  651   b . The driver circuit  639  is configured to alter the variable capacitance based upon a control signal received from the control circuit  645 . The RF filter  637  is operatively coupled between the driver circuit  639  and the first and second capacitor arrays  651   a ,  651   b . In response to the control signal sent by the control unit  645 , the driver circuit  639  and RF filter  637  are configured to send a command signal to the command input  629 . The command signal is configured to alter the variable capacitance by instructing at least one of the electronic switches to activate or deactivate (a) at least one the discrete capacitors of the first plurality of discrete capacitors or (b) at least one of the discrete capacitors of the second plurality of discrete capacitors. 
     In the exemplified embodiment, the driver circuit  639  is configured to switch a high voltage source on or off in less than 15 μsec, the high voltage source controlling the electronic switches of each of the first and second capacitor arrays for purposes of altering the variable capacitance. The EVC  651 , however, can be switched by any of the means or speeds discussed in the present application. 
     The control circuit  645  can be configured to calculate coarse and fine capacitance values to be provided by the respective capacitor arrays  651   a ,  651   b . In the exemplified embodiment, the control circuit  645  is configured to calculate a coarse capacitance value to be provided by controlling the on and off states of the first capacitor array  651   a . Further, the control circuit is configured to calculate a fine capacitance value to be provided by controlling the on and off states of the second capacitor array  651   b . In other embodiments, the capacitor arrays  651   a ,  651   b  can provide alternative levels of capacitance. 
     In other embodiments, the EVC can utilize additional capacitor arrays.  FIG. 2C  shows an embodiment of an EVC  651 ′ in which a third capacitor array  651   c ′ is utilized to provide an additional degree of control over the variable capacitance. Like the EVC  651  of  FIG. 2B , the EVC  651 ′ of  FIG. 2C  includes an input  613 ′, an output  630 ′, and a command input  629 ′. Similar to the first and second capacitor arrays  651   a ′,  651   b ′, the third capacitor array  651   c ′ can have a third plurality of discrete capacitors. Each discrete capacitor of the third plurality of discrete capacitors can have a third capacitance value, this value being different from both the first capacitance value and the second capacitance value. The first capacitor array  651   a ′, second capacitor array  651   b ′, and third capacitor array  651   c ′ can be coupled in parallel between the signal input  613 ′ and the signal output  630 ′. A control circuit can be operably coupled to the third capacitor array  651   c ′, and be further configured to alter the variable capacitance by controlling on and off states of each discrete capacitor of the third plurality of discrete capacitors. Additional capacitor arrays enable an EVC to utilize several different capacitance values in controlling the overall EVC capacitance. In other embodiments, the third plurality of discrete capacitors can be replaced with a single discrete capacitor, or an alternative device for varying the overall capacitance of the EVC  651 ′. 
     The first, second, and third capacitance values of EVC  651 ′ can be any values sufficient to provide the desired overall capacitance values for EVC  651 ′. In one embodiment, the second capacitance value is less than or equal to one-half (½) of the first capacitance value, and the third capacitance value is less than or equal to one-half (½) of the second capacitance value. In another embodiment, the second capacitance value is less than or equal to one-third (⅓) of the first capacitance value, and the third capacitance value is less than or equal to one-third (⅓) of the second capacitance value. 
     The EVCs  651 ,  651 ′ of  FIGS. 2B and 2C , respectively, can be used in most systems requiring a varying capacitance. For example, the EVCs  651 ,  651 ′ can be used as a series EVC and/or a shunt EVC in a matching network, such as the RF matching network  11  discussed above with respect to  FIG. 1 . It is often desired that the differences between the capacitance values allow for both a sufficiently fine resolution of the overall capacitance of the circuit and a wide range of capacitance values to enable a better impedance match at the input of a RF matching network, and EVCs  651 ,  651 ′ allow this. 
     The EVCs  651 ,  651 ′ can also be used in a system or method for fabricating a semiconductor, a method for controlling a variable capacitance, and/or a method of controlling an RF impedance matching network. Such methods can include altering at least one of the series variable capacitance and the shunt variable capacitance to the determined series capacitance value and the shunt capacitance value, respectively. This altering can be accomplishing by controlling, for each of the series EVC and the shunt EVC, on and off states of each discrete capacitor of each plurality of discrete capacitors. In other embodiments, the EVC  651 ,  651 ′ and circuit  650  can be used in other methods and systems to provide a variable capacitance. 
       FIG. 3A  shows an embodiment of a high voltage switching circuit  101 , which is shown including a driver circuit  102  and a PiN/NiP diode  103  as an electronic switch. Although this switching circuit is shown with the driver circuit  102  integrated with the PiN/NiP diode  103 , one of skill in the art will understand that in practice, the PiN/NiP diode  103 , or any other type of electronic switch, may be integrated with the discrete capacitors in an EVC that is part of an RF impedance matching network, with the RF choke and filter circuit connected between the output of the driver circuit  102  and the PiN/NiP diode  103 . 
     The switching circuit  101  may be used for switching one of the discrete capacitors in an EVC between an ‘ON’ state and an ‘OFF’ state. One of skill in the art will recognize that the use of the PiN/NiP diode  103  in this embodiment is exemplary, and that the switching circuit  101  may include other types of circuitry that does not include the PiN/NiP diode  103 , yet still provides some of the same fast switching advantages of the PiN/NiP diode  103  for switching one of the discrete capacitors in an EVC. One of skill in the art will also recognize that certain components of the driver circuit  102  may be replaced with other components that perform the same essential function while also greater allowing variability in other circuit parameters (e.g., voltage range, current range, and the like). 
     This driver circuit  102  has an input  105  which receives a common input signal for controlling the voltage on the common output  107  that is connected to and drives the PiN/NiP diode  103 . The voltage on the common output  107  switches the PiN/NiP diode  103  between the ‘ON’ state and the ‘OFF’ state, thus also switching ‘ON’ and ‘OFF’ the discrete capacitor to which the PiN/NiP diode  103  is connected. The state of the discrete capacitor, in this exemplary embodiment, follows the state of the state of the PiN/NiP diode  103 , such that when the PiN/NiP diode  103  is ‘ON’, the discrete capacitor is also ‘ON’, and likewise, when the PiN/NiP diode  103  is ‘OFF’, the discrete capacitor is also ‘OFF’. Thus, statements herein about the state of the PiN/NiP diode  103  inherently describe the concomitant state of the connected discrete capacitor of the EVC. 
     The input  105  is connected to both a first power switch  111  and into a second power switch  113 . As depicted, the first power switch  111  is an optocoupler phototransistor  111 ′, and the second power switch  113  is a MOSFET  113 ′. A high voltage power supply  115  is connected to the first power switch  111 , providing a high voltage input which is to be switchably connected to the common output  107 . A low voltage power supply  117  is connected to the second power switch  113 , providing a low voltage input which is also to be switchably connected to the common output  107 . In the configuration of the driver circuit  102  shown, the low voltage power supply  117  may supply a low voltage input which is about −5 V. Such a low voltage, with a negative polarity, is sufficient to provide a forward bias for switching the PiN/NiP diode  103 . For other configurations of the driver circuit  102 , a higher or lower voltage input may be used, and the low voltage input may have a positive polarity, depending upon the configuration and the type of electronic switch being controlled. 
     The common input signal asynchronously controls the ‘on’ and ‘off’ states of the first power switch  111  and the second power switch  113 , such that when the first power switch  111  is in the ‘on’ state, the second power switch  113  is in the ‘off’ state, and similarly, when the first power switch is in the ‘off’ state, the second power switch  113  is in the ‘on’ state. In this manner, the common input signal controls the first power switch  111  and the second power switch  113  to asynchronously connect the high voltage input and the low voltage input to the common output for purposes of switching the PiN/NiP diode  103  between the ‘ON’ state and the ‘OFF’ state. 
     The input  105  may be configured to receive any type of appropriate control signal for the types of switches selected for the first power switch  111  and the second power switch  113 , which may be, for example, a +5 V control signal. Of course, to maintain simplicity of the overall driver circuit  102  and avoid incurring additional manufacturing costs, the first and second power switches  111 ,  113  are preferably selected so that they may directly receive the common input signal without requiring additional circuitry to filter or otherwise transform the common input signal. 
     The switching circuit  101  has design features which make it particularly useful for switching between a high voltage input and a low voltage input on the common output quickly and without the need to float the drive circuit, with respect to the high voltage input, or require use of special gate charging circuits due to isolation of the input signal from the high voltage input. Another advantage of the switching circuit  101  is that it provides the ability to switch the common output between voltage modes quickly, within the time frame of about 15 μsec or less. The simplicity of the switching circuit  101  should considerably reduce manufacturing costs, especially when compared to other circuits performing similar functionality, and it should also significantly reduce space requirements for the circuit, and again, especially as compared to other circuits performing similar functionality. These advantages make the switching circuit  101  particularly advantageous with the incorporated PiN/NiP diode  103 . 
     One of the ways in which these advances are realized is the first power switch  111  being a monolithic circuit element, such as the optocoupler phototransistor  111 ′. A monolithic element reduces both cost and space requirements. When an optocoupler phototransistor  111 ′ is used as the monolithic element, it can perform the necessary high voltage switching quickly, and it serves to isolate the high voltage input from the common input signal. Other, as yet unrealized advantages may also be present through the use of an optocoupler phototransistor  111 ′. 
     An optocoupler phototransistor  111 ′ serves well as the first power switch  111  for use in conjunction with the PiN/NiP diode  103  because of the low current requirements for the PiN/NiP diode  103  when in the ‘OFF’ state. During the ‘OFF’ state, the PiN/NiP diode  103  is reverse biased, and thus non-conducting, and as such the ‘OFF’ state current requirement falls within the current handling capability of most optocoupler phototransistors. In addition, in implementations when one or both of the voltage requirements or the current requirements exceed the specifications for a single optocoupler phototransistor, additional optocoupler phototransistors may be added into the circuit in series or in parallel to increase the voltage and/or current handling capabilities of the switching circuit. 
     To further highlight the advantages of the switching circuit  101 , its operation is detailed when the first power switch  111  is an optocoupler phototransistor  111 ′ and the second power switch  113  is an appropriate MOSFET  113 ′. In this example, the common input signal may be a 5 V control signal which is alternated between a first voltage level and a second voltage level that serve to switch both the optocoupler phototransistor  111 ′ and the MOSFET  113 ′ between ‘on’ and ‘off’ states. The manner of implementing a 5 V control signal is well known to those of skill in the art. 
     When the PiN/NiP diode  103  is to be turned to the ‘OFF’ state, the optocoupler phototransistor  111 ′ is turned to the ‘on’ state by applying the first voltage level from the common input signal across the photodiode inputs of the optocoupler phototransistor  111 ′. Turning the optocoupler phototransistor  111 ′ to the ‘on’ state connects high voltage input to the common output  107 , thereby reverse biasing the PiN/NiP diode  103 . At the same time, during this ‘OFF’ state of the PiN/NiP diode  103 , application of the first voltage level from the common input signal to the MOSFET  113 ′ places the MOSFET  113 ′ in the ‘off’ state, thereby disconnecting low voltage input from the common output  107 . 
     When the PiN/NiP diode  103  is to be turned to the ‘ON’ state, the optocoupler phototransistor  111 ′ is turned to the ‘off’ state by applying the second voltage level from the common input signal across the photodiode inputs of the optocoupler phototransistor  111 ′. Turning the optocoupler phototransistor  111 ′ to the ‘off’ state disconnects high voltage input from the common output  107 . At the same time, application of the second voltage level from the common input signal to the MOSFET  113 ′ places the MOSFET  113 ′ in the ‘on’ state, thereby connecting the low voltage input to the common output  107 . With the MOSFET  113 ′ in the ‘on’ state, and the optocoupler phototransistor  111 ′ to the ‘off’ state, only the low voltage input is connected to the common output  107 , so that the PiN/NiP diode  103  is forward biased and placed in the ‘ON’ state. 
     As indicated above, the optocoupler phototransistor  111 ′ provides the advantage that the common input signal is electrically isolated, through the internal optical switch (not shown) of the optocoupler phototransistor  111 ′, from the switched high voltage, thus alleviating the need to float the drive circuit (such as when a MOSFET is used to switch the high voltage). Use of the optocoupler phototransistor  111 ′ provides the additional advantage that the driver circuit  102  can quickly switch the common output  107  between the high voltage input and the low voltage input, with the switching occurring within the time frame of about 15 μsec or less. This fast switching time helps reduce switching loss, thereby reducing stress on the PiN/NiP diode itself, and introduces improvements in the semiconductor fabrication process by reducing the amount of time it takes for the RF impedance matching network to create an impedance match between the RF source and the plasma chamber. 
     The use of optocoupler phototransistors in the driver circuit  102  also provides advantages for switching a high voltage input in the range of 500 V-1000 V. Higher or lower voltages may also be switched with this driver circuit  102 . The high voltage input may therefore differ from the low voltage input by at least two or three orders of magnitude, or more. Advantageously, when the switching circuit  101  incorporates the PiN/NiP diode  103 , the high voltage input and the low voltage input may have opposite polarities. 
     In certain embodiments, the switching circuit  101  may include a multiple-diode arrangement, examples of which are shown in  FIGS. 3B-C . In such embodiments, the common output  107  of the driver circuit  102  is used to switch each diode in the multiple-diode arrangement. A switching circuit  101  including a multiple-diode arrangement is particularly advantageous when the RF signal output from the RF source approaches 1,000 V or more. For example, in order to switch an RF signal having a 1,000 V peak amplitude (which is the equivalent of a 2,000 V peak-to-peak amplitude), the high voltage power supply  115  of the driver circuit  102  may provide a high voltage input of −1,200 V. This voltage for the high voltage power supply  115  provides the needed voltage to reverse bias the PiN/NiP diode while also providing upper and lower margins for blocking the RF signal, each of the upper and lower margins being about 10% of the RF signal peak voltage. In such embodiments, the −1,200 V reverse bias voltage places the use of the PiN/NiP diode well within the typical operational range of a single PiN/NiP diode. In general, the operational range of a PiN/NiP diode may be defined by the breakdown voltage, such that the minimum breakdown voltage for PiN/NiP diode within the switching circuit  101  is defined by:
 
 BV   min   =V   UM   +V   LM +2× V   RF-Peak ,
 
where BV min  is the minimum required breakdown voltage of the PiN/NiP diode; V UM  is the desired upper margin provided in the high voltage input; V LM  is the desired lower margin provided in the high voltage input; and V RF-Peak  is the peak voltage of the RF signal. Since PiN/NiP diodes are generally available on the market having breakdown voltages of up to 4,000 V, when the peak voltage of the RF signal is less than about 1,800 V, a single PiN/NiP diode suffices as the electronic switch. However, in certain uses, the peak voltage of the RF signal output from the RF source may be in excess of 1,800 V, even approaching 5,000 V or more. In such instances, a single PiN/NiP diode does not suffice as the electronic switch. For example, in a use in which the peak voltage of the RF signal is about 4,600 V, the necessary breakdown voltage for a single PiN/NiP diode would be about 9,200 V. However, such a single PiN/NiP diode is not available on the market.
 
     In order to have an operating switching circuit in uses where the RF signal output from the RF source may be in excess of 1,800 V, multiple PiN/NiP diodes may be placed in series as part of the switching circuit  101 , with the common output  107  reverse biasing the series of PiN/NiP diodes as if the multiple PiN/NiP diodes were a single, monolithic PiN/NiP diode. In other words, the multiple PiN/NiP diodes connected in series may be directly substituted for the single PiN/NiP diode  103  of  FIG. 3A  without any further modification to the switching circuit  101 . By using multiple PiN/NiP diodes connected in series, the breakdown voltage of the multiple PiN/NiP diodes is higher than the breakdown voltage of a single PiN/NiP diode. Advantageously, multiple bare die PiN/NiP diodes may be formed into a stack of diodes for use in this manner 
     The PiN/NiP diode stack  121  shown in  FIG. 3B  may be used as part of the switching circuit  101 . The stack  121  includes several bare die PiN/NiP diodes  123  stacked together and directly coupled to a first conductive surface  125 . Each bare die PiN/NiP diode  123  includes a cathode end and an anode end, and within the stack  121  the cathode end of one bare die PiN/NiP diode  123  is directly coupled to the anode end of an adjacent bare die PiN/NiP diode  123 . The direct coupling between the adjacent bare die PiN/NiP diodes  123  may be achieved by soldering. The cathode or anode of the bottom bare die PiN/NiP diode  123  in the stack  121  serves as the cathode/anode for the entire stack  121 , and the cathode or anode of the top bare die PiN/NiP diode  123  in the stack  121  serves as the anode/cathode, respectively, for the entire stack  121 . The cathode/anode of the top bare die PiN/NiP diode  123  in the stack  121  is coupled by a strap or wirebond  127  to a second conductive surface  129 . In certain embodiments, the first conductive surface  125  may connect the stack  121  to the top electrode  59  of the EVC  51 , and the second conductive surface may connect the stack  121  to the driver circuit  103 . In certain embodiments, the first and second conductive surfaces  125 ,  129  may be contact pads on the substrate  60  of the EVC  51 . In certain other embodiments, the first conductive surface  125  may be the top electrode  59  of an EVC  51 . 
     The alternative embodiment of the PiN/NiP diode stack  131  shown in  FIG. 3C  may also be used as part of the switching circuit  101 . The stack  131  includes several bare die PiN/NiP diodes  133  stacked together and directly coupled to a first conductive surface  135 . Each bare die PiN/NiP diode  133  includes a cathode end and an anode end, and within the stack  131  the cathode end of one bare die PiN/NiP diode  133  is directly coupled to the anode end of an adjacent bare die PiN/NiP diode  133 . The direct coupling between the adjacent bare die PiN/NiP diodes  133  may again be achieved by soldering. The cathode or anode of the bottom bare die PiN/NiP diode  133  in the stack  131  serves as the cathode/anode for the entire stack  131 , and the cathode or anode of the top bare die PiN/NiP diode  133  in the stack  131  serves as the anode/cathode, respectively, for the entire stack  131 . The cathode/anode of the top bare die PiN/NiP diode  133  in the stack  131  is coupled by a strap or wirebond  137  to a second conductive surface  139 , to which another bare die PiN/NiP diode  141  is directly coupled. In certain embodiments, this other bare die PiN/NiP diode  141  may also be formed by a stack of bare die PiN/NiP diode diodes. The cathode/anode of the bare die PiN/NiP diode  141  that is not coupled to the second conductive surface  139  may be coupled to the driver circuit  103 . In certain embodiments, the first conductive surface  135  may connect the stack  131  to the top electrode  59  of the EVC  51 . In certain embodiments, the first and second conductive surfaces  135 ,  139  may be contact pads on the substrate  60  of the EVC  51 . In certain other embodiments, the first conductive surface  135  may be the top electrode  59  of an EVC  51 . 
     The ability of the driver circuit  102  of  FIG. 3A  to provide quick switching capabilities is exemplified by the graphs  151 ,  161  of  FIGS. 4 and 5 . The voltage curve  153  of  FIG. 4  shows the voltage on the common output  107  of the driver circuit  102  in order to switch the connected PiN/NiP diode  103  to the ‘OFF’ state. As is shown by the voltage curve  153 , the driver circuit  102  is capable of switching to connect the high voltage input, which in this example is approximately 1,000 V, to the common output  107  within about 11 μsec. The voltage curve  163  of  FIG. 5  shows the voltage on the common output  107  of the driver circuit  102  in order to switch the connected PiN/NiP diode  103  to the ‘ON’ state. As is shown by the voltage curve  163 , the driver circuit  102  is capable of switching to connect the low voltage input, which in this example is approximately −12 V, to the common output  107  within about 9 μsec. Thus, an RF impedance matching network which includes EVCs and switching circuits, as described above, shows significant improvements as compared to an RF impedance matching network which includes VVCs. 
     A switching circuit  201  which includes a driver circuit  202  having multiple optocoupler phototransistors  203  to increase the high voltage capabilities is shown in  FIG. 6A . Like the driver circuit  102  of  FIG. 3A , this driver circuit  202  includes an input  205  which receives a common input signal for controlling the voltage on the common output  207 . The switching circuit  201  includes a PiN/NiP diode  209  connected to the common output  207 , and the voltage on the common output  207  may be used to switch the PiN/NiP diode  209  between ‘ON’ state and ‘OFF’ states. The input  205  is connected to both a first power switch  211 , which includes the optocoupler phototransistors  203 , and to a second power switch  213 , which includes another optocoupler phototransistor  215  and a MOSFET  217 . Also like the switching circuit  101  of  FIG. 3A , the common output  207  of the driver circuit  202  may be used to switch a multiple-diode arrangement. In certain embodiments, the multiple-diode arrangement may be those depicted in  FIGS. 3B and 3C . In certain other embodiments, other types of multiple-diode arrangements may be used. 
     A high voltage power supply  219  is connected to the first power switch  211 , providing a high voltage input which is to be switchably connected to the common output  207 . A low voltage power supply  221  is connected to the second power switch  213 , providing a low voltage input which is also to be switchably connected to the common output  207 . 
     The optocoupler phototransistors  203  of the first power switch  211  are connected in series to each other in order to enable the first power switch  211  to switch higher voltages onto the common output  207  in the same manner as discussed above with a single optocoupler phototransistor. With appropriate selection of the optocoupler phototransistors  203 , the first power switch  211 , as shown, is capable of switching about 1000 V or more from the high voltage power supply  219  to the common output  207 . Additional optocoupler phototransistors may be added in series for the first power switch  211  to increase the high voltage switching capabilities. One of skill in the art will recognize that one or more optocoupler phototransistors may be connected in parallel to each other to increase the current load capabilities of the first power switch  211 . One optocoupler phototransistor may be used to switch low voltages through the design rating of the optocoupler phototransistor, with more optocoupler phototransistors being added to switch higher voltages. 
     The optocoupler phototransistor  215  of the second power switch  213  receives the common input signal, like the optocoupler phototransistors  203  of the first power switch  211 . This optocoupler phototransistor  215  is connected to the MOSFET  217  and places the MOSFET  217  in the ‘off’ state by connecting the source to the gate when the common input signal places the first power switch  211  in the ‘on’ state. In this configuration, when the MOSFET  217  is in the ‘on’ state, the second power switch  213  is also in the ‘on’ state, connecting the low power input to the common output  207 . Likewise, when the MOSFET  217  is in the ‘off’ state, the second power switch  213  is also in the ‘off’ state, so that the low power input is disconnected from the common output  207 . When the first power switch is in the ‘off’ state, optocoupler phototransistor  215  disconnects the gate from the source, so that the MOSFET  217  placed in the ‘on’ state by the gate being connected to the voltage V 2 , which is an appropriate voltage for controlling the gate of the MOSFET  217 . 
       FIG. 6B  shows a  FIG. 6B  shows a switching circuit  201 - 1  according to yet another embodiment of the invention. In this embodiment, the switching circuit  201 - 1  can utilize a cascode structure  218 - 1  to increase high voltage capabilities and increase switching speed while providing a simple control scheme. 
     In the exemplified embodiment, the switching circuit  201 - 1  includes a driver circuit  202 - 1  (sometimes referred to as a control circuit) and a PiN/NiP diode  209 - 1 . As in other embodiments, the driver circuit  202 - 1  includes an input  205 - 1  that receives a common input signal for controlling the voltage on the common output  207 - 1 . The PiN/NiP diode  209 - 1  is connected to the common output  207 - 1 , and the voltage on the common output  207 - 1  may be used to switch the PiN/NiP diode  209 - 1  between ‘ON’ and ‘OFF’ states. The common input  205 - 1  is connected to both a first power switch  211 - 1  and a second power switch  213 - 1 . 
     As with switching circuits  101  and  201 , switching circuit  201 - 1  may be used for switching one of the discrete capacitors in an EVC between an ‘ON’ state and an ‘OFF’ state. One of skill in the art will recognize that the use of the PiN/NiP diode  209 - 1  in this embodiment is exemplary, and that the switching circuit  201 - 1  may include other types of circuitry that does not include the PiN/NiP diode  209 - 1 , yet still provides some of the same advantages of the PiN/NiP diode  209 - 1  for switching one of the discrete capacitors in an EVC. One of skill in the art will also recognize that certain components of the driver circuit  202 - 1  may be replaced with other components that perform the same essential function while also greater allowing variability in other circuit parameters (e.g., voltage range, current range, and the like). One of skill in the art will also recognize that certain commonly known components have been omitted from discussion for clarity. 
     The PiN/NiP diode  209 - 1  is configured to receive an RF signal. In the exemplified embodiment, the RF signal is a high voltage RF signal (e.g., 1000 V peak amplitude, 3000 V peak amplitude, or 4000 V peak amplitude). Accordingly, a high voltage power supply (e.g., 1200 VDC for a 1000V peak amplitude RF signal) is required to reverse bias the PiN/NiP diode  209 - 1  and thereby turn the switching circuit  201 - 1  ‘OFF’. The high voltage of the high voltage power supply  219 - 1  can be two orders of magnitude or more greater than the low voltage of the low voltage power supply  221 - 1 . 
     The high voltage power supply  219 - 1  is connected to the first power switch  211 - 1 , providing a high voltage input which is to be switchably connected to the common output  207 - 1 . A low voltage power supply  221 - 1  is connected to the second power switch  213 - 1 , providing a low voltage input which is also to be switchably connected to the common output  207 - 1 . In the configuration of the driver circuit  202 - 1  shown, the low voltage power supply  221 - 1  may supply a low voltage input which is about −5 V. Such a low voltage, with a negative polarity, is sufficient to provide a forward bias for switching the PiN/NiP diode  209 - 1 . For other configurations of the driver circuit  202 - 1 , a higher or lower voltage input may be used, and the low voltage input may have a positive polarity, depending upon the configuration and the type of electronic switch being controlled. 
     The common input signal asynchronously controls the ‘on’ and ‘off’ states of the first power switch  211 - 1  and the second power switch  213 - 1 , such that when the first power switch  211 - 1  is in the ‘on’ state, the second power switch  213 - 1  is in the ‘off’ state, and similarly, when the first power switch  211 - 1  is in the ‘off’ state, the second power switch  213 - 1  is in the ‘on’ state. In this manner, the common input signal controls the first power switch  211 - 1  and the second power switch  213 - 1  to asynchronously connect the high voltage input and the low voltage input to the common output for purposes of switching the PiN/NiP diode  209 - 1  between the ‘ON’ state and the ‘OFF’ state. 
     The common input  205 - 1  may be configured to receive any type of appropriate control signal for the types of switches selected for the first power switch  211 - 1  and the second power switch  213 - 1 , which may be, for example, a +5 V control signal. 
     The switching circuit  201 - 1  has design features which make it particularly useful for switching between a high voltage input and a low voltage input on the common output quickly and without the need to float the drive circuit, with respect to the high voltage input, or require use of special gate charging circuits due to isolation of the input signal from the high voltage input. Another advantage of the switching circuit  201 - 1  is that it can provide the ability to switch the common output between voltage modes quickly, within the time frame of about 5 μsec or less. The simplicity of the switching circuit  201 - 1  should considerably reduce manufacturing costs, especially when compared to other circuits performing similar functionality, and it should also significantly reduce space requirements for the circuit, and again, especially as compared to other circuits performing similar functionality. These advantages make the switching circuit  201 - 1  particularly advantageous with the incorporated PiN/NiP diode  209 - 1 . 
     Similar to first power switches  111  and  211 , first power switch  211 - 1  can utilize at least one optocoupler phototransistor  203 - 1 . (The terms optocoupler and optocoupler phototransistor are used interchangeably herein.) In the exemplified embodiment, three optocoupler phototransistors  203 - 1  are utilized. The high voltage power supply  219 - 1  is connected to the collector port of the topmost optocoupler phototransistor  203 - 1 . Advantages of the use of optocoupler phototransistors in the first power switch are discussed above. The optocoupler phototransistors  203 - 1  of the first power switch  211 - 1  are connected in series to each other to enable the first power switch  211 - 1  to switch higher voltages onto the common output  207  in a manner similar to that discussed above. With appropriate selection of the optocoupler phototransistors  203 - 1 , the first power switch  211 - 1  is capable of switching 1000 V or more from the high voltage power supply  219 - 1  to the common output  207 - 1 . In other embodiments, additional optocoupler phototransistors may be added in series for the first power switch  211 - 1  to increase the high voltage switching capabilities. In yet other embodiments, fewer optocoupler phototransistors may be used, including use of a single optocoupler phototransistor. 
     The second power switch  213 - 1  can include a cascode structure  218 - 1  designed to increase the blocking voltage capability of the switching circuit  201 - 1 . The cascode structure  218 - 1  comprises multiple JFETs J 1 , J 2 , J 3  in series. These JFETs are connected in series with a low-voltage MOSFET M 2 . As a non-limiting example, the JFETs can be 1700 VDC JFETs, while and the MOSFET can be a 30V MOSFET. Specifically, the MOSFET M 2  is connected in series between the JFETs J 1 , J 2 , J 3  the and low voltage power supply. Between each of the JFET gates is a diode D 5 , D 6 . In other embodiments, a single JFET (rather than multiple JFETs) can be utilized for the cascode structure. A voltage source V 2  is connected to the gate of MOSFET M 2 . The voltage source V 2  is also connected to optocoupler phototransistor  215 - 1  (sometimes referred to as input optocoupler  215 - 1 ). When the optocoupler phototransistor  215 - 1  is turned on, the optocoupler phototransistor  215 - 1  can essentially short the gate of MOSFET M 2  to the source of MOSFET M 2 , turning MOSFET M 2  ‘off’. It is noted that the JFETs, MOSFETs, and optocoupler phototransistors can be replaced with other appropriate transistors or switches. Accordingly, a JFET such as one of JFETs J 1 , J 2 , J 3  can be referred to as a first transistor, and a MOSFET such as MOSFET M 2  can be referred to as a second transistor. 
     When the PiN/NiP diode  209 - 1  is in the ‘ON’ state, the first power switch  211 - 1  is in the ‘off’ state and the second power switch  213 - 1  is in the ‘on’ state. In the exemplified embodiment, the PiN/NiP diode  209 - 1  is put in the ‘ON’ state by applying a first common input signal of +0 V at the common input  205 - 1 . When the +0 V first common input signal is applied, input MOSFET M 3  (which can be another type of transistor, such as a BJT, and is sometimes referred to as the input transistor) is turned ‘off’. Consequently, no current flows through the photodiode inputs of the optocoupler phototransistors  203 - 1 ,  215 - 1 . Thus, the optocoupler transistors  203 - 1 ,  215 - 1  are turned ‘off’, common output  207 - 1  does not receive high voltage from the high voltage power supply  219 - 1 , and the diode  209 - 1  is not reverse biased. 
     At the same time, since optocoupler  215 - 1  is ‘off’, the gate of MOSFET M 2  can receive a voltage from voltage V 2 . R 1  and R 2  form a voltage divider for voltage V 2 , so that the gate of MOSFET M 2  receives a divided voltage from V 2 . In the exemplified embodiment, voltage V 2  is +5 V. The receipt of divided voltage V 2  at the gate of MOSFET M 2  causes MOSFET M 2  to switch ‘on’, which turns ‘on’ the first JFET J 1  since the gate of first JFET J 1  is then connected to its source. Next, the second JFET J 2  can start conducting and turn ‘on’, since the voltage on the gate of JFET J 5  is −VF (the forward voltage drop of diode D 6 ). The same process can be repeated for turning ‘on’ the remaining JFETs (third JFET J 3 ), until the voltage of the low voltage power supply  221 - 1  appears at the common output  207 - 1 , thereby providing the necessary biasing voltage to forward bias PiN/NiP diode  209 - 1 . 
     With the MOSFET M 2  in the ‘on’ state, and the optocoupler phototransistors  203 - 1 ,  215 - 1  in the ‘off’ state, only the low voltage input is connected to the common output  209 - 1 , so that the PiN/NiP diode  209 - 1  is forward biased and placed in the ‘ON’ state. When the optocouplers  203 - 1  of the first power switch are switched off, a voltage drop from the high voltage (of high voltage power supply  219 - 1 ) to the low voltage (of the low voltage power supply  221 - 1 ) occurs across the plurality of optocouplers. 
     By contrast, when the PiN/NiP diode  209 - 1  is in the ‘OFF’ state, the first power switch  211 - 1  is in the ‘on’ state and the second power switch  213 - 1  is in the ‘off’ state. In the exemplified embodiment, the PiN/NiP diode  209 - 1  is put in the ‘ON’ state by applying a second common input signal of +5 V at the common input  205 - 1 . When the +5 V first common input signal is applied, input MOSFET M 3  is turned ‘on’. Consequently, current flows through the photodiode inputs of the optocoupler phototransistors  203 - 1 ,  215 - 1 . Thus, the optocoupler transistors  203 - 1 ,  215 - 1  are turned ‘on’, and common output  207 - 1  receives high voltage from the high voltage power supply  219 - 1  to reverse bias diode  209 - 1 . 
     At the same time, the gate of MOSFET M 2  does not receive voltage V 2 , because optocoupler  215 - 1  is ‘on’, and therefore diverts voltage from the gate of MOSFET M 2 . Since the gate of MOSFET M 2  does not receive voltage V 2 , MOSFET M 2  switches ‘off’, which causes JFETS J 1 , J 2 , J 3  to turn off, thereby preventing the low voltage of the low voltage power supply  221 - 1  to appear at the common output  207 - 1 . 
     In this state, where the first power switch  211 - 1  is switched ‘on’ and the second power switch  213 - 1  is switched ‘off’, the high voltage power source can cause a large voltage across the MOSFET M 2  and the JFETs J 1 , J 2 , J 3 . One benefit of this structure is that the MOSFET M 2  can be a low-voltage MOSFET (e.g., 30 V), while the JFETs J 1 , J 2 , J 3  can be higher-voltage JFETS (e.g., 1700 V) for handling the high voltage from the high voltage power source. For different applications, the MOSFET M 2  can remain the same (in number and type), while the number or type of JFETs can be adjusted to handle the voltage requirements. Building a higher voltage switch can be achieved by simply adding one or more JFETs in series with the existing JFETs. There is no need to alter the switch configuration or how the switch needs to be driven. In this manner, the cascode structure increases the blocking voltage capability of the switching circuit. 
     With MOSFET M 2  in the ‘off’ state, and the optocoupler phototransistors  203 - 1 ,  215 - 1  in the ‘on’ state, only the high voltage input is connected to the common output  209 - 1 , so that the PiN/NiP diode  209 - 1  is reverse biased and placed in the ‘ON’ state. 
     The non-linear capacitance range of a single EVC switched by a switching circuit is shown in the graph  301  of  FIG. 7 . The single EVC used to generate the capacitance curve  303  has 24 discrete capacitors in the manner described above, with the top electrodes of the discrete capacitors being selectively connected to arrive at the capacitance curve  303  shown. As can be seen, the single EVC may provide a capacitance ranging from only one active discrete capacitor (i.e., none of the top electrodes of any of the discrete capacitors are connected, so that the RF signal only flows through a single discrete capacitor) to all 24 discrete capacitors being active (i.e., all the top electrodes of all the discrete capacitors are connected). Any number of the 24 discrete capacitors may be connected, so that the capacitance of the single EVC may range from a low capacitance, with one active discrete capacitor, to a high capacitance, with all 24 discrete capacitors active. The low capacitance and the high capacitance are a matter of design choice for the EVC. In the capacitance curve shown, the low capacitance is about 25 pF, while the high capacitance is over 1,600 pF. The number of discrete capacitance values that is achievable between the low capacitance and the high capacitance is also a matter of design choice for the EVC, as more or fewer discrete capacitors may be included as part of the EVC. The only significant constraints on an EVC are the mechanical limitations posed by specific implementations (e.g., size or weight restrictions on the EVC). Mechanical limitations aside, an EVC does not appear to have any issues for achieving high value capacitance (e.g., 200,000 pF or higher). 
     The stable delivered power of an RF impedance matching network incorporating EVCs is shown in the graph  331  of  FIG. 8 , which does not show or take into account switching capabilities of an EVC controlled by a switching circuit. There are three curves shown in this graph  331 : the output power  333  of the RF signal output from the RF source, which is about 500 V; the delivered power  335  to the plasma chamber; and the reflected power  337  back to the RF source. The output power  333  is a little over 500 V, while the reflected power  337  is in the range of about 10 V, so that the delivered power  335  to the plasma chamber is about 500 V. Not only is the delivered power  335  about 98% of the output power  333 , but the delivered power  335 , as can be seen, is substantially stable, without significant fluctuations. Both the percentage of delivered power  335  and the stability of the delivered power  335  represent significant improvements over an RF impedance matching network that is based on VVCs. 
     When the switching capabilities of an EVC controlled by a switching circuit, in the manner described above, are incorporated into an RF impedance matching network, high speed switching is enabled for the RF impedance matching network.  FIG. 9  is a graph  401  having voltage along the two y-axes and time along the x-axis to show the speed at which an RF impedance matching network using EVCs performs impedance matching (also referred to as the “match tune process”). A representation of an RF power profile  403  is shown, taken at the RF input of an RF impedance matching network, and the y-axis for the RF power profile has 50 mV divisions. A representation of the voltage of the common input signal  405  for driver circuits is also shown in the lower portion of the graph  401 , the common input signal  405  originating from the control circuit of the RF impedance matching network, and the y-axis for the common input signal  405  has 5 V divisions. The x-axis has 50 μsec divisions, with the 56 μsec point marked in approximately the middle of the graph and the t=0 point as marked. 
     Initially, a significant amount of reflected power  407  is shown in the left portion of the RF power profile  403  (i.e., before the 56 μsec mark). This reflected power represents inefficiencies in the RF power being transferred between the RF source and the plasma chamber as a result of an impedance mismatch. At about t=−36 μsec, the match tune process begins. The first approximately 50 μsec of the match tune process is consumed by measurements and calculations performed by the control circuit in order to determine new values for the variable capacitances of one or both of the series and shunt EVCs. 
       FIG. 10  is a flow chart showing a process  500  for matching an impedance according to one embodiment. Similar to the matching networks discussed above, the matching network  11  of the exemplified process includes the following (shown in  FIG. 1 ): an RF input  13  configured to operably couple to an RF source  15 , the RF source  15  having a fixed RF source impedance (e.g., 50 Ohms); an RF output  17  configured to operably couple to a plasma chamber  19 , the plasma chamber  19  having a variable plasma impedance; a series electronically variable capacitor (“series EVC”)  31  having a series variable capacitance, the series EVC  31  electrically coupled in series between the RF input  13  and the RF output  17 ; a shunt electronically variable capacitor (“shunt EVC”)  33  having a shunt variable capacitance, the shunt EVC  33  electrically coupled in parallel between a ground  40  and one of the RF input  13  and the RF output  17 ; an RF input sensor  21  operably coupled to the RF input  13 , the RF input sensor  21  configured to detect an RF input parameter at the RF input  13 ; an RF output sensor  49  operably coupled to the RF output, the RF output sensor configured to detect an RF output parameter; and a control circuit  45  operatively coupled to the series EVC  31  and to the shunt EVC  33  to control the series variable capacitance and the shunt variable capacitance. The steps of the exemplified process  500  can be carried out as part of the manufacture of a semiconductor, where a substrate  27  is placed in a plasma chamber  19  configured to deposit a material layer onto the substrate  27  or etch a material layer from the substrate  27 , and plasma is energized within the plasma chamber  19  by coupling RF power from the RF source  15  into the plasma chamber  19  to perform a deposition or etching. 
     In the first step of the exemplified process  500  of  FIG. 10 , an input impedance at the RF input  13  is determined (step  501 ). The input impedance is based on the RF input parameter detected by the RF input sensor  21  at the RF input  13 . The RF input sensor  21  can be any sensor configured to detect an RF input parameter at the RF input  13 . The input parameter can be any parameter measurable at the RF input  13 , including a voltage, a current, or a phase at the RF input  13 . In the exemplified embodiment, the RF input sensor  21  detects the voltage, current, and phase at the RF input  13  of the matching network  11 . Based on the RF input parameter detected by the RF input sensor  21 , the control circuit  45  determines the input impedance. 
     Next, the control circuit  45  determines the plasma impedance presented by the plasma chamber  19  (step  502 ). In one embodiment, the plasma impedance determination is based on the input impedance (determined in step  501 ), the capacitance of the series EVC  31 , and the capacitance of the shunt EVC  33 . In other embodiments, the plasma impedance determination can be made using the output sensor  49  operably coupled to the RF output, the RF output sensor  49  configured to detect an RF output parameter. The RF output parameter can be any parameter measurable at the RF output  17 , including a voltage, a current, or a phase at the RF output  17 . The RF output sensor  49  may detect the output parameter at the RF output  17  of the matching network  11 . Based on the RF output parameter detected by the RF output sensor  21 , the control circuit  45  may determine the plasma impedance. In yet other embodiments, the plasma impedance determination can be based on both the RF output parameter and the RF input parameter. 
     Once the variable impedance of the plasma chamber  19  is known, the control circuit  45  can determine the changes to make to the variable capacitances of one or both of the series and shunt EVCs  31 ,  33  for purposes of achieving an impedance match. Specifically, the control circuit  45  determines a first capacitance value for the series variable capacitance and a second capacitance value for the shunt variable capacitance (step  503 ). These values represent the new capacitance values for the series EVC  31  and shunt EVC  33  to enable an impedance match, or at least a substantial impedance match. In the exemplified embodiment, the determination of the first and second capacitance values is based on the variable plasma impedance (determined in step  502 ) and the fixed RF source impedance. 
     Once the first and second capacitance values are determined, the control circuit  45  generates a control signal to alter at least one of the series variable capacitance and the shunt variable capacitance to the first capacitance value and the second capacitance value, respectively (step  504 ). This is done at approximately t=−5 μsec. The control signal instructs the switching circuit  101  ( FIG. 3A ) to alter the variable capacitance of one or both of the series and shunt EVCs  31 ,  33 . 
     This alteration of the EVCs  31 ,  33  takes about 9-11 μsec total, as compared to about 1-2 sec of time for an RF matching network using VVCs. Once the switch to the different variable capacitances is complete, there is a period of latency as the additional discrete capacitors that make up the EVCs join the circuit and charge. This part of the match tune process takes about 55 μsec. Finally, the RF power profile  403  is shown decreasing, at just before t=56 μsec, from about 380 mV peak-to-peak to about 100 mV peak-to-peak. This decrease in the RF power profile  403  represents the decrease in the reflected power  407 , and it takes place over a time period of about 10 μsec, at which point the match tune process is considered complete. 
     The altering of the series variable capacitance and the shunt variable capacitance can comprise sending a control signal to the series driver circuit  39  and the shunt driver circuit  43  to control the series variable capacitance and the shunt variable capacitance, respectively, where the series driver circuit  39  is operatively coupled to the series EVC  31 , and the shunt driver circuit  43  is operatively coupled to the shunt EVC  43 . When the EVCs  31 ,  33  are switched to their desired capacitance values, the input impedance may match the fixed RF source impedance (e.g., 50 Ohms), thus resulting in an impedance match. If, due to fluctuations in the plasma impedance, a sufficient impedance match does not result, the process of  500  may be repeated one or more times to achieve an impedance match, or at least a substantial impedance match. 
     Using an RF matching network  11 , such as that shown in  FIG. 1 , the input impedance can be represented as follows: 
               Z     i   ⁢           ⁢   n       =         (       Z   P     +     Z   L     +     Z   series       )     ⁢     Z   shunt           Z   P     +     Z   L     +     Z   series     +     Z   shunt               
where Z in  is the input impedance, Z P  is the plasma impedance, Z L  is the series inductor impedance, Z series  is the series EVC impedance, and Z shunt  is the shunt EVC impedance. In the exemplified embodiment, the input impedance (Z in ) is determined using the RF input sensor  21 . The EVC impedances (Z series  and Z shunt ) are known at any given time by the control circuitry, since the control circuitry is used to command the various discrete capacitors of each of the series and shunt EVCs to turn ON or OFF. Further, the series inductor impedance (Z L ) is a fixed value. Thus, the system can use these values to solve for the plasma impedance (Z P ).
 
     Based on this determined plasma impedance (Z P ) and the known desired input impedance (Z′ in ) (which is typically 50 Ohms), and the known series inductor impedance (Z L ), the system can determine a new series EVC impedance (Z′ series ) and shunt EVC impedance (Z′ shunt ). 
     
       
         
           
             
               Z 
               
                 i 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 n 
               
               ′ 
             
             = 
             
               
                 
                   ( 
                   
                     
                       Z 
                       P 
                     
                     + 
                     
                       Z 
                       L 
                     
                     + 
                     
                       Z 
                       series 
                       ′ 
                     
                   
                   ) 
                 
                 ⁢ 
                 
                   Z 
                   shunt 
                   ′ 
                 
               
               
                 
                   Z 
                   P 
                 
                 + 
                 
                   Z 
                   L 
                 
                 + 
                 
                   Z 
                   series 
                   ′ 
                 
                 + 
                 
                   Z 
                   shunt 
                   ′ 
                 
               
             
           
         
       
     
     Based on the newly calculated series EVC variable impedance (Z′ series ) and shunt EVC variable impedance (Z′ shunt ), the system can then determine the new capacitance value (first capacitance value) for the series variable capacitance and a new capacitance value (second capacitance value) for the shunt variable capacitance. When these new capacitance values are used with the series EVC  31  and the shunt EVC  33 , respectively, an impedance match may be accomplished. 
     This exemplified method of computing the desired first and second capacitance values and reaching those values in one step is significantly faster than moving the two EVCs step-by-step to bring either the error signals to zero, or to bring the reflected power/reflection coefficient to a minimum. In semiconductor plasma processing, where a faster tuning scheme is desired, this approach provides a significant improvement in matching network tune speed. 
     From the beginning of the match tune process, which starts with the control circuit determining the variable impedance of the plasma chamber and determining the series and shunt variable capacitances, to the end of the match tune process, when the RF power reflected back toward the RF source decreases, the entire match tune process of the RF impedance matching network using EVCs has an elapsed time of approximately 110 μsec, or on the order of about 150 μsec or less. This short elapsed time period for a single iteration of the match tune process represents a significant increase over a VVC matching network. Moreover, because of this short elapsed time period for a single iteration of the match tune process, the RF impedance matching network using EVCs may iteratively perform the match tune process, repeating the two determining steps and the generating another control signal for further alterations to the variable capacitances of one or both of the electronically variable capacitors. By iteratively repeating the match tune process, it is anticipated that a better impedance match may be created within about 2-4 iterations of the match tune process. Moreover, depending upon the time it takes for each repetition of the match tune process, it is anticipated that 3-4 iterations may be performed in 500 μsec or less. Given the 1-2 sec match time for a single iteration of a match tune process for RF impedance matching networks using VVCs, this ability to perform multiple iterations in a fraction of the time represents a significant advantage for RF impedance matching networks using EVCs. 
     Those of skill in the art will recognize that several factors may contribute to the sub-millisecond elapsed time of the impedance matching process for an RF impedance matching network using EVCs. Such factors may include the power of the RF signal, the configuration and design of the EVCs, the type of matching network being used, and the type and configuration of the driver circuit being used. Other factors not listed may also contribute to the overall elapsed time of the impedance matching process. Thus, it is expected that the entire match tune process for an RF impedance matching network having EVCs should take no more than about 500 μsec to complete from the beginning of the process (i.e., measuring by the control circuit and calculating adjustments needed to create the impedance match) to the end of the process (the point in time when the efficiency of RF power coupled into the plasma chamber is increased due to an impedance match and a reduction of the reflected power). Even at a match tune process on the order of 500 μsec, this process time still represents a significant improvement over RF impedance matching networks using VVCs. 
     Table 1 presents data showing a comparison between operational parameters of one example of an EVC versus one example of a VVC. As can be seen, EVCs present several advantages, in addition to enabling fast switching for an RF impedance matching network: 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                 Typical 1000 pF 
               
               
                 Parameter 
                 EVC 
                 Vacuum Capacitors 
               
               
                   
               
             
            
               
                 Capacitance 
                 20 pF~1400 pF 
                  15 pF~1000 pF 
               
               
                 Reliability 
                 High 
                 Low 
               
            
           
           
               
               
               
               
            
               
                 Response Time 
                 ~500 
                 μsec 
                 1 s~2 s 
               
            
           
           
               
               
               
               
               
            
               
                 ESR 
                 ~13 
                 mW 
                 ~20 
                 mW 
               
               
                 Voltage 
                 7 
                 kV 
                 5 
                 kV 
               
               
                 Current Handling Capability 
                 216 
                 A rms 
                 80 
                 A rms 
               
               
                 Volume 
                 4.5 
                 in 3   
                 75 
                 in 3   
               
               
                   
               
            
           
         
       
     
     As is seen, in addition to the fast switching capabilities made possible by the EVC, EVCs also introduce a reliability advantage, a current handling advantage, and a size advantage. Additional advantages of the RF impedance matching network using EVCs and/or the switching circuit itself for the EVCs include:
         The disclosed RF impedance matching network does not include any moving parts, so the likelihood of a mechanical failure reduced to that of other entirely electrical circuits which may be used as part of the semiconductor fabrication process. For example, the typical EVC may be formed from a rugged ceramic substrate with copper metallization to form the discrete capacitors. The elimination of moving parts also increases the resistance to breakdown due to thermal fluctuations during use.   The EVC has a compact size as compared to a VVC, so that the reduced weight and volume may save valuable space within a fabrication facility.   The design of the EVC introduces an increased ability to customize the RF matching network for specific design needs of a particular application. EVCs may be configured with custom capacitance ranges, one example of which is a non-linear capacitance range. Such custom capacitance ranges can provide better impedance matching for a wider range of processes. As another example, a custom capacitance range may provide more resolution in certain areas of impedance matching. A custom capacitance range may also enable generation of higher ignition voltages for easier plasma strikes.   The short match tune process (˜500 μsec or less) allows the RF impedance matching network to better keep up with plasma changes within the fabrication process, thereby increasing plasma stability and resulting in more controlled power to the fabrication process.   The use of EVCs, which are digitally controlled, non-mechanical devices, in an RF impedance matching network provides greater opportunity to fine tune control algorithms through programming.   EVCs exhibit superior low frequency (kHz) performance as compared to VVCs.       

     While the invention has been described with respect to specific examples including presently preferred modes of carrying out the invention, those skilled in the art will appreciate that there are numerous variations and permutations of the above described systems and techniques. It is to be understood that other embodiments may be utilized and structural and functional modifications may be made without departing from the scope of the present invention. Thus, the spirit and scope of the invention should be construed broadly as set forth in the appended claims.