Patent Publication Number: US-9899470-B2

Title: Method for forming a power semiconductor device and a power semiconductor device

Description:
TECHNICAL FIELD 
     Embodiments of the present invention relate to methods for forming a power semiconductor device, in particular to methods for forming power semiconductor switches, and to power semiconductor devices. 
     BACKGROUND 
     Particularly with regard to power devices capable of switching large currents and/or operating at higher voltages, both high breakdown voltages U bd  and low on-resistance R on  are often desired. 
     Power semiconductor switches often handle voltages differences of more than several 10 V or even several 100 V within the same semiconductor piece. To avoid breakdown during blocking mode, drift zones are used. The dimension of the drift zones depend on the breakdown voltage U bd , which has to be blocked, but also on the doping level of the semiconductor material. For lateral devices, the size of the drift zone mainly determines the size of the chip and has, thus, a high influence on costs. To keep wafer cost low, the doping level of the wafer material should be low too. Wafer material doped at a level of about 10 15 /cm 3  enables small drift zone dimensions, while still having enough doping concentration too keep also R on  low enough to enable a decent ON-state of the switch. 
     Small chip size may also be achieved, if the drift zone is arranged in a vertical structure. However, at the edge of such structures again high voltage differences to neighboring structures may occur. Effective isolation between regions of high voltage differences is often required. Such isolations may be realized with oxide filled trenches, so called Shallow Trench Isolations or Deep Trench Isolations. However, a leakage path may occur at the semiconductor-oxide interface. This may hinder the desired blocking behavior. 
     For these and other reasons there is a need for the present invention. 
     SUMMARY 
     According to an embodiment of a method of forming a power semiconductor device, the method includes providing a semiconductor layer of a first conductivity type extending to a first side and comprising a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the semiconductor layer, and forming a deep trench isolation. Forming the deep trench isolation includes forming a trench which extends from the first side into the semiconductor layer and comprises, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall, the compensation semiconductor region including a second doping concentration of the first dopants which is higher than the first doping concentration, and filling the trench with a dielectric material. An amount of the first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type, which are trapped in the trench, is at least partly compensated next to the wall. 
     According to an embodiment of a method of forming a power semiconductor device, the method includes providing a wafer including a first side and a semiconductor layer of a first conductivity type, etching a trench from the first side into the semiconductor layer so that the trench has in a vertical cross-section perpendicular to the first side two sidewalls, forming a compensation semiconductor region of the first conductivity type extending along the two sidewalls, and filling the trench with a dielectric material. The method is performed so that, in the vertical cross-section, an amount of dopants of the first conductivity type in the compensation semiconductor region times a number of majority charge carriers per unit, which are provided by the dopants of the first conductivity type in the compensation semiconductor region, is at least about an absolute value of a non-vanishing total charge of trapped charges in the trench divided by the elementary charge, wherein the total charge is of the same electric charge type as the majority charge carriers. 
     According to an embodiment of a power semiconductor device, the power semiconductor device includes a semiconductor body including a first side and a semiconductor layer extending to the first side and comprising first dopants providing majority charge carriers of a first electric charge type in the semiconductor layer. At least one deep trench extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall and a dielectric region comprising fixed charges of the first electric charge type. A compensation semiconductor region is arranged at the wall and has a higher concentration of first dopants than the semiconductor layer. The dielectric region extends along the wall and/or along the compensation semiconductor region. An amount of the first dopants in the compensation semiconductor region is such that a field-effect of the fixed charges is, next to the wall, at least partly compensated. 
     Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The components in the figures are not necessarily to scale, instead emphasis being placed upon illustrating the principles of the invention. Moreover, in the figures, like reference numerals designate corresponding parts. In the drawings: 
         FIGS. 1 to 7  illustrate method steps of a method for forming a power semiconductor device on wafer level in respective vertical cross-sections through a wafer according to embodiments; 
         FIG. 8  illustrates a vertical cross-section through a power semiconductor device according to an embodiment; 
         FIG. 9  illustrates a vertical cross-section through a power semiconductor device according to an embodiment; 
         FIGS. 10 to 13  illustrate method steps of a method for forming a power semiconductor device on wafer level in respective vertical cross-sections through a wafer according to embodiments; 
         FIGS. 14 to 17  illustrate method steps of a method for forming a power semiconductor device on wafer level in respective vertical cross-sections through a wafer according to further embodiments; and 
         FIGS. 18 to 21  illustrate method steps of a method for forming a power semiconductor device on wafer level in respective vertical cross-sections through a wafer according to yet further embodiments; and 
         FIGS. 22 to 24  illustrate method steps of a method for forming a power semiconductor device on wafer level in respective vertical cross-sections through a wafer according to further embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
     Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only. For clarity, the same elements or manufacturing steps have been designated by the same references in the different drawings if not stated otherwise. 
     The term “horizontal” as used in this specification intends to describe an orientation substantially parallel to a first or main horizontal side of a semiconductor substrate or body. This can be for instance the surface of a wafer or a die. 
     The term “vertical” as used in this specification intends to describe an orientation which is substantially arranged perpendicular to the first side, i.e. parallel to the normal direction of the first side of the semiconductor substrate or body. 
     In this specification, p-doped is referred to as first conductivity type while n-doped is referred to as second conductivity type. The majority charge carriers of a p-doped semiconductor material are holes, i.e. positive charge carriers also referred to as charge carriers of the first electric charge type. Alternatively, the semiconductor devices can be formed with opposite doping relations so that the first conductivity type can be n-doped and the second conductivity type can be p-doped. Furthermore, some Figures illustrate relative doping concentrations by indicating “−” or “+” next to the doping type. For example, “p-” means a doping concentration which is less than the doping concentration of an “p”-doping region while an “p+”-doping region has a larger doping concentration than the “p”-doping region. However, indicating the relative doping concentration does not mean that doping regions of the same relative doping concentration have to have the same absolute doping concentration unless otherwise stated. For example, two different p+-doping regions can have different absolute doping concentrations. The same applies, for example, to an n+-doping and a p+-doping region. 
     Specific embodiments described in this specification pertain to, without being limited thereto, manufacturing power semiconductor devices on wafer level and the manufactured power semiconductor devices. 
     When referring to semiconductor devices, at least two-terminal devices are meant, an example is a diode. Semiconductor devices can also be three-terminal devices such as a field-effect transistors (FETs), in particular fin field-effect transistors (FinFETs), insulated gate bipolar transistors (IGBTs), junction field effect transistors (JFETs), and thyristors to name a few. The semiconductor devices can also include more than three terminals. Further, the semiconductor devices can also include several two-terminal devices and/or three-terminal devices on a single chip. 
     The term “power semiconductor device” as used in this specification intends to describe a semiconductor device on a single chip with high voltage and/or high current switching capabilities. In other words, power semiconductor devices are intended for high current, typically in the ampere range. Within this specification the terms “power semiconductor device” and “power semiconductor component” are used synonymously. 
     A power semiconductor device may have an active area with a plurality of FET-cells (field-effect-transistor-cells such as MOSFET-cells, IGBT-cells and reverse conducting IGBT-cells) for controlling a load current between two load metallization. Furthermore, the power semiconductor device may have a peripheral area at least partially surrounding an active area when seen from above and typically having at least one edge-termination structure. 
     The term “edge-termination structure” as used in this specification intends to describe a structure that is configured to provide in a blocking mode a transition region in which the high electric fields around an active area of the semiconductor device change gradually to the potential at or close to the edge of the device and/or between a reference potential such as ground and a high voltage e. g. at the edge and/or backside of the semiconductor device. The edge-termination structure may, for example, lower the field intensity around a termination region of a rectifying junction by spreading the electric field lines across the termination region. 
     The term “field-effect” as used in this specification intends to describe the modulation of the electrical conductivity of a semiconductor material or region by the application of an external electric field. The external electric field may be caused by external electric charges arranged next to the semiconductor material or region. When the external electric charges are of the same charge type as the majority charge carriers of the semiconductor material or region, e.g, positive charges for a p-type the semiconductor material or region, a depletion layer or even a conductive “inversion channel” may be formed in the semiconductor material or region due to the “field-effect”. 
     In the context of the present specification, the term “gate electrode” intends to describe an electrode which is situated next to, and configured to form and/or control a channel region due to the field-effect. The term “gate electrode” shall embrace an electrode or conductive region which is situated next to, and insulated from the body region by an insulating region forming a gate dielectric region and configured to form and/or control a channel region through the body region by charging to an appropriate voltage. 
     In the context of the present specification, the terms “in ohmic contact”, in resistive electric contact” and “in resistive electric connection” intend to describe that there is an ohmic current path between respective elements or portions of a semiconductor device at least when no voltages or only low testing voltages are applied to and/or across the semiconductor device. Likewise, the terms in low ohmic contact, “in low resistive electric contact” and “in low resistive electric connection” intend to describe that there is a low resistive ohmic current path between respective elements or portions of a semiconductor device at least when no voltages or only low testing voltages are applied to and/or across the semiconductor device. Within this specification the terms “in low ohmic contact”, “in low resistive electric contact”, and “in low resistive electric connection” are used synonymously. 
     In the following, embodiments pertaining to semiconductor devices and manufacturing methods for forming semiconductor devices are explained mainly with reference to silicon (Si) semiconductor devices having a monocrystalline Si semiconductor body. Accordingly, a semiconductor region or layer is typically a monocrystalline Si-region or Si-layer if not stated otherwise. 
     It should, however, be understood that the semiconductor body can be made of any semiconductor material suitable for manufacturing a semiconductor device. For power semiconductor applications currently mainly Si, SiC, GaAs and GaN materials are used. If the semiconductor body is made of a wide band-gap material, i.e. of a semiconductor material with a band-gap of at least about two electron volts such as SiC or GaN and having a high breakdown field strength and high critical avalanche field strength, respectively, the doping of the respective semiconductor regions can be chosen higher which reduces the on-state resistance R on . 
       FIG. 1  to  FIG. 7  illustrate processes of a method for forming a power semiconductor device  100 ,  100 ′ on wafer-level. 
     In a first process, a wafer  40  having a p-doped silicon semiconductor layer  1  may be provided. Accordingly, the semiconductor layer  1  is made of silicon doped with dopants providing holes (positive electric charges) as majority charge carriers. In the following, these dopants are also referred to as first dopants. 
     The semiconductor layer  1  may e.g. be slightly doped with boron acting as acceptor in silicon and providing one hole per unit in silicon, respectively. 
     Typically the doping concentration of the dopants is in a range from about 10 15 /cm 3  to about 10 15 /cm 3 , more typically in a range from about 10 15 /cm 3  to about 2*10 15 /cm 3  for dopants providing one positive charge carrier per unit. 
     The semiconductor layer  1  may extend between and/or even form a first side  101  and a second side  102  opposite the first side  101 . 
     Thereafter, a trench  50  extending from the first side  101  into the semiconductor layer  1  is formed. 
     As illustrated in  FIG. 1 , the trench  50  may be etched from the first side  101  using a mask  5  formed on the first side  101 . Mask  5  is typically a photo lithographically structured hardmask, for example a structured silicon oxide mask. 
       FIG. 1  may correspond to a section through one power semiconductor device  100  of a plurality of power semiconductor devices  100  to be manufactured in parallel on wafer level or even to a section of a part of such a device  100 . 
     As illustrated in  FIG. 1 , two or more trenches  50  may be formed in the shown vertical section of the power semiconductor device  100  to be manufactured. Accordingly, one or more mesas  60  may be formed. 
     In the vertical section, each trench  50  may have two typically straight sidewalls  51  and a typically straight bottom wall  52  forming the respective wall  51 ,  52  of the trench  50 . In the following the sidewalls  51  and the bottom wall  52  of a trench  50  are also referred to as side portion  51  of the wall and bottom portion  52  of the wall, respectively. 
     The vertical extension d of the trenches  50  is typically at least about 5 μm (deep trench), for example in a range from about 6 μm to about 7 μm. 
     Further, the horizontal extension (distance of sidewalls  51 ) w of each trench  50  is typically smaller than the vertical extension d. 
     The aspect ratio d/w of the trenches  50  may be larger than 2 or even 5. 
     Thereafter, a first silicon oxide layer  5   a  covering the sidewalls  51  and the bottom walls  52  may be deposited. The resulting structure  100  is illustrated in  FIG. 2 . 
     The first silicon oxide layer  5   a  is typically comparatively thin, e.g. about 5 nm to about 20 nm thick, more typically 5 nm to about 10 nm thick. 
     Thereafter, a semiconductor layer  6  doped with the first dopants may be formed at the sidewalls  51  and bottom walls  52 . For example, a highly boron doped poly-Si layer  6  may be formed by conformal deposition. The resulting structure  100  is illustrated in  FIG. 3 . 
     The semiconductor layer  6  may, depending on doping concentration, also be comparatively thin, e.g. about 5 nm to about 20 nm thick, more typically 5 nm to about 10 nm thick. 
     As illustrated by the dotted arrows in  FIG. 4 , a subsequent thermal process may be used to outdiffuse the first dopants from the semiconductor layer  6  through the f first silicon oxide layer  5   a  into adjoining the portions of the semiconductor layer  1 . 
     This result in forming a p-type compensation semiconductor region  1   a  along the sidewalls  51  and the bottom wall  52  of each trench  50  with a typically at least ten times higher doping concentration than the remaining semiconductor layer  1 . 
     Thereafter, the semiconductor layer  6  may be removed, typically by isotropic dry or wet etch, selective to the first silicon oxide layer  5   a.    
     As illustrated in  FIG. 5 , the thickness of the compensation semiconductor region(s)  1   a  is typically comparatively small. The thickness of the compensation semiconductor region(s)  1   a  may be in a range from about 5 nm to about 100 nm, more typically from about 10 nm to about 50 nm. 
     Thereafter, a second silicon oxide layer  5   b  may be deposited to fill the trench(es)  50 . The resulting structure  100  is illustrated in  FIG. 6 . 
     Thereafter, any remainders of the oxide layers  5 ,  5   b  on the first side and the mask  5  may be removed. This may be achieved by dry etching, wet etching and/or chemical mechanical polishing (CMP). 
     As illustrated by the “+” symbols in  FIG. 7 , positive charges may be trapped in the trench(es)  50  during manufacturing. Forming of such intrinsic charges in dielectrics next to semiconductor material is difficult or impractical to avoid during manufacturing. The intrinsic charges, in the following also referred to as fixed charges and trapped charges, may be trapped in a dielectric material or at an interface formed with a semiconductor material or a different dielectric material. Sometimes the intrinsic charges are positive, like in silicon oxide, and sometimes the charges are negative. Close to the semiconductor—dielectric interface, in particular a silicon-silicon oxide interface (Si/Si0 2  interface), the fixed charges have a field-impact to the semiconductor material (silicon). This field impact becomes more significant with lowering the doping level of the semiconductor material (silicon). 
     At low enough doping level, a leakage path as illustrated by the u-shaped dash-dotted curve next to the right trench  50  in  FIG. 7  may be formed along the Si/Si0 2  interface in the low p-doped adjoining semiconductor material and hinder a decent voltage blocking. This can be avoided by a large enough amount of first dopants in the compensation semiconductor region  1   a.    
     To keep the overall doping level of the semiconductor layer  1  low as often desired in power applications, the higher doped compensation semiconductor region  1   a  is typically formed only close to or even only in close proximity to semiconductor-dielectric interface of up to a few or a few ten nanometers and the trench  50 , respectively. 
     In some embodiments (not shown in  FIG. 7 ), it is sufficient to interrupt forming of an otherwise continuous depletion layer or a continuous inversion channel, which may e.g. be formed between adjacent mesas  60  of the semiconductor layer  1 , by a higher doped compensation semiconductor region  1   a  formed only at a portion of the wall, for example at the bottom wall  52  or at one of the sidewalls  51 . 
     Determining the desired doping level of the compensation semiconductor region  1   a  may include estimating the amount of the fixed charges expected due to the dielectric filling of the trench  50 . This may be based on experience and/or simulation. 
     The desired doping level of the compensation semiconductor region  1   a  may be determined from the relation:
 
 N   1   *I   1   &gt;=I   2 /(2* e ),
 
     where e, N1, I1, and I2 refer to the elementary charge, the number of the majority charge carriers per unit provided by the first dopants in the semiconductor material (N1=1 for boron in silicon), a line integral of the doping concentration along a first curve L 1 , which runs through the compensation semiconductor region  1   a , and line integral of a concentration of the fixed charges (+) along a second curve L 2  which runs through the trench  50 , and wherein the first curve L 1  and the second curve L 2  form respective line segments of a straight line L perpendicular to the interface and the respective wall portion  51 ,  52 , respectively. 
     For typical boron doping concentrations of the semiconductor layer  1  in a range between about 1015/cm 3  and about 1016/cm 3  and SiO2 as dielectric trench filling  55 , the first quantity I1 is typically in a range between about 1010/cm 2  and about 1011/cm 2 . 
     The doping concentration of the first dopants is typically at least one order of magnitude higher in the compensation semiconductor region  1   a  compared to the semiconductor layer  1 . 
     The doping concentration of the first dopants in the compensation semiconductor region  1   a  may be larger than 10 17 /cm 3 , 10 18 /cm 3  or even 5*10 18 /cm 3 . 
     To keep the average doping level of the semiconductor layer  1  and the compensation semiconductor region  1   a  low, N1*I1&lt;=I2/e is typically also ensured. 
     In embodiments in which the the dielectric material  55  in the trench  50  is, in the vertical cross-section, surrounded by the compensation semiconductor region  1   a  except at the first side  101  as shown in  FIG. 7 , the amount of the first dopants in the compensation semiconductor region  1   a  may also be determined so that that the amount of the first dopants times N1 is at least about (and typically less than twice) an absolute value of the expected total charge of trapped charges (+) in the trench  50  divided by the elementary charge e. 
     The doping level of the compensation semiconductor region  1   a  may also be somewhat smaller, for example 20% or 25% smaller compared to ideal compensation of fixed charges, when only a partial compensation is reasonable. 
     After or prior to forming the deep trench isolation including the compensation semiconductor region  1   a , further manufacturing processes may be used to form devices in the mesa(s)  60 . This may include forming next to the trenches  50  field-effect structure(s), for example FinFET-structures, diode structure(s) and/or edge-termination structures. 
     Further device manufacturing from the first side  101  may include processes like implanting dopants, annealing, etching shallow trenches from the first side  101  into the semiconductor layer  1 , insulating sidewalls of the shallow trenches, forming insulated gate electrodes in the shallow trenches, forming insulated gate electrodes on and/or at the first side  101 , and forming contact metallizations on the first side  101 . 
     Further device manufacturing from the second side  102  may include implanting dopants, forming a contact metallizations on the second side  101  and the like. 
     Thereafter, the wafer  40  may be singulated into individual chips  100 . 
     Due to the compensation semiconductor regions  1   a  of the deep trench isolations  1   a ,  50 ,  55 , the device structures formed in the mesas  60  are well protected against leakage currents. Accordingly, the devices may safely be operated at different voltage levels A, B, C as illustrated in  FIG. 8 . 
     The deep trench isolation  1   a ,  50 ,  55 , may also be used to separate an active device area  110  from a peripheral area  120  surrounding the active device area  110  when seen from above and extending to an edge  41  delimiting the semiconductor body  40  in a direction parallel to the first side  101 . This is illustrated in  FIG. 9  for an exemplary vertical power diode  100 ′ having in the active area  110  an n-type cathode region  2  forming a pn-junction with the semiconductor layer  1 . Further, a cathode metallization  10  in Ohmic contact with the cathode region  2  is formed on the first side  101 , and an anode metallization  12  in Ohmic contact with the semiconductor layer  1  is formed on the second side  102 . The deep trench isolation  1   a ,  50 ,  55 , may surround the active device area  110  when seen from above. 
     Due to the compensation semiconductor regions  1   a , low leakage current during blocking mode of the power diode  100 ′ can be ensured. 
     According to an embodiment, the power semiconductor device  100 ,  100 ′ includes a semiconductor body  40  including a first side  101  and a semiconductor layer  1  of a first conductivity type extending to the first side, at least one deep trench isolation which extends from the first side  101  into the semiconductor layer  1  and includes, in a vertical cross-section perpendicular to the first side  101 , two sidewalls  51 , a dielectric region  55  extending between the two sidewalls  51 , and fixed charges. A compensation semiconductor region  1   a  extends along the two sidewalls  51  and the dielectric region  55 . In the vertical cross-section, an amount of dopants of the first conductivity type in the compensation semiconductor region  1   a  times a number of charge carriers per unit, which are provided by the dopants of the first conductivity type in compensation semiconductor region, is at least about an absolute value of a non-vanishing total charge of the fixed charges divided by the elementary charge. The total charge is of the same electric charge type as the charge carriers. 
       FIG. 10  to  FIG. 13  illustrate processes of a method for forming a power semiconductor device  200 . 
     Similar as explained above with regard to  FIG. 1 , deep trenches  50  may be etched into a provided semiconductor layer  1  using a photo lithographically structured hardmask  5  formed thereon. The resulting structure  200  is shown in  FIG. 10 . 
     Thereafter, (boron) doped silicon may be deposited at the walls  51 ,  52  using selective epitaxy to form a compensation semiconductor regions  1   b  in each trench  50 . The resulting structure  200  is shown in  FIG. 11 . 
     Thereafter, silicon oxide may be deposited to fill the trenches  50  with a dielectric region  55 . The resulting structure  200  with two exemplary deep trench isolations is shown in  FIG. 12 . 
     In this embodiment, the compensation semiconductor regions  1   b  are also formed at the wall  51 ,  52  but inside the respective trench  50 . 
     Thereafter, the mask  5  may be removed, e.g. by dry etching, wet etching and/or CMP. The resulting structure  200  is shown in  FIG. 13 . 
     After or prior to forming the deep trench isolations, further manufacturing processes may be used as explained above with regard to  FIG. 8  and  FIG. 9 . 
       FIG. 14  to  FIG. 17  illustrate processes of a method for forming a power semiconductor device  300 . 
     Similar as explained above with regard to  FIG. 1 , deep trenches  50  may be etched into a provided semiconductor layer  1  using a photo lithographically structured hardmask  5  formed thereon. The resulting structure  300  is shown in  FIG. 14 . 
     Thereafter, gas phase doping may be used for insitu doping and diffusion of first dopants into portions of the semiconductor layer  1  at the walls  51 ,  52 . Accordingly, compensation semiconductor regions  1   a  may be formed at the walls  51 ,  52 . The resulting structure  300  is shown in  FIG. 15 . 
     Thereafter, silicon oxide may be deposited to fill the trenches  50  with a dielectric region  55 . The resulting structure  300  with two exemplary deep trench isolations is shown in  FIG. 16 . 
     Thereafter, the mask  5  may be removed, e.g. by dry etching, wet etching and/or CMP. The resulting structure  200  is shown in  FIG. 17 . 
     After or prior to forming the deep trench isolations, further manufacturing processes may be used as explained above with regard to  FIG. 8  and  FIG. 9 . 
       FIG. 18  to  FIG. 21  illustrate processes of a method for forming a power semiconductor device  400 . 
     Similar as explained above with regard to  FIG. 1 , deep trenches  50  may be etched into a provided semiconductor layer  1  using a photo lithographically structured hardmask  5  formed thereon. 
     Thereafter, a first silicon oxide layer  7  highly doped with the first dopants, e.g. boron doped silicon oxide, may be deposited to cover the sidewalls  51  and the bottom walls  52 . The resulting structure  400  is illustrated in  FIG. 18 . 
     Thereafter, an outdiffusion anneal may be used to introduce the first dopants into the semiconductor layer  1  as illustrated by the dashed-dotted arrows in  FIG. 19 . 
     Accordingly, compensation semiconductor regions  1   a  may be formed at the walls  51 ,  52 . The resulting structure  400  is shown in  FIG. 20 . 
     A separate outdiffusion anneal may also be omitted, if later thermal processes are used for further device processing. 
     Thereafter, silicon oxide may be deposited to fill the trenches  50  with a dielectric region  55 . The resulting structure  400  with two exemplary deep trench isolations is shown in  FIG. 20 . 
     Thereafter, the hard mask  5  may be removed, e.g. by dry etching, wet etching and/or CMP. The resulting structure  400  is shown in  FIG. 21 . 
     After or prior to forming the deep trench isolations, further manufacturing processes may be used as explained above with regard to  FIG. 8  and  FIG. 9 . 
     The methods described above with regard to the  FIGS. 1 to 21  may be described as providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the semiconductor material of the semiconductor layer and forming a deep trench isolation. Forming the deep trench isolation includes forming a trench from the first side into the semiconductor layer, the trench having, in a vertical cross-section perpendicular to the first side, a sidewall, forming a typically thin compensation semiconductor region of the first conductivity type at and along the sidewall, the compensation semiconductor region having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The method is performed so that the first dopants in the compensation semiconductor region mainly compensate, substantially compensate or even overcompensate a field-effect, in particular field induced leakage paths, of fixed charges of the first electric charge type, which are trapped in the trench, in the semiconductor material next to the dielectric material. 
     In one embodiment, the semiconductor layer is a typically low-doped p-type silicon layer and the dielectric material is silicon oxide. Without the higher p-doped silicon compensation semiconductor region, the intrinsic amount of trapped positive charges in the dielectric material of the deep trench isolation, a leakage path may be formed along the silicon/silicon oxide interface and hinder a decent voltage blocking. This can be avoided by the compensation semiconductor region. 
     Likewise, a higher n-doped compensation semiconductor region may be used for an n-type semiconductor layer and a trench dielectric with trapped negative charges. 
     According to an embodiment of a method of forming a power semiconductor device, the method includes providing a semiconductor layer of a first conductivity type extending to a first side and comprising a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the semiconductor layer, and forming a deep trench isolation. Forming the deep trench isolation includes forming a trench which extends from the first side into the semiconductor layer and comprises, in a vertical cross-section perpendicular to the first side, a sidewall, forming a compensation semiconductor region of the first conductivity type at and along the sidewall, the compensation semiconductor region including a second doping concentration of the first dopants which is higher than the first doping concentration, and filling the trench with a dielectric material. An amount of the first dopants in the compensation semiconductor region is chosen so that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated. 
       FIG. 22  to  FIG. 24  illustrate processes of a method for forming a power semiconductor device  500 . 
     Similar as explained above with regard to  FIG. 1 , deep trenches  50  may be etched into a provided semiconductor layer  1  using a photo lithographically structured hardmask  5  formed thereon. 
     Thereafter, a first silicon oxide layer  5   a  may be deposited to cover at least the bottom walls  52 . The resulting structure  500  is illustrated in  FIG. 22 . 
     Thereafter, first dopants, e.g. boron, may be implanted from the first side  101  as indicated by the dotted arrows in  FIG. 23 . 
     Depending on thickness of first silicon oxide layer  5   a  and implantation energy, the first dopants may even be implanted through the bottom wall(s)  52 . 
     Thereafter, a thermal process may be used to further outdiffuse and/or activate implanted dopants. Accordingly, compensation semiconductor regions  1   a  may be formed at the bottom walls  52  only. 
     A separate thermal process may also be omitted, if later thermal processes are used for further device processing. 
     Thereafter, silicon oxide may be deposited to fill the trenches  50  with a dielectric region  55 . 
     Thereafter, the hard mask  5  may be removed, e.g. by dry etching, wet etching and/or CMP. The resulting structure  500  is shown in  FIG. 24 . 
     After or prior to forming the deep trench isolations, further manufacturing processes may be used as explained above with regard to  FIG. 8  and  FIG. 9 . 
     Although various exemplary embodiments of the invention have been disclosed, it will be apparent to those skilled in the art that various changes and modifications can be made which will achieve some of the advantages of the invention without departing from the spirit and scope of the invention. It will be obvious to those reasonably skilled in the art that other components performing the same functions may be suitably substituted. It should be mentioned that features explained with reference to a specific figure may be combined with features of other figures, even in those cases in which this has not explicitly been mentioned. 
     Spatially relative terms such as “under”, “below”, “lower”, “over”, “upper” and the like are used for ease of description to explain the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device in addition to different orientations than those depicted in the figures. Further, terms such as “first”, “second”, and the like, are also used to describe various elements, regions, sections, etc. and are also not intended to be limiting. Like terms refer to like elements throughout the description. 
     As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. 
     With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.