Patent Publication Number: US-7907218-B2

Title: Receiver apparatus and receiver system

Description:
This non provisional application claims priority under 35 U.S.C. §119 (a) on patent application Ser. No. 2005-322056 filed in Japan on Nov. 7, 2005, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to a receiver apparatus and a receiver system for receiving a radio-frequency signal such as a digital television signal. 
     2. Description of Related Art 
       FIG. 5  is a block diagram showing an outline of the configuration of a conventional receiver system. The receiver system  900  shown in  FIG. 5  is composed of: an antenna  901  for receiving a radio-frequency signal; a receiver apparatus  902  for performing predetermined processing on the signal received by the antenna  901  to acquire a desired signal; and a video display apparatus  903  for performing predetermined processing on the signal acquired by the receiver apparatus  902  to extract video and audio signals. 
     The receiver apparatus  902  is provided with: a tuner circuit portion  911  that converts the radio-frequency signal received by the antenna  901  into an intermediate-frequency signal; a digital demodulating portion  912  that converts the intermediate-frequency signal outputted from the tuner circuit portion  911  into a compressed digital signal; and a power supply portion  913  that feeds the tuner circuit portion  911  and the digital demodulating portion  912  with electric power from which they operate. The digital demodulating portion  912  is provided with a digital demodulating IC  914 , which is a processing IC for converting the intermediate-frequency signal into a digital signal. 
     The video display apparatus  903  is provided with: a digital circuit portion  921  that converts the compressed digital signal fed from the receiver apparatus  902  into digital video and audio signals; a video/audio output circuit  922  that converts the digital video and audio signals outputted from the digital circuit portion  921  into analog video and audio signals; a display processing portion  923  that performs processing for displaying video based on the analog video signal outputted from the video/audio output circuit  922 ; an audio processing portion  924  that performs processing for outputting audio based on the analog audio signal outputted from the video/audio output circuit  922 ; and a power supply portion  925  that feeds the digital circuit portion  921 , the video/audio output circuit  922 , the display processing portion  923 , and the audio processing portion  924  with electric power from which they operate. The digital circuit portion  921  is provided with: a video/audio processing IC  928  for extracting video and audio signals from the compressed digital signal; a video/audio processing memory  926  for temporarily storing data being processed during video/audio processing; and a program memory  927  for storing control codes for controlling the receiver apparatus. 
     In this conventional receiver system  900  configured as described above, the receiver apparatus  902  is electromagnetically shielded by being covered with a shield. On the other hand, the video display apparatus  903  has many functional blocks mounted on the circuit board thereof, namely the video/audio processing IC  928 , the video/audio processing memory  926 , the program memory  927 , the video/audio output circuit  922 , the display processing portion  923 , and the audio processing portion  924 . This requires an accordingly large number of components and conductors to be mounted and laid on the circuit board of the video display apparatus  903 , which thus necessitates the use of a multiple-layer circuit board. 
     Moreover, the above-mentioned functional blocks mounted on the circuit board of the video display apparatus  903 , namely the video/audio processing IC  928 , the video/audio processing memory  926 , the program memory  927 , the video/audio output circuit  922 , the display processing portion  923 , and the audio processing portion  924 , generate unnecessary electromagnetic emission and noise, against which measures need to be taken on the video display apparatus  903  as by providing it with an additional shield. 
     Furthermore, the above-mentioned functional blocks mounted on the circuit board of the video display apparatus  903 , namely the video/audio processing IC  928 , the video/audio processing memory  926 , the program memory  927 , the video/audio output circuit  922 , the display processing portion  923 , and the audio processing portion  924 , also generate heat, against which measures need to be taken as by increasing the area of the circuit board or providing it with an additional heat-dissipating plate. 
     SUMMARY OF THE INVENTION 
     In view of the conventionally encountered inconveniences mentioned above, it is an object of one or more as efts of the present invention to provide a receiver system provided with a video display apparatus having a simple configuration. 
     To achieve the above object, according to an aspect of the present invention, a receiver apparatus is provided with: a tuner circuit portion that converts a radio-frequency signal received by an antenna into an intermediate-frequency signal; a digital demodulating portion that converts the intermediate-frequency signal outputted from the tuner circuit portion into a compressed digital signal; an intermediate-frequency processing circuit portion that converts the intermediate-frequency signal outputted from the tuner circuit portion into a sound intermediate-frequency signal; a digital circuit portion that converts the compressed digital signal outputted from the digital demodulating portion into digital video and audio signals; and a video/audio output circuit that converts the digital video and audio signals outputted from the digital circuit portion into analog video and audio signals. 
     With such configuration, a digital circuit portion and a video/audio output circuit, which are conventionally incorporated in a video display apparatus, are mounted on the circuit board of a receiver apparatus. This makes it possible to realize the video display apparatus with a single-layer circuit board instead of a multiple-layer circuit board. Also, a video processing IC no longer needs to be mounted on the circuit board of the video display apparatus, and thus no measures need to be taken against the heat dissipated from the IC. It is thus possible to realize a receiver system with a video display apparatus having a simple configuration. Moreover, an intermediate-frequency processing circuit portion for converting an intermediate-frequency signal into an audio intermediate-frequency signal is now provided in the receiver apparatus. This makes possible electrical connection with a video display apparatus that is provided with a decoding circuit for an audio intermediate-frequency signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram showing an outline of the configuration of a receiver system according to an embodiment of the present invention; 
         FIGS. 2A and 2B  are diagrams schematically showing how functional blocks are mounted on the receiver apparatus  3  shown in  FIG. 1 ; and 
         FIG. 3  is a diagram schematically showing another example of how functional blocks are mounted on the receiver apparatus  3  shown in  FIG. 1 ; 
         FIG. 4  is a diagram schematically showing still another example of how functional blocks are mounted on the receiver apparatus  3  shown in  FIG. 1 ; 
         FIG. 5  is a block diagram showing an outline of the configuration of a conventional receiver system. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Hereinafter, the configuration of an example receiver system according to the present invention will be described with reference to the accompanying drawings.  FIG. 1  is a block diagram showing an outline of the configuration of a receiver system according to an embodiment of the present invention. 
     The receiver system  1  shown in FIG,  1  includes: an antenna  2  for receiving a radio-frequency signal; a receiver apparatus  3  for performing predetermined processing on the signal received by the antenna  2  to acquire video and audio signals; and a video display apparatus  4  for displaying video based on the video signal fed from the receiver apparatus  3  and/or outputs audio based on the audio signal fed from the receiver apparatus  3 . The antenna  2  is connected via a coaxial cable to a tuner input terminal of the receiver apparatus  3 , and an interface terminal of the receiver apparatus  3  is connected to the video display apparatus  4 . 
     The receiver apparatus  3  is provided with: a tuner circuit portion  11  that converts the radio-frequency signal received by the antenna  2  into an intermediate-frequency signal (hereinafter referred to as the “IF signal”); a digital demodulating portion  12  that converts the IF signal outputted from the tuner circuit portion  11  into a compressed digital signal; an intermediate-frequency processing circuit portion  15  that converts the IF signal outputted from the tuner circuit portion  11  into an audio intermediate-frequency signal (also called sound intermediate-frequency signal and hereinafter referred to as the “SIF signal”); a digital circuit portion  13  that converts the compressed digital signal outputted from the digital demodulating portion  12  into digital video and audio signals; a video/audio output circuit  14  that converts the digital video and audio signals outputted from the digital circuit portion  13  into analog video and audio signals; and a power supply portion  16  that feeds the tuner circuit portion  11 , the digital demodulating portion  12 , the digital circuit portion  13 , and the video/audio output circuit  14 , and the intermediate-frequency processing circuit portion  15  with electric power from which they operate. 
     The digital demodulating portion  12  is provided with a digital demodulating IC  21 , which is a processing IC for converting the IF signal into a digital signal. The intermediate-frequency processing circuit portion  15  is provided with an intermediate-frequency processing IC  25 , which is a processing IC for converting the intermediate-frequency signal into a SIF signal. The digital circuit portion  13  is provided with: a video/audio processing IC  24  for extracting video and audio signals from the compressed digital signal; a video/audio processing memory  22  for storing the compressed digital video and audio signals and a decoded digital video signal; and a program memory  23  for storing control codes for controlling the receiver apparatus. A serial control signal for controlling the tuner circuit portion  11  and the digital demodulating IC  21  is fed to the video/audio processing IC  24 . 
     The video display apparatus  4  is provided with: a display processing portion  31  that performs processing for displaying video based on the analog video signal fed from the receiver apparatus  3 ; an audio processing portion  32  that performs processing for outputting audio based on the analog audio signal fed from the receiver apparatus  3 ; and a power supply portion  33  that feeds the display processing portion  31  and the audio processing portion  32  with electric power from which they operate. The audio processing portion  32  is provided with a decoding circuit for decoding the SIF signal fed from the intermediate-frequency processing IC  25 . 
       FIGS. 2A and 2B  are diagrams schematically showing how functional blocks are mounted on the receiver apparatus  3  shown in  FIG. 1 , with  FIG. 2A  showing the receiver apparatus  3  as seen from one face (top face) thereof and  FIG. 2B  showing the receiver apparatus  3  as seen from the other face (bottom face) thereof. 
     As shown in  FIG. 2A , the receiver apparatus  3  is composed of two circuit boards, namely a first circuit board  50  and a second circuit board  60 . Between these circuit boards, a first shield plate  51  is inserted to electromagnetically shield them from each other. 
     Mounted on the first circuit board  50  is the tuner circuit portion  11 . The first circuit board  50  is fitted on a chassis  70 , and the analog ground pattern of the tuner circuit portion  11  is electrically connected to the chassis  70 . The first circuit board  50  is provided with a tuner input terminal  53 , via which the radio-frequency signal received by the antenna  2  is fed to the tuner circuit portion  11 . The chassis  70  has lids fitted thereto, one on the top face and another on the bottom face thereof, and thereby the first and second circuit boards  50  and  60  are each covered with a shield. 
     The first circuit board  50  is also provided with a first connector  54  along the edge thereof opposite to the edge at which the tuner input terminal  53  is provided. The second circuit board  60  is provided with a second connector  55  along the edge thereof facing the first circuit board  50 . The first and second connectors  54  and  55  are electrically connected together with jumper wires  61 . These jumper wires  61  may all be connected only on one face (bottom face) of each circuit board. 
     Mounted on the second circuit board  60  are the digital demodulating portion  12 , the digital circuit portion  13 , the video/audio output circuit  14 , the intermediate-frequency processing circuit portion  15 , and the power supply portion  16 . As described above, the second circuit board  60  is electromagnetically shielded with the first shield plate  51  provided between it and the first circuit board  50 . 
     The second circuit board  60  is provided with a third connector  56  along one edge thereof. The third connector  56  includes, in addition to the input/output terminals of the tuner circuit portion  11 , the input/output terminals related to the functional blocks mounted on the second circuit board  60 , namely the digital demodulating portion  12 , the digital circuit portion  13 , the video/audio output circuit  14 , the intermediate-frequency processing circuit portion  15 , and the power supply portion  16 . Within the third connector  56 , near the first circuit board  50  is arranged the IF output terminal of the tuner circuit portion  11 . Via this IF output terminal, the IF signal is outputted. Within the third connector  56 , away from the first circuit board  50  are arranged the output terminal and the ground terminal of the video/audio output circuit  14 . 
     The third connector  56  is arranged in a concentrated fashion along one edge of the second circuit board  60 ; specifically, the third connector  56  is arranged along the edge of the second circuit board  60  located in the direction forming the letter “L” with respect to the axis of the tuner input terminal  53 . 
     The digital demodulating portion  12  and the digital circuit portion  13  are electromagnetically shielded from each other with a second shield plate  52 . As the second circuit board  60 , a multiple-layer circuit board is adopted so that the digital demodulating IC  21  provided in the digital demodulating portion  12  and the video/audio processing IC  24  provided in the digital circuit portion  13  are electrically connected together via an interlayer conductor pattern laid inside the second circuit board  60 . These two ICs are mounted in positions apart from each other on the same face of the second circuit board  60 . Moreover, the packages of the digital demodulating IC  21  and the video/audio processing IC  24  each make contact with the chassis  70  via a thermally conductive member laid in between. 
     The connection of the digital ground pattern of the second circuit board  60  to the chassis  70  and the connection of the analog ground pattern of the first circuit board  50  to the chassis  70  are both achieved with solder applied at several spots on the bottom faces of the circuit boards (see solder spots  81  to  88  shown in  FIGS. 2A and 2B ). Here, the bottom faces of the circuit boards denote the faces thereof at which the distance from them to the lids is smaller, in other words, the faces thereof at which the height of the side faces of the chassis is smaller. Performing soldering on the bottom faces of the circuit boards helps reduce the likeliness of the soldering machine or tool touching the side faces of the chassis during the manufacturing process of the receiver apparatus. This ensures highly efficient mounting. 
     Here, as shown in  FIGS. 2A and 2B , the spots at which the ground patterns are connected to the chassis are located not only at one edge of the first and second circuit boards  50  and  60  but at two or more edges thereof. This increases the number of connection points between the chassis and the ground patterns, and thus helps reduce the connection impedance. In the example shown in  FIGS. 2A and 2B , the soldering spots are located at all edges of the circuit boards. This permits an increased number of connection points to be efficiently distributed over a wide area, contributing to an accordingly low impedance. 
     Here, connecting the above-mentioned jumper wires  61  on the same face as the soldering spots, that is, on the bottom face, eliminates the need to turn the circuit boards over between when the jumper wires  61  are connected and when the ground patterns are connected to the chassis  70  with solder. This helps reduce the number of manufacturing steps. 
     The digital circuit portion  13  has the video/audio processing IC  24  mounted on one face (top face) of the second circuit board  60 , and has the video/audio processing memory  22  and the program memory  23  mounted on the other face (bottom face) of the second circuit board  60 . The video/audio processing IC  24 , the video/audio processing memory  22 , and the program memory  23  are electrically connected together via the interlayer conductor pattern. 
     The power supply terminals of the tuner circuit portion  11 , the digital demodulating portion  12 , the digital circuit portion  13 , and the video/audio output circuit  14  are arranged, within the third connector  56 , between the output terminal of the video/audio output circuit  14  and the IF output terminal of the tuner circuit portion  11 . 
     With this configuration, as the result of the digital circuit portion  13  and the video/audio output circuit  14  being mounted on the circuit board of the receiver apparatus  3 , the video display apparatus  4  now needs to incorporate only the display processing portion  31  for displaying as video the video signal fed from the receiver apparatus  3  and the audio processing portion  32  for outputting as audio the audio signal fed from the receiver apparatus  3 . This eliminates the need to adopt a multiple-layer circuit board. In the conventional configuration, since the digital circuit portion is provided in the video display apparatus, measures against the unnecessary electromagnetic emission and noise generated by the video/audio processing IC, the video/audio processing memory, the program memory, and the like need to be taken in the video display apparatus. By contrast, with the configuration according to the present invention, the digital circuit portion is provided in the receiver apparatus, and thus the video display apparatus can be configured without a digital circuit portion. This eliminates the need to take measures against unnecessary electromagnetic emission and noise in the video display apparatus. 
     Moreover, the receiver apparatus  3  incorporates the intermediate-frequency processing circuit portion  15  for converting the intermediate-frequency signal into an SIF signal. This makes possible electrical connection with a video display apparatus provided with a decoding circuit for an SIF signal. 
     The first circuit board  50  now incorporates no IC having a large number, for example, several tens, of pins, and can thus adopt a circuit board having fewer layers than the second circuit board  60  provided with the video/audio processing IC and the digital demodulating IC. For example, the first circuit board  50  may adopt a two-layer circuit board and the second circuit board  60  a four-layer circuit board. 
     The digital demodulating IC  21  and the video/audio processing IC  24  mounted on the circuit board of the receiver apparatus  3  are each connected to the chassis  70  via a thermally conductive member laid in between. Thus, measures against the heat generated by the IC packages are taken. On the other hand, in the video display apparatus, which no longer needs to be provided with IC packages, no measures need to be taken against heat as by increasing the area of the circuit board or providing it with an additional heat-dissipating plate. 
     With the configuration according to the present invention, within the receiver apparatus, the first circuit board composed of analog circuits and the second circuit board composed of digital circuits are separated from each other. This prevents the digital noise generated by the digital demodulating portion and the digital circuit portion from entering the tuner circuit portion, and thus helps prevent degradation of the performance of the tuner circuit portion. 
     The analog ground pattern and the digital ground pattern are each electrically connected to the chassis  70 . This eliminates the need to connect them, for ground connection, to the first connector provided on the first circuit board and the second connector provided on the second circuit board, and also helps reduce the impedance between the analog and digital grounds. 
       FIG. 3  shows a modified embodiment of what is shown in  FIG. 2A . Here, as shown in  FIG. 3 , the digital demodulating portion  12  and the intermediate-frequency processing circuit portion  15  are shielded from each other with a third shield plate  57 . This prevents the digital noise generated by the digital demodulating portion  12  from entering the intermediate-frequency processing IC  25 , and thus helps prevent degradation of performance. 
       FIG. 4  shows a modified embodiment of what is shown in  FIG. 2B . Here, as shown in  FIG. 4 , the intermediate-frequency processing IC  25  is arranged on a face of the circuit board different from the face thereof on which the video/audio processing IC  24  and the digital demodulating IC  21  are arranged (in  FIG. 4 , the intermediate-frequency processing IC  25  is arranged on the bottom face of the circuit board, and the video/audio processing IC  24  and the digital demodulating IC  21  are arranged on the top face of the circuit board). This prevents the digital noise generated by the digital demodulating portion  12  or the digital circuit portion  13  from entering the intermediate-frequency processing circuit portion  15 , and thus helps prevent degradation of performance. 
     The first and second circuit boards are separated from each other with a shield plate. This prevents the electromagnetic emission generated by the digital demodulating portion and the digital circuit portion mounted on the second circuit board from entering the tuner circuit portion on the first circuit board. 
     In addition, on the second circuit board, the digital demodulating portion and the digital circuit portion are separated from each other with a shield plate. This prevents the electromagnetic emission generated by the digital circuit portion from entering the digital demodulating portion. 
     A receiver system according to one or more aspects of the present invention can be suitably used as a receiver system for receiving a digital television broadcast or the like to display received video.