Patent Publication Number: US-10778203-B2

Title: Clock generation circuit and charge pumping system

Description:
PRIORITY CLAIM 
     The present application is a continuation of U.S. application Ser. No. 16/392,765, filed Apr. 24, 2019, now U.S. Pat. No. 10,483,954, issued Nov. 19 2019, which is a continuation of U.S. application Ser. No. 15/823,242, filed Nov. 27, 2017, now U.S. Pat. No. 10,355,682, issued Jul. 16, 2019, which is a continuation of U.S. application Ser. No. 15/003,330, filed Jan. 21, 2016, now U.S. Pat. No. 9,831,860, issued Nov. 28, 2017, which claims the priority of U.S. Provisional Application No. 62/133,924, filed Mar. 16, 2015, each of which are incorporated herein by reference in their entireties. 
    
    
     BACKGROUND 
     A pair of two-phase non-overlapping clock signals includes two clock signals that do not concurrently have a predetermined logical value. Non-overlapping clock signals have been used in many circuit applications, such as a charge pump, a filter, or an amplifier having switched-capacitor configurations, or other applications. In many applications, a pair of two-phase non-overlapping clock signals is generated based on processing a single input clock signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG. 1A  is a functional block diagram of a charge pump and a clock generation circuit illustrating an application of a pair of two-phase non-overlapping clock signals, in accordance with one or more embodiments. 
         FIG. 1B  is a timing diagram of the pair of two-phase non-overlapping clock signals in  FIG. 1A , in accordance with one or more embodiments. 
         FIG. 2A  is a schematic diagram of an example clock generation circuit usable in the circuit depicted in  FIG. 1A , in accordance with one or more embodiments. 
         FIG. 2B  is a timing diagram of various signals in the clock generation circuit in  FIG. 2A , in accordance with one or more embodiments. 
         FIG. 3A  is a schematic diagram of an inverter usable in a clock generation circuit, such as the clock generation circuit depicted in  FIG. 2A , in accordance with one or more embodiments. 
         FIGS. 3B-3D  are schematic diagrams of various example delay circuit usable in a clock generation circuit, such as the clock generation circuit depicted in  FIG. 2A , in accordance with one or more embodiments. 
         FIG. 4A  is a schematic diagram of another example clock generation circuit usable in the circuit depicted in  FIG. 1A , in accordance with one or more embodiments. 
         FIG. 4B  is a timing diagram of various signals in the clock generation circuit in  FIG. 4A , in accordance with one or more embodiments. 
         FIG. 5  is a flow chart of a method of operating a clock generation circuit, such as the clock generation circuit depicted in  FIG. 2A  or  FIG. 4A , in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     In accordance with some embodiments of the present disclosure, a delay circuit and an inverter are used to generate a non-inverted clock signal and an inverted clock signal based on the same clock input signal. A two-phase non-overlapping clock generation circuit generates two non-overlapping clock signals based on the non-inverted clock signal and the inverted clock signal. In accordance with some embodiments of the present disclosure, a delay of the delay circuit is set to improve the symmetry of the waveforms of the generated non-overlapping clock signals. 
       FIG. 1A  is a functional block diagram of a charge pump  110  and a clock generation circuit  120  illustrating an application of a pair of two-phase non-overlapping clock signals CLKφ 1  and CLKφ 2  in accordance with one or more embodiments. 
     Charge pump  110  includes a supply voltage node  112 , a pumped voltage node  114 , a first clock input node  116 , and a second clock input node  118 . Charge pump  110  is configured to generate a pumped voltage VPP at pumped voltage node  114  based on the energy provided from supply voltage VDD at supply voltage node  112  and controlled by clock signal CLKφ 1  at first clock input node  116  and clock signal CLKφ 2  at second clock input node  118 . 
     Clock generation circuit  120  includes an input clock node  122 , a first output clock node  124 , and a second output clock node  126 . Clock generation circuit  120  is configured to generate clock signal CLKφ 1  at first output clock node  124  and clock signal CLKφ 2  at second output clock node  126  based on an input clock signal CLKIN. First output clock node  124  is electrically coupled with first clock input node  116 , and second output clock node  126  is electrically coupled with second clock input node  118 . In some embodiments, input clock signal CLKIN has a predetermined frequency and a corresponding period, which is an inverse of the predetermined frequency. In some embodiments, clock signals CLKφ 1  and CLKφ 2  also have the predetermined frequency. 
       FIG. 1B  is a timing diagram of the pair of two-phase non-overlapping clock signals CLKφ 1  and CLKφ 2  in  FIG. 1A  in accordance with one or more embodiments. During a clock cycle  130  from time t 4  to time t 10 , clock signal CLKφ 1  is at a logic high from time t 4  to time t 6  and at a logic low from time t 6  to time t 10 ; and clock signal CLKφ 2  is at a logic high from time t 7  to time t 9  and at a logic low from time t 4  to time t 7  and from time t 9  to t 10 . Clock cycle  130  has a duration T that equals the inverse of the predetermined frequency of input clock signal CLKIN. 
     During the clock cycle  130 , the portion that clock signal CLKφ 1  is at logic high does not overlap the portion that clock signal CLKφ 2  is at logic high. During the clock cycle  130 , clock signals CLKφ 1  and CLKφ 2  are both logically low from time t 6  to t 7  and having a duration T L1  and are both logically low from time t 9  to t 10  and having a duration T L2 . In some embodiments, a difference between duration T L1  and duration T L2  is usable to measure the symmetry between clock signals CLKφ 1  and CLKφ 2 . The smaller the difference between duration T L1  and duration T L2 , the more symmetry there is between clock signals CLKφ 1  and CLKφ 2 . In some embodiments, the more symmetry between clock signals CLKφ 1  and CLKφ 2 , the better the power conversion efficiency of charge pump  110 . 
       FIG. 2A  is a schematic diagram of an example clock generation circuit  200  usable in the circuit depicted in  FIG. 1A  in accordance with one or more embodiments. Components that are the same or similar to those in  FIG. 1A  are given the same reference numbers, and detailed description thereof is thus omitted. 
     Clock generation circuit  200  includes an input clock node  202 , a first output clock node  204 , and a second output clock node  206 . Input clock node  202  corresponds to input clock node  122  and is configured to receive input clock signal CLKIN. First output clock node  204  corresponds to first output clock node  124  and is configured to output a first phase clock signal CLKφ 1 . Second output clock node  206  corresponds to second output clock node  126  and is configured to output a second phase clock signal CLKφ 2 . 
     Clock generation circuit  200  further includes a two-phase non-overlapping clock generation circuit  210 , a first inverter  222 , and a first delay circuit  224 . Two-phase non-overlapping clock generation circuit  210  is configured to generate first phase clock signal CLKφ 1  and second phase clock signal CLKφ 2  based on a non-inverted clock signal CLKP and an inverted clock signal CLKN. Inverter  222  is configured to generate inverted clock signal CLKN based on input clock signal CLKIN. Delay circuit  224  is configured to generate the non-inverted clock signal CLKP based on input clock signal CLKIN. In some embodiments, input clock signal CLKIN has a predetermined frequency Freq (not shown). 
     Inverter  222  is configured to cause a phase-inverted delay D N  ( FIG. 2B ) between the output terminal  222   b  of inverter  222  and input terminal  222   a  of inverter  222 . Delay circuit  224  is configured to cause a non-phase-inverted delay D P  ( FIG. 2B ) between output terminal  224   b  of delay circuit  224  and input terminal  224   a  of delay circuit  224 . In some embodiments, a difference between the phase-inverted delay D N  and the non-phase-inverted delay D P  is within a first predetermined tolerance. In some embodiments, the first predetermined tolerance is 1.0% of an inverse of the predetermined frequency Freq. 
     Two-phase non-overlapping clock generation circuit  210  includes NAND gates  212  and  213 , delay circuits  214  and  215 , and inverters  216  and  217 . NAND gate  212  includes a first input terminal  212   a , a second input terminal  212   b , and an output terminal  212   c . NAND gate  213  includes a first input terminal  213   a , a second input terminal  213   b , and an output terminal  213   c . Delay circuit  214  includes an input terminal  214   a  and an output terminal  214   b . Delay circuit  215  includes an input terminal  215   a  and an output terminal  215   b . Inverter  216  includes an input terminal  216   a  and an output terminal  216   b . Inverter  217  includes an input terminal  217   a  and an output terminal  217   b.    
     First input terminal  212   a  of NAND gate  212  is configured to receive non-inverted clock signal CLKP. Output terminal  212   c  of NAND gate  212  is electrically coupled with input terminal  214   a  of delay circuit  214 . Delay circuit  214  is configured to generate a signal S 1  at output terminal  214   b  of delay circuit  214 . Input terminal  216   a  of inverter  216  is electrically coupled with output terminal  214   b  of delay circuit  214 . Output terminal  216   b  of inverter  216  is electrically coupled with first output clock node  204 . 
     First input terminal  213   a  of NAND gate  213  is configured to receive inverted clock signal CLKN. Output terminal  213   c  of NAND gate  213  is electrically coupled with input terminal  215   a  of delay circuit  215 . Delay circuit  215  is configured to generate a signal S 2  at output terminal  215   b  of delay circuit  215 . Input terminal  217   a  of inverter  217  is electrically coupled with output terminal  215   b  of delay circuit  215 . Output terminal  217   b  of inverter  217  is electrically coupled with second output clock node  206 . 
     Second input terminal  212   b  of NAND gate  212  is electrically coupled with output terminal  215   b  of delay circuit  215  and is configured to receive signal S 2 . Second input terminal  213   b  of NAND gate  213  is electrically coupled with output terminal  214   b  of delay circuit  214  and is configured to receive signal S 1 . 
     Delay circuit  214  includes 2N inverters electrically coupled in series between input terminal  214   a  and output terminal  214   b . Delay circuit  215  includes 2N inverters electrically coupled in series between input terminal  215   a  and output terminal  215   b . N is a positive, non-zero integer. 
     Moreover, inverter  222  includes an input terminal  222   a  and an output terminal  222   b , and delay circuit  224  includes an input terminal  224   a  and an output terminal  224   b . Input terminal  222   a  of inverter  222  and input terminal  224   a  of delay circuit  224  are electrically coupled with input clock node  202 . Output terminal  224   b  of delay circuit  224  is electrically coupled with first input terminal  212   a  of NAND gate  212 . Output terminal  222   b  of inverter  222  is electrically coupled with first input terminal  213   a  of NAND gate  213 . 
       FIG. 2B  is a timing diagram of various signals, including signals CLKIN, CLKP, CLKN, CLKφ 1 , and CLKφ 2 , in the clock generation circuit  200  in  FIG. 2A  in accordance with one or more embodiments. 
     In some embodiments, input clock signal CLKIN has a predetermined frequency Freq (not shown). An inverse of the predetermined frequency Freq is a time duration T of a clock cycle period of input clock signal CLKIN. 
     At time t 0 , clock signal CLKIN transitions from logically low to logically high. In response to the transition of clock signal CLKIN at time t 0 , at time t 1 , delay circuit  224  causes non-inverted clock signal CLKP to transition from logically low to logically high. Also, in response to the transition of clock signal CLKIN at time t 0 , at time t 2 , inverter  222  causes inverted clock signal CLKN to transition from logically high to logically low. Delay circuit  224  causes a non-phase-inverted delay D P  between time t 1  and time t 0 . Inverter  222  causes a phase-inverted delay D N  between time t 2  and time t 0 . In some embodiments, a difference between the phase-inverted delay D N  and the non-phase-inverted delay D P  is within a first predetermined tolerance. In some embodiments, predetermined tolerance is 1.0 of T, the inverse of the predetermined frequency Freq. 
     At time t 3 , in response to the rising edge of signal CLKP at time t 1  and the falling edge of signal CLKN at time t 2 , two-phase non-overlapping clock generation circuit  210  causes clock signal CLKφ 2  to transition from logically high to logically low. Also, at time t 4 , in response to the rising edge of signal CLKP at time t 1  and the falling edge of signal CLKN at time t 2 , two-phase non-overlapping clock generation circuit  210  causes clock signal CLKφ 1  to transition from logically low to logically high. 
     At time t 5 , clock signal CLKIN transitions from logically high to logically low. In response to the transition of clock signal CLKIN at time t 5 , delay circuit  224  causes non-inverted clock signal CLKP to transition from logically high to logically low. Also, in response to the transition of clock signal CLKIN at time t 5 , inverter  222  causes inverted clock signal CLKN to transition from logically low to logically high. At time t 6 , two-phase non-overlapping clock generation circuit  210  then causes clock signal CLKφ 1  to transition from logically high to logically low. Also, at time t 7 , two-phase non-overlapping clock generation circuit  210  then causes clock signal CLKφ 2  to transition from logically low to logically high. 
     At time t 8 , clock signal CLKIN transitions from logically low to logically high. In response to the transition of clock signal CLKIN at time t 8 , delay circuit  224  causes non-inverted clock signal CLKP to transition from logically low to logically high. Also, in response to the transition of clock signal CLKIN at time t 8 , inverter  222  causes inverted clock signal CLKN to transition from logically high to logically low. At time t 9 , two-phase non-overlapping clock generation circuit  210  then causes clock signal CLKφ 2  to transition from logically high to logically low. Also, at time t 10 , two-phase non-overlapping clock generation circuit  210  then causes clock signal CLKφ 1  to transition from logically low to logically high. 
     In response to a clock cycle  232  from time t 0  to time t 8 , clock signals CLKφ 1  and CLKφ 2  form a clock cycle  234  from time t 4  to time t 10 . Clock cycle  232  has a time duration T, and clock cycle  234  has the same time duration T. During the clock cycle  234 , clock signals CLKφ 1  and CLKφ 2  are both logically low from time t 6  to t 7  and having a duration T L1  and are both logically low from time t 9  to t 10  and having a duration T L2 . In some embodiments, a difference between duration T L1  and duration T L2  is usable to measure the symmetry between clock signals CLKφ 1  and CLKφ 2 . In some embodiments, delay circuit  224  is configured to have a predetermined delay D P  sufficient to cause a difference between duration T L1  and duration T L2  to be less than a predetermined tolerance. In some embodiments, the predetermined tolerance between duration T L1  and duration T L2  is 1.0% of T, which is the inverse of the predetermined frequency Freq. 
       FIG. 3A  is a schematic diagram an inverter  310  usable in a clock generation circuit, such as the clock generation circuit  200  depicted in  FIG. 2A , in accordance with one or more embodiments. 
     Inverter  310  includes a P-type transistor  312  and an N-type transistor  314  electrically coupled in series between a power node  302  and a reference node  304 . Power node  302  is configured to carry a supply voltage VDD, and reference node  304  is configured to carry a reference voltage VSS. A gate  312   g  of transistor  312  and a gate  314   g  of transistor  314  are electrically coupled with an input terminal  316  of inverter  310 . A drain  312   d  of transistor  312  and a drain  314   d  of transistor  314  are electrically coupled with output terminal  318  of inverter  310 . A source  312   s  of transistor  312  is electrically coupled with power node  302 . A source  314   s  of transistor  314  is electrically coupled with reference node  304 . In some embodiments, input terminal  316  corresponds to input terminal  222   a  in  FIG. 2A , and output terminal  318  corresponds to output terminal  222   b.    
     In some embodiments, P-type transistor  312  has a first channel width versus channel length (W/L) ratio. In some embodiments, N-type transistor  314  has a second W/L ratio. 
       FIG. 3B  is a schematic diagram an example delay circuit  320  usable in a clock generation circuit, such as the clock generation circuit  200  depicted in  FIG. 2A , in accordance with one or more embodiments. 
     Delay circuit  320  includes a P-type transistor  322  and an N-type transistor  324  electrically coupled in parallel between an input terminal  326  of delay circuit  320  and an output terminal  328  of delay circuit  320 . In some embodiments, input terminal  326  corresponds to input terminal  224   a  in  FIG. 2A , and output terminal  328  corresponds to output terminal  224   b . A drain  322   d  of transistor  322  and a drain  324   d  of transistor  324  are electrically coupled with output terminal  328  of delay circuit  320 . A source  322   s  of transistor  322  and a source  324   s  of transistor  324  are electrically coupled with input terminal  326  of delay circuit  320 . In some embodiments, the placement of source  322   s  and drain  322   d  is interchangeable. In some embodiments, the placement of source  324   s  and drain  324   d  is interchangeable. 
     A gate  322   g  of P-type transistor  322  is configured to receive a signal sufficient to turn on P-type transistor  322 . In some embodiments, gate  322   g  of P-type transistor  322  is electrically coupled with reference node  304  ( FIG. 3A ). A gate  324   g  of N-type transistor  324  is configured to receive a signal sufficient to turn on N-type transistor  324 . In some embodiments, gate  324   g  of N-type transistor  324  is electrically coupled with power node  302  ( FIG. 3A ). 
     In some embodiments, P-type transistor  322  has a third W/L ratio. In some embodiments, N-type transistor  324  has a fourth W/L ratio. In some embodiments, third W/L ratio is less than the first W/L ratio of P-type transistor  312 . In some embodiments, third W/L ratio is half of the first W/L ratio of P-type transistor  312 . In some embodiments, fourth W/L ratio is less than the second W/L ratio of N-type transistor  314 . In some embodiments, fourth W/L ratio is half of the second W/L ratio of N-type transistor  314 . 
       FIG. 3C  is a schematic diagram another example delay circuit  330  usable in a clock generation circuit, such as the clock generation circuit  200  depicted in  FIG. 2A , in accordance with one or more embodiments. 
     Delay circuit  330  includes P-type transistors  332  and  333  and N-type transistors  334  and  335 . P-type transistors  332  and  333  are electrically coupled in series between and an input terminal  336  of delay circuit  330  and an output terminal  338  of delay circuit  330 . N-type transistors  334  and  335  are electrically coupled in series between and input terminal  336  of delay circuit  330  and output terminal  338  of delay circuit  330 . In some embodiments, input terminal  336  corresponds to input terminal  224   a  in  FIG. 2A , and output terminal  338  corresponds to output terminal  224   b.    
     A source  332   s  of transistor  332  is electrically coupled with input terminal  326 . A drain  332   d  of transistor  332  is electrically coupled with a source  333   s  of transistor  333 . A drain  333   d  of transistor  333  is electrically coupled with output terminal  338 . A source  334   s  of transistor  334  is electrically coupled with input terminal  326 . A drain  334   d  of transistor  334  is electrically coupled with a source  335   s  of transistor  335 . A drain  335   d  of transistor  335  is electrically coupled with output terminal  338 . In some embodiments, the placement of source  332   s  and drain  332   d  or source  333   s  and drain  333   d  is interchangeable. In some embodiments, the placement of source  334   s  and drain  334   d  or source  335   s  and drain  335   d  is interchangeable. 
     A gate  332   g  of P-type transistor  332  and a gate  333   g  of P-type transistor  333  are configured to receive a signal sufficient to turn on P-type transistors  332  and  333 . In some embodiments, gates  332   g  and  333   g  of P-type transistors  322  and  333  are electrically coupled with reference node  304  ( FIG. 3A ). A gate  334   g  of N-type transistor  334  and a gate  335   g  of N-type transistor  335  are configured to receive a signal sufficient to turn on N-type transistors  334  and  335 . In some embodiments, gates  334   g  and  335   g  of N-type transistors  324  and  335  are electrically coupled with power node  302  ( FIG. 3A ). 
     In some embodiments, P-type transistors  332  and  333  has a fifth W/L ratio. In some embodiments, N-type transistors  334  and  335  has a sixth W/L ratio. In some embodiments, fifth W/L ratio is less than the first W/L ratio of P-type transistor  312 . In some embodiments, fifth W/L ratio is the same as the first W/L ratio of P-type transistor  312 . In some embodiments, sixth W/L ratio is less than the second W/L ratio of N-type transistor  314 . In some embodiments, sixth W/L ratio the same as the second W/L ratio of N-type transistor  314 . 
       FIG. 3D  is a schematic diagram another example delay circuit  340  usable in a clock generation circuit, such as the clock generation circuit  200  depicted in  FIG. 2A , in accordance with one or more embodiments. 
     Delay circuit  340  is a resistance-capacitance delay circuit including a capacitive device  342  and a resistive device  344 . Capacitive device  342  is electrically coupled between input terminal  346  of delay circuit  340  and reference node  304 . Resistive device  344  is electrically coupled between input terminal  346  of delay circuit  340  and an output terminal  348  of delay circuit  340 . In some embodiments, input terminal  346  corresponds to input terminal  224   a  in  FIG. 2A , and output terminal  348  corresponds to output terminal  224   b.    
       FIG. 4A  is a schematic diagram of another example clock generation circuit  400  usable in the circuit depicted in  FIG. 1A  in accordance with one or more embodiments. Components in  FIG. 4A  that are the same or similar to those in  FIG. 2A  are given the same reference numbers, and detailed description thereof if thus omitted. 
     Compared with clock generation circuit  200 , clock generation circuit  400  replaces two-phase non-overlapping clock generation circuit  210  with two-phase non-overlapping clock generation circuit  410 . Clock generation circuit  400  includes a first output clock node  404  and a second output clock node  406 . Two-phase non-overlapping clock generation circuit  410  is configured to generate a first phase clock signal CLKφ 3  and a second phase clock signal CLKφ 4  based on a non-inverted clock signal CLKP and an inverted clock signal CLKN. Signals CLKP and CLKN are generated by delay circuit  224  and inverter  222  based on input clock signal CLKIN. In some embodiments, input clock signal CLKIN has a predetermined frequency Freq (not shown). 
     Two-phase non-overlapping clock generation circuit  410  includes NOR gates  412  and  413  and delay circuits  414  and  415 . NOR gate  412  includes a first input terminal  412   a , a second input terminal  412   b , and an output terminal  412   c . NOR gate  413  includes a first input terminal  413   a , a second input terminal  413   b , and an output terminal  413   c . Delay circuit  414  corresponds to delay circuit  214  and includes an input terminal  414   a  and an output terminal  414   b . Delay circuit  415  corresponds to delay circuit  215  and includes an input terminal  415   a  and an output terminal  415   b.    
     First input terminal  412   a  of NOR gate  412  is configured to receive non-inverted clock signal CLKP. Output terminal  412   c  of NOR gate  412  is electrically coupled with input terminal  414   a  of delay circuit  414 . Delay circuit  414  is configured to generate a signal S 3  at output terminal  414   b  of delay circuit  414 . Output terminal  414   b  is electrically coupled with first output clock node  404 . 
     First input terminal  413   a  of NOR gate  413  is configured to receive inverted clock signal CLKN. Output terminal  413   c  of NOR gate  413  is electrically coupled with input terminal  415   a  of delay circuit  415 . Delay circuit  415  is configured to generate a signal S 4  at output terminal  415   b  of delay circuit  415 . Output terminal  415   b  is electrically coupled with second output clock node  406 . 
     Second input terminal  412   b  of NOR gate  412  is electrically coupled with output terminal  415   b  of delay circuit  415  and is configured to receive signal S 4 . Second input terminal  413   b  of NOR gate  413  is electrically coupled with output terminal  414   b  of delay circuit  414  and is configured to receive signal S 3 . 
     Delay circuit  414  corresponds to delay circuit  214  and includes 2N inverters electrically coupled in series between input terminal  414   a  and output terminal  414   b . Delay circuit  415  corresponds to delay circuit  215  and includes 2N inverters electrically coupled in series between input terminal  415   a  and output terminal  415   b . N is a positive, non-zero integer. 
       FIG. 4B  is a timing diagram of various signals, including signals CLKIN, CLKP, CLKN, CLKφ 3 , and CLKφ 4 , in the clock generation circuit  400  in  FIG. 4A  in accordance with one or more embodiments. Components that are the same or similar to those in  FIG. 2B  are given the same reference numbers, and detailed description thereof is thus omitted. 
     In some embodiments, input clock signal CLKIN has a predetermined frequency Freq (not shown). An inverse of the predetermined frequency Freq is a time duration T of a clock cycle period of input clock signal CLKIN. 
     At time t 3 , in response to the rising edge of signal CLKP at time t 1  and the falling edge of signal CLKN at time t 2 , two-phase non-overlapping clock generation circuit  410  causes clock signal CLKφ 3  to transition from logically high to logically low. Also, at time t 4 , in response to the rising edge of signal CLKP at time t 1  and the falling edge of signal CLKN at time t 2 , two-phase non-overlapping clock generation circuit  410  causes clock signal CLKφ 4  to transition from logically low to logically high. 
     At time t 5 , clock signal CLKIN transitions from logically high to logically low. In response to the transition of clock signal CLKIN at time t 5 , delay circuit  224  causes non-inverted clock signal CLKP to transition from logically high to logically low, and inverter  222  causes inverted clock signal CLKN to transition from logically low to logically high. At time t 6 , two-phase non-overlapping clock generation circuit  410  then causes clock signal CLKφ 4  to transition from logically high to logically low. Also, at time t 7 , two-phase non-overlapping clock generation circuit  410  then causes clock signal CLKφ 3  to transition from logically low to logically high. 
     At time t 8 , clock signal CLKIN transitions from logically low to logically high. In response to the transition of clock signal CLKIN at time t 8 , delay circuit  224  causes non-inverted clock signal CLKP to transition from logically low to logically high, and inverter  222  causes inverted clock signal CLKN to transition from logically high to logically low. At time t 9 , two-phase non-overlapping clock generation circuit  410  then causes clock signal CLKφ 3  to transition from logically high to logically low. Also, at time t 10 , two-phase non-overlapping clock generation circuit  410  then causes clock signal CLKφ 4  to transition from logically low to logically high. 
     In response to a clock cycle  432  from time t 0  to time t 8 , clock signals CLKφ 3  and CLKφ 4  form a clock cycle  434  from time t 4  to time t 10 . Clock cycle  432  has a time duration T, and clock cycle  434  has the same time duration T. During the clock cycle  434 , clock signals CLKφ 3  and CLKφ 4  are both logically low from time t 6  to t 7  and having a duration T L3  and are both logically low from time t 9  to t 10  and having a duration T L4 . In some embodiments, a difference between duration T L3  and duration T L4  is usable to measure the symmetry between clock signals CLKφ 3  and CLKφ 4 . In some embodiments, delay circuit  224  is configured to have a predetermined delay D P  sufficient to cause a difference between duration T L3  and duration T L4  to be less than a predetermined tolerance. In some embodiments, the predetermined tolerance between duration T L3  and duration T L4  is 1.0% of T, which is the inverse of the predetermined frequency Freq. 
       FIG. 5  is a flow chart of a method  500  of operating a clock generation circuit, such as the clock generation circuit depicted in  FIG. 2A  or  FIG. 4A , to generate a pair of two-phase non-overlapping clock signals in accordance with some embodiments. It is understood that additional operations may be performed before, during, and/or after the method  500  depicted in  FIG. 5 , and that some other processes may only be briefly described herein. 
     The method  500  begins with operation  510 , where an inverted clock signal CLKN is generated by an inverter  222  based on an input clock signal CLKIN. In some embodiments, input clock signal CLKIN has a predetermined frequency Freq. 
     The method  500  proceeds to operation  520 , where a non-inverted clock signal CLKP is generated by a delay circuit  224  based on input clock signal CLKIN. The delay circuit  224  has a predetermined delay D P . 
     The method  500  proceeds to operation  530 , where a first phase clock signal CLKφ 1  or CLKφ 3  and a second phase clock signal CLKφ 2  or CLKφ 4  of the pair of two-phase non-overlapping clock signals are generated by a two-phase non-overlapping clock generation circuit  210  or  410 . The first phase clock signal CLKφ 1  or CLKφ 3  and the second phase clock signal CLKφ 2  or CLKφ 4  correspond to a same logical value during a first duration T L1  or T L3  and a second duration and T L2  or T L4  within a clock cycle  234  or  434 . The first phase clock signal CLKφ 1  or CLKφ 3  and the second phase clock signal CLKφ 2  or CLKφ 4  correspond to different logical values during the remainder of the clock cycle  234  or  434 . The clock cycle  234  or  434  has a duration T, which is an inverse of the predetermined frequency Freq. 
     In some embodiments, the predetermined delay D P  of delay circuit  224  is set to be sufficient to cause a difference between the first duration T L1  or T L3  and the second duration T L2  or T L4  to be less than a predetermined tolerance. In some embodiments, the predetermined tolerance is 1.0% of the duration T of the clock cycle  234  or  434 . 
     Operation  530  further includes performing generating a first signal S 1  or S 3  based on performing a first logical operation on the non-inverted clock signal CLKP and a second signal S 2  or S 4  (operation  532 ); and generating the second signal S 2  or S 4  based on performing a second logical operation on the inverted clock signal CLKN and the first signal S 1  or S 3 . In some embodiments, the first logical operation and the second logical operation are both NAND operations or are both NOR operations. 
     In some embodiments, the generating first signal S 1  or S 3  is performed by a logical gate  212  or  412  and a delay circuit  214  or  414 . In some embodiments, the generating second signal S 2  or S 4  is performed by a logical gate  213  or  413  and a delay circuit  215  or  415 . In some embodiments, logical gate  212  or  412  and logical gate  213  and  413  correspond to a same logical gate configuration. In some embodiments, delay circuit  214  or  414  and delay circuit  215  or  415  correspond to a same delay circuit configuration. 
     In an embodiment, a clock generation circuit includes: a two-phase clock generation circuit including first and second branches correspondingly configured to generate a first phase clock signal and a second phase clock signal based correspondingly on a non-inverted clock signal and an inverted clock signal, the first and second branches being cross-coupled with each other; an inverter configured to generate the inverted clock signal based on an input clock signal; and a delay circuit which is non-inverter-based and which is configured to generate the non-inverted clock signal based on the input clock signal; and wherein the inverter includes a first P-type transistor and a first N-type transistor, the first P-type transistor and the first N-type transistor being coupled in series, gates of the first P-type transistor and the first N-type transistor being coupled with an input terminal of the inverter, and drains of the first P-type transistor and the first N-type transistor being coupled with an output terminal of the inverter; the delay circuit includes a second P-type transistor and a second N-type transistor, the second P-type transistor and the second N-type transistor being coupled in parallel between input and output terminals of the delay circuit; the first P-type transistor has a first channel width versus channel length (W/L) ratio; the first N-type transistor has a second W/L ratio; and at least one of the following conditions is true: the second P-type transistor having a third W/L ratio less than the first W/L ratio; or the second N-type transistor having a fourth W/L ratio less than the second W/L ratio. In an embodiment, the first phase clock signal and the second phase clock signal correspond: to a same logical value during a first duration and a second duration within a cycle of the input clock signal; and to different logical values during a remainder of the input clock signal; and a difference between the first duration and the second duration to be less than a predetermined tolerance. In an embodiment, the input clock signal has a predetermined frequency; a period of the input clock signal has a duration equal to an inverse of the predetermined frequency; and the predetermined tolerance is 1.0% of the duration of the input clock signal. In an embodiment, wherein the delay circuit includes: a plurality of P-type transistors and a plurality of N-type transistors, the plurality of P-type transistors being coupled in series between an input terminal of the delay circuit and an output terminal of the delay circuit, and the plurality of N-type transistors being coupled in series between output terminals of the delay circuit; a resistance-capacitance delay circuit; or a pass gate circuit. In an embodiment, wherein the resistance-capacitance delay circuit includes: a resistive device connected between an input and an output of the delay circuit; and a capacitive device connected between the input of the delay circuit and a reference voltage. In an embodiment, wherein the delay circuit has a predetermined delay sufficient to induce symmetry in the first phase clock signal relative to the second phase clock signal such that midpoints in time of overlapping opposite phases of the first and second phase clock signals are substantially aligned. In an embodiment, wherein the overlapping opposite phases of the first and second phase clock signals have different corresponding durations. 
     In an embodiment, a charge pumping system includes: a clock generation circuit which has an input terminal and which has first and second branches that are cross-coupled with each other and that are configured to provide corresponding first and second phase clock signals on corresponding first and second output terminals, and which includes: a first delay circuit, a first logical gate and a second delay circuit coupled in series along a first path between the input terminal and a first node, the first path including a first input electrode of the first logical gate, a version of the first phase clock signal appearing the first node; and a first inverter, a second logical gate and a third delay circuit coupled in series along a second path between the input terminal and a second node, the second path including a first input electrode of the second logical gate, a version of the second phase clock signal appearing on the second node; the first logical gate also having a second input electrode coupled to the second node; and the second logical gate also having a second input electrode coupled to the first node; and a charge pump configured to generate a pumped voltage according to the first phase clock signal and the second phase clock signal; and wherein the first inverter and the first delay circuit are configured to cause corresponding phase-inverted and non-phase-inverted delays of an input clock signal; the first inverter includes a first P-type transistor and a first N-type transistor coupled in series, gates of the first P-type transistor and the first N-type transistor being coupled with an input node of the first inverter, and drains of the first P-type transistor and the first N-type transistor being coupled with an output node of the first inverter; the first delay circuit includes a second P-type transistor and a second N-type transistor coupled in parallel between an input node of the third delay circuit and an output node of the third delay circuit; the first P-type transistor has a first channel width versus channel length (W/L) ratio; the first N-type transistor has a second W/L ratio; and at least one of the following conditions is true: the second P-type transistor having a third W/L ratio less than the first W/L ratio; or the second N-type transistor having a fourth W/L ratio less than the second W/L ratio. In an embodiment, the first delay circuit is coupled between the input terminal and a third node; the first inverter is coupled between the input terminal and a fourth node; the first input electrode of the first logical gate is coupled to the third node; the first logical gate is coupled between the third node and a fifth node; the first input electrode of the second logical gate is coupled to the fourth node; the second logical gate is coupled between the fourth node and a sixth node; the second delay circuit is coupled between the fifth node and the first node; and the third delay circuit is coupled between the sixth node and the second node. In an embodiment, the first phase clock signal and the second phase clock signal correspond: to a same logical value during a first duration and a second duration within a cycle of the input clock signal; and to different logical values during a remainder of the input clock signal; and a difference between the first duration and the second duration to be less than a predetermined tolerance. In an embodiment, the input clock signal has a predetermined frequency; a period of the input clock signal has a duration equal to an inverse of the predetermined frequency; and the predetermined tolerance is 1.0% of the duration of the input clock signal. In an embodiment, the first delay circuit is non-inverter-based. In an embodiment, the first delay circuit includes: a pass gate circuit; or a resistance-capacitance delay circuit. In an embodiment, the charge pumping system further satisfies one of the following conditions: each of the first logical gate and the second logical gate is a NAND gate; or each of the first logical gate and the second logical gate is a NOR gate. In an embodiment, the phase-inverted and non-phase-inverted delays of the input clock signal induce symmetry in the second phase clock signal relative to the first phase clock signal such that midpoints in time of overlapping opposite phases of the first and second phase clock signals are substantially aligned. 
     In an embodiment, a method (of generating first and second phase clock signals) includes: generating, by an inverter which has a first predetermined delay and receives an input clock signal having a predetermined frequency, an inverted clock signal, the inverter including: a first P-type transistor having a first channel width versus channel length (W/L) ratio; and a first N-type transistor having a second W/L ratio and coupled in series with the first P-type transistor; gates of the first P-type transistor and the first N-type transistor being coupled with an input terminal of the inverter, and drains of the first P-type transistor and the first N-type transistor being coupled with an output terminal of the inverter; and the first predetermined delay being based on the first and second W/L ratios; generating, by a first delay circuit which has a second predetermined delay and receives the input clock signal, a non-inverted clock signal, the first delay circuit including: a second P-type transistor having a third W/L ratio; and a second N-type transistor having a fourth W/L ratio; the second P-type transistor and the second N-type transistor being coupled in parallel between input and output terminals of the first delay circuit; and the second predetermined delay being based on the third and fourth W/L ratios; and generating the first and second phase clock signals, based correspondingly on the non-inverted clock signal and the inverted clock signal, using a two-phase non-overlapping clock generation circuit which has first and second branches that are cross-coupled with each other and that are configured to provide the first and second phase clock signals; and wherein the first predetermined delay and the second predetermined delay are related based on at least one of the following conditions being true: the third W/L ratio is less than the first W/L ratio; or the fourth W/L ratio is less than the second W/L ratio. In an embodiment, the first and second phase clock signals correspond to a same logical value during a first duration and a second duration within a clock cycle; 
     the first and second phase clock signals correspond to different logical values during a remainder of input clock signal; the input clock signal has a duration equal to an inverse of the predetermined frequency; and the second predetermined delay is set to be sufficient to cause a difference between the first duration and the second duration to be less than a predetermined tolerance. In an embodiment, the generating the first and second phase clock signals includes: generating a first signal based on performing a first logical operation on the non-inverted clock signal and a second signal; and generating the second signal based on performing a second logical operation on the inverted clock signal and the first signal, signal; and each of the first and second logical operations is a NAND operation or each of the first and second logical operations is a NOR operation. In an embodiment, the generating a first signal is performed by a first logical gate and a second delay circuit; the generating the second signal is performed by a second logical gate and a third delay circuit; the first and second logical gates correspond to a same logical gate configuration; and the second and third delay circuits correspond to a same delay circuit configuration. In an embodiment, the first and second predetermined delays induce symmetry in the second phase clock signal relative to the first phase clock signal such that midpoints in time of overlapping opposite phases of the first and second phase clock signals are substantially aligned. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.