Patent Publication Number: US-7710155-B2

Title: Dynamic dual output latch

Description:
BACKGROUND OF THE INVENTION 
     A latch is typically the first stage of a register element. In a dynamic or a timing-critical application, dual monotonic signal outputs are required. “Monotonic” refers to a data transition characteristic of the output signals of the latch. The output signals are “monotonic” when exactly one of these output signals transitions, and transitions only once, during a given clock phase. A clock-gated dynamic latch has the desired behavior, but has the drawback of using ratioed logic. That is, to allow the latch to be written into, one of the cross-coupled devices is provided a lesser output drive capability, so that the new data can overwrite the existing data by contending with and overcoming the drive strength of this lesser drive capability. In the ratioed logic circuit, a pull-down NMOS device is required to pull a dynamic node to ground reference (i.e., voltage V ss ,) over PMOS pull-up devices (“keeper device”) that attempts to drive the dynamic node to the supply voltage (i.e., voltage V dd ). Consequently, ratioed logic circuits require larger pull-down devices. Therefore, greater power and area than desired are required. 
     Ratioed logic suffers from a number of disadvantages. First, the contention between pull-up PMOS transistors or pull-down NMOS transistors during the write process dissipates power. Second, the contention present when the latch is written into requires time to resolve, hence affecting evaluation time performance, thus slowing circuit operation. Ratioed logic also does not scale well over a large range of operating voltages, and tends to fail more frequently at the lower end of the operating voltages. In addition, ratioed logic circuits are sensitive to variations in process parameter values, and are therefore susceptible to failure modes relating to process variations. 
     SUMMARY 
     According to one embodiment of this invention, a dynamic latch includes a first stage for receiving an input data value and for providing true and complement logic values representing the input data value; a second stage for receiving the true and complement logic values into first and second dynamic nodes, when a control signal is active; and a holding circuit that outputs the true and complement logic values while the control signal is active. The second stage may provide a feedback signal to the first stage to block propagation of changes in the input data value after the true and complement logic values have been received. The feedback signal may be derived, for example, from logic values on the dynamic nodes. The holding circuit may include cross-coupled logic gates receiving as input the true and complement data values from the first and second dynamic nodes, and the logic values on the dynamic nodes may be driven by an output circuit as the output of the dynamic latch, so as to provide dual output values. 
     This invention is better understood upon consideration of the detailed description below in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows monotonic dual-output flip-flop  100 , according to one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     This invention provides a latch which includes a first stage for receiving an input data bit and a second stage for providing the data bit received in true and complement forms at two output dynamic nodes. In addition, a holding circuit may be provided to hold the output values of the dynamic nodes. The second stage provides a feedback signal to the first stage to block propagation of subsequent changes in the input data value after the full logic states are achieved at the dynamic nodes. The dynamic latch of this invention does not have ratioed logic contention. By avoiding ratioed logic contention, a latch of this invention may operate in very low operating voltages, and may use smaller transistors, thereby reducing power and area requirements. 
       FIG. 1  shows monotonic dual-output latch or flip-flop  100 , according to one embodiment of the present invention. As shown in  FIG. 1 , flip-flop  100  includes dynamic nodes  101  and  102  driven by dynamic clocked stacks  105  and  106 . Dynamic clocked stacks  105  and  106  each includes a PMOS transistor (i.e., PMOS transistor  105   a  or  106   a ) and an NMOS transistor (i.e., NMOS transistor  105   c  or  106   c ) controlled by a control signal (i.e., control signal CLK). Dynamic clocked stacks  105  and  106  each further include an input transistor (i.e., input transistor  105   b  or  106   b ) that receives a single-bit data input. The logic values received by input transistors  105   b  and  106   b  are complementary because of inverter  107 . 
     When control signal CLK is not active (i.e., at logic ‘0’ or LOW), PMOS transistors  105   a  and  106   a  precharge dynamic nodes  101  and  102  to supply voltage V.sub.dd. As a result, NAND gate  108  provides a logic ‘0’ output value (i.e., signal FB is at logic ‘0’), thereby allowing the complementary input logic values at terminals  109   a  and  109   b  to propagate through NOR gates  110   a  and  110   b , respectively. 
     When control signal CLK becomes active (i.e., asserted, at logic ‘1’ or HIGH), PMOS transistors  105   a  and  106   a  are turned off, and NMOS transistors  105   c  and  106   c  become conducting. Dynamic clocked stacks  105  and  106  therefore evaluate the input signals at dynamic nodes  101  and  102 . As the data bits at the gate terminals of input transistors  105   b  and  106   b  are complementary, exactly one of dynamic nodes  101  and  102  is discharged to the ground reference. NAND gate  108  then provides a logic ‘1’ value output, thereby blocking propagation of any subsequent change in input data value at terminals  109   a  and  109   b . At the same time, one of PMOS transistors  120   a  and  121   a  in cross-coupled NAND gates  120  and  121  becomes conducting, as a result of the corresponding one of nodes  101  and  102  having discharged. 
     At this time, signal FB (now having a logic ‘1’ value) renders NMOS transistors  120   c  and  120   d  conducting, while control signal CLK renders NMOS transistors  120   d  and  121   d  conducting. Thus, the discharged one of dynamic nodes  101  and  102  is held to the ground reference by the action of corresponding NMOS transistor  120   b  or  121   b , while the undischarged one of dynamic nodes  101  and  102  is held to supply voltage V dd  by the action of the conducting one of PMOS transistors  120   a  and  120   b . Thus, cross-couple NAND gates  120  and  121  form a holding circuit for the output logic values until control signal CLK becomes inactive (i.e., deasserted). Complementary output values are driven by inverting drivers  103  and  104  onto terminals  122  and  123 . 
     The holding circuit of NAND gates  120  and  121  turns on as one of dynamic nodes  101  and  102  discharges. Unlike the ratioed logic at the output nodes of prior art latches, contention exists in neither dynamic node  101  nor dynamic node  102 . Accordingly, power dissipation due to contention at the holding circuit is avoided. The feedback signal FB is asserted only after dynamic nodes  101  and  102  achieve full logic values. 
     Accordingly, output flip-flop  100  provides dual output values. When control signal CLK is not active, the output values of flip-flop  100  are pre-charged to logic value ‘1’ for evaluation in the next cycle. 
     As shown in  FIG. 1 , flip-flop  100  has a two-gate delay from clock transition to output, which is a desirable timing characteristic suitable for use in a critical path. Since ratioed logic contention is not present, flip-flop  100  can operate at very low operating voltages. In addition, without ratioed logic contention, smaller NMOS pull-down devices can be used to implement flip-flop  100 , thereby providing power and area savings. 
     During hold mode (i.e., when feedback signal FB is at logic value ‘1’), the holding circuit of NAND gates  120  and  121  maintains dynamic nodes  101  and  102  even though various sources of charge leakage may exist. Flip-flop  100  uses only a single clock signal, obviating the need for complementary clock signals to achieve storage. Because the holding circuit is turned off when data is sampled, there is little power loss due to crowbar currents. 
     In one example, latch  100  is implemented using the following components, provided here for illustrative purpose (all transistors have a channel length of 60 nm): 
     
       
         
           
               
               
               
             
               
                   
                   
               
               
                   
                 DEVICE 
                 WIDTH (μm) 
               
               
                   
                   
               
             
            
               
                   
                 Inverter 107 
                 0.25 (NMOS) 0.5 (PMOS) 
               
               
                   
                 NAND 108 
                 0.6 (NMOS) 1.2 (PMOS) 
               
               
                   
                 NOR gates 110a and 110b 
                 0.3 (NMOS) 1.2 (PMOS) 
               
               
                   
                 PMOS 105a and 106a 
                 0.7 
               
               
                   
                 NMOS 105b and 106b 
                 1.0 
               
               
                   
                 NMOS 105c and 106c 
                 2.0 
               
               
                   
                 PMOS 120a and 121a 
                 0.3 
               
               
                   
                 NMOS 120b, 120c, 120d, 
                 0.5 
               
               
                   
                 121b, 121c and 121d 
               
               
                   
                 INVERTERS 103 and 104 
                 1.0 (NMOS) 3.0 (PMOS) 
               
               
                   
                   
               
            
           
         
       
     
     A latch of this invention is especially suitable for use, for example, in (a) the address or command decode circuits for static random access memories (SRAMs), read-only memories (ROMs) and register files; (b) any dynamic circuit, such as various types of comparators; (c) content addressable memories (CAMs) and ternary CAMs (TCAMs); (d) fast adders, arithmetic logic units (ALUs), Booth coder/decoders for Booth multipliers; (e) any decoding circuit, and (f) synchronizer circuits. For example, in the address and command decode circuits of SRAMs, ROMs or register files, a latch of this invention provides complimentary monotonic data which speeds up read/write accesses and lowers power dissipation, In CAM or TCAM applications, the registers elements of the present invention provides the required monotonic results in comparisons of key data. In adders and ALU applications, the register elements of this invention allow operands to be stored and output as dual rail domino signals, thus allowing interface with dual dynamic domino logic circuits often found in these same applications. In general, the registers of this invention allows lower power, smaller silicon area and low-voltage operations. 
     Using transistor models for a 90 nm CMOS manufacturing process, simulation results from a SPICE simulator show that flip-flop  100  can operate from a 0.95 volts operating voltage at 3 GHz down to a 0.25 volts operating voltage at 200 MHz. 
     The hardware described above, including any logic or transistor circuit, may be generated automatically by computer based on a description of the hardware expressed in the syntax and the semantics of a hardware description language, as known by those skilled in the art. Applicable hardware description languages include those provided at the layout, circuit netlist, register transfer, and schematic capture levels. Examples of hardware description languages include GDS II and OASIS (layout level), various SPICE languages and IBIS (circuit netlist level), Verilog and VHDL (register transfer level) and Virtuoso custom design language and Design Architecture-IC custom design language (schematic capture level). The hardware description may also be used, for example, in various behavior, logic and circuit modeling and simulation purposes. 
     The above detailed description is provided to illustrate specific embodiments of this invention and is not intended to be limiting. Numerous variations and modifications within the scope of this invention are possible. This invention is set forth in the following claims.