Patent Publication Number: US-2002009842-A1

Title: High-voltage device and method for manufacturing high-voltage device

Description:
BACKGROUND OF THE INVENTION  
       [0001] Field of Invention  
       [0002] The present invention relates to a semiconductor and a method for manufacturing a semiconductor. More particularly, the present invention relates to a high-voltage device and a method for manufacturing a high-voltage device.  
       [0003] Description of Related Art  
       [0004] A high voltage device is one of the most important devices utilized in a highly integrated circuit. Erasable programmable read only memory (EPROM) and flash memory are two of the high-voltage devices most often used in computers and electronic products.  
       [0005] Due to the increasing number of semiconductor devices incorporated in integrated circuits, the size of transistors needs to be decreased. Accordingly, as the channel length of the transistors is decreased, the operating speed is increased. However, the short channel effect caused by the reduced channel length is becoming serious. If the voltage level is fixed as the channel length is shortened, the strength of the electrical field is increased according to the equation, electrical field=electrical voltage/channel length. Thus, as the strength of the electrical field increases, the electron energy increases and electrical breakdown is likely to occur.  
       [0006] In the conventional high-voltage device. the formation of an isolation layer is used for the purpose of increasing the channel length. Hence, the high-voltage device is able to work normally at a high electrical voltage.  
       [0007]FIG. 1 is a schematic. cross-sectional view showing a portion of a conventional high-voltage device.  
       [0008] As shown in FIG. 1. two field oxide layers  102  are formed in the P-type silicon substrate  100 . A gate oxide layer  112  is formed on the substrate  100  between the two field oxide layers  102 . The field oxide layers  102  are used to increase the channel length between an N + -type source region  106  and an N − -type drain region  108 . An N − -type doped region  116  expands from a portion of the substrate beneath the source region  106  to the far side of one of the field oxide layers  102 . An N − -type doped region  118  expands from a portion of the substrate beneath the drain region  108  to the far side of the other of the field oxide layers  102 . A portion of a gate  104  is located on the gate oxide layer  112  and the other portion of the gate  104  is positioned on the field oxide layers  102 . The N − -type doped regions  116  and  118  are used as drift regions for carriers while the device is operated.  
       [0009] In order to increase the breakdown voltage of the high-voltage device. it is necessary to decrease the dopant concentration of the drift region, which concentration is the dopant concentration of the N − -type doped regions  116  and  118 . However, the current-driving performance and the channel conductivity between the source region  106  and the drain region  108  under the gate electrode  104  in the substrate  100  are decreased.  
       [0010] Additionally, when the manufacturing technique is promoted to a sub-quarter micron level, for example. a line width of 0.18 microns or less. it is difficult to decrease the typical design rule of the high-voltage device.  
       SUMMARY OF THE INVENTION  
       [0011] The invention provides a high-voltage device constructed on a substrate. The high-voltage device comprise a first well region with the first conductive type. a second well region with a second conductive type, several isolation regions a first doped region with the second conductive type, a second doped region with the first conductive type, a gate structure and a source/drain region with the second conductive type. The first well region is located in the substrate. The isolation regions are located on the first well region. Each of the isolation regions comprises two field oxide layers on either side of a shallow trench isolation structure. The gate structure is formed on the first well region between the isolation regions and the gate structure expands on a portion of the isolation regions. The source/drain region is located in the first well region exposed by the gate structure and the isolation regions. The second well region is located in the first well region beneath the isolation region and the source/drain region. The first doped region is located in the second well region beneath each of the field oxide layers. The second doped region is located in the second well region beneath each of the shallow trench isolation structures.  
       [0012] The invention also provides a method for manufacturing a high-voltage CMOS device. A substrate having a first P-type well region and a first N-type region formed therein is provided. Several first isolation regions and second isolation regions are respectively formed on the first P-type well and the first N-type well. Every first isolation region comprises two first field oxide layers on either side of a first shallow trench isolation structure and every second isolation region comprises two second field oxide layers on either side of a second shallow trench isolation structure. Furthermore, a first N-type doped region and a first P-type doped region are respectively formed beneath each of the first oxide layers and each of the second field oxide layers. A second P-type doped region and a second P-type well region are respectively formed beneath each of the first shallow trench isolation structures and in the first N-type well region under the second isolation regions. A second N-type doped region and a second N-type well region are respectively formed beneath each of the second shallow trench isolation structures and in the first P-type well region under the first isolation regions. A first and a second gate structure are respectively formed on the first P-type well region between the first isolation regions and on the first N-type well region between the second isolation regions. An N-type source/drain region is formed in the second N-type well region exposed by the first gate structure and the first isolation regions. A P-type source/drain region is formed in the second P-type well region exposed by the second gate structure and the second isolation regions.  
       [0013] In the method described above, when the first conductive type is N-type, the second conductive type is P-type. Conversely when the first conductive type is P-type, the second conductive type is N-type.  
       [0014] In the invention, the depletion regions exist between the second P-type doped region and the second N-type well region and between the second N-type doped region and the second P-type well region. Furthermore, each depth of the second N-type well region and the second P-type well region is larger than that of the conventional N − -type doped regions  116  and  118 , so that the intensity of the electric field caused by the high voltage applied on the N-type source/drain region and on the P-type source/drain region is decreased. Therefore, the crowding electric force lines effect does not occur. Hence, it can provide a bulk breakdown near the N-type source/drain region and near the P-type source/drain region.  
       [0015] It is to be understood that both the foregoing general description and the following detailed description are exemplary. and are intended to provide further explanation of the invention as claimed. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0016] The accompanying drawings are included to provide a further understanding of the invention. and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and. together with the description. serve to explain the principles of the invention. In the drawings,  
     [0017]FIG. 1 is a schematic, cross-sectional view showing a portion of a conventional high-voltage device; and  
     [0018]FIGS. 2A through 2D are schematic. cross-sectional views of the process for manufacturing a high-voltage CMOS device in a preferred embodiment according to the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0019]FIGS. 2A through 2D are schematic. cross-sectional views of the process for manufacturing a high-voltage complementary metal-oxide semiconductor (CMOS) device in a preferred embodiment according to the invention.  
     [0020] As shown in FIG. 2A, a substrate  200  is provided. The substrate  200  possesses a well region  202   a  with a first conductive type and a well region  202   b  with a second conductive type. The dosages of the well regions  202   a  and  202   b  are each about 1×10 12 ˜1×10 13  atoms/cm 2 .  
     [0021] Thereafter, a drive-in process is performed. A pad oxide layer  206  and a patterned silicon nitride layer  208  are formed over the substrate  200  in sequence. The patterned silicon nitride layer  208  exposes portions of the pad oxide layer  206  above the well regions  202   a  and  202   b.  The exposed portions of the pad oxide layer  206  are used to form field oxide layers in the subsequent process.  
     [0022] A doped region  210   a  with the second conductive type and a doped region  210   b  with the first conductive type are respectively formed in the well regions  202   a  and  202   b  under the exposed portions of the pad oxide layer  206 . The dosages of the doped regions  210   a  and  210   b  are each about 1×10 12 ˜1×10 14  atoms/cm 2 . Field oxide layers  212   a  and  212   b  are respectively formed on the doped regions  210   a  and  210   b.    
     [0023] As shown in FIG. 2B, the patterned silicon nitride layer  208  and the pad oxide layer  206  are removed in sequence. A trench  215   a  is formed in every other space between the field oxide layers  210   a  in the substrate  200  while trenches are respectively formed in every other space between the field oxide layers  210   b  in the substrate  200 . An oxide layer  214  is formed over the substrate  200 . Portions of the oxide layer  214  respectively located in the trenches  215   a  and  215   b  are respectively denoted as linear layers  214   a  and  214   b.  The method for forming the oxide layer  214  can be thermal oxidation and the thickness of the oxide layer  214  is about 100-500 angstroms.  
     [0024] Oxide layers  216   a  and  216   b  are formed in the trenches  215   a  and  215   b  and fill the trenches  215   a  and  215   b.  The oxide layers  216   a  and  216   b  are used as shallow trench isolation structures. The method for forming the shallow trench isolation structures  216   a  and  216   b  comprises the steps of forming an oxide layer (not shown) on the oxide layer  214  with a thickness of about 5000-9000 angstroms by atmospheric pressure chemical vapor deposition (APCVD). and then performing a densification process to reinforce the compactness of the oxide layer in the trenches  215   a  and  215   b.  The densification process is performed in a temperature of about 1000 degrees centigrade for 10-30 minutes. A chemical-mechanical polishing (CMP) is performed to remove a portion of the oxide layer, thereby to expose the surface of the oxide layer  214  and to form the oxide layers  216   a  and  216   b.  The structure constructed by the field oxide layer  212   a,  the shallow trench isolation structure  216   a  and the field oxide layer  212   a  is denoted as an isolation region  217   a  (FIG. 2D). Simultaneously. the structure constructed by the field oxide layer  212   b,  the shallow trench isolation structure  216   b  and the field oxide layer  212   b  is denoted as an isolation region  217   b  (FIG. 2D).  
     [0025] As shown in FIG. 2C, a doped region  218   a  with the first conductive type is formed in the well region  202   a  beneath the shallow trench isolation structure  216   a  while a well region  218   b  with the first conductive type is formed in the well region  202   b  under the isolation region  217   b  (FIG. 2D). Each dosage of the doped region  218   a  and well region  218   b  is about 1×10 13  atoms/cm 2  Additionally the well region  218   b  expands from the interface between the well region  202   b  and the isolation region  217   b  into the well region  202   b  and laterally expands far away from a portion of the well region  202   b  between the isolation regions  217   b.    
     [0026] A well region  220   a  with the second conductive type is formed in the well region  202   a  beneath the isolation region  217   a  while a doped region  220   b  with the second conductive type is formed in the well region  218   b  under the shallow trench isolation structure  216   b.  The dosages of the well region  220   a  and doped region  220   b  are each about 1×10 13  atoms/cm 2 . Additionally, the well region  220   a  expands from the interface between the well region  202   a  and the isolation region  217   a  into the well region  202   a  and laterally expands far away from a portion of the well region  202   a  between the isolation regions  217   a.    
     [0027] As shown in FIG. 2D, an oxide layer (not shown) and a conductive layer (not shown) are formed over the substrate  200  in sequence. The conductive layer. the oxide layer and the oxide layer  214  layer are patterned to form a gate electrode  222   a  and a gate oxide layer  214   c  on the well region  202   a  between the isolation regions  217   a  and to form a gate electrode  222   b  and a gate oxide layer  214   d  on the well region  202   b  between the isolation regions  217   b.  The patterned conductive layer is transformed into the gate electrodes  222   a  and  222   b  and the patterned oxide layer and the patterned oxide layer  214  together form the gate oxide layers  214   c  and  214   d.  The gate structure  228   a  constructed by the gate electrode  222   a  and the gate oxide layer  214   c  is located on the well region  202   a  and laterally expands over a portion of the isolation regions  217   a.  The gate structure  228   b  constructed by the gate electrode  222   b  and the gate oxide layer  214   d  is located on the well region  202   b  and laterally expands over a portion of the isolation regions  217   b.    
     [0028] A source/drain region  224  with the second conductive type is formed in the well region  220   a  exposed by the gate structure  228   a  and the isolation regions  217   a.  The dosage of the source/drain region  224  is about 1×10 15  atoms/cm 2 .  
     [0029] A source/drain region  926  with the first conductive type is formed in the well regions  218   b  exposed by the gate structure  228   b  and the isolation regions  217   b.  Therefore, the manufacturing process for forming the high-voltage CMOS device is finished. The dosage of the source/drain region  226  is about 1×10 15  atoms/cm 2 .  
     [0030] Notably, when the first conductive type is N-type, the second conductive type is P-type. Simultaneously when the first conductive type is P-type, the second conductive type is N-type. The method according to the invention can be applied not only to the formation of a CMOS. but also to the formation of a single-type MOS, such as NMOS or PMOS.  
     [0031] In the invention. the well region  202   a  with the first conductive type is located in the substrate  200 . Several isolation regions  217   a  are located on the well region  202   a.  Each of the isolation regions  217   a  is constructed by two field oxide layers  212   a  on either side of one shallow trench isolation structure  216   a.  The gate structure  228   a  is positioned on the well region  202   a  between the isolation regions  217   a  and expands onto the isolation regions  217   a.  The source/drain region  224  with the second conductive type is located in the well region  202   a  exposed by the gate structure  228   a  and the isolation regions  217   a.  The doped region  210   a  with the second conductive type is located beneath each of the field oxide layers  210   a  and the doped region  218   a  with the first conductive type is located beneath each of the shallow trench isolation structures  216   a  in the well region  202   a.  The well region  220   a  with the second conductive type is located in the well region  202   a  under the isolation region  217   a  and the source/drain regions  224 .  
     [0032] In the invention, the depletion regions respectively exist between the doped region  218   a  and the well region  220   a  and between the doped region  220   b  and the well region  218   b.  Furthermore each depth of the well regions  220   a  and  218   b  is larger than that of the conventional N − -type doped regions  116  and  118 , so that the intensity of the electric field caused by the high voltage applied on the source/drain region  224  is decreased. Therefore, the crowding electric force lines effect does not occur. Hence. it can provide a bulk breakdown near the source/drain regions  224 .  
     [0033] Moreover, the distance between the source/drain region  224  is increased by using the method according to the invention so that the channel length can be greatly increased. Therefore, the short channel effect can be avoided and the method can be applied on the integration of the sub-quarter micron level technique.  
     [0034] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.