Patent Publication Number: US-11664425-B2

Title: P-type field effect transistor and method for fabricating the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application of U.S. application Ser. No. 16/836,953, filed on Apr. 1, 2020, which is a division of U.S. application Ser. No. 15/893,681, filed on Feb. 11, 2018. The contents of these applications are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a method for fabricating metal-oxide-semiconductor (MOS) transistor, and more particularly to a method of using ion implantation process to form channel layer in a substrate. 
     2. Description of the Prior Art 
     In current semiconductor industry, polysilicon has been widely used as a gap-filling material for fabricating gate electrode of metal-oxide-semiconductor (MOS) transistors. However, the conventional polysilicon gate also faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of gate dielectric layer, reduces gate capacitance, and worsens driving force of the devices. In replacing polysilicon gates, work function metals have been developed to serve as a control electrode working in conjunction with high-K gate dielectric layers. 
     Nevertheless, as semiconductor technology advances, gate structures employing work function materials soon reaches their physical and electrical limitation, causing side-effects including electrical instability and negative bias temperature instability (NBTI) effect. 
     NBTI effect is typically caused by accumulation of electrical potentials between silicon substrate and silicon oxide layers, which induces an effect when gate electrode is negatively biased. As PMOS transistors apply negative bias to generate electrons on metal gate adjacent to gate oxide, reject electrons on n-type substrate, and generate electron holes on n-type substrate and electron hole channel under gate structure thereby inducing electron holes of the source/drain region to be transmitted through this channel, NBTI effect is especially influential in CMOS devices containing PMOS structures. 
     SUMMARY OF THE INVENTION 
     According to an embodiment of the present invention, a method for fabricating a p-type field effect transistor (pFET) includes the steps of providing a substrate; performing an ion implantation process to implant germanium (Ge) into the substrate to form a channel region, wherein the channel region comprises silicon germanium (SiGe), a concentration of germanium is between 5×10 13  ions/cm 2  to 1×10 17  ions/cm 2 , an energy of the ion implantation process is between 0.5 KeV to 20 KeV, and a temperature of the ion implantation process is between 0° C. to 120° C.; performing an anneal process to divide the channel region into a top portion and a bottom portion, wherein a depth of the top portion is equal to a depth of the bottom portion; and forming a gate structure on the substrate. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 - 6    illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIGS.  1 - 6   ,  FIGS.  1 - 6    illustrate a method for fabricating a semiconductor device according to an embodiment of the present invention. As shown in  FIG.  1   , a substrate  12 , such as a silicon substrate or silicon-on-insulator (SOI) substrate is first provided, at least a transistor region such as a PMOS region used for preparing a p-type field effect transistor (FET) is defined on the substrate  12 , and isolation structures such as shallow trench isolation (STI) made of silicon oxide could be formed in the substrate  12  to separate the transistor region. 
     It should be noted that even though this embodiment pertains to the fabrication of a planar device, it would also be desirable to apply the following process to fabricate a non-planar FET device such as FinFET device. For instance, it would be desirable to form at least a fin-shaped structure on the substrate  12 , in which the bottom of the fin-shaped structure is surrounded by a shallow trench isolation (STI), which is also within the scope of the present invention. 
     According to an embodiment of the present invention, the fin-shaped structure could be obtained by a sidewall image transfer (SIT) process. For instance, a layout pattern is first input into a computer system and is modified through suitable calculation. The modified layout is then defined in a mask and further transferred to a layer of sacrificial layer on a substrate through a photolithographic and an etching process. In this way, several sacrificial layers distributed with a same spacing and of a same width are formed on a substrate. Each of the sacrificial layers may be stripe-shaped. Subsequently, a deposition process and an etching process are carried out such that spacers are formed on the sidewalls of the patterned sacrificial layers. In a next step, sacrificial layers can be removed completely by performing an etching process. Through the etching process, the pattern defined by the spacers can be transferred into the substrate underneath, and through additional fin cut processes, desirable pattern structures, such as stripe patterned fin-shaped structures could be obtained. 
     Alternatively, the fin-shaped structure could also be obtained by first forming a patterned mask (not shown) on the substrate,  12 , and through an etching process, the pattern of the patterned mask is transferred to the substrate  12  to form the fin-shaped structure. Moreover, the formation of the fin-shaped structure could also be accomplished by first forming a patterned hard mask (not shown) on the substrate  12 , and a semiconductor layer composed of silicon germanium is grown from the substrate  12  through exposed patterned hard mask via selective epitaxial growth process to form the corresponding fin-shaped structure. These approaches for forming fin-shaped structure are all within the scope of the present invention. 
     Next, a pad layer  14  is formed on the surface of the substrate  12 . In this embodiment, the pad layer  14  is preferably a single-layered structure made of dielectric material including but not limited to for example silicon oxide. It should be noted that even though the pad layer  14  in this embodiment pertains to be a single-layered structure, it would also be desirable to form a pad layer  14  composed of multiple dielectric layers selected from the group consisting of silicon oxide and silicon nitride, which is also within the scope of the present invention. 
     Next, an ion implantation process is conducted to implant ions through the pad layer  14  and into the substrate  12  to form a well region. Since the present invention pertains to fabricate a p-type FET, the ion implantation is preferably conducted to implant n-type dopants into the substrate  12  to form a n-well  16 . 
     Next, as shown in  FIG.  2   , another ion implantation process  18  is conducted to implant germanium ions through the pad layer  14  and into the substrate  12  to form a channel region  20  made of silicon germanium (SiGe). It should be noted that as germanium ions are implanted into the substrate  12  to form the channel region  20  the germanium ions within the channel region  20  are arranged according to a gradient distribution. For instance, the concentration of germanium ions closer to the junction or boundary between the pad layer  14  and the channel layer  20  is preferably higher than the concentration of germanium ions closer to the junction or boundary between the channel region  20  and the substrate  12 . Nevertheless, there is still no clearly separation between the higher germanium region and the lower germanium region at this stage. 
     Preferably, the concentration of germanium implanted through the ion implantation process  18  is preferably between 5×10 13  ions/cm 2  to 1×10 17  ions/cm 2  and the energy of the ion implantation process  18  is preferably between 0.5 KeV to 20 KeV. The ion implantation process  18  is preferably a low temperature implantation process, in which the process is preferably conducted at a temperature between 0° C. to 120° C. 
     Next, as shown in  FIG.  3   , an anneal process is conducted to activate the germanium ions within the channel region  20  and at the same time divide the channel region  20  into a top portion  22  and a bottom portion  24 . Preferably, the depth of the top portion  22  is equal to the depth of the bottom portion  24 , in which the depth of each of the top portion  22  and the bottom portion  24  is preferably between 13 Angstroms to 17 Angstroms or most preferably at around 15 Angstroms. 
     Moreover, the temperature of the anneal process is preferably greater than 1000° C. or more specifically between 1000° C. to 1200° C. and the germanium concentration of the bottom portion  24  is slightly lower than the germanium concentration of the top portion  22 , in which the germanium concentration of the top portion  22  is preferably between 0.9×10 22  ions/cm 3  to 1.1×10 22  ions/cm 3  or most preferably at around 1.0×10 22  ions/cm 3  and the germanium concentration of the bottom portion  24  is preferably between 0.9×10 18  ions/cm 3  to 1.1×10 18  ions/cm 3  or most preferably at around 1.0×10 18  ions/cm 3 . 
     Next, as shown in  FIG.  4   , an etching process is conducted to remove the pad layer  14  to expose the surface of the substrate  12  or channel region  20 . In this embodiment, the removal of the pad layer  14  could be accomplished by using an etchant including but not limited to for example diluted hydrofluoric acid (dHF) to fully remove the pad layer  14  on the surface of the substrate  12  and at the same time remove impurities from the substrate  12  surface. 
     Next, as shown in  FIG.  5   , a gate structure  26  or dummy gate could be formed on the surface of the substrate  12 . In this embodiment, the formation of the gate structure  26  could be accomplished by a gate first process, a high-k first approach from gate last process, or a high-k last approach from gate last process. Since this embodiment pertains to a high-k last approach, a gate dielectric layer or interfacial layer, a gate material layer made of polysilicon, and a selective hard mask could be formed sequentially on the substrate  12 , and a photo-etching process is then conducted by using a patterned resist (not shown) as mask to remove part of the gate material layer and part of the gate dielectric layer through single or multiple etching processes. After stripping the patterned resist, a gate structure  26  composed of a patterned gate dielectric layer  28  and a patterned material layer  30  are formed on the substrate  12 . 
     Next, a lightly doped drain  32  is formed in the substrate  12  adjacent to two sides of the gate structure  26 , at least a spacer  34  is formed on the sidewalls of the gate structure  26 , a source/drain region  36  and/or epitaxial layer is formed in the substrate  12  adjacent to two sides of the spacer  34 , and selective silicide layers (not shown) could be formed on the surface of the source/drain region  36 . In this embodiment, the spacer  34  could be a single spacer or a composite spacer, such as a spacer including but not limited to for example an offset spacer and a main spacer. Preferably, the offset spacer and the main spacer could include same material or different material while both the offset spacer and the main spacer could be made of material including but not limited to for example SiO 2 , SiN, SiON, SiCN, or combination thereof. Each of the lightly doped drain  32  and the source/drain region  36  could include dopants n-type dopants or p-type dopants depending on the type of device being fabricated. Since the present invention pertains to fabricate a p-type FET, both the lightly doped drain  32  and the source/drain region  36  in this embodiment include p-type dopants. 
     Next, a contact etch stop layer (CESL)  38  is formed on the gate structure  26  and an interlayer dielectric (ILD) layer  40  is formed on the CESL  38 . Next, a planarizing process such as CMP is conducted to remove part of the ILD layer  40  and part of the CESL  38  for exposing the gate material layer  30  made of polysilicon, in which the top surface of the gate material layer  30  is even with the top surface of the ILD layer  40 . 
     Next, as shown in  FIG.  6   , a replacement metal gate (RMG) process is conducted to transform the gate structure  26  into metal gate. For instance, the RMG process could be accomplished by first performing a selective dry etching or wet etching process using etchants including but not limited to for example ammonium hydroxide (NH 4 OH) or tetramethylammonium hydroxide (TMAH) to remove the gate material layer  30  and even gate dielectric layer  28  from the gate structure  26  for forming a recess (not shown) in the ILD layer  40 . 
     Next, a selective interfacial layer  42  or gate dielectric layer (not shown), a high-k dielectric layer  44 , a work function metal layer  46 , and a low resistance metal layer  48  are formed in the recesses, and a planarizing process such as CMP is conducted to remove part of low resistance metal layer  48 , part of work function metal layer  46 , and part of high-k dielectric layer  44  to form gate structure made of metal gate. In this embodiment, the gate structures or metal gate fabricated through high-k last process of a gate last process preferably includes an interfacial layer  42  or gate dielectric layer (not shown), a U-shaped high-k dielectric layer  44 , a U-shaped work function metal layer  46 , and a low resistance metal layer  48 . 
     In this embodiment, the high-k dielectric layer  44  is preferably selected from dielectric materials having dielectric constant (k value) larger than 4. For instance, the high-k dielectric layer  44  may be selected from hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), barium strontium titanate (Ba x Sr 1-x TiO 3 , BST) or a combination thereof. 
     In this embodiment, the work function metal layer  46  is formed for tuning the work function of the metal gate in accordance with the conductivity of the device. For an NMOS transistor, the work function metal layer  46  having a work function ranging between 3.9 eV and 4.3 eV may include titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or titanium aluminum carbide (TiAlC), but it is not limited thereto. For a PMOS transistor, the work function metal layer  46  having a work function ranging between 4.8 eV and 5.2 eV may include titanium nitride (TiN), tantalum nitride (TaN), tantalum carbide (TaC), but it is not limited thereto. An optional barrier layer (not shown) could be formed between the work function metal layer  46  and the low resistance metal layer  48 , in which the material of the barrier layer may include titanium (Ti), titanium nitride (TiN), tantalum (Ta) or tantalum nitride (TaN). Furthermore, the material of the low-resistance metal layer  48  may include copper (Cu), aluminum (Al), titanium aluminum (TiAl), cobalt tungsten phosphide (CoWP) or any combination thereof. 
     Referring again to  FIG.  6   , which further illustrates a structural view of a pFET according to an embodiment of the present invention. As shown in  FIG.  6   , the pFET includes a gate structure  26  composed of metal gate on the substrate  12 , a channel region  20  in the substrate  12  directly under the gate structure  26 , a lightly doped drain  32  in the substrate  12  adjacent to two sides of the gate structure  26 , and a source/drain region  36  in the substrate  12  adjacent to two sides of the spacer  34 . 
     Viewing from a more detailed perspective, the channel region  20  preferably composed of silicon germanium is divided into a top portion  22  and a bottom portion  24 , in which the concentration of germanium in the bottom portion  24  is lower than the concentration of germanium in the top portion  22 . In this embodiment, the germanium concentration of the top portion  22  is preferably between 0.9×10 22  ions/cm 3  to 1.1×10 22  ions/cm 3  or most preferably at around 1.0×10 22  ions/cm 3  and the germanium concentration of the bottom portion  24  is preferably between 0.9×10 18  ions/cm 3  to 1.1×10 18  ions/cm 3  or most preferably at around 1.0×10 18  ions/cm 3 . Moreover, the depth of the top portion  22  is preferably equal to the depth of the bottom portion  24 , in which the depth of each of the top portion  22  and the bottom portion  24  is preferably between 13 Angstroms to 17 Angstroms or most preferably at around 15 Angstroms. 
     Overall, the present invention discloses an approach to fabricate silicon germanium channel, which preferably forms a pad layer made of silicon oxide on the surface of the substrate, conducts an ion implantation process to implant germanium ions into the substrate to form a channel region, and then performs an anneal process to separate the germanium ions within the channel region into a top portion and a bottom portion, in which the concentration of germanium in the bottom portion is preferably lower than the concentration of germanium in the top portion. By using this approach of segregate germanium concentration in the channel region, it would be desirable to improve the issue of NBTI in pFET devices when negative bias is applied. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.