Patent Publication Number: US-2016233017-A1

Title: Inductor array chip and dc-to-dc converter module using the same

Description:
FIELD OF THE DISCLOSURE 
     The present disclosure relates to an inductor array chip, and in particular, relates to an inductor array chip including a multilayer body formed by laminating a plurality of ceramic sheets at least some of which have magnetism and a plurality of inductors provided in the multilayer body and having a plurality of inductance values at least one of which is different from other inductance values. 
     The disclosure also relates to a DC-to-DC converter module, and in particular, relates to a DC-to-DC converter module including a multilayer body formed by laminating a plurality of ceramic sheets at least some of which have magnetism, a plurality of inductors provided in the multilayer body and having a plurality of inductance values at least one of which is different from other inductance values, and a switching integrated circuit (IC) mounted on the multilayer body and connected to the plurality of inductors. 
     DESCRIPTION OF THE RELATED ART 
     A multi-channel DC-to-DC converter in which a plurality of inductors are provided in a single multilayer body and a switching IC is mounted on a top surface of the multilayer body and that outputs a plurality of direct-current (DC) voltages, which are different from one another, at the same time has been known. In the multi-channel DC-to-DC converter, specifications of output voltages and/or output currents (load currents) are different from channel to channel. Therefore, different inductance values are also required for the inductors provided in the multilayer body.
     Patent Document 1: International Publication No. 2012/169242   

     BRIEF SUMMARY OF THE DISCLOSURE 
     In order to make inductance values different among channels, wiring widths and the numbers of coil conductor patterns formed on respective laminated ceramic sheets are required to be changed among the channels. It should be noted that the change causes the deterioration in the flatness of the multilayer body undesirably. 
     Further, magnetic lines generated on inductors tend to bend to the inner side of the inductors in the vicinity of both ends of the inductors. The unintended bending causes the deterioration in the inductor characteristics. 
     In consideration with the circumstances, a main object of the disclosure is to provide an inductor array chip and a DC-to-DC converter module that can keep flatness of a multilayer body in which a plurality of inductors having inductance values at least one of which is different from other inductance values are provided, and can suppress the deterioration in the inductor characteristics. 
     An inductor array chip according to an aspect of the disclosure includes a multilayer body formed by laminating a plurality of ceramic sheets at least some of which have magnetism, and a plurality of inductors provided in the multilayer body and having a plurality of inductance values at least one of which is different from other inductance values, wherein each of the plurality of inductors is configured by a plurality of coiled conductors which are provided between the plurality of ceramic sheets and the number of which is common to the plurality of inductors, a first via hole conductor which spirally connects the plurality of coiled conductors, and a second via hole conductor which additionally connects at least two coiled conductors of the plurality of coiled conductors, which are close to an outermost layer of the multilayer body. 
     It is preferable that the at least two coiled conductors be coiled conductors respectively close to two outermost layers forming the multilayer body. 
     It is preferable that respective positions of the plurality of coiled conductors in a lamination direction be different between at least two of the plurality of inductors. 
     A DC-to-DC converter module according to another aspect of the disclosure includes a multilayer body formed by laminating a plurality of ceramic sheets at least some of which have magnetism, a plurality of inductors provided in the multilayer body and having a plurality of inductance values at least one of which is different from other inductance values, and a switching IC mounted on the multilayer body and connected to the plurality of inductors, wherein each of the plurality of inductors is configured by a plurality of coiled conductors which are provided between the plurality of ceramic sheets and the number of which is common to the plurality of inductors, a first via hole conductor which spirally connects the plurality of coiled conductors, and a second via hole conductor which additionally connects at least two coiled conductors of the plurality of coiled conductors, which are close to an outermost layer of the multilayer body. 
     The coiled conductors forming each inductor are provided between the laminated ceramic sheets and the number of coiled conductors is common to the inductors. With this configuration, the flatness of the multilayer body is kept. 
     Further, the at least two coiled conductors forming each inductor are additionally connected by the second via hole conductor. With this configuration, an inductor value can be arbitrarily adjusted. 
     Moreover, the coiled conductors which are connected by the second via hole conductor are provided at positions close to the outermost layer of the multilayer body. With this configuration, a phenomenon that magnetic lines generated on each inductor bend to the inner side of a wound body in the vicinity of the outermost layer can be suppressed, and the deterioration in the inductor characteristics can be suppressed eventually. 
     The above-mentioned object, another object, characteristics, and advantages of the disclosure will be further clarified from the following detail description of embodiments, which are made with reference to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1  is an exploded view illustrating a part of an inductor array chip in an exploded state in an embodiment. 
         FIG. 2  is an exploded view illustrating another part of the inductor array chip in the exploded state in the embodiment. 
         FIG. 3A  is a plan view illustrating an example of a ceramic sheet SH 0  forming the inductor array chip and  FIG. 3B  is a plan view illustrating an example of a ceramic sheet SH 1  forming the inductor array chip. 
         FIG. 4A  is a plan view illustrating an example of a ceramic sheet SH 2  forming the inductor array chip and  FIG. 4B  is a plan view illustrating an example of a ceramic sheet SH 3 , SH 5  or SH 9  forming the inductor array chip. 
         FIG. 5A  is a plan view illustrating an example of a ceramic sheet SH 7  forming the inductor array chip and  FIG. 5B  is a plan view illustrating an example of a ceramic sheet SH 11  forming the inductor array chip. 
         FIG. 6A  is a plan view illustrating an example of a ceramic sheet SH 6 , SH 8  or SH 10  forming the inductor array chip and  FIG. 6B  is a plan view illustrating an example of a ceramic sheet SH 4  forming the inductor array chip. 
         FIG. 7A  is a plan view illustrating an example of a ceramic sheet SH 12  forming the inductor array chip and  FIG. 7B  is a plan view illustrating an example of a ceramic sheet SH 13  forming the inductor array chip. 
         FIG. 8  is a perspective view illustrating outer appearance of the inductor array chip in the embodiment. 
         FIG. 9A  is a cross-sectional view cut along a line A-A of the inductor array chip as illustrated in  FIG. 8  and  FIG. 9B  is a cross-sectional view cut along a line B-B of the inductor array chip as illustrated in  FIG. 8 . 
         FIG. 10A  is a graphic explanation view illustrating main parts of the laminated ceramic sheets SH 10  and SH 11  and  FIG. 10B  is a graphic explanation view illustrating main parts of the laminated ceramic sheets SH 3  and SH 4 . 
         FIG. 11A  is a circuit diagram illustrating a partial inductor formed by coil conductor patterns CP 103  and CP 113 , a via hole conductor VH 113   b , and an additional via hole conductor VH 113   c  and  FIG. 11B  is a circuit diagram illustrating a partial inductor formed by coil conductor patterns CP 31  and CP 41 , a via hole conductor VH 41   b , and an additional via hole conductor VH 41   c.    
         FIG. 12  is a graphic explanation view illustrating an example of magnetic lines generated on an inductor IDT 1 . 
         FIG. 13A  is a graphic explanation view illustrating a part of the configuration of an inductor provided on an inductor array chip in another embodiment and  FIG. 13B  is a graphic explanation view illustrating a part of the configuration of an inductor provided on an inductor array chip in still another embodiment. 
         FIG. 14A  is a cross-sectional view illustrating a cross section of an inductor array chip in still another embodiment and  FIG. 14B  is a cross-sectional view illustrating another cross section of the inductor array chip in still another embodiment. 
         FIG. 15  is a graphic explanation view schematically illustrating a part of the configuration of the inductor in the embodiment. 
         FIG. 16  is a graphic explanation view illustrating a path of an electric current flowing through the inductor as illustrated in  FIG. 15 . 
         FIG. 17  is a graphic explanation view schematically illustrating a part of the configuration of an inductor in another embodiment. 
         FIG. 18  is a graphic explanation view illustrating a path of an electric current flowing through the inductor as illustrated in  FIG. 17 . 
         FIG. 19  is a perspective view illustrating a DC-to-DC converter module in another embodiment. 
         FIG. 20  is a circuit diagram illustrating an example of the configuration of the DC-to-DC converter module as illustrated in  FIG. 19 . 
     
    
    
     DETAILED DESCRIPTION OF THE DISCLOSURE 
     With reference to  FIG. 1  and  FIG. 2 , an inductor array chip  10  in an embodiment is applied to a multi-channel DC-to-DC converter which outputs a plurality of DC voltages at least one voltage value of which is different from other voltage values or a plurality of DC currents at least one current value of which is different from other current values at the same time, and includes laminated ceramic sheets SH 0  to SH 13  having rectangular main surfaces. Sizes of the respective main surfaces of the ceramic sheets SH 0  to SH 13  are identical to one another and the ceramic sheets SH 0  to SH 13  are laminated in this order. The ceramic sheets SH 0 , SH 7 , and SH 13  include non-magnetic substances whereas other ceramic sheets SH 1  to SH 6  and SH 8  to SH 12  include magnetic substances. 
     A multilayer body  12  has a rectangular parallelepiped shape, the ceramic sheets SH 1  to SH 6  form a magnetic layer  12   a , the ceramic sheets SH 8  to SH 12  form a magnetic layer  12   b , the ceramic sheet SH 0  forms a non-magnetic layer  12   c , the ceramic sheet SH 7  forms a non-magnetic layer  12   d , and the ceramic sheet SH 13  forms a non-magnetic layer  12   e.    
     That is to say, the multilayer body  12  configuring the inductor array chip  10  has a lamination configuration in which the magnetic layer  12   a  is held between the non-magnetic layers  12   c  and  12   d  and the magnetic layer  12   b  is held between the non-magnetic layers  12   d  and  12   e . The long sides and the short sides of the rectangle forming the main surface (=the upper surface or the lower surface) of the multilayer body  12  extend along an X axis and a Y axis, and the thickness of the multilayer body  12  is increased along a Z axis. 
     With reference to  FIG. 3A , via hole conductors EL 01   a  to EL 01   c , EL 02   a  to EL 02   c , EL 03   a  to EL 03   c , and EL 04   a  to EL 04   c  reaching the lower surface of the ceramic sheet SH 0  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 01   a , EL 01   b , EL 02   a , and EL 02   b  are aligned along the long side at the positive side in the Y-axis direction and the via hole conductors EL 03   a , EL 03   b , EL 04   a , and EL 04   b  are aligned along the long side at the negative side in the Y-axis direction. The via hole conductors EL 01   c  and EL 03   c  are aligned along the short side at the negative side in the X-axis direction and the via hole conductors EL 02   c  and EL 04   c  are aligned along the short side at the positive side in the X-axis direction. 
     The via hole conductors EL 01   a  to EL 01   c  correspond to a channel CH 1  and are gathered in the vicinity of a corner portion at the negative side in the X-axis direction and at the positive side in the Y-axis direction. The via hole conductors EL 02   a  to EL 02   c  correspond to a channel CH 2  and are gathered in the vicinity of a corner portion at the positive side in the X-axis direction and at the positive side in the Y-axis direction. The via hole conductors EL 03   a  to EL 03   c  correspond to a channel CH 3  and are gathered in the vicinity of a corner portion at the negative side in the X-axis direction and at the negative side in the Y-axis direction. The via hole conductors EL 04   a  to EL 04   c  correspond to a channel CH 4  and are gathered in the vicinity of a corner portion at the positive side in the X-axis direction and at the negative side in the Y-axis direction. 
     With reference to  FIG. 3B , via hole conductors EL 11   a  to EL 11   c , EL 12   a  to EL 12   c , EL 13   a  to EL 13   c , and EL 14   a  to EL 14   c  reaching the lower surface of the ceramic sheet SH 1  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 11   a  to EL 11   c  correspond to the channel CH 1  and the via hole conductors EL 12   a  to EL 12   c  correspond to the channel CH 2 . The via hole conductors EL 13   a  to EL 13   c  correspond to the channel CH 3  and the via hole conductors EL 14   a  to EL 14   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 1  is laminated on the ceramic sheet SH 0 , the via hole conductors EL 11   a  to EL 11   c , EL 12   a  to EL 12   c , EL 13   a  to EL 13   c , and EL 14   a  to EL 14   c  overlap with the via hole conductors EL 01   a  to EL 01   c , EL 02   a  to EL 02   c , EL 03   a  to EL 03   c , and EL 04   a  to EL 04   c , respectively. 
     With reference to  FIG. 4A , via hole conductors EL 21   a  to EL 21   c , EL 22   a  to EL 22   c , EL 23   a  to EL 23   c , and EL 24   a  to EL 24   c  reaching the lower surface of the ceramic sheet SH 2  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 21   a  to EL 21   c  correspond to the channel CH 1  and the via hole conductors EL 22   a  to EL 22   c  correspond to the channel CH 2 . The via hole conductors EL 23   a  to EL 23   c  correspond to the channel CH 3  and the via hole conductors EL 24   a  to EL 24   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 2  is laminated on the ceramic sheet SH 1 , the via hole conductors EL 21   a  to EL 21   c , EL 22   a  to EL 22   c , EL 23   a  to EL 23   c , and EL 24   a  to EL 24   c  overlap with the via hole conductors EL 11   a  to EL 11   c , EL 12   a  to EL 12   c , EL 13   a  to EL 13   c , and EL 14   a  to EL 14   c , respectively. 
     Coil conductor patterns CP 21  to CP 24  corresponding to the channels CH 1  to CH 4 , respectively, are also formed on the upper surface of the ceramic sheet SH 2 . The coil conductor pattern CP 21  is provided in a region at the negative side in the X-axis direction and at the positive side in the Y-axis direction, that is, in an upper left region and the coil conductor pattern CP 22  is provided in a region at the positive side in the X-axis direction and at the positive side in the Y-axis direction, that is, in an upper right region. Further, the coil conductor pattern CP 23  is provided in a region at the negative side in the X-axis direction and at the negative side in the Y-axis direction, that is, in a lower left region and the coil conductor pattern CP 24  is provided in a region at the positive side in the X-axis direction and at the negative side in the Y-axis direction, that is, in a lower right region. 
     When partial conductor patterns belonging to regions of the respective coil conductor patterns CP 21  to CP 24 , which are surrounded by dashed lines, are defined as “extra conductor patterns”, the respective coil conductor patterns CP 21  to CP 24  form loops while excluding the extra conductor patterns. 
     The loop formed by the coil conductor pattern CP 21  extends in the counterclockwise direction while a substantially center position in the upper left region is set to a starting end and a slightly upper left position relative to the starting end is set to a terminating end. The loop formed by the coil conductor pattern CP 22  extends in the clockwise direction while a substantially center position in the upper right region is set to a starting end and a slightly upper right position relative to the starting end is set to a terminating end. 
     The loop formed by the coil conductor pattern CP 23  extends in the clockwise direction while a substantially center position in the lower left region is set to a starting end and a slightly lower right position relative to the starting end is set to a terminating end. The loop formed by the coil conductor pattern CP 24  extends in the counterclockwise direction while a substantially center position in the lower right region is set to a starting end and a slightly upper right position relative to the starting end is set to a terminating end. 
     With reference to  FIG. 4B , via hole conductors EL 31   a  to EL 31   c , EL 32   a  to EL 32   c , EL 33   a  to EL 33   c , and EL 34   a  to EL 34   c  reaching the lower surface of the ceramic sheet SH 3  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 31   a  to EL 31   c  correspond to the channel CH 1  and the via hole conductors EL 32   a  to EL 32   c  correspond to the channel CH 2 . The via hole conductors EL 33   a  to EL 33   c  correspond to the channel CH 3  and the via hole conductors EL 34   a  to EL 34   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 3  is laminated on the ceramic sheet SH 2 , the via hole conductors EL 31   a  to EL 31   c , EL 32   a  to EL 32   c , EL 33   a  to EL 33   c , and EL 34   a  to EL 34   c  overlap with the via hole conductors EL 21   a  to EL 21   c , EL 22   a  to EL 22   c , EL 23   a  to EL 23   c , and EL 24   a  to EL 24   c , respectively. 
     Via hole conductors VH 31   a  to VH 34   a  corresponding to the channels CH 1  to CH 4 , respectively, are also formed on the upper surface of the ceramic sheet SH 3 . When observed from the lamination direction in a state where the ceramic sheet SH 3  is laminated on the ceramic sheet SH 2 , the via hole conductor VH 31   a  overlaps with the starting end of the loop formed by the coil conductor pattern CP 21 , the via hole conductor VH 32   a  overlaps with the starting end of the loop formed by the coil conductor pattern CP 22 , the via hole conductor VH 33   a  overlaps with the starting end of the loop formed by the coil conductor pattern CP 23 , and the via hole conductor VH 34   a  overlaps with the starting end of the loop formed by the coil conductor pattern CP 24 . 
     Coil conductor patterns CP 31  to CP 34  corresponding to the channels CH 1  to CH 4 , respectively, are also formed on the upper surface of the ceramic sheet SH 3 . The coil conductor pattern CP 31  is provided in the upper left region in a loop form and the coil conductor pattern CP 32  is provided in the upper right region in a loop form. The coil conductor pattern CP 33  is provided in the lower left region in a loop form and the coil conductor pattern CP 34  is provided in the lower right region in a loop form. 
     The coil conductor pattern CP 31  extends in the counterclockwise direction around the via hole conductor VH 31   a  while a slightly upper left position relative to the via hole conductor VH 31   a  is set to a starting end and an upper left position of the upper left region is set to a terminating end. The coil conductor pattern CP 32  extends in the clockwise direction around the via hole conductor VH 32   a  while a slightly upper right position relative to the via hole conductor VH 32   a  is set to a starting end and an upper right position of the upper right region is set to a terminating end. 
     The coil conductor pattern CP 33  extends in the clockwise direction around the via hole conductor VH 33   a  while a lower right position relative to the via hole conductor VH 33   a  is set to a starting end and a lower left position of the lower left region is set to a terminating end. The coil conductor pattern CP 34  extends in the counterclockwise direction around the via hole conductor VH 34   a  while an upper right position relative to the via hole conductor VH 34   a  is set to a starting end and an upper left position of the lower right region is set to a terminating end. 
     Via hole conductors VH 31   b  to VH 34   b  corresponding to the channels CH 1  to CH 4 , respectively, are further formed on the upper surface of the ceramic sheet SH 3 . The via hole conductor VH 31   b  is provided at the starting end of the coil conductor pattern CP 31  and the via hole conductor VH 32   b  is provided at the starting end of the coil conductor pattern CP 32 . The via hole conductor VH 33   b  is provided at the starting end of the coil conductor pattern CP 33  and the via hole conductor VH 34   b  is provided at the starting end of the coil conductor pattern CP 34 . 
     The structures of via hole conductors and coil conductor patterns provided on the ceramic sheet SH 5  and the SH 9  are the same as those of the via hole conductors and the coil conductor patterns provided on the ceramic sheet SH 3 . Therefore, an upper-order one digit of two-digit numbers forming reference numerals, which is “3”, is replaced by “5” and “9” and overlapped description is omitted. 
     The ceramic sheet SH 7  as illustrated in  FIG. 5A  includes the non-magnetic substance as described above. It should be noted that the structures of via hole conductors and coil conductor patterns provided on the ceramic sheet SH 7  are also the same as those of the via hole conductors and the coil conductor patterns provided on the ceramic sheet SH 3 . Therefore, the upper-order one digit of the two-digit numbers forming the reference numerals, which is “3”, is replaced by “7” and overlapped description is omitted. 
     With reference to  FIG. 5B , the structures of via hole conductors and coil conductor patterns provided on the ceramic sheet SH 11  are substantially the same as those of the via hole conductors and the coil conductor patterns provided on the ceramic sheet SH 3 . Therefore, the upper-order one digit of the two-digit numbers forming the reference numerals, which is “3”, is replaced by “11” and overlapped description relating to the same configuration is omitted. 
     The ceramic sheet SH 11  is different from the ceramic sheet SH 3  in a point that additional via hole conductors VH 111   c  to VH 114   c  reaching the lower surface of the ceramic sheet SH 111  from the upper surface thereof are added. The additional via hole conductor VH 111   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 111  and overlapping with the coil conductor pattern CP 111 . The additional via hole conductor VH 112   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 112  and overlapping with the coil conductor pattern CP 112 . The additional via hole conductor VH 113   c  is provided at a terminating end position of a coil conductor pattern CP 113 . The additional via hole conductor VH 114   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 114  and overlapping with the coil conductor pattern CP 114 . 
     With reference to  FIG. 6A , via hole conductors EL 61   a  to EL 61   c , EL 62   a  to EL 62   c , EL 63   a  to EL 63   c , and EL 64   a  to EL 64   c  reaching the lower surface of the ceramic sheet SH 6  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 61   a  to EL 61   c  correspond to the channel CH 1  and the via hole conductors EL 62   a  to EL 62   c  correspond to the channel CH 2 . The via hole conductors EL 63   a  to EL 63   c  correspond to the channel CH 3  and the via hole conductors EL 64   a  to EL 64   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 6  is laminated on the ceramic sheet SH 5 , the via hole conductors EL 61   a  to EL 61   c , EL 62   a  to EL 62   c , EL 63   a  to EL 63   c , and EL 64   a  to EL 64   c  overlap with the via hole conductors EL 51   a  to EL 51   c , EL 52   a  to EL 52   c , EL 53   a  to EL 53   c , and EL 54   a  to EL 54   c , respectively. 
     Via hole conductors VH 61   a  to VH 64   a  corresponding to the channels CH 1  to CH 4 , respectively, are also formed on the upper surface of the ceramic sheet SH 6 . When observed from the lamination direction in a state where the ceramic sheet SH 6  is laminated on the ceramic sheet SH 5 , the via hole conductors VH 61   a  to VH 64   a  overlap with the via hole conductors VH 51   a  to VH 54   a , respectively. 
     Coil conductor patterns CP 61  to CP 64  corresponding to the channels CH 1  to CH 4 , respectively, are also formed on the upper surface of the ceramic sheet SH 6 . The coil conductor pattern CP 61  is provided in the upper left region in a loop form and the coil conductor pattern CP 62  is provided in the upper right region in a loop form. The coil conductor pattern CP 63  is provided in the lower left region in a loop form and the coil conductor pattern CP 64  is provided in the lower right region in a loop form. 
     The coil conductor pattern CP 61  extends in the counterclockwise direction around the via hole conductor VH 61   a  while an upper left position of the upper left region is set to a starting end and an upper left position relative to the via hole conductor VH 61   a  is set to a terminating end. The coil conductor pattern CP 62  extends in the clockwise direction around the via hole conductor VH 62   a  while an upper right position of the upper right region is set to a starting end and an upper right position relative to the via hole conductor VH 62   a  is set to a terminating end. 
     The coil conductor pattern CP 63  extends in the clockwise direction around the via hole conductor VH 63   a  while a lower left position of the lower left region is set to a starting end and a lower right position relative to the via hole conductor VH 63   a  is set to a terminating end. The coil conductor pattern CP 64  extends in the counterclockwise direction around the via hole conductor VH 64   a  while an upper left position of the lower right region is set to a starting end and an upper right position relative to the via hole conductor VH 64   a  is set to a terminating end. 
     Via hole conductors VH 6   lb  to VH 64   b  corresponding to the channels CH 1  to CH 4 , respectively, are further formed on the upper surface of the ceramic sheet SH 6 . The via hole conductor VH 6   lb  is provided at the starting end of the coil conductor pattern CP 61  and the via hole conductor VH 62   b  is provided at the starting end of the coil conductor pattern CP 62 . The via hole conductor VH 63   b  is provided at the starting end of the coil conductor pattern CP 63  and the via hole conductor VH 64   b  is provided at the starting end of the coil conductor pattern CP 64 . 
     The structures of via hole conductors and coil conductor patterns provided on the ceramic sheet SH 8  and SH 10  are the same as those of the via hole conductors and the coil conductor patterns provided on the ceramic sheet SH 6 . Therefore, an upper-order one digit of two-digit numbers forming reference numerals, which is “6”, is replaced by “8” and “10” and overlapped description is omitted. 
     With reference to  FIG. 6B , the structures of via hole conductors and coil conductor patterns provided on the ceramic sheet SH 4  are substantially the same as those of the via hole conductors and the coil conductor patterns provided on the ceramic sheet SH 6 . Therefore, the upper-order one digit of the two-digit numbers forming the reference numerals, which is “6”, is replaced by “4” and overlapped description relating to the same configuration is omitted. 
     The ceramic sheet SH 4  is different from the ceramic sheet SH 6  in a point that additional via hole conductors VH 41   c  to VH 44   c  reaching the lower surface of the ceramic sheet SH 4  from the upper surface thereof are added. The additional via hole conductor VH 41   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 41  and overlapping with the coil conductor pattern CP 41 . The additional via hole conductor VH 42   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 42  and overlapping with the coil conductor pattern CP 42 . 
     The additional via hole conductor VH 43   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 43  and overlapping with the coil conductor pattern CP 43 . The additional via hole conductor VH 44   c  is provided at a position different from a starting end position and a terminating end position of a coil conductor pattern CP 44  and overlapping with the coil conductor pattern CP 44 . 
     With reference to  FIG. 7A , via hole conductors EL 121   a  to EL 121   c , EL 122   a  to EL 122   c , EL 123   a  to EL 123   c , and EL 124   a  to EL 124   c  reaching the lower surface of the ceramic sheet SH 12  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 121   a  to EL 121   c  correspond to the channel CH 1  and the via hole conductors EL 122   a  to EL 122   c  correspond to the channel CH 2 . The via hole conductors EL 123   a  to EL 123   c  correspond to the channel CH 3  and the via hole conductors EL 124   a  to EL 124   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 12  is laminated on the ceramic sheet SH 11 , the via hole conductors EL 121   a  to EL 121   c , EL 122   a  to EL 122   c , EL 123   a  to EL 123   c , and EL 124   a  to EL 124   c  overlap with the via hole conductors EL 111   a  to EL 111   c , EL 112   a  to EL 112   c , EL 113   a  to EL 113   c , and EL 114   a  to EL 114   c , respectively. 
     Via hole conductors VH 121   a  to VH 124   a  and via hole conductors VH 121   b  to VH 124   b  are also formed on the upper surface of the ceramic sheet SH 12 . The via hole conductors VH 121   a  and VH 121   b  correspond to the channel CH 1 , the via hole conductor VH 122   a  and VH 122   b  correspond to the channel CH 2 , the via hole conductor VH 123   a  and VH 123   b  correspond to the channel CH 3 , and via hole conductor VH 124   a  and VH 124   b  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 12  is laminated on the ceramic sheet SH 11 , the via hole conductors VH 121   a  to VH 124   a  overlap with the via hole conductors VH 111   a  to VH 114   a , respectively. The via hole conductor VH 121   b  overlaps with the terminating end of the coil conductor pattern CP 111 , the via hole conductor VH 122   b  overlaps with the terminating end of the coil conductor pattern CP 112 , the via hole conductor VH 123   b  overlaps with the terminating end of the coil conductor pattern CP 113 , and the via hole conductor VH 124   b  overlaps with the terminating end of the coil conductor pattern CP 114 . 
     With reference to  FIG. 7B , via hole conductors EL 131   a  to EL 131   c , EL 132   a  to EL 132   c , EL 133   a  to EL 133   c , and EL 134   a  to EL 134   c  reaching the lower surface of the ceramic sheet SH 13  are formed on end portions or edge portions of the upper surface thereof. The via hole conductors EL 131   a  to EL 131   c  correspond to the channel CH 1  and the via hole conductors EL 132   a  to EL 132   c  correspond to the channel CH 2 . The via hole conductors EL 133   a  to EL 133   c  correspond to the channel CH 3  and the via hole conductors EL 134   a  to EL 134   c  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 13  is laminated on the ceramic sheet SH 12 , the via hole conductors EL 131   a  to EL 131   c , EL 132   a  to EL 132   c , EL 133   a  to EL 133   c , and EL 134   a  to EL 134   c  overlap with the via hole conductors EL 121   a  to EL 121   c , EL 122   a  to EL 122   c , EL 123   a  to EL 123   c , and EL 124   a  to EL 124   c , respectively. 
     Via hole conductors VH 131   a  to VH 134   a  and via hole conductors VH 131   b  to VH 134   b  are also formed on the upper surface of the ceramic sheet SH 13 . The via hole conductors VH 131   a  and VH 131   b  correspond to the channel CH 1 , the via hole conductors VH 132   a  and VH 132   b  correspond to the channel CH 2 , the via hole conductors VH 133   a  and VH 133   b  correspond to the channel CH 3 , and the via hole conductors VH 134   a  and VH 134   b  correspond to the channel CH 4 . 
     When observed from the lamination direction in a state where the ceramic sheet SH 13  is laminated on the ceramic sheet SH 12 , the via hole conductors VH 131   a  to VH 134   a  overlap with the via hole conductors VH 121   a  to VH 124   a , respectively, and the via hole conductors VH 131   b  to VH 134   b  overlap with the via hole conductors VH 121   b  to VH 124   b , respectively. 
     Pad electrodes PD 1   a  to PD 4   a  and PD 1   b  to PD 4   b  are further formed on the upper surface of the ceramic sheet SH 13 . The pad electrodes PD 1   a  to PD 4   a  are provided at positions covering the via hole conductors VH 131   a  to VH 134   a  and the pad electrodes PD 1   b  to PD 4   b  are provided at positions covering the via hole conductors VH 131   b  to VH 134   b.    
     The ceramic sheets SH 0  to SH 13  are configured as described above. With this configuration, the coil conductor patterns CP 21  to CP 111  are spirally connected by the via hole conductor VH 31   a  to VH 131   a  and VH 31   b  to VH 131   b  and the coil conductor patterns CP 22  to CP 112  are spirally connected by the via hole conductors VH 32   a  to VH 132   a  and VH 32   b  to VH 132   b . Further, the coil conductor patterns CP 23  to CP 113  are spirally connected by the via hole conductors VH 33   a  to VH 133   a  and VH 33   b  to VH 133   b  and the coil conductor patterns CP 24  to CP 114  are spirally connected by the via hole conductors VH 34   a  to VH 134   a  and VH 34   b  to VH 134   b.    
     When the ceramic sheets SH 0  to SH 13  are laminated, the inductor array chip  10  as illustrated in  FIG. 8  is produced. An A-A cross section and a B-B cross section of the inductor array chip  10  have the configurations as illustrated in  FIG. 9A  and  FIG. 9B , respectively. As is seen from  FIG. 9A  and  FIG. 9B , four inductors IDT 1  to IDT 4  wound about the Z axis as winding axes are formed in the inductor array chip  10 . 
     It should be noted that passive elements such as a capacitor and a resistive element and active elements such as an IC and a field effect transistor (FET) (not illustrated) are mounted on the top surface of the ceramic sheet SH 13 . These elements are connected to the pad electrodes PD 1   a  to PD 4   a , and PD 1   b  to PD 4   b  and the via hole conductors EL 131   a  to EL 131   c , EL 132   a  to EL 132   c , EL 133   a  to EL 133   c , and EL 134   a  to EL 134   c.    
     In this embodiment, the coil conductor patterns CP 101  and CP 111  are additionally connected by the additional via hole conductor VH 111   c , the coil conductor patterns CP 102  and CP 112  are additionally connected by the additional via hole conductor VH 112   c , the coil conductor patterns CP 103  and CP 113  are additionally connected by the additional via hole conductor VH 113   c , and the coil conductor patterns CP 104  and CP 114  are additionally connected by the additional via hole conductor VH 114   c  (see  FIG. 10A ). 
     Further, the coil conductor patterns CP 31  and CP 41  are additionally connected by the additional via hole conductor VH 41   c , the coil conductor patterns CP 32  and CP 42  are additionally connected by the additional via hole conductor VH 42   c , the coil conductor patterns CP 33  and CP 43  are additionally connected by the additional via hole conductor VH 43   c , and the coil conductor patterns CP 34  and CP 44  are additionally connected by the additional via hole conductor VH 44   c  (see  FIG. 10B ). 
     An inductance value of the inductor IDT 1  is finely adjusted by the additional via hole conductors VH 4   lc  and VH 111   c , an inductance value of the inductor IDT 2  is finely adjusted by the additional via hole conductors VH 42   c  and VH 112   c , an inductance value of the inductor IDT 3  is finely adjusted by the additional via hole conductors VH 43   c  and VH 113   c , and an inductance value of the inductor IDT 4  is finely adjusted by the additional via hole conductors VH 44   c  and VH 114   c.    
     With this, the inductance values can be set to desired values without changing the wiring widths or the thicknesses of the coil conductor patterns CP 21  to CP 111 , CP 22  to CP 112 , CP 23  to CP 113 , and CP 24  to CP 114  or the number of coil conductor patterns (that is, without deteriorating the flatness of the multilayer body  12 ). 
     For example, when an inductor component of the coil conductor pattern CP 103  is defined as “Lcp 103 ”, an inductor component of the coil conductor pattern CP 113  is defined as “Lcp 113 ”, an inductor component of the via hole conductor VH 113   b  is defined as “Lvh 113   b ”, and an inductor component of the additional via hole conductor VH 113   c  is defined as “Lvh 113   c ”, these inductor components are connected as illustrated in  FIG. 11A . That is to say, the inductor components Lcp 103 , Lvh 113   b , and Lcp 113  are connected in series and the inductor component Lvh 113   c  is connected to the three inductor components in parallel or in a short-circuit state. 
     Further, when an inductor component of the coil conductor pattern CP 31  is defined as “Lcp 31 ”, an inductor component of the coil conductor pattern CP 41  is defined as “Lcp 41 ”, an inductor component of the via hole conductor VH 4   lb  is defined as “Lvh 41   b ”, and an inductor component of the additional via hole conductor VH 41   c  is defined as “Lvh 41   c ”, these inductor components are connected as illustrated in  FIG. 11B . That is to say, the inductor components Lcp 31 , Lvh 41   b , and Lcp 41  are connected in series and the inductor component Lvh 41   c  is connected to a part of these inductor components in parallel or in a short-circuit state. 
     For example, magnetic lines are generated on the inductor IDT 1  as illustrated in  FIG. 12 . That is to say, the magnetic lines bend to the inner side of the inductor IDT 1  in the vicinity of both ends of the inductor IDT 1 . In order to cope with this, the additional via hole conductors VH 41   c  and VH 111   c  are provided in the vicinity of both ends of the inductor IDT 1  (that is, at positions close to the outermost layers of the multilayer body  12 ). Therefore, bending of the magnetic lines to the inner side of the inductor IDT 1  is suppressed, and the deterioration in the characteristics of the inductor IDT 1  is suppressed eventually. 
     It should be noted that the ceramic sheets SH 0 , SH 7 , and SH 13  are made of non-magnetic ferrite (relative magnetic permeability: 1) as a material and thermal expansion coefficients thereof indicate values in a range of “8.5” to “9.0”. Further, the ceramic sheets SH 1  to SH 6  and SH 8  to SH 12  are made of magnetic ferrite (relative magnetic permeability: 100 to 120) as a material and thermal expansion coefficients thereof indicate values in a range of “9.0” to “10.0”. In addition, the pad electrodes PD 1   a  to PD 4   a  and PD 1   b  to PD 4   b , the coil conductor patterns CP 21  to CP 111 , CP 22  to CP 112 , CP 23  to CP 113 , and CP 24  to CP 114 , the via hole conductors VH 31   a  to VH 131   a  and VH 31   b  to VH 131   b , the via hole conductors VH 32   a  to VH 132   a  and VH 32   b  to VH 132   b , the via hole conductors VH 33   a  to VH 133   a  and VH 33   b  to VH 133   b , the via hole conductors VH 34   a  to VH 134   a  and VH 34   b  to VH 134   b , and the additional via hole conductors VH 41   c  to VH 44   c  and VH 111   c  to VH 114   c  are made of silver as a material, and thermal expansion coefficients thereof indicate “20”. 
     As is seen from the above description, the multilayer body  12  is produced by laminating the plurality of ceramic sheets SH 0  to SH 13  at least some of which have magnetism. The inductors IDT 1  to IDT 4  have a plurality of inductance values at least one of which is different from other inductance values, and are provided in the multilayer body  12 . 
     The numbers of coil conductor patterns CP 21  to CP 111  forming the inductor IDT 1 , coil conductor patterns CP 22  to CP 112  forming the inductor IDT 2 , coil conductor patterns CP 23  to CP 113  forming the inductor IDT 3 , and coil conductor patterns CP 24  to CP 114  forming the inductor IDT 4  are common to the channels and they are provided between the ceramic sheet SH 2  to SH 12 . 
     The coil conductor patterns CP 21  to CP 111  are spirally connected by the via hole conductors VH 31   a  to VH 131   a  and VH 31   b  to VH 131   b  and the coil conductor patterns CP 22  to CP 112  are spirally connected by the via hole conductors VH 32   a  to VH 132   a  and VH 32   b  to VH 132   b . The coil conductor patterns CP 23  to CP 113  are spirally connected by the via hole conductors VH 33   a  to VH 133   a  and VH 33   b  to VH 133   b  and the coil conductor patterns CP 24  to CP 114  are spirally connected by the via hole conductors VH 34   a  to VH 134   a  and VH 34   b  to VH 134   b.    
     Further, the coil conductor patterns CP 31  and CP 41  are additionally connected by the additional via hole conductor VH 41   c  and the coil conductor patterns CP 32  and CP 42  are additionally connected by the additional via hole conductor VH 42   c . The coil conductor patterns CP 33  and CP 43  are additionally connected by the additional via hole conductor VH 43   c  and the coil conductor patterns CP 34  and CP 44  are additionally connected by the additional via hole conductor VH 44   c.    
     In the same manner, the coil conductor patterns CP 101  and CP 111  are additionally connected by the additional via hole conductor VH 111   c  and the coil conductor patterns CP 102  and CP 112  are additionally connected by the additional via hole conductor VH 112   c . The coil conductor patterns CP 103  and CP 113  are additionally connected by the additional via hole conductor VH 113   c  and the coil conductor patterns CP 104  and CP 114  are additionally connected by the additional via hole conductor VH 114   c.    
     Thus, the coil conductor patterns forming the respective inductors are provided between the laminated ceramic sheets and the numbers of coil conductor patterns aligned in the lamination direction are common to the inductors. With this, the flatness of the multilayer body is kept. At least two coiled conductors forming each of the inductors are additionally connected by the additional via hole conductor. This enables the inductor value to be adjusted arbitrarily. In addition, the coil conductor patterns that are connected by the additional via hole conductors are provided at positions close to the outermost layer of the multilayer body. With this configuration, a phenomenon that magnetic lines generated on each inductor bend to the inner side of a wound body in the vicinity of the outermost layer can be suppressed, and the deterioration in the inductor characteristics can be suppressed eventually. 
     In the embodiment, the additional via hole conductors VH 41   c  to VH 44   c  are provided at positions close to one outermost layer forming the multilayer body  12  and the additional via hole conductors VH 111   c  to VH 114   c  are provided at positions close to the other outermost layer forming the multilayer body  12 . However, the additional via hole conductors may be formed at only positions close to any one of the outermost layers (see  FIG. 13A ) or the additional via hole conductors may be formed over three layers (see  FIG. 13B ). 
     Some coil conductor patterns may be removed and a removable position thereof may be made different among the channels as long as the number of coil conductor patterns is common to the channels (see  FIG. 14A  to  FIG. 14B ). 
     Moreover, in the embodiment, as schematically illustrated in  FIG. 15 , two coil conductor patterns CP 1  and CP 2  adjacent in the lamination direction are additionally connected by a single additional via hole conductor VHadd 1 . Alternatively, the two coil conductor patterns CP 1  and CP 2  adjacent in the lamination direction may be connected by a plurality of additional via hole conductors VHadd 1  and VHadd 2  as illustrated in  FIG. 17 . 
     In the case of the configuration as illustrated in  FIG. 15 , an electric current I flowing to the coil conductor pattern CP 2  from the coil conductor pattern CP 1  is shortcut by the additional via hole conductor VHadd 1  as illustrated in  FIG. 16 . An electrode portion through which no current flows is generated on each of the coil conductor patterns CP 1  and CP 2 . By contrast, in the case of the configuration as illustrated in  FIG. 17 , a current flowing to the coil conductor pattern CP 2  from the coil conductor pattern CP 1  is made to branch by the additional via hole conductors VHadd 1  and VHadd 2  as illustrated in  FIG. 18 . Although the electrode portions through which no current flows are also generated in the configuration as illustrated in  FIG. 17 , the lengths of the electrode portions are smaller than those in the configuration as illustrated in  FIG. 15 . 
     As a result, an inductance value when the configuration as illustrated in  FIG. 17  is employed is identical to an inductance value when the configuration as illustrated in  FIG. 15  is employed. However, a resistance value when the configuration as illustrated in  FIG. 17  is employed can be reduced from that when the configuration as illustrated in  FIG. 15  is employed. That is to say, conductor loss can be reduced by connecting the coil conductor patterns CP 1  and CP 2  by the plurality of additional via hole conductors VHadd 1  and VHadd 2 . 
       FIG. 19  illustrates a DC-to-DC converter module  20  using the inductor array chip  10  in the embodiment. With reference to  FIG. 19 , capacitors C 0  to C 4  and a switching IC  14  are mounted on the top surface of the multilayer body  12  configuring the inductor array chip  10 . A conductive bonding member such as solder is used for mounting. 
     The inductors IDT 1  to IDT 4  provided in the inductor array chip  10  are connected to the capacitors C 0  to C 4  and the switching IC  14  in a manner as illustrated in  FIG. 20 . It should be noted that in  FIG. 20 , wirings and the inductors IDT 1  to IDT 4  provided on outer side portions of rectangles as drawn by dashed lines are formed in the inductor array chip  10 . 
     With reference to  FIG. 20 , the switching IC  14  includes control circuits  161  to  164  corresponding to the channels CH 1  to CH 4 , respectively. Further, MOS transistors T 1   a  and T 1   b  are assigned to the control circuit  161 , MOS transistors T 2   a  and T 2   b  are assigned to the control circuit  162 , MOS transistors T 3   a  and T 3   b  are assigned to the control circuit  163 , and MOS transistors T 4   a  and T 4   b  are assigned to the control circuit  164 . 
     One ends of the transistors T 1   a  to T 4   a  are commonly connected to an input terminal Vin, and the other ends of the transistors T 1   a  to T 4   a  are connected to one ends of the transistors T 1   b  to T 4   b , respectively. The other ends of the transistors T 1   b  to T 4   b  are commonly connected to a reference potential surface. The control circuit  161  turns ON/OFF the transistors T 1   a  and T 1   b  alternately or turns OFF both the transistors T 1   a  and Tlb, the control circuit  162  turns ON/OFF the transistors T 2   a  and T 2   b  alternately or turns OFF both the transistors T 2   a  and T 2   b , the control circuit  163  turns ON/OFF the transistors T 3   a  and T 3   b  alternately or turns OFF both the transistors T 3   a  and T 3   b , and the control circuit  164  turns ON/OFF the transistors T 4   a  and T 4   b  alternately or turns OFF both the transistors T 4   a  and T 4   b.    
     The inductor IDT 1  is provided between a connection point of the transistor T 1   a  and the transistor T 1   b  and an output terminal Vout 1 , the inductor IDT 2  is provided between a connection point of the transistor T 2   a  and the transistor T 2   b  and an output terminal Vout 2 , the inductor IDT 3  is provided between a connection point of the transistor T 3   a  and the transistor T 3   b  and an output terminal Vout 3 , and the inductor IDT 4  is provided between a connection point of the transistor T 4   a  and the transistor T 4   b  and an output terminal Vout 4 . 
     The capacitor C 0  is provided between the input terminal Vin and the reference potential surface, the capacitor C 1  is provided between the output terminal Vout 1  and the reference potential surface, the capacitor C 2  is provided between the output terminal Vout 2  and the reference potential surface, the capacitor C 3  is provided between the output terminal Vout 3  and the reference potential surface, and the capacitor C 4  is provided between the output terminal Vout 4  and the reference potential surface. 
     In this embodiment, the DC-to-DC converter module  20  functions as a switching power supply for the plurality of channels. In this case, the flatness of the top surface of the multilayer body  12  is preferable and the DC-to-DC converter module  20  functions as the switching power supply with less deterioration of the inductors IDT 1  to IDT 4 , that is, with preferable manufacturing performance and electric characteristics even when the inductance values of the inductors IDT 1  to IDT 4  are adjusted for the respective channels. 
     In the embodiment, all the channels CH 1  to CH 4  are of a step-down type. However, switching power supply circuits of various systems using inductors of a step-up type, a step-up/step-down type, an inversion-type, or the like may be formed for all or some of the plurality of channels. 
     In the embodiment, the channels CH 1  to CH 4  are integrated into the switching IC  14 . However, four switching ICs corresponding to the respective channels CH 1  to CH 4  may be mounted on the multilayer body  12  or a switching IC corresponding to some channels of the channels CH 1  to CH 4  and another switching IC corresponding to the other channels may be combined to be mounted on the multilayer body  12 .
           10  INDUCTOR ARRAY CHIP     12  MULTILAYER BODY     14  SWITCHING IC     161  TO  164  CONTROL CIRCUIT     20  DC-TO-DC CONVERTER MODULE   SH 0  TO SH 13  CERAMIC SHEET   IDT 1  TO IDT 4  INDUCTOR   CP 21  TO  111 , CP 22  TO  112 , CP 23  TO  113 , CP 24  TO  114  COIL CONDUCTOR PATTERN (COILED CONDUCTOR)   VH 31   a  TO VH 131   a , VH 31   b  TO VH 131   b , VH 32   a  TO VH 132   a , VH 32   b  TO VH 132   b , VH 33   a  TO VH 133   a , VH 33   b  TO VH 133   b , VH 34   a  TO VH 134   a , AND VH 34   b  TO VH 134   b  VIA HOLE CONDUCTOR (FIRST VIA HOLE CONDUCTOR)   VH 41   c  TO VH 44   c  AND VH 111   c  TO VH 114   c  ADDITIONAL VIA HOLE CONDUCTOR (SECOND VIA HOLE CONDUCTOR)