Patent Publication Number: US-2023156364-A1

Title: Image pickup device that is provided with peripheral circuits to prevent chip area from being increased, and image pickup apparatus

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention relates to an image pickup device and an image pickup apparatus, and more particularly to a technique concerning a circuit forming the image pickup device. 
     Description of the Related Art 
     Conventionally, there has been developed an image pickup apparatus, such as a digital camera and a digital video camera, which records a shot image using a CMOSAPS (complementary metal oxide semiconductor active pixel sensor) as an image pickup device. The image pickup device includes a pixel section and a peripheral circuit section. The peripheral circuit section reads out a signal from each pixel and is output to the outside as an image signal. The pixel section performs photoelectric conversion by photo diodes, and a pixel circuit formed in the pixel section reads out a signal obtained by photoelectric conversion to the peripheral circuit section. 
     In recent years, as the pixel becomes finer, as for inside each pixel, the number of circuits is reduced as much as possible and the area of a photo diode is increased, whereby the performance of the image pickup device is ensured. Further, as the function of the image pickup device is improved, the area of the peripheral circuit section is also increased. Therefore, a technique for forming the pixel section and the peripheral circuit section on respective separate chips is being developed. The technique disclosed in Japanese Patent Laid-Open Publication No. 2008-211220 employs a method in which a pixel is formed only by a photo diode and some of switches, and the other switches are formed in a separate chip. 
       FIG.  27    is a schematic block diagram useful in explaining a conventional image pickup device. 
     The image pickup device includes a pixel section  101 ′, a vertical selection circuit  102 ′ for selecting at least one of rows of pixels in the pixel section  101 ′, and column circuits  103 ′ each of which performs predetermined processing on signals read from pixels on a row selected by the vertical selection circuit  102 ′ in the pixel section  101 ′. The image pickup device further includes column memories  104 ′ each of which holds signals which have been processed by the column circuits  103 ′ on a column basis, horizontal selection circuits  105 ′ each of which selects a column of signals held in the column memories  104 ′, and output signal lines  106 ′ each for reading out a signal from a column selected by an associated one of the horizontal selection circuits  105 ′ to an associated one of output circuits  107 ′. Note that the image pickup device further includes not only illustrated components but also a timing generator which supplies a timing signal to each of the vertical selection circuit  102 ′, the horizontal selection circuits  105 ′, the column circuits  103 ′, etc., a control circuit, and so forth. 
     The vertical selection circuit  102 ′ sequentially selects a plurality of rows in the pixel section  101 ′, and outputs selected signals to the column memories  104 ′. The horizontal selection circuits  105 ′ sequentially select signals held in the respective associated column memories  104 ′, and output selected signals to the respective associated output circuits  107 ′ through the associated output signal lines  106 ′. The pixel section  101 ′ is formed by arranging a plurality of pixels in a two-dimensional array in order to provide a two-dimensional image. These circuits are formed on one semiconductor substrate, and along with finer designing of a semiconductor process, reduction of a pixel pitch and reduction of the area of peripheral circuits are in progress. 
       FIG.  28    is a diagram showing the configuration of one pixel in the conventional image pickup device, and the configuration of a circuit for reading out a signal from the pixel. 
     As shown in  FIG.  28   , a pixel array which provides a two-dimensional image is formed by arranging a plurality of pixels in a two-dimensional array. Each pixel  201 ′ is configured to include a photo diode (hereinafter also referred to as the “PD”)  202 ′, a transfer switch  203 ′, a floating diffusion (hereinafter also referred to as the “FD”)  204 ′, a reset switch  207 ′, a MOS amplifier  205 ′, and a selection switch  206 ′. 
     The PD  202 ′ functions as a photoelectric conversion element which converts light incident through an optical system to an electric signal by photoelectric conversion to thereby generate electric charges. The anode of the PD  202 ′ is connected to a ground line, and the cathode of the PD  202 ′ is connected to the source of the transfer switch  203 ′. The transfer switch  203 ′ is driven by a transfer pulse ϕTX input to a gate terminal thereof to transfer the electric charges generated in the PD  202 ′ to the FD  204 ′. The FD  204 ′ functions as a charge-voltage converting section which temporarily accumulates electric charges and converts the accumulated electric charges to a voltage signal. 
     The MOS amplifier  205 ′ functions as a source follower, and has a gate to which the voltage signal converted from the electric charges in the FD  204 ′ is input. Further, the MOS amplifier  205 ′ has a drain connected to a first power line VDD 1  for supplying a first potential, and a source connected to the selection switch  206 ′. The selection switch  206 ′ is driven by a vertical selection pulse ϕSEL input to a gate thereof, and has a drain connected to the MOS amplifier  205 ′, and a source connected to a vertical signal line (column signal line)  208 ′. When the vertical selection pulse ϕSEL becomes an active level (high level), the selection switch  206 ′ of each pixel belonging to the corresponding row on the pixel array becomes conductive, whereby the source of the MOS amplifier  205 ′ is connected to the vertical signal line  208 ′. 
     The reset switch  207 ′ has a drain connected to a second power line VDD 2  for supplying a second potential (reset potential), and a source connected to the FD  204 ′. Further, the reset switch  207 ′ is driven by a reset pulse (RES input to a gate thereof to remove electric charges accumulated in the FD  204 ′. 
     A floating diffusion amplifier is formed by not only the FD  204 ′ and the MOS amplifier  205 ′, but also a constant current source  209 ′ for supplying a constant current to the vertical signal line  208 ′. In each of pixels forming the row selected by the selection switch  206 ′, the electric charges transferred from the PD  202 ′ to the FD  204 ′ is converted to the voltage signal by the FD  204 ′, and the voltage signal is output to the vertical signal line (column signal line)  208 ′ provided on a column basis through the floating diffusion amplifier. 
     The column circuits  103 ′ connected to the vertical signal lines (column signal lines)  208 ′ are each implemented e.g. by a CDS (correlated double sampling) circuit and a gain amplifier. Further, the column circuits  103 ′ are formed by respective circuits each having the same configuration on a column basis. A signal processed by the column circuit  103 ′ is held in an associated one of the column memories  104 ′. The signal held in the column memory  104 ′ is transferred to the output circuit  107 ′ through the output signal line  106 ′. The output circuit  107 ′ performs amplification, impedance conversion, and so forth on the input signal, and outputs the processed signal to the outside of the image pickup device. 
     However, in the technique described in Japanese Patent Laid-Open Publication No. 2008-211220, chips are connected via the floating diffusions in each of which the signal is faint among all signals within the pixel, and hence variation in the manufacturing of products of the FD results in variation in the capacity value of the FD, which causes PRNU (photo response non-uniformity) and DSNU (dark signal non-uniformity). Further, although the layout and position of a readout circuit is not described in Japanese Patent Laid-Open Publication No. 2008-211220, it is desirable to more efficiently lay out and position the reading circuit than the prior art, since the pixel section and the peripheral circuit section are formed on separate chips. Further, recently, a circuit which realizes a plurality of functions has come to be introduced into the peripheral circuits, as in the case where an analog-to-digital converter is introduced into the column circuit, on a column basis, and hence the chip areas of the peripheral circuits are increased. This brings about not only a problem that heat generated in the peripheral circuits generates dark current in the PD  202 ′ in each pixel, but also a problem that the dark current becomes non-uniform in a screen-associated region if the peripheral circuits are biased in arrangement. 
     SUMMARY OF THE INVENTION 
     The present invention provides an image pickup device which suppresses an increase in chip area of peripheral circuits without degrading the performance of a pixel section and makes it possible to prevent costs from being increased, and an image pickup apparatus. 
     The present invention further provides an image pickup device which has a pixel section and a peripheral circuit section formed in different areas, wherein an increase in chip area is suppressed by efficiently arranging peripheral circuits without degrading the performance of the pixel section, and non-uniformity of dark current within a screen-associated region due to heat generated in the peripheral circuits is suppressed, and an image pickup apparatus. 
     In a first aspect of the present invention, there is provided an image pickup device comprising a first semiconductor substrate and a second semiconductor substrate, a pixel section including photoelectric conversion elements each configured to generate electric charges by photoelectric conversion, floating diffusions each configured to temporarily store the electric charges generated in one of the photoelectric conversion elements, and amplifiers each configured to output signals dependent on potentials of the one of the floating diffusions, a plurality of column signal lines configured to have the signals output thereto from the pixel section, on a column basis, and a plurality of column circuits connected to the plurality of column signal lines, respectively, and configured to perform predetermined processing on the signals output to the column signal lines, wherein the pixel section is formed on an area of the first semiconductor substrate and the plurality of column circuits are formed on an area of the second semiconductor substrate such that the plurality of column circuits are located under the pixel section in an overlapping manner when the image pickup device is viewed from a side where light enters. 
     In a second aspect of the present invention, there is provided an image pickup apparatus comprising this image pickup device. 
     In a third aspect of the present invention, there is provided an image pickup device comprising a semiconductor substrate including a first side and a second side, a pixel section including photoelectric conversion elements each configured to generate electric charges by photoelectric conversion, floating diffusions each configured to temporarily store the electric charges generated in one of the photoelectric conversion elements, and amplifiers each configured to output signals dependent on potentials of one of the floating diffusions, a plurality of column signal lines configured to have the signals output thereto from the pixel section, on a column basis, and a plurality of column circuits connected to the plurality of column signal lines, respectively, and configured to perform predetermined processing on the signals output to the column signal lines, wherein the pixel section is formed on the first side of the semiconductor substrate and the plurality of column circuits are formed on the second side of the semiconductor substrate such that the plurality of column circuits are located under the pixel section in an overlapping manner when the image pickup device is viewed from a side where light enters. 
     In a fourth aspect of the present invention, there is provided an image pickup apparatus comprising this image pickup device. 
     According to the above-described aspects of the present invention, it is possible to obtain an advantageous effect that it is possible to prevent costs from being increased due to an increase in chip area of the peripheral circuits without degrading the performance of the pixel section. 
     According to the above-described aspects of the present invention, it is possible to efficiently arrange the peripheral circuits without degrading the performance of the pixel section, and it is possible to reduce non-uniformity of dark current within a screen-associated region due to heat generated in the peripheral circuits. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram useful in explaining the overall configuration of an image pickup device according to a first embodiment of the present invention. 
         FIG.  2    is a diagram showing pixels and the circuit configuration for reading out signals from the pixels, in the image pickup device according to the first embodiment. 
         FIG.  3    is a diagram showing a variation of the circuit configuration shown in  FIG.  2   . 
         FIG.  4    is a diagram showing another variation of the circuit configuration shown in  FIG.  2   . 
         FIG.  5    is a view showing a cross-sectional structure of the image pickup device according to the first embodiment. 
         FIG.  6    is a block diagram showing a variation of the overall configuration of the image pickup device shown in  FIG.  1   . 
         FIG.  7    is a block diagram showing another variation of the overall configuration of the image pickup device shown in  FIG.  1   . 
         FIG.  8    is a view showing a cross-sectional structure of an image pickup device according to a second embodiment of the present invention. 
         FIG.  9    is a block diagram showing still another variation of the overall configuration of the image pickup device shown in  FIG.  1   . 
         FIG.  10    is a schematic diagram of a digital camera as an example of an image pickup apparatus equipped with the image pickup device according to any of the first and second embodiments and variations thereof. 
         FIG.  11    is a diagram showing a configuration of a pixel and a circuit configuration for reading out a signal from the pixel, in an image pickup device according to a third embodiment of the present invention. 
         FIG.  12    is a diagram showing a variation of the circuit configuration of the image pickup device shown in  FIG.  11   . 
         FIG.  13    is a diagram showing another variation of the circuit configuration of the image pickup device shown in  FIG.  11   . 
         FIG.  14    is a diagram of the overall configuration of the image pickup device according to the third embodiment, as viewed from above. 
         FIG.  15    is a cross-sectional view of an image pickup device as a variation of the third embodiment. 
         FIG.  16    is a diagram of the overall configuration of an image pickup device according to a fifth embodiment of the present invention, as viewed from above. 
         FIG.  17    is a diagram of a variation of the overall configuration of the image pickup device according to the fifth embodiment, as viewed from above. 
         FIG.  18    is a diagram of another variation of the overall configuration of the image pickup device according to the fifth embodiment, as viewed from above. 
         FIG.  19    is a diagram of the overall configuration of an image pickup device according to a sixth embodiment of the present invention, as viewed from above. 
         FIG.  20    is a diagram of a variation of the overall configuration of the image pickup device according to the sixth embodiment, as viewed from above. 
         FIG.  21    is a diagram of another variation of the overall configuration of the image pickup device according to the sixth embodiment, as viewed from above. 
         FIG.  22    is a diagram of the overall configuration of an image pickup device according to a seventh embodiment of the present invention, as viewed from above. 
         FIG.  23    is a diagram of the overall configuration of an image pickup device according to an eighth embodiment of the present invention, as viewed from above. 
         FIG.  24    is a diagram of the overall configuration of an image pickup device according to a ninth embodiment of the present invention, as viewed from above. 
         FIG.  25    is a diagram of a variation of the overall configuration of the image pickup device according to the ninth embodiment, as viewed from above. 
         FIG.  26    is a diagram of another variation of the overall configuration of the image pickup device according to the ninth embodiment, as viewed from above. 
         FIG.  27    is a schematic block diagram useful in explaining a conventional image pickup device. 
         FIG.  28    is a diagram showing the configuration of one pixel in the conventional image pickup device, and a circuit configuration for reading out a signal from the pixel. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     The present invention will now be described in detail below with reference to the accompanying drawings showing embodiments thereof. 
       FIG.  1    is a block diagram useful in explaining the overall configuration of an image pickup device according to a first embodiment of the present invention. It is assumed that in actuality, illustrated areas  1  and  2  overlap in a vertical direction. 
     In  FIG.  1   , the image pickup device includes a pixel section  101 , a vertical selection circuit  102  which selects at least one of rows of pixels in the pixel section  101 , and column circuits  103  each of which reads out signals from pixels on a pixel row in the pixel section  101  selected by the vertical selection circuit  102 , and performs predetermined processing on the read signals. The image pickup device further includes column memories  104  each of which holds signals processed by the column circuits  103 , on a column basis, horizontal selection circuits  105  each of which selects a signal held in the associated column memory  104 , and output signal lines  106  each of which reads out signals from a column selected by the horizontal selection circuit  105  to an associated one of output circuits  107 . Note that the image pickup device may further incorporate not only illustrated components but also a timing generator  1007 , referred to hereinafter, which supplies a timing signal to each of the vertical selection circuit  102 , the horizontal selection circuits  105 , the column circuits  103 , etc., a control circuit  1009 , referred to hereinafter, a digital-to-analog converter, and so forth. However, these components are not necessarily required to be provided on the same chip as the image pickup device, but the timing generator  1007  and the control circuit  1009  may be provided separately from the image pickup device, as shown in  FIG.  10   . 
     The vertical selection circuit  102  sequentially selects a plurality of rows in the pixel section  101 , and outputs signals from a selected row to the column memories  104  via the column circuits  103 . Each horizontal selection circuits  105  sequentially selects signals held in the associated column memory  104 , and outputs the selected signals to the associated output circuit  107  via the associated output signal line  106 . The pixel section  101  is formed by arranging a plurality of pixels in a two-dimensional array to provide a two-dimensional image. 
     The pixel section  101 , the vertical selection circuit  102 , and the output circuits  107 , which are included in the area  1 , are formed on a first semiconductor substrate. On the other hand, the column circuits  103 , the column memories  104 , the horizontal selection circuits  105 , and the output signal lines  106 , which are included in the area  2 , are formed on a second semiconductor substrate. The first semiconductor substrate and the second semiconductor substrate are separately formed, and are laminated while providing interconnections requiring electrical connection, whereby both the substrates are mounted in the same package. That is, as viewed from an upper surface of the image pickup device package (from a side of the pixel section  101  where light enters), the column circuits  103 , the column memories  104 , the horizontal selection circuits  105 , and the output signal lines  106 , which are formed on the area  2  on the second semiconductor substrate, are disposed under the pixel section  101  formed on the area  1  on the first semiconductor substrate, in an overlapping manner. By disposing the timing generator  1007 , the control circuit  1009 , the digital-to-analog converter, etc. in the area  2  under the vertical selection circuit  102  and the output circuits  107  in the area  1 , a high area efficiency is achieved. Note that although in a plurality of embodiments described hereinafter, the arrangement including the first semiconductor substrate and the second semiconductor substrate will be described by way of example, this is not limitative, but the arrangement may include still another semiconductor substrate. 
       FIG.  2    is a diagram showing a pixel and the circuit configuration for reading out a signal from the pixel in the image pickup device according to the first embodiment. 
     As shown in  FIG.  2   , a pixel array which provides a two-dimensional image is formed by arranging a plurality of pixels in a two-dimensional array. Each pixel  201  is configured to include a photo diode (hereinafter also referred to as the “PD”)  202 , a transfer switch  203 , a floating diffusion (hereinafter also referred to as the “FD”)  204 , a reset switch  207 , a MOS amplifier  205 , and a selection switch  206 . 
     The PD  202  functions as a photoelectric conversion element which converts light incident through an optical system to an electric signal by photoelectric conversion to thereby generate electric charges. The anode of the PD  202  is connected to a ground line, and the cathode of the PD  202  is connected to the source of the transfer switch  203 . The transfer switch  203  is driven by a transfer pulse ϕTX input to a gate terminal thereof to transfer the electric charges generated in the PD  202  to the FD  204 . The FD  204  functions as a charge-voltage converting section which temporarily accumulates electric charges, and converts the accumulated electric charges to a voltage signal. 
     The MOS amplifier  205  is implemented by an amplification circuit, such as a MOSFET, functions as a source follower, and has a gate to which the voltage signal converted from the electric charges in the FD  204  is input. Further, the MOS amplifier  205  has a drain connected to a first power line VDD 1  for supplying a first potential thereto, and a source connected to the selection switch  206 . The selection switch  206  is driven by a vertical selection pulse ϕSEL input to a gate thereof, and has a drain connected to the MOS amplifier  205 , and a source connected to a vertical signal line  208 . When the vertical selection pulse ϕSEL becomes an active level (high level), the selection switch  206  of each pixel belonging to the corresponding row on the pixel array becomes conductive, whereby the source of the MOS amplifier  205  is connected to the vertical signal line  208 . 
     The reset switch  207  has a drain connected to a second power line VDD 2  for supplying a second potential (reset potential) as a constant potential, and a source connected to the FD  204 . Further, the reset switch  207  is driven by a reset pulse ϕRES input to a gate thereof to remove the electric charges accumulated in the FD  204 . The pulses ϕTX, ϕSEL, and ϕRES are supplied from the vertical selection circuit  102 . 
     A floating diffusion amplifier is formed by not only the FD  204  and the MOS amplifier  205 , but also a constant current source  209  for supplying a constant current to the vertical signal line  208 . In each of pixels forming the row selected by the selection switch  206 , the electric charges transferred from the PD  202  to the FD  204  is converted to the voltage signal, and the voltage signal is output to the vertical signal line (column signal line)  208  provided on a column basis through the floating diffusion amplifier. 
     The column circuits  103  connected to the vertical signal lines (column signal lines)  208  are each implemented e.g. by a CDS (correlated double sampling) circuit and a gain amplifier. The CDS circuit performs correlated double sampling processing on a signal output to the vertical signal line  208 . The gain amplifier amplifies a signal output to the vertical signal line  208  with a predetermined gain. Further, the column circuits  103  are formed by respective circuits each having the same configuration on a column basis. A signal subjected to the above-mentioned processing by the column circuit  103  is held by an associated one of the column memories  104 . The signal held by the column memory  104  is transferred to the output circuit  107  through the output signal line  106 . The output circuit  107  performs amplification, impedance conversion, etc., on the input signal, and outputs the processed signal to the outside of the image pickup device. 
     Although the column circuit  103 , the column memory  104 , and the output circuit  107  can be configured to have the above-described circuit configuration, the column circuit  103  may be configured to have an analog-to-digital converter on a column basis. In this case, the column circuit  103  includes an analog-to-digital converter in addition to the CDS circuit and the gain amplifier. Further, each column memory  104  in this case is a digital memory, and each output circuit  107  is provided with components including an LVDS (low voltage differential signaling) driver. 
     The illustrated area  1 , i.e. the first semiconductor substrate is configured to include the PD  202 , the transfer switch  203 , the FD  204 , the reset switch  207 , the MOS amplifier  205 , and the selection switch  206 , provided on a pixel basis, and the output circuits  107 . 
     The illustrated area  2 , i.e. the second semiconductor substrate is configured to include the vertical signal lines  208 , the constant current sources  209 , the column circuits  103 , the column memories  104 , and the output signal lines  106 , provided on a column basis. The vertical signal lines (column signal lines)  208  are interconnections connecting between the pixel section  101  and the column circuits  103 , and may be included in either the area  1  or the area  2 . Further, each selection switch  206  may be included in the area  2 . 
     Further, as in a variation of the circuit configuration shown in  FIG.  3   , the constant current source  209  may be included in the area  1 . However, in this case, the constant current source  209  is disposed on the same board as that on which the pixels are disposed, and hence the area efficiency is not very high. This arrangement is effective only in a case where an area for arranging the column circuit  103 , the column memory  104 , and the output signal line  106  is larger than the area of the pixel section. 
     Further, as in another variation of the circuit configuration shown in  FIG.  4   , the selection switch  206  may be omitted. In the circuit configuration without the selection switch  206 , each selected row and each non-selected row are set by controlling the reset pulse ϕRES and the potential of the second power line VDD 2 . 
       FIG.  5    is a view showing a cross-sectional structure of the image pickup device according to the first embodiment of the present invention.  FIG.  5    shows the structure in which the area  1  as the first semiconductor substrate is laminated on the area  2  as the second semiconductor substrate. The same components as those shown in  FIG.  2    are denoted by the same reference numerals. 
     The area  1  indicating the first semiconductor substrate is formed on a semiconductor substrate  501 . The area  1  includes a region  502  of a first conductivity type, a region  202  of the PDs, and a region  503  of the first conductivity type for reducing dark current of the PDs  202 . The area  1  further includes the transfer switches  203 , the FDs  204 , and the MOS amplifiers  205 . In addition to these, the area  1  includes the reset switches  207 . 
     The area  1  further includes an element isolation region  504 , a interconnection layer  505  formed in a multilayered manner, and an interlayer film  506  between the multiple layers of the interconnection layer  505 . A through hole  507  electrically connects between the interconnections. Since the area  1  includes the pixel section, it also includes a color filter  508  for performing color separation, and a micro lens  509  for collecting light. 
     The area  2  indicating the second semiconductor substrate as a semiconductor substrate other than the first semiconductor substrate is formed on a semiconductor substrate  510 . Each circuit of the column circuit  103  is formed by a plurality of types of switches in each of switch type groups  511 . The area  2  further includes the column memories  104 , the output signal lines  106 , and so on. Connection points  115  of the vertical signal lines  208  are formed e.g. by micro bumps which electrically connect between the area  1  and the area  2 . Further, in addition to the connection points  115  of the vertical signal lines  208 , the area  2  includes connection points  512  formed e.g. by micro bumps which electrically connect interconnections for supplying power and various kinds of drive pulses. Although in the present embodiment, there is illustrated the first semiconductor substrate in which a light receiving section is formed by a back side illumination type, the light receiving section may be formed by a front side illumination type instead of the back side illumination type. 
     Although in the present embodiment, the pixel section  101 , the vertical selection circuit  102 , and the output circuits  107  are formed in the area  1 , and the other drive circuits are disposed in the area  2 , this is not limitative. For example, as in a variation of the overall configuration of the image pickup device shown in  FIG.  6   , the output circuits  107  may be disposed in the area  2 . 
     Further, as in another variation of the overall configuration of the image pickup device shown in shown in  FIG.  7   , part of the vertical selection circuit  102  may be disposed in the area  1 , and the rest of the vertical selection circuit  102  may be disposed in the area  2 . Further, in this case, it is possible to improve the area efficiency by arranging the part and the rest of the vertical selection circuit  102  at approximately the same location, as viewed from above. That is, in the present invention, it is only required to arrange at least the transfer switches  203 , the FDs  204 , the reset switches  207 , and the MOS amplifiers  205  of the pixel section  101  in the area  1  so as to prevent the FDs  204  from being divided between the area  1  and the area  2 . The other drive circuits can be disposed in the area  1  or the area  2  depending on the area efficiency of the semiconductor substrate. 
     Although in the above-described embodiment, as shown in  FIG.  5   , the area  1  is set on the first semiconductor substrate, and the area  2  is set on the second semiconductor substrate, this is not limitative, but the areas  1  and  2  may be formed on the same semiconductor substrate, as shown in  FIG.  8   . 
       FIG.  8    is a view showing a cross-sectional structure of an image pickup device according to a second embodiment of the present invention. The same components as those shown in  FIGS.  2  and  5    are denoted by same reference numerals, and description thereof is omitted. 
     In the second embodiment shown in  FIG.  8   , the area  1  and the area  2  are formed on the front side (first side or second side) and the back side (first side or second side) of the semiconductor substrate  501 , respectively. In the present embodiment, a description will be given assuming that a side on which the area  1  is formed is the front side, and a side on which the area  2  is formed is the back side. A protective layer  801  protects the interconnection layer  505  on the back side. Plugs  802  electrically connect between the front side and the back side. 
     Further, although in the above-described embodiments, the description has been given of the area  1  and the area  2 , the areas are not limited to two, but may be divided into a plurality of areas and have various components arranged thereon. For example, as in a variation shown in  FIG.  9   , the pixel section  101  and the vertical selection circuit  102  may be formed on the area  1 , and the rest of the drive circuits may be formed in a manner divided between the areas  2  and  3 . In the illustrated example, the rest of the vertical selection circuit  102  and the column circuits  103  are formed on the area  2 , and the rest of the column circuits  103  and the other drive circuits are formed on the area  3 , separately. As described above, by separately arranging the components across the plurality of areas, it is possible to mount an analog-to-digital converter and the like, on a column basis, and effectively arrange an increasing number of column circuits  103 . Note that the areas  1 ,  2 , and  3  may be formed on different semiconductor substrates, respectively. 
       FIG.  10    is a schematic diagram of a digital camera as an example of an image pickup apparatus equipped with the image pickup device according to any of the above-described embodiments and variations. 
     In  FIG.  10   , a lens unit  1001  which forms an optical image of an object into an image on a solid image pickup device (the image pickup device according to any of the above-described embodiments and variations)  1005  is driven by a lens drive unit  1002  so as to perform zoom control, focus control, aperture control, and so forth. A mechanical shutter  1003  is controlled by a shutter control unit  1004 . The solid image pickup device  1005  converts an object image formed by the lens unit  1001  to an image signal, and outputs the image signal. An image pickup signal processing circuit  1006  performs various kinds of correction on an image signal output from the solid image pickup device  1005 , and compresses data. 
     The timing generator  1007  is a drive unit which supplies various kinds of timing signals to the solid image pickup device  1005  and the image pickup signal processing circuit  1006 . The control circuit  1009  controls various kinds of computations and the overall operation of the image pickup apparatus. A memory  1008  temporarily stores image data. An recording medium control interface  1010  records or reads out data in or from a removable storage medium  1011 , such as a semiconductor memory. A display unit  1012  displays various information items and a shot image. 
     Next, a description will be given of the operation of the digital camera having the above-described arrangement during shooting. 
     When the main power, not shown, is switched on, the power of a control system turns on, and further, the power of image pickup system circuits, such as the image pickup signal processing circuit  1006 , turns on. Subsequently, when a release button, not shown, is depressed, the control circuit  1009  extracts a high-frequency component based on a signal output from a distance measurement device  1014 , and performs calculation of a distance to the object. Thereafter, the control circuit  1009  drives the lens unit  1001  by the lens drive unit  1002 , and determines whether or not the object is in focus. If it is determined that the object is not in focus, the control circuit  1009  drives the lens unit  1001  again, and performs distance measurement. Then, when it is confirmed that the object is in focus, an image pickup operation is started. 
     When the image pickup operation is terminated, the image signal output from the solid image pickup device  1005  is subjected to image processing in the image signal processing circuit  1006 , and is written into the memory  1008  by the control circuit  1009 . The data accumulated in the memory  1008  is recorded in the removable storage medium  1011 , such as a semiconductor memory, through the recording medium control interface  1010  by the control of the control circuit  1009 . Note that the data may be directly input e.g. to a computer for image processing through an external interface section, not shown. 
       FIG.  11    is a diagram showing a configuration of a pixel and a circuit configuration for reading out a signal from the pixel, in an image pickup device according to a third embodiment of the present invention. The area  1  is a chip including circuits formed on the first semiconductor substrate, and the area  2  is a chip including circuits formed on the second semiconductor substrate. 
     The area  1  mainly includes the pixels  201 , and the area  2  mainly includes the column circuit for processing a signal from each pixel  201 . 
     The area  1  is formed by arranging a plurality of the pixels  201  in a two-dimensional array as a pixel array which provides a two-dimensional image. Each pixel  201  can be configured to include the photo diode (hereinafter also referred to as the “PD”)  202 , the transfer switch  203 , the floating diffusion (hereinafter also referred to as the “FD”)  204 , the MOS amplifier  205 , the selection switch  206 , and the reset switch  207 . 
     The PD  202  functions as a photoelectric conversion section which converts light incident through an optical system to an electric signal by photoelectric conversion to thereby generate electric charges. The anode of the PD  202  is connected to a ground line, and the cathode of the PD  202  is connected to a source of the transfer switch  203 . The transfer switch  203  is driven by a transfer pulse ϕTX input to a gate terminal thereof to transfer the electric charges generated in the PD  202  to the FD  204 . The FD  204  functions as a charge-voltage converting section which temporarily accumulates electric charges, and converts the accumulated electric charges to a voltage signal. 
     The MOS amplifier  205  functions as a source follower, and has a gate to which the voltage signal converted from the electric charges in the FD  204  is input. Further, the MOS amplifier  205  has a drain connected to the first power line VDD 1  for supplying a first potential thereto, and a source connected to the selection switch  206 . The selection switch  206  is driven by a vertical selection pulse ϕSEL input to a gate thereof, and has a drain connected to the MOS amplifier  205 , and a source connected to the vertical signal line  208 . When the vertical selection pulse ϕSEL becomes an active level (high level), the selection switch  206  of each pixel belonging to the corresponding row on the pixel array becomes conductive, whereby the source of the MOS amplifier  205  is connected to the vertical signal line  208 . The vertical signal line  208  is shared by a plurality of pixels  201  sharing a column. 
     The reset switch  207  has a drain connected to the second power line VDD 2  for supplying a second potential (reset potential), and a source connected to the FD  204 , and is driven by a reset pulse (RES input to the gate thereof to remove electric charges accumulated in the FD  204 . 
     A floating diffusion amplifier is formed by not only the FD  204  and the MOS amplifier  205 , but also the constant current source  209  for supplying a constant current to the vertical signal line  208 . In each of pixels forming the row selected by the selection switch  206 , the electric charges transferred from the PD  202  to the FD  204  is converted to the voltage signal by the FD  204 , and the voltage signal is output to the vertical signal line (column signal line)  208  provided on a column basis through the floating diffusion amplifier. The pulses ϕTX, ϕSEL, and ϕRES are supplied from the vertical selection circuit, referred to hereinafter. 
     The column circuit  103  connected to each of the vertical signal lines (column signal line)  208  is implemented e.g. by a column amplifier  110 . The column circuits  103  are formed by respective circuits each having the same configuration on a column basis. The column circuit  103  may have the configuration including only the column amplifier  110  appearing in  FIG.  11   , or may have a configuration including a CDS (correlated double sampling) circuit. 
     A signal subjected to the above-mentioned processing by the column circuit  103  is held by an associated one of the column memories  104 . The signal held by the column memory  104  is transferred to the output circuit  107  through the output signal line  106 . The output circuit  107  performs amplification, impedance conversion, etc., on the input signal, and outputs the processed signal to the outside of the image pickup device. 
     The area  1  and the area  2  are electrically connected via the connection points  115  of the vertical signal lines (column signal lines)  208 . Each connection points  115  is disposed downstream of the MOS amplifier  205  as shown in  FIG.  11   , whereby it is possible to reduce PRNU (photo response non-uniformity) and DSNU (dark signal non-uniformity). The constant current source  209  may be disposed in the area  2  or in the area  1 . 
       FIG.  12    is a diagram showing a variation of the circuit configuration of the image pickup device shown in  FIG.  11   . 
     In  FIG.  12   , a column AD  111  is mounted at a location downstream of the column amplifier  110 . The column AD  111  is an analog-to-digital converter provided on a column basis, which performs analog-to-digital conversion. In this case, the column circuit  103  is formed by the column amplifier  110  and the column AD  111 . The column circuit  103  may further include the above-mentioned CDS circuit, etc. In the case of the configuration including the column AD  111 , the column memory  104  is a digital memory, and the output circuit  107  is provided with components including an LVDS (low voltage differential signaling) driver. 
     Further, as shown in another variation shown in  FIG.  13   , the circuit configuration may exclude the selection switch  206 . 
       FIG.  14    is a schematic diagram of the image pickup device according to the third embodiment, as viewed from above. The area  1  and the area  2  are chips formed on different semiconductor substrates, respectively, and are mounted on the same package by providing interconnections requiring electrical connection. That is, as viewed from an upper surface of the package, the area  2  is disposed under the area  1 , in an overlapping manner. 
     The area  1  has the pixels  201  formed on a plurality of rows and columns in an array. The above-mentioned pulses ϕTX, ϕSEL, and ϕRES for driving the pixels  201  are supplied from the vertical selection circuit  102 , on a row basis. The vertical signal line  208  for taking out a signal from a pixel is shared by pixels in the same column. Here, the vertical signal lines  208  in the first to fourth columns are denoted by reference numerals  208 _ 1 ,  208 _ 2 ,  208 _ 3 , and  208 _ 4 . The area  1  and the area  2  each have the connection points  115  for connecting the vertical signal lines  208  to the column circuits  103 . The connection point  115  included in the vertical signal line  208 _ 1  is denoted by reference numeral  115 _ 1 . Further, the column circuit  103  connected to the vertical signal line  208 _ 1  is denoted by reference numeral  103 _ 1 , and the column memory  104  connected to the column circuit  103 _ 1  is denoted by reference numeral  104 _ 1 . The area  2  includes the horizontal selection circuits  105  each for transferring signals from the column memory  104  to the output circuit  107 . Each horizontal selection circuit  105  transfers signals from the column memory  104  to the output circuit  107  on a time-series basis. 
     Although not shown, one of the area  1  and the area  2  includes the above-mentioned constant current source  209  in addition to the illustrated components. The constant current source  209  may be included in the column circuit  103 . Further, in addition, for example, one of the area  1  and the area  2  includes a timing generator or a control circuit which provides a timing signal to the vertical selection circuit  102 , the horizontal selection circuit  105 , and the column circuit  103 , etc., and a serial communication interface, and a digital-to-analog converter. 
     Various kinds of pulses are supplied from the timing generator etc., to each horizontal selection circuit  105 , and hence it is desirable that the horizontal selection circuits  105  are disposed close to respective ends of the chip. As shown in  FIG.  14   , by arranging the connection point  115  in the vicinity of the center of the chip in a direction along each column, it is possible to arrange the horizontal selection circuits  105  in the vertical direction. 
     A cross-sectional structure of the image pickup device according to the present embodiment is substantially the same as that according to the first embodiment shown in  FIG.  5   , and hence illustration and description thereof are omitted. 
     As shown in  FIG.  14   , by sharing the connection point  115  on each vertical signal line (column signal line) between pixels, the number of connection points is smaller than in a case where the connection points are provided on a pixel basis, so that it is possible to solve a problem that yields are reduced due to a formation error of connection points. It is to be understood that the number of connection points is not limited to one, but the connection point may be provided in plurality taking into account the yields. In the present embodiment, each vertical signal line in the area  1  is shared between the pixels, whereby it is not necessary to connect the area  1  and the area  2 , on a pixel-by-pixel basis. 
     Although in the present embodiment, there is illustrated the first semiconductor substrate in which a light receiving section is formed by a back side illumination type, the light receiving section may be formed by a front side illumination type instead of the back side illumination type.  FIG.  15    is a view showing a cross-sectional structure of the front side illumination type as a variation of the present embodiment.  FIG.  15    shows the structure in which the area  1  as the first semiconductor substrate is laminated on the area  2  as the second semiconductor substrate. Description of components denoted by the same reference numerals as those shown in  FIG.  5    is omitted. In the front side illumination type, the micro lens  509  is disposed on top of the interconnection layer  505  with respect to the semiconductor substrate  501 . In the front side illumination type, through vias  601  are formed to connect the connection points  115  and the components in the area  1 . 
     A cross-sectional structure according to a fourth embodiment of the present invention in which the area  1  and the area  2  of the front side illumination type are formed on the same substrate  501  is substantially the same as the cross-sectional structure of the second embodiment shown in  FIG.  8   , and hence illustration and description thereof are omitted, but as described above, in this case, the connection points  115  are formed by the through vias  601  to connect the vertical signal lines  208  and the circuits on the backside. 
       FIG.  16    is a diagram of the overall configuration of an image pickup device according to a fifth embodiment of the present invention, as viewed from above.  FIGS.  17  and  18    are diagrams of respective variations thereof. 
     Differently from  FIG.  14   , in the overall configuration of the image pickup device according to the fifth embodiment shown in  FIG.  16   , the connection points  115 _ 1  and  115 _ 2  as the connection points  115  are displaced in the direction along each column, whereby it is possible to dispose the connection points  115  immediately close to the column circuits  103 _ 1  and  103 _ 2 . This reduces the length of interconnections in the area  2 , and makes it possible to further efficiently arrange the column circuits  103  etc. 
     In the variation shown in  FIG.  17   , the connection points  115 _ 1 ,  115 _ 2 ,  115 _ 3 , and  115 _ 4  are displaced, whereby it is possible to arrange the column circuits  103 _ 1  to  103 _ 4  in a sparse or unconcentrated manner. In the case of the arrangement shown in  FIG.  14   , in which the column circuits  103  are concentrated in a particular area, heat generated in the column circuits  103  is concentrated, whereby non-uniformity of dark current within a screen-associated region of a shot image is caused by the PDs  202  which receive heat from the column circuits  103 . However, with the arrangement of the circuit configuration shown in  FIG.  17   , it is possible to reduce non-uniformity of dark current within the screen-associated region due to heat generation in the column circuits  103 . In  FIG.  17   , by reversing the arrangement of the column circuit  103 _ 1  and the column memory  104 _ 1 , and the column circuit  103 _ 3  and the column memory  104 _ 3 , the column circuits  103  are dispersed. To this end, the arrangement is improved such that an output signal line  106  is also disposed in the center along the direction of each column. However, in the case of the arrangement illustrated in  FIG.  18    in which the column circuits  103  and the column memories  104  can be sufficiently reduced in size, it is not necessary to dispose the output line in the center, and the column circuits  103 _ 1  and  103 _ 3  may be arranged in the same direction. 
     As described above, by displacing the connection points  115  on a column-by-column basis, it is possible to efficiently arrange the circuits, and realize the arrangement which reduces the influence of heat generation by the column circuits  103 . 
       FIG.  19    is a diagram of the overall configuration of an image pickup device according to a sixth embodiment of the present invention, as viewed from above.  FIGS.  20  and  21    are diagrams of respective variations thereof. 
     Although in  FIGS.  14 ,  16 ,  17 , and  18   , the column circuit  103  and the column memory  104  are illustrated as the circuits having a width corresponding to two columns in the direction along each row, this is not limitative, but the column circuit  103  and the column memory  104  can be differently configured in the present invention. For example, as shown in  FIG.  19   , the column circuit  103  and the column memory  104  may have a width corresponding to one column in the direction along each row. However, the column circuit  103  and the column memory  104  are increased in length in the direction along each column, and become vertically still longer. The column circuit  103  and the column memory  104  are isolated from the adjacent column circuit  103  and the column memory  104  in the element isolation region, and hence it is possible to achieve a more excellent area efficiency when the column circuit  103  and the column memory  104  are formed in an area closer to a square in shape. In the variation shown in  FIG.  20   , the column circuit  103  and the column memory  104  have a width corresponding to four columns in the direction along each row. Although the column circuit  103  and the column memory  104  look horizontally long in the schematic diagram, in actuality, to make the area for the circuits closer to a square in shape, by displacing the connection points  115  on a column-by-column basis, it is possible to provide such a layout. As shown the variation in  FIG.  21   , with the increase in the width of the column circuit  103  and the column memory  104  in the direction along each line, it is possible to dispose a plurality of output signal lines  106 . The output signal lines  106  do not consume electric power, and hence by increasing the number of the output signal lines  106  and disposing them between the column circuits  103  and the column memories  104 , it is possible to disperse heat generation. 
       FIG.  22    is a diagram of the overall configuration of an image pickup device according to a seventh embodiment of the present invention, as viewed from above. Although the arrangement shown in  FIG.  22    is configured based on the same concept as that of the arrangement shown in  FIG.  17   , if the column circuit  103  and the column memory  104  are small in size, vacant space is formed between the circuits. In a case where the column AD is mounted as in the case illustrated in  FIG.  12   , it is possible to dispose digital circuits  1401 . Each digital circuit  1401  is capable of performing various kinds of correction processing, such as gamma correction, and image processing, such as white balance adjustment, on signals output from the column memories  104 . The arrangement is not limited to the examples shown in  FIGS.  17  and  21   , but by arranging the column circuits  103  in a dispersed manner, the digital circuits  1401  may be also arranged in a dispersed manner, whereby it is also possible to reduce non-uniformity of dark current due to heat generation by the digital circuits  1401 . Further, when the column ADs are mounted, the horizontal selection circuits  105  are not necessarily required. 
       FIG.  23    is a diagram of the overall configuration of an image pickup device according to an eighth embodiment of the present invention, as viewed from above. In  FIG.  23   , the connection points  115  are disposed at vertically one-sided locations. In this case, although it is not possible to reduce non-uniformity of dark current, the arrangement is effective for forming the through vias, as shown in  FIGS.  15  and  8   . When the characteristics of the pixels  201  in the vicinity of the connection points  115  are degraded due to formation of the through vias, it is possible to make the corresponding pixels having low characteristics unnoticeable as an image, by displacing the connection points  115  toward the upper and lower regions which are relatively unnoticeable within the screen. 
       FIG.  24    is a diagram of the overall configuration of an image pickup device according to a ninth embodiment of the present invention, as viewed from above.  FIGS.  25  and  26    are diagrams of respective variations thereof. 
     Although in the above-described circuit configuration, the vertical selection circuit  102  is formed in the area  1 , and the output circuits  107  are formed in the area  2 , this is not limitative. As shown in  FIG.  24   , the output circuits  107  may be formed in the area  1 . In this case, the output signal lines  106  and the output circuits  107  are connected between the area  1  and the area  2 . As schematically shown in  FIG.  24   , the area  1  and the area  2  are not required to be the same in size. Further, as shown in the variation in  FIG.  25   , part of the vertical selection circuit  102  may be formed in the area  2 . In this configuration, a drive buffer of the vertical selection circuit  102  for driving the pixels  201  can be moved to the area  1 , and the digital section of the same can be moved to the area  2 . Further, as shown in the variation in  FIG.  26   , it is possible to arrange the output circuits  107  such that they do not extend in the horizontal direction, but extend in the vertical direction. When the column circuits are small in the vertical direction, it is possible to make the area  1  and the area  2  nearly equal in size by adopting such a layout. 
     The configuration and operations of the digital camera as an image pickup apparatus using the image pickup device according to any of the above-described embodiments and variations thereof are the same as those described with reference to  FIG.  10   , and hence description thereof is omitted. 
     Aspects of the present invention can also be realized by a computer of a system or apparatus (or devices such as a CPU or MPU) that reads out and executes a program recorded on a memory device to perform the functions of the above-described embodiment(s), and by a method, the steps of which are performed by a computer of a system or apparatus by, for example, reading out and executing a program recorded on a memory device to perform the functions of the above-described embodiment(s). For this purpose, the program is provided to the computer for example via a network or from a recording medium of various types serving as the memory device (e.g., computer-readable medium). 
     While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2011-169291 filed Aug. 2, 2011, and Japanese Patent Application No. 2012-159605 filed Jul. 18, 2012, which are hereby incorporated by reference herein in their entirety.