Patent Publication Number: US-8542031-B2

Title: Method and apparatus for regulating a power supply of an integrated circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of application Ser. No. 12/843,139 filed Jul. 26, 2010 and issued as U.S. Pat. No. 8,081,011, which is a continuation-in-part of application Ser. No. 12/012,733 filed on Feb. 5, 2008 and issued as U.S. Pat. No. 7,791,368, which claimed the benefit of U.S. Provisional Application No. 60/899,684 filed Feb. 6, 2007. The teachings of application Ser. No. 12/843,139; application Ser. No. 12/012,733; and U.S. Provisional Application No. 60/899,684 are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     The present invention relates generally to integrated circuits (ICs) and more specifically to the regulating of a power supply of an IC. 
     Integrated circuits (ICs) typically include many switching elements, such as transistors. These switching elements are configured to perform a variety of circuit functions. 
     The operation of a transistor is typically affected by its process, voltage, and temperature (“PVT”). The “process” component of PVT refers to the process of manufacturing a transistor. The process is often classified as “fast”, “slow”, “nominal”, or anywhere in between. A transistor manufactured using a fast process will transmit signals at a faster rate as compared to a transistor manufactured using a slower process. Likewise, a transistor manufactured using a slow process will transmit signals at a slower rate as compared to a transistor manufactured using a faster process. Once a transistor is manufactured using a particular process, the effect of the process is fixed. Thus, the “process” component of PVT cannot be adjusted to change the operating characteristics of a manufactured transistor. 
     The “temperature” component of PVT is the temperature at which the transistor operates. Similar to the process used to manufacture a transistor, the temperature at which a transistor operates affects how a transistor operates. In particular, the rate at which a transistor transmits a signal is affected by the temperature at which the transistor operates. For example, a transistor operating at a reference temperature requires a first voltage to transmit signals at a first rate. If the temperature of the transistor decreases, less voltage is needed to transmit signals at the first rate. Similarly, if the temperature of the transistor increases, more voltage is needed to transmit signals through the transistor at the first rate. The “temperature” component of PVT varies during operation of the transistor. While there is some control over the temperature of an IC, such temperature cannot be sufficiently adjusted to result in a change in its operating characteristics. 
     The only component of PVT that can be varied effectively during operation to adjust a transistor&#39;s characteristics is its voltage. The optimum supply voltage of a transistor varies depending on the transistor&#39;s process (e.g., fast or slow) and the transistor&#39;s operating temperature. A conventional solution to the variation in the optimum supply voltage is to set the supply voltage to a worst-case value. In transistors manufactured with a fast process or operating at a low temperature, this conventional solution often results in too much power being supplied to the transistor, with the excess power being dissipated (i.e., wasted). 
     As an example, if a circuit designer determines (e.g., via simulation of an IC having many transistors) that a transistor manufactured with a slow process needs 3.2 V as a supply voltage, the circuit designer may provide a supply voltage of 3.2 V to each transistor on the IC. If another transistor on the IC was manufactured with a fast process, however, that transistor might only need a supply voltage of 3.0 V. When 3.2 V is supplied, excess power is dissipated on the transistor that only needs 3.0 V as a supply voltage. As the number of transistors on the IC that were manufactured with a fast process (or are operating at a low temperature) increases, the amount of dissipated power increases. 
     Increased power dissipation on an IC often corresponds to an increase in IC component cost because increased packaging requirements have to be satisfied. This additional packaging results in increased cost for the IC. Also, increased power dissipation often decreases reliability of the IC. 
       FIG. 1  depicts a conventional method for setting the output voltage of a voltage regulator  112  in a power supply circuit  110  to provide a particular voltage V dd    132  to an IC  130  in a system  100 . A resistive voltage divider formed by resistors R 1  and R 2  provides a voltage-control signal V 2  (or feedback signal) to the voltage regulator. Voltage regulator  112  is conventionally designed such that its output voltage V OUT  is a function of the output-voltage control signal V 2 . Resistors R 1  and R 2  are located externally to IC  130  and may even be located internally to voltage regulator  112 . In such a system, the manufacturer of the IC generally has no control over the specific values of resistors R 1  and R 2 , which values ultimately determine the output voltage of the power supply circuit. As a result, the manufacturer of the IC must rely on the designers of system  100  to select appropriate values of resistors R 1  and R 2  to set the output voltage V OUT  of the power supply circuit  110 . 
     Therefore, there remains a need to adjust, via internal components of an IC, the voltage applied to the IC by a power supply. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with an embodiment of the present invention, the invention is an integrated circuit (IC) comprising an input node configured to receive a power supply voltage (e.g., V dd ) generated by an external power supply circuit. A PVT detector on the IC is configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC. An interface circuit on the IC is configured to produce a voltage control signal based on the interface control signal, and the power supply circuit generates the power supply voltage based on the voltage control signal. 
     In another embodiment, the invention is a method of controlling a power supply voltage (e.g., V dd ) provided by an external power supply circuit to an IC. An input node of the IC receives the power supply voltage. A PVT detector generates an interface control signal based on at least one of process, voltage, and temperature of the IC. An interface circuit produces a voltage control signal based on the interface control signal, and the power supply circuit generates the power supply voltage based on the voltage control signal. 
     In another embodiment, the invention is an IC comprising a PVT detector configured to generate an interface control signal based on at least one of process, voltage, and temperature of the IC. An interface circuit on the IC is configured to produce a voltage control signal based on the interface control signal, and a power supply circuit on the IC is configured to produce a maximum power supply voltage for the IC based on the voltage control signal. 
     In another embodiment, the invention is a method of controlling a positive supply voltage (e.g., Vdd) of an IC. A PVT detector generates an interface control signal based on at least one of process, voltage, and temperature of the IC. An interface circuit produces a voltage control signal based on the interface control signal, and a power supply circuit located on the IC produces the positive supply voltage for the IC based on the voltage control signal. 
     In another embodiment, the invention is a power supply circuit. The power supply circuit comprises a resistive voltage divider comprising a first resistor connected to a second resistor at a first node. The power supply circuit further comprises a voltage regulator having a voltage-control input connected to said first node and configured to generate a power supply voltage as a function of a voltage level at the voltage-control input. The power supply circuit still further comprises a terminal configured to receive a voltage control signal from an external circuit, said terminal being connected to the first node such that the voltage level at the voltage control input is based on the voltage control signal. 
     Other aspects, features, and advantages of the present invention will become more fully apparent from the following detailed description, the appended claims, and the accompanying drawings in which like reference numerals identify similar or identical elements. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a prior-art system having a power supply connected to an IC; 
         FIG. 2  is a block diagram of a system having a power supply connected to an IC having an interface circuit and a PVT detector in accordance with an embodiment of the present invention; 
         FIG. 3  is a block diagram of a system illustrating an embodiment of the interface circuit of  FIG. 2 ; 
         FIG. 4  is a block diagram of an exemplary embodiment of the PVT detector of  FIG. 3 ; 
         FIG. 5  is a block diagram of a system illustrating another embodiment of the interface circuit of  FIG. 2 ; 
         FIG. 6  is a block diagram of an exemplary embodiment of the PVT detector of  FIG. 5 ; 
         FIG. 7  depicts exemplary operation of the processor of  FIG. 6 ; 
         FIG. 8  is a block diagram of a system illustrating another embodiment of the interface circuit of  FIG. 2 ; 
         FIG. 9  is a more-detailed block diagram of the system shown in  FIG. 8 ; and 
         FIG. 10  is a block diagram of an exemplary embodiment of the PVT detector of  FIGS. 8 and 9 . 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a block diagram of a system  200  comprising an integrated circuit (IC)  230  in communication with an external power supply circuit  210 . The IC  230  includes a PVT detector  280  to detect the process, voltage, and/or temperature (PVT) characteristics of transistors on the IC  230 . For example, the PVT detector  280  can detect whether a transistor on the IC  230  was manufactured via a fast process or via a slow process. As is known to one of ordinary skill in the art, the PVT detector  280  can perform this detection in a variety of ways, e.g., by using a ring oscillator that produces an output signal with a frequency that is a function of the ring oscillator&#39;s process, voltage, and temperature. See, e.g., U.S. Pat. No. 7,321,254, the teachings of which are incorporated herein by reference. 
     The PVT detector  280  produces an interface control signal  270  that passes to interface circuit  240  (located within IC  230 ). Interface circuit  240 , in turn, produces a voltage control signal  222  based on interface control signal  270 . Power supply circuit  210  is adapted to receive voltage control signal  222  and to adjust voltage V dd  provided to IC  230  via connection  220  as a function thereof. In certain embodiments, interface circuit  240  has a resistance that is adjusted in response to the interface control signal  270 . As described in more detail below, the interface circuit  240  can include, for example, a configuration of one or more resistors and/or a configuration of active elements. 
     A simplified embodiment of an interface circuit is shown in  FIG. 3 . System  300  includes a power supply circuit  310  in communication with IC  330 . The IC  330  includes PVT detector  380  that adjusts the configuration of interface circuit  340  (shown with dashed lines) by generating interface control signals  370 ,  372 . Adjusting the configuration of interface circuit  340  results in a change in the voltage V dd  provided by the power supply circuit  310  to IC  330  at input node  332 . 
     The PVT detector  380  controls the configuration of the interface circuit  340  by controlling the opening and closing of switches  341 ,  342  with interface control signals  370 ,  372 . Each of switches  341 ,  342  may be implemented as a bipolar or Metal-Oxide-Semiconductive (MOS) transistor or as a three-stateable transmission gate (a.k.a., analog switch) similar to those commercially available in the DS3690 transmission gate integrated circuit manufactured by Maxim Integrated Products, Inc. of Sunnyvale, Calif. This change in configuration effectively adjusts a maximum voltage V dd  provided by the power supply circuit  310  to the IC  330  at circuit point  336  (via input node  332 ). 
     Power supply circuit  310  includes a regulator  314  that regulates an input voltage V 1    312  to produce the maximum voltage V dd    336  with respect to a minimum voltage (e.g., ground)  338 , based on a control signal V 2  at node  318  that is input to regulator  314  at a voltage-control input  316 . More specifically, regulator  314  is configured to generate the maximum voltage V dd    316  as a function of a voltage level at voltage-control input  316 . Power supply circuit  310  further includes a terminal  324  configured to receive a voltage-control signal from interface circuit  340 . Terminal  324  is connected to node  318  such that the voltage level at the voltage-control input is based on the voltage-control signal. 
     The power supply circuit  310  further includes a resistor R 1   320  and a resistor R 2   322 . Resistor R 1   320  and a resistor R 2   322  form a voltage divider with a load resistor R adapt    326 . Load resistor R adapt    326  may be implemented as a fixed resistor external to power supply circuit  310  and IC  330 , as shown in  FIG. 3 . Alternatively, load resistor R adapt    326  may be integrated into either the power supply circuit  310  or IC  330 . The configuration of R 1   320  and R 2   322  with load resistor R adapt    326  is used to provide a different control voltage V 2  to regulator  314  at circuit point  318 . 
     Regulator  314  may be implemented using any commercially available regulator controller IC having resistive programming for output voltage control, such as the ISL62870 PWM DC/DC Voltage Regulator Controller available from Intersil Corporation in Milpitas, Calif. See, e.g., Intersil Corporation, ISL62870 Datasheet, No. FN6708.0 (Aug. 14, 2008), the teachings of which are incorporated herein by reference. 
     In a default state, both of switches  341 ,  342  are in an “open” condition. As such, the nominal voltage V 2,NOM  of control voltage V 2  is given by the following equation: 
     
       
         
           
             
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     The control voltage V 2  at circuit point  318  is adjusted according to whether the load resistor R adapt    326  is connected to the maximum voltage V dd    336  or the minimum voltage  338  (e.g., ground), which depends on the configuration of the switches  341 ,  342 . Specifically, if switch  342  is closed and switch  341  is open, then the circuit point  334  and, therefore, the load resistor R adapt    326  are connected to minimum voltage. In this first case, the formula for the voltage at circuit point  318  of the system  300  is: 
     
       
         
           
             
               
                 
                   
                     
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     If switch  342  is open and switch  341  is closed, however, then the circuit point  334  and, therefore, the load resistor R adapt    326  are connected to maximum voltage V dd    336 . In this second case, the formula for the voltage at circuit point  318  of the system  300  is: 
     
       
         
           
             
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     Thus, when switch  341  is closed and switch  342  is open, the control voltage V 2  at circuit point  318  will be a maximum voltage V 2,MAX . When switch  342  is closed and switch  341  is open, the control voltage V 2  at circuit point  318  will be a minimum voltage V 2,MIN . When the control voltage V 2  is at the maximum voltage V 2,MAX , regulator  314  produces a maximum output voltage V dd,MAX . Conversely, when the control voltage V 2  is at the minimum voltage V 2,MIN , regulator  314  produces a minimum output voltage V dd,MIN . 
     If the PVT detector  380  determines that the voltage V dd  being supplied to transistors on the IC  330  is resulting in excess power being dissipated, then the control voltage V 2  at circuit point  318  needs to be decreased. As a result, the PVT detector  380  closes switch  342  and opens switch  341 , thus decreasing control voltage V 2  and causing regulator  314  to decrease voltage V dd . If the PVT detector  380  determines that the voltage V dd  being supplied to transistors on the IC  330  is too low, then the control voltage V 2  at circuit point  318  needs to be increased. As a result, the PVT detector  380  closes switch  341  and opens switch  342 , thus increasing control voltage V 2  and causing regulator  314  to increase voltage V dd . The PVT detector  380  can determine the voltage V dd  supplied to the transistors on the IC  330  in a variety of ways known to one of ordinary skill in the art. 
     In one embodiment, the PVT detector  380  may determine that the voltage at circuit point  318  needs to be increased when the PVT detector  380  determines that the process used to generate some or all of the transistors on the IC  330  was a slow process. In another embodiment, the PVT detector  380  determines that the voltage at circuit point  318  needs to be increased when the PVT detector  380  determines that the temperature of one or more transistors on the IC  330  is increasing. In still another embodiment, the PVT detector  380  determines that the voltage at circuit point  318  needs to be increased when the PVT detector  380  determines that a frequency of oscillation of a ring oscillator is less than a predetermined frequency. 
     It should be understood that, although the voltage level of voltage V dd  is described in the above paragraphs as a positive function of control voltage V 2  at circuit point  318 , regulator  314  may also be adapted to produce voltage V dd  as a negative function of control voltage V 2 . In such an embodiment, the control of switches  341 ,  342  by PVT detector would be opposite to that described above. For example, if the PVT detector  380  determined that the voltage V dd  being supplied to transistors on the IC  330  is resulting in excess power being dissipated, then the control voltage at circuit point  318  would need to be increased, rather than decreased, in such an embodiment. 
       FIG. 4  depicts an exemplary embodiment of PVT detector  380 , comprising a ring oscillator  410 , a frequency-to-voltage converter  420 , and a control circuit  430 . Ring oscillator  410  comprises a plurality of interconnected inverting buffers  412  that form a loop. Ring oscillator  410  oscillates and produces a signal  414  having a frequency that is dependent upon (i) the process with which integrated circuit  330  was manufactured, (ii) supply voltage V dd , and (iii) the temperature of ring oscillator  410 . Frequency-to-voltage converter  420  is adapted to receive signal  414  and to produce a signal  422  that has a voltage proportional to the frequency of signal  414 . Suitable implementations for frequency-to-voltage converter  420  are known to those of ordinary skill in the art and include those described in U.S. Pat. Nos. 4,816,704 and 5,514,988, the teachings of which are incorporated herein by reference. 
     Control circuit  430  receives signal  422  and generates interface control signals  372  and  370  to respectively control switches  342  and  341  based thereon. Control circuit  430  comprises two comparators  440 ,  442  that receive signal  422  at a first input. At a second input, comparators  440 ,  442  receive a reference voltage V REF , which is produced by amplifier  432 , buffer transistor  434 , and the voltage divider formed by resistors  436 ,  438 . When the voltage of signal  422  is greater than V REF , interface control signal  372  closes switch  342 , while interface control signal  370  opens switch  341 . Similarly, when the voltage of signal  422  is less than V REF , interface control signal  372  opens switch  342 , while interface control signal  370  closes switch  341 . 
     Another embodiment of an interface circuit is shown in  FIG. 5 . System  500  includes an external power supply circuit  510  (with voltage regulator  514 ) and PVT detector  580  that is internal to an IC  530 . System  500  includes a first resistor R 1   520  and a second resistor R 2   522 . These two resistors R 1   520  and R 2   522  form a voltage divider with the resistance of interface circuit  540  internal to the IC  530 . 
     Interface circuit  540  includes a plurality of individually controllable switches  541 - 550  connected to a corresponding plurality of resistors  551 - 560 . Each of switches  541 - 550  may be implemented as a bipolar or metal-oxide-semiconductive (MOS) transistor or as a three-stateable transmission gate (a.k.a., analog switch) similar to those commercially available in the DS3690 transmission gate integrated circuit manufactured by Maxim Integrated Products, Inc. of Sunnyvale, Calif. Interface circuit  540  enables a finer control relative to interface circuit  340  of  FIG. 3 , because a plurality of resistors can be connected in parallel to adjust the resistance at circuit point  534 . For example, any number of switches  541 - 545  can be turned on to connect corresponding resistors  551 - 555  in parallel to the maximum voltage V dd    536  and to circuit point  534 . Further, any number of switches  546 - 550  can be turned on to connect corresponding resistors  556 - 560  in parallel to a minimum voltage (e.g., ground)  538  and to circuit point  534 . The PVT detector  580  is coupled to the switches of the interface circuit  540 . 
     The PVT detector  580  controls switches  541 - 550  so that one or more of the resistors that can be connected to maximum voltage V dd    536 , such as resistors  551  and  553 , are connected to maximum voltage V dd  when the PVT detector  580  determines that the control voltage V 2  at circuit point  534  needs to be increased (e.g., in order to cause voltage regulator  514  to increase the magnitude of maximum voltage V dd ). The PVT detector  580  control switches so that one or more of the resistors that can be connected to minimum voltage  538 , such as resistors  556  and  559 , are connected to minimum voltage  538  when the PVT detector  580  determines that the control voltage V 2  at circuit point  534  needs to be decreased (e.g., in order to cause voltage regulator  514  to decrease the magnitude of maximum voltage V dd ). 
       FIG. 6  depicts an exemplary embodiment of PVT detector  580 . Like PVT detector  330 , PVT detector  580  comprises a ring oscillator  602  having interconnected inverting buffers  604  and a frequency-to-voltage converter  606 . In PVT detector  580 , however, the signal  608  from frequency-to-voltage converter  606  is converted by analog-to-digital converter  610  to a digital signal  612  that is then passed to a processor  614  connected to a memory  616 . Processor  614  is preferably a microprocessor, but may alternatively be a microcontroller or an application-specific integrated circuit (ASIC). Memory  616  contains look-up table  618 , in which are stored the switch settings of switches  541 - 550  that are needed to obtain a desired resistance of interface circuit  540 . 
       FIG. 7  depicts exemplary operation of processor  614 . In step  702 , processor  614  reads a value V PVT  of digital signal  612 , which value is a digital representation of the voltage produced by frequency-to-voltage converter  606 . In step  704 , processor  614  compares value V PVT  to a predetermined setpoint value V SET . Based on the comparison and upon the current switch configuration, in step  706 , processor  614  obtains from look-up table  618  new switch settings suitable to increase or decrease the resistance of interface circuit  540 , as appropriate. Finally, in step  708 , processor  614  outputs interface control signals  570 ,  572  to switches  541 - 550 . 
     Another embodiment of an interface circuit is shown in  FIG. 8 . System  800  includes an external power supply circuit  810  (with voltage regulator  814 ) being controlled by a PVT detector  880  that is internal to an IC  830 . System  800  includes a first resistor R 1   820  and a second resistor R 2   822 . These two resistors R 1   820  and R 2   822  form a voltage divider with interface circuit  840  internal to the IC  830 . 
     Interface circuit  840  includes one or more active elements  842 , such as bipolar or Metal Oxide Semiconductor (MOS) transistors. The active elements  842  provide a finer control of the resistance at circuit point  834  of the IC  830  than the previously described embodiments. Specifically, the active elements  842  provide a resistance that is not limited to discrete resistance levels. 
     PVT detector  880  controls the resistance of the interface circuit  840  by transmitting an interface control signal  870  to the active elements  842 . In response to the interface control signal  870 , the active elements  842  adjust their collector-emitter or drain-source resistances in order to adjust the resistance of the interface circuit  840 . For example, the active elements  842  may be set to a particular collector-emitter or drain-source resistance based on the interface control signal  870 . The interface control signal  870  is based on one or more PVT characteristics of transistors on the IC  830 . 
       FIG. 9  is a more-detailed block diagram of the system shown in  FIG. 8 . In the embodiment shown in  FIG. 9 , the active elements  842  comprise a p-type MOS transistor Q 1   904  and an n-type MOS transistor Q 2   906 , which are preferably configured to operate in their triode regions. The drain-source resistances of transistors Q 1  and Q 2  are adjusted as a function of the interface control signal  870 . In particular, as the voltage of interface control signal  870  increases, the drain-source resistance of transistor Q 1  increases, and the drain-source resistance of transistor Q 2  decreases. The system further includes a buffer  902  that isolates node  834  from node  908 . 
       FIG. 10  depicts an exemplary embodiment of PVT detector  880 . Like PVT detectors  330  and  580 , PVT detector  880  comprises a ring oscillator  1010  having interconnected inverting buffers  1012  connected to a frequency-to-voltage converter  1020  via connection  1014 . In PVT detector  880 , however, the signal  1022  from frequency-to-voltage converter  1020  is connected to one input of an analog difference amplifier  1030 , while the other input of difference amplifier  1030  is connected to a setpoint voltage V SET . When the voltage of the signal  1022  is greater than the setpoint voltage V SET , differential amplifier  1030  outputs a lower voltage to interface circuit  840 , thus reducing the resistance of transistor Q 2   906  (shown on  FIG. 9 ) and increasing the resistance of transistor Q 1   904 . Conversely, when the voltage of the signal  1022  is less than the setpoint voltage V SET , differential amplifier  1030  outputs a higher voltage to interface circuit  840 , thus increasing the resistance of transistor Q 2   906  (shown on  FIG. 9 ) and decreasing the resistance of transistor Q 1   904 . 
     Although power supply circuits  210 ,  310 ,  510 , and  810  are described above and depicted in the figures as comprising a regulator and discrete resistors external to the regulator, the regulator and resistors may alternatively be integrated together on a single power supply IC. In this case, the power supply circuit may be provided with a terminal that is (i) connected internally to the regulator&#39;s output-voltage control input (e.g., node  318 ) and (ii) suitable for connection to a control terminal of the downstream IC (e.g., circuit point  334  of IC  330 ). 
     Alternatively, the various elements of systems  300 ,  500 , and  800  may be integrated on a single integrated circuit. Such an integrated circuit advantageously is adapted to regulate its internal supply voltage V dd  as a function of its PVT characteristics. 
     The foregoing Detailed Description is to be understood as being in every respect illustrative and exemplary, but not restrictive, and the scope of the invention disclosed herein is not to be determined from the Detailed Description, but rather from the claims as interpreted according to the full breadth permitted by the patent laws. It is to be understood that the embodiments shown and described herein are only illustrative of the principles of the present invention and that various modifications may be implemented by those skilled in the art without departing from the scope and spirit of the invention. 
     For example, although the various embodiments of PVT detectors employ a frequency-to-voltage converter, a frequency-to-current converter may be substituted therefore. In this case, the downstream elements are adapted to receive a current signal output from the frequency-to-current converter. 
     The present invention may be implemented as (analog, digital, or a hybrid of both analog and digital) circuit based processes, including possible implementation as a single integrated circuit (such as an ASIC or an FPGA), a multi chip module, a single card, or a multi-card circuit pack. As would be apparent to one skilled in the art, various functions of circuit elements may also be implemented as processing blocks in a software program. Such software may be employed in, for example, a digital signal processor, micro controller, or general purpose computer. 
     Also for purposes of this description, the terms “couple,” “coupling,” “coupled,” “connect,” “connecting,” or “connected” refer to any manner known in the art or later developed in which energy is allowed to be transferred between two or more elements, and the interposition of one or more additional elements is contemplated, although not required. Conversely, the terms “directly coupled,” “directly connected,” etc., imply the absence of such additional elements. 
     Also, for purposes of this description, it is understood that all gates are powered from a fixed voltage power domain (or domains) and ground unless shown otherwise. Accordingly, all digital signals generally have voltages that range from approximately ground potential to that of one of the power domains and transition (slew) quickly. However and unless stated otherwise, ground may be considered a power source having a voltage of approximately zero volts, and a power source having any desired voltage may be substituted for ground. Therefore, all gates may be powered by at least two power sources, with the attendant digital signals therefrom having voltages that range between the approximate voltages of the power sources. 
     Signals and corresponding nodes or ports may be referred to by the same name and are interchangeable for purposes here. 
     Transistors are typically shown as single devices for illustrative purposes. However, it is understood by those with skill in the art that transistors will have various sizes (e.g., gate width and length) and characteristics (e.g., threshold voltage, gain, etc.) and may consist of multiple transistors coupled in parallel to get desired electrical characteristics from the combination. Further, the illustrated transistors may be composite transistors. 
     As used in this specification and claims, the term “output node” refers generically to either the source or drain of a metal oxide semiconductor (MOS) transistor device (also referred to as a MOSFET), and the term “control node” refers generically to the gate of the MOSFET. Similarly, as used in the claims, the terms “source,” “drain,” and “gate” should be understood to refer either to the source, drain, and gate of a MOSFET or to the emitter, collector, and base of a bi polar device when the present invention is implemented using bi-polar transistor technology. 
     Unless explicitly stated otherwise, each numerical value and range should be interpreted as being approximate as if the word “about” or “approximately” preceded the value of the value or range. 
     It will be further understood that various changes in the details, materials, and arrangements of the parts which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the scope of the invention as expressed in the following claims. 
     The use of figure numbers and/or figure reference labels in the claims is intended to identify one or more possible embodiments of the claimed subject matter in order to facilitate the interpretation of the claims. Such use is not to be construed as necessarily limiting the scope of those claims to the embodiments shown in the corresponding figures. 
     It should be understood that the steps of the exemplary methods set forth herein are not necessarily required to be performed in the order described, and the order of the steps of such methods should be understood to be merely exemplary Likewise, additional steps may be included in such methods, and certain steps may be omitted or combined, in methods consistent with various embodiments of the present invention. 
     Although the elements in the following method claims, if any, are recited in a particular sequence with corresponding labeling, unless the claim recitations otherwise imply a particular sequence for implementing some or all of those elements, those elements are not necessarily intended to be limited to being implemented in that particular sequence. 
     Reference herein to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments necessarily mutually exclusive of other embodiments. The same applies to the term “implementation.” 
     The embodiments covered by the claims in this application are limited to embodiments that (1) are enabled by this specification and (2) correspond to statutory subject matter. Non-enabled embodiments and embodiments that correspond to non-statutory subject matter are explicitly disclaimed even if they fall within the scope of the claims.