Patent Publication Number: US-11024215-B2

Title: Display panel having dual-gate structure, control circuit, and display device

Description:
This application claims the benefit of U.S. provisional application Ser. No. 62/808,875, filed Feb. 22, 2019, the disclosure of which is incorporated by reference herein in its entirety. 
    
    
     TECHNICAL FIELD 
     The disclosure relates in general to a dual-gate display panel, a control circuit, and a display device, and more particularly to a dual-gate display panel, a control circuit, and a display device capable of raising the quality of visual effects. 
     BACKGROUND 
     A display panel usually has M*N subpixels being arranged in a matrix of M columns and N rows. For a non-dual-gate display panel, the column number of the subpixels M is equivalent to the number of source lines J (that is, M=J), and the row number of the subpixels N is equivalent to the number of gate lines K (that is, N=K). In the specification, M, N, J, K are positive integers, and their lower case letters represent indexes of the components. 
     On the other hand, for a dual-gate (hereinafter, DG) display panel, the column number of the subpixels M is equivalent to two times of source lines J (that is, M=2*J), and the row number of the subpixels N is equivalent to the half of the number of gate lines K (that is, N=½*K). Alternatively speaking, for the DG display panel, the number of source lines (J) is halved, and the number of gate lines (K) is doubled. 
     As the number of the source lines (J) in the DG display panel is reduced, the number of the (source) circuits can be halved. Thus, the area and the cost of the source drivers can be reduced, and the screen-to-body ratio can be raised. Because the screen-to-body ratio is an essential factor for the small-sized display panel, the small-sized amorphous silicon (a-Si) display panels starts to adopt the DG structure. 
     For illustration purpose, the subpixels are represented in a coordinated notation to indicate their positions. For example, a subpixel SP(m, n) (m=1˜M, and n=1˜N) is located at the m-th column and the n-th row. The subpixel SP(m, n) is electrically connected to a j-th (j=1˜J) source line and a k-th (k=1˜K) gate line. In the specification, an identical notation is used for representing a signal line and the control signal being transmitted by the signal line. For example, the k-th gate line GL[k] transmits the k-th gate control signal GL[k]. 
       FIGS. 1A and 1B  (prior art) are schematic diagrams illustrating the subpixel layout of a conventional DG display panel. An example of the conventional DG display panel having M=4, N=4, J=2, K=8 is shown. 
     For illustration purpose, different patterns of screentone are applied to represent different colors. The vertical screentone represents the red color, the dotted screentone represents the green color, and the diagonal screentone represents the blue color. In the specification, each of the pixels is assumed to include a red subpixel (SPr), a green subpixel (SPg) and a blue subpixel (SPb). The data voltage received by the red, green, and blue subpixels are respectively represented as dVr, dVg, and dVb. It should be noted that the colors of the subpixels and their layout/configuration/sequence are not limited in practical application. In the specification, the circuits corresponding to the positive polarity (+) are shown in the grid, and the circuits corresponding to the negative polarity (−) have horizontal screentone. 
       FIGS. 1A and 1B  show the polarities of the subpixels when an odd frame and an even frame are displayed, respectively. The duration for displaying an odd frame is defined as an odd frame duration (Tframe_odd), and the duration for displaying an even frame is defined as an even frame duration (Tframe_even). The lengths of the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) are equivalent. The polarities of all the subpixels are preferred to switch in the continuous frames. 
     The source lines S[ 1 ], S[ 2 ] are arranged vertically and parallel to each other while the gate lines GL[ 1 ]˜GL[ 8 ] are arranged horizontally and parallel to each other. The source line S[ 1 ] is placed in between and electrically connected to the subpixels located in the first column (m=1) and the ones located in the second column (m=2), and the source line S[ 2 ] is placed in between and electrically connected to the subpixels located in the third column (m=3) and the ones located at the fourth column (m=4). 
     As shown in  FIGS. 1A and 1B , the subpixels at the first row (SP(m, n), m=1˜M and n=1) are sandwiched by the gate line GL[ 1 ] and the gate line GL[ 2 ]. That is, the gate lines GL[ 1 ], GL[ 2 ] are respectively disposed at the top side, and the bottom side of the subpixels disposed at the first row (SP(m, n), m=1˜M and n=1). Similarly, the subpixels at the second row (SP(m, n), n=2) are sandwiched by the gate line GL[ 3 ] and the gate line GL[ 4 ]. That is, the gate lines GL[ 3 ], GL[ 4 ] are respectively disposed at the top side and the bottom side of the subpixels at the second row (SP(m,n), m=1˜M and n=2). 
     The relationships between the data voltages being supplied by the driving circuits  101 ,  102 , polarities of the data voltages, and the source lines from which the subpixels receive their data voltages during the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) are summarized in Table 1. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                   
                   
                   
                   
                 source 
                   
               
               
                   
                   
                   
                   
                 data 
                 line(s) 
                 subpixel(s) 
               
               
                   
                 frame 
                   
                 polarity 
                 voltage 
                 being 
                 being 
               
               
                   
                 dura- 
                 driving 
                 of data 
                 to be 
                 electrically 
                 electrically 
               
               
                 figure 
                 tion 
                 circuit 
                 voltage 
                 provided 
                 connected to 
                 connected to 
               
               
                   
               
             
            
               
                 FIG. 
                 odd 
                 driving 
                 positive 
                 dVr_dft 
                 S[1] 
                 SP(1, n) 
               
               
                 1A 
                 frame 
                 circuit 
                 (+) 
                 or 
                   
                 SP(2, n) 
               
               
                   
                 dura- 
                 101 
                   
                 dVg_dft 
               
               
                   
                 tion 
                 driving 
                 negative 
                 dVb_dft 
                 S[2] 
                 SP(3, n) 
               
               
                   
                   
                 circuit 
                 (−) 
                 or 
                   
                 SP(4, n) 
               
               
                   
                   
                 102 
                   
                 dVr_dft 
               
               
                 FIG. 
                 even 
                 driving 
                 positive 
                 dVb_dft 
                 S[2] 
                 SP(3, n) 
               
               
                 1B 
                 frame 
                 circuit 
                 (+) 
                 or 
                   
                 SP(4, n) 
               
               
                   
                 dura- 
                 101 
                   
                 dVr_dft 
               
               
                   
                 tion 
                 driving 
                 negative 
                 dVr_dft 
                 S[1] 
                 SP(1, n) 
               
               
                   
                   
                 circuit 
                 (−) 
                 or 
                   
                 SP(2, n) 
               
               
                   
                   
                 102 
                   
                 dVg_dft 
               
               
                   
               
            
           
         
       
     
     In the odd frame duration (Tframe_odd), each of the gate lines GL[k] (k=1˜K) is alternatively set to a high voltage level (H) for a gate control duration Tgl. Once all the gate lines GL[k] (k=1˜K) have been alternatively set to high voltage level (H), the even frame duration (Tframe_even) starts and the gate lines GL[k] (k=1˜K) alternatively set to high voltage level (H) for a gate control duration Tgl again. The flow is repetitively performed. 
     During the odd frame duration (Tframe_odd) (see  FIG. 1A ), the source line S[ 1 ] receives data voltages having positive polarity (+) from the driving circuit  101 , and the source line S[ 2 ] receives the data voltages having negative polarity (−) from the driving circuit  102 . Thus, during the odd frame duration (Tframe_odd), the source line S[ 1 ] continuously provides data voltages having positive polarity (+) to subpixels at the first column (m=1) and the second column (m=2), and the source line S[ 2 ] continuously provides data voltages having negative polarity (−) to subpixels at the third column (m=3) and the fourth column (m=4). 
     During the even frame duration (Tframe_even) (see  FIG. 1B ), the source line S[ 1 ] receives data voltages having negative polarity (−) from the driving circuit  102 , and the source line S[ 2 ] receives the data voltages having positive polarity (+) from the driving circuit  101 . Thus, during the even frame duration (Tframe_even), the source line S[ 1 ] continuously provides data voltages having positive polarity (+) to subpixels at the third column (m=3) and the fourth column (m=4), and the source line S[ 2 ] continuously provides data voltages having negative polarity (−) to subpixels at the first column (m=1) and the second column (m=2). 
     The subpixels in the first column P(m,n) (m=1 and n=1˜N) are enabled by the even-numbered gate lines GL[k] (k=even) to receive their data voltages. As the subpixels in the first column P(m,n) (m=1 and n=1˜N) are red subpixel (SPr), to which the source line S[ 1 ] provides the red data voltages having positive polarity (+)dVr during the odd frame duration (Tframe_odd) and the source line S[ 1 ] provides the red data voltages having negative polarity (−)dVr during the even frame duration (Tframe_even). 
     The subpixels in the second column P(m,n) (m=2 and n=1˜N) are enabled by the odd-numbered gate lines GL[k] (k=odd) to receive their data voltages. As the subpixels in the second column P(m,n) (m=2 and n=1˜N) are green subpixel (SPg), to which the source line S[ 1 ] provides the green data voltages having positive polarity (+)dVg during the odd frame duration (Tframe_odd) and the source line S[ 1 ] provides the green data voltages having negative polarity (−)dVg during the even frame duration (Tframe_even). 
     The subpixels in the third column P(m,n) (m=3 and n=1˜N) are enabled by the even-numbered gate lines GL[k] (k=even) to receive their data voltages. As the subpixels in the third column are blue subpixel (SPb), to which the source line S[ 2 ] provides the blue data voltages having negative polarity (−)dVb during the odd frame duration (Tframe_odd) and the source line S[ 2 ] provides the blue data voltages having positive polarity (+)dVb during the even frame duration (Tframe_even). 
     The subpixels in the fourth column P(m,n) (m=4 and n=1˜N) are enabled by the odd-numbered gate lines GL[k] (k=odd) to receive their data voltages. As the subpixels in the fourth column are red subpixel (SPr), to which the source line S[ 2 ] provides the red data voltages having negative polarity (−)dVr during the odd frame duration (Tframe_odd) and the source line S[ 2 ] provides the red data voltages having positive polarity (+)dVr during the even frame duration (Tframe_even). 
     Please refer to  FIGS. 1A and 1B  together. Controls to the subpixels are basically identical in the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even), except that the polarities of the data voltages are switched. Thus, only the panel control signals in the odd frame duration (Tframe_odd) are illustrated. 
       FIG. 2  (prior art) is a schematic waveform diagram showing the panel control signals to be applied to a display panel having the conventional DG structure. The horizontal axis represents different time points t 0 ˜t 6 . The frame duration between time point t 0  to time point t 6  is assumed to be an odd frame duration (Tframe_odd). The vertical axis shows gate control signals GL[ 1 ], GL[ 2 ], and source signals S[ 1 ], S[ 2 ]. The voltage levels of the gate lines GL[ 1 ], GL[ 2 ] determine which of the subpixels are enabled to receive the data voltages provided by the source lines S[ 1 ], S[ 2 ]. In the specification, it is assumed that the subpixels are enabled by high voltage level (H). 
     The odd frame duration (Tframe_odd) can be divided into N line control durations Tln (that is, Tframe_odd=N*Tln), a duration for controlling the subpixels located at the same row SP( 1 , n)˜SP(M, n) for receiving their data voltages. Moreover, the line control duration Tln is equivalent to two times of the gate control duration Tgl (that is, Tln=2*Tgl). The gate control duration Tgl is a duration for controlling the subpixels located at the same row and electrically connected to the same gate line GL[k] (k=(n+1)/2 when n is odd, or k=n/2 when n is even). 
     In practical application, a horizontal synchronization Hsync duration may exist between every two continuous frame durations (Tframe_odd and/or Tframe_even), and vertical synchronization durations Vsync may exist between each line control duration Tln. For the sake of illustration, the horizontal and vertical synchronization durations Hsync, Vsync are not shown nor described. 
     During the gate control duration Tgc between time point t 0  and time point t 1 , the gate line GL[ 1 ] is set to high voltage level (H), the subpixel SP( 2 ,  1 ) receives its data voltage (+)dV 21 =(+)dVg through the source line S[ 1 ], and the subpixel SP( 4 ,  1 ) receives its data voltage (−)dV 41 =(−)dVr) through the source line S[ 2 ]. During the gate control duration Tgc between time point t 1  and time point t 2 , the gate line GL[ 2 ] is set to high voltage level (H), the subpixel SP( 1 ,  1 ) receives its data voltage (+)dV 11 =(+)dVr through the source line S[ 1 ], and the subpixel SP( 3 ,  1 ) receives its data voltage (−)dV 31 =(−)dVb through the source line S[ 2 ]. During the gate control duration Tgc between time point t 2  and time point t 3 , the gate line GL[ 3 ] is set to high voltage level (H), the subpixel SP( 2 ,  2 ) receives its data voltage (+)dV 22 =(+)dVg through the source line S[ 1 ], and the subpixel SP( 4 ,  2 ) receives its data voltage (−)dV 41 =(−)dVr through the source line S[ 2 ]. During the gate control duration Tgc between time point t 3  and time point t 4 , the gate line GL[ 4 ] is set to logic high voltage level (H), the subpixel SP( 1 ,  2 ) receives its data voltage (+)dV 12 =(+)dVr through the source line S[ 1 ], and the subpixel SP( 3 ,  2 ) receives its data voltage (−)dV 32 =(−)dVb through the source line S[ 2 ]. 
     The subpixels at the same column but different row have similar operations. That is, they have the same color, and they receive their data voltages from the same source lines, except they are enabled by different gate lines. For example, although being respectively enabled by the gate lines GL[ 1 ], GL[ 3 ], both of the subpixel SP( 2 ,  1 ), SP( 2 , 2 ) are green subpixels (SPg) receiving their data voltages, that is, (+)dVg during the odd frame duration (Tframe_odd) and (−)dVg during the even frame duration (Tframe_even), from the source line S[ 1 ]. Similarly, although being respectively enabled by the gate lines GL[ 1 ], GL[ 3 ], both of the subpixel SP( 4 ,  1 ), SP( 4 , 2 ) are red subpixels (SPr) receiving their data voltages, that is, (−)dVr during the odd frame duration (Tframe_odd) and (+)dVr during the even frame duration (Tframe_even), from the source line S[ 2 ]. 
     Please refer to  FIGS. 1A, 1B, and 2  together. For the conventional DG display panel, the polarities of the subpixels are switched in every two columns because each source line is electrically connected to subpixels located at two adjacent columns. Generally, the luminance of the pixel is determined by an average value of the data voltage having positive polarity (+) and the data voltage having a negative polarity (−). Ideally, for the same grey level, magnitudes of the data voltages having the positive polarity (+) and the negative polarity (−) should be identical to assure that the luminance of the same subpixel should remain consistent in different frame durations, regardless the polarity changes of the data voltages. 
     As illustrated above, the subpixels at every two adjacent columns are controlled by a driving circuit providing data voltages having positive polarity in one frame duration and by another driving circuit having negative polarity in another frame duration. However, the driving capabilities of different driving circuits might not be symmetric, and this results in degrading the visual effects. 
     For the sake of illustration, the input image being displayed by the DG display panel can be assumed to be a solid color picture. Thus, in one frame duration, the magnitudes of the data voltages received by the subpixels in the same color should be equivalent. Moreover, the data voltages received by each individual subpixel in the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) should be equivalent, although the data voltages are generated by different driving circuits. 
     In an ideal case, the magnitude of the data voltage being transmitted to the subpixel SP( 1 , 1 ) should be equivalent to the magnitude of the data voltage being transmitted to the subpixel SP( 4 , 1 ), despite that the data voltages received by the subpixels SP( 1 ,  1 ), SP( 4 ,  1 ) are provided by the driving circuit  101 ,  102 , respectively. In addition, the data voltages received by the subpixel SP( 1 ,  1 ) during the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) should be equivalent, despite that these data voltages are originated from different driving circuits  101 ,  102 . 
     However, the driving capabilities of the driving circuits  101 ,  102  might not match to each other. Thus, the luminance of the subpixels SP( 1 ,  1 ), SP( 4 ,  1 ) during the same frame duration might not be the same, and the luminance of the subpixel SP( 1 ,  1 ) in different frame durations might not be the same either. Consequentially, a vertical pattern phenomenon with a width of every two subpixels might appear on the DG display panel because every two subpixels share the same source line being controlled by different driving circuits whose driving capabilities are asymmetric. Thus, the screen might have column flickering on it, especially when the position of the display panel is shaken by the influence of the external force. 
     SUMMARY 
     The disclosure is directed to a dual-gate display panel, a control circuit, and a display device. While displaying solid color pictures, data voltages being supplied to the source lines swift in between the same magnitude but opposite polarities. With the DG structure, the width of the vertical pattern caused by clamping between the positive and negative frames is halved so that the visual effect is improved. 
     According to one embodiment, a display panel is provided. The display panel includes a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. The first subpixel and the third subpixel are electrically connected to a first source line. The second subpixel and the fourth subpixel are electrically connected to a second source line. The first, the second, the third, and the fourth subpixels are sequentially arranged along a first direction. 
     According to another embodiment, a control circuit is provided. The control circuit is electrically connected to a display panel including a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. The first, the second, the third, and the fourth subpixels are sequentially arranged along a first direction. The control circuit includes a source driver. The source driver includes a first source line being electrically connected to the first subpixel and the third subpixel, a second source line being electrically connected to the second subpixel and the fourth subpixel. 
     According to an alternative embodiment, a display device is provided. The display device includes a display panel and a control circuit. The display panel includes a first subpixel, a second subpixel, a third subpixel, and a fourth subpixel. The first, the second, the third, and the fourth subpixels are sequentially arranged along a first direction. The control circuit includes a source driver, and the source driver includes a first source line, a second source line, a first driving circuit and a second driving circuit. The first source line is electrically connected to the first subpixel and the third subpixel, and the second source line is electrically connected to the second subpixel and the fourth subpixel. The first driving circuit is electrically connected to the first source line during a first gate control duration and electrically connected to the second source line during a second gate control duration. The second driving circuit is electrically connected to the second source line during the first gate control duration and electrically connected to the first source line during the second gate control duration. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  (prior art) are schematic diagrams illustrating subpixel layout in a conventional DG display panel. 
         FIG. 2  (prior art) is a schematic waveform diagram showing the panel control signals to be applied to the conventional DG display panel for displaying the solid color picture. 
         FIG. 3  is a schematic diagram of a display device according to the embodiment of the present disclosure. 
         FIG. 4  is a schematic diagram illustrating an exemplary DG structure of the subpixels, source lines, gate lines, and switches. 
         FIG. 5A  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 1 ] is set to high voltage level (H) during the odd frame duration (Tframe_odd). 
         FIG. 5B  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 2 ] is set to logic voltage level (H) during the odd frame duration (Tframe_odd). 
         FIG. 5C  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 3 ] is set to high voltage level (H) during the odd frame duration (Tframe_odd). 
         FIG. 6A  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 1 ] is set to high voltage level (H) during the even frame duration (Tframe_even). 
         FIG. 6B  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 2 ] is set to high voltage level (H) during the even frame duration (Tframe_even). 
         FIG. 7  is a waveform diagram illustrating changes in the panel control and subpixels shown in  FIGS. 5A ˜ 5 C,  6 A, and  6 B. 
         FIGS. 8A and 8B  are schematic diagrams illustrating another panel layout and associated control mechanism. 
         FIG. 9A  is a schematic diagram illustrating operations of still another panel layout and associated control mechanism during the odd frame duration (Tframe_odd). 
         FIG. 9B  is a schematic diagram illustrating operations of still another panel layout and associated control mechanism during the even frame duration (Tframe_even). 
         FIG. 10A  is a schematic diagram illustrating operations of an alternative panel layout and associated control mechanism during the odd frame duration. 
         FIG. 10B  is a schematic diagram illustrating operations of the alternative panel layout and associated control mechanism during the even frame duration (Tframe_even). 
         FIGS. 11A and 11B  are schematic diagrams showing an exemplary display panel including a mixture of different layout of the subpixels. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DETAILED DESCRIPTION 
     In the specification, a DG display panel is provided. The layout of the DG display panel is designed so that the J source lines are electrically connected to the subpixels in an interleaving manner. That is, each of the odd-numbered source lines S[j] (j=odd) is electrically connected to the subpixels which are respectively located at two odd-numbered columns P(m, n) (m=2*j−1 or m=2*j+1), and each of the even-numbered source lines S[j](j=even) is electrically connected to the subpixels which are respectively located at two even-numbered columns P(m, n) (m=2*(j−1) or m=2*j). For example, the source line S[ 1 ] is electrically connected to the subpixels at the first column (m=1) and the third column (m=3), and the source line S[ 2 ] is electrically connected to the subpixels at the second column (m=2) and the fourth column (m=4). 
       FIG. 3  is a schematic diagram of a DG display device according to the embodiment of the present disclosure. The display device  3  includes a DG display panel  31  and a control circuit  32 , and the control circuit  32  further includes a timing controller  321 , a source driver  325 , and a gate driver  323 . The timing controller  321  generates and transmits gate timing control signals Stg and the source timing control signals Sts to the source driver  325  and the gate driver  323 , respectively. Then, the driving circuits in the source driver  325  and the shift control circuits in the gate driver  323  respectively transmit the data voltages dV and gate control signals Sgc to the subpixels. The data voltages dV and gate control signals Sgc are defined as panel control signals. Detail illustrations related to the timing control signals and the panel control signals are omitted to avoid redundancy. 
     The subpixels are arranged in a matrix with M columns and N rows, and every three subpixels at the same row jointly form a pixel (P). Thus, the display panel includes pixels being arranged in M/ 3  columns and N rows. Ideally, M is a multiple of 3. It is assumed that each of the pixels P( 1 ,  1 ), P( 2 ,  1 ), P( 1 ,  1 ), P( 2 , N), P(M/ 3 ,  1 ), P(M/ 3 , N) include three subpixels (that is, a red subpixel (SPr), a green subpixel (SPg), and a blue subpixel SPb). Although the sequence of the subpixels is assumed to be R-G-B in the exemplary DG structures, other sequences of subpixels such as G-B-R, G-R-B, B-G-R, can be used as well. 
     The gate driver  323  includes shift control circuits SR[k] (k=1˜K) and gate lines GL[k] (k=1˜K). The shift control circuits SR[k] (k=1˜K) are respectively electrically connected to the gate lines GL[k] (k=1˜K). Every two adjacent gate lines are separately arranged at the upper side and the lower side of the subpixels located at the same row. The interconnections between the gate lines GL[k] (k=1˜K) and the subpixels SP(m, n) (m=1˜M, n=1˜N) may vary with different exemplary DG structures. 
     The source driver  325  includes J source driving circuits, source lines S[j] (j=1˜J), and M switches (M=2*J). Every two adjacent source lines can be considered as a pair, and every four switches are jointly used with a pair of the source lines. The connections and correspondences between the source lines and the switches are shown in  FIG. 4 . 
       FIG. 4  is a schematic diagram illustrating the common part of the embodiments according to the embodiments of the present disclosure. According to the embodiments of the present disclosure, the layout of the subpixels and associated interconnections is repeated in a unit of every four subpixels. Alternatively speaking, every four horizontally adjacent subpixels have similar layouts and similar interconnections with the source lines and gate lines. Thus, four subpixels SP( 1 ,  1 )˜SP( 4 ,  1 ) are shown, together with two gate lines GL[ 1 ], GL[ 2 ], two source lines S[ 1 ], S[ 2 ], four switches sw 1 , sw 2 , sw 3 , sw 4 , and two driving circuits  401 ,  402 . 
     In all the exemplary DG structures, each of the odd-numbered source lines (S[j], j=odd) is electrically connected to the subpixels located at two odd-numbered columns P(m, n) (m=j*2−1 or m=j*2+1), and each of the even-numbered source lines (S[j], j=even) is electrically connected to the subpixels located at two even-numbered columns P(m, n) (m=(j−1)*2 or m=j*2). For example, the source line S[ 1 ] is electrically connected to the subpixels P(m, n) (m=1 or m=3), and the source line S[ 2 ] is electrically connected to the subpixels P(m, n) (m=2 or m=4). 
     The subpixel SP(m, n) is electrically connected to one of the source lines S[j] (j=(m+1)/2 or j=(m−1)/2) when m is odd. For example, the subpixels located in the first column (m=1) and the third column (m=3) are electrically connected to the source line S[ 1 ]. On the other hand, the subpixel SP(m, n) is electrically connected to one of the source lines S[j] (j=m/2+1 or j=m/2) when m is even. For example, the subpixels located in the second column (m=2) and the fourth column (m=4) are electrically connected to the source line S[ 2 ]. The connections between the subpixels SP( 1 ,  1 ), SP( 2 ,  1 ), SP( 3 ,  1 ), SP( 4 ,  1 ) and the source lines S[ 1 ], S[ 2 ] are summarized in Table 2. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 2 
               
             
            
               
                   
                   
               
               
                   
                 subpixels 
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 SP(1, 1) 
                 SP(2, 1) 
                 SP(3, 1) 
                 SP(4, 1) 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 source line 
                 S[1] 
                 S[2] 
                 S[1] 
                 S[2] 
               
               
                   
                   
               
            
           
         
       
     
     The gate lines GL[k] (k=1˜K) are parallel to the first direction (for example, horizontal direction), and the source lines S[j] (j=1˜J) are parallel to a second direction (for example, vertical direction). The first direction and the second direction are orthogonal. The gate line GL[k] is placed along the upper side of the subpixels SP(m, n) (n=(k+1)/2) when k is odd, and the gate line GL[k] is placed along the lower side of the subpixels SP(m, n) (n=k/2) when k is even. For example, the gate line GL[ 1 ] is placed along the upper side of the subpixel SP(m,  1 ), and the gate line GL[ 2 ] is placed along the lower side of the subpixel SP(m,  1 ). 
     Depending on a different design, the interconnections between the subpixels SP( 1 , 1 )˜SP( 4 , 1 ) and the gate lines GL[ 1 ], GL[ 2 ] may vary. Whereas, the interconnections between the subpixels SP( 1 ,  1 )˜SP( 4 ,  1 ) and the source lines S[ 1 ], S[ 2 ] n different exemplary DG structures are similar. That is, the subpixels SP( 1 ,  1 ), SP( 3 ,  1 ) are always electrically connected to the source line S[ 1 ], and the subpixels SP( 2 ,  1 ), SP( 4 ,  1 ) are always electrically connected to the source line S[ 2 ]. The internal connections between the subpixel SP( 3 ,  1 ) and the source line S[ 1 ] might be disposed at the upper side or lower side of the subpixel SP( 2 , 1 ), and the internal connections between the subpixel SP( 2 ,  1 ) and the source line S[ 2 ] might be disposed at the upper side or lower side of the subpixel SP( 3 ,  1 ). 
     The switch sw 1  is electrically connected to the driving circuit  401  and the source line S[ 1 ], the switch sw 2  is electrically connected to the driving circuit  402  and the source line S[ 2 ], the switch sw 3  is electrically connected to the driving circuit  402  and the source line S[ 1 ], and the switch sw 4  is electrically connected to the driving circuit  401  and the source line S[ 2 ]. When a switch is turned on, the driving circuit and the source line at its two terminals are conducted. The controls of switches statuses are summarized in Table 3. The switching statuses of the switches sw 1 , sw 2  are synchronized and opposite to those of the switches sw 3 , sw 4 . 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 3 
               
             
            
               
                   
                   
               
               
                   
                 switches 
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 sw1 
                 sw2 
                 sw3 
                 sw4 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 odd frame duration 
                 ON 
                   
                 OFF 
                   
               
               
                   
                 even frame duration 
                 OFF 
                   
                 ON 
               
               
                   
                   
               
            
           
         
       
     
     For illustration purpose, the DG display panels are assumed to display a solid color picture having a default color. The default color is generated by a mixture of the red light emitted by the red subpixel (SPr), the green light emitted by the green subpixel (SPg), and the blue light emitted by the blue subpixel (SPb). To display the default color, the luminance of all the red subpixels (SPr) should be the same, the luminance of all the green subpixels (SPg) should be the same, and luminance of all the blue subpixels (SPb) should be the same. Thus, all the red subpixels (SPr) should receive a default red data voltage dVr_dft, all the green subpixels (SPg) should receive a default green data voltage dVg_dft, and all the blue subpixels (SPb) should receive a default blue data voltage dVb_dft. In the practical application, the magnitudes of the default data voltages (dVr_dft, dVg_dft, dVb_dft) should be determined by the grey levels of the input picture. 
     In the following embodiments, statuses of the subpixels (SP) are distinguished by different styles of edges. The subpixels (SP) having dotted edges are the ones have not received their data voltages. The subpixels (SP) having thick solid edges are the ones which are currently receiving their data voltages from the driving circuits. The subpixels (SP) having thin solid edges are the ones who have received their data voltage before. 
     Furthermore, the gate lines being set to high voltage level (H) are shown in thick solid lines. Moreover, the data voltages being supplied to the subpixels during the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) are notated without and with an apostrophe, respectively. For example, dV 31  and dV 31 ′ respectively represent the data voltage being supplied to the subpixel SP( 3 ,  1 ) during the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even). One of the data voltages dV 31 , dV 31 ′ has the positive polarity (+) and the other one of the data voltages dV 31 , dV 31 ′ has the negative polarity (−), depending on the practical application. 
       FIGS. 5A ˜ 5 C,  6 A, and  6 B represent different operation states of a first exemplary DG structure.  FIGS. 5A ˜ 5 C are corresponding to the odd frame duration (Tframe_odd) and  FIGS. 6A and 6B  are corresponding to the even frame duration (Tframe_even). In  FIGS. 5A ˜ 5 C, the source lines S[ 1 ], S[ 2 ], S[ 3 ], S[ 4 ] are respectively electrically connected to the driving circuits  501 ,  502 ,  503 ,  504 . In  FIGS. 6A and 6B , the source lines S[ 1 ], S[ 2 ] are crossly electrically connected to the driving circuits  501 ,  502 , and the source lines S[ 3 ], S[ 4 ] are crossly electrically connected to the driving circuits  503 ,  504 . The layout of the subpixels and associated interconnections is repeated in a unit of every four subpixels. Therefore, the layout of the subpixels SP( 1 , 1 )˜SP( 4 ,  1 ) are similar to the layout of the subpixels SP( 5 ,  1 )˜SP( 8 ,  1 ) and the layout of the subpixels SP( 1 , 2 )˜SP( 4 ,  2 ). 
       FIG. 5A  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 1 ] is set to high voltage level (H) during the odd frame duration (Tframe_odd). As the gate line GL[ 1 ] is set to high voltage level (H), the subpixels connected to the gate line GL[ 1 ], that is, subpixels SP( 3 ,  1 ), SP( 4 ,  1 ), SP( 7 ,  1 ), SP( 8 ,  1 ), receive their data voltages (dV 31 , dV 41 , dV 71 , dV 81 ). 
     As a blue subpixel (SPb), the subpixel SP( 3 ,  1 ) receives the data voltage dV 31  having a magnitude of default blue data voltage dVb_dft and positive polarity (+) from the driving circuit  501 . As a red subpixel (SPr), the subpixel SP( 4 ,  1 ) receives the data voltage dV 41  having a magnitude of default red data voltage dVr_dft and negative polarity (−) from the driving circuit  502 . As a red subpixel (SPr), the subpixel SP( 7 ,  1 ) receives the data voltage dV 71  having a magnitude of default red data voltage dVr_dft and positive polarity (+) from the driving circuit  503 . As a green subpixel (Spg), the subpixel SP( 8 ,  1 ) receives the data voltage dV 81  having a magnitude of default green data voltage dVg_dft and negative polarity (−) from the driving circuit  504 . 
       FIG. 5B  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 2 ] is set to high voltage level (H) during the odd frame duration (Tframe_odd). As the gate line GL[ 2 ] is set to high voltage level (H), the subpixels SP( 1 ,  1 ), SP( 2 ,  1 ), SP( 5 ,  1 ), SP( 6 ,  1 ) being electrically connected to the gate line GL[ 2 ] are enabled to receive their data voltages dV 11 , dV 21 , dV 51 , dV 61 . 
     As a red subpixel (SPr), the subpixel SP( 1 ,  1 ) receives the data voltage dV 11  having a magnitude of default red data voltage dVr_dft and positive polarity (+) from the driving circuit  501 . As a green subpixel (SPg), the subpixel SP( 2 ,  1 ) receives a magnitude of default green data voltage dVg_dft and the data voltage dV 21  having a negative polarity (−) from the driving circuit  502 . As a green subpixel (SPg), the subpixel SP( 5 ,  1 ) receives the data voltage dV 51  having a magnitude of default green data voltage dVg_dft and positive polarity (+) from the driving circuit  503 . As a blue subpixel(SPb), the subpixel SP( 6 ,  1 ) receives the data voltage dV 61  having a magnitude of default blue data voltage dVb_dft and negative polarity (−) from the driving circuit  504 . 
       FIG. 5C  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 3 ] is set to high voltage level (H) during the odd frame duration (Tframe_odd). As the gate line GL[ 3 ] is set to high voltage level (H), the subpixels SP( 3 ,  2 ), SP( 4 ,  2 ), SP( 7 ,  2 ), SP( 8 ,  2 ) being electrically connected to the gate line GL[ 3 ] are enabled to receive their data voltages dV 32 , dV 42 , dV 72 , dV 82 . 
     As a blue subpixel (SPb), the subpixel SP( 3 ,  2 ) receives the data voltage dV 32  having a magnitude of default blue data voltage dVb_dft and positive polarity (+) from the driving circuit  501 . As a red subpixel (SPr), the subpixel SP( 4 ,  2 ) receives the data voltage dV 42  having a magnitude of default red data voltage dVr_dft and negative polarity (−) from the driving circuit  502 . As a red subpixel (SPr), the subpixel SP( 7 ,  2 ) receives the data voltage dV 71  having a magnitude of default red data voltage dVr_dft and positive polarity (+) from the driving circuit  503 . As a green subpixel (SPg), the subpixel SP( 8 ,  2 ) receives the data voltage dV 81  having a magnitude of default green data voltage dVg_dft and negative polarity (−) from the driving circuit  504 . 
     Please refer to  FIGS. 5A and 5C  together. The operations of panel control signals related to the subpixels at the third row in  FIG. 5C  are similar to those at the first row in  FIG. 5A . 
       FIG. 6A  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 1 ] is set to high voltage level (H) during the even frame duration (Tframe_even). Please refer to  FIGS. 5A and 6A  together. In  FIG. 6A , the voltage levels of the gate lines GL[ 1 ], GL[ 2 ], the subpixels being enabled for receiving data voltages SP( 3 , 1 ), SP( 4 , 1 ), SP( 7 , 1 ), SP( 8 , 1 ), the data voltages being supplied to the subpixels dVb_dft, dVr_dft, dVr_dft, dVg_dft, and the source lines transmitting the data voltage S[ 1 ], S[ 2 ] are the same as the ones in  FIG. 5A , but the polarities of these data voltages are swapped. 
       FIG. 6B  is a schematic diagram illustrating the first exemplary DG structure when the gate line GL[ 2 ] is set to high voltage level (H) during the even frame duration (Tframe_even). Please refer to  FIGS. 5B and 6B  together. In  FIG. 6B , the voltage levels of the gate lines GL[ 1 ], GL[ 2 ], the subpixels being enabled for receiving data voltages SP( 1 , 1 ), SP( 2 , 1 ), SP( 5 , 1 ), SP( 6 , 1 ), the data voltages being supplied to the subpixels dVr_dft, dVg_dft, dVg_dft, dVb_dft, and the source lines transmitting the data voltage S[ 1 ], S[ 2 ] are the same as the ones in  FIG. 5B , but the polarities of these data voltages are swapped. 
     In  FIGS. 5A ˜ 5 C,  6 A and  6 B, the touch sensing electrode  51  is formed in between the subpixels at the fourth column SP(m, n) (m=4 and n=1˜N) and the subpixels at the fifth column SP(m, n) (m=5 and n=1˜N), and the touch sensing electrode  53  is formed at the right side of the subpixels at the eighth column SP(m, n) (m=8 and n=1˜N). As the touch sensing electrodes  51 ,  53  do not cross over any of the source lines S[ 1 ], S[ 2 ], nor the interconnections between the source lines S[ 1 ], S[ 2 ] and the subpixels SP(m, n) (m=1˜8 and n=1˜2), such layout plan can simplify the manufacturing procedure of the DG display panel. 
       FIG. 7  is a waveform diagram illustrating changes in the panel control signals and subpixels shown in  FIGS. 5A ˜ 6 B. Please refer to  FIGS. 5A ˜ 5 C,  6 A,  6 B, and  7  together. In  FIG. 7 , the duration between time point t 0  and time point t 4  corresponds to the odd frame duration (Tframe_odd), and the duration between the time point t 4  to the time point t 8  corresponds to the even frame duration (Tframe_even). For both the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even), N rows (lines) of subpixels should be respectively enabled. Therefore, both the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) include N line control durations Tln (Tframe_odd=Tframe_even=N*Tln). Furthermore, each of the line control duration Tln includes two gate control durations Tgc. 
     Please refer to  FIGS. 5A, 6A, and 7  together.  FIGS. 5A and 6A  are corresponding to the duration from the time point t 0  to the time point t 1  and the duration from the time point t 4  to time point t 5  in  FIG. 7 , respectively. In FIGS.  5 A and  6 A, the settings of the source lines S[ 1 ]˜S[ 4 ], gate lines GL[ 1 ]˜GL[ 4 ] and subpixels SP( 3 ,  1 ), SP( 4 ,  1 ), SP( 7 ,  1 ), SP( 8 ,  1 ) are similar, but the connections between the source lines S[ 1 ]˜S[ 4 ] and driving circuits  501 ˜ 504  and polarities of the transmitted data voltages are changed. For the sake of comparison, the data voltages being supplied to the subpixels in  FIGS. 5A and 6A  are summarized in Table 4. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 4 
               
             
            
               
                   
                   
               
               
                   
                 data voltages 
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 FIG. 5A 
                 FIG. 6A 
                   
                   
               
               
                   
                 (duration 
                 (duration 
                 subpixel 
                 magnitude 
               
               
                   
                 t0~t1 in 
                 t3~t4 in 
                 receiving 
                 of data 
               
               
                   
                 FIG. 7) 
                 FIG. 7) 
                 data voltage 
                 voltage 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 source 
                 j = 1 
                 (+)dV31 
                 (−)dV31′ 
                 SP(3, 1) 
                 dVb_dft 
               
               
                 lines 
                 j = 2 
                 (−)dV41 
                 (+)dV41′ 
                 SP(4, 1) 
                 dVr_dft 
               
               
                 S[j] 
                 j = 3 
                 (+)dV71 
                 (−)dV71′ 
                 SP(7, 1) 
                 dVr_dft 
               
               
                   
                 j = 4 
                 (−)dV81 
                 (+)dV81′ 
                 SP(8, 1) 
                 dVg_dft 
               
               
                   
               
            
           
         
       
     
     Please refer to  FIGS. 5B, 6B, and 7  together.  FIGS. 5B and 6B  are corresponding to the duration from the time point t 1  to the time point t 2  and the duration from the time point t 5  to time point t 6  in  FIG. 7 , respectively. In  FIGS. 5B and 6B , the settings of the source lines S[ 1 ]˜S[ 4 ], gate lines GL[ 1 ]˜GL[ 4 ] and subpixels SP( 1 ,  1 ), SP( 2 ,  1 ), SP( 5 ,  1 ), SP( 6 ,  1 ) are similar, but connections between the source lines S[ 1 ]˜S[ 4 ] and driving circuits  501 ˜ 504  and polarities of the transmitted data voltages are changed. For the sake of comparison, the data voltages being supplied to the subpixels in  FIGS. 5B and 6B  are summarized in Table 5. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 5 
               
             
            
               
                   
                   
               
               
                   
                 Data voltages 
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 FIG. 5B 
                 FIG. 6B 
                   
                   
               
               
                   
                 (duration 
                 (duration 
                 subpixel 
                 magnitude 
               
               
                   
                 t1~t2 in 
                 t5~t6 in 
                 receiving 
                 of data 
               
               
                   
                 FIG. 7) 
                 FIG. 7) 
                 data voltage 
                 voltage 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 source 
                 j = 1 
                 (+)dV11 
                 (−)dV11′ 
                 SP(1, 1) 
                 dVr_dft 
               
               
                 lines 
                 j = 2 
                 (−)dV21 
                 (+)dV21′ 
                 SP(2, 1) 
                 dVg_dft 
               
               
                 S[j] 
                 j = 3 
                 (+)dV51 
                 (−)dV51′ 
                 SP(5, 1) 
                 dVg_dft 
               
               
                   
                 j = 4 
                 (−)dV61 
                 (+)dV61′ 
                 SP(6, 1) 
                 dVb_dft 
               
               
                   
               
            
           
         
       
     
     Please refer to  FIGS. 5A ˜ 5 C,  6 A,  6 B, and  7  together. The interconnections between the subpixel SP(m, n), the source line S[j] and the gate line GL[k] based on the first exemplary DG structure are be summarized in Table 6. 
     
       
         
           
               
               
               
             
               
                 TABLE 6 
               
             
            
               
                   
               
               
                 first exemplary DG structure 
                 gate line GL[k] 
                   
               
            
           
           
               
               
               
            
               
                 FIGS. 5A~5C, 6A, 6B 
                 k = odd 
                 k = even 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                 source 
                 j = odd 
                 j = (m − 1)/2 
                 j = (m + 1)/2 
               
               
                 line 
                   
                 k = (n*2) − 1 
                 k = n*2 
               
               
                 S[j] 
                 j = even 
                 j = m/2 
                 j = m/2 + 1 
               
               
                   
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                   
               
            
           
         
       
     
     The operations of the gate lines GL[ 1 ], GL[ 2 ], source lines S[ 1 ], S[ 2 ] and the subpixels SP( 1 ,  1 ), SP( 2 ,  1 ), SP( 3 ,  1 ), SP( 4 , 1 ) mentioned in the embodiments above are illustrated as examples, and the control mechanism can be applied to other gate lines GL[k] (k=1˜K), source lines S[j] (j=1˜J), and subpixels SP(m, n) (m=1˜M and n=1˜N) on the display panel. Moreover, the color sequence and combinations of the subpixels may vary in practical application. Therefore, the colors of the subpixels are not shown in the following exemplary DG structures. 
       FIGS. 8A and 8B  are schematic diagrams illustrating a second exemplary DG structure. The interconnections between the subpixel SP(m, n), the source line S[j] and the gate line GL[k] based on the second exemplary DG structure are summarized in Table 7. 
     
       
         
           
               
               
               
             
               
                 TABLE 7 
               
             
            
               
                   
               
               
                 second exemplary DG structure 
                 gate line GL[k] 
                   
               
            
           
           
               
               
               
            
               
                 FIGS. 8A and 8B 
                 k = odd 
                 k = even 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                 source 
                 j = odd 
                 j = (m + 1)/2 
                 j = (m − 1)/2 
               
               
                 line 
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                 S[j] 
                 j = even 
                 j = m/2 + 1 
                 j = m/2 
               
               
                   
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                   
               
            
           
         
       
     
       FIGS. 9A and 9B  are schematic diagrams illustrating operations of the third exemplary DG structure. The interconnections between the subpixel SP(m, n), the source line S[j] and the gate line GL[k] based on the third exemplary DG structure are summarized in Table 8. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 8 
               
             
            
               
                   
                   
               
               
                   
                 third exemplary DG structure 
                   
                 gate line GL[k] 
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 FIGS. 9A and 9B 
                   
                 k = odd 
                 k = even 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
            
               
                   
                 source 
                 j = odd 
                 j = (m + 1)/2 
                 j = (m − 1)/2 
               
               
                   
                 line 
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                   
                 S[j] 
                 j = even 
                 j = m/2 
                 j = m/2 + 1 
               
               
                   
                   
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                   
                   
               
            
           
         
       
     
       FIGS. 10A and 10B  are schematic diagrams illustrating operations of the fourth exemplary DG structure. The interconnections between the subpixel SP(m,n), the source line S[j] and the gate line GL[k] based on the fourth exemplary DG structure are summarized in Table 9. 
     
       
         
           
               
               
               
             
               
                 TABLE 9 
               
             
            
               
                   
               
               
                 Fourth exemplary DG structure 
                 gate line GL[k] 
                   
               
            
           
           
               
               
               
            
               
                 FIGS. 10A, 10B 
                 k = odd 
                 k = even 
               
               
                   
               
            
           
           
               
               
               
               
            
               
                 source 
                 j = odd 
                 j = (m − 1)/2 
                 j = (m + 1)/2 
               
               
                 line 
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                 S[j] 
                 j = even 
                 j = m/2 + 1 
                 j = m/2 
               
               
                   
                   
                 k = n*2 − 1 
                 k = n*2 
               
               
                   
               
            
           
         
       
     
     Four different exemplary DG structures are illustrated above. Based on different viewpoints, some connections rules can be applied to these DG structures. 
     Depending on the gate lines being connected to, the subpixels can be defined as subpixel groups. The four exemplary DG structure can be classified into two categories, a first category includes the first and the second exemplary DG structures, and a second category includes the third and the fourth exemplary DG structures. Please refer to Table 10 for such classification. 
     
       
         
           
               
             
               
                 TABLE 10 
               
               
                   
               
             
            
               
                 first category 
               
            
           
           
               
               
               
            
               
                 subpixels in subpixel 
                   
                   
               
               
                 group 
                 SP(1, 1) and SP(2, 1) 
                 SP(3, 1) and SP(4, 1) 
               
               
                   
               
               
                 first exemplary DG 
                 GL[2] 
                 GL[1] 
               
               
                 structure 
               
               
                 second exemplary DG 
                 GL[1] 
                 GL[2] 
               
               
                 structure 
               
               
                   
               
            
           
           
               
            
               
                 second category 
               
            
           
           
               
               
               
            
               
                 subpixels in subpixel 
                   
                   
               
               
                 group 
                 SP(1, 1) and SP(4, 1) 
                 SP(2, 1) and SP(3, 1) 
               
               
                   
               
               
                 third exemplary DG 
                 GL[1] 
                 GL[2] 
               
               
                 structure 
               
               
                 fourth exemplary DG 
                 GL[2] 
                 GL[1] 
               
               
                 structure 
               
               
                   
               
            
           
         
       
     
     For the (first and second) exemplary DG structures belong to the first category, the subpixels SP( 1 , 1 )˜SP( 1 , 4 ) can be classified into a subpixel group including subpixels SP( 1 , 1 ), SP( 2 , 1 ) and another subpixel group including subpixels SP( 3 , 1 ), SP( 4 ,  1 ). For the (third and fourth) exemplary DG structures belong to the second category, the subpixels SP( 1 , 1 )˜SP( 1 , 4 ) can be classified into a subpixel group including subpixels SP( 1 , 1 ), SP( 4 , 1 ) and another subpixel group including subpixels SP( 2 , 1 ), SP( 3 ,  1 ). 
     Depending on whether the subpixels have similar connections with the gate lines, the four exemplary DG structures can be grouped in another two categories, a third category that the subpixels SP( 1 ,  1 ), SP( 3 ,  1 ) are respectively electrically connected to the gate lines GL[ 1 ], GL[ 2 ], and a fourth category that the subpixels SP( 1 ,  1 ), SP( 3 ,  1 ) are respectively electrically connected to the gate lines GL[ 2 ], GL[ 1 ]. Please refer to Table 11 for such classification. 
     
       
         
           
               
             
               
                 TABLE 11 
               
               
                   
               
             
            
               
                 third category 
               
            
           
           
               
               
               
               
               
            
               
                 subpixels 
                 SP(1, 1) 
                 SP(2, 1) 
                 SP(3, 1) 
                 SP(4, 1) 
               
               
                   
               
               
                 second exemplary DG 
                 GL[1] 
                 GL[1] 
                 GL[2] 
                 GL[2] 
               
               
                 structure 
               
               
                 third exemplary DG 
                   
                 GL[2] 
                   
                 GL[1] 
               
               
                 structure 
               
               
                   
               
            
           
           
               
            
               
                 fourth category 
               
            
           
           
               
               
               
               
               
            
               
                 subpixels 
                 SP(1, 1) 
                 SP(2, 1) 
                 SP(3, 1) 
                 SP(4, 1) 
               
               
                   
               
               
                 first exemplary DG 
                 GL[2] 
                 GL[2] 
                 GL[1] 
                 GL[1] 
               
               
                 structure 
               
               
                 fourth exemplary DG 
                   
                 GL[1] 
                   
                 GL[2] 
               
               
                 structure 
               
               
                   
               
            
           
         
       
     
     For the (second and third) exemplary DG structures belong to the third category, the connections between the gate lines GL[ 1 ], GL[ 2 ] and the subpixels SP( 1 ,  1 ), SP( 3 ,  1 ) are the same, but the connections between the gate lines GL[ 1 ], GL[ 2 ] and the subpixels SP( 2 , 1 ), SP( 4 , 1 ) are interchanged. For the (first and second) exemplary DG structures belong to the fourth category, the connections between the gate lines GL[ 2 ], GL[ 1 ] and the subpixels SP( 1 ,  1 ), SP( 3 ,  1 ) are the same, but the connections between the gate lines GL[ 1 ], GL[ 2 ] and the subpixels SP( 2 , 1 ), SP( 4 , 1 ) are interchanged. 
     Based on the nature of the DG structure, half of the subpixels SP(m, n) (m=1˜M) are electrically connected to the gate line GL[k] (k=2*n−1), and the other half of the subpixels SP(m, n) (m=1˜M) are electrically connected to the gate line GL[k] (k=2*n). Furthermore, among the subpixels located at the same row and electrically connected to the same gate line, half of which are located at the odd-numbered columns (m=odd), and the other half of which are located at the even-numbered columns (m=even). 
     In all the above-mentioned embodiments, the patterns of the connections between the gate lines, the source lines, and the subpixels can be repeatedly adopted in the whole display panel. In practical application, it is also possible to implement one or more different layout in the same display panel.  FIGS. 11A and 11B  show an example of the display panel having a mixture of the four exemplary DG structures. 
       FIGS. 11A and 11B  are schematic diagrams showing a display panel including a mixture of the exemplary DG structures mentioned above.  FIG. 11A  is corresponding to the odd frame duration (Tframe_odd) and  FIG. 11B  is corresponding to the even frame duration (Tframe_even). 
     Please refer to  FIGS. 11A and 11B  together. In  FIGS. 11A and 11B , the connections between the subpixels and the gate lines GL[ 1 ]˜GL[ 8 ] are different in each row (line). The subpixels at the first row SP(m, n) (m=1˜M, and n=1) are arranged according to the first exemplary DG structure. The subpixels at the second row SP(m, n) (m=1˜M, and n=2), the subpixels at the third row SP(m, n) (m=1˜M, and n=3), and the subpixels at the fourth row SP(m, n) (m=1˜M, and n=4) are respectively arranged according to the second, the third, and the fourth exemplary DG structures. 
     On the other hand, the connections between the subpixels and the source lines S[j] (j=1˜J) are not changed with rows. That is, all the subpixels located at the first column and the third column SP(m, n) (m=1 or 3) are electrically connected to the source line S[ 1 ], and all the subpixels located at the second column and the fourth column SP(m, n) (m=2 or 4) are electrically connected to the source line S[ 2 ]. The supplement of the data voltages can be summarized in Table 12. 
     
       
         
           
               
               
             
               
                   
                 TABLE 12 
               
             
            
               
                   
                   
               
               
                   
                 SP(m, n) 
               
            
           
           
               
               
               
            
               
                   
                 FIG. 11A 
                 FIG. 11B 
               
               
                 frame 
                 odd frame duration 
                 even frame duration 
               
               
                 duration 
                 (Tframe_odd) 
                 (Tframe_even) 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 source line 
                 j = (m + 1)/2 
                 j = m/2 
                 j = (m + 1)/2 
                 j = m/2 
               
               
                 S[j] 
                 m = odd 
                 m = even 
                 m = odd 
                 m = even 
               
               
                 polarities of 
                 positive 
                 negative 
                 negative 
                 positive 
               
               
                 data voltages 
                 polarity (+) 
                 polarity (−) 
                 polarity (−) 
                 polarity (+) 
               
               
                   
               
            
           
         
       
     
     During the odd frame duration (Tframe_odd), the driving circuits  901 ˜ 906  transmit data voltages to source lines SL[ 1 ]˜S[ 6 ] in a sequential and parallel manner. As shown in  FIG. 11A , the subpixels located at the odd columns (SP(m, n), m=odd) receive the data voltages with positive polarity (+) through the odd-numbered source lines S[I] (j=(m+1)/2), and the subpixels located at the even columns (SP(m, n), m=even) receive the data voltages with negative polarity (−) through the even-numbered source lines S[j] (j=m/2). During the even frame duration (Tframe_even), the driving circuits  901 ˜ 906  transmit data voltages to source lines SL[ 1 ]˜S[ 6 ] in a pair and crossed manner. As shown  FIG. 11B , the subpixels located at the odd columns (SP(m, n), m=odd) receive the data voltages with negative polarity (−) through the odd source lines S[j] (j=(m+1)/2), and the subpixels located at the even columns (SP(m, n), m=even) receive the data voltages with negative polarity (−) through the even-numbered source lines S[j] (j=m/2). In practical application, the control mechanisms in the odd frame duration (Tframe_odd) and the even frame duration (Tframe_even) may be swapped. 
     In  FIGS. 11A and 11B , none of the touch sensing electrodes  91 ,  93 ,  95  crosses over any of the source lines S[ 1 ]˜S[ 6 ], nor the interconnections between the source lines S[ 1 ]˜S[ 6 ] and the subpixels SP(m, n) (m=1˜12 and n=1˜4), such layout plan can simplify the manufacture procedure of the DG display panel. 
     Comparing with the conventional DG structure, the subpixels receiving the data voltages having the same polarity are not at adjacent columns. That is, the subpixels at every adjacent column receive data voltages having opposite polarities. Therefore, the potential flicker, caused by the vertical pattern phenomenon when the display panel is shaken, becomes invisible. 
     According to the embodiments, the odd-numbered source lines S[j](j=odd) receive data voltages having positive polarity during the odd frame duration (Tframe_odd), and receives data voltages having negative polarity during the even frame duration (Tframe_even). As the polarities of the data voltages remain unchanged within the same frame duration, the power loss of caused by voltage shifting of the data voltages is limited to a specific range, and the power loss caused by data voltage switching of the driving circuits can be minimized. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.