Patent Publication Number: US-7221351-B2

Title: Display device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a display device, especially to a display device with a DA conversion function converting a digital image signal into an analog image signal. 
     2. Description of the Related Art 
     An electroluminescent (referred to as EL hereinafter) display device with an EL element has been gathering attention as a display device substituting a CRT or an LCD. The development effort for the EL display device with a thin film transistor (referred to as TFT hereinafter) as a switching element for driving the EL element has been made accordingly. 
       FIG. 7  is an equivalent circuit diagram of a pixel of an organic EL display panel. A gate signal line  50  supplying a gate signal Gn and a drain signal line  60  supplying a drain signal, a video signal Dm, cross each other. The video signal Dm is produced by sampling a video signal by using a sampling signal. 
     An organic EL element  120 , a TFT  100  for driving the organic El element  120 , and a TFT  110  for selecting the pixel are disposed near the crossing of the signal lines. 
     A positive source voltage PVdd is applied to the drain  100   d  of the driving TFT  100  of the organic EL element. And the source  100   s  is connected to an anode  121  of the organic EL element  120 . 
     The gate  110   g  of the TFT  110  for selecting pixel is provided with the gate signal Gn by being connected to the gate signal line  50 , and provided with the video signal Dm by being connected to the drain signal line  60 . The source  110   s  of the TFT  110  is connected to the gate  100   g  of the TFT  100 . The gate signal Gn is generated from a gate driver circuit (not shown in the figure). The video signal Dm is outputted from a drain driver circuit (not shown in the figure). 
     The organic EL element  120  includes the anode  121 , a cathode  122  and an emissive layer  123  inserted between the anode  121  and the cathode  122 . The cathode  122  is provided with a negative source voltage CV. 
     A storage capacitance element  130  is connected to the gate  100   g  of the TFT  100 . That is, one of the electrodes of the storage capacitance element  130  is connected to the gate  100   g,  and the other electrode is connected to a storage capacitance electrode  131 . The storage capacitance element  130  is disposed in order to keep the video signal of the pixel for one field period by keeping the charge corresponding to the video signal Dm. 
     The operation of the display device with the above configuration is as follows. The TFT  110  turns on when the gate signal Gn becomes a high level for one horizontal period. Then the video signal Dm is supplied from the drain signal line  60  to the gate  100   g  of the TFT  100  through the TFT  110 . The conductance of the TFT  100  changes according to the video signal supplied to the gate  100   g  and the corresponding driving electric current is supplied to the organic EL element  120  through the TFT  100 , which results in an illumination of the organic EL element  120 . 
     An analog image signal inputted to the drain signal line  60  is obtained by converting the inputted digital image signal into the analog image signal by a D/A converter. Conventional display devices with a D/A converter built inside the display panel usually have the D/A converter near the driver circuit disposed in the peripheral area of the pixels. 
     However, since the D/A converter is disposed near the driver circuit, the conventional display device has complicated circuit designs in the peripheral area of the pixels, leading to an enlarged framing area of the display panel to accommodate the D/A converter. 
     SUMMARY OF THE INVENTION 
     The invention provides a display device that includes a plurality of pixels. Each of the pixels includes an emissive element emitting a light in response to a digital signal and an electric current generating circuit generating a driving current corresponding to the digital signal and applying the driving current to the emission element. 
     The invention also provides an electroluminescent display device that includes a plurality of drain signal lines, a driving signal source and a plurality of pixels. Each of the drain signal lines is provided with a corresponding bit of a digital signal. Each of the pixels includes a plurality of pixel selection transistors collectively selecting a pixel in response to a scanning signal, an electroluminescent element and a plurality of driving transistors. Each of the pixel selection transistors connects the corresponding drain signal line and a gate of the corresponding driving transistor. Each of sources of the driving transistors receives a driving signal from the driving signal source. The driving capacity of each of the driving transistors is weighed based on the corresponding bit of the digital signal. The driving transistors collectively supply a driving current to the electroluminescent element. 
     The invention further provides an electroluminescent display device that includes a plurality of drain signal lines, a driving signal source and a plurality of pixels. Each of the drain signal lines is provided with a corresponding bit of a digital signal. Each of the pixels includes a plurality of pixel selection transistors collectively selecting a pixel in response to a scanning signal, an electroluminescent element, a plurality of driving transistors and a plurality of resistance elements. Each of the pixel selection transistors connects the corresponding drain signal line and a gate of the corresponding driving transistor. Each of sources of the driving transistors receives a driving signal from the driving signal source. The driving transistors collectively supply a driving current to the electroluminescent element. Each of the resistance elements connects the driving signal source and the corresponding driving transistor and has a resistance weighed based on the corresponding bit of the digital signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a display device of a first embodiment of this invention. 
         FIG. 2  is an equivalent circuit diagram of the electric current generating circuit and the organic EL element of the display device of  FIG. 1 . 
         FIG. 3  shows the resistance of the driving transistors shown in  FIG. 1  as a function of the bit level of a digital image signal. 
         FIG. 4  shows the driving current and the luminescence of the organic El element shown in  FIG. 1  as a function of a voltage. 
         FIG. 5  is a timing chart of an operation of the display device of the first embodiment. 
         FIG. 6  is a circuit diagram of a display device of a second embodiment of this invention. 
         FIG. 7  is an equivalent circuit diagram of a pixel of a conventional organic EL display device. 
     
    
    
     DESCRIPTION OF THE INVENTION 
     A first embodiment of this invention will be explained by referring to  FIGS. 1–5 .  FIG. 1  is a circuit diagram of a display device of the first embodiment of this invention. Only one pixel is shown in the figure for the sake of simplicity, but a plurality of pixels are disposed in a matrix configuration in an actual display device. 
     A gate signal line G 1  is disposed in one direction on an insulating substrate (not shown in the figure). A scanning signal is supplied to the gate signal line G 1  from a gate driver (not shown in the figure). Four drain signal lines D 0 –D 3  are disposed in the direction perpendicular to the gate signal line G 1 . A digital data driving circuit  1  outputs a 4-bit digital image signal corresponding to a sampling signal. 
     Each bit of the digital image signal (n 3 , n 2 , n 1 , n 0 ) is outputted to the drain signal lines D 0 –D 3  respectively. That is, the drain signal line D 0  receives the lowest bit n 0 , and the drain signal line D 3  receives the highest bit n 3 .The amplitude of the digital image signal can be expressed as (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ) when the voltage signal is V 1 . Here, n 0 –n 3  are binary data of 0 or 1. 
     A display with a multiple level gradation is possible by increasing the number of the bits of the digital image signal. On the other hand, a display with a low gradation can be made by decreasing the number of the bits of the digital image signal. 
     N-channel type pixel selection transistors GT 0 –GT 3  are connected to the drain signal lines D 0 –D 3  respectively. The gate signal line G 1  is connected to all gates of the pixel selection transistors GT 0 –GT 3 . The term “transistor” in this embodiment represents a TFT. 
     The digital image signal (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ) is supplied to the current generating circuit  2  through the pixel selection transistors GT 0 –GT 3 . The current generating circuit  2  is the circuit for generating the driving current corresponding to the digital image signal (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ). The driving current is supplied to an organic EL element  3 . The organic EL element includes an anode  4 , a cathode  5  and an emission  6 , which is made of organic material and is inserted between the anode  4  and the cathode  5 . The reference numeral  7  indicates a parasitic capacitance connected to the anode  4 . 
     The current generating circuit  2  has the following configurations: four N-channel type driving transistors DT 0 –DT 3 , the gates of which receive the corresponding bits of the digital image signal (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ), respectively, for switching; a driving signal source  8  for outputting a driving signal Vps that is applied to the driving transistors DT 0 –DT 3 ; and four coupling capacitors C 0 –C 3  connected between the driving signal source  8  and the driving transistors DT 0 –DT 3 . These four coupling capacitors C 0 –C 3  are disposed for ascending the gate voltage when the driving transistors DT 0 –DT 3  turn on, as described below. 
     Also, four N-channel type timing controlling transistors CT 0 –CT 3  are disposed for controlling the timing when to feed the driving current generated from the driving transistors DT 0 –DT 3  to the organic El element  3 . 
     The driving current generated from each of the driving transistors DT 0 –DT 3  is fed to the organic EL element  3  through the timing controlling transistors CT 0 –CT 3 . Therefore, the sum of the driving current generated from each of the driving transistors DT 0 –DT 3  is applied to the organic EL element  3 . 
     The current driving capacity of each of the driving transistors DT 0 –DT 3  is weighed according to each of the bits of the digital image signal (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ) as described below. 
     It is known that the current driving capacity of the driving transistors DT 0 –DT 3  is in proportion to GW/(GL·Tox), where GW is the width of the gate, GL is the length of the channel, and Tox is the thickness of the gate insulating film. Therefore, weightd can be added by adjusting the width of the gate. For example, the gate width GW 1  of the driving transistor DT 1  should be 2W, the gate width GW 2  of the driving transistor DT 2  should be 4W, and the gate width GW 3  of the driving transistor DT 3  should be 8W, assuming that the gate width GW 0  of the driving transistor DT 0  is W. 
       FIG. 2  shows the equivalent circuit diagram of the current generating circuit  2  and the organic EL element  3 , in which the total resistivity of the driving transistors DT 0 –DT 3  is R, and the resistivity of the organic EL element is R′. The voltage V generated between the anode  4  and the cathode  5  of the organic EL element  3  is expressed by the following equation obtained from the equivalent circuit in shown  FIG. 2 :
   V=Vps×R ′/( R+R ′)  (1) 
     The voltage of the cathode  5  is 0V. 
     On the other hand, the total resistivity R of the driving transistors DT 0 –DT 3  is approximately expressed as follows:
 
1 /R =( n 0/8 r+n 1/4 r+n 2/2 r+n 3 /r )  (2)
 
     Here, r denotes the on-resistance of the driving transistor DT 3 . Also, the on-resistance of the timing controlling transistors CT 0 –CT 3  is minimal compared to the on-resistance of the driving transistor DT 0 –DT 3 . 
     Therefore, the resistivity R corresponding to the bit data of the digital image signal (n 3 , n 2 , n 1 , n 0 ) should be infinite when the bit data is (0, 0, 0, 0), 8r when the bit data is (0, 0, 0, 1), 4r when the bit data is (0, 0, 1, 0,), and 8/3·r when the bit data is (0, 0, 1, 1), 2r when the digital data is (0, 1, 0, 0) . . . , and 8/15·r when the digital data is (1, 1, 1, 1). The off-resistance of the driving transistors DT 0 –DT 3  is approximately infinite. 
     The change of the resistivity is shown in  FIG. 3 . The x-axis shows the bit data (n 3 , n 2 , n 1 , n 0 ) and the y-axis shows the resistivity R in the figure. As the bit data (n 3 , n 2 , n 1 , n 0 ) of the digital image signal increases, the total resistivity R decreases, as seen from the figure. 
     The voltage V applied to the organic EL element  3  increases as the bit data (n 3 , n 2 , n 1 , n 0 ) increases according to the equation (1) described above. When the voltage V applied to the organic EL element  3  increases, the driving current I going through the organic EL element  3  from the driving transistors DT 0 –DT 3  also increases, leading to the increased luminescence L of the organic EL element  3 .  FIG. 4  shows the driving current I and the luminescence L of the organic EL element  3  as a function ot the voltage V. 
     Therefore, the luminescence L of the organic EL element  3  can be controlled in steps by feeding the driving current I to the organic EL element  3  according to the digital image signal in the display device with the above configuration. In other words, a D/A conversion function is built in the pixel for converting the digital image signal into the driving current I, making the gradation display possible. 
     The operation of the display device with the above configuration will be explained by referring to  FIG. 5 . The driving signal Vps outputted from the driving signal source  8  is 8V before the pixel is selected, and this voltage 8V is fed to the sources of the driving transistors DT 0 –DT 3 . The sources of the driving transistors DT 0 –DT 3  are set to be 0V when the driving signal Vps changes from 8V to 0V. Next, the voltage V (G 1 ) of the gate signal line G 1  becomes 4V+α, where α is the voltage larger than the threshold voltage of the pixel selection transistors GT 0 –GT 3 . 
     Then, the pixel selection transistors GT 0 –GT 3  turn on, and each bit of the digital image signal (n 3 , n 2 , n 1 , n 0 ) is read from the drain signal lines D 0 –D 3 . This makes the voltage of the gate of the driving transistor DT 0  n 0 ×4V, the voltage of the gate of the driving transistor DT 1  n 1 ×4V, the voltage of the gate of the driving transistor DT 2  n 2 ×4V, and the voltage of the gate of the driving transistor DT 3  n 3 ×4V. 
     Next, the voltage V (G 1 ) of the gate signal line G 1  becomes 0V. And this makes the pixel selection transistors GT 0 –GT 3  turn off. Then, the voltage of the driving signal Vsp changes from 0V to 8V. The voltage of the gate of the driving transistor DT 0 –DT 3  increases by 8V due to the coupling capacitors C 0 –C 3 . But, this is only the case when the parasitic capacitance that is formed, for example, between the gate and the drain of the driving transistors DT 0 –DT 3  is ignored. 
     The voltage of the driving transistor DT 0  becomes n 0 ×4V+8V. That is, the voltage of the gate is 8V when n0 is “0”. In this case, the driving transistor DT 0  turns off. On the other hand, when n 0  is “1”, the voltage of the gate becomes about 12V, enough to turn on the driving transistor DT 0 . The same applies to the other driving transistors DT 1 –DT 3 . Since the coupling capacitors C 0 –C 3  are utilized for ascending the voltage of the driving transistors DT 0 –DT 3  as described above, it is possible to suppress the amplitude of the digital image signal. 
     The driving transistors DT 0 –DT 3  switch according to the corresponding bits of the digital image signal (n 3 , n 2 , n 1 , n 0 ), determining the total resistivity of the driving transistors DT 0 –DT 3  based on the equation (2). 
     Then, the timing controlling transistors CT 0 –CT 3  turn on when the timing controlling signal CP becomes 8V+β. Here, β is a voltage larger than the threshold voltage of the timing controlling transistors CT 0 –CT 3 . The electric current I goes through the timing controlling transistors CT 0 –CT 3  from the driving transistors DT 0 –DT 3 , and is applied to the organic EL element  3  that emits light with the luminescence corresponding to the driving current I. 
     The timing controlling transistors CT 0 –CT 3  turn off when the timing controlling signal CP becomes 0V. The supply of the driving current I to the organic El element  3  stops, making the organic EL element  3  stop emitting light. 
     The timing controlling transistors CT 0 –CT 3  are formed in this embodiment for adjusting the timing for the driving current I through the organic EL element  3 . The timing controlling transistors are formed only when the above configuration is required. Each drain of the driving transistors DT 0 –DT 3  should be connected directly to the organic EL element  3 , when the timing controlling transistors CT 0 –CT 3  are not necessary. 
     Although the coupling capacitors C 0 –C 3  are formed for ascending the gate voltage when the driving transistors DT 0  –DT 3  turn on, it is also possible to omit the coupling capacitance. In this case, however, the amplitude of the digital image signal should be large. The number of the bits of the digital image signal (n 3 , n 2 , n 1 , n 0 ) is not limited to four. The smaller or larger number of the bits is also possible for the digital image signal. 
     The weight is added to the current driving capacity of the driving transistors DT 0 –DT 3  by adjusting the gate width of the driving transistors DT 0 –DT 3 . However, it is also possible to add the weight by adjusting the channel length GL or adjusting the film thickness Tox of the gate insulating film. 
     Next, a second embodiment of this invention will be explained by referring to  FIG. 6 , which is a circuit diagram of the second embodiment. Only one pixel is shown in the figure for the sake of simplicity. But a plurality of the pixels are disposed in a matrix configuration in an actual display device. The same components as in the first embodiment are give the same reference numerals in this embodiment. 
     A resistance element is connected in series to each of the driving transistors DT 0 –DT 3  in this embodiment. The resistivity of these resistance elements is weighed according to the corresponding bit of the digital image signal (n 3 . n 2 , n 1 , n 0 ). 
     The current generating circuit  10  in  FIG. 6  has the following configuration. Four N-channel type driving transistors DT 0 ′–DT 3 ′, to the gates of which the corresponding bits of the digital image signal (n 3 ·V 1 , n 2 ·V 1 , n 1 ·V 1 , n 0 ·V 1 ) are applied for switching. Here, the voltage V 1  is the signal amplitude (for example, 8V+α). 
     Also, a driving voltage source  11  outputs the direct current driving voltage VDC (for example 8V) and supplies it to the sources of the driving transistors DT 0 ′–DT 3 ′. Resistance elements, which have the resistivity of 8r0, 4r0, 2r0 and r0, respectively, are connected between the output of the driving voltage source  11  and the driving transistors DT 0 ′–DT 3 ′, respectively. 
     Also, storage capacitance elements CS 0 –CS 3  for holding the digital image signal are connected to the gates of the driving transistors DT 0 ′–DT 3 ′. 
     The equivalent circuit diagram of the current generating circuit  10  and the organic EL element  3  is the same as the circuit diagram shown in  FIG. 2  assuming that the total resistivity of the driving transistors DT 0 ′–DT 3 ′ is R and that the resistivity of the organic EL element  3  is R′. The voltage V generated between the anode  4  and the cathode  5  of the organic EL element  3  is expressed as the equation (3) obtained from the above equivalent circuit.
 
 V=VDC×R ′/( R+R ′)  (3)
 
     The voltage of the cathode  5  is 0V. 
     The total resistivity of the driving transistors DT 0 ′–DT 3 ′ can be expressed approximately as follows:
 
1 /R =( n 0/8 r 0+ n 1/4 r 0 +n 2/2 r 0 +n 3 /r 0)  (4)
 
     Here, the on-resistance of the driving transistors DT 0 ′–DT 3 ′ is small enough compared to the resistivity r. 
     Therefore, the resistivity R corresponding to the bit data of the digital image signal (n 3 , n 2 , n 1 , n 0 ) should be infinite when the bit data is (0, 0, 0, 0), 8r0 when the bit data is (0, 0, 0, 1), 4r0 when the bit data is (0, 0, 1, 0,), and 8/3·r0 when the bit data is (0, 0, 1, 1), 2r0 when the digital data is (0, 1, 0, 0) . . . , and 8/15·r0 when the digital data is (1, 1, 1, 1), as is the case with the first embodiment. The off-resistance of the driving transistors DT 0 ′–DT 3 ′ is approximately infinite. 
     The voltage V applied to the organic EL element  3  increases as the bit data (n 3 , n 2 , n 1 , n 0 ) increases as in the first embodiment. When the voltage V applied to the organic El element  3  increases, the driving current I going through the organic El element  3  from the driving transistors DT 0 ′–DT 3 ′ also increases, leading the increased luminescence L of the organic EL element  3 . Therefore, the luminescence L of the organic EL element  3  can be controlled in steps by feeding the driving current I to the organic EL element  3  according to the digital image signal in the display device of this embodiment. 
     The operation of the display device with the above configuration will be explained. The threshold voltage of the driving transistors DT 0 ′–DT 3 ′ and the pixel selection transistors GT 0 –GT 3  is ignored to make the explanation simple. 
     The voltage V (G 1 ) of the gate signal line G 1  becomes 8V. Then, the pixel selection transistors GT 0 –GT 3  turn on, and each bit of the digital image signal (n 3 , n 2 , n 1 , n 0 ) is read into from the drain signal lines D 0 –D 3 . This makes the voltage of the gate of the driving transistor DT 0 ′ n 0 ×8V, the voltage of the gate of the driving transistor DT 1 ′ n 1 ×8V, the voltage of the gate of the driving transistor DT 2 ′ n 2 ×8V, and the voltage of the gate of the driving transistor DT 3  n 3 ×8V. 
     The voltage of the gate is 0V when n 0  is “0” as to the driving transistor DT 0 ′, turning the driving transistor DT 0 ′ off. On the other hand, when n 0  is “1”, the voltage of the gate becomes 8V, turning the driving transistor DT 0 ′ on. The same applies to the other driving transistors DT 1 ′–DT 3 ′. 
     The driving transistors DT 0 ′–DT 3 ′ switch according to the corresponding bits of the digital image signal (n 3 , n 2 , n 1 , n 0 ), determining the total resistivity of the driving transistors DT 0 –DT 3  based on the equation (2). The driving current I is applied to the organic EL element  3  through the driving transistors DT 0 ′–DT 3 ′, and the organic EL element  3  emits light with the luminescence corresponding to the driving current I. 
     The timing controlling transistors CT 0 –CT 3  for adjusting the timing of the driving current I through the organic EL element  3  are omitted in this embodiment. However, the timing controlling transistors can be formed as in the first embodiment. The number of the bits of the digital image signal (n 3 , n 2 , n 1 , n 0 ) is not limited to four. The smaller or larger number of bits is also possible for the digital image signal. 
     The embodiments ate applied to the display device with the organic EL element  3 , but are not limited to the EL devices. The features of these embodiments are applicable to any display device with a current driven emission element such as LED.