Patent Publication Number: US-10319309-B2

Title: Display device that corrects for variations between reference voltages and method for driving the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the priority benefit of Republic of Korea Patent Application No. 10-2016-0139176 filed on Oct. 25, 2016, which is hereby incorporated herein by reference in its entirety. 
     BACKGROUND 
     Field of Technology 
     The present disclosure relates to a display device and a method for driving the same. 
     Description of the Related Art 
     The market for displays which act as an intermediary between users and information is growing with the development of information technology. Thus, display devices such as organic light-emitting displays (OLEDs), liquid crystal displays (LCDs), and plasma display panels (PDPs) are increasingly used. 
     An organic light-emitting display comprises a display panel comprising a plurality of subpixels and a drive part that drives the display panel. The drive part comprises a scan driver that supplies scan signals (or gate signals) to the display panel and a data driver that supplies data signals to the display panel. When a scan signal, a data signal, etc. are supplied to the subpixels on the organic light-emitting display, selected subpixels emit light, thereby displaying an image. 
     On the display panel, the subpixels are implemented based on devices, such as thin-film transistors that are formed on a substrate by deposition. Due to differences in intrinsic characteristics such as threshold voltage, devices such as thin-film transistors require compensation even in an initial stage in order to exhibit uniform brightness characteristics, and they degrade when driven for a long time, like a threshold voltage shift or a decrease in lifetime. When device degradation occurs, the brightness characteristics of the display panel which displays images based on these devices change too. 
     In the conventionally proposed solution, data voltages compensated through parameters are applied to each pixel, in order to compensate for variations in device characteristics, and a common reference voltage of a particular level is applied to adjust brightness level. Implementing a multi-sectional, large-screen and high-resolution organic light-emitting display by the above compensation method may cause variations in brightness between split screens due to variations in reference voltage. Thus, there is a need for research on output variations between reference voltage generators that generate reference voltages. 
     SUMMARY 
     The present disclosure provides a display device comprising: a display panel displaying an image; M reference voltage generators (M is an integer of 2 or greater) that respectively supply reference voltages to N display areas (N is an integer of 2 or greater) defined on the display panel; and a voltage variation corrector that corrects for voltage variations between the M reference voltages (M is an integer of 2 or greater). 
     In another aspect, the present disclosure provides a method for driving a display device, the display device comprising M reference voltage generators (M is an integer of 2 or greater) that respectively supply reference voltages to N display areas (N is an integer of 2 or greater) defined on a display panel and a voltage variation corrector that corrects for voltage variations between the M reference voltages (M is an integer of 2 or greater), the method comprising: obtaining the reference voltages output from the M reference voltage generators (M is an integer of 2 or greater); extracting correction parameters based on the obtained reference voltages; generating correction values for correcting for the voltage variations between the reference voltages based on the extracted correction parameters; and supplying the correction values to the reference voltage generators. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention. In the drawings: 
         FIG. 1  is a schematic block diagram of an organic light-emitting display according to an exemplary embodiment of the present disclosure; 
         FIG. 2  is a schematic circuit diagram of a subpixel according to an exemplary embodiment of the present disclosure; 
         FIG. 3  is a detailed circuit diagram of a subpixel according to an exemplary embodiment of the present disclosure; 
         FIG. 4  is an illustration of a cross-section of a display panel according to an exemplary embodiment of the present disclosure; 
         FIG. 5  is a schematic block diagram of an organic light-emitting display according to a test example according to an exemplary embodiment of the present disclosure; 
         FIGS. 6 to 8  are views for explaining a method for correcting voltage variations according to the test example; 
         FIG. 9  is a view showing problems with the test example; 
         FIG. 10  is a schematic block diagram of an organic light-emitting display according to a first exemplary embodiment of the present disclosure; 
         FIG. 11  is a view explaining a method for correcting voltage variations according to the first exemplary embodiment of the present disclosure; 
         FIG. 12  is a view showing improvements made by the first exemplary embodiment of the present disclosure; 
         FIG. 13  is a block diagram showing a modification of the first exemplary embodiment of the present disclosure; 
         FIG. 14  is a schematic block diagram of an organic light-emitting display according to a second exemplary embodiment of the present disclosure; and 
         FIG. 15  is a view showing improvements made by the second exemplary embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to embodiments of the disclosure, examples of which are illustrated in the accompanying drawings. 
     Hereinafter, a concrete example according to an exemplary embodiment of the present disclosure will be described with reference to the accompanying drawings. 
     A display device according to the present disclosure is implemented as a television, a video player, a personal computer (PC), a home theater, a smartphone, etc. An organic light-emitting display will be given as an example of the display device according to the present disclosure. However, this is merely for illustration, and other types of display devices may be applicable as long as they can perform compensations using reference voltages. 
     Moreover, a thin-film transistor to be described below may be referred to as a source electrode and a drain electrode or as a drain electrode and a source electrode depending on the type, but without a gate electrode. Thus, the thin-film transistor will be described as a first electrode and a second electrode so that it is not limited by such terms. 
       FIG. 1  is a schematic block diagram of an organic light-emitting display according to an exemplary embodiment of the present disclosure.  FIG. 2  is a schematic circuit diagram of a subpixel.  FIG. 3  is a detailed circuit diagram of a subpixel according to an exemplary embodiment of the present invention.  FIG. 4  is an illustration of a cross-section of a display panel according to an exemplary embodiment of the present disclosure. 
     As illustrated in  FIG. 1 , an organic light-emitting display according to an exemplary embodiment of the present disclosure comprises an image processor  110 , a timing controller  120 , a data driver  130 , a scan driver  140 , and a display panel  150 . 
     The image processor  110  outputs a data enable signal DE, etc., along with an externally supplied data signal DATA. In addition to the data enable signal DE, the image processor  110  may output one or more among a vertical synchronization signal, a horizontal synchronization signal, and a clock signal. But, these signals will be omitted in the drawings for convenience of explanation. 
     The timing controller  120  receives the data signal DATA from the image processor  110 , along with the data enable signal DE or driving signals including the vertical synchronization signal, horizontal synchronization signal, and clock signal. The timing controller  120  outputs a gate timing control signal GDC for controlling the operation timing of the scan driver  140  and a data timing control signal DDC for controlling the operation timing of the data driver  130 , based on the driving signals. 
     The data driver  130  samples and latches the data signal DATA supplied from the timing controller  120  responsive to the data timing control signal DDC being supplied from the timing controller  120 . The data driver  130  converts digital data signal DATA to an analog data signal and outputs the analog data signal, in conjunction with an internal or external programmable gamma part. The data driver  130  outputs data signals DATA through data lines DL 1  to DLn. The data driver  130  may be provided in the form of an IC (integrated circuit). 
     The scan driver  140  outputs a scan signal responsive to the gate timing control signal GDC being supplied from the timing controller  120 . The scan driver  140  outputs scan signals through scan lines GL 1  to GLm. The scan driver  140  is provided in the form of an IC (integrated circuit), or provided on the display panel  150  in the form of a gate-in-panel. 
     The display panel  150  displays an image in response to the data signals DATA and scan signals respectively supplied from the data driver  130  and scan driver  140 . The display panel  150  comprises subpixels SP that display an image. 
     The subpixels are formed by a top-emission scheme, bottom-emission scheme, or dual-emission scheme depending on the structure. The subpixels SP may comprise red subpixels, green subpixels, and blue subpixels, or may comprise white subpixels, red subpixels, green subpixels, and blue subpixels. The subpixels SP may have one or more different light-emission areas depending on the light-emission characteristics. The subpixels SP may produce white, red, green, and blue based on a white organic-emitting layer and red, green, and blue color filters, but are not limited thereto. 
     As illustrated in  FIG. 2 , one subpixel comprises a switching transistor SW, a driving transistor DR, a capacitor Cst, a compensation circuit CC, and an organic light-emitting diode OLED. 
     The switching transistor SW acts as a switch in response to a scan signal supplied through the first scan line GL 1  to store a data signal supplied through the first data line DL 1  as a data voltage in the capacitor Cst. The driving transistor DR causes a drive current to flow between a first power supply line EVDD and a second power supply line EVSS by the data voltage stored in the capacitor Cst. The organic light-emitting diode OLED emits light by the drive current formed by the driving transistor DR. 
     The compensation circuit CC is a circuit that is added within the subpixel to compensate for a threshold voltage, etc. of the driving transistor DR. The compensation circuit CC comprises of one or more transistors. The configuration of the compensation circuit CC varies widely depending on the method of compensation, and an example thereof will be described below. 
     As illustrated in  FIG. 3 , the compensation circuit CC comprises a sensing transistor ST and a sensing line VREF. The sensing transistor ST is connected between a source line of the driving transistor DR and an anode (hereinafter, “sensing node”) of the organic light-emitting diode OLED. The sensing transistor ST may operate to supply a reference voltage (or sensing voltage) delivered through the sensing line VREF to the sensing node or sense the voltage or current in the sensing node. 
     The switching transistor SW has a first electrode connected to a first data line DL 1  and a second electrode connected to a gate electrode of the driving transistor DR. The driving transistor DR has a first electrode connected to the first power supply line EVDD and a second electrode connected to the anode of the organic light-emitting diode OLED. The capacitor Cst has a first electrode connected to the gate electrode of the driving transistor DR and a second electrode connected to the anode of the organic light-emitting diode OLED. The organic light-emitting diode OLED has the anode connected to the second electrode of the driving transistor DR and a cathode connected to the second power supply line EVSS. The sensing transistor ST has a first electrode connected to the sensing line VREF and a second electrode connected to the anode of the organic light-emitting diode OLED that is a sensing node. 
     The operating time of the sensing transistor ST may be similar/equal to that of the switching transistor SW or different from it, depending on the compensation algorithm (or the compensation circuit configuration). The switching transistor SW may have a gate electrode connected to a scan line GL 1   a , and the sensing transistor ST may have a gate electrode connected to a scan line GL 1   b . In another example, the scan line GL 1   a  connected to the gate electrode of the switching transistor SW and the scan line GL 1   b  connected to the gate electrode of the sensing transistor ST may be commonly connected so as to be shared. 
     The sensing line VREF may be connected to the data driver. In this case, the data driver may sense the sensing node of the subpixel in real time, during a non-display period of an image or for an N frame period (N is an integer of 1 or greater), and may generate a sensing result. The switching transistor SW and the sensing transistor ST may be turned on simultaneously. In this case, a sensing operation through the sensing line VREF and a data output operation of outputting a data signal may be done separately based on a time-division system of the data driver. 
     A light blocking layer LS is provided to block ambient light. The light blocking layer LS may cause the problem of parasitic voltage charging when formed from a metallic material. Due to this, the light blocking layer LS may be disposed only below a channel region of the driving transistor DR, or may be disposed below channel regions of the switching transistor SW and sensing transistor ST. Meanwhile, the light blocking layer LS may be used simply for the purpose of blocking ambient light, or the light blocking layer LS may be used as an electrode that facilitates a connection with other electrodes or lines and forms a capacitor, etc. 
     Targets to be compensated for according to the sensing result may include a digital data signal, an analog data signal, or a gamma voltage. The compensation circuit, which generates a compensated signal (or compensated voltage) based on the sensing result, may be implemented as an internal circuit of the data driver, as an internal circuit of the timing controller, or as a separate circuit. 
       FIG. 3  illustrates, by way of example, a subpixel having a 3-transistors/1-capacitor structure comprising the switching transistor SW, the driving transistor DR, the capacitor Cst, the organic light-emitting diode OLED, and the sensing transistor ST. However, when a compensation circuit CC is added, the subpixel may be configured to have a 3T2C, 4T2C, 5T1C, or 6T2C structure. 
     As illustrated in the  FIG. 4 , subpixels P are formed in a display area AA of a first substrate  150   a  of the display panel  150 , based on the circuit explained with reference to  FIG. 3 . The subpixels formed in the display area AA are sealed by a protective film (or a protective substrate)  150   b  of the display panel  150 . Area NA refers to a non-display area. 
     The subpixels P may be horizontally or vertically arranged in the display area AA, for example, in order of red (R), white (W), blue (B), and green (G) colors. The red, white, blue, and green subpixels R, W, B, and G may form a single pixel P. However, the sequence of the subpixels P may be altered in various ways depending on emitting materials, light-emission areas, the compensation circuit configuration (or structure), and so on. Also, the red, blue, and green subpixels R, B, and G may form a single pixel P. 
     On the above-described display panel, the subpixels are implemented based on devices, such as thin-film transistors that are formed on a substrate by deposition. Devices such as thin-film transistors degrade when driven for a long time, like a threshold voltage shift or a decrease in lifetime. When device degradation occurs, the brightness characteristics of the display panel which displays images based on these devices change too. 
     In the organic light-emitting display according to the present disclosure, data voltages compensated through parameters are applied to each pixel, in order to compensate for variations in device characteristics, and a common reference voltage of a particular level is applied to adjust brightness level. 
     A large-screen and high-resolution organic light-emitting display requires a plurality of reference voltage generators that generate and output reference voltage when the display panel is driven in multiple sections. The reference voltage generators may be implemented as gamma voltage generators or power supply parts that may change voltage in a programmable fashion. 
     However, when implementing such a large-screen and high-resolution organic light-emitting display by the above compensation method, output variations between the reference voltage generators should be taken into consideration, and thus, there is a need for research on this. 
     Hereinafter, descriptions will be made with respect to the problem of output variations between the reference voltage generators and a test example and exemplary embodiments of the present invention for solving this problem. 
     Test Example 
       FIG. 5  is a schematic block diagram of an organic light-emitting display according to a test example.  FIGS. 6 to 8  are views explaining a method for correcting voltage variations according to the test example.  FIG. 9  is a view showing problems with the test example. 
     Referring to  FIG. 5 , the organic light-emitting display according to the test example comprises a high-resolution display panel  150 . The high-resolution display panel  150  has a first display area AA 1 , a second display area AA 2 , a third display area AA 3 , and a fourth display area AA 4 . 
     A first timing controller  120 A and a first reference voltage generator VPWR 1  are located on a first control board C-PCB 1 . The first timing controller  120 A outputs a first data signal for the first display area AA 1  of the display panel  150 . The first reference voltage generator VPWR 1  outputs a first reference voltage for the first display area AA 1 . 
     A second timing controller  120 B and a second reference voltage generator VPWR 2  are located on a second control board C-PCB 2 . The second timing controller  120 B outputs a second data signal for the second display area AA 2  of the display panel  150 . The second reference voltage generator VPWR 2  outputs a second reference voltage for the second display area AA 2 . 
     A third timing controller  120 C and a third reference voltage generator VPWR 3  are located on a third control board C-PCB 3 . The third timing controller  120 C outputs a third data signal for the third display area AA 3  of the display panel  150 . The third reference voltage generator VPWR 3  outputs a third reference voltage for the third display area AA 3 . 
     A fourth timing controller  120 D and a fourth reference voltage generator VPWR 4  are located on a fourth control board C-PCB 4 . The fourth timing controller  120 D outputs a fourth data signal for the fourth display area AA 4  of the display panel  150 . The fourth reference voltage generator VPWR 4  outputs a fourth reference voltage for the fourth display area AA 4 . 
     First to fourth data driver groups  130 A to  130 D supply the first to fourth data signals and the first to fourth reference voltages to the first to fourth display areas AA 1  to AA 4  of the display panel  150 , based on the first to fourth data signals and the first to fourth reference voltages. The first to fourth data signals and the first to fourth reference voltages are supplied to display period on the display panel  150 . The first to fourth data signals are supplied via data lines, and the first to fourth reference voltages are supplied via sensing lines. 
     As above, the high-resolution organic light-emitting display drives the display panel  150  in at least four sections or N sections (N is an integer of 2 or greater) because it is difficult to control frame data signals for all display areas on the display panel  150  and supply them to a single timing controller. 
     There are output variations between AD converters ADC of the first to fourth data driver groups  130 A,  130 B,  130 C, and  130 D. The AD converters ADC of the first to fourth data driver groups  130 A to  130 D serve to charge the sensing line VREF with a reference voltage and sense it. Thus, variations between the AD converters ADC need to be corrected for. A method of correcting for variations between the AD converters ADC will be described below. 
     As illustrated in  FIG. 6 , during a sensing period, the sensing line VREF stores a reference voltage output from a reference voltage generator. The switching transistor SW and the sensing transistor ST are instantly turned off. The reference voltage stored in the sensing line VREF is sensed by the AD converter ADC provided internally in the data driver  130  that drives the illustrated subpixel. The sensed analog reference voltage is converted into digital sensing data Sd (or digital reference voltage) by the AD converter ADC. 
     For reference, the period in which a reference voltage is stored in the sensing line VREF and sensed precedes the period in which a characteristic of the driving transistor is extracted. This is because the reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4  need to be uniform and constant to extract a characteristic of the driving transistor and compensate for it. 
     As illustrated in  FIGS. 5 to 8 , the first to fourth reference voltage generators VPWR 1  to VPWR 4  are driven to apply reference voltages VREF 1  to VREF 4  respectively to the first to fourth display areas AA 1  to AA 4  of the display panel  150  (S 120 ). Next, the sensing data Sd output from the AD converters ADC of the first to fourth data driver groups  130 A to  130 D is extracted (S 130 ). 
     Afterwards, the step S 120  of applying reference voltage and the step S 130  of extracting sensing data Sd are repeated while gradually changing the reference voltage. These steps are repeated because sensing data Sd extracted through a single test alone is not enough to take into consideration variations in gain/offset parameters of the AD converters ADC included in the first to fourth data driver groups  130 A to  130 D and correct for them. 
     Next, the relationship between ideal sensing data  Sd  and the sensing data Sd output from the AD converters ADC is extracted (S 140 ). Based on this, optimum compensation parameters for minimizing output variations between the AD converters ADC included in the first to fourth data driver groups  130 A to  130 D are extracted and stored (S 150 ). The compensation parameters may be stored in internal registers of the first to fourth data driver groups  130 A to  130 D. 
     Using the method of the test example, the output variations between the AD converters ADC included in the first to fourth data driver groups  130 A to  130 D were eliminated to some extent. 
     However, the test example showed that there were still variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  placed in different sections, and this caused brightness variations on the display panel  150 , as in the first to fourth display areas AA 1 ≠AA 2 ≠AA 3 ≠AA 4  of  FIG. 9 . 
     First Exemplary Embodiment 
       FIG. 10  is a schematic block diagram of an organic light-emitting display according to a first exemplary embodiment of the present disclosure.  FIG. 11  is a view for explaining a method for correcting for voltage variations according to the first exemplary embodiment of the present invention.  FIG. 12  is a view showing improvements made by the first exemplary embodiment of the present disclosure.  FIG. 13  is a block diagram showing a modification of the first exemplary embodiment of the present disclosure. 
     As illustrated in  FIGS. 5 and 10 , an organic light-emitting display according to the first exemplary embodiment comprises a high-resolution display panel  150 . The high-resolution display panel  150  has a first display area AA 1 , a second display area AA 2 , a third display area AA 3 , and a fourth display area AA 4 . 
     A first timing controller  120 A and a first reference voltage generator VPWR 1  are located on a first control board C-PCB 1 . The first timing controller  120 A outputs a first data signal for the first display area AA 1  of the display panel  150 . The first reference voltage generator VPWR 1  outputs a first reference voltage for the first display area AA 1 . 
     A second timing controller  120 B and a second reference voltage generator VPWR 2  are located on a second control board C-PCB 2 . The second timing controller  120 B outputs a second data signal for the second display area AA 2  of the display panel  150 . The second reference voltage generator VPWR 2  outputs a second reference voltage for the second display area AA 2 . 
     A third timing controller  120 C and a third reference voltage generator VPWR 3  are located on a third control board C-PCB 3 . The third timing controller  120 C outputs a third data signal for the third display area AA 3  of the display panel  150 . The third reference voltage generator VPWR 3  outputs a third reference voltage for the third display area AA 3 . 
     A fourth timing controller  120 D and a fourth reference voltage generator VPWR 4  are located on a fourth control board C-PCB 4 . The fourth timing controller  120 D outputs a fourth data signal for the fourth display area AA 4  of the display panel  150 . The fourth reference voltage generator VPWR 4  outputs a fourth reference voltage for the fourth display area AA 4 . 
     First to fourth data driver groups  130 A to  130 D supply the first to fourth data signals and the first to fourth reference voltages to the first to fourth display areas AA 1  to AA 4  of the display panel  150 , based on the first to fourth data signals and the first to fourth reference voltages. The first to fourth data signals are supplied to display period on the display panel  150 , whereas the first to fourth reference voltages are supplied to sensing period on the display panel  150 . 
     The first to fourth reference voltage generators VPWR 1  to VPWR 4  correspond to the number of sections on the display panel  150 . Accordingly, the first to fourth reference voltage generators VPWR 1  to VPWR 4  may consist of M reference voltage generators (M is an integer of 2 or greater). From the above description, it can be seen that M reference voltage generators and M timing controllers are individually placed on control boards. 
     A voltage variation corrector  160  obtains reference voltages from the first to fourth reference voltage generators VPWR 1  to VPWR 4 . The voltage variation corrector  160  may obtain reference voltages from the first to fourth reference voltage generators VPWR 1  to VPWR 4  in a time-division manner, or may obtain reference voltages from a single reference voltage generator over several phases. 
     The voltage variation corrector  160  may extract correction parameters based on the obtained reference voltages, and minimize output voltage variations between the reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4  based on the extracted corrected parameters. 
     The voltage variation corrector  160  comprises a multiplexer MUX and a correction circuit ADIC. The multiplexer MUX performs a selection operation for obtaining the reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4  in a time-division manner, under control of external circuits such as the correction circuit ADIC or the timing controllers. 
     Although the multiplexer MUX may be placed on the first control board C-PCB 1  by way of example, it also may be placed on one of the second to fourth control boards C-PCB 2  to C-PCB 4 . The multiplexer MUX may obtain the reference voltages output from the second to fourth reference voltage generators VPWR 2  to VPWR 4  placed on the second to fourth control boards C-PCB 2  to C-PCB 4  by a cable system, electric wiring system, or communication system. That is, the multiplexer MUX and the reference voltage generators are connected by a cable system, electric wiring system, or communication system. 
     The correction circuit ADIC extracts correction parameters based on the reference voltages obtained by the multiplexer MUX, and generates correction values ADV 1  to ADV 4  for minimizing voltage variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  based on the extracted correction parameters. The correction circuit ADIC may be placed on the first control board C-PCB or another substrate, as in the case of the multiplexer MUX. 
     As illustrated in  FIGS. 10 and 11 , the correction circuit ADIC comprises a selector  161 , a converter  162 , a parameter extractor  163 , a correction value generator  165 , and an output part  167 . 
     The selector  161  outputs selection signals VPWR 1  Select to VPWR 4  select for selecting one of the first to fourth reference voltage generators VPWR 1  to VPWR 4 . The selection signals VPWR 1  Select to VPWR 4  Select control the selection operation of the multiplexer MUX. 
     The converter  162  senses the first to fourth reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4 . The converter  162  converts sensed analog voltages to digital data. 
     When the first selection signal VPWR 1  Select is output from the selector  161 , the multiplexer MUX selects the first reference voltage generator VPWR 1 . The first reference voltage output from the first reference voltage generator VPWR 1  is obtained as first data Vd 1  by a sensing operation of the converter  162 . On the other hand, when the second selection signal VPWR 2  Select is output, the multiplexer MUX selects the second reference voltage generator VPWR 2 . The second reference voltage output from the second reference voltage generator VPWR 2  is obtained as second data Vd 2  by a sensing operation of the converter  162 . 
     In this manner, the selector  161  outputs third and fourth selection signals VPWR 3  Select and VPWR 4  Select for obtaining third data Vd 3  corresponding to the third reference voltage output from the third reference voltage generator VPWR 3  and fourth data Vd 4  corresponding to the fourth reference voltage output from the fourth reference voltage generator VPWR 4 . In this case, the selector  161  may sequentially or non-sequentially output the first to fourth selection signals VPWR 1  Select to VPWR 4  Select. 
     The parameter extractor  163  extracts correction parameters para 1  to para 4  for minimizing output voltage variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  based on the first to fourth data Vd 1  to Vd 4  obtained by the sensing operations of the converter  162 . 
     The correction value generator  165  generates correction values ADV 1  to ADV 4  to minimize output voltage variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  based on the extracted correction parameters para 1  to para 4 . 
     The output part  167  outputs the correction values ADV 1  to ADV 4  generated by the correction value generator  165  and supplies them to the first to fourth reference voltage generators VPWR 1  to VPWR 4 . The output part  167  may output an arbitrary voltage value as well as the correction values ADV 1  to ADV 4 , so as to use it to compensate for initial voltage variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4 . 
     Based on the multiplexer MUX and the correction circuit ADIC, the voltage variation corrector  160  may supply an arbitrary voltage value to the first to fourth reference voltage generators VPWR 1  to VPWR 4  and perform sensing on them regularly and continuously to minimize voltage output variations between them. That is, a tracking operation may be performed for continuous sensing and correction, and this may prevent voltage variations that may occur later with time. 
     The operation of the voltage variation corrector  160  allows the first to fourth reference voltage generators VPWR 1  to VPWR 4  to output the same reference voltage or reference voltages whose variations converge to a certain value (which may be described as a reference voltage of an intermediate value or reference value). 
     As a result, in the first exemplary embodiment, the variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  placed in different sections may be eliminated. Thus, there are almost no brightness variations on the display panel  150 , as in the first to fourth display areas AA 1 ≈AA 2 ≈AA 3 ≈AA 4  of  FIG. 12 . 
     As illustrated in  FIG. 13 , the voltage variation corrector  160  may use the AD converter included in a particular data driver  130 A as the converter  162  of the correction circuit ADIC. In this case, the AD converter included in the particular data driver  130 A performs sensing and correction operations based on the joint operation between the timing controller and the correction circuit ADIC. Moreover, some of the components included in the voltage variation corrector  160 —for example, the selector, parameter generator, correction value generator, and output part—that may be implemented based on an algorithm may be included within the timing controller. 
     Second Exemplary Embodiment 
       FIG. 14  is a schematic block diagram of an organic light-emitting display according to a second exemplary embodiment of the present disclosure.  FIG. 15  is a view showing improvements made by the second exemplary embodiment of the present invention. 
     As illustrated in  FIGS. 5 and 14 , an organic light-emitting display according to the second exemplary embodiment comprises a high-resolution display panel  150 . The high-resolution display panel  150  has a first display area AA 1 , a second display area AA 2 , a third display area AA 3 , and a fourth display area AA 4 . 
     A first timing controller  120 A and a first reference voltage generator VPWR 1  are located on a first control board C-PCB 1 . The first timing controller  120 A outputs a first data signal for the first display area AA 1  of the display panel  150 . The first reference voltage generator VPWR 1  outputs a first reference voltage for the first display area AA 1 . 
     A second timing controller  120 B and a second reference voltage generator VPWR 2  are located on a second control board C-PCB 2 . The second timing controller  120 B outputs a second data signal for the second display area AA 2  of the display panel  150 . The second reference voltage generator VPWR 2  outputs a second reference voltage for the second display area AA 2 . 
     A third timing controller  120 C and a third reference voltage generator VPWR 3  are located on a third control board C-PCB 3 . The third timing controller  120 C outputs a third data signal for the third display area AA 3  of the display panel  150 . The third reference voltage generator VPWR 3  outputs a third reference voltage for the third display area AA 3 . 
     A fourth timing controller  120 D and a fourth reference voltage generator VPWR 4  are located on a fourth control board C-PCB 4 . The fourth timing controller  120 D outputs a fourth data signal for the fourth display area AA 4  of the display panel  150 . The fourth reference voltage generator VPWR 4  outputs a fourth reference voltage for the fourth display area AA 4 . 
     First to fourth data driver groups  130 A to  130 D supply the first to fourth data signals and the first to fourth reference voltages to the first to fourth display areas AA 1  to AA 4  of the display panel  150 , based on the first to fourth data signals and the first to fourth reference voltages. The first to fourth data signals and the first to fourth reference voltages are supplied to display period on the display panel  150 . 
     A voltage variation corrector  160  obtains reference voltages from the first to fourth reference voltage generators VPWR 1  to VPWR 4 . The voltage variation corrector  160  may obtain reference voltages from the first to fourth reference voltage generators VPWR 1  to VPWR 4  in a time-division manner, or may obtain reference voltages from a single reference voltage generator over several phases. 
     The voltage variation corrector  160  may extract correction parameters based on the obtained reference voltages, and minimize voltage variations between the reference voltage generators VPWR 1  to VPWR 4  based on the extracted corrected parameters. 
     The voltage variation corrector  160  comprises a multiplexer MUX and a correction circuit ADIC. The multiplexer MUX performs a selection operation for obtaining the reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4  in a time-division manner, under control of external circuits such as the correction circuit ADIC or the timing controllers. 
     The correction circuit ADIC extracts correction parameters based on the reference voltages obtained by the multiplexer MUX, and generates correction values ADV 1  to ADV 4  for minimizing voltage variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  based on the extracted correction parameters. 
     The multiplexer MUX and the correction circuit ADIC are placed on a connection board BRB. The multiplexer MUX may obtain the reference voltages output from the first to fourth reference voltage generators VPWR 1  to VPWR 4  placed on the first to fourth control boards C-PCB 1  to C-PCB 4  by a cable system, electric wiring system, or communication system. The correction circuit ADIC may forward or transmit the correction values ADV 1  to ADV 4  to the first to fourth reference voltage generators VPWR 1  to VPWR 4  by a cable system, electric wiring system, or communication system. The multiplexer MUX and the correction circuit ADIC may temporally divide the time and operation for generating the reference voltages and the correction values. 
     As in  FIG. 11  of the first exemplary embodiment, the correction circuit ADIC comprises a selector  161 , a converter  162 , a parameter extractor  163 , a correction value generator  165 , and an output part  167 . Their functions and operations are identical to those in the first exemplary embodiment, so they will be explained by reference to  FIG. 11 . 
     In the second exemplary embodiment as well, variations between the first to fourth reference voltage generators VPWR 1  to VPWR 4  placed in different sections may be eliminated. Thus, there are almost no brightness variations on the display panel  150 , as in the first to fourth display areas AA 1 ≈AA 2 ≈AA 3 ≈AA 4  of  FIG. 15 . 
     As stated above, the present invention has the advantage of improving display quality by correcting for variations between reference voltages which cause brightness variations between sections when the display panel is driven in multiple sections. The present invention has another advantage of comparing output voltages from all reference voltage generators and performing a continuous tracking operation so that these reference voltage generators output the same reference voltage or their voltage variations converge to a certain value.