Patent Publication Number: US-2022216333-A1

Title: Hemt transistor with adjusted gate-source distance, and manufacturing method thereof

Description:
BACKGROUND 
     Technical Field 
     The present disclosure relates to a high-electron-mobility transistor (HEMT) (and to the manufacturing method thereof. In particular, the present disclosure regards a HEMT transistor with adjusted gate-source distance. 
     Description of the Related Art 
     Transistors are known, which are based upon the formation of layers of two-dimensional electron gas (2DEG) with high mobility at a heterojunction, i.e., at the interface between semiconductor materials with different band gaps. For instance, HEMT transistors are known based upon the heterojunction between a layer of aluminum gallium nitride (AlGaN) and a layer of gallium nitride (GaN). 
     HEMT transistors based upon AlGaN/GaN heterojunctions afford a wide range of advantages that render them particularly suited and widely used for various applications. 
     For instance, the high breakdown threshold of HEMT transistors is exploited for high-performance power switches. The high mobility of the electrons in the conductive channel makes it possible to provide high-frequency amplifiers. Moreover, the high concentration of electrons in the 2DEG enables a low ON-state resistance (Rory) to be obtained. 
     On account of the high cost of gallium-nitride substrates, HEMT transistors based upon AlGaN/GaN heterojunctions are normally obtained via growth of GaN and AlGaN layers on silicon substrates. Consequently, the HEMT transistors thus obtained are of a planar type; i.e., they have the source, gate, and drain electrodes or terminals aligned in a plane parallel to the substrate. 
     A known solution for providing HEMT transistors consists in the use of recessed-gate terminals. 
     A transistor of this type is illustrated schematically in  FIG. 1 . 
       FIG. 1  shows, in a triaxial system of mutually orthogonal axes X, Y, Z, a HEMT device  1 , which includes: a substrate  2 , made, for example, of silicon; a channel layer  4  of intrinsic gallium nitride (GaN), which extends over the substrate  2 ; a barrier layer  6  of intrinsic aluminum gallium nitride (AlGaN), which extends over the channel layer  4 ; an insulation layer  7  of dielectric material, such as nickel oxide (NiO), which extends on an upper side  6   a  of the barrier layer  6 ; and a gate region  8 , which extends in the insulation layer  7  between a source terminal  10  and a drain terminal  12 . 
     The channel layer  4  and the barrier layer  6  form a heterostructure  3 . 
     In a way not illustrated in the figure, a buffer layer may be present between the substrate  2  and the heterostructure  3 . 
     A gate terminal  8 , of a recessed type, extends in depth through the insulation layer  7 , until it reaches the barrier layer  6 . In other words, the gate terminal  8  is formed in a trench  9  etched through the insulation layer  7 . The source terminal  10  and the drain terminal  12 , which are made of conductive material, for example metal material, extend in depth in the semiconductor body  5 , completely through the barrier layer  6 , terminating at the interface between the barrier layer  6  and the channel layer  4 . The channel layer  4  and the barrier layer  6  are, in general, made of materials such that, when they are coupled together as illustrated in  FIG. 1 , they form a heterojunction that enables formation of a region, or layer, of two-dimensional gas (2DEG). 
     A gate dielectric layer  8   a  extends in the trench  9 , facing the bottom and side walls of the trench  9 . A gate metallization  8   b  completes filling of the trench  9  and extends over the gate dielectric layer  8   a.  The gate dielectric layer  8   a  and the gate metallization  8   b  form the gate terminal  8  of the HEMT device  1 . 
     The gate terminal  8  is separated laterally (i.e., along X) from the source terminal  10  and drain terminal  12  by means of respective portions  7   a  and  7   b  of the insulation layer  7 . As illustrated in  FIG. 1 , as a consequence of the manufacturing process currently used, the gate metallization  8   b  likewise extends over the insulation layer  7 , alongside the trench  9 , forming in particular a field-plate element  8   c  that extends along X towards the source terminal  10 . A similar field-plate element  8   d  extends along X in the opposite direction, i.e., towards the drain terminal  12 . 
     A passivation layer  5 , for example made of insulating or dielectric material, in particular silicon nitride (Si 3 N 4 ), extends over the source terminal  10 , the drain terminal  12 , and the gate terminal  8 , and over the insulation layer  7 . The passivation layer  5  has the function of protection of the source terminal  10 , the drain terminal  12 , and the gate terminal  8  from external agents. 
     The field-plate gate topology is an efficient technique used for reducing the high electrical field in the region between the gate terminal and the drain terminal. The field-plate gate topology implies a design of the HEMT device  1  such that the side of the gate terminal  8  facing the drain terminal  12  extends over the insulation layer  7  to form the field-plate element  8   d,  so as to reduce the electrical field in the region between the gate terminal  8  and the drain terminal  12  and thus raise the breakdown threshold of the HEMT device  1 . 
     In current manufacturing processes, formation of the field-plate element  8   d,  oriented towards the drain terminal  12 , is obtained simultaneously with formation of the field-plate element  8   c,  oriented towards the source terminal  10 . 
     The present applicant has found that, even though AlGaN/GaN structures form a 2DEG layer with low electrical resistance thanks to the high current density and electron mobility, the distance LD between the gate terminal  8  and the source terminal  10  is a parameter that significantly affects the value of the current density supplied at output from the HEMT device  1 , the value of ON-state resistance R ON , and the peak value of the transconductance, in particular for radiofrequency (RF) applications and low-voltage power applications. 
     In particular, the aforementioned parameters improve by approaching the gate terminal  8  to the source terminal  10 , i.e., reducing the distance LD between the gate terminal  8  and the source terminal  10 , measured along the axis X at the top surface  6   a  of the channel layer  6 . 
     However, a reduction of the distance LD causes an undesired approach of the field-plate element  8   c  to the source terminal  10 . This aspect is undesired in so far as it increases the risk of short-circuits between the gate terminal  8  and the source terminal  10  and likewise increases the value of capacitance C GS  between the gate terminal  8  and the source terminal  10 . 
     Moreover, it should be noted that the RF gain, RF gain , is proportional to the ratio between the cut-off frequency Ft and the value of frequency f (RF gain ≈F t /f), where Ft is proportional to the inverse of the capacitance C GS  between the gate terminal  8  and the source terminal  10  (F t ≈1/C GS ). Consequently, to maximize the RF gain, it is expedient to reduce the value of the capacitance C GS , or, in other words, to move the field-plate element  8   c  away from the source terminal  10 . Moreover, it may be noted that also the capacitance that is formed between the field-plate element  8   c  and the underlying heterostructure  3  has a negative impact on the RF gain. 
     BRIEF SUMMARY 
     One or more embodiments of the present disclosure provide a HEMT, and a manufacturing method thereof, that take into due consideration the contrasting drawbacks set forth previously. 
     Hence, according to the present disclosure a HEMT transistor and a method for manufacturing the transistor are provided. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       For a better understanding of the present disclosure, preferred embodiments thereof are now described, purely by way of non-limiting example, with reference to the attached drawings, wherein: 
         FIG. 1  is a side section view of a HEMT transistor according to an embodiment of a known type; 
         FIG. 2A  is a side section view of a HEMT transistor according to an embodiment of the present disclosure; 
         FIG. 2B  is a side section view of a HEMT transistor according to a further embodiment of the present disclosure; and 
         FIGS. 3A-3F  show steps for manufacturing the HEMT transistor of  FIG. 2A . 
         FIG. 2A  shows a HEMT device  31 , in a triaxial system of mutually orthogonal axes X, Y, Z. The present disclosure applies indifferently to a HEMT device of a normally-off type or of a normally-on type. 
     
    
    
     DETAILED DESCRIPTION 
     An HEMT device  31  includes a substrate  12 , made, for example, of silicon, or silicon carbide (SiC), or sapphire (Al 2 O 3 ); an (optional) buffer layer  22 , which extends on the substrate  12 ; a channel layer  14  made of intrinsic gallium nitride (GaN), which extends on the buffer layer  22  (or directly on the substrate  12  in the case where the buffer layer  22  is not present), and has a thickness comprised between approximately 1 μm and 5 μm; a barrier layer  16 , made of intrinsic aluminum gallium nitride (AlGaN) or, more in general, of compounds based upon ternary or quaternary alloys of gallium nitride, such as Al x Ga 1-x N, AlInGaN, In x Ga 1-x N, and Al x In 1-x Al, which extends on the channel layer  14  and has a thickness t b  comprised between approximately 5 nm and 30 nm; an insulation layer  17 , made of dielectric material, such as nickel oxide (NiO), which extends on an upper side  16   a  of the barrier layer  16 ; and a gate terminal  18 , which extends in the insulation layer  7  between a source terminal  21  and a drain terminal  22 . 
     The channel layer  14  and the barrier layer  16  form a heterostructure  13 . The substrate  12 , the buffer layer  22  (when present), the channel layer  14 , and the barrier layer  16  are hereinafter referred to, as a whole, as “semiconductor body  20 ”. The heterostructure  13  hence extends between an underside  14   a  of the channel layer  14 , which constitutes part of the interface with the underlying substrate  12 , and an upper side  16   a  of the barrier layer  16 . The channel layer  14  and the barrier layer  16  are, in general, made of materials such that, when coupled together, as illustrated in  FIG. 2A , form a heterojunction that enables formation of a region, or layer, of two-dimensional gas (2DEG). 
     The gate terminal  18 , which comprises a gate dielectric  18   a  and a gate metallization  18   b,  extends throughout the thickness of the insulation layer  17 , until it reaches the barrier layer  16 . Optionally, according to a different embodiment (not illustrated), the gate terminal  18  extends through a part of the barrier layer  16  and terminates within the barrier layer  16 . The gate dielectric layer  18   a  electrically insulates the gate metallization  18   b  from the barrier layer  16 . 
     The source region  21  and the drain region  22 , which are made of conductive material, for example metal, extend in depth in the semiconductor body  20 , right through the barrier layer  16 , terminating at the interface between the barrier layer  16  and the channel layer  14 . 
     The 2DEG region extends at the interface between the channel layer  14  and the barrier layer  16  underneath the insulation layer  17 , i.e., in interface portions between the channel layer  14  and the barrier layer  16  corresponding to the projection along Z of the insulation layer  17 . According to further embodiments, the semiconductor body  20  may comprise just one or more than one layer of GaN, or GaN alloys, appropriately doped or of an intrinsic type. 
     According to an aspect of the present disclosure, the gate terminal  18  is separated laterally (i.e., along X) from the drain terminal  22  by means of a portion  17 ′ of the insulation layer  17 . A respective portion of the insulation layer  17  is not, instead, present between the gate terminal  18  and the source terminal  21 . In this way, during the manufacturing steps, as illustrated more fully hereinafter, there is no formation of a field-plate element, of the type designated by the reference  8   c  in  FIG. 1 , which protrudes towards the source terminal  21 . 
     A minimum distance L GS ′ between the gate terminal  18  and the source terminal  21 , measured along X, is equal to a distance L D ′ between the gate terminal  18  and the source terminal  21  measured at the surface  16   a  of the barrier layer  16 . Given the absence of the field-plate element between the gate terminal  18  and the source terminal  21 , the distance between the gate terminal  18  and the source terminal  21  remains constant throughout the extension, along Z, of the side surface  25  of the gate terminal  18  that faces the source terminal  21 . In other words, this side surface  25  extends, or lies, in the plane YZ and has, in each point considered, the same distance L D  from the source terminal  21 . The distance L D  is measured, in each point considered of the side surface, in a direction parallel to the axis X, which is orthogonal to the plane YZ. It is evident that the distance L D  is considered constant even in the presence of non-idealities deriving from the manufacturing process, for example corrugations, depressions, or protuberances present on the side surface  25  of the gate terminal  18  and/or on the facing surface of the source terminal  21 . 
     According to the present disclosure, the distance between the gate terminal  18  and the source terminal  21  is chosen, in the design step, so as to improve at the same time the value of ON-state resistance R ON  and the peak value of the transconductance, and to maximize the RF gain. 
     In fact, as compared to the embodiment of a known type represented in  FIG. 1 , the present disclosure makes it possible to approach the gate terminal  18  to the source terminal  21  with a reduction of the risk of shorting (owing to the absence of the corresponding field-plate element) and at the same time to maximize the RF gain when the contribution of capacitance between the field-plate element facing the source terminal and the underlying heterostructure is eliminated. 
     Moreover, the side extension, along X, of the HEMT device  31  can be reduced, for example by a value equal to the extension along X of the field-plate element  8   c,  which is now no longer present. 
     In other words, according to the present disclosure, by eliminating the field-plate element exclusively in the spatial region between the gate terminal and the source terminal, it is possible to obtain a HEMT transistor configured to meet as well as possible specific needs of application, reducing the design constraints. 
     A passivation layer  24 , made, for example, of insulating or dielectric material such as Si 3 N 4 , SiO 2 , Al 2 O 3 , or AlN, extends on the source terminal  21 , the drain terminal  22 , and the gate terminal  18 , and in particular between the gate terminal  18  and the source terminal  21 . The passivation layer  24  extends between the gate terminal  18  and the source terminal  21  until it reaches and physically contacts the channel layer  16 . 
     The passivation layer  24  has the function of protection of the source terminal  21 , the drain terminal  22 , and the gate terminal  18  from external agents and likewise has the function of side electrical insulation between the gate terminal  18  and the source terminal  21 . 
     According to another embodiment, a further field-plate metal layer  26 , illustrated in  FIG. 2B , extends over the passivation layer  24 , in particular on the gate terminal  18  and likewise alongside the latter. To provide protection and insulation of the above further field-plate metal layer  26 , a dielectric layer  27 , for example made of SiO 2 , is, in this case, present. The remaining elements of  FIG. 2B  correspond to the ones already illustrated in  FIG. 2A  and described with reference to  FIG. 2A . They are not hence described any further, and they are identified by the same reference numbers. 
     Illustrated in what follows, with reference to  FIGS. 3A-3F , are steps for manufacturing the HEMT device  1 .  FIG. 3A  shows, in cross-sectional view, a portion of a wafer  40  during a step for manufacturing the HEMT device  31 , according to an embodiment of the present disclosure. Elements of the wafer  40  common to the ones already described above with reference to  FIG. 2 , and illustrated in  FIG. 2 , are designated by the same reference numbers. In particular ( FIG. 3A ), the wafer  40  is provided, comprising: the substrate  12 , made, for example, of silicon (Si) or silicon carbide (SiC) or aluminum oxide (Al 2 O 3 ), having a front side  12   a  and a back side  12   b  opposite to one another in a direction Z; the channel layer  14 , made of gallium nitride (GaN), having its own underside  14   a  that extends adjacent to and overlapping the front side  12   a  of the substrate  12 ; and the barrier layer  16 , made of aluminum gallium nitride (AlGaN), which extends over the channel layer  14 . The barrier layer  16  and the channel layer  14  form the hetero structure  13 . 
     Next ( FIG. 3B ), formed on a front side  16   a  of the barrier layer  16  is the insulation layer  17 , made of dielectric material such as silicon oxide (SiO 2 ) and having a thickness comprised between 10 nm and 150 nm. The insulation layer  17  may also be made of nickel oxide (NiO), or silicon nitride (Si 3 N 4 ), or aluminum oxide (Al 2 O 3 ), or aluminum nitride (AlN). Formation of the insulation layer  17  is performed via epitaxial growth on the barrier layer  6  (AlGaN). With reference to Roccaforte, F. et al., “Epitaxial NiO gate dielectric on AlGaN/GaN heterostructures,” Appl. Phys. Lett., vol. 100, 063511, 2012, it is known that it is possible to carry out an epitaxial growth of NiO on AlGaN by means of MOCVD (Metal Organic Chemical Vapor Deposition). 
     Then ( FIG. 3C ), a step of masked etching of the insulation layer  17  is carried out to remove selective portions of the latter that extend in regions of the wafer  40  in which it is desired to form the source region  21  and the drain region  22  of the HEMT device  1 . Etching proceeds, possibly with a different etching chemistry, for removing exposed portions of the barrier layer  16 , until the channel layer  14  is reached. In particular, openings  34   a  and  34   b  are formed. 
     Then ( FIG. 3D ), a step of formation of ohmic contacts is carried out to obtain the source and drain regions  21 ,  22  by depositing conductive material, in particular a metal, such as titanium (Ti), tantalum (Ta), aluminum (Al), or alloys or compounds thereof, by means of sputtering or vapor deposition, within the openings  34   a,    34   b.    
     This is followed by a step of rapid thermal annealing (RTA), for example at a temperature of between approximately 500° C. and 700° C. for a time of from 30 s to 120 s, which makes it possible to perfect formation of the ohmic contacts of the source region  21  and the drain region  22  with the underlying region (presenting the 2DEG). 
     Then ( FIG. 3E ), the insulation layer  17  is selectively removed, for example by means of lithographic and etching steps so as to remove selective portions thereof in a region of the wafer  40  in which, in subsequent steps, the gate region  18  of the HEMT device  31  is to be formed. 
     The etching step can stop at the underlying barrier layer  16  (as illustrated in  FIG. 3E ), or else proceed partially within the barrier layer  16  or, again, completely involve the barrier layer  16  (in a way not illustrated in the figures). 
     A surface portion  16 ′ of the barrier layer  16  is thus exposed. Etching of the barrier layer  16  is, for example, of a dry type. The portion of the barrier layer  16  removed generates a trench  19 , which extends throughout the thickness of the insulation layer  17 . 
     As described with reference to  FIG. 2A , the step of  FIG. 3E  envisages etching of the insulation layer  17  in a region that extends from the source terminal  21  towards the drain terminal  22  (without reaching the latter), with removal of the insulation layer  17  alongside the source terminal  21 . 
     Then ( FIG. 3F ), formed, for instance by deposition, is the gate dielectric layer  18   a,  made for example of a material chosen from among aluminum nitride (AlN), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), and silicon oxide (SiO 2 ). The gate dielectric layer  18   a  has a thickness chosen between 5 nm and 50 nm, for example 30 nm. 
     Then, a step of deposition of conductive material on the wafer  40  is carried out to form, by means of known photolithographic techniques, the gate metallization  18   b  on the gate dielectric layer  18   a,  filling the trench  19  and thus forming the gate region  18 . For instance, the gate metallization  18   b  is made of metal material, such as tantalum (Ta), tantalum nitride (TaN), titanium nitride (TiN), palladium (Pa), tungsten (W), tungsten silicide (WSi 2 ), titanium aluminum (Ti/Al), and nickel gold (Ni/Au). 
     The gate dielectric layer  18   a  that is not protected by the gate metallization  18   b  (and in particular the portion of the gate dielectric  18   a  that extends, in top plan view in the plane XY, between the gate metallization  18   b  and the source terminal  21 ), can be removed by means of an etching step or kept on the wafer  40 , indifferently. 
     Formation of the gate terminal  18  does not damage the source and drain terminals already formed. In fact, even though some of the metals of the source and drain terminals (typically, Ti and Ta) could be partially etched, the effect thereon is not important for operation of the device; the aluminum is not damaged, nor partially etched, by the chemistry used for etching the gate dielectric  18   a.    
     The gate terminal  18  is formed, as mentioned previously with reference to  FIG. 2A , so as to provide the gate metallization  18   b  at a distance L D  from the source terminal  21 . Just one field-plate element  18 ′ extends as a continuation of the gate metallization  18   b  towards the drain terminal  22 , on the insulation layer  17 . No similar field-plate element is instead present extending towards the source terminal  21  in so far as, in the spatial region between the gate terminal  18  and the source terminal  21 , the insulation layer  17  is absent. 
     Finally, a step of deposition of the passivation layer  24  is carried out. This step is performed, for example, by depositing a layer of 400 nm by means of PECVD. 
     The material of the passivation layer  24  is deposited within the space present between the gate terminal  18  and the source terminal  21 , filling it and electrically insulating the gate terminal  18  from the source terminal  21 . 
     The HEMT device  31  illustrated in  FIG. 2A  is thus formed. 
     The advantages of the disclosure according to the present disclosure emerge clearly from what has been set forth previously. 
     In particular, there may be noted, according to the present disclosure, a reduction in the R ON  (due to a shorter gate-source distance), and hence an increase in the maximum current supplied at output from the device and also in the output power. 
     Moreover, there may be noted a reduction in the gate-to-source capacitance C GS  and hence an increase in the cut-off frequency and gain, in particular in RF applications. 
     Finally, it is clear that modifications and variations may be made to what has been described and illustrated herein, without thereby departing from the sphere of protection of the present disclosure. 
     For instance, the metallization of the (source, drain, and gate) contacts on the front of the wafer can be performed using any variant known in the literature, such as formation of contacts made of AlSiCu/Ti or Al/Ti, or W-plugs, or others still. 
     Moreover, the channel layer  4  and the barrier layer  6  may be made of other materials chosen from among compound materials constituted by elements of Groups III and V, such as InGaN/GaN or AlN/GaN. 
     The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above-detailed description. In general, in the following claims, the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims, but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the disclosure.