Patent Publication Number: US-10326418-B2

Title: Large input swing circuit, corresponding device and method

Description:
PRIORITY CLAIM 
     This application claims the priority benefit of Italian Application for Patent No. 102017000054686, filed on May 19, 2017, the disclosure of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. 
     TECHNICAL FIELD 
     The description relates to electronic circuits. 
     One or more embodiments may be applied in buffer circuit stages for digital-to-analog or analog-to-digital converters. 
     BACKGROUND 
     Electronic circuits exposed in operation to large variability of, for example, input voltage (that is large input swings) have been an area of extensive research and development over the years. 
     Buffer circuits for digital-to-analog or analog-to-digital converters (DACs or ADCs) are exemplary of possible applications of such circuits. 
     Despite that intensive activity in that area, further improved solutions are still desirable, for example, in respect of one or more of the following aspects:
         availability of flexible solutions suited for use in any circuit exposed to large input voltage swings,   improved performance when used in DACs or ADCs,   possibility of using input transistors of a voltage class lower than the supply voltage (for example, 1.8V v. 3V),   facilitated use in a wide variety of circuits such as, for example, High Voltage—HV operational amplifier (OpAmps).       

     There is a need in the art to contribute in providing such an improved solution. 
     SUMMARY 
     One or more embodiments relate to a device (for example, a device including digital-to-analog or analog-to-digital converters) and a corresponding method. 
     The claims are an integral part of the disclosure of one or more embodiments as provided herein. 
     One or more embodiments may provide an arrangement which facilitates achieving high precision without penalizing performance. 
     In one or more embodiments, the drain-source voltage V DS  of an input couple or pair may contribute in keeping the characteristic of the circuit constant. 
     In an embodiment, a circuit, includes: a power-supply terminal, at least one current generator transistor arranged with its current path between the power-supply terminal and a current supply node, an input transistor pair including a first input transistor and a second input transistor, the first and second input transistors having their current paths coupled to the current supply node, the first input transistor having a control terminal configured for receiving an input signal to the circuit, a cascode transistor pair including a first cascode transistor and a second cascode transistor, the current paths of the first and second cascode transistor between the supply terminal and the current paths of the second input transistor and the first input transistor respectively; the cascode transistors in the cascode transistor pair having their control terminals coupled to a common control node, and a bias circuit having a bias input configured for receiving said input signal and a bias output coupled to the common node of the control terminals of the cascode transistors in the cascode transistor pair, the bias circuit including a signal tracking circuit stage active between the bias input and the bias output wherein the common node of the control terminals of the cascode transistors in the cascode transistor pair is configured to track the input signal to the circuit. 
     In one or more embodiments, the first cascode transistor and the second cascode transistor in the cascode transistor pair may have their current paths coupled to the supply terminal via respective paired transistors arranged with their current paths between the supply terminal and the first cascode transistor and the second cascode transistor in the cascode transistor pair, respectively. 
     In one or more embodiments, one of the transistors in said respective paired transistors is diode-coupled. 
     In one or more embodiments, the signal tracking circuit stage in the bias circuit may include a bias input transistor pair having control terminals commonly coupled to the bias input to receive said input signal, the bias input transistors in the bias input transistor pair having their current paths set between the supply terminal and ground with respective coupling resistors set between the bias input transistors in the bias input transistor pair and ground and a further resistor in the current path through one bias input transistor in the bias input transistor pair, the further resistor set between the one bias input transistor in the bias input transistor pair and the bias output. 
     In one or more embodiments, the first bias input transistor and the second bias input transistor in the bias input transistor pair may have their current paths coupled to the supply terminal via respective paired bias transistors arranged with their current paths between the supply terminal and the first bias input transistor and the second bias input transistor in the bias input transistor pair, respectively, with said further resistor between the first bias input transistor in the bias input transistor pair and a first paired bias transistor in said respective paired bias transistors. 
     In one or more embodiments, the second paired bias transistor in said respective paired bias transistors is diode-coupled. 
     In one or more embodiments, the signal tracking circuit stage in the bias circuit may be coupled with a current generation arrangement sensitive to said input signal dropping below a lower level, the current generation arrangement coupled to the transistors in the cascode transistor pair to maintain the common node of the control terminals of the cascode transistors in the cascode transistor pair at a fixed bottom value with the input signal below said lower level. 
     In one or more embodiments, the current generation arrangement may be coupled between said further resistor and the first bias input transistor in the bias input transistor pair. 
     In an embodiment, a device may include a circuit according to one or more of the embodiments described above. 
     Such a device may include: a digital-to-analog converter having the circuit as an output buffer, or an analog-to-digital converter having the circuit as an input buffer. 
     In an embodiment, a method comprises: providing at least one current generator transistor arranged with its current path between a power-supply terminal and a current supply node, providing an input transistor pair including a first input transistor and a second input transistor, the first and second input transistors having their current paths coupled to the current supply node, by applying to the control terminal of the first input transistor an input signal to the circuit, providing a cascode transistor pair including a first cascode transistor and a second cascode transistor with the current paths of the first and second cascode transistors between the supply terminal and the current paths of the second input transistor and the first input transistor, respectively; the cascode transistors in the cascode transistor pair having their control terminals coupled to a common control node, and providing a bias circuit having a bias input receiving said input signal and a bias output coupled to the common node of the control terminals of the cascode transistors in the cascode transistor pair, the bias circuit including a signal tracking circuit stage acting between the bias input and the bias output wherein the common node of the control terminals of the cascode transistors in the cascode transistor pair tracks the input signal to the circuit. 
     In an embodiment, a circuit comprises: a pair of differential input transistors coupled to a tail current source, wherein one input transistor of said pair of differential input transistors has a control node configured to receive an input signal; a pair of load transistors coupled in series with the pair of differential input transistors and having a first bias common control terminal biased by a first bias signal; a bias generator circuit configured to generate said first bias signal. The bias generator circuit comprises: a first pair of transistors having a first common control terminal configured to receive said input signal; a second pair of transistors coupled in series with the first pair of transistors and having a second common control terminal; a first current source coupled to source a first current through a first diode-connected transistor coupled to a node between a first transistor of the first pair of transistors and a first transistor of the second pair of transistors; a second current source coupled to source a second current through a second diode-connected transistor; and a circuit configured to combine the first and second currents to generate the first bias signal. 
     In an embodiment, a circuit comprises: a pair of differential input transistors coupled to a tail current source, wherein one input transistor of said pair of differential input transistors has a control node configured to receive an input signal; a folded cascode output stage including a pair of cascode transistors coupled to the pair of load transistors and having a first bias common control terminal configured to receive a first bias signal; a bias generator circuit configured to generate said first bias signal. The bias generator circuit comprises: a first pair of transistors having a first common control terminal configured to receive said input signal; a second pair of transistors coupled in series with the first pair of transistors and having a second common control terminal; and a first output node coupled between a first transistor of the first pair of transistors and a first transistor of the second pair of transistors, said first output node generating the first bias signal which tracks the input signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       One or more embodiments will now be described, by way of example only, with reference to the annexed figures, wherein: 
         FIG. 1  is a block diagram of a digital-to-analog converter (DAC), 
         FIGS. 2 and 3  are exemplary of possible implementations of a part of the circuit of  FIG. 1 , 
         FIG. 4  is a circuit diagram exemplary of embodiments, 
         FIG. 5  is exemplary of possible operation of embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     In the ensuing description, one or more specific details are illustrated, aimed at providing an in-depth understanding of examples of embodiments of this description. The embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other cases, known structures, materials, or operations are not illustrated or described in detail so that certain aspects of embodiments will not be obscured. 
     Reference to “an embodiment” or “one embodiment” in the framework of the present description is intended to indicate that a particular configuration, structure, or characteristic described in relation to the embodiment is comprised in at least one embodiment. Hence, phrases such as “in an embodiment” or “in one embodiment” that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment. Moreover, particular conformations, structures, or characteristics may be combined in any adequate way in one or more embodiments. 
     The references used herein are provided merely for convenience and hence do not define the extent of protection or the scope of the embodiments. 
     In  FIG. 1 , reference  100  denotes as a whole a device such as a digital-to-analog converter (DAC) including an output buffer circuit stage  10 . 
     The converter  100  exemplified in  FIG. 1  includes an input differential circuit stage  102  which receives on a (non-inverting) input a signal REF DAC  and whose output drives a transistor (for example, a MOSFET transistor)  104  via the control terminal thereof (gate, in the case of a field effect transistor such as a MOSFET transistor). The current path (for example, the source terminal) of the transistor  104  is coupled to a supply line V DD  and to a set of current generators  106  having associated electronic switches  106   a  configured to be turned on and off (that is, made conductive and non-conductive) according to the “N-Bits” of the converter. 
     The converter  100  exemplified in  FIG. 1  also includes a set of resistors  108  arranged in a voltage-divider arrangement between the transistor  104  and ground and having associated respective electronic switches  108   a  configured to be selectively turned on and off (that is made conductive and non-conductive) according to the so-called “M-Bits” of the converter. 
     The top end of the divider  108  (which is coupled to the transistor  104 , for example, to the drain thereof) is also coupled in a feedback path to the other (inverting) input of the differential input circuit stage  102 . 
     The common ends of the switches  106   a  and  108   a  are coupled to the inputs (for example, inverting and non-inverting) of a differential circuit stage (for example, an operational amplifier)  110  in an output buffer  10  having a (negative) feedback resistor  110   a  coupled between the output terminal of the converter  100 , providing an output signal OUT DAC  and the (inverting) input of the circuit stage  110 . 
     Further details on the structure and operation of a converter as exemplified in  FIG. 1  can be derived, for example, from U.S. Pat. Nos. 7,098,831 or 7,348,912 (incorporated by reference), thus making it unnecessary to provide a detailed description herein. 
     It will otherwise be appreciated that reference to the arrangement of  FIG. 1  is merely exemplary of a possible context of use of embodiments: the instant detailed description makes reference to a digital-to-analog converter (DAC) as a possible context of use; however one or more embodiments can be applied, for example, to an analog-to-digital converter (ADC) or, more generally, to circuits for which the ability to withstand large input voltage swings without unduly penalizing performance is a desirable feature. 
     For instance, operation of a converter arrangement as exemplified in  FIG. 1  may be facilitated by the capability of admitting (for example, at the non-inverting input  10   a  of the buffer circuit stage  10 ) voltage ranges from, say 0.1V to 1.8V (also) in circumstances where the circuit is supplied with a voltage in a range from, for example, 3.2V to 2.8V. 
     The circuit diagram of  FIG. 2  is exemplary of possible critical aspects of such a situation. 
     In  FIG. 2 , V DD   _   MIN  (for example, 2.8V) is exemplary of a lower bound of an admissible range of the values for the supply voltage V DD  applied to an input transistor pair M 1 , M 2  of the differential circuit stage  110  via a tail transistor M 3  in a current mirror pair supplied by a voltage V DD , with the control electrode (for example, gate in the case of a field effect transistor such as a MOSFET transistor) of M 1  receiving an input voltage between 0.1V and 1.8V at the input terminal  10   a.    
     It will be otherwise appreciated that the quantitative values given in the foregoing are merely exemplary and not intended to be limitative of the embodiments discussed in the following. 
     Transistors (such as MOSFET transistors) sustaining 5V can be used in an arrangement as exemplified in  FIG. 2  in an output buffer as exemplified at 10 with a power supply V DD  around 3V. 
     These transistors have a high threshold voltage V T  so that with a threshold voltage V T  of 1V or higher, and in the presence of an input gate voltage for M 1  and M 2  of about 1.8V, this may result in a value of 2.8V or higher for the voltage at the node V S  (for example, drain of M 3 ) where M 1 , M 2  are coupled (for example, via their sources). This leaves no headroom for the tail transistor M 3  to work as desired when the supply voltage V DD  reaches a value of, for example, V DD   _   MIN =2.8 as exemplified in  FIG. 2 . 
     A possible approach in dealing with these issues is represented by the solution exemplified in  FIG. 3 , including a full-swing input circuit stage with an n-channel input circuit stage M 10 , M 20  in parallel to a p-channel input circuit stage M 30 , M 40  and a current summation circuit stage  12  set there between. 
     In an arrangement as exemplified in  FIG. 3 , the circuit stages M 10 , M 20  and M 30 , M 40  are coupled to respective current generators in turn coupled to supply lines V DD  and V SS ). 
     Even if both p-channel and n-channel thresholds are high, when the input signal is close to V SS  (ground) the p-channel transistors M 30 , M 40  and the upper tail current (as provided, for example, by a p-channel transistor) may operate correctly while the n-channel transistors M 10 , M 20  and the lower tail current are off. Complementary operation occurs when the input signal is close to V DD . 
     An arrangement as exemplified in  FIG. 3  facilitates admitting a large input swing for the circuit, at the expense of an offset depending on the input signal amplitude. This results in a low common mode rejection ratio—CMRR for an amplifier in an amplifying chain or in degradation in terms of differential non-linearity (DNL) or integral non-linearity (INL) in so far as monotonicity cannot be achieved, for example, in a circuit operating as an output buffer in a digital-to-analog converter or as an input buffer in an analog-to-digital converter. 
     Still another approach may involve using for M 1 , M 2  and M 3  in an arrangement as exemplified in  FIG. 2 , for example, 1.8V MOS transistors. Such transistors may in fact exhibit lower threshold voltages, for example, less than 0.6V: in that way, for an input of 1.8V, the voltage V S  will be around 2.5V thus leaving enough voltage headroom for M 3  to operate correctly as a tail current generator. However, for an input as low as 0.1V, V S  will be about 0.8V with M 3  having a drain-source voltage V DS  higher than 1.8V, thus exiting the upper bound rating of the process. 
     One or more embodiments as exemplified in  FIG. 4  may retain the basic layout exemplified in  FIG. 2 :
         by selecting a folded cascode topology for an associated output circuit as indicated by  20  on the right-hand side of  FIG. 4 , and   by biasing the common gate of the cascode transistors (for example, M 6 , M 7  in  FIG. 4 ) by means of a signal V B  generated by an “input tracking” dynamic bias circuit as indicated by  30  on the left-hand side of  FIG. 4 .       

     In the right-hand portion of  FIG. 4  like parts or elements as those already discussed in connection with previous figures such as  FIG. 2  are indicated with like symbols/numerals: a corresponding detailed description will not be repeated here for the sake of brevity. 
     In the exemplary folded cascode portion  20  of  FIG. 4 , opposite to the tail transistor M 3  (node V S ), the current paths of the transistors M 1 , M 2  are arranged in series with the current paths (again source-drain paths, in the case of field effect transistors such a MOSFET transistor) of two transistors (for example, MOSFET transistors) M 4 , M 5  set between the transistors M 1 , M 2  and ground. 
     Also, intermediate nodes: a) between the transistor M 1  and M 4 , where a voltage V D1  is present, and b) between the transistor M 2  and M 5 , where a voltage V D2  is present, are coupled with the current paths (for example, to the source terminals, in the case of field effect transistors such a MOSFET transistor) of the cascode transistors M 7  and M 6 . These latter transistors have their control terminals (gates, in the case of a field effect transistors such as MOSFET transistors) coupled to a voltage V B  (generated in the bias circuit  30  as discussed in the following). 
     In the exemplary folded cascode portion  20  of  FIG. 4 , the cascode transistors M 6 , M 7  have their current paths (here, the drain terminals) coupled with the supply node at voltage V DD  via a respective transistors M 8 , M 9  having common control terminals (for example, gates) mutually coupled with M 9  connected in a diode arrangement. 
     In the exemplary embodiment of  FIG. 4 , the output V OUT  from the circuit  10  is provided at an output terminal  10   b  such as the common drains of transistors M 6  and M 8  in the folded cascode amplifier. 
     The bias circuit  30  exemplified in  FIG. 4  can be regarded as a “dynamic” bias circuit in view of its tracking ability of the input signal V IN . 
     In the arrangement exemplified in  FIG. 4 , the input signal V IN  is applied:
         at node  10   a , to the control terminal of the transistor M 1  in the cascode circuit  20 , and   to the mutually coupled control terminals (gates, in the case of field effect transistors such as MOSFET transistors) of an input pair MB 1 , MB 2  including transistors (such as MOSFET transistors) having their current generation terminals (source terminals, in the case of field effect transistors such as MOSFET transistors) coupled to ground via bias resistors R 1 .       

     The transistors MB 1 , MB 2  have their current paths (here the drain terminals) coupled to the supply node V DD  via respective further transistors (again MOSFET transistors, for instance) MB 3 , MB 4  having their control terminals (gates, in the case of field effect transistors such as MOSFET transistors) mutually coupled with the transistor MB 4  coupled in a diode arrangement. 
     A resistor R 2  is set between the transistor MB 1  and the transistor MB 3  and the voltage V B —which is applied to the (common) control terminals of the transistors M 6  and M 7  in the cascode circuit  20 —available between the transistor MB 3  and the resistor R 2 . 
     The signal available between the resistor R 2  and the transistor MB 1  (that is the signal at the terminal of the resistor R 2  opposed to the one at which the voltage V B  is available) is coupled to a transistor MB 7  in a diode arrangement crossed by a current generator IB 1 . 
     The source terminal of MB 7  is in turn connected to the source and drain terminals of two transistors MB 6  and MB 5 , respectively, with transistor MB 6  is connected in a diode arrangement with control terminal (gate, in the case of a field effect transistors such as a MOSFET transistor) of MB 6  coupled to the homologous terminal of MB 5  and to a current generator IB 2 . 
     The transistor MB 5  shares a common connection of its control terminal (gate terminal, in the case of a field effect transistor such as a MOSFET transistor) with the homologous terminals of the transistors M 4  and M 5 . 
     In operation of an arrangement as exemplified in  FIG. 4 , when the input signal V IN  is low (for example, close to 0.1V) no current will flow through MB 1 , MB 2 , MB 3  and MB 4 ; no current will likewise flow through the resistor R 2 . Consequently, a bottom “pedestal” value for V B  (for example, V B0 ) can be selected by sizing MB 5 , MB 6 , MB 7 , IB 1  and IB 2 . 
     In one or more embodiments such a value V B0  can be fixed so that V D1  and V D2  are in, say, the hundred mV range, so that—in those circumstances—M 4  and M 5  will be saturated thus operating essentially as current generators. 
     As a result of an increase in the input signal above the threshold voltage of MB 1  and MB 2 , all of MB 1 , MB 2 , MB 3  and MB 4  will start conducting a current I R1 =I R2 =(V IN −V THN )/R 1 , where V THN  indicates the threshold voltages of these transistors, which may be reasonably assumed to be essentially the same. 
     In that way, the currents I R1  and I R2  will have a value proportional to the input signal V IN . This will in turn result in a voltage drop on R 2  which can be expressed as V drop   _   R2 =(R 2 /R 1 )(V IN −V THN ), that is still proportional to the input voltage amplitude. 
     The value of V B  will be given (as a function of the input signal V IN ) by a relationship such as:
 
 V   B   =V   B0 +( R 2 /R 1)( V   IN   −V   THN ).
 
     Since V D1 =V D2 =(V B −V THN ) the drains of the input transistors will “track” the input voltage applied on their control terminals thus facilitating having a value for V DS  (much) lower than 1.8V and almost constant versus their input signal amplitude. 
     Such a behavior is exemplified in  FIG. 5 , where the behavior of various signal is shown in an arbitrary ordinate scale (for example, volt V) as a function of V IN  (abscissa scale). 
     The dashed line represents, so-to-say, V IN  itself, while the upper continuous line represents the common source voltage V S  of M 1  and M 2 , and finally the lower chain line represents the voltage V D1 =V D2 =V D  at the drains of M 1  and M 2 , respectively; the shaded area represents V DS1 =V DS2 =V DS , i.e. the voltage difference between V S  and V D  which is approximately constant versus V IN , other than at the left hand side (low values for Vin) where the “pedestal” behavior of V B0  comes into play. 
     One or more embodiment may thus provide one or more of the following advantages:
         the drain voltages of the input transistor pair are rendered capable of tracking the input signal,   the drain/source voltage of the input pair exhibits a (very) low dependence on the input signal,   controlling the ratio of the values R 2 /R 1  of the homologous resistors exemplified in  FIG. 4  makes it possible to tune the slope of the tracking action,   the possibility exists of dispensing with a rail-to-rail input circuit stage, thus avoiding CMRR and INL/DNL degradation,   one or more embodiments may be implemented by using transistors of a voltage class lower than the power-supply value.       

     One or more embodiments may thus concern a circuit (for example,  10 ), including:
         a power-supply terminal (for example, V DD ),   at least one current generator transistor (for example, M 3 ) arranged with its current path (for example, source-drain in the exemplary case of a field-effect transistor) between the power-supply terminal and a current supply node (for example, V S ),   an input transistor pair (for example, M 1 , M 2 ) including a first input transistor and a second input transistor, the first and second input transistors having their current paths coupled to the current supply node, the first input transistor having a control terminal (for example, gate, in the exemplary case of a field-effect transistor) configured for receiving an input signal (for example, V IN ) to the circuit,   a cascode transistor pair (for example, M 6 , M 7 ) including a first cascode transistor and a second cascode transistor, the current paths of the first and second cascode transistor between the supply terminal and the current paths of the second input transistor and the first input transistor respectively; the cascode transistors in the cascode transistor pair having their control terminals coupled to a common control node (for example, V B ), and   a bias circuit (for example,  30 ) having a bias input configured for receiving said input signal and a bias output coupled to the common node of the control terminals of the cascode transistors in the cascode transistor pair, the bias circuit ( 30 ) including a signal tracking circuit stage (for example, MB 1 , MB 2 , MB 3 , MB 4 , R 1 , R 2 ) active between the bias input and the bias output wherein the common node of the control terminals of the cascode transistors in the cascode transistor pair is configured to track the input signal to the circuit. In one or more embodiments, the first cascode transistor and the second cascode transistor in the cascode transistor pair may have their current paths coupled to the supply terminal via respective paired transistors (for example, M 8 , M 9 ) arranged with their current paths between the supply terminal and the first cascode transistor and the second cascode transistor in the cascode transistor pair, respectively.       

     In one or more embodiments, one (for example, M 9 ) of the transistors in said respective paired transistors is diode-coupled (for example, gate shorted to drain). 
     In one or more embodiments, the signal tracking circuit stage in the bias circuit may include a bias input transistor pair (for example, MB 1 , MB 2 ) having control terminals commonly coupled to the bias input to receive said input signal, the bias input transistors in the bias input transistor pair having their current paths set between the supply terminal and ground with respective coupling resistors (for example, R 1 ) set between the bias input transistors in the bias input transistor pair and ground and a further resistor (for example, R 2 ) in the current path through one (for example, MB 1 ) bias input transistor in the bias input transistor pair, the further resistor set between the one bias input transistor (for example, MB 1 ) in the bias input transistor pair and the bias output (for example, V B ). 
     In one or more embodiments, the first bias input transistor and the second bias input transistor in the bias input transistor pair may have their current paths coupled to the supply terminal via respective paired bias transistors (for example, MB 3 , MB 4 ) arranged with their current paths between the supply terminal and the first bias input transistor and the second bias input transistor in the bias input transistor pair, respectively, with said further resistor between the first bias input transistor in the bias input transistor pair and a first paired bias transistor (for example, MB 3 ) in said respective paired bias transistors. 
     In one or more embodiments, the second paired bias transistor (for example, MB 4 ) in said respective paired bias transistors is diode-coupled (for example, gate shorted to drain). 
     In one or more embodiments, the signal tracking circuit stage in the bias circuit may be coupled with a current generation arrangement (for example, IB 1 , IB 2 , IB 5 , IB 6 , IB 7 ) sensitive to said input signal dropping below a lower level, the current generation arrangement coupled (for example, M 4 , M 5 , VD 1 , VD 2 ) to the transistors in the cascode transistor pair to maintain the common node of the control terminals of the cascode transistors in the cascode transistor pair at a fixed bottom value (for example, V B0 ) with the input signal below said lower level. 
     In one or more embodiments, the current generation arrangement may be coupled between said further resistor (for example, R 2 ) and the first bias input transistor (for example, MB 1 ) in the bias input transistor pair. 
     A device according to one or more embodiments, may include a circuit according to one or more embodiments. 
     Such a device may include: a digital-to-analog converter having the circuit as an output buffer, or an analog-to-digital converter having the circuit as an input buffer. 
     A method according to one or more embodiments may include: providing at least one current generator transistor arranged with its current path between a power-supply terminal and a current supply node, providing an input transistor pair including a first input transistor and a second input transistor, the first and second input transistors having their current paths coupled to the current supply node, by applying to the control terminal of the first input transistor an input signal to the circuit, providing a cascode transistor pair including a first cascode transistor and a second cascode transistor with the current paths of the first and second cascode transistors between the supply terminal and the current paths of the second input transistor and the first input transistor, respectively; the cascode transistors in the cascode transistor pair having their control terminals coupled to a common control node, and providing a bias circuit having a bias input receiving said input signal and a bias output coupled to the common node of the control terminals of the cascode transistors in the cascode transistor pair, the bias circuit including a signal tracking circuit stage acting between the bias input and the bias output wherein the common node of the control terminals of the cascode transistors in the cascode transistor pair tracks the input signal to the circuit. 
     Without prejudice to the underlying principles, the details and embodiments may vary, even significantly, with respect to what has been described by way of example only without departing from the extent of protection. The extent of protection is defined by the annexed claims.