Patent Publication Number: US-8122307-B1

Title: One time programmable memory test structures and methods

Description:
RELATED APPLICATIONS 
     This utility patent application claims the benefit of U.S. Provisional Application Ser. No. 60/837,679 filed on Aug. 15, 2006, which is hereby claimed under 35 U.S.C. §119(e). The provisional application is incorporated herein by reference. 
    
    
     BACKGROUND 
     Memory devices are electronic devices arranged to store electrical signals. For example, a basic memory element may be a fuse that can either be open or be closed. Open and closed states of the fuse may be used to designate one bit of information corresponding to a value of 1 or 0. A plurality of memory elements can be combined in various arrangements in order to store multiple bits arranged in words or other combinations. Various electronic circuits including semiconductor devices such as transistors are used as memory elements. 
     Memory elements may be classified in two main categories: volatile and nonvolatile. Volatile memory loses any data as soon as the system is turned off. Thus, it requires constant power to remain viable. Most types of random access memory (RAM) fall into this category. Non-volatile memory does not lose its data when the system or device is turned off. An NVM device may be implemented as a MOS transistor that has a source, a drain, an access or a control gate, and a floating gate. It is structurally different from a standard MOSFET in its floating gate, which is electrically isolated, or “floating”. 
     A range of considerations including a purpose of the device, power consumption, size, retention capacity and duration may influence design of non-volatile memory devices. For example, some NVM devices may be categorized as floating gate or charge-trapping from a programming perspective. 
     Non-volatile memory devices may also be implemented as NVM arrays that include a plurality of NVM cells arranged in rows and columns. In general, single-transistor n-channel NVM cells operate as follows. During an erase operation, electrons are removed from a floating gate of the NVM cell, thereby lowering the threshold voltage of the NVM cell. During a program operation, electrons are inserted into the floating gate of the NVM cell, thereby raising the threshold voltage of the NVM cell. Thus, during program and erase operations, the threshold voltages of selected NVM cells are changed. During a read operation, read voltages are applied to selected NVM cells. In response, read currents flow through these selected NVM cells. 
     An important part of memory manufacturing process is testing the manufactured memory devices. For multiple times programmable devices, the memories may be programmed with test values, then read, and their usability confirmed. Since the devices are multiple times programmable, the tested devices may then be returned to the manufactured batch. 
     On the other hand, testing one time programmable memories presents a number of challenges. 100% testing is impossible, since any memory programmed for testing becomes unusable for other purposes. Sample testing brings in statistical risk factors as well as a wasted group of memories for each tested batch. 
     SUMMARY 
     This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter. 
     Embodiments are directed to only One Time Programmable (OTP) memory structures and methods of testing those. One or more dedicated memory test cells may be utilized for testing support circuitry associated with a group of regular OTP memory cells. The dedicated memory test cells may be an extra group of cells in an array, randomly selected cells among the regular OTP cells, and the like. During a pretest process, the dedicated test cells are programmed and read. The read values are then compared to the programmed or expected values enabling a determination whether the support circuitry for the associated regular OTP memory cells are usable or not. 
     This and other features and advantages of the invention will be better understood in view of the Detailed Description and the Drawings, in which: 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Non-limiting and non-exhaustive embodiments are described with reference to the following drawings. 
         FIG. 1  is a diagram of an electronic device that includes a memory storing information to be used by other circuits; 
         FIG. 2A  is a block diagram of one type of memory comprising a homogeneous memory core and associated support circuitry; 
         FIG. 2B  is a block diagram of another type of memory comprising a hybrid memory core and associated support circuitry; 
         FIG. 3A  is a detailed block diagram of a hybrid memory including an only One-Time Programmable (OTP) portion and example support circuits; 
         FIG. 3B  is an electrical schematic diagram of a memory cell in accordance with one embodiment; 
         FIG. 4  is a conceptual diagram for explaining the conventional order of a process for manufacturing, testing, and regularly programming for a memory circuit such as the memory of  FIG. 3A ; 
         FIG. 5A  is a detail for showing how a regular cell of an OTP memory can be controlled by a support circuit, as is a dedicated memory cell, whose purpose is to pretest the support circuitry according to embodiments; 
         FIG. 5B  is a detail for showing how a group of regular cells of an OTP memory, such as the cell of  FIG. 5A , here disposed along a line, for example, are controlled by a support circuit, as is a dedicated memory cell whose purpose is to pretest the support circuitry according to embodiments; 
         FIG. 5C  is a block diagram of an initially manufactured OTP memory according to embodiments, having regular only one time programmable cells, associated support circuitry for controlling the regular cells, and dedicated memory cells for pretesting the support circuitry; 
         FIG. 5D  is the block diagram of  FIG. 5C , after the support circuitry has been pretested by the dedicated memory cells; 
         FIG. 5E  is the block diagram of  FIG. 5D , after the regular only one time programmable cells have been further regularly programmed for supporting an operational component; 
         FIG. 6A  is a flowchart for describing memory pretesting and programming processes according to embodiments; 
         FIG. 6B  is a flowchart for describing a pretesting operation of  FIG. 6A  according to embodiments; 
         FIG. 7  is a conceptual diagram for showing situations arising from following the process of  FIG. 6A ; 
         FIGS. 8A-8E  illustrate different dedicated test element configurations in which multiple regular cells and multiple dedicated cells can be arranged in an OTP memory array; and 
         FIG. 9  illustrates dedicated test elements in a multiple array OTP memory configuration. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments will be described in detail with reference to the drawings, where like reference numerals represent like parts and assemblies throughout the several views. Reference to various embodiments does not limit the scope of the invention, which is limited only by the scope of the claims attached hereto. Additionally, any examples set forth in this specification are not intended to be limiting and merely set forth some of the many possible embodiments for the claimed subject matter. 
     Throughout the specification and claims, the following terms take at least the meanings explicitly associated herein, unless the context clearly dictates otherwise. The meanings identified below are not intended to limit the terms, but merely provide illustrative examples for the terms. The meaning of “a,” “an,” and “the” includes plural reference, the meaning of “in” includes “in” and “on.” The term “connected” means a direct electrical connection between the items connected, without any intermediate devices. The term “coupled” means either a direct electrical connection between the items connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means either a single component or a multiplicity of components, either active and/or passive, that are coupled together to provide a desired function. The term “signal” means at least one current, voltage, charge, temperature, data, or other measurable quantity. 
     All of the circuits described in this document may be implemented as circuits in the traditional sense, such as with integrated circuits and the like. All or some of them can also be implemented equivalently by other ways known in the art, such as by using one or more processors, Digital Signal Processing (DSP), a Floating Point Gate Array (FPGA), a general purpose micro processor and the like. 
       FIG. 1  is a diagram of an electronic device that includes a memory storing information to be used by other circuits. 
     Device  100  includes memory  110  that is adapted to interact with other circuits  102 . Individual cells of memory  110  are adapted to store information as a result of “write” operation  104  and provide the stored information as a result of “read” operation  106 . The information is stored even during a power-off state of device  100 . 
     “Read” operation  106 , which provides the stored information to one or more of the other circuits  102 , may occur during a transition from the power-off state to a power-on state for some parts of memory  110 . For other parts of memory  110 , “read” operation  106  may occur during the power-on state upon being addressed by another circuit (e.g. a controller). 
     As a result, different circuits of device  100  may receive data for their operation at different states of powering the device. For example, an oscillator circuit may be provided calibration data during the transition from the power-off state from one part of memory  110 , while a digital signal processor circuit may be provided programming data after the transition. 
     The information stored in memory  110  may include analog, digital or other types of data. For example, different parts of memory  110  may provide logic bits, ON/OFF states, latched outputs for trimming analog circuits, and the like. 
       FIG. 2A  is a block diagram of one type of memory comprising a homogeneous memory core and associated support circuitry. 
     Memory  210  may include memory core  212  for storing information and support circuitry  218  for operations associated with the memory core  212 . Operational component  202  may be one of the other circuits  102  of  FIG. 1  and be part of the same device with memory  210  or in a separate device. 
     Memory core  212  may be an ordinary NVM circuit that is arranged to store data (“1”), a logic or non-logic value, such as an ON/OFF state, in individual cells and provide the data upon being addressed. In one embodiment, memory core may be in an array form comprising cells that are addressable in terms of a row and a column. 
     In some embodiments, a value for the data may be encoded in an amount of charge stored in a device. In another embodiment, the data may be at least one logical bit, such as a 1 or a zero, stored in a cell. Of course, the data may need more than one cell, and so on. 
     As mentioned above, support circuitry  218  is for performing operations associated with memory core  212 . These operations may include, but are not limited to, providing supply voltage, providing programming voltage, selecting a cell for programming or reading, reading a cell, testing a cell, and the like. In addition, support circuitry  218  may cooperate with other components, such as operational component  202 . 
     Operational component  202  may be adapted to receive the data for processing, calibration, and the like. In  FIG. 2A , the data is input in operational component  202  directly. In other embodiments, the data may be routed through any suitable component before being input in operational component  202 . For example, the data may be first input from a cell into a binary output circuit. Then, from the binary output circuit, the data may be input in operational component  202 . 
     Memory  210  may be implemented with fewer or additional components such as communication circuitry for interaction with other devices. 
       FIG. 2B  is a block diagram of another type of memory comprising a hybrid memory core and associated support circuitry. 
     The memory core  262  of memory  250  includes first type memory  264  and second type memory  266 . First type memory  264  and second type memory  266  may include any type of memory circuits such as One Time Programmable (OTP), Multiple Times Programmable (MTP), transistor based memory circuits, fuse-based memory circuits, different formations of arrays, and the like. Each type may be used for a different purpose of operational component (e.g. operational components  252 - 1  and  252 - 2 ). 
     For example, first type memory  264  may provide a fast output for calibrating operational component  252 - 1  during a transition to the power-on state, while second type memory  266  may provide programming data to operational component  252 - 2  in the power-on state upon being addressed by support circuitry  268 . 
     Support circuitry  268  is adapted to interact with both types of memories. The interaction may include programming the memories, addressing individual cells to output their data, and the like. 
     By integrating first type memory  264  and second type memory  266 , and combining at least a portion of the support operations in a single support circuitry, size and power consumption can be optimized. 
       FIG. 3A  is a detailed block diagram of a hybrid memory including a One-Time Programmable (OTP) portion and example support circuits. 
     The memory core of memory  310  includes first type memory  314 , which is an OTP memory, second type memory  316 , and third type memory  317 . These memories are examples of different memory types as described in conjunction with previous figures. 
     Memory circuits commonly comprise a number of cells (e.g. cells  332 ,  334 , and  336 ), which store the data to be consumed by operational components. Memory circuits may be implemented in form of a memory array (e.g. an NVM array) comprising cells that are addressable in terms of a row and a column. First type memory  314  and second type memory  316  are examples of NVM arrays, while third type memory  317  illustrates a non-array NVM circuit. 
     In some embodiments (as illustrated, for example, in  FIG. 3B ), a non-volatile memory cell may be constructed using a floating-gate pFET readout transistor  340  having its source  342  tied to a power source  344  and its drain  346  providing a current  348 , which can be sensed to determine the state of the cell  340 . The gate  350  of the pFET readout transistor  340  provides for charge storage, which can be used to represent information such as binary bits. A control capacitor structure  352  having its first terminal  354  coupled to a first voltage source  356  and its second terminal  358  coupled to the floating gate  350  and a tunneling capacitor structure  360  having its first terminal  362  coupled to a second voltage source  364  and its second terminal  366  coupled to the floating gate  350  may be utilized in each embodiment. 
     The control capacitor structure  352  is fabricated so that it has much more capacitance than does the tunneling capacitor structure  360  (and assorted stray capacitance between the floating gate  350  and various other nodes of the cell  340 ). Manipulation of the voltages applied to the first voltage source  356  and second voltage source  364  controls an electric field across the capacitor structure and pFET dielectrics and thus Fowler-Nordheim tunneling of electrons onto and off of the floating gate, thus controlling the charge on the floating gate  350  and the information value stored thereon. 
     High voltage switches  322  and  324  are examples of a series of high voltage switches that are arranged to provide the first and the second voltages for programming and erasing of the memory cells. 
     NVM controller  326  is arranged to program and address individual cells of the memory circuits to output their data by managing high voltage switches  322 ,  324 , and the like. 
     Charge pump  328  is an electronic circuit that uses capacitors as energy storage elements to convert low voltages into higher voltage outputs. Charge pump circuits are typically capable of high efficiencies, sometimes as high as 90-95%. 
     Charge pump  328  may use switches to control a connection of voltages to the capacitor. For example, to generate a higher voltage, a first stage may involve the capacitor being connected across a voltage and charged up. In a second stage, the capacitor is disconnected from the original charging voltage and reconnected with its negative terminal to the original positive charging voltage. Because the capacitor retains the voltage across it (ignoring leakage effects) the positive terminal voltage is added to the original, effectively doubling the voltage. This higher voltage output may then be smoothed by the use of another capacitor. 
     The examples of  FIGS. 2A ,  2 B, and  3 A are for illustration purposes, and do not constitute a limitation on the present invention. Embodiments may be implemented in other memory circuits and other combinations of circuits for providing common support circuitry to a plurality of memory cells, without departing from the scope and spirit of the invention. For example, memory  310  may further include an oscillator, an ESD protection device, and the like. 
       FIG. 4  is a conceptual diagram for explaining the conventional order of a process for manufacturing, testing, and regularly programming for a memory circuit such as the memory of  FIG. 3 . 
     An OTP memory such as the OTP memory array  410  includes a number of OTP memory cells most of which, if not all, are unprogrammed during manufacturing  440 . Because the cells are OTP, a test step for confirming whether the cells are usable cannot include programming all cells. Such a test is destructive for this type of memory. 
     Thus, test step  450  typically includes programming (and reading) of sampled memories  452  from OTP memory array  410 . As a result of the test, a group of memories may fail the test ( 453 ) and another group pass (“succeeded”  455 ). While the “succeeded” group included usable memory cells at the beginning of the test, after the test step  450 , the memories in that group are wasted ( 457 ), because they cannot be used for other purposes any more. 
     In a typical manufacturing and testing environment for OTP memories, regular programming step  460  does not strictly follow the test step  450 , since the testing is done on a sampling of the manufactured memories and provides only an indication of how many memories may ultimately fail, but not which ones. 
     Hence, when all remaining memories are regularly programmed, a portion still fails ( 463 ) and another portion succeeds ( 465 ). The manufacturing loss includes not only the failed memories as a result of regular programming, but also all of the sampled memories used for testing. 
       FIG. 5A  is a detail for showing how a regular cell of an OTP memory can be controlled by a support circuit, as is a dedicated memory cell, whose purpose is to pretest the support circuitry according to embodiments. 
     As discussed before, support circuitry  578 -A supports both the regular OTP memory cell and the dedicated memory cell. Support circuitry  578 -A may include, but is not limited to, a High Voltage (HV) switch, a charge pump, a controller, a select switch, a voltage regulator, a current source, a sense amplifier, a High Voltage (HV) driver, a bias block, and an Error Correction Circuit (ECC). 
       FIG. 5B  is a detail for showing how a group of regular cells of an OTP memory, such as the cell of  FIG. 5A , here disposed along a line, for example, are controlled by a support circuit, as is a dedicated memory cell whose purpose is to pretest the support circuitry according to embodiments. 
     Memory devices typically include a plurality of memory cells, which may be configured in rows, columns, or arrays of rows and columns. In such cases, each group of regular OTP memory cells may be associated with one or more dedicated memory cell for testing the support circuitry. 
     In  FIG. 5B , the regular OTP memory cells are configured as a row of memory cells with the last cell being the dedicated memory cell for testing the support circuitry. 
     Support circuitry  578 -B is configured to support all of the regular OTP memory cells in the row as well as the dedicated memory cell. In addition to the above listed examples, support circuitry  578 -B may also be a row driver. 
       FIG. 5C  is a block diagram of an initially manufactured OTP memory according to embodiments, having regular only one time programmable (OTP) cells, associated support circuitry for controlling the regular (OTP) cells, and dedicated memory cells for pretesting the support circuitry. 
     Memory  510  of  FIG. 5C  includes a memory core  512  with an array of regular OTP memory cells  553 . The array also includes an extra row and an extra column of dedicated memory cells  554 . 
     Thus, the extra row and column of dedicated memory cells may be utilized in pretesting portions of the support circuitry  518  such as row drivers (each dedicated memory cell in the extra column), column multiplexers (each dedicated memory cell in the extra row), and the like. 
       FIG. 5D  is the block diagram of  FIG. 5C , after the support circuitry has been pretested by the dedicated memory cells. 
     Memory  510  of  FIG. 5D  illustrates the memory core after the pretesting process. During the testing of the support circuitry  518 , the dedicated memory cells in the extra column and row are programmed. If the dedicated memory cells are also OTP memory, they may not be used again. If they are MTP, they be reprogrammed for other purposes. 
     On the other hand, the regular OTP cells are not programmed during the pretest. Thus, the cells are still available for use despite the fact that 100% of the memories may have been tested. 
       FIG. 5E  is the block diagram of  FIG. 5D , after the regular only one time programmable cells have been further regularly programmed for supporting an operational component. 
     Memory  510  of  FIG. 5E  illustrates the memory core after the regular programming. Following the pretest, the memories that fail the test may be discarded. The memories that pass (“Usable”) the test are programmed for their regular purpose (shaded cells) and they can be used for providing data to operational component  502  as discussed in conjunction with earlier figures. 
     The invention also includes methods. Some are methods of determining whether portions of a memory are usable without programming the portions intended to store the information. Others are methods for pretesting support circuitry for a memory device in a memory manufacturing and testing system. 
     These methods can be implemented in any number of ways, including the structures described in this document. One such way is by machine operations, of devices of the type described in this document. 
     Another optional way is for one or more of the individual operations of the methods to be performed in conjunction with one or more human operators performing some. These human operators need not be collocated with each other, but each can be only with a machine that performs a portion of the program. 
     The invention additionally includes programs, and methods of operation of the programs. A program is generally defined as a group of steps or operations leading to a desired result, due to the nature of the elements in the steps and their sequence. A program is usually advantageously implemented as a sequence of steps or operations for a processor, such as the structures described above. 
     Performing the steps, instructions, or operations of a program requires manipulation of physical quantities. Usually, though not necessarily, these quantities may be transferred, combined, compared, and otherwise manipulated or processed according to the steps or instructions, and they may also be stored in a computer-readable medium. These quantities include, for example, electrical, magnetic, and electromagnetic charges or particles, states of matter, and in the more general case can include the states of any physical devices or elements. It is convenient at times, principally for reasons of common usage, to refer to information represented by the states of these quantities as bits, data bits, samples, values, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are associated with the appropriate physical quantities, and that these terms are merely convenient labels applied to these physical quantities, individually or in groups. 
     The invention furthermore includes storage media. Such media, individually or in combination with others, have stored thereon instructions of a program made to execute the methods according to the invention. A storage medium according to the invention is a computer-readable medium, such as a memory, and is read by a processor of the type mentioned above. If a memory, it can be implemented in a number of ways, such as Read Only Memory (ROM), Random Access Memory (RAM), and the like, some of which are volatile and some non-volatile. 
     Even though it is said that the program may be stored in a computer-readable medium, it should be clear to a person skilled in the art that it need not be a single memory, or even a single machine. Various portions, modules or features of it may reside in separate memories, or even separate machines. The separate machines may be connected directly, or through a network such as a local access network (LAN) or a global network such as the Internet. 
     Often, for the sake of convenience only, it is desirable to implement and describe a program as software. The software can be unitary, or thought in terms of various interconnected distinct software modules. 
     This detailed description is presented largely in terms of flowcharts, algorithms, and symbolic representations of operations on data bits on and/or within at least one medium that allows computational operations, such as a computer with memory. Indeed, such descriptions and representations are the type of convenient labels used by those skilled in programming and/or the data processing arts to effectively convey the substance of their work to others skilled in the art. A person skilled in the art of programming may use these descriptions to readily generate specific instructions for implementing a program according to the present invention. 
     Embodiments of support circuit pretesting system can be implemented as a combination of hardware and software. It is advantageous to consider such a system as subdivided into components or modules. A person skilled in the art will recognize that some of these components or modules can be implemented as hardware, some as software, some as firmware, and some as a combination. 
     Methods are now described more particularly according to embodiments. 
       FIG. 6A  is a flowchart for describing memory pretesting and programming processes according to embodiments. 
     Process  600  begins at optional operation  610 , where an OTP memory is manufactured. Manufacturing process is typically associated with testing of the manufactured memory to some degree. 
     According to a next optional operation  620 , dedicated memory cells within the manufactured memory are selected. The selection and subsequent testing utilizing these cells may be performed by a test device providing instructions to the manufactured memory or by a test program stored within the device enabling the memory to perform a self-test routine. 
     According to a next operation  630 , the support circuit is pretested by programming the dedicated memory cells only and not the regular memory cells. This way, OTP memories with good cells are not wasted during the test process. 
     According to a next decision operation  640 , a determination is made whether the pretesting was successful. If the pretest was indeed successful, the tested memory is designated as “Usable” in the next operation  650 . 
     According to a next optional operation  660 , the regular OTP cells of the “Usable” memory are programmed according to manufacturing specifications. 
     If the determination at decision operation  640  is that the pretest was not successful, the tested memory is designated as “Not-Usable” memory in the next operation  670 . 
     According to a next optional operation  680 , the “Not-Usable” designated memories may be discarded. 
       FIG. 6B  is a flowchart for describing a pretesting operation of  FIG. 6A  according to embodiments. 
     The pretesting operation  630  of  FIG. 6A  may include several sub-operations and begin with operation  632 , where the dedicated memory cells are programmed with test data. Test data may include a predefined pattern, a single bit value, and the like. 
     According to a next operation  634 , the programmed dedicated memory cells are read. In some embodiments, the fact that the programmed dedicated memory cells can be read alone may be an indication of successful pretesting of a portion of the support circuitry and the actual read value(s) may not matter. 
     According to a next optional operation  636 , the programmed value(s) of the dedicated memory cells is compared to the read value(s) or expected value(s). The comparison is then used to determine whether the pretest was successful or not. 
     According to a next optional operation, the unprogrammed regular OTP cells may also be read. Since they are known not to have been programmed, the regular OTP cells should not provide a programmed value in a read operation. If they do, the memory may be designated as “Not-Usable”. In practical implementations, this may indicate a short in the support lines which results in the regular cells also being programmed when the dedicated cells are programmed. 
     The operations included in processes  600  and  630  are for illustration purposes. Pretesting support circuitry using dedicated memory cells may be implemented by similar processes with fewer or additional steps, as well as in different order of operations using the principles described herein. 
       FIG. 7  is a conceptual diagram for showing situations arising from following the process of  FIG. 6A . 
     An example memory  710  during manufacturing  740  includes regular unprogrammed OTP memory cells and dedicated unprogrammed memory cells associated with groups of the regular OTP memory cells. 
     During the pretest step  750 , the dedicated memory cells of all or a sampled group of memories are programmed ( 752 ). As a result of the pretest step  750 , a portion of the memories may fail the test and designated “Unusable” ( 753 ). 
     Subsequently, any untested memories and the “Usable” memories ( 755 ) that successfully pass the pretest are regularly programmed during the regular programming step  760 . Thus, no memories are wasted in testing ( 757 ). 
     During the regular programming the regular OTP memory cells of all memories are programmed ( 762 ). Still, a portion of the memories may fail the regular programming ( 763 ) and be discarded, but their percentage is likely to be smaller due to the pretest step resulting in an increase in the successfully programmed memories  765  and no wasted memories in pretesting. 
       FIGS. 8A-8E  illustrate different dedicated test element configurations in which multiple regular cells and multiple dedicated cells can be arranged in an OTP memory array. 
     In  FIG. 8A , for each row of regular OTP memory cells  851  there is a dedicated memory test cell in column  852  for pretesting the support circuitry of each row. 
     In  FIG. 8B , for each row and column of regular OTP memory cells  853  there are dedicated memory test cells in column  854  and the last row of the array. Thus, the support circuitry of each row of regular memory cells may be pretested using the dedicated memory test cells of the last column and the support circuitry of each column of regular memory cells may be pretested using the dedicated memory test cells of the last row. 
       FIG. 8C  and  FIG. 8D  are examples of partial pretesting. In  FIG. 8C , dedicated memory test cells  858  are present for testing the support circuitry for only a portion of columns of regular memory cells  857 . Similarly, in  FIG. 8D , only the support circuitry for a portion of regular memory cell rows  859  may be tested by the dedicated memory test cells  860  in the last column. 
     Finally,  FIG. 8E  illustrates that using dedicated memory test cells  856  for pretesting support circuitry is not limited to row or column formats of the dedicated cells. Indeed, the dedicated memory test cells may be selected in any order including random order throughout the memory cell array  855 . 
       FIG. 9  illustrates dedicated test elements in a multiple array OTP memory configuration. 
     The multi-array memory device  970  of  FIG. 9  includes row logic  972  for providing support operations for the arrays and column logic  976  for providing support operations for the columns of the arrays. The column logic may be multiplexed using column multiplexer  974 . 
     According to some embodiments, each of the arrays may include a row (an extra row) of dedicated memory test cells for pretesting the column logic  976 , while the row logic  972  shared by all arrays may be pretested by a single extra column of dedicated memory test cells ( 971 ) in the last array. 
     Other configurations of multi-array memory devices in light of the different configurations shown in  FIGS. 8A-8E  may also be implemented according to embodiments. 
     In this description, numerous details have been set forth in order to provide a thorough understanding. In other instances, well-known features have not been described in detail in order to not obscure unnecessarily the description. 
     A person skilled in the art will be able to practice the embodiments in view of this description, which is to be taken as a whole. The specific embodiments as disclosed and illustrated herein are not to be considered in a limiting sense. Indeed, it should be readily apparent to those skilled in the art that what is described herein may be modified in numerous ways. Such ways can include equivalents to what is described herein. 
     The following claims define certain combinations and sub-combinations of elements, features, steps, and/or functions, which are regarded as novel and non-obvious. Additional claims for other combinations and sub-combinations may be presented in this or a related document.