Patent Publication Number: US-8543752-B2

Title: Peripheral component interconnect express interface card with a switch

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates to interface cards, and particular, to a Peripheral Component Interconnect Express (PCIE) interface card. 
     2. Description of Related Art 
     PCIE is a high-speed I/O bus, and can be used in mobile devices, desktop computers, and servers. A common PCIE interface card is a PCIE interface video card, a PCIE interface network card, or a PCIE interface sound card. 
     However, because a PCIE interface card is only limited to having a single function, such as a video card function, a network card function, or a sound card function, and because one PCIE interface card occupies a slot on a motherboard, many PCIE interface cards occupy much space in a computer. Additionally, there must be many slots on the motherboard to electrically connect a CPU of the motherboard to the PCIE interface cards. Thus, manufacture of the motherboard is complicated. 
     Therefore, what is needed is a new PCIE interface card that can overcome the described limitations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a PCIE interface card according to a first embodiment. 
         FIG. 2  is a block diagram of a PCIE switch of a PCIE interface card according to a second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments will now be described in detail with reference to drawings. 
     In general, the word “module”, as used herein, refers to logic embodied in hardware or firmware, or to a collection of software instructions, written in a programming language, such as, Java, C, or assembly. One or more software instructions in the modules may be embedded in firmware, such as in an EPROM. The modules described herein may be implemented as either software and/or hardware modules and may be stored in any type of non-transitory computer-readable medium or other storage device. Some non-limiting examples of non-transitory computer-readable media include CDs, DVDs, BLU-RAY, flash memory, and hard disk drives. 
     Referring to  FIG. 1 , a PCIE interface card  100 , in accordance with an exemplary embodiment, is electrically coupled to a CPU  200 . 
     The PCIE interface card  100  includes a circuit board  10  having a plurality of golden fingers  20  extending from the circuit board  10  and electrically coupled to the CPU  200 . A first PCIE interface module  30  is positioned on the circuit board  10 , and a PCIE switch  50  is arranged on the circuit board  10  and electrically coupled to the golden fingers  20  and the first PCIE module  30 . A second PCIE interface module  70  is arranged on the circuit board  10  and electrically coupled to the PCIE switch  50 . 
     In the present embodiment, the first PCIE interface module  30  is a video card module, and includes an image processing module  303 . The first PCIE interface module  30  receives a data packet based on a PCIE protocol from the CPU  200 , and transmits the data packet to the image processing module  303 . The image processing module  303  is a microprocessor for performing image processing based on an image processing command in the data packet from the CPU  200 . In other embodiments, the first PCIE interface module  30  may be a network card module, a sound card module, for example. 
     The PCIE switch  50  transmits data from the CPU  200  to the first PCIE interface module  30  and exchanges data between the CPU  200  and the second PCIE interface  70 . In the present embodiment, the PCIE switch  50  includes a receiving module  501  and a transmitting module  503 . 
     The receiving module  501  receives a data packet from the CPU  200 , and transmits the data packet to the first PCIE interface module  30  and the second PCIE interface module  70 . The receiving module  501  includes a copy module  505  and a transmitting module  507  electrically coupled to the copy module  505 . 
     The copy module  505  makes two copies of the data packet, and transmits the two copied data packets to the transmitting module  507 . 
     The transmitting module  507  receives the two copied data packets, and transmits the two copied data packets to the first PCIE interface module  30  and the second PCIE interface module  70 , respectively. 
     After the first PCIE interface module  30  and the second PCIE interface module  70  receives the two copied data packets, the first PCIE interface module  30  and the second PCIE interface module  70  analyze the two copied data packets, respectively. If the copied data packet is the data packet for the first PCIE interface module  30  or the data pack for the second PCIE interface module  70 , the first PCIE interface module  30  or the second PCIE interface module  70  will retain the copied data packet and perform the corresponding operation based on a command in the copied data packet. If the copied data packet is not the data packet for the first PCIE interface module  30  or the data packet for the second PCIE interface module  70 , the first PCIE interface module  30  or the second PCIE interface module  70  will abandon the copied data packet, and wait for a next copied data packet. 
     The transmitting module  503  transmits a data packet from the second PCIE interface module  70  to the CPU  200  via the golden finger  20 . The transmitting module  503  includes a buffer module  509 . The buffer module  509  temporarily stores a plurality of data packets from the second PCIE interface module  70 , such that the CPU  200  gathers one data packet at a time. 
     In the present embodiment, the second PCIE interface module  70  is a solid state hard disk module, and includes a first control module  702 , a second control module  703 , a reading module  704  electrically coupled to the first control module  702 , a writing module  705  electrically coupled to the second control module  702 , and a solid state storage module  706  electrically coupled to the reading module  704  and the writing module  705 . 
     The second PCIE interface module  70  transmits a data packet based on the PCIE protocol from the solid state storage module  706  to the buffer module  509 , and receives a data packet based on the PCIE protocol from the CPU  200  via the PCIE switch  50 . 
     The first control module  702  analyzes a data packet from the transmitting module  507 , gains a data reading command, and transmits the data reading command to the reading module  704 . In addition, package the data read by the reading module  704  into a data packet based on the PCIE protocol, and then transmits the packaged data packet to the buffer module  509 . 
     The second control module  703  analyzes a data packet from the transmitting module  507 , gains a data writing command and a storable data, and transmits the data writing command and the storable data to the writing module  705 . 
     The reading module  704  performs the data reading command from the first control module  702 , reads data from the solid state storage module  706 , and transmits the read data to the first control module  702 . 
     The writing module  705  performs the data writing command from the second control module  703 , and writes the storable data into the solid state storage module  706 . 
     In alternative embodiments, the second PCIE interface module  70  may be a PCIE interface network card module, or a PCIE interface sound card module. In further alternative embodiments, except the first PCIE interface module  30  and the second PCIE interface module  70  on the circuit board  10 , a PCIE interface sound card module electrically coupled to the PCIE switch  50 , a PCIE interface network card module electrically coupled to the PCIE switch  50 , a PCIE interface solid state hard disk module electrically coupled to the PCIE switch  50 , or more PCIE interface modules electrically coupled to the PCIE switch  50  may be arranged on the circuit board  10 . 
     In still further embodiments, the first PCIE interface module  30  may be a solid state hard disk module. In such case, the PCIE switch  70  is configured for exchanging data between the CPU  200  and the first PCIE interface module  30  and exchanging data between the CPU  200  and the second PCIE interface  70 . 
     In the present embodiment, because the first interface module  30  and the second interface module  70  are arranged on the circuit board  10  of the PCIE interface card  100 , the CPU  200  can be electrically coupled to two PCIE interface modules with different functions via one PCIE interface card  100 . Accordingly, a space occupied by the first PCIE interface module  30  and the second PCIE interface module  70  in a computer can be reduced, and the volume of the computer can be reduced. In addition, compared to the two PCIE interface modules with different functions on two PCIE interface cards, respectively, the number of the PCIE interface card  100  can be reduced, and the number of slots on a motherboard can be reduced. The manufacturing of the motherboard can thus be simplified 
     Referring to  FIG. 2 , a PCIE switch  90  of a PCIE interface card, in accordance with a second embodiment, includes a data table  91 . The data table  91  includes two preset data packet headers and two preset PCIE interface modules corresponding to the preset data packet headers, respectively. In other embodiments, there may be three, four, or more preset data packet headers and three, four, or more preset PCIE interface modules corresponding to the preset data packet headers, respectively, in data table  91 . 
     For clearly showing the data table  91 , a table  1  is given. Understandably, the data in the table  1  can be changed by the user based on need. 
     
       
         
           
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
             
            
               
                 data packet header 
                 01000111 00000111 
                 01111000 11111100 
               
               
                 PCIE interface module 
                 first PCIE interface 
                 second PCIE interface 
               
               
                   
                 module 
                 module 
               
               
                   
               
            
           
         
       
     
     A receiving module  901  of the PCIE switch  90  includes a determination module  903  and a transmitting module  905  electrically coupled to the determination module  903 . 
     The determination module  903  is configured for receiving a data packet from the CPU  200  via the golden finger  20 , and finding a PCIE interface module corresponds to a data packet header of the data packet in the table 1. 
     The transmitting module  905  is configured for transmitting the data packet to the corresponding PCIE interface module based on a finding result from the determination module  903 . 
     In the present embodiment, when a data packet header of the data packet received by the determination module  903  is “01000111 00000111”, the transmitting module  905  will transmit the data packet with the data packet header “01000111 00000111” to the first PCIE interface module  30 . When a data packet header of the data packet received by the determination module  903  is “01111000 11111100”, the transmitting module  906  will transmit the data packet with the data packet header “01111000 11111100” to the second PCIE interface module  70   
     While certain embodiments have been described and exemplified above, various other embodiments will be apparent from the foregoing disclosure to those skilled in the art. The disclosure is not limited to the particular embodiments described and exemplified but is capable of considerable variation and modification without departure from the scope and spirit of the appended claims.