Patent Publication Number: US-10771046-B2

Title: Comparator and oscillator circuit using said comparator

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Continuation application of PCT Application No. PCT/JP2018/040507, filed Oct. 31, 2018 and based upon and claiming the benefit of priority from Japanese Patent Application No. 2017-240723, filed Dec. 15, 2017, the entire contents of all of which are incorporated herein by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates to a comparator and to an oscillator circuit using the comparator. 
     BACKGROUND ART 
     Semiconductor integrated circuits include an oscillator circuit configured to output a clock signal with a constant frequency for in-circuit time setting. One example of such an oscillator circuit includes an oscillator circuit using a comparator. 
     Comparators are one of the elements, and Patent Document 1 describes a comparator as one example. 
     Some oscillator circuits using a comparator include external resistor and capacitor connecting to one of the input terminals of the comparator, and change a reference voltage input to the other input terminal of the comparator depending on the output of the comparator. Such an oscillator circuit has an oscillatory frequency that is determined by the resistance value and the capacitance value of the external resistor and capacitor, and by the reference voltage. 
       FIG. 27  illustrates a conventional oscillator circuit using a comparator. An oscillator circuit  1  includes: a power-supply terminal VDD to receive an external power-supply voltage; an input terminal CG connecting to external resistor R 0  and capacitor C 0  to determine the oscillatory frequency; and a ground terminal GND connecting to the ground level. In this drawing, VDD indicates the power-supply voltage as well. The input terminal CG also functions as the input terminal to receive an external control signal to control the comparator and thus the oscillator circuit. 
     The oscillator circuit  1  also includes a comparator having a differential unit  2  and a gain unit  3  each connecting to the power-supply terminal VDD and the ground terminal GND, and a transistor (P-type MOSFET) P 5  connecting to the power-supply terminal VDD and the ground terminal GND. The drain of the transistor P 5  connects to a constant current source to flow a constant current “ibias”. 
     The differential unit  2  includes transistors (P-type MOSFETs) P 2  to P 4  and transistors (N-type MOSFETs) N 3  and N 4 . The drain of the transistor P 5  connects to the gate of this transistor and to the gate of the transistor P 2 . The sources of the transistors P 5  and P 2  connect to the power-supply terminal VDD. The transistors P 5  and P 2  make up a current mirror circuit, and the transistor P 2  serves as a constant current source that supplies a bias current to the differential unit  2 , where the constant current “ibias” flowing through the transistor P 5  is the reference current of the bias current (i.e., the bias current is proportional to the constant current “ibias”). 
     The drain of the transistor P 2  connects to the sources of the transistors P 3  and P 4  that make up a differential pair. The gates of the transistors P 3  and P 4  are the input of the differential unit  2 . The gate of the transistor P 3  receives the electric potential at the connecting point of the resistor R 0  and the capacitor C 0 , or a control signal via the input terminal CG. The gate of the transistor P 4  receives a reference voltage to be compared with the electric potential at the connecting point of the resistor R 0  and the capacitor C 0  or with the control signal input from an external circuit. The drain of the transistor P 3  connects to the drain of the transistor N 3 . The drain of the transistor P 4  connects to the drain and the gate of the transistor N 4  and to the gate of the transistor N 3 . The sources of the transistors N 3  and N 4  connect to the ground terminal GND. The transistors N 3  and N 4  make up a current mirror circuit, and serve as an active load of the differential unit  2 . The drain of the transistor P 3  and the drain of the transistor N 3  are the output of the differential unit  2 . 
     The gain unit  3  includes a transistor (P-type MOSFET) P 1  and a transistor (N-type MOSFET) N 2  as an amplifier. A constant current flows through the transistor P 1 , and the constant current “ibias” is the reference current of this constant current (i.e., this constant current is proportional to the constant current “ibias”). The source of the transistor P 1  connects to the power-supply terminal VDD, and the gate of this transistor connects to the drain of the transistor P 5  and to the gate of the transistor P 5 . The transistors P 5  and P 1  make up a current mirror circuit. The drain and the source of the transistor N 2  connect to the drain of the transistor P 1  and the ground terminal GND, respectively. The gate of the transistor N 2  receives the output of the differential unit  2 . The connecting point of the drain of the transistor P 1  and the drain of the transistor N 2  is the output of the gain unit  3 . 
     The oscillator circuit  1  also includes: a voltage-dividing circuit having resistors R 2  to R 6  that are serially connected in sequence between the power-supply terminal VDD and the ground terminal GND; and switches (N-type MOSFETs) N 5  and N 6 . This voltage-dividing circuit yields a first reference voltage V 1  that is a voltage at the connecting point between the resistor R 3  and the resistor R 4 , and a second reference voltage V 2  that is a voltage at the connecting point between the resistor R 4  and the resistor R 5 . The second reference voltage V 2  is lower than the first reference voltage. The first reference voltage V 1  is input to the gate of the transistor P 4  via the switch N 5 . The second reference voltage V 2  is input to the gate of the transistor P 4  via the switch N 6  that operates in the opposite phase of the switch N 5 . 
     The comparator includes inverters INV 1  and INV 2  in addition to the differential unit  2  and the gain unit  3 . The output of the gain unit  3  is input to the inverter INV 2 . The output of this inverter INV 2  is input to the inverter INV 1  and to the gate of the switch N 5 . The output of this inverter INV 1  connects to the gate of the switch N 6 . The output of the inverter INV 1  is the output of the comparator. 
     The oscillator circuit  1  also includes a discharge circuit to discharge the capacitor C 0 . The discharge circuit includes: a resistor R 1  and a transistor (N-type MOSFET) N 1  serially connected between the input terminal CG and the ground terminal GND. The gate of the transistor N 1  receives the output of the comparator. A D-type flip-flop circuit D-FF frequency-divides the comparator output so that the resultant frequency is ½ and the resultant duty ratio is 50%, and the output after such frequency-dividing is the clock output (the output of the oscillator circuit  1 ). 
     For typical operation of such an oscillator circuit  1 , the oscillator circuit includes a resistor R 0  externally connecting to the input terminal CG and the power-supply terminal VDD. The oscillator circuit also includes a capacitor C 0  externally connecting to the input terminal CG and the ground terminal GND. In this case, charge-discharge of the capacitor C 0  yields a control signal to be input to the input terminal CG. 
     In one example, let the power-supply voltage be 5 V, and the reference potential of the oscillator circuit  1  be at the ground level, i.e., 0 V. The resistors R 2  to R 6  have the same resistance values. This means that the first reference voltage V 1  is 3 V, and the second reference voltage V 2  is 2 V. All logical threshold voltages for the inverter INV 1 , the inverter INV 2 , and the D-type flip-flop circuit D-FF are ½×VDD. The resistance value of the resistor R 1  is sufficiently smaller than the resistance value of the resistor R 0 . The resistance value of the resistor R 0  and the capacitance value of the capacitor C 0  are set so that the oscillatory frequency of the comparator output is about 200 kHz, i.e., the frequency of the clock output is about 100 kHz. The gate threshold voltage of the transistor N 2  is set at 0.7 V. 
       FIGS. 28( a )-28( e )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1  during typical operation. The horizontal axis in this drawing indicates time (μs). The vertical axis indicates CG voltage (V) that is the voltage at the input terminal CG in  FIG. 28( a ) , output voltage of the differential unit (V) in  FIG. 28( b ) , output voltage of the gain unit (V) in  FIG. 28( c ) , comparator output voltage (V) in  FIG. 28( d ) , and clock output voltage (V) in  FIG. 28( e ) . 
     When the comparator output voltage is at a low level (0 V), the output of the inverter INV 1  is at a low level and the output of the inverter INV 2  is at a high level. This turns the switch N 5  on and the switch N 6  off. The reference voltage input to the differential unit  2  therefore is the first reference voltage V 1 , i.e., 3 V. The transistor N 1  also turns off. This charges the capacitor C 0  with a charge current I c  illustrated in  FIG. 27 , so that the CG voltage increases from 2 V to 3 V. At this time, the output voltage of the differential unit is at a high level. The transistor N 2  in the gain unit  3  therefore turns on, and the output voltage of the gain unit is at a low level (0 V). 
     When the CG voltage exceeds the first reference voltage V 1 , i.e., 3 V, the current flowing through the transistor P 4  exceeds the current flowing through the transistor P 3 , so that the gate voltage of the transistors N 3  and N 4  increases. The output voltage of the differential unit gradually decreases while discharging the Miller capacitance between the gate and the drain of the transistor N 2  and the gate capacitance of this transistor via the current flowing through the transistor N 3 . 
     Note here that the capacitance (parasitic capacitance) between the gate and the drain of the transistor N 2  acts while having the magnitude multiplied by the voltage amplification factor of the transistor (strictly multiplied by (the voltage amplification factor+1)). This phenomenon is called the Miller effect. The value obtained by multiplying the capacitance between the gate and the drain by the voltage amplification factor of the transistor is called the Miller capacitance between the gate and the drain. 
     When the output voltage of the differential unit falls below the gate threshold voltage of the transistor N 2 , then the transistor N 2  turns off. The output voltage of the gain unit then gradually increases while charging the Miller capacitance between the gate and the drain of the transistor N 2  via the constant current from the transistor P 1 . 
     When the output voltage of the gain unit reaches the logical threshold voltage of the inverter INV 2 , then the output voltage of the inverter INV 2  changes to a low level. The output voltage of the inverter INV 1 , i.e., the comparator output voltage changes to a high level (5 V). This turns the switch N 5  off and the switch N 6  on. The reference voltage input to the differential unit  2  therefore is the second reference voltage V 2 , i.e., 2 V. Turning on the transistor N 1  discharges the capacitor C 0 . That is, as illustrated in  FIG. 27 , a discharge current I d  flows from the capacitor C 0  to the ground terminal GND via the input terminal CG, the resistor R 1 , and the transistor N 1 . This lowers the CG voltage. 
     When the CG voltage falls below the second reference voltage V 2 , i.e., 2 V, the current flowing through the transistor P 3  exceeds the current flowing through the transistor P 4  and the current flowing through the transistor P 4  decreases, so that the gate voltage of the transistors N 3  and N 4  decreases. The output voltage of the differential unit changes to a high level. The transistor N 2  therefore turns on, and the output voltage of the gain unit changes to a low level (0 V). The output voltage of the inverter INV 2  change to a high level, and the output voltage of the inverter INV 1 , i.e., the comparator output voltage changes to a low level (0 V). This turns the switch N 5  on and the switch N 6  off. The reference voltage input to the differential unit  2  therefore is the first reference voltage V 1 , i.e., 3 V. The transistor N 1  also turns off. This charges the capacitor C 0  with the charge current I c , so that the CG voltage increases. 
     Such an operation is repeated, so that the comparator output has the rectangular waveforms having the frequency determined by the resistance value of the resistor R 0 , the capacitance value of the capacitor C 0 , the first reference voltage V 1  and the second reference voltage V 2  ( FIG. 28( d ) ). The D-type flip-flop circuit D-FF frequency-divides the comparator output so that the resultant frequency is ½ and the resultant duty ratio is 50%, and the output after such frequency-dividing is the clock output ( FIG. 28( e ) ). 
       FIG. 29  illustrates the configuration to conduct an inspection before shipment of a semiconductor integrated circuit including a digital circuit operating with the clock output of the oscillator circuit  1 . In  FIG. 29 , like reference numerals indicate like parts in  FIG. 27 , and their detailed descriptions are omitted. To conduct the inspection before shipment, a rectangular-wave generation circuit  9  is externally connected to the input terminal CG, instead of the resistor R 0  and the capacitor C 0 . This rectangular-wave generation circuit  9  is to input a rectangular-wave control signal to the input terminal CG, the rectangular-wave control signal having a frequency higher than the oscillatory frequency determined by the resistance value of the resistor R 0  and the capacitance value of the capacitor C 0 . Such inputting of a control signal with a relatively high frequency is to overclock the clock output of the oscillator circuit  1  and to shorten the time required for the inspection before shipment of the semiconductor integrated circuit. 
       FIGS. 30( a )-30( e )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1  when the rectangular-wave control signal by the rectangular-wave generation circuit  9  is input to the input terminal CG. As illustrated in  FIG. 30( a )  in the drawing, the rectangular waves have the amplitude between 0 V and 5 V, and have the frequency of 2 MHz. That is, the period of the rectangular waves is 500 ns. 
     When the CG voltage rises from a low level (0 V) to a high level (5 V), then the output voltage of the differential unit gradually decreases while discharging the Miller capacitance between the gate and the drain of the transistor N 2  and the gate capacitance of this transistor via the current flowing through the transistor N 3 . In  FIG. 30( b ) , “K 51 ” denotes this. 
     When the output voltage of the differential unit falls below the gate threshold voltage of the transistor N 2 , then the transistor N 2  turns off. The output voltage of the gain unit then gradually increases while charging the Miller capacitance between the gate and the drain of the transistor N 2  via the constant current from the transistor P 1 . In  FIG. 30( c ) , “K 52 ” denotes this. 
     In this way, rising of the CG voltage decreases the output voltage of the differential unit and increases the output voltage of the gain unit. The CG voltage, however, falls before the output voltage of the gain unit reaches the logical threshold voltage (2.5 V) of the inverter INV 2 . Falling of the CG voltage decreases the output voltage of the gain unit as well, so that the output voltage of the gain unit finally changes to a low level. 
     That is, the output voltage of the gain unit does not reach the logical threshold voltage (2.5 V) of the inverter INV 2  through the entire period. The comparator output voltage therefore is fixed to a low level (0 V) through the entire period, and so the oscillation does not occur. The clock output voltage therefore is fixed to a high level (5 V) (in the case of  FIG. 30( e ) ) or to a low level (0 V) through the entire period, and so the oscillation does not occur. 
     In this way, the comparator output voltage fails to follow the rectangular-wave control signal with 2 MHz from the rectangular-wave generation circuit  9 , i.e., overclocking to 2 MHz fails. 
     REFERENCE DOCUMENT LIST 
     Patent Document 
     Patent Document 1: JP 2001-267893 A 
     SUMMARY 
     The present inventor found that such a failure of the comparator output to follow a relatively high-frequency control signal that is input externally results from the time required to charge and discharge the Miller capacitance between the gate and the drain of a MOSFET as an amplifier in the gain unit of the comparator and the gate capacitance of such a MOSFET. 
     The present invention aims to provide an oscillator circuit using a comparator, the oscillator circuit controlling charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and enabling the comparator output to follow a relatively high-frequency control signal that is input externally. 
     To achieve the object, a comparator according to one aspect of the present invention has a differential unit and a gain unit. The comparator includes: a charge-discharge control unit configured to connect to the output of the differential unit and configured to control charge-discharge of Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and gate capacitance of the MOSFET; and an output control unit configured to control the output of the gain unit. A signal generated at an external terminal of the comparator is input to one of the inputs of the differential unit. The output control unit includes: a first inverter configured to receive a signal generated at the external terminal as an input; a first logic circuit configured to receive the output of the first inverter and the output of the gain unit as an input; a first transistor having a drain configured to connect to the output of the gain unit, a source configured to connect to a reference potential of the comparator, and a gate configured to connect to the output of the first logic circuit; and a first capacitor configured to connect to the input and the output of the first logic circuit. 
     The first logic circuit may include: a second inverter configured to receive the output of the first inverter as an input; and a first negative OR circuit configured to receive the output of the second inverter and the output of the gain unit as an input. The output of the first negative OR circuit may be the output of the first logic circuit. 
     The charge-discharge control unit may include: a third inverter configured to receive a signal generated at the external terminal as an input; a second logic circuit configured to receive the output of the differential unit and the output of the third inverter as an input; a second transistor having a gate configured to connect to the output of the second logic circuit, a source configured to connect to a power-supply voltage of the comparator, and a drain configured to connect to the drain of the MOSFET; and a second capacitor configured to connect to two inputs of the second logic circuit. 
     The second logic circuit may include: a second negative OR circuit configured to receive the output of the differential unit and the output of the third inverter as an input; and a fourth inverter configured to receive the output of the second negative OR circuit as an input. The output of the fourth inverter may be the output of the second logic circuit. 
     The charge-discharge control unit may include a third transistor having a drain configured to connect to the gate of the MOSFET, a source configured to connect to the reference potential of the comparator, and a gate configured to connect to the output of the second negative OR circuit. 
     The signal generated at the external terminal may be a signal generated based on the output of the gain unit or a signal externally input to the external terminal of the comparator. 
     An oscillator circuit according to one aspect of the present invention uses the comparator as stated above. The oscillator circuit includes: a third capacitor configured to connect between one of the inputs of the differential unit and the reference potential of the comparator; a current-supply element configured to connect between the power-supply voltage of the comparator and the one of the inputs of the differential unit; and a discharge circuit configured to discharge the third capacitor according to the output of the comparator. A reference voltage is input to the other input of the differential unit. 
     The current-supply element may be a resistor or a constant current circuit. 
     A value of the reference voltage may be switched based on the output of the comparator. 
     The present invention provides a comparator and an oscillator circuit using the comparator, the oscillator circuit controlling charge-discharge of the Miller capacitance between the gate and the drain of a MOSFET serving as an amplifier of the gain unit and the gate capacitance of the MOSFET, and so enabling the comparator output to follow a relatively high-frequency control signal that is input externally. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  describes an oscillator circuit (receiving 2 MHz control signal) according to one embodiment of the present invention. 
         FIGS. 2( a )-2( f )  are timing charts illustrating the operation of the oscillator circuit (receiving 2 MHz control signal) according to one embodiment of the present invention. 
         FIGS. 3( a )-3( f )  are timing charts illustrating the operation of the oscillator circuit (receiving 5 MHz control signal) according to one embodiment of the present invention. 
         FIG. 4  describes an oscillator circuit (including externally connected CR) according to one embodiment of the present invention. 
         FIGS. 5( a )-5( f )  are timing charts illustrating the operation of the oscillator circuit (including externally connected CR) according to one embodiment of the present invention. 
         FIG. 6  describes an oscillator circuit (receiving 2 MHz control signal) according to a second embodiment of the present invention. 
         FIGS. 7( a )-7( f )  are timing charts illustrating the operation of the oscillator circuit (receiving 2 MHz control signal) according to the second embodiment of the present invention. 
         FIGS. 8( a )-8( f )  are timing charts illustrating the operation of the oscillator circuit (receiving 10 MHz control signal) according to the second embodiment of the present invention. 
         FIGS. 9( a )-9( f )  are timing charts illustrating the operation of the oscillator circuit (receiving 20 MHz control signal) according to the second embodiment of the present invention. 
         FIG. 10  describes an oscillator circuit (including externally connected CR) according to the second embodiment of the present invention. 
         FIGS. 11( a )-11( f )  are timing charts illustrating the operation of the oscillator circuit (including externally connected CR) according to the second embodiment of the present invention. 
         FIG. 12  describes an oscillator circuit (receiving 10 MHz control signal) according to a third embodiment of the present invention. 
         FIGS. 13( a )-13( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 10 MHz control signal) according to the third embodiment of the present invention. 
         FIGS. 14( a )-14( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 17 MHz control signal) according to the third embodiment of the present invention. 
         FIG. 15  describes an oscillator circuit (including externally connected CR) according to the third embodiment of the present invention. 
         FIGS. 16( a )-16( g )  are timing charts illustrating the operation of the oscillator circuit (including externally connected CR) according to the third embodiment of the present invention. 
         FIG. 17  describes an oscillator circuit (receiving a rectangular-wave control signal) according to a fourth embodiment of the present invention. 
         FIGS. 18( a )-18( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 2 MHz control signal with an amplitude between 0 V and 5 V) according to the fourth embodiment of the present invention. 
         FIGS. 19( a )-19( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 50 MHz control signal with an amplitude between 0 V and 5 V) according to the fourth embodiment of the present invention. 
         FIGS. 20( a )-20( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 50 MHz control signal with an amplitude between 1.5 V and 3.5 V) according to the fourth embodiment of the present invention. 
         FIGS. 21( a )-21( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 50 MHz control signal with an amplitude between 0 V and 2.7 V) according to the fourth embodiment of the present invention. 
         FIGS. 22( a )-22( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 50 MHz control signal with an amplitude between 2.3 V and 5 V) according to the fourth embodiment of the present invention. 
         FIGS. 23( a )-23( g )  are timing charts illustrating the operation of the oscillator circuit (receiving 50 MHz control signal with an amplitude between 2.3 V and 2.7 V) according to the fourth embodiment of the present invention. 
         FIG. 24  describes the relationship between the rectangular-wave control signal voltage and the reference voltage, and the outputs of the negative OR circuit and the gain unit. 
         FIG. 25  describes an oscillator circuit (including externally connected CR) according to the fourth embodiment of the present invention. 
         FIGS. 26( a )-26( g )  are timing charts illustrating the operation of the oscillator circuit (including externally connected CR) according to the fourth embodiment of the present invention. 
         FIG. 27  describes a conventional oscillator circuit (including externally connected CR). 
         FIGS. 28( a )-28( e )  are timing charts illustrating the operation of the conventional oscillator circuit (including externally connected CR). 
         FIG. 29  describes a conventional oscillator circuit (receiving 2 MHz control signal). 
         FIGS. 30( a )-30( e )  are timing charts illustrating the operation of the conventional oscillator circuit (receiving 2 MHz control signal). 
     
    
    
     EMBODIMENTS 
     The following describes some embodiments of the present invention. The present invention is not limited to the following embodiments. 
     First Embodiment 
       FIG. 1  illustrates an oscillator circuit  1   a  and a rectangular-wave generation circuit  9  externally connected to the oscillator circuit, as a first embodiment of the present invention. In  FIG. 1 , like reference numerals indicate like parts in  FIG. 29 , and their detailed descriptions are omitted. The oscillator circuit  1   a  includes a charge-discharge control unit  4  in addition to the conventional configuration, and the charge-discharge control unit  4  is configured to control charge-discharge of the Miller capacitance between the gate and the drain of the transistor N 2  and the gate capacitance of this transistor. The charge-discharge control unit  4  includes an inverter INV 3 , a negative OR circuit NOR 1 , a transistor (N-type MOSFET) N 7 , an inverter INV 4 , and a transistor (P-type MOSFET) P 6 . 
     The input of the inverter INV 3  connects to the input terminal CG. That is, the inverter INV 3  receives a rectangular-wave control signal from the rectangular-wave generation circuit  9 . The output of this inverter INV 3  is sent to one of the inputs of the negative OR circuit NOR 1 . The output of the negative OR circuit NOR 1  connects to the gate of the transistor N 7 . The source of the transistor N 7  connects to the ground terminal GND. 
     The output of the differential unit  2  (connecting point between the drain of the transistor P 3  and the drain of the transistor N 3 ) connects not only to the gate of the transistor N 2  but also to the other input of the negative OR circuit NOR 1  and the drain of the transistor N 7 . That is, the drain of the transistor N 7  connects to the gate of the transistor N 2 . 
     The output of the negative OR circuit NOR 1  connects to the input of the inverter INV 4  as well. The output of the inverter INV 4  connects to the gate of the transistor P 6 . The source of the transistor P 6  connects to the power-supply terminal VDD, and the drain of the transistor P 6  connects to the output of the gain unit (connecting point between the drain of the transistor P 1  and the drain of the transistor N 2 ). 
     In one example, let the power-supply voltage VDD be 5 V, and the reference potential of the oscillator circuit  1   a  be at the ground level, i.e., 0 V. The resistors R 2  to R 6  have the same resistance values. This means that the first reference voltage V 1  input to the comparator is 3 V, and the second reference voltage V 2  is 2 V. All logical threshold voltages for the inverters INV 1  to INV 4 , the negative OR circuit NOR 1 , and the D-type flip-flop circuit D-FF are ½×VDD. The gate threshold voltage of the transistor N 2  is 0.7 V. 
       FIGS. 2( a )-2( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   a  when the rectangular-wave control signal by the rectangular-wave generation circuit  9  is input to the input terminal CG. The horizontal axis in this drawing indicates time (μs). The vertical axis indicates CG voltage (V) that is the voltage at the input terminal CG in  FIG. 2( a ) , output voltage of the differential unit (V) in  FIG. 2( b ) , output voltage of the negative OR circuit NOR 1  (V) in  FIG. 2( c ) , output voltage of the gain unit (V) in  FIG. 2( d ) , comparator output voltage (V) in  FIG. 2( e ) , and clock output voltage (V) in  FIG. 2( f ) . 
     As illustrated in  FIG. 2( a )  in the drawing, the rectangular-wave control signal has the amplitude between 0 V and 5 V, and has the frequency of 2 MHz. That is, the period of the rectangular-wave control signal is 500 ns. 
     When the CG voltage changes from a low level (0 V) to a high level (5 V), the output of the inverter INV 3 , which is one of the inputs of the negative OR circuit NOR 1 , changes to a low level. Subsequently, since the gate voltage of the transistor P 3  is at a high level, the output voltage of the differential unit gradually decreases while discharging the Miller capacitance between the gate and the drain of the transistor N 2  and the gate capacitance of this transistor. In  FIG. 2( b ) , “K 11 ” denotes this. 
     When the output voltage of the differential unit falls below the logical threshold voltage ½×VDD (2.5 V) of the negative OR circuit NOR 1 , both of the inputs of the negative OR circuit NOR 1  change to a low level and the output of the negative OR circuit NOR 1  changes to a high level (5 V). 
     This turns the transistor N 7  on, so that the output of the differential unit generates a short with the ground terminal GND. This speeds up the discharging of the Miller capacitance and the gate capacitance as stated above, and the output voltage of the differential unit reaches 0 V almost concurrently with falling-below of 2.5 V. In  FIG. 2( b ) , “K 12 ” denotes this. As a result, the transistor N 2  turns off. 
     Receiving the output of the negative OR circuit NOR 1 , the output of the inverter INV 4  changes to a low level. As a result, the transistor P 6  turns on. At this time, the current flowing through the transistor P 6  is much greater than the constant current flowing through the transistor P 1 , so that the Miller capacitance is rapidly charged with the current flowing through the transistor P 6 . This changes the output voltage of the gain unit to a high level almost concurrently with the output of the negative OR circuit NOR 1  changing to a high level. In  FIG. 2( d ) , “K 21 ” denotes this. 
     As illustrated in  FIGS. 30( a )-30( e ) , after 250 ns from the rising of the CG voltage in the conventional oscillator circuit  1 , the output of the gain unit is still at a low level (less than 2.5 V). In contrast, as illustrated in  FIGS. 2( a )-2( f ) , the output of the gain unit of the present embodiment changes to a high level before 100 ns from the rising of the CG voltage, and the comparator output voltage also changes to a high level. 
     In this way, the transistor N 7  shortens the time required for discharging of the Miller capacitance between the gate and the drain of the transistor N 2  and the gate capacitance of this transistor. The transistor P 6  shortens the time required for charging of the Miller capacitance. This shortens the time required for the output voltage of the gain unit to reach the logical threshold voltage of the inverter INV 2 . The comparator output of the present embodiment therefore follows a relatively high-frequency control signal that is externally input. 
     The output of the differential unit is input to the gate of the transistor N 2  and to the negative OR circuit NOR 1 , and the output of this negative OR circuit NOR 1  is input to the gate of the transistor N 7  that connects to the output of the differential unit and the ground terminal GND. Such a configuration functions with the logical threshold voltage of the negative OR circuit NOR 1  that is higher than the gate threshold voltage of the transistor N 2 . 
     Specifically, the transistor N 2  of the conventional oscillator circuit  1  turns off and the output voltage of the gain unit starts to increase only after the output voltage of the differential unit falls below the gate threshold voltage (e.g., 0.7 V) of the transistor N 2 . In contrast, the transistor N 2  of the oscillator circuit  1   a  of the present embodiment turns off and the output voltage of the gain unit starts to increase when the output voltage of the differential unit decreases to the logical threshold voltage (e.g., 2.5 V) of the negative OR circuit NOR 1  that is higher than the gate threshold voltage of the transistor N 2 . Additionally, charging with the transistor P 6  starts at the timing of turning-off of the transistor N 2 . This shortens the time required for rising of the output of the gain unit. 
       FIGS. 3( a )-3( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   a  when the rectangular-wave control signal having the amplitude of 0 V to 5 V and the frequency of 5 MHz is input to the input terminal CG. This drawing illustrates that the comparator output voltage changes while following the voltage of the input terminal CG. In other words, the comparator output voltage is overclocked to about 5 MHz. 
       FIG. 4  illustrates the oscillator circuit  1   a  during typical operation. The oscillator circuit also includes a resistor R 0  externally connected between the input terminal CG and the power-supply terminal VDD as well as a capacitor C 0  externally connected between the input terminal CG and the ground terminal GND.  FIGS. 5( a )-5( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   a  during typical operation. In a manner similar to that in  FIGS. 28( a )-28( e ) , the drawing illustrates that the comparator output voltage has about 200 kHz and the D-type flip-flop circuit D-FF yields the clock output at about 100 kHz. 
     The inverters INV 3  and INV 4  may be called a first inverter and a second inverter, respectively, in the charge-discharge control unit. The transistors N 7  and P 6  may be called a discharge switch and a charge switch, respectively. 
     The configuration of the charge-discharge control unit  4  may be changed as needed. In one example, the inverter INV 3  and the negative OR circuit NOR 1  may be combined as one logic circuit. In this configuration, the input of the inverter INV 3  can be the input of this logic circuit, and the output of the negative OR circuit NOR 1  can be the output of this logic circuit. 
     Second Embodiment 
       FIG. 6  illustrates an oscillator circuit  1   b  and a rectangular-wave generation circuit  9  externally connecting to the oscillator circuit, as a second embodiment of the present invention. In  FIG. 6 , like reference numerals indicate like parts in  FIG. 1 , and their detailed descriptions are omitted. Note here that the charge-discharge control unit  4  of  FIG. 1  corresponds to the combination of a first detection logic unit  41  and a first auxiliary circuit  42  in  FIG. 6 . The first detection logic unit  41  includes an inverter INV 3 , a negative OR circuit NOR 1  and an inverter INV 4 , and is configured to firstly detect the CG voltage reaching a high level. The first auxiliary circuit  42  includes transistors P 6  and N 7 , and is configured to help the output of the gain unit change rapidly to a high level at the exact timing when the output of the gain unit is to change to a high level. 
     The oscillator circuit  1   b  includes a second auxiliary circuit  5  in addition to the configuration of the oscillator circuit  1   a . The second auxiliary circuit  5  includes a switch (N-type MOSFET) N 8  and transistors (N-type MOSFETs) N 9  to N 11 , and is configured to help the output of the gain unit change to a low level speedily at the exact timing when the output of the gain unit is to change to a low level. 
     The drain of the transistor N 10  connects to the output of the gain unit, and the source of the transistor N 10  connects to the drain of the transistor N 11 . The source of the transistor N 11  connects to the ground terminal GND. The output of the inverter INV 4  is input to the gates of the switch N 8  and of the transistor N 10  in addition to the gate of the transistor P 6 . 
     The switch N 8  is inserted between the output of the differential unit  2  and the gate of the transistor N 11 . The gate of the transistor N 11  connects to the drain of the transistor N 9 . The output of the differential unit  2  is input not only to the gate of the transistor N 2  but also to the drain of the transistor N 9  and the gate of the transistor N 11  via the switch N 8 . The source of the transistor N 9  connects to the ground terminal GND, and the gate of the transistor N 9  receives the output of the negative OR circuit NOR 1 . 
       FIGS. 7( a )-7( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   b  when the rectangular-wave control signal by the rectangular-wave generation circuit  9  is input to the input terminal CG. The horizontal axis in this drawing indicates time (μs). The vertical axis indicates CG voltage (V) that is the voltage at the input terminal CG in  FIG. 7( a ) , output voltage of the differential unit (V) in  FIG. 7( b ) , output voltage at the negative OR circuit NOR 1  (V) in  FIG. 7( c ) , output voltage of the gain unit (V) in  FIG. 7( d ) , comparator output voltage (V) in  FIG. 7( e ) , and clock output voltage (V) in  FIG. 7( f ) . 
     As illustrated in  FIG. 7( a )  in the drawing, the rectangular-wave control signal has an amplitude between 0 V and 5 V, and has a frequency of 2 MHz. That is, the period of the rectangular waves is 500 ns. 
     In the case other than “when the CG voltage as the input of the inverter INV 3  is at a high level (&gt;½×VDD) and the output of the differential unit  2  is at a low level (&lt;½×VDD)”, i.e., at the exact timing when the output of the gain unit  3  is to change to a low level (or is at a low level), the output of the negative OR circuit NOR 1  changes to a low level and the output of the inverter INV 4  changes to a high level. Then, the switch N 8  and the transistor N 10  turn on and the transistor N 9  turns off. 
     This results in the transistor N 11  connecting in parallel to the transistor N 2 . This means an increase of the current capacity, so that the output of the gain unit  3  rapidly decreases to a low level. In the drawing (d), “Q 1 ” denotes this. As is clear from the comparison with “Q 2 ” in  FIG. 2( d ) , this shortens the time from the output of the negative OR circuit NOR 1  changing to a low level to the output of the gain unit changing to a low level. 
     In the case “when the CG voltage as the input of the inverter INV 3  is at a high level (&gt;½×VDD) and the output of the differential unit  2  is at a low level (&lt;½×VDD)”, i.e., at the exact timing when the output of the gain unit  3  is to change to a high level (or is at a high level), the output of the negative OR circuit NOR 1  changes to a high level and the output of the inverter INV 4  changes to a low level. Then, the switch N 8  and the transistor N 10  turn off and the transistor N 9  turns on. This disconnects the transistor N 11  from the transistor N 2  and the output of the gain unit. 
       FIGS. 8( a )-8( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   b  when the rectangular-wave control signal having the amplitude of 0 V to 5 V and the frequency of 10 MHz is input to the input terminal CG.  FIGS. 9( a )-9( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   b  when the rectangular-wave control signal having the amplitude of 0 V to 5 V and the frequency of 20 MHz is input to the input terminal CG. These drawings illustrate that the comparator output voltage changes while following the voltage of the input terminal CG. In other words, the comparator output voltage is overclocked to about 20 MHz. 
       FIG. 10  illustrates the oscillator circuit  1   b  during typical operation. The oscillator circuit also includes a resistor R 0  externally connected between the input terminal CG and the power-supply terminal VDD as well as a capacitor C 0  externally connected between the input terminal CG and the ground terminal GND.  FIGS. 11( a )-11( f )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   b  during typical operation. In a manner similar to that in  FIG. 28 , the drawing illustrates that the comparator output voltage has about 200 kHz and the D-type flip-flop circuit D-FF yields the clock output at about 100 kHz. 
     The second auxiliary circuit  5  may be called an output control unit to control the output of the gain unit. 
     Third Embodiment 
       FIG. 12  illustrates an oscillator circuit  1   c  and a rectangular-wave generation circuit  9  externally connecting to the oscillator circuit, as a third embodiment of the present invention. In  FIG. 12 , like reference numerals indicate like parts in  FIG. 6 , and their detailed descriptions are omitted. 
     The oscillator circuit  1   c  includes a second detection logic unit  6  and a second auxiliary circuit  7  in addition to the configuration of the oscillator circuit  1   a . The second detection logic unit  6  includes an inverter INV 5 , a negative AND circuit NAND 1  and an inverter INV 6 , and is configured to first detect the CG voltage reaching a low level. The second auxiliary circuit  7  includes a transistor (N-type MOSFET) N 8   a  having a drain connecting to the output of the gain unit and a source connecting to the ground terminal GND, and is configured to help the transistor N 8   a  turn on at the exact timing when the output of the gain unit is to change to a low level and the output of the gain unit change to a low level speedily. 
     The output of the gain unit is input to the inverter INV 5 . The output of this inverter INV 5  and the output of the inverter INV 3  are input to the negative AND circuit NAND 1 . The output of the negative AND circuit NAND 1  is input to the inverter INV 6 , and the output of this inverter INV 6  is input to the gate of the transistor N 8   a.    
     In one example, let the power-supply voltage VDD be 5 V, and the reference potential of the oscillator circuit  1   c  be at the ground level, i.e., 0 V. The resistors R 2  to R 6  have the same resistance values. This means that the first reference voltage V 1  input to the comparator is 3 V, and the second reference voltage V 2  is 2 V. All logical threshold voltages for the inverters INV 1  to INV 4  and INV 6  and the D-type flip-flop circuit D-FF are ½×VDD. The logical threshold voltage of the inverter INV 5  is ⅔×VDD. This means that the logical threshold voltage of the inverter INV 5  is higher than the logical threshold voltage of the inverter INV 3 . 
       FIGS. 13( a )-13( g )  illustrates simulated waveforms of the voltage at various parts of the oscillator circuit  1   c  when the rectangular-wave control signal by the rectangular-wave generation circuit  9  is input to the input terminal CG. The horizontal axis in this drawing indicates time (ns). The vertical axis indicates CG voltage (V) that is the voltage at the input terminal CG in  FIG. 13( a ) , output voltage of the differential unit (V) in  FIG. 13( b ) , output voltage of the negative OR circuit NOR 1  (V) in  FIG. 13( c ) , output voltage of the negative AND circuit NAND 1  (V) in  FIG. 13( d ) , output voltage of the gain unit (V) in  FIG. 13( e ) , comparator output voltage (V) in  FIG. 13( f ) , and clock output voltage (V) in  FIG. 13( g ) . 
     As illustrated in  FIG. 13( a )  in the drawing, the rectangular-wave control signal has the amplitude between 0 V and 5 V, and has the frequency of 10 MHz. That is, the period of the rectangular waves is 100 ns. 
     When the second detection logic unit  6  detects that the CG voltage and the output of the gain unit are input and the CG voltage changes to a low level (0 V in  FIG. 12 ) and the output of the gain unit changes to a low level (⅔×VDD or less), then the output of the negative AND circuit NAND 1  changes to a low level (the output of the inverter INV 6  is at a high level). Such output of the negative AND circuit NAND 1  at a low level (the output of the inverter INV 6  at a high level) turns the transistor N 8   a  of the second auxiliary circuit on, so that the output of the gain unit rapidly changes to a low level (“Q 3 ” in  FIG. 13( e ) ). As illustrated in  FIG. 13( e ) , the output voltage of the gain unit changes gently and decreases slowly at the initial stage of the falling. The logical threshold voltage of the inverter INV 5  to detect the falling of the output voltage of the gain unit therefore is set higher than the logical threshold voltages of other inverters so as to enable rapid detection of the start of the falling of such output voltage of the gain unit. 
       FIGS. 14( a )-14( g )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   c  when the rectangular-wave control signal having the amplitude of 0 V to 5 V and the frequency of 17 MHz is input to the input terminal CG. This drawing illustrates that the comparator output voltage changes while following the voltage of the input terminal CG. In other words, the comparator output voltage is overclocked to about 17 MHz. 
       FIG. 15  illustrates the oscillator circuit  1   c  during typical operation. The oscillator circuit also includes a resistor R 0  externally connected between the input terminal CG and the power-supply terminal VDD as well as a capacitor C 0  externally connected between the input terminal CG and the ground terminal GND.  FIGS. 16( a )-16( g )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   c  during typical operation. In a manner similar to that in  FIG. 28 , the drawing illustrates that the comparator output voltage has about 200 kHz and the D-type flip-flop circuit D-FF yields the clock output at about 100 kHz. 
     The second detection logic unit  6  and the second auxiliary circuit  7  may be collectively called an output control unit to control the output of the gain unit. 
     The configuration of the second detection logic unit  6  may be changed as needed. In one example, the inverter INV 5 , the negative AND circuit NAND 1  and the inverter INV 6  may be combined as one logic circuit. In this configuration, the input of the inverter INV 5  can be the input of this logic circuit, and the output of the inverter INV 6  can be the output of this logic circuit. 
     Fourth Embodiment 
       FIG. 17  illustrates an oscillator circuit  1   d  and a rectangular-wave generation circuit  9  externally connected to the oscillator circuit, as a fourth embodiment of the present invention. Like reference numerals indicate like parts in  FIG. 12 , and their detailed descriptions are omitted. “CMP” in the drawing represents a comparator of the present embodiment. 
     An oscillator circuit  1   d  in this embodiment includes a charge-discharge control unit  4   d  including a first detection logic unit  41   d  and a first auxiliary circuit  42 , instead of the charge-discharge control unit  4  in the oscillator circuit  1   c . The first detection logic unit  41   d  includes a capacitor (speedup capacitor) C 1  in addition to the configuration of the first detection logic unit  41 . The capacitor C 1  connects to the two inputs of the negative OR circuit NOR 1 , and functions as an AC path between these inputs. 
     The oscillator circuit  1   d  includes a second detection logic unit  6   d , instead of the second detection logic unit  6  in the oscillator circuit  1   c . The second detection logic unit  6   d  includes inverters INV 5   d  and INV 6   d , a negative OR circuit NOR 2  and a capacitor (speedup capacitor) C 2 , and is configured to detect the CG voltage changing to a low level. 
     The input of the inverter INV 5   d  connects to the input terminal CG that connects to the gate of the transistor P 3  making up a differential pair. That is, the inverter INV 5   d  receives a rectangular-wave control signal from the rectangular-wave generation circuit  9 . The output of this inverter INV 5   d  is input to the inverter INV 6   d . The output of the inverter INV 6   d  and the output of the gain unit  3  are input to the negative OR circuit NOR 2 . The output of the negative OR circuit NOR 2  is input to the gate of the transistor N 8   a . The input of the inverter INV 6   d  and the output of the negative OR circuit NOR 2  connect to the capacitor C 2 . The capacitor C 2  functions as an AC path between the input of the inverter INV 6   d  and the output of the negative OR circuit NOR 2 . 
       FIGS. 18( a )-18( g )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   d  using the comparator CMP when the rectangular-wave control signal having the frequency of 2 MHz is input to the input terminal CG. The horizontal axis in this drawing indicates time (μs). The vertical axis indicates CG voltage (V) in  FIG. 18( a ) , output voltage of the differential unit (V) in  FIG. 18( b ) , output voltage of the negative OR circuit NOR 1  (V) in  FIG. 18( c ) , output voltage of the negative OR circuit NOR 2  (V) in  FIG. 18( d ) , output voltage of the gain unit (V) in  FIG. 18( e ) , output voltage of the comparator (V) in  FIG. 18( f ) , and clock output voltage (V) in  FIG. 18( g ) . 
     As illustrated in  FIG. 18( a )  in the drawing, the rectangular-wave control signal has the amplitude between 0 V and 5 V, and has the frequency of 2 MHz. The power-supply voltage VDD is 5 V and the reference potential (GND voltage) of the oscillator circuit  1   d  and the comparator CMP is 0 V. The resistors R 2  to R 6  have the same resistance values. This means that the reference voltage V 1  and the second reference voltage V 2  that are input to the comparator are 3 V and 2 V, respectively. All logical threshold voltages for the inverters INV 1  to INV 4 , INV 5   d  and INV 6   d , the D-type flip-flop circuit D-FF, and the negative OR circuits NOR 1  and NOR 2  are ½×VDD. 
       FIGS. 18( a )-18( g )  illustrate that the oscillator circuit  1   d  successfully operates when it receives the rectangular-wave control signal of 2 MHz. 
       FIGS. 19( a )-19( g )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   d  when the rectangular-wave control signal having the frequency of 50 MHz is input to the input terminal CG. The rectangular-wave control signal in this case has the amplitude between 0 V and 5 V and has the frequency of 50 MHz as illustrated in  FIGS. 19( a ) and ( a )  of  FIG. 24 .  FIGS. 19( a )-19( g )  illustrate that the oscillator circuit  1   d  successfully operates also when it receives the rectangular-wave control signal of 50 MHz. 
     Referring to  FIGS. 19( a )-19( g ) , the following describes the operation of the oscillator circuit  1   d  using the comparator CMP. 
     (1) Operation of the First Detection Logic Unit  41   d    
     The output voltage of the differential unit, which is one of the inputs of the negative OR circuit NOR 1 , does not reach the logical threshold voltage (½×VDD) of this negative OR circuit, and maintains a low level that is lower than the logical threshold value. The output voltage of the negative OR circuit NOR 1  is therefore in phase with the CG voltage that is input to the other input terminal of this negative OR circuit via the inverter INV 3 . 
     (2) Operation of the First Auxiliary Circuit  42   
     The above (1) means that the transistor N 7  having the gate connecting to the output of the negative OR circuit NOR 1  turns on when the CG voltage is at a high level, and turns off when the CG voltage is at a low level. This also means that the transistor P 6  having the gate connecting to the output of the negative OR circuit NOR 1  via the inverter INV 4  turns on when the CG voltage is at a high level, and turns off when the CG voltage is at a low level. 
     (3) Operation of the Second Detection Logic Unit  6   d    
     The transistor N 2  (having the gate threshold voltage of 0.7 V) turns on due to the output of the differential unit, and the output voltage of the gain unit changes to a low level. When the output voltage of the gain unit is at a low level, the output of the negative OR circuit NOR 2 , to which this output voltage of the gain unit is input and the CG voltage is input via the inverters INV 5   d  and INV 6   d , is in opposite phase of the CG voltage. The input of the inverter INV 6   d  also is in opposite phase of the CG voltage due to the inverter INV 5   d.  The input of the inverter INV 6   d  and the output of the negative OR circuit NOR 2  are in synchronization stably via the capacitor C 2 . 
     (4) Operation of the Second Auxiliary Circuit  7   
     The above (3) means that the transistor N 8   a  having the gate connecting to the output of the negative OR circuit NOR 2  turns off when the CG voltage is at a high level, and turns on when the CG voltage is at a low level. 
     (5) Output of the Gain Unit 
     The above means that, when the CG voltage is at a high level, the first auxiliary circuit  42  and the second auxiliary circuit  7  allow the output of the negative OR circuit NOR 1  to be at a high level, the output of the negative OR circuit NOR 2  to be at a low level, and the output of the gain unit to be at a high level (see the table above (b) of  FIG. 24 ). When the CG voltage is at a low level, the output of the negative OR circuit NOR 1  is at a low level, the output of the negative OR circuit NOR 2  is at a high level, and the output of the gain unit is at a low level. 
     Next the following describes the operation of the comparator of the present embodiment that compares the CG voltage with the reference voltage. 
       FIGS. 20( a )-20( g )  illustrate simulated waveforms of the voltage at various parts when the rectangular-wave control signal having the frequency of 50 MHz (the amplitude of 1.5 V and 3.5 V) is input. As illustrated in (b) of  FIG. 24 , 3.5 V as the maximum value exceeds 3 V that is the first reference voltage, and 1.5 V as the minimum value falls below 2 V that is the second reference voltage. The output voltage of the gain unit is therefore in phase with the rectangular-wave control signal (see the table above (b) of  FIG. 24 ). This means that the resultant output of the comparator is in phase with the rectangular-wave control signal. The detection operation is as described in the above (1) to (5). 
       FIGS. 21( a )-21( g )  illustrate simulated waveforms of the voltage at various parts when the rectangular-wave control signal having the frequency of 50 MHz (the amplitude of 0 V and 2.7 V) is input. As illustrated in (c) of  FIG. 24 , 2.7 V as the maximum value falls below 3 V that is the first reference voltage. This means that the output voltage of the gain unit is at a low level, and the output of the comparator also is at a low level. 
     The operation is as follows. When the CG voltage changes from 0 V to 2.7 V, the current flowing from the transistor P 3  to the output of the differential unit reduces in the differential unit  2 . This is because, although the first reference voltage (3 V) exceeds the CG voltage, the difference is small. While the output of the inverter INV 3  is at a low level, the inverter INV 3  has a small power to change the output to a low level, because the input voltage 2.7 V of the inverter INV 3  is close to the threshold voltage VDD/2=2.5 V of the inverter INV 3 . Specifically, the output at a low level means that the output of the inverter INV 3  absorbs the current. The amount of the absorbed current, however, decreases as the input approaches the threshold voltage. 
     When the CG voltage is about to reach 2.7 V, the capacitor C 1  is charged with a difference in voltage between 5 V, which is the output voltage of the inverter INV 3 , and about 1 V ( FIG. 21( b ) ), which is the output voltage of the differential unit. A change in the CG voltage from 0 V to 2.7 V therefore does not instantly change the output of the inverter INV 3  to a low level. The suppressed current flowing through the transistor P 3  and the inverter INV 3  therefore discharges the charge in the capacitor C 1 . This gradually decreases the output of the inverter INV 3 , and accordingly increases the output of the negative OR circuit NOR 1 . The output of the inverter INV 3  transmitted via the capacitor C 1  increases the output of the negative OR circuit NOR 1 . This turns the transistor N 7  on, and the output voltage of the differential unit accordingly decreases to 0 V. 
     As a result, the output of the negative OR circuit NOR 1  has the waveform having a smaller duty ratio than that of the CG voltage. This shortens the time to turn the transistor P 6  on. 
     The output of the negative OR circuit NOR 2  is as follows. When the CG voltage is 0 V, the output is at a high level similarly to  FIG. 18( d ) , because a difference from the threshold voltage of the inverter INV 5   d , VDD/2=2.5 V, is large. When the CG voltage is 2.7 V, the inverter INV 5   d  has a small power to change the output to a low level, because the input voltage 2.7 V of the inverter INV 5   d  is close to the threshold voltage 2.5 V of the inverter INV 5   d . Specifically, the output at a low level means that the output of the inverter INV 5   d  absorbs the current. The amount of the absorbed current, however, decreases as the input approaches to the threshold voltage. This requires a long time to transmit a change of the CG voltage (0 V→2.7 V) to the output of the negative OR circuit NOR 2 , so that the CG voltage reaches 0 V again before the output of the negative OR circuit NOR 2  changes. This means that the transistor N 8  is always on and the output voltage of the gain unit is at a low level. 
       FIGS. 22( a )-22( g )  illustrate simulated waveforms of the voltage at various parts when the rectangular-wave control signal having the frequency of 50 MHz (the amplitude of 2.3 V and 5 V) is input. As illustrated in (d) of  FIG. 24 , 2.3 V as the minimum value exceeds the second reference voltage (2 V). The output voltage of the gain unit is at a high level, the output voltage of the comparator is accordingly at a high level. 
     The operation is as follows. The CG voltage exceeds the second reference voltage (2 V) in the differential unit  2 . This turns the transistor P 3  off and the transistor N 3  on, so that the output voltage of the differential unit is at a low level. That is, the above (1) and (2) hold, so that the transistor P 6  turns on or off. In contrast, the above (3) does not hold, so that the transistor N 2  remains off. When the CG voltage is 2.3 V, this CG voltage is close to the threshold voltage 2.5 V of the inverter INV 5   d . The output voltage of the negative OR circuit NOR 2 , which is the gate voltage of the transistor N 8   a , is therefore not very high as compared with the threshold voltage of the transistor N 8   a  ( FIG. 22( d ) ), so that the current flowing through the transistor N 8   a  is restricted. The output voltage of the negative OR circuit NOR 1  gradually decreases from 5 V, so that the output voltage of the inverter INV 4 , which is the gate voltage of the transistor P 6 , gradually increases from 0 V. This maintains the current-feeding state from the transistor P 6  for a while. This means that a decrease in the output of the gain unit is small during a change of the CG voltage from 5 V to 2.3 V. As a result, the output of the gain unit maintains a high level. 
       FIGS. 23( a )-23( g )  illustrate simulated waveforms of the voltage at various parts when the rectangular-wave control signal having the frequency of 50 MHz (the amplitude of 2.3 V and 2.7 V) is input. As illustrated in (e) of  FIG. 24 , 2.3 V as the minimum value exceeds the second reference voltage (2 V), and 2.7 V as the maximum value falls below the first reference voltage (3 V). The output voltage of the gain unit is at a high level, and the output of the comparator accordingly is at a high level. The negative OR circuit NOR 2  operates similarly to  FIG. 21 . 
     As stated above,  FIGS. 20( a )-20( g )  to  FIGS. 23( a )-23( g )  demonstrate that the comparator performs a comparison operation for the input signal of 50 MHz. 
     The oscillator circuit  1   d  is configured so that the first detection logic unit  41   d  and the first auxiliary circuit  42  allow the output of the gain unit to change to a high level speedily following a change of the CG voltage from a low level (0 V) to a high level (5 V), and the second detection logic unit  6   d  and the second auxiliary circuit  7  allow the output of the gain unit to change to a low level speedily following a change of the CG voltage from a high level to a low level. 
     A higher-frequency signal passes through the capacitor C 1  more easily. Since rectangular waves include numerous high-frequency components at the rising and the falling, the rising edge and the falling edge of the rectangular waves easily pass through the capacitor C 1 . A sudden change of the output of the inverter INV 3 , which is in opposite phase with the high-frequency rectangular-wave control signal and is one of the inputs of the negative OR circuit NOR 1 , therefore leads to a similar change of the other input of the negative OR circuit NOR 1 . This allows the negative OR circuit NOR 1  to perform a pseudo-inverter operation to speedily switch in phase with the rectangular-wave control signal. 
     Similarly, a sudden change of the output of the inverter INV 5   d , which is in opposite phase with the high-frequency rectangular-wave control signal, leads to transmission of such a change to the output of the negative OR circuit NOR 2  via the capacitor C 2 . Accordingly, when the high-frequency rectangular-wave control signal changes to a low level, the output of the negative OR circuit NOR 2  speedily changes to a high level, and the output voltage of the gain unit changes to a low level. A comparison between the waveform of “Q 4 ” in  FIG. 13( d )  and “Q 5 ” in  FIG. 13( e )  and the waveform in  FIG. 19( d )  and  FIG. 19( e )  also confirms this. When the rectangular-wave control signal changes to a high level, the output of the negative OR circuit NOR 2  speedily changes to a low level, and the output voltage of the gain unit changes to a high level. 
       FIG. 25  illustrates the oscillator circuit  1   d  during typical operation. The oscillator circuit includes a resistor R 0  externally connected between the input terminal CG and the power-supply terminal VDD, where the resistor R 0  functions as a current-supply element. The oscillator circuit also includes a capacitor C 0  externally connected between the input terminal CG and the ground terminal GND.  FIGS. 26( a )-26( g )  illustrate simulated waveforms of the voltage at various parts of the oscillator circuit  1   d  during typical operation. Similarly to  FIGS. 28( a )-28( e ) , the drawing illustrates that the comparator output voltage has about 200 kHz, and the output of the D-type flip-flop circuit D-FF yields the clock output at about 100 kHz. 
     The current-supply element is not limited to a resistor, which may be a constant current circuit using a current mirror circuit, for example. 
     The second detection logic unit  6   d  and the second auxiliary circuit  7  may be collectively called an output control unit to control the output of the gain unit. The configuration may omit the capacitor C 1 . 
     In one example, the inverter INV 6   d  and the negative OR circuit NOR 2  may be combined as one logic circuit. In this configuration, the input of the inverter INV 6   d  can be the input of this logic circuit, and the output of the negative OR circuit NOR 2  can be the output of this logic circuit. 
     In one example, the negative OR circuit NOR 1  and the inverter INV 4  may be combined as one logic circuit. In this configuration, the two inputs of the negative OR circuit NOR 1  can be the two inputs of this logic circuit, and the output of the inverter INV 4  can be the output of this logic circuit. 
     These are descriptions of specific embodiments of the present invention, and the present invention is not limited to these embodiments. The concept of the present invention includes various modifications based on the technical idea of the present invention. 
     In one example, the reference potential of the oscillator circuit is not limited to the ground, which may be set at any potential. To distinguish a plurality of inverters, each of these inverters may be called a n-th inverter. Note here that “n” is a natural number. Similarly, to distinguish a plurality of transistors, each of these transistors may be called an n-th transistor. To distinguish a plurality of capacitors, each of these capacitors may be called an n-th capacitor. 
     A signal generated at the input terminal CG of the oscillator circuit can be input to one of the inputs (the gate of the transistor P 3 ) of the differential unit  2  via the external terminal of the comparator CMP. As stated above, a signal generated at the external terminal of the comparator CMP can be a signal generated based on the output of the gain unit of the comparator or a signal externally input to the external terminal of this comparator. 
     As stated above, a control signal to control the oscillator circuit may be a signal generated based on the output of the gain unit or a signal externally input to the oscillator circuit. Such a control signal is input to one of the inputs of the differential unit. 
     REFERENCE SYMBOL LIST 
     
         
         CMP Comparator 
           1  Oscillator circuit 
         VDD Power-supply terminal 
         CG Input terminal 
         GND Ground terminal 
           2  Differential unit 
         P 2  to P 5  Transistor 
         N 3 , N 4  Transistor 
         N 5 , N 6  Switch 
         R 2  to R 6  Resistor 
         V 1 , V 2  Reference voltage 
           3  Gain unit 
         P 1  Transistor 
         N 2  Transistor 
         INV 2  Inverter 
         INV 1  Inverter 
         R 1  Resistor 
         N 1  Transistor 
         D-FF D-type flip-flop circuit 
           1   a  Oscillator circuit 
           4  Charge-discharge control unit 
         INV 3  Inverter 
         NOR 1  Negative OR circuit 
         N 7  Transistor 
         INV 4  Inverter 
         P 6  Transistor 
         R 0  Resistor 
         C 0  Capacitor 
           9  Rectangular-wave generation circuit 
           1   b  Oscillator circuit 
           41  First detection logic unit 
           42  First auxiliary circuit 
           5  Second auxiliary circuit 
         N 8  Switch 
         N 9  to N 11  Transistor 
           1   c  Oscillator circuit 
           6  Second detection logic unit 
         INV 5 , INV 6  Inverter 
         NAND 1  Negative AND circuit 
           7  Second auxiliary circuit 
         N 8   a  Transistor 
           1   d  Oscillator circuit 
           4   d  Charge-discharge control unit 
           41   d  First detection logic unit 
           6   d  Second detection logic unit 
         INV 5   d , INV 6   d  Inverter 
         NOR 2  Negative OR circuit 
         C 1 , C 2  Capacitor