Patent Publication Number: US-8536038-B2

Title: Manufacturing method for metal gate using ion implantation

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a manufacturing method for a metal gate, and more particularly, to a manufacturing method for a metal gate integrated with the gate last process. 
     2. Description of the Prior Art 
     With a trend towards scaling down size of the semiconductor device, conventional methods, which are used to achieve optimization, such as reducing thickness of the gate dielectric layer, for example the thickness of silicon dioxide layer, have faced problems such as leakage current due to tunneling effect. In order to keep progression to next generation, high dielectric constant (hereinafter abbreviated as high-k) materials are used to replace the conventional silicon oxide to be the gate dielectric layer because it decreases physical limit thickness effectively, reduces leakage current, and obtains equivalent capacitor in an identical equivalent oxide thickness (EOT). 
     On the other hand, the conventional polysilicon gate also has faced problems such as inferior performance due to boron penetration and unavoidable depletion effect which increases equivalent thickness of the gate dielectric layer, reduces gate capacitance, and worsens a driving force of the devices. Thus work function metals are developed to replace the conventional polysilicon gate to be the control electrode that competent to the high-K gate dielectric layer. 
     However, there is always a continuing need in the semiconductor processing art to develop semiconductor device renders superior performance and reliability such as ensure the metal gate of the n-type metal-oxide-semiconductor (nMOS) having a work function of about 4.1 eV and the metal gate of the p-type MOS (pMOS) having a work function of about 5.1 eV even though the conventional silicon dioxide or silicon oxynitride gate dielectric layer is replaced by the high-K gate dielectric layer and the conventional polysilicon gate is replaced by the metal gate. 
     SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, a manufacturing method for a metal gate is provided. The manufacturing method includes providing a substrate having at least a semiconductor device with a conductivity type formed thereon, forming a gate trench in the semiconductor device, forming a work function metal layer having the conductivity type and an intrinsic work function corresponding to the conductivity type in the gate trench, and performing an ion implantation to adjust the intrinsic work function of the work function metal layer to a target work function. 
     According another aspect of the present invention, a manufacturing method for metal gates is further provided. The manufacturing method includes providing a substrate having at least a first semiconductor device and a second semiconductor device formed thereon, the first semiconductor device having a first conductivity type, the second semiconductor device having a second conductivity type, and the first conductivity type and the second conductivity type being complementary; forming a first gate trench and a second gate trench respectively in the first semiconductor device and the second semiconductor device; forming a first work function metal layer in the first gate trench, the first work function metal layer having the first conductivity type and a first intrinsic work function corresponding the first conductivity type; performing a first ion implantation to adjust the first intrinsic work function to a first target work function; removing a portion of the first work function metal layer to expose a bottom of the second gate trench; forming a second work function metal layer in the second gate trench, the second work function metal layer having the second conductivity type and a second intrinsic work function corresponding to the second conductivity type; and performing a second ion implantation to adjust the second intrinsic work function to a second target work function. 
     According to the manufacturing method for a metal gate provided by the present invention, the p-type or n-type work function metal layer having the intrinsic work function is formed in the corresponding p-type or n-type semiconductor device and followed by performing the ion implantation to implant specific dopants into the p-type or n-type work function metal layer. Thus the intrinsic work function is adjusted to a target work function that fulfills the requirement to a metal gate of the p-type or n-type semiconductor device. In other words, the manufacturing method for a metal gate provided by the present invention ensures the p-type or n-type semiconductor device obtains a metal gate having the work function fulfilling its requirement and thus ensures the performance of the p-type or n-type semiconductor device. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-10  are drawings illustrating a manufacturing method for metal gates, wherein  FIG. 2  is drawing illustrating a modification to the preferred embodiment,  FIG. 4  is a drawing illustrating another modification to the preferred embodiment, and  FIG. 8  is a drawing illustrating still another modification to the preferred embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIGS. 1-10 , which are drawings illustrating a manufacturing method for metal gates provided by a preferred embodiment of the present invention. As shown in  FIG. 1 , the preferred embodiment first provides a substrate  100  such as a silicon substrate, silicon-containing substrate, or silicon-on-insulator (SOI) substrate. The substrate  100  includes a first semiconductor device  110  and a second semiconductor device  112  formed thereon. And a shallow trench isolation (STI)  102  is formed in the substrate  100  between the first semiconductor device  110  and the second semiconductor device  112  for providing electrical isolation. The first semiconductor device  110  includes a first conductivity type, the second semiconductor device  112  includes a second conductivity type, and the first conductivity type and the second conductivity type are complementary. In the preferred embodiment, the first conductivity type is a p-type and the second conductivity type is an n-type, however those skilled in the art would easily realize that it is not limited to have the first conductivity type being the n-type and the second conductivity type being the p-type. 
     Please refer to  FIG. 1 . The first semiconductor device  110  and the second semiconductor device  112  respectively includes a gate dielectric layer  104 , a bottom barrier layer  106  and a dummy gate such as a polysilicon layer (not shown). The gate dielectric layer  104  can be a conventional silicon oxide (SiO 2 ) layer, a high-K gate dielectric layer, or its combination. The bottom barrier layer  106  can include titanium nitride (TiN), but not limited to this. Furthermore, the first semiconductor device  110  and the second semiconductor device  112  respectively includes first lightly doped drains (LDDs)  120  and second LDDs  122 , a spacer  124 , a first source/drain  130  and a second source/drain  132 . It is well-known to those skilled in the art that selective strain scheme (SSS) can be used in the preferred embodiment. For example, a selective epitaxial growth (SEG) method can be used to form the first source/drain  130  and the second source/drain  132 . Since the first semiconductor device  110  is a p-type semiconductor device and the second semiconductor device  112  is an n-type semiconductor device, epitaxial silicon layers with silicon germanium (SiGe) are used to form the p-type source/drain  130  and epitaxial silicon layers with silicon carbide (SiC) can be used to form the n-type source/drain  132 . Additionally, salicides  134  are formed on the first source/drain  130  and the second source/drain  132 . After forming the first semiconductor device  110  and the second semiconductor device  112 , a contact etch stop layer (CESL)  140  and an inter-layer dielectric (ILD) layer  142  are sequentially formed. Since the steps and material choices for the abovementioned elements are well-known to those skilled in the art, those details are omitted herein in the interest of brevity. 
     Please still refer to  FIG. 1 . After forming the CESL  140  and the ILD layer  142 , a planarization process is performed to remove a portion of the CESL  140  and a portion of the ILD layer  142  to expose the dummy gates of the first semiconductor device  110  and the second semiconductor device  112 . Then, a suitable etching process is performed to remove the dummy gates of the first semiconductor device  110  and the second semiconductor device  112 , and thus a first gate trench  150  and a second gate trench  152  are respectively formed in the first semiconductor device  110  and the second semiconductor device  112 . It is noteworthy that the preferred embodiment is integrated with the high-k first process; therefore the gate dielectric layer  104  includes high-k materials such as rare earth metal oxide. The high-k gate dielectric layer  104  can include material selected from the group consisting of as hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate, (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), and barium strontium titanate (Ba x Sr 1-x TiO 3 , BST). Additionally, an interfacial layer (not shown) can be formed in between the high-k gate dielectric layer  104  and the substrate  100 . After forming the first gate trench  150  and the second gate trench  152 , an etch stop layer  108  can be formed on the bottom barrier layer  106  in both of the first gate trench  150  and the second gate trench  152 . Accordingly, the etch stop layer  108  is exposed in bottoms of the first gate trench  150  and the second gate trench  152 . The etch stop layer  108  can include tantalum nitride (TaN), but not limited to this. 
     Please refer to  FIG. 2 , which is drawing illustrating a modification to the preferred embodiment. As shown in  FIG. 2 , the modification is integrated with the high-k last process; therefore the gate dielectric layer  104  includes a conventional SiO 2  layer. After removing the polysilicon layer to form the first gate trench  150  and the second gate trench  152 , the gate dielectric layer  104  exposed in the bottoms of the first gate trench  150  and the second gate trench  152  serves as an interfacial layer. Next, a high-k gate dielectric layer  104   a  is formed on the substrate  100 . The high-k gate dielectric layer  104  includes materials as mentioned above. As shown in  FIG. 2 , the high-k gate dielectric layer  104   a  formed in the first gate trench  150  and the second gate trench  152  have a U shape and covers the bottoms and sidewalls of the first gate trench  150  and the second gate trench  152 . After forming the high-k gate dielectric layer  104   a , the etch stop layer  108  is formed on the high-k gate dielectric layer  104   a.    
     Please refer to  FIG. 3 . After forming the etch stop layer  108  as shown in  FIG. 1  or  FIG. 2 , a chemical vapor deposition (CVD) or a physical vapor deposition (PVD) is performed to form a first work function metal layer  160  in the first gate trench  150  and the second gate trench  152 . The first work function metal layer  160  includes an intrinsic work function that is corresponding to the conductivity type of the first semiconductor device  110 . That means the first work function metal layer  160  is a p-type work function metal layer and exemplarily includes TiN, TaN, titanium carbide (TiC), tantalum carbide (TaC), tungsten carbide (WC), or aluminum titanium nitride (TiAlN), but not limited to this. In addition, the first work function metal layer  160  can be a single-layered structure or a multi-layered structure. 
     Please still refer to  FIG. 3 . After forming the first work function metal layer  160 , an ion implantation  162  is performed to implant aluminum (Al), nitrogen (N), chlorine (Cl), oxygen (O), fluorine (F), or bromine (Br) into the first work function metal layer  160 . Thus the intrinsic work function of the first work function metal layer  160  is adjusted to a target work function, and the target work function is between 4.9 eV and 5.2 eV. Preferably the target work function is 5.1 eV. 
     Furthermore, the ion implantation  162  can be performed before forming the first work function metal layer  160 : Please refer to  FIG. 4 , which is a drawing illustrating another modification to the preferred embodiment. As shown in  FIG. 4 , the modification is to perform the ion implantation  162  after forming the etch stop layer  108  but before forming the first work function metal layer  160 . Accordingly, dopants such as Al, N, Cl, O, F, or Br are implanted into the etch stop layer  108 . After the ion implantation  162 , the first work function metal layer  160  is formed in the first gate trench  150  and the second gate trench  152 . 
     After performing the ion implantation  162  and forming the first work function metal layer  160 , a thermal treatment  164  is performed to drive the dopants in the etch stop layer  108  to the first work function metal layer  160  for adjusting the intrinsic work function of the first work function metal layer  160  to the target work function. Additionally, the thermal treatment  164  further includes introduction of oxygen that involves adjustment to the intrinsic work function of the first work function metal layer  160 . It is noteworthy that the thermal treatment  164  is also performed after the ion implantation  162  that is performed after forming the first work function metal layer  160  as shown in  FIG. 5 . Thus result of the adjustment to the intrinsic work function of the first work function metal layer  160  is improved. However, when the ion implantation  162  has already adjusted the intrinsic work function of the first work function metal layer  160  to the target work function, the thermal treatment  164  can be eliminated. In other words, when the ion implantation  162  provided by the preferred embodiment has already adjusted the intrinsic work function of the first work function metal layer  160  to the target work function, the thermal treatment  164  is replaced by the ion implantation  162  according to the preferred embodiment. 
     Please refer to  FIG. 6 . Next, a patterned mask is formed on the substrate  100 . The patterned mask can be a patterned photoresist layer (not shown), but not limited to this. The patterned mask covers the first semiconductor device  110  and exposes the first work function metal layer  160  in the second semiconductor device  112 . Then, a suitable etchant is used to remove the first work function metal layer  160  not cover by the patterned mask to expose the etch stop layer  108  in the second gate trench  152 . During removing the first work function metal layer  160 , the etch stop layer  108  renders protection to the underneath bottom barrier layer  106  and high-k gate dielectric layer  104 . It is noteworthy that for improving the gap-filling result of the following formed metal materials, the patterned mask can be formed only in the first gate trench  150  and a surface of the patterned mask is lower than the opening of the first gate trench  150 . Accordingly, the first work function metal layer  160  not covered by the patterned mask is removed and the remained first work function metal layer  160  is left only in the first gate trench  160 , particularly on the bottom and sidewalls of the first gate trench  160 . That means a height of the remained first work function metal layer  160  is smaller than a depth of the first gate trench  150 . Consequently, the gap-filling result of the following formed metal materials can be improved. 
     Please still refer to  FIG. 6 . After removing the first work function metal layer  160  from the second gate trench  152 , a CVD process or a PVD process is performed to form a second work function metal layer  170  on the substrate  100 . The second work function metal layer  170  includes an intrinsic work function that is corresponding to the conductivity type of the second semiconductor device  120 . That means the second work function metal layer  170  is an n-type work function metal layer. Additionally, the second work function metal layer  170  can be a single-layered structure or a multi-layered structure. In the preferred embodiment, the second work function metal layer  170  can be a metal layer preferably a Ti layer formed by the CVD process or the PVD process. And a Al ion implantation  172  is performed after forming the Ti layer for implanting Al into the metal layer. Thus, the second work function metal layer  170  such as a TiAl layer is formed and the intrinsic work function of the second work function metal layer  170  is pre-adjusted. 
     Furthermore, the second work function metal layer  170  provided by the preferred embodiment can be a titanium aluminide (TiAl) layer, a zirconium aluminide (ZrAl) layer, a tungsten aluminide (WAl) layer, a tantalum aluminide (TaAl) layer, or a hafnium aluminide (HfAl) layer formed by the CVD process or the PVD process, but not limited to this. Moreover, after forming the TiAl layer, the ZrAl layer, the WAl layer, the TaAl layer, or the HfAl layer, the Al ion implantation  172  is performed to implant Al into the second work function metal layer  170  for adjusting an Al concentration of the second work function metal layer  170  and pre-adjusting the intrinsic work function of the second work function metal layer  170 . 
     Please refer to  FIG. 7 . After forming the second work function metal layer  170 , an ion implantation  174  is performed to implant lanthanum (La), zirconium (Zr), hafnium (Hf), titanium (Ti), aluminum (Al), niobium (Nb) or tungsten (W) into the second work function metal layer  170 . Thus the intrinsic work function of the second work function metal layer  170  is adjusted to a target work function, and the target work function is between 3.9 eV and 4.2 eV. Preferably the target work function is 4.1 eV. 
     Furthermore, the ion implantation  174  can be performed before forming the second work function metal layer  170 : Please refer to  FIG. 8 , which is a drawing illustrating another modification to the preferred embodiment. As shown in  FIG. 8 , the modification is to perform the ion implantation  174  after removing the first work function metal layer  160  and exposing the etch stop layer  108 , but before forming the second work function metal layer  170 . Accordingly, dopants such as La, Zr, Hf, Ti, Al, Nb, or W are implanted into the etch stop layer  108 . After the ion implantation  174 , the second work function metal layer  170  is formed on the substrate  100 . 
     After performing the ion implantation  174  and forming the second work function metal layer  170 , a thermal treatment  176  is performed to drive the dopants in the etch stop layer  108  to the second work function metal layer  170  for adjusting the intrinsic work function of the second work function metal layer  170  to the target work function. Additionally, the thermal treatment  176  further includes introduction of nitrogen for densifying the second work function metal layer  170 . It is noteworthy that the thermal treatment  176  is also performed after the ion implantation  174  that is performed after forming the second work function metal layer  170  as shown in  FIG. 9 . Thus result of the adjustment to the intrinsic work function of the second work function metal layer  170  is improved. 
     Please refer to  FIG. 10 . Next, a filling metal layer  180  is formed on the second work function metal layer  170  in both of the first gate trench  150  and the second gate trench  152 . Additionally, a top barrier layer (not shown) is preferably formed between the second work function metal layer  170  and the filling metal layer  180 . The top barrier layer can include TiN, but not limited to this. The filling metal layer  180  is formed to fill up the first gate trench  150  and the second gate trench  152 . The filling metal layer  180  includes materials with low resistance and superior gap-filling characteristic, such as Al, TiAl, or titanium aluminum oxide (TiAlO), but not limited to this. 
     Subsequently, a planarization process, such as a chemical mechanical polishing (CMP) process is performed to remove unnecessary filling metal layer  180 , second work function metal layer  170 , first work function metal layer  160 , and etch stop layer  108 . Consequently, a first metal gate (not shown) and a second metal gate (not shown) are obtained. In addition, the ILD layer  140  and the CESL  142  can be selectively removed and sequentially reformed on the substrate  100  for improving performance of the semiconductor devices  110 / 112  in the preferred embodiment. 
     According to the manufacturing method for a metal gate provided by the present invention, the p-type or n-type work function metal layer having the intrinsic work function is formed in the corresponding p-type or n-type semiconductor device and followed by performing the ion implantation to implant specific dopants into the p-type or n-type work function metal layer. Thus the intrinsic work function is adjusted to a target work function that fulfills the requirement to a metal gate of the p-type or n-type semiconductor device. In other words, the manufacturing method for a metal gate provided by the present invention ensures the p-type or n-type semiconductor device obtains a metal gate having the work function fulfilling its requirement and thus ensures the performance of the p-type or n-type semiconductor device. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.