Patent Publication Number: US-11664287-B2

Title: Packaged semiconductor devices and methods of packaging semiconductor devices

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a continuation of U.S. patent application Ser. No. 16/829,275, filed on Mar. 25, 2020, and entitled “Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices,” now U.S. Pat. No. 10,950,514 issued on Mar. 16, 2021, which is a continuation of U.S. patent application Ser. No. 16/390,437, filed on Apr. 22, 2019, and entitled “Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices,” now U.S. Pat. No. 10,629,508 issued on Apr. 21, 2020, which is a continuation of U.S. patent application Ser. No. 15/906,399, filed on Feb. 27, 2018, and entitled “Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices,” now U.S. Pat. No. 10,269,673 issued on Apr. 23, 2019, which is a continuation of U.S. patent application Ser. No. 14/995,865, filed on Jan. 14, 2016, and entitled “Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices,” now U.S. Pat. No. 9,911,675 issued on Mar. 6, 2018, which is a division of U.S. patent application Ser. No. 14/180,208, filed on Feb. 13, 2014, and entitled “Packaged Semiconductor Devices and Methods of Packaging Semiconductor Devices,” now U.S. Pat. No. 9,252,135 issued on Feb. 2, 2016, which applications are incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment, as examples. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     Dozens or hundreds of integrated circuits are typically manufactured on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, in multi-chip modules, or in other types of packaging, as examples. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also require smaller packages that utilize less area than packages of the past, in some applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1  through  10    illustrate cross-sectional views of a method of packaging semiconductor devices at various stages in accordance with some embodiments of the present disclosure. 
         FIGS.  11  and  12    illustrate cross-sectional views of a method of packaging semiconductor devices at various stages in accordance with some embodiments. 
         FIG.  13    is a cross-sectional view illustrating a packaged semiconductor device in accordance with some embodiments. 
         FIG.  14    is a cross-sectional view illustrating a packaged semiconductor device in accordance with other embodiments. 
         FIG.  15    is a cross-sectional view illustrating a packaged semiconductor device in accordance with some embodiments. 
         FIGS.  16  and  17    are more detailed views of portions of the packaged semiconductor device shown in  FIG.  15    in accordance with some embodiments. 
         FIG.  18    is a cross-sectional view illustrating a packaged semiconductor device in accordance with some embodiments. 
         FIG.  19    is a flow chart of a method of packaging a semiconductor device in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     Some embodiments of the present disclosure provide novel methods and structures for packaging semiconductor devices. A sacrificial layer is formed over integrated circuit dies prior to forming a molding compound around the dies, and the sacrificial layer is later removed. The sacrificial layer prevents molding compound residue from forming on the integrated circuit dies, and the formation of recesses between the integrated circuit dies and the molding compound is reduced or prevented. 
       FIGS.  1  through  10    illustrate cross-sectional views of a method of packaging semiconductor devices at various stages in accordance with some embodiments. Referring first to  FIG.  1   , a workpiece  110  is provided that includes a plurality of integrated circuit dies  106 . The workpiece  110  may include a semiconductor substrate comprising silicon or other semiconductor materials and may be covered by an insulating layer, for example. The workpiece  110  may also include other active components or circuits, not shown. The workpiece  110  may comprise silicon oxide over single-crystal silicon, for example. The workpiece  110  may conductive layers or semiconductor elements, e.g., transistors, diodes, etc. Compound semiconductors, GaAs, InP, Si/Ge, or SiC, as examples, may be used in place of silicon. The workpiece  110  may comprise a silicon-on-insulator (SOI) or a germanium-on-insulator (GOI) substrate, as examples. The workpiece  110  may comprise a wafer or strip comprising the plurality of integrated circuit dies  106 , for example. Alternatively, the workpiece  110  may comprise other types of materials, material layers, and components formed thereon. 
     The integrated circuit dies  106  are formed within and/or over the workpiece  110  may include a plurality of connectors such as contact pads  114  disposed on a surface thereof. The contact pads  114  may comprise Cu, Al, other metals, or alloys, combinations, or multiple layers thereof, for example. The contact pads  114  may be disposed within an insulating material (not shown) which may comprise silicon nitride, silicon dioxide, other insulators or polymers, or combinations or multiple layers thereof, for example. The contact pads  114  may be coupled to internal wiring of the integrated circuit dies  106 , such as to vias and/or conductive lines in metallization layers or polysilicon layers of the integrated circuit dies  106 , as examples, not shown. 
     Referring next to  FIG.  2   , a sacrificial layer  108  is formed over the workpiece  110 , e.g., over the integrated circuit dies  106 . The sacrificial layer  108  comprises a photoresist material, an organic material, a polymer material, other materials that solidify after curing, and/or combinations of multiple layers thereof, in some embodiments, for example. In some embodiments, the sacrificial layer  108  comprises polybenzoxazole (PBO), as an example. The sacrificial layer  108  is formed in some embodiments using a spin-on method, chemical vapor deposition (CVD), a spin coating process, a printing process, or other coating methods, as examples. The sacrificial layer  108  comprises a material layer having a thickness comprising dimension d 1 , wherein dimension d 1  comprises about 2 μm to about 5 μm in some embodiments. In some embodiments, dimension d 1  comprises about 1 μm to about 10 μm, as another example. Alternatively, the sacrificial layer  108  may comprise other materials, dimensions, and formation methods. 
     The integrated circuit dies  106  are singulated along scribe lines (not shown) using a die saw, laser, or other device, to form a plurality of separated integrated circuit dies  106 , as shown in  FIG.  3   , which shows a single integrated circuit die  106 . In some embodiments, a backside of the workpiece  110  may be thinned using a grinding process prior to the singulation process, for example. In other embodiments, the backside of the workpiece  110  is not thinned. 
     Next, a carrier  100  is provided, as shown in  FIG.  4   . The carrier  100  may comprise a wafer such as a semiconductor wafer, or the carrier  100  may comprise an organic substrate or other types of substrates. The carrier  100  comprises a sacrificial component that will be removed after one or more integrated circuit dies  106  are packaged, such as integrated circuit dies  106  shown in  FIG.  3   . The carrier  100  may later be cleaned and used to package other semiconductor devices, for example. Alternatively, the carrier  100  may be discarded after the packaging process. 
     The carrier  100  includes a foil and die bond material  102  formed thereon. The foil facilitates in the later removal of the carrier  100  from integrated circuit dies  106 , for example. The die bond material assists in adhering the integrated circuit dies  106  to the carrier  100 , for example. In some embodiments, the die bond material of the foil and die bond material  102  also includes a temperate bond layer that is coated on the top surface of the carrier  100 . The temperate bond layer may comprise about 1 μm to about 10 μm of a light to heat conversion (LTHC) material supplied by 3M, for example. The temperate bond layer may be formed using a deposition process or a spin coating process, as examples. Alternatively, the foil and die bond material  102  may comprise other materials, dimensions, and formation methods. In some embodiments, the foil and die bond material  102  is not included. 
     A plurality of the integrated circuit dies  106  shown in  FIG.  3    are inverted and are attached to the carrier  100 , as shown in  FIG.  4   . The sacrificial layer  108  disposed over the integrated circuit dies  106  is coupled to the top surface of the carrier  100 , for example. In some embodiments, a die attach film (DAF) (not shown) may be formed over the sacrificial layer  108  before or after the singulation process for the integrated circuit dies  106 , for example. The DAF may comprise a glue, an adhesive, or an adhesive film that is adapted to adhere the integrated circuit dies  106  to the foil and die bond material  102  disposed over the carrier  100  in some embodiments, for example. In some embodiments, a DAF is not included. The integrated circuit dies  106  may be attached over the carrier  100  (e.g., over the foil and die bond material  102  disposed over the carrier  100 ) using a pick-and-place machine, other mechanism, or manually, for example. 
     In some embodiments, a single integrated circuit die  106  is coupled over the carrier  100  (not shown). In other embodiments, a plurality of integrated circuit dies  106  are coupled over the carrier  100 . In some embodiments, the integrated circuit dies  106  are packaged individually in separate packages. In other embodiments, a plurality of the integrated circuit dies  106  are packaged together side-by-side in a single package, e.g., in a two-dimensional (2D) packaging scheme. Two or more of the integrated circuit dies  106  may be packaged together in accordance with some embodiments, for example. 
     After the integrated circuit dies  106  are coupled to the carrier  100 , a molding compound  120  is disposed around the integrated circuit dies  106  over the carrier  100 , as shown in  FIG.  5   . The molding compound  120  is formed using a laminating process or other process, in some embodiments. The molding compound  120  fills spaces between the dies  106  and encapsulates the dies  106 , for example. The molding compound  120  comprises a molding material and may comprise epoxy, an organic polymer, or a polymer with a silica-based or glass filler added, as examples. In some embodiments, the molding compound  120  comprises a liquid molding compound (LMC) that is a gel type liquid when applied. Alternatively, the molding compound  120  may comprise other insulating materials and may be applied using other methods. The molding compound  120  is then cured using a heating process, infrared (IR) energy exposure process, an ultraviolet (UV) light exposure process, or other methods, as examples. 
     If the molding compound  120  extends over a top surface of the integrated circuit dies  106  after the curing process, the molding compound  120  is removed from over the integrated circuit dies  106  using a chemical-mechanical polish (CMP), grinding process, etch process, and/or other methods in some embodiments, for example. Because the sacrificial layer  108  is disposed over the integrated circuit dies  106  during the molding compound  120  application and curing process, the molding compound  120  does not reside over the integrated circuit dies  106  after the application and curing process for the molding compound  120  in some embodiments, for example. The molding compound  120  is formed around the integrated circuit dies  106  in some embodiments. 
     The carrier  100  and foil and die bond material  102  are removed, as shown in  FIG.  6   . The carrier  100  may be removed using a de-bonding process, and the foil and die bond material  102  are removed by peeling the foil and using a cleaning process to remove the die bond material, for example. 
     The sacrificial layer  108  is removed, as shown in  FIG.  7   . The sacrificial layer  108  is removed in some embodiments using an organic solvent, an organic acid, or other materials. The sacrificial layer  108  may be removed using as isopropyl alcohol (IPA), acetone, or ethanol in some embodiments, as examples. A surface of the integrated circuit dies  106  and the contact pads  114  is left exposed after the removal of the sacrificial layer  108 . In some embodiments, a top portion of the molding compound  120  in the view shown in  FIG.  7    may be removed in the removal process for the sacrificial layer  108 . In other embodiments, a top portion of the molding compound  120  is not removed. 
     Because the sacrificial layer  108  was disposed over the integrated circuit dies  106  during the molding compound  120  application and curing process, the molding compound  120  does not reside over the integrated circuit dies  106  in some embodiments, for example. In other embodiments, a portion of the molding compound  120  may form over the sacrificial layer  108 , and the portion of the molding compound  120  disposed over the sacrificial layer  108  is advantageously removed during the removal of the sacrificial layer  108 . 
     The molding compound  120  has a first thickness comprising dimension d 2  in some embodiments, and the integrated circuit dies  106  have a second thickness comprising dimension d 3  in some embodiments. Dimensions d 2  and d 3  may comprise about 100 μm to about 500 μm, as examples. Dimension d 2  is greater than dimension d 3  in some embodiments. Dimension d 2  is greater than dimension d 3  by about dimension d 1  in some embodiments, for example. Dimension d 1  comprises a thickness of the sacrificial layer  108 , and dimension d 1  also comprises a difference in the thicknesses of the molding compound  120  and the integrated circuit dies  106 , for example. 
     Dimension d 1  also comprises an amount of a step height between the integrated circuit dies  106  and the molding compound  120 , as another example. In other words, dimension d 1  comprises a distance between a top surface of the molding compound  120  and a top surface of the integrated circuit dies  106  in the view shown in  FIG.  7   . 
     The novel structure of the packaging device at the packaging step shown in  FIG.  7    comprises integrated circuit dies  106  encapsulated by molding compound  120 , yet the molding compound  120  is not disposed over the top surfaces of the integrated circuit dies  106  in the view shown in  FIG.  7   . The molding compound  120  top surface is higher than the integrated circuit die  106  top surface in the view shown in  FIG.  7   , for example. 
     An interconnect structure  122  is formed over the integrated circuit dies  106  and the molding compound  120 , as shown in  FIG.  8   . The interconnect structure  122  includes a plurality of insulating material layers  124  and a plurality of conductive lines  126  and a plurality of conductive vias  128  formed within the insulating material layers  124 . The interconnect structure  122  may include a plurality of contact pads  130  formed proximate a surface thereof. The contact pads  130  may comprise ball grid array (BGA) ball mounts in some embodiments, for example. In some embodiments, portions of the interconnect structure  122  comprise an under-ball metallization (UBM) structure, as another example. The insulating material layers  124  may comprise polybenzoxazole (PBO) or other insulators, and the conductive lines  126 , conductive vias  128 , and contact pads  130  may comprise Cu, Al, other metals, or alloys or multiple layers thereof, in some embodiments, as examples. The plurality of insulating material layers  124 , plurality of conductive lines  126 , plurality of conductive vias  128 , and contact pads  130  of the interconnect structure  122  may be formed using subtractive etch techniques, by damascene techniques, other methods, or combinations thereof, for example. The interconnect structure  122  is disposed over the integrated circuit dies  106  and the molding compound  120 , for example. 
     In some embodiments, the interconnect structure  122  may comprise a redistribution layer (RDL) or a post-passivation interconnect (PPI) structure, for example. In some embodiments, the interconnect structure  122  comprises horizontal electrical connections for the packaged semiconductor devices (see packaged semiconductor devices  140  shown in  FIG.  9   ), for example. The interconnect structure  122  may comprise fan-out electrical connections in some embodiments. In embodiments wherein two or more of the integrated circuit dies  106  are packaged together, the interconnect structure  122  may comprise horizontal electrical connections between the integrated circuit dies  106 , for example. Alternatively, the interconnect structure  122  may comprise other types of electrical connection structures. 
     Because of the step height comprising dimension d 1  between the integrated circuit dies  106  and the molding compound  120 , a portion of the interconnect structure  122  extends downwardly below a top surface of the molding compound  120  in the view shown in  FIG.  8   . For example, a portion of a lower level insulating material  124  layer and a lower portion of conductive vias  128  coupled to the contact pads  114  of the integrated circuit dies  106  extend below a top surface of the molding compound  120  to make electrical contact to the integrated circuit dies  106 . 
     In some embodiments, a plurality of conductors  132  are coupled to the interconnect structure  122 , as shown in  FIG.  9   . The plurality of conductors  132  are coupled to portions of the interconnect structure  122  in some embodiments, for example. The plurality of conductors  132  may be coupled to the contact pads  130  of the interconnect structure  122  in some embodiments, as shown in  FIG.  9   . The conductors  132  are formed over and are coupled to portions of the horizontal electrical connections of the interconnect structure  122  in some embodiments, for example. 
     The conductors  132  may comprise a eutectic material such as solder that is coupled to contact pads  130  or bond pads of the interconnect structure  122 , for example. The conductors  132  may each comprise a solder bump or a solder ball, as examples. The conductors  132  may function as electrical connectors for the packaged semiconductor device. The eutectic material of the conductors  132  may be re-flowed to electrically and mechanically connect the packaged semiconductor device to another device or object, for example. 
     The use of the word “solder” herein includes both lead-based and lead-free solders, such as Pb—Sn compositions for lead-based solder; lead-free solders including InSb; tin, silver, and copper (“SAC”) compositions; and other eutectic materials that have a common melting point and form conductive solder connections in electrical applications. For lead-free solder, SAC solders of varying compositions may be used, such as SAC  105  (Sn 98.5%, Ag 1.0%, Cu 0.5%), SAC  305 , and SAC  405 , as examples. Lead-free conductors  132  such as solder balls may be formed from SnCu compounds as well, without the use of silver (Ag). Alternatively, lead-free solder connectors may include tin and silver, Sn—Ag, without the use of copper. The conductors  132  may be one among an array of the conductors  132  formed as a grid, referred to as a “ball grid array” or “BGA”. The conductors  132  may alternatively be arranged in other shapes. The conductors  132  may also comprise non-spherical conductive connectors, for example. In some embodiments, the conductors  132  are not included. 
     In some embodiments, the interconnect structure  122  and the molding compound  120  are singulated using a die saw, laser, or other device to form a plurality of packaged semiconductor devices  140 , as shown in  FIG.  10   , with each of the plurality of packaged semiconductor devices  140  including one of the plurality of integrated circuit dies  106 . The interconnect structure  122  and the molding compound  120  may be singulated on scribe lines  133  between adjacent integrated circuit dies  106 , as shown in  FIG.  9   , for example. In some embodiments, the packaged semiconductor devices  140  may be attached to a dicing tape (not shown) before the singulation process, and the dicing tape is removed after the singulation process. 
     In other embodiments, the interconnect structure  122  and the molding compound  120  are singulated to form a plurality of packaged semiconductor devices  140  (see  FIGS.  13 ,  14  and  15   ), each of the plurality of packaged semiconductor devices  140  including two or more of the plurality of integrated circuit dies  106 . The integrated circuit dies  106  packaged together in the packaged semiconductor device  140  may comprise similar, the same, or different functions, for example. The molding compound  120  is disposed around the integrated circuit dies  106  and between adjacent integrated circuit dies  106 . 
       FIGS.  11  and  12    illustrate cross-sectional views of a method of packaging semiconductor devices at various stages in accordance with some embodiments. After the packaging process steps shown in  FIGS.  1  through  7   , a plurality of through-vias  138  are formed within the molding compound  120 . The through-vias  138  may be formed using an etch process or laser drilling process after the molding compound  120  is applied to form apertures in the molding compound  120 , and a conductive material may be filled into the apertures using a deposition or plating process to form the through-vias  138 , for example. In other embodiments, before the integrated circuits dies  106  are attached to the carrier  100 , the through-vias  138  may be plated onto the carrier  100  by forming a seed layer over the carrier  100 , forming a photoresist over the seed layer, patterning the photoresist using a lithography process, and plating a conductive material such as Cu, a Cu alloy, or other metals over the seed layer through the patterned photoresist to form the through-vias  138 . The photoresist is then removed. The packaging process steps shown in  FIGS.  4  through  7    are then performed. Alternatively, the through-vias  138  may be formed using other methods. The packaging process steps shown in  FIGS.  8  and  9    are then performed, to form the interconnect structure  122  and conductors  132 , as shown in  FIG.  12   , and the packaged semiconductor devices  140 ′ are singulated along scribe lines  133 . 
     In some embodiments, the plurality of conductors  132  of the packaged semiconductor devices  140  (and also packaged semiconductor devices  140 ′, not shown) are coupled to a substrate  144 , as shown in  FIG.  13    in a cross-sectional view. The substrate  144  may comprise a printed circuit board (PCB) in some embodiments. Alternatively, the substrate  144  may comprise other materials, such as an interposer, another integrated circuit die, or other objects, as example. The packaged semiconductor device  150  includes the packaged semiconductor device  140  that is coupled to the substrate  144 . 
     In some embodiments, an underfill material  146  may be disposed between the plurality of conductors  132  and between the substrate  144  and the interconnect structure  122 , also illustrated in  FIG.  13   . The underfill material  146  may comprise an epoxy material, a SiO 2  filler or other fillers, or other materials, as example. The underfill material  146  may be applied using a needle along one or more sides of the packaged semiconductor device  150  or through an aperture formed within the molding compound  120  and interconnect structure  122 , for example, not shown. 
     The molding compound  120  is also referred to herein as a first molding compound  120 . In some embodiments, a second molding compound  134  is disposed around the plurality of conductors  132 , as shown in  FIG.  14   . The second molding compound  134  may comprise similar materials described for the first molding compound  120 , for example. In some embodiments, the second molding compound  134  comprises an LMC. In some embodiments, the second molding compound  134  is not included. In other embodiments, the second molding compound  134  is included, and an underfill material  146  is not included, not shown. 
     In some embodiments, the second molding compound  134  is included, and an underfill material  146  is also included in the packaged semiconductor device  150 , also shown in  FIG.  14   . The second molding compound  134  may be disposed between the plurality of conductors  132  and between the underfill material  146  and the interconnect structure  122 , for example. 
     In some embodiments, a lid, a heat spreader, or a backside protective film  142  is disposed over the molding compound  120  and the integrated circuit die or dies  106 , as shown in  FIG.  15   . The lid or heat spreader  142  may comprise Al, Cu, alloys thereof, ceramic, or other materials comprising a thickness of about 100 μm to about 1,000 μm, or other dimensions, as examples. The protective film  142  may comprise about 10 μm to about 100 μm of a polymer, an epoxy, or other materials, as examples. The lid, heat spreader, or backside protective film  142  may be attached using an adhesive or formed using a deposition or coating process, for example. Alternatively, a lid, heat spreader, or backside protective film  142  may not be included. 
     In some embodiments, the interconnect structure  122  is disposed over a first side of the integrated circuit die or dies  106  and the molding compound  120  (e.g., the bottom side in the view shown in  FIG.  15   ). The lid, heat spreader, or backside protective film  142  is disposed over a second side of the integrated circuit die or dies  106  and the molding compound  120  (e.g., the top side in the view shown in  FIG.  15   ). The second side is opposite the first side of the integrated circuit die or dies  106  and the molding compound  120 . 
       FIGS.  16  and  17    are more detailed views of portions of the packaged semiconductor device  150  shown in  FIG.  15    in accordance with some embodiments.  FIG.  16    shows a cross-sectional view of a lower corner of an integrated circuit die  106  proximate the molding compound  120 . A portion of the interconnect structure  122  comprising dimension d 1  due to the step height between the molding compound and the integrated circuit die  106  is shown; e.g., after applying the molding compound  120 , the integrated circuit die  106  surface is different than the molding compound  120  surface. The step height comprising dimension d 1  advantageously prevents or reduces a recess from forming between the integrated circuit dies  106  proximate the interconnect structure  122  and/or molding compound  120 , e.g., which may form during a curing process for the molding compound  120  or from grinding processes used to package the semiconductor devices. 
     In some embodiments, the molding compound  120  includes a filler that comprises glass spheres  152 , as shown in  FIG.  17    in a cross-sectional view. Advantageously, grinding processes used in the packaging processes are prevented from deleteriously affecting the filler materials of the molding compound  120 , because of the inclusion of the backside protective film  142  in some embodiments, for example. 
       FIG.  18    is a cross-sectional view illustrating a packaged semiconductor device  160  in accordance with some embodiments. The packaged semiconductor device  160  comprises a package-on-a package (PoP) device in accordance with some embodiments. The PoP device  160  includes a packaged semiconductor device  150  described herein that is coupled to a packaged semiconductor device  170 . The packaged semiconductor device  150  comprises a first packaged semiconductor device, and the packaged semiconductor device  170  comprises a second packaged semiconductor device that is coupled to the packaged semiconductor device  150  in accordance with some embodiments, for example. 
     The packaged semiconductor device  150  includes a plurality of through-vias  138  formed within the molding compound  120 . The through-vias  138  provide vertical connections for the packaged semiconductor devices  150  and  160 . Contact pads  164  are coupled to the through-vias  138 . The contact pads  164  may be formed over or within the molding compound  120 , as illustrated in  FIG.  18   . The contact pads  164  of the packaged semiconductor device  150  are coupled to contact pads (not shown) of packaged semiconductor device  170  by conductors  178  which may comprise solder balls or other materials. The conductors  178  may comprise similar materials described for conductors  132 , for example. 
     Packaged semiconductor device  170  includes one or more integrated circuit dies  176  coupled to a substrate  174 . Wire bonds  172  may be coupled to contact pads on a top surface of the integrated circuit die or dies  176 , which are coupled to bond pads (not shown) on the substrate  174 . A molding compound  168  may be disposed over the wire bonds  172 , integrated circuit die or dies  176 , and the substrate  174 . 
     Alternatively, a PoP device  160  may include two packaged semiconductor devices  150  described herein that are coupled together in some embodiments, not shown in the drawings. In some embodiments, the PoP device  160  may comprise a system-on-a-chip (SOC) device, as another example. 
     In  FIGS.  13  through  15  and  18   , the step height comprising dimension d 1  is not shown; however, the packaged semiconductor devices  150  and  160  shown in  FIGS.  13  through  15  and  18    include the step height between the molding compound  120  and the integrated circuit dies  106  that is shown in  FIGS.  7  through  12   , in accordance with some embodiments of the present disclosure. 
       FIG.  19    is a flow chart  180  of a method of packaging semiconductor devices in accordance with some embodiments. In step  182 , a sacrificial layer  108  (see also  FIG.  2   ) is disposed over an integrated circuit die  106 . In step  184 , the integrated circuit die  106  is coupled to a carrier  100  ( FIG.  4   ). In step  186 , a molding compound  120  is disposed around the integrated circuit die  106  ( FIG.  5   ). In step  188 , the sacrificial layer  108  is removed ( FIG.  7   ). In step  190 , an interconnect structure  122  is formed over the integrated circuit die  106  and the molding compound  120  ( FIG.  8   ). 
     Embodiments of the present disclosure include methods of packaging semiconductor devices, and also include packaged semiconductor devices that have been packaged using the methods described herein. Some embodiments include PoP devices that include the packaged semiconductor devices described herein. Some embodiments are particularly beneficial when implemented in wafer level packaging (WLP) applications, fan-out WLP (FOWLP) applications, 2D packages, 3D packages, and other types of packaging, as examples. 
     Advantages of some embodiments of the present disclosure include providing a novel sacrificial layer  108  and packaging process that results in reduced recessing between a molding compound and integrated circuit dies encapsulated by the molding compound. The sacrificial layer  108  also prevents or reduces overflow of the molding compound over the integrated circuit dies, preventing molding compound residue from forming on the integrated circuit dies in some embodiments. Residual molding compound that may form over the sacrificial layer  108  is removed when the sacrificial layer  108  is removed, thus avoiding a need for a grinding process to remove excess molding compound from over the integrated circuit dies. The sacrificial layer  108  also prevents failure of the interconnect structures by preventing or reducing recesses between the molding compound and integrated circuit dies. Increased packaging yields are achievable by implementing embodiments of the present disclosure. Furthermore, the novel packaged semiconductor devices and methods are easily implementable into packaging process flows. 
     In some embodiments, a packaged semiconductor device includes an integrated circuit die, a molding compound disposed around the integrated circuit die, and an interconnect structure disposed over the integrated circuit die and the molding compound. The molding compound is thicker than the integrated circuit die. 
     In other embodiments, a method of packaging a semiconductor device includes disposing a sacrificial layer over an integrated circuit die and coupling the integrated circuit die to a carrier. A molding compound is disposed around the integrated circuit die. The sacrificial layer is removed, and an interconnect structure is formed over the integrated circuit die and the molding compound. 
     In other embodiments, a method of packaging a semiconductor device includes disposing a sacrificial layer over a wafer including a plurality of integrated circuit dies, singulating the plurality of integrated circuit dies, and coupling the plurality of integrated circuit dies to a carrier. A molding compound is disposed around the plurality of integrated circuit dies. The method includes removing the carrier, removing the sacrificial layer, and forming an interconnect structure over the plurality of integrated circuit dies and the molding compound. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.