Patent Publication Number: US-2010109744-A1

Title: Level shifter having a cascode circuit and dynamic gate control

Description:
PRIORITY INFORMATION 
     This patent application claims priority from German Patent Application No. 10 2008 056 130.4 filed Nov. 6, 2008, which is hereby incorporated by reference in its entirety. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to electronic circuits, and in particular to level shifter circuits. 
     Level shifters of this type are known from the related art, for example, from German Patent DE 10 2004 052 092 A1 for converting an input signal in from a first operating voltage range I having a first ground potential VSS 1  and a first supply potential VDD 1  into an output signal out in a second operating voltage range II having a second ground potential VSS 2  and a second supply potential VDD 2 . 
       FIGS. 3 and 4  schematically illustrate prior art level shifters. 
       FIG. 3  is a schematic illustration of a prior art level shifter  300  is a first input transistor T 1   302  and a first output transistor T 3   304  with a series circuit of a second input transistor T 2   306  and a second output transistor T 4   308  and is connected between first ground potential VSS 1   310  and second supply potential VDD 2   312 . The first output transistor T 3   304  and the second output transistor T 4   308  are cross-coupled, i.e., a control input of the first output transistor T 3   304  is connected to a junction point between the second input transistor T 2   306  and the second output transistor T 4   308 , and a control input of the second output transistor T 4   308  is connected to a junction point between the first input transistor T 1   302  and the first output transistor T 3   304 . Input signal in on line  314  may be directly supplied to a control input of the first input transistor T 1   302 , while it may be supplied to a control input of the second input transistor T 2   306  as an inverted input signal inq on line  316 . An output signal out on line  318  may be picked off at the junction point between the second input transistor T 2  and the second output transistor T 4 , while an inverted output signal outq on line  320  may be picked off at the junction point between the first input transistor T 1  and the first output transistor T 3 . 
     If, for example, a high signal is applied on the line  314 , the first input transistor T 1  is switched to a conducting state and raises the downstream junction point to the first ground potential VSS 1 . The second input transistor T 2 , to which the inverted high signal, i.e., a low signal, is supplied, becomes non-conductive. The first ground potential VSS 1 , applied to the junction point between the first input transistor T 1  and the first output transistor T 3 , switches the second output transistor T 4 , which is designed as a p-channel transistor, into a conducting state, so that the junction point between the second input transistor T 2  and the second output transistor T 4  is raised to the second supply potential VDD 2 . The potential applied to the junction point brings the first output transistor T 3 , which is also designed as a p-channel transistor, into a blocking state. On the output side, a high signal, namely, the second supply potential VDD 2 , may thus be picked off at the junction point between the second input transistor T 2  and the second output transistor T 4  as the output signal out on the line  318 . On the output side, at the junction point between the first input transistor T 1  and the first output transistor T 3 , a low signal, namely the first ground potential VSS 1 , may be picked off as inverted output signal outq on line  320 . 
     If first operating voltage range I is in a range from 0 V to 3 V, for example, and second operating voltage range II is in a range of 7 V to 12 V, it is also necessary, as  FIG. 4  shows, to replace each input transistor T 1 , T 2  with a cascode circuit made up of first transistors T 11 , T 21   402 ,  404  and second transistors T 12 , T 22   406 ,  408  for surge protection. The control inputs of the second transistors T 12 , T 22   406 ,  408  are connected to the first supply potential VDD 1 , so that the two second transistors T 12 , T 22   406 ,  408  designed as n-channel transistors, are permanently in a conducting state. The two first transistors T 11 , T 21   402 ,  404  are technologically designed in such a way that they do not overcome the high potential difference between the first ground potential VSS 1  and the second supply potential VDD 2  without being damaged. This disadvantage is eliminated by the second transistors T 12 , T 22   406 ,  408 . 
     If, in a level shifter according to the prior art, a potential difference in first operating voltage range I is so small that a resulting effective gate voltage Veff G  is in the proximity of threshold voltage V th  of the input transistors T 11  and T 21   402 ,  404 , and no transistors having a lower threshold voltage V th , which is achieved by a thinner gate oxide and a suitable channel doping, can be used, the level shifter known from the prior art will not operate, since the effective gate voltage of the cascode transistors T 12 , T 22   406 ,  408  is no longer high enough. Effective gate voltage Veff G  is defined as the difference between an actually applied gate-source voltage V GS  and threshold voltage V th  of a transistor. 
     There is a need for a level shifter that operates reliably even in the case of a low potential difference in the first operating voltage range I and a high potential difference in the second operating voltage range II. 
     SUMMARY OF THE INVENTION 
     A level shifter according to an aspect of the present invention converts an input signal from a first operating voltage range having a first ground potential and a first operating potential into an output signal in a second operating voltage range having a second ground potential and a second operating potential. The level shifter includes an input circuit and an output circuit; the input signal may be applied to the input circuit, and the output signal may be picked off at the output circuit. The input circuit includes a parallel circuit made up of a first cascode circuit and a second cascode circuit, each cascode circuit having a first transistor in the source circuit and a second transistor in the gate circuit. The level shifter includes a dynamic control for the second transistors. 
     By using dynamic gate control for the second transistors, the second transistors may be designed in a manufacturing process according to the requirements for the second operating voltage range. Using the dynamic gate control the second transistors may be brought into a conducting state despite a low potential difference in the first operating voltage range. 
     Dynamic gate control may be achieved, for example, by using a capacitor that between a control terminal of the first transistor and a control terminal of the second transistor. If a signal is applied to the first transistor, depending on the shape of the signal, charges are pushed from the capacitor to the control input of the second transistor or pulled from the control input of the second transistor to the capacitor. If a high signal is applied, the corresponding charges are thus moved from the capacitor to the control terminal of the second transistor, so that an increased potential is briefly applied there, which is sufficient to set the second transistor into a conducting state. 
     To prevent an excessively rapid charge leveling to the first operating potential, a resistor may be situated between the control terminal of each of the second transistors and the first operating potential. To prevent voltage-induced defects, that may occur due to an excessively high or excessively low potential at the control input of the second transistor, a clamping circuit, that clamps to the first operating potential may be situated parallel to the resistor. This clamping circuit may be implemented, for example, by using two diodes connected in antiparallel or two transistors connected as diodes. 
     Dynamic gate control is used preferably in level shifters in which the first transistors are suitable for the first operating voltage range and the second transistors are suitable for the second operating voltage range. The suitability of the particular transistors for the first and second operating voltage ranges determines the technological dimensioning of the particular transistors. For example, the transistors for the first operating voltage range are provided with a thinner gate oxide and a lower threshold voltage than those for the second operating voltage range. Thus, however, the result of this is that the first transistors do not overcome a high potential difference between the second supply potential and the first ground potential without being damaged. If the second transistors connected in cascode, which are designed in such a way that they overcome the potential difference in the second operating voltage range without being damaged, are provided for surge protection of the first transistors, this results in the second transistors having to be dimensioned to have a thicker gate oxide and a higher threshold voltage. Due to the dynamic gate control, an effective gate voltage may be achieved at the second transistors, which is sufficiently high for setting them into a conducting state. The effective gate voltage is defined as the difference between a gate source voltage applied to the transistor and a threshold voltage of the transistor. 
     To provide defined input signals and output signals for the level shifter, inverters may be provided both at the input and at the output of the level shifter. 
     The capacitors of the dynamic gate control may be formed, for example, by gate capacitors of MOS transistors or by metal finger capacitors or MIM capacitors. The gate capacitors of MOS transistors have the advantage that they have a high capacitor coating per surface area. Metal finger capacitors or MIM capacitors are associated with a higher surface area requirement. 
     The resistors of the dynamic gate control may be formed, for example, by polysilicon, diffusion resistors, or well resistors, polysilicon resistors having the advantage that they are uncoupled from the substrate. 
     The input circuit and/or the output circuit may have different protective circuits for protection against electrostatic damage. 
     For example, to prevent excessive voltages between the first ground potential and the second ground potential, a circuit comprising two clamping diodes connected in antiparallel or transistors connected as diodes may be provided. Furthermore, a potential difference in the first operating voltage range may be limited by a first operating voltage clamping circuit, and a potential difference in the second operating voltage range may be limited by a second operating voltage clamping circuit, each of which is situated between the ground potential and the supply potential. The output signal may be limited to the second operating voltage range by clamping diodes or by transistors connected as diodes, so that no damaging voltages may be applied to the output. In addition, further resistors may be situated between the input circuit and the output circuit for current limitation. 
     These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of preferred embodiments thereof, as illustrated in the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic illustration of a level shifter having cascode circuits and a dynamic gate control; 
         FIG. 2  is a pictorial illustration of typical voltage curves when switching over from a low level to a high level using a level shifter according to an aspect of the present invention; 
         FIG. 3  is a schematic illustration of a prior art level shifter; and 
         FIG. 4  is a schematic illustration of a prior art level shifter having a cascode circuit. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  is a schematic illustration of a level shifter  100  that converts an input signal in on a line  102  from a first operating voltage range I into an output signal out on a line  104  in a second operating voltage range II. The first operating voltage range I has a first ground potential VSS 1  and a first operating potential VDD 1 . The second operating voltage range II has a second ground potential VSS 2  and a second operating potential VDD 2 . Input circuit  1  is designed as a parallel circuit made up of a first input stage  10  and a second input stage  20 , each having, as a cascode circuit, a first transistor T 11 , T 21  in the source circuit and a second transistor T 12 , T 22  in the gate circuit. Each input stage  10 ,  20  also has a dynamic gate control for controlling a control input of second transistors T 12 , T 22 . The dynamic gate control may be implemented using capacitors C 1 , C 2 , each of which is situated between a control input of the first transistor T 11 , T 21  and the control input of the second transistor T 12 , T 22 . To prevent excessively rapid potential leveling between the control input of the second transistor T 12 , T 22  and the first supply potential VDD 1 , a resistor R 1 , R 2  is situated between the control inputs of each of the second transistors T 12 , T 22  and first supply potential VDD 1 . Two diodes D 11 , D 12 , D 21 , D 22 , connected in antiparallel, are provided in parallel to resistors R 1 , R 2  as first clamping circuit K 1  and second clamping circuit K 2  for clamping to first supply potential VDD 1 . 
     The input signal in on the line  102  is inverted by a first inverter I 1  for first transistor T 11  of the first input stage  10  and supplied inverted again, i.e., normal, by a second inverter I 2 , to first transistor T 21  of the second input stage  20 . 
     Resistors R 3 , R 4  are situated between the input circuit  1  and the output circuit  2  to limit current flowing between the circuits. 
     The output circuit  2  is formed by two cross-coupled third transistors T 13 , T 23 , which are designed as p-channel transistors. The third transistors T 13 , T 23  are situated in the source circuit; the output signal out on the line  104  may be picked off at the drain terminal of one third transistor T 13 , which is connected to the first input stage  10 , and an inverted output signal outq may be picked off at the drain terminal of the other third transistor T 23 , which is connected to the second input stage  20 . Inverted output signal outq is clamped by first clamping diode D 1  and a second clamping diode D 2  to second operating voltage range II, the first clamping diode D 1  clamping to the first supply potential VDD 2  and the second clamping diode D 2  clamping to the second ground potential VSS 2 . The output circuit  2  is connected downstream from a third inverter I 3 , so that output signal out on the line  104  may be picked off at an output of the third inverter I 3 . 
     To prevent high potential differences between the first ground potential VSS 1  and the second ground potential VSS 2 , two diodes D 3 , D 4 , connected in antiparallel, which may also be designed as MOS transistors connected as diodes, are connected between the first ground potential VSS 1  and the second ground potential VSS 2 . 
     The potential differences between the ground potential VSS 1 , VSS 2  and the supply potential VDD 1 , VDD 2  in the particular operating voltage ranges  1 ,  2  are limited by appropriately situated other clamping circuits C 11 , C 12   120 ,  122 , which are connected to the particular ground potential VSS 1 , VSS 2  and the particular supply potential VDD 1 , VDD 2 . 
     The function of the above-described level shifter is explained below with reference to the voltage curves depicted in  FIG. 2  for a transition of input signal in on the line  102  from a low level to a high level as an example. 
       FIG. 2  shows corresponding voltage curves at the outputs of the second and third inverters I 2 , I 3  at the control input of the second transistor T 22  of the second input stage  20  and at the drain terminal of the third transistor T 23 . First operating voltage range I is specified as having a ground voltage of 0 V and a supply voltage of 1 V for this purpose as an example. 
     The output signal of the inverter I 2  describes double inverted input signal in which is applied to the first transistor T 21  of the second input stage  20 . Inverted output signal outq, may be picked off at the drain terminal of the third transistor T 23 ; it subsequently may be picked off at the output of the inverter I 3  as output signal out. 
     If a transition from a low level (0 V) to a high level is present at the output of the second inverter I 2 , charges are pushed to the control terminal of the second transistor T 22  by the capacitor C 2  via the capacitive coupling. The control terminal of the second transistor T 22  is normally at the first supply potential VSS 1  and is briefly raised over the first supply potential VSS 1  by the additional charges from the capacitor C 2 , whereby the second transistor T 22  is set to a conducting state and, together with also conducting the first transistor T 21 , pulls the drain terminal of the third transistor T 23  toward the first ground potential VDD 1 . A low level may thus be picked off at the drain terminal of the third transistor T 23 ; this low level is converted by the third inverter I 3  to a high level, which may be picked off as output signal out on the line  104 . 
     As evident from  FIG. 2 , the potential at the input of the second transistor T 22  is lowered below the first supply potential VDD 1  by approximately 0.5 V when the input signal is switched from a high level to a low level, while the input potential of the second transistor T 22  is raised by approximately 0.7 V when switching from a low level to a high level. The input potential of the second transistor is set again to the value of the first supply potential VDD 1  in the form of a charge or discharge curve for the capacitor C 2 . 
     Using the above-described dynamic gate control, a gate-source voltage V GS  of the second transistors T 12 , T 22  may be increased in such a way that an effective gate voltage Veff G  of the second transistors T 12 , T 22  is sufficiently high for setting them into a conducting state despite a threshold voltage V th  that is elevated for technological reasons. 
     Although the present invention has been illustrated and described with respect to several preferred embodiments thereof, various changes, omissions and additions to the form and detail thereof, may be made therein, without departing from the spirit and scope of the invention.