Patent Publication Number: US-8988953-B2

Title: Memories and methods for sharing a signal node for the receipt and provision of non-data signals

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of U.S. patent application Ser. No. 12/874,938, filed Sep. 2, 2010, and issued as U.S. Pat. No. 8,526,247, on Sep. 3, 2013. This application and patent are incorporated herein by reference, in their entirety, for any purpose. 
    
    
     TECHNICAL FIELD 
     Embodiments of the present invention relate generally to memory, and more specifically, in one or more of the illustrated embodiments, to combining receipt and provision of non-data signals at a shared signal node. 
     BACKGROUND OF THE INVENTION 
     Data strobe signals are signals that are provided from a memory or provided to the memory when read data is output and write data is received by the memory, respectively. Data strobe signals are related to read and write data, but are not themselves data signals. For example, a read data strobe signal is provided by the memory and typically has signal transitions between a high and low levels that are coincident with the signal transitions between bits of read data output by the memory. A write data strobe signal is provided to the memory and typically has signal transitions that are coincident with “data eyes” of the bits of write data received by the memory. The write data strobe signal may be used by the memory to time the latching of the write data. Both read data and write data strobe signals typically include preamble and post amble portions that frame a strobe portion of the data strobe signals. The preamble portion may be used to establish a stable strobe condition just prior to use (either by the memory in the case of write data or a requesting entity in the case of read data) for example, at a rising edge of a next clock cycle. The post amble portions signal may be used to provide a clean strobe completion, for example, a low time after a falling edge used for data capture. 
     Read and write data strobe signals are typically provided from and received at a shared signal node. That is, the read data strobe is provided from a signal node during the output of data by the memory and the write data strobe is provided to the same signal node during receipt of write data by the memory. In situations where read and write operations occur immediately in sequence, a buffer coupled to the shared signal node must be allowed to conclude provision of, for example, the read data strobe and then prepare to receive, for example, the write data strobe without missing the beginning of the write strobe. In order to provide sufficient “turn around” time for the buffer, at least one clock period is typically inserted between the end of one data strobe signal and the beginning of the other data strobe signal. During the turn around time, no data can be provided or received by the memory. As a result, data bandwidth of the memory is negatively affected. 
     In addition to data strobe signals, other signals that are not data signals and that are not data strobe signals, but are related to read or write data may be received or provided by the memory. For example, a data mask DM signal may be provided to a memory receiving write data and used to mask portions of the write data written to memory. Another example is an output data valid QV signal which may be provided by the memory with the output of read data to indicate that the read data is valid and can be latched by a receiving entity. As known, there are other examples of non-data signals related to data as well. 
     Although not all examples of non-data signals are used in every memory application, memory designers often design a memory to include the functionality in order to provide flexibility in the use of the memory for various types of memory systems. As a result, the memory includes additional signal nodes to and from which non-data signals may be provided, thereby increasing the “pin count” for memories. Increasing memory pin count may be undesirable due to size constraints and board layout complexity resulting from the signal nodes, among other reasons. As the number of memory signals continues to increase, the difficulties associated with increasing memory pin count may increase as well. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of a portion of input and output signal nodes for a memory according to an embodiment of the invention. 
         FIG. 2  is a timing diagram for various signals during operation of the embodiment of  FIG. 1 . 
         FIG. 3  is a block diagram of a portion of input and output signal nodes for a memory according to an embodiment of the invention. 
         FIG. 4  is a block diagram of a portion of input and output signal nodes for a memory according to an embodiment of the invention. 
         FIG. 5  is a block diagram of a memory system according to an embodiment of the invention including a portion of input and output signals nodes according to an embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     Certain details are set forth below to provide a sufficient understanding of embodiments of the invention. However, it will be clear to one skilled in the art that embodiments of the invention may be practiced without these particular details. Moreover, the particular embodiments of the present invention described herein are provided by way of example and should not be used to limit the scope of the invention to these particular embodiments. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail in order to avoid unnecessarily obscuring the invention. 
       FIG. 1  illustrates a portion of input and output signal nodes for a memory according to an embodiment of the invention. The portion shown in  FIG. 1  are related to write data strobe signals and read data strobe signals, which as previously discussed, are both examples of non-data signals that are related to data signals. As known, a write data strobe signal is received by the memory and may be used to time the latching of write data by the memory and a read data strobe signal may be provided by the memory and may be used by the requesting entity to time reception of the read data. In contrast to conventional memory having a shared write and read data strobe node, or separate, dedicated write data strobe signal node and read data strobe signal node,  FIG. 1  illustrates an embodiment of the invention in which at least one of the data strobe signals shares a node and circuitry with a non-data signal. 
     For example, as shown in  FIG. 1 , a write data strobe signal DS is provided to a signal node  110  to which an input buffer  120  is coupled to receive and buffer a DS signal. The input buffer  120  provides an internal DS signal in response. An input/output buffer  140  is coupled to a signal node  130  to which a data mask signal DM is applied and from which a read data strobe QS is provided. In operation, a DM signal applied to the signal node  130  is buffered and output internally by the input/output buffer  140 . An internal QS signal is buffered and output externally on the signal node  130  by the input/output buffer  140 . In some embodiments, the DS signal and the QS signal may include a “preamble” portion and may further include a “postamble” portion. A preamble is a portion of the data strobe signals that precedes the strobe portion of the DS and QS signals and a postamble is a portion of the data strobe signals that follows the strobe portion of the DS and QS signals. The DM signal is an example of a signal that typically does not have a preamble or postamble. 
       FIG. 2  illustrates a timing diagram for various signals during an example operation of a memory that includes an embodiment of the invention. For example, the timing diagram may apply to the embodiment illustrated in  FIG. 1 , that is, a DS signal applied to signal node  110  and a combined data mask DM signal (provided to the signal node  130 ) and a QS signal (provided from the signal node  130 ). The combined signal of signal node  130  will be referred to as the DMQS signal. The example operation of  FIG. 2  includes a read operation followed by a write operation. Shown in  FIG. 2 , among other signals, are the write data strobe signal DS, the data mask and read data strobe signal DMQS, and read and write data signals DQ. 
     At time T 0  a read command is issued to the memory. After about four clock cycles of read latency, a QS signal preamble is issued (from the DMQS signal node, e.g., signal node  130  of  FIG. 1 ) at time T 4  to stabilize the strobe prior to use on the next clock cycle, that is, at time T 5 . At time T 5  the QS signal clocks in synchronicity with the read data signals DQ. In the example operation illustrated by  FIG. 2 , eight bits of read data are provided over four clock cycles. Also at time T 5  a write command is issued to the memory to follow the output of read data. The eighth bit of read data is output during the last half-clock cycle preceding time T 9 . Coincident with the eighth bit is a postamble portion for the QS signal cleanly terminating the last transition of the QS signal. 
     At time T 9  a DS signal preamble is received (at the DS signal node, e.g., signal node  110  of  FIG. 1 ) to stabilize the strobe prior to use on the next clock cycle, that is, at time T 10 . The write data signals DQ are provided to the memory at a time relative to the DS signal (e.g., center of the “data eye” coincident with a clock edge of the DS signal) so that the DS signal may be used to latch the write data signals DQ. In the example operation of  FIG. 1 , valid write data signals can be latched beginning at time T 10 . Eight bits of write data are provided to the memory over four clock cycles T 10  through T 13 . Also provided to the memory is a DM signal (at the DMQS signal node, e.g., signal node  130  of  FIG. 1 ). A mask bit is provided coincident with each bit of write data over clock cycles T 10  through T 13 . The DM signal may be received at the same node (e.g., signal node  130 ,  FIG. 1 ) from which the QS signal was provided during the read operation responsive to the read command at time T 0 . 
     As illustrated by the example operation of  FIG. 2 , the QS and DS signals are provided from and received at respective signal nodes, one of which, namely the read strobe signal, is shared with a signal that is not active during a respective operation. In the example operation, the signal node shared with the read strobe signal is the data mask DM signal, which is typically provided to the memory during a write operation. As previously mentioned, the DM signal which typically does not include a preamble or postamble portion can be provided to the memory at the signal node from which the QS signal was provided at a next clock cycle of the memory clock. Separating the signal nodes for the QS and DS signals may eliminate a need to include turn-around time between a last clock cycle of one of the data strobe signals and a first clock cycle of the other data strobe signal to ensure signal integrity of the data strobe signals. As illustrated in  FIG. 2 , for example, the DS signal begins at the time the QS signal ends at time T 9 . Because the QS signal is provided from a first signal node and the DS signal is provided to a second signal node, the DS signal will not affect the integrity of the QS signal. Sharing a signal node between a strobe signal and another signal that is not active during the time the data strobe signal is active may reduce the number of signal nodes required for operation of the memory. The non-data signal has a direction relative to the memory opposite of the data strobe signal. Although the particular embodiment of  FIG. 1  illustrates combining the QS signal with a non-data signal (i.e., data mask DM), in some embodiments of the invention, the DS signal is combined with a non-data signal. That is, a signal having pre- and/or postamble portions is combined at a signal node with a non-data signal. 
       FIG. 3  illustrates a portion of input and output signal nodes for a memory according to an embodiment of the invention. In contrast to conventional memory having a shared write and read data strobe node, or separate, dedicated write data strobe signal node and read data strobe signal node,  FIG. 3  illustrates an embodiment of the invention in which differential signals are utilized and at least one of the data strobe signals shares a node and circuitry with a non-data signal. For example, as shown in  FIG. 3 , an input/output buffer  340  is coupled to a signal node  330  to which a DM signal is applied and from which a QS signal is provided. A DM signal applied to the signal node  330  is buffered and output internally by the input/output buffer  340 . An internal QS signal is buffered and output externally on the signal node  330  by the input/output buffer  340 . A write data strobe signal DS is provided to a signal node  310  to which an input buffer  320  is coupled to receive and buffer a DS signal. Further illustrated in  FIG. 3  is an input/output buffer  380  coupled to a signal node  370  to which a complementary write data strobe signal DS# is applied to buffer and provide internally the DS# signal. The input/output buffer  380  further receives an internal non-data signal ND, which is buffered and provided to the signal node  370 . An input/output buffer  360  coupled to a signal node  350  to which a data inversion signal (DI) or error correction signal (EC) is applied. An internal complementary QS# signal is buffered and output externally on the signal node  350  by the input/output buffer  360 . 
     Although the DI, EC signals may not be present in all implementations,  FIG. 3  illustrates an embodiment where differential data strobe signals are utilized and at least one of the data strobe signals is combined with a non-data signal that is not used during the operation that the respective strobe signal is used. The signal that is combined with the data strobe signal may also not include a preamble and/or postamble portion but may allow overall turnaround time reduction over combining QS and DS. The signal that is combined with the data strobe signal has a direction relative to the memory that is the opposite that of the data strobe signal. Operation of the embodiment illustrated in  FIG. 3  is similar to the operation of the embodiments illustrated in  FIG. 1 , with the additional operation of the input/output buffers associated with the complementary data strobe signals. Although not specifically described herein, operation of the embodiment illustrated in  FIG. 3  would be understood by those ordinarily skilled in the art based on the description previously provided. 
       FIG. 4  illustrates a portion of input and output signal nodes for a memory according to an embodiment of the invention. In contrast to the previously described embodiments that included at least one data strobe signal combined with a non-data signal,  FIG. 4  illustrates an embodiment in which two non-data signals are combined to be provided from and receive by the memory at a signal node  410 . In the particular embodiment of  FIG. 4 , an input/output buffer  420  is coupled to receive a data mask signal DM at the signal node  410  and provide an internal DM signal responsive thereto. The input/output buffer  420  further receives and buffers an internal output data valid signal QV to be provided from the signal node  410 . In other embodiments, other non-data signals may be combined at a signal node, such as signal node  410 . Although not specifically described herein, operation of the embodiment illustrated in  FIG. 4  would be understood by those ordinarily skilled in the art based on the description previously provided. 
       FIG. 5  illustrates a portion of a memory  500  according to an embodiment of the present invention. The memory  500  includes an array  502  of memory cells, which may be, for example, DRAM memory cells, SRAM memory cells, flash memory cells, or some other types of memory cells. The memory system  500  includes a command decoder  506  that receives memory commands through a command bus  508  and generates corresponding control signals within the memory system  500  to carry out various memory operations. The command decoder  506  responds to memory commands applied to the command bus  508  to perform various operations on the memory array  502 . For example, the command decoder  506  is used to generate internal control signals to read data from and write data to the memory array  502 . Row and column address signals are applied to the memory system  500  through an address bus  520  and provided to an address latch  510 . The address latch then outputs a separate column address and a separate row address. 
     The row and column addresses are provided by the address latch  510  to a row address decoder  522  and a column address decoder  528 , respectively. The column address decoder  528  selects bit lines extending through the array  502  corresponding to respective column addresses. The row address decoder  522  is connected to word line driver  524  that activates respective rows of memory cells in the array  502  corresponding to received row addresses. The selected data line (e.g., a bit line or bit lines) corresponding to a received column address are coupled to a read/write circuitry  530  to provide read data to a data output buffer  534  via an input-output data bus  540 . Write data are applied to the memory array  502  through a data input buffer  544  and the memory array read/write circuitry  530 . 
     An input/output buffer  550  is configured to receive internal signals, and buffer and provide the same externally. The input/output buffer  550  is further configured to receive a signal, and buffer and provide an internal signal responsive thereto according to an embodiment of the invention. Examples of such signals include data strobe signals S and non-data signals ND. For example, in some embodiments the input/output buffer  550  receives an internal read data strobe signal and provides the same externally, and the input/output buffer  550  further receives an externally provided data mask signal and provides an internal data mask signal for use with write data. In other embodiments, other types of signals may be handled by the input/output buffer  550  as well. 
     From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. Accordingly, the invention is not limited except as by the appended claims.