Patent Publication Number: US-6710629-B2

Title: Impedance comparison integrator circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The disclosure relates to an impedance comparison integrated circuit, and more particularly to an impedance comparison integrated circuit for interfacing a sensed signal of a capacitive touch sensor. 
     2. Description of the Related Art 
     In general, an impedance comparator detects variation of capacitance induced between a user and an electrode when the user&#39;s approaching the impedance comparator, detects minute variation of resistance induced by variation of an external environment such as variation of humidity, or detects variation of inductance. Also, the impedance comparator may detect variation of complex impedance. 
     Recently, switches for an LCD monitor have been changed from a conventional push switch type to a touch switch type as. 
     In the touch switch type switch, electrodes are installed in a front cover of the touch switch product, the switch senses variation of capacitance induced between the electrodes and user when the user touches around the electrodes, and the switch transfers the sensed signal to a microprocessor or a microcomputer etc. 
     Accordingly, the front cover becomes thicker according as home appliances becomes larger, the capacitance of the touch switch decreases, and the sensed capacitance value has very minute variation, so that there is required a more precise detection of capacitance variation. 
     In addition, many countries have restricted power consumption of home appliances, especially power consumption in a standby state. 
     According to the conventional impedance comparison method, a measurement capacitor used for measurement is charged and discharged by current, the frequency or time of the charging and the discharging operation is measured, and the capacitance value is compared by comparing the measured frequency or time with a reference frequency of reference time. In the conventional impedance comparison method, there exist errors of voltage comparator, reference voltage errors of the charging and discharging operation and time delay errors of the switch that controls the charging and discharging operation, so that these errors lead to very large measurement errors of impedance variation. 
     FIG. 1 is a circuit diagram showing a conventional impedance comparison circuit for touch switch. 
     Referring to FIG. 1, according to the conventional impedance comparison circuit, a current source and a measurement capacitor to be measured are connected to each other, the charged voltage level charged in the measurement capacitor and the discharged voltage level discharged from the capacitor are compared by means of voltage comparators (U 1 A, U 1 B), and capacitance difference is measured by detecting the charging and discharging frequencies or charging time. 
     For the purpose of comparing the charged voltage in the reference capacitor (CA) with that of the measurement capacitor (CB), an upper reference voltage (VCH) and an lower reference voltage (VCL) is generated at the comparators (U 1 A, U 1 B), are applied to a non-inverting terminal (VIN+) of the comparators, and the charging and discharging control switch should be controlled by logic circuits when the charging and discharging operations is finished. 
     The input offset error V   —     offset  of the comparators (U 1 A, U 1 B) causes an comparison error of the comparators. Also, reference voltage error V ref     —     diff  is generated in both comparators (U 1 A, U 1 B) because different voltages (VCH, VCL) are applied to the comparators (U 1 A, U 1 B), so that the sensed output frequency has errors. 
     Also, a difference of time (Tcs), which is taken to begin the charging operation, between a reference circuit and a measurement circuit is generated because of a basic transmission delay and a difference of transmission path, so that output errors increase. 
     Accordingly, the final output error (T   —     out     —     err ) is shown as follows. 
     
       
           T     —     out     —     err ∝2 ×V     —     offset +4 ×V   ref     —     diff +2 ×Tcs   Expression 1 
       
     
     According to another conventional impedance comparison circuit that has a voltage comparator (or inverter) and compares the frequency or charging time for the purpose of measuring capacitance variation, there is generated an output error similar to the expression 1. Therefore, in order to use a capacitance comparator with a high precision, another adjustments are required, and manufacturing cost increases. Power consumption of the comparator increases because current source for charging operation is in a turn-on state during the charging and discharging operation. 
     BRIEF SUMMARY OF THE INVENTION 
     The present invention provides an impedance comparison integrated circuit for detecting impedance variations with a high precision. 
     The present invention provides an impedance comparison integrated circuit having minimized power consumption. 
     In one aspect of the invention, there is provided an impedance comparison integrated circuit comprising: a current mirror means for providing current to a first input terminal and a second input terminal, respectively, during a first interval of every period; a discharging means for providing a discharging path to the first and the second input terminals, respectively, during a second interval of the every period; a differential amplification means for performing a differential amplification on signals input from the first and the second input terminals, respectively, during the first interval of the every period; and a first output means for outputting a first output signal to the first output terminal in response to the differential amplification means. 
     The current mirror means comprises: a first current source for generating an output current corresponding to a reference current provided by a bias resistor; a current sink section for providing a sink current corresponding to the output current of the first current source; and a second current source for providing currents to the first and the second input terminals, respectively, in response to the sink current. 
     The current mirror means further comprises a mode switching means, the mode switching means maintaining the current sink section a turn-on state in a high precision mode, turning on the current sink section during the first interval of the every period in the normal mode, and turning off the current sink section during the second interval of the every period in the normal mode. 
     The current mirror means minimizes a parasitic impedance difference of the integrating circuit for the first and second input terminals, and minimizes power consumption. 
     The first output means comprises: a first current sink means for providing a first sink current to a first node in response to the first differential amplified current signal; a second current sink means for providing a second sink current to a second node in response to the second differential amplified current signal; a current source coupled between the first node and a second node; and a capacitor coupled to the first node, for charging a current provided to the first node. Accordingly, the capacitor of the first output means prevents the chattering of the output signal. 
     The impedance comparison integrated circuit further comprises: a buffer means for buffering an output signal of the capacitor; a schmitt trigger means for performing a schmitt triggering operation on an output signal of the buffer means; and a second output means for outputting an output signal of the schmitt trigger means to a second output terminal. 
     The buffer means comprises: a first buffer coupled to the first node, for buffering the first output signal; and a second buffer coupled to the second node, for compensating a current loss of the first node due to the first buffer. 
     The first output means comprises: a first driving means for providing a sink current corresponding to the first differential amplified current signal to the first output terminal in a normal mode, the first driving means providing the sink current corresponding to the first differential amplified current signal to the first output terminal during the first interval of the every period in a high precision mode, and the first driving means providing a source current corresponding to the first differential amplified current signal to the first output terminal during the second interval in the high precision mode; and a second driving means for providing a source current corresponding to the second differential amplified current signal to the first output terminal in the normal mode, the second driving means providing the source current corresponding to the second differential amplified current signal to the first output terminal during the first interval of the every period in the high precision mode, and the second driving means providing a sink current corresponding to the second differential amplified current signal to the first output terminal during the second interval in the high precision mode. 
     The impedance comparison integrated circuit further comprises: a clock generating means for generating a clock signal having a predetermined period; a timing control means for receiving the clock signal and generating a timing control signal having a first interval and a second interval; a control input terminal for receiving an external control signal which selects the normal mode and the high precision mode; and a mode control signal generating means for generating a mode control signal base on the external control signal and the timing control signal so as to control the normal mode and the high precision mode. The normal mode begins when the control input terminal is connected to a pull up circuit and the control input terminal is left in a floating state. Also, the high precision mode begins when the control input terminal is connected to a pull down circuit and the control input terminal is left in a floating state. 
     The first input terminal and the second input terminal is disposed symmetrically with respect to a power terminal in a package so as to minimize a difference of parasitic impedance between the first input terminal and the second input terminal. 
     In another aspect, there is provided an impedance comparison integrated circuit package having an impedance comparison integrated circuit chip, wherein one chip or even number of chips is packaged in a body, first input pins and first output pins of at least one first chips is arranged in a first side of the package, second input pins and second output pins of at least one second chips corresponding to the first chips is arranged in a second side of the package. 
     The first and the second input pins are disposed symmetrically with respect to at least one pins in the first and second side of the package, or are disposed parallel. 
     In further aspect, there is provided a touch switch. The touch switch comprises: a case having a cubic shape, a horizontal supporting plate being disposed in the case, a lower space section formed on a lower surface of the horizontal supporting plate, and a upper space section formed on a upper surface of the horizontal supporting plate; a printed circuit board mounted on the horizontal supporting plate, the printed circuit board having a plurality of external lead lines projected toward the lower space section through the horizontal supporting plate, and an impedance comparison integrated circuit chip being mounted on the printed circuit board; a conductive elastic terminal installed on the printed circuit board, and projected toward the upper space section; and a insulating substrate installed on the case, the insulating substrate having a lower electrode layer and a upper electrode layer, the lower electrode layer being formed on a lower surface of the insulating substrate and being electrically connected to the conductive elastic terminal, and the upper electrode being formed on a upper surface of the insulating substrate and being externally touchable. 
     Preferably, a conductive elastic body is coupled to the upper electrode layer, a conductive pole is coupled to a center of the upper electrode layer, and the conductive pole is covered with a conductive rubber cap. 
     In further aspect, there is provided touch switch comprising: a case having a cubic shape, a horizontal supporting plate being disposed in the case, a lower space section formed on a lower surface of the horizontal supporting plate, and a upper space section formed on a upper surface of the horizontal supporting plate; a printed circuit board mounted on the case, the printed circuit board having a plurality of external lead lines projected toward the lower space section through the horizontal supporting plate, and an impedance comparison integrated circuit chip being mounted on a lower surface of the printed circuit board; and a electrode layer formed on the printed circuit board, and being electrically connected to the impedance comparison integrated circuit chip. 
     According to the impedance comparison integrated circuit of the present invention, a reference impedance device and a comparison impedance device are externally connected to the chip of the impedance comparison integrated circuit, currents are provided by means of current mirrors under same parasitic impedance conditions in the chip. Therefore, the input offset error of the differential amplification circuit is minimized to detect capacitance variation of about 0.01 pF. 
     Also, impedance variations are detected periodically, current consumption is minimized while sensing operation is not performed, so that a low current consumption, for example about 70 microamperes, can be accomplished. 
     The touch switch of the present invention minimize errors due to external parasitic impedance, provide impedance comparison with a high precision, can be easily installed, is strong against water and moisture and has a long life time due to a tightly sealed structure especially when used as a switch of home appliances 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the accompanying drawings, in which: 
     FIG. 1 is a circuit diagram showing a conventional impedance comparison circuit for touch switch; 
     FIG. 2 is a circuit diagram showing an impedance comparison integrated circuit according to one exemplary embodiment of the present invention; 
     FIG. 3 is a concrete circuit diagram showing a clock generator of FIG. 2; 
     FIG. 4 is a graph showing a waveform for the clock generator and a timing control signal generating circuit in FIG. 2; 
     FIG. 5 is a circuit diagram showing a timing control signal generating circuit of FIG. 2; 
     FIG. 6 is a circuit diagram showing a mode control signal generating circuit of FIG. 2; 
     FIG. 7 is a concrete circuit diagram showing a current mirror circuit, differential amplification circuit and a discharge circuit of FIG. 2; 
     FIG. 8 is a concrete circuit diagram showing a first output circuit, a schmitt trigger circuit and a second output circuit of FIG. 2; 
     FIG. 9 is a timing chart illustrating an operation of the impedance comparison integrated circuit of FIG. 2; 
     FIG. 10 is a circuit diagram showing an impedance comparison integrated circuit according to another exemplary embodiment of the present invention; 
     FIG. 11 is a circuit diagram showing a timing control signal generating circuit of FIG. 10; 
     FIG. 12 is a graph showing a waveform for the timing control signal generating circuit of FIG. 11; 
     FIG. 13 is a circuit diagram showing a mode control signal generating circuit and a first output circuit of FIG. 10; 
     FIG. 14 is a timing chart illustrating an operation of the impedance comparison integrated circuit of FIG. 10; 
     FIG. 15 is a circuit diagram showing a circuit for preventing chattering of digital output signal when comparing capacitive impedance; 
     FIG. 16 is a circuit diagram showing a circuit for outputting analog instantaneous signal when comparing capacitive impedance; 
     FIG. 17 is a circuit diagram showing a circuit for preventing chattering of digital output signal when comparing resistive impedance; 
     FIG. 18 is a circuit diagram showing a circuit for outputting analog instantaneous signal when comparing resistive impedance; 
     FIG. 19 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 5 pins is mounted in a package; 
     FIG. 20 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 6 pins is mounted in a package; 
     FIG. 21 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 8 pins is mounted in a package; 
     FIG. 22 is a block diagram showing various combinations of pin arrangement when two impedance comparison integrated circuits each having 8 pins are mounted in a package; 
     FIG. 23 is a block diagram showing various combinations of pin arrangement when four impedance comparison integrated circuits each having 14 pins are mounted in a package; 
     FIG. 24 is a block diagram showing layout of line pattern in a printed circuit board on which 2 impedance comparison integrated circuits each having 8 pins; 
     FIG. 25 is a sectional view of the touch screen module having the impedance comparison integrated circuit according to a preferred embodiment of the present invention; 
     FIG. 26 is a plane view of FIG. 25; 
     FIG. 27 is a bottom view of FIG. 25; 
     FIG. 28 is a sectional view showing a variation of the combined structure between a conductive elastic body and a upper electrode layer of FIG. 25; 
     FIG. 29 is a sectional view of the touch screen module having the impedance comparison integrated circuit according to another preferred embodiment of the present invention; 
     FIG. 30 is a circuit diagram of the touch screen module having the impedance comparison integrated circuit according to a preferred embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Embodiment 1 
     FIG. 2 is a circuit diagram showing an impedance comparison integrated circuit according to one exemplary embodiment of the present invention. 
     Referring to FIG. 2, the impedance comparison integrated circuit  100  includes a input terminal  10  for inputting an external control signal, a first input terminal  12 , a second input terminal  14 , a first output terminal  16 , a second output terminal  18 , a first power terminal  20  and a second power terminal  22 . Each of the first input terminal  12  and the second input terminal  14  is connected to an external electrical device with an external impedance, for example a capacitor (CA), and an external electrical device with a sensing impedance, for example a capacitor (CB). A driving voltage VCC is applied to the first power terminal  20 , and the second power terminal is connected to a ground. 
     The impedance comparison integrated circuit  100  includes a clock generator  110 , a control signal generating circuit  120 , a timing control signal generating circuit  122 , a mode control signal generating circuit  124 , a current mirror circuit  140 , a discharge circuit  150 , a differential amplification circuit  160 , a first output circuit  170 , an integrating circuit  180 , a buffer circuit  190 , a schmitt trigger circuit  200  and a second output circuit  210 . 
     FIG. 3 is a concrete circuit diagram showing a clock generator of FIG. 2, and FIG. 4 is a graph showing a waveform for the clock generator and a timing control signal generating circuit in FIG.  2 . 
     Referring to FIG. 3, the clock generator  110  includes an oscillating circuit  112  and D-flip flop ( 114 ,  116 ). The oscillating circuit  112  includes bipolar transistors (Q 1 ˜Q 5 ), a capacitor (C 1 ) and resistors (R 1 ˜R 7 ), and generates a clock signal (CLK) of FIG.  4 . 
     The oscillating circuit  112  generates a bias current through a resistor (R 1 ) and transistors (Q 1 ˜Q 5 , Q 14 ), and charges or discharges the capacitor (C 1 ) by means of the charge-discharge circuit comprised of the capacitor (C 1 ) and transistors (Q 6 ˜Q 8 ). A waveform of a voltage signal applied between both ends of the capacitor (C 1 ) is transformed into a pulse shape through a wave shaping circuit, for example a schmitt trigger circuit comprised of transistors (Q 9 ˜Q 13 ) and resistors (R 3 ˜R 6 ), and a signal of the pulse shape is outputted as a clock signal (CLK) through a resistor (R 7 ) and transistor (Q 15 ). 
     A D-flip flops ( 114 ,  116 ) receive the clock signal and each D-flip flop generates a two-dividend signal (a signal with ½ frequency of the clock frequency) (FQ 1 ) and a four-dividend signal (a signal with ¼ frequency of the clock frequency) (FQ 2 ) of FIG. 4, respectively. 
     The control signal generating circuit  120  includes a timing control signal generating circuit  122  and a mode control signal generating circuit  124 . 
     FIG. 5 is a circuit diagram showing a timing control signal generating circuit of FIG.  2 . 
     Referring to FIG. 5, the timing control signal generating circuit  122  receives the clock signal (CLK), two-dividend signal (FQ 1 ) and four-dividend signal (FQ 2 ), and generates a timing control signal (T 1 , T 2 ) of FIG.  4 . An AND gate (XG 1 ) of the timing control signal generating circuit  122  receives the two-dividend signal (FQ 1 ) and four-dividend signal (FQ 2 ), and generates a first timing control signal (T 1 ). The first timing control signal (T 1 ) has an active interval of a high level for one clock period and a non-active interval of a low level for three clocks period. An inverter (XG 2 ) inverts the first timing control signal (T 1 ) into a second timing control signal (T 2 ). 
     FIG. 6 is a circuit diagram showing a mode control signal generating circuit of FIG.  2 . 
     Referring to FIG. 6, the mode control signal generating circuit  124  includes an AND gate (XG 3 ). The AND gate (XG 3 ) receives an external control signal (CTR) and the T 2  signal, and generates an internal control signal (CTR 1 ) 
     FIG. 7 is a concrete circuit diagram showing a current mirror circuit, differential amplification circuit and a discharge circuit of FIG.  2 . 
     Referring to FIG. 7, the current mirror circuit  140  includes resistors (R 8 , R 9 ) and transistors (Q 16 ˜Q 25 ). The current mirror circuit  140  generates a reference current by means of R 8 , Q 16 , Q 17  and Q 18 , and provides a same current to both a node N 1  and node N 2  by means of a first current mirror (Q 19 , Q 20 ) and a second current mirror (Q 22 , Q 23 , Q 25 ). The current mirror circuit  140  operates in response to the internal control signal (CTR 1 ) inputted through R 9  and Q 21 . 
     In case of a normal mode in which CTR is high level, the current mirror circuit  140  operates to provide currents during a low level interval of T 2 , the current mirror circuit  140  dose not operate and does not provide currents during a high level interval of T 2 . In case of the normal mode, the current mirror circuit  140  operates for only one clock period among four clocks period, and does not operate for the rest three clocks period to minimize power consumption. 
     However, in case of a high precision mode in which CTR is low level, the current mirror circuit  140  operates regardless of a state of T 2 . 
     The discharge circuit  150  includes resistors (R 10 ˜R 13 ) and transistors (Q 26 , Q 29 ). Q 26  and Q 29  maintain turn-off state in response to the T 2  signal for one clock period in which the T 2  signal has a low level, and provide the current supplied from the current mirror circuit  140  to the input terminals ( 12 ,  14 ). Q 26  and Q 29  maintain turn-on state for three clocks period in which the T 2  signal has a high level, and discharge the charge in the nodes N 1  and N 2  to the ground. Resistors R 12  and R 13  has an appropriate resistance to prevent abrupt discharging current when discharge operation occurs. 
     The differential amplification circuit  160  includes transistors (Q 24 , Q 27 , Q 28 ), compares a voltage difference between the node N 1  and the node N 2 , outputs currents lo_ 1  and lo_ 2  to which the voltage difference are reflected. 
     FIG. 8 is a concrete circuit diagram showing a first output circuit, a schmitt trigger circuit and a second output circuit of FIG.  2 . 
     Referring to FIG. 8, the first output circuit  170  includes transistors (Q 29 ˜Q 34 ). 
     A current mirror (Q 29 , Q 30 , Q 30 A) provides a node N 3  with a current corresponding to the current lo_ 2 , a current mirror (Q 31 , Q 32 ) provides a node N 4  with a current corresponding to the current lo_ 1 . A current mirror (Q 33 , Q 34 ) provides a current to nodes N 3  and N 4 . 
     The integrating circuit  180  includes a capacitor (C_LPF) connected between the node N 3  and the ground. Accordingly, a voltage corresponding to a difference between the lo_ 1  and lo_ 2  is charged in the capacitor (CLPF). The node N 3  is connected to the first output terminal  16 , and outputs an instantaneous anolog voltage signal that is charged in the capacitor (C_LPF). 
     The buffer circuit  190  includes transistors (Q 35 ˜Q 44 ) and resistors (R 14 ˜R 17 ). A first buffer  192  includes transistors (Q 35 ˜Q 38 ) and resistors (R 14 ˜R 15 ), and a second buffer  194  includes transistors (Q 39 ˜Q 42 ) and resistors (R 16 ˜R 17 ). The first buffer  192  and the second buffer forms an emitter follow having high impedance. Preferably, the capacitor (CLPF) is designed to have small capacitance so as to reduce a chip area occupied by the capacitor (C_LPF). However, when a capacitor (C_LPF) of small capacitance is used, it is possible that the voltage of the capacitor (C_LPF) varies due to a loading of the buffer because small charges are charged in the capacitor (C_LPF). 
     The first buffer  192  is a dummy buffer for buffering the node N 4  so as to compensate the signal loss in the node N 3  when signals are buffering by the second buffer  194 . Accordingly, sensing error due to the buffering is minimized. 
     The schmitt trigger circuit  200  includes transistors (Q 45 ˜Q 50 ) and resistors (R 18 ˜R 22 ). The schmitt trigger circuit  200  transforms a sensed signal buffered by the second buffer  194  to a digital signal based on a high reference signal of resistors (R 18 , R 19 , R 20 ) and a low reference signal of resistors (R 18 , R 19 ). 
     The second output circuit  210  includes transistors (Q 51 ˜Q 57 ) and resistors (R 23 ). The transistors (Q 51 ˜Q 54 ) and resistors (R 23 ) provide a bias current. A cascade connected inverter includes Q 55  and Q 56 , and Q 57  with an open collector is connected to the second output terminal  18 . A signal from the second output terminal is a digital sensed signal that reflects a change of impedance of an input device in a microcomputer or microprocessor, and the digital sensed signal is provided to the microcomputer or microprocessor. 
     An external capacitor can be connected to the first output terminal  16  so as to prevent the chattering of the digital signal output to the second output terminal  18 . Hereinafter, an operation of one exemplary embodiment of the present invention is described. 
     The current mirror circuit  140  provides current to the input terminals ( 12 ,  14 ) through, respectively, parasitic impedance Zs 1  and Zs 2 . Each parasitic impedance Zs 1  and Zs 2  is designed to have a same impedance. 
     Each input terminal of the two input terminals of a chip is arranged to be a mirror input terminal so that a pad capacitance of each input terminal is the same and a length of wiring of each input terminal is the same. Also, each input terminal uses a same bonding of a chip, and each input terminal uses a same bonding of a lead. Accordingly, a parasitic capacitance of each input terminal is the same to each other, a parasitic resistance of each input terminal is the same to each other, and a parasitic inductance of each input terminal is the same to each other. 
     Also, each input terminal uses a printed circuit board with a same wiring so as to have same impedance between a measurement point and a reference impedance point. The current mirror circuit  140  provides same current (Is) to each reference impedance (Z_ref) and measurement impedance (Z_test). The reference impedance (Z_ref) and measurement impedance (Z_test) are connected to each of the input terminals ( 12 ,  14 ) through lines with same condition. Accordingly, input impedance of each nodes (N 1 , N 2 ) is expressed as the following. 
     
       
           Z in 1 = Z ref+ Zs   1   Expression 2 
       
     
     
       
           Z in 2 = Z test+ Zs   2   Expression 3 
       
     
     The current mirror circuit  140  maintains turn-on state, as shown in FIG. 9, during t 1  clock period of T 2  generated from the control signal generating circuit  120 , and maintains turn-off state during t 2 ˜t 4  clocks period. Also, the discharge circuit  150  maintains turn-on state during t 2 ˜t 4  clocks period of T 2 , and maintains turn-off during t 1  clock period. 
     The differential amplification circuit  160  maintains turn-on state, and maintains turn-off state to have no input current during t 2 ˜t 4  clocks period. Specifically, The current ‘Is’ charges the parasitic impedances (Zs 1 , Zs 2 ) and the external impedances (Z_ref, Z_test) during t 1  clock period, and current charged in the input impedance is discharged during t 2 ˜t 4  clocks period. 
     Also, the current mirror circuit  140  and the differential amplification circuit  160  maintains turn-off state to reduce consumption of power during t 2 ˜t 4  clocks period, so that an output current of the differential amplification circuit  160  does not flow into the differential amplification circuit  160  during t 2 ˜t 4  clocks period. 
     An input voltage is generated in the differential amplification circuit  160  by current input into the input impedance during t 1  clock period. The input voltage has a voltage difference proportional to the difference between Zin 1  and Zin 2 , and is amplified to generate the output current of the differential amplification circuit  160 . 
     The Zs 1  and Zs 2  have the same impedance, and Zin 1  is equal to (Zref+Zs 1 ) and Zin 2  is equal to (Ztest+Zs 2 ), so that the Zs 1  and Zs 2  do not cause the input voltage difference because. 
     The input impedance can be expressed by means of capacitive impedance as the following. 
     
       
           V in=1 /C×Is dt   Expression 4 
       
     
     
       
           V in= Is×t   1 ×1 /C   Expression 5 
       
     
     
       
           C=C in+ Cs   Expression 6 
       
     
     The ‘Cs’ influences an incremental gradient of the ‘Vin’, but does not influence inversion of the differential value because the ‘Vin’ of the differential amplification circuit  160  is equal to (Vin 1 −Vin 2 ). 
     An impedance difference error due to the parasitic capacitance is not generated because ‘t 1 ’ has a period long enough to prevent occurrence of an effect of the parasitic impedance. 
     The differential amplification circuit  160  receives the input voltage, and outputs the output current of the differential amplification circuit  160 . The output current (lo) is proportional to the difference between Zin 1  and Zin 2 . 
     
       
           lo=Gm+V in ( Gm :transconductance of the differential amplification circuit  160 )  Expression 7 
       
     
     The output current (lo) is sensed by an analogue output voltage signal (Vo) through an external resistor Ro nected to the first output terminal  16 . 
       Vo   —   A=lo×Ro   Expression 8 
     Also, the output current (lo) is integrated by the capacitor (C_LPF) for a plurality of t 1  periods, and is sensed by an digital output voltage (Vo_D) through a buffer ( 192 ,  194 ) with high impedance, the schmitt trigger circuit  200  and the second output circuit  210 . The digital output voltage (Vo_D) is output through an open drain (or open collector), so that each digital output voltage of a plurality of the impedance comparison integrated circuits according to the present invention is easily transformed to an analogue output signal by using a resistor ladder. DC output voltage of the resistor ladder is applied to an input terminal of the microcomputer, so that the number of input terminals of the microcomputer can be minimized. 
     Also, the current mirror circuit  140  and differential amplification circuit  160  is turned on during t 1  period by the second timing control T 2 , so that current consumption can be minimized to be not greater than about 70 μm. While the differential amplification circuit  160  is turned off, current does not flow through the differential amplification circuit  160 , so that the integrating circuit  180  holds a value of the integrating circuit  180  when the t 1  period ends. 
     Current is provided to the capacitor (C_LPF) of the integrating circuit  180  only during t 1  period, the capacitance of the capacitor (C_LPF) is reduced by t 1 /(t 1 +t 2 +t 3 +t 4 ), so that a chip area occupied by the capacitor (C_LPF) can be minimized in a chip design. 
     The analogue output voltage signal (Vo_A) has a peak voltage corresponding to a maximum voltage of the input voltage (Vin), which is applied between the two input terminals ( 12 ,  14 ) of the differential amplification circuit  160  during t 1  period and reflects the difference between two input terminals ( 12 ,  14 ) by repeating the above mentioned procedure periodically. When large current ‘Is’, compared with the input impedance, is provided and charged voltages (V N1 , V N2 ) increase to an applied voltage (Vc), the current mirror circuit  140  operates at a saturation region of transistor for a early ‘t 11 ’ period of ‘t 1 ’ period, so that the current mirror circuit  140  stops to supply current. 
     As shown in FIG. 9, the power consumption is normal only during ‘t 11 ’ period, and is very low during ‘t 12 ’ period. Also, the differential amplification circuit  160  reaches about turn-off state because the input voltage of the differential amplification circuit  160  is about the applied voltage (Vc), so that the power consumption of the current mirror circuit  140  and the differential amplification circuit  160  is small enough to be disregarded. Accordingly, the power consumption of the impedance comparison integrated circuit  100  can be minimized. 
     Also, when external resistor Ro is increased infinitely, the output of the integrating circuit  180  reaches a threshold voltage of the shmitt trigger circuit  200  according as the clock signal (CLK) repeats periodically. Then, the output voltage Vo_D of the second output terminal  18  is changed into a high or low level according to the size of the Zin 1  and Zin 2 . 
     The error of the differential amplification circuit  160  includes a V discharge  error due to a discharging voltage V discharge  and an input offset error of the differential amplification circuit  160 . The V discharge  error is due to the V discharge  generated through the Zin 1  and Zin 2  during t 2 ˜t 4 . The error of the differential amplification circuit  160  is reduced greatly compared with the conventional error. 
     The discharge operation begins through the input impedance during t 2 ˜t 4 , no error is generated when the discharge operation begins because the differential amplification circuit  160  is in a turn-off state before the discharge operation begins. When the discharge operation is completed and charging operation begins, an charging delay error, which is generated because the beginning of charging operation is delayed, may be disregarded due to starting delay of charging operation because one clock sends the same charging starting signals. 
     Accordingly, the error, V offset     —     error , of the impedance comparison integrated circuit  100  is expressed as below. 
     
       
         
           V 
           out 
           
             — 
           
           error 
           =V 
           discharge 
           
             — 
           
           error 
           +V 
           offset 
           
             — 
           
           error 
         
       
     
     Embodiment 2 
     FIG. 10 is a circuit diagram showing an impedance comparison integrated circuit according to another exemplary embodiment of the present invention. 
     Referring to FIG. 10, the impedance comparison integrated circuit  100  according to another embodiment of the present invention has the same circuits as that according to one embodiment of the present invention except a control signal generating circuit  130  and a first output circuit  175 . The same reference numerals are used for the same circuit, and explanation is omitted. 
     The control signal generating circuit  130  includes a timing control signal generating circuit  132  and a mode control signal generating circuit  134 . 
     FIG. 11 is a circuit diagram showing a timing control signal generating circuit of FIG. 10, and FIG. 12 is a graph showing a waveform for the timing control signal generating circuit of FIG.  11 . 
     Referring to FIG. 11, the timing control signal generating circuit  132  receives the clock signal (CLK), two-dividend signal (FQ 1 ) and four-dividend signal (FQ 2 ), and generates a timing control signal (T 1 , T 2 , T 3 , T 4 , TA, TB) of FIG.  12 . 
     The timing control signal generating circuit  132  generates a delayed clock signal (DCLK 1 ) through a first delay circuit comprised of inverters (G 1 , G 2 ) and capacitor (C 2 ). An AND gate (G 4 ) of the timing control signal generating circuit  132  receives the two-dividend signal (FQ 1 ) and four-dividend signal (FQ 2 ), and performs an AND operation on the FQ 1  and FQ 2  signals to generate a first timing control signal (T 1 ). The first timing control signal (T 1 ) has an active interval of a high level for one clock period and a non-active interval of a low level for three clocks period. An inverter (G 5 ) inverts the first timing control signal (T 1 ) into a second timing control signal (T 2 ). An AND gate (G 3 ) receives DCLK 1  and T 1  signals, and performs an AND operation on the DCKL 1  and T 1  signals to output a timing control signal (TA) at every 4-clock period that has the same duty ratio as that of the clock signal (CLK). 
     The timing control signal generating circuit  132  generates a delayed clock signal (DCLK 2 ) through a second delay circuit comprised of inverters (G 6 , G 7 ) and capacitor (C 3 ). An NOR gate (G 9 ) of the timing control signal generating circuit  132  receives the two-dividend signal (FQ 1 ) and four-dividend signal (FQ 2 ), and performs an NOR operation on the FQ 1  and FQ 2  signals to output a third timing control signal (T 3 ). The third timing control signal (T 1 ) is a phase-delayed signal by 3 clock periods compared with the T 1  signal. An AND gate (G 8 ) receives DCKL 3  and T 3  signals, and performs an AND operation on the DCKL 3  and T 3  signals to output a timing control signal (TB) that has a high level for one clock period at every 4-clock period. The TB signal is a phase-delayed signal by 3 clock periods compared with the TA signal. 
     The XOR gate (G 10 ) receives FQ 1  and FQ 2  signals, and performs an exclusive OR operation on the FQ 1  and FQ 2  signals to output an EX signal. The AND gate (G 11 ) performs an AND operation on the T 2  signal in response to the control signal (CTR). Accordingly, T 2  signal is output in case of the normal mode and a low level signal is output in case of the high precision mode. The OR gate (G 12 ) outputs selectively an output signal (EX 2 ) of G 11  gate or the EX signal. Accordingly, T 4  signal is the T 2  signal in case of the normal mode, and is the EX signal in case of the high precision mode. 
     FIG. 13 is a circuit diagram showing a mode control signal generating circuit and a first output circuit of FIG.  10 . 
     Referring to FIG. 13, the mode control signal generating circuit  134  includes gates (G 13 ˜G 22 ). The external control signal maintains a high level in the normal mode, and maintains a low level in the high precision mode. 
     The AND gate (G 13 ) outputs the T 2  signal as an internal control signal (CTR 1 ) in the normal mode, and the CTR 1  signal maintains a low level in the high precision mode. 
     Accordingly, the current mirror circuit  140  and the differential amplification circuit  160  is turned on during a T 2  period, and maintains turn-off states during the T 2 ˜T 4  periods. However, the differential amplification circuit  160  maintains always turn-on state. 
     The discharge circuit  150  discharges during T 2 ˜T 4  periods because the T 4  signal is provided as the T 2  signal in the normal mode, and discharges only during T 2  and T 3  periods because the T 4  signal is provided as the EX signal. 
     Gates G 19  and G 20 , respectively, receive a low level signal at their input port in the normal mode because the CTR signal is in the high level, so that the TA and TB signals are not output through the gates G 19  and G 20  in the normal mode. Also, the T 2  signal is not output through a gate G 15 . An output of a gate G 15  is maintained at a low level, so that an output of a gate G 17  has a low level and an output of a gate G 18  has a high level. 
     Accordingly, an output of a gate G 21  maintains a low level state and an output of a gate G 22  maintains a high level state. 
     Outputs of Gates G 17  and G 18 , respectively, has a low level in the high precision mode because the CTR signal is in the low level, and TA and TB signals are output through the gates G 19  and G 20  in the high precision mode. 
     The first output circuit  175  includes a first driver circuit  175 A and a second driver circuit  175 B. 
     The first driver circuit  175 A includes transistors (M 11 ˜M 11 ), and the second driver circuit  175 B includes transistors (M 12 ˜M 22 ). 
     In the normal mode, the first mode control signal maintains a low level, the second mode control signal maintains a high level, and the M 4  of the first driver circuit  175 A is turned off, so that the M 3 , M 5 , M 10  and M 11  maintains turn-on state. Also, in the normal mode, the M 8  maintains turn-off state, the M 3 , M 5 , M 10  and M 11  maintains turn-on state, M 8  maintains turn-on state, and the M 7  and M 9  is turned off, so that the first driver circuit  175 A provides pull down current that discharges the capacitor C-LPF in response to the second current lo_ 2 . 
     In the normal mode, the M 19  of the second driver circuit  175 B is turned off, the M 18  and M 20  maintains turn-on state, the M 15  maintains turn-on state, the M 14  and M 16  is turned off, so that the second driver circuit  175 B provides pull up current that charges the capacitor C-LPF in response to the first current lo_ 1 . 
     Accordingly, in the normal mode, the capacitor C-LPF is discharged for one clock period, the charged voltage of the capacitor C-LPF is held for three clock periods, and repeats the charging and holding operations for the next clock period. 
     FIG. 14 is a timing chart illustrating an operation of the impedance comparison integrated circuit of FIG.  10 . 
     Referring to FIG. 14, in the high precision mode, the TA signal is provided as a first mode control signal, and the TB signal is provided as a second mode control signal. 
     The M 8  and M 15  is turned off while the TA signal is in a high level, and the M 4  and M 19  maintains a turn-on state, so that the M 7 , M 9 , M 14  and M 16  are turned on. Accordingly, the first driver circuit  175 A provides pull up current, which charges the capacitor C-LPF in response to the second current lo_ 2 , through the M 1 , M 6 , M 7  and M 9 . Also, the second driver circuit  175 B provides pull up current, which charges the capacitor C-LPF in response to the second current lo_ 1 , through the M 11 , M 13 , M 14 , M 16 , M 21  and M 22 . Accordingly, the capacitor C-LPF is charged by a current difference between the pull current and the pull down current. 
     While the TA and TB signals have both low level, the M 4 , M 8 , M 15  and M 19  are turned on, and the outputs of the first and second driver circuit is maintained as a high level state, so that the voltage of the capacitor C-LPF is maintained as the last voltage state of the charging period. 
     While the TB signal has a high level, the M 4  and M 19  are turned off, and the M 8  and M 15  maintains turn-on state, so that the M 3 , M 5 , M 18  and M 20  is turned on. Accordingly, compared with the current path formed by the TA signal with a high level, a current path is formed in an opposite direction when the TB signal has a high level. In other words, the first driver circuit  175 A provides pull down current, which discharges the capacitor C-LPF in response to the second current lo_ 2 , through the M 1 , M 2 , M 3 , M 5 , M 10  and M 11 . Also, the second driver circuit  175 B provides pull up current, which charges the capacitor C-LPF in response to the second current lo_ 1 , through the M 12 , M 17 , M 18  and M 20 . The first and second currents (lo_ 1 , lo_ 2 ) has only the input offset error of the differential amplification circuit  160  and the V discharge  error due to the discharging voltage V discharge  when input signals through the first and second input terminal ( 12 ,  14 ) are excluded, and only the error signal charged on the capacitor (C-LPF) is discharged through the opposite current path, so that only the input signals are remained. Accordingly, impedance sensing with high precision is possible since error signals are removed from the input signals and only the input signals are sensed. 
     In addition, in the high precision mode, the charging and discharging periods is set to be Ta and Tb, respectively, shorter than t 1  period, so that the inflow of the error signals is minimized at the rising edge and falling edge in on/off operations. This has the purpose of removing the errors of integrated current due to the delay of the discharging periods of the t 2  and t 3  since the differential amplification circuit  160  is in a turn-on state during the charging and discharging period. 
     The integrating circuits according to the embodiments of the present invention can be designed by means of bipolar transistors or MOS transistors. Preferably, the buffer circuit is designed by means of MOS transistor since the buffer circuit can be designed by using only one MOS transistor to have more simple circuit configuration compared with the buffer circuit designed by using bipolar transistors. 
     FIG. 15 is a circuit diagram showing a circuit for preventing chattering of digital output signal when comparing capacitive impedance. 
     Referring to FIG. 15, an capacitor (C 1 ) is connected to an input terminal (in+), and an capacitor (C 2 ) is connected to an input terminal (in−). A capacitor (C 3 ) for preventing chattering is connected to an output terminal (OUT 1 ), and an external power voltage (VDD) terminal is connected through a pull up resistor Rd to an output terminal (OUT 2 ). 
     FIG. 16 is a circuit diagram showing a circuit for outputting analog instantaneous signal when comparing capacitive impedance. 
     Referring to FIG. 16, compared with FIG. 15, a pull down resistor Ra, instead of the capacitor (C 3 ), is connected to the output terminal (OUT 1 ) to output an analog out signal. 
     FIG. 17 is a circuit diagram showing a circuit for preventing chattering of digital output signal when comparing resistive impedance. 
     Referring to FIG. 17, compared with FIG. 15, resistor R 1  and R 2 , instead of the capacitor C 1  and C 2 , are connected to the input terminals in+ and in−, respectively. 
     FIG. 18 is a circuit diagram showing a circuit for outputting analog instantaneous signal when comparing resistive impedance. 
     Referring to FIG. 18, compared with FIG. 16, resistor R 1  and R 2 , instead of the capacitor C 1  and C 2 , are connected to the input terminals in+ and in−, respectively. 
     FIG. 19 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 5 pins is mounted in a package. The first output terminal  16  and the input terminal  10  are not connected to an external pin to be in a floating state. The first input (IN_A) pin and the second input (IN_B) pin are disposed to be symmetric each other with respect to a VDD pin or a GND pin, disposed to be symmetric each other at edge portions of the package, or disposed apart each other at edge portions of the package. These configurations of the input pins (IN_A, IN_B) minimize the parasitic capacitance of the input pins (IN_A, IN_B) or minimize the input errors by providing the same condition, so that exact sensing is made. 
     FIG. 20 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 6 pins is mounted in a package. The input terminal  10  is not connected to an external pin to be in a floating state. The first input (IN_A) pin and the second input (IN_B) pin are disposed in the same way as those mentioned above. 
     FIG. 21 is a block diagram showing various combinations of pin arrangement when an impedance comparison integrated circuit having 8 pins is mounted in a package. The input terminal  10  is not connected to an external pin to be in a floating state. 
     FIG. 22 is a block diagram showing various combinations of pin arrangement when two impedance comparison integrated circuits each having 8 pins are mounted in a package. The first output terminal  16  and the input terminal  10  are not connected to an external pin to be in a floating state. When a plurality pair of input pins (IN 1 _A, IN 1 _B; or IN 2 _A, IN 2 _B) exist in a package, the plurality pair of input pins are disposed to be opposite to each other in the package, the plurality pair of input pins are disposed parallel to each other at a portion of the package, or power pin or output pin are disposed between the plurality pair of input pins. 
     FIG. 23 is a block diagram showing various combinations of pin arrangement when four impedance comparison integrated circuits each having 14 pins are mounted in a package. The first output terminal  16  and the input terminal  10  are not connected to an external pin to be in a floating state. Each chips of two impedance comparison integrated circuits is disposed in a package. The pins of each chip are separated each other with respect to the power pin or the GND pin at a portion of the package. 
     FIG. 24 is a block diagram showing layout of line pattern in a printed circuit board on which 2 impedance comparison integrated circuits each having 8 pins. According to the line pattern of FIG. 24, the difference of the parasitic impedance is minimized, so that more precise impedance comparison is possible. 
     Hereinafter, there is described the detailed configurations of the touch screen module having the impedance comparison integrated circuit according to a preferred embodiment of the present invention. 
     FIG. 25 is a sectional view of the touch screen module having the impedance comparison integrated circuit according to a preferred embodiment of the present invention, FIG. 26 is a plane view of FIG. 25, and FIG. 27 is a bottom view of FIG.  25 . 
     The touch screen  300  of a preferred embodiment of the present invention includes a case  302  having a cubic shape. A horizontal supporting plate  304  is disposed in the case  302 . Accordingly, a first space section  306  is formed from a lower surface of the horizontal supporting plate  304  to lower edges of the case  302 , and a second space section  308  is formed from a upper surface of the horizontal supporting plate  304  to upper edges of the case  302 . The first and second space sections ( 306 ,  308 ) reduce the effect of the parasitic capacitance. 
     Three holes  310  for lead lines are arranged in series on the horizontal supporting plate  304 . A chip  313  of impedance comparison integrated circuit is mounted on the printed circuit board (PCB,  312 ), and is electrically connected to three lead lines ( 314   a ,  314   b ,  314   c ; hereinafter referred to  314 ). Also, a conductive elastic body is installed on the chip  313 . The lead lines are comprised of a driving voltage (VCC) lead line  314   a , a ground voltage lead line  314   b  and an output lead line  314   c . The output lead line is disposed outermost compared other lead lines. 
     The three lead lines  314  are inserted through the holes  310 , projected toward lower side of the case  302 , and mounted on the horizontal supporting plate  304 . 
     Preferably, the chip  313  is mounted without being packaged thereon, and the second space section  308  is filled with a mold resin to be sealed completely. 
     A lower electrode layer  320  and an upper electrode layer  322  are formed on an insulating substrate  318 . Accordingly, the insulating substrate  318  acts as a dielectric layer between the lower and upper electrode layers ( 320 ,  322 ) to form a capacitor. 
     The insulating substrate  318  is mounted on a recess  324  formed on a upper edge, is combined by ultrasonic fusion welding, and to seal tightly inside of the case  302 . 
     When the insulating substrate  318  is mounted thereon, the lower electrode layer  320  is electrically connected to the conductive elastic body  316 . An elasticity of the conductive elastic terminal  316  can be adjusted to be electrically well contacted to the lower electrode layer  320 . 
     A conductive elastic body  326  is attached on the upper electrode layer  322 . The conductive elastic body  326  allows the upper electrode layer  322  to be tightly contacted with an external switch electrode, so that the upper electrode layer  322  is electrically connected to the external switch electrode. 
     FIG. 28 is a sectional view showing a variation of the combined structure between a conductive elastic body and an upper electrode layer of FIG.  25 . 
     Referring to FIG. 28, a conductive electrode pole  323  is coupled with a central portion of the upper electrode layer  322 , the conductive electrode pole  323  is covered with a conductive rubber cap  327 . Accordingly, the conductive rubber cap  327  is closely contacted with the conductive electrode pole  323  corresponding to the variation of dimension of the conductive electrode pole  323 , and can easily standardize components to enhance productivities. Also, according to the variation of the combined structure, conductive contact can be maintained even when external vibration is applied thereon, shock can be well absorbed, abrasion due to friction is little, and the corrosion of the electrode pole  323  can be prevented. A conductive cap can be used instead of the conductive rubber cap. 
     FIG. 29 is a sectional view of the touch screen module having the impedance comparison integrated circuit according to another preferred embodiment of the present invention. 
     Referring to FIG. 29, according to the touch switch module of another preferred embodiment of the present invention, there is provided a structure where the insulating substrate  318  is removed, and the touch switch module functions as a PCB  312  and the insulating substrate  318 . A chip  313 , lead lines  314  and a capacitor  328  are mounted on the lower surface of the PCB  312 , an electrode layer  312  is formed on the upper surface of the PCB  312 , and the electrode layer  312  is connected to an end of the capacitor  328 . The PCB  312  is mounted on the recess  324 , is combined by ultrasonic fusion welding, and to seal tightly inside of the case  302 . 
     A conductive elastic body  326  is attached on the electrode layer  322 . The conductive elastic body  326  allows the electrode layer  322  to be tightly contacted with an external switch electrode, so that the electrode layer  322  is electrically connected to the external switch electrode. 
     FIG. 30 is a circuit diagram of the touch screen module having the impedance comparison integrated circuit according to a preferred embodiment of the present invention. 
     Referring to FIG. 30, a second output pin (OUT-D) is connected to a output lead line  314   c , a ground pin (GND) is connected to a ground voltage lead line  314   b , and the power pin (VDD) is connected to a power voltage lead line  314   a . A conductive elastic terminal  316  or the electrode layer  322  is connected to the inverting input pin (IN−) through a resistor XR 2  and a capacitor XC 5 . The resistor XR 2  and a capacitor XC 5  restrict the size of an external input current, or protect internal circuits of the chip  313  from static electricity. 
     The first output pin (OUT-A) is connected to the ground through a capacitor XC 3  reduces noise such as chattering at a second output pin (OUT-D). 
     The non-inverting input pin (IN+) is connected to the ground through a capacitor XC 4 . The capacitor XC 4  has a first capacitance greater than the capacitor XC 5  connected to the inverting input pin (IN−) when the capacitor XC 4  is not touched as a reference capacitor, but the capacitor XC 4  has a second capacitance smaller than the capacitor XC 5  when the capacitor XC 4  is touched as the reference capacitor. Preferably, the capacitance of the capacitor XC 4  is an intermediate value between the first and second capacitances. 
     The devices externally connected to the chip  313  can be mounted in the case  302  or outside of the case  302 . 
     This invention has been described with reference to the exemplary embodiments. It is evident, however, that many alternative modifications and variations will be apparent to those having skill in the art in light of the foregoing description. Accordingly, the present invention embraces all such alternative modifications and variations as fall within the spirit and scope of the appended claims. 
     For example, although above preferred embodiments discuss the impedance comparison integrated circuit designed by means of bipolar transistors, the impedance comparison integrated circuit could also be designed by means of MOS transistor to perform the same function. If the MOS transistor is used to design the impedance comparison integrated circuit, the first output circuit could be designed simply by one MOS transistor due to input characteristics of the MOS transistor. 
     Also, many alternative modifications and variations can be made for the combined structure of the conductive elastic body of the touch screen module.