Patent Publication Number: US-10762958-B2

Title: Resistive memory device including a reference cell and method of controlling a reference cell to identify values stored in memory cells

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0118843, filed on Sep. 15, 2017, and Korean Patent Application No. 10-2018-0020006, filed on Feb. 20, 2018, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. 
     BACKGROUND 
     The inventive concept relates to a resistive memory device, and more particularly, to a resistive memory device including a reference cell and a method of controlling the reference cell. 
     Resistive memory devices may store data in memory cells including variable resistance elements. To detect the data stored in the memory cells of the resistive memory devices, for example, a read current may be provided to the memory cells. A voltage, generated due to the read current and the variable resistance elements of the memory cells, may be detected. 
     In the memory cells storing certain values, resistances of the variable resistance elements may have distributions that may vary according to a process voltage temperature (PVT) and the like. To accurately read the values stored in the memory cells, it may be important to accurately and promptly set a threshold resistance that may be used to distinguish distributions of resistances that respectively correspond to different values. 
     SUMMARY 
     The inventive concept provides a resistive memory device, and more particularly, a resistive memory device that is capable of accurately reading values stored in memory cells by controlling a reference cell and a method of controlling the reference cell. 
     According to an aspect of the inventive concept, there is provided a method of controlling a reference cell included in a resistive memory to identify values stored in a plurality of memory cells. The method includes writing a first value to the plurality of memory cells, providing, to the reference cell, reference currents that monotonically increase or monotonically decrease, reading the plurality of memory cells as each of the reference currents is provided to the reference cell, and determining a read reference current based on results of the reading. 
     According to another aspect of the inventive concept, there is provided a method of controlling a reference cell in a resistive memory to identify values stored in a plurality of memory cells. The method includes writing a first value to the plurality of memory cells, setting monotonically increasing or monotonically decreasing resistances of a reference resistor connected to the reference cell and through which a reference current passes, reading the plurality of memory cells under each of resistances of the reference resistor; and determining a read reference resistance based on results of the reading. 
     According to another aspect of the inventive concept, there is provided a resistive memory device that is configured to receive a reference adjustment signal. The resistive memory device includes a cell array including a memory cell and a reference cell. The memory cells are connected to respective first source lines and respective first bit lines, and the reference cell is connected to a second source line and a second bit line The resistive memory device includes a current source circuit configured to provide a read current and a variable reference current respectively to the memory cells and the reference cell via the first source lines or the second source line. The resistive memory device includes an amplification circuit configured to detect voltages between the first source lines connected to the memory cells and second source line connected to the reference cell, and a control circuit configured to control the current source circuit such that the reference current may be adjusted regardless of the read current, in response to the reference adjustment signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a block diagram illustrating a memory device and a controller, according to example embodiments; 
         FIG. 2  is a timing diagram illustrating an example of communication between the memory device and the controller of  FIG. 1 , according to an example embodiment; 
         FIG. 3  is a diagram illustrating an example of a memory cell illustrated in FIG.  1 , according to example embodiments; 
         FIG. 4  is a graph showing distribution of resistances provided by the memory cell illustrated in  FIG. 3 , according to example embodiments; 
         FIGS. 5A and 5B  are block diagrams showing examples of the memory device of  FIG. 1 , according to example embodiments; 
         FIG. 6  is a circuit diagram showing an example of a current source circuit illustrated in  FIG. 1 , according to example embodiments; 
         FIGS. 7A and 7B  are circuit diagrams showing examples of a reference resistor circuit illustrated in  FIG. 1 , according to example embodiments; 
         FIG. 8  is a flowchart showing a method of controlling a reference cell, according to example embodiments; 
         FIGS. 9A and 9B  are flowcharts showing examples of operations S 200  through S 600  shown in  FIG. 8 , according to example embodiments; 
         FIG. 10  is a flowchart showing an example of operation S 800  shown in  FIG. 8 , according to example embodiments; 
         FIG. 11  is a graph showing an example of an operation of determining a threshold resistance by operation S 800   a  shown in  FIG. 10 , according to example embodiments; 
         FIG. 12  is a flowchart showing an example of operation S 800   b  shown in  FIG. 8 , according to example embodiments; 
         FIG. 13  is a graph showing an example of an operation of determining a threshold resistance by the operation S 800   b  shown in  FIG. 12 , according to example embodiments; 
         FIG. 14  is a block diagram showing a memory device according to example embodiments; and 
         FIG. 15  is a block diagram showing a system-on-chip including the memory device according to example embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     It is noted that aspects of the inventive concept described with respect to one embodiment, may be incorporated in a different embodiment although not specifically described relative thereto. That is, all embodiments and/or features of any embodiment can be combined in any way and/or combination. These and other objects and/or aspects of the present inventive concept are explained in detail in the specification set forth below. 
       FIG. 1  is a block diagram illustrating a memory device  100  and a controller  200  according to an example embodiment, and  FIG. 2  is a timing diagram showing an example of communication between the memory device  100  and the controller  200  of  FIG. 1 , according to an example embodiment. 
     Referring to  FIG. 1 , the memory device  100  may communicate with the controller  200 . The memory device  100  may receive a command CMD such as a write command, a read command, and/or an address ADDR from the controller  200 , and may receive data DATA (that is, write data) from the controller  200  and/or transmit data DATA (that is, read data) to the controller  200 . In addition, as illustrated in  FIG. 1 , the memory device  100  may receive a reference adjustment signal ADJ from the controller  200 . Although the command CMD, the address ADDR, the data DATA, and the reference adjustment signal ADJ are separately illustrated in  FIG. 1 , in some embodiments, at least two of the command CMD, the address ADDR, the data DATA, and/or the reference adjustment signal ADJ may be transmitted via a same channel. As illustrated in  FIG. 1 , the memory device  100  may include a cell array  110 , a current source circuit  120 , a reference resistor circuit  130 , an amplification circuit  140 , a control circuit  150 , and/or a non-volatile memory (NVM)  160 . As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expressions such as “at least one of,” when preceding a list of elements, modify the entire list of elements and do not modify the individual elements of the list. 
     The cell array  110  may include a plurality of memory cells M. A memory cell M may include a variable resistance element (for example, a magnetic tunnel junction (MTJ) illustrated in  FIG. 3 ). The variable resistance element may have a resistance corresponding to a value stored in the memory cell M. Accordingly, the memory device  100  may be referred to as a resistive memory device, resistive random access memory (RRAM) (or ReRAM), and so on. For example, as a non-limited example, the memory device  100  may include a cell array  110  having a structure such as phase change random access memory (PRAM) or ferroelectric random access memory (FRAM), or a cell array having a magnetic random access memory (MRAM) structure, for example, spin transfer torque-magnetic random access memory (STT-MRAM), spin transfer torque magnetization switching RAM (Spin-RAM), and spin momentum transfer RAM (SMT-RAM). As will be described with reference to  FIG. 3 , example embodiments will be mainly described with reference to MRAM, but it should be noted that the example embodiments are not limited thereto. 
     The cell array  110  may include a reference cell R used for identifying values stored in the memory cells M. For example, as illustrated in  FIG. 1 , the cell array  110  may include the plurality of memory cells M and the reference cell R commonly connected to a word line WLi, and accordingly, the plurality of memory cells M and the reference cell R, which are commonly connected to the word line WLi, may simultaneously be selected by the word line WLi that is activated. Although only one reference cell R is illustrated in  FIG. 1 , in some embodiments, the cell array  110  may include more than two reference cells connected to the word line WLi. 
     The current source circuit  120  may provide a read current I_RD and a reference current I_REF to the cell array  110 . For example, the current source circuit  120  may provide the read current I_RD to the memory cells M, and provide the reference current I_REF to the reference cell R. The current source circuit  120  may also adjust the reference current I_REF in response to a current control signal CC received from the control circuit  150 . An example of the current source circuit  120  will be described with reference to  FIG. 6 . 
     The reference resistor circuit  130  may provide resistors through which the reference current I_REF passes. For example, the reference resistor circuit  130  may provide resistors having a reference resistance R_REF between a first node N 1  and a second node N 2 . In addition, the reference resistor circuit  130  may adjust the reference resistance R_REF according to a resistance control signal RC received from the control circuit  150 . The resistors of the reference resistor circuit  130  may have a characteristic different from a characteristic of one or more resistors formed in the cell array  110 . In some embodiments, the resistors of the reference resistor circuit  130  may have a characteristic of being better, for example, more insensitive to process voltage temperature (PVT) changes, than one or more of the resistors formed in the cell array  110 . Examples of the reference resistor circuit  130  will be described with reference to  FIGS. 7A and 7B . It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, elements should not be limited by these terms; rather, these terms are only used to distinguish one element from another element. Thus, a first element discussed below could be termed a second element without departing from the scope of the present inventive concepts. 
     The amplification circuit  140  may receive a read voltage V_RD and a reference voltage V_REF, and may, based on the read voltage V_RD and the reference voltage V_REF, identify the values stored in the memory cells M. For example, by comparing the read voltage V_RD to the reference voltage V_REF, the amplification circuit  140  may output signals corresponding to the values stored in the memory cells M. The read voltage V_RD may include a voltage drop caused due to the read current I_RD, which is provided by the current source circuit  120 , passing through the variable resistance elements included in the memory cells M. The read voltage V_RD may, besides the voltage drop caused due to the memory cells M, further include a voltage drop generated due to parasitic resistance (for example, a column decoder  170   a , a source line SLj, and a bit line BLj illustrated in  FIG. 5A ) of paths through which the read current I_RD passes. 
     Similarly to the read voltage V_RD, the reference voltage V_REF may include not only a voltage drop, which is generated as the reference current I_REF provided by the current source circuit  120  passes through the reference cell R, but also a voltage drop generated by parasitic resistance (for example, the column decoder  170   a , a short source line SSL, and a short bit line SBL illustrated in  FIG. 5A ) of paths through which the reference current I_REF passes. In addition, the reference voltage V_REF may further include a voltage drop generated due to the reference resistance R_REF provided by the reference resistor circuit  130 . Accordingly, by controlling the reference current I_REF and the reference resistance R_REF of the reference resistor circuit  130 , the reference voltage V_REF may be adjusted, and a reference for identifying the values stored in the memory cells M may also be adjusted. In some embodiments, the reference resistance of a reference resistor may be monotonically increasing or monotonically decreasing. In particular, the reference resistance may be a monotonically increasing resistance that is repeatedly stepped-up during multiple read or write cycles. In some embodiments, the reference resistance may be a monotonically decreasing resistance that is repeatedly stepped-down during multiple read or write cycles. This monotonically increasing or decreasing reference resistance may be a stair-step sequence of resistance or a linear ramp-shaped sequence of resistance, for example. 
     As described with reference to  FIG. 5A  and subsequent figures, in some embodiments, the reference cell R may be a shorted cell that does not include a resistor element such as a variable resistance element. Accordingly, the reference voltage V_REF, due to a characteristic of the reference resistor circuit  130 , may be insensitive to PVT changes. As will be described with reference to  FIG. 8  and subsequent figures, when the reference voltage V_REF is accurately determined, the operation reliability of the memory device  100  may be increased. 
     The control circuit  150  may, by using the current control signal CC and the resistor control signal RC, respectively control the current source circuit  120  and the reference resistor circuit  130 , and/or access the NVM  160 . In some embodiments, the control circuit  150  may generate the current control signal CC and the resistor control signal RC, in response to a reference adjustment signal ADJ received from the controller  200 . For example, based on the reference adjustment signal ADJ, the control circuit  150  may increase or decrease the reference current I_REF and increase or decrease the reference resistance R_REF of the reference resistor circuit  130 . Consequentially, a reference voltage V_REF may be adjusted in response to the reference adjustment signal ADJ provided by the controller  200 . 
     In some embodiments, to adjust the reference voltage V_REF, one of the reference current I_REF or the reference resistance R_REF of the reference resistor circuit  130  may be fixed. For example, when the reference current I_REF is fixed, the control circuit  150  may not generate the current control signal CC and adjust the reference resistance R_REF of the reference resistance circuit  130 , by using the resistor control signal RC, according to the reference adjustment signal ADJ. On the other hand, when the reference resistance R_REF of the reference resistor circuit  130  is fixed, the control circuit  150  may not generate the resistor control signal RC and may adjust the reference current I_REF, by using the current control signal CC, according to the reference adjustment signal ADJ. 
     The NVM  160  may store data regarding the reference voltage V_REF. For example, the NVM  160  may store data regarding a read reference current, which is a reference current used for reading data from the memory cells M, and data regarding a read reference resistor, which is a reference resistor used for reading data from the memory cells M. For example, control data corresponding to the read reference current may be written to the resistive memory. In some embodiments, the control circuit  150  may, in response to a command CMD that commands setting of a reference voltage V_REF (or a setting command) received from the controller  200 , write data regarding the reference voltage V_REF to the NVM  160 , and in response to a command CMD controlling a read operation of data (or a read command), generate a current control signal CC and a resistance control signal RC according to the data stored in the NVM  160 . In some embodiments, the NVM  160  may be omitted. For example, at least some of the memory cells M included in the cell array  110  may store data regarding the reference voltage V_REF and be accessed by the control circuit  150 . 
     The controller  200  may include a reference trimmer  210 . The reference trimmer  210  may adjust the reference voltage V_REF of the memory device  100  by using the reference adjustment signal ADJ. Based on results of reading data from the memory cells M according to the adjusted reference voltage V_REF, the reference trimmer  210  may help determine the reference voltage V_REF, which may be a read reference voltage to be used for reading data from the memory cells M. 
     In some embodiments, the reference adjustment signal ADJ may be synchronized with the read command READ. That is, the reference adjustment signal ADJ may occur at the same time, overlapping in time as the read command READ, or preceded or followed by the read command READ, to be provided to the memory device  100 . For example, as illustrated in  FIG. 2 , the controller  200  may, by using the command CMD, the address ADDR, and the reference adjustment signal ADJ, provide the read command READ, a first address A 1 , and a first option OP 1  to the memory device  100  beginning at time t 1 . The control circuit  150  of the memory device  100  may generate the current control signal CC and the resistance control signal RC according to the first option OP 1 , and accordingly, the reference current I_REF and the reference resistance R_REF of the reference resistor circuit  130  may be determined. According to the read command READ, memory cells M and the reference cell R corresponding to the first address A 1  may be selected. Also, by a read voltage V_RD according to the memory cells M and a reference voltage V_REF according to the reference resistance R_REF of the reference resistor circuit  130 , values stored in the memory cells M may be identified. The identified values may, via data DATA, be provided to the controller  200  as first output OUT 1 . Similarly, at time t 2 , in response to the read command READ, a second address A 2 , and a second option OP 2  of the controller  200 , the memory device  100  may provide a second output OUT 2  to the controller  200 . In some embodiments, unlike shown in  FIG. 2 , the reference adjustment signal ADJ may be synchronized with an exclusive command, which is a command different from the read command READ, and be provided to the memory device  100 . 
     In some embodiments, according to reference voltages that monotonically increase or decrease, the reference trimmer  210  may read data from the plurality of memory cells to which predetermined values are written, and determine a read reference voltage, based on results of reading. In particular, the reference voltage may be a monotonically increasing voltage that is repeatedly stepped-up during multiple read or write cycles. In some embodiments, the reference voltage may be a monotonically decreasing voltage that is repeatedly stepped-down during multiple read or write cycles. This monotonically increasing or decreasing reference voltage may be a stair-step sequence of voltages or a linear ramp-shaped sequence of voltages, for example. 
     As described above, by controlling the reference cell R, an accurate threshold resistance of the memory cells M may be induced, as it will be described later, and values stored in the memory cells M may be accurately read. In addition, as the accurate threshold resistance is promptly detected, improved productivity of the memory device  100  may be provided, and according to an operation environment of the memory device  100 , adaptive calibration may be provided. 
       FIG. 3  is a drawing showing an example of the memory cell M of  FIG. 1 , according to an example embodiment, and  FIG. 4  is a graph illustrating distributions of resistances provided by the memory cell M illustrated in  FIG. 3 , according to some example embodiments. Referring now to  FIG. 3 , a memory cell M′ including a magnetic tunnel junction (MTJ) element as a variable resistance element is illustrated.  FIG. 4  shows distributions of resistances for the MTJ element configured as the variable resistance element of  FIG. 3 . 
     As shown in  FIG. 3 , the memory cell M′ may include the variable resistance element (MTJ element) and a cell transistor CT serially connected between a bit line BLj and a source line SLj. In some embodiments, as shown in  FIG. 3 , between the bit line BLj and the source line SLj, the variable resistance element (MTJ element) and the cell transistor CT may be connected in the order of the variable resistance element (MTJ element) and the cell transistor CT. In some embodiments, unlike shown in  FIG. 3 , between the bit line BLj and the source line SLj, the variable resistance element (MTJ element) and the cell transistor CT may be connected in the order of the cell transistor CT and the variable resistance element (MTJ element). 
     The variable resistance element (MTJ element) may include a free layer FL and a pinned layer PL, and a barrier layer BL between the free layer FL and the pinned layer PL. As marked with arrows in  FIG. 3 , while a magnetization direction of the pinned layer PL may be fixed, the free layer FL may have a magnetization that is equal to or opposite to the magnetization direction of the pinned layer PL. When the pinned layer PL and the free layer FL have identical magnetization directions, the variable resistance element (MTJ element) may be referred to be in a parallel state P. On the other hand, when the pinned layer PL and the free layer FL have magnetization directions different from one another, the variable resistance element (MTJ element) may be referred to be in an anti-parallel state AP. In some embodiments, the variable resistance element (MTJ element) may further include an anti-ferromagnetic layer so that the pinned layer PL may have a fixed magnetization direction. 
     The variable resistance element (MTJ element), which may have a low resistance R P  in the parallel state P, may have a high resistance R AP  in the anti-parallel state AP. In the specification, it is assumed that when the variable resistance element (MTJ element) has a low resistance R P  the memory cell M′ stores ‘0’, and when the variable resistance element (MTJ element) has a high resistance R AP , the memory cell M′ stores ‘1’. Also, in the specification, the resistance R P  corresponding to ‘0’ may be referred to as a parallel resistance R P , and the resistance R AP  corresponding to ‘1’ may be referred to as an anti-parallel resistance R AP . However, various embodiments described herein may apply to the opposite storage case as well. 
     Referring to  FIG. 4 , resistances of the variable resistance elements MTJ may have distributions. For example, as shown in  FIG. 4 , there may be a parallel resistance R P  distribution (or a first distribution) between the memory cells storing ‘0’, and there may be an anti-parallel resistance R AP  distribution (or a second distribution) between the memory cells storing ‘1’. In some embodiments, as shown in  FIG. 4 , the anti-parallel resistance R AP  distribution may be degraded, that is, have a higher variance, compared to the parallel resistance R P  distribution. In other words, some values of the higher portion of the parallel resistance R P  distribution may be close to values in a lower portion of the anti-parallel resistance R AP  distribution. Also, as marked with dash lines in  FIG. 4 , due to various causes, the distributions of the resistances of the variable resistance elements (MTJ element) may be degraded. Accordingly, a range of a threshold resistance R TH  for distinguishing the parallel resistance R P  distribution from the anti-parallel resistance R AP  distribution may be reduced, and it may be important to determine an accurate threshold resistance R TH . As it will be described later with reference to  FIGS. 8 through 13 , according to example embodiments, by controlling the reference cell R, distributions of resistances of the variable resistance elements MTJ may be estimated, and based on the estimated distributions, a threshold resistance R TH  may be determined. 
     Referring again to  FIG. 3 , the cell transistor CT may include a gate connected to the word line WLi, a source and a drain respectively connected to the source line SLi and the variable resistance element (MTJ element). The cell transistor CT may, according to a signal applied to the word line WLi, electrically connect or block the variable resistance element (MTJ element) and the source line SLj. For example, in a write operation, to write ‘0’ to the memory cell M′, the cell transistor CT may be turned on, and a current flowing from the bit line BLj to the source line SLj may pass through the variable resistance element (MTJ element) and the cell transistor CT. To write ‘1’ to the memory cell M′, the cell transistor CT may be turned on, and a current flowing from the source line SLj to the bit line BLj may pass through the cell transistor CT and the variable resistance element (MTJ element). In a read operation, the cell transistor CT may be turned on, and a current flowing from the bit line BLj to the source line SLj or a current flowing from the source line SLj to the bit line BLj, that is, the read current I_RD, may pass through the cell transistor CT and the variable resistance element (MTJ element). In various embodiments described herein, it is assumed that the read current I_RD flows from the source line SLj to the bit line BLj. 
       FIGS. 5A and 5B  are block diagrams showing examples of the memory device  100  of  FIG. 1 , according to example embodiments. Referring now to  FIGS. 5A and 5B ,  FIGS. 5A and 5B  respectively show memory devices  100   a  and  100   b  during read operations. In memory devices  100   a  and  100   b , reference resistor circuits  130   a  and  130   b  may be arranged differently from one another. Hereinafter,  FIGS. 5A and 5B  will be described with reference to  FIG. 1 . Among descriptions of  FIGS. 5A and 5B , descriptions overlapping with those of  FIG. 1  are omitted for brevity. 
     Referring to  FIG. 5A , memory device  100   a  may include a cell array  110   a , a current source circuit  120   a , a reference resistor circuit  130   a , an amplification circuit  140   a , and a column decoder  170   a . The cell array  110   a  may include memory cells M and the reference cell R which are connected to the word line WLi in common. Each memory cell M may be connected to a bit line BLj and a source line SLj, and the reference cell R may be connected to a short bit line SBL and a short source line SSL. The bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL may extend to and be connected to the column decoder  170   a.    
     While the memory cell M may include the variable resistance element (MTJ element) and the cell transistor CT that are serially connected between the bit line BLj and the source line SLj, the reference cell R may include the cell transistor CT connected to the short bit line SBL and the short source line SSL. Accordingly, the cell transistor CT of the reference cell R, the short bit line SBL and the short source line SSL may be electrically shorted or opened. The reference cell R that does not include a resistance element may be referred to as a shorted cell. To compensate for a voltage drop caused due to the bit line BLj and the source line SLj connected to the memory cell M, as shown in  FIG. 5A , the reference cell R, which is connected to the short bit line SBL and the short source line SSL, may be arranged as in the cell array  110   a . As shown in  FIG. 5A , the reference cell R may be a shorted cell. Accordingly, a voltage drop caused due to the variable resistance element (MTJ element) of the memory cell M may be compared to a voltage drop caused due to a reference resistor circuit  130   a  arranged outside of the cell array  110   a . Being free from spatial and structural limits of the cell array  110 , the reference resistor circuit  130   a , which is arranged outside of the cell array  110   a , may provide a reference resistance R_REF that has a wide variable range and may be insensitive to PVT and the like, such that reference voltage V_REF may be more accurately adjusted. 
     The column decoder  170   a  may, according to a column address COL, perform routing on the bit line BLj, the source line SLj, the short bit line SBL, and the short source line SSL. The column address COL may be generated due to the address ADDR received from the controller  200  of  FIG. 1 . The column decoder  170   a  may select at least some of the memory cells and the reference cells that are selected according to the activated word line WLi in the cell array  110   a , according to the column address COL. For example, as shown in  FIG. 5A , the column decoder  170   a  may connect the bit line BLj of the memory cell M to a negative supply voltage source VSS, and connect the source line SLj to the current source circuit  120   a . In addition, the column decoder  170   a  may connect the short bit line SBL of the reference cell R to the reference resistor circuit  130   a , and connect the short source line SSL to the current source circuit  120   a . Accordingly, the read current I_RD may pass through the source line SLj, the memory cell M, and the bit line BLj and flow toward the negative supply voltage source VSS. The reference current I_REF may pass through the short source line SSL, the reference cell R, the short bit line SBL, and the reference resistor circuit  130   a , and flow toward the negative supply voltage source VSS. 
     The amplification circuit  140   a  may be connected to nodes through which the read current I_RD and the reference current I_REF are respectively output from the current source circuit  120   a . The amplification circuit  140   a  may generate an output signal Q according to the read voltage V_RD and the reference voltage V_REF at the nodes. While the read voltage V_RD may be determined by a resistance of the variable resistance element (MTJ element) in the memory cell M and the read current I_RD, the reference voltage V_REF may be determined by the reference resistance R_REF and the reference current I_REF. When the read voltage V_RD is higher than the reference voltage V_REF (that is, when a resistance of the variable resistance element (MTJ element) of the memory cell M is greater than a threshold resistance R TH ), the amplification circuit  140   a  may generate an output signal Q corresponding to ‘1’. When the read voltage V_RD is lower than the reference voltage V_REF (that is, when the resistance of the variable resistance element (MTJ element) of the memory cell M is less than the threshold resistance R TH ), the amplification circuit  140   a  may generate an output signal Q corresponding to ‘0’. 
     Referring to  FIG. 5B , the memory device  100   b  may include a cell array  110   b , a current source circuit  120   b , a reference resistor circuit  130   b , an amplification circuit  140   b , and a column decoder  170   b . Compared to the memory device  100   a  of  FIG. 5A , the memory device  100   b  of  FIG. 5B  may optionally further include the reference resistor circuit  130   b  arranged between the column decoder  170   b  and the current source circuit  120   b . Accordingly, the reference current I_REF may pass through the reference resistor circuit  130   b , the short source line SSL, the reference cell R, and the short bit line SBL and flow toward the negative supply voltage source VSS. Hereinafter, example embodiments will be described mainly with reference to cases, like the memory device  100   a  of  FIG. 5A , in which the reference resistor circuit  130   a  is arranged between the reference cell R and the negative supply voltage source VSS, but example embodiments are not limited thereto. 
       FIG. 6  is a circuit diagram showing the current source circuit  120  of  FIG. 1 , according to some example embodiments. As described above with reference to  FIG. 1 , a current source circuit  120 ′ illustrated in  FIG. 6  may generate the read current I_RD and the reference current I_REF, and when n is a positive integer, the current source circuit  120 ′ may adjust the reference current I_REF according to current control signals CC[ 1 :n] of a control circuit  150 ′. 
     Referring to  FIG. 6 , the current source circuit  120 ′ may include a plurality of transistors P 0 , P 1 , P 2  through Pn, Pr having sources connected in common to a positive supply voltage VDD. The plurality of transistors P 0 , P 1 , P 2  through Pn, Pr may be PMOS transistors and form current mirrors. Therefore, according to a current I_ 0  flowing through the transistor P 0  and respective sizes of the plurality of transistors P 0 , P 1 , P 2  through Pn, Pr, a magnitude of a current being withdrawn from the positive supply voltage VDD may be determined. In some embodiments, the transistor P 0  and the transistor Pr may have identical sizes. Accordingly, the read current I_RD may have a magnitude that is substantially identical to a magnitude of the current I_ 0 . 
     The n transistors P 1 , P 2  through Pn generating the reference current I_REF may be respectively and serially connected to n transistors PS 1 , PS 2  through PSn controlled by the current control signals CC[ 1 :n]. The current control signals CC[ 1 :n] may respectively be applied to gates of the n transistors PS 1 , PS 2  through PSn, and thus, by the current control signals CC[ 1 :n], a magnitude of the reference current I_REF may be determined. For example, when the transistor PS 1  is turned on in response to a first current control signal CC[ 1 ] of a low level, a current passing through the transistor P 1  may be included in the reference current I_REF. When the transistor PS 1  is turned off in response to a first current control signal CC[ 1 ] of a high level, the current passing through the transistor P 1  may be excluded from the reference current I_REF. The n transistors P 1 , P 2 , through Pn may have identical sizes in some embodiments and may have different sizes in some embodiments. 
       FIGS. 7A and 7B  are circuit diagrams showing the reference resistor circuit  130  of  FIG. 1 , according to example embodiments. As described with reference to  FIG. 1 , reference resistor circuits  130   a ′ and  130   a ″ of  FIGS. 7A and 7B  may respectively provide a resistor through which the reference current I_REF passes, and when m is a positive integer, in response to resistor control signals RC[ 1 :m] of control circuits  150   a ′ and  150   a ″, a resistance of the resistor, which is the reference resistance R_REF, may be adjusted. The reference resistor circuits  130   a ′ and  130   a ″ of  FIGS. 7A and 7B  may, as described with reference to  FIG. 5A , respectively provide the resistor having the reference resistance R_REF between the short source line SSL and the negative supply voltage source VSS. Hereinafter, among descriptions of  FIGS. 7A and 7B , overlapped descriptions will not be given. 
     Referring to  FIG. 7A , the reference resistor circuit  130   a ′ may, between the short source line SSL and the negative supply voltage source VSS, include a plurality of resistors R 1   a , R 2   a  through Rma, and a plurality of transistors N 1   a , N 2   a  through Nma which are respectively and serially connected to the plurality of resistors R 1   a , R 2   a  through Rma. The resistor control signals RC[ 1 :m] may be applied to gates of the plurality of transistors N 1   a , N 2   a  through Nma, and accordingly, the reference resistance R_REF may be determined by the resistor control signals RC[ 1 :m]. For example, when the transistor N 1   a  is turned on in response to a first resistor control signal RC[ 1 ] of a high level, the reference resistance R_REF may be determined by the first resistor R 1   a ; when the transistor N 1   a  is turned off in response to a first resistor control RC[ 1 ] of a low level, the reference resistance R_REF may be determined regardless of the first resistor R 1   a . Consequentially, the reference resistance R_REF of the reference resistor circuit  130   a ′ may be determined by an equivalent circuit that is made by connecting, in parallel, the resistors selected by the resistor control signals RC[ 1 :m] from among the plurality of resistors R 1   a , R 2   a  through Rma. 
     Referring to  FIG. 7B , the reference resistor circuit  130   a ″ may include a plurality of resistors R 1   b , R 2   b  through Rmb serially connected between the short source line SSL and the negative supply voltage source VSS, and a plurality of transistors N 1   b , N 2   b  through Nmb which are respectively connected in parallel to the plurality of resistors R 1   b , R 2   b  through Rmb. The resistor control signals RC[ 1 :m] may be applied to gates of the plurality of transistors N 1   b , N 2   b  through Nmb, and accordingly, by the resistor control signals RC[ 1 :m], a reference resistance R_REF may be determined. For example, when the transistor N 1   b  is turned off in response to the first resistor control signal RC[ 1 ] of the low level, the reference resistance R_REF includes a resistance of a first resistor R 1   b ; when the transistor N 1   b  is turned on in response to the first resistor control signal RC[ 1 ] of the high level, the reference resistance R_REF, when a turn-on resistance of the transistor N 1   b  is approximately 0, may not include a resistance of the first resistor R 1   b . Consequentially, the reference resistance R_REF of the reference resistor circuit  130   a ″ may be determined by an equivalent circuit that is made by connecting, in series, the resistors selected by the resistor control signals RC[ 1 :m] among the plurality of resistors Rib, R 2   b  through Rmb. 
       FIG. 8  is a flowchart showing a method of controlling the reference cell, according to example embodiments. As illustrated in  FIG. 8 , the method of controlling the reference cell may include a plurality of operations S 200 , S 400 , S 600 , and S 800 . In some embodiments, for controlling the reference cell R included in the memory device  100  of  FIG. 1 , the method described with reference to  FIG. 8  may be performed by the controller  200  including the reference trimmer  210 . Hereinafter,  FIG. 8  will be described with reference to  FIG. 1 . 
     In operation S 200 , an operation of writing identical values to a plurality of memory cells may be performed. For example, an operation of writing ‘0’ or ‘1’ to the plurality of memory cells may be performed. According to the values written to the plurality of memory cells, in the following operation S 400 , a method of controlling a reference voltage may be determined. The example of writing ‘0’ to the plurality of memory cells will be described later with reference to  FIG. 9A , and the example of writing ‘1’ to the plurality of memory cells will be described later with reference to  FIG. 9B . 
     In operation S 400 , an operation of generating reference voltages that monotonically increase or decrease may be performed. For example, in the operation S 200 , when ‘0’ corresponding to the parallel resistance R P  of the variable resistance elements is written to the plurality of memory cells, reference voltages that monotonically increase from a minimum reference voltage may be generated. On the other hand, in the operation S 200 , when ‘1’ corresponding to the anti-parallel resistances R AP  of the variable resistance elements is written to the plurality of memory cells, reference voltages that monotonically decrease from a maximum reference voltage may be generated. 
     In operation S 600 , operations of reading data from the plurality of memory cells under each of the reference voltages may be performed. For example, an operation of reading data from the plurality of memory cells under respective reference voltages that monotonically increase may be performed, or an operation of reading data from the plurality of memory cells under respective reference voltages that monotonically decrease may be performed. The examples of the operations S 200  through S 600  will be described with reference to  FIGS. 9A and 9B . 
     In operation S 800 , an operation of determining a read reference voltage, based on reading results, may be performed. In some embodiments, from results of reading data from the plurality of memory cells to which ‘0’ is written under each of the monotonically increasing reference voltages or monotonically decreasing reference currents, a parallel resistance R P  distribution (or a first distribution) of the variable resistance elements may be estimated. In some embodiments, from results of reading data from the plurality of memory cells to which ‘1’ is written under each of the monotonically decreasing reference voltages or monotonically increasing reference currents, an anti-parallel resistance R AP  distribution (or a second distribution) may be estimated. Based on at least one of the estimated distributions, a threshold resistance R TH  may be determined, from which a read reference voltage may be determined. The examples of the operation S 800  will be described with reference to  FIGS. 10 through 13 . 
       FIGS. 9A and 9B  are flowcharts showing examples of the operations S 200  through S 600  of  FIG. 8 , according to example embodiments. As described above with reference to  FIG. 8 , in operations S 200   a  and S 200   b  of  FIGS. 9A and 9B , the operation of writing identical values to the plurality of memory cells may be performed. In operations S 400   a  and S 400   b , the operation of generating the reference voltages that monotonically decrease or increase may be performed. In operations S 600   a  and S 600   b , the operation of reading data from a plurality of memory cells under each of the reference voltages may be performed. Hereinafter,  FIGS. 9A and 9B  will be described with reference to  FIG. 1  and  FIG. 4 , which shows the distributions of the resistances of the variable resistance elements, and among descriptions of  FIGS. 9A and 9B , overlapped descriptions will be omitted. 
     Referring to  FIG. 9A , in the operation S 200   a , the operation of writing ‘0’ to the plurality of memory cells may be performed. For example, the controller  200  may transmit the command CMD that commands writing, the address ADDR corresponding to the plurality of memory cells, and the data DATA including ‘0’ to the memory device  100 . Accordingly, the plurality of memory cells may have resistances distributed like the parallel resistance R P  distribution of  FIG. 4 . In some embodiments, in the cell array  110 , ‘0’ may be written to the plurality of memory cells connected to one same word line WLi. 
     The operation S 400   a  may include an operation S 420   a  and an operation S 440   a . In the operation S 420   a , an operation of setting a minimum reference current and a minimum reference resistance may be performed. For example, the controller  200  may transmit the reference adjustment signal ADJ, which corresponds to the minimum reference current and the minimum reference resistance, to the memory device  100 . The control circuit  150  of the memory device  100  may, by generating the current control signal CC and the resistor control signal RC in response to the reference adjustment signal ADJ, set the reference current I_REF and the reference resistance R_REF respectively as minimum values. Accordingly, a reference voltage V_REF determined by the reference current I_REF and the reference resistance R_REF may respectively have a minimum value, and a threshold resistance R TH  corresponding to the reference voltage V_REF may be lower than a mean of the parallel resistance R P  distribution. 
     In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set as minimum values. For example, based on variations in the parallel resistance R P  distribution, an arbitrary reference current I_REF and an arbitrary reference resistance R_REF may be set for a reference voltage V_REF corresponding to a threshold resistance R TH  which is lower than the mean of the parallel resistance R P  distribution. As shown in  FIG. 9A , in some embodiments, after the operation S 420   a , an operation S 620   a  may be performed. 
     In operation S 620   a , an operation of reading data from a plurality of memory cells may be performed. For example, the controller  200  may transmit the command CMD, which commands the reading operation, and the address ADDR, corresponding to the plurality of memory cells, to the memory device  100 . In some embodiments, as described above with reference to  FIG. 2 , the command CMD for the read operation and the address ADDR may be synchronized with the reference adjustment signal ADJ for setting the minimum reference current and the minimum reference resistance of the operation S 420   a  and be transmitted to the memory device  100 . The memory device  100  may transmit data DATA including results of reading data from the memory cells to which ‘0’ is written, by using the minimum reference voltage according to the minimum reference current and the minimum reference resistance that have been set, to the controller  200 . 
     In operation S 640   a , based on the number of ‘1’&#39;s included in the result of reading, an operation of determining whether to re-perform the read operation of the plurality of memory cells may be performed. For example, as shown in  FIG. 9A , the reference trimmer  210  of the controller  200  may compare the number of ‘0’s included in the data DATA received from the memory device  100 , which is the number of memory cells from which the stored values are read to be ‘0’, with a preset value ‘X’, (X&gt;0). When the number of ‘0’ is equal to or greater than ‘X’, the operations of setting the reference current and the reference resistance and reading data from the plurality of memory cells may be ceased, and otherwise, the operation S 440   a  may be performed after the operation S 640   a . In other words, until ‘0’ is read from a certain number of memory cells from among the plurality of memory cells to which ‘0’ is written, the operation of setting the reference current I_REF and the reference resistance R_REF and the operation of reading data from the plurality of memory cells may be repeated. In some embodiments, ‘X’ may be equal to the number of the memory cells to which ‘0’ is written, and in some embodiments, ‘X’ may be half the number of the memory cells to which ‘0’ is written. 
     In operation S 440   a , an operation of setting an increased reference current and/or an increased reference resistance may be performed. For example, the controller  200  may transmit a reference adjustment signal ADJ, which corresponds to an increased reference current and/or an increased reference resistance, to the memory device  100 , and the control circuit  150  of the memory device  100  may, by generating a current control signal CC and/or a resistor control signal RC in response to the reference adjustment signal ADJ, set the increased reference current I_REF and the increased reference resistance R_REF. Accordingly, a reference voltage V_REF may also increase, and a threshold resistance R TH  corresponding to the reference voltage V_REF may, from the parallel resistance R P  distribution of  FIG. 4 , move to the right in the graph. 
     When the operations S 440   a  and S 600   a  are repeated, according to a reference voltage V_REF that gradually increases, a threshold resistance R TH  may, from the parallel resistance R P  distribution, move to the right in the graph of  FIG. 4 . Accordingly, as the threshold resistance R TH  moves from the left to the right of the parallel resistance R P  distribution, the parallel resistance R P  distribution may be estimated. After the operation S 600   a , operations of estimating the distributions and determining a read reference voltage from the estimated distributions, such as in examples of the operation S 800  of  FIG. 8 , will be described after with reference to  FIGS. 10 through 13 . 
     Referring to  FIG. 9B , in the operation S 200   b , an operation of writing ‘1’ to the plurality of memory cells may be performed. Accordingly, the plurality of memory cells may have resistances distributed like the anti-parallel resistance R AP  distribution of  FIG. 4 . 
     An operation S 400   b  may include an operation S 420   b  and an operation S 440   b . In the operation S 420   b , an operation of setting a maximum reference current and a maximum reference resistance may be performed. For example, the controller  200  may transmit a reference adjustment signal ADJ, which corresponds to the maximum reference current and the maximum reference resistance, to the memory device  100 , and the control circuit  150  of the memory device  100 . The control circuit  150  may, by generating a current control signal CC and a reference control signal RC in response to the reference adjustment signal ADJ, set maximum values respectively for the reference current I_REF and the reference resistance R_REF. Accordingly, a reference voltage V_REF, which is determined by the reference current I_REF and the reference resistance R_REF, may have a maximum value, and a threshold resistance R TH  corresponding to the reference voltage V_REF may be higher than a mean of the anti-parallel resistance R AP  distribution. 
     In some embodiments, the reference current I_REF and the reference resistance R_REF may not be set as maximal values. For example, based on variations in the anti-parallel resistance R AP  distribution, a reference current I_REF and a reference resistance R_REF may be set for a reference voltage V_REF corresponding to a threshold resistance R TH  which is higher than an average of the anti-parallel resistance R AP  distribution may have. As shown in  FIG. 9B , an operation S 620   b  may be performed after the operation S 420   b.    
     In operation S 620   b , an operation of reading data from the plurality of memory cells may be performed. Accordingly, the memory device  100  may transmit data DATA including results of reading data from the memory cells to which ‘1’ is written by using the maximum reference voltage according to the maximum reference current and the maximum reference resistance to the controller  200 . 
     In operation S 640   b , based on the number of ‘1’ included in the result of reading, an operation of determining whether to re-perform the read operation on the plurality of memory cells may be performed. For example, as shown in  FIG. 9B , the reference trimmer  210  of the controller  200  may compare the number of ‘1’ included in the data DATA received from the memory device  100 , which is the number of memory cells from which the stored values are read to be ‘1’, with a preset value ‘Y’ (Y&gt;0). When the number of ‘1’ is equal to or greater than ‘Y’, the operation of setting the reference current and the reference resistance and the operation of reading data from the plurality of memory cells may be ceased, or otherwise the operation S 440   b  may be performed after the operation S 640   b . In other words, until ‘1’ is read from a preset number of memory cells from among the plurality of memory cells to which ‘1’ is written, the operation of setting the reference current I_REF and the reference resistance R_REF and the operation of reading data from the plurality of memory cells may be repeated. In some embodiments, ‘Y’ may be equal to the number of the memory cells to which ‘1’ is written, and in some embodiments, ‘Y’ may be half the number of the memory cells to which ‘1’ is written. 
     In operation S 440   b , an operation of setting a decreased reference current and/or a decreased reference resistance may be performed. Accordingly, the reference voltage V_REF may also increase, and the threshold resistance R TH  corresponding to the reference voltage V_REF may, from the parallel resistance R P  distribution of  FIG. 4 , move to the right of the graph. 
     When the operations S 440   b  and S 600   b  are repeated, according to a reference voltage V_REF that gradually decreases, a threshold resistance R TH  may, from the anti-parallel resistance R AP  distribution, move to the left. Accordingly, similarly to the embodiment of  FIG. 9A , as the threshold resistance R TH  moves from the right to the left of the anti-parallel resistance R AP  distribution, the anti-parallel resistance R AP  distribution may be estimated. 
       FIG. 10  is a flowchart showing an example of the operation S 800  of  FIG. 8 , according to some example embodiments, and  FIG. 11  is a graph showing an example of an operation of determining a threshold resistance by operation S 800   a  of  FIG. 10 , according to some example embodiments. In detail, the operation S 800   a  of  FIG. 10  may be performed after preparing the threshold resistance R TH  derived from the plurality of memory cells to which ‘0’ is written, as described above with reference to  FIG. 9A , and the threshold resistance R TH  derived from the plurality of memory cells to which ‘1’ is written, as described above with reference to  FIG. 9B . As described above with reference to  FIG. 8 , in the operation S 800   a  of  FIG. 10 , an operation of determining a read reference voltage, based on the results from the read operation under each of the reference voltages, may be performed. 
     In operation S 820   a , an operation of estimating a parallel resistance R P  distribution and an anti-parallel resistance R AP  distribution may be performed. For example, the threshold resistance R TH  derived from the embodiment of  FIG. 9A  may be estimated to be a mean R P ′ of the parallel resistance R P  distribution. In some embodiments, when the number of memory cells to which ‘0’ is written and from which ‘0’ is read is relatively greater, it may be identified whether ‘0’ is read from at least half of the memory cells (that is, when ‘X’ in  FIG. 9  is half the number of the memory cells to which ‘0’ is written). In this case, the threshold resistance R TH  may be estimated to be an average of the parallel resistance R P  distribution. In some embodiments, when the number of memory cells to which ‘0’ is written and from which ‘0’ is read are relatively less, it may be identified whether ‘0’ is read from all of the memory cells (that is, when ‘X’ in  FIG. 9  is equal to the number of memory cells to which ‘0’ is written). In this case, a threshold resistance R TH  may be estimated to be a mean of a parallel resistance R P  distribution. Similarly, the threshold resistance R TH  derived from the embodiment of  FIG. 9B  may be estimated to be a mean R AP ′ of the anti-parallel resistance R AP  distribution. In some embodiments, when the number of memory cells to which ‘1’ is written and from which ‘1’ is read is relatively greater, ‘Y’ in  FIG. 9B  may be half the number of the memory cells to which ‘1’ is written. In some other embodiments, when the number of memory cells to which ‘1’ is written and from which ‘1’ is read is relatively less, ‘Y’ in  FIG. 9B  may be equal to the number of memory cells to which ‘1’ is written. Accordingly, as shown in  FIG. 11 , by the operation S 820   a , locations of the parallel resistance R P  distribution and the anti-parallel resistance R AP  distribution may be estimated by the mean R P ′ of the parallel resistances R P  and the average R AP ′ of the anti-parallel resistances R AP . As described above, by estimating the means, the distributions of the resistances may be promptly estimated. 
     In operation S 840   a , an operation of calculating a threshold resistance R TH  from the parallel resistance R P  distribution and the anti-parallel resistance R AP  distribution may be performed. In some embodiments, offsets based on standard deviations of the estimated distributions may be applied to the means, and from results of applying the offsets to the means, the threshold resistance R TH  may be calculated. The standard deviations may be pre-derived by testing variable resistance elements (for example, MTJ of  FIG. 3 ). As the standard deviations are applied to estimated mean values, the threshold resistance R TH  may be more accurately determined. For example, as shown in  FIG. 11 , when values a and b, related to the number of cells, are greater than 0, an offset a·σ P  proportional to a standard deviation σP may be added to the mean R P ′ of the parallel resistances R P . In addition, an offset b·σ AP  proportional to a standard deviation σ AP  may be subtracted from the mean R AP ′ of the anti-parallel resistances R AP . Accordingly, the threshold resistance R TH  may be calculated by a function ƒ having the values R P ′+a·σ P , R AP ′−b·σ AP , which are generated by respectively applying the standard deviations σ A , σ AP  to the means R P ′, R AP ′, as factors. In some embodiments, the threshold resistance R TH  for reading data from the memory cell may be calculated based on [Equation 1] written below. The read reference current may be based on a median value of a first resistance and a second resistance. The first resistance may be generated by adding a first standard resistance based on a standard deviation of the first distribution to the mean of the first distribution. The second resistance may be generated by subtracting a second standard resistance based on a standard deviation of the second distribution from the mean of the second distribution. 
     
       
         
           
             
               
                 
                   
                     
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     In operation S 860   a , an operation of determining a read reference current and/or a read reference resistance may be performed. For example, the reference trimmer  210  may calculate a reference voltage V_REF, that is, a read reference voltage, corresponding to the threshold resistance R TH  calculated in the operation S 840   a , and determine a reference current I_REF and a reference resistance R_REF corresponding to the reference voltage V_REF as the read reference current and the read reference resistance. Information or data regarding the read reference current and the read reference resistance, which are determined, may be transmitted to the control circuit  150  of the memory device  100 . The control circuit  150  may store the data regarding the read reference current and the read reference resistance in the NVM  160  as data regarding the read reference voltage. 
       FIG. 12  is a flowchart showing the operation S 800  of  FIG. 8 , according to example embodiments, and  FIG. 13  is a graph showing an example of an operation of determining a threshold resistance by operation S 800   b  of  FIG. 12 . In detail, the operation S 800   b  of  FIG. 12 , compared to the operation S 800   a  of  FIG. 10 , may use the threshold resistance R TH  determined from the plurality of memory cells to which ‘0’ is written, as described above with reference to  FIG. 9A . As described above with reference to  FIG. 8 , in the operation S 800   b  of  FIG. 12 , an operation of determining a read reference voltage, based on results of read operations under each of the reference voltages, may be performed. Hereinafter, among descriptions of  FIG. 12 , descriptions overlapping with those of  FIG. 10  will be omitted. 
     In operation S 820   b , an operation of estimating a parallel resistance R P  distribution may be performed. Similarly to the operation S 820   a  of  FIG. 10 , the threshold resistance R TH  derived from the example of  FIG. 9A  may be estimated to be a mean R P ′ of the parallel resistance distribution R P . Accordingly, as shown in  FIG. 13 , a location of the parallel resistance distribution R P  may be estimated by the mean R P ′. In some embodiments, due to features of the variable resistance elements, the anti-parallel resistance R AP  distribution may be degraded than the parallel resistance R P  distribution, and thus, the parallel resistance R P  distribution may be used. 
     In operation S 840   b , an operation of calculating a threshold resistance R TH  from the parallel resistance R P  distribution may be performed. In some embodiments, an offset based on a standard deviation of the estimated distribution may be applied to the mean, and from the result of applying the offset to the mean, the threshold resistance R TH  may be calculated. For example, as shown in  FIG. 13 , when c is greater than 0, to the mean R P ′ of the parallel resistances R P , an offset c·σ P  that is proportional to the standard deviation σ P  may be added. Accordingly, the threshold resistance R TH  may be calculated by a function g having a value of R P ′+c·σ P , which is generated by applying the standard deviation σ P  to the mean R P ′, as a factor. In some embodiments, the threshold resistance R TH  used for reading data from the memory cells may be calculated based on [Equation 2] written below.
 
 R   TH =( R   P   ′+c·σ   P )+ d, c &gt;0 and  d ≥0  [Equation 2]
 
     In operation S 860   b , an operation of determining a read reference current and/or a read reference resistance may be performed. For example, the reference trimmer  210  may determine a reference voltage V_REF, that is, a read reference voltage, corresponding to the threshold resistance R TH  calculated in the operation S 840   b , and determine a reference current I_REF and a reference resistance R_REF corresponding to the reference voltage V_REF as the read reference current and the read reference resistance. Information or data regarding the determined read reference current and the read reference resistance may be transmitted to the control circuit  150  of the memory device  100 , and the control circuit  150  may store the data regarding the read reference current and the read reference resistance in the NVM  160  as data regarding the read reference voltage. 
       FIG. 14  is a block diagram of a memory device  300  according to an example embodiment. As illustrated in  FIG. 14 , the memory device  300  may include an amplification circuit  340 , a control circuit  350 , a non-volatile memory  360 , and a reference trimmer  370 . Although not illustrated in  FIG. 14 , the memory device  300  of  FIG. 14  may, like the memory device  100  of  FIG. 1 , include a cell array, a current source circuit, and/or a reference resistance circuit. Hereinafter, among descriptions of  FIG. 14 , descriptions overlapping with those of  FIG. 1  are omitted. 
     Compared to the memory device  100  of  FIG. 1 , the memory device  300  of  FIG. 14  may receive a calibration signal CAL and further include the reference trimmer  370 . Accordingly, the memory device  300  may, in response to the calibration signal CAL, independently derive an accurate reference voltage, and the system including the memory device  300  may, by providing the calibration signal CAL to the memory device  300 , maintain operation reliability of the memory device  300 . 
     The reference trimmer  370  may, in response to the received calibration signal CAL, write identical values to the plurality of memory cells of the cell array, and transmit signals to the control circuit  350  for generating reference voltages that monotonically increase or monotonically decrease. The reference trimmer  370  may receive a signal corresponding to values from the plurality of memory cells under each of the reference voltages from the amplification circuit  340 , and may, based on results of the reading, determine a read reference voltage. The reference trimmer  370  may provide data regarding the read reference voltage to the control circuit  350 , and the control circuit  350  may store data regarding the read reference voltage in the NVM  360 . Afterwards, when the memory device  300  receives a read command, the control circuit  350  may control the reference current I_REF and/or the reference resistance R_REF such that the reference voltage is generated based on the data regarding the read reference voltage stored in the NVM  360 . 
       FIG. 15  is a block diagram illustrating a system on chip (SOC)  400  including the memory device, according to an example embodiment. The SOC  400  may refer to an integrated circuit in which components of a computing system or other electronic systems are integrated. For example, as the SOC  400 , an application processor (AP) may include components for a processor and other functions. As illustrated in  FIG. 15 , the system-on-chip  400  may include a core  410 , a digital signal processor (DSP)  420 , a graphic processing unit (GPU)  430 , an embedded memory  440 , a communication interface  450 , and a memory interface  460 . Components of the system-on-chip  400  may communicate with each other via a bus  470 . 
     The core  410  may process commands and control operations of the components included in the system-on-chip  400 . For example, the core  410  may, by processing a series of commands, drive an operation system and execute applications in the operation system. The DSP  420  may process digital signals, for example, digital signals provided from the communication interface  450 , to generate useful data. The GPU  430  may generate data for images output through a display device by using image data provided by the embedded memory  440  or the memory interface  460 , and may also encode the image data. 
     The embedded memory  440  may store data required for operations of the core  410 , the DSP  420 , and the GPU  430 . The embedded memory  440  may include the resistive memory according to an example embodiment, and accordingly, the embedded memory  440  may provide high reliability resulting from accurate reference voltages. 
     The communication interface  450  may provide interfaces for communication networks or one to one communications. The memory interface  460  may provide interfaces for external memories of the SOC  400 , for example, dynamic random access memory (DRAM), a flash memory, and the like. 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.