Patent Publication Number: US-7714639-B2

Title: Stabilizing methods for current source

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The invention relates to a stabilizing method for a current source, and more particularly to a stabilizing method for a current source which provides a current varying with temperature. 
   2. Description of the Related Art 
   For integrated circuit design, reference voltages and reference currents are required. Wherein, the reference voltages and the reference currents are usually included in a bias part of the integrated circuit. For general applications, the bias part of an integrated circuit is designed according to operating temperature of the integrated circuit. However, variations in operating temperature are not considered for the design of the bias part. 
   During the operation of integrated circuits, operating temperature varies according to ambient temperature variation or heat generated by electronic elements within the integrated circuit. Operating temperature variations may affect signal transmitting operations of the integrated circuit, so that the transformed signals have noise resulted from the operation temperature variation. For example, an analog-to-digital converter is affected by temperature noise. Moreover, a microprocessor with a sensor is more sensitive to temperature variations, thus, temperature variations also affects operations of microprocessors with sensors. 
   In general, bipolar junction transistors (BJTs) are used to design integrated circuits having temperature variation. There is a logarithmic relationship between base-emitter voltage V BE  and collector current I C  of a BJT and the base-emitter voltage V BE  is affected by temperature variation. The relationship between the base-emitter voltage V BE  and the temperature variation is represented by the following:
 
 V   BE ( H,I   C )= E   GE   −H ( E   GE   −V   BEN )+ V   TH   H  log( I   C   /I   N )−η V   TH   H  log  H   (Function 1)
 
   wherein, H=T/T N , and T represents absolute temperature, and T N  represents standardized temperature. T N  is usually a middle value of an operating temperature range, such as 300K (27°). E EG  represents an assumed value of the base-emitter voltage V BE  at absolute zero (zero degree Kelvin), or about 1.14V to 1.19 V. V BEN  represents a value of the base-emitter voltage V BE  when junction temperature of a BJT is equal to the specific value T N  and collector current I C  is equal to a specific value I N . V TN  represents a value of thermal voltage (=kT/q) at the standardized temperature T N . η represents a curve constant, about 2 to 4. 
     FIG. 1  shows a line diagram of Function 1. Referring to  FIG. 1 , showing characteristics of BJTs, the base-emitter voltage V BE  decreases when temperature rises and increases when collector current I C  increases. BJTs are usually applied in circuits, wherein when there is a rise in temperature, current increases, achieving current balance so that the current remains at a constant value. 
   However, since diodes are required in a BJT circuit, requirement for a BJT circuit increases hardware costs and device/element volume. Thus, it is desired to provide an alternative method for stabilizing a current source. 
   BRIEF SUMMARY OF THE INVENTION 
   An exemplary embodiment of a stabilizing method for stabilizing a current provided by a current source is provided. The current of the current source increases when temperature rises. The stabilizing method comprises: providing an adjustment circuit which provides an input current that rises when temperature rises, wherein a rising ratio of the input current with temperature is the same as a rising ratio of the current of the current source with temperature; and providing a coupling to subtract the current of the current source from the input current. After the current of the current source is subtracted from the input current, the current of the current source does not vary with temperature. 
   An exemplary embodiment of a stabilizing method for stabilizing a current provided by a current source when temperature varies is provided. The current of the current source increases when temperature rises. The stabilizing method comprises: providing an input current which increases when temperature rises, wherein a rising ratio of the input current with temperature is the same as a rising ratio of the current of the current source with temperature; and subtracting the current of the current source from the input current before the current of the current source is output, so that the current of the current source does not vary with temperature when the current of the current source is output. 
   A detailed description is given in the following embodiments with reference to the accompanying drawings. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein: 
       FIG. 1  shows a line diagram of Function 1; 
       FIG. 2  shows an embodiment of a stabilizing circuit for a current source of the invention; and 
       FIGS. 3   a - 3   c  are diagrams of a stabilizing current process according to the embodiment of the invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   The following description is of the best-contemplated mode of carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims. 
   Stabilizing circuits for a current source are provided. In an embodiment of a stabilizing circuit  2  for a current source of the invention in  FIG. 2 , a stabilizing circuit  2  comprises a current source circuit  21  and an adjustment circuit  22 . The current source circuit  21  comprises a P-type metal oxide semiconductor (PMOS) transistor  211 , a first NMOS transistor  212 , a first resistor  213 , a second PMOS transistor  214 , a second NMOS transistor  215 , and a ground terminal  216 . 
   The adjustment circuit  22  comprises third, fourth, fifth, and sixth NMOS transistors  221 ,  222 ,  223 , and  224 . 
   A source of the first PMOS transistor  211  is coupled to sources of the second PMOS transistor  214  and the third NMOS transistor  221 , a gate thereof is coupled to a gate of the second PMOS transistor  214 , and a drain thereof is coupled to a source of the first NMOS transistor  212 . A gate of the first NMOS transistor  212  is coupled to a drain of the second PMOS transistor  214  and a source of the second NMOS transistor  215 , and a drain thereof is coupled to one terminal of the first resistor  213  and a gate of the second NMOS transistor  215 . The other terminal of the first resistor  213  is coupled to the ground terminal  216 . 
   The drain of the second PMOS transistor  214  is coupled to the source of the second NMOS transistor  215 , a drain of the fifth NMOS transistor  223 , and a source of the sixth NMOS transistor  224 . A drain of the second NMOS transistor  215  is coupled to the ground terminal  216 . 
   A drain of the third NMOS transistor  221  is coupled to a source of the fourth NMOS transistor  222 . A drain of the fourth NMOS transistor  222  is coupled to a source of the fifth NMOS transistor  223 . The drain of the fifth NMOS transistor  223  is coupled to the source of the sixth NMOS transistor  224 . A drain of the sixth NMOS transistor  224  is coupled to the ground terminal  216 . A gate of the fifth NMOS transistor  223  is coupled to a gate of the sixth NMOS transistor  224  and further to the sources of the third NMOS transistor  221 , the second PMOS transistor  214 , and the first PMOS transistor  211 . 
   The current source circuit  21  can be a self-biasing MOSFET Vt reference current source for providing a current to serve as a current source. The adjustment circuit  22  can be a start-up circuit for providing an input current. Given bandgap reference voltage and the characteristic where input current increases when temperature rises, before the current of the current source circuit  21  is input, the adjustment circuit  22  subtracts the current of the current source circuit  21  from the input current. The MOS transistors in the adjustment circuit  22  can adjust a rising ratio of the input current with temperature to be the same as rising ratio of the current of the current source circuit  21  with temperature. Accordingly, after the input current is subtracted from the current of the current source circuit  21 , an output current of the stabilizing circuit  2  has a stable value, so that the output current will not increase when temperature rises or decreases when temperature falls. Thus, the current source circuit  21  is more stable since the effect of temperature variation for output current is eliminated, 
     FIGS. 3   a - 3   b  is a diagram of a stabilizing current process according to the embodiment of the invention.  FIG. 3   a  is a relationship diagram between the current provided by current source circuit  21  and temperature, and  FIG. 3   b  is a relationship diagram between the input current of the adjustment circuit  22  and temperature. In  FIGS. 3   a  and  3   b , the vertical axes represent current magnitude, and the horizontal axes represent temperature. A relationship coefficient between the current and the temperature in  FIG. 3   a  is same as that in  FIG. 3   b .  FIG. 3   c  is a relationship diagram between the output current and temperature after the input current is subtracted from the current of the current source circuit  21 . Referring to  FIG. 3   c , the value of the output current is constant and does not vary with temperature. 
   In above embodiment, the four NMOS transistors in the adjustment circuit  22  are given as an example, without limitation. The current source circuit  21  is not limited to a self-biasing MOSFET Vt reference current source. 
   According to the embodiment of the invention, the stabilizing circuit  2  does not use conventional BJT circuit and diodes therein, thus, saving hardware costs and hardware space. 
   While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. To the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.