Patent Publication Number: US-2019180671-A1

Title: Gate driver circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of China application serial no. 201711314919.8, filed on Dec. 12, 2017. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention relates to a gate driver circuit. 
     2. Description of Related Art 
     Thanks to advancement in optoelectronic and semiconductor technologies, the flat displays have become widely applied in recent years. A gate in panel (GIP) technology has gradually developed currently in order to achieve cost reduction and meet the design requirement of narrow border. Nevertheless, display panels are required to provide high resolution in existing trends, the resistive-capacitive loading of the conductive lines disposed at the peripheral circuit areas is inevitably increased. It is thus difficult for the gate driver circuits to provide driving voltages large enough to drive the display panels. 
     Therefore, how to provide sufficient driving capability, meet the design requirement of narrow border, and deliver high resolution are important goals for the researchers in this field. 
     SUMMARY OF THE INVENTION 
     The invention relates to a gate driver circuit which may suppress a noise of a gate driver unit so as to provide favorable driving capability, deliver high resolution, and meet design requirement of narrow border. 
     In an embodiment of the invention, a gate driver circuit includes a plurality of gate driver units. The gate driver units are coupled to each other in sequence, and each of the gate driver units includes a shift register and a de-multiplexer. The shift register receives one of a plurality of operation clock signals and a startup signal and generates a first control signal and a second control signal according to the startup signal and the received operation clock signal. The de-multiplexer is coupled to the shift register and receives a portion of a plurality of gate clock signals to output the received portion of the gate clock signals according to the first control signal to generate a plurality of gate signals in sequence. The gate clock signals are enabled in sequence, and enabling durations of two consecutive clock signals in the gate clock signals are partially overlapped. 
     To sum up, in the gate driver circuit of the embodiments of the invention, one shift register corresponds to plural de-multiplexers to control the de-multiplexers to output the gate signals. Moreover, the anti-noise unit in the shift register may ensure that the first internal voltage, the first control signal, and the gate signals are not in the floating state when the gate driver unit is in the non-operational period. Therefore, in the gate driver unit, output stability may be enhanced and erroneous output may be less likely to occur. 
     To make the aforementioned and other features and advantages of the invention more comprehensible, several embodiments accompanied with drawings are described in detail as follows. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is a schematic diagram of a system of a display panel according to an embodiment of the invention. 
         FIG. 1B  is a schematic diagram of a system of a gate driver circuit according to an embodiment of the invention. 
         FIG. 2A  is a schematic diagram of a circuit of a gate driver unit according to a first embodiment of the invention. 
         FIG. 2B  is a schematic diagram of driving waveforms of the gate driver units according to the first embodiment of the invention. 
         FIG. 3A  is a schematic diagram of a circuit of a gate driver unit according to a second embodiment of the invention. 
         FIG. 3B  is a schematic diagram of driving waveforms of the gate driver units according to the second embodiment of the invention. 
         FIG. 4A  is a schematic diagram of a circuit of a gate driver unit according to a third embodiment of the invention. 
         FIG. 4B  is a schematic diagram of driving waveforms of the gate driver units according to the third embodiment of the invention. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1A  is a schematic diagram of a system of a display panel according to an embodiment of the invention. With reference to  FIG. 1A , in this embodiment, a display panel  10  includes a pixel array  11  and gate driver circuits  13  and  15 , wherein a plurality of pixels (not shown) arranged in an array may be disposed in the pixel array  11 , but the invention is not limited to the above. The gate driver circuits  13  and  15  are disposed at two opposite sides of the pixel array  11 , so as to respectively provide gate signals G 1  to Gm required for driving the pixel array  11 . The gate driver circuit  13  provides, for example, the odd gate signals G 1 , G 3 , . . . , Gm- 1 , the gate driver circuit  15  provides, for example, the even gate signals G 2 , G 4 , . . . , Gm, and m is a row number of the pixel array  11 . 
       FIG. 1B  is a schematic diagram of a system of a gate driver circuit according to an embodiment of the invention. With reference to  FIG. 1  A and  FIG. 1B , identical or similar components are assigned with identical or similar reference numerals. The gate driver circuit  13  is taken as an example herein, and a circuit structure of the gate driver circuit  15  is similar to a circuit structure of the gate driver circuit  13 . In this embodiment, the gate driver circuit  13  includes a plurality of gate driver units  100 _ 1  to  100 _k, wherein k is a positive integer and is less than m. The gate driver units  100 _ 1  to  100 _k are coupled to each other in sequence to be triggered in sequence. Moreover, each of the gate driver units  100 _ 1  to  100 _k provides plural odd gate signals (e.g., G 1 , G 3 , . . . , Gm- 1 , etc.). m divided by a number of the odd gate signals (e.g., G 1 , G 3 , Gm- 1 , etc.) provided by each of the gate driver units  100 _ 1  to  100 _k equals k. Herein, each of the gate driver units  100 _ 1  to  100 _k provides  4  odd gate signals (e.g., G 1 , G 3 , . . . , Gm- 1 , etc.), but the invention is not limited to the above. 
     Each of the gate driver units  100 _ 1  to  100 _k respectively includes a shift register (e.g.,  110 _ 1  to  110 _k) and a de-multiplexer (e.g.,  120 _ 1  to  120 _k). The shift register (e.g.,  110 _ 1  to  110 _k) of each of the gate driver units  100 _ 1  to  100 _k receives one of a plurality of operation clock signals OCK 1  to OCKi and a startup signal and generates a first control signal GC and a second control signal PA according to the startup signal and the received operation clock signal (e.g., OCK 1  to OCKi). The startup signal may be an initial signal STV or the first control signal GC provided by the shift register (e.g.,  110 _ 1  to  110 _k) of the gate driver unit two stages before (e.g.,  100 _ 1  to  100 _k), and i may be a positive integer. For instance, the startup signals of the shift registers  110 _ 1  and  110 _ 2  of the gate driver units  100 _ 1  and  100 _ 2  are the initial signals STV, and the startup signal of the shift register  110 _ 3  of the gate driver unit  100 _ 3  is the first control signal GC provided by the shift register  110 _ 1 . 
     The de-multiplexer (e.g.,  120 _ 1  to  120 _k) of each of the gate driver units  100 _ 1  to  100 _k is coupled to the corresponding shift register (e.g.,  110 _ 1  to  110 _k) and receives a portion of a plurality of gate clock signals GCK 1  to GCKj (i.e., two or more gate clock signals GCK 1  to GCKj), so as to output the received portion of the gate clock signals (e.g., GCK 1  to GCKj) according to the corresponding first control signal GC to generate plural odd gate signals (e.g., G 1 , G 3 , . . . , Gm- 1 , etc.) in sequence. The gate clock signals (e.g., GCK 1  to GCKj) are enabled in sequence and are different from the operation clock signals (e.g., OCK 1  to OCKi), wherein enabling durations of two consecutive clock signals in the gate clock signals (e.g., GCK 1  to GCKj) are partially overlapped, and j is a positive integer greater than i. 
     In addition, the shift register (e.g.,  110 _ 1  to  110 _k) of each of the gate driver units  100 _ 1  to  100 _k may receive a turn-off signal to allow the shift register (e.g.,  110 _ 1  to  110 _k) to stop providing the second signal PA. With reference to  FIG. 1B , the turn-off signal may be a reset signal RST or the first control signal GC provided by the shift register (e.g.,  110 _ 1  to  110 _k) of the gate driver unit two stages later (e.g.,  100 _ 1  to  100 _k) in this embodiment. 
     Moreover, when the shift register (e.g.,  110 _ 1  to  110 _k) of each of the gate driver units  100 _ 1  to  100  k is activated, the first control signal GC provided by the activated shift register (e.g.,  110 _ 1  to  110 _k) is related to the received operation clock signal (e.g., OCK 1  to OCKi), and the second control signal PA is fixed to be a gate low voltage VGL. When the shift register (e.g.,  110 _ 1  to  110 _k) of each of the gate driver units  100 _ 1  to  100 _k is turned off, the first control signal GC provided by the turned-off shift register (e.g.,  110 _ 1  to  110 _k) is fixed to be the gate low voltage VGL, and the second control signal PA is related to the received operation clock signal (e.g., OCK 1  to OCKi). In other words, in this embodiment, one of the first control signal GC and the second control signal PA provided by the shift register (e.g.,  110 _ 1  to  110 _k) of each of the gate driver units  100 _ 1  to  100 _k is related to the received operation clock signal (e.g., OCK 1  to OCKi), and the other one of the first control signal GC and the second control signal PA is fixed to be the gate low voltage VGL. 
       FIG. 2A  is a schematic diagram of a circuit of a gate driver unit according to a first embodiment of the invention. With reference to  FIG. 1A ,  FIG. 1B , and  FIG. 2A , identical or similar components are assigned with identical or similar reference numerals. Moreover, the gate driver units (e.g.,  100 _ 1  to  100 _k) may be implemented as a gate driver unit  100 a, but the embodiments of the invention are not limited to the above. In this embodiment, the gate driver unit  100   a  includes a shift register  110   a  and a de-multiplexer  120   a.  The shift register  110   a  includes a voltage setting unit  111 , a shift output unit  113 , and an anti-noise unit  115 . 
     The voltage setting unit  111  receives a forward scanning voltage Vfwd, a backward scanning voltage Vbwd, the corresponding initial signal (e.g., a first control signal GCn- 2  two stages before), and the turn-off signal (e.g., a first control signal GCn+ 2  two stages later) to set a first internal voltage Q, wherein n is an index number. The shift output unit  113  receives the corresponding operation clock signal OCKx (i.e., one of the operation clock signals OCK 1  to OCKi, and x is an index number) and the first internal voltage Q and determines whether to output the received operation clock signal OCKx according to the first internal voltage Q to provide the first control signal GC. The anti-noise unit  115  receives the first internal voltage Q and the first control signal GC to provide the second control signal PA according to the first internal voltage Q and pull down the first control signal GC according to the first internal voltage Q. 
     The de-multiplexer  120   a  includes a plurality of signal transmission units ( 4  signal transmission units  121 ,  123 ,  125 , and  127  are taken as an example herein). The signal transmission units  121 ,  123 ,  125 , and  127  respectively receive one of the portion of the continuity gate clock signals (e.g., the gate clock signal GCKy, wherein y is an index number) in the gate clock signals GCK 1  to GCKj, the first control signal GC, and the second control signal PA, wherein the signal transmission units  121 ,  123 ,  125 , and  127  are turned on simultaneously according to the first control signal PA. The signal transmission units  121 ,  123 ,  125 , and  127  respectively provide the received clock signals (e.g., the gate clock signal GCKy) to respectively generate the gate signals (e.g., Gn). Moreover, the signal transmission units  121 ,  123 ,  125 , and  127  are cut off simultaneously according to the second control signal PA. That is, the signal transmission units  121 ,  123 ,  125 , and  127  have identical circuit structures but receive different gate clock signals (e.g., GCK 1  to GCKj). 
     Further, the voltage setting unit  111  includes a first transistor Ti and a second transistor T 2 . The first transistor T 1  has a first terminal receiving the forward scanning voltage Vfwd, a control terminal receiving the startup signal (e.g., the first control signal GCn- 2  two stages before), and a second terminal receiving the first internal voltage Q. The second transistor T 2  has a first terminal receiving the backward scanning voltage Vbwd, a control terminal receiving the turn-off signal (e.g., the first control signal GCn+ 2  two stages later), and a second terminal receiving the first internal voltage Q. 
     The shift output unit  113  includes a third transistor T 3  and a first capacitor C 1 . The third transistor T 3  has a first terminal receiving the operation clock signal OCKx, a control terminal receiving the first internal voltage Q, and a second terminal providing the first control signal GCn. The first capacitor C 1  is coupled between the control terminal of the third transistor T 3  and the second terminal of the third transistor T 3 . 
     The anti-noise unit  115  includes a fourth transistor T 4 , a fifth transistor T 5 , a sixth transistor T 6 , a seventh transistor T 7 , and a second capacitor C 2 . The fourth transistor T 4  has a first terminal receiving the second control signal PA, a control terminal receiving the first internal voltage Q, and a second terminal receiving the gate low voltage VGL. The fifth transistor T 5  has a first terminal receiving the first internal voltage Q, a control terminal receiving the second control signal PA, and a second terminal receiving the gate low voltage VGL. The sixth transistor T 6  has a first terminal receiving the first control signal GC, a control terminal receiving the second control signal PA, and a second terminal receiving the gate low voltage VGL. The seventh transistor T 7  has a first terminal receiving the first control signal GC, a control terminal receiving the operation clock signal two stages later of the operation clock signal OCKx received by the shift output unit  113 , and a second terminal receiving the gate low voltage VGL. The second capacitor C 2  is coupled between the operation clock signal OCKx and the second control signal PA. 
     The signal transmission unit  121  includes an eighth transistor T 8 , a ninth transistor T 9 , a tenth transistor T 10 , an eleventh transistor T 11 , and a capacitor C 3 . The eighth transistor T 8  has a first terminal receiving the first control signal GC, a control terminal receiving one gate clock signal GCKo (corresponding to a charge control signal) of the gate clock signals GCK 1  to GCKj not received by the de-multiplexer  120   a,  and a second terminal receiving a second internal voltage R, wherein o is an index number. The ninth transistor T 9  has a first terminal receiving the gate clock signal GCKy, a control terminal receiving the second internal voltage R, and a second terminal providing the corresponding gate signal Gn. The third capacitor C 3  is coupled between the control terminal of the ninth transistor T 9  and the second terminal of the ninth transistor T 9 . The tenth transistor T 10  has a first terminal receiving the corresponding gate signal Gn, a control terminal receiving the second control signal PA, and a second terminal receiving the gate low voltage VGL. The eleventh transistor T 11  has a first terminal receiving the corresponding gate signal Gn, a control terminal receiving the operation clock signal OCKx+2 (corresponding to a pull-down control signal), and a second terminal receiving the gate low voltage VGL. 
       FIG. 2B  is a schematic diagram of driving waveforms of the gate driver units according to the first embodiment of the invention. With reference to  FIG. 2A  and  FIG. 2B , in this embodiment,  4  operation clock signals OCK 1  to OCK 4  are taken as an example,  7  gate clock signals GCK 1  to GCK 7  are taken as an example, and the startup signal is the initial signal STV. Herein, the operation clock signals OCK 1  to OCK 4  are signals having identical pulse widths but enabled in sequence, and enabling durations of the adjacent operation clock signals in the operation clock signals OCK 1  to OCK 4  are partially overlapped. Herein, the gate clock signals GCK 1  to GCK 7  are signals having identical pulse widths but enabled in sequence, and the enabling durations of the adjacent gate clock signals in the gate clock signals GCK 1  to GCK 7  are partially overlapped. 
     During a time period tO to a time period t 1 , the initial signal STV is enabled to turn on the first transistor Ti for charging the first internal voltage Q, and the operation clock signal OCK 1  is at a low level at this time. Moreover, the third transistor T 3  is turned on, so as to pull down the first control signal GC 1  to the low level. Since the fourth transistor T 4  is turned on by the first internal voltage Q, the anti-noise unit  115  is in a turn-off state. 
     Next, during the time period t 1  to a time period t 2 , the operation clock signal OCK 1  is transferred from the low level to a high level, the third transistor T 3  starts to charge the first control signal GC 1 , while a boot-strapping effect is generated to the first internal voltage Q by the first capacitor C 1 . As such, the first internal voltage Q is raised to a higher potential and that the first control signal GC 1  may be outputted more completely. 
     When the first control signal GC 1  is at the high level, the gate clock signal GCK 6  turns on the eighth transistor T 8  and pre-charges the second internal voltage R. At this time, the gate clock signal GCK 1  is at the low level, and the ninth transistor T 9  is turned on and that the gate signal G 1  is pulled down to the low level. At this time, the second control signal PA is still at the low level, and the anti-noise unit  115  is thereby maintained to be in the turn-off state. 
     During the time period t 2  to a time period t 3 , the gate clock signal GCK 1  is transited to the high level, the ninth transistor T 9  starts to charge the gate signal G 1 , while the boot-strapping effect is generated to the second internal voltage R by the third capacitor C 3 . As such, the second internal voltage R is raised to a higher potential and that the gate signal G 1  may be outputted more completely. At this time, the gate signals G 3 , G 5 , and G 7  are outputted in sequence as well. 
     During the time period t 3  to a time period t 4 , the first control signal GC 1  is transited to the low level, and the gate clock signal GCK 6  turns on the eighth transistor T 8  again, and the first internal voltage Q is discharged by the third transistor T 3 . Moreover, the operation clock signal OCK 3  turns on the seventh transistor T 7  and the eleventh transistor T 11 , such that the first control signal GC 1  and the gate signal G 1  are pulled down to the low level. After the time period t 4 , operation of the gate driver unit  100   a  is generally completed until the next startup signal, while the anti-noise unit  115  starts to operate, so as to ensure that when the gate driver unit  100   a  is in a non-operational period, the first internal voltage Q, the first control signal GC 1 , and the gate signal G 1  are not in a floating state. 
     Similarly, after the first control signal GC 1  is enabled, the first control signal GC 2  of the next stage is enabled next for providing the subsequent gate signals G 9 , G 11 , G 13 , and G 15 . 
       FIG. 3A  is a schematic diagram of a circuit of a gate driver unit according to a second embodiment of the invention. With reference to  FIG. 2A  and  FIG. 3A , a gate driver unit  100   b  is substantially identical to the gate driver unit  100   a,  and a difference therebetween includes signal transmission units  121   a,    123   a,    125   a,  and  127   a  of a de-multiplexer  120   b.  Herein, identical or similar components are assigned with identical or similar reference numerals. Comparing between the signal transmission unit  121 a and the signal transmission unit  121 , the control terminal of the eighth transistor T 8  of the signal transmission unit  121 a receives a pre-charge clock signal Gpre 1 , meaning that the control terminal of the eighth transistor T 8  of the signal transmission unit  121   a  receives clock signals other than the operation clock signals OCK 1  to OCKi and the gate clock signals GCK 1  to GCKj. 
       FIG. 3B  is a schematic diagram of driving waveforms of the gate driver units according to the second embodiment of the invention. With reference to  FIG. 2A ,  FIG. 2B ,  FIG. 3A , and  FIG. 3B , a difference between  FIG. 3B  and  FIG. 2B  includes the pre-charge clock signal Gpre 1  and a pre-charge clock signal Gpre 2 . In this embodiment, the pre-charge clock signals Gpre 1  and Gpre 2  have the same pulse widths but are enabled in sequence, and central points of enabling durations of the pre-charge clock signals Gpre 1  and Gpre 2  are substantially aligned with rising edges of the operation clock signals OCK 1  to OCK 4  respectively. Such that, when the first internal voltage Q is at the high level, the eighth transistors T 8  in the signal transmission units  121   a,    123   a,    125   a,    127   a  are thereby turned on, so as to charge the second internal voltages R 1  to R 4  in the signal transmission units  121   a,    123   a,    125   a,  and  127   a.    
       FIG. 4A  is a schematic diagram of a circuit of a gate driver unit according to a third embodiment of the invention. With reference to  FIG. 2A  and  FIG. 4A , a gate driver unit  100 c is substantially identical to the gate driver unit  100   a,  wherein identical or similar components are assigned with identical or similar reference numerals. In this embodiment, an anti-noise unit  115   a  of a shift register  110   b  further includes a twelfth transistor T 12 , a thirteenth transistor T 13 , a fourteenth transistor T 14 , a fifteenth transistor T 15 , a sixteenth transistor T 16 , a seventeenth transistor T 17 , and an eighteenth transistor T 18 . 
     The twelfth transistor T 12  has a first terminal receiving a third control signal PB, a control terminal receiving the first internal voltage Q, and a second terminal receiving the gate low voltage VGL. The thirteenth transistor T 13  has a first terminal receiving the first internal voltage Q, a control terminal receiving the third control signal PB, and a second terminal receiving the gate low voltage VGL. The fourteenth transistor T 14  has a first terminal receiving the second control signal PA, a control terminal receiving a first low frequency signal V 1 , and a second terminal receiving the first low frequency signal V 1 . The fifteenth transistor T 15  has a first terminal receiving the third control signal PB, a control terminal receiving the first low frequency signal V 1 , and a second terminal receiving the gate low voltage VGL. The sixteenth transistor T 16  has a first terminal receiving a second low frequency signal V 2 , a control terminal receiving the second low frequency signal V 2 , and a second terminal receiving the third control signal PB. The seventeenth transistor T 17  has a first terminal receiving the second control signal PA, a control terminal receiving the second low frequency signal V 2 , and a second terminal receiving the gate low voltage VGL. The eighteenth transistor T 18  has a first terminal receiving the first control signal GCn, a control terminal receiving the third control signal PB, and a second terminal receiving the gate low voltage VGL. 
     In signal transmission units  121   b,    123   b,    125   b,  and  127   b  of a de-multiplexer  120   c,  the control terminal of the eleventh transistor T 11  receives the third control signal PB (corresponding to the pull-down control signal) as shown in the signal transmission unit  121   b.    
       FIG. 4B  is a schematic diagram of driving waveforms of the gate driver units according to the third embodiment of the invention. With reference to  FIG. 2A ,  FIG. 2B ,  FIG. 4A , and  FIG. 4B , a difference between  FIG. 4B  and  FIG. 2B  includes the first low frequency signal V 1  and the second low frequency signal V 2 , wherein the second low frequency signal V 2  is opposite to the first low frequency signal V 1 . When the first internal voltage Q is at the low level, the enabled first low frequency signal V 1  raises the second control signal PA and pulls down the third control signal PB. Alternatively, the enabled second low frequency signal V 2  raises the third control signal PB and pulls down the second control signal PA. As such, stress of the fifth transistor T 5 , the sixth transistor T 6 , the tenth transistor T 10 , the eleventh transistor T 11 , the thirteenth transistor T 13 , and the eighteenth transistor T 18  can be suppressed. 
     In view of the foregoing, in the gate driver circuit of the embodiments of the invention, one shift register corresponds to plural de-multiplexers to control the de-multiplexers to output the gate signals. Moreover, the anti-noise unit in the shift register may ensure that the first internal voltage, the first control signal, and the gate signals are not in the floating state when the gate driver unit is in the non-operational period. Therefore, in the gate driver unit, output stability may be enhanced and erroneous output may be less likely to occur.