Patent Publication Number: US-2022223705-A1

Title: Steep-slope field-effect transistor and fabrication method thereof

Description:
TECHNICAL FIELD 
     Embodiments of the inventive concept described herein relate to a structure of a field-effect transistor (FET) capable of performing a steep-slope operation and a fabrication method thereof, and more particularly, relate to a steep-slope FET capable of implementing steep-slope performance, in a transistor having a transition layer and a control gate on an upper portion of a gate of an existing FET, and a fabrication method thereof. 
     BACKGROUND ART 
     In the era of the 4th industrial revolution, recently, there has been a rapid increase in demand for related industries such as artificial intelligence (AI), autonomous vehicles, big data, augmented/virtual reality (AR/VR), and Internet of Things (IoT). The importance and market of the semiconductor industry which is the basis of all these industries is gradually growing. To produce, store, and process vast amounts of data incapable being processed in the past in mobile devices, large servers, and the like, high performance and high integration of semiconductor devices and low power consumption for reducing the increased power consumption due to this are essential. 
     The semiconductor industry has developed rapidly after the development of a metal-oxide-semiconductor field-effect transistor (MOSFET) using silicon (Si) and silicon oxide (SiO2) in the 1960s. The development of these silicon-based MOSFET miniaturization processes and technologies has successfully led the semiconductor industry, but due to the unique physical and material characteristics of silicon semiconductors, performance improvement through ultra-fine processes is limited. Furthermore, high leakage current derived from miniaturization and high power consumption caused by a relatively high operating voltage are emerging as one of the current biggest problems of silicon-based semiconductor devices. 
     The power consumption of the semiconductor device is defined as a value obtained by adding operation power consumption, short-circuit power consumption, and leakage power consumption. To reduce total power consumption, both of a leakage current value in an off-state and a driving voltage necessary to make an on-state among transistor performance indexes should be reduced. 
     Meanwhile, because channel establishment is caused by means of thermionic diffusion, an existing MOSFET has a threshold of an on-off switching operation speed depending on temperature. Such a switching operation is determined as a slope value of a transistor electrical characteristic, that is, subthreshold swing (SS). This SS value is unable to be less than 60 mV/decade which is a physical limit value at room temperature. Due to this limit, the existing MOSFET is unable to decrease a driving voltage to a certain level or less. Particularly, at a current time when power consumption in a static state more increases than power consumption in a dynamic state, there is a need to develop a new concept device capable of reducing the power consumption in the static state. 
     Thus, to address such a problem and reduce both the driving voltage and the leakage current, there is an urgent need to discover a new on-off switching mechanism which is completely different from the existing operating mechanism dependent on thermal diffusion. Because the development of a so-called new concept steep-slope semiconductor device for overcoming the limit of 60 mV/dec of a silicon-based CMOS is able to reduce an operating voltage and simultaneously decrease a leakage current to address a low voltage of the existing semiconductor device, a low power of the existing semiconductor device, and the limit of an integration level, it is expected to become a technology that not only replaces the existing MOSFET-based semiconductor device, but also leads the 4th industrial revolution in the future. 
     Various steep-slope field-effect transistors are developed to overcome the limit of the MOSFET, but existing steep-slope field-effect transistors operate with an operation principle of a structure different from the MOSFET to have a smaller on-current than the MOSFET and have a limitation in miniaturization. In addition, the drain current duration showing the steep-slope is only 30% of the entire switching current duration. 
     Thus, there is a need for a structure capable of addressing all of on-current, limited steep-slope performance, and a probability of miniaturization, which are limitations of the existing steep-slope field-effect transistors. 
     DETAILED DESCRIPTION OF THE INVENTION 
     Technical Problem 
     Embodiments of the inventive concept provide a steep-slope field-effect transistor capable of implementing steep-slope performance, a transistor having a transition layer and a control gate on an upper portion of a gate of an existing FET, and a fabrication method thereof. 
     In detail, the inventive concept provides a structure of a new structure steep-slope field-effect transistor for meeting a high on-current and a probability of miniaturization based on the structure and the operation principle of the existing MOSFET and simultaneously showing SS performance of 50% or more of the entire switching current duration and 60 mV/dec or less, an operation principle, and a fabrication method thereof. 
     Herein, technical problems to be addressed by the inventive concept are not limited to the problem, and may be expanded in various manners from a common part which does not deviate from the technical spirit and scope and the inventive concept. 
     Technical Solution 
     According to an exemplary embodiment, a steep-slope field-effect transistor may include a source, a channel region, and a drain formed on a substrate, a gate insulating film formed on an upper portion of the channel region, a floating gate formed on an upper portion of the gate insulating film, a transition layer formed on an upper portion of the floating gate, and a control gate formed on an upper portion of the transition layer. 
     The steep-slope field-effect transistor may apply a reference potential or more to the control gate to discharge or bring in at least one charge stored in the floating gate. 
     The channel region may be formed as one of a non-embedded structure including a planar structure, a fin structure, a nanosheet structure, a nanowire structure, and a multi-nanowire structure and an embedded structure. 
     The channel region of the non-embedded structure may be formed as one of the fin structure, the nanosheet structure, the nanowire structure, and the multi-nanowire structure used in a finFET, a tri-gate MOSFET, a Π-gate MOSFET, an Ω-gate MOSFET, a gate-all-around MOSFET, a bulk finFET, or a bulk gate-all-around MOSFET. 
     The channel region of the embedded structure may be formed as one of embedded channel structures used in a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET. 
     The channel region, the source, and the drain may include at least one of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium, silicon on insulator (SOI), and III-V semiconductor materials. 
     The source and the drain may be formed on left and right sides of the channel region for a lateral transistor, may be formed on upper and lower portions of the channel region for a vertical transistor, and may be formed of one of n-type silicon, p-type silicon, and metal silicide. 
     The source and the drain formed of the n-type silicon or the p-type silicon may be formed by at least one of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat-treatment. 
     The source and the drain formed of the metal silicide may include the metal silicide formed of one of tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolinium (Gd), terbium (Tb), cerium (Ce), platinum (Pt), and iridium (Ir) to improve junction using dopant segregation. 
     The gate insulating film may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium zirconium oxide (HZO), or hafnium oxynitride (HfON). 
     The floating gate may be formed by at least one or more of metal, two or three types of metal alloys, n+ polycrystalline silicon, p+ polycrystalline silicon, or silicide. 
     The floating gate may be formed as at least one of a non-embedded gate structure including a planar-gate structure, a multiple-gate structure, or a gate-all-around structure and an embedded gate structure, depending on a channel structure. 
     The floating gate of the non-embedded gate structure may be formed as one of non-embedded gate structures used in a finFET, a tri-gate MOSFET, a Π-gate MOSFET, an Ω-gate MOSFET, a gate-all-around MOSFET, a bulk finFET, or a bulk gate-all-around MOSFET. 
     The floating gate of the embedded gate structure may be formed as one of embedded gate structures used in a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET. 
     The transition layer may be formed including silicon (Si), germanium (Ge), Group III-V compounds, a 2-D material (at least one of carbon nanotube, MoS2, and graphene), silicon nitride (Si3N4), a nitride film, silicon oxynitride (SiON), silicon oxide (SiO2), a solid oxide film, aluminum oxide (Al2O3), IGZO, hafnium oxide (HfO2), a transition material, a semiconductor material (SrTiO3, SrZrO3, NiO, TiO2, HfOx, AlOx, NiOx, TiOx, TaOx, TaN, CuxO, CuOx, TiN, TaN, WOx, SiNx, VO2, IrO2, ZrOx, ZnO, NbOx, IGZO, HZO, or HfON), a solid electrolyte material (wherein the solid electrolyte material includes a sulfide-based material, an oxide-based material, and an ion conductive polymer). 
     The steep-slope field-effect transistor may apply a potential of a reference voltage or more to the control gate to generate a potential difference between the control gate and the floating gate and may discharge or bring in at least one charge stored in the floating gate. 
     The steep-slope field-effect transistor may more increase a change in voltage of the floating gate than a change in voltage of the control gate, when the control gate arrives at a specific voltage region, in a situation where at least one charge stored in the floating gate passes through an energy barrier by the transition layer to be discharged or brought in to the control gate, when a potential of a reference voltage or more is applied to the control gate. 
     The steep-slope field-effect transistor may more decrease a slope value of a threshold voltage or less, when putting the control gate as a gate to operate a device than when putting the floating gate as a gate to operate the device. 
     According to another exemplary embodiment, a fabrication method of a steep-slope field-effect transistor may include forming a source, a channel region, and a drain on a substrate, forming a gate insulating film on an upper portion of the channel region, forming a floating gate on an upper portion of the gate insulating film, forming a transition layer on an upper portion of the floating gate, and forming a control gate on an upper portion of the transition layer. 
     The forming of the control gate may include forming an inter-layer dielectric on an upper portion of the transition layer, etching the inter-layer dielectric to expose a portion of the upper portion of the transition layer, and forming the control gate on an upper portion of the exposed transition layer. 
     According to another exemplary embodiment, an operation method for a steep-slope field-effect transistor including a source, a channel region, and a drain formed on a substrate, a gate insulating film formed on an upper portion of the channel region, a floating gate formed on an upper portion of the gate insulating film, a transition layer formed on an upper portion of the floating gate, and a control gate formed on an upper portion of the transition layer may include applying a certain voltage to the control gate, such that a potential difference of a reference voltage or more is generated between the control gate and the floating gate and discharging or bringing in at least one charge stored in the floating gate by means of the potential difference of the reference voltage, the potential difference being generated between the control gate and the floating gate. 
     Advantageous Effects of the Invention 
     According to an embodiment of the inventive concept, steep-slope performance may be implemented, in a transistor having a transition layer and a control gate on an upper portion of a gate of an existing FET. 
     Such an inventive concept may meet a high on-current and a probability of miniaturization based on the structure and the operation principle of the existing MOSFET and may simultaneously show SS performance of 50% or more of the entire switching current duration and 60 mV/dec or less. By means of the structure and method, a semiconductor device having the steep-slope performance while ensuring the high on-current and the probability of miniaturization of the existing MOSFET without change may be implemented. Thus, a low-power operation of the semiconductor device is possible. 
     An embodiment of the inventive concept is applicable to various devices and systems including a logic device of the inventive concept. Thus, the inventive concept may be useful for various electronic devices such as a mobile phone, a smartphone, a PDA, a PMP, a digital camera, a camcorder, a PC, a server computer, a workstation, a notebook, a digital TV, a set-top box, a music player, a portable game console, a navigation device, a wearable device, an loT device, a VR device, and an AR device. 
     Herein, the effect of the inventive concept is not limited to the effects and may be expanded in various manners from a common part which does not deviate from the technical spirit and scope and the inventive concept. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a perspective view illustrating a steep-slope field-effect transistor Γ-FET according to embodiments of the inventive concept; 
         FIG. 2  is a plan view illustrating the steep-slope field-effect transistor of  FIG. 1 ; 
         FIG. 3  is a cross-sectional view taken along the line I-I′ of  FIG. 2 ; 
         FIG. 4  is a view illustrating various non-embedded gate FET structures capable of being used as a lower MOSFET under a transition layer in Γ-FET; 
         FIG. 5  is a view illustrating various embedded gate FET structures capable of being used as a lower MOSFET under a transition layer in Γ-FET; 
         FIG. 6  is a view illustrating a process of fabricating a steep-slope field-effect transistor according to embodiments of the inventive concept; 
         FIG. 7  is a view illustrating a transmission electron microscopy picture of a device fabricated according to an embodiment of the inventive concept; 
         FIG. 8  is a view schematically illustrating an environment where a steep-slope field-effect transistor is measured according to embodiments of the inventive concept; 
         FIG. 9  is a view illustrating a result value of actually measuring a steep-slope field-effect transistor fabricated according to embodiments of the inventive concept; 
         FIG. 10  is a view illustrating secondary data extracted from a result value of actually measuring a steep-slope field-effect transistor fabricated according to embodiments of the inventive concept; and 
         FIG. 11  is a view illustrating a process of deriving a floating gate voltage modeling formula. 
     
    
    
     BEST MODE 
     Advantages, features, and methods of accomplishing the same will become apparent with reference to embodiments described in detail below together with the accompanying drawings. However, the inventive concept is not limited by embodiments disclosed hereinafter, and may be implemented in various forms. Rather, these embodiments are provided so that this disclosure will be through and complete and will fully convey the concept of the invention to those skilled in the art, and the inventive concept will only be defined by the scope of the appended claims. 
     Terms used in the specification are used to describe embodiments of the inventive concept and are not intended to limit the scope of the inventive concept. In the specification, the terms of a singular form may include plural forms unless otherwise specified. The expressions “comprise” and/or “comprising” used herein indicate existence of stated components, steps, operations, and/or elements, but do not exclude presence or addition of one or more other components, steps, operations, and/or elements. 
     Unless otherwise defined herein, all terms (including technical and scientific terms) used in the specification may have the same meaning that is generally understood by a person skilled in the art. Also, terms which are defined in a dictionary and commonly used should be interpreted as not in an idealized or overly formal detect unless expressly so defined. 
     Hereinafter, exemplary embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. The same reference denotations are used for the same components on the drawings, and a duplicated description of the same components will be omitted. 
     Embodiments of the inventive concept have the subject matter of implementing steep-slope performance, in a transistor having a transition layer and a control gate on an upper portion of a gate of an existing FET. 
     Because of having a steep-slope on a current-voltage characteristic curve and being shown in the form of a Greek capital letter, ‘Γ’ (gamma), in appearance, a semiconductor device in the inventive concept is referred to as a Γ-FET to be used. 
     The Γ-FET may implement steep-slope performance while maintaining high on-current and a probability of miniaturization, which are advantages of an existing MOSFET, thus facilitating a low-power operation of the device. 
       FIG. 1  is a perspective view illustrating a steep-slope field-effect transistor Γ-FET  100  according to embodiments of the inventive concept.  FIG. 2  is a plan view seen from the top.  FIG. 3  is a cross-sectional view taken along the line I-I′ of  FIG. 2 .  FIGS. 4 and 5  are views illustrating various non-embedded and embedded gate FET structures capable of being used as a lower MOSFET under a transition layer in Γ-FET. 
     The Γ-FET may have a structure where a transition layer  102  and a control gate  101  are formed on a gate of an existing MOSFET and may use MOSFETs of various structures used in the field as lower MOSFETs. The Γ-FET may be fabricated by using MOSFETs of non-embedded and embedded structures partially shown in  FIGS. 4 and 5  other than flat MOSFETs shown in  FIGS. 1 to 3  as lower MOSFETs. 
     Referring to  FIGS. 1 to 3 , the Γ-FET  100  may include a substrate  108 , a channel region  106 , a gate insulating film  104 , a floating gate  103 , a transition layer  102 , a control gate  101 , a source  105  and a drain  107 . 
     The substrate  108  may include at least one of silicon, germanium, silicon-germanium, strained silicon, strained germanium, strained silicon-germanium, silicon on insulator (SOI), and III-V semiconductor materials. 
     The source  105  and the drain  107  may be formed on left and right sides of the channel region  106  for a lateral transistor, may be formed on upper and lower portions of the channel region  106  for a vertical transistor, and may be formed of one of n-type silicon, p-type silicon, and metal silicide. 
     The source  105  and the drain  106  formed of the n-type or the p-type silicon may be formed by at least one of diffusion, solid-phase diffusion, epitaxial growth, selective epitaxial growth, ion implantation, or subsequent heat-treatment. 
     The source and the drain formed of the metal silicide may include the metal silicide formed of one of tungsten (W), titanium (Ti), cobalt (Co), nickel (Ni), erbium (Er), ytterbium (Yb), samarium (Sm), yttrium (Y), gadolinium (Gd), terbium (Tb), cerium (Ce), platinum (Pt), plumbum (Pb), and iridium (Ir), which may improve junction using dopant segregation. 
     The channel region  106  may be formed as one of a non-embedded structure, such as a fin structure, a nanosheet structure in a form where an aspect ratio (height/width) of the channel region is less than or equal to 0.5, a nanowire structure in a form where the aspect ratio (height/width) of the channel region is greater than or equal to 0.5, or a multi-nanowire structure, which is partially shown in  FIG. 4 , including a planar structure or an embedded structure partially shown in  FIG. 5 . 
     Herein, the channel region of the embedded structure may be formed as one of embedded channel structures used in a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET. 
     The gate insulating film  104  may be formed on an upper portion of the channel region  106 . The gate insulating film  104  may insulate the floating gate  103  and the channel region  106 . For example, the gate insulating film  104  may be formed including at least one of silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ), silicon oxynitride (SiON), hafnium oxide (HfO 2 ), aluminum oxide (Al 2 O 3 ), zirconium oxide (ZrO 2 ), hafnium zirconium oxide (HZO), and hafnium oxynitride (HfON). Furthermore, the gate insulating film  104  may be formed including at least one of any insulating materials which do not show a memory characteristic. 
     The floating gate  103  may be formed on an upper portion of the gate insulating film  104 . For example, the floating gate  103  may be formed by at least one or more of metal, two or three types of metal alloys, n+ polycrystalline silicon, p+ polycrystalline silicon, or silicide (e.g., tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or the like). Because the floating gate  103  is located between a control gate and a channel region (or a channel), it may be referred to as an internal gate. 
     The floating gate  103  may be formed as at least one of a non-embedded gate structure, such as a multiple-gate structure partially shown in  FIG. 4  or a gate-all-around structure, including a planar-gate structure, and an embedded gate structure partially shown in  FIG. 5 , depending on a channel structure. 
     In this case, the floating gate of the non-embedded gate structure may be formed as one of non-embedded gate structures used in a finFET, a tri-gate MOSFET, a Π-gate MOSFET, an Ω-gate MOSFET, a gate-all-around MOSFET, a bulk finFET, or a bulk gate-all-around MOSFET. 
     In this case, the floating gate of the embedded gate structure may be formed as one of embedded gate structures used in a buried gate MOSFET, a recessed gate MOSFET, a sphere-shaped recessed gate MOSFET, a saddle finFET, a groove gate MOSFET, or a V-groove gate MOSFET. 
     The transition layer  102  may be formed on an upper portion of the floating gate  103 . The transition layer  102  may insulate the floating gate  103  and the control gate  101  (or a control gate structure). For example, the transition layer  102  may be formed including at least one of silicon (Si), germanium (Ge), Group III-V compounds, a 2-D material (at least one of and carbon nanotube, MoS 2 , and graphene), silicon nitride (Si 3 N 4 ), a nitride film, silicon oxynitride (SiON), silicon oxide (SiO 2 ), a solid oxide film, aluminum oxide (Al 2 O 3 ), IGZO, hafnium oxide (HfO 2 ), various other transition materials, a semiconductor material (SrTiO 3 , SrZrO 3 , NiO, TiO 2 , HfO x , AlO x , NiO x , TiO x , TaO x , TaN, Cu x O, CuO x , TiN, TaN, WO x , SiN x , VO 2 , IrO 2 , ZrO x , ZnO, NbO x , IGZO, HZO, or HfON), a solid electrolyte material (a sulfide-based material (e.g., Li 10 GeP 2 S 12 , Li 9.545 Si 1.74 P 1.44 S 11.7 Cl 0.3 , argyrodite, LPS (lithium phosphorus sulfide), LPS+LiCl), an oxide-based material (e.g., perovskite, NASICON (Na 1+x NZr 2 Si x P 3x O 12 , 0&lt;x&lt;3), LISICON (Li 2+2x Zn 1x GeO 4 ), LiPON (Li x PO y N z ), garnet) or an ion conductive polymer (e.g., polyethylene oxide (PEO), polyethylene glycol (PEG), a polyethylene glycol dimethacrylate (PEGDMA), polytetrafluoroethylene (PTFE), polyether ether ketone (PEEK), or nafion (C 7 HF 13 O 5 S—C 2 F 4 )). 
     Such a transition layer  102  may be composed of a single material or several materials. 
     In an embodiment, an area of the floating gate  103  with which the transition layer  102  or the control gate  101  is in contact may be narrower than the entire area of the floating gate. In other words, the transition layer  102  and the control gate  101  may be formed on at least a portion of an upper portion of the floating gate  103 . 
     The control gate  101  may be formed on an upper portion of the transition layer  102  and may generate a potential difference with the floating gate  103 . For example, the control gate  101  may be formed adjacent to the floating gate  103  to allow current to flow to the floating gate  103 . 
     In an embodiment, the control gate  101  may be formed by one or more of metal, two or three types of metal alloys, n+ polycrystalline silicon, p+ polycrystalline silicon, or silicide (e.g., tungsten silicide (WSi), titanium silicide (TiSi), cobalt silicide (CoSi), nickel silicide (NiSi), or the like). 
     When a voltage signal is applied to the control gate  101 , the transition layer  102  may allow current to flow to the floating gate  103  depending on a voltage difference between gates of both ends, that is, a voltage difference between the floating gate  103  and the control gate  101 . 
     In the inventive concept, all the channel region  106 , the source  105 , and the drain  107  may be formed on the substrate  108 . For example, the channel region  106  may be formed as a nanowire structure. In this case, as shown in  FIG. 3 , the gate insulating film  104 , the floating gate  103 , the transition layer  102 , and the control gate  101  may be formed to sequentially surround a portion of the channel region  106 , and an empty space may be present between the rest of the channel region  106  (e.g., the other portion except for the portion) and the substrate  108 . In other words, the channel region  106  may be supported by the components  104 ,  103 ,  102 , and  101  and may float like a bridge on the substrate  108 . 
     The Γ-FET  100  of the inventive concept having such a structure may apply a potential of a reference voltage or more to the control gate  101  to generate a potential difference between the control gate  101  and the floating gate  103 , thus discharging or bringing in at least one charge stored in the floating gate  103 . 
     At this time, when the potential of the reference voltage or more is applied to the control gate  101 , in a situation where at least one charge stored in the floating gate  103  passes through an energy barrier by the transition layer  102  to be discharged/brought in to the control gate  101 , when the control gate  101  arrives at a specific voltage region, the Γ-FET  100  may more increase a change in voltage of the floating gate  103  than a change in voltage of the control gate  101 . 
     At this time, the Γ-FET  100  may more decrease a subthreshold slope (SS) value of a threshold voltage or less, when putting a control gate electrode as a gate to operate a device, than when putting a floating gate electrode as a gate to operate the device. 
       FIG. 6  is a view illustrating a process of fabricating a Γ-FET  100 . 
     Referring to  FIG. 6 , the Γ-FET of the inventive concept may form an existing MOSFET structure (an internal MOSFET) through a process of forming a channel region, a source, and a drain on a substrate, forming a gate insulating film on an upper portion of the channel region, and forming a floating gate on an upper portion of the gate insulating film. 
     A transition layer TL and an inter-layer dielectric (ILD) may be sequentially formed on an upper portion of the floating gate, and a portion of the TL and the ILD may be etched such that a portion of the floating gate is exposed. As a portion of the TL and the ILD may be etched to form a floating gate pattern and as a portion of the ILD is etched to form a control gate pattern such that a portion of the TL is exposed, the Γ-FET of the inventive concept may be fabricated. 
       FIG. 7  is a view illustrating a transmission electron microscopy picture of a device fabricated according to an embodiment of the inventive concept, that is, a Γ-FET 100.  FIG. 8  is a view schematically illustrating an environment where a Γ-FET  100  is measured according to embodiments of the inventive concept. An electrical characteristic of the Γ-FET  100  may be ensured by applying voltage to a control gate  101 . Furthermore, voltage may be applied to a floating gate  103  on purpose to verify a characteristic of a lower MOSFET to be compared with it. There is no need to separately apply voltage to the floating gate in an actual device operation. 
       FIG. 9  is a result value of actually measuring a Γ-FET  100  and a lower MOSFET, and  FIG. 10  is secondary data extracted from it. The Γ-FET  100  may use only a smaller voltage for a switching operation than the lower MOSFET, and this may lead to a difference in subthreshold slope (SS). It may be seen that an SS value is greater than or equal to 60 mV/dec as is widely known for the lower MOSFET, whereas an SS of the Γ-FET  100  fabricated by adding the transition layer  102  and the control gate  101  on an upper portion thereof decreases to 26 mV/dec over the limit of 60 mV/dec. A cause why the steep-slope is implemented is because an amount of change in voltage of the control gate  101  is represented as a very large amount of change in voltage of the floating gate  103 . 
     A detailed principle of implementing the steep-slope may be described by means of a formula which will be described below. A device of the inventive concept should meet a formula used in a memory of the existing planar floating gate  103  in form. In the memory of the floating gate  103 , a voltage of the floating gate  103  is normally given as Equation 1 below with regard to capacitance coupling and a load in the floating gate  103 . 
     
       
         
           
             
               
                 
                   
                     V 
                     FG 
                   
                   = 
                   
                     
                       
                         
                           C 
                           CF 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             V 
                             CG 
                           
                           - 
                           
                             W 
                             CF 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         
                           C 
                           DF 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             V 
                             D 
                           
                           - 
                           
                             W 
                             DF 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         
                           C 
                           SF 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           
                             V 
                             S 
                           
                           - 
                           
                             W 
                             SF 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         
                           C 
                           OX 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         ( 
                         
                           φ 
                           - 
                           
                             W 
                             BF 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         Q 
                         F 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ] 
                 
               
             
           
         
       
     
       FIG. 11  is a view illustrating a process of deriving a voltage formula of a floating gate  103 . Q C , Q F , Q S , Q B , Q D  refer to charges of respective points, that is, a control gate  101 , a floating gate  103 , a source  105 , a surface of a channel  106 , and a drain  107 , and V CG , V FG , V S , φφ, V D  refer to voltages of respective points, that is, the control gate  101 , the floating gate  103 , the source  105 , the surface of the channel  106 , and the drain  107 . A capacitance and a flat-band voltage between the respective points may be respectively represented as alphabet C and subscript and alphabet W and subscript as shown in  FIG. 9 . In addition, the sum of all capacitances the floating gate  103  feels may be represented as C T . As shown in  FIG. 9 , the voltage formula of the floating gate  103  may be derived without any other assumption using a basic C-V formula. 
     Variables which varies in value with a change in voltage of the control gate  101  may be a voltage V CG  of the control gate  101 , a voltage V FG  of the floating gate  103 , an internal load Q F  of the floating gate  103 , and a surface potential (φφ) of the channel  106  of the lower MOSFET channel. 
     For a memory of the conventional floating gate  103 , a load in the floating gate  103  is not a variable because of being kept constant, but a charge of the floating gate  103  becomes also variable because of being supplied from the control gate  101  to the floating gate  103  through the transition layer  102  in the Γ-FET  100  of the inventive concept. 
     When Equation 1 above is differentiated into a voltage of the control gate  101 , a voltage change value of the floating gate  103  according to a change in voltage of the control gate  101  may be understood. Constants which are not changed disappear, only variables which vary with a voltage of the control gate  101  remain. This may be represented as Equation 2 below. 
     
       
         
           
             
               
                 
                   
                     
                       dV 
                       FG 
                     
                     
                       dV 
                       CG 
                     
                   
                   = 
                   
                     
                       
                         
                           C 
                           CF 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           dV 
                           CG 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                     + 
                     
                       
                         
                           C 
                           OX 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           φ 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           dQ 
                           F 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     Arranging Equation 2 above may be converted into Equation 3 below. 
     
       
         
           
             
               
                 
                   
                     
                       dV 
                       FG 
                     
                     
                       dV 
                       CG 
                     
                   
                   = 
                   
                     
                       
                         C 
                         CF 
                       
                       
                         C 
                         T 
                       
                     
                     + 
                     
                       
                         
                           C 
                           OX 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           φ 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           dQ 
                           F 
                         
                         dt 
                       
                       ⁢ 
                       
                         dt 
                         
                           dV 
                           CG 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   ] 
                 
               
             
           
         
       
     
     Herein, t may refer to time. The left term of Equation 3 above is a change in voltage of the floating gate  103  compared to a change in voltage of the control gate, and a steep-slope is possible when this value becomes greater than 1. 
     The amount of change in charge of the floating gate  103  over time may be current which flows through the transition layer  102 . Current (=dQ F /dt) which flows through the transition layer  102  may be a function of a difference between voltages loaded onto both ends of the transition layer  102 , that is, a voltage of the control gate  101  and a voltage of the floating gate  103 . Thus, Equation 3 above may change to Equation 4 below. 
     
       
         
           
             
               
                 
                   
                     
                       dV 
                       FG 
                     
                     
                       dV 
                       CG 
                     
                   
                   = 
                   
                     
                       
                         C 
                         CF 
                       
                       
                         C 
                         T 
                       
                     
                     + 
                     
                       
                         
                           C 
                           OX 
                         
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           φ 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         f 
                         ⁡ 
                         
                           ( 
                           
                             
                               V 
                               CG 
                             
                             - 
                             
                               V 
                               FG 
                             
                           
                           ) 
                         
                       
                       ⁢ 
                       
                         dt 
                         
                           dV 
                           CG 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
     Herein, f refers to current which flows through the transition layer, and is referred to as a transition current function to be used hereafter. 
     The transition current function may vary with voltage loaded onto both ends. A form and size of the transition current function may vary with a configuration and form of each of the control gate  101 , the transition layer  102 , and the floating gate  103 , including a characteristic of the transition layer  102 . A surface potential of the lower MOSFET among them may be deeply associated with a voltage of the floating gate  103 . Rearranging Equation 4 above to suit it may be represented as Equation 5 below. 
     
       
         
           
             
               
                 
                   
                     
                       
                         dV 
                         FG 
                       
                       
                         dV 
                         CG 
                       
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         - 
                         
                           
                             
                               C 
                               OX 
                             
                             
                               C 
                               T 
                             
                           
                           ⁢ 
                           
                             
                               d 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               φ 
                             
                             
                               dV 
                               FG 
                             
                           
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         C 
                         CF 
                       
                       
                         C 
                         T 
                       
                     
                     + 
                     
                       
                         1 
                         
                           C 
                           T 
                         
                       
                       ⁢ 
                       
                         f 
                         ⁡ 
                         
                           ( 
                           
                             
                               V 
                               CG 
                             
                             - 
                             
                               V 
                               FG 
                             
                           
                           ) 
                         
                       
                       ⁢ 
                       
                         
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           t 
                         
                         
                           dV 
                           CG 
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     Arranging such that only a change in voltage of the floating gate  103  compared to a change in voltage of the control gate  101  remains on a left term of Equation 5 below may be represented as Equation 6 below. 
     
       
         
           
             
               
                 
                   
                     
                       dV 
                       FG 
                     
                     
                       dV 
                       CG 
                     
                   
                   = 
                   
                     
                       
                         
                           C 
                           CF 
                         
                         
                           C 
                           T 
                         
                       
                       + 
                       
                         
                           1 
                           
                             C 
                             T 
                           
                         
                         ⁢ 
                         
                           f 
                           ⁡ 
                           
                             ( 
                             
                               
                                 V 
                                 CG 
                               
                               - 
                               
                                 V 
                                 FG 
                               
                             
                             ) 
                           
                         
                         ⁢ 
                         
                           dt 
                           
                             dV 
                             CG 
                           
                         
                       
                     
                     
                       ( 
                       
                         1 
                         - 
                         
                           
                             
                               C 
                               OX 
                             
                             
                               C 
                               T 
                             
                           
                           ⁢ 
                           
                             
                               d 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               φ 
                             
                             
                               dV 
                               FG 
                             
                           
                         
                       
                       ) 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                   ] 
                 
               
             
           
         
       
     
     There are four things to note here. First, there is no second term of the numerator in the right term in the memory of the conventional floating gate  103 . This is because current which flows from the control gate  101  to the floating gate  103  is not generated during a read operation. On the other hand, because there is a current term in the Γ-FET  100  of the inventive concept, the amount of change in voltage of the floating gate  103  may more increase than an existing technology. Secondly, when the denominator becomes less than 1 in a situation where the size of the numerator in the right term is adjusted to be large enough by means of the above-mentioned current term, because a change in voltage of the floating gate  103  becomes very large, steep-slope implementation is possible. Thirdly, the situation where the denominator of the right term becomes small is a situation where the amount of change in surface potential of the lower MOSFET becomes sufficiently large compared to a voltage of the floating gate  103 . Fourthly, the situation occurs in a weak inversion region where ON/OFF of the lower MOSFET is divided. 
     As a result, when the Γ-FET  100  of the inventive concept sweeps a voltage of the control gate  101  in the situation of adjusting the amount of current which flows through the transition layer  102  to increase the numerator in the right term of Equation 6 above, a denominator value in the right term may become small in the region where the ON/OFF of the lower MOSFET is divided, and consequently, the amount of change in voltage of the floating gate  103  increases to be very large compared to a voltage of the control gate, such that the steep-slope is implemented. 
     As described above, the steep-slope operation is greatly affected by the transition current function f, that is, a function of current which flows through the transition layer. When the transition current function value is too smaller than a surrounding term (C CF /C T ) irrespective of the size of voltage loaded onto both ends of the transition layer, the transition layer operates as the memory of the floating gate in which current does not flow and rather, the slope increases. On the other hand, when the transition layer operates as metal because the transition current function value is too large, because a voltage difference between the control gate and the floating gate is unable to be generated and because the amount of change in voltage of the floating gate and the amount of change in voltage of the control gate are always the same as each other, the steep-slope is unable to be implemented. For the steep-slope operation, the transition current function should be smaller than the surrounding term (C CF /C T ), when voltage loaded onto both ends is small, and has a need to be larger than the surrounding term (C CF /C T ), when the voltages loaded onto both the ends are large. In other words, the transition current function value should be larger or smaller than the surrounding term (C CF /C T ) to vary with the voltage loaded onto both the ends. 
     As such, the steep-slope FET an embodiment of the inventive concept may implement steep-slope performance, in a transistor having a transition layer and a control gate on an upper portion of a gate of an existing FET. 
     Such inventive concept may meet a high on-current and a probability of miniaturization based on the structure and the operation principle of the existing MOSFET and may simultaneously show SS performance of 50% or more of the entire switching current duration and 60 mV/dec or less. By means of the structure and method, the inventive concept may implement a semiconductor device having the steep-slope performance while ensuring the high on-current and the probability of miniaturization in the existing MOSFET without change. Thus, a low-power operation of the semiconductor device is possible. 
     In addition, the steep-slope FET of the inventive concept may apply a certain voltage to the control gate, such that a potential difference of a reference voltage or more between the control gate and the floating gate is generated, thus implementing the operation of discharging or bringing in at least one charge stored in the floating gate. In other words, an operation method of the steep-slope according to an embodiment of the inventive concept may include applying a certain voltage to a control gate to generate a potential difference of a reference voltage or more between the control gate and a floating gate and discharging and bringing in at least one charge stored in the floating gate by means of the potential difference of the reference voltage or more, which is generated between the control gate and the floating gate. 
     While a few exemplary embodiments have been shown and described with reference to the accompanying drawings, it will be apparent to those skilled in the art that various modifications and variations can be made from the foregoing descriptions. For example, adequate effects may be achieved even if the foregoing processes and methods are carried out in different order than described above, and/or the aforementioned elements, such as systems, structures, devices, or circuits, are combined or coupled in different forms and modes than as described above or be substituted or switched with other components or equivalents. 
     Therefore, other implements, other embodiments, and equivalents to claims are within the common part of the following claims.