Patent Publication Number: US-11653582-B2

Title: Chip containing an onboard non-volatile memory comprising a phase-change material

Description:
PRIORITY CLAIM 
     This application claims the priority benefit of French Application for Patent No. 1760543, filed on Nov. 9, 2017, the content of which is hereby incorporated by reference in its entirety to the maximum extent allowable by law. 
     TECHNICAL FIELD 
     The present disclosure relates to electronic chips and, in particular, a chip containing a non-volatile memory comprising a phase-change material, and to a method of manufacturing such a chip. 
     BACKGROUND 
     A chip containing an onboard non-volatile memory comprising a phase-change material simultaneously comprises logic circuits and phase-change material memory cells. The memory cells and the various transistors of the circuits are electrically connected by vias to interconnection tracks located in electrically-insulating layers. 
     Each memory cell comprises a phase-change material and a resistive element for heating the phase-change material. The resistive heating element enables to have the phase-change material transit from a crystalline state to the amorphous state for the programming of the memory cell, and transit from an amorphous state to the crystalline state to erase the memory cell. The heating element is typically located under the phase-change material and on a via of connection to one of the terminals of one of the memory transistors. 
     Chips containing an onboard non-volatile memory comprising a phase-change material obtained by known methods have various disadvantages. In particular, it is desired to decrease the electric resistance of access to the transistors due, in particular, to the electric resistance of the vias. 
     SUMMARY 
     An embodiment provides overcoming all or part of the above disadvantages. 
     Thus, an embodiment provides a method of manufacturing an electronic chip containing memory cells comprising a phase-change material and transistors, comprising: a) forming the transistors and first and second vias extending from terminals of the transistors and reaching a same height; b) forming a first metal level comprising first interconnection tracks in contact with the first vias; c) for each memory cell, forming an element for heating the phase-change material on one of the second vias; d) forming the phase-change material of each memory cell on the heating element; and e) forming a second metal level comprising second interconnection tracks and located above the phase-change materials, and forming third vias extending from the phase-change materials to the second interconnection tracks. 
     According to an embodiment, the method comprises, between steps b) and c), depositing a protection layer on the first interconnection tracks. 
     According to an embodiment, the protection layer is made of silicon nitride. 
     According to an embodiment, the method comprises at step c): c1) depositing a first layer made of a thermal insulator covering the second vias; c2) etching portions of the first layer all the way to the level of the tops of the second vias, and then forming first spacers against the sides of the remaining portions of the first layer, while ascertaining that the top of each second via is partially covered with one of the first spacers and partially exposed; c3) forming a second conformal layer made of the material of the future heating element; c4) forming a second spacer covering the portion of the second layer located against each first spacer, and then removing the exposed portions of the second layer; c5) forming a third spacer against each second spacer; c6) partially etching the structure down to the level of the tops of second vias to individualize the heating elements each formed of a portion of the second layer; and c7) covering the structure with a third protection layer. 
     According to an embodiment, the method comprises at step c): c8) depositing a thermal insulator in the portions etched at step c2) and left exposed at step c5), up to the upper level of the first layer; c9) depositing a thermal insulator in the portions etched at step c5) and left empty after step c6), up to the upper level of the first layer; and c10) removing the portions of the structure located above the level of the tops of the heating elements. 
     According to an embodiment, a band extending in the spacer width direction is left in place at step c6), said band comprising the heating element between portions of the spacers, the width of said band being smaller than 30 nm. 
     According to an embodiment, the method comprises, before step c1), depositing an etch step layer. 
     According to an embodiment, each thermal insulator is made of silicon oxide or of silicon oxycarbide, and said spacers and the third layer are made of silicon nitride or of silicon carbonitride. 
     An embodiment provides an electronic chip comprising: transistors and memory cells comprising a phase-change material; a first metal level comprising first interconnection tracks connected to terminals of the transistors by first vias; and a second metal level comprising second interconnection tracks and located above the first metal level, wherein the phase-change materials of the memory cells are located between the first and second metal levels on heating elements connected to the transistors by second vias, and are connected to second tracks of the second metal level by third vias. 
     According to an embodiment, each heating element crosses a thermally-insulating region. 
     According to an embodiment, each heating element is surrounded with a protection region separating the heating element from the thermally-insulating region. 
     According to an embodiment, the thermally-insulating region comprises silicon oxide or silicon oxycarbide, and the protection region is made of silicon nitride or of silicon carbonitride. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The foregoing and other features and advantages will be discussed in detail in the following non-limiting description of specific embodiments in connection with the accompanying drawings, wherein: 
         FIG.  1    is a partial simplified cross-section view of a chip containing an onboard memory comprising a phase-change material; 
         FIGS.  2 A to  2 C  are partial simplified cross-section views illustrating steps of an embodiment of a method of manufacturing a chip containing an onboard memory comprising a phase-change material; and 
         FIGS.  3 A to  3 M  schematically illustrate a more detailed example of steps of implementation of the method of  FIGS.  2 A to  2 C . 
     
    
    
     DETAILED DESCRIPTION 
     The same elements have been designated with the same reference numerals in the various drawings and, further, the various drawings are not to scale. For clarity, only those steps and elements which are useful to the understanding of the described embodiments have been shown and are detailed. In particular, the transistors and their manufacturing method, which are well known by those skilled in the art, are not described in detail. 
     In the following description, when reference is made to terms qualifying the position, such as terms “top”, “bottom”, “upper”, “lower”, etc., reference is made to the orientation of the concerned elements in the concerned cross-section views, it being understood that, in practice, the described devices may have a different orientation. 
       FIG.  1    is a partial simplified cross-section view of a chip containing an onboard memory comprising a phase-change material. 
     The chip comprises a region  102  where circuits comprising transistors  110  are located, and a region  104  where phase-change material memory cells associated with transistors  112  are located. A transistor  110  and a transistor  112  are each represented by an insulated gate having spacers on its sides. The chip has been obtained as described hereafter. 
     Transistors  110  and  112  have first been formed inside and on top of a substrate  114 . Steps of depositing electrically-insulating layers (not shown) on the structure and of forming electrically-conductive elements in the insulator layers have then been implemented. The conductive elements formed successively are:
         vias  120 A and vias  120 B, vias  120 A extending from contacting areas  122 A of the drains of transistors  112 , and vias  120 B extending from contacting areas  122 B of the drains, of the sources, and of the gates of transistors  110  and of the sources of transistors  112 ; vias  120 A and  120 B reach a same level L 1  above substrate  114 ;   memory cells  130  each comprising, on one of vias  120 A, a heating element  132  topped with a region  134  of a phase-change material;   vias  140  located on vias  120 B, and vias  142 , each located on one of regions  134 , vias  140  and  142  extending all the way to a same level L 2  above substrate  114 ;   a first metal level M 1  comprising first interconnection tracks  150  in contact with vias  140  and  142 ; and   a second metal level M 2  comprising second interconnection tracks  160  connected to tracks  150  by vias  162 .       

     In the chip thus obtained, contacting areas, or terminals,  122 B of the transistors are connected to tracks  150  of first metallization level M 1  by stacks  170  of a via  120 B and of a via  140 . A problem is that the electric resistance of each stack  170  is high, particularly due to the great height of stack  170  and due to various issues, particularly of alignment, to form the electric contact between via  120 B and via  140 . Such an electric resistance results in various performance and electric power consumption issues, particularly for the circuits of region  102 . 
       FIGS.  2 A to  2 C  are partial simplified cross-section views illustrating steps of an embodiment of a method of manufacturing a chip containing an onboard memory comprising a phase-change material. Only a region  104  of phase-change material memory is partially shown in  FIGS.  2 A and  2 B . As in  FIG.  1 A , the insulating layers covering the transistors and the substrate are not shown in  FIGS.  2 A and  2 B . 
     At the step of  FIG.  2 A , elements identical or similar to those of the chip of  FIG.  1    located under the same level L 1  as that of  FIG.  1   , arranged identically or similarly, are formed. These elements are particularly, in region  104 , a transistor  112  and, from drain contacting areas  122 A and source contacting areas  122 B of transistor  112 , respective vias  120 A and  120 B extending all the way to level L 1 . 
     A first metal level M 1 ′ comprising first interconnection tracks  202  on vias  120 B is formed. It should be noted that no track is formed on vias  120 A. Conversely to tracks  150  of  FIG.  1   , tracks  202  are directly in contact with vias  120 B. 
     At the step of  FIG.  2 B , memory cells  130  each comprising, on one of vias  120 A, a heating element  132  topped with a phase-change material region  134  are formed. 
     At the step of  FIG.  2 C , a second metal level M 2 , located above the level of regions  134  and comprising second interconnection tracks  160 , is formed. Tracks  160  are connected to tracks  150  by vias  162  and to regions  134  by vias  204 . 
     In the obtained chip, each memory cell has its phase-change material  134  located between levels M 1 ′ and M 2 . 
     According to an advantage, due to the fact that phase-change material regions  134  are located between levels M 1 ′ and M 2 , it has been possible to directly connect tracks  202  of first metal level M 1 ′ to contacting areas  122 B of the transistors by vias  120 B. The electric resistance of access to the transistors is particularly decreased. Indeed, unlike stacks  170  of the chip of  FIG.  1   , vias  120 B are formed in a single step. Further, vias  120 B have a decreased height as compared with stacks  170  of the chip of  FIG.  1   . As a result, the circuits of region  102  have a decreased electric power consumption. It should be noted that this advantage of a decreased electric resistance also exists for the direct connection by via  120 B between transistors  112  of region  104  of memory cells and tracks  202 , which provides a decreased electric power consumption of the memory cells. 
     According to another advantage, the connection between phase-change material  134  and tracks  160  is formed by single via  204 , unlike the connection between phase-change material  134  and tracks  160  of the chips of  FIG.  1   , formed by a via  142 , a track  150 , and a via  162 . Various issues of the forming of a via  142  of  FIG.  1   , such as alignment issues, are thus avoided. 
       FIGS.  3 A to  3 L  schematically illustrate a more detailed example of steps of implementation of the method of  FIGS.  2 A to  2 C .  FIGS.  3 A to  3 F  are partial cross-section views along a first direction,  FIG.  3 G  is a partial top view,  FIG.  3 H  is a partial perspective view,  FIGS.  3 I and  3 J  are partial cross-section views along a second direction orthogonal to the first direction, and  FIGS.  3 K and  3 L  are partial cross-sections views along the first direction. Only memory region  104  is partially shown. 
       FIG.  3 A  illustrates the step of forming the first metal level of  FIG.  2 A . It is started from the structure comprising the elements located under level L 1 , particularly vias  120 A and  120 B, only the upper portions thereof being shown. Vias  120 A and  120 B are in an insulator layer  302 , for example made of silicon oxide or comprising silicon oxide, and are flush with the surface of insulator layer  302  at level L 1 . As an example, vias  120 A and  120 B are made of tungsten. 
     The structure is covered with an etch stop layer  304 , for example, made of silicon carbonitride. A layer  306  is then formed on the structure, preferably thermally insulating and with a low dielectric constant, for example, made of silicon oxide, for example, porous. As an example, layer  304  has a thickness in the range from 10 to 25 nm. Layer  306  has a thickness for example in the range from 30 to 200 nm. 
     Trenches  308  crossing layers  306  and  304  at the locations of the future first interconnection tracks  202 , that is, above vias  120 B, are then etched. The trenches are etched all the way to the upper surface, or top, or vias  120 B. 
     After this, trenches  308  are filled with an electrically-conductive material, for example, copper, up to the upper level of layer  306 . To perform this filling, the structure may for example be covered with a layer of the conductive material filling trenches  308 , and then all the elements located above the upper level of layer  306  may be removed by chem.-mech. polishing. 
     At the step of  FIG.  3 B , the structure is covered with a layer  310 , for example, made of silicon nitride, intended to protect tracks  202  during the forming of the memory cell. A silicon oxide layer  312  is then formed on the structure. As an example, protection layer  310  has a thickness in the range from 10 to 40 nm. 
     After this, the entire thickness of layers  312 ,  310 ,  306  and  304  is etched in portions  314 , to at least partly expose the top of each of vias  120 A. The remaining portions of the etched layers exhibit sides  316 . For each via  120 A, a side  316  is positioned with respect to via  120 A in a selected way described hereafter in relation with the step of  FIG.  3 C . 
     A the step of  FIG.  3 C , a spacer  320  is formed against each side  316 , that is, the structure is covered with a layer of the material of spacer  320 , for example, a silicon nitride, and the horizontal portions of this layer are removed by anisotropic etching. The position relative to via  120 A of side  316  obtained at the step of  FIG.  3 B , and the thickness of spacer  320 , are selected so that spacer  320  partially covers the top of via  120 A while leaving via  120 A partially exposed, that is, so that the exposed side of the spacer is located vertically in line with via  120 A. As an example, spacers  320  have a thickness in the range from 5 to 30 nm. 
     At the step of  FIG.  3 D , the structure is conformally covered with a layer  132 A intended to form the future heating elements. Layer  132 A is for example made of silicon nitride and of titanium TiSiN. Layer  132 A covers a side of each spacer  320  and a portion of each via  120 A. As an example, layer  132 A has a thickness in the range from 2 to 10 nm. 
     At the step of  FIG.  3 E , a spacer  330 , for example, made of silicon nitride, is formed against the portion of layer  132 A covering each spacer  320 . The portions which have remained exposed of layer  132 A are removed by etching. At this step, there only remain of layer  132 A vertical portions  332  between spacers  320  and  330 , and horizontal portions  334  under spacers  330 . As an example, spacers  330  have a thickness in the range from 5 to 30 nm. 
     At the step of  FIG.  3 F , a spacer  340 , for example, made of silicon nitride, is formed against each spacer  330 . Spacers  340  cover the sides of horizontal portions  334  of the remainders of layer  132 A. As an example, spacers  340  have a thickness in the range from 5 to 30 nm. 
     After this, the structure is covered with a layer  342 , preferably thermally insulating, for example, made of silicon oxide, reaching, in the portions  314  etched at the step of  FIG.  3 B  and which have remained exposed, the level of the upper surface of layer  310 . All the elements located abode the upper level of layer  310  are then removed by chemical-mechanical polishing (CMP). 
       FIG.  3 G  is a top view of the structure of  FIG.  3 F  in the example of a rectilinear side  316 . The various elements covering vias  120 A,  120 B and insulator  302 , up to the upper level of vias  120 A and  120 B, are etched in regions  350  shown in  FIG.  3 G  by hatchings delimited by dotted lines. Regions  350  are provided so that the etching leaves in place, for each via  120 A, the elements located in top view for example in a strip  352  running over via  120 A and extending in the spacer thickness direction, that is, orthogonally to the direction of side  316 . Regions  350  are provided so that the etching further leaves in place the portions of layers  304 ,  306  and of protection layer  310  surrounding and covering tracks  202 . 
       FIG.  3 H  shows the structure obtained after etching of regions  350 . The etching has individualized for each via  120 A a vertical portion of layer  132 A located on via  120 A (only a portion of the upper surface thereof being shown). This portion forms heating element  132 . The heating element extends in its lower portion in a horizontal portion  334 . Portions of spacers  320 ,  330  sandwiching the heating element and covering horizontal portion  334 , and a spacer portion  340  against the side of horizontal portion  334 , have been left in place. 
     Preferably, the width of the heating element, corresponding to the width of strip  352 , is small, for example, smaller than 30 nm. As an example, the heating element is integrally located on via  120 A. As an example, via  120 A has a diameter in the range from 30 to 60 nm. 
     At the step of  FIG.  3 I , the entire structure is conformally covered with a protection layer  360 , for example, made of silicon nitride. 
     At the step of  FIG.  3 J , a layer  370  of a material which is preferably thermally insulating, for example, a silicon oxide, is deposited on the structure, reaching, in the portions of regions  150  which have remained exposed, the upper level of heating elements  132 . All the elements located above the upper level of heating elements  132  are then removed by chemical-mechanical polishing. 
     Each heating element  132  thus obtained is totally surrounded with the portions of spacers  320 ,  330 ,  340  and of layer  360 . 
     At the step of  FIG.  3 K , the structure is covered: with a layer  134 A of the phase-change material, for example, a chalcogenide; with an electrically-conductive layer  380 , for example, made of titanium nitride; and then with a masking layer  382 , for example, made of silicon nitride. 
     At the step of  FIG.  3 L , layers  382 ,  380 , and  134 A are etched in regions  390 , to leave in place, on each heating element, a region  134 A of the phase-change material topped with a portion of layer  380  forming a contacting area. The memory cells have thus been formed. 
     After this, the structure is covered with a protection layer  392 , for example, a silicon nitride. 
     The step of  FIG.  3 M  corresponds to that of  FIG.  2 C , of forming vias  162  and  204  and second interconnection tracks  160 . The structure is covered with an insulator  400 , for example, based on silicon oxide, up to a level L 3 . 
     The structure is then successively covered with an etch stop layer  402 , for example, made of silicon carbonitride, and with a layer  404  having a low dielectric constant, for example, made of silicon oxide, for example, porous. 
     Trenches  406  crossing layers  404  and  402  across their entire thickness are etched at the locations of the future second interconnection tracks  160 . 
     The locations of the future vias  162  and  204  are etched from the bottom of trenches  406 , all the way to tracks  202  for vias  162  (location  408 ), and all the way to contacting area  380  (location  410 ) for vias  204 . 
     After this, trenches  406  and locations  408  and  410  are filled with a conductive material, for example, copper, up to the upper level of layer  404 . 
     In addition to the advantages already described, an advantage of the chip obtained by implementing the method example of  FIGS.  3 A to  3 M  results from the fact that each heating element  132  is laterally surrounded with portions of layers  306  and  342  as well as with portions of layer  370  (not shown in  FIG.  3 M ). The portions of layers  306  and  342  surround heating element  132  along a direction orthogonal to that of side  316  (along the plane of  FIG.  3 M ), and the portions of layer  370  surround heating element  132  along a direction parallel to that of side  316 . The portions of layers  306 ,  342 , and  370  thus form a thermally-insulating region, for example, made of silicon oxide, crossed by heating element  132 . Silicon oxide has a low thermal conductivity, smaller than a value in the order of 1.5 W/(m·K), that is, for example, more than from 10 to 40 times smaller than that of silicon nitride (which may for example be in the order of 17 W/(m·K)). This enables to avoid, when the heating element heats up for example during the memory cell programming, for the regions surrounding the heating element to also heat up. Such a heating would risk causing, for example, the erasing of neighboring memory cells. Further, it is avoided for part of the heat generated in the heating element to be lost in the surrounding regions. Small quantities of generated heat are then sufficient to heat up the heating element, which corresponds to a decreased electric power consumption to program and erase the memory cell. 
     It should be noted that each heating element is separated from the materials of layers  306 ,  342 , and  370  by portions of spacers  320 ,  330 , and  340  and of layer  360 , for example, made of silicon nitride. The portions of spacers  320 ,  330 , and  340  and of layer  360  thus form a region of protection of the heating element. This enables for each heating element to be only in contact with the silicon nitride. A contact between the heating element and a material such as, for example, the silicon oxide of layers  306 ,  342 , and  370 , is thus avoided. Such a contact would be likely to alter the material of the heating element, for example, if the heating element is made of titanium silicon nitride. 
     According to another advantage, the provision of a heating element having a decreased width enables to decrease the volume of phase-change material to be heated for the programming or the erasing. Small quantities of heat generated in the heating element are sufficient to program and erase the memory cell, which provides a decreased electric power consumption. 
     Specific embodiments have been described. Various alterations, modifications, and improvements will occur to those skilled in the art. Although, in the steps of  FIGS.  3 A to  3 M , thermally-insulating regions (portions of layers  306 ,  342 , and  370 ) crossed by heating elements are made of silicon oxide, any adapted thermally-insulating material, that is, having a thermal conductivity smaller for example than 2 W/(m·K), may be used for these regions. As an example, the silicon oxide of all or part of these regions may be replaced with silicon oxycarbide, for example, porous. Spacers  320  and  340  may then be omitted in the case where a material which can be in contact with the heating element without risking damaging it is used. 
     Further, although spacers  320 ,  330 , and  340 , and layer  370  described hereabove are made of silicon nitride, the silicon nitride of all or part of these regions may be replaced with any other material capable of protecting the heating element, such as silicon carbonitride. 
     Although a specific example of steps of implementation of the method of  FIGS.  2 A to  2 C  has been described in relation with  FIGS.  3 A to  3 M , any other steps capable of implementing the method of  FIGS.  2 A to  2 C  may be provided. In particular, the steps of forming the heating elements and of forming phase-change material regions, described in relation with  FIGS.  3 A to  3 M , may be replaced with any method of forming heating elements topped with phase-change material regions. 
     Although the transistors  110  and  112  described hereabove are represented by gates having spacers on their sides, transistors  110  and/or  112  may be bipolar transistors, the above-described gates, sources, and drains then respectively corresponding to the bases, collectors, and emitters of the transistors. 
     Such alterations, modifications, and improvements are intended to be part of this disclosure, and are intended to be within the spirit and the scope of the present invention. Accordingly, the foregoing description is by way of example only and is not intended to be limiting. The present invention is limited only as defined in the following claims and the equivalents thereto.