Patent Publication Number: US-2023163199-A1

Title: Method for fabricating thin film transistor substrate

Description:
FIELD OF INVENTION 
     The present disclosure relates to a field of display panel technology, and particularly to a method for fabricating a thin film transistor substrate. 
     BACKGROUND 
     Thin film transistors with top-gate structure (top-gate TFTs) have low parasitic capacitance and excellent electrical characteristics and, thus, are widely used in display devices. 
     In the prior art, a top-gate TFT is fabricated by a self-aligning process between a gate pattern and a gate insulating pattern. The gate pattern is usually fabricated by a wet etching process. The gate insulating pattern is fabricated by a dry etching process. When a gate layer is etched by the wet etching process, an etching solution will etch more gate layer under a photoresist so that the gate pattern is smaller than the gate insulating pattern. That is, an orthographic projection of the gate pattern does not completely coincide with that of the gate insulating pattern on a substrate. Because there is no gate on edge of the gate insulating pattern, a portion of an active layer pattern under a portion of the gate insulating pattern that is not covered by the gate is not regulated by the gate, resulting in insufficient turn-on current of the top-gate TFT, thereby affecting electrical characteristics of the top-gate TFT and affecting display effect of a display device. 
     Therefore, it is necessary to develop a novel method for fabricating a thin film transistor substrate to overcome the drawbacks of the prior art. 
     SUMMARY OF DISCLOSURE 
     The present disclosure provides a method for fabricating a thin film transistor substrate to solve the technical problem, in the prior art, of the insufficient turn-on current of the thin film transistor caused by no gate on the edge of the gate insulating layer pattern. 
     To solve the aforementioned technical problem, the present disclosure provides a method for fabricating a thin film transistor substrate. The method comprises: 
     Step S 1 : providing a substrate, depositing a light shielding layer on the substrate, and etching the light shielding layer to form a light shielding layer pattern; 
     Step S 2 : sequentially depositing a buffer layer and an active layer, and etching the active layer to form an active layer pattern; 
     Step S 3 : sequentially depositing a gate insulating layer and a gate layer on the active layer pattern, and wet etching the gate layer to form a gate layer pattern with a photoresist; 
     Step S 4 : stripping off the photoresist, dry etching a surface of the gate layer pattern, and forming a protective layer on the surface of the gate layer pattern; and dry etching the gate insulating layer to form a gate insulating layer pattern and metalizing a non-channel region of the active layer pattern; 
     Step S 5 : depositing an interlayer dielectric layer, and forming a first via hole through the interlayer dielectric layer; 
     Step S 6 : depositing a source/drain layer and etching the source/drain layer to form a source/drain layer pattern; 
     Step S 7 : depositing an organic layer, and forming a second via hole through the organic layer; and 
     Step S 8 : depositing a pixel electrode layer and etching the pixel electrode layer to form a pixel electrode. 
     In Step S 4 , the dry etching the gate insulating layer to form the gate insulating layer pattern and metalizing the non-channel region of the active layer pattern are performed by using the gate layer pattern as a mask. This step can ensure that an orthographic projection of the gate layer pattern completely coincides with that of the gate insulating pattern on the substrate. That is, the entire active layer pattern is under the gate insulating layer pattern. Therefore, the entire active layer pattern can be regulated by the gate layer pattern. This step solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. 
     In an embodiment, the active layer is an oxide semiconductor. 
     In an embodiment, the oxide semiconductor is indium gallium zinc oxide. 
     In an embodiment, the active layer has a thickness of 400 Å to 600 Å. 
     In an embodiment, the gate insulating layer is composed of silicon oxide or silicon nitride. 
     In an embodiment, in the step S 4 , the dry etching the surface of the gate layer pattern is performed with a fluorine-based etching gas. 
     In an embodiment, the fluorine-based etching gas is composed of nitrogen trifluoride and oxygen. 
     In an embodiment, in the step S 4 , the metalizing the non-channel region of the active layer pattern is performed by bombarding the non-channel region with argon or helium ions. 
     In an embodiment, in the step S 4 , the metalizing the non-channel region of the active layer pattern is performed by implanting aluminum or calcium ions. 
     In an embodiment, the protective layer has a thickness ranging from 40 Å to 60 Å. 
     The present disclosure provides a method for fabricating a thin film transistor substrate, comprising: sequentially depositing an active layer, a gate insulating layer, and a gate layer on a substrate, wet etching the gate layer to form a gate layer pattern, forming a protective layer on a surface of the gate layer pattern, and etching the gate insulating layer and metalizing a naked region of the active layer with the gate layer pattern as a mask. This method can ensure that an orthographic projection of the gate layer pattern completely coincides with that of the gate insulating pattern on the substrate. That is, the entire active layer pattern is under the gate insulating layer pattern. Therefore, the entire active layer pattern can be regulated by the gate layer pattern. This method solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, a brief description of accompanying drawings used in the description of the embodiments of the present disclosure or the prior art will be given below. The accompanying drawings in the following description are merely some embodiments of the present disclosure. For those skilled in the art, other drawings may be obtained from these accompanying drawings without creative labor. 
         FIG.  1    is a flowchart of a method for fabricating a thin film transistor substrate according to an embodiment of the present disclosure. 
         FIG.  2    is a schematic diagram of a thin film transistor substrate in step S 1  in the method according to the embodiment of the present disclosure. 
         FIG.  3    is a schematic diagram of a thin film transistor substrate in step S 2  in the method according to the embodiment of the present disclosure. 
         FIG.  4    is a schematic diagram of a thin film transistor substrate in step S 3  in the method according to the embodiment of the present disclosure. 
         FIG.  5    is a schematic diagram of a thin film transistor substrate in step S 4  in the method according to the embodiment of the present disclosure. 
         FIG.  6    is a schematic diagram of a thin film transistor substrate in step S 5  in the method according to the embodiment of the present disclosure. 
         FIG.  7    is a schematic diagram of a thin film transistor substrate in step S 6  in the method according to the embodiment of the present disclosure. 
         FIG.  8    is a schematic diagram of a thin film transistor substrate in step S 7  in the method according to the embodiment of the present disclosure. 
         FIG.  9    is a schematic diagram of a thin film transistor substrate in step S 8  in the method according to the embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. It is apparent that the described embodiments are merely a part of the embodiments of the present disclosure and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present disclosure without creative labor are within the claimed scope of the present disclosure. 
     The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present disclosure. The present disclosure may be embodied in many alternative ways and should not be construed as being limited only to the embodiments described herein. 
     The present disclosure provides a method for fabricating a thin film transistor substrate. Please refer to  FIG.  1   , which is a flowchart of a method for fabricating a thin film transistor substrate according to an embodiment of the present disclosure. The method comprises the following steps. 
     Step S 1 : providing a substrate  100 , depositing a light shielding layer on the substrate  100 , and etching the light shielding layer to form a light shielding layer pattern  11 . 
     Please refer to  FIG.  2   , which is a schematic diagram of a thin film transistor substrate in step S 1  in the method according to the embodiment of the present disclosure. 
     Step S 2 : depositing a buffer layer  12  and an active layer, and etching the active layer to form an active layer pattern  13 . 
     Please refer to  FIG.  3   , which is a schematic diagram of a thin film transistor substrate in step S 2  in the method according to the embodiment of the present disclosure. 
     In this embodiment, the active layer may be composed of indium tin oxide (ITO), indium zinc oxide (IZO) or indium gallium zinc oxide (IGZO), but is not limited thereto. 
     In this embodiment, the active layer has a thickness of 400 Å to 600 Å. 
     Step S 3 : sequentially depositing agate insulating layer  14  and agate layer on the active layer pattern  13 , and wet etching the gate layer to form a gate layer pattern  15  with a photoresist. 
     Please refer to  FIG.  4   , which is a schematic diagram of a thin film transistor substrate in step S 3  in the method according to the embodiment of the present disclosure. 
     In this embodiment, the gate insulating layer  14  may be composed of silicon oxide or silicon nitride but is not limited thereto. 
     Step S 4 : stripping off the photoresist, dry etching a surface of the gate layer pattern  15 , and forming a protective layer  151  on the surface of the gate layer pattern  15 ; and dry etching the gate insulating layer  14  to form a gate insulating layer pattern  14 , and metalizing a non-channel region  131  of the active layer pattern  13 . 
     Please refer to  FIG.  5   , which a schematic diagram of a thin film transistor substrate in step S 4  in the method according to the embodiment of the present disclosure. 
     The protective layer  151  is configured to protecting the gate layer pattern  15 , and preventing the gate layer pattern  15  from being etched when the gate insulating layer  14  is etched and the active layer pattern  13  is metalized. 
     In this embodiment, the protective layer  151  has a thickness ranging from 40 Å to 60 Å. 
     In this embodiment, the dry etching the surface of the gate layer pattern  15  is performed with a fluorine-based etching gas, specifically nitrogen trifluoride and oxygen. 
     In this embodiment, the metalizing the non-channel region of the active layer pattern  15  may be performed by bombarding the non-channel region with argon or helium ions, or by implanting aluminum or calcium ions, but is not limited thereto. 
     The dry etching the gate insulating layer  14  to form the gate insulating layer pattern  14  and metalizing the non-channel region  131  of the active layer pattern  13  are performed by using the gate layer pattern  15  as a mask. This step can ensure that width of the gate layer pattern  15  is equal to that of the gate insulating layer pattern  14 , and that an orthographic projection of the gate layer pattern  15  completely coincides with that of the gate insulating pattern  14  on the substrate. That is, the entire active layer pattern  13  is under the gate insulating layer pattern  14 . Therefore, the entire active layer pattern  13  can be regulated by the gate layer pattern  15 . This step solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. 
     Step S 5 : depositing an interlayer dielectric layer  16 , and forming a first via hole  161  through the interlayer dielectric layer  16 . 
     Please refer to  FIG.  6   , which is a schematic diagram of a thin film transistor substrate in step S 5  in the method according to the embodiment of the present disclosure. 
     Step S 6 : depositing a source/drain layer and etching the source/drain layer to form a source/drain layer pattern  17 . 
     Please refer to  FIG.  7   , which is a schematic diagram of a thin film transistor substrate in step S 6  in the method according to the embodiment of the present disclosure 
     Step S 7 : depositing an organic layer  18 , and forming a second via hole  181  through the organic layer  18 . 
     Please refer to  FIG.  8   , which is a schematic diagram of a thin film transistor substrate in step S 7  in the method according to the embodiment of the present disclosure. 
     Step S 8 : depositing a pixel electrode layer and etching the pixel electrode layer to form a pixel electrode  19 . 
     Please refer to  FIG.  9   , which is a schematic diagram of a thin film transistor substrate in step S 8  in the method according to the embodiment of the present disclosure. 
     The present disclosure provides a method for fabricating a thin film transistor substrate, comprising: sequentially depositing an active layer, a gate insulating layer, and a gate layer on a substrate, wet etching the gate layer to form a gate layer pattern, forming a protective layer on a surface of the gate layer pattern, and etching the gate insulating layer and metalizing a naked region of the active layer with the gate layer pattern as a mask. This method can ensure that an orthographic projection of the gate layer pattern completely coincides with that of the gate insulating pattern on the substrate. That is, the entire active layer pattern is under the gate insulating layer pattern. Therefore, the entire active layer pattern can be regulated by the gate layer pattern. This method solves the drawbacks, in the prior art, of no gate on the edge of the gate insulating layer pattern, thereby improving a turn-on current and electrical characteristics of a thin film transistor and improving display effect of a display device. 
     The above description is only preferred embodiments of the present disclosure. it should be noted that those skilled in the art can make various modifications to the above embodiments without departing from the technical idea of the present disclosure, and the modifications are all within the scope defined by the claims of the present disclosure.