Patent Publication Number: US-8983013-B2

Title: Signal processing circuit and signal processing method

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority of the prior Japanese Patent Application No. 2013-001896, filed on Jan. 9, 2013, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments discussed herein are related to a signal processing circuit and a signal processing method. 
     BACKGROUND 
     The improvement of system performance depends on the improvement of the performance of parts such as memory, processor, or switch large scale integrated circuits (LSI) included in a computer or information processing device and the improvement (increase in transmission capacities or decrease in transmission delays measured in units of bits per second) of the signal transmissions speed between parts or elements. For example, in order to improve the performance of a computer (server), the signal transmission rate has to be improved between a memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM) and a processor. As the performance of information processing devices such as backbone communication devices is improved, the data rate at which signals are sent or received inside or outside the devices is desired to be improved. 
     The related art is disclosed in Japanese Laid-open Patent Publication No. 63-1119 or Japanese Laid-open Patent Publication No. 2005-223420. 
     SUMMARY 
     According to one aspect of the embodiments, a signal processing circuit includes: a delay line configured to output, to a plurality of taps, signals with different delay times obtained by delaying an input signal, respectively; and a plurality of synchronization circuits configured to sample the signals from the plurality of taps in a phase in synchronization with a clock signal, wherein each of the plurality of synchronization circuits samples a sample signal from one of the plurality of taps in different phases and outputs a plurality of output signals. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention, as claimed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  depicts an example of a receiver; 
         FIG. 2A  depicts an example of a signal processing circuit; 
         FIG. 2B  depicts an example of outputs of a signal processing circuit; 
         FIG. 3  depicts an example of a signal processing circuit; 
         FIG. 4  depicts an example of a signal processing circuit; 
         FIGS. 5A and 5B  depict an example of a voltage control oscillator; 
         FIG. 6A  depicts an example of a signal processing circuit; 
         FIG. 6B  depicts an example of an output of a signal processing circuit; 
         FIG. 7  depicts an example of an output of a signal processing circuit; 
         FIG. 8  depicts an example of an adjusting circuit; 
         FIG. 9  depicts an example of a circuit for generating an expected value; 
         FIG. 10  depicts an example of a predicted value output circuit; 
         FIG. 11A  depicts an example of a signal processing circuit; 
         FIG. 11B  depicts an example of an output of a signal processing circuit; and 
         FIG. 12  depicts an example of an adjusting circuit. 
     
    
    
     DESCRIPTION OF EMBODIMENT 
     An analog-digital conversion system may include a delay line with taps, sample-hold circuit, an analog-digital conversion circuit, a temporary digital memory, and a multiplexer. 
     A signal processing circuit may include a first multi-tap delay line for delaying an input signal, a second multi-tap delay line for delaying a clock signal, and a plurality of clock control comparators. The data input lines of the clock control comparator are coupled to the taps of the first delay line and the clock input lines are coupled to the taps of the second delay line. 
     In order to increase the data rate, the data rate of the input/output (I/O) circuit in an integrated circuit may be increased from several gigabits per second to several tens of gigabits per second. For example, it is considered that the current high end server is desired to have a data rate of approximately 10 gigabits per second to 30 gigabits per second and the next generation machine is desired to have a data rate of approximately 30 gigabits per second to 60 gigabits per second. 
       FIG. 1  depicts an example of a receiver. A receiver  1201  includes a signal processing circuit  1202  and receives an input analog data signal Di.  FIG. 2A  depicts an example of a signal processing circuit.  FIG. 2B  depicts an example of outputs of a signal processing circuit. The signal processing circuit  1202  may be a front end circuit of a clock data recovery (CDR) circuit that, for example, performs one-bit determination of an input with two-times oversampling (at a sampling rate twice the data rate). The CDR circuit receives the signal Di on a transmission path, which includes data having a clock superimposed thereon and restores (reproduces) the data and signal based on the received signal Di. As depicted in  FIG. 2B , the input analog signal Di may be a received signal of a no-return-to-zero (NRZ) binary code and may have a transmission rate of 64 gigabits per second. A NRZ binary code indicates a high level when data is 1 or a low level when data is 0, and does not change its level during the unit interval (1 UI). 1 UI is a one-bit time slot width (pulse width). The frequency corresponding to the data rate D (bits/second) of the data signal Di is the baud frequency fb (=D). The reciprocal (1/fb) of the baud frequency fb equals 1 UI. 
     The signal processing circuit includes a delay line  101 , buffers  102   a  to  102   h , synchronization circuits (latch circuits)  103   a  to  103   h , and two-phase buffer circuit  104 . The delay line  101  has four taps T 1  to T 4  and is terminated with a resistor R. An inductor L and capacitors C and Cin are disposed between the taps T 1  and T 2 , between the taps T 2  and T 3 , and between the taps T 3  and T 4 . The resistor R is the characteristic impedance √L/(C+Cin)) of the delay line  101  and its resistance may be, for example, 50Ω. The inductor L and the capacitors C and Cin may be, for example, a parasitic inductance and parasitic capacitances, respectively. The delay line  101  delays the input analog signal Di and outputs four signals with different delays to the four taps T 1  to T 4 . The signal from the tap T 2  may be, by delay time Td, later than the signal from the tap T 1 . The signal from the tap T 3  may be, by delay time Td, later than the signal from the tap  2 . The signal from the tap T 4  may be, by delay time Td, later than the signal from the tap  3 . Delay time Td is, for example, 0.5 UI, which is half the unit interval 1 UI. 
     The buffers  102   a  and  102   b  buffer the signal from the tap T 1  and output it to the synchronization circuits  103   a  and  103   b , respectively. The buffers  102   c  and  102   d  buffer the signal from the tap T 2  and output it to the synchronization circuits  103   c  and  103   d , respectively. The buffers  102   e  and  102   f  buffer the signal from the tap T 3  and output it to the synchronization circuits  103   e  and  103   f , respectively. The buffers  102   g  and  102   h  buffer the signal from the tap T 4  and output it to the synchronization circuits  103   g  and  103   h , respectively. The buffers  102   a  to  102   h  may reduce noise generated in the delay line  101  when the synchronization circuits  103   a  to  103   h  kick back the signals. 
     The two-phase buffer circuit  104  outputs two-phase clock signals CK 1  and CK 2  based on a clock signal CK. The two-phase clock signals CK 1  and CK 2  have mutually reversed phases and their frequency may be, for example, 16 GHz. 
     The synchronization circuits  103   a ,  103   c ,  103   e , and  103   g  sample the signals from the four taps T 1  to T 4 , respectively, in a phase in sync with the leading edge of the clock signal CK 1  (the leading edge of the clock signal CK) and outputs two-level digital data signals S 1 ( n ), S 2 ( n ), S 3 ( n ), and S 4 ( n ), respectively. The synchronization circuits  103   b ,  103   d ,  103   f , and  103   h , sample the signals from the four taps T 1  to T 4 , respectively, in a phase in sync with the leading edge of the clock signal CK 2  (the trailing edge of the clock signal CK) and outputs two-level digital data signals S 1 ( n +1), S 2 ( n +1), S 3 ( n +1), and S 4 ( n +1), respectively. The synchronization circuits  103   a  to  103   h , which are latch circuits, receive an analog signal and output a high level when the input analog signal is larger than the threshold or output a low level when the input analog signal is smaller than the threshold. The data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) in  FIG. 1B  represent sampling points. 
     The synchronization circuits  103   a  and  103   b  sample a single signal from the tap T 1  in different phases and outputs the signals S 1 ( n ) and S 1 ( n +1), respectively. The synchronization circuits  103   c  and  103   d  sample a single signal from the tap T 2  in different phases and outputs the signals S 2 ( n ) and S 2 ( n +1), respectively. The synchronization circuits  103   e  and  103   f  sample a single signal from the tap T 3  in different phases and outputs the signals S 3 ( n ) and S 3 ( n +1), respectively. The synchronization circuits  103   g  and  103   h , sample a single signal from the tap T 4  in different phases and outputs the signals S 4 ( n ) and S 4 ( n +1), respectively. The synchronization circuits  103   a ,  103   c ,  103   e , and  103   g  and the synchronization circuits  103   b ,  103   d ,  103   f , and  103   h , may sample signals through interleaving. 
     The cycle of the clock signals CK 1  and CK 2  may be 4 UI. The signal from tap T 2  is, by delay time Td, later than the signal from tap T 1 . The signal from tap T 3  is, by delay time 2×Td, later than the signal from tap T 1 . The signal from tap T 4  is, by delay time 3×Td, later than the signal from tap T 1 . The maximum delay time for the taps T 1  to T 4  is delay time 3×Td in the case of the tap T 4 . Delay time Td may be 0.5 UI, for example. The cycle of the clock signal CK 1  and CK 2  is 4 UI, which is longer than the maximum delay time (3×Td (=1.5 UI)) for the signals from the taps T 1  to T 4 . 
     The sampling period for the four data signals S 1 ( n ) to S 4 ( n ) is Td and the sampling period for the next four data signals S 1 ( n +1) to S 4 ( n +1) is also Td. The sampling period for the data signals S 4 ( n ) and S 1 ( n +1) is also Td. Accordingly, the eight sampling data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) are obtained for 4 UI. For example, two-times oversampling, which obtains two sampling data signals per UI, may be performed. The CDR circuit restores (reproduces) the data of each bit by selecting the data signals S 2 ( n ), S 4 ( n ), S 2 ( n +1), and S 4 ( n +1) in a phase near the middle of 1 UI for each bit. 
     The data rate of the input analog data signal Di may be 64 gigabits per second. The frequency of the clock signals CK 1  and CK 2  may be 16 GHz. Since the eight synchronization circuits  103   a  to  103   h , each output the data signals of 16 gigasamples per second, the signal processing circuit outputs the data signals of 128 (=8×16) gigasamples per second. For example, the signal processing circuit may output the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) of 128 gigasamples per second by performing two-times oversampling of the input analog data signal Di of 64 gigabits per second. The two-times oversampling of the input analog data signal Di with a high data rate is performed using the 16 GHz two-phase clock signal CK 1  and CK 2 . 
     When the delay times between adjacent taps of the taps T 1  to T 4  are Td, the four taps T 1  to T 4  are used to adjust a time span of 2 UI (=4×Td). Combination of time interleaving of the synchronization circuits  103   a  to  103   h , and the delay line  101  enables the oversampling of the input analog data signal Di with a high data rate. 
     The input analog data signal Di is sampled using the delay line  101  with n taps. When the delay between adjacent taps is Td, the m synchronization circuits  103   a  and so on are coupled to one tap. The number m and number n may be larger than  2 . The clock signal CK 1  or so on for driving the m synchronization circuits  103   a  or so on may be an m-phase clock signal with a cycle of m×n×Td and the inter-phase time difference may be n×Td. For example, the m synchronization circuits  103   a  or so on coupled to the tap T 1  or so on perform interleaving of m phases. n signals at time intervals of Td are generated and these signals are sampled at time intervals of n×Td. Combination of n-deep sampling via the delay line  101  and m-phase interleaving causes the clock cycle to become m×n×Td, which is sufficiently longer than the sampling interval. 
     Combination of an n-fold increase in the sampling interval by the delay line  101  with n taps and an m-fold increase in the sampling interval by the m-phase time interleaving causes an m×n-fold increase in the sampling interval. This may reduce the frequency of the clock signal CK 1  for driving the synchronization circuits  103   a  or so on to 1/(n×m). The number of phases of the multi-phase clock signal CK 1  or so on may become 1/n of the number of phases when only interleaving is used. Therefore, the power consumption of the clock system and the area may be reduced significantly. 
       FIG. 3  depicts an example of a signal processing circuit. In  FIG. 3 , synchronization circuits  201   a  to  201   h  are disposed in place of the synchronization circuits  103   a  to  103   h  depicted in  FIG. 2A , and a buffer  202  and an analog-digital converter sets  203   a  to  203   h  are added. Since the other structure in  FIG. 3  is substantially the same as or similar to that in  FIG. 2A , its description may be omitted or reduced. 
     The synchronization circuits  201   a ,  201   c ,  201   e , and  201   g , which may be sampling circuits, receive analog signals from the buffers  102   a ,  102   c ,  102   e , and  102   g , respectively, sample the analog signals in sync with the leading edge of the clock signal CK 1 , and output the analog signals. The synchronization circuits  201   b ,  201   d ,  201   f , and  201   h , which may be sampling circuits, receive analog signals from the buffers  102   b ,  102   d ,  102   f , and  102   h , respectively, sample the analog signals in sync with the leading edge of the clock signal CK 2 , and output the analog signals. 
     The eight-phase buffer  202  outputs a 2 GHz eight-phase clock signal CK 4  based on a clock signal CK 3 . The analog-digital converter set  203   a  includes eight analog-digital converters. The analog-digital converter set  203   a  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   a  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 1 ( n ). The analog-digital converter set  203   b  includes eight analog-digital converters. The analog-digital converter set  203   b  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   b  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 1 ( n +1). The analog-digital converter set  203   c  includes eight analog-digital converters. The analog-digital converter set  203   c  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   c  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 2 ( n ). The analog-digital converter set  203   d  includes eight analog-digital converters. The analog-digital converter set  203   d  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   d  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 2 ( n +1). The analog-digital converter set  203   e  includes eight analog-digital converters. The analog-digital converter set  203   e  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   e  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 3 ( n ). The analog-digital converter set  203   f  includes eight analog-digital converters. The analog-digital converter set  203   f  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   f  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 3 ( n +1). The analog-digital converter set  203   g  includes eight analog-digital converters. The analog-digital converter set  203   g  performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   g  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 4 ( n ). The analog-digital converter set  203   h , includes eight analog-digital converters. The analog-digital converter set  203   h , performs analog-to-digital conversion of a single output signal from the synchronization circuit  201   h  in sync with eight phases (with different leading edges) of the eight-phase clock signal CK 4  and outputs eight 4-bit digital signals S 4 ( n +1). 
     Each of the analog-digital converter sets  203   a  to  203   h , performs the interleaving of eight phases in sync with the eight-phase clock signal CK 4 . The frequency of the eight-phase clock signal CK 4  is, for example, 2 GHz, therefore, the analog-digital converter sets  203   a  to  203   h , may convert data at a rate of 2 gigasamples per second. 
     The delay line  101  has n (=4) taps T 1  to T 4 . Each of the taps T 1  to T 4  has m (=2) synchronization circuits  201   a  and  201   b  coupled thereto and each of the synchronization circuits  201   a  to  201   h  has p (=8) analog-digital converters coupled thereto. Each of the eight analog-digital converter sets  203   a  to  203   h , has eight analog-digital converters and a total of 64 (=8×8) analog-digital converters are present, therefore, a 64-fold increase in the clock cycle may be obtained. Each of the 64 analog-digital converters outputs a data signal of 2 gigasamples per second in sync with the 2 GHz eight-phase clock signal CK 4 . A total of data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) of 128 (=64×2) gigasamples per second are output. For example, the signal processing circuit may output the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) of 128 gigasamples per second by performing the two-times oversampling of the input analog data signal Di of 64 gigabits per second. 
     The two-times oversampling of the input analog data signal Di of 64 gigabits per second may be performed by using the 16 GHz two-phase clock signal CK 1  and CK 2 . Due to a three-stage structure including the delay line  101 , the synchronization circuits  201   a  to  201   h , and the analog-digital converter sets  203   a  to  203   h , a 64-fold increase in the clock cycle may be obtained as an effective value. Accordingly, the data signals are digitized by the analog-digital converter sets  203   a  to  203   h , of 2 gigasamples per second. Since conversion into 4-bit digital signals is performed, clock signal and data are restored in the digital circuit. This may reduce the usage of analog components such as a phase interpolator for adjusting the phase of a clock signal. 
       FIG. 4  depicts an example of a signal processing circuit. In  FIG. 4 , voltage controlled oscillators (VCO)  301   a  to  301   c  are added to the signal processing circuit depicted in  FIG. 3 . Since the other components in  FIG. 4  are substantially the same as or similar to those in  FIG. 3 , their description may be omitted or reduced. A plurality of, for example, three, voltage controlled oscillators  301   a  to  301   c  are coupled to each other to distribute the two-phase clock signals CK 1  and CK 2  to the eight synchronization circuits  201   a  to  201   h.    
       FIGS. 5A and 5B  depict an example of a voltage control oscillators.  FIG. 5A  depicts the layout of the three voltage controlled oscillators  301   a  to  301   c  depicted in  FIG. 4 . The three voltage controlled oscillators  301   a  to  301   c  are aligned and coupled via wires to precisely drive the eight synchronization circuits  201   a  to  201   h  substantially at the same time. The output terminals of the plurality of voltage controlled oscillators  301   a  to  301   c  are coupled to each other and the precise clock signals CK 1  and CK 2  are distributed to the synchronization circuits  201   a  to  201   h , respectively. The synchronization circuits  201   a ,  201   c ,  201   e , and  201   g  receive the clock signal CK 1  with the same phase and are driven substantially at the same time. The synchronization circuits  201   b ,  201   d ,  201   f , and  201   h  receive the clock signal CK 2  with the same phase and are driven substantially at the same time. Since the clocks are delivered at low power and high precision, timing margins of the circuits may be improved. 
       FIG. 5B  depicts the structure of the voltage controlled oscillator  301   a  depicted in  FIG. 3 . The structure of the voltage controlled oscillators  301   b  to  301   c  depicted in  FIG. 4  may also be substantially the same as that of the voltage controlled oscillator  301   a . A capacitor  401  is coupled between nodes N 1  and N 2 . An inductor  402  is coupled between the nodes N 1  and N 2 . The source of a p-channel field effect transistor  403  is coupled to a power source voltage node, the gate is coupled to the node N 2 , and the drain is coupled to the node N 1 . The drain of an n-channel field effect transistor  405  is coupled to the node N 1 , the gate is coupled to the node N 2 , and the source is coupled to the drain of an n-channel field effect transistor  407 . The source of a p-channel field effect transistor  404  is coupled to the power source voltage node, the gate is coupled to the node N 1 , and the drain is coupled to the node N 2 . The drain of an n-channel field effect transistor  406  is coupled to the node N 2 , the gate is coupled to the node N 1 , and the source is coupled to the drain of the n-channel field effect transistor  407 . The gate of the n-channel field effect transistor  407  is coupled to a node of a control voltage Bi and the source is coupled to a reference voltage (ground voltage) node. The clock signal CK 1  is output from the node N 1  and the clock signal CK 2  is output from the node N 2 . 
       FIG. 6A  depicts an example of a signal processing circuit.  FIG. 6B  depicts an example of outputs of a signal processing circuit. In  FIG. 6A , the voltage controlled oscillators  301   a  to  301   c  and capacitors  501   a  to  501   h  are added to the receiver depicted in  FIG. 2A . Since the other components in  FIG. 6A  are substantially the same as or similar to those in  FIG. 1A , their description may be omitted or reduced. The synchronization circuits  103   a  to  103   h , in  FIG. 5A  may correspond to the synchronization circuits  103   a  to  103   h , in  FIG. 2A . The synchronization circuits  103   a  to  103   h , output analog signals or digital signals including a plurality of bits as the synchronization circuits  201   a  to  201   h  and/or the analog-digital converter sets  203   a  to  203   h  in  FIG. 3 . 
     The three voltage controlled oscillators  301   a  to  301   c  have the output terminals coupled to each other as in  FIG. 4 , distribute the clock signal CK 1  with the same phase to the synchronization circuits  103   a ,  103   c ,  103   e , and  103   g , and distribute the clock signal CK 2  with the same phase to the synchronization circuits  103   b ,  103   d ,  103   f , and  103   h.    
     The capacitors  501   a ,  501   c ,  501   e , and  501   g  are coupled to the output terminals of the synchronization circuits  103   a ,  103   c ,  103   e , and  103   g , holds output signals from the synchronization circuits  103   a ,  103   c ,  103   e , and  103   g , and outputs them as the data signals S 1 ( n ) to S 4 ( n ), respectively. The capacitors  501   b ,  501   d ,  501   f , and  501   h  are coupled to the output terminals of the synchronization circuits  103   b ,  103   d ,  103   f , and  103   h , holds output signals from the synchronization circuits  103   b ,  103   d ,  103   f , and  103   h , and outputs them as the data signals S 1 ( n +1) to S 4 ( n +1), respectively. 
     As depicted in  FIG. 6B , a phase Ta of the data signal S 1 ( n ) is based on a start phase (data transition phase) of one bit (1 UI). A phase Tb of the data signal S 1 ( n +1) is based on a start phase (data transition phase) of one bit (1 UI). The start phase of one bit is represented by 0 UI and obtained based on, for example, the value of the data signal S 1 ( n ). For example, if the value of the data signal S 1 ( n ) is an intermediate value between the high level and the low level, the phase of the data signal S 1 ( n ) is the start phase of one bit. If the value of the data signal S 1 ( n ) deviates from the intermediate value, the start phase of one bit is obtained based on the amount of deviation. When the delay times between adjacent taps of taps T 1  to T 4  of the delay line  101  are 0.5 UI, the phase interval of adjacent signals of the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) may be 0.5 UI. 
       FIG. 7  depicts an example of outputs of a signal processing circuit. If the delay times between adjacent taps of the taps T 1  to T 4  of the delay line  101  deviate from 0.5 UI, the phase interval of the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) may deviate from 0.5 UI as depicted in  FIG. 7 . For example, the deviation in the phase of the data signal S 1 ( n ) may be 0, the deviation in the phase of the data signal S 2 ( n ) may be 6, the deviation in the phase of the data signal S 3 ( n ) may be 26, and the deviation in the phase of the data signal S 4 ( n ) may be 36. Similarly, the deviation in the phase of the data signal S 1 ( n +1) may be 0, the deviation in the phase of the data signal S 2 ( n +1) may be 6, the deviation in the phase of the data signal S 3 ( n +1) may be 26, and the deviation in the phase of the data signal S 4 ( n +1) may be 36. In this case, the deviation in the phase may become uneven and the interval between the phase of the data signal S 4 ( n ) and the phase of the data signal S 1 ( n +1) may increase, possibly causing data restoration error. 
       FIG. 8  depicts an example of an adjusting circuit. The delay line  101  may correspond to the delay line  101  in  FIG. 6A . A phase expected value &lt;S 1 &gt; may be a phase expected value of the data signal S 1 ( n ), &lt;S 2 &gt; may be a phase expected value of the data signal S 2 ( n ), and &lt;S 4 &gt; may be a phase expected value of the data signal S 4 ( n ). &lt;S 2 &gt;-&lt;S 1 &gt;, which is the phase obtained by subtracting the phase expected value &lt;S 1 &gt; of the data signal S 1 ( n ) from the expected value &lt;S 2 &gt; of the data signal S 2 ( n ), may correspond to the delay time between the tap T 1  and the tap T 2 . An adder  700  adds the phase expected value &lt;S 4 &gt; and the inter-tap delay time &lt;S 2 &gt;-&lt;S 1 &gt;. The output phase of the adder  700  may be substantially the same as the phase of the data signal S 1 ( n +1) if there is no deviation in the delay times between adjacent taps of the taps T 1  to T 4 . The phase of the data signal S 1 ( n +1) may be substantially the same as that of the data signal S 1 ( n ). Accordingly, the output phase of the adder  700  may be substantially the same as the phase of the data signal S 1 ( n ) if there is no deviation in the delay times between adjacent taps of the taps T 1  to T 4 . 
     A phase detector  701  detects the phase Ta of the data signal S 1 ( n ). A subtracter  702  subtracts an output phase of the adder  700  from the phase Ta of the data signal S 1 ( n ) and outputs the result to an integrator  703 . The integrator  703  integrates the output value from the subtracter  702  and outputs the result to a code converter  704 . The code converter  704  converts the output value from the integrator  703  into control codes and outputs them to four capacity adjusting units  705   a  to  705   d . The four capacity adjusting units  705   a  to  705   d  each include a circuit in which a plurality of switches (SW) and capacitors C 1  are coupled in series, and are coupled to taps T 1  to T 4  of the delay line  101 . The four capacity adjusting units  705   a  to  705   d  each control the turning on and off of switches according to the control code to adjust the capacitances coupled to the taps T 1  to T 4  of the delay line  101 . The delay times between adjacent taps of the taps T 1  to T 4  are adjusted so that the output of the subtracter  702  substantially becomes 0. For example, as depicted in  FIG. 6B , the phase interval of the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) may be adjusted to 0.5 UI and data restoration error may be reduced. 
     In the adjusting circuit, the deviation in the phases of output signals from the synchronization circuits  103   a  to  103   h , is detected by the subtracter  702  and the delay time of the delay line  101  is adjusted depending on the detected deviation in the phases. Since the input analog data signal Di is sampled at certain intervals, timing margins during data restoration may be improved. 
       FIG. 9  depicts an example of a circuit for generating an expected value. The circuit depicted in  FIG. 9  generates the phase expected value &lt;S 1 &gt; of the data signal S 1 ( n ) depicted in  FIG. 8 . A phase detector  800  detects the phase of the data signal S 1 ( n ). The phase of the data signal S 1 ( n ) is based on 0 UI. The subtracter  802  subtracts the phase expected value &lt;S 1 &gt; from the output value from the phase detector  800 . Multipliers  803  and  804  multiply the output value from the subtracter  802  by coefficients G 1  and G 2 , respectively. An integrator  805  integrates the output value from the multiplier  803 . An adder  806  adds the output value from the integrator  805  and the output value from the multiplier  804 . An integrator  807  integrates the output value from the adder  806  and outputs the phase expected value &lt;S 1 &gt; of the data signal S 1 ( n ). The phase expected value &lt;S 1 &gt; of the data signal S 1 ( n ) is calculated as the average value of the phases of the data signals S 1 ( n ) in past cycles. For example, when the data signals S 2 ( n ) and S 4 ( n ) are entered instead of the data signal S 1 ( n ), the phase expected value &lt;S 2 &gt; of the data signal S 2 ( n ) and the phase expected value &lt;S 4 &gt; of the data signal S 4 ( n ) are generated. 
       FIG. 10  depicts an example of a predicted value output circuit. In  FIG. 10 , the predicted value output circuit is disposed in place of the adjusting circuit depicted in  FIG. 8 . Since the other components in  FIG. 10  are substantially the same as or similar to those in  FIG. 8 , their description may be omitted or reduced. In the predicted value output circuit in  FIG. 10 , an adder  801 , a phase detector  901 , a subtracter  902 , an integrator  903 , an adder  904 , and a determination circuit  905  are added to the circuit in  FIG. 9 . 
     The phase detector  901  detects the phase Ta of the data signal S 1 ( n ). The subtracter  902  subtracts the phase Ta from an expected value Ta 2 . The integrator  903  integrates the output value from the subtracter  902 . The four phase detectors  800  detect the phases of the four the data signals S 1 ( n ) to S 4 ( n ). The phase of the data signal S 1 ( n ) is based on the first bit 0 UI, the phase of the data signal S 2 ( n ) is based on the first bit 0.5 UI, the phase of the data signal S 3 ( n ) is based on the second bit 0 UI, and the phase of the data signal S 4 ( n ) is based on the second bit 0.5 UI. For example, if the delay times between adjacent taps of the taps T 1  to T 4  are 0.5 UI, the phases of the four data signals S 1 ( n ) to S 4 ( n ) may be substantially the same. The adder  801  adds the output values from the four phase detectors  800 . The subtracter  802  subtracts a predicted value P 1  from the output value from the adder  801  and outputs the result to the multipliers  803  and  804 . The multipliers  803  and  804  multiply the output value from the subtracter  802  by coefficients G 1  and G 2 . The integrator  805  integrates the output value from the multiplier  803 . The adder  806  adds the output values from the integrator  903 , the integrator  805 , and the multiplier  804 . The integrator  807  integrates the output value from the adder  806  and outputs the phase predicted value P 1  of the data signal S 1 ( n ). The adder  904  adds the predicted value P 1  and a shift amount SH and outputs an expected value Ta 2 . The predicted value P 1  is a phase predicted value in consideration of deviation in the delay time. The shift amount SH may be a value corresponding to the deviation in the delay time and may be a known value that was preset. The expected value Tat is a phase expected value when there is no deviation in the delay time. The determination circuit  905  presumes the phases of the data signals S 1 ( n ) to S 4 ( n ) based on the phase predicted value P 1  of the data signal S 1 ( n ), performs two-level determination of the data signals S 1 ( n ) to S 4 ( n ), and restores data. For example, the determination circuit  905  selects the data of a phase near the middle of 1 UI of each bit as described above and restores the data of each bit. 
     The predicted value output circuit detects a deviation in the phase of the output signal S 1 ( n ) using the subtracter  902 , and outputs the phase predicted value P 1  of the output signal S 1 ( n ) from the synchronization circuit  103   a  depending on the detected deviation in the phase. 
     As depicted in  FIGS. 6A and 6B , with no circuit for adjusting the delay time of the delay line  101 , the deviation in the phase of the data signal S 1 ( n ) from the average value of past phases is detected and the phase predicted value P 1  is output, whereby effects of error of sampling intervals may reduce. Since the adjusting circuit in  FIG. 8  may not be disposed, the size of the circuit may be reduced. 
       FIG. 11A  depicts an example of a signal processing circuit.  FIG. 11B  depicts an example of the operation of the signal processing circuit. In  FIG. 11A , a tap T 5 , a synchronization circuit  103   i , and a capacitor C 501   i  are added to the signal processing circuit in  FIG. 6A . Since the structure in  FIG. 11A  is substantially the same as or similar to that in  FIG. 6A , its description may be omitted or reduced. 
     The delay line  101  includes the tap T 5  in addition to the taps T 1  to T 4 . The delay time between the taps T 4  and T 5  may be Td (=0.5 UI). For example, the signal from the tap T 5  may be, by delay time Td, later than the signal from the tap T 4 . The synchronization circuit  103   i , which may have substantially the same structure as the synchronization circuits  103   a  to  103   h , samples the signal from the tap T 5  in sync with the leading edge of the clock signal CK 1 . The synchronization circuit  103   i  outputs a high level when the signal is larger than the threshold or outputs a low level when the signal is smaller than the threshold. For example, the voltage controlled oscillators  301   a  to  301   c  supply the clock signal CK 1  to the synchronization circuit  103   i . The capacitor C 501   i , which is coupled to the output terminal of the synchronization circuit  103   i , holds the output signal from the synchronization circuit  103   i  and outputs the output signal as the data signal S 5 ( n ). 
     As depicted in  FIG. 11B , the difference between the phase of the data signal S 4 ( n ) and the phase of the data signal S 5 ( n ) may be the delay time Td. Accordingly, if the delay time of the delay line  101  includes no deviation, the phase of the data signal S 5 ( n ) and the phase of the data signal S 1 ( n +1) may be substantially the same. The delay time of the delay line  101  may be adjusted so that the phase of the data signal S 5 ( n ) and the phase of the data signal S 1 ( n +1) are substantially the same. 
       FIG. 12  depicts an example of an adjusting circuit. The adjusting circuit depicted in  FIG. 12  may be disposed in the signal processing circuit depicted in  FIG. 11A . In  FIG. 12 , a phase detector  1101  is disposed in place of the adder  700  in the adjusting circuit depicted in  FIG. 8 . Since the structure in  FIG. 12  is substantially the same as or similar to that in  FIG. 8 , its description may be omitted or reduced. The phase detector  1101  detects the phase of the data signal S 5 ( n ). The phase detector  701  detects the phase of the data signal S 1 ( n +1). The subtracter  702  subtracts the phase of the data signal S 5 ( n ) from the phase Tb of the data signal S 1 ( n +1) and outputs the result to the integrator  703 . The integrator  703  integrates the output value from the subtracter  702  and outputs the result to the code converter  704 . The code converter  704  converts the output value from the integrator  703  into control codes and outputs them to the four capacity adjusting units  705   a  to  705   d . The four capacity adjusting units  705   a  to  705   d  each control the turning on and off of switches according to the control codes to adjust the capacitances coupled to the taps T 1  to T 4  of the delay line  101 . The delay times between adjacent taps of the taps T 1  to T 4  are adjusted so that the difference between the phase Tb of the data signal S 1 ( n +1) and the phase of the data signal S 5 ( n ) substantially becomes 0. As depicted in  FIG. 11B , the phase interval of the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) may be adjusted to 0.5 UI and data restoration error may be reduced. 
     The adjusting circuit depicted in  FIG. 12  adjusts the delay time of the delay line  101  depending on the deviation between the phase of the output signal S 1 ( n +1) from the synchronization circuit  103   b  corresponding to the tap T 1  with the minimum delay time of the delay line  101  and the phase of the output signal S 5 ( n ) from the synchronization circuit  103   i  corresponding to the tap T 5  with the maximum delay time. 
     A five-tap delay line  101  having the taps T 1  to T 4  in  FIG. 8  and an additional tap T 5  is used. The fact may be utilized that the phase of a data signal S 5 ( n ) obtained from the tap T 5  is substantially the same as the phase of the data signal S 1 ( n +1) obtained from the tap T 1  in a subsequent sampling interval. For example, the inter-tap delay time is adjusted so that the phase of the data signal S 1 ( n +1) is substantially the same as the phase of a data signal S 5 ( n ). For example, the two data signals S 5 ( n ) and S 1 ( n +1) that have substantially the same phase are obtained by using an additional tap. Accordingly, the correction precision of phase error may become high and the timing margin of data determination may be improved. 
     In the adjusting circuits depicted in  FIGS. 8 and 12 , the delay time of the delay line  101  is adjusted. The phases of the clock signals CK 1 , CK 2 , and CK 4  may be adjusted according to control codes so that the phase interval of the data signals S 1 ( n ) to S 4 ( n ) and S 1 ( n +1) to S 4 ( n +1) becomes 0.5 UI. 
     Since the delay line  101  and the synchronization circuits  103   a  to  103   h , or  201   a  to  201   h  are disposed, the data signal Di of a high data rate may be received. A plurality of data signals with different delay times are generated by the delay line  101 , and the synchronization circuits  103   a  to  103   h  or  201   a  to  201   h  perform interleaving. Therefore, the number of phases of clocks CK 1  and CK 2  may be reduced, the generation and distribution of a clock signal may be facilitated, the power consumption and the area of a circuit may be reduced. In the above signal processing circuits, signal transmission between semiconductor chips, between circuit blocks in a cabinet, or between cabinets may be performed at high speed. 
     All examples and conditional language recited herein are intended for pedagogical purposes to aid the reader in understanding the invention and the concepts contributed by the inventor to furthering the art, and are to be construed as being without limitation to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although the embodiment of the present invention has been described in detail, it should be understood that the various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.