Patent Publication Number: US-7915930-B2

Title: Dual power-up signal generator for stabilizing an internal voltage generator

Description:
TECHNICAL FIELD 
     This disclosure relates to a semiconductor memory and, more particularly, to a power-up signal generator. 
     BACKGROUND 
     Generally, a power-up signal is used in a semiconductor memory to determine if the level of a power supply voltage VDD reaches a voltage level required for the normal operation of the semiconductor memory when the power supply voltage VDD is applied to the semiconductor memory in an initial stage of the operation thereof. 
     The power-up signal is necessary because the semiconductor memory may abnormally operate when power is applied to the semiconductor memory before the level of the power supply voltage reaches the voltage level for the normal operation of the semiconductor memory. At this time, if the power-up signal is activated, the power-up signal may become a high level or a low level. In the following description, it is assumed that the power-up signal is a high level. 
     Accordingly, the semiconductor memory essentially includes a power-up generator that generates a power-up signal activated according to the level of the power supply voltage. 
       FIG. 1  is a graph for explaining a power-up signal according to the conventional technology. 
     As shown in  FIG. 1 , the power-up signal rises corresponding to the level of the power supply voltage VDD when the power supply voltage VDD is applied to the semiconductor memory in an initial stage of the operation thereof. Thereafter, if the level of the power supply voltage VDD exceeds a predetermined voltage level, the power-up signal is low. 
     Such a power-up signal shorts an internal voltage to the power supply voltage VDD, and resets registers of a logic module for the duration in which the power-up signal PWRUP is high. At this time, if the power-up signal PWRUP is set to a low level, internal voltages are generated from their respective internal voltage drivers, and the logic module becomes a stand-by state, such that the logic module can always be operated. 
     However, if the power-up signal PWRUP becomes a high level in the lowest level of the power supply voltage VDD due to the requirement for low power supply voltage in a mobile product, registers in all logic modules are reset, so that the level of the power supply voltage VDD of an internal voltage supplying circuit cannot but descend. 
     Due to such a problem, a driver for an internal voltage must maintain a target voltage level in a low power supply voltage. In other words, since the internal voltage must be applied in the low power supply voltage as soon as the power-up operation is completed, the internal voltage is unstable, so that fatal errors may occur. 
     BRIEF SUMMARY 
     In an aspect of this disclosure, a dual power-up signal generator is provided that is capable of stabilizing an internal voltage generator in a mobile product that requires a low power supply voltage. 
     In an embodiment, a dual power-up signal generator includes a power-up signal generator which generates a first power-up signal by using a first voltage signal obtained by detecting a level of a power supply voltage, and generates a second power-up signal by using a second voltage signal obtained by detecting the level of the power supply voltage. 
     The first power-up signal can be used to reset a register of a logic module of a semiconductor memory, and the second power-up signal can be used to control an internal voltage driver. 
     The power-up signal generator can include a power supply voltage level detector which outputs the first and second voltage signals obtained by detecting the level of the power supply voltage, and a power-up signal driver which outputs the first and second power-up signals activated according to the voltage levels of the first and second voltage signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other aspects, features and other advantages of the subject matter of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a graph for explaining a power-up signal according to the conventional technology. 
         FIG. 2  is a circuit diagram showing a dual power-up signal generator according to an embodiment of the present invention; 
         FIG. 3  is a graph for explaining operation of the dual power-up signal generator of  FIG. 3 ; and 
         FIG. 4  is a circuit diagram showing an internal voltage generator, particularly, used to explain the operation of the internal voltage generator for the duration of power-up. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Hereinafter, examples and exemplary embodiments of the present invention will be described with reference to accompanying drawings. However, the examples and embodiments are for illustrative purposes only and are not intend to limit the scope of the invention. 
       FIG. 2  is a circuit diagram showing a dual power-up signal generator according to an embodiment of the present invention. 
     In the embodiment shown in  FIG. 2 , the dual power-up signal generator includes a power supply voltage level detector  10 , which outputs first and second voltage signals V 1  and V 2  obtained by detecting the level of a power supply voltage VDD supplied to a semiconductor memory, a first power-up signal driver  20 , which outputs first power-up signals PWRUP  1  and PWRUP 1 B activated according to the level of the first voltage signal V 1 , and a second power signal driver  30 , which outputs second power-up signals PWRUP 2  and PWRUP 2 B activated according to the level of the second voltage signal V 2 . 
     The power supply voltage level detector  10  includes a resistor array R 1  and R 2 , which divides the power supply voltage VDD to output a second voltage signal V 2 , and a first NMOS transistor M 1  which is connected between the resistor array R 1  and R 2  and a grounding voltage VSS to output the first voltage signal V 1  in response to the power supply voltage VDD. 
     The first power-up signal driver  20  includes a first pull-up driver M 3  pull-up driven in response to the first voltage signal V 1 , a first resistor R 3  connected in series to the first pull-up driver M 3 , a first pull-down driver M 2  connected in series to the first resistor R 3  and pull-down driven in response to the first voltage signal V 1 , and a first buffer unit  40  that buffers the output signal of the first power-up signal driver  20 . 
     The second power-up signal driver  30  includes a second pull-up driver M 4  pull-up driven in response to the second voltage signal V 2 , a second resistor R 4  connected in series to the second pull-up driver M 4 , a second pull down driver M 5  pull-down driven in response to the second voltage signal V 2 , and a second buffer module that buffers the output signal of the second power-up signal driver  30 . 
     The first power-up signal PWRUP 1  resets a resistor of a logic module in a semiconductor memory in order to perform initial setting when the semiconductor memory is powered up. The second power-up signal PWRUP 2  is used to control an internal voltage driver. 
     Hereinafter, operation of the dual power-up signal generator of  FIG. 2  will be described in detail with reference to accompanying drawings. 
     As shown in  FIG. 2 , the power supply voltage level detector  10  outputs the first voltage signal V 1  and the second voltage signal V 2  obtained by dividing the power supply voltage VDD according to a resistance ratio between the first NMOS transistor M 1  and the resistor array R 1  and R 2 , in which the first NMOS transistor M 1  is connected in series to the resistor array R 1  and R 2  between the power supply voltage VDD and a ground voltage VSS. 
     In this case, the second voltage signal V 2  has a voltage level higher than that of the first voltage signal V 1  by a ratio corresponding to the resistor R 2 . 
     Thus, the first power-up signal driver  20  outputs the first power-up signal PWRUP 1  activated according to a voltage level of the first voltage signal V 1 , and the second power-up signal driver  30  outputs the second power-up signal PWRUP 2  activated according to a voltage level of the second voltage signal V 2 . 
     Accordingly, as shown in  FIG. 3 , the second power-up signal PWRUP  2  is low in a at level higher than that of the first power-up signal PWRUP  1 . In other words, since the internal voltage generator, which generates internal voltage in response to the second power-up signal PWRUP 2 , operates when the voltage level of the power supply voltage VDD sufficiently rises, the internal voltage generator can stably drive internal voltage. 
       FIG. 4  is a circuit diagram showing the internal voltage generator, particularly, a view used to explain operation of the internal voltage generator for the duration of power-up. 
     As shown in  FIG. 4 , since the second power-up signal PWRUP 2  is high in the internal voltage generator for the duration of power-up, a reference voltage vref 0  has a level approximating the level of the power supply voltage VDD, and a reference voltage vref has a level approximating the level of the power supply voltage level VDD. 
     Thereafter, the voltage level of a transistor M 6  is determined by a voltage vrefc obtained by dividing the reference voltage vref so that a core voltage VCORE is driven. At the same time, a transistor M 7  shorts the power supply voltage VDD to the core voltage VCORE by using the second power-up signal PWRUP 2 B, to generate a core voltage. 
     Then, if the level of the power supply voltage VDD becomes a predetermined level, the second power-up signal PWRUP 2  is low, so that the levels of the reference voltages vref 0 , vref, and vrefc are switched into original target levels, the transistor M 7  is turned off. 
     For example, if the power-up level of the internal voltage generator is set to 1.4 v slightly lower than the level (1.45 v) of the core voltage VCORE on the assumption that the logic module has a power-up level of 1.1 v (this power-up level of 1.1 v may be changed according to conditions), it is possible to prevent problems caused by the weak driving force of the core voltage VCORE under the low power supply voltage. This is adjustable for all internal voltage generators that generate other internal voltages as well as the core voltage VCORE. 
     As described above, according to this disclosure, the power-up level of the logic module is set differently from the power-up level of the internal voltage generator such that an internal voltage can be generated in a power supply voltage level enabling the internal voltage generator to sufficiently operate. Accordingly, the instability of a power circuit occurring in the initial stage of a power-up operation can be overcome in a mobile product requiring a low power supply voltage. 
     While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of this disclosure and the following claims. 
     This disclosure claims priority to Korean application number 10-2008-0024983, filed on Mar. 18, 2008, the entire contents of which are incorporated herein by reference.