Patent Publication Number: US-7911835-B2

Title: Programming and reading five bits of data in two non-volatile memory cells

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
     This application claims the benefit under 35 USC §119 of Korean Patent Application No. 10-2006-0097602, filed Oct. 4, 2006, and Korean Patent Application No. 10-2007-0001627, filed on Jan. 5, 2007, the disclosures of both of which are hereby incorporated herein by reference in their entirety as if set forth fully herein. 
     FIELD OF THE INVENTION 
     The present invention relates to programming a non-volatile memory device and reading data from the non-volatile memory device, and more particularly, to programming a non-volatile memory device by using 6 threshold voltage levels and reading data from the non-volatile memory device by using the 6 threshold voltage levels. 
     BACKGROUND OF THE INVENTION 
     In order to store data of 2 or more bits, conventional non-volatile memory devices include 4-level non-volatile memory cells, each having 4 threshold voltage levels, or 8-level non-volatile memory cells, each having 8 threshold voltage levels. Since a 4-level non-volatile memory cell is programmed using four threshold voltage levels, the 4-level non-volatile memory cell is able to store 2-bit data. Since an 8-level non-volatile memory cell is programmed using eight threshold voltage levels, the 8-level non-volatile memory cell is able to store 3-bit data. 
     SUMMARY OF THE INVENTION 
     Some embodiments of the present invention provide methods of programming a non-volatile memory device that includes a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. According to some embodiments, five bits of data are programmed in the first and second non-volatile memory cells by programming an initial subset of at least two of the five bits of data into the first and second non-volatile memory cells and then programming a remaining subset of the five bits of data into the first and second non-volatile memory cells according to threshold voltage levels at which the initial subset of at least two of the five bits have been programmed into the first and second non-volatile memory cells. Related non-volatile memory cells, including controllers that are configured to program five bits of data, may also be provided according to other embodiments of the present invention. Moreover, methods of reading a non-volatile memory device in which five bits of data have been programmed in the first and second non-volatile memory cells, and related non-volatile memory devices, are also provided according to other embodiments of the invention. 
     According to some embodiments of the present invention, there are provided methods of programming a non-volatile memory device comprising a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. These methods may comprise a first program operation for programming the first and second non-volatile memory cells with one of the first threshold voltage level or the second threshold voltage level in order to store first and second bits of data, and a second program operation for programming one of the first or second non-volatile memory cells with one of the third through sixth threshold voltage levels in order to store third through fifth bits of the data according to a threshold voltage level with which the first and second bits of the data have been programmed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: 
         FIGS. 1A and 1B  are circuit diagrams of a non-volatile memory device according to embodiments of the present invention; 
         FIG. 1C  illustrates 6 threshold voltage levels of a non-volatile memory cell of the non-volatile memory device shown in  FIGS. 1A and 1B ; 
         FIG. 2  is a flowchart of programming operations that may be performed according to first embodiments of the present invention; 
         FIGS. 3A ,  3 B and  3 C, which collectively form  FIG. 3 , show diagrams for further illustrating the program operations according to embodiments illustrated in  FIG. 2 ; 
         FIG. 4  shows diagrams for further illustrating the program operations according to embodiments illustrated in  FIG. 2 , when first and second bits of data are “11”; 
         FIG. 5  shows diagrams for further illustrating the program operations according to embodiments illustrated in  FIG. 2 , when the first and second bits of data are “10”; 
         FIG. 6  shows diagrams for further illustrating program operations according to embodiments illustrated in  FIG. 2 , when the first and second bits of data are “01”; 
         FIG. 7  shows diagrams for further illustrating program operations according to embodiments illustrated in  FIG. 2 , when the first and second bits of data are “00”; 
         FIG. 8  illustrates non-volatile memory cells programmed according to embodiments illustrated in  FIG. 2 ; 
         FIG. 9  illustrates a data read methods according to embodiments of the present invention; 
         FIG. 10  illustrates programming operations according to second embodiments of the present invention; 
         FIGS. 11A and 11B , which collectively form  FIG. 11 , illustrate a first program operation for programming first through third bits of data in embodiments of  FIG. 10 ; 
         FIG. 12  illustrates a second program operation for programming fourth and fifth of the data in embodiments of  FIG. 10 ; 
         FIG. 13  illustrates a first program operation for programming first through third bits of data according to third embodiments of the present invention; and 
         FIG. 14  illustrates a second program operation for programming fourth and fifth bits of the data according to the third embodiments. 
         FIG. 15  illustrates the second program operation for programming the fourth and fifth bits of the data according to the third embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
     It will be understood that when an element such as a layer, region or substrate is referred to as being “on” another element, it can be directly on the other element or intervening elements may also be present. In contrast, the term “directly” means that there are no intervening elements. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various embodiments, elements, components, regions, layers and/or sections, these embodiments, elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one embodiment, element, component, region, layer or section from another region, layer or section. Thus, a first embodiment, region, layer or section discussed below could be termed a second embodiment, region, layer or section, and, similarly, a second embodiment, region, layer or section could be termed a first embodiment, region, layer or section without departing from the teachings of the present invention. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present invention. As used herein, the singular forms “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” “including,” “have” and/or “having” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     The present invention is described below with reference to block diagrams and/or flowchart illustrations of methods and/or apparatus (systems and/or devices) according to embodiments of the invention. It is understood that a block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations, can be implemented by hardware and may also include computer program instructions, which execute via a processor and/or other programmable data processing apparatus to create means (functionality) and/or structure for implementing the functions/acts specified in the block diagrams and/or flowchart block or blocks. Accordingly, the present invention may be embodied in hardware and also may include software (including firmware, resident software, micro-code, etc.). 
     It should also be noted that in some alternate implementations, the functions/acts noted in the blocks may occur out of the order noted in the flowcharts. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Moreover, the functionality of a given block of the flowcharts and/or block diagrams may be separated into multiple blocks and/or the functionality of two or more blocks of the flowcharts and/or block diagrams may be at least partially integrated. 
     As used herein, “data” refers to any digital information to be stored in a non-volatile memory device, regardless of the source or meaning of the information. Data may also be referred to synonymously herein as “page data”. Moreover, methods of programming and reading non-volatile memory devices may be implemented by a controller, which may be designed to implement the program and/or read operations that are described herein. The controller may include logic and/or processor circuits that, in some embodiments, may executed a stored program, and that are configured to perform the programming and reading operations described herein. The design of controllers for non-volatile memory devices is well known to those having skill in the art and need not be described further herein. 
     Hereinafter, it is assumed that a non-volatile memory cell according to the present invention has 6 threshold voltage levels. However, the number of threshold voltage levels that the non-volatile memory cell according to the present invention is not limited to 6. For example, the non-volatile memory cell according to the present invention may have 12 threshold voltage levels. 
       FIGS. 1A and 1B  are respectively circuit diagrams of a non-volatile memory device  100 A and  100 B according to embodiments of the present invention. 
       FIG. 1C  illustrates 6 threshold voltage levels that a non-volatile memory cell of the non-volatile memory device  100 A or  100 B shown in  FIGS. 1A and 1B  has. 
     Referring to  FIG. 1C , first and second non-volatile memory cells CELL 1  and CELL 2  included in each of the non-volatile memory devices  100 A and  100 B may be programmed to have one of first through sixth threshold voltage levels that sequentially increase. More specifically, the sixth threshold voltage level is the highest, and the first threshold voltage level is the lowest. The non-volatile memory device  100 A or  100 B can program 5-bit data (also referred to herein as 5-page data) by using the two non-volatile memory cells CELL 1  and CELL 2  each having 6 threshold voltage levels. 
     The first and second non-volatile memory cells CELL 1  and CELL 2  may be connected to the same wordline or bitline. In  FIG. 1A , the first and second non-volatile memory cells CELL 1  and CELL 2  are connected to a given wordline. In  FIG. 1B , the first and second non-volatile memory cells CELL 1  and CELL 2  are connected to a given bitline. A controller  110  also may be provided to control programming and/or reading operations described herein. 
       FIG. 2  is a flowchart of a program operations  200  according to first embodiments of the present invention. 
     Referring to  FIG. 2 , the program operations  200  include first and second bits of the data bit program operation  210 , a third data bit program operation  230 , a fourth data bit program operation  240 , and a fifth data bit program operation  250 . 
     In the first and second bits of the data bit program operation  210 , in order to store first and second bits of data, the first and second non-volatile memory cells are programmed to have a first threshold voltage level or a second threshold voltage level. In the third data bit program operation  230 , in order to store a third bit of the data, the first non-volatile memory cell is programmed to have a third threshold voltage level or a fourth threshold voltage level according to the first and second bits of the data. In the fourth data bit program operation  240 , in order to store a fourth bit of the data, the first non-volatile memory cell or the second non-volatile memory cell is programmed to have a fifth threshold voltage level or a sixth threshold voltage level according to the third bit of the data. In the fifth data bit program operation  250  in order to store a fifth bit of the data, the first non-volatile memory cell or the second non-volatile memory cell is programmed to have a third threshold voltage level or a fourth threshold voltage level according to the fourth bit of the data. 
     In the third data bit program operation  230 , to store the third bit of the data, the first non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level according to the threshold voltage level with which the first non-volatile memory cell has been programmed in operation  210 . In the fourth data bit program operation  240 , to store the fourth bit of the data, the first non-volatile memory cell or the second non-volatile memory cell may be programmed with the fifth threshold voltage level or the sixth threshold voltage level according to the threshold voltage level with which the first non-volatile memory cell has been programmed. In the fifth data bit program operation  250 , to store the fifth bit of the data, the first non-volatile memory cell or the second non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level according to the threshold voltage level with which the second non-volatile memory cell has been programmed. 
       FIGS. 3A ,  3 B and  3 C, which collectively form  FIG. 3 , show diagrams for further illustrating the programming  200  according to the embodiments illustrated in  FIG. 2 . 
     Referring to  FIGS. 2 and 3A , in the first and second bits of the data bit program operation  210 , the first data are programmed with the first threshold voltage level and the second threshold voltage level in the first memory cell CELL 1 . Also, the second data are programmed with the first threshold voltage level and the second threshold voltage level in the second memory cell CELL 2 . A single non-volatile memory cell includes the threshold voltage levels. Thus, the two non-volatile memory cells can include four threshold voltage level combinations, whereby the first and second bits of the data can be written to the two non-volatile memory cells. 
     Referring to  FIGS. 2 and 3B , in the third data bit program operation  230 , to store the third bit of the data, the first non-volatile memory cell may be programmed with a combination of the first threshold voltage level and the third threshold voltage level or a combination of the second threshold voltage level and the fourth threshold voltage level. For example, when the logic level of the third bit of the data is 0, the first non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level. On the other hand, when the logic level of the third bit of the data is 1, the first non-volatile memory cell may be programmed with the first threshold voltage level or the second threshold voltage level. 
     More specifically, in the third data bit program operation  230 , when the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level, to store the third bit of the data, the first non-volatile memory cell may be programmed with the first threshold voltage level or the third threshold voltage level according to the third bit of the data. On the other hand, when the threshold voltage level with which the first non-volatile memory cell has been programmed is the second threshold voltage level, to store the third bit of the data, the first non-volatile memory cell may be programmed with the second threshold voltage level or the fourth threshold voltage level according to the third bit of the data. When the third bit of the data is “0”, the first non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level. On the other hand, when the third bit of the data is “1”, the first non-volatile memory cell may be programmed with the first threshold voltage level or the second threshold voltage level. For example, when the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level and the third bit of the data is “0”, the first non-volatile memory cell is programmed with the third threshold voltage level. 
     Referring to  FIGS. 2 and 3C , in the fourth data bit program operation  240 , to store the fourth bit of the data, the first non-volatile memory cell may be programmed with a combination of the third threshold voltage level and the fifth threshold voltage level or a combination of the fourth threshold voltage level and the sixth threshold voltage level. Alternatively, to store the fourth bit of the data, the second non-volatile memory cell may be programmed with a combination of the first threshold voltage level and the fifth threshold voltage level or a combination of the second threshold voltage level and the sixth threshold voltage level. If the logic level of the fourth bit of the data is 0, the first non-volatile memory cell or the second non-volatile memory cell may be programmed with the fifth threshold voltage level or the sixth threshold voltage level. 
     To be more specific, in the fourth data bit program operation  240 , when the threshold voltage level with which the first non-volatile memory cell has been programmed is the third threshold voltage level, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the third threshold voltage level or the fifth threshold voltage level according to the fourth bit of the data. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the fourth threshold voltage level, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the fourth threshold voltage level or the sixth threshold voltage level according to the fourth bit of the data. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level, to store the fourth bit of the data, the second non-volatile memory cell may be programmed with the first threshold voltage level or the fifth threshold voltage level according to the fourth bit of the data. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the second threshold voltage level, to store the fourth bit of the data, the second non-volatile memory cell may be programmed with the second threshold voltage level or the sixth threshold voltage level according to the fourth bit of the data. 
     In the fourth data bit program operation  240 , when the threshold voltage level with which the first non-volatile memory cell has been programmed is the third threshold voltage level or the fourth threshold voltage level and the fourth bit of the data is “0”, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the fifth threshold voltage level or the sixth threshold voltage level respectively. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the third threshold voltage level or the fourth threshold voltage level and the fourth bit of the data is “1”, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level respectively. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level or the second threshold voltage level and the fourth bit of the data is “0”, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the fifth threshold voltage level or the sixth threshold voltage level respectively. When the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level or the second threshold voltage level and the fourth bit of the data is “1”, to store the fourth bit of the data, the first non-volatile memory cell may be programmed with the first threshold voltage level or the second threshold voltage level respectively. 
     Referring to  FIGS. 2 and 3B , in the fifth data bit program operation  250 , to store the fifth bit of the data, the first non-volatile memory cell may be programmed with a combination of the first threshold voltage level and the third threshold voltage level or a combination of the second threshold voltage level and the fourth threshold voltage level. Alternatively, to store the fifth bit of the data, the second non-volatile memory cell may be programmed with a combination of the first threshold voltage level and the third threshold voltage level or a combination of the second threshold voltage level and the fourth threshold voltage level. If the logic level of the fifth bit of the data is 0, the first or second non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level. 
     In the fifth data bit program operation  250 , when the threshold voltage level with which the second non-volatile memory cell has been programmed is the fifth threshold voltage level, to store the fifth bit of the data, the first non-volatile memory cell may be programmed with the first threshold voltage level or the third threshold voltage level according to the fifth bit of the data. When the threshold voltage level with which the second non-volatile memory cell has been programmed is the sixth threshold voltage level, to store the fifth bit of the data, the first non-volatile memory cell may be programmed with the second threshold voltage level or the fourth threshold voltage level according to the fifth bit of the data. When the threshold voltage level with which the second non-volatile memory cell has been programmed is the first threshold voltage level, to store the fifth bit of the data, the second non-volatile memory cell may be programmed with the first threshold voltage level or the third threshold voltage level according to the fifth bit of the data. When the threshold voltage level with which the second non-volatile memory cell has been programmed is the second threshold voltage level, to store the fifth bit of the data, the second non-volatile memory cell may be programmed with the second threshold voltage level or the fourth threshold voltage level according to the fifth bit of the data. 
     In the fifth data bit program operation  250 , when the fifth bit of the data is “0”, the first non-volatile memory cell or the second non-volatile memory cell may be programmed with the third threshold voltage level or the fourth threshold voltage level. On the other hand, when the fifth bit of the data is “1”, the first non-volatile memory cell or the second non-volatile memory cell may be programmed with the first threshold voltage level or the second threshold voltage level. 
       FIG. 4  illustrates the programming  200  according to the embodiments illustrated in  FIG. 2 , when the first and second bits of the data are “11”. 
     Referring to  FIG. 4 , in the first and second bits of the data bit program operation  210 , to store the first and second bits of the data, which are “11”, the first and second non-volatile memory cells are programmed with the first threshold voltage level. In the third data bit program operation  230 , when the third bit of the data is “0”, the first non-volatile memory cell, which has been programmed with the first level, is programmed with the third threshold voltage level. Meanwhile, the second non-volatile memory cell is not programmed. When the third bit of the data is “1”, the first non-volatile memory cell is programmed with the first threshold voltage level. That is, the threshold voltage of the first non-volatile memory cell is not varied. In the fourth data bit program operation  240 , when the third bit of the data is “1” and the fourth bit of the data is “0”, the second non-volatile memory cell is programmed with the fifth threshold voltage level. On the other hand, when the third bit of the data is “0” and the fourth bit of the data is “0”, the first non-volatile memory cell is programmed with the fifth threshold voltage level. 
     In the fifth data bit program operation  250 , when the third bit of the data is “1”, the fourth bit of the data is “1”, and the fifth bit of the data is “0”, the second non-volatile memory cell is programmed with the third threshold voltage level. When the third bit of the data is “1”, the fourth bit of the data is “0”, and the fifth bit of the data is “0”, the first non-volatile memory cell is programmed with the third threshold voltage level. When the third bit of the data is “0”, the fourth bit of the data is “1”, and the fifth bit of the data is “0”, the second non-volatile memory cell is programmed with the third threshold voltage level. When the third bit of the data is “0”, the fourth bit of the data is “0”, and the fifth bit of the data is “0”, the first non-volatile memory cell is programmed with the third threshold voltage level. 
       FIG. 5  shows diagrams for further illustrating the programming  200  according to the embodiments illustrated in  FIG. 2 , when the first and second bits of the data are “10”. 
       FIG. 6  shows diagrams for further illustrating the programming  200  according to the embodiments illustrated in  FIG. 2 , when the first and second bits of the data are “01”. 
       FIG. 7  shows diagrams for further illustrating the programming  200  according to the embodiments illustrated in  FIG. 2 , when the first and second bits of the data are “00”. 
     The programming illustrated in  FIGS. 5 through 7  correspond to the programming illustrated in  FIG. 4 , so that detailed descriptions thereof will be omitted. 
       FIG. 8  illustrates non-volatile memory cells programmed with the programming operations  200  according to the embodiment illustrated in  FIG. 2 . 
     In  FIG. 8 , 5-bit data, namely, “00000” through “11111”, are programmed in 2 non-volatile memory cells each having 6 threshold voltage levels. 
       FIG. 9  illustrates a data read according to embodiments of the present invention. 
     Referring to  FIG. 9 , the data read includes a first and second data bit read operation, a third data bit read operation, a fourth data bit read operation, and a fifth data bit read operation. 
     In the first and second data bit read operations, the first and second bits of the data are read using a first read threshold voltage between the first threshold voltage level and the second threshold voltage level, a third read threshold voltage between the third threshold voltage level and the fourth threshold voltage level, and a fifth read threshold voltage between the fifth threshold voltage level and the sixth threshold voltage level. In the third data bit read operation, the third bit of the data is read using a second read threshold voltage between the second threshold voltage level and the third threshold voltage level. In the fourth data bit read operation, the fourth bit of the data is read using a fourth read threshold voltage between the fourth threshold voltage level and the fifth threshold voltage level. In the fifth data bit read operation, the third bit of the data is read using the second read threshold voltage and the fourth read threshold voltage. 
     Programming according to the second embodiments includes a first program operation and a second program operation. In the first program operation the first through third bits of the data are programmed, and in the second program operation the fourth and fifth bits of the data are programmed. 
       FIG. 10  illustrates the first program operation according to second embodiments of the present invention. 
     Referring to  FIG. 10 , in the first program operation, the first through third bits of the data are programmed into the first non-volatile memory cell and the second non-volatile memory cell. In the first program operation, to store the first through third bits of the data, the first non-volatile memory cell and the second non-volatile memory cell are programmed with the first threshold voltage level (i.e.,  1  shown in  FIG. 10 ), or a first intermediate threshold voltage level (i.e., T 1  shown in  FIG. 10 ) higher than at least one of the threshold voltage levels of the first and second non-volatile memory cells, or a second intermediate threshold voltage level (i.e., T 2  shown in  FIG. 10 ) higher than the first intermediate threshold voltage level. 
     The distribution of each of the first and second intermediate threshold voltage levels may be wider than that of the at least one of the threshold voltage levels of the first and second non-volatile memory cells. Furthermore, in some embodiments, the distribution of each of the first and second intermediate threshold voltage levels may be wider than all of the threshold voltage levels of the first and second non-volatile memory cells. 
     The second intermediate threshold voltage level may be lower than at least one of the threshold voltage levels in other embodiments. The first intermediate threshold voltage level may be lower than the second intermediate threshold voltage level in other embodiments. 
     The first intermediate threshold voltage level may be higher than the second threshold voltage level and lower than the third threshold voltage level in other embodiments. The second intermediate threshold voltage level may be higher than the fourth threshold voltage level and lower than the fifth threshold voltage level in other embodiments. 
       FIGS. 11A and 11B , which collectively form  FIG. 11 , illustrate the first program operation for programming the first through third bits of the data in the programming of  FIG. 10 .  FIG. 11A  illustrates the case in which a first data (a first bit) is “1”, and  FIG. 11B  illustrates the case in which a first bit is “0”. The first program operation will now be described in detail with reference to  FIGS. 10 and 11 . 
     The first program operation may include a first data bit program operation, a second data bit program operation, and a third data bit program operation. 
     In the first data bit program operation, to store the first data, the first non-volatile memory cell is programmed with the first threshold voltage level or the first intermediate threshold voltage level. For example, when the first data is “1”, the first non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 1  shown in  FIG. 11(   a )). On the other hand, when the first data is “0”, the first non-volatile memory cell may be programmed with the first intermediate threshold voltage level (T 1  of CELL 1  shown in  FIG. 11(   b )). 
     In the second data bit program operation, according to the threshold voltage level with which the first non-volatile memory cell has been programmed, the first non-volatile memory cell may be programmed with the first intermediate threshold voltage level or the second intermediate threshold voltage level, or the second non-volatile memory cell may be programmed with the first threshold voltage level or the second intermediate threshold voltage level. 
     More specifically, referring to  FIG. 11A , when the threshold voltage level with which the first non-volatile memory cell has been programmed is the first threshold voltage level ( 1  of CELL 1 ), to store the second data, the second non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 2 ) or the second intermediate threshold voltage level (T 2  of CELL 2 ). For example, when the second data is “0”, the second non-volatile memory cell may be programmed with the second intermediate threshold voltage level (T 2  of CELL 2 ). That is, the threshold voltage of the second non-volatile memory cell is moved to the second intermediate threshold voltage level (T 2  of CELL 2 ) from the first threshold voltage level ( 1  of CELL 2 ). On the other hand, when the second data is “1”, the second non-volatile memory cell may be programmed with the first threshold voltage level (T 1  of CELL 2 ). That is, the threshold voltage of the second non-volatile memory cell is maintained as the first threshold voltage level ( 1  of CELL 2 ). 
     Also, referring to  FIG. 11B  when the threshold voltage level with which the first non-volatile memory cell has been programmed is the first intermediate threshold voltage level (T 1  of CELL 1 ), to store the second data, the first non-volatile memory cell may be programmed with the first intermediate threshold voltage level (T 1  of CELL 1 ) or the second intermediate threshold voltage level (T 2  of CELL 2 ). For example, when the second data is “0”, the first non-volatile memory cell may be programmed with the second intermediate threshold voltage level. That is, the threshold voltage of the first non-volatile memory cell is moved to the second intermediate threshold voltage level (T 2  of CELL 1 ) from the first intermediate threshold voltage level (T 1  of CELL 1 ). On the other hand, when the second data is “1”, the first non-volatile memory cell may be programmed with the first intermediate threshold voltage level. That is, the threshold voltage of the first non-volatile memory cell is maintained as the first intermediate threshold voltage level (T 1  of CELL 1 ). 
     In the third data bit program operation, according to the threshold voltage level with which the second non-volatile memory cell has been programmed, the first non-volatile memory cell may be programmed with the first threshold voltage level or the first intermediate threshold voltage level, or the second non-volatile memory cell may be programmed with the first threshold voltage level or the first intermediate threshold voltage level. 
     More specifically, in the third data bit program operation, when the threshold voltage level with which the second non-volatile memory cell has been programmed in the second data bit program operation is the first threshold voltage level ( 1  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ), the second non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ) and the first intermediate threshold voltage level (T 1  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ) in order to store the third bit of the data. For example, when the third bit of the data is “0”, the second non-volatile memory cell may be programmed with the first intermediate threshold voltage level (T 1  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ). On the other hand, when the third bit of the data is “1”, the second non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ). 
     When the threshold voltage level with which the second non-volatile memory cell has been programmed in the second data bit program operation is the second intermediate threshold voltage level (T 2  of CELL 2  shown in the  FIG. 11A  or  FIG. 11B ), the first non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 1  shown in the  FIG. 11A  or  FIG. 11B ) and the first intermediate threshold voltage level (T 1  of CELL 1  shown in the  FIG. 11A  or  FIG. 11B ) in order to store the third bit of the data. For example, when the third bit of the data is “0”, the first non-volatile memory cell may be programmed with the first intermediate threshold voltage level (T 1  of CELL 1  shown in the  FIG. 11A  or  FIG. 11B ). On the other hand, when the third bit of the data is “1”, the first non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 1  shown in the  FIG. 11A  or  FIG. 11B ). 
       FIG. 12  illustrates the second program operation of programming according to second embodiments of the present invention. 
     Referring to  FIG. 12 , in the second program operation, to store the fourth and fifth bits of the data, the first non-volatile memory cell or the second non-volatile memory cell is programmed with one of the first through sixth threshold voltage levels ( 1  to  6  of CELL 1  or CELL 2 ) according to a threshold voltage level with which previous data has been programmed. 
     In the first program operation illustrated in  FIG. 10 , in order to store the first through a fifth bit of the data in the first non-volatile memory cell or the second non-volatile memory cell, first, the first non-volatile memory cell or the second non-volatile memory cell is programmed with intermediate levels (for example, the first and second intermediate threshold voltage levels) in order to store the first through third bits of the data. Next, the first non-volatile memory cell or the second non-volatile memory cell is programmed with final levels (i.e., the first through sixth threshold voltage levels) in order to store the fourth and fifth bits of the data. 
     In the second program operation, to store the fourth data, the threshold voltage of the first non-volatile memory cell is changed and the threshold voltage of the second non-volatile memory cell is not changed. That is, the threshold voltage of the first non-volatile memory cell is moved to the first through sixth threshold voltage levels ( 1 ˜ 6  of CELL 1 ) from the first threshold voltage level ( 1  of CELL 1 ), the first intermediate threshold voltage level (T 1  of CELL 1 ), and the second intermediate threshold voltage level (T 2  of CELL 1 ). 
     In the second program operation, to store the fifth data, the threshold voltage of the first non-volatile memory cell is not changed and the threshold voltage of the second non-volatile memory cell is changed. That is, the threshold voltage of the second non-volatile memory cell is moved to the first through sixth threshold voltage levels ( 1 ˜ 6  of CELL 2 ) from the first threshold voltage level ( 1  of CELL 2 ), the first intermediate threshold voltage level (T 1  of CELL 2 ), and the second intermediate threshold voltage level (T 2  of CELL 2 ). 
       FIG. 13  illustrates the second program operation for programming the fourth and fifth bits of the data in the program method of  FIG. 12 . 
     In the second program operation, when the first non-volatile memory cell has been programmed with the first threshold voltage level ( 1  of CELL 1 ) in the first program operation, the first non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 1 ) or the second threshold voltage level ( 2  of CELL 1 ) in order to store the fourth bit of the data. For example, when the fourth bit of the data is “0”, the first non-volatile memory cell may be programmed with the second threshold voltage level ( 2  of CELL 1 ). On the other hand, when the fourth bit of the data is “1”, the first non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 1 ). 
     In the second program operation, when the first non-volatile memory cell has been programmed with the first intermediate threshold voltage level (T 1  of CELL 1 ) in the first program operation, the first non-volatile memory cell may be programmed with the third threshold voltage level ( 3  of CELL 1 ) or the fourth threshold voltage level ( 4  of CELL 1 ) in order to store the fourth bit of the data. For example, when the fourth bit of the data is “0”, the first non-volatile memory cell may be programmed with the fourth threshold voltage level ( 4  of CELL 1 ). On the other hand, when the fourth bit of the data is “1”, the first non-volatile memory cell may be programmed with the third threshold voltage level ( 3  of CELL 1 ). 
     In the second program operation, when the first non-volatile memory cell has been programmed with the second intermediate threshold voltage level (T 2  of CELL 1 ) in the first program operation, the first non-volatile memory cell may be programmed with the fifth threshold voltage level ( 5  of CELL 1 ) or the sixth threshold voltage level ( 6  of CELL 1 ) in order to store the fourth bit of the data. For example, when the fourth bit of the data is “0”, the first non-volatile memory cell may be programmed with the sixth threshold voltage level ( 6  of CELL 1 ). On the other hand, when the fourth bit of the data is “1”, the first non-volatile memory cell may be programmed with the fifth threshold voltage level ( 5  of CELL 1 ). 
     In the second program operation, when the second non-volatile memory cell has been programmed with the first threshold voltage level ( 1  of CELL 2 ) in the first program operation, the second non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 2 ) or the second threshold voltage level ( 2  of CELL 2 ) in order to store the fifth bit of the data. For example, when the fifth bit of the data is “0”, the second non-volatile memory cell may be programmed with the second threshold voltage level ( 2  of CELL 2 ). On the other hand, when the fifth bit of the data is “1”, the second non-volatile memory cell may be programmed with the first threshold voltage level ( 1  of CELL 2 ). 
     In the second program operation, when the second non-volatile memory cell has been programmed with the first intermediate threshold voltage level (T 1  of CELL 2 ) in the first program operation, the second non-volatile memory cell may be programmed with the third threshold voltage level ( 3  of CELL 2 ) or the fourth threshold voltage level ( 4  of CELL 2 ) in order to store the fifth bit of the data. For example, when the fifth bit of the data is “0”, the second non-volatile memory cell may be programmed with the fourth threshold voltage level ( 4  of CELL 2 ). On the other hand, when the fifth bit of the data is “1”, the second non-volatile memory cell may be programmed with the third threshold voltage level ( 3  of CELL 2 ). 
     In the second program operation, when the second non-volatile memory cell has been programmed with the second intermediate threshold voltage level (T 2  of CELL 2 ) in the first program operation, the first non-volatile memory cell may be programmed with the fifth threshold voltage level ( 5  of CELL 2 ) or the sixth threshold voltage level ( 6  of CELL 2 ) in order to store the fifth bit of the data. For example, when the fifth bit of the data is “0”, the second non-volatile memory cell may be programmed with the sixth threshold voltage level ( 6  of CELL 2 ). On the other hand, when the fifth bit of the data is “1”, the second non-volatile memory cell may be programmed with the fifth threshold voltage level ( 5  of CELL 2 ). 
     After the first program operation, the first and second non-volatile memory cells have one of the first threshold voltage level ( 1  of CELL 1  or CELL 2 ), the first intermediate threshold voltage level (T 1  of CELL 1  or CELL 2 ), and the second intermediate threshold voltage level (T 2  of CELL 1  or CELL 2 ), respectively. After the fourth data bit programming of the second program operation, the first non-volatile memory cells has one of the first through the sixth threshold voltage level ( 1 ˜ 6  of CELL 1 ). After the fifth data bit programming of the second program operation, the second non-volatile memory cells has one of the first through the sixth threshold voltage level ( 1 ˜ 6  of CELL 2 ). 
     Programming according to third embodiments of the present invention includes a first program operation in which the first through third bits are programmed and a second program operation in which the fourth and fifth bits are programmed. 
       FIG. 14  illustrates the first program operation for programming the first through third bits of the data according to the third embodiment of the present invention. 
     Referring to  FIG. 14 , in the first program operation, to store the first through third bits of the data, the first and second non-volatile memory cells are programmed with one of the first through third threshold voltage levels ( 1 ˜ 3  of CELL 1  and CELL 2 ). 
     The first program operation includes a first data bit program operation, a second data bit program operation, and a third bit program operation. 
     In the first data bit program operation, to store the first bit of the data, the first non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 1 ) or the first intermediate threshold voltage level (T 1  of CELL 1 ). In the second data bit program operation, to store the second bit of the data, the first non-volatile memory cell is programmed with the second threshold voltage level ( 2  of CELL 1 ) or the third threshold voltage level ( 3  of CELL 1 ) or the second non-volatile memory cell is programmed with the first threshold voltage level (T 1  of CELL 2 ) or the third threshold voltage level ( 3  of CELL 2 ), according to the threshold voltage level with which the first non-volatile memory cell has been programmed. 
     In the second data bit program operation, when the threshold voltage level with which the first non-volatile memory cell has been programmed in the first data bit program operation is the first threshold voltage level ( 1  of CELL 1 ), the second non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 2 ) or the third threshold voltage level ( 3  of CELL 2 ) in order to store the second data. When the threshold voltage level with which the first non-volatile memory cell has been programmed in the first data bit program operation is the second threshold voltage level ( 2  of CELL 1 ), the first non-volatile memory cell is programmed with the second threshold voltage level ( 2  of CELL 1 ) or the third threshold voltage level ( 3  of CELL 1 ) in order to store the second data. 
     In the third data bit program operation, according to the threshold voltage level with which the second non-volatile memory cell has been programmed, either the first non-volatile memory cell or the second non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 1  or CELL 2 ) or the second threshold voltage level ( 2  of CELL 1  or CELL 2 ) in order to store the third bit of the data. 
     In the third data bit program operation, when the threshold voltage level with which the second non-volatile memory cell has been programmed in the second data bit program operation is the first threshold voltage level ( 1  of CELL 2 ), the second non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 2 ) or the second threshold voltage level ( 2  of CELL 2 ) in order to store the third bit of the data. When the threshold voltage level with which the second non-volatile memory cell has been programmed in the second data bit program operation is the third threshold voltage level ( 3  of CELL 2 ), the first non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 1 ) or the second threshold voltage level ( 2  of CELL 1 ) in order to store the third bit of the data. 
       FIG. 15  illustrates the second program operation for programming the fourth and fifth bits of the data in the program method according to the third embodiments. 
     Referring to  FIG. 15 , in the second program operation, to store the fourth and fifth bits of the data, either the first non-volatile memory cell or the second non-volatile memory cell is programmed with one of the fourth through sixth threshold voltage levels ( 4 ˜ 6  of CELL 1  or CELL 2 ) according to a threshold voltage level with which the previous bits of the data have been programmed. 
     In the second program operation, when the second non-volatile memory cell has been programmed with the first threshold voltage level ( 1  of CELL 2 ) in the first program operation, the second non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 2 ) or the fourth threshold voltage level ( 4  of CELL 2 ) in order to store the fourth bit of the data. When the second non-volatile memory cell has been programmed with the second threshold voltage level ( 2  of CELL 2 ) in the first program operation, the second non-volatile memory cell is programmed with the second threshold voltage level ( 2  of CELL 2 ) or the fifth threshold voltage level ( 5  of CELL 2 ) in order to store the fourth bit of the data. When the second non-volatile memory cell has been programmed with the third threshold voltage level ( 3  of CELL 2 ) in the first program operation, the second non-volatile memory cell is programmed with the third threshold voltage level ( 3  of CELL 2 ) or the sixth threshold voltage level ( 6  of CELL 2 ) in order to store the fourth bit of the data. 
     In the second program operation, when the first non-volatile memory cell has been programmed with the first threshold voltage level in the first program operation, the first non-volatile memory cell is programmed with the first threshold voltage level ( 1  of CELL 1 ) or the fourth threshold voltage level ( 4  of CELL 1 ) in order to store the fifth bit of the data. When the first non-volatile memory cell has been programmed with the second threshold voltage level ( 2  of CELL 1 ) in the first program operation, the first non-volatile memory cell is programmed with the second threshold voltage level ( 2  of CELL 1 ) or the fifth threshold voltage level ( 5  of CELL 1 ) in order to store the fifth bit of the data. When the first non-volatile memory cell has been programmed with the third threshold voltage level ( 3  of CELL 1 ) in the first program operation, the first non-volatile memory cell is programmed with the third threshold voltage level ( 3  of CELL 1 ) or the sixth threshold voltage level ( 6  of CELL 1 ) in order to store the fifth bit of the data. 
     Each of the non-volatile memory devices illustrated in  FIGS. 1A and 1B  includes at least one non-volatile memory cell pair including a first non-volatile memory cell and a second non-volatile memory cell. Each of the first non-volatile memory cell and the second non-volatile memory cell may be programmed with a plurality of threshold voltage levels that sequentially increase. The logic level of the non-volatile memory cell pair depends on a combination of a threshold voltage level with which the first non-volatile memory cell has been programmed and a threshold voltage level programmed in the second non-volatile memory cell. 
     Each of the first non-volatile memory cell and the second non-volatile memory cell may be programmed with the first through sixth threshold voltage levels that sequentially increase. In this case, each non-volatile memory cell pair may store 5-bit data. 
     Furthermore, each of the first non-volatile memory cell and the second non-volatile memory cell may be programmed with the first through third threshold voltage levels that sequentially increase. Also, each of the first non-volatile memory cell and the second non-volatile memory cell may be programmed with first through twelfth threshold voltage levels that sequentially increase. 
     Accordingly, methods and controllers (circuits) for programming non-volatile memory devices have been described. The non-volatile memory devices include a first non-volatile memory cell and a second non-volatile memory cell, each of which can be programmed with first through sixth threshold voltage levels that sequentially increase. The methods comprise programming five bits of data in the first and second non-volatile memory cells by programming an initial subset of at least two of the five bits of data into the first and second non-volatile memory cells and programming a remaining subset of the five bits of data into the first and second non-volatile memory cells according to threshold voltage levels at which the initial subset of at least two of the five bits have been programmed into the first and second non-volatile memory cells. A controller may be configured to perform this programming. 
     As described above, in a non-volatile memory device, a method of programming the non-volatile memory device, and a method of reading data from the non-volatile memory device according to the present invention, program and data read are performed using 6 threshold voltage levels, so that 5-bit data can be stored and read out. Therefore, the non-volatile memory device has high integration as compared to when 4 threshold voltage levels are used, and is reliable as compared to when 8 threshold voltage levels are used. 
     In the drawings and specification, there have been disclosed embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.