Patent Publication Number: US-10312925-B1

Title: Multiplying DAC of pipelined ADC

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a pipelined analog-to-digital converter (pipelined ADC, also known as a pipeline ADC), and, more particularly, to a multiplying digital-to-analog converter (multiplying DAC, hereinafter referred to as MDAC) of a pipelined ADC. 
     2. Description of Related Art 
       FIG. 1  is a conventional pipelined analog-to-digital converter (pipelined ADC)  100  including a plurality of series-connected operational stages  110 , a terminal ADC  120 , and a digital correction circuit  130 . After the differential input signal V in  is processed by multiple operational stages in which comparison, subtraction, and amplification operations are conducted, the correction circuit  130  finally corrects the output of each operational stage  110  and the output of the terminal ADC  120  to generate a digital code D, which is the result the analog-to-digital conversion of the differential input signal V in . The operation principles of the pipelined ADC  100  are well known to those of ordinary skill in the art and thus omitted for brevity. 
       FIG. 2  is a functional block diagram of one of the operational stages  110  of  FIG. 1 . The operational stage  110  includes a sub ADC  112 , a decoder  114 , and an MDAC  116 . The sub ADC  112  includes a plurality of comparators that compare the differential input signal V in  with multiple predetermined voltages V R1  to V Rn  to thereby generate a digital signal b. The number of comparators and the number of predetermined voltages (i.e., the numeral n) are related to the number of bits of the pipelined ADC  100 . The decoder  114  provides the reference voltage V REF+ , the reference voltage V REF− , and/or the voltage V CM   _   REF  to the MDAC  116  according to the digital signal b. The voltage V CM   _   REF  is a common-mode voltage of the reference voltage V REF+  and the reference voltage V REF− . The MDAC  116  samples the differential input signal V in  and performs subtraction and multiplication on the differential input signal V in  according to the voltages provided by the decoder  114  to thereby output the differential output signal V out . The differential output signal V out  becomes the differential input signal of the following operational stage  110  or the terminal ADC  120 . 
     To ensure a stable operation of the pipelined ADC  100 , the voltage V CM   _   REF  should ideally be equal to the common-mode voltage V CM   _   PGA  of the differential input signal V in , and the voltage difference between the reference voltage V REF+  and the reference voltage V REF−  is generally half of the allowed maximum peak-to-peak value V pp   _   max  of the differential input signal V in . For example, if the differential input signal V in  is limited between VDD and ground (i.e., V pp   _   max =VDD−0=VDD), then V REF+ −V REF− =0.5V pp   _   max =0.5VDD and V CM   _   REF =V CM   _   PGA =0.5VDD.  FIG. 3  is a conventional circuit diagram for generating the reference voltage V REF+  and the reference voltage V REF− . This circuit is well known to those of ordinary skill in the art and its details are not discussed herein for brevity. In order to satisfy the above requirements, the prior art often makes V REF+ =0.75VDD and V REF− =0.25VDD by adjusting the resistance values of the resistors R 1  and R 2  and the current of the current source Ir in  FIG. 3 . However, the above requirements limit the design flexibility of the reference voltage V REF+  and the reference voltage V REF− . Furthermore, the unit gain buffers  310  and  320  of  FIG. 3  take up considerably large circuit areas. 
     SUMMARY OF THE INVENTION 
     In view of the issues of the prior art, an object of the present invention is to provide an MDAC of a pipelined ADC, so as to improve the design flexibility of reference voltages of the MDAC and to further reduce the overall circuit area of the pipelined ADC. 
     An MDAC applied to a pipelined ADC and operating in a sampling phase or an amplification phase is provided. The MDAC includes an operational amplifier, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor has a first end and a second end. The first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase. The second capacitor has a third end and a fourth end. The third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase. The third capacitor has a fifth end and a sixth end. The fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase. The fourth capacitor has a seventh end and an eighth end. The seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase. One of the second reference voltage and the third reference voltage is substantially ground. 
     An MDAC applied to a pipelined ADC and operating in a sampling phase or an amplification phase is also provided. The MDAC includes an operational amplifier, a first capacitor, a second capacitor, a third capacitor, and a fourth capacitor. The first capacitor has a first end and a second end. The first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase. The second capacitor has a third end and a fourth end. The third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase. The third capacitor has a fifth end and a sixth end. The fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase. The fourth capacitor has a seventh end and an eighth end. The seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase. The DC voltages of the first and second input terminals of the operational amplifier in the amplification phase are not substantially equal to the first reference voltage. 
     An MDAC applied to a pipelined ADC and operating in a sampling phase or an amplification phase is also provided. The MDAC includes an operational amplifier, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, and a sixth capacitor. The first capacitor has a first end and a second end. The first end is coupled to a first reference voltage in the sampling phase and coupled to a first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The second end receives a differential input signal in the sampling phase and is coupled to a first output terminal of the operational amplifier in the amplification phase. The second capacitor has a third end and a fourth end. The third end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The fourth end receives the differential input signal in the sampling phase and is coupled to a second reference voltage in the amplification phase. The third capacitor has a fifth end and a sixth end. The fifth end is coupled to the first reference voltage in the sampling phase and coupled to a second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The sixth end receives the differential input signal in the sampling phase and is coupled to a second output terminal of the operational amplifier in the amplification phase. The fourth capacitor has a seventh end and an eighth end. The seventh end is coupled to the first reference voltage in the sampling phase and coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The eighth end receives the differential input signal in the sampling phase and is coupled to a third reference voltage in the amplification phase. The fifth capacitor has a ninth end and a tenth end. The ninth end is coupled to the first reference voltage in the sampling phase and coupled to the first input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The tenth end receives the differential input signal in the sampling phase and is coupled to a common-mode voltage of the second reference voltage and the third reference voltage in the amplification phase. The sixth capacitor has an eleventh end and a twelfth end. The eleventh end is coupled to the first reference voltage in the sampling phase, and is coupled to the second input terminal of the operational amplifier but not to the first reference voltage in the amplification phase. The twelfth end receives the differential input signal in the sampling phase and is coupled to the common-mode voltage in the amplification phase. 
     The MDAC of the pipelined ADC of the present invention enables shift and scaling of the reference voltages without affecting the operation of the MDAC. Compared with the prior art, the present invention improves the design flexibility of the reference voltages, which can in turn reduce the overall circuit area of the pipelined ADC. 
     These and other objectives of the present invention no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiments with reference to the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a conventional pipelined analog-to-digital converter. 
         FIG. 2  illustrates a functional block diagram of one of the operational stages of  FIG. 1 . 
         FIG. 3  illustrates a conventional circuit diagram for generating the reference voltage V REF+  and the reference voltage V REF− . 
         FIG. 4  illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to an embodiment of the present invention. 
         FIG. 5A  illustrates a circuit diagram of the pipelined ADC of  FIG. 4  operating in the sampling phase. 
         FIG. 5B  illustrates a circuit diagram of the pipelined ADC of  FIG. 4  operating in the amplification phase. 
         FIG. 6  illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention. 
         FIG. 7  illustrates a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention. 
         FIG. 8  illustrates a circuit diagram of one operational stage of a 2.5-bit pipelined ADC according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     The following description is written by referring to terms of this technical field. If any term is defined in this specification, such term should be explained accordingly. In addition, the connection between objects or events in the below-described embodiments can be direct or indirect provided that these embodiments are practicable under such connection. Said “indirect” means that an intermediate object or a physical space exists between the objects, or an intermediate event or a time interval exists between the events. 
     The disclosure herein includes an MDAC of a pipelined ADC. On account of that some or all elements of the MDAC could be known, the detail of such elements is omitted provided that such detail has little to do with the features of this disclosure and this omission nowhere dissatisfies the specification and enablement requirements. A person having ordinary skill in the art can choose components or steps equivalent to those described in this specification to carry out the present invention, which means that the scope of this invention is not limited to the embodiments in the specification. 
       FIG. 4  is a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to an embodiment of the present invention. The differential input signal V in  (including the signals V in   +  and V in   − ) can be the output of a previous stage of the pipelined ADC (e.g., a programmable gain amplifier (PGA)) or the output of a previous operational stage that the current operational stage follows. The operational stage  400  includes a sub ADC  410 , a decoder  420 , and an MDAC  430 . The operation principles of the sub ADC  410  and the decoder  420  are respectively the same as or similar to those of the conventional sub ADC  112  and decoder  114  and thus omitted for brevity. The MDAC  430  includes an operational amplifier  432 , capacitors C 0   a , C 1   a , C 0   b , C 1   b , switches S 0   a  to S 4   a , and switches S 0   b  to S 4   b . The capacitance values of the capacitors C 0   a , C 1   a , C 0   b , and C 1   b  are substantially the same. The MDAC  430  operates alternately in the sampling phase and the amplification phase. In the sampling phase, the switches S 0   a , S 1   a , S 2   a , S 0   b , S 1   b , S 2   b  are turned on, and the remaining switches are turned off ( FIG. 5A ). In the amplification phase, the switches S 3   a , S 4   a , S 3   b , S 4   b  are turned on, and the remaining switches are turned off ( FIG. 5B ). As shown in  FIG. 5B , the DC voltage of the input terminals of the operational amplifier  432  in the amplification phase are V X . 
     One end of the capacitor C 0   a  (or C 0   b ) is coupled to the reference voltage V CM   _   OPI   _   S  through the switch S 2   a  (or S 2   b ) in the sampling phase, and is coupled to an input terminal of the operational amplifier  432  but not to the reference voltage V CM   _   OPI   _   S  in the amplification phase; the other end of the capacitor C 0   a  (or C 0   b ) receives the input signal V in   +  (or V in   − ) through the switch S 0   a  (or S 0   b ) in the sampling phase, and is coupled to the non-inverting output (or inverting output) of the operational amplifier  432  through the switch S 3   a  (or S 3   b ) in the amplification phase. 
     One end of the capacitor C 1   a  (or C 1   b ) is coupled to the reference voltage V CM   _   OPI   _   S  through the switch S 2   a  (or S 2   b ) in the sampling phase, and is coupled to an input terminal of the operational amplifier  432  but not to the reference voltage V CM   _   OPI   _   S  in the amplification phase; the other end of the capacitor C 1   a  (or C 1   b ) receives the input signal V in   +  (or V in   − ) through the switch S 1   a  (or S 1   b ) in the sampling phase, and receives the output voltage of the decoder  420  through the switch S 4   a  (or S 4   b ) in the amplification phase. 
     The decoder  420  outputs the reference voltage V REF+ , the reference voltage V REF− , and/or the voltage V CM   _   REF  according to the digital signal b. For example, in a certain amplification phase, the decoder  420  outputs the reference voltage V REF+  to the capacitor C 1   a  through the switch S 4   a  and outputs the reference voltage V REF−  to the capacitor C 1   b  through the switch S 4   b ; in another amplification phase, the decoder  420  outputs the voltage V CM   _   REF  to the capacitor C 1   a  through the switch S 4   a  and to the capacitor C 1   b  through the switch S 4   b.    
     According to the principle of charge conservation, for all capacitors coupled to one of the input terminals of operational amplifier  432  (i.e., capacitors C 0   a  and C 1   a  or capacitors C 0   b  and C 1   b ), the total charge stored in the sampling phase should ideally be equal to the total charge stored in the amplification phase, which gives the derivation below. Note that the above reference voltage V CM   _   OPI   _   S  corresponds to the situation in which the voltage V CM   _   REF  is not equal to the voltage V CM   _   PGA , and, in the following equations demonstrating the derivation of the DC voltage V X , the reference voltage V CM   _   OPI   _   S  is temporarily replaced by the voltage V CM   _   OPI , which corresponds to the situation in which the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA . 
                 (       V   CM_PGA     -     V   CM_OPI       )     ⁢   NC     =         (     N   -   1     )     ⁢     C   ⁡     (       V   CM_REF     -     V   X       )         +       (       V   CM_OPO     -     V   X       )     ⁢   C                       NV   CM_PGA     -     NV   CM_OPI       =         (     N   -   1     )     ⁢     V   CM_REF       -       (     N   -   1     )     ⁢     V   X       +     V   CM_OPO     -     V   X                       NV   CM_PGA     -     NV   CM_opi       =         (     N   -   1     )     ⁢     V   CM_REF       -     NV   X     +     V   CM_OPO                     V   X     =           (     N   -   1     )     ⁢     V   CM_REF       -     NV   CM_PGA     +     NV   CM_OPI     +     V   CM_OPO       N           
In these equations, C is the capacitance value of the capacitors C 0   a , C 1   a , C 0   b , C 1   b , V CM   _   PGA  is the common-mode voltage of the differential input signal V in , N is the number of capacitors coupled to one of the input terminals of the operational amplifier  432  (N=2 P , P being the integer part of the number of bits of the pipelined ADC), and V CM   _   OPO  is the common-mode voltage of the differential output signal V out  (including the output signals V out   +  and V out   − ).
 
     When the common-mode voltage of the reference voltages V REF+  and V REF−  is substantially equal to the common-mode voltage of the differential input signal V in  (i.e., when the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA ), the voltage V CM   _   OPO  is ideally also substantially equal to the voltages V CM   _   REF  and V CM   _   PGA , which gives the equations below. 
     
       
         
           
             
               V 
               X 
             
             = 
             
               
                 
                   
                     ( 
                     
                       N 
                       - 
                       1 
                     
                     ) 
                   
                   ⁢ 
                   
                     V 
                     CM_REF 
                   
                 
                 - 
                 
                   
                     ( 
                     
                       N 
                       - 
                       1 
                     
                     ) 
                   
                   ⁢ 
                   
                     V 
                     CM_PGA 
                   
                 
                 + 
                 
                   NV 
                   CM_OPI 
                 
               
               N 
             
           
         
       
       
         
           
             
               V 
               X 
             
             = 
             
               
                 
                   NV 
                   CM_OPI 
                 
                 N 
               
               = 
               
                 V 
                 CM_OPI 
               
             
           
         
       
     
     It can be observed from the above derivation that when the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA , the DC voltage V X  of the input terminal of the operational amplifier  432  in the amplification phase is substantially equal to the reference voltage V CM   _   OPI . 
     When the voltage V CM   _   REF  is deliberately controlled to be not equal to the voltage V CM   _   PGA  for the purpose of increasing the design flexibility of the MDAC  430 , the following equation is obtained (assuming that V CM   _   PGA =ΔV CM +V CM   _   REF  and that the voltage V CM   _   OPO  is still substantially equal to V CM   _   PGA ): 
     
       
         
           
             
               V 
               X 
             
             = 
             
               
                 
                   
                     - 
                     
                       ( 
                       
                         N 
                         - 
                         1 
                       
                       ) 
                     
                   
                   N 
                 
                 ⁢ 
                 Δ 
                 ⁢ 
                 
                     
                 
                 ⁢ 
                 
                   V 
                   CM 
                 
               
               + 
               
                 V 
                 CM_OPI 
               
             
           
         
       
     
     This equation shows that if a voltage level shift of 
                 N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM           
is applied to the reference voltage V CM   _   OPI , the DC voltage V X  of the input terminal of the operational amplifier  432  in the amplification phase will substantially not be affected even though the voltage V CM   _   REF  is altered to be not equal to the voltage V CM   _   PGA ; that is, the DC voltage V X  will still be substantially equal to the originally designed reference voltage V CM   _   OPI . In other words, when the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA , the DC voltage V X  of the input terminal of the operational amplifier  432  in the amplification phase is substantially equal to the reference voltage V CM   _   OPI ; when, on the other hand, the voltage V CM   _   REF  is not equal to the voltage V CM   _   PGA , this invention applies a voltage level shift of
 
                 N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM           
to the reference voltage V CM   _   OPI , and, therefore, the shifted reference voltage
 
               V     CM_OPI   ⁢   _S       =       V   X     +         N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM               
will cause the DC voltage V X  of the input terminal of the operational amplifier  432  in the amplification phase is still substantially equal to the original reference voltage V CM   _   OPI . The above discussion explains that in the embodiment of  FIG. 4 , the DC voltage V X  of the input terminal of the operational amplifier  432  in the amplification phase is not equal to the reference voltage V CM   _   OPI   _   S . By creating a voltage difference of
 
                 N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM           
between the reference voltage V CM   _   OPI   _   S  and the DC voltage V X , the operational amplifier  432  is less affected by the fact that the voltage V CM   _   REF  is not equal to the voltage V CM   _   PGA .
 
     With the circuit design of  FIG. 4 , the common-mode voltage V CM   _   REF  of the reference voltage V REF+  and the reference voltage V REF−  can be arbitrary, rather than having to be substantially equal to the common-mode voltage V CM   _   PGA  of the differential input signal V in . As a result, in some embodiments, the reference voltage V REF−  can be shifted to ground. For example, the reference voltage V REF+ , the common-mode voltage V CM   _   REF , and the reference voltage V REF−  can be shifted from 0.75VDD, 0.5VDD, and 0.25VDD to 0.5VDD, 0.25VDD, and 0, respectively, and the difference between the voltage V REF+  and the common-mode voltage V CM   _   REF  and the difference between the reference voltage V REF−  and the common-mode voltage V CM   _   REF  remain substantially unchanged (i.e., 0.25 VDD). Setting the reference voltage V REF−  to ground has the following advantages: (1) a unity gain buffer is saved to effectively reduce the circuit area; (2) ground provides a greater driving capability than any electric potential other than ground. 
       FIG. 6  is a circuit diagram of one operational stage of a 1.5-bit pipelined ADC according to another embodiment of the present invention. The operational stage  600  includes a sub ADC  610 , a decoder  620 , and an MDAC. The MDAC is the circuit besides the sub ADC  610  and the decoder  620 . The operations of the sub ADC  610  and the decoder  620  are the same as or similar to those of the conventional sub ADC  112  and decoder  114 , respectively, and are thus omitted for brevity. The MDAC includes an operational amplifier  632 , capacitors C 0   a , C 1   a , C 1   a ′, C 0   b , C 1   b , C 1   b ′, switches S 0   a  to S 4   a , S 1   a ′, S 4   a ′, and switches S 0   b  to S 4   b , S 1   b ′, and S 4   b ′. The capacitance values of the capacitor C 0   a  and the capacitor C 0   b  are substantially the same. The MDAC operates alternately in the sampling phase and the amplification phase. In the sampling phase, the switches S 0   a , S 1   a , S 1   a ′, S 2   a , S 0   b , S 1   b , S 1   b ′, S 2   b  are turned on, and the remaining switches are turned off. In the amplification phase, the switches S 3   a , S 4   a , S 4   a ′, S 3   b , S 4   b , S 4   b ′ are turned on, and the remaining switches are turned off. 
     The connections and operations of the capacitors C 0   a , C 0   b , C 1   a , C 1   b  are similar to the capacitors C 0   a , C 0   b , C 1   a , C 1   b  of  FIG. 4 , respectively. In this embodiment, however, the reference voltage V CM   _   OPI  is substantially equal to the DC voltage V X  of the input terminal of the operational amplifier  632  in the amplification phase because the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA  (i.e., the voltage V CM   _   REF  is not shifted). 
     One end of the capacitor C 1   a ′ (or C 1   b ′) is coupled to the reference voltage V CM   _   OPI  through the switch S 2   a  (or S 2   b ) in the sampling phase, and is coupled to an input terminal of the operational amplifier  632  but not to the reference voltage V CM   _   OPI  in the amplification phase; the other end of the capacitor C 1   a ′ (or C 1   b ′) receives the input signal V in   +  (or V in   − ) through the switch S 1   a ′ (or S 1   b ′) in the sampling phase, and receives the common-mode voltage V CM   _   REF  of the reference voltage V REF+  and the reference voltage V REF−  through the switch S 4   a ′ (or S 4   b ′) in the amplification phase. 
     In this embodiment, the reference voltage V REF+  and the reference voltage V REF−  do not necessarily satisfy V REF+ −V REF− =0.5V pp   _   max  (V pp   _   max  is the allowed maximum peak-to-peak value of the differential input signal V in ), but the common-mode voltage V CM   _   REF  of the reference voltage V REF+  and the reference voltage V REF−  is still substantially equal to the common-mode voltage V CM   _   PGA  of the differential input signal V in . For example, if the differential input signal V in  is limited between VDD and ground (i.e., V pp   _   max =VDD−0=VDD), then the difference between the voltages V REF+  and V REF−  can be designed to be equal to V pp   _   max =VDD (e.g., V REF+ =VDD and V REF−  =0), and V CM   _   REF  is still substantially equal to V CM   _   PGA =0.5VDD. In this embodiment, since the common-mode voltage V CM   _   REF  of the reference voltage V REF+  and the reference voltage V REF−  is still substantially equal to the common-mode voltage V CM   _   PGA  of the differential input signal V in , the reference voltage V CM   _   OPI  is substantially equal to the DC voltage V X  of the input terminal of the operational amplifier  632  in the amplification phase. 
     In response to the changes in the reference voltage V REF+  and the reference voltage V REF− , the capacitance values of the capacitors C 1   a , C 1   a ′, C 1   b , and C 1   b ′ need to be adjusted accordingly. The sum of the capacitance values of the capacitors C 1   a  (or C 1   b ) and C 1   a  (or C 1   b ′) is substantially equal to the capacitance value of the capacitor C 0   a  (or C 0   b ). The ratio of the capacitance value of the capacitor C 1   a  to that of the capacitor C 1   a ′ (or C 1   b  to C 1   b ′) is related to (V REF+ −V REF− )/V pp   _   max . More specifically, if the capacitance value of the capacitor C 0   a  (or C 0   b ) is C, the capacitance value of the capacitor C 1   a  (or C 1   b ) is XC (0&lt;X&lt;1), and the capacitance value of the capacitor C 1   a  (or C 1   b ′) is YC (0&lt;Y&lt;1), then X+Y is substantially equal to 1, and X=0.5×V pp   _   max /(V REF+ −V REF− ). That is, when (V REF+ −V REF− ) is R times V pp   _   max , X=½R. In one example, when V pp   _   max  VDD−0=VDD, V REF+ =VDD, and V REF− =0 (V CM   _   REF  (VDD+0)/2=0.5VDD=V CM   _   PGA ), R=(VDD−0)/VDD=1, X=½R=0.5, and Y=1−X=0.5. In another example, when V pp   _   max =VDD−0=VDD, V REF+ =0.9VDD, and V REF− =0.1VDD (V CM   _   REF =(0.9VDD+0.1VDD)/2=0.5VDD=V CM   _   PGA ), R=(0.9VDD−0.1VDD)/VDD=0.8, X=½R=0.625, and Y=1−X=0.325. 
     With the circuit design of  FIG. 6 , the difference between the reference voltage V REF+  and the reference voltage V REF−  can be arbitrary, rather than having to be substantially equal to 0.5 times the allowed maximum peak-to-peak value V pp   _   max  of the differential input signal V in . Therefore, in some embodiments, the reference voltage V REF−  can be scaled to ground. 
     In summary, in order to increase the design flexibility of the MDAC or the pipelined ADC employing same, the present invention proposes the embodiments of  FIG. 4  and  FIG. 6  that respectively enable shift and scaling of the reference voltage (V REF+  and V REF− ) for the MDAC. When one of the reference voltages is shifted or scaled to ground, a unity gain buffer can be omitted to thereby effectively reduce the circuit area. 
     The foregoing voltage level shift and scaling operations can be implemented at the same time, and  FIG. 7  shows the embodied circuit. The circuit and operation of the operational stage  700  are similar to the operational stage  600 , except that the reference voltage V CM   _   OPI  to which the capacitor in  FIG. 6  couples in the sampling phase is substantially equal to the DC voltage V X  of the input terminal of the operational amplifier  632  in the amplification phase, whereas the reference voltage V CM   _   OPI   _   S  to which the capacitor in  FIG. 7  couples in the sampling phase is not equal to the DC voltage V X  of the input terminal of the operational amplifier  632  in the amplification phase. The reference voltage V CM   _   OPI   _   S  can be designed as 
                 V     CM_OPI   ⁢   _S       =       V   X     +         N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM           ,         
where ΔV CM  V CM   _   PGA −V CM   _   REF .
 
       FIG. 8  is a circuit diagram of one operational stage of a 2.5-bit pipelined ADC according to another embodiment of the present invention. The operational stage  800  includes a sub ADC  810 , a decoder  820 , and an MDAC. The MDAC is the circuit besides the sub ADC  810  and the decoder  820 . The operations of the sub ADC  810  and decoder  820  are the same as or similar to those of the conventional sub ADC  112  and decoder  114 , respectively, and are thus omitted for brevity. The MDAC operates alternately in the sampling phase and the amplification phase.  FIG. 8  depicts only a part of the MDAC, that is, the partial circuit coupled to one of the input terminals of the operational amplifier  832 . Those skilled in the art can understand the circuitry of the rest of the MDAC of  FIG. 8  based on the disclosures of  FIG. 6  to  FIG. 8 . Based on the disclosures of  FIG. 6  to  FIG. 8 , those skilled in the art can also understand the circuit and operation details when the present invention is applied to a higher-order pipelined ADC. 
     In comparison with the operational stages  600  and  700 , the operational stage  800  further includes capacitors C 2   a , C 2   a ′, C 3   a , C 3   a ′, and capacitors C 2   b , C 2   b ′, C 3   b , C 3   b ′ (not shown). The capacitors C 2   b , C 2   b ′, C 3   b , C 3   b ′ are coupled to the other input terminal of the operational amplifier  832 . The capacitors C 1   a  to C 3   a  (or C 1   b  to C 3   b , not shown) receive the input signal V in   +  (or V in   − , not shown) through the switch group S 1 A (or SIB, not shown), and receive the output voltage(s) of the decoder  820  through the switch group S 4 A (or S 4 B, not shown). The capacitor C 1   a ′ to C 3   a ′ (or C 1   b ′ to C 3   b ′, not shown) receives the input signal V in   +  (or V in   − , not shown) through the switch group S 1 A′ (or S 1 B′, not shown), and coupled to the common-mode voltage V CM   _   REF  of the reference voltage V REF+  and the reference voltage V REF−  through the switch group S 4 A′ (or S 4 B′, not shown). The capacitors C 1   a  to C 3   a  and C 1   a ′ to C 3   a  (or C 1   b  to C 3   b  and C 1   b ′ to C 3   b ′, not shown) are coupled to the reference voltage V CM   _   OPI   _   S  through the switch S 2   a  (or S 2   b , not shown). The three switches in each of the switch groups S 1 A, S 1 A′, S 4 A, S 4 A′ (or S 1 B, S 1 B′, S 4 B, S 4 B′, not shown) are simultaneously turned on or off, and the switching operations of the switch groups S 1 A, S 1 A′, S 4 A, S 4 A′ (or S 1 B, S 1 B′, S 4 B, S 4 B′, not shown) are the same as those of the switches S 1   a , S 1   a ′, S 4   a , S 4   a  (or S 1   b , S 1   b ′, S 4   b , S 4   b ′) of  FIG. 6  and  FIG. 7 , respectively, and thus omitted for brevity. 
     If the capacitance value of the capacitor C 0   a  is C, the capacitance value of the capacitor C 1   a  is XC (0&lt;X&lt;1), and the capacitance value of the capacitor C 1   a ′ is YC (0&lt;Y&lt;1), then X+Y is substantially equal to 1, and X=0.5×V pp    _   max /(V REF+ −V REF− ). The same applies to the capacitor pairs (C 2   a , C 2   a ) and (C 3   a , C 3   a ′). When the voltage V CM   _   REF  is substantially equal to the voltage V CM   _   PGA , the DC voltage V X  of the input terminal of the operational amplifier  832  in the amplification phase is substantially equal to the reference voltage V CM   _   OPI   _   S . When the voltage V CM   _   REF  is not equal to the voltage V CM   _   PGA , the DC voltage V X  of the input terminal of the operational amplifier  832  in the amplification phase is not equal to the reference voltage V CM   _   OPI   _   S , that is, 
                 V     CM_OPI   ⁢   _S       =       V   X     +         N   -   1     N     ⁢   Δ   ⁢           ⁢     V   CM           ,         
where ΔV CM =V CM   _   PGA −V CM   _   REF  and N=4 for a 2.5-bit pipelined ADC. In one embodiment, the reference voltage V REF−  may be ground.
 
     Since a person having ordinary skill in the art can appreciate the implementation detail and the modification thereto of the present method invention through the disclosure of the device invention, repeated and redundant description is thus omitted. Furthermore, the shape, size, and ratio of any element in the disclosed figures are exemplary for understanding, not for limiting the scope of this invention. In addition, although the foregoing embodiments are exemplified by a 1.5-bit or 2.5-bit pipelined ADC, the present invention is not limited thereto. Those skilled in the art can apply the present invention to other pipelined ADCs of different bits according to the disclosure of the present invention. 
     The aforementioned descriptions represent merely the preferred embodiments of the present invention, without any intention to limit the scope of the present invention thereto. Various equivalent changes, alterations, or modifications based on the claims of the present invention are all consequently viewed as being embraced by the scope of the present invention.