Patent Publication Number: US-8526558-B1

Title: Recursive range controller

Description:
RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 11/403,509 filed Apr. 12, 2006, now issued as U.S. Pat. No. 8,073,042 on Dec. 6, 2011, which claims priority to U.S. Provisional Application No. 60/671,388 filed on Apr. 13, 2005, both of which are hereby incorporated by reference herein. 
    
    
     TECHNICAL FIELD 
     This invention relates generally to a range controller and, more particularly, to a recursive range controller. 
     BACKGROUND 
     Communications links, due to distance, are normally specified as synchronous or plesiochronos in nature, and in the presence of link errors or faults, may receive input streams at completely uncontrolled signaling rates. Examples of such communication links include SONET, OTN, Fibre Channel, Ethernet, InfiniBand, Serial ATA, SAS (serial attached SCSI), and some forms of PCI Express. Some of these links may be configured to transmit using a recovered clock (e.g., SONET), though most transmit using a local reference clock so as to limit any jitter transfer from a recovered clock. 
     All of these interfaces specify maximum allowed tolerance of the local reference clock, or maximum offset between the reference clock at the transmitting and receiving ends of a link. For SONET links this offset is normally specified as low as 20 ppm, while for Fibre Channel it can be as high as +/−100 ppm. 
     The logic that processes received data needs to process at least some portion of the data in the recovered clock domain. This logic is normally designed to operate over the normal or “operating” range of the system signaling rate, plus some small margin. However, in the case of a fiber break or similar fault, the receiver in the communication system may start processing noise as if it were data. When the receive phase locked loop (PLL) attempts to track the uncontrolled transitions in this noise, it can speed up to much faster than the normal operating range of the system. Typical voltage controller oscillators (VCOs) can operate at 2× or faster than their target operating frequency. If the downstream data-processing logic were presented with a clock this far out of specification, the logic would suffer multiple errors due to setup and hold violations. 
     To prevent this from happening, range-control hardware is added to the clock recovery hardware to limit the range of operation of the recovered clock to that which the downstream logic can tolerate. When an out-of-specification data stream is detected, the clock recovery circuit is directed to ignore the received data, and instead lock onto a local controlled signal that is within the allowed range of operation. 
     For these range-control circuits to work, they need to be able to respond to all of the potential link-fault conditions before the recovered clock presents an out of specification clock to the downstream logic. Likewise, it must also detect and report variations in link signaling rate that do not cause a permanent out-of-specification clock, but do present an invalid clock for a short period. However, tradeoffs in PLL bandwidth vs. phase noise are often necessary that allow the VCO to move faster than the evaluation period needed to ensure proper operating range. This leaves the user with a “hole” where, when presented with some types of external conditions, the normal range-control logic cannot detect the out-of-spec condition until the system is substantially out of specification, if at all. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. 
         FIG. 1A  is a block diagram illustrating an example of a PLL-based clock and data separator. 
         FIG. 1B  is a block diagram illustrating an example of a clock multiplication phase lock loop circuit. 
         FIG. 2  is a block diagram illustrating a conventional range controller. 
         FIG. 3  is a diagram illustrating an example of runaway VCO frequency. 
         FIG. 4  is a diagram illustrating an example of a non-detected range violation. 
         FIG. 5  is a block diagram illustrating an example of an evaluation period. 
         FIG. 6  is a block diagram illustrating an example of sub-period intervals according to one embodiment. 
         FIG. 7  is a block diagram illustrating an example of overlapped evaluation events according to one embodiment. 
         FIG. 8  is a block diagram illustrating a recursive range controller according to one embodiment. 
         FIG. 9  is a flow diagram illustrating a method for providing a recursive range controller in accordance with one embodiment. 
         FIG. 10  is a flow diagram illustrating a method for evaluating the corresponding data starting at each of the n sub-periods in accordance with one embodiment. 
         FIG. 11  is a flow diagram illustrating a method for processing the captured value at the end of each n sub-period in accordance with one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques are not shown in detail or are shown in block diagram form in order to avoid unnecessarily obscuring an understanding of this description. 
     References in the description to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification do not necessarily all refer to the same embodiment. The term “coupled” as used herein may include both directly coupled and indirectly coupled through one or more intervening components. 
     A recursive range controller is described. In one embodiment, the range controller detects frequency excursions of a VCO outside the allowed operating range. This may be performed by comparing the number of clocks (generated by the VCO), occurring within a known or fixed time window, to an allowed range of values. The time window is usually created by a counter running from a known or fixed clock frequency. This may be performed to ensure that the VCO for the clock-recovery (or transmit) PLL is operating at the frequency of the received data stream (instead of a harmonic of that frequency), and that the frequency is within allowed tolerance limits. 
       FIG. 1A  illustrates a block diagram illustrating one type of a conventional clock recovery phase locked loop circuit  10 . The circuit  10  generally comprises a phase detector  12 , a filter  14 , an oscillator  16 , and a decoding device  17 . This type of phase locked loop is used to synchronize a clock frequency  26  with serial data  33  such that the data can be recovered correctly. 
     Serial data is presented to an input  24  of the phase detector  12 . The phase detector  12  is generally coupled to the oscillator  16  through the filter  14 . An output  26  of the oscillator  16  is presented to an input  30  of the phase detector  12  as well as to an input  31  of the decoding device  17 . The decoding device  17  also has an input  33  that receives the serial data input. The circuit  10  is generally used to provide a properly timed clock (i.e., a clock at the same rate as the serial data, and with proper phase alignment to ensure adequate time margins) to the decoding device  17 . 
     A typical voltage controlled oscillator (VCO) has the capability to operate over a wide frequency range to (i) provide a flexible frequency of operation and (ii) accommodate process and environmental variations. A phase detector (PD) only reports phase error and is insensitive to the frequency of operation of the PLL. This insensitivity is required since serial data consists of variable width marks (or 1) and variable width spaces (or 0). The transitions, when they occur, are at predictable intervals, but the data stream has no intrinsic operating frequency because of the nature of the serial data stream. It is difficult for a conventional PLL to correct for frequency error when decoding serial data. Edges generally occur at approximately regular intervals of an input clock (i.e., the intrinsic operating frequency), but gross errors in clock rate can be misinterpreted as data running at another frequency. 
     One problem associated with the circuit  10  may occur when the VCO  16  operates at a harmonic (e.g., one half, twice, or other multiples) of the data rate of the serial data input. In such a case, the phase detector  12  will not report the error, but will instead indicate proper phase alignment. This occurs while the oscillator  16  provides an out of tolerance clock to the decoder device  17 . Another problem occurs when the frequency of oscillation of the signal at the output  26  is out of tolerance by a large amount. A range controller, further described in  FIG. 1A , coupled to the oscillator  16  may be used to detect whether the VCO  16  is operating within an operating range. 
     One approach to remedying the problem associated with the VCO  16  operating at a harmonic of the serial data input is to limit the operating range of the VCO, as closely as possible, to a small percentage around an expected data rate. In such a system a trimmed oscillator, or tunable oscillator, may be used to provide such a correction. 
     Referring to  FIG. 1B , another conventional phase locked loop circuit  10 ′ is shown. This type of phase locked loop is generally used to multiply a reference frequency by some multiple set by a feedback divider. The circuit  10 ′ generally substitutes a phase frequency detector  20  for the phase detector  12 . The phase frequency detector  20  is generally coupled to the oscillator  16  through the filter  14 . A divider circuit  18  has an input  28  that receives the output of the oscillator  16 . The divider  18  generally presents a signal to the input  30  of the phase frequency detector  20 . The phase frequency detector  20  is capable of indicating both phase error and frequency error though error information presented to the filter  14 . Errors coupled through the filter  14  cause the VCO  16  to change its frequency and phase to minimize the error. VCO frequency errors are easily managed by the circuit  10 ′. The nominal frequency of operation will be the reference frequency multiplied by a divider ratio. A typical phase frequency detector  20  as used in phase locked loop  10 ′ cannot tolerate irregular input data streams that may be found in a serial data input. 
       FIG. 2  illustrates one type of non-recursive range controller used in conjunction with the phase locked loops  10  and  10 ′ of  FIGS. 1A ,  1 B. The range controller of  FIG. 2  is configured to operate with two counters: one counter (Counter_A  202 ) clocked by the local reference clock (Clk_A), and the other counter (Counter_B  204 ) clocked by a derivative of the recovered clock Voltage Controller Oscillator (VCO) (Clk_B). At the end of an evaluation period, the count result  210  is compared to a short list of allowed values. If it does not match any of these values, then the VCO is operating out of range, and it is directed to operate in a recovery mode by comparison logic  212 . The local reference clock (Clk_A) is used to operate a controlling state machine  206  using a Sub-period trigger input  208 . However, this may prevent the system from properly reporting an invalid data stream if this reference clock ever dies or is otherwise disabled. To overcome this, the VCO clock may be used to run the controlling state machine  206 , which is then compared to the reference clock (Clk_A). 
     Several issues may exist with the range controller of  FIG. 2 . When used in conjunction with the clock and data recovery circuit illustrated in  FIG. 1A , the controlling state machine  206  generates events to both enable and disable the alternate counter. Since the alternate counter exists in a separate time domain, these control signals must go through time domain conversion circuits (generally in the form of metastable prevention circuits). Both the start event and the stop event cause one bit of uncertainty in the resulting count, which requires a longer count sequence to achieve the necessary accuracy. 
     Another issue is that frequency excursions that occur near the start of an evaluation period are not reported as being “out of range” until the end of the evaluation period, as shown in  FIG. 3 .  FIG. 3  illustrates two evaluation periods  302  and  304 . Because the VCO frequency  306  is within the allowed operating range  308  at the beginning of the first evaluation period  302  and the beginning of the second evaluation period  304 , the VCO frequency  306  passes the test of the comparator logic  212  of  FIG. 2 . However, use of a range controller such as that described in  FIG. 2 , results in a system  200  unable to respond to frequency excursions until well after the fact. In the second evaluation period  304 , the VCO frequency  306  goes outside the allowed operating range  308 . Frequency excursions that occur near the start  310  of the second evaluation period  304  are not reported as being “out of range” until the end  312  of the second evaluation period  304 . Because of the length of the evaluation period  304 , the VCO frequency  306  can move to a frequency well outside the allowed operating range  308 , before the excursion is caught and the VCO  16  is forced to lock a local reference. 
     Undetected offsetting frequency excursions such as that shown in  FIG. 4  may also occur as a result of the system  200  described in  FIG. 2 . The VCO frequency  402  goes outside the allowed operating range  308  both high and low within the same evaluation period  304 . At the beginning and end of the evaluation period  304 , the VCO frequency  402  is within the allowed operating range  308 . Such offsetting frequency excursion is not detectable within such a system. 
       FIG. 5  illustrates a traditional evaluation period. Each count period  502 ,  504 ,  506 , may be for example, 16-bits in length. Because of the long evaluation period in this example, events occurring in an early portion of this evaluation period are neither reported or acted upon until the end of the complete evaluation period. 
       FIG. 6  illustrates an evaluation period in accordance with one embodiment of the invention. Each count period  602 ,  604 ,  606 , may be for example, 16-bits in length. Each 16-bit count period may also be made from a concatenated sequence of eight 13-bit count sequences  608 . Performing an evaluation over one of these shorter periods  608  may not be sufficient to achieve the accuracy needed to determine if the VCO is operating within spec or not. However, by concatenating eight of these sub-periods  608  sequentially, sufficient time is present to validate the frequency. Instead of evaluating over a set of these sub-periods  608 , followed by evaluation of the next sequential set of sub-periods  608  (which would yield the same results as evaluating over the full evaluation period), it is possible to start a new evaluation at each sub-period boundary. This creates a continuous stream of overlapped evaluation events, with each event starting at one n-th the normal evaluation period. An example of this is shown in  FIG. 7 . 
       FIG. 7  illustrates that each of the overlapped evaluation periods  702  is made from a sequence of n-sub-periods. Since these evaluation periods overlap, the count events that occur in one are also part of n−1 other evaluation periods. An embodiment of the present invention operates by summing the counts that occur in each sub-period, and removing (subtracting) those counts from older sub-periods that no longer are part of the current evaluation period. 
       FIG. 8  is a block diagram illustrating one embodiment of a hardware implementation. A range controller  800  has two counters: one for the reference domain, Counter_A block  802 , and one for the VCO domain, Counter_B block  804 . Counter blocks  802 ,  804  can be either free running (requiring counter-relative measurements) or synchronous resettable. In one particular embodiment, for fail-safe operation (i.e., valid detection in the absence of a valid reference clock), a controlling state machine block  806  is operated in the VCO time domain. To evaluate the operating frequency to some specific tolerance requires approximately the same total evaluation period of time as with the range controller of  FIG. 2 . Note that this evaluation period may be shortened, relative to the range controller of  FIG. 2 , by the one count reduction in measurement uncertainty. 
     An embodiment of the range controller  800  of the present invention operates by segmentation of the evaluation period into n sub-periods, each of which is the same length, and some multiple of which equal the normal evaluation period. Segmenting the evaluation period into four, eight, or some other fraction allows n-times faster response to events, while allowing detection of high-accuracy limits. 
     At the end of each sub-period, the value of the Counter_B  804  is captured, processed, and the counter is synchronously set to zero (0). The processing is composed of 1) saving the captured count into a register file or first-in-first-out (FIFO) register block  808  having n-entries, 2) using an arithmetic logic unit (ALU) block  810  or similar logic to sum the captured count with the result from the previous count sum, 3) using the same or similar ALU block  812  to subtract the n-th previous captured count (as saved in the register file) from the summing register, and 4) checking to see if the result block  814  is within the allowed operating bounds. 
     Unlike the counter blocks  802  and  804 , which by default are able to operate at the character or other sub-multiple of the VCO rate, the arithmetic and register file operations occur only once per sub-period, and thus can be created from very slow and low-power circuits, potentially making use of clock gating to further reduce system power. 
     The ALU result block  814  after summing the present count and subtracting the n-th previous count is the sum of the previous n sub-periods, which is equivalent to the count of one complete evaluation period. Since sufficient counts have occurred, a Limit Compare block  816  determines (to the necessary level of accuracy) whether the VCO is operating within its allowed frequency range. But because a new evaluation is completed n-times in this evaluation period, the previously missed or late-reported events are now both detected and reported at or near the time of the error. 
     In more detail,  FIG. 8  illustrates two clocks (Clk_A and Clk_B). Clk_A is the local reference. Clk_B is the VCO clock. These clocks can be interchanged without impacting operation of the present embodiment. In one embodiment, a failsafe operation is achieved by making Clk_A the recovered (VCO) clock, and placing the local reference clock on Clk_B. 
     The period of Counter_A block  802  is set equal to the sub-period of the evaluation. Once each sub-period, it sends a Set pulse signal to the Sub-Period trigger block  818 , to start the actual evaluation of the current sub-period. This can occur at any time in Counter_A block  802 , but must always occur at the same point in Counter_A block  802 &#39;s evaluation period. This may occur at either the selected maximum (terminal) count of Counter_A block  802 , or when Counter_A block  802  restarts at zero. 
     Counter_B block  804  counts continuously, once per Clk_B input. When a trigger marker is generated by Counter_A block  802 , and converted to the Counter_B block  804  time domain, Counter_B block  804 &#39;s state is transferred to a holding register block  820 . The signal used to transfer Counter_B block  804 &#39;s state to the holding register block  820  may also be used to simultaneously clear Counter_B  804 . The sub-period trigger block  818  may also be synchronously cleared to prepare it for the next sub-period trigger. 
     In one embodiment, the sub-period trigger block  818  may be implemented as a latch, which can only be set from the Clk_A time domain, and can only be cleared from the Clk_B time domain. As an additional failure-detection mechanism, the logic in the Clk_A time domain may verify that the sub-period trigger block  818  is not set prior to attempting to set it. If, when attempting to set the latch, it is found in a set condition, then Clk_B is non-operational and a Fail condition should be generated. 
     The control state machine block  806  may be needed to initialize the FIFO block  808  and the different registers. While shown as operating directly from Clk_B, this may not be required. Since the operation of the evaluation circuits are non-time sensitive, they can be configured to operate from any reasonable clock, including a divided-down version of Clk_B, and could potentially operate from Clk_A (this would require a second monitor function on the sub-period trigger to ensure that the evaluation did not start until after the trigger was recognized in the Clk_B domain, and the counter value was captured in the holding register block  808 ), or some other clock source. 
     Following the removal of system reset, the controlling state machine  806  must ensure that the contents of the FIFO block  808  (or register file) and summing register block  810  are cleared to all zeros. This is necessary to ensure that the first n-cycles are properly summed without stale content in the FIFO block  808 . This may be done by physically clearing the FIFO block  808 , or mixing a value of zero into the ALU block  812  input from the FIFO block  808  for the first n sub-period cycles. 
     Those of ordinary skills in the art will recognize that the FIFO block  808  is not limited to a traditional FIFO structure. In an alternative embodiment, the FIFO block  808  may be clocked fully synchronously to the local clock domain, and can be implemented as another type of memory storage element such as a latch, memory cell, etc. Requirements may include that it have a fixed depth of n locations, and that the oldest (n-th) location is not overwritten until it has been subtracted from the current count. As each new count value is written to the FIFO block  808 , the previously captured counts are moved down through the FIFO block  808 , with each location x in the FIFO block  808  accepting the contents of the x−1 location, and location 0 accepting the newly captured count. 
     Two ALU  810 ,  812  operations are required to process each sub-period count: addition of the new count to a running sum, and a subtraction of the n-th FIFO location from that same running sum. It should be noted that as with normal addition and subtraction, these operations are fully commutative and may be done in any order. 
     The application of the embodiments of the present invention described herein allows fast excursions in frequency to be detected and reported to the system, as well as acted upon to prevent out-of-specification clocks from being driven into the system logic. Moreover, counters may be shortened (fewer bits); uncertainty may be reduced to one bit-time instead of two; evaluations occur multiple times per interval, using overlapped windows, allowing fast response to excursions; and offsetting excursions may be detected. 
     In an alternative embodiment, to limit the power in the counters  802 ,  804 , the counters  802 ,  804  can be changed from loadable/resettable to free-running. Grey-code counters may be used for this technical application because only a single-bit changes on any clock cycle, thus lowering the dynamic power significantly. When this is done, the counter state at the end of each sub period is still captured as before, but now contains a relative count instead of absolute count. To convert this relative count to absolute it is necessary to also maintain a saved copy of the previous captured counter state, and perform a subtraction of one from the other. 
     This subtraction may include carry compensation, since a free-running counter will roll-over regularly. This carry compensation is composed of a magnitude comparison of the two values. If the previous captured value is greater than or equal to the present captured count, then the maximum value of the counter plus one (max_val_count+1) must be added to the present captured count before subtracting the previous captured count. This delta between previous and current count values is then processed the same as in the previously described implementation. 
     In another embodiment, a hardware intensive implementation of the present invention may be made using multiple instances of the full counter, each started at the next sequential evaluation boundary. 
     Embodiments of the recursive range controller  800  may enable segmentation of the evaluation period into n sub-periods; use of a register file or FIFO to store intermediate results; the ability to detect link faults in less than a full evaluation period; and/or the ability to detect offsetting frequency excursions. Embodiments of the range controller described herein may be used in high-speed serial communications links. Such links may be used, for example, to replace the parallel interfaces on a static random access memory (SRAM) and a network search engine (NSE), also referred to as a content addressable memory (CAM). 
     It should be noted that various components described herein may be implemented with other similar types of components. For example, the registers described herein may be implemented as another type of memory storage element such as a latch, memory cell, etc. 
       FIG. 9  illustrates a flow diagram illustrating a method for detecting out-of-specification data streams. At  902 , data is received over several evaluation periods. At  904 , each evaluation period is segmented into n sub-periods. Each sub-period has a same length and spans a corresponding portion of the data. At  906 , the corresponding data period starting each of the n sub-periods is evaluated. 
       FIG. 10  illustrates a flow diagram illustrating a method for evaluating the corresponding data starting at each of the n sub-periods. At  1002 , the evaluation of the corresponding data period starts at an n-th sub-period of a first evaluation period and finishes at an n-th sub-period of a second evaluation period. At  1004 , at the end of each of the n-subperiods, a value of a counter is captured. At  1006 , the captured value is processed. At  1008 , the counter value is synchronously reset to zero. 
       FIG. 11  illustrates a flow diagram illustrating a method for processing the captured value at the end of each n sub-period. At  1102 , the captured count value is saved into a first register. At  1104 , an n-th previous captured count is saved. At  1106 , a first logic circuit is used to sum the captured count with a result from a previous count sum and generate a summed result. At  1108 , a second logic circuit is used to subtract an n-th previous captured count from the summed result to generate a subtraction result. At  1110 , the subtraction result is checked to determine whether it is within an allowed operating bound. If the subtraction result is within the allowed operating bound, the test passes at  1112 . If the subtraction result is outside the allowed operating bound, the test fails at  1114   
     Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit and scope of the invention as set forth in the claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.