Patent Publication Number: US-2023163021-A1

Title: Rf devices with enhanced performance and methods of forming the same utilizing localized soi formation

Description:
RELATED APPLICATIONS 
     This application is a divisional of U.S. patent application Ser. No. 16/390,496, filed Apr. 22, 2019, which claims the benefit of provisional patent application Ser. No. 62/660,374, filed Apr. 20, 2018, the disclosures of which are hereby incorporated herein by reference in their entireties. 
    
    
     FIELD OF THE DISCLOSURE 
     The present disclosure relates to a radio frequency (RF) device and a process for making the same, and more particularly to an RF device with enhanced thermal and electrical performance, and a die-level packaging process to provide the RF device with enhanced performance by utilizing localized silicon on insulator (SOI) formation through porous silicon. 
     BACKGROUND 
     The wide utilization of cellular and wireless devices drives the rapid development of radio frequency (RF) technologies. The substrates on which RF devices are fabricated play an important role in achieving high level performance in the RF technologies. Fabrications of the RF devices on conventional silicon handle substrates may benefit from low cost of silicon materials, a large scale capacity of wafer production, well-established semiconductor design tools, and well-established semiconductor manufacturing techniques. 
     Despite the benefits of using conventional silicon handle substrates for the RF device fabrications, it is well known in the industry that the conventional silicon handle substrates may have two undesirable properties for the RF devices: harmonic distortion and low resistivity values. The harmonic distortion is a critical impediment to achieving high level linearity in the RF devices built over silicon handle substrates. In addition, high speed and high performance transistors are more densely integrated in RF devices. Consequently, the amount of heat generated by the RF devices will increase significantly due to the large number of transistors integrated in the RF devices, the large amount of power passing through the transistors, and/or the high operation speed of the transistors. Accordingly, it is desirable to package the RF devices in a configuration for better heat dissipation. 
     To accommodate the increased heat generation of the RF devices and to reduce deleterious harmonic distortion of the RF devices, it is therefore an object of the present disclosure to provide an improved packaging process for enhanced thermal and electrical performance. Further, there is also a need to enhance the performance of the RF devices without increasing the package size. 
     SUMMARY 
     The present disclosure relates to a radio frequency (RF) device with enhanced thermal and electrical performance, and a die-level packaging process for making the same. The disclosed RF device includes a device substrate having a top surface, a thinned device die with a device region and a number of bump structures, a first mold compound, and a second mold compound. The device region of the thinned device die includes an isolation portion, a back-end-of-line (BEOL) portion with a number of connecting layers, and a front-end-of-line (FEOL) portion with a contact layer and a first active section. The contact layer of the FEOL portion resides over the BEOL portion, the first active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the first active section. The bump structures are formed at a bottom surface of the BEOL portion and attached to the top surface of the device substrate. Herein, the bump structures are electrically coupled to the FEOL portion via certain ones of the connecting layers. The first mold compound resides over the top surface of the device substrate, surrounds the thinned device die, and extends vertically beyond the thinned device die to define an opening over the thinned device die and within the first mold compound. The isolation portion of the thinned device is at the bottom of the opening. The second mold compound substantially fills the opening and is in contact with the isolation portion. 
     In one embodiment of the RF device, the first active section is configured to provide an n-type field-effect transistor (NFET), and includes a P-well with an N-source and an N-drain inside. Herein, the P-well is encapsulated by the isolation portion. The contact layer includes a gate structure extending from underneath the N-source to underneath the N-drain, a source contact connected to the N-source, a drain contact connected to the N-drain, and a gate contact connected to the gate structure. At least one of the drain contact and the source contact is coupled to the certain ones of the connecting layers by vias. 
     In one embodiment of the RF device, the FEOL portion further includes a second active section. Herein, the second active section resides over the contact layer and is encapsulated by the isolation portion. The first active section and the second active section are separated by the isolation portion. 
     In one embodiment of the RF device, the first active section and the second active section are electrically coupled by one of the connecting layers within the BEOL portion. 
     In one embodiment of the RF device, the first active section is configured to provide a first NFET, and includes a first P-well with a first N-source and a first N-drain inside, while the second active section is configured to provide a second NFET and includes a second P-well with a second N-source and a second N-drain inside. The first active section and the second active section are encapsulated and separated by the isolation portion. The contact layer includes a first gate structure extending from underneath the first N-source to underneath the first N-drain, a first source contact connected to the first N-source, a first drain contact connected to the first N-drain, a first gate contact connected to the first gate structure, a second gate structure extending from underneath the second N-source to underneath the second N-drain, a second source contact connected to the second N-source, a second drain contact connected to the second N-drain, and a second gate contact connected to the second gate structure. Herein, the first N-source contact is electrically coupled to the second N-drain contact by one of the connecting layers and vias. 
     In one embodiment of the RF device, the first mold compound and the second mold compound are formed of different materials. 
     In one embodiment of the RF device, the first mold compound and the second mold compound are formed of a same material. 
     In one embodiment of the RF device, the second mold compound has a thermal conductivity greater than 1 W/m·K. 
     In one embodiment of the RF device, the second mold compound has a dielectric constant less than 8. 
     In one embodiment of the RF device, the first mold compound and the second mold compound have a dielectric constant between 3 and 5. 
     According to an exemplary process, a precursor package, which includes a device substrate, a first mold compound, a device die with a device region, a silicon handle substrate, and a number of bump structures, is firstly provided. The device region includes an isolation portion, a back-end-of-line (BEOL) portion with a number of connecting layers, and a front-end-of-line (FEOL) portion with a contact layer and a first active section. The contact layer resides over the BEOL portion, the first active section resides over the contact layer, and the isolation portion resides over the contact layer to encapsulate the first active section. The bump structures are formed at a bottom surface of the BEOL portion and attached to a top surface of the device substrate. Herein, the bump structures are electrically coupled to the FEOL portion via certain ones of the connecting layers. The silicon handle substrate resides over the isolation portion of the device region, and the first mold compound resides over the top surface of the device substrate to encapsulate the device die. Next, the first mold compound is thinned down to expose the silicon handle substrate of the device die. The silicon handle substrate is then removed completely to provide a thinned device die, and form an opening within the first mold compound and over the thinned device die. The isolation portion is at the top of the thinned device die and exposed at the bottom of the opening. A second mold compound is applied to substantially fill the opening and reside directly over the isolation portion. 
     In one embodiment of the exemplary process, the first active section is configured to provide an NFET and includes a P-well with an N-source and an N-drain inside. Herein, the P-well is encapsulated by the isolation portion. The contact layer includes a gate structure extending from underneath the N-source to underneath the N-drain, a source contact connected to the N-source, a drain contact connected to the N-drain, and a gate contact connected to the gate structure. At least one of the drain contact and the source contact is coupled to one of the connecting layers by vias. 
     In one embodiment of the exemplary process, the FEOL portion further includes a second active section. Herein, the second active section resides over the contact layer and is encapsulated by the isolation portion, and the first active section and the second active section are separated by the isolation portion. 
     In one embodiment of the exemplary process, the first active section and the second active section are electrically coupled by one of the connecting layers within the BEOL portion. 
     In one embodiment of the exemplary process, the first active section is configured to provide a first NFET and includes a first P-well with a first N-source and a first N-drain inside, while the second active section is configured to provide a second NFET and includes a second P-well with a second N-source and a second N-drain inside. The first P-well of the first active section and the second P-well of the second active section are encapsulated and separated by the isolation portion. The contact layer includes a first gate structure extending from underneath the first N-source to underneath the first N-drain, a first source contact connected to the first N-source, a first drain contact connected to the first N-drain, a first gate contact connected to the first gate structure, a second gate structure extending from underneath the second N-source to underneath the second N-drain, a second source contact connected to the second N-source, a second drain contact connected to the second N-drain, and a second gate contact connected to the second gate structure. Herein, the first N-source of the first active section is electrically coupled to the second N-drain of the second active section by one of the connecting layers. 
     In one embodiment of the exemplary process, the second mold compound has a thermal conductivity greater than 1 W/m·K. 
     In one embodiment of the exemplary process, the second mold compound has a dielectric constant less than 8. 
     In one embodiment of the exemplary process, the first mold compound and the second mold compound have a dielectric constant between 3 and 5. 
     In one embodiment of the exemplary process, providing the precursor package starts with providing a SOI starting wafer that includes a P-well, the isolation portion, and the silicon handle substrate. Herein, the isolation portion resides around and underneath the P-well and the silicon handle substrate resides underneath the isolation portion, such that the isolation portion separates the P-well from the silicon handle substrate. The FEOL portion is then formed, where the first active section of the FEOL portion is formed from the P-well and the contact layer is formed over the first active section. The isolation portion resides around and underneath the first active section and separates the first active section from the silicon handle substrate. The BEOL portion is formed over the FEOL portion. Next, the bump structures are formed at the top surface of BEOL portion to complete the device die. The device die is flipped upside down and mounted to the device substrate. As such the bump structures are at the bottom surface of the BEOL portion and attached to the device substrate. The backside of the silicon handle substrate is the tallest component. The first mold compound is then applied over the device substrate to encapsulate the device die. 
     In one embodiment of the exemplary process, providing the SOI starting wafer starts with providing a p-type silicon wafer. A buried p-type layer within the p-type silicon wafer is then formed by p-type ion implementation. The buried p-type layer divides the silicon wafer into the silicon handle substrate underneath the buried p-type layer and an upper p-type layer over the buried p-type layer. Next, the upper p-type layer is converted into an upper n-type layer by n-type ion implantation. A number of P+ sections are then formed, each of which extends from a top surface of the upper n-type layer into the buried p-type layer under the upper n-type layer, such that an individual upper n-type section is formed in the upper n-type layer and separate from other portions of the upper n-type layer. An electrochemical etching process is performed to convert the buried p-type layer and the P+ sections into a continuous p-type porous silicon (PSi) portion. Herein, the p-type PSi portion resides around and underneath the upper n-type section. At last, the p-type PSi portion is oxidized to provide the isolation portion, and the upper n-type section is converted into the P-well. Herein, the isolation portion resides around and underneath the P-well, and separates the P-well from the silicon handle substrate. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG.  1    shows an exemplary radio frequency (RF) device with enhanced thermal and electrical performance according to one embodiment of the present disclosure. 
         FIGS.  2 - 18    provide an exemplary die-level packaging process that illustrates steps to fabricate the exemplary RF device shown in  FIG.  1   . 
     
    
    
     It will be understood that for clear illustrations,  FIGS.  1 - 18    may not be drawn to scale. 
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     With the looming shortage of conventional radio frequency silicon on insulator (RFSOI) wafers expected in the coming years, alternative technologies are being devised to get around the need for the RFSOI wafers. One of these alternative technologies is a localized SOI technology by the oxidation of electrochemically etched porous silicon (PSi). However, the localized SOI technology will also suffer from the deleterious distortion effects due to the silicon substrate, similar to what is observed in an RFSOI technology, such that high resistivity substrates and trap-rich layer formation may still be requested. The present disclosure, which relates to an RF device with enhanced thermal and electrical performance, and a die-level packaging process to provide the RF device with enhanced performance by utilizing localized SOI formation through porous silicon, is based on a low-cost low resistivity silicon substrate without a trap-rich layer. 
       FIG.  1    shows an exemplary RF device  10 , which is formed from a low-cost low resistivity silicon handle substrate (not shown herein, processing details are described in following paragraphs), according to one embodiment of the present disclosure. The exemplary RF device  10  includes a device substrate  12 , a thinned device die  14 , a first mold compound  16 , and a second mold compound  18 . In detail, the device substrate  12  may be formed from a multi-layer laminate. The thinned device die  14  is attached to a top surface of the device substrate  12 , and includes a number of bump structures  20 , a device region  22  with a back-end-of-line (BEOL) portion  24 , a front-end-of-line (FEOL) portion  26 , and an isolation portion  28 . For the purpose of this illustration, the FEOL portion  26  includes a contact layer  30 , a first active section  32 , and a second active section  34 . The contact layer  30  resides over the BEOL portion  24  and the first and second active sections  32  and  34  reside over the contact layer  30 . The isolation portion  28  resides over the contact layer  30 , and the first active section  32  and the second active section  34  are encapsulated and separated by the isolation portion  28 . In different applications, the FEOL portion  26  may include fewer or more active sections. 
     In one embodiment, the first active section  32  is configured to provide a first n-type field-effect transistor (NFET) and includes a first P-well  36  with a first N-source  38  and a first N-drain  40  inside. The second active section  34  is configured to provide a second NFET and includes a second P-well  42  with a second N-source  44  and a second N-drain  46  inside. The isolation portion  28 , which may be formed of silicon dioxide, encapsulates the first P-well  36  and the second P-well  42  separately, as to isolate the first active section  32  from the second active section  34 . A top surface of the isolation portion  28  is a top surface of the thinned device die  14 . In other applications, the first/second active section  32 / 34  may be configured to provide a P-type FET, a diode, or a resistor. 
     The contact layer  30  includes a first gate structure  48 , a first source contact  50 , a first drain contact  52 , a first gate contact  54 , a second gate structure  56 , a second source contact  58 , a second drain contact  60 , a second gate contact  62 , and vias  64  (only one via is labeled with a reference number for clarity), each of which is formed within an insulating material  66 . The first gate structure  48  may be formed of silicon oxide, and extends from underneath the first N-source  38  to underneath the first N-drain  40 . The first source contact  50 , the first drain contact  52 , and the first gate contact  54  are directly connected to and under the first N-source  38 , the first N-drain  40 , and the first gate structure  48 , respectively. Similarly, the second gate structure  56  may be formed of silicon oxide, and extends from underneath the second N-source  44  to underneath the second N-drain  46 . The second source contact  58 , the second drain contact  60 , and the second gate contact  62  are directly connected to and under the second N-source  44 , the second N-drain  46 , and the second gate structure  56 , respectively. 
     The BEOL portion  24  includes multiple connecting layers  68  formed within dielectric layers  70 . Each via  64  extends from the first source contact  50 , the first drain contact  52 , the second source contact  58 , or the second drain contact  60  to a corresponding connecting layer  68 . In this embodiment, the first N-drain  40  is electrically coupled to the second N-source  44  through the first drain contact  52 , vias  64 , one of the connecting layers  68 , and the second source contact  58 , such that the first NFET provided by the first active section  32  and the second NFET provided by the second active section  34  are coupled in series to form a switch. In some applications, the FEOL portion  26  may provide more FETs (between 4 and 40), and the connecting layers  68  in the BEOL portion  24  connect these FETs in series to form a switch with a desired OFF state voltage. In some applications, the first active section  32  and the second active section  34  may not be electrically connected. 
     The bump structures  20  are formed at a bottom surface of the BEOL portion  24 , and attached to the top surface of the device substrate  12 . Herein, the bump structures  20  are electrically coupled to at least one of the first active section  32  and the second active section  34  (the first source contact  50  and the second drain contact  60  in this illustration) by certain ones of the connecting layers  68  and certain ones of the vias  64 . The bump structures  20  may be solder balls or copper pillars. 
     The first mold compound  16  resides over the top surface of the device substrate  12 , underfills and surrounds the thinned device die  14 , and extends above a top surface of the thinned device die  14  to form an opening  72  over the top surface of the thinned device die  14  and within the first mold compound  16 . Herein, the top surface of the thinned device die  14  (the top surface of the isolation portion  28 ) is at the bottom of the opening  72 . The first mold compound  16  may be an organic epoxy resin system or the like, which can be used as an etchant barrier to protect the thinned device die  14  against etching chemistries such as potassium hydroxide (KOH), sodium hydroxide (NaOH), and acetylcholine (ACH). In some applications, there may be an underfilling layer (not shown) residing over the top surface of the device substrate  12 , such that the underfilling layer encapsulates the bump structures  20  and underfills the thinned device die  14  between the bottom surface of the BEOL portion  24  and the top surface of the device substrate  12 . The underfilling layer may be formed of a same or different material as the first mold compound, and is configured to mitigate the stress effects caused by Coefficient of Thermal Expansion (CTE) mismatch between the thinned device die  14  and the device substrate  12 . Herein, the first mold compound  16  resides over the underfilling layer and surrounds the thinned device die  14 , but does not underfill the thinned device die  14 . 
     The second mold compound  18  substantially fills the opening  72 , and is in contact with the top surface of the thinned device die  14  (the top surface of the isolation portion  28 ). The second mold compound  18  has a thermal conductivity greater than 1 W/m·K or greater than 10 W/m·K, has an electrical resistivity greater than 1E6 Ohm-cm, and has a low dielectric constant less than 8, or between 3 and 5 to yield low RF coupling. The second mold compound  18  may be formed of thermoplastics or thermoset materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, diamond-like thermal additives, or the like. The second mold compound  18  may be formed of the same or different material as the first mold compound  16 . However, unlike the second mold compound  18 , the first mold compound  16  does not have thermal conductivity, electrical resistivity, or dielectric constant requirements. Herein, a portion of the second mold compound  18  may reside over the first mold compound  16 . 
       FIGS.  2 - 18    provide an exemplary die-level packaging process that illustrates steps to provide the exemplary RF device  10  shown in  FIG.  1   . In addition,  FIGS.  2 - 10    illustrate exemplary steps to provide a SOI starting wafer by utilizing localized SOI formation through porous silicon (PSi).  FIGS.  11 - 18    illustrate exemplary steps to fabricate the exemplary RF device  10  with enhanced performance from the SOI starting wafer shown in  FIG.  10   . Although the exemplary steps are illustrated in a series, the exemplary steps are not necessarily order dependent. Some steps may be done in a different order than that presented. Further, processes within the scope of this disclosure may include fewer or more steps than those illustrated in  FIGS.  2 - 18   . 
     Initially, a silicon wafer  74  with a screen oxide layer  76  on top is provided as illustrated in  FIG.  2   . The silicon wafer  74  is a p-type wafer and may have a low resistivity between 1 Ohm-cm and 50 Ohm-cm. The screen oxide layer  76  is grown over the silicon wafer  74  and may have a thickness about 50 nm. A low-dose high-energy p-type ion (such as boron) is then implanted into the silicon wafer  74  to form a higher concentration buried p-type layer  78 , as illustrated in  FIG.  3   . The buried p-type layer  78  divides the silicon wafer  74  into two portions, a silicon handle substrate  80  with a thickness between 200 μm and 1500 μm (or between 200 μm and 700 μm) and an upper p-type layer  82  with a thickness between 100 Å and 5000 Å (or between 100 Å and 1000 Å). The buried p-type layer  78  extends horizontally across the whole wafer  74 , such that the silicon handle substrate  80  and the upper p-type layer  82  are completely separated by the buried p-type layer  78 . The buried p-type layer  78  will be activated at an appropriate high temperature (typically between 600° C. and 1200° C. depending on the conditions of the implant and actual ion species used). 
     Next, the screen oxide layer  76  is removed and replaced with a silicon nitride layer  84  as illustrated in  FIG.  4   . The silicon nitride layer  84  may be formed of Si 3 N 4  by low pressure chemical vapor deposition (LPCVD), and may have a thickness about 150 nm. A high-dose fluorine ion implantation is then performed to convert the upper p-type layer  82  into an upper n-type layer  86  (the thickness does not change), as illustrated in  FIG.  5   . Because of the buried p-type layer  78 , the silicon handle substrate  80  is untouched and remains p-type. 
     A lithography step is followed as illustrated in  FIG.  6   . One or more photoresist components  88  are placed over the silicon nitride layer  84  to selectively block the silicon nitride layer  84 . A number of P+ sections  90  are then formed underneath exposed regions of the silicon nitride layer  84 , as illustrated in  FIG.  7   . Herein, the P+ sections  90  may be connected to each other and may be formed by a high dose p-type ion (such as boron) implantation into portions of the upper n-type layer  86 , which are underneath the exposed regions of the silicon nitride layer  84 . The P+ sections  90  will also be activated at an appropriate high temperature (typically between 600° C. and 1200° C. depending on the conditions of the implant and actual ion species used). Each P+ section  90  may extend from a top surface of the upper n-type layer  86  into the buried p-type layer  78 . As such, the upper n-type layer  86  is divided into separate sections, a first upper n-type section  86 - 1  and a second upper n-type section  86 - 2  in this illustration. In different applications, there may be much more upper n-type section formed from the upper n-type layer  86 . In this step, the silicon handle substrate  80  is untouched and remains p-type. 
     Removal of the one or more photoresist components  88  and the silicon nitride layer  84  is followed to provide a precursor wafer  92 , as illustrated in  FIG.  8   . The silicon nitride layer  84  may be removed by reactive ion etching. When the precursor wafer  92  is annealed in Nitrogen at temperatures between 600° C. and 1200° C., the silicon lattice properties in the first upper n-type section  86 - 1 , the second upper n-type section  86 - 2 , the buried p-type layer  78 , and the P+ sections  90  are restored. Herein, the p-type ions (such as boron) in the P+ sections  90  and in the buried p-type layer  78  are substantially fully activated. An electrochemical etching process is then performed to provide a PSi wafer  94 , which includes a p-type PSi portion  96  formed from the buried p-type layer  78  and the P+ sections  90 , as illustrated in  FIG.  9   . The first upper n-type section  86 - 1  and the second upper n-type section  86 - 2  are untouched and remain separate from each other. The electrochemical etching process requires that a bias voltage is applied across the wafer  92 / 94  and the wafer  92 / 94  is immersed in an appropriate wet chemistry. For instance, a bias of 0.4V-1 V for a period of several minutes (5 m-15 m) and a chemistry of 4:1 hydrofluoric acid:isopropyl alcohol (HF:IPA) may be used to convert the boron-doped buried p-type layer  78  and the boron-doped P+ sections  90  into the high quality p-type PSi portion  96 , while leaving the first upper n-type section  86 - 1  and the second upper n-type section  86 - 2  unchanged. A width of the first/second upper n-type section  86 - 1 / 86 - 2  must be carefully selected so as to not have any gaps under the first/second upper n-type section  86 - 1 / 86 - 2 , which are not fully converted into PSi. The p-type PSi portion  96  resides around and underneath the first upper n-type section  86 - 1  and the second upper n-type section  86 - 2 , and also separates the first upper n-type section  86 - 1  and the second upper n-type section  86 - 2  from each other. 
     Next, a multistep thermal process is performed to provide a SOI starting wafer  98  from the PSi wafer  94 , as illustrated in  FIG.  10   . In one embodiment, the multistep thermal process starts with placing the PSi wafer  94  in oxygen (O 2 ) at 300° C. for one hour; then the wafer is placed in water steam at 900° C. for fifteen minutes; next, the wafer is placed in O 2  at 1000° C. for one hour; and at last, the wafer is placed in nitrogen (N 2 ) at 1100° C. for four hours. This process completely oxidizes the p-type PSi portion  96  to provide the isolation portion  28  that is composed of silicon oxide. Ideally, a porosity factor of 56% void in the silicon is targeted in the p-type PSi portion  96 , so as to create an ideal density and no volume expansion for when the p-type PSi portion  96  is converted to silicon oxide. In addition, this process converts the first and second upper n-type sections  86 - 1  and  86 - 2  into the first and second P-well  36  and  42  (the thickness does not change), respectively, which are used for device fabrication in the following steps. Consequently, the isolation portion  28  resides around and underneath the first P-well  36  and the second P-well  42 , separates the first P-well  36  and the second P-well  42  from each other, and also separates the first P-well  36  and the second P-well  42  from the silicon handle substrate  80 . If there are more upper n-type sections in the PSi wafer  94 , there will be more P-wells formed in the SOI starting wafer  98  separated by the isolation portion  28 . Note that the silicon handle substrate  80  is not oxidized and remains p-type. 
     After the SOI starting wafer  98  is prepared, the FEOL portion  26  is formed based on the first P-well  36  and the second P-well  42 , as illustrated in  FIG.  11   . The FEOL portion  26  may be formed by a complementary-metal-oxide-semiconductor (CMOS) process, and includes the first active section  32 , the second active section  34 , and the contact layer  30 . The first active section  32  and the second active section  34  are formed from the first P-well  36  and the second P-well  42 , respectively. If the first active section  32  is configured to provide NFET, the first active section  32  may be formed by ion implantation in the first P-well  36  to add the first N-source  38  and the first N-drain  40  within the first P-well  36 . Similarly, the second active section  34  may be formed by ion implantation in the second P-well  42  to add the second N-source  44  and the second N-drain  46  within the second P-well  42 . The ion implantation may be realized by Halo implant, LDD implant, or other implanting technologies. Herein, the isolation portion  28  resides around and underneath the first active section  32  and the second active section  34 , separates the first active section  32  and the second active section  34  from each other, and also separates the first active section  32  and the second active section  34  from the silicon handle substrate  80 . 
     The contact layer  30  resides over the first active section  32 , the second active section  34 , and the isolation portion  28 . The first (second) gate structure  48  ( 56 ) extends over from the first (second) N-source  38  ( 44 ) to the first (second) N-drain  40  ( 46 ). The first (second) source contact  50  ( 58 ), the first (second) drain contact  52  ( 60 ), and the first (second) gate contact  54  ( 62 ) are directly connected to the first (second) N-source  38  ( 44 ), the first (second) N-drain  40  ( 46 ), and the first (second) gate structure  48  ( 56 ), respectively. The first gate structure  48 , the first source contact  50 , the first drain contact  52 , the first gate contact  54 , the second gate structure  56 , the second source contact  58 , the second drain contact  60 , and the second gate contact  62  are formed within the insulating material  66 . Each via  64  extends from the first source contact  50 /the first drain contact  52 /the second source contact  58 /the second drain contact  60  to a top surface of the contact layer  30 . 
     Next, the BEOL portion  24  is formed over the FEOL portion  26  to complete the device region  22 , which includes the BEOL portion  24 , the FEOL portion  26 , and the isolation portion  28 , as illustrated in  FIG.  12   . The BEOL portion  24  includes the connecting layers  68  within the dielectric layers  70 . Each via  64  exposed at the top surface of the contact layer  30  is electrically coupled to a corresponding connecting layer  68 . When the first active section  32  and the second active section  34  are configured to provide NFETs, the first active section  32  and the second active section  34  may be connected in series by one of the connecting layers  68  to form a CMOS switch. When the first active section  32  and the second active section  34  are configured to provide different types of FETs or other electronic components, the first active section  32  and the second active section  34  may not be electrically connected. Portions of certain ones of the connecting layers  68  are exposed through the dielectric layers  70  at the top surface of the BEOL portion  24 . In addition, the BEOL portion  24  may further provide metal-insulator-metal (MIM) capacitors (not shown) by utilizing the connecting layers  68  and the dielectric layers  70 . 
     The bump structures  20  are then formed at the top surface of the BEOL portion  24  to provide a device wafer  100 , as depicted in  FIG.  13   . Each bump structure  20  is in contact with the exposed portion of a corresponding connecting layer  68 . Herein, each bump structure  20  is electrically coupled to the first active section  32  (the first N-source  38  in this illustration) or the second active section  34  (the second N-drain  46  in this illustration) by certain ones of the connecting layers  68  and a corresponding via  64 . The bump structures  20  may be formed by a solder ball bumping technology or a copper pillar packaging technology. Each bump structure  20  protrudes from the top surface of the BEOL portion  24  between 20 μm and 350 μm. The device wafer  100  is then singulated into individual dies (not shown), each of which realizes a circuit function and includes one or more active sections in the FEOL portion  26 . Herein, an exemplary singulated device die  14 F includes the device region  22  with the first active section  32  and the second active section  34 , the bump structures  20  at the top of the device region  22 , and the silicon handle substrate  80  underneath the isolation portion  28  of the device region  22 . 
     The device die  14 F is then flipped upside down and mounted to the device substrate  12  as depicted in  FIG.  14   . It is clear to those skilled in the art that, a top surface of any layer/portion/region of the device die  14 F becomes a bottom surface, while a bottom surface of any layer/portion/region of the device die  14 F becomes a top surface. Herein, the bump structures  20  of the device die  14 F are attached to the top surface of the device substrate  12 , and the backside of the silicon handle substrate  80  is the tallest component after the attaching process. In different applications, there may be multiple device dies mounted to the device substrate  12 . Next, the first mold compound  16  is applied over the top surface of the device substrate  12  to provide a precursor package  102  as illustrated in  FIG.  15   . The device die  14 F is fully encapsulated by the first mold compound  16 . If there are multiple device dies mounted to the device substrate  12 , the first mold compound  16  individually encapsulates each device die, and separates one from each other. 
     The first mold compound  16  may be applied by various procedures, such as sheet molding, overmolding, compression molding, transfer molding, dam fill encapsulation, and screen print encapsulation. The first mold compound  16  may be formed from an organic epoxy resin system or the like, such as Hitachi Chemical Electronic Materials GE-100LFC, which can be used as an etchant barrier to protect the device die  14 F against etching chemistries such as KOH, NaOH, and ACH. A curing process (not shown) is followed to harden the first mold compound  16 . The curing temperature may be between 100° C. and 320° C. depending on which material is used as the first mold compound  16 . 
     Notice that, if the RF device  10  includes an underfilling layer, there may be extra steps to form the underfilling layer (not shown) before applying the first mold compound  16  over the top surface of the device substrate  12 . Forming the underfilling layer is provided by applying an underfilling material over the top surface of the device substrate  12  and then curing the underfilling material to form the underfilling layer. The underfilling layer encapsulates the bump structures  20  and underfills the device die  14 F between the bottom surface of the BEOL portion  24  and the top surface of the device substrate  12 . The first mold compound  16  is then applied over the underfilling layer, and encapsulates at least the sides and the top surface of the device die  14 F. 
       FIG.  16    shows a thinning procedure where the first mold compound  16  is thinned down to expose the backside of the silicon handle substrate  80  of the device die  14 F. The thinning procedure may be done with a mechanical grinding process. The silicon handle substrate  80  is then selectively removed to provide an etched package  104 , where the selective removal is stopped on the isolation portion  28 , as illustrated in  FIG.  17   . The removal of the silicon handle substrate  80  from the device die  14 F provides the thinned device die  14  and forms the opening  72  within the first mold compound  16  and over the thinned device die  14 . The top surface of the surface of the thinned device die  14  is the top surface of the isolation portion  28 , which is exposed at the bottom of the opening  72 . The isolation portion  28  remains encapsulated by the first active section  32  and the second active section  34 . 
     The removal of the silicon handle substrate  80  may be provided by an etching process with a wet/dry etchant chemistry, which may be TMAH, KOH, ACH, NaOH, or the like. The isolation portion  28  functions as an etching stop to protect the first active section  32 , the second active section  34 , and the contact layer  30  of the thinned device die  14 . The first mold compound  16  protects the sides and bottom surface of the thinned device die  14  from the etching process. 
     Next, the second mold compound  18  is applied over the etched package  104  to provide a mold device package  106 , as illustrated in  FIG.  18   . The second mold compound  18  substantially fills the opening  72  and is in contact with the top surface of the thinned device die  14 . Herein, substantially filling an opening refers to filling at least 75% of the entire opening. There is no silicon handle substrate  80  left in the opening  72 , such that there is no silicon handle substrate  80  between the second mold compound  18  and the isolation portion  28 . In some applications, portions of the second mold compound  18  may extend over the first mold compound  16 . 
     The second mold compound  18  may have a superior thermal conductivity greater than 1 W/m·K, or greater than 10 W/m·K, and may have a dielectric constant less than 8, or between 3 and 5. The second mold compound  18  may be formed of thermoplastics or thermoset materials, such as PPS (poly phenyl sulfide), overmold epoxies doped with boron nitride, alumina, carbon nanotubes, diamond-like thermal additives, or the like. The second mold compound  18  may be formed of the same or different material as the first mold compound  16 . However, unlike the second mold compound  18 , the first mold compound  16  does not have thermal conductivity, electrical resistivity, or dielectric constant requirements. The second mold compound  18  may be applied by various procedures, such as compression molding, sheet molding, overmolding, transfer molding, dam fill encapsulation, and screen print encapsulation. A curing process (not shown) is followed to harden the second mold compound  18 . The curing temperature is between 100° C. and 320° C. depending on which material is used as the second mold compound  18 . After the curing process, the second mold compound  18  may be thinned and/or planarized (not shown). 
     Lastly, the mold device package  106  may be marked, diced, and singulated into individual devices (not shown). The RF device  10  is an exemplary singulated device, which achieves switch functionality. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.