Patent Publication Number: US-3969719-A

Title: Electronic watch

Description:
CROSS REFERENCE TO RELATED CASES 
     This application is a divisional of commonly assigned patent application, Ser. No. 320,223, filed Jan. 2, 1973 for &#34;ELECTRONIC WATCH&#34;, now U.S. Pat. No. 3,815,354 the disclosure of which is hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     This invention is directed to a signal phase controller for use in the electronic watch disclosed in the above referenced patent application. The referenced electronic watch is designed to consume extremely small amounts of electrical power during operation so that the useful lifetime of a battery power source is considerably prolonged over conventional electronic watches. The watch is composed of electronic circuits which are operated at a relatively low voltage, e.g. 1.5 volts DC, and other electronic circuits which are operated at a relatively high voltage, e.g. approximately 15 volts DC. The low voltage portion circuitry generates low voltage control signals which must be converted to relatively high voltage control signals in order to drive a liquid crystal display. 
     SUMMARY OF THE INVENTION 
     The invention comprises a system for controlling the relative phase of a pair of relatively high voltage signals in response to a relatively low voltage control signal from a source. In the preferred embodiment, the system comprises C MOS electronic circuitry including a source for providing a pair of periodic relatively high voltage signals of opposite phase; a level converter adapted to be coupled to said source of low voltage control signal for converting said low voltage control signal to a high voltage control signal; and a transfer gate having a pair of transfer inputs each coupled to a different one of said pair of periodic relatively high voltage signals and a control portion coupled to said level converter for transmitting a first one of said pair of periodic relatively high voltage signals to the output thereof in the absence of said control signal and for transmitting the other one of said pair of periodic relatively high voltage signals to the output thereof when said control signal is present. 
     The transfer gate includes first and second pairs of complementary transistors, each pair comprising two opposite conductivity type transistors connected in parallel in source-drain fashion, the gate of each transistor of one pair being coupled to the gate of the opposite conductivity type of each said pair comprising said transfer inputs, a second commonly coupled source-drain connection of each said pair comprising said transfer output, and the commonly connected gates comprising said control portion. 
    
    
     For a fuller understanding of the nature and advantages of the invention, reference should be had to the ensuing detailed description taken in conjunction with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a system diagram of the electronic watch embodying the invention; 
     FIG. 2 is a circuit diagram illustrating the preferred embodiment of the invention; and 
     FIG. 3 is a waveform diagram illustrating the operation of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT 
     Turning now to the drawings, FIG. 1 illustrates an electronic watch embodying the invention. An oscillator 10 having a control crystal 12 provides a train of high frequency reference pulses preferably at a frequency of 32,768 HZ to the input of a frequency divider circuit 14. Frequency divider circuit 14 divides the high frequency reference signal down to 64 HZ, 32 HZ and 1 HZ reference signals. The 64 HZ and 1 HZ reference signals are coupled to the input of a time keeping unit 16, which provides output signals representative of minutes and hours to a decoder unit 18. 
     Decoder unit 18 is provided with a plurality of output leads 19 1  -19 i  each coupled to a low voltage control input terminal of a different level converter 20 1  -20 i . It is noted that the 1 HZ output signal from divider 14 is also coupled directly to a level converter 20 o . 
     The output of each level converter 20 0  -20 i  is coupled to the control input of a different transfer gate 22 0  -22 i . The output of each transfer gate 22 o  -22 i  is a high level signal for enabling a different one of a plurality of display segment control electrodes 24 0  -24 i  of a liquid crystal display 25. 
     In the preferred embodiment, liquid crystal display 25 is arranged as a plurality of conventional 7 segment digital display characters. By selectively actuating different combinations of the individual segments the decimal digits 0-9 may be displayed. In the preferred embodiment two such characters are used for indicating minutes and two characters for indicating hours. A special segment 24 0  is pulsed at a 1 second rate by the 1HZ signal on lead 19 0  to provide a visual indication to the wearer that the electronic watch is functioning properly. The structure and operation of liquid crystal displays are well known and further structural details of display 25 are accordingly omitted to avoid prolixity. Such displays are characterized by low current consumption compared to light emitting diode displays or other known types of displays suitable for use as time indicators. However, for proper operation a liquid crystal display requires the application of a relatively high enabling potential between a given segment 24 i  and the common electrode 30. Moreover, this relatively high enabling potential is preferably applied in an A.C. mode as described below in order to prolong the life of the display. 
     As will be apparent, the number of level converters 20 0  -20 i , transfer gates 22 0  -22 i  and display segment control electrodes 24 0  -24 i  is determined by the number of desired reference characters and the number of segments per character. To avoid needless repetition, the majority of such elements have been indicated in the FIG. 1 diagram by broken lines. 
     A low voltage source 26 providing a source voltage V D  of approximately 1.5 volts DC in the preferred embodiment is coupled to the supply voltage input of oscillator 10, divider unit 14, time keeping unit 16 and decoder unit 18. Low voltage source 26 is also coupled to a regulated voltage converter 27 which converts the relatively low voltage from source 26 to a relatively high voltage of the order of approximately 15 volts DC in the preferred embodiment. The output from regulated voltage converter 27 is coupled to the supply voltage input of level converters 20 0  -20 i , a level converter 20 j  and a shaper 29. The high level output of the shaper 29 is coupled to the transfer inputs of transfer gates 22 0  -22 i  and to common electrode 30 of liquid crystal display 25. 
     As will now be apparent, oscillator 10, divider 14, time keeping unit 16 and decoder 18 are all powered by the relatively low voltage V D  from source 26. Since these units are all well known to those skilled in the art their details have been omitted to avoid prolixity. These units are preferably implemented by CMOS circuitry. As will be evident to those skilled in the art, circuits designed in accordance with the principles of CMOS (complementary metal oxide semiconductor) technology utilize opposite conductivity type transistors arranged in such a manner that current is only drawn during extremely small switching periods. Thus, such circuits require extremely small amounts of current for proper operation. In addition, such circuits can readily be designed to function properly from extremely low supply voltage. Thus, low voltage source 26 may comprise any one of a number of commercially available 1.5 volt DC batteries. 
     In operation, the train of high frequency reference pulses from oscillator 10 is divided down by divider 14 to the 64 Hz, 32 Hz and 1 Hz time reference signals. The 1 Hz reference signals are applied to timekeeping unit 16 which provides a minutes and hours count in response thereto. The minutes and hours signals from time keeping unit 16 are decoded by decoder unit 18 into low level signals on leads 19 1  -19 i  for specifying the individual segments 24 1  -24 i  of liquid crystal display 25 which are to be actuated in order to provide a visual time indication. The low level 1 Hz reference signals on lead 19 0  are also utilized to specify the actuation of seconds segment 24 0  of liquid crystal display 25. 
     Level converters 20 0  -20 i  and 20 j , transfer gates 22 0  -22 i  and shaper 29 are all operated at a relatively high potential V D , provided by regulated voltage converter 27. Level converters 20 0  -20 i  convert the low level control signals at their respective inputs 19 0  -19 i  to high level control signals for operating transfer gates 22 0  -22 i . Level converter 20 j  converts the low level 32 Hz control signal present on input lead 19 j  to high level 32 Hz signals. These high level signals from level converter 20 j  are shaped by shaper 29 to provide high level 32 Hz segment actuation signals with sharply defined leading and trailing edges. The segment actuation signals are coupled through transfer gates 22 0  -22 i  to segments 24 0  -24 i  and directly to common electrode 30 of liquid crystal display 25. As more fully described below in connection with FIGS. 7 and 8, transfer gates 22 0  -22 i  control the phase of the segment actuation signals coupled therethrough with reference to the phase of the segment actuation signal coupled directly to common electrode 30. When the segment actuation signals on a given segment 24 i  and common electrode 30 are in phase, that segment is not displayed; when segment actuation signals are out of phase that segment is actuated. Thus, various segments of the minutes and hours digit characters are displayed or not depending on the low level output signals on leads 19 1  -19 i  from decoder unit 18. In this manner, the various digits indicating minutes and hours are displayed. 
     An important feature of the watch shown in FIG. 1 resides in the operation of the time keeping system comprising oscillator 10, divider unit 14, time keeping unit 16 and decoder unit 18 at the low voltage level V D  provided by source 26 and the operation of the level converters 20 0  -20 i , 20 j , transfer gates 22 0  -22 i  and shaper 29 at the high voltage level V D , provided by regulated voltage converter 27. Because of the low voltage operation of the time keeping system and the use of complementary semiconductor circuitry, the power consumption of the continuously operating time keeping system is held to a minimum. Because of the complementary semiconductor circuit configuration of the high level operated level converters 20 0  -20 i , 20 j , gates 22 0  -22 i  and shaper 29, power consumption of this relatively high voltage portion of the preferred embodiment is also held to a minimum. 
     FIG. 2 illustrates the actual circuitry employed in the preferred embodiment for implementing level converter 20 j , shaper 29 and level converter 20 i  and transfer gate 22 i , the latter circuitry being typical of level converters 20 1  -20 i  and transfer gates 22 1  -22 i . In this Fig. the elements comprising the various blocks shown in FIG. 1 are enclosed in broken rectangles bearing the same reference numeral. 
     Level converter 20 j  includes a first and second pair of P-type MOS transistors 100, 101 and 102, 103, respectively, each pair being connected source-to-source and drain-to-drain as shown. The commonly-connected sources of each pair are coupled to ground potential. The gate of each inner transistor of each pair is coupled to the common drain terminal of the other pair. The gate inputs to outer transistors 100,103 are the 32 Hz reference signals on lead 19 j  from divider 14 of FIG. 1 and the output of an inverter 105, respectively. The common drain terminal of each pair is coupled to the drain terminal of a different N-type MOS transistor 106,107 respectively. The gate of each transistor 106,107 is coupled to the gate of the associated inner transistor 101,102 respectively. A constant current source comprising an N-type MOS transistor 108 having relatively high voltage V D  &#39; coupled to the source terminal thereof and biasing voltage V B  coupled to the gate thereof in order to permanently bias transistor 108 on is provided in the left main branch of level converter 20 j . An identically configured constant current source comprising N-type MOS transistor 109 is provided in the right branch of level converter 20 j . 
     In operation, with enabling voltages V D  &#39; and V B  applied to transistors 108,109 and the low level input signal on terminal 19 j  at the true level, transistor 100 is biased off. The inverted input signal from inverter 105 is false and transistor 103 is thus biased on. Q j  is thus at ground potential and biases transistor 101 off and transistor 106 on. Since transistor 106 is biased on by Q j  and transistor 108 is biased on by voltage V B , Q j  is at voltage V D  &#39;. Q j  at voltage V D  &#39; biases transistor 102 on and transistor 107 off. 
     When the low level input signal on terminal 19 j  transitions false, transistor 100 is biased on and transistor 103 is biased off. Since transistor 100 is now on, the voltage at Q j  rises to ground potential, turning transistor 102 off and transistor 107 on. As transistor 102 is biased off, the voltage at Q j  falls to V D  &#39;, biasing transistor 101 on and transistor 106 off. The circuit remains latched in this state until the input signal on lead 19 j  transitions true. 
     When the low level input signal on lead 19 j  transitions true, transistor 100 is biased off and transistor 103 is biased on. As transistor 103 is biased on, the voltage at Q j  rises to ground potential, biasing transistor 101 off and transistor 106 on. As transistor 106 is biased on, the voltage at Q j  falls to V D  &#39;, biasing transistor 102 on and transistor 107 off. The circuit remains latched in this state until the input signal on lead 19 j  again transitions false. Further operation of level converter 20 j  proceeds as already described. 
     As will now be apparent, level converter 20 j  provides a pair of oppositely phased output signals on terminals Q j , Q j  which range in magnitude between a negative voltage V D  &#39; having a relatively high magnitude and ground potential in response to an input signal on lead 19 j  which ranges in magnitude between a negative voltage V D  having a relatively low magnitude and ground potential. As noted above, in the preferred embodiment the range of the magnitude of the input signal is approximately 0-1.5 volts DC while the range on the magnitude of the output signal is approximately 0-15.0 volts DC. Thus, level converter 20 j , as well as level converters 20 1  -20 i , permit the low voltage portion of the electronic time keeping system to control the relatively high voltage display. It is important to note that level converter 20 j  draws current only during the extremely short transitional periods when the circuit is being switched between opposite latched states, due to the complementary configuration of the circuit. Thus, the current consumption of level converter 20 j  is extremely small and discontinuous, being of the order of 1 microamp when switching. 
     The output signals from level converter 20 j  on leads Q j  and Q j  are coupled to the control gate of complementary MOS transistors 110, 111, 112, 113, respectively, of shaper 29. Shaper 29 comprises a CMOS set-reset flip-flop which is used to steepen the leading and trailing edges of the output signal pulses from level converter 20 j . As illustrated by wave forms B and C of FIG. 8, the output signals on terminals Q 29 , Q 29  of shaper 29 comprise a pair of oppositely phased 32 Hz square wave pulse trains ranging in magnitude between voltage V D  &#39; and ground potential. The output signal on Q 29  is coupled directly to common electrode 30. of liquid crystal display 25. The output signals on Q 29  and Q 29  are coupled to transmission gates 22 0  -22 i , only one of which is shown in FIG. 7. 
     Transmission gate 22 i  comprises two pair of parallel connected CMOS transistors 120, 121 and 122, 123 respectively. The gates of CMOS transistors 121,122 are commonly connected to the Q i  output terminal of level converter 20 i . Similarly, the gates of CMOS transistors 120, 123 are commonly connected to the Q i  output terminal of level converter 20 i . Whenever the output signal on Q i  is high (ground potential) and the output signal on Q i  is low (V D  &#39;) transistors 120 and 121 are biased on and the signal on Q 29  is transmitted to display segment 24 i . Conversely, whenever the output signal on Q i  is high and the output signal of Q i  is low, transistors 122 and 123 are biased on and the signal of Q 29  is transmitted to display segment 24 i . 
     Level converter 20 i  is substantially identical in configuration to above-described level converter 20 j . The input signal to level converter 20 i , however, is a relatively low frequency time control signal from decoder unit 18, it being remembered that the control signals change at the maximum rate of 1 per minute for segments representing the units minutes characters and the minimum rate of 1 per 12 hours for segments representing the tens hours character. Due to the relatively low frequency of the control signals applied to level converter 20 i , it is not necessary to shape the output signals from this element present on terminals Q i , Q i . 
     The output signals from level converter 20 i  control the phase of the commutated square wave signal applied to display segment 24 i  relative to the phase of the commutated square wave signal applied to common electrode 30. This is best illustrated with reference to FIG. 3. Wave form A represents the relatively low level 32 Hz square wave input signal to level converter 20 j  present on lead 19 j . Wave forms B and C illustrate the 32 Hz relatively high level output signals from shaper 29 present on output terminals Q 29 , Q 29  respectively. Wave form D illustrates the relatively low level control signal to level converter 20 i  present on lead 19 i . Wave forms E and F represent the relatively high level output signal from level converter 20 i  present on the output terminals Q i  and Q i  respectively. Wave form G illustrates the output signal from transfer gate 22 i  coupled to display segment 24 i . Wave form H illustrates the signal from terminal Q 29  coupled to common electrode 30 of liquid crystal display 25. For economy of space all of the above wave forms are represented in abbreviated form indicated by the broken central portion. 
     When wave forms G and H are in phase, the potential difference between display segment 24 i  and common electrode 30 is zero and the segment 24 i  is off. Conversely, when wave forms G and H are out of phase a striking potential is established between segment 24 i  and common electrode 30 and segment 24 i  is on. The relative phase of wave forms G and H is determined by control wave form D. When this control signal is true, wave forms E and F are false and true respectively, and wave form G follows wave form H. When wave form D is false wave forms E and F are true and false, respectively, and wave form G is oppositely phased from wave form H. Thus, with segment 24 i  initially off, indicated by the hatched area, when wave form D transitions false segment 24 i  is turned on as indicated by the unhatched area. When wave form D again transitions true, segment 24 i  is again turned off. 
     In the preferred embodiment, each segment 24 i  is operated in an A.C. mode by reversing the direction of the potential between the segment and common electrode 30 at the arbitrary rate of 32 Hz. This mode of operation of all character segments is utilized in order to prolong the life of liquid crystal display 25. When the preferred embodiment is used to drive other types of relatively high voltage display devices, A.C. operation may not be required for efficient operation. In such applications, the display segments 24 and common electrode 30 may be driven directly by level converters 20 0  -20 i  and level converter 20 j , transmission gates 22 0  -22 i , and shaper 29 may be omitted. 
     The entire electronic time keeping and display system disclosed herein can be virtually fabricated from a single integrated circuit chip, the outline of which is outlined in FIG. 1 by the phantom-lined border indicated by reference character C. As indicated by this Fig., the only components which are not included in the single integrated circuit chip are oscillator crystal 12, low voltage source 26, which must be removable when exhausted, and a portion of regulated voltage converter 27. With reference to FIG. 6, those elements of regulated voltage converter 26 which are not housed in the single integrated circuit chip, also outlined in phantom in this Fig., are resistor 42 and the discreet elements of voltage converter 44: viz, transistor 52, inductor 53, diode 54 and capacitor 55. Thus, only seven circuit elements -- one of which must be readily replacable -- are carried externally of the single integrated circuit chip. As will be evident to those skilled in the art, this enables the electronic time keeping system of the invention to be fabricated and assembled at an extremely low cost. 
     Referring again to FIG. 1, liquid crystal display 25 comprises a separate physical package, indicated by the phantom-lined border D, from the integrated circuit chip, and may be arranged relative thereto in any convenient manner. 
     As will now be evident to those skilled in the art, the level converters utilized in the electronic time keeping system enable the low voltage time control signals to control the operation of the high voltage display without comsuming great quantities of current, thereby contributing to the efficient low power operation of the entire system. 
     While the above provides a full and complete disclosure of the preferred embodiment of the invention, various modifications, alternate constructions and equivalents may be employed without departing from the true spirit and scope of the invention. Therefore, the above description and illustrations should not be construed as limiting the scope of the invention which is solely defined by the appended claims.