Patent Publication Number: US-7222287-B2

Title: Decoder, error position polynomial calculation method, and program

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a decoder for Reed-Solomon codes, an error position polynomial calculation method, and a program for executing the error position polynomial calculation method. 
   This application claims the priority of the Japanese Patent Application No. 2003-050327 filed on Feb. 27, 2003, the entirety of which is incorporated by reference herein. 
   2. Description of the Related Art 
   Reference Cited (Non-Patent Publication) 1: 
   Communications, 1998. ICC 98. Conference Record. 1998 IEEE International Conference on, Volume: 2, 1998, A (208,192;8) “Reed-Solomon decoder for DVD application” by: Rsie-Chia Chang; Shung, C. B., Page(s): 957–960 vol. 2. 
   Reference Cited (Non-Patent Publication) 2: 
   Communications, IEEE Transactions on, Volume: 47 Issue: 10, Oct. 1999, “On decoding of both errors and erasures of a Reed-Solomon code using an inverse-free Berlekamp-Massey algorithm” by: Jyh-Horng Jeng; Trieu-Kien Truong, Page(s): 1488–1494. 
   There has been a coding method of decoding Reed-Solomon codes. In this method, if positions of those received words that have dropped from a transmission path are given, more errors can be corrected based on data concerning the positions than errors corrected in normal corrections. 
   This method uses an erasure position polynomial which takes an erasure position as a solution thereof, in addition to a group of numerical values which is called a syndrome and is calculated and obtained from received words during normal decoding. It is hence possible to compensate for drops of data up to a number equal to the parity number at the maximum. When this method is used in combination with a so-called interleave method, it is possible to cope with drops of large received data which may depend on a damage on a recording medium. 
   A description will now be made along a decoding method for Reed-Solomon codes. 
   When corrections are normally made in Reed-Solomon decoding, the relationship of N−K=2t−1 exists between the maximum number t of correctible errors t and code parameters (N, K). 
   At first, a syndrome S 0 , S 1 , . . . , S 2t−1  is calculated from received data by a syndrome calculation circuit. 
   The syndrome polynomial is expressed by the following expression (1). 
   
     
       
         
           
             
               
                 
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   Also from the syndrome S 0 , S 1 , . . . , S 2t−1 , an error position polynomial is obtained by use of an error position polynomial calculation circuit. The error position polynomial is a polynomial expressed by the following expression (2) where positions of errors are Z 0 , Z 1 , . . . , Z 2t−1 . 
   
     
       
         
           
             
               
                 
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   Further, an error value polynomial Ω(x) is obtained by the following expression (3) from the error position polynomial σ(x) and the syndrome.
 
Ω( x )= S ( x )σ( x ) mod x   2t   (3)
 
   Hence, the position and numerical value of an actual error can be derived from these expressions. 
   To construct a circuit for decoding Reed-Solomon codes, the circuit which derives the error position polynomial σ(x) makes the greatest influences on the circuit scale and the number of operation steps. The foregoing cited reference 1 introduces a circuit equipped with Berlekamp algorithms, as the circuit which calculates the error position polynomial σ(x). This circuit is shown in  FIG. 1 . 
   Provided in the circuit shown in  FIG. 1  are input registers rg 14  for the syndrome S 0 , S 1 , . . . S 2t−1  and a selector SEL 14  for making a selection from the input registers rg 14 . Also provided are a shift register SR 1  for the series of variable σ and a shift register SR 2  for the series of valuable λ. There are further provided adders AD 11  and AD 12 , multipliers ML 11 , ML 12 , and ML  13 , registers rg 11 , rg 12 , and rg 13 , and selectors SEL 11  and SEL 12 . 
   In case of this circuit, a Galois field operation circuit having a large scale is constructed from only three circuits (multipliers ML 11 , ML 12 , and ML 13 ), which is superior from the viewpoint of the circuit scale. This circuit, however, does not support erasure corrections. 
   When an erasure position expressed in form of a Galois field which indicates an error position of a symbol among code words is obtained in advance in correction processing for Reed-Solomon codes, the number of correctible errors can be raised up to N−K. This is called an erasure correction. The number of erasure position codes, Neras (the number of erasure errors), and Nerr (the number of errors) have the following relationship (4) between each other.
 
 N−K=N   eras +2 N   err   (4)
 
   To make only erasure corrections, at first, the erasure position polynomial Λ(x) expressed by the following expression (5) is calculated from a Galois field expressing an erasure position. 
   
     
       
         
           
             
               
                 
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   To make only erasure corrections, the error value polynomial may be derived by substituting this expression for σ(x) in the foregoing expression (2). 
   In case of performing simultaneously both the normal error corrections and the erasure corrections, the error position polynomial σ is derived from the syndrome and the erasure position polynomial Λ. 
   The other foregoing cited reference  2  proposes modified Berlekamp algorithms which can perform erasure corrections with less changes to conventional algorithms. 
     FIG. 2  shows the entire configuration of a decoder proposed in the cited reference  2  in case of performing the normal error corrections and the erasure corrections simultaneously. 
   A syndrome calculator  31  calculates the syndrome S 0 , S 1 , . . . , S 2t−1  from inputted data c. 
   An erasure position polynomial calculator  32  obtains the erasure position polynomial Λ(x) from erasure flags e 0 , e 1 , . . . , e 2t−1  by the foregoing expression (5). 
   An error position polynomial calculator  33  derives an error position polynomial σ(x) from the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position polynomial Λ(x). 
   A Chien searcher  35  obtains a numerical error value from the error position polynomial σ and the error value polynomial  106  (x). Further, inputted data c is delayed by a delay buffer  36  to predetermined timing and inputted to an operator  37 . In this operator  37 , the inputted data c is subjected to an operation using the numerical error value from the Chien searcher  35 , and is outputted as decoded data c′. 
   This configuration performs the normal error corrections and the erasure corrections simultaneously. It is however necessary for this configuration to derive the erasure position polynomial Λ(x) from the erasure flags e 0 , e 1 , . . . , e 2t−1  before deriving the error position polynomial σ(x). In addition, the erasure position polynomial Λ(x) must be processed after the syndrome calculation because the erasure position polynomial Λ(x) cannot be calculated before all the erasure flags are inputted. Therefore, if the configuration shown in  FIG. 2  is adopted, an operation step of calculating the erasure position polynomial is needed after completion of the syndrome calculation. A problem hence arises in that the number of necessary operation steps increases. 
   SUMMARY OF THE INVENTION 
   The present invention has been made in view of these problems, and has an object of realizing a decoder and an error position polynomial calculation method which can achieve erasure corrections by making less changes to a conventional calculation circuit based on Berlekamp-Massey algorithms. 
   Hence, a decoder according to the present invention comprises: a syndrome calculator which performs a syndrome calculation with respect to inputted data; an erasure position data calculator which calculates erasure position data from an inputted erasure flag; an error position polynomial calculator which calculates an error position polynomial on the basis of a syndrome obtained by the syndrome calculator and the erasure position data obtained by the erasure position data calculator; an error value polynomial calculator which calculates an error value polynomial from the error position polynomial; and a correction processor which calculates an error value from the error position polynomial and the error value polynomial, and performs a correction processing on the inputted data. 
   Further, the error position polynomial calculator includes a buffer having a selector to switch an input based on the number of processing steps from start of processing, and a selector which switches connection between the buffer and an operator, based on the number of processing steps and the number of pieces of erasure data, and wherein the error position polynomial calculator is constructed in a structure in which the error position polynomial which has the error position data as a solution, from a Galois field expression of an erasure position and the syndrome, is obtained. 
   In an error position polynomial calculation method according to the present invention, an error position polynomial is calculated by use of a syndrome calculated from inputted data and erasure position data calculated from an inputted erasure flag. 
   In particular, switching of connection between a buffer holding an uncompleted result of an operation and an operator is controlled on the basis of the number of erasure received words and the number of processing steps, to obtain the error position polynomial which has error position data as a solution, from a Galois field expression of an erasure position and a syndrome. 
   A program according to the present invention realizes this error position polynomial calculation method. 
   That is, conventionally, the error position polynomial σ(x) is calculated on the basis of the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position polynomial Λ(x) in case where erasure corrections are supported. In contrast, according to the present invention, the error position polynomial σ(x) is calculated on the basis of the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position data Er 0 , Er 1 , . . . , Er 2t−1 . In addition, the erasure position data calculator obtains the erasure position data Er 0 , Er 1 , . . . , Er 2t−1  from erasure flags e 0 , e 1 , . . . , e 2t−1  through a simple calculation. 
   Moreover, switching of connection between buffers holding uncompleted results of operations, and the operator is controlled based on the number of erased received words and the number of processing steps, so that derivations of both the erasure position polynomial and the error position polynomial from erasure position data can be realized by one equal circuit (the error position polynomial calculator). 
   As a result, an advantage is obtained in that a decoder capable of erasure corrections can be constructed by making less changes to a conventional calculation circuit based on Berlekamp-Massey algorithms. This is also capable of reducing increase of the circuit scale to the minimum without involving increase in number of the Galois field multipliers. 
   Further, regardless of the number of erased received code words, processings can be achieved by a least necessary number of fixed steps, so that coding delays can be reduced to the minimum. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a circuit diagram of a circuit equipped with Berlekamp algorithms; 
       FIG. 2  is a block diagram of a decoder which supports erasure corrections; 
       FIG. 3  is a block diagram of a decoder according to an embodiment of the present invention; 
       FIG. 4  is a circuit diagram of an error position polynomial calculator in the embodiment; 
       FIGS. 5A and 5B  explain switching operations of Galois field multipliers in the embodiment; 
       FIG. 6  is a flowchart of error position polynomial calculation processing in the embodiment; 
       FIG. 7  is a flowchart of error position polynomial calculation processing in the embodiment; and 
       FIG. 8  is a flowchart of error position polynomial calculation processing in the embodiment. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   Hereinafter, a decoder and an error position polynomial calculation method according to an embodiment of the present invention will be described with reference to  FIGS. 3 to 8 . 
   The decoder according to the present embodiment can support erasure position corrections while reducing the circuit scale and the number of operation steps. 
     FIG. 3  shows the entire decoder for Reed-Solomon codes according to the present embodiment. 
   A syndrome calculator  1  calculates a syndrome S 0 , S 1 , . . . , S 2t−1  from input data c. 
   An erasure position data calculator  2  calculates erasure position data Er 0 , Er 1 , . . . , Er 2t−1  from inputted erasure flags e 0 , e 1 , . . . , e 2t−1 . 
   An error position polynomial calculator  3  derives an error position polynomial σ(x) from the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position data Er 0 , Er 1 , . . . , Er 2t−1 . 
   An error value polynomial calculator  4  obtains an error value polynomial Ω(x) from the foregoing expression (3) by use of the error position polynomial σ. 
   A Chien searcher  5  obtains a numerical error value from the error position polynomial σ and the error value polynomial Ω(x). Inputted data c is delayed by a delay buffer  6  to predetermined timing and inputted to an operator  7 . The operator  7  operates the inputted data c by use of the numerical error value from the Chien searcher  5 , and outputs decoded data c′. 
   This kind of decoder in the present embodiment differs from the foregoing decoder shown in  FIG. 2  in the following two points (i) and (ii). 
   (i) In  FIG. 2 , the erasure position polynomial Λ(x) is obtained by the erasure position polynomial calculator  32  in parallel with the calculation of the syndrome. In  FIG. 3  according to the present embodiment, however, a module which converts the erasure flags e 0 , e 1 , . . . , e 2t−1  into the erasure position data Er 0 , Er 1 , . . . , Er 2t−1  expressing Galois fields is provided as the erasure position data calculator  2 . 
   (ii) In  FIG. 2 , the error position polynomial calculator  33  derives the error position polynomial σ(x) from the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position polynomial Λ(x). In  FIG. 3  according to the present embodiment, however, the error position polynomial calculator  3  derives the error position polynomial σ(x) from the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position data Er 0 , Er 1 , . . . , Er 2t−1 . 
   At first, the erasure position data calculator  2  mentioned in (i) transmits Galois fields expressions of erasure positions (Er 0 , Er 1 , . . . , Er 2t−1 ), which are obtained by the module, to the error position polynomial calculator  3  mentioned in (ii), i.e., a module which executes Berlekamp algorithms modified in this embodiment. 
   In place of calculating the erasure position polynomial, the erasure position data calculator  2  calculates the erasure position data Er 0 , Er 1 , . . . , Er 2t−1  indicative of the erasure positions expressed by Galois fields, from the erasure flags (erasure positions) e 0 , e 1 , . . . , e 2t−1 , to obtain the following expression (6).
 
 Er   i =α e   i   (6)
 
   In this expression, α is a primitive element of a Galois field. Although a lot of operation steps are needed to calculate the erasure position polynomial, the Galois field expression of each erasure position can be calculated through one operation step from one erasure position. Thus, the erasure position data calculator  2  is a simple circuit. 
   The error position polynomial calculator  3  mentioned in foregoing (ii) derives the error position polynomial σ(x) by use of the algorithms shown in  FIGS. 6 to 8  which are modified on the basis of the Berlekamp algorithms, when a syndrome and erasure position data are given as inputs. A circuit configuration which realizes the algorithms is as shown in  FIG. 4 . 
   The configuration shown in  FIG. 4  is described as follows:
     Two counter values (C 1 , C 2 ) updated by the number of processing steps   Buffers controlled by counter values   Galois field multiplier   Galois field multiplier switching circuit   Syndrome selection circuit   

   These components will now be described. 
   &lt;Two Counter Values Updated by the Number of Processing Steps (C 1 , C 2 )&gt; 
   These two counter values C 1  and C 2  do not appear on the circuit shown in  FIG. 4  but are values to control the operation of this circuit. In the algorithms in  FIGS. 6 to 8  which will be described later, the counter values C 1  and C 2  are set as variables j and i. C 1 =j and C 2 =i are given. 
   The two counter values C 1  and C 2  are to perform processings I, II, III, and IV below. C 1 n and C 2 n are registers for holding the counter values.
         I. C 1 n=0 and C 2 n=0   II. C 1 =C 1 n and C 2 =C 2 n   III. If C 1 =C 2 , C 1 n=C 1 +1 and C 2 n=0
           (If C 1 ≠C 2 , C 1 n=C 1  and C 2 n=C 2 +1)   
           IV. Return to II       

   Of I to IV, I is executed when starting the processings, and the operations from II to IV are repeated for every processing step. 
   More specifically, the counter values “C 1  and C 2 ” thus shift to values as described below for every processing step. 
   “C 1 , C 2 ”=“0, 0”→“1, 0”→“1, 1”→“2, 0”→“2, 1”→“2, 2”→“3, 0”→. . . 
   It is to be noted that this is merely an example. Ranges of countable values as the variables j and i are set for the counter values C 1  and C 2  as will be described later with reference to  FIGS. 6 to 8 . 
   &lt;Buffers Controlled by Counter Values&gt; 
   The buffers controlled by counter values are buffers Bf 1  and Bf 2  shown in  FIG. 4   
   The buffers Bf 1  and Bf 2  are each constructed as a shift register having selectors that switch inputs based on the number of processing steps from the start of processings. 
   That is, in the buffer Bf 1 , a shift register is constructed by registers σrg(0) to σrg(2t−1). The registers σrg(0) to σrg(2t−2) are respectively provided with selectors SLσ(0) to SLσ(2t−2) each of which selects and inputs the output of the register in an immediately preceding stage and the operation result inputted to the buffer Bf 1 . 
   Similarly in the buffer Bf 2 , a shift register is constructed by registers λrg(0) to λrg(2t−1). The registers λrg(1) to σrg(2t−2) are respectively provided with selectors SLλ(1) to SLλ(2t−2) each of which selects and inputs the output of the register in an immediately preceding stage and the operation result inputted to the buffer Bf 2 . 
   Also, the buffer Bf 1  is inputted with an operation result σiter from an adder AD 1 . 
   Selectors SEL 0  and SEL 2  are provided in the input stage of the buffer Bf 2 . The selector SEL 0  selects the value σreg from the register σrg( 0 ) in the buffer Bf 1  and the value λreg from the register λrg(0) in the buffer Bf 2 . The selector SEL 2  selects the operation result σiter from the adder AD 1  and the selected value from the selector SEL 0 , and inputs them to the buffer Bf 2  as a value λiter+1. 
   Each of the shift registers (σrg(0) to σrg(2t−1) and λrg(0) to λrg(2t−1)) has to select an input to itself from the register in an immediately preceding stage and the operation results (σiter and λiter+1) inputted to the buffers, according to the counter value C 2 . That is, selection states of the selectors SLσ(0) to SLσ(2t−2) and the selectors SLλ(1) to SLλ(2t−2) are controlled by the counter value C 2 . 
   This kind of configuration can suppress the number of necessary processing steps, compared with the circuit shown in  FIG. 1 . 
   &lt;Galois Field Multiplier&gt; 
   Galois field multipliers ML 1 , ML 2 , and ML 3  are provided. These Galois field multipliers ML 1 , ML 2 , and ML 3  multiply arbitrary two elements of Galois fields. 
   &lt;Galois Field Multiplier Switching Circuit&gt; 
   The circuit system including the Galois field multipliers ML 1 , ML 2 , and ML 3  is constructed as follows. 
   The Galois field multiplier ML 3  multiplies the syndrome S selected by the selector SEL 6  by the operation result σiter of the adder AD 1 , and outputs a multiplication result MUL 3 . The output MUL 3  of the Galois field multiplier ML 3  is supplied to the adder AD 2 . 
   The adder AD 2  adds up the outputs from register rg 6  and the Galois field multiplier ML 3 , and outputs the addition result (δk+1). The output δk+1 from the adder AD 2  is held by the register rg 6 . That is, the register rg 6  then becomes a register which holds the value δk+1. 
   The output δk+1 from the adder AD 2  is supplied to the selector SEL 3 . The selector SEL 3  selects the output δk+1 and the value of the register rg 5 , and inputs them to the register rg 5 . This register rg 5  then becomes a register which holds the value δ. 
   The value δ of the register rg 5  is supplied to the selectors SEL 1  and SEL 4 . 
   The selector SEL 4  selects the value δ and the value Er of an erasure position and supplies them to the Galois field multiplier ML 2 . The Galois field multiplier ML 2  multiplies the value from the selector SEL 4  by the value λreg from the buffer Bf 2 , and supplies the multiplication result MUL 2  to the adder AD 1 . 
   The selector SEL 1  selects the value δ from the register rg 5  and the value γ held by the register rg 7 , and inputs them to the register rg 7 . The register rg 7  then becomes a register which holds the value γ. 
   The value γ of the register rg 7  is supplied to the selector SEL 5 . The selector SEL 5  selects the value γ and the value “1”, and outputs them to the Galois field multiplier ML 1 . 
   The Galois field multiplier ML 1  multiplies the value from the selector SEL 5  by the value σreg from the buffer Bf 1 , and supplies the multiplication result MUL 1  to the adder AD 1 . 
   In this circuit system, switching of inputs and outputs of the Galois field multipliers ML 1 , ML 2 , and ML 3  are carried out by comparing the counter value C 1  with the number Eras_num of data pieces marked with erasure flags. 
   Connections of the three Galois field multipliers ML 1 , ML 2 , and ML 3  are respectively switched as shown in  FIGS. 5A and 5B  by the selectors SEL 5 , SEL 4 , and SEL 6 . 
     FIG. 5A  shows the case where C 1 &lt;Eras_num is the result of comparing the counter value C 1  with the number Eras_num of data pieces marked with erasure flags. 
   The Galois field multiplier ML 1  is inputted with the value “1” and the value σ (σreg) from the buffer Bf 1 , and outputs the multiplication result MUL 1 . 
   The Galois field multiplier ML 2  is inputted with the value Er C1  of the erasure position data based on the counter value C 1  and the λ(λreg) from the buffer Bf 2 , and outputs the multiplication result MUL 2 . 
   The Galois field multiplier ML 3  is inputted with the syndrome S and the operation result (σiter=MUL 1 +MUL 2 ) from the adder AD 1 , and outputs the multiplication result MUL 3 . 
     FIG. 5B  shows the case where C 1 &gt;Eras_num is the result of comparing the counter value C 1  with the number Eras_num of data pieces marked with erasure flags. 
   The Galois field multiplier ML 1  is inputted with the value γ and the value σ(σreg) from the buffer Bf 1 , and outputs the multiplication result MUL 1 . 
   The Galois field multiplier ML 2  is inputted with the value δ and the value λ(λreg) from the buffer Bf 2 , and outputs the multiplication result MUL 2 . 
   The Galois field multiplier ML 3  is inputted with the syndrome S and the operation result (σiter=MUL 1 +MUL 2 ) from the adder AD 1 , and outputs the multiplication result MUL 3 . 
   The Galois field multiplier switching circuit is thus constructed. 
   &lt;Syndrome Selection Circuit&gt; 
   The syndrome selection circuit is constructed by a register rg 8  which holds the inputted syndrome S 0 , S 1 , . . . , S 2t−1 , and a selector SEL 6  which supplies the Galois field multiplier ML 3  with the syndrome S which has selected the value (S 0 , S 1 , . . . , S 2t−1 ) of the register rg 8 . 
   The selector SEL 6  takes as an index a value calculated from the counter values C 2  and C 1 , and outputs any of the syndrome S corresponding to the index. That is, in case where i is given as the index, this selector is a circuit which outputs Si from the syndrome S 0 , S 1 , . . . , S 2t−1 . 
   Hereinafter, the algorithms according to the present embodiment which can be realized by the circuit shown in  FIG. 4  will be described with reference to  FIGS. 6 to 8 . 
   As described with reference to  FIG. 3 , the error position polynomial calculator  3  as the circuit shown in  FIG. 4  is supplied with, as inputs thereto, the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position data Er 0 , Er 1 , . . . , Er 2t−1 . 
   In this case, the algorithms for deriving the error position polynomial σ(x) are as shown in  FIGS. 6 to 8 . 
   As has been described above, Eras_num is given by the erasure position calculation block in a preceding stage and is the number of positions where erasures have occurred. 
   As explained in the foregoing description, t is given by N−K=2t−1 where the code length is N and the transmission data word length is K. 
   σreg is a parameter to store σ, and λreg is a parameter to store λ. σiter and λiter are selected respectively from σ0 to σ2t−1 and from λ0 to λ2t−1, in correspondance with the value of the variable iter indicative of the number of repetitions. 
   In the step F 101  in  FIG. 6 , initialization is carried out. That is, σ0 to σ2t−1 and λ0 to λ2t−1 are all set to “0”. Also it is set that the internal variable L=0 used for processings. Further, σ0=λ0=γ=1 and δ=S 0  are set. More specifically, initialization is thus performed on the registers of the buffers Bf 1  and Bf 2  in  FIG. 4 , and the register rg 5  which holds the value δ, and the register rg 7  which holds the value γ. 
   In the step F 102 , 0 to the number Eras_num of erasure positions are set as the variable j corresponding to the count value C 1 , to define the number of loops of the variable j, i.e., the countable range of the count value C 1 . 
   In the step F 103 , the value of j+1 is set as the variable iter of the number of repetitions, and the value δk+1 in the register rg 6  is set to “0”. 
   In the step F 104 , 0 to the value iter are set as the variable i corresponding to the count value C 2 , to define the number of loops of the variable i, i.e., the countable range of the count value C 2 . 
   In the step F 105 , the value σ0 is set as the value σreg. In addition, the value λ0 is set as the value λreg. 
   Further in the step F 106 , 0 to 2t−1 are set as the variable k, to define the number of loops of the variable k. 
   In the step F 107 , the value λk is changed to the value σk+1, and the value λk is changed to the value λk+1. This is executed until the loop of k ends in the step F 108 . 
   That is, the values of the shift registers in the buffers Bf 1  and Bf 2  are shifted by the number of loops of the value k. 
   In the step F 109 , multiplications are performed by the Galois field multipliers ML 1  and ML 2 , and an addition of the multiplication results MUL 1  and MUL 2  is performed by the adder AD 1 , to obtain the operation result Titer. 
   At this time, C 1 &lt;Eras_num, i.e., the switched state shown in  FIG. 5A  is given because the count value C 1  (=the value of j) has been set by the step F 102 . Therefore, the Galois field multiplier ML 1  performs the multiplication of MUL 1 =1×σreg, and the Galois field multiplier ML 2  the multiplication of MUL 2 =Er j ×λreg. The operation result σiter of the adder AD 1  is accordingly obtained to be σiter=1×σreg+Er j ×λreg. 
   In the step F 110 , the value λiter+1 is changed to the operation result σiter. That is, the value σiter is inputted to the buffer Bf 1  and also inputted to the buffer Bf 2  as the selector SEL 2  selects the σiter. 
   In the step F 111 , a multiplication and an addition are performed respectively by the Galois field multiplier ML 3  and the adder AD 2 , so that the value δk+1 of the register rg 6  is updated. 
   That is, the Galois field multiplier ML 3  multiplies the operation result σiter and the syndrome Sj+1−i selected by the selector SEL 6 , and outputs the multiplication result MUL 3  (=σiter×Sj+1−i). The adder AD 2  adds up the multiplication result MUL 3  and the value δk+1 of the register rg 6 . Further, the addition result (δk+1+σiter×Sj+1−i) is set as the value δk+1 of the register rg 6 . 
   The above processings are executed repeatedly until the loop of the variable i ends. After the end of the loop, the procedure goes from the step F 112  to F 113 , and the value δ is updated to the value δk+1. That is, the selector SEL 3  selects the value δk+1 and updates the value δ of the register rg 5 . 
   After the loop of the variable j ends, the procedure goes from the step F 114  to the step F 115  in  FIG. 7 . 
   In the step F 115 , the number Eras_num of the erasure positions to 2t−1 are set as the variable j corresponding to the count value C 1 , to define the loop processing of the variable j. 
   In the step F 116 , the value of j+1 is set as the variable iter of the number of repetitions, and the value δk+1 of the register rg 6  is set to “0”. 
   In the step F 117 , 0 to the value iter are set as the variable i corresponding to the count value C 2 , to define the loop processing of the variable i. 
   In the step F 118 , the value σ0 is set as the value σreg. In addition, the value λ0 is set as the value λreg. 
   In the step F 119 , 0 to 2t−1 are set as the variable k, to define the loop processing of the variable k. 
   Further in the step F 120 , the value σk is changed to the value σk+1, and the value λk is changed to the value λk+1. This is executed repeatedly until the loop of k ends in the step F 121 . 
   That is, the values of the shift registers in the buffers Bf 1  and Bf 2  are each shifted by the number of loops of the value k. 
   In the step F 122 , multiplications are performed by the Galois field multipliers ML 1  and ML 2 , and an addition of the multiplication results MUL 1  and MUL 2  is performed by the adder AD  1 , to obtain the operation result σiter. 
   At this time, C 1 ≧Eras_num, i.e., the switched state shown in  FIG. 5B  is given because of the count value C 1  (=the value of j) has been set by the step F 115 . Therefore, the Galois field multiplier ML 1  performs the multiplication of MUL 1 =γ×σreg, and the Galois field multiplier ML 2  performs the multiplication of MUL 2 =δ×λreg. The operation result σiter of the adder AD 1  is accordingly obtained to be σiter=γ×σreg+δ×λreg. 
   In the step F 123 , whether δ=0 is satisfied or the control variable L satisfies 2L&gt;j−Eras_num is determined. 
   If any of these conditions is satisfied, the value λiter+1 is changed to the σreg in the step F 124 . 
   In this case, the operation result σiter is inputted to the buffer Bf 1 . In addition, the selectors SEL 0  and SEL 2  select the value σreg of the buffer Bf 1 , so the value σreg is inputted to the buffer Bf 2 . 
   Alternatively, if none of the conditions in the step F 123  is satisfied, the value λiter+1 is set as the value λreg. 
   In this case, the operation result σiter is inputted to the buffer Bf 1 . In addition, the selectors SEL 0  and SEL 2  select the value λreg of the buffer Bf 2 , so that the value λreg is inputted to the buffer Bf 2 . 
   In the step F 126 , a multiplication and an addition are performed respectively by the Galois field multiplier ML 3  and the adder AD 2 , so the value δk+1 of the register rg 6  is updated. 
   That is, the Galois field multiplier ML 3  multiplies the operation result σiter and the syndrome Sj+1−i selected by the selector SEL 6 , and outputs the multiplication result MUL 3  (=σiter×Sj+1−i). The adder AD 2  adds up the multiplication result MUL 3  and the value δk+1 of the register rg 6 . Further, the addition result (δk+1+σiter×Sj+1−i) is set as the value δk+1 of the register rg 6 . 
   The above processings are executed repeatedly until the loop of the variable i ends. After the end of the loop, the procedure goes from the step F 127  to F 128  in  FIG. 8 . Further, whether δ=0 is satisfied or L satisfies 2L&gt;j−Eras_num is determined. 
   If any of these conditions is satisfied, the procedure goes to the step F 130 . 
   If none of the conditions is satisfied, the variable L is set to j−Eras_num+1−L in the step F 129 , and the value γ is updated to the value δ. With respect to the value γ, the selector SEL 1  selects the value δ of the register rg 5 , and updates the register rg 7 . 
   In the step F 130 , the value δ is updated to the value δk+1. That is, the selector SEL 3  selects the value δk+1, and updates the value δ of the register rg 5 . 
   The processings from the step F 116  to step F 131  are executed repeatedly until the loop of the variable j ends. After the end of the loop, the procedure goes to the step F 132 . At this time point, σ0 to σ2t−1 are outputted as the values held by the shift registers σrg(0) to σrg(2t−1), as the buffer Bf 1 , and then the processing flow is terminated. 
   Through the processings described above, the error position polynomial σ(x) is outputted from the error position polynomial calculator  3 . 
   That is, according to the present embodiment, the error position polynomial σ(x) is calculated on the basis of the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position data Er 0 , Er 1 , . . . , Er 2t−1  in case where erasure corrections are supported. In contrast, conventionally, the error position polynomial σ(x) is calculated on the basis of the syndrome S 0 , S 1 , . . . , S 2t−1  and the erasure position polynomial Λ(x) in the same case. 
   In addition, switching of the connection between the buffers Bf 1  and Bf 2  holding uncompleted results of operations, and the operator (Galois field multipliers ML 1 , ML 2 , and ML 3 ) is controlled based on the number (Eras_num) of erased received words and the number (the count value C 1 ) of processing steps, so that derivations of both the erasure position polynomial and the error position polynomial from the erasure position data can be realized by only the circuit shown in  FIG. 4 . 
   According to this method, it is possible to construct a decoder capable of erasure corrections by making less changes to the calculation circuits based on the Berlekamp-Massey algorithms. 
   Expansion of the circuit scale can be reduced to the minimum without involving increase in number of Galois field multipliers. 
   In addition, the processings can be realized by a least necessary number of fixed steps regardless of the number of erased words among received code words, so that decoding delays can be reduced to the minimum. 
   The decoder according to the present invention has the configuration shown in  FIG. 3  and using the error position polynomial calculator  3  which obtains the error position polynomial σ(x) by the algorithms shown in  FIGS. 6 to 8  in the circuit configuration shown in  FIG. 4 . 
   An error position polynomial calculation method or program according to the present invention is, for example, a calculation method using the algorithms shown in  FIGS. 6 to 8  or a program to execute the calculation method. 
   That is, the embodiment described above corresponds to the decoder, error position polynomial calculation method, and program according to the present invention. The present invention, however, is not limited to this embodiment but various modifications can be considered within the scope of the subject matter of the invention. 
   The program according to the present invention may be temporarily or permanently stored (recorded) in a ROM, non-volatile memory, or RAM in an electronic device (e.g., a disc drive device, tape recording/reproducing device, communication device, or the like) including a decoder. Alternatively, the program may be temporarily or permanently stored (recorded) in a removable recording medium such as a flexible disc, CD-ROM (Compact Disc Read Only Memory), MO (Magnet Optical) disc, DVD (Digital Versatile Disc), magnetic disc, semiconductor memory, or the like. This kind of removable recording medium can be supplied in form of a so-called software package, and can be used for designing/manufacturing electronic devices such as a disc drive device mentioned above. 
   Note that the program can be not only installed from a removable recording medium as described above but also downloaded from a server or the like which stores the program by a network such as the Internet via a LAN (Local Area Network).