Patent Publication Number: US-11658819-B2

Title: Method for generating public key and secret key based on module-wavy and module-LWR and method of encryption and decryption using the keys

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of International Application No. PCT/KR2018/016014, filed on Dec. 17, 2018, which claims priority to Korean Application No. 10-2017-0183661, filed on Dec. 29, 2017. Both applications are incorporated herein by reference in their entirety. 
    
    
     TECHNICAL FILED 
     The present disclosure relates to a lattice-based public key cryptographic method. More specifically, the present disclosure relates to a method for generating a public key and a secret key based on Module-Wavy and Module-LWR, an encryption/decryption method using the keys. 
     BACKGROUND 
     Encryption methods are generally divided into a symmetric key encryption and an asymmetric key encryption. In the symmetric key encryption, the same key is used for encryption and decryption, thereby providing fast encryption and decryption. However, the security can be severely attacked when the key is stolen by a third party. In order to solve the problem, an asymmetric key encryption has been introduced. The asymmetric key cryptographic method uses a public key which is disclosed and a secret key (private key) which is provided only to a user. A plain text is encrypted by a public key and the encrypted message is decrypted by a secret key. Among the public key encryption schemes, RSA algorithm has been widely used. However, it is expected that RSA encryption can be broken by a quantum computer. Thus, more powerful encryption scheme is needed. 
     Recently, lattice-based public key cryptography called “Kyber” has been introduced. The Kyber scheme is shown in “Bos, J., Ducas, L., Kiltz, E., Lepoint, T., Lyubashevsky, V., Schanck, J. M., Schwabe, P., Stehl&#39;e, D.: CRYSTALS—kyber: a CCA-secure module lattice-based KEM. Cryptology ePrint Archive, Report 2017/634 (2017)” and website of http://eprint.iacr.org/2017/634. However, the size of the encrypted message is large since the encrypted message consists of two components and the speed is low compared to the conventional scheme such as “NTRU.” 
     SUMMARY 
     The object of the present disclosure is to provide a lattice-based public key cryptographic method wherein the size of an encrypted message, communication load and communication traffic are reduced compared with the conventional arts. 
     The computer-implemented method for generating a public key and a secret key of the present disclosure comprises determining, by a processor, the secret key (s) which is a vector of polynomials of degree (n−1), the coefficients of which are −1, 0, or +; determining, by a processor, a first error vector (e) by sampling from (D αq   n ) d  and a second error value (e′) by sampling from D αq   n ; choosing, by a processor, a randomly uniform matrix A∈R q   d×d  which satisfies A·s=e (mod q); choosing, by a processor, a random column vector b∈R q   d  which satisfies 
                 〈     b   ,   s     〉     =       ⌊     q   2     ⌋     +       e   ′     ⁡     (     mod   ⁢           ⁢   q     )           ;         
and determining, by a processor, the public key (pk) by (A∥b)∈R q   d×(d+1) .
 
     The secret key (s) can be sampled from  WT n (h s ) d . 
     The computer-implemented method of encrypting a message using the public key of the present disclosure comprises receiving, by a processor, the public key (pk) and a message (m∈R 2 ); randomly selecting, by a processor, d polynomials of degree (n−1), the coefficients of which are −1, 0, or +1; generating, by a processor, a first value by operating the polynomials and at least a portion of the public key (pk); generating, by a processor, a second value by encoding the message with at least a portion of the public key (pk); generating, by a processor, a third value by operating the first value and the second value; and generating a ciphertext by rounding operation to the third value for removing pre-set lower bits. 
     In an embodiment of the present disclosure, a column vector (r) of the polynomials is determined by sampling over  WT n (h r ) d ; the first value is determined by A T ·r; the second value is determined by m·b; the third value is determined by A T ·r+m·b; and then the ciphertext (c) is generated by 
     
       
         
           
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     The computer-implemented method of decrypting the ciphertext of the present disclosure comprises receiving, by a processor, a ciphertext c; and decrypting, by a processor, the ciphertext c to obtain the message (m). The message (m) is obtained by the decryption process of 
     
       
         
           
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       BRIEF DESCRIPTION OF DRAWINGS 
       The present disclosure will be more fully understood from the following detailed description taken in conjunction with the accompanying drawings. 
         FIG.  1    is one embodiment of an example diagrammatic view of a device architecture which carries out the present disclosure. 
         FIG.  2    is a flow chart of the process which generates a public key and a secret key according to the present disclosure. 
     
    
    
     It should be understood that the above-referenced drawings are not necessarily to scale, presenting a somewhat simplified representation of various preferred features illustrative of the basic principles of the disclosure. The specific design features of the present disclosure will be determined in part by the particular intended application and use environment. 
     DETAILED DESCRIPTION 
     Hereinafter, the present disclosure will be described in detail with reference to the accompanying drawings. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present disclosure. Further, throughout the specification, like reference numerals refer to like elements. 
     In this specification, the order of each step should be understood in a non-limited manner unless a preceding step must be performed logically and temporally before a following step. That is, except for the exceptional cases as described above, although a process described as a following step is preceded by a process described as a preceding step, it does not affect the nature of the present disclosure, and the scope of rights should be defined regardless of the order of the steps. In addition, in this specification, “A or B” is defined not only as selectively referring to either A or B, but also as including both A and B. In addition, in this specification, the term “comprise” has a meaning of further including other components in addition to the components listed. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. The term “coupled” denotes a physical relationship between two components whereby the components are either directly connected to one another or indirectly connected via one or more intermediary components. Unless specifically stated or obvious from context, as used herein, the term “about” is understood as within a range of normal tolerance in the art, for example within 2 standard deviations of the mean. “About” can be understood as within 10%, 9%, 8%, 7%, 6%, 5%, 4%, 3%, 2%, 1%, 0.5%, 0.1%, 0.05%, or 0.01% of the stated value. Unless otherwise clear from the context, all numerical values provided herein are modified by the term “about.” 
     The method according to the present disclosure can be carried out by an electronic arithmetic device such as a computer, tablet, mobile phone, portable computing device, stationary computing device, etc. Additionally, it is understood that one or more various methods, or aspects thereof, may be executed by at least one processor. The processor may be implemented on a computer, tablet, mobile device, portable computing device, etc. A memory configured to store program instructions may also be implemented in the device(s), in which case the processor is specifically programmed to execute the stored program instructions to perform one or more processes, which are described further below. Moreover, it is understood that the below information, methods, etc. may be executed by a computer, tablet, mobile device, portable computing device, etc. including the processor, in conjunction with one or more additional components, as described in detail below. Furthermore, control logic may be embodied as non-transitory computer readable media on a computer readable medium containing executable program instructions executed by a processor, controller/control unit or the like. Examples of the computer readable mediums include, but are not limited to, ROM, RAM, compact disc (CD)-ROMs, magnetic tapes, floppy disks, flash drives, smart cards and optical data storage devices. The computer readable recording medium can also be distributed in network coupled computer systems so that the computer readable media is stored and executed in a distributed fashion, e.g., by a telematics server or a Controller Area Network (CAN). 
     A variety of devices can be used herein.  FIG.  1    illustrates an example diagrammatic view of an exemplary device architecture according to embodiments of the present disclosure. As shown in  FIG.  1   , a device  109  may contain multiple components, including, but not limited to, a processor (e.g., central processing unit (CPU)  110 , a memory  120 , a wired or wireless communication unit  130 , one or more input units  140 , and one or more output units  150 . It should be noted that the architecture depicted in  FIG.  1    is simplified and provided merely for demonstration purposes. The architecture of the device  109  can be modified in any suitable manner as would be understood by a person having ordinary skill in the art, in accordance with the present claims. Moreover, the components of the device  109  themselves may be modified in any suitable manner as would be understood by a person having ordinary skill in the art, in accordance with the present claims. Therefore, the device architecture depicted in  FIG.  1    should be treated as exemplary only and should not be treated as limiting the scope of the present disclosure. 
     The processor  110  is capable of controlling operation of the device  109 . More specifically, the processor  110  may be operable to control and interact with multiple components installed in the device  109 , as shown in  FIG.  1   . For instance, the memory  120  can store program instructions that are executable by the processor  110  and data. The process described herein may be stored in the form of program instructions in the memory  120  for execution by the processor  110 . The communication unit  130  can allow the device  109  to transmit data to and receive data from one or more external devices via a communication network. The input unit  140  can enable the device  109  to receive input of various types, such as audio/visual input, user input, data input, and the like. To this end, the input unit  140  may be composed of multiple input devices for accepting input of various types, including, for instance, one or more cameras  142  (i.e., an “image acquisition unit”), touch panel  144 , microphone (not shown), sensors  146 , keyboards, mice, one or more buttons or switches (not shown), and so forth. The term “image acquisition unit,” as used herein, may refer to the camera  142 , but is not limited thereto. The input devices included in the input  140  may be manipulated by a user. The output unit  150  can display information on the display screen  152  for a user to view. The display screen  152  can also be configured to accept one or more inputs, such as a user tapping or pressing the screen  152 , through a variety of mechanisms known in the art. The output unit  150  may further include a light source  154 . The device  109  is illustrated as a single component, but the device may also be composed of multiple, separate components that are connected together and interact with each other during use. 
     The device  109  can thus be programmed in a manner allowing it to carry out the steps and/or processes of the present disclosure. 
     Generally, bold lowercase letter(s) means a column vector and bold uppercase letters(s) means a matrix in this specification. 
     Notations 
     n: a power of 2 
     d: a positive integer 
     q: a positive integer; a large modulus 
     p: a positive integer less than q; a rounding modulus 
               ℤ   q     =       (       -     q   2       ,     q   2       ]     ⋂   ℤ           
which means set of integers, where
 
                   -     q   2       &lt;     the   ⁢         integer     ≤     q   2       )     ;     ℤ   t           
is defined by the same way.
 
     
       
         
           
             
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     (f(x)): ideal of    q [x] which is generated by f(x) 
     f(x): polynomial of degree n (for example, a cyclotomic polynomial when n=Φ(N)) 
     R (ring): set of polynomials of degree (n−1), the coefficients of which are integers 
     Operation over R: calculation of remainder after dividing the results of operation for every polynomial by f(x) 
     R q  (ring): set of polynomials of degree (n−1), the coefficients of which are elements of    q    
     Operation over R q : every polynomial is operated; the results of the operation is divided by f(x); and then q is added to or is subtracted from each coefficient such that all coefficients are included in    q    
     R t  (ring): set of polynomials of degree (n−1), the coefficients of which is elements of    t    
     Operation over R t : every polynomial is calculated; the results of the calculation is divided by f(x); and then t is added to or is subtracted from each coefficient such that all coefficients are included in    t    
     [r]: the nearest integer to real number r, rounding upwards in case of a tie 
     For two matrices A and B having the same number of rows, (A∥B) denotes their concatenation, i.e., for A∈   m×n     1    and B∈   m×n     2   , the m×(n 1 +n 2 ) matrix C=(A∥B) is defined as 
     
       
         
           
             
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     x←D: sampling x according to the distribution D. It denotes the uniform sampling when D is a finite set. 
     D σ : a discrete Gaussian distribution; a probability distribution with support   that assigns a probability proportional to 
             exp   ⁡   (     -       π   ⁢     x   2         σ   2         )         
to each x∈ . The variance of D σ  is very close to σ 2 /2π unless σ is very small.
 
     For an integer 0≤h≤n, the distribution  WT n (h) samples a vector from {−1, 0, 1} n , under the condition that it has h nonzero elements. This sampled vector a=(a 0 , a 1 , . . . , a n-1 ) is identified to a polynomial a(x)=Σ i=0   n-1 a i ·x i  of degree (n−1). 
     For an integer n≥1, D n  denotes the product of independent and identically distributed random variables which are according to Distribution D. 
     Module-LWR problems are disclosed in Alperin-Sheriff, Jacob, and Daniel Apon. “Dimension-Preserving Reductions from LWE to LWR.” (IACR Cryptology ePrint Archive report 2016/589. (2016). http://eprint.iacr.org/2016/589). 
     For positive integers n, d, q, p (p&lt;q), let s∈R d  be a secret polynomial vector. A n,d,q,p   MLWR (s) is the distribution of 
                 (     a   ,         ⌊       p   q     ⁢       〈     a   ,   s     〉     q       ⌉       )     ∈       R   q   d     ×     R   p         ,         
where a←R q   d . The Module-LWR problem MLWR n,q,q,p (D) is to distinguish between A n,d,q,p   MLWR (s) and the uniform distribution over R q   d ×R p  where s←D.
 
     For a secret polynomial s∈R d , we first choose an error polynomial e←D αq   n , and uniform randomly choose a←R q   d  satisfying  a, s   q =e in R q . Denote the distribution a by A n,d,q,α   MWavy (s). The Module-Wavy problem MWavy n,d,q,α (D) is to distinguish A n,d,q,α   MWavy (s) and the uniform distribution over R q   d  where s←D. 
     The method for generating the public key and the secret key according to the present disclosure will be described hereinafter. 
     A security parameter is determined and then the positive integers n, h s , h r , p, q are chosen based on the determined security parameter, where h s  and h r  are less than n. Further, fix an error parameter α with 0&lt;α&lt;1. The security parameter λ is a measure of the security of an encryption scheme. For example, the security parameter λ is set to “128.” 
     In the step S 100 , a polynomial column vector s is sampled by s← WT n (h s ) d . The polynomial of the column vectors has coefficients of “0,” “+1,” or “−1.” The polynomial can be determined as a secret key as described in the below. 
     In the step S 110 , the first error vector (e) and a second error value (e′) are sampled as follows:
 
 e ←( D   αq   n ) d  
 
 e′←D   αq   n  
 
     In the step S 120 , the matrix A∈R q   d×d  satisfying A·s=e(mod q) uniformly at random is chosen. 
     In the step S 130 , the random column vector b∈R q   d  satisfying 
               〈     b   ,   s     〉     =       ⌊     q   2     ⌋     +       e   ′     (     mod   ⁢        q     )             
is chosen.
 
             ⌊     q   2     ⌋         
means the round down of
 
     
       
         
           
             
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     In the step S 140 , the public key and the secret key of the present disclosure can be determined as follows:
 
Public key( pk )=( A∥b )∈ R   q   d×(d+1)  
 
Secret key( sk )= s  
 
     The encryption and decryption methods of the present disclosure will be described in the below. 
     A message m∈R 2  is received by a user having a public key. The message m can be represented by polynomial of degree n, the coefficients of which are elements of    2 . 
     A polynomial column vector r, the coefficient of which is 0, −1, or +1 is sampled as follows:
 
 r←     WT   n ( h   r ) d  
 
       WT n (h s ) d  and  WT n (h r ) d  means to randomly sample d polynomials of degree (n−1), the coefficient of which is −1, 0, or +1, from  WT n (h s ) and  WT n (h r ), respectively. 
     A first value is generated by operating the aforementioned polynomials and at least a portion of the public key; a second value is generated by encoding the message with at least a portion of the public key; and then a third value is generated by operating the first value and the second value. 
     The first value can be generated by the operation of A T ·r. The second value can be generated by the operation of m·b. The third value can be generated by the operation of A T ·r+m·b. The ciphertext is generated by rounding operation to the third value so as to remove pre-set lower bits. 
     The ciphertext c can be generated as follows: 
     
       
         
           
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     R p   d  means a ring, the elements of which are tuples of d polynomials of degree (n−1). The coefficients of the polynomial are the elements of    p . 
     The size of the ciphertext c of the present disclosure is significantly reduced since the ciphertext has one component unlike the conventional Kyber scheme and p&lt;q. Thus, the encryption process is faster and communication traffic is significantly reduced compared to the conventional lattice-based public key cryptography. 
     The ciphertext c can be decrypted as follows such that the message is obtained. 
     
       
         
           
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     Although the present disclosure has been described with reference to accompanying drawings, the scope of the present disclosure is determined by the claims described below and should not be interpreted as being restricted by the embodiments and/or drawings described above. It should be clearly understood that improvements, changes and modifications of the present disclosure disclosed in the claims and apparent to those skilled in the art also fall within the scope of the present disclosure. Accordingly, this description is to be taken only by way of example and not to otherwise limit the scope of the embodiments herein.