Patent Publication Number: US-5892712-A

Title: Semiconductor non-volatile latch device including embedded non-volatile elements

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority from copending provisional patent application Ser. No. 60/016,664 filed May 1, 1996. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to bistable non-volatile semiconductor latches, and, more particularly, to a flip-flop circuit which includes electrically erasable, electrically programmable memory elements for setting and storing the configuration of programmable semiconductor circuitry. 
     2. Description of the Related Art 
     There is a strong need to remember the state of conditions entered or derived in semiconductor devices whenever the devices are on. These states must reliably configure the devices to act in one way or another. Examples of devices needing different configurations with the same basic device are EPLD&#39;s (Electrically Programmable Logic Devices), FPGA&#39;s (Field Programmable Gate Arrays) and memory devices that require repairing defective rows or columns of memory cells with spare or redundant rows or columns of memory cells. 
     Since these devices and systems have no prior knowledge of the desired conditions, non-volatile memory would be needed to store the state of conditions when the devices are turned off. When the devices are turned back on, the state of conditions are restored for proper device operation. 
     An array of non-volatile memory cells is a way of storing the desired conditions, but because the structure of an array of memory cells requires additional circuitry to function, simultaneous access of all states in the array is not practical. Sometimes in the EPLD case, an array of non-volatile memory cells on or off chip is used, and during device and system power up, the entire content of the array is downloaded into state latches on the device which store and configure the device while it is on. The problem with this scheme is off chip it requires more system board space and algorithms for downloading the data, and on chip it requires a memory array with its associated overhead circuitry. Both methods require algorithms for downloading the data into state latches on chip. 
     For memory devices, the above scheme does not work since on power up, the memory device needs to start working right away without downloading from a non-volatile memory. Usually, memory devices incorporate fuse links to configure redundant elements and are an efficient way to implement redundancy on a memory device, but this method requires large development and production cost. 
     A better approach would be integrate a non-volatile latch into the configuration logic of these circuits; however, almost all manufacturable non-volatile memory elements available today require voltages during the erase and write operations that greatly exceed the typical operating voltage range of logic circuitry. In order to accommodate these higher voltages, special high voltage devices and structures must be fabricated in an integrated fashion with the standard logic devices. The additional manufacturing steps required to integrate the high voltage devices adds non-productive manufacturing costs to the logic and increases logic production yield losses. Oftentimes, these two factors increase the cost of the logic well beyond what customers would be willing to accept. 
     It is therefore desirable to integrate non-volatile memory elements in a novel manner that would eliminate the need for voltages significantly higher that the typical operation voltage range of the logic circuitry. 
     Therefore, what is needed is a method and apparatus for providing instantaneous logic configuration upon power up when data latch devices are used to configure the state of the logic without incorporating large numbers of extra devices and manufacturing steps. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a semiconductor non-volatile latch which provides non-volatile data storage for logic configurability. 
     Another object of the invention is to provide a a semiconductor non-volatile latch in which the erase operation is carried out while using a lower voltage. 
     It is another object of the invention to provide a semiconductor non-volatile latch in which the write operation is carried out while using a lower voltage. 
     It is still another object of the invention to provide a semiconductor non-volatile latch having an output that can be configured upon power up. 
     Another object of the invention is to provide a semiconductor non-volatile latch which provides full rail CMOS output levels independent of the state of the latch. 
     It is a further object of the invention to provide a semiconductor non-volatile latch which achieves its operation with a minimum number of additional devices over a standard cross-coupled CMOS inverter latch. 
     It is yet another object of the invention to provide a semiconductor non-volatile latch which consumes very little power during operation. 
     Yet another object of the invention is to provide a semiconductor non-volatile latch which eliminates data disturbs of the non-volatile elements during normal operation. 
     It is still further another object of the invention to provide a semiconductor non-volatile latch which can be produced at lower costs by reliably utilizing a dielectric charge storage. 
     Yet a further object of the invention is to provide a semiconductor non-volatile latch which can withstand substantial amounts of noise input while the latch is being set upon power up or during a reset operation. 
     Still another object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be erased by the application of a negative potential to the gate of the non-volatile elements with respect to the body of the non-volatile elements. 
     Still yet another object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be programmed by the application of a positive potential to the gate of the non-volatile elements with respect to the body of the non-volatile elements while the logical low levels of the latch are taken to a negative potential. 
     An additional object of the invention is to provide a semiconductor non-volatile latch whose non-volatile elements can be erased and programmed by using a single negative voltage source in addition to the power supply voltage. 
     Thus, according to the invention, there is provided a non-volatile latch, which comprises typically a CMOS latch. The CMOS latch has two CMOS inverters with the output of each CMOS inverter connected, directly or indirectly to the input of the other. Each CMOS inverter has a p-channel IGFET transistor and an n-channel IGFET transistor. The source of the p-channel transistor is connected to a logic high potential and the source and bulk of the n-channel transistor is connected to a controllable signal, S rc , the value of which can be set within the range of Vcc to -V pp , where V cc  is the supply potential and -V pp  is a negative potential with respect to the supply reference. The gates of each transistor are connected together to form the CMOS inverter input, and the drains of each transistor are connected together to form the CMOS inverter output. 
     In addition to the CMOS latch, the non-volatile latch has two non-volatile elements, each non-volatile element having at least an n-channel non-volatile memory transistor, each including a source node, a drain node, a gate node, a bulk region, a channel region between the source and drain nodes and lying beneath the gate region, and a charge storage layer residing between, and insulated from, the channel region and the gate region. The gates of the two non-volatile memory transistors are tied together and further to a control gate voltage generator. The bulk of the two non-volatile memory transistors are typically connected together to the controlled signal S rc . Either the source or the drain of each of the two non-volatile memory transistors is tied uniquely to one of the drains of the transistors within the CMOS inverters of the CMOS latch. 
     The remaining non-volatile memory transistor source or drain node is connected to any number or other nodes to form either a static or dynamic current path to the CMOS drains. The current path through the non-volatile elements serves to provide a differential current to the CMOS inverter p-channel drains, especially during the set or reset period when the non-volatile latch output is being set. 
     The differential current is established by setting the states of the two non-volatile memory transistors to opposite logic conditions, represented by an erased condition or a programmed condition, prior to setting the output of the non-volatile latch. 
    
    
     The above and further objects, features and advantages of the invention will become apparent from the detailed description of the preferred embodiments presented hereinafter, when read in conjunction with the accompanying drawings and appended claims. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     In the detailed description of preferred embodiments of the invention presented below, reference is made to the accompanying drawings of which: 
     FIG. 1 shows a schematic representation of a non-volatile latch according to a preferred embodiment of the invention in which the n-channel non-volatile elements form the cross coupling path in the CMOS latch. 
     FIG. 2 illustrates the development of voltage signals V cc , C g , G1 and G2 in accordance with properly setting the output of the non-volatile latch circuit shown schematically in FIG. 1. 
     FIG. 3 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the n-channel non-volatile elements are placed between the drains of the n-channel and p-channel transistors the CMOS inverters and the non-volatile latch input and output nodes are tied to the drain of the n-channel inverter transistors. 
     FIG. 4 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the n-channel non-volatile elements are placed between the drains of the n-channel and p-channel transistors the CMOS inverters and the non-volatile latch input and output nodes are tied to the drain of the p-channel transistors. 
     FIG. 5 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the sources of the n-channel non-volatile elements are selectively connected to or isolated from the power supply reference potential by n-channel transistors. 
     FIG. 6 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the drains of the n-channel non-volatile elements are selectively connected to or isolated from the supply potential by p-channel transistors. 
     FIG. 7 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the sources of the n-channel non-volatile elements are isolated from data input lines by n-channel transistors. 
     FIG. 8 illustrates the development of voltages on nodes V cc , I so  /, Out, and Out/ in accordance with properly setting the output of the non-volatile latch circuit shown schematically in FIG. 7. 
     FIG. 9 shows a representative physical layout of non-volatile latch circuit shown schematically in FIG. 7. 
     FIG. 10 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the sources of the n-channel non-volatile elements are selectively connected to or isolated from a signal S rc  by n-channel transistors, and p-channel input/output devices are provided to the latch. 
     FIG. 11 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which two separate configuration states are supported by two pairs of non-volatile elements, and the sources of all four n-channel non-volatile elements are selectively connected to or isolated from a signal S rc  by n-channel transistors, and p-channel input/output devices are provided to the latch. 
     FIG. 12 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the n-channel transistors of the CMOS inverters are replaced by n-channel non-volatile devices. 
     FIG. 13 shows a schematic representation of a non-volatile latch according to another preferred embodiment of the invention in which the pull-up load devices in the latch comprise high impedance devices rather than p-channel transistors. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The method described herein incorporates non-volatile elements within state latches to form non-volatile latches (herein nv-latches) that power up in the correct state dependent on the states stored in the non-volatile elements. Using nv-latches has the benefits of no complicated download algorithms, no system board space utilization, little on chip area utilization, and no costly fuse-link program. Non-volatile latches are unlike nvsram cells in which data written into the SRAM part of nvsram cells are independent of what is stored in the non-volatile elements of nvsram cells. Only when necessary is data stored in non-volatile elements of nvsram cells recalled into the SRAM portion of the nvsram cells. 
     In contrast, the latch of the nv-latch of the invention always holds or mirrors the data stored in the non-volatile element and is never written to during the entire on-time of the nv-latch. (If different data is written into the nv-latch than what is stored, then the configuration of the device that the nv-latch is configuring will change immediately with potentially catastrophic effects. Also the different data written could put the nv-latch into an unstable condition with unwanted high operating currents one of the outcomes.) 
     The placement of non-volatile elements within latches to form nv-latches accomplishes certain criteria for operation. First, the non-volatile elements cause the nv-latch to power up in the desired state; second, preferably zero power is consumed by the nv-latch during normal operation; third, the outputs are at CMOS levels for use by subsequent standard logic circuits; fourth, the states stored in the nv-latches do not disturb the data stored in the non-volatile elements; and fifth, the non-volatile elements are configured within the nv-latch in as efficient manner as possible so that a minimum of devices are used to form the nv-latch and that the operation is as simple as possible. 
     FIG. 1 shows an nv-latch that uses two non-volatile elements NV1 13&#39; and NV2 13 within the gate leads of cross coupled inverters Inv1 14 and Inv2 14&#39;. Inverters 14 and 14&#39; include p-channel transistors 10 and 10&#39;, respectively, and n-channel transistors 11 and 11&#39;, respectively. The drains of transistors 10 and 11 are connected together and to output node 104 to supply signal Out, and likewise the drains of transistors 10&#39; and 11&#39; are connected together and to output node 104&#39; to supply signal Out/. 
     The gates of transistors 10 and 11 are connected together and likewise the gates of transistors 10&#39; and 11&#39; are connected together. The source nodes of p-channel transistors 10 and 10&#39; are tied to node 100 where the power supply level V cc  is provided. The source and body nodes of n-channel transistors 11 and 11&#39; along with the body of non-volatile devices 13 and 13&#39; are connected to node 101 which supplies signal S rc . The drain node 104 of inverter 14 is connected to a first one of two source/drain nodes of transistor 13 and the drain node 104&#39; of inverter 14&#39; is connected to a first one of two source/drain nodes of non-volatile device 13&#39;. The gate node 106 of inverter 14 is connected to a second one of two source/drain nodes of transistor 13&#39; and the gate node 106&#39; of inverter 14&#39; is connected to a second one of two source/drain nodes of non-volatile device 13. The gates of non-volatile devices 13 and 13&#39; are connected together through nodes 105 and 105&#39;, respectively, to signal C g . 
     An n-channel input selection transistor N1 12 is provided to connect an input signal In supplied to an input node 103 that is connected to the drain of transistor 12. The source of input selection transistor 12 is connected to node 104 of the latch. A select signal Sel is provided to node 102 which is connected to the gate of transistor 12 to connect the input signal on node 103 to the latch node 104. No nodes within non-volatile latch 1 are connected to the power supply reference potential. 
     In operation, on power up, the gates of the non-volatile elements (C g  connected to nodes 105 and 105&#39;) rise, but delayed from the power supply V cc  100, and couple the proper nodes of the nv-latch high. The non-volatile elements have been programmed such that there is a difference in thresholds between the two devices 13 and 13&#39;. The non-volatile element with the more negative threshold will start to couple high the input of one inverter and the output node of the second inverter before the other non-volatile elements turns on, and starts to couple the other side of the nv-latch high. The slew of the power supply potential at node 100 thus creates a differential signal at the outputs 104 and 104&#39; of the nv-latch 1 because of the difference in the turn-on of the two non-volatile elements 13 and 13&#39;. When there is enough differential signal coupled into the nv-latch and the power supply voltage at node 100 is higher than the larger of p-channel and n-channel thresholds, the active p-channel and n-channel devices will self amplify the differential signal to CMOS levels. 
     Since the basic configuration of the nv-latch is that of two cross coupled inverters 14 and 14&#39;, when the outputs 104 and 104&#39; are at CMOS levels, the power consumed goes to zero if the voltage transferred to the gates G1 106 and G2 106&#39; of the two inverters 14 and 14&#39; are substantially also at CMOS levels. This will happen if the non-volatile elements 13 and 13&#39; transfers the CMOS levels, but this is hard to do since the non-volatile elements 13 and 13&#39; are configured as source followers. However, if one of the non-volatile elements 13 and 13&#39; always has a positive threshold and the other always has a negative threshold, and the inverter gate that needs to go high is connected to the negative threshold device while the inverter gate that needs to go low is connected to the positive threshold device, CMOS levels can be attained at the gates 106 and 106&#39; of the Atwo inverters 14 and 14&#39; when the control gate signal (C g  connected to nodes 105 and 105&#39;) is ramped positively to V cc . 
     Thus, according to the invention, the non-volatile latch outputs can present full CMOS rail levels of either V cc  or the supply reference potential that properly reflect the information previously stored in the non-volatile elements while consuming very little or no current. 
     Referring now to FIG. 3, as signal 15 C g  connected to nodes 105 and 105&#39; ramps positively, the non-volatile element with the negative threshold, for example, NV1 13&#39;, couples the gate G1 106 of INV1 14 and the output 104&#39; of INV2 14&#39; (Out/) high as shown in signal 17. Thereafter, device NV2 13 with the positive threshold will turn on and also start to couple gate G2 106&#39; of INV2 14&#39; and the output 104 of INV1 14 (Out) high as shown in signal 18. 
     The differential voltage that is created can then be amplified when the power supply potential 16 supplied to node 100 is greater than the highest p-channel or n-channel threshold, and when the voltage at G1 106 is higher (referenced from ground) than the n-channel 11 threshold of Inv1 14 or the voltage at G2 106&#39; is lower (referenced from he power supply 16) than the p-channel 10&#39; threshold of Inv2 14&#39;, which drives the outputs signals on 104 (Out) and 104&#39; (Out/) in opposite directions. The voltage waveforms of the power supply (V cc ) 16, C g  15, G1 17 and G2 18 are plotted against time as illustrated in FIG. 2. 
     Thus, the desired state of the latch output can be readily established upon applying power to the non-volatile latch circuit according to the current invention. 
     To program the non-volatile elements of the nv-latch shown in FIG. 1 a sequence of steps need be performed. First, the non-volatile elements 13 and 13&#39; are erased to negative thresholds. Second, data is written into the nv-latch 1. Third, the non-volatile elements 13 and 13&#39; are programmed using the data written into the nv-latch 1. 
     Though not shown in FIG. 1, NV1 13&#39; and NV2 13 are n-channel devices and are in the same p-well node 101 as the n-channel 11 and 11&#39; devices of INV1 14 and INV2 14&#39;. Also, input device N1 12 is shown to be an n-channel device with the same p-well, but device N1 12 does not necessarily need to be a single n-channel device. The input means can be two devices, one connected to 104 and the other connected to 104&#39;, and can be n-channel, p-channel or other device types. 
     In the erase phase, control gates 105 and 105&#39;, connected to signal C g , of both NV1 13&#39; and NV2 13 are brought to a negative potential, -V pp  and the p-well potential on node 101 at the same time is brought to the positive power supply voltage through source connection signal S rc . This bias condition tunnels holes from the accumulated p-well surface into the storage area, and after some time (typically milliseconds) changes both thresholds to a negative value. Since the thresholds of both NV1 13&#39; and NV2 13 are negative and signal C g  is returned to the positive power supply after erasing, the nv-latch 1 can act as a normal CMOS type cross-coupled latch and the desire data state is written into the latch at this point through device N1 12 when signal Sel supplied to node 102 is high. It is important that the time lag between erasing and writing the desired data is as short as possible, since after erasure, the data state that exists within the nv-latch 1 is unknown and could degrade the erase state of NV1 13&#39; or NV2 13. 
     Thus, the non-volatile elements according to the invention can be erased by establishing a voltage across the non-volatile elements by using voltages of lower magnitude than that used by conventional approaches. More specifically, according to the invention a voltage of V cc  is placed on the p-well while -V pp  is placed on the gate, rather than placing a negative potential of -V pp  -V cc  on the gate while the p-well and source nodes of the n-channel transistors in the latch are held at ground. 
     To program the data just written into the nv-latch 1, the control gates 105 and 105&#39;, connected to signal C g , of NV1 13&#39; and NV2 13 is at the positive power supply while signal S rc  is brought to a negative potential. With S rc  at a negative potential, the low data state in the nv-latch 1 is also at a negative potential due to the action of the latch. If a low from signal In on node 103 has been previously written into the latch, node 104&#39; Out/ is high and 104 Out is at the negative potential. 
     Since signal C g  connected to nodes 105 and 105&#39; is high and signal Out/ on node 104&#39; is high, non-volatile element NV1 13&#39; is inhibited from being programmed and its negative threshold is preserved, but since signal Out on node 104 is at the negative potential, non-volatile element NV2 13 is programmed and its negative threshold is changed to a positive one. After a short period of time (typically milliseconds), signal S rc  is returned to the ground potential and the voltage at 104 also returns to the ground potential preserving the state written into the latch. No sensing after programming is necessary if the nv-latch 1 stays on. On device power-up, the nv-latch 1 will be in the right state as described earlier. 
     Thus, according to the invention the non-volatile elements can be programmed by establishing a voltage across the non-volatile elements by using voltages of lower magnitude than that used by conventional approaches. More particularly, according to the invention, a voltage of -V pp  is placed on the p-well while V cc  is placed on the gate, rather than placing a positive potential of +V pp  +V cc  on the gate, while the p-well and source nodes of the n-channel transistors in the latch are held at ground as provided by prior art. 
     Moreover, according to the invention, both the erase and program operations can be executed by using a V pp  supply of a single negative polarity, rather than two polarities, namely -V pp  and +V pp , as used by prior art. 
     During the normal operation of the nv-latch 1 where the state of the non-volatile elements 13 and 13&#39; are mirrored in the latch and output signals Out and Out/ on nodes 104 and 104&#39; are driving other logic gates, the bias C g  on nodes 105 and 105&#39; and the potentials within the nv-latch 1 are such that the latch does not disturb the retention of devices NV1 13&#39; and NV2 13. 
     Retention of non-volatile elements 13 an 13&#39; will not degrade if the biases are either neutral, i.e., zero potential difference between C g  and the channel potentials of non-volatile elements 13 and 13&#39;. Alternatively, if the polarity between C g  and the channels of non-volatile elements 13 and 13&#39; reinforces the state, i.e., a programmed device that has a bias that is a program condition except with magnitudes that are much smaller. If non-volatile element NV1 13&#39; is erased and NV2 13 is programmed, G1 106 and Out/ 104&#39; are high, and G2 106&#39; and Out 104 are low. C g  is high during normal operation and with G1 106 and Out/ 104&#39; high, no differential bias exist between C g  on gate 105&#39; and the channel of erased NV1 13&#39; and retention is not adversely affected. Also, C g  is high enough to turn on programmed NV2 13 (assuming a 2 v to 3 v threshold) so that its channel is at a ground potential and a bias exist that reinforces the program state. 
     Table 1 shows the biases signals and internal nodes for the normal (read), erase, write and program modes just described for nv-latch 1. Therefore, the non-volatile latch according to the invention utilizes a minimum number of additional elements over a standard latch while eliminating disturb biases during normal operation. 
     
                       TABLE 1
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g Vcc
V.sub.pp                    V.sub.cc
                                    V.sub.cc
In      x         V.sub.cc  V.sub.cc /V.sub.ss
                                    x
Sel     V.sub.ss  x         V.sub.cc
V.sub.pp
S.sub.rc
        V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
G1, G2  V.sub.cc /V.sub.ss
                  Float     V.sub.cc /V.sub.ss
                                    V.sub.cc /-V.sub.pp
Out, Out/
        V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.cc /-V.sub.pp
______________________________________
 
    
     If a p-well technology is not available (p-substrate only) but n-channel non-volatile devices 13 and 13&#39; are still desired, the potential of signal S rc  cannot be placed at V cc  during the erase mode and at -V pp  during the program mode. Another method of erasing and programming the non-volatile devices is to keep the potential of S rc  at V ss , and increase the negative voltage on C g  during an erase and increase the positive voltage on C g  (and on the power supply equal to the voltage on C g ) during a program. This monopolar method of erasing and programming is summarized in Table 2 below. 
     
                       TABLE 2
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g V.sub.cc
V.sub.pp                    V.sub.cc
                                    V.sub.pp
In      x         x         V.sub.cc /V.sub.ss
                                    x
Sel     V.sub.ss  V.sub.ss  V.sub.cc
                                    V.sub.ss
S.sub.rc
        V.sub.ss  V.sub.ss  V.sub.ss
                                    V.sub.ss
G1, G2  V.sub.cc /V.sub.ss
                  Float     V.sub.cc /V.sub.ss
                                    V.sub.cc /V.sub.ss
Out, Out/
        V.sub.cc /V.sub.ss
                  V.sub.cc /V.sub.ss
                            V.sub.cc /V.sub.ss
                                    V.sub.pp /V.sub.ss
______________________________________
 
    
     An alternative method for implementing an nv-latch from the circuit of FIG. 1 relies on non-volatile devices being placed in series with the drain or source legs of the active CMOS devices and not in the gate leads of those devices. FIG. 3 shows nv-latch 2 that uses non-volatile devices 23 and 23&#39; in this manner. Though not shown, the non-volatile elements, NV1 23 and NV2 23&#39;, are n-channel devices and are tied to the same p-well signal S rc  on node 201 as the other n-channel transistors 21, 21&#39;, and 22. 
     Inverters 24 and 241 include p-channel transistors 20 and 20&#39;, respectively, and n-channel transistors 21 and 21&#39;, respectively. The drains of n-channel transistors 21 and 21&#39; are connected to output nodes 204 and 204&#39;, respectively, and also to the source nodes of non-volatile devices 23 and 23&#39;, respectively. Nodes 204 and 204&#39; also supply output signals Out and Out/, respectively. Likewise, the drains of p-channel transistors 20 and 20&#39; are connected to the drain nodes of non-volatile devices 23 and 23&#39;, respectively. The gates of non-volatile devices 23 and 23&#39; are connected together at node 205 where signal C g  is supplied. The gates of transistors 20 and 21 are connected together to form the gate node of inverter 24, and likewise the gates of transistors 20&#39; and 21&#39; are connected together to form the gate node of inverter 24&#39;. 
     The source nodes of p-channel transistors 20 and 20&#39; are connected to node 200 where the power supply level V cc  is supplied. The source and body nodes of n-channel transistors 21 and 21&#39; along with the body of non-volatile devices 23 and 23&#39; are connected to node 201 which supplies signal S rc . The drain node 204 of inverter 24 is connected to the gate node of inverter 24&#39;, and the drain node 204&#39; of inverter 24&#39; is connected the gate node of inverter 24. 
     An n-channel input selection transistor N1 22 is provided to connect an input signal In supplied to an input node 203 that is connected to the drain of transistor 22. The source of input selection transistor 22 is connected to node 204 of the latch. A select signal Sel is provided to node 202 connected to the gate of transistor 22 to connect the input signal In on node 203 to the latch node 204 through transistor 22. There are no nodes within non-volatile latch 2 that are connected to the power supply reference potential. 
     It should be pointed out that the non-volatile elements, NV1 23 and NV2 23&#39;, are between the drain leads of the p-channel and n-channel CMOS devices in both Inv1 24 and Inv2 24&#39;, respectively. The operation of this nv-latch 2 is similar to the one described with respect to the embodiment of FIG. 1, including the power-up sequence and the program sequence of erase, write and program described above for non-volatile latch 1. 
     In the power-up sequence, C g  supplied to node 205 couples high with the V cc  potential on node 200 which in turn couples high the nodes of the nv-latch 2 side with the on erased non-volatile element and at some time later, determined by the slew of V cc , the programmed non-volatile element turns on and couples high the other side of the nv-latch. As before, the differential in threshold voltage between the erased and programmed non-volatile elements causes a lag between the turn on of those elements which in turn causes a difference in magnitude of the coupled voltage to each side of the nv-latch 2 and results in a differential voltage between opposite sides of the nv-latch at nodes 204 and 204&#39;. This differential signal is then amplified when V cc  is high enough to turn on the CMOS devices. 
     To erase, write and program the nv-latch 2, the exact same sequence of steps are performed as done for the circuit of FIG. 1. For a given technology, the magnitude of the biases will also be the same. As before, erasing of NV1 23 and NV2 23&#39; are done by bringing signal C g  down to a negative potential while S rc  is at a V cc  potential. After erasure, C g  is kept high so that negative threshold non-volatile devices can pass full CMOS levels and data can be written into the nv-latch 2. Care must be taken to write data into the nv-latch 2 right after erasure so that NV1 23 or NV2 23&#39; are not disturbed. The correct data state written in the nv-latch 2 can now be programmed into the non-volatile elements 23 and 23&#39; simply by bringing S rc  to a negative potential while C g  is at the positive power supply potential. Table 1 also shows necessary biases for normal, erase, write and program modes for the circuit of FIG. 3. 
     As with the schematic of FIG. 1, the biases during the normal mode do not create disturb conditions, and with C g  at a high level, CMOS levels can be maintained at the outputs. Monopolar erase and program voltages can also be utilized in the event that p-well technology is not available. 
     Therefore, the non-volatile elements according to the invention can be erased and programmed by establishing a voltage across the non-volatile elements by using voltages of lower magnitude than that used by conventional approaches. Also, according to the invention, both the erase and program operations can be executed by using a V pp  supply of a single negative polarity, rather than two polarities, namely -V pp  and +V pp , as used by prior art. According to the non-volatile latch of the invention, the desired state of the latch output can be readily established upon applying power to the non-volatile latch circuit and that the outputs can achieve full CMOS rail levels of either V cc  or the supply reference potential while consuming very little or no current, and that this state can be maintained during normal operation using a minimum number of additional devices over a simple latch without disturbing the state of the non-volatile elements. 
     Shown in FIG. 4 is a variation of FIG. 3, except that data input and outputs are at nodes above the non-volatile elements. FIG. 4 shows an nv-latch 3 that uses non-volatile devices 32 and 32&#39; in this manner. Though not shown, the non-volatile elements NV1 32 and NV2 32&#39;, are n-channel devices and are tied to the same p-well signal S rc  on node 301 as the other n-channel transistors 31, 31&#39;, and 33. 
     Inverters 34 and 34&#39; include p-channel transistors 30 and 30&#39;, respectively, and n-channel transistors 31 and 31&#39;, respectively. The drains of p-channel transistors 30 and 30&#39; are connected to respective output nodes 304 and 304&#39; and also to the respective drain nodes of non-volatile devices 32 and 32&#39;. Nodes 304 and 304&#39; also supply respective output signals Out and Out/. Likewise, the drains of n-channel transistors 31 and 31&#39; are connected to the respective source nodes of non-volatile devices 32 and 32&#39;. The gates of non-volatile devices 32 and 32&#39; are connected together at node 305 where signal C g  is supplied. The gates of transistors 30 and 31 are connected together to form the gate node of inverter 34, and likewise the gates of transistors 30&#39; and 31&#39; are connected together to form the gate node of inverter 341. The source nodes of p-channel transistors 30 and 30&#39; are connected to node 300 where the power supply level V cc  is supplied. The source and body nodes of n-channel transistors 31 and 31&#39;, along with the body of non-volatile devices 32 and 32&#39;, are connected to node 301 which supplies signal S rc . The drain node 304 of inverter 34 is connected to the gate node of inverter 34&#39;, and the drain node 304&#39; of inverter 34&#39; is connected the gate node of inverter 34. 
     An n-channel input selection transistor N1 33 is provided to connect an input signal In/ supplied to an input node 303 that is connected to the drain of transistor 33. 
     The source of input selection transistor 33 is connected to node 304 of the latch. A select signal Sel is provided to node 302 connected to the gate of transistor 33 to connect the input signal In/ on node 303 to the latch node 304 through transistor 33. There are no nodes within non-volatile latch 3 that are connected to the power supply reference potential. 
     Operation of this nv-latch 3 is different from the two previous circuits. First of all, during the power-up read and normal modes, C g  is held at ground. Second, complement data is written and programmed into the latch. Third, after programming, the device will need to be powered down then up for proper true data to be read. The differences between operation of FIG. 1 and 3 and that of FIG. 4 are all due to the outputs 304 and 304&#39; and cross-coupling nodes being taken off the drain side of the non-volatile devices 32 and 32&#39;. As before though, output voltage levels will go to CMOS levels, retention of the non-volatile states are not adversely affected by disturb mechanisms, and zero power is consumed during the normal operation. As before, the non-volatile elements 32 and 32&#39; are n-channel devices connected to the same p-well signal S rc  as the other n-channel devices 31, 31&#39; and 33. 
     Since the outputs are taken above NV1 32 and NV2 32&#39;, the erased non-volatile element will produce a logic low during the power-up read at the output of its side of the nv-latch 3, but a high data state is necessary to keep the erase state during the program operation. Likewise, the programmed non-volatile element will produce a logic high at the output of its side of the nv-latch 3, but a low data state is necessary to program the non-volatile element during the program operation. For example if In/ is low during a write, Out will also be low before and after the program operation, NV1 32 will be programmed, and NV2 32&#39; will be erased. After a power-up read, Out will be high, which is the complement of In/. The problem is that after a power-up read and a program operation the data must be the same. As a result, complement data needs to be written into this nv-latch 3 before the program operation and a read operation must be done after the program operation for true data to be present at the outputs 304 and 304&#39; of the nv-latch 3. 
     In the power-up read mode, signals Sel, S rc  and C g  are held at ground while V cc  is ramped to its operating level. When V cc  is near the turn on of the two p-channel devices 30 and 30&#39;, both Out and Out/ start to rise, but the side with the erased non-volatile element will rise slower due to more capacitance presented by the erased non-volatile element. A differential voltage will result and when Out or Out/(program side) rise to close to the n-channel threshold, the nv-latch 3 will self amplify the signals at the outputs 304 and 304&#39; to CMOS levels. 
     The erase, write and program modes are similar to previous circuits except that data/, In/, is written into the latch. After programming, C g  must be quickly brought to V ss  to avoid disturbs. And the nv-latch 3 and all signals must be powered down and a subsequent power-up read of true data accomplished after programming. 
     In the previous examples of FIG. 1 and 3, C g  of NV1 and NV2 are high during the read or normal operation. This was done because during a power-up read, C g  was used to couple the proper node within the nv-latch high, C g  high resulted in CMOS levels at the output, and C g  high also was needed for a non-disturb bias scheme within the nv-latch. For the circuit of FIG. 4, C g  needs to be low during a power-up read since the nv-latch 3 side that stays low is the side that has the erased non-volatile element and C g  slewing high would couple a wrong positive signal into the low side. Also, since the erased non-volatile element is on and its channel is at zero potential during the normal operation, the only potential on C g  that would create a non-disturb condition is the zero potential that is in the channel. A high or low potential on C g  would allow the outputs 304 and 304&#39; to go to CMOS levels, but because of disturb biases, the only C g  bias that could work for this schematic is with C g  at zero potential. Table 3 shows the biases for the schematic of FIG. 4. Again, monopolar erase and program biases can be incorporated when a p-well technology is not available. 
     
                       TABLE 3
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g V.sub.ss
V.sub.pp                    V.sub.cc
                                    V.sub.cc
In/     x         V.sub.cc  V.sub.ss /V.sub.cc
                                    x
Sel     V.sub.ss  x         V.sub.cc
V.sub.pp
S.sub.rc
        V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
Out, Out/
        V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.cc /-V.sub.pp
______________________________________
 
    
     For the circuits discussed so far, the power-up read mode requires direct or indirect coupling mechanisms to read the states stored in the non-volatile elements. Though these coupling mechanisms work, the non-volatile elements do not actively steer the nv-latch nodes in a d.c. method and as a result, the nv-latch is susceptible to data destroying noise during the power-up read mode. What could happen is noise can be injected during the power-up read mode that would reduce or even change polarities of the differential signals developing as a result of coupling and wrong data could be amplified at that point. The best method to guard against noise destroying the differential signals is to configure the non-volatile elements to actively steer the nodes in the nv-latch. By using this method, developing signals that are affected by noise would quickly return to the proper state by the active non-volatile devices. 
     FIG. 5 shows a schematic that uses non-volatile elements to actively steer nodes of the nv-latch 4 to proper states during the power-up read mode through the use of additional isolating devices 44 and 44&#39; on the source side of the non-volatile elements 43 and 43&#39;. These isolating devices are used to isolate the nv-latch 4 nodes from ground during the erase, write and program modes, and to prevent unwanted currents during the normal operation. The non-volatile devices 43 and 43&#39; and the isolating devices are n-channel devices that can be in the same p-well as the other In-channel devices 41 and 41&#39; in the p-well connected to S rc . 
     Inverters 45 and 45&#39; include p-channel transistors 40 and 40&#39;, respectively, and n-channel transistors 41 and 41&#39;, respectively. The source nodes of p-channel transistors 40 and 40&#39; are connected to node 400 where the power supply level V cc  is supplied. The drains of p-channel transistors 40 and 40&#39; are connected to the drains of n-channel transistors 41 and 41&#39;, respectively, and also to output nodes 406 and 406&#39;, respectively. Nodes 406 and 406&#39; also supply output signals Out and Out/, respectively. The source and body nodes of n-channel transistors 41 and 41&#39; are connected to node 401 which supplies signal S rc . 
     The gates of transistors 40 and 41 are connected together to form the gate node of inverter 45, and likewise the gates of transistors 40&#39; and 41&#39; are connected together to form the gate node of inverter 45&#39;. The drain node 406 of inverter 45 is connected to the gate node of inverter 45&#39;, and the drain node 406&#39; of inverter 45&#39; is connected the gate node of inverter 45. 
     Further, nodes 406 and 406&#39; are connected to the drain nodes of non-volatile devices 43 and 43&#39;, respectively. The gates of non-volatile devices 43 and 43&#39; are connected together at node 404 where signal C g  is supplied. The body of non-volatile devices 43 and 43&#39; are connected to node 401 which supplies signal S rc . The source nodes of 43 and 43&#39; are connected to the drain nodes of n-channel transistors 44 and 44&#39;, respectively. Transistors 44 and 44&#39; can either isolate the source nodes of the non-volatile elements 43 and 43&#39;, respectively, or can connect the source nodes to the power supply reference potential. The source of transistors 44 and 44&#39; are tied to the supply reference potential and the gates of transistors 44 and 44&#39; are connected together to node 405 where signal I so  / is supplied. An n-channel input selection transistor N1 42 is provided to connect an input signal In/ supplied to an input node 403 that is connected to the drain of transistor 42. The source of input selection transistor 42 is connected to node 406 of the latch and the body of device 42 is connected to node 401. 
     A select signal Sel is provided to node 402 connected to the gate of transistor 42 to connect the input signal In/ on node 403 to the latch node 406 through transistor 42. It should be pointed out that there are no nodes within the latch circuit of non-volatile latch 4 that are connected to the power supply reference potential. 
     As can be seen in FIG. 5, the non-volatile elements 43 and 43&#39; provide a direct path from the output nodes 406 and 406&#39; of the nv-latch 4 through the isolating devices 44 and 44&#39; to ground. The latch of the nv-latch 4 is now just a simple pair of cross-coupled inverters 45 and 45&#39; with an input device 42 gated with Sel and input from In/ for writing to the latch. 
     Similar to the schematic of FIG. 4 and discussed previously, the outputs 406 and 406&#39; are taken above from drains of the non-volatile elements 43 and 43&#39;. Because of this, complement data must be written into the nv-latch 4 for programming, and, after programming, the nv-latch 4 and its signals must be powered down and a power-up read initiated for true data to be read. 
     During the power-up read mode, the main difference between the schematics of FIG. 4 and 5 is that in FIG. 5 a new signal, I so  /, that is supplied to the gate of the isolating transistors 44 and 44&#39;, is brought high with V cc  to turn on the steering paths through the non-volatile devices 43 and 43&#39; as soon as possible. When V cc  rises, the output node associated with the off programmed non-volatile element will rise while the output node connected to the on erased non-volatile element will be actively held low. A differential signal between the output nodes 406 and 406&#39; will result and amplification of that signal will occur when the high side output node approaches an n-channel threshold. 
     After the output nodes 406 and 406&#39; of the nv-latch 4 have been amplified to CMOS levels, I so  / can be brought low or left high if unwanted end-of life program current is not a concern. After a long period of time that is specified, the thresholds of the programmed non-volatile device could get close enough to zero volts for some leakage current to flow. If this current level is a concern, then the best thing to do is to bring I so  / low during normal modes to turn off the isolating devices 44 and 44&#39;. 
     During the erase, write and program modes the sequence of events and signals generated are the same as that in FIG. 4 except now I so  / is used. During the erase and write modes, I so  / is held low. While in the program mode, I so  / is taken to the same negative level as the S rc  signal to isolate both positive and negative levels within the nv-latch 4 from the ground of the isolating transistors 44 and 44&#39;. When a p-well technology is not available, monopolar erase and program voltages can be utilized. 
     Another embodiment of this invention is as shown in FIG. 6. This circuit uses simple cross-coupled inverters as in FIG. 5, but the steering non-volatile devices 52 and 52&#39; are placed above the outputs 504 and 504&#39; with extra isolating devices 53 and 53&#39; placed between V cc  and the non-volatile elements 52 and 52&#39;. The isolating devices 53 and 53&#39; are p-channel type with their gates connected together to node 506 where signal I so  is supplied. Since the outputs 504 and 504&#39; are taken from the sources of the non-volatile elements 52 and 52&#39; that are connected to V cc  through the drain, the data written into the nv-latch 5 is the same as that read in power-up. Therefore, no power-up read is necessary after a program. 
     Inverters 55 and 55&#39; include p-channel transistors 50 and 50&#39;, respectively, and n-channel transistors 51 and 51&#39;, respectively. The source nodes of p-channel transistors 50 and 50&#39; are connected to node 500 where the power supply level V cc  is supplied. The drains of p-channel transistors 50 and 50&#39; are connected to the drains of n-channel transistors 51 and 51&#39;, respectively, and also to output nodes 504 and 504&#39;, respectively. 
     Nodes 504 and 504&#39; also supply output signals Out and Out/, respectively. The source and body nodes of n-channel transistors 51 and 51&#39; are connected to node 501 which supplies signal S rc . The gates of transistors 50 and 51 are connected together to form the gate node of inverter 55, and likewise the gates of transistors 50&#39; and 51&#39; are connected together to form the gate node of inverter 55&#39;. The drain node 504 of inverter 55 is connected to the gate node of inverter 55&#39;, and the drain node 504&#39; of inverter 55&#39; is connected the gate node of inverter 55. 
     Further, nodes 504 and 504&#39; are connected to the source nodes of non-volatile devices 52 and 52&#39;, respectively. The gates of non-volatile devices 52 and 521 are connected together at node 507 where signal C g  is supplied. The body of non-volatile devices 52 and 52&#39; are connected to node 501 which supplies signal S rc . The drain nodes of 52 and 52&#39; are connected to the drain nodes of p-channel transistors 53 and 53&#39;, respectively. Transistors 53 and 53&#39; can either isolate the drain nodes of the non-volatile elements 52 and 52&#39;, respectively, or can connect the drain nodes to the power supply potential V cc . The source of transistors 53 and 53&#39; are tied to the supply potential V cc  and the gates of transistors 53 and 53&#39; are connected together to node 506 where signal I so  is supplied. 
     An n-channel input selection transistor N1 54 is provided to connect an input signal In supplied to an input node 503 that is connected to the drain of transistor 54. The source of input selection transistor 54 is connected to node 504 of the latch and the body of device 54 is connected to node 501. A select signal Sel is provided to node 502 connected to the gate of transistor 54 to connect the input signal In on node 503 to the latch node 504 through transistor 54. No nodes within the non-volatile latch 5 are connected to the power supply reference potential. 
     In the power-up read mode, as V cc  rises to near a p-channel threshold above ground, p-channel devices 50 and 50&#39; of the nv-latch 5 and isolating devices 53 and 53&#39; start to conduct and create a differential signal between the outputs 504 and 504&#39; of the nv-latch 5 due to the erased and programmed steering non-volatile devices. When the higher output nears an n-channel threshold, the cross-coupled inverters self-amplify the differential signals to CMOS levels. Signals S rc , Sel, In and I so  are held to ground during the power-up read while C g  is taken to the V cc  level and left there in the normal mode so that no disturbs occur as explained with FIG. 1 and 3. 
     During the normal mode, I so  can be brought high or low as explained earlier. The erase, write and program modes is much like that of FIG. 1 and 3 except now signal I so  at V cc  is used to isolate the non-volatile elements 52 and 52&#39; from V cc . As before, monopolar erase and program voltages can be used. 
     In all previous nv-latch circuits, input device N1 is a single n-channel device with outputs that go directly to logic that the nv-latch is influencing. In the next two circuits are other means of inputting and/or outputting to and from the nv-latch. FIG. 7 shows an nv-latch 6 that uses two non-volatile elements NV1 62 and NV2 62&#39; within the input leads of cross coupled inverters Inv1 64 and Inv2 64&#39;. Inverters 64 and 64&#39; include p-channel transistors 60 and 60&#39;, respectively, and n-channel transistors 61 and 61&#39;, respectively. The source nodes of p-channel transistors 60 and 60&#39; are connected to node 600 where the power supply level V cc  is supplied. The drains of p-channel transistors 60 and 60&#39; are connected to the drains of n-channel transistors 61 and 61&#39;, respectively, and also to output nodes 603 and 603&#39;, respectively. Nodes 603 and 603&#39; also supply output signals Out and Out/, respectively. The source and body nodes of n-channel transistors 61 and 61&#39; are connected to node 601 which supplies signal S rc . The gates of transistors 60 and 61 are connected together to form the gate node of inverter 64, and likewise the gates of transistors 60&#39; and 61&#39; are connected together to form the gate node of inverter 64&#39;. The drain node 603 of inverter 64 is connected to the gate node of inverter 64&#39;, and the drain node 603&#39; of inverter 64&#39; is connected the gate node of inverter 64. 
     Further, nodes 603 and 603&#39; are connected to the drain nodes of non-volatile devices 62 and 62&#39;, respectively. The gates of non-volatile devices 62 and 62&#39; are connected together at node 604 where signal C g  is supplied. The body of non-volatile devices 62 and 62&#39; is connected to node 601 which supplies signal S rc . The source nodes of 62 and 62&#39; are connected to the drain nodes of n-channel transistors 63 and 63&#39;, respectively. Transistors 63 and 63&#39; can either isolate the source nodes of the non-volatile elements 62 and 62&#39;, respectively, or can connect the source nodes to respective input signals In/ and In. The source of transistors 63 and 63&#39; are tied to nodes 602 and 602&#39;, respectively, where the input signals are supplied, and the gates of transistors 63 and 63&#39; are connected together to node 605 where signal I so  / is supplied. 
     No input selection transistor is provided since input signals In and In/ are supplied through transistors 63 and 63&#39;, thereby eliminating the need for an additional input select device. Also, there are no nodes within the non-volatile latch 6 that are connected to the power supply reference potential. 
     Referring now to FIG. 8, a plot of node voltages versus time shows the wave forms of the nv-latch during the power up condition. During normal operation the non-volatile elements 62 and 62&#39; have been erased and one selectively programmed such that the threshold of the erased device is negative and that of the programmed device is positive. The theory behind this circuit is that on power up, the gates on node 605 of the input isolation devices 63 and 63&#39; (signal 65 I so  /) rises with the power supply V cc  66 (with C g  r S rc , In and In/ held to ground) and provide a dc path to ground through devices NV1 62 and NV2 62&#39;, whichever is erased and actively holds its side of the nv-latch 6 to ground. 
     This creates a differential signals 67 and 68 at the outputs 603 and 603&#39; of the nv-latch 6 because of the difference in the impedance of the two non-volatile elements 62 and 62&#39;. When there is enough differential signal coupled into the nv-latch 6 and the power supply voltage 66 is higher than the larger of p-channel and n-channel thresholds, the active p-channel and n-channel devices will self amplify the differential signals 67 and 68 to CMOS levels. Since the basic configuration of the nv-latch 6 is that of two cross coupled inverters 64 and 64&#39;, when the outputs 67 and 68 are at CMOS levels, the power consumed goes to zero. However, if at the very end of life the threshold of the programmed non-volatile element becomes slightly depletion, an unwanted current path would exist and isolation devices 63 and 63&#39; gated on node 605 with signal I so  / is required to turn off the current path. These isolation devices 63 and 63&#39; also serve to isolate the non-volatile elements 62 and 62&#39; from In and In/ during the erase and program modes. 
     For the condition of device NV1 62 erased and device NV2 62&#39; programmed, once V cc  66 reaches near a p-channel threshold, subthreshold current from the p-channel devices of Inv1 64 and Inv2 64&#39; will cause Out 68 and Out/ 67 to rise. Even though device NV1 62 is erased, Out 68 can still rise depending on the relative impedance between device NV1 62 and the p-channel device 60, but Out/ 67 will rise faster since NV2 62&#39; has a much higher impedance than NV1 61. 
     Once the voltage on signal Out 68 is lower than V cc  66 by a p-channel threshold or the voltage on Out/ 67 is higher than ground by a n-channel threshold, the cross coupled inverters 64 and 64&#39; will self-amplify the voltages 67 and 68 to CMOS levels as shown by the change in slope of signal Out 68 and Out/ 67. Also, after signal Out 68 and Out/ 67 are at CMOS levels, I so  / 65 can be brought low to turn off the isolation devices 63 and 63&#39;. 
     To store desired states in non-volatile elements 62 and 62&#39; of the nv-latch 6 shown in FIG. 7, a sequence of steps need be performed. First, the non-volatile elements 62 and 62&#39; are erased to negative thresholds. Second, data is written into the nv-latch 6. And third, the non-volatile elements 62 and 62&#39; are programmed using the data written into the nv-latch 6. In FIG. 1, device NV1 62 and device NV2 62&#39; are n-channel devices and are in the same p-well as the n-channel devices 61 and 61&#39; of Inv1 64 and Inv2 64&#39;. 
     In the erase phase, signal C g  supplied to control gate node 604, of both devices NV1 62 and NV2 62&#39; are brought to a negative potential and the p-well potential supplied by S rc  through node 601 is brought to the positive power supply voltage at the same time. This bias condition tunnels holes from the accumulated p-well surface into the storage area and after some time (milliseconds) changes both thresholds to a negative value. Since the thresholds of both devices NV1 62 and NV2 62&#39; are negative and signal C g  is returned to the positive power supply after erasing, the desire data state is written into the latch through the isolation devices 63 and 63&#39; when signal I so  / supplied to node 605 is high. It is critical that time lag between erasing and writing the desired data is as short as possible since after erasure the data state that exist within the nv-latch 6 is unknown and could degrade the erase state of devices NV1 62 or NV2 62&#39;. 
     To program the data just written into the nv-latch 6, the control gate signal, C g , of devices NV1 62 and NV2 62&#39; is at the positive power supply while S rc  and I so  / is brought to a negative potential. With S rc  at a negative potential, the low data state in the nv-latch 6 is also at a negative potential due to the normal action of the latch. If a low from In has been previously written into the latch, node 603&#39; signal Out/ is at the negative potential. 
     Since signal C g  is high and signal Out 603 is high, non-volatile element NV1 62 is inhibited from being programmed and its negative threshold is preserved, but since signal Out/ is at the negative potential, non-volatile element NV2 62&#39; is programmed and its negative threshold is changed to a positive one. After a short period of time (milliseconds), S rc  and I so  / are returned to the ground potential and the voltage of Out/ also returns to the ground potential preserving the state written into the latch. 
     Since device NV1 62 is erased and device NV2 62&#39; is programmed, the nv-latch 6 will power-up with Out low and Out/ high which is opposite that written during the erase/write/program store operation. Therefore, after the store operation, a power down then up must be performed to get the proper data polarity. 
     During the normal operation of the nv-latch 6 where the state of the non-volatile elements 62 and 62&#39; are mirrored in the latch and outputs Out and Out/ are driving other logic gates, the biases of C g  and within the nv-latch 6 is such that it does not disturb the retention of devices NV1 62 and NV2 62&#39;. Retention of non-volatile elements 62 and 62&#39; will not degrade if the biases are either neutral, i.e., zero potential difference between C g  and the channel, or of the polarity to reinforce the state, i.e., a programmed device that has a bias that is a program condition except with magnitudes that are much smaller. If device NV1 62 is erased and device NV2 62&#39; is programmed, Out is low and Out/ is high. C g  is low during normal operation and with Out low, no differential bias exist between C g  and the channel of erased device NV1 62 and retention is not adversely affected. Also, since C g  is low and Out/ is high device NV2 62&#39; is off and no differential bias exist between C g  and substrate or channel. 
     Table 4 shows the biases signals and internal nodes for the normal (read), erase, write and program modes just described. 
     
                       TABLE 4
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g V.sub.ss
V.sub.pp                    V.sub.cc
                                    V.sub.cc
In, In/ x         V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.ss
I.sub.so /
        V.sub.ss  x         V.sub.cc
V.sub.pp
S.sub.rc
        V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
Out, Out/
        V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.cc /-V.sub.pp
______________________________________
 
    
     FIG. 9 shows an example of the layout of the nv-latch 6. Notice that all n-channel devices 61, 61&#39;, 62, 62&#39;, 63, 63&#39; are in the same p-well 69. Inputs signals In and In/ run on active runners 602 and 602&#39; to a metal bus that is orthogonal to the active runners. This metal bus is not shown, since it is not part of the nv-latch 6 but is a part of the normal bus structure of the EPLD or FPGA. Also not shown are the S rc  connections to the p-well 69, since these connections can be made at the ends of groups of nv-latches 6 in a row having contiguous p-wells 69. 
     Besides using the SONOS path as the input path, another means of inputting and outputting is to use p-channel devices as shown in FIG. 10. This is done primarily to isolate the internal nodes 707 and 707&#39; of the nv-latch 7 from input-output lines 702 and 702&#39; that are common to more than two nv-latches of this type. The description of this latch is similar to that in FIG. 7 except a low signal on the p-channel input gates on nodes 703 and 703&#39; are necessary when writing and reading the nv-latch 7. Also when programming, the gates 703 and 703&#39; of the p-channel devices 72 and 72&#39; need to be at V cc  to turn off the path to the common input-output lines 702 and 702&#39;. 
     The p-channel devices 72 and 72&#39; can also be n-channel devices with the proper change of signal polarity on the gates. As in previous circuits, when the non-volatile devices 73 and 73&#39; are below the output nodes 707 and 707&#39;, the polarity of the input and output signals are opposite. 
     Inverters 75 and 75&#39; include p-channel transistors 70 and 70&#39;, respectively, and n-channel transistors 71 and 71&#39;, respectively. The source nodes of p-channel transistors 70 and 70&#39; are connected to node 700 where the power supply level V cc  is supplied. The drains of p-channel transistors 70 and 70&#39; are connected to the drains of n-channel transistors 71 and 71&#39;, respectively, and also to output nodes 707 and 707&#39;, respectively. The source and body nodes of n-channel transistors 71 and 71&#39; are connected to node 701 which supplies signal S rc . The gates of transistors 70 and 71 are connected together to form the gate node of inverter 75, and likewise the gates of transistors 70&#39; and 71&#39; are connected together to form the gate node of inverter 75&#39;. The drain node 707 of inverter 75 is connected to the gate node of inverter 75&#39;, and the drain node 707&#39; of inverter 75&#39; is connected the gate node of inverter 75. 
     Further, nodes 707 and 707&#39; are connected to the respective drain nodes of non-volatile devices 73 and 73&#39;. The gates of non-volatile devices 73 and 73&#39; are connected together at node 704 where signal C g  is supplied. The body of non-volatile devices 73 and 73&#39; and isolation devices 74 and 74&#39; are connected to node 701 which supplies signal S rc . The source nodes of 73 and 73&#39; are connected to the drain nodes of n-channel transistors 74 and 74&#39;, respectively. Transistors 74 and 74&#39; can either isolate the source nodes of the respective non-volatile elements 73 and 73&#39;, or can connect the source nodes to node 701 which supplies signal S rc . The gates of transistors 74 and 74&#39; are connected together to node 705 where signal I so  / is supplied. 
     Two p-channel selection transistor 72 and 72&#39; are provided to connect input and output signals In/-Out and In-Out/ supplied to nodes 702 and 702&#39;, respectively, at the sources of transistors 72 and 72&#39;. The drains of selection transistors 72 and 72&#39; are connected to nodes 707 and 707&#39;, respectively, of the latch. A select signal Sel/ is provided to nodes 703 and 703&#39; connected to the gates of transistors 72 and 72&#39;, respectively, to connect the signals In/-Out and In-Out/ on nodes 702 and 702&#39; to the latch nodes 707 and 707&#39;. No nodes within the non-volatile latch 7 are connected to the power supply reference potential. 
     To all previous circuit configurations, more than a pair of non-volatile element can be added to each nv-latch to enable the nv-latch to store more than a single bit of information. For each pair of non-volatile elements added, another bit of data can be stored per nv-latch. Shown in FIG. 11 is the schematic of FIG. 10 with an extra pair of non-volatile elements and isolation devices added. 
     Inverters 87 and 87&#39; include p-channel transistors 80 and 80&#39;, respectively, and n-channel transistors 81 and 81&#39;, respectively. The source nodes of p-channel transistors 80 and 80&#39; are connected to node 800 where the power supply level V cc  is supplied. The drains of p-channel transistors 80 and 80&#39; are connected to the drains of n-channel transistors 81 and 81&#39;, respectively, and also to nodes 802 and 802&#39;, respectively. The source and body nodes of n-channel transistors 81 and 81&#39; are connected to node 801 which supplies signal S rc . The gates of transistors 80 and 81 are connected together to form the gate node of inverter 87, and likewise the gates of transistors 80&#39; and 81&#39; are connected together to form the gate node of inverter 87&#39;. The drain node 802 of inverter 87 is connected to the gate node of inverter 87&#39;, and the drain node 802&#39; of inverter 87&#39; is connected the gate node of inverter 87. 
     Further, nodes 802 and 802&#39; are connected to the drain nodes of non-volatile devices 83 and 83&#39;, respectively, and then again to the drain nodes of non-volatile devices 85 and 85&#39;. The gates of non-volatile devices 83 and 83&#39; are connected together at node 806 where signal C g  is supplied. The gates of non-volatile devices 85 and 85&#39; are connected together at node 808 where signal C g  2 is supplied. The body of non-volatile devices 83, 83&#39;, 85, and 85&#39; and select transistors 84, 84&#39;, 86, and 86&#39; are connected to node 801 which supplies signal S rc . 
     The source nodes of 83 and 83&#39; are connected to the drain nodes of n-channel transistors 84 and 84&#39;, respectively. The source nodes of 85 and 85&#39; are connected to the respective drain nodes of n-channel transistors 86 and 86&#39;. Transistors 84, 84&#39;, 86 and 86&#39; can either isolate the source nodes of the non-volatile elements 83, 83&#39;, 85 and 85&#39;, respectively, or can connect the source nodes to node 801 which supplies signal S rc . The gates of transistors 84 and 84&#39; are connected together to node 807 where signal I so1  / is supplied. The gates of transistors 86 and 86&#39; are connected together to node 809 where signal I so2  / is supplied. 
     Two p-channel selection transistor 82 and 82&#39; are provided to connect input and output signals In/-Out and In-Out/ supplied to nodes 805 and 805&#39;, respectively, at the sources of transistors 82 and 82&#39;. The drains of selection transistors 82 and 82&#39; are connected to respective nodes 802 and 802&#39; of the latch. A select signal Sel/ is provided to nodes 804 and 804&#39; connected to the gates of transistors 82 and 82&#39;, respectively, to connect the signals In/-Out and In-Out/ on nodes 805 and 805&#39; to the latch nodes 802 and 802&#39;. No nodes within the non-volatile latch 8 are connected to the power supply reference potential. 
     Devices NV1 83 and NV2 83&#39; are used to store a first data state while device NV3 85 and NV4 85&#39; are used to store another data state. Each device of each pair of non-volatile elements are connected to opposite sides of internal nodes in the nv-latch 8. Signal C g1  goes to the gates of devices NV1 83 and NV2 83&#39;, and signal C g2  goes to the gates of devices NV3 85 and NV4 86. Signal I so1  / goes to the gates of isolating transistors 84 and 84&#39; for devices NV1 and NV2, and signal I so2  / goes to the gates of isolating transistors for NV3 86 and NV4 86&#39;. 
     When restoring data from devices NV1 83 and NV2 83&#39; to the nv-latch 8, I so2  / is low in order to cut off the current through devices NV3 85 and NV4 85&#39;. Similarly, when restoring data from devices NV3 85 and NV4 85&#39; to the nv-latch 8, I so1  / is low in order to cut off the current through devices NV1 83 and NV2 83&#39;. 
     Table 5 summarizes the signal biases for FIG. 11. The entries for signals C g1 , C g2  and I so1  /, I so2  / comes in pairs of selected value, deselected value. Signal biases for FIG. 10 can be also taken from Table 5 by assuming that C g1  and C g2  is C g  and I so1  / and I so2  / is I so  /, and only the selected value is used. 
     
                       TABLE 5
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g1, C.sub.g2
        V.sub.ss, V.sub.ss
V.sub.pp, V.sub.cc          V.sub.ss, V.sub.ss
                                    V.sub.cc, -V.sub.pp
In-Out/,
        V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.ss
In/-Out
I.sub.so1 /,
        V.sub.cc →
                  V.sub.ss, V.sub.ss
                            V.sub.ss, V.sub.ss
Vpp
I.sub.so2 /
        V.sub.ss, V.sub.ss
S.sub.rc
        V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
Sel/    V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.cc /-V.sub.pp
Gnd     V.sub.ss  V.sub.cc  V.sub.ss
                                    V.sub.ss
______________________________________
 
    
     A compact nv-latch embodiment of this invention uses non-volatile elements as replacements for the n-channel devices within the latch as seen in FIG. 12. Inverters 92 and 92&#39; include p-channel transistors 90 and 90&#39;, respectively, and n-channel non-volatile transistors 91 and 91&#39;, respectively. The source nodes of p-channel transistors 90 and 90&#39; are connected to node 900 where the power supply level V cc  is supplied. The drains of p-channel transistors 90 and 90&#39; are connected to the drains of n-channel non-volatile transistors 91 and 91&#39;, respectively, and also to output nodes 903 and 903&#39;, respectively. Nodes 903 and 903&#39; also supply respective output signals Out and Out/. The source nodes of n-channel transistors 91 and 91&#39; are connected to nodes 902 and 902&#39;, respectively. Signal S rc  is supplied to node 902&#39; and signal S rc  / is supplied to node 902. The gates of non-volatile transistors 91 and 91&#39; are connected together to node 904 where signal C g  is supplied. The bulk nodes of non-volatile transistors 91 and 91&#39; are connected to a common node 901 where the P-Well signal is supplied. The drain of transistor 90 of inverter 92 is connected to the gate transistor 90&#39; of inverter 92&#39;, and the drain of transistor 90&#39; of inverter 92&#39; is connected the gate of transistor 90 of inverter 92. No nodes within the non-volatile latch 6 are connected to the power supply reference potential. 
     After programming, the threshold of one of the non-volatile elements is negative and the other positive. The p-channel devices 90 and 90&#39; are cross-coupled as before but the non-volatile elements 91 and 91&#39; have a common gate input node 904 where signal C g  is provided. During normal modes of operation with C g  at ground, the state of this nv-latch 9 cannot be different than that stored in the non-volatile elements 91 and 91&#39; since only one of the non-volatile elements can actively hold its drain node low. 
     As before, the outputs 903 and 903&#39; can be taken directly from the internal nodes of the nv-latch 9 or the internal nodes can be accessed from common data lines by single or double n-channel or p-channel devices. Such access devices are not shown. Without input or output access devices, programming is done by bringing a source of one of the non-volatile elements 91 or 91&#39; to -V pp , a negative potential with respect to the power supply reference, while the other source is at a voltage higher than -V pp . Signal C g  during programming is at V cc . The p-well connection of each non-volatile element 91 and 91&#39; is common and at -V pp  during programming. For erasing, C g  is brought to -V pp  while the sources at nodes 902 and 902&#39; and p-well node 901 of the non-volatile elements 91 and 91&#39; are at V cc . No nodes within the non-volatile latch 9 are connected to the power supply reference potential. Table 6 summarizes the bias scheme for the nv-latch 9 of FIG. 12. 
     
                       TABLE 6
______________________________________
Normal        Erase     Write     Program
______________________________________
C.sub.g V.sub.ss
V.sub.pp                    V.sub.ss
                                    V.sub.cc
Out,Out/
        V.sub.cc /V.sub.ss
                  V.sub.cc  V.sub.cc /V.sub.ss
                                    V.sub.ss
S.sub.rc, S.sub.rc /
        V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
P-well  V.sub.ss  V.sub.cc  V.sub.ss
V.sub.pp
______________________________________
 
    
     Unlike each a the embodiments previously described, an nv-latch according to the invention can be constructed which utilizes high impedance passive pull-up elements, rather than p-channel transistors as shown in FIG. 13 for nv-latch 10. Such high impedance passive pull-up elements could comprise high resistance polysilicon resistors such as commonly used today in a building SRAM memory cells, back to back diodes which supply low level leakage current under bias, or depletion MOS devices. 
     Inverters 114 and 114&#39; include high impedance passive elements 110 and 110&#39;, respectively, and n-channel transistors 111 and 111&#39;, respectively. One end of elements 110 and 110&#39; are connected to node 1000 where the power supply level V cc  is supplied. The other end of elements 110 and 110&#39; are connected to the respective drains of n-channel transistors 111 and 111&#39; and also to output respective nodes 1003 and 1003&#39;. Nodes 1003 and 1003&#39; also supply output signals Out and Out/, respectively. 
     The source and body nodes of n-channel transistors 111 and 111&#39; are connected to node 1001 which supplies signal S rc . The drain node 1003 of transistor 111 in inverter 114 is connected to the gate of transistor 111&#39; in inverter 114&#39;, and the drain node 1003&#39; of transistor 111&#39; in inverter 114&#39; is connected the gate node of transistor 111 in inverter 114. 
     Further, nodes 1003 and 1003&#39; are connected to the drain nodes of non-volatile devices 112 and 1121, respectively. The gates of non-volatile devices 112 and 112&#39; are connected together at node 1004 where signal C g  is supplied. The body of non-volatile devices 112 and 112&#39; are connected to node 1001 which supplies signal S rc . The source nodes of 112 and 112&#39; are connected to the drain nodes of n-channel transistors 113 and 113&#39;, respectively. Transistors 113 and 113&#39; can either isolate the source nodes of the non-volatile elements 112 and 112&#39;, respectively, or can connect the source nodes to input signals In/ and In, respectively. 
     The source of transistors 113 and 113&#39; are tied to nodes 1002 and 1002&#39;, respectively, where the input signals are supplied, and the gates of transistors 113 and 113&#39; are connected together to node 1005 where signal I so  / is supplied. No input selection transistor is provided, since input signals In and In/ are supplied through transistors 113 and 113&#39;, thereby eliminating the need for an additional input select device. No nodes within the non-volatile latch 10 are connected to the power supply reference potential. 
     Ten different non-volatile latches have been disclosed. FIG. 1 shows cross-coupled inverters with non-volatile elements within the gate or input leads of the inverters. FIGS. 3 and 4 incorporates non-volatile elements in series with the drain leads of the p-channel or n-channel devices. In FIG. 3, the outputs are taken below the non-volatile elements, while in FIG. 4, the outputs are taken above the non-volatile elements and as a result, a power-up read must be done after a program. For FIG. 1, 3 and 4 coupling mechanisms during power-up are used to read non-volatile data stored which present possibilities of noise disturbing the data. But in FIG. 5 and 6, d.c. non-volatile steering devices connected to V cc  or V ss  through isolation devices are used to greatly lessen the effects of noise. In FIG. 5, the outputs are taken above the non-volatile elements connected to ground and thus, a program must be followed by a power-up read. 
     The outputs in FIG. 6 are taken below non-volatile elements connected to V cc  and no power-up read after a program is necessary. Because of noise immunity and the fact that no power-up read after program is needed, FIG. 6 is the schematic of choice for non-volatile latches. This disclosure only describes nv-latch circuits implemented with n-channel non-volatile elements, but p-channel non-volatile elements can be used by the appropriate changes of voltages in a complementary fashion. FIG. 7 shows another schematic of choice that inputs through the non-volatile elements to write the latch. FIG. 10 incorporates p-channel devices as input/output (I/O) devices and this non-volatile latch can be used when more than one nv-latch share the same output lines. The p-channel I/O devices can also be n-channel devices. FIG. 11 shows a schematic of a nv-latch similar to the one in FIG. 10 but with two pair of non-volatile elements that store two different data states. A very compact nv-latch is described with FIG. 12 and replaces the n-channel devices within the latch with non-volatile elements. Finally, FIG. 13 shows a schematic of a nv-latch that is similar to the one shown in FIG. 7, but incorporates high impedance passive pull up elements rather than p-channel transistors in the cross coupled inverters. All nv-latches in this description can be implemented with more than one pair of non-volatile elements. 
     Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.