Patent Publication Number: US-6912246-B1

Title: Clock signal transmitting system, digital signal transmitting system, clock signal transmitting method, and digital signal transmitting method

Description:
BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to a system and method for generating a transmission digital signal from a source digital signal and reproducing the source digital signal as a reproduced digital signal from the transmission digital signal, and in particular, to a system and method for suppressing an electromagnetic noise generated by the transmission digital signal. The source digital signal is, for example, a clock signal and a data signal. 
   2. Prior Art 
   Since a clock signal is composed of repetitive pulses having the same frequencies, the clock signal has a large spectrum at the clock frequency and its higher harmonic frequencies. When the clock signal is transmitted through a transmission path, the signal radiates electromagnetic noise having these frequencies. A data signal does not have a higher periodicity than the clock signal. However, a video signal and an audio signal which have been band-compressed have a high entropy. Thus, these signals have a high periodicity and large spectrums at ½ frequency of the clock signal and its higher harmonic frequencies. Therefore, a data signal transmitted through a transmission path radiates electromagnetic noise at these frequencies. 
   Conventionally, in order to suppress the electromagnetic noise, the voltage amplitudes or current amplitudes of a clock signal and a data signal are decreased. In addition, a differential transmission system such as ECL (Emitter-Coupled Logic) is used. 
   As a prior art reference, a method and apparatus for suppressing the electromagnetic noise are disclosed in JPA 9-289527. According to the prior art reference, a clock signal is frequency-modulated. The frequency of a spectrum generated from the clock signal is dispersed so as to suppress the electromagnetic noise. 
   In the method and apparatus of the prior art reference disclosed as JPA 9-289527, a source clock signal is frequency-modulated with a particular frequency so that the frequency of the transmission clock signal is dynamically varied. On the reception side, a PLL removes a modulation signal component so that the source clock signal is reproduced. The frequency change ratio of the transmission clock signal which has been frequency-modulated is supposed to be±several percent. 
   Generally, the lock range and capture range of a PLL are as high as several hundred ppm at the maximum. Thus, in the method and apparatus of the prior art reference, the conventional PLL circuit cannot be used to perform adjustment in a several percent range. Instead, a more complicated circuit is required. 
   SUMMARY OF THE INVENTION 
   In order to overcome the disadvantage mentioned above, the present invention has been made and accordingly, has an object to provide a digital signal transmitting system and method which suppress an electromagnetic noise radiated from a transmission digital signal transmitted through a transmission path with a simpler circuit. 
   According to a first aspect of the present invention, there is provided a clock signal transmitting system, comprising: a controlling circuit for generating a first control signal and a second control signal which contains synchronization information of the first control signal; a first reference voltage generating circuit for generating a first reference voltage which periodically varies corresponding to the first control signal; a second reference voltage generating circuit for generating a second reference voltage which periodically varies corresponding to the second control signal; a first comparator for comparing a source clock signal with the first reference voltage in order to generate a transmission clock signal; and a second comparator for comparing the transmission clock signal with the second reference voltage in order to generate a reproduced clock signal. 
   The sum of the first reference voltage generated by the first reference voltage generating circuit and the second reference voltage generated by the second reference voltage generating circuit may be a constant voltage. 
   The first reference voltage generated by the first reference voltage generating circuit and the second reference voltage generated by the second reference voltage generating circuit may periodically vary in the same period. 
   The first reference voltage generating circuit may switch the first reference voltage at a frequency twice as high as the source clock signal, and the second reference voltage generating circuit may switch the second reference voltage at the frequency twice as high as the source clock signal. 
   The controlling circuit may be disposed on a transmission side. 
   The controlling circuit may generate the first control signal and the second control signal on the basis of the source clock signal. 
   The controlling circuit may generate the first control signal and the second control signal on the basis of the transmission clock signal. 
   The controlling circuit may generate the first control signal and the second control signal on the basis of the source clock signal and the transmission clock signal. 
   The controlling circuit may generate the second control signal having a frequency which is lower than a frequency of the source clock signal. 
   The first reference voltage generating circuit may generate the first reference voltage on the basis of the first control signal and the source clock signal. 
   The first reference voltage generating circuit may generate the first reference voltage on the basis of the first control signal and the transmission clock signal. 
   The second reference voltage generating circuit may generate the second reference voltage on the basis of the second control signal and the transmission clock signal. 
   The second reference voltage generating circuit may generate the second reference voltage on the basis of the second control signal and the reproduced clock signal. 
   The clock signal transmitting system may further comprise: a local oscillator disposed on a reception side for generating a local clock signal, wherein the second reference voltage generating circuit generates the second reference voltage on the basis of the second control signal and the local clock signal. 
   The clock signal transmitting system may further comprise: a PLL circuit which inputs the reproduced clock signal as a reference signal in order to output a refined reproduced clock signal. 
   The clock signal transmitting system may further comprise: a PLL circuit which inputs the reproduced clock signal as a reference signal in order to output a refined reproduced signal, wherein the second reference voltage generating circuit generates the second reference voltage on the basis of the second control signal and the refined reproduced signal. 
   The clock signal transmitting system may further comprise: a phase compensating circuit for compensating the phase of the reproduced clock signal. 
   The first control signal may be the same as the second control signal. 
   According to a second aspect of the present invention, there is provided a digital signal transmitting system, comprising: the above clock transmitting system; a third comparator for comparing a source data signal with the first reference voltage in order to generate a transmission data signal; and a fourth comparator for comparing the transmission data signal with the second reference voltage in order to generate a reproduced data signal. 
   These and other objects, features and advantages of the present invention will become more apparent in light of the following detailed description of the best modes of embodiment thereof, as illustrated in the accompanying drawings. 

   
     BRIEF DESCRIPTION OF DRAWING 
       FIG. 1  is a block diagram showing the structure of a clock signal transmitting system according to a first embodiment of the present invention; 
       FIG. 2  is a timing diagram showing the operation of the clock signal transmitting system according to the first embodiment of the present invention; 
       FIG. 3  is a flow chart showing the operation of a controlling circuit according to the first embodiment of the present invention; 
       FIG. 4  is a flow chart showing the operation of a first reference voltage generating circuit according to the first embodiment of the present invention; 
       FIG. 5  is a flow chart showing the operation of a second reference voltage generating circuit according to the first embodiment of the present invention; 
       FIG. 6  is a flow chart showing the operation of a first comparator according to the first embodiment of the present invention; 
       FIG. 7  is a flow chart showing the operation of a second comparator according to the first embodiment of the present invention; 
       FIG. 8  is a block diagram showing the structure of a clock signal transmitting system according to a second embodiment of the present invention; 
       FIG. 9A  is a circuit diagram showing an example of a change detection signal generating circuit of the controlling circuit according to the second embodiment of the present invention; 
       FIG. 9B  is a timing diagram of the change detection signal generating circuit according to the second embodiment of the present invention; 
       FIG. 10  is a flow chart showing the operation of the controlling circuit according to the second embodiment of the present invention; 
       FIG. 11  is a block diagram showing the structure of a clock signal transmitting system according to a third embodiment of the present invention; 
       FIG. 12  is a block diagram showing the structure of a clock signal transmitting system according to a fourth embodiment of the present invention; 
       FIG. 13  is a block diagram showing the structure of a clock signal transmitting system according to a fifth embodiment of the present invention; 
       FIG. 14  is a block diagram showing the structure of a clock signal transmitting system according to a sixth embodiment of the present invention; 
       FIG. 15  is a block diagram showing the structure of a clock signal transmitting system according to a seventh embodiment of the present invention; 
       FIG. 16  is a block diagram showing the structure of a clock signal transmitting system according to an eighth embodiment of the present invention; 
       FIG. 17  is a block diagram showing the structure of a clock signal transmitting system according to a ninth embodiment of the present invention; 
       FIG. 18  is a flow chart showing the operation of the first reference voltage generating circuit according to the ninth embodiment of the present invention; 
       FIG. 19  is a block diagram showing the structure of a clock signal transmitting system according to a tenth embodiment of the present invention; 
       FIG. 20  is a block diagram showing the structure of a clock signal transmitting system according to an eleventh embodiment of the present invention; 
       FIG. 21  is a block diagram showing the structure of a clock signal transmitting system according to a twelfth embodiment of the present invention; 
       FIG. 22  is a block diagram showing the structure of a clock signal transmitting system according to a thirteenth embodiment of the present invention; 
       FIG. 23  is a block diagram showing the structure of a clock signal transmitting system according to a fourteenth embodiment of the present invention; 
       FIG. 24  is a block diagram showing the structure of a digital signal transmitting system according to a sixteenth embodiment of the present invention; and 
       FIG. 25  is a timing diagram showing the timing of the digital signal transmitting system according to the sixteenth embodiment of the present invention. 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   Next, with reference to the accompanying drawings, embodiments of the present invention will be explained in detail. 
   [First Embodiment] 
   First of all, with reference to  FIG. 1 , the structure of a clock signal transmitting system according to a first embodiment will be explained. 
   Referring to  FIG. 1 , the clock signal transmitting system according to the first embodiment comprises clock signal transmitting circuit  31  and clock signal receiving circuit  32 . 
   Clock signal transmitting circuit  31  comprises controlling circuit  1 , first reference voltage generating circuit  2 , and first comparator  3 . Controlling circuit  1  generates first control signal  14  and second control signal  15 . First control signal  14  and second control signal  15  are used to periodically vary first reference voltage  16  and second reference voltage  17 , respectively, and to synchronize voltages  16  and  17 . First reference voltage generating circuit  2  determines first reference voltage  16  corresponding to first control signal  14  and outputs first reference voltage  16 . First comparator  3  inputs source clock signal  11  and first reference voltage  16 , compares them, and outputs transmission clock signal  12  whose frequency periodically varies. 
   Clock signal receiving circuit  32  comprises second reference voltage generating circuit  4  and second comparator  5 . Second reference voltage generating circuit  4  receives second control signal  15  which is supplied from controlling circuit  1  in clock signal transmitting circuit  31  through transmission path  33 , determines second reference voltage  17  corresponding to second control signal  15 , and outputs second reference voltage  17 . Second comparator  5  inputs transmission clock signal  12  which is supplied from clock signal transmitting circuit  31  through transmission path  33  and whose frequency periodically varies and second reference voltage  17  which is generated in second reference voltage generating circuit  4 , compares transmission clock signal  12  with second reference voltage  17 , and outputs reproduced clock signal  13  having a single frequency. 
   Next, with reference to  FIGS. 1 and 2 , the operation of the clock signal transmitting system according to the first embodiment will be explained. 
   First, the operation of clock signal transmitting circuit  31  will be explained. 
   Source clock signal  11  having waveform  101  is input to a + (plus) input terminal of first comparator  3 . 
   First reference voltage  16  having waveform  104  is input to a − (minus) input terminal of first comparator  3 . First reference voltage  16  is generated by first reference voltage generating circuit  2 . First reference voltage  16  has five voltage levels, that is, VT 1 , VT 2 , VT 3 , VT 4 , and VT 5  (where VT 1 &lt;VT 2 &lt;VT 3 &lt;VT 4 &lt;VT 5 ). First reference voltage  16  is in the range of the voltage amplitude of source clock signal  11  which is input to the + input terminal of first comparator  3 . In this case, the high level voltage of source clock signal  11  is VH 1 , whereas the low level voltage of source clock signal  11  is VL 1 . Thus, the relation of VL 1 &lt;VT 1 &lt;VT 2 &lt;VT 3 &lt;VT 4 &lt;VT 5 &lt;VH 1  is satisfied. 
   First reference voltage  16  which is input to first comparator  3  is selected by controlling circuit  1 . Controlling circuit  1  generates first control signal  14  in order that first reference voltage  16  varies in the order of VT 1 , VT 2 , VT 3 , VT 4 , VT 5 , VT 4 , VT 3 , VT 2 , VT 1 , VT 2 , VT 3 , . . . whenever the logical level of source clock signal  11  changes. First control signal  14  designates first reference voltage  16 . Alternatively, controlling circuit  1  may generate first control signal  14  at intervals of at least one period of first reference voltage  16 . First reference voltage generating circuit  2  autonomously switches first reference voltage  16  in synchronization with first control signal  14 . In the latter case, when necessary, first reference voltage generating circuit  2  compensates the phase of first control signal  14 . 
   Next, the operation of first comparator  3  will be explained. At the beginning, first reference voltage generating circuit  2  selects VT 1  as first reference voltage  16  corresponding to first control signal  14 . When the voltage source clock signal  11  becomes VT 1  (waveform  101 ) at time T 21 , first comparator  3  determines that the logical level of source clock signal  11  becomes high and causes the logical level (waveform  102 ) of transmission clock signal  12  to be high. After first reference voltage generating circuit  2  causes the voltage level of first reference voltage  16  to be raised to VT 2 ., when the voltage level of source clock signal  11  becomes VT 2  at time T 22 , first comparator  3  causes the logical level (waveform  102 ) of transmission clock signal  12  to be low. Thereafter, because first reference voltage generating circuit  2  varies the voltage level of first reference voltage  16  as represented by waveform  104 , first comparator  4  outputs transmission clock signal  12  are represented by waveform  102 . It is apparent that frequency of transmission clock signal  12  (waveform  102 ) periodically varies. The change amount and change period of the frequency of transmission clock signal  12  depend on the period of source clock signal  11  and the resolution of first reference voltage  16 . 
   Next, the operation of clock signal receiving circuit  32  will be explained. 
   A + (plus) input terminal of second comparator  5  inputs transmission clock signal  12  supplied from clock signal transmitting circuit  31  through transmission path  33 . 
   Second reference voltage  17  is input to a − (minus) input terminal of second comparator  5 . Second reference voltage  17  is generated by second reference voltage generating circuit  4 . Second reference voltage  17  has five voltage levels VT 11 , VT 12 , VT 13 , VT 14 , and VT 15  (where VT 11 &lt;VT 12 &lt;VT 13 &lt;VT 14 &lt;VT 15 ). Second reference voltage  17  is in the range of the voltage amplitude of transmission clock signal  12  which is supplied to second comparator  5 . In this case, the voltage of the high level of transmission clock signal  12  is VH 2 , whereas the voltage of the low level of transmission clock signal  12  is VL 2 . Thus, the relation of VL 2 &lt;VT 11 &lt;VT 12 &lt;VT 13 &lt;VT 14 &lt;VT 15 &lt;VH 2  is satisfied. The number of voltage levels of first reference voltage  16  of clock signal transmitting circuit  31  is the same as the number of voltage levels of second reference voltage  17  of clock signal receiving circuit  32 . In addition, as will be explained later, the voltage level of first reference voltage  16  of clock signal transmitting circuit  31  synchronizes with the voltage level of second reference voltage  17  of clock signal receiving circuit  32 . 
   Controlling circuit  1  of clock signal transmitting circuit  31  sends second control signal  15  to second reference voltage generating circuit  4  of clock signal receiving circuit  32 . Second control signal  15  contains the synchronization information of first reference voltage  16 . Since the phase of first reference voltage  16  is designated by first control signal  14 , second control signal  15  also contains the synchronization information of first control signal  14 . 
   For example, even in case first control signal  14  designates first reference voltage  16  whenever first reference voltage  16  should change, controlling circuit  1  only have to send second control signal  15  to second reference voltage generating circuit  4  only when the voltage level of first reference voltage  16  varies from VT 1  to VT 2 . In this case, second reference voltage generating circuit  4  autonomously switches the voltage level of second reference voltage  17  in synchronization with second control signal  15 . When necessary, second reference voltage generating circuit  4  compensates the phase of second reference voltage  17  with respect to second control signal  15 . 
   It is tolerable that the frequency of first control signal  14  sent from controlling circuit  1  to first reference voltage generating circuit  2  is twice as high as the frequency of source clock signal  11  from a view point for suppressing electromagnetic noise. However, the frequency of second control signal  15  sent from controlling circuit  1  to second reference voltage generating circuit  4  should be lower than the frequency of source clock signal  11  from a view point for suppressing electromagnetic noise. Second control signal  15  only have to have information at either one of a rising edge or falling edge. Therefore, the duty of second control signal  15  is defined from a view point for suppressing the electromagnetic noise. 
   However, first control signal  14  and second control signal  15  may be unified into a common control signal. In this case, controlling circuit  1  may generate the common control signal at intervals of at least one period of first reference voltage  16  and second reference voltage  17  and output the common control signal to first reference voltage generating circuit  2  and second reference voltage generating circuit  4 . Also in this case, first reference voltage generating circuit  2  and second reference voltage generating circuit  4  autonomously operate in synchronization with common control signal and in predetermined sequences of voltage levels of the reference voltages, respectively. 
   As the relation of the first reference voltage of clock signal transmitting circuit  31  and the second reference voltage of clock signal receiving circuit  32 , VT 1  corresponds to VT 15 ; VT 2  corresponds to VT 14 ; VT 3  corresponds to VT 13 ; VT 4  corresponds to VT 12 ; and VT 5  corresponds to VT 11 . In other words, he lowest voltage level of first reference voltage  16  of clock signal transmitting circuit  31  corresponds to the highest voltage level of second reference voltage  17  of clock signal receiving circuit  32 . The second lowest voltage level of first reference voltage  16  corresponds to the second highest voltage level of second reference voltage  17 . The rest of the voltage levels satisfy the same relation. This the relation of VT 1 +VT 15 =VT 2 +VT 14 =VT 3 +VT 13 =VT 4 +VT 12 =VT 5 +VT 11 =(a constant voltage) is satisfied. The voltage level of second reference voltage  17  varies in the order of VT 15 , VT 14 , VT 13 , VT 12 , VT 11 , VT 12 , VT 13 , VT 14 , VT 15 , VT 14 , VT 13 , and so forth when the logical level of source clock signal  11  changes. 
   Next, with reference to  FIG. 2 , the operation of second comparator  5  will be explained. At the beginning, transmission clock signal  12  when VT 1  is selected as the voltage level of first reference voltage  16  is transmitted from clock signal transmitting circuit  31  to second comparator  5 . At this point, since VT 15  has been selected as the voltage level of the second reference voltage by second reference voltage generating circuit  4 , when the voltage level (waveform  102 ) of transmission clock signal  12  becomes VT 15  at time T 31 , second comparator  5  determines that the logical level of transmission clock signal  12  is high and causes the logical level (waveform  103 ) of reproduced clock signal  13  to be high. Thereafter, second reference voltage generating circuit  4  varies the voltage level of reference voltage  17  to VT 14  corresponding to second control signal  15 . After transmission clock signal  12  corresponding to VT 2  of first reference voltage  16  is transmitted, when the voltage level of transmission clock signal  12  lowers to VT 14  at time T 32 , second reference voltage generating circuit  4  causes the logical level (waveform  103 ) of reproduced clock signal  13  to be low. Thereafter, the voltage level of second reference voltage  17  varies as represented by waveform  105 , and second comparator  5  outputs reproduced clock signal  13  as represented by waveform  103 . The period (the period between rising edges and the period between falling edges) and duty of reproduced clock signal  13  are the same as those of source clock signal  11 . In other words, reproduced clock signal  13  having the same waveform  103  as waveform  101  of source clock signal  11  is obtained by clock signal receiving circuit  32 . 
   The voltage levels of first reference voltage  16  and second reference voltage  17  selected in a repetitive period may be any voltages as long as first reference voltage generating circuit  2  matches second reference voltage generating circuit  4 . Although the voltage levels of first reference voltage  16  and second reference voltage  17  vary whenever the logical level of the clock signal changes in the above explanation, they may vary only when the logical level of the clock signal changes several times. 
   Next, with reference to flow charts as shown in  FIGS. 3  to  7 , the operations of the individual blocks of the first embodiment will be explained. 
   First, with reference to  FIG. 3 , the operation of controlling circuit  1  will be explained. 
   At step S 101 , ΔT 1 , T C , and N C  are set. ΔT 1  is a time counting unit. T C  is the period in which first control signal  14  is output. N C  is the ratio of the period of second control signal  15  to the period of first control signal  14 . 
   At step S 102 , N is set to 0. N is a variable used to control the period of second control signal  15 . At step S 103 , T is set to 0. T is a variable used to control the period of first control signal  14 . At step S 104 , ΔT 1  is added to T. At step S 105 , it is determined whether or not T is equal to or greater than T C . When the determined result at step S 105  is Yes, the flow advances to step S 106 . At step S 106 , first control signal  14  is output. When the determined result at step S 105  is No, the flow returns to step S 104 . The flow advances from step S 106  to step S 107 . At step S 107 , N is incremented by 1. At step S 108 , it is determined whether or not N is equal to N C . When the determined result at step S 108  is Yes, the flow advances to step S 109 . At step S 109 , second control signal  15  is output. When the determined result at step S 108  is No, the flow returns to step S 103 . The flow advances from step S 109  to step S 110 . At step S 110 , N is reset to 0. Thereafter, the flow returns to step S 103 . The value of T C  is represented by T C =n×(T CLK /2) (where n is an integer greater than zero; and T CLK  is the period of the clock signal). When N is set to 1 at step S 101 , the period of first control signal  14  is equal to the period of second control signal  15 . 
   Next, with reference to  FIG. 4 , the operation of the first reference voltage generating circuit  2  will be explained. 
   At step S 201 , ΔT 2  is set. ΔT 2  is a time counting unit. Thereafter, at step S 202 , T is set to 0. T is a variable used to control the time at which the voltage level of first reference voltage  16  is varied. Thereafter, at step S 203 , it is determined whether or not first control signal  14  has been input. When the determined result at step S 203  is Yes, the flow advances to step S 207 . At step S 207 , the voltage level of first reference voltage  16  is set to VT 1 . When the determined result at step S 203  is No, the flow advances to step S 204 . At step S 204 , ΔT 2  is added to T. Thereafter, at step S 205 , it is determined whether or not T is equal to or larger than T CLK /2. When the determined result at step S 205  is Yes, the flow advances to step S 206 . At step S 206 , the voltage level of first reference voltage  16  is varied to the next voltage level in the sequence. Thereafter, the flow returns to step S 202 . When the determined result at step S 205  is No, the flow returns to step S 203 . 
   Next, with reference to  FIG. 5 , the operation of second reference voltage generating circuit  4  will be explained. 
   At step S 301 , ΔT 4  is set. ΔT 4  is a time counting unit. At step S 302 , T is set to 0. T is a variable used to control the time at which the voltage level of second reference voltage  17  is varied. Thereafter, at step S 303 , it is determined whether or not second control signal  15  has been input. When the determined result at step S 303  is Yes, the flow advances to step S 307 . At step S 307 , the voltage level of the first reference voltage  16  is set to VT 15 . When the determined result at step S 303  is No, the flow advances to step S 304 . At step S 304 , ΔT 4  is added to T. Thereafter, the flow advances to step S 305 . At step S 305 , it is determined whether or not T is equal to or larger than T CLK /2. When the determined result at step S 305  is Yes, the flow advances to step S 306 . At step S 306 , the voltage level of second reference voltage  17  is varied to the next voltage level in the sequence. Thereafter, the flow returns to step S 302 . When the determined result at step S 305  is No, the flow returns to step S 303 . 
   Next, with reference to  FIG. 6 , the operation of the first comparator  3  will be explained. 
   At step S 401 , it is determined whether or not the voltage of source clock signal  11  is equal to or higher than first reference voltage  16 . When the determined result at step S 401  is Yes, the flow advances to step S 402 . When the determined result at step S 401  is No, the flow advances to step S 403 . At step S 402 , the logical level of transmission clock signal  12  is set to high. Thereafter, the flow returns to step S 401 . At step S 403 , the logical level of transmission clock signal  12  is set to low. Thereafter, the flow returns to step S 401 . 
   Next, with reference to  FIG. 7 , the operation of second comparator  5  will be explained. 
   At step S 501 , it is determined whether or not the voltage of the transmission clock signal  12  is equal to or higher than second reference voltage  17 . When the determined result at step S 501  is Yes, the flow advances to step S 502 . When the determined result at step S 501  is No, the flow advances to step S 503 . At step S 502 , the logical level of reproduced clock signal  13  is set to high. Thereafter, the flow returns to step S 501 . At step S 503 , the logical level of reproduced clock signal  13  is set to low. Thereafter, the flow returns to step S 501 . 
   [Second Embodiment] 
   According to a second embodiment of the present invention shown in  FIG. 8 , controlling circuit  1  inputs source clock signal  11  and detects the timing at which the voltage level of the waveform of source clock signal  11  becomes VH 1  and the timing at which the voltage level of the waveform of source clock signal  11  becomes VL 1 . Corresponding to these timings, controlling circuit  1  generates first control signal  14  and second control signal  15 . This operation is based on the principle that when the voltage level of source clock signal  11  is varied, the voltage levels of first reference voltage  16  and second reference voltage  17  should be varied. First control signal  14  is output whenever the voltage level of the waveform of source clock signal  11  becomes VH 1  or VL 1 . Alternatively, first control signal  14  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. Second control signal  15  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. First control signal  14  and second control signal  15  may be unified. In this case, first reference signal  14  and second control signal  15  are simultaneously output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. 
   Next, with reference to  FIGS. 9A ,  9 B, and  10 , the structure and the operation of controlling circuit  1  according to the second embodiment of the present invention will be explained. 
   The timings at which the voltage level of the waveform of source clock signal  11  becomes VH 1  and VL 1  are detected by supplying source clock signal  11  to a circuit shown in FIG.  9 A and observing the timing at which the logical level of a change detection signal becomes high.  FIG. 9B  shows waveforms of the input signal of the circuit shown in FIG.  9 A and the change detection signal. 
   Referring to  FIG. 10 , at step S 601 , M C  and N C  are set. M C  represetnts the ratio of the period of first control signal  14  to the period of the clock signal. N C  represents the ratio of the period of second control signal  15  to the period of first control signal  14 . Thereafter, at step S 602 , N is set to 0. N is a variable used to control the period of first control signal  14 . Thereafter, at step S 603 , M is set to 0. M is a variable used to control the period of second control signal  15 . Thereafter, at step S 604 , it is determined whether or not the change detecting signal has been output from the circuit shown in FIG.  9 A. When the determined result at step S 604  is Yes, the flow advances to step S 605 . When the determined result at step S 604  is No, the flow returns to step S 604 . At step S 605 , M is incremented by 1. Thereafter, at step S 606 , it is determined whether or not M is equal to M C . When the determined result at step S 606  is Yes, the flow advances to step S 607 . when the determined result at step S 606  is No, the flow returns to step S 604 . At step S 607 , the first control signal is output. Thereafter, at step S 608 , N is incremented by 1. Thereafter, at step S 609 , it is determined whether or not N is equal to N C . When the determined result at step S 609  is Yes, the flow advances to step S 610 . When the determined result at step S 609  is No, the flow returns to step S 603 . At step S 610 , the second control signal is output. Thereafter, at step S 611 , N is set to 0. Thereafter, the flow returns to step S 603 . 
   [Third Embodiment] 
   According to a third embodiment of the present invention shown in  FIG. 11 , controlling circuit  1  inputs transmission clock signal  12 , detects the timings at which the voltage level of the waveform of transmission clock signal  12  becomes VH 2  and the timings at which the voltage level of the waveform of transmission clock signal  12  becomes VL 2 , and generates first control signal  14  and second control signal  15  corresponding to these detection timings. This operation is based on the principle that when the voltage level of transmission clock signal  12  is varied, the voltage level of the second reference voltage  17  may be varied and the voltage level of first reference voltage  16  may be varied. It is not too late to vary the voltage of first reference voltage  16  when the voltage level of transmission clock signal  12  is changed. First control signal  14  is output whenever the voltage level of the waveform of source clock signal  11  becomes VH 1  or VL 1 . Alternatively, first control signal  14  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. Second control signal  15  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. First control signal  14  and second control signal  15  may be unified. In this case, first reference signal  14  and second control signal  15  are simultaneously output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. 
   Since the structure and operation of the controlling circuit  1  according to the third embodiment are the same as those according to the second embodiment (see FIGS.  9  and  10 ), the redundant description is omitted. 
   [Fourth Embodiment] 
   According to a fourth embodiment of the present invention shown in  FIG. 12 , controlling circuit  1  inputs source clock signal  11  and transmission clock signal  12 , detects the timings at which the voltage level of the waveform of source clock signal  11  becomes VH 1  and timings at which the voltage level of the waveform of source clock signal  11  becomes VL 1 , generates first control signal  14  corresponding to the detection timings, detects the timings at which the voltage level of the waveform of transmission clock signal  12  becomes VH 2  and timings at which the voltage level of the waveform of transmission clock signal  12  becomes VL 2 , and generates second control signal  15  corresponding to the detection timings. This operation is based on the principle that when the voltage level of source clock signal  11  is varied, the voltage level offirst reference voltage  16  can be varied, and when the voltage level of transmission clock signal  12  is varied, the voltage level of first reference voltage  16  can be varied. First control signal  14  is output whenever the voltage level of the waveform of source clock signal  11  becomes VH 1  or VL 1 . Alternatively, first control signal  14  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. Second control signal  15  is output every time when one or more period of first reference voltage  16  and second reference voltage  17  elapse. 
   Since the structure and operation of the controlling circuit  1  according to the fourth embodiment of the present invention are the same as those according to the second embodiment, the redundant description is omitted. 
   Controlling circuit  1  may generates first control signal  14  and second control signal  15  at the timing at which the logical level of source clock signal  11  becomes identical with the logical level of transmission clock signal  12 . In this case, similarly to the second embodiment and the third embodiment, first control signal  14  and second control signal  15  may be unified. 
   [Fifth Embodiment] 
   According to a fifth embodiment of the present invention shown in  FIG. 13 , a PLL  6  is disposed. Thus, clock signal receiving circuit  32 B is used in the place of clock signal receiving circuit  32 . PLL  6  inputs reproduced clock signal  13  as a reference signal from second comparator  5  to output reproduced clock signal  13 B. The fifth embodiment is used when high accuracy of the frequency of the clock signal is required. Since certain accuracy of the frequency of reproduced clock signal  13  is obtained, a conventional PLL may be used as PLL  6 . Thus, a reproduced clock signal with desired accuracy can be obtained without need to use a complicated PLL circuit which compensates the frequency fluctuation of several percent. 
   [Sixth Embodiment] 
   Since there is a phase difference between source clock signal  11  and reproduced clock signal  13 , phase compensating circuit  7  as shown in  FIG. 14  may be disposed at the following stage of the second comparator  5  in order to have the phase difference of reproduced clock signal  13  to a data signal (not shown) be equal to the phase difference of source clock signal  11  to the data signal (not shown). 
   [Seventh Embodiment] 
   In order to attain the same purpose as the sixth embodiment, as shown in  FIG. 15 , phase compensating circuit  7  may be disposed between second comparator  5  and PLL  6 . 
   [Eighth Embodiment] 
   In order to attain the same purpose as the sixth embodiment, as shown in  FIG. 16 , phase compensating circuit  7  may be disposed at the following stage of PLL  6 . 
   [Ninth Embodiment] 
   According to a ninth embodiment of the present invention shown in  FIG. 17 , controlling circuit  1  outputs first control signal  14  to first reference voltage generating circuit  2  every time when one or more periods of first reference voltage  16  and second reference voltage  17  elapse. First reference voltage generating circuit  2  inputs source clock signal  11  and first control signal  14  and causes a built-in flywheel circuit to use source clock signal  11  as a clock signal and first control signal  14  as a phase synchronization signal so as to generate first reference voltage  16 . 
   Next, with reference to  FIG. 18 , the operation of first reference voltage generating circuit  2  according to the ninth embodiment will be explained. 
   Referring to  FIG. 18 , at step S 701 , it is determined whether or not first control signal  14  has been input. When the determined result at step S 701  is Yes, the flow advances to step S 704 . At step S 704 , the voltage level of first reference voltage  16  is set to VT 1 . When the determined result at step S 701  is No, the flow advances to step S 702 . At step S 702 , it is determined whether or not the change detection signal has been output from the circuit shown in  FIG. 9  included in first reference voltage generating circuit  2 . When the determined result at step S 702  is Yes, the flow advances to step S 703 . At step S 703 , the voltage level of the first reference voltage is varied to the next voltage level in the sequence. When the determined result at step S 702  is No, the flow returns to step S 701 . 
   [Tenth Embodiment] 
   According to a tenth embodiment of the present invention shown in  FIG. 19 , controlling circuit  1  outputs first control signal  14  to first reference voltage generating circuit  2  every time when one or more periods of first reference voltage  16  and second reference voltage  17  elapse. First reference voltage generating circuit  2  inputs transmission clock signal  12  and first control signal  14  and causes a built-in flywheel circuit to use transmission clock signal  12  as a clock signal and first control signal  14  as a phase synchronization signal so as to generate first reference voltage  16 . 
   Since the operation of first reference voltage generating circuit  2  according to the tenth embodiment is the same as that according to the ninth embodiment (see FIG.  18 ), the redundant description is omitted. 
   [Eleventh Embodiment] 
   According to an eleventh embodiment of the present invention shown in  FIG. 20 , controlling circuit  1  outputs second control signal  15  to second reference voltage generating circuit  4  every time when one or more periods of first reference voltage  16  and the second reference voltage  17  elapse. Second reference voltage generating circuit  4  inputs transmission clock signal  12  and second control signal  15  and causes a built-in flywheel circuit to use transmission clock signal  12  as a clock signal and second control signal  15  as a phase synchronization signal so as to generate second reference voltage  17 . 
   Since the operation of second reference voltage generating circuit  4  according to the eleventh embodiment is the same as the operation of first reference voltage generating circuit  2  according to the ninth embodiment (see FIG.  18 ), the redundant description is omitted. 
   [Twelfth Embodiment] 
   According to a twelfth embodiment of the present invention shown in  FIG. 21 , controlling circuit  1  outputs second control signal  15  to second reference voltage generating circuit  4  every time when one or more periods of first reference voltage  16  and second reference voltage  17  elapse. Second reference voltage generating circuit  4  inputs reproduced clock signal  13  and second control signal  15  and causes a built-in flywheel circuit to use reproduced clock signal  13  as a clock signal and second control signal  15  as a phase synchronization signal so as to generate second reference voltage  17 . 
   Since the operation of second reference voltage generating circuit  4  according to the twelfth embodiment is the same as the operation of first reference voltage generating circuit  2  according to the ninth embodiment (see FIG.  18 ), the redundant description is omitted. 
   [Thirteenth Embodiment] 
   According to a thirteenth embodiment of the present invention shown in  FIG. 22 , controlling circuit  1  outputs second control signal  15  to second reference voltage generating circuit  4  every time when one or more periods of first reference voltage  16  and second reference voltage  17  elapse. Local oscillator  8  outputs local clock signal  18  to second reference voltage generating circuit  4 . Second reference voltage generating circuit  4  inputs local clock signal  18  and second control signal  15  and causes a built-in flywheel to use local clock signal  18  as a clock signal and second control signal  15  as a phase synchronization signal so as to generate second reference voltage  17 . 
   Since the operation of second reference voltage generating circuit  4  according to the thirteenth embodiment is the same as the operation of first reference voltage generating circuit  2  according to the ninth embodiment (see FIG.  18 ), the redundant description is omitted. 
   [Fourteenth Embodiment] 
   According to a fourteenth embodiment of the present invention shown in  FIG. 23 , controlling circuit  1  outputs second control signal  15  to second reference voltage generating circuit  4  every time when one or more periods of first reference voltage  16  and second reference voltage  17  elapse. Second reference voltage generating circuit  4  inputs reproduced clock signal  13 B and second control signal  15  and causes a built-in flywheel circuit to use reproduced clock signal  13 B as a clock signal and second control signal  15  as a phase synchronization signal so as to generate second reference voltage  17 . 
   Since the operation of second reference voltage generating circuit  4  according to the fourteenth embodiment is the same as the operation of first reference voltage generating circuit  2  according to the ninth embodiment (see FIG.  18 ), the redundant description is omitted. 
   [Fifteenth Embodiment] 
   Since the second to fourth embodiments, the ninth and tenth embodiments, and the eleventh to fourteenth embodiments can be freely combined,  24  modifications (3×2×4=24) can be accomplished. 
   [Sixteenth Embodiment] 
     FIG. 24  shows the structure of a digital signal transmitting system according to a sixteenth embodiment of the present invention. Referring to  FIG. 24 , according to the sixteenth embodiment, third comparator  9  and fourth comparator  10  are added to the structure of the first embodiment shown in FIG.  1 . Third comparator  9  and fourth comparator  10  are used to transmit a data signal. Third comparator  9  inputs first reference voltage  16  and source data signal  21 , compares them, and outputs the compared result as transmission data signal  22 . Fourth comparator  10  inputs second reference voltage  17  and transmission data signal  22 , compares them, and outputs the compared result as reproduced data signal  23 . 
     FIG. 25  is a timing diagram showing waveform  201  of source data signal  21 , waveform  202  of transmission data signal  22 , waveform  203  of reproduced data signal  23 , waveform  104  of first reference voltage  16 , and waveform  105  of second reference voltage  17 . Referring to  FIG. 25 , although the timing of the rising edge of transmission data signal  22  is not simultaneous with the timing of the falling edge of transmission data signal  22 , the timing the of rising edge of the reproduced data signal  23  is simultaneous with the timing of the falling edge of reproduced data signal  23 . 
   In other words, when the logical level of source data signal  21  becomes high, the waveform  202  of transmission data signal  22  begins to rise at times T 21 , T 23 , T 25 , T 27 , and T 29 . When the logical level of transmission data signal  22  becomes high, the waveform  203  of reproduced data signal  23  begins to rise at times T 31 , T 33 , T 35 , T 37 , and T 39 . On the other hand, when the logical level of source data signal  21  becomes low, waveform  202  of the logical level of transmission data signal  22  begins to fall at times T 41 , T 23 , T 43 , T 27 , and T 45 . When the logical level of transmission data signal  22  becomes low, the waveform  203  of reproduced data signal  23  begins to fall at times T 31 , T 33 , T 35 , T 37 , and T 39 . 
   Thus, although the phase of reproduced data signal  23  is delayed from the phase of source data signal  21 , the waveform of reproduced data signal  23  becomes identical with the waveform of source data signal  21 . In other words, jitters contained in the transmission data signal  22  is removed from reproduced data signal  23 . 
   It should be noted that the second to fifteenth embodiments can be applied to the sixteenth embodiment as their modifications. 
   As was explained above, according to the present invention, since a source clock signal and a first reference voltage that periodically varies are input to a first comparator, the frequency of a transmission clock signal can be periodically varied corresponding to the timings at which the logical level of the clock signal becomes high and low. Thus, electromagnetic noise which takes place upon transmission of the transmission clock signal can be suppressed. This effect applies to a data signal. 
   Synchronization information of a control signal on a transmission side of a transmission clock signal is transmitted to a clock signal receiving circuit. Corresponding to the synchronous signal, a second reference voltage is periodically varied. Thus, a reproduced clock signal having a single frequency is obtained from a transmission clock signal whose frequency periodically varies. This effect applies to a data signal. 
   Although the present invention has been shown and explained with respect to the best modes of embodiment thereof, it should be understood by those skilled in the art that the foregoing and various other changes, omissions, and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention.