Patent Publication Number: US-6906561-B2

Title: Cascode stage input/output device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is related to U.S. patent application Ser. No. 10/159,881, filed May 30, 2002, U.S. patent application Ser. No. 10/159,002, filed May 30, 2002, and U.S. patent application Ser. No. 10/159,684, filed May 30, 2002. 
    
    
     BACKGROUND OF THE INVENTION 
       FIG. 1  illustrates in block diagram form a microprocessor  10  coupled to memory device  12  via a data bus  14 . Although not shown, data bus  14  includes a plurality of conductive lines, each one of which is capable of transmitting a data bit signal between memory device  12  and microprocessor  10 . 
     Microprocessor  10  includes a plurality of input/output (IO) devices (not shown in  FIG. 1 ) coupled to respective conductive lines of data bus  14 . IO devices transmit or receive data bit signals.  FIG. 2  is a schematic diagram of a driver  16  contained in one of the IO devices of microprocessor  10 . Driver  16  drives one of the conductive lines of data bus  14  in response to receiving an input data bit signal. 
     Driver  16  includes a p-channel field effect transistor  20 , an n-channel field effect transistor  22 , an input node  24 , and an output node  26 . Although not shown, output node  26  is coupled to a conductive line of data bus  14 . P-channel field effect transistors will be referred to as p-channel FETs, and n-channel field effect transistors will be referred to as n-channel FETs. N-channel and p-channel FETs include a gate, a drain, and a source designated g, d, and s, respectively. The gates of FETs  20  and  22  are coupled to input node  24 . The drains of FETs  20  and  22  are coupled to output node  26 . The source of FET  20  is coupled to V dd , while the source of FET  22  is coupled to V cg . V dd  is a supply voltage provided from a source external to microprocessor  12 , while V cg  is common ground. 
     In operation, input node  24  receives an input data bit signal D in  directly or indirectly from the core of microprocessor  10 . Although not shown, D in  is typically provided to input node  24  by a signal inverting circuit. The input data bit signal D in  varies between two voltage levels V dd  or V cg  representing a binary one or a binary zero, respectively. In response to receiving D in  driver  16  chargers or discharges output node  26  and the conductive line of data bus  14  coupled thereto. When driver  16  receives D in  equal to V cg , driver  16  charges output node  26  to V dd . When driver  16  receives D in  equal to V dd , driver  16  discharges output node  26  to V cg . In this manner, driver  16  generates an output data bit signal D out  at output node  26  that varies between V dd  and V cg  in response to receiving input data bit signal D in  that varies between V dd  and V cg . 
     P-channel or n-channel FETs are often referred to as electronic switches. A p-channel FET is active or “switched on” when its gate voltage V g  is a threshold voltage V t  or more below its source voltage V s . In other words, a p-channel FET is active when V g &lt;V s −V t . When active, a p-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. When its gate voltage V g  is greater than a threshold voltage V t  below its source voltage V s  the p-channel FET is inactive. In other words, a p-channel FET is inactive when V g &gt;V s −V t . When inactive, essentially no current can flow between the p-channel FET&#39;s source and drain. In  FIG. 2 , p-channel FET  20  is active when the voltage of D in  is V cg  and inactive when D in  is V dd . 
     An n-channel FET is active or “switched on” when its gate voltage V g  is a threshold voltage V t  or more above its source voltage V s . In other words, an n-channel FET is active when V g &gt;V s +V t . When active, an n-channel FET provides a very low impedance path between its source and drain such that current can flow therebetween. An n-channel FET is inactive when V g &lt;V s +V t . When inactive, essentially no current can flow between the n-channel FET&#39;s source and drain. In  FIG. 2 , n-channel FET  22  is active when the voltage of D in  is V dd  and inactive when D in  is V cg . 
     N-channel or p-channel FET operation is subject to limitations. More particularly, the voltage V gd  between the gate and the drain of the devices or the voltage V gs  between the gate and source of the devices should not exceed a gate oxide voltage limit V limit . If V gs  or V gd  exceeds V limit  in either a p-channel or n-channel FET, damage can occur to the FET that renders it permanently inoperable. 
     V limit  (also known as gate oxide integrity) depends on failure in time (FIT) rate, the gate area of the FET, and/or the distance between the source and drain of the FET. The FIT rate requirement is provided by a system design specification. For p-channel and n-channel FETs manufactured using a 0.18 micron process, V limit  may vary between 1.4-1.8 volts depending on how the p-channel FETs are operated. The V limit  for p-channel and n-channel FETs of a particular size and used in a particular manner, can be determined based on experimental results. 
     The sizes of FETs, including the distance between sources and drains thereof, in microprocessors continue to reduce as semiconductor manufacturing technology advances. As FETs continue to reduce in size, so does their V limit . 
     As noted above, driver  16  operates to charge or discharge output node  26 , and thus the conductive line of data bus  14  and the memory device  12  coupled thereto, in accordance with the input data bit signal D in  Characteristics of driver  16  are subject to variations in operational parameters such as temperature and/or magnitude of supply voltage V dd . For example, an increase in operating temperature of driver  16  may increase its output impedance and potentially reduce driver  16 &#39;s drive strength or ability to fully charge or discharge output node  26  within a predetermined amount of time. 
     Notwithstanding variations in operational parameters, which are dynamic in nature, the actual output impedance of driver  16  may not match the expected impedance of driver  16  due to unexpected and permanent variations in the physical structure of FETs  20  and  22 . More particularly, microprocessors including their drivers are manufactured on silicon wafers using complex equipment and processes. Once completed, the microprocessors are severed from the silicon wafer and individually packaged for subsequent use. A single wafer, depending on its size, is capable of producing several microprocessors. In theory, each of these microprocessors should be identical to each other in physical structure. In practice, slight physical variations exist between these microprocessors. For example, due to variations in the fabrication process, the doping density in the source or drain regions of FETs  20  and  22  of driver  16 , or the length or width of gates of FETs  20  and  22  of driver  16 , may unexpectedly vary from microprocessor to microprocessor. These physical variations in the FETs are static in nature and may unexpectedly increase or decrease the output impedance of driver  16 . 
     Generally, the output impedance of driver  16  can be represented as its output voltage V divided by its output current I. As noted above, the output impedance of driver  16  may vary with, for example, temperature and/or magnitude of V dd .  FIG. 3  illustrates IV curves that plot the output voltage V of driver  16  versus the output current I of driver  16 . Each IV curve corresponds to driver  16  operating at different temperatures and/or magnitudes of V dd . The IV curves of  FIG. 3  were drawn with the presumption that no load is applied to output node  26 . 
     As can be seen from  FIG. 3 , each of the IV curves are non-linear which means that the output impedance of driver  16  varies with its output voltage. The IV curves of  FIG. 3  also show that output impedance of driver  16  varies with temperature and/or magnitude of V dd  for a given output voltage V. The impedance of the conductive line and the memory device  12  coupled to output node  26 , however, is static or substantially static. As a consequence, a mismatch generally occurs between the output impedance of driver  16  and the combined impedance of the conductive line and memory device  12 . This mismatch of impedances may degrade or limit the ability of driver  16  to transmit data bit signals to memory device  12  for storage therein. 
     SUMMARY OF THE INVENTION 
     Disclosed is an input/output (IO) device for transmitting an input data bit signal. In one embodiment, the IO device includes an IO device input node for receiving the input data bit signal and an IO device output node. The IO device also includes a driver coupled between the IO device input node and the IO device output node. The driver includes at least one FET that defines a gate oxide voltage limit. The driver receives a supply voltage and the input data bit signal. The driver charges and discharges the IO device output node to the supply voltage and ground, respectively, in response to driver receiving the supply voltage and the input data bit signal. The supply voltage is greater than the gate oxide voltage limit. 
     In one embodiment, the driver includes first and second p-channel FETs each having a source, drain, and gate, and first and second n-channel FETs each having a source, drain, and gate. The gate of the first n-channel FET is coupled to the IO device input node. The drains of the first p-channel FET and the second n-channel FET are coupled to the IO device output node. The source of the second n-channel FET is coupled to the drain of the first n-channel FET. The source of the first p-channel FET is coupled to the drain of the second p-channel FET. The source of the second p-channel FET is coupled to the supply voltage when the driver receives the supply voltage. 
     A first circuit may be coupled between the IO device input node and the gate of the second p-channel FET. This first circuit receives the input data bit signal and the supply voltage and generates a modified input data bit signal which varies between the supply voltage and an intermediate voltage in response to receiving the supply voltage and the input data bit signal. The intermediate voltage is greater than ground but less than the supply voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention may be better understood, and its numerous objects, features and advantages made apparent to those skilled in the art by referencing the accompanying drawings. The use of the same reference number throughout the figures designates a like or similar element. 
         FIG. 1  is a block diagram of a microprocessor coupled to a memory device via a data bus; 
         FIG. 2  is a schematic diagram of a driver contained in an IO device of the microprocessor of  FIG. 1 ; 
         FIG. 3  illustrates IV curves of the driver shown in  FIG. 2 ; 
         FIG. 4  is a block diagram of a microprocessor coupled to a memory device via a data bus; 
         FIG. 5  is a schematic diagram of one embodiment of a driver contained in an IO device of the microprocessor of  FIG. 4 ; 
         FIG. 6  is a timing diagram illustrating operational aspects of the driver shown in  FIG. 5 ; 
         FIG. 7  is a schematic diagram of another embodiment of a driver contained in an IO device of the microprocessor of  FIG. 4 ; 
         FIG. 8  is an IV curve representing the output impedance characteristics of the driver shown in  FIG. 7 ; 
         FIG. 9  is a schematic diagram of another embodiment of a driver contained in an IO device of the microprocessor of  FIG. 4 ; 
         FIG. 10  illustrates another embodiment of a driver contained in the IO device of microprocessor of  FIG. 4 ; 
         FIG. 11A  illustrates another embodiment of a driver contained in the IO device of microprocessor of  FIG. 4 ; 
         FIG. 11B  illustrates IV curves representing the output impedance characteristics of the driver shown in  FIG. 11A  employing the pull-up and pull-down circuits of  FIG. 5 ; 
         FIG. 11C  illustrates IV curves representing the output impedance characteristics of the driver shown in  FIG. 11A  employing the pull-up and pull-down circuits of  FIGS. 7 and 9 ; 
         FIG. 12  illustrates another embodiment of a driver contained in the IO device of microprocessor of  FIG. 4 ; and 
         FIG. 13  is a schematic diagram of one embodiment of the level converter circuit employed in the drivers of  FIGS. 4 ,  6 ,  8  and  9 . 
     
    
    
     While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. However, the drawings and detailed description thereto are not intended to limit the invention to the particular form disclosed. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the present invention as defined by the appended claims. 
     DETAILED DESCRIPTION 
     Computer systems, including computer servers, employ one or more microprocessors coupled to one or more memory devices via a serial or parallel data bus. The present invention will be described with reference to a microprocessor coupled to a memory device via a parallel data bus, it being understood that the present invention should not be limited thereto. The term device (e.g., microprocessors, memory, FETs, etc.) includes circuits of transistors coupled together to perform a function. As used herein, devices can be coupled together either directly, i.e., without any intervening device, or indirectly, with one or more intervening devices. As used herein the term connected devices means two or more devices directly connected together without any intervening circuit via one or more conductors. The term coupled includes the term connected within its definition. 
       FIG. 4  is a block diagram of a microprocessor  32  coupled to memory device  34  via a data bus  36 . Although not shown, data bus  36  includes a plurality of conductive lines coupled between microprocessor  32  and memory device  34 . Microprocessor  32  includes a plurality of IO devices (not shown in  FIG. 4 ) coupled to respective conductive lines of data bus  14 . 
       FIG. 5  shows a schematic diagram of an exemplary driver  40  that may be used in one or more of the IO devices of microprocessor  32 . Driver  40  drives one of the conductive lines of data bus  36  in response to receiving an input data bit signal. Driver  40  includes a pull-up stage circuit  42 , pull-down stage circuit  44 , and a voltage level converter circuit  46 . The operational aspects of circuit  46  will be more fully described below. Lastly, driver  40  includes an input node  50  and an output node  52 . Although not shown, output node  52  is coupled to one of the conductive lines of data bus  36 . 
     Pull-up stage  42  includes a pair of p-channel FETs  60  and  62 , while pull-down stage  44  includes a pair of n-channel FETs  64  and  66 . The source of p-channel FET  60  is coupled to V dd—h  while the gate of p-channel FET  60  is coupled to the output of level converter circuit  46 . V dd—h  is a supply voltage. The source of p-channel FET  62  is coupled to the drain of p-channel FET  60 , while the gate of p-channel FET  62  is coupled to a direct current (DC) voltage V p . The drains of p-channel FET  62  and n-channel FET  64  are coupled together and to output node  52 . The source of n-channel FET  64  is coupled to the drain of n-channel FET  66 . The source of n-channel FET  66  is coupled to V cg . The gate of n-channel FET  64  is coupled to a DC voltage V n . The gate of n-channel FET  66  is coupled to input node  50 . 
     In operation, input node  50  receives an input data bit signal D in  directly or indirectly from the core of microprocessor  32 . Although not shown, D in  is provided to input node  50  by an inverter gate or other circuit for inverting the binary state of a data bit signal. The input data bit signal D in  varies between two voltage levels V dd  or V cg  representing a binary one or a binary zero, respectively. In response to receiving D in , driver  40  charges or discharges output node  52  and the conductive line of data bus  36  coupled thereto. When driver  40  receives D in  equal to V cg , driver  40  drives or charges output node  52  to V dd—h . When driver  40  receives D in  equal to V dd , driver  40  drives or discharges output node  52  to V cg . In this manner, driver  40  generates an output data bit signal D out  at output node  52  that varies between V dd—b  and V cg  in response to receiving input data bit signal D in  that varies between V dd  and V cg . 
     It is noted that driver  40  may receive D in  with voltage levels that vary between a voltage that is slightly lower than V dd  and a voltage that is slightly higher than V cg . Further, it is noted that driver  40  may charge output node  52  to a voltage slightly lower than V dd—h  or discharge output node  52  to a voltage slightly greater than V cg . However, for purposes of explanation, it will be presumed that D in  varies between V dd  and V cg  and that driver  40  charges and discharges output node  52  to V dd—h  and V cg , respectively. 
     V dd—h  and V dd  are supply voltages. Each may be provided from one or more sources external to microprocessor  32 . V cg  is common ground or a voltage less than V dd—h  and V dd . V dd—h  is greater than V dd  and V limit , the gate oxide voltage of devices  60 - 66 . V limit  is described in the background section above. 
     In one embodiment, V n  is distinct from V p . In another embodiment, V n  and V p  are the same. For purposes of explanation, V n  is presumed distinct from V p  In general V n  and V p  are subject to the following restrictions:
 
 V   limit   &gt;V   p   &gt;V   dd—h   −V   limit   (1)
 
  V   limit   &gt;V   n   &gt;V   dd—h   —V   limit   (2)
 
     Voltage level converter circuit  46  is coupled to input node  50  and receives input data bit signal D in  therefrom. In response to receiving D in , converter circuit  46  generates a modified input data bit signal D mod  that varies between voltages V dd—h  and an intermediate voltage V int  representing binary one and binary zero, respectively. V int  is subject to the following limitations:
 
 V   dd—h   −V   t   &gt;V   int   &gt;V   dd—h   −V   limit   (3) 
 
Circuit  46  generates D mod  equal to V dd—h  in response to receiving D in  equal to V dd , and circuit  46  generates D mod  equal to V int  in response to receiving D in  equal to V cg .
 
     Further operational aspects of driver  40  shown in  FIG. 5  will be explained with reference to the timing diagram shown in FIG.  6 . At time t=0, the voltage level of D in  equals V cg . With D in  equal to V cg , n-channel FET  66  is inactive thereby decoupling output node  52  from V cg . Circuit  46  generates D mod  equal to V int  in response to receiving D in  equal to V cg . Because V int &lt;V dd—h −V t , p-channel FET  60  is active and charges the drain and source of p-channel FETs  60  and  62 , respectively, to V dd—h . With both the drain and source of p-channel FET  60  charged to V dd—h  and with the constraints on V int  imposed by equation (3) above, V gs  and V gd  of p-channel FET  60  are both less than V limit , and p-channel FET  60  should not experience the damage described in the background section above. 
     As noted above, the source of p-channel FET  62  is charged to V dd—h . V p  is less than V dd—h −V t , and, as a result p-channel FET  62  activates. With p-channel FETs  60  and  62  active and with at least n-channel FET  66  inactive, output node  52 , and thus the conductive line of data bus  36  coupled to output node  52 , is charged to V dd—h . Additionally, the drain of p-channel FET  62  and the drain of n-channel FET  64  are also charged to V dd—h . With both the drain and source of p-channel FET  62  charged to V dd—h  and with the constraints on V p  imposed by equation (1) above, both V gs  and V gd  of p-channel FET  62  are less than V limit , and p-channel FET  62  should not experience the damage described in the background section above. 
     As will be more fully described below, the source of n-channel FET  64  and the drain of n-channel FET  66  are charged to V n −V t . With the drain and source of n-channel FET  66  charged to V n −V t  and V cg , respectively, with the gate of n-channel FET  66  at V cg , and with the constraints on V n  imposed by equation (2) above, both V gs  and V gd  of n-channel FET  66  are less than V limit , and n-channel FET  66  should not experience the damage described in the background section above. Further, with the drain and source of n-channel FET  64  charged to V dd—h  and V n −V t , respectively and with the constraints on V n  imposed by equation (2) above, both V gs  and V gd  of n-channel FET  64  are less than V limit , and n-channel FET  66  should not experience the damage described in the background section above. 
     With continuing reference to  FIGS. 5 and 6 , at time t=t 1 , D in  changes to V dd . In response shortly thereafter, D mod  generated by circuit  42  changes to V dd—h , which in turn deactivates p-channel FET  60 . Output node  52  is disconnected from V dd—h  when FET  60  deactivates. Also at time t=t 1 , n-channel FET  66  activates in response to D in  changing to V dd  and FET  66  discharges the drain of n-channel FET  66  and the source of n-channel FET  64  to V cg . With the source and drain of n-channel FET  66  at V cg  and with the gate of n-channel FET  66  at V dd , V gs  and V gd  of n-channel FET  66  are less than V limit . 
     With the source voltage of n-channel FET  64  at V cg  and with V n  greater than V cg +V t , n-channel FET  64  activates. With n-channel FETs  64  and  66  active, and with p-channel FET  60  inactive as noted above, output node  52  discharges to V cg . Additionally, the drains of n-channel FET  64  and the p-channel FET  62  discharge to V cg . With the source and drain of n-channel FET  64  at V cg , and with the constraints imposed on V n  by equation (2), both V gs  and V gd  of n-channel FET  64  are less than V limit , and n-channel FET  64  should not experience the damage described in the background section above. 
     As noted above, p-channel FET  60  is deactivated shortly after time t=t 1 . While p-channel FET  62  is still activated and while p-channel FET  60  is deactivated, the source of p-channel FET  62 , and thus the drain of p-channel FET  60 , discharges until it reaches V p +V t . Once the source of p-channel FET  62  reaches V p +V t , p-channel FET  62  deactivates. At that point, and with the constraints on V p  imposed by equation (1) above, both V gs  and V gd  of p-channel FETs  60  and  62  are less than V limit . 
     At time t=t 2 , D in  changes back to V cg , and in response n-channel FET  66  deactivates thereby disconnecting output node  52  from V cg . Circuit  42 , also in response to the change in D in , generates D mod  equal to V int . With D mod  equal to V int , p-channel FET  60  again activates and the source of p-channel FET  62  is charged to V dd—h . V p  activates p-channel FET  62 , and the drain of p-channel FET  62 , the drain of n-channel FET  64  and output node  52  are charged to V dd—h . N-channel FET  64  remains activated until its source is charged to V n +V t . When the source of n-channel FET  64  reaches V n +V t , n-channel FET  64  is deactivated. The voltages at the nodes of FETs  60 - 66  return to the state they were shortly after time t=t 0 , at which point V gs  and V gd  of the FETs  60 - 66  do not exceed V limit . 
     Driver  40  charges or discharges output node  52 , and thus the conductive line of data bus  36  and the memory device  34  coupled thereto, in accordance with the input data bit signal D in . Driver  40  is similar to driver  16  described above, in that the output impedance of driver  40  varies with its output voltage, temperature, and/or magnitude of V dd—h . In other words, the IV characteristics of driver  40  are similar to that shown in FIG.  4 . The non-linearity of driver  40  output impedance can be improved.  FIG. 7  shows driver  40  of  FIG. 5  with p-channel FETs  70  and  72 , and n-channel FETs  74  and  76  added to pull-up stage  42  and pull-down stage  44 , respectively. More particularly p-channel FETs  70  and  72  are connected in series, and the combination of p-channel FETs  70  and  72  is coupled in parallel with p-channel FET  62 . Likewise, n-channel FETs  74  and  76  are connected in series, and the combination of n-channel FETs  74  and  76  is coupled in parallel with n-channel FET  64 . The combination of p-channel FETs  70  and  72  and n-channel FETs  74  and  76  represent one embodiment of a circuit for improving the linearity of the output impedance of a driver including driver  40  shown in FIG.  5 .  FIG. 8  illustrates an IV curve that characterizes the output impedance of driver  40  of  FIG. 7  operating at constant temperature and V dd—h  magnitude. As can be seen in  FIG. 8 , the current I generated by driver  40  varies linearly or substantially linearly with voltage V at output node  52 . The increased linear relationship exists for at least a predetermined range of driver  40  output voltages V. Because I varies linearly or in a substantial linear relationship with V, the output impedance of driver  40  shown in  FIG. 7  is substantially constant as output voltage V varies. The illustration of  FIG. 8  presumes that no load is applied to output node  52 . 
     The output impedance of driver  40  of  FIG. 7  is proportional to the slope of the IV curve shown in FIG.  8 . The slope of the IV curve is dependent on the sizes of the FETs  60 - 66  and  70 - 76 . Computer simulation can be used to calculate the output impedance of driver  40  shown in FIG.  7 . More particularly, computer simulation can be used to adjust the sizes of FETs  60 - 66  and  70 - 76  so that the output impedance of driver  40  is made to match or substantially match the combined impedance of the memory device and the conductive line coupled to output node  52 . With FETs  60 - 66  and  70 - 76  properly sized, the output impedance of driver  40  equals or substantially equals the combined impedance of memory device  34  and the conductive line coupled to output node  52 , and driver  40  should not experience the same degradation or limitation of abilities to transmit data bit signals as would be expected by driver  16  of  FIG. 2  or driver  40  of FIG.  5 . 
       FIG. 9  illustrates an extension of the driver  40  shown in FIG.  7 . More particularly,  FIG. 9  shows the driver  40  of  FIG. 7  along with diode connected p-channel FETs  80  and  82 , and diode connected n-channel FETs  84  and  86  added to pull-up circuit  42  and pull-down circuit  44 , respectively. Diode connected p-channel FETs  80  and  82  are substantially smaller in size when compared to p-channel FET  60 , and diode connected n-channel FETs  84  and  86  are substantially smaller in size when compared to n-channel FET  66  such that the amount of current passed by FETs  80 - 86  is substantially smaller than the current passed by devices  60  and  66  when active. 
     Diode connected p-channel FETs  80  and  82  and diode connected n-channel FETs  84  and  86  operate to protect devices  60  and  66 , respectively. Capacitance coupling or other mechanisms may cause the voltage at the common node between FETs  60  and  62  to fall below V dd—h  by more than V limit . Diode connected p-channel FETs  80  and  82  allow a small current to charge this common node thus ensuring the voltage at the common node doesn&#39;t fall more than V limit  below V dd—h . Likewise, capacitance coupling or other mechanisms may cause the voltage at the common node between FETs  64  and  66  to increase beyond V limit . Diode connected n-channel FETs  84  and  86  allow a small current to discharge the common node between FETs  64  and  66  thus ensuring the voltage at this node doesn&#39;t beyond V limit . It is noted that a single diode connected p-channel FET between V dd—h  and the common node between FETs  60  and  62  may also ensure that the voltage at this node does not fall more than V limit  below V dd—h , and that a single diode connected n-channel FET between V cg  and the common node between FETs  64  and  66  may also ensure that the voltage at this node does not beyond V limit . 
       FIG. 10  illustrates another driver  40  that may be employed in the microprocessor  32  shown in FIG.  4 .  FIG. 10  also shows a pull-up control code generator  132  and a pull-down control code generator  134 . Driver  40  shown in  FIG. 10  includes any of the pull-up circuits  42  and/or any of the pull-down circuits  44  illustrated in  FIG. 5 ,  7 , or  9 . Additionally, driver  40  shown in  FIG. 10  includes pull-up capacitors  140 ( 0 )- 140 ( 7 ), pull-down capacitors  142 ( 0 )- 142 ( 7 ), pull-up switches  144 ( 0 )- 144 ( 7 ), pull-down switches  146 ( 0 )- 146 ( 7 ), and inverting buffers  150  through  162 . Although not shown, it is noted that additional components may be included within the driver  40  shown in FIG.  10 . 
     Driver  40  shown in  FIG. 10  will be described as having eight pull-up capacitors  140 ( 0 )- 140 ( 7 ), eight pull-down capacitors  142 ( 0 )- 142 ( 7 ), eight pull-up switches  144 ( 0 )- 144 ( 7 ), and eight pull-down switches  146 ( 0 )- 146 ( 7 ). It is noted that a larger or smaller number of capacitors and switches may be employed in driver  40  of FIG.  10 . It is also noted that, unlike drivers  40  shown in  FIGS. 5 ,  7 , and  9 , D in  is not provided to driver  40  of  FIG. 10  by an inverter or other circuit for inverting the state of a data bit signal. 
     Each of the pull-up and pull-down capacitors is coupled between V cg  and a respective switch. For example, pull-up capacitors  140 ( 0 ) is coupled between switch  144 ( 0 ) and V cg , and pull-down capacitor  142 ( 0 ) is coupled between switch  146 ( 0 ) and V cg . The size of pull-up and pull-down capacitors may vary. For example, each of pull-up capacitors  140 ( 0 )- 140 ( 7 ) may be different from each other in capacitive size, and each of pull-down capacitors  142 ( 0 )- 142 ( 7 ) may be different from each other in capacitive size. Alternatively, the sizes of pull-up and pull-down capacitors may be identical. 
     Pull-up switches  144 ( 0 )- 144 ( 7 ) and pull-down switches  146 ( 0 )- 146 ( 7 ) may take form in one or more FETs. In the embodiment shown, each of the pull-up switches  144 ( 0 )- 144 ( 7 ) and pull-down switches  146 ( 0 )- 146 ( 7 ) take form in an n-channel FET and a p-channel FET coupled in parallel between a respective capacitor and node  170  or node  172 . The gates of the FETS of pull-up switch FETs  144 ( 0 )- 144 ( 7 ) are coupled to pull-up control code generator  132 , and the gates of the FETs of the pull-down switch FETs  146 ( 0 )- 146 ( 7 ) are coupled to the pull-down control code generator  134 . Pull-up control code generator  132  and pull-down control code generator  134  generate a multibit pull-up control code (PUCC( 0 )-PUCC( 7 )) and a multibit pull-down control code (PDCC( 0 )-PDCC( 7 )), respectively. The n-channel FETs of pull-up switches  144 ( 0 ) through  144 ( 7 ) are controlled by PUCC( 0 )-PUCC( 7 ), respectively, the p-channel FETs of pull-up switches  144 ( 0 ) through  144 ( 7 ) are controlled by the inverse of PUCC( 0 )-PUCC( 7 ), respectively, the n-channel FETs of pull-down switches  146 ( 0 ) through  146 ( 7 ) are controlled by PDCC( 0 )-PDCC( 7 ), respectively, and the p-channel FETs of pull-down switches  146 ( 0 ) through  146 ( 7 ) are controlled by the inverse of PDCC( 0 )-PDCC( 7 ), respectively. At any point in operation of driver  40  shown in  FIG. 10 , none, some or all of pull-up switches  144 ( 0 )- 144 ( 7 ) may be closed in response to receiving PUCC( 0 )-PUCC( 7 ) (and its inverse) from pull-up control code generator  132 . Likewise, at any point in time in the operation of driver  40  shown in  FIG. 10 , none, some, or all of the switches  146 ( 0 )- 146 ( 7 ) may be closed in response to receiving PDCC( 0 )-PDCC( 7 ) (and its inverse) provided by the pull-down control code generator  134 . 
     Pull-up control code generator  132  and pull-down control code generator  134  each generate the pull-up control code PUCC( 0 )-PUCC( 7 ) and pull-down control code PDCC( 0 )-PDCC( 7 ), respectively, in response to comparing an output impedance of a driver, such as driver  40  shown in  FIG. 11A  (more fully described below), against a known impedance. The output impedance of this driver is controlled by the pull-up and pull-down control codes such that when the pull-up control code PUCC( 0 )-PUCC( 7 ) increases (e.g., from 00000011 to 00000111), the output impedance of the driver decreases and vice-versa, and when the pull-down control code decreases (e.g., from 01111111 to 00111111), the output impedance of the driver decreases and vice-versa. The pull-up and pull-down control codes are adjusted until the output impedance of the driver compares substantially equal to the know impedance. If the output impedance of the driver increases or decreases due to variations in, for example, power supply voltage V dd—h  provided to the driver or temperature T of the driver, then the pull-up and/or pull-down control codes adjust accordingly. It is noted that PUCC( 0 )-PUCC( 7 ) may be distinct from PDCC( 0 )-PDCC( 7 ) at any point in time. U.S. Pat. No. 6,060,907 describes embodiments of pull-up control code generator  132  and/or pull-down control code generator  134 , and is incorporated herein by reference in its entirety. 
     Inverting buffers  150  through  154  are coupled between input node  50  and level converter circuit  46 . Likewise, inverting buffers  156  through  162  are coupled between input node  50  and pull-down circuit  44 . Switches  144 ( 0 )- 144 ( 7 ) are coupled to node  170  between inverting buffers  150  and  152  as shown in FIG.  10 . Likewise, switches  146 ( 0 )- 146 ( 7 ) are coupled to node  172  between inverting buffers  156  and  160 . The transmission delay of signals between inverters  150  and  152  depends on the number of capacitors  140 ( 0 )- 140 ( 7 ) coupled to node  170  via respective switches  144 ( 0 )- 144 ( 7 ), respectively. Likewise, the transmission delay of signals between inverting buffers  156  and  160  depends upon the number of capacitors  142 ( 0 ) through  142 ( 7 ) coupled to the transmission path between inverting buffers  156  and  160  via switches  146 ( 0 ) through  146 ( 7 ), respectively. 
     As noted above, pull-up control code generator  132  and pull-down control code generator  134  generate PUCC( 0 )-PUCC( 7 ) and PDCC( 0 )-PDCC( 7 ), respectively, based indirectly upon T and/or V dd—h . PUCC( 0 )-PUCC( 7 ) and PDCC( 0 )-PDCC( 7 ) are generated to ensure that driver  40  of  FIG. 10  charges or discharges output node  52  during predetermined timing windows defined by the specifications for data bus  36 . For example, if the temperature T increases beyond a predetermined temperature, the time it takes pull-up circuit  42  and pull-down circuit  44  to fully charge or discharge output node  52  in response to receiving D in , will be delayed when compared to the time it takes pull-up circuit  42  and pull-down circuit  44  to fully charge or discharge output node  52  when T equals the predetermined temperature. With the temperature T greater than the predetermined value, pull-up control code generator  132  and pull-down control code generator  134  may generate PUCC( 0 )-PUCC( 7 ) and PDCC( 0 )-PDCC( 7 ), respectively, which opens one or more switches  144 ( 0 )- 144 ( 7 ) and  146 ( 0 )- 146 ( 7 ) to offset the delay caused by the increased temperature T. 
     As noted in its background section, the output impedance of driver  16  shown in  FIG. 3  is subject to unexpected variations due to changes in temperature during operation and/or changes in the magnitude of supply voltage V dd . Additionally, as noted above, the actual output impedance of driver  16  operating at a predetermined temperature and magnitude of V dd—h  may not match the expected output impedance of driver due to unexpected variations in the physical structure of FETs  20  and  22  which occurred during the manufacturing process. The output impedance of driver  40  shown in  FIGS. 5 ,  7 ,  9 , and  10  is also subject to these variations.  FIG. 11A  illustrates another embodiment of driver  40  that may be employed in the microprocessor  32  of FIG.  4 . Driver  40  has the capability to dynamically change its output impedance. 
     Driver  40  shown in  FIG. 11A  includes a plurality of pull-up circuits  42 A and  42 ( 0 )- 42 ( 7 ), and a plurality of pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ). Driver  40  of  FIG. 11A  also includes a plurality of level converter circuits  46 A and  46 ( 0 )- 46 ( 7 ). Lastly, driver  40  of  FIG. 11A  includes a plurality of logic gates including inverters  92  and  94 , nand gates  100 ( 0 )- 100 ( 7 ) and nor gates  102 ( 0 )- 102 ( 7 ). It is also noted that, unlike drivers  40  shown in  FIGS. 5 ,  7 , and  9 , D in  is provided to driver  40  of  FIG. 11A  without first passing through an inverter or other circuit for inverting the state of a data bit signal.  FIG. 11A  also shows pull-up control code generator  182  and pull-down control code generator  184 , which will be more fully described below. 
     Each of the pull-up base circuits  42 A and  42 ( 0 )- 42 ( 7 ) may take form in any of the pull-up circuits  42  shown in  FIGS. 5 ,  7 , and  9 . Likewise, any of the pull-down circuits  44   a  and  44 ( 0 )- 44 ( 7 ) may take form in any of the pull-down circuits  44  shown in  FIG. 5 ,  7 , or  9 . The level converter circuits  46 A and  46 ( 0 )- 46 ( 7 ) operate in a manner substantially similar to the converter circuit  46  described in  FIGS. 5 ,  7 , and  9 . A more detailed embodiment of the level converter circuit will be described below. 
     Nand gates  100 ( 0 )- 100 ( 7 ) are coupled to the pull-up control code generator  182  shown in  FIG. 10 , and configured to receive pull-up control code PUCC( 0 )-PUCC( 7 ), respectively, therefrom. Each of the nand gates  100 ( 0 )- 100 ( 7 ) is also coupled to input node  50  and configured to receive the input data bit signal D in . Nor gates  102 ( 0 )- 102 ( 7 ) are coupled to pull-down control code generator  184  shown in FIG.  10  and configured to receive the logical inverse of pull-down control code PDCC( 0 )-PDCC( 7 ), respectively, therefrom. Nor gates  102 ( 0 )- 102 ( 7 ) are also coupled to input node  50  and configured to receive input data bit signal D in . 
     Inverters  92  and  94  are coupled to input node  50  and configured to receive data bit signal D in . The output of inverter  92  is received by level converter circuit  46 A. The output of inverter  94  is received by pull-down circuit  44 A. The outputs of pull-up circuits  42 A and  44 ( 0 )- 42 ( 7 ) and pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ) are coupled to output node  52 . 
     In operation, driver  40  shown in  FIG. 11A  charges or discharges output node  52 , and any data bus transmission line or memory device coupled thereto, to V dd—h  or V cg , respectively, in response to input node  50  receiving input data bit signal D in  that varies between V dd  and V cg . Pull-up control code generator  182  selectively enables one or more of the pull-up circuits  42 ( 0 )- 42 ( 7 ) and level converters  46 ( 0 )- 46 ( 7 ) via nand gates  100 ( 0 )- 100 ( 7 ). It is noted that in the embodiment shown, pull-up circuit  42 A and level converter  46 A are permanently enabled. However, driver  40  of  FIG. 11A  could be modified so that pull-up circuit  42 A and level converter  46 A are also selectively enabled. 
     When enabled, level converters  46 A and  46 ( 0 )- 46 ( 7 ) generate D mod  equal to V dd—h  or V int  when D in  equals V cg  and V dd , respectively. When disabled, level converters  46 ( 0 )- 46 ( 7 ) generate D mod  equal to V dd—h  regardless of D in . When enabled, pull-up circuits  42 A and  42 ( 0 )- 42 ( 7 ) operate in the active or inactive state when D mod  equals V int  or V dd—h , respectively. When active, each pull-up circuit drives output node  52  to V dd—h . When inactive, each pull-up circuit is incapable of driving output node  52 . When disabled, each of the pull-circuits  42 ( 0 )- 42 ( 7 ) operates only in the inactive state. 
     Pull-up control code bits PUCC( 0 )-PUCC( 7 ) equal V dd  or V cg  representing a logical one or logical zero, respectively. As will be appreciated by one of ordinary skill in the art, pull-up circuits  42 ( 0 )- 42 ( 7 ) and corresponding level converters  46 ( 0 )- 46 ( 7 ) will be enabled when respective nand gates  100 ( 0 )- 100 ( 7 ) receive a pull-up control code bit that equals V dd . 
     Pull-down control code generator  184  selectively enables one or more of the pull-down circuits  44 ( 0 )- 44 ( 7 ) via nor gates  102 ( 0 )- 102 ( 7 ). It is noted that in the embodiment shown, pull-down circuit  44 A is permanently enabled. However, driver  40  of  FIG. 11A  could be modified so that pull-down circuit  44 A is also selectively enabled. 
     When enabled, pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ) operate in the active or inactive state when D in  equals V dd  or V cg , respectively. When active, each pull-down circuit drives output node  52  to V cg . When inactive, each pull-down circuit is incapable of driving output node  52 . When disabled, each of the pull-down circuits  44 ( 0 )- 44 ( 7 ) operates only in the inactive state. 
     Pull-down control code bits PDCC( 0 )-PDCC( 7 ) equal V dd  or V cg  representing a logical one or logical zero, respectively. As will be appreciated by one of ordinary skill in the art, pull-down circuits  44 ( 0 )- 44 ( 7 ) will be enabled when respective nor gates  102 ( 0 )- 102 ( 7 ) receive a pull-down control code bit that equals V cg . 
     As noted above, parameters of driver  40  may change during operation thereof. For example, the operating temperature of driver  40  may increase or decrease from a predetermined value, or the magnitude of supply voltage V dd—h  may increase or decrease from a predetermined value. A change in operating parameters may affect the output impedance of driver  40 . Additionally, as noted above, unexpected physical variations in the FETs of driver  40  may affect its output impedance. 
       FIG. 11B  shows IV Curves C normal , C high  and C low  representing output impedance of the driver  40  shown in  FIG. 11A  when pull-up circuits  42 A and  42 ( 0 )- 42 ( 7 ) take form in the pull-up circuit  42  shown in FIG.  5  and when pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ) take form in the pull-down circuit  44  also shown in FIG.  5 .  FIG. 11C  shows IV curves C normal , C high  and C low  illustrating output impedance of the driver  40  shown in  FIG. 11A  when pull-up circuits  42 A and  42 ( 0 )- 42 ( 7 ) take form in the pull-up circuit  42  shown in  FIG. 7  or  9 , and when pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ) take form in the pull-down circuit  44  also shown in  FIG. 7  or  9 . As noted above, temperature, magnitude of V dd—h , and/or unexpected physical variations in the FETs may affect the expected output impedance of driver  40 . C normal  represents the expected output impedance of driver  40  of  FIG. 10  with driver  40  operating at a predetermined temperature, with V dd—h  provided at a predetermined magnitude, and with the FETs of driver  40  manufactured without unexpected physical variations. Driver  40  produces output impedance represented by C normal  in response to receiving a first PUCC( 0 )-PUCC( 7 ) and a first PUCC( 0 )-PDCC( 7 ) generated by pull-control code generator  182  and pull-down control code generator  184 , respectively. 
     C high  represents the output impedance of driver  40  with the operating temperature of driver  40  below a predetermined value, with the magnitude of supply voltage V dd—h  above a predetermined value, and/or with unexpected physical variations in the FETs of Driver  40 . C low  represents the output impedance of driver  40  with the operating temperature of driver  40  above a predetermined value, with the magnitude of supply voltage V dd—h  below a predetermined value, and/or with unexpected physical variations in the FETs of Driver  40 . C high  and C low  also result when the first PUCC( 0 )-PUCC( 7 ) and the first PDCC( 0 )-PDCC( 7 ) are provided to driver  40  of FIG.  11 A. 
     As noted above, driver  40  of  FIG. 11A  is coupled to the pull-up control code generator  182  and the pull-down control code generator  184 . In one embodiment, pull-up control code generator  182  and the pull-down control code generator  184  may operate similar to the pull-up control code generator  132  and the pull-down control code generator  134 , respectively, described in FIG.  10 . Indeed, as an alternative embodiment, driver  40  of  FIG. 11A  may be coupled to pull-up control code generator  132  and the pull-down control code generator  134 . 
     Pull-up control code generator  182  and pull-down control code generator  184  directly or indirectly monitor the output impedance of driver  40 . Should the output impedance of driver  40  deviate from that defined by C normal  due to changes in operating temperature of driver  40  and/or changes in magnitude of V dd—h , pull-up control code generator  182  and/or pull-down control code generator  184  may generate new PUCC( 0 )-PUCC( 7 ) and PDCC( 0 )-PDCC( 7 ), respectively. For example, the output impedance of driver  40  shown in  FIG. 11A  may drift down to that represented by C low  as a result of an increase in operating temperature and/or a decrease in the magnitude of supply voltage V dd—h . In response, pull-up control code generator  182  and/or pull-down control code generator  184  may generate new PUCC and/or PDCC, respectively. The new PUCC and/or PDCC may enable and/or disable one or more of the pull-up circuits  42 ( 0 )- 42 ( 7 ) and/or pull-down circuits  44 ( 0 )- 44 ( 7 ) to increase the output impedance to that defined by C normal . Similarly, output impedance of driver  40  shown in  FIG. 11A  may drift up to that defined by C high  as a result of a decrease in operating temperature T and/or an increase in the magnitude of supply voltage V dd—h . In response, pull-up control code generator  182  and/or pull-down control code generator  184  may generate new PUCC( 0 )-PUCC( 7 ) and/or PDCC( 0 )-PDCC( 7 ), respectively that enable and/or disable one or more of the pull-up circuits  42 ( 0 )- 42 ( 7 ) and/or pull-down circuits  44 ( 0 )- 44 ( 7 ) to decrease the output impedance to that represented by C normal . 
     Pull-up circuits  42 A and  42 ( 0 )- 42 ( 7 ) are distinct from each other in one embodiment. For example, pull-up circuit  42 A may have higher drive strength when compared to pull-up circuits  42 ( 0 )- 42 ( 7 ). Pull-up circuit  42 A may include FETs  60  and  62  that are larger in size when compared to the FETs  60  and  62  of pull-up circuits  42 ( 0 )- 42 ( 7 ). Pull-up circuits  42 ( 0 )- 42 ( 7 ) may vary in their drive strengths from pull-up circuit  42 ( 0 ) having relatively high drive strength to pull-up circuit  42 ( 7 ) having relatively low drive strength. 
     Likewise, pull-down circuits  44 A and  44 ( 0 )- 44 ( 7 ) are distinct from each other in one embodiment. For example, pull-down circuit  44 A may have a higher drive strength when compared to pull-down circuits  44 ( 0 )- 44 ( 7 ). Pull-down circuit  44 A may include FETs  64  and  66  that are larger in size when compared to the FETs  64  and  66  of pull-down circuits  44 ( 0 )- 44 ( 7 ). Pull-down circuits  44 ( 0 )- 44 ( 7 ) may vary in their drive strengths from pull-down circuit  44 ( 0 ) having relatively high drive strength to pull-down circuit  44 ( 7 ) having relatively low drive strength. 
       FIG. 12  illustrates another embodiment of driver  40  that can be employed in the microprocessor  32  shown in FIG.  4 .  FIG. 12  represents a merger of the drivers  40  shown in  FIGS. 10 and 11A . Driver  40  shown in  FIG. 12  operates substantially similar to that described in FIG.  11 A. Additionally, driver  40  has the added ability to ensure that driver  40  charges or discharges output node  52  during predetermined timing windows defined by the specifications for data bus  36  shown in FIG.  4 . In one embodiment, the pull up control code PUCC( 0 )-PUCC( 7 ) provided to switches  144 ( 0 )- 144 ( 7 ) and the pull down control code PDCC( 0 )-PDCC( 7 ) provided to switches  142 ( 0 )- 142 ( 7 ) are provided by pull up control code generator  132  and pull down control code generator  134 , respectively, described with reference to FIG.  10 . Further, the pull up control code PUCC( 0 )-PUCC( 7 ) provided to nand circuits  100 ( 0 )- 100 ( 7 ) and the pull down control code PDCC( 0 )-PDCC( 7 ) provided to nor gates  102 ( 0 )- 102 ( 7 ) are provided by pull up control code generator  182  and pull down control code generator  184 , respectively, described with reference to FIG.  11 A. Alternatively, pull up control code generator  132  or pull up control code generator  182  may provide pull up control code PUCC( 0 )-PUCC( 7 ) to both the switches  144 ( 0 )- 144 ( 7 ) and nand gates  100 ( 0 )- 100 ( 7 ) while either pull down control code generator  134  or pull down control code generator  184  provides pull down control code PDCC( 0 )-PDCC( 7 ) to both switches  143 ( 0 )- 143 ( 7 ) and nor gates  102 ( 0 )- 102 ( 7 ). 
       FIG. 13  is a schematic diagram of one embodiment of the voltage level converter  46  which can be used in any of the embodiments shown herein. Other embodiments are contemplated.  FIG. 13  shows level converter circuit  46  having n-channel and p-channel FETs coupled between an input node  232  and an output note  234 . Input node  232  is configured to receive D in  which, as noted above, varies between V dd  and V cg . Circuit  46 , as noted above, generates D mod  at output node  234 . Output node  234  is coupled to the gate of p-channel FET  60  shown in, for example,  FIGS. 5 and 7 . 
     In the embodiment shown in  FIG. 13 , circuit  46  includes an inverter  236  having a p-channel FET  242  coupled to an n-channel FET  244 . The gates of FETs  242  and  244  are coupled to input node  232 , while the sources of FETs  242  and  244  are coupled to V dd  and V cg , respectively. The remaining FETs of circuit  46  are divided among substantially symmetric circuits  246 L and  246 R. More particularly, circuit  246 L includes n-channel FETs  250 L- 264 L and p-channel FET  266 L, while circuit  246 R includes n-channel FETs  250 R- 264 R and p-channel FET  266 R. 
     N-channel FETs  264 L and  264 R are arranged as drain connected diodes coupled to supply voltage V dd—h . P-channel FETs  266 L and  266 R are cross-coupled with the gate of p-channel FET  266 L coupled to the drain of p-channel FET  266 R, and with the gate of p-channel FET  266 R coupled to the drain of p-channel FET  266 L. As shown in  FIG. 12 , the sources of p-channel FETs  266 L and  266 R are coupled to V dd—h . Output node  234  is coupled to the drain of p-channel FET  266 R. 
     A pair of diode connected n-channel FETs  260 R and  262 R are coupled between n-channel FET  256 R and p-channel FET  266 R. Likewise, circuit  246 L includes a pair of diode connected n-channel FETs  260 L and  262 L coupled between n-channel FET  256 L and p-channel FET  266 L. 
     The gates of n-channel FETs  256 L and  256 R are coupled to a DC voltage V ok . Voltage V ok  is subject to the following limitations:
 
 V   dd−h   −V   limit   &lt;V   ok   &lt;V   cg   +V   limit   (5) 
 
     Lastly, circuits  246 L and  246 R include n-channel FETs  250 L through  254 L and  250 R- 254 R, respectively. N-channel FETs  250 L and  254  are connected as diodes in series, the combination of which is connected in parallel with n-channel FET  252 L. Likewise, n-channel FETs  250 R and  254 R are connected as diodes in series, the combination of which is connected in parallel with n-channel FET  252 R. The sources of n-channel FETs  252 L and  252 R are coupled to V cg , while the gates of n-channel FETs  252 L and  252 R are coupled to the input node  232  and the output of inverter  236 , respectively. 
     Although the present invention has been described in connection with several embodiments, the invention is not intended to be limited to the specific forms set forth herein. On the contrary, it is intended to cover such alternatives, modifications, and equivalents as can be reasonably included within the spirit and scope of the invention as defined by the appended claims.