Patent Publication Number: US-10312195-B2

Title: Fan-out semiconductor package

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application claims benefit of priority to Korean Patent Application No. 10-2017-0089722 filed on Jul. 14, 2017 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to a semiconductor package, and more particularly, to a fan-out semiconductor package in which connection terminals may extend outwardly of a region in which a semiconductor chip is disposed. 
     BACKGROUND 
     When a wiring design of a semiconductor package is observed, ground patterns disposed in order to dissipate heat or return signals may be confirmed, in addition to signal patterns, which are fine circuit, disposed in order to transfer the signals. Since a remaining rate of a copper foil is very high in a ground region, a risk of interlayer delamination is high. In order to solve such a problem, a degas design having a circular or linear shape is reflected in a design to improve close adhesion between an insulating layer and the copper foil and allow a degas component discharged from a lower insulating layer to be easily discharged. 
     However, such a degassing hole is filled with an insulating material, such that an insulating layer dent phenomenon may occur in a surface of an insulating layer. In this case, patterns disposed on the insulating layer are broken or close adhesion between the insulating layer and a dry film resist is reduced due to a step of the surface of the insulating layer. Resultantly, a plating solution permeates into the insulating layer and the dry film resist, such that a defect such as a short-circuit may occur. 
     SUMMARY 
     An aspect of the present disclosure may provide a fan-out semiconductor package in which a problem in which a signal pattern passing over a degassing hole of a ground pattern in which a step is mainly generated is broken may be prevented. 
     According to an aspect of the present disclosure, a fan-out semiconductor package may be provided, in which a line width of a signal pattern passing over a degassing hole of a ground pattern is changed or a metal portion is formed in a degassing hole of a ground pattern over which a signal pattern passes. 
     According to an aspect of the present disclosure, a fan-out semiconductor package may include: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of holes, the second redistribution layer includes a second pattern having a first line portion having a first line width and a second line portion connected to the first line portion and having a second line width greater than the first line width, and the second line portion overlaps at least one of the plurality of holes when being projected in a direction perpendicular to the active surface. 
     According to another aspect of the present disclosure, a fan-out semiconductor package may include: a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the semiconductor chip; and a first connection member disposed on the active surface of the semiconductor chip and including a first redistribution layer electrically connected to the connection pads and a second redistribution layer electrically connected to the connection pads and disposed on the first redistribution layer. The first redistribution layer includes a first pattern having a plurality of holes, the second distribution layer includes a second pattern, and at least one of the plurality of holes has a metal portion disposed in a region over which the second pattern passes, when being projected in a direction perpendicular to the active surface. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a schematic block diagram illustrating an example of an electronic device system; 
         FIG. 2  is a schematic perspective view illustrating an example of an electronic device; 
         FIGS. 3A and 3B  are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged; 
         FIG. 4  is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package; 
         FIG. 5  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is finally mounted on a main board of an electronic device; 
         FIG. 6  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is finally mounted on a main board of an electronic device; 
         FIG. 7  is a schematic cross-sectional view illustrating a fan-out semiconductor package; 
         FIG. 8  is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device; 
         FIG. 9  is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package; 
         FIG. 10  is a schematic plan view taken along line I-I′ of the fan-out semiconductor package of  FIG. 9 ; 
         FIG. 11  is a schematic cross-sectional view illustrating an example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip; 
         FIG. 12  is a schematic plan view taken along line II-II′ of the first and second redistribution layers of  FIG. 11 ; 
         FIG. 13  is a schematic cross-sectional view illustrating another example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip; 
         FIG. 14  is a schematic cross-sectional view illustrating another example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip; 
         FIG. 15  is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package; and 
         FIG. 16  is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated or shortened for clarity. 
     Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounted surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above. 
     The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” means the concept including a physical connection and a physical disconnection. It can be understood that when an element is referred to with “first” and “second”, the element is not limited thereby. They may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element. 
     The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part one with another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein. 
     Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context. 
     Electronic Device 
       FIG. 1  is a schematic block diagram illustrating an example of an electronic device system. 
     Referring to  FIG. 1 , an electronic device  1000  may accommodate a motherboard  1010  therein. The motherboard  1010  may include chip related components  1020 , network related components  1030 , other components  1040 , and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines  1090 . 
     The chip related components  1020  may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DRAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components  1020  are not limited thereto, but may also include other types of chip related components. In addition, the chip related components  1020  may be combined with each other. 
     The network related components  1030  may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), IEEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+ (HSPA+), high speed downlink packet access+ (HSDPA+), high speed uplink packet access+ (HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols designated after the abovementioned protocols. However, the network related components  1030  are not limited thereto, but may also include a variety of other wireless or wired standards or protocols. In addition, the network related components  1030  may be combined with each other, together with the chip related components  1020  described above. 
     Other components  1040  may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMI) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components  1040  are not limited thereto, but may also include passive components used for various other purposes, or the like. In addition, other components  1040  may be combined with each other, together with the chip related components  1020  or the network related components  1030  described above. 
     Depending on a type of the electronic device  1000 , the electronic device  1000  may include other components that may or may not be physically or electrically connected to the motherboard  1010 . These other components may include, for example, a camera module  1050 , an antenna  1060 , a display device  1070 , a battery  1080 , an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, but may also include other components used for various purposes depending on a type of electronic device  1000 , or the like. 
     The electronic device  1000  may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device  1000  is not limited thereto, but may be any other electronic device processing data. 
       FIG. 2  is a schematic perspective view illustrating an example of an electronic device. 
     Referring to  FIG. 2 , a semiconductor package may be used for various purposes in the various electronic devices  1000  as described above. For example, a motherboard  1110  may be accommodated in a body  1101  of a smartphone  1100 , and various electronic components  1120  may be physically or electrically connected to the motherboard  1110 . In addition, other components that may or may not be physically or electrically connected to the motherboard  1110 , such as a camera module  1130 , may be accommodated in the body  1101 . Some of the electronic components  1120  may be the chip related components, and the semiconductor package  100  may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone  1100 , but may be other electronic devices as described above. 
     Semiconductor Package 
     Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, but may be packaged and used in an electronic device, or the like, in a packaged state. 
     Here, semiconductor packaging is required due to the existence of a difference in a circuit width between the semiconductor chip and a main board of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the main board used in the electronic device and an interval between the component mounting pads of the main board are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the main board, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the main board is required. 
     A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof. 
     The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings. 
     Fan-in Semiconductor Package 
       FIGS. 3A and 3B  are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged. 
       FIG. 4  is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package. 
     Referring to the drawings, a semiconductor chip  2220  may be, for example, an integrated circuit (IC) in a bare state, including a body  2221  including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads  2222  formed on one surface of the body  2221  and including a conductive material such as aluminum (Al), or the like, and a passivation layer  2223  such as an oxide film, a nitride film, or the like, formed on one surface of the body  2221  and covering at least portions of the connection pads  2222 . In this case, since the connection pads  2222  are significantly small, it is difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the main board of the electronic device, or the like. 
     Therefore, a connection member  2240  may be formed depending on a size of the semiconductor chip  2220  on the semiconductor chip  2220  in order to redistribute the connection pads  2222 . The connection member  2240  may be formed by forming an insulating layer  2241  on the semiconductor chip  2220  using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes  2243   h  opening the connection pads  2222 , and then forming wiring patterns  2242  and vias  2243 . Then, a passivation layer  2250  protecting the connection member  2240  may be formed, an opening  2251  may be formed, and an underbump metal layer  2260 , or the like, may be formed. That is, a fan-in semiconductor package  2200  including, for example, the semiconductor chip  2220 , the connection member  2240 , the passivation layer  2250 , and the underbump metal layer  2260  may be manufactured through a series of processes. 
     As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size. 
     However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has a large spatial limitation. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the main board of the electronic device. Here, even in a case that a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the main board of the electronic device. 
       FIG. 5  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is finally mounted on a main board of an electronic device. 
       FIG. 6  is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is finally mounted on a main board of an electronic device. 
     Referring to the drawings, in a fan-in semiconductor package  2200 , connection pads  2222 , that is, I/O terminals, of a semiconductor chip  2220  may be redistributed through an interposer substrate  2301 , and the fan-in semiconductor package  2200  may be finally mounted on a main board  2500  of an electronic device in a state in which it is mounted on the interposer substrate  2301 . In this case, solder balls  2270 , and the like, may be fixed by an underfill resin  2280 , or the like, and an outer side of the semiconductor chip  2220  may be covered with a molding material  2290 , or the like. Alternatively, a fan-in semiconductor package  2200  may be embedded in a separate interposer substrate  2302 , connection pads  2222 , that is, I/O terminals, of the semiconductor chip  2220  may be redistributed by the interposer substrate  2302  in a state in which the fan-in semiconductor package  2200  is embedded in the interposer substrate  2302 , and the fan-in semiconductor package  2200  may be finally mounted on a main board  2500  of an electronic device. 
     As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the main board of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the main board of the electronic device through a packaging process or may be mounted and used on the main board of the electronic device in a state in which it is embedded in the interposer substrate. 
     Fan-Out Semiconductor Package 
       FIG. 7  is a schematic cross-sectional view illustrating a fan-out semiconductor package. 
     Referring to the drawing, in a fan-out semiconductor package  2100 , for example, an outer side of a semiconductor chip  2120  may be protected by an encapsulant  2130 , and connection pads  2122  of the semiconductor chip  2120  may be redistributed outwardly of the semiconductor chip  2120  by a connection member  2140 . In this case, a passivation layer  2150  may be further formed on the connection member  2140 , and an underbump metal layer  2160  may be further formed in openings of the passivation layer  2150 . Solder balls  2170  may be further formed on the underbump metal layer  2160 . The semiconductor chip  2120  may be an integrated circuit (IC) including a body  2121 , the connection pads  2122 , a passivation layer (not illustrated), and the like. The connection member  2140  may include an insulating layer  2141 , redistribution layers  2142  formed on the insulating layer  2141 , and vias  2143  electrically connecting the connection pads  2122  and the redistribution layers  2142  to each other. 
     As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case that a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the main board of the electronic device without using a separate interposer substrate, as described below. 
       FIG. 8  is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a main board of an electronic device. 
     Referring to the drawing, a fan-out semiconductor package  2100  may be mounted on a main board  2500  of an electronic device through solder balls  2170 , or the like. That is, as described above, the fan-out semiconductor package  2100  includes the connection member  2140  formed on the semiconductor chip  2120  and capable of redistributing the connection pads  2122  to a fan-out region that is outside of a size of the semiconductor chip  2120 , such that the standardized ball layout may be used in the fan-out semiconductor package  2100  as it is. As a result, the fan-out semiconductor package  2100  may be mounted on the main board  2500  of the electronic device without using a separate interposer substrate, or the like. 
     As described above, since the fan-out semiconductor package may be mounted on the main board of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to occurrence of a warpage phenomenon. 
     Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the main board of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein. 
     A fan-out semiconductor package in which a problem in which a signal pattern passing over a degassing hole of a ground pattern is broken may be prevented will hereinafter be described with reference to the drawings. 
       FIG. 9  is a schematic cross-sectional view illustrating an example of a fan-out semiconductor package. 
       FIG. 10  is a schematic plan view taken along line I-I′ of the fan-out semiconductor package of  FIG. 9 . 
       FIG. 11  is a schematic cross-sectional view illustrating an example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip. 
       FIG. 12  is a schematic plan view taken along line II-II′ of the first and second redistribution layers of  FIG. 11 . 
     Referring to the drawings, a fan-out semiconductor package  100 A according to an exemplary embodiment in the present disclosure may include a second connection member  110  having a through-hole  110 H, a semiconductor chip  120  disposed in the through-hole  110 H of the second connection member  110  and having an active surface having connection pads  122  disposed thereon and an inactive surface opposing the active surface, an encapsulant  130  encapsulating at least portions of the second connection member  110  and the semiconductor chip  120 , a first connection member  140  disposed on the second connection member  110  and the active surface of the semiconductor chip  120 , a passivation layer  150  disposed on the first connection member  140 , an underbump metal layer  160  disposed in openings  151  of the passivation layer  150 , and connection terminals  170  disposed on the passivation layer  150  and connected to the underbump metal layer  160 . 
     The first connection member  140  may include a first insulating layer  141   a  disposed on the second connection member  110  and the active surface of the semiconductor chip  120 , a first redistribution layer  142   a  disposed on the first insulating layer  141   a , first vias  143   a  connecting the first redistribution layer  142   a  and the connecting pads  122  of the semiconductor chip  120  to each other, a second insulating layer  141   b  disposed on the first insulating layer  141   a , a second redistribution layer  142   b  disposed on the second insulating layer  141   b , second vias  143   b  penetrating through the second insulating layer  141   b  and connecting the first and second redistribution layers  142   a  and  142   b  to each other, a third insulating layer  141   c  disposed on the second insulating layer  141   b , a third redistribution layer  142   c  disposed on the third insulating layer  141   c , and third vias  143   c  penetrating through the third insulating layer  141   c  and connecting the second and third redistribution layers  142   b  and  142   c  to each other. 
     Meanwhile, when a wiring design of a semiconductor package is observed, ground patterns disposed in order to dissipate heat or return signals may be confirmed, in addition to signal patterns, which are fine circuit, disposed in order to transfer the signals. Since a remaining rate of a copper foil is very high in a ground region, a risk of interlayer delamination is high. In order to solve such a problem, a degas design having a circular or linear shape is reflected in a design to improve close adhesion between an insulating layer and the copper foil and allow a degas component discharged from a lower insulating layer to be easily discharged. However, such a degassing hole is filled with an insulating material, such that an insulating layer dent phenomenon may occur in a surface of an insulating layer. In this case, patterns disposed on the insulating layer are broken or close adhesion between the insulating layer and a dry film resist is reduced due to a step of the surface of the insulating layer. Resultantly, a plating solution permeates into the insulating layer and the dry film resist, such that a defect such as a short-circuit may occur. 
     On the other hand, referring to  FIGS. 11 and 12 , in the fan-out semiconductor package  100 A according to the exemplary embodiment, the first redistribution layer  142   a  may include a ground pattern  142   ag  having a plurality of degassing holes dh, the second redistribution layer  142   b  may include a signal pattern  142   bs  having a first line portion  142   bs   1  having a first line width w 1  and a second line portion  142   bs   2  connected to the first line portion  142   bs   1  and having a second line width w 2  greater than the first line width w 1 , and the second line portion  142   bs   2  may overlap at least one of the plurality of degassing holes dh when being projected in a direction perpendicular to the active surface of the semiconductor chip  120 . As described above, when the second line width w 2  of the second line portion  142   bs   2  of the signal pattern  142   bs  passing over the degassing hole dh is partially relatively increased, reliability of the signal pattern may be increased. Therefore, even in a case in which a step s is formed in the second insulating layer  141   b  formed on the degassing hole dh, occurrence of a problem in which the signal pattern at the time of forming the signal pattern  142   bs  is broken may be prevented. 
     The respective components included in the fan-out semiconductor package  100 A according to the exemplary embodiment will hereinafter be described in more detail. 
     The second connection member  110  may improve rigidity of the fan-out semiconductor package  100 A depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant  130 . When through-wirings, or the like, are formed in the second connection member  110 , the fan-out semiconductor package  100 A may be utilized as a package-on-package (POP) type package. The second connection member  110  may have the through-hole  110 H. The semiconductor chip  120  may be disposed in the through-hole  110 H to be spaced apart from the second connection member  110  by a predetermined distance. Side surfaces of the semiconductor chip  120  may be surrounded by the second connection member  110 . However, such a form is only an example and may be variously modified to have other forms, and the second connection member  110  may perform another function depending on such a form. The second connection member  110  may be omitted, if necessary, but it may be more advantageous in securing the board level reliability intended in the present disclosure that the fan-out semiconductor package  100 A includes the second connection member  110 . 
     The second connection member  110  may include an insulating layer  111 . An insulating material may be used as a material of the insulating layer  111 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. The second connection member  110  may serve as a support member. 
     The semiconductor chip  120  may be an integrated circuit (IC) provided in an amount of several hundreds to several millions of elements or more integrated in a single chip. In this case, the IC may be, for example, a processor chip (more specifically, an application processor (AP)) such as a central processor (for example, a CPU), a graphic processor (for example, a GPU), a field programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a micro processor, a micro controller, or the like, but is not limited thereto. That is, the IC may be a logic chip such as an analog-to-digital converter, an application-specific IC (ASIC), or the like, or a memory chip such as a volatile memory (for example, a DRAM), a non-volatile memory (for example, a ROM), a flash memory, or the like. In addition, the abovementioned elements may also be combined with each other and be disposed. 
     The semiconductor chip  120  may be formed on the basis of an active wafer. In this case, a base material of a body  121  may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body  121 . The connection pads  122  may electrically connect the semiconductor chip  120  to other components. A material of each of the connection pads  122  may be a conductive material such as aluminum (Al), or the like. A passivation layer  123  exposing the connection pads  122  may be formed on the body  121 , and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. A lower surface of the connection pad  122  may have a step with respect to a lower surface of the encapsulant  130  through the passivation layer  123 . Resultantly, a phenomenon in which the encapsulant  130  bleeds into the lower surface of the connection pads  122  may be prevented to some extent. An insulating layer (not illustrated), and the like, may also be further disposed in other required positions. The semiconductor chip  120  may be a bare die, a redistribution layer (not illustrated) may be further formed on the active surface of the semiconductor chip  120 , if necessary, and bumps (not illustrated), or the like, may be connected to the connection pads  122 . 
     The encapsulant  130  may protect the second connection member  110 , the semiconductor chip  120 , and the like. An encapsulation form of the encapsulant  130  is not particularly limited, but may be a form in which the encapsulant  130  surrounds at least portions of the second connection member  110 , the semiconductor chip  120 , and the like. For example, the encapsulant  130  may cover the second connection member  110  and the inactive surface of the semiconductor chip  120 , and fill spaces between walls of the through-hole  110 H and the side surfaces of the semiconductor chip  120 . In addition, the encapsulant  130  may also fill at least a portion of a space between the passivation layer  123  of the semiconductor chip  120  and the first connection member  140 . Meanwhile, the encapsulant  130  may fill the through-hole  110 H to thus serve as an adhesive and reduce buckling of the semiconductor chip  120  depending on certain materials. 
     A material of the encapsulant  130  is not particularly limited. For example, an insulating material may be used as the material of the encapsulant  130 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material. 
     The first connection member  140  may redistribute the connection pads  122  of the semiconductor chip  120 . Several tens to several hundreds of connection pads  122  of the semiconductor chip  120  having various functions may be redistributed by the first connection member  140 , and may be physically or electrically connected to an external source through the connection terminals  170  depending on the functions. The first connection member  140  may include the first insulating layer  141   a  disposed on the second connection member  110  and the active surface of the semiconductor chip  120 , the first redistribution layer  142   a  disposed on the first insulating layer  141   a , the first vias  143   a  connecting the first redistribution layer  142   a  and the connecting pads  122  of the semiconductor chip  120  to each other, the second insulating layer  141   b  disposed on the first insulating layer  141   a , the second redistribution layer  142   b  disposed on the second insulating layer  141   b , the second vias  143   b  penetrating through the second insulating layer  141   b  and connecting the first and second redistribution layers  142   a  and  142   b  to each other, the third insulating layer  141   c  disposed on the second insulating layer  141   b , the third redistribution layer  142   c  disposed on the third insulating layer  141   c , and the third vias  143   c  penetrating through the third insulating layer  141   c  and connecting the second and third redistribution layers  142   b  and  142   c  to each other. The first to third redistribution layers  142   a ,  142   b , and  142   c  may be electrically connected to the connection pads  122  of the semiconductor chip  120 . 
     An insulating material may be used as a material of each of the insulating layers  141   a ,  141   b , and  141   c . In this case, a photosensitive insulating material such as a photoimagable dielectric (PID) resin may also be used as the insulating material. That is, the insulating layers  141   a ,  141   b , and  141   c  may be photosensitive insulating layers. When the insulating layers  141   a ,  141   b , and  141   c  have photosensitive properties, the insulating layers  141   a ,  141   b , and  141   c  may be formed to have a smaller thickness, and fine pitches of the vias  143   a ,  143   b , and  143   c  may be achieved more easily. The insulating layers  141   a ,  141   b , and  141   c  may be photosensitive insulating layers including an insulating resin and an inorganic filler. When the insulating layers  141   a ,  141   b , and  141   c  are multiple layers, the materials of the insulating layers  141   a ,  141   b , and  141   c  may be the same as one another, and may also be different from one another, if necessary. When the insulating layers  141   a ,  141   b , and  141   c  are the multiple layers, the insulating layers  141   a ,  141   b , and  141   c  may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent. A larger number of insulating layers than those illustrated in the drawings may be formed. 
     The redistribution layers  142   a ,  142   b , and  142   c  may serve to substantially redistribute the connection pads  122 . A material of each of the redistribution layers  142   a ,  142   b , and  142   c  may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers  142   a ,  142   b , and  142   c  may perform various functions depending on designs of their corresponding layers. For example, the redistribution layers  142   a ,  142   b , and  142   c  may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers  142   a ,  142   b , and  142   c  may include via pad patterns, connection terminal pad patterns, and the like. 
     The first redistribution layer  142   a  may include the ground pattern  142   ag  having the plurality of degassing holes dh. The second redistribution layer  142   b  may include the signal pattern  142   bs  having the first line portion  142   bs   1  having the first line width w 1  and the second line portion  142   bs   2  connected to the first line portion  142   bs   1  and having the second line width w 2  greater than the first line width w 1 . The second line portion  142   bs   2  may overlap at least one of the plurality of degassing holes dh when being projected in the direction perpendicular to the active surface of the semiconductor chip  120 . When the second line width w 2  of the second line portion  142   bs   2  of the signal pattern  142   bs  passing over the degassing hole dh is partially relatively increased, the reliability of the signal pattern may be increased. Therefore, even in the case in which the step s is formed in the second insulating layer  141   b  formed on the degassing hole dh, the occurrence of the problem in which the signal pattern at the time of forming the signal pattern  142   bs  is broken may be prevented. When a larger number of redistribution layers are formed, the relationship between the ground pattern and the signal pattern described above may also be applied to a relationship between redistribution layers formed on different layers. 
     The vias  143   a ,  143   b , and  143   c  may electrically connect the redistribution layers  142   a ,  142   b , and  142   c , the connection pads  122 , or the like, formed on different layers to each other, resulting in an electrical path in the fan-out semiconductor package  100 A. A material of each of the vias  143   a ,  143   b , and  143   c  may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias  143   a ,  143   b , and  143   c  may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias  143   a ,  143   b , and  143   c  may have all of the shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. 
     The passivation layer  150  may protect the first connection member  140  from external physical or chemical damage. The passivation layer  150  may have the openings  151  exposing at least portions of the redistribution layer  142   c  of the first connection member  140 . The number of openings  151  formed in the passivation layer  150  may be several tens to several thousands. A material of the passivation layer  150  is not particularly limited. For example, an insulating material may be used as the material of the passivation layer  150 . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a solder resist may also be used. 
     The underbump metal layer  160  may improve connection reliability of the connection terminals  170  to improve board level reliability of the fan-out semiconductor package  100 A. The underbump metal layer  160  may be connected to the redistribution layer  142  of the first connection member  140  exposed through the openings  151  of the passivation layer  150 . The underbump metal layer  160  may be formed in the openings  151  of the passivation layer  150  by the known metallization method using the known conductive metal such as a metal, but is not limited thereto. 
     The connection terminals  170  may physically or electrically externally connect the fan-out semiconductor package  100 A. For example, the fan-out semiconductor package  100 A may be mounted on the main board of the electronic device through the connection terminals  170 . Each of the connection terminals  170  may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the connection terminals  170  is not particularly limited thereto. Each of the connection terminals  170  may be a land, a ball, a pin, or the like. The connection terminals  170  may be formed as a multilayer or single layer structure. When the connection terminals  170  are formed as a multilayer structure, the connection terminals  170  may include a copper (Cu) pillar and a solder. When the connection terminals  170  are formed as a single layer structure, the connection terminals  170  may include a tin-silver solder or copper (Cu). However, this is only an example, and the connection terminals  170  are not limited thereto. 
     The number, an interval, a disposition, or the like, of the connection terminals  170  is not particularly limited, but may be sufficiently modified by a person skilled in the art depending on design particulars. For example, the connection terminals  170  may be provided in an amount of several tens to several thousands according to the number of connection pads  122 , or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less. When the connection terminals  170  are solder balls, the connection terminals  170  may cover side surfaces of the underbump metal layer  160  extending onto one surface of the passivation layer  150 , and connection reliability may be more excellent. 
     At least one of the connection terminals  170  may be disposed in a fan-out region. The fan-out region is a region except for a region in which the semiconductor chip  120  is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness. 
     Meanwhile, although not illustrated in the drawings, a metal thin film may be formed on the walls of the through-hole  110 H, if necessary, in order to dissipate heat or block electromagnetic waves. In addition, a plurality of semiconductor chips  120  performing functions that are the same as or different from each other may be disposed in the through-hole  110 H, if necessary. In addition, a separate passive component such as an inductor, a capacitor, or the like, may be disposed in the through-hole  110 H, if necessary. In addition, a passive component, for example, a surface mounted technology (SMT) component including an inductor, a capacitor, or the like, may be disposed on a surface of the passivation layer  150 , if necessary. 
       FIG. 13  is a schematic cross-sectional view illustrating another example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip. 
     Referring to the drawing, the first redistribution layer  142   a  may include a ground pattern  142   ag  having a plurality of degassing holes dh. The second redistribution layer  142   b  may include a signal pattern  142   bs . At least one of the plurality of degassing holes dh may have a metal portion  142   ad  disposed in a region over which the signal pattern  142   bs  passes, when being projected in the direction perpendicular to the active surface of the semiconductor chip  120 . In detail, the metal portion  142   ad  may be disposed and isolated in the degassing hole dh. In this case, the metal portion  142   ad  may serve as a reinforcing structure, and the signal pattern  142   bs  may pass over such a reinforcing structure. Therefore, a step due to a fall-down phenomenon of the second insulating layer  141   b  may be significantly reduced, resulting in prevention of a phenomenon that the signal pattern is broken or a defect such as a short-circuit, or the like, due to permeation of a plating solution. The metal portion  142   ad  may include the same material as that of the ground pattern  142   ag , for example, copper (Cu). 
       FIG. 14  is a schematic cross-sectional view illustrating another example of a case in which a form of a ground pattern, having a degassing hole, of a first redistribution layer of a connection member of the fan-out semiconductor package of  FIG. 9  and a signal pattern of a second redistribution layer passing over the degassing hole is projected in a direction perpendicular to an active surface of a semiconductor chip. 
     Referring to the drawing, the first redistribution layer  142   a  may include a ground pattern  142   ag  having a plurality of degassing holes dh. The second redistribution layer  142   b  may include a signal pattern  142   bs . At least one of the plurality of degassing holes dh may have a metal portion  142   ap  disposed in a region over which the signal pattern  142   bs  passes, when being projected in the direction perpendicular to the active surface of the semiconductor chip  120 . In detail, the metal portion  142   ap  may have a form of a metal path separating at least one degassing hole into a plurality of sub-degassing holes dh 1  and dh 2 . Likewise, the metal portion  142   ap  may serve as a reinforcing structure, and the signal pattern  142   bs  may pass over such a reinforcing structure. Therefore, a step due to a fall-down phenomenon of the second insulating layer  141   b  may be significantly reduced, resulting in prevention of a phenomenon that the signal pattern is broken or a defect such as a short-circuit, or the like, due to permeation of a plating solution. The metal portion  142   ap  may include the same material as that of the ground pattern  142   ag , for example, copper (Cu), and may be integrated with the ground pattern  142   ag.    
       FIG. 15  is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package. 
     Referring to the drawing, in a fan-out semiconductor package  100 B according to another exemplary embodiment in the present disclosure, a second connection member  110  may include a first insulating layer  111   a  in contact with a first connection member  140 , a first wiring layer  112   a  in contact with the first connection member  140  and embedded in the first insulating layer  111   a , a second wiring layer  112   b  disposed on the other surface of the first insulating layer  111   a  opposing one surface of the first insulating layer  111   a  in which the first wiring layer  112   a  is embedded, a second insulating layer  111   b  disposed on the first insulating layer  111   a  and covering the second wiring layer  112   b , and a third wiring layer  112   c  disposed on the second insulating layer  111   b . The first to third wiring layers  112   a ,  112   b , and  112   c  may be electrically connected to connection pads  122 . The first and second wiring layers  112   a  and  112   b  and the second and third wiring layers  112   b  and  112   c  may be electrically connected to each other through first and second vias  113   a  and  113   b  penetrating through the first and second insulating layers  111   a  and  111   b , respectively. 
     When the first wiring layer  112   a  is embedded in the first insulating layer  111   a , a step generated due to a thickness of the first wiring layer  112   a  may be significantly reduced, and an insulating distance of the first connection member  140  may thus become constant. That is, a difference between a distance from a first redistribution layer  142   a  of the first connection member  140  to a lower surface of the first insulating layer  111   a  and a distance from the first redistribution layer  142   a  of the first connection member  140  to the connection pad  122  of a semiconductor chip  120  may be smaller than a thickness of the first wiring layer  112   a . Therefore, a high density wiring design of the first connection member  140  may be easy. 
     A lower surface of the first wiring layer  112   a  of the second connection member  110  may be disposed on a level above a lower surface of the connection pad  122  of a semiconductor chip  120 . In addition, a distance between the first redistribution layer  142   a  of the first connection member  140  and the first wiring layer  112   a  of the second connection member  110  may be greater than that between the first redistribution layer  142   a  of the first connection member  140  and the connection pad  122  of the semiconductor chip  120 . Here, the first wiring layer  112   a  may be recessed into the first insulating layer  111   a . As described above, when the first wiring layer  112   a  is recessed into the first insulating layer  111   a , such that the lower surface of the first insulating layer  111   a  and the lower surface of the first wiring layer  112   a  have a step therebetween, a phenomenon in which a material of the encapsulant  130  bleeds to pollute the first wiring layer  112   a  may be prevented. The second wiring layer  112   b  of the second connection member  110  may be disposed on a level between an active surface and an inactive surface of the semiconductor chip  120 . The second connection member  110  may be formed at a thickness corresponding to that of the semiconductor chip  120 . Therefore, the second wiring layer  112   b  formed in the second connection member  110  may be disposed on the level between the active surface and the inactive surface of the semiconductor chip  120 . 
     Thicknesses of the wiring layers  112   a ,  112   b , and  112   c  of the second connection member  110  may be greater than those of the redistribution layers  142   a ,  142   b , and  142   c  of the first connection member  140 . Since the second connection member  110  may have a thickness equal to or greater than that of the semiconductor chip  120 , the wiring layers  112   a ,  112   b , and  112   c  may be formed at large sizes depending on a scale of the second connection member  110 . On the other hand, the redistribution layers  142   a ,  142   b , and  142   c  of the first connection member  140  may be formed at sizes relatively smaller than those of the wiring layers  112   a ,  112   b , and  112   c  for thinness. 
     A material of each of the insulating layers  111   a  and  111   b  is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layers  111   a  and  111   b . In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material. 
     The wiring layers  112   a ,  112   b , and  112   c  may serve to redistribute the connection pads  122  of the semiconductor chip  120 . A material of each of the wiring layers  112   a ,  112   b , and  112   c  may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers  112   a ,  112   b , and  112   c  may perform various functions depending on designs of their corresponding layers. For example, the wiring layers  112   a ,  112   b , and  112   c  may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals except for the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers  112   a ,  112   b , and  112   c  may include via pads, wire pads, connection terminal pads, and the like. 
     The vias  113   a  and  113   b  may electrically connect the wiring layers  112   a ,  112   b , and  112   c  formed on different layers to each other, resulting in an electrical path in the second connection member  110 . A material of each of the vias  113   a  and  113   b  may be a conductive material. Each of the vias  113   a  and  113   b  may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of via holes. In addition, each of the vias  113   a  and  113   b  may have all of the shapes known in the related art, such as a tapered shape, a cylindrical shape, and the like. When holes for the first vias  113   a  are formed, some of the pads of the first wiring layer  112   a  may serve as a stopper, and it may thus be advantageous in a process that each of the first vias  113   a  has the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the first vias  113   a  may be integrated with the pad patterns of the second wiring layer  112   b . In addition, when holes for the second vias  113   b  are formed, some of the pads of the second wiring layer  112   b  may serve as a stopper, and it may thus be advantageous in a process that each of the second vias  113   b  has the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the second vias  113   b  may be integrated with the pad patterns of the third wiring layer  112   c.    
     Other configurations except for the abovementioned configuration, for example, the contents described with reference to  FIGS. 11 through 14  may be applied to the fan-out semiconductor package  100 B according to another exemplary embodiment, and a detailed description thereof overlaps that described above, and is thus omitted. 
       FIG. 16  is a schematic cross-sectional view illustrating another example of a fan-out semiconductor package. 
     Referring to the drawing, in a fan-out semiconductor package  100 C according to another exemplary embodiment in the present disclosure, a second connection member  110  may include a first insulating layer  111   a , a first wiring layer  112   a  and a second wiring layer  112   b  disposed on opposite surfaces of the first insulating layer  111   a , respectively, a second insulating layer  111   b  disposed on the first insulating layer  111   a  and covering the first wiring layer  112   a , a third wiring layer  112   c  disposed on the second insulating layer  111   b , a third insulating layer  111   c  disposed on the first insulating layer  111   a  and covering the second wiring layer  112   b , and a fourth wiring layer  112   d  disposed on the third insulating layer  111   c . The first to fourth wiring layers  112   a ,  112   b ,  112   c , and  112   d  may be electrically connected to connection pads  122 . Since the second connection member  110  may include a larger number of wiring layers  112   a ,  112   b ,  112   c , and  112   d , a first connection member  140  may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the first connection member  140  may be suppressed. Meanwhile, the first to fourth wiring layers  112   a ,  112   b ,  112   c , and  112   d  may be electrically connected to each other through first to third vias  113   a ,  113   b , and  113   c  respectively penetrating through the first to third insulating layers  111   a ,  111   b , and  111   c.    
     The first insulating layer  111   a  may have a thickness greater than those of the second insulating layer  111   b  and the third insulating layer  111   c . The first insulating layer  111   a  may be basically relatively thick in order to maintain rigidity, and the second insulating layer  111   b  and the third insulating layer  111   c  may be introduced in order to form a larger number of wiring layers  112   c  and  112   d . The first insulating layer  111   a  may include an insulating material different from those of the second insulating layer  111   b  and the third insulating layer  111   c . For example, the first insulating layer  111   a  may be, for example, prepreg including a core material, a filler, and an insulating resin, and the second insulating layer  111   b  and the third insulating layer  111   c  may be an ABF or a PID film including a filler and an insulating resin. However, the materials of the first insulating layer  111   a  and the second and third insulating layers  111   b  and  111   c  are not limited thereto. Similarly, the first vias  113   a  penetrating through the first insulating layer  111   a  may have a diameter greater than those of second vias  113   b  and third vias  113   c  respectively penetrating through the second insulating layer  111   b  and the third insulating layer  111   c.    
     A lower surface of the third wiring layer  112   c  of the second connection member  110  may be disposed on a level below a lower surface of the connection pad  122  of a semiconductor chip  120 . In addition, a distance between a first redistribution layer  142   a  of the first connection member  140  and the third wiring layer  112   c  of the second connection member  110  may be smaller than that between the first redistribution layer  142   a  of the first connection member  140  and the connection pad  122  of the semiconductor chip  120 . Here, the third wiring layer  112   c  may be disposed in a protruding form on the second insulating layer  111   b , resulting in being in contact with the first connection member  140 . The first wiring layer  112   a  and the second wiring layer  112   b  of the second connection member  110  may be disposed on a level between an active surface and an inactive surface of the semiconductor chip  120 . The second connection member  110  may be formed at a thickness corresponding to that of the semiconductor chip  120 . Therefore, the first wiring layer  112   a  and the second wiring layer  112   b  formed in the second connection member  110  may be disposed on the level between the active surface and the inactive surface of the semiconductor chip  120 . 
     Thicknesses of the wiring layers  112   a ,  112   b ,  112   c , and  112   d  of the second connection member  110  may be greater than those of the redistribution layers  142   a ,  142   b , and  142   c  of the first connection member  140 . Since the second connection member  110  may have a thickness equal to or greater than that of the semiconductor chip  120 , the wiring layers  112   a ,  112   b ,  112   c , and  112   d  may also be formed at large sizes. On the other hand, the redistribution layers  142   a ,  142   b , and  142   c  of the first connection member  140  may be formed at relatively small sizes for thinness. 
     Other configurations except for the abovementioned configuration, for example, the contents described with reference to  FIGS. 11 through 14  may be applied to the fan-out semiconductor package  100 C according to another exemplary embodiment, and a detailed description thereof overlaps that described above, and is thus omitted. 
     As set forth above, according to the exemplary embodiments in the present disclosure, a problem in which a signal pattern passing over a degassing hole of a ground pattern in which many steps are generated is broken may be prevented may be prevented. 
     While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims.