Patent Publication Number: US-11652143-B2

Title: III-N transistors integrated with thin-film transistors having graded dopant concentrations and/or composite gate dielectrics

Description:
BACKGROUND 
     Solid-state devices that can be used in high-frequency and/or high voltage applications are of great importance in modern semiconductor technologies. For example, radio frequency (RF) integrated circuits (RFIC) and power management integrated circuits (PMIC) may be critical functional blocks in system on a chip (SoC) implementations. Such SoC implementations may be found in mobile computing platforms such as smartphones, tablets, laptops, netbooks, and the like. In such implementations, the RFIC and PMIC are important factors for power efficiency and form factor, and can be equally or even more important than logic and memory circuits. 
     Due, in part, to their large band gap and high mobility, III-N material based transistors, such as gallium nitride (GaN) based transistors, may be particularly advantageous for high-frequency and high voltage applications. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings. 
         FIG.  1    provides a cross-sectional side view illustrating an integrated circuit (IC) structure that includes a III-N transistor and a thin-film transistor (TFT) integrated with the III-N transistor, according to some embodiments of the present disclosure. 
         FIG.  2 A  provides a cross-sectional side view illustrating a first example of the IC structure of  FIG.  1   , with the TFT having a horizontal dopant gradient in source and/or drain (S/D) regions, according to some embodiments of the present disclosure. 
         FIG.  2 B  provides a cross-sectional side view illustrating a second example of the IC structure of  FIG.  1   , with the TFT having a vertical dopant gradient in a channel region, according to some embodiments of the present disclosure. 
         FIG.  2 C  provides a cross-sectional side view illustrating a third example of the IC structure of  FIG.  1   , with the TFT having a composite gate dielectric, according to some embodiments of the present disclosure. 
         FIG.  3    is a flow diagram of an example method of manufacturing an IC structure that includes a III-N transistor and a TFT integrated with the III-N transistor, in accordance with various embodiments of the present disclosure. 
         FIGS.  4 A- 4 D  are various views illustrating different example stages in the manufacture of an IC structure that includes a III-N transistor and a TFT integrated with the III-N transistor using the method of  FIG.  3   , according to some embodiments of the present disclosure. 
         FIGS.  5 A- 5 B  are top views of a wafer and dies that include one or more IC structures having one or more TFTs with graded dopant concentrations and/or composite gate dielectrics integrated with one or more III-N transistors in accordance with any of the embodiments of the present disclosure. 
         FIG.  6    is a cross-sectional side view of an IC package that may include one or more IC structures having one or more TFTs with graded dopant concentrations and/or composite gate dielectrics integrated with one or more III-N transistors in accordance with any of the embodiments of the present disclosure. 
         FIG.  7    is a cross-sectional side view of an IC device assembly that may include one or more IC structures having one or more TFTs with graded dopant concentrations and/or composite gate dielectrics integrated with one or more III-N transistors in accordance with any of the embodiments of the present disclosure. 
         FIG.  8    is a block diagram of an example computing device that may include one or more IC structures having one or more TFTs with graded dopant concentrations and/or composite gate dielectrics integrated with one or more III-N transistors in accordance with any of the embodiments of the present disclosure. 
         FIG.  9    is a block diagram of an example RF device that may include one or more IC structures having one or more TFTs with graded dopant concentrations and/or composite gate dielectrics integrated with one or more III-N transistors in accordance with any of the embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Overview 
     As mentioned above, transistors based on III-N semiconductor materials (i.e., III-N transistors) have properties that make them particularly advantageous for certain applications. For example, because GaN has a larger band gap (about 3.4 electronvolts (eV)) than silicon (Si; band gap of about 1.1 eV), a GaN transistor is expected to withstand a larger electric field (resulting, e.g., from applying a large voltage to the drain, Vdd) before suffering breakdown, compared to a Si transistor of similar dimensions. 
     Furthermore, III-N transistors may advantageously employ a 2D electron gas (2DEG) (i.e., a group of electrons, an electron gas, free to move in two dimensions but tightly confined in the third dimension, e.g., a 2D sheet charge) as its transport channel, enabling high mobilities without relying on using impurity dopants. For example, the 2DEG may be formed just below a heterojunction interface formed by deposition (e.g., epitaxial deposition), on a given III-N semiconductor material, of a charge-inducing film of a material having larger spontaneous and piezoelectric polarization, compared to the III-N semiconductor material. Such a film is generally referred to as a “polarization material” while the III-N semiconductor material may be referred to as a “III-N channel material” because this is where a conductive channel (2DEG) is formed during operation of the III-N transistor. Together, a stack of a III-N channel material and a polarization material provided thereon may be referred to as a “III-N channel stack” of a III-N transistor. Providing a polarization material such as AlGaN over a III-N channel material such as GaN may induce tensile strain in the polarization material (e.g., due to the lattice mismatch between these two materials; e.g., due to the lattice constant of a polarization material such as AlGaN being smaller than that of the III-N semiconductor material such as GaN), which allows forming very high charge densities in the underlying III-N channel material without intentionally adding impurity dopants. As a result, high mobilities of charge carriers in the III-N channel material may, advantageously, be realized. 
     As used herein, the term “III-N semiconductor material” (or, simply, “III-N material”) refers to a compound semiconductor material with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sub-lattice of nitrogen (N). As used herein, the term “III-N transistor” refers to a field-effect transistor (FET) that includes a III-N material (which may include one or more different III-N materials, e.g., a plurality of different III-N materials stacked over one another) as an active material (i.e., the material in which a conducting channel of the transistor forms during operation, in which context the III-N material may also be referred to as a “III-N channel material”). 
     While discussions provided herein refer to the two-dimensional charge carrier layers as “2DEG” layers, embodiments described herein are also applicable to systems and material combinations in which 2D hole gas (2DHG) may be formed, instead of 2DEG. Thus, unless stated otherwise, explanations of embodiments referring to 2DEG may be applied to transistors implementing 2DHG instead, all of such embodiments being within the scope of the present disclosure. 
     Despite the advantages, there are some challenges associated with III-N transistors that may hinder their large-scale implementation. One such challenge resides in the absence of viable low voltage (e.g., below about 5 volts) P-type metal-oxide-semiconductor (PMOS) transistors that can be built using III-N materials. Therefore, present III-N ICs are limited to using N-type metal-oxide-semiconductor (NMOS) transistors only. The standby current and good logic performance of such ICs are extremely challenging. In addition, since various devices require complementary metal-oxide-semiconductor (CMOS) circuits that use both PMOS and NMOS transistors, PMOS transistors have to be implemented (e.g., as conventional silicon front end of line (FEOL) transistors) on a chip separate from that housing the III-N ICs. A chip with PMOS silicon FEOL transistors and a chip with III-N transistors can then be connected with input/output (I/O) pins, in a multi-chip package (MCP). While such a solution may be acceptable for a small number of I/O pins, as logic solutions increase in complexity, the number of required I/O pins between the NMOS and PMOS chips increases as well, compromising the viability of this solution. 
     Disclosed herein are IC structures, packages, and device assemblies that include TFTs monolithically integrated on the same support structure/material (which may be, e.g., a substrate, a die, or a chip) as III-N transistors. In various aspects, TFTs may have a channel and source/drain materials that include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. Embodiments of the present disclosure are based on recognition that TFTs may provide a viable approach to implementing PMOS transistors on the same support structure with NMOS transistors, which may be either III-N or non-III-N transistors (e.g., NMOS TFTs, SiGe transistors, III-V transistors, etc.), thus providing an integrated logic solution based on any suitable transistor technology (e.g., III-N transistor technology, Si, SiGe, or Ge transistor technology, III-V transistor technology, etc.). For example, in some embodiments of the present disclosure, a TFT may be integrated with a III-N transistor by being disposed side-by-side with the III-N transistor, advantageously enabling implementation of both types of transistors in a single device layer. In other embodiments, a TFT may be integrated by being disposed above or below a III-N transistor, i.e., in a different device layer, which may be advantageous in terms of a smaller x-y footprint. Embodiments of the present disclosure are further based on recognition that using conventional TFTs, e.g., those used in display technology, would not be suitable for applications in which III-N transistors may be used. For example, conventional TFTs would not be efficient, and may fail altogether, when used with analog-like voltages (e.g., greater than 1.8 volts) that may be employed in high-frequency and high-power applications. Therefore, in various aspects of the present disclosure, TFTs integrated with III-N transistors are engineered to include one or more of 1) graded dopant concentrations in their source/drain (S/D) regions, 2) graded dopant concentrations in their channel regions, and 3) thicker and/or composite gate dielectrics in their gate stacks. Such TFTs (i.e., TFTs that implement graded dopant concentrations and/or composite gate dielectrics as described herein) may be referred to as “optimized TFTs” to highlight the fact that their structures are different from conventional TFTs, which may make them particularly suitable for integration with III-N transistors, other III-V devices (e.g., high electron mobility transistors (HEMTs) and heterojunction bipolar transistors (HBTs)), SiGe transistors (e.g., SiGe HBTs), or III-V devices. Such optimized TFTs may allow implementation of CMOS circuit solutions which would not be possible in most conventional III-N, III-V or SiGe technologies that typically feature only one type of devices (absent PMOS). 
     While some embodiments of the present disclosure refer to integration of optimized TFTs with III-N transistors, these embodiments are equally applicable to devices other than III-N transistors, such as, HEMTs and HBTs, SiGe transistors, or various III-V devices. 
     Graded dopant concentration in a S/D region of an optimized TFT refers to the doping of the S/D region being graded (i.e., gradually changing) in a direction parallel to a gate length of the TFT (e.g., in a direction parallel to the support structure over which the TFT may be provided), which may be considered a horizontal direction, and which may, therefore, justify referring to such grading as “horizontal grading.” For example, for a given S/D region that is horizontally graded, a portion of the S/D region that is closest to the channel region of the TFT may have a lower dopant concentration than portions of the S/D region that are farther away from the channel region. Such horizontal grading in the S/D regions may advantageously reduce abruptness of, or smoothen, a P-N junction formed by a material of a S/D region doped with one type of dopant atoms (e.g., P-type dopant atoms if the TFT is a PMOS TFT) and a material of a channel region doped with the other type of dopant atoms (e.g., N-type dopant atoms for the PMOS TFT), which may advantageously mitigate hot carrier effects and improve reliability of the TFT. 
     Graded dopant concentration in a channel region of an optimized TFT refers to doping of the channel region being graded in a direction perpendicular to the plane of the channel material of the TFT (e.g., in a direction perpendicular to the support structure on which the TFT may be provided), which may be considered a vertical direction, and which may, therefore, justify referring to such grading as “vertical grading.” For example, when a TFT has a horizontally graded channel region, a portion of the channel region that is closest to a gate stack of the TFT may have a lower dopant concentration than portions of the channel region that are farther away from the gate stack. Such vertical grading in the channel region may advantageously create a quantum well in the portion closest to the gate stack, which may improve confinement of charge carriers in that portion and may lead to improvements in terms of hot carrier effects and device reliability. 
     Using thicker gate dielectrics in a gate stack of an optimized TFT may advantageously enable the TFT to handle higher voltages without suffering breakdown, i.e., it may increase the breakdown voltage of the TFT. The breakdown voltage, commonly abbreviated as BVDS, refers to the drain-source voltage, VDS, which causes a transistor to enter the breakdown region (i.e., a region of operation where the transistor receives too much voltage across its drain-source terminal, which causes the drain-source terminal to break down and makes the drain current, ID, drastically increase). 
     In various embodiments, optimized TFTs described herein may be referred to as “non-III-N transistors” to highlight the fact that they may be transistors employing one or more semiconductor materials other than III-N materials (i.e., non-III-N materials) as active channel materials. For example, such TFTs may advantageously employ group IV semiconductor materials, such as silicon or germanium. 
     Because III-N transistors and optimized TFTs as described herein are both provided over a single support structure, they may be referred to as “integrated” transistors. When a III-N transistor and a TFT are provided over different portions of the III-N semiconductor material (and, therefore, over different portion of the support structure), their integration may be referred to as “side-by-side” integration (as opposed to, e.g., stacked integration where one transistor could be provided over another transistor). In this manner, one or more TFTs may, advantageously, be integrated with one or more III-N transistors, enabling monolithic integration of PMOS transistors, which may be provided by at least some of the TFTs, on a single chip with NMOS transistors, which may be provided by at least some of the III-N transistors. In some implementation, both PMOS and NMOS transistors of a given CMOS circuit may be implemented as any of the TFT as descried herein, enabling monolithic integration of CMOS circuits with III-N transistors. Various integration schemes described herein may reduce costs and improve performance, e.g., by reducing RF losses incurred when power is routed off chip in an MCP. Side-by-side arrangement of III-N transistors and TFTs provides a further advantage of the ability to share at least some of the fabrication processes used to manufacture these transistors (i.e., the ability to use a single fabrication process to form a portion of a III-N transistor and a portion of a TFT). 
     While various embodiments described herein refer to III-N transistors (i.e., transistors employing one or more III-N materials as an active channel material), these embodiments are equally applicable to any other III-N devices besides III-N transistors, such as III-N diodes, sensors, light-emitting diodes (LEDs), and lasers (i.e., other device components employing one or more III-N materials as active materials). 
     Each of the structures, packages, methods, devices, and systems of the present disclosure may have several innovative aspects, no single one of which being solely responsible for the all of the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings. 
     In the following detailed description, various aspects of the illustrative implementations may be described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. For example, the term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term “coupled” means either a direct electrical or magnetic connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. If used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds containing, respectively, oxygen, carbon, nitrogen, etc. Similarly, the terms naming various compounds refer to materials having any combination of the individual elements within a compound (e.g., “gallium nitride” or “GaN” refers to a material that includes gallium and nitrogen, “aluminum indium gallium nitride” or “AlInGaN” refers to a material that includes aluminum, indium, gallium and nitrogen, and so on). Further, the term “high-k dielectric” refers to a material having a higher dielectric constant (k) than silicon oxide, while the term “low-k dielectric” refers to a material having a lower k than silicon oxide. The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−20%, preferably within +/−10%, of a target value based on the context of a particular value as described herein or as known in the art. Similarly, terms indicating orientation of various elements, e.g., “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between the elements, generally refer to being within +/−5-20% of a target value based on the context of a particular value as described herein or as known in the art. 
     The terms “over,” “under,” “between,” and “on” as used herein refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described to be “on” a second layer refers to a layer that is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening layers. 
     For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C). 
     The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. For convenience, if a collection of drawings designated with different letters are present, e.g.,  FIGS.  5 A- 5 B , such a collection may be referred to herein without the letters, e.g., as “ FIG.  5   .” In the drawings, same reference numerals refer to the same or analogous elements/materials shown so that, unless stated otherwise, explanations of an element/material with a given reference numeral provided in context of one of the drawings are applicable to other drawings where element/materials with the same reference numerals may be illustrated. 
     In the drawings, some schematic illustrations of example structures of various structures, devices, and assemblies described herein may be shown with precise right angles and straight lines, but it is to be understood that such schematic illustrations may not reflect real-life process limitations that may cause the features to not look so “ideal” when any of the structures described herein are examined using e.g., scanning electron microscopy (SEM) images or transmission electron microscope (TEM) images. In such images of real structures, possible processing defects could also be visible, e.g., not-perfectly straight edges of materials, tapered vias or other openings, inadvertent rounding of corners or variations in thicknesses of different material layers, occasional screw, edge, or combination dislocations within the crystalline region(s), and/or occasional dislocation defects of single atoms or clusters of atoms. There may be other defects not listed here but that are common within the field of device fabrication. 
     Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. 
     Various IC structures that include at least one III-N device (e.g., a III-N transistor) integrated with at least one optimized TFT over a single support structure as described herein may be implemented in one or more components associated with an IC or/and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those that are mounted on an IC, provided as an integral part of an IC, or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a RFIC, which may, e.g., be included in any component associated with an IC of an RF receiver, an RF transmitter, or an RF transceiver, e.g., as used in telecommunications within base stations (BS) or user equipment (UE). Such components may include, but are not limited to, power amplifiers, low-noise amplifiers, RF filters (including arrays of RF filters, or RF filter banks), switches, upconverters, downconverters, and duplexers. In some embodiments, the IC structures as described herein may be employed as part of a chipset for executing one or more related functions in a computer. 
     Integrating a III-N Transistor with an Optimized TFT 
       FIG.  1    provides a cross-sectional side view illustrating an IC structure  100  that includes a III-N device, e.g., a III-N transistor  102  (an approximate boundary of which is illustrated in  FIG.  1    with a thick dashed line) integrated with a TFT  104 , according to some embodiments of the present disclosure. A legend provided within a dashed box at the bottom of  FIG.  1    illustrates colors/patterns used to indicate some classes of materials of some of the elements shown in  FIG.  1   , so that  FIG.  1    is not cluttered by too many reference numerals. For example,  FIG.  1    uses different colors/patterns to identify a support structure  108 , an insulator  110 , a III-N material  112 , a polarization material  114 , source/drain (S/D) regions  116  of the III-N transistor  102 , an electrically conductive material  118  used to implement contacts to various transistor terminals, a gate dielectric material  120 , a gate electrode material  122 , a buffer material  124 , and a hard-mask material  126 . The TFT  104  may be an optimized TFT in accordance with various embodiments described herein, some of which are shown in  FIGS.  2 A- 2 C . 
     The support structure  108  may be any suitable structure, e.g., a substrate, a die, or a chip, on which TFTs and III-N transistors as described herein may be implemented. In some embodiments, the support structure  108  may include a semiconductor, such as silicon. In other implementations, the support structure  108  may include/be alternate materials, which may or may not be combined with silicon, that include but are not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of group III-N or group IV materials. 
     In some embodiments, the support structure  108  may include a ceramic material, or any other non-semiconductor material. For example, in some embodiments, the support structure  108  may include glass, a combination of organic and inorganic materials, embedded portions having different materials, etc. Although a few examples of materials from which the support structure  108  may be formed are described here, any material that may serve as a foundation upon which at least one Optimized TFT and at least one III-N transistor as described herein may be built falls within the spirit and scope of the present disclosure. 
     Although not specifically shown in  FIG.  1   , in some embodiments, the support structure  108  of the IC structure  100  may include an insulating layer, such as an oxide isolation layer, provided thereon. For example, in some embodiments, a layer of the insulator  110  may be provided over the support structure  108  (not shown in  FIG.  1   ). The insulator  110  may include any suitable insulating material, e.g., any suitable interlayer dielectric (ILD), to electrically isolate the semiconductor material of the support structure  108  from other regions of or surrounding the III-N transistor  102  and/or from other regions of or surrounding the TFT  104 . Providing such an insulating layer over the support structure  108  may help mitigate the likelihood that conductive pathways will form through the support structure  108  (e.g., a conductive pathway between the S/D regions  116 ). Examples of the insulator  110  may include, in some embodiments, silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. In general, the insulator  110  may be provided in various portions of the IC structure  100 . In some embodiments, the insulator  110  may include a continuous insulator material encompassing at least portions of the III-N transistor  102  as well as at least portions of the TFT  104 . In various embodiments, the insulator  110  may include different insulating materials in different portions of the IC structure  100 . 
     In some embodiments, the III-N material  112  may be formed of a compound semiconductor with a first sub-lattice of at least one element from group III of the periodic table (e.g., Al, Ga, In), and a second sub-lattice of nitrogen (N). In some embodiments, the III-N material  112  may be a binary, ternary, or quaternary III-N compound semiconductor that is an alloy of two, three, or even four elements from group III of the periodic table (e.g., boron, aluminum, indium, gallium) and nitrogen. 
     In general, the III-N material  112  may be composed of various III-N semiconductor material systems including, for example, N-type or P-type III-N materials systems, depending on whether the III-N transistor  102  is an N-type or a P-type transistor. For some N-type transistor embodiments, the III-N material  112  may advantageously be a III-N material having a high electron mobility, such a, but not limited to GaN, InGaAs, InP, InSb, and InAs. For some In x Ga 1-x As embodiments, In content (x) may be between 0.6 and 0.9, and advantageously is at least 0.7 (e.g., In 0.7 Ga 0.3 As). For some such embodiments, the III-N material  112  may be a ternary III-N alloy, such as InGaN, or a quaternary III-N alloy, such as AlInGaN. 
     In some embodiments, the III-N material  112  may be a semiconductor material having a band gap greater than a band gap of silicon (i.e., greater than about 1.1 eV), preferably greater than 1.5 eV, or greater than 2 eV. Thus, in such embodiments, the III-N material  112  may include, e.g., GaN, AlN, or any alloy of Al, Ga, and N, but not InN because InN has a band gap of only about 0.65 eV. Such embodiments where the III-N material  112  is a wide-band gap material may be particularly advantageous when the channel material of the TFT  104  is provided directly on the III-N material  112 , or over a thin intermediate layer of another material, as a wide-band gap III-N material  112  may assist electrical isolation from the channel material of the TFT  104 , while providing mechanical support for the TFT  104 . 
     In some embodiments, the III-N material  112  may be formed of a highly crystalline semiconductor, e.g., of substantially a monocrystalline semiconductor (possibly with some limited amount of defects, e.g., dislocations). The quality of the III-N material  112  (e.g., in terms of defects or crystallinity) may be higher than that of other III-N materials of, or near, the III-N transistor  102  since, during the operation of the III-N transistor  102 , a transistor channel will form in the III-N material  112 . A portion of the III-N material  112  where a transistor channel of the III-N transistor  102  forms during operation may be referred to as a “III-N channel material/region” of the III-N transistor  102 . 
     In some embodiments, the III-N material  112  may be an intrinsic III-N semiconductor material or alloy, not intentionally doped with any electrically active impurity. In alternate embodiments, one or more a nominal impurity dopant level may be present within the III-N material  112 , for example to set a threshold voltage Vt of the III-N transistor  102 , or to provide halo pocket implants, etc. In such impurity-doped embodiments however, impurity dopant level within the III-N material  112  may be relatively low, for example below 10 15  dopant atoms per cubic centimeter (#/cm 3  or, simply, cm −3 ), or below 10 13  cm −3 . 
     In various embodiments, a thickness of the III-N material  112  may be between about 5 and 2000 nanometers, including all values and ranges therein, e.g., between about 50 and 1000 nanometers, or between about 10 and 50 nanometers. Unless specified otherwise, all thicknesses described herein refer to a dimension measured in a direction perpendicular to the support structure  108 . 
     Turning now to the polarization material  114  of the III-N transistor  102 , in general, the polarization material  114  may be a layer of a charge-inducing film of a material having larger spontaneous and/or piezoelectric polarization than that of the bulk of the III-N layer material immediately below it (e.g., the III-N material  112 ), creating a heterojunction (i.e., an interface that occurs between two layers or regions of semiconductors having unequal band gaps) with the III-N material  112 , and leading to formation of 2DEG at or near (e.g., immediately below) that interface, during operation of the III-N transistor  102 . As described above, a 2DEG layer may be formed during operation of a III-N transistor in a layer of a III-N semiconductor material immediately below a suitable polarization layer. In various embodiments, the polarization material  114  may include materials such as AlN, InAlN, AlGaN, or Al x In y Ga 1-x N, and may have a thickness between about 1 and 50 nanometers, including all values and ranges therein, e.g., between about 5 and 15 nanometers or between about 10 and 30 nanometers. In some embodiments, the polarization material  114  may include any suitable semiconductor material having a lattice constant smaller than that of the III-N material  112 . 
     As also shown in  FIG.  1   , the III-N transistor  102  may include two S/D regions  116 , where one of the S/D regions  116  is a source region and another one is a drain region, where the “source” and the “drain” designations may be interchangeable. As is well-known, in a transistor, S/D regions (also sometimes interchangeably referred to as “diffusion regions”) are regions that can supply charge carriers for the transistor channel (e.g., the transistor channel  112 ) of the transistor (e.g., the III-N transistor  102 ). In some embodiments, the S/D regions  116  may include highly doped semiconductor materials, such as highly doped InGaN. Often, the S/D regions may be highly doped, e.g., with dopant concentrations of at least above 1×10 21  cm −3 , in order to advantageously form Ohmic contacts with the respective S/D electrodes of the III-N transistor  102  (e.g., electrodes  142  shown in  FIG.  1   , made of the electrically conductive material  118 ), although these regions may also have lower dopant concentrations in some implementations. Regardless of the exact doping levels, the S/D regions  116  are the regions having dopant concentration higher than in other regions between the source region (e.g., the S/D region  116  shown on the left side in  FIG.  1   ) and the drain region (e.g., the S/D region  116  shown on the right side in  FIG.  1   ), i.e., higher than the III-N material  112 . For that reason, sometimes the S/D regions are referred to as highly doped (HD) S/D regions. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions  116 . 
     The electrically conductive material  118  of the S/D electrodes  142  may include any suitable electrically conductive material, alloy, or a stack of multiple electrically conductive materials. In some embodiments, the electrically conductive material  118  may include one or more metals or metal alloys, with metals such as copper, ruthenium, palladium, platinum, cobalt, nickel, hafnium, zirconium, titanium, tantalum, and aluminum, tantalum nitride, titanium nitride, tungsten, doped silicon, doped germanium, or alloys and mixtures of these. In some embodiments, the electrically conductive material  118  may include one or more electrically conductive alloys, oxides, or carbides of one or more metals. In some embodiments, the electrically conductive material  118  may include a doped semiconductor, such as silicon or another semiconductor doped with an N-type dopant or a P-type dopant. Metals may provide higher conductivity, while doped semiconductors may be easier to pattern during fabrication. In some embodiments, the S/D electrodes  142  may have a thickness between about 2 nanometers and 1000 nanometers, preferably between about 2 nanometers and 100 nanometers.  FIG.  1    further illustrates that the electrically conductive material  118  may also be used to form electrical contact to the gate electrode of the III-N transistor  102  (i.e., in general, the electrically conductive material  118  may also be used to form electrical contacts to any of the transistor terminals of the III-N transistor  102 ), while  FIGS.  2 A- 2 D  illustrate that the electrically conductive material  118  may also be used to form electrical contacts to any of the transistor terminals of the TFT  104 . In various embodiments, the exact material compositions of the electrically conductive material  118  may be different when used to implement contacts to different electrodes of different transistors within the IC structure  100 . 
       FIG.  1    further illustrates a gate stack  144  provided over the channel portion of the III-N material  112 . The gate stack  144  may include a layer of a gate dielectric material  120 , and a gate electrode material  122 . 
     The gate dielectric material  120  is typically a high-k dielectric material, e.g., a material including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric material  120  may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric material  120  during manufacture of the III-N transistor  102  to improve the quality of the gate dielectric material  120 . A thickness of the gate dielectric material  120  may be between 0.5 nanometers and 3 nanometers, including all values and ranges therein, e.g., between 1 and 3 nanometers, or between 1 and 2 nanometers. 
     The gate electrode material  122  may include at least one P-type work function metal or N-type work function metal, depending on whether the III-N transistor  102  is a PMOS transistor or an NMOS transistor (e.g., P-type work function metal may be used as the gate electrode material  122  when the transistors  102  is a PMOS transistor and N-type work function metal may be used as the gate electrode material  122  when the III-N transistor  102  is an NMOS transistor, depending on the desired threshold voltage). For a PMOS transistor, metals that may be used for the gate electrode material  122  may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, titanium nitride, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, metals that may be used for the gate electrode material  122  include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and nitrides of these metals (e.g., tantalum nitride, and tantalum aluminum nitride). In some embodiments, the gate electrode material  122  may include a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. 
     Further layers may be included next to the gate electrode material  122  for other purposes, such as to act as a diffusion barrier layer or/and an adhesion layer, not specifically shown in  FIG.  1   . Furthermore, in some embodiments, the gate dielectric material  120  and the gate electrode material  122  may be surrounded by a gate spacer, not shown in  FIG.  1   , configured to provide separation between the gates of different transistors. Such a gate spacer may be made of a low-k dielectric material (i.e., a dielectric material that has a lower dielectric constant (k) than silicon dioxide, which has a dielectric constant of 3.9). Examples of low-k materials that may be used as the dielectric gate spacer may include, but are not limited to, fluorine-doped silicon dioxide, carbon-doped silicon dioxide, spin-on organic polymeric dielectrics such as polyimide, polynorbornenes, benzocyclobutene, and polytetrafluoroethylene (PTFE), or spin-on silicon-based polymeric dielectric such as hydrogen silsesquioxane (HSQ) and methylsilsesquioxane (MSQ)). Other examples of low-k materials that may be used as the dielectric gate spacer include various porous dielectric materials, such as for example porous silicon dioxide or porous carbon-doped silicon dioxide, where large voids or pores are created in a dielectric in order to reduce the overall dielectric constant of the layer, since voids can have a dielectric constant of nearly 1. 
     In some embodiments, the IC structure  100  may, optionally, include a buffer material  124  between the III-N material  112  and the support structure  108 , as shown in  FIG.  1   . In some embodiments, the buffer material  124  may be a layer of a semiconductor material that has a band gap larger than that of the III-N material  112 , so that the buffer material  124  can serve to prevent current leakage from the future III-N transistor to the support structure  108 . A properly selected semiconductor for the buffer material  124  may also enable better epitaxy of the III-N material  112  thereon, e.g., it may improve epitaxial growth of the III-N material  112 , for instance in terms of a bridge lattice constant or amount of defects. For example, a semiconductor that includes aluminum, gallium, and nitrogen (e.g., AlGaN) or a semiconductor that includes aluminum and nitrogen (e.g., AlN) may be used as the buffer material  124  when the III-N material  112  is a semiconductor that includes gallium and nitrogen (e.g., GaN). Other examples of materials for the buffer material  124  may include materials typically used as ILD, described above, such as oxide isolation layers, e.g., silicon oxide, silicon nitride, aluminum oxide, and/or silicon oxynitride. When implemented in the III-N transistor  102 , the buffer material  124  may have a thickness between about 100 and 5000 nm, including all values and ranges therein, e.g., between about 200 and 1000 nanometers, or between about 250 and 500 nanometers. 
     In some embodiments, the IC structure  100  may, optionally, include a hard-mask material  126  over the polarization material  114 , as shown in  FIG.  1   . In some embodiments, the hard-mask material  126  may be silicon nitride. 
     Although not specifically shown in  FIG.  1   , the IC structure  100  may further include additional transistors similar to the III-N transistor  102 , described above. 
     Turning now to the TFT  104 ,  FIG.  1    only provides a schematic illustration that, in some embodiments, the TFT  104  may be provided to the side of the III-N transistor  102 . In particular, in some embodiments, both the III-N transistor  102  and the TFT  104  may be seen as being implemented in a single layer above the support structure  108 . In some embodiments, both the III-N transistor  102  and the TFT  104  may be implemented as FEOL transistors. In other embodiments, both the III-N transistor  102  and the TFT  104  may be implemented as back end of line (BEOL) transistors. In general, FEOL and BEOL refer to different layers, or different fabrication processes used to manufacture different portions of IC devices (e.g., logic devices) in context of CMOS processes. In some embodiments, at least portions of the III-N transistor  102  and the TFT  104  may be implemented in the same metal layer of a metallization stack of the IC structure  100 . Although not specifically shown in  FIG.  1   , the IC structure  100  may further include additional TFTs similar to the TFT  104 , described herein. 
     In some embodiments, the IC structure  100  may be included in, or used to implement at least a portion of an RF FE. In some embodiments, the III-N transistor  102  of the IC structure  100  may be included in, or used to implement at least a portion of an RF circuit or a part of a power circuit included in the IC structure. In some embodiments, the TFT  104  of the IC structure  100  may be included in, or used to implement at least a portion of a CMOS circuit included in the IC structure (e.g., control logic, current mirrors, level shifters, buffers, power gating, etc.). 
     Turning to the details of the TFT  104 , a TFT is a special kind of a FET, made by depositing a thin film of an active semiconductor material, as well as a dielectric layer and metallic contacts, over a supporting layer that may be a non-conducting layer. During operation of a TFT, at least a portion of the active semiconductor material forms a channel of the TFT, and, therefore, the thin film of such active semiconductor material is referred to herein as a “TFT channel material.” This is different from conventional, non-TFT, transistors where the active semiconductor channel material is typically a part of a semiconductor substrate, e.g., a part of a silicon wafer. Using the TFT  104  as a PMOS transistor integrated side-by-side with the III-N transistor  102  provides several advantages and enables unique architectures that were not possible with conventional transistors, although embodiments described herein are not limited to the TFT  104  being a PMOS transistor. For example, in some embodiments, the TFT  104  may be an NMOS transistor, or multiple TFTs  104  may be included in the IC structure  100  (e.g., as shown in  FIGS.  2 A- 2 C , each of which illustrating two TFTs,  104 - 1  and  104 - 2 ), e.g., with some being PMOS and other being NMOS transistors, e.g., to implement various CMOS circuits. 
     In various embodiments, the TFT  104  may be a TFT of any suitable architecture, e.g., a top-gated TFT or a back-gated TFT, with or without fins, etc., as known in the art. Furthermore, the TFT  104  may be an optimized TFT, which means that it may include one or more of 1) graded dopant concentrations in one or both of the S/D regions of the TFT  104 , 2) graded dopant concentrations in the channel region of the TFT  104 , and 3) thicker composite gate dielectrics in the gate stack of the TFT  104 .  FIGS.  2 A- 2 C  illustrate different example manners in which the TFT  104  may be implemented, according to some embodiments of the present disclosure. In particular, the IC structures  200 A,  200 B, and  200 C (together referred to as “IC structures  200 ”), shown in  FIGS.  2 A- 2 C , may be seen as examples of the IC structure  100  shown in  FIG.  1    with two examples of the TFT  104  being implemented according to different example variations of a top-gated optimized TFT. The two examples of the TFT  104  shown in  FIG.  2 A  are labeled as TFTs  104 A- 1  and  104 A- 2  (together referred to as “TFTs  104 A”), the two examples of the TFT  104  shown in  FIG.  2 B  are labeled as TFTs  104 B- 1  and  104 B- 2  (together referred to as “TFTs  104 B”), and the two examples of the TFT  104  shown in  FIG.  2 C  are labeled as TFTs  104 C- 1  and  104 C- 2  (together referred to as “TFTs  104 C”). One reason why each of  FIGS.  2 A- 2 C  illustrate two TFTs  104  is merely to illustrate the differences, for each of the embodiments of these figures, between PMOS and NMOS TFTs. In general, present descriptions related to integration of optimized TFTs with III-N transistors or any other III-N devices are applicable to and include embodiments where only a single optimized TFT is used, or when multiple optimized TFTs are used where any of the TFTs may be in accordance to any of the embodiments described herein. 
     Each of  FIGS.  2 A- 2 C  illustrates a cross-section of the IC structure  200  similar to that shown in  FIG.  1   , i.e., an x-z cross-section. Descriptions provided with reference to  FIG.  1    are applicable to the IC structures  200  of  FIGS.  2 A- 2 C  and, in the interests of brevity, are not repeated here. Instead, only the differences and additional details shown in  FIGS.  2 A- 2 C  are described. Similar to  FIG.  1   , a legend provided within a dashed box at the bottom of each of  FIGS.  2 A- 2 C  illustrates colors/patterns used to indicate some classes of materials of some of the elements shown in  FIGS.  2 A- 2 C . 
     Optimized TFTs with Dopant Concentration Grading in S/D Regions 
       FIG.  2 A  provides a cross-sectional side view illustrating an IC structure  200 A that may be a first example of the IC structure  100  of  FIG.  1   , with the TFT  104  having a horizontal dopant concentration gradient in S/D regions, according to some embodiments of the present disclosure. More specifically,  FIG.  2 A  illustrates two examples of the TFT  104  of  FIG.  1   , one being a PMOS TFT having a horizontal dopant concentration gradient in S/D regions and another one being an NMOS TFT having a horizontal dopant concentration gradient in S/D regions, according to some embodiments of the present disclosure. For example, consider that the TFT  104 A- 1  is a PMOS TFT and the TFT  104 A- 2  is an NMOS TFT (in other embodiments, their designation may be reversed). 
     As shown in  FIG.  2 A , both TFTs  104 A may be provided over a continuous portion of the III-N channel stack of the III-N material  112  and the polarization material  114 . A semiconductor material that will form the basis of the TFTs  104 A may then be provided over the III-N channel stack. In some embodiments, first, an undoped semiconductor material  246  may be provided over the III-N channel stack, in which then doped channel regions for different TFTs  104 A will be formed. In some such embodiments, as shown in  FIG.  2 A , the undoped semiconductor material  246  may be provided over the hard-mask material  126  that is provided over the polarization material  114 , possibly with a layer of an intermediate material  248 , e.g., silicon dioxide, provided between the undoped semiconductor material  246  and the hard-mask material  126 . In other such embodiments, not shown in  FIG.  2 A , the undoped semiconductor material  246  may be provided directly over the polarization material  114 , or some other intermediate material may be between the undoped semiconductor material  246  and the polarization material  114 , or the intermediate material  248  may be present but the hard-mask material  126  may be absent. The undoped semiconductor material  246  may include any suitable semiconductor material based on which the TFTs  104 A as described herein may be formed. In some embodiments, the undoped semiconductor material  246  may include a group IV semiconductor material, e.g., silicon, germanium, or silicon germanium. The term “undoped semiconductor material” is used to merely describe that the material  246  is not intentionally doped with dopant atoms. Of course, the undoped semiconductor material  246  may include unintentional impurities present therein, as often happens in semiconductor manufacturing. In general, a material may be described as “undoped” if concentration of dopant atoms present therein, either added deliberately or accidentally, is below about 10 15  cm −3 . 
     Each of the TFTs  104 A may include a TFT channel material  230 , which may be composed of semiconductor material systems including, for example, N-type or P-type materials systems, depending on whether the TFT  104  is a PMOS or an NMOS TFT. Thus, if the TFT  104 A is a PMOS TFT, then the channel material  230  would be an N-type material (i.e., a material doped with N-type dopant atoms), and, if the TFT  104 A is an NMOS TFT, then the channel material  230  would be a P-type material (i.e., a material doped with P-type dopant atoms). In some embodiments, the dopant concentration of the dopant atoms in the TFT channel material  230  (i.e., of the N-type dopants for a PMOS TFT  104 A and P-type dopants for an NMOS TFT  104 A) may be at least about 5×10 17  cm −3 , including all values and ranges therein, e.g., at least about 1×10 19  cm −3  or at least about 1×10 20  cm −3 . 
     In some embodiments, the TFT channel material  230  may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In general, the TFT channel material  230  may include one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, indium phosphide, and black phosphorus, each of which may possibly be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In particular, the TFT channel material  230  may be formed of a thin-film material. In some embodiments, the TFT channel material  230  may have a thickness between about 5 and 30 nanometers, including all values and ranges therein. 
     In some embodiments, the TFT channel material  230  may include one or more of a crystalline material, a polycrystalline semiconductor material, or a laminate of crystalline and polycrystalline materials. Such layers or laminates of crystalline and polycrystalline channel materials may be deposit by known chemical vapor deposition (CVD), sputter or epitaxial techniques, or by layer transfer techniques where a thin layer (e.g., a layer having a thickness of less than about 100 nanometers, or single to several monoatomic layers) of monocrystalline channel material is cleaved from another, donor, substrate and bonded to the support structure. In some embodiments, the TFT channel material  230  may include an amorphous material. In other embodiments, the TFT channel material  230  may include a crystalline and/or a polycrystalline material with crystalline grains larger (in at least one dimension) than about 10 nanometers, e.g., larger than about 50 nanometers, larger than about 60 nanometers, or larger than about 70 nanometers. Larger grains may advantageously provide higher mobility and less traps, so may be desirable for achieving adequate performance, variability, and reliability. 
     As any FET, each of the TFTs  104 A includes a pair of S/D regions  216  and a gate stack  244 . A channel portion of the TFT  104 A is the portion between the respective S/D regions  216  of the TFT, and adjacent to the gate stack  244 . 
       FIG.  2 A  illustrates an embodiment where the gate stack  244  of the TFT  104 A may include the gate dielectric material  120  and a gate electrode material  122 . In particular,  FIG.  2 A  illustrates that, in some embodiments, the TFT  104 A may be implemented as a top-gated (also referred to as “front-gated”) TFT, which means that at least a portion of the TFT channel material  230  may be between at least a portion of the gate dielectric material  120  of the gate stack  244  of the TFT  104 A and the support structure  108 , and which also means that at least a portion of the gate dielectric material  120  of the gate stack  244  may be between at least a portion of the gate electrode material  122  of the gate stack  244  and the support structure  108 . The top-gated architecture of the TFT  104 A may be particularly suitable for integrating the TFT  104  side-by-side with the III-N transistor  102 . 
     In general, the gate dielectric material  120  of the TFT  104 A may include any of the materials listed for the gate dielectric material  120  of the III-N transistor  102 , and may be either the same or different material than that selected for the gate dielectric material  120  of the III-N transistor  102 . Similarly, in general, any of the materials listed for the gate electrode material  122  of the III-N transistor  102  may be suitable for implementing the gate electrode material  122  for the TFT  104 A. 
     In some embodiments, some of the materials listed above for the gate electrode material  122  may be used both as the gate electrode material  122  for NMOS and PMOS transistors, e.g., for NMOS and PMOS TFTs  104 A. For example, titanium nitride is a “mid-gap” material with a workfunction that is between N-type and P-type. Therefore, it may be suitable both for implementing the TFT  104 A- 1  (e.g., a crystalline silicon or polysilicon TFT) as a PMOS transistor to provide the desired PMOS threshold voltage, and also for implementing the TFT  104 A- 2  (e.g., a crystalline silicon or polysilicon TFT) and/or the III-N transistor  102  as an NMOS transistor to provide the desired NMOS threshold voltage. Using the same gate electrode material for the PMOS and NMOS transistors may simplify fabrication as the gate electrode material for both of these types of transistors may then be deposited in a single deposition process. However, in other embodiments, various PMOS and NMOS transistors that may be present in the IC structures  100 / 200  may use different gate electrode materials. 
     In some embodiments, to implement an NMOS transistor (e.g., to implement an NMOS III-N transistor  102  and/or the NMOS TFT  104 A- 2 ), the gate electrode material  122  may include one or more of hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), while to implement a PMOS transistor (e.g., to implement the PMOS TFT  104 A- 1 ), the gate electrode material  122  may include ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). 
     When the TFT  104 A is implemented as a PMOS transistor, some of the TFT channel materials listed above for the TFT channel material  230  may be more suitable than others. Some examples of the TFT channel material  230  particularly suitable for a PMOS implementation of the TFT  104 A include, but are not limited to, silicon, silicon germanium, germanium, indium antimonide, III-V materials (e.g., gallium arsenide), indium tin oxide, molybdenum diselenide, tungsten diselenide, and black phosphorus. On the other hand, some examples of the TFT channel material  230  particularly suitable for an NMOS implementation of the TFT  104 A include, but are not limited to, silicon, silicon germanium, germanium, III-V materials (e.g., gallium arsenide), zinc oxide, gallium oxide, titanium oxide, and IGZO. 
     Although not specifically shown in the present figures, in some embodiments, the gate electrode of the III-N transistor  102  may be electrically coupled to the gate electrode of the TFT  104 . When the TFT  104  is implemented as a PMOS transistor, and the III-N transistor  102  is implemented as an NMOS transistor, such a configuration where the gates of these transistors are electrically coupled may be used to implement an inverter device. In other embodiments, the gate electrode of the first TFT  104 A- 1  may be coupled to the gate electrode of the second TFT  104 A- 2 . When the first TFT  104 A- 1  is implemented as a PMOS transistor, and the second TFT  104 A- 2  is implemented as an NMOS transistor, such a configuration where the gates of these transistors are electrically coupled may also be used to implement an inverter device. 
     In other embodiments of the IC structure  100 / 200 , both the TFT  104  and the III-N transistor  102  may be implemented as NMOS devices, or both the TFT  104  and the III-N transistor  102  may be implemented as PMOS devices. In some such embodiments, the TFT  104  and the III-N transistor  102  may still have their gate electrodes coupled or shared (again, not specifically shown in the present figures). Such modified IC structures  100  may be included in any circuits that use cascaded transistors of the same type, such as gate protection circuits. Similarly, in other embodiments of the IC structure  200 , both the first TFT  104 A- 1  and the second TFT  104 A- 2  may be implemented as NMOS devices, or both the first TFT  104 A- 1  and the second TFT  104 A- 2  may be implemented as PMOS devices. In some such embodiments, the first TFT  104 A- 1  and the second TFT  104 A- 2  may still have their gate electrodes coupled or shared (again, not specifically shown in the present figures) and such modified IC structures  200 A may be included in any circuits that use cascaded transistors of the same type, such as gate protection circuits. 
     Turning to the S/D regions  216  of the TFTs  104 A, a shown in  FIG.  2 A , similar to the S/D regions  116  of the III-N transistor  102 , the S/D regions  216  of the TFT  104  include two S/D regions  216 , where one of these two S/D regions  216  is a source region and another one is a drain region. Also similar to the S/D regions  116 , for each of the TFTs  104 A, S/D electrodes  242  may be provided above the TFT channel material  230 , in particular, interfacing the S/D regions  216  of said TFT  104 A. In various embodiments, the same or different ones of the electrically conductive material  118  may be used to implement the S/D electrodes  142  of the III-N transistor  102  and the S/D electrodes  242  of the TFTs  104 A. 
     Also similar to the S/D regions  116 , each of the S/D regions  216  may include portions containing highly doped semiconductor materials. However, for the embodiment of optimized TFTs illustrated in  FIG.  2 A , the doping of the S/D regions  216  may be nuanced further. In particular, as shown in  FIG.  2 A , in some embodiments, each of the S/D regions  216  of the TFTs  104 A may include two portions, shown as a first portion  216 - 1  and a second portion  216 - 2 , which are example portions of different dopant concentrations. For each of such S/D regions  216 , the portion of the S/D region  216  that is further away from the gate stack  244  would have a higher dopant concentration than the portion of the S/D region  216  that is closer to the gate stack  244 . Thus, the first portion  216 - 1  has a higher dopant concentration of dopants than the second portion  216 - 2 , for each of the S/D regions  216  where horizontal grading in S/D regions is implemented. In some embodiments, the dopant concentration in the first portion  216 - 1  may be at least about 5×10 19  cm −3 , including all values and ranges therein, e.g., at least about 1×10 20  cm −3  or at least about 1×10 21  cm −3 . In some embodiments, the dopant concentration in the second portion  216 - 2  may be below about 1×10 18  cm −3 , including all values and ranges therein, e.g., below about 5×10 17  cm −3  or below about 1×10 17  cm −3 . It should be noted that the dopant concentrations are given for the majority dopant type, and that which type of dopants is a majority dopant type in the S/D region  216  would be different depending on whether the TFT  104 A is a PMOS or an NMOS transistor. Namely, dopant concentrations in different portions of S/D regions  216  as described herein are dopant concentrations of P-type dopants if the TFT  104 A is a PMOS transistor, and are dopant concentrations of N-type dopants if the TFT  104 A is an NMOS transistor. Furthermore, in the present disclosure, various dopant concentration values refer to values of net majority dopants. For example, an N-type material may include dopant atoms of not only N-type (majority dopants) but also P-type (minority dopants). A dopant concentration of such a material then refers to the difference between the dopant atoms of N-type and the dopant atoms of P-type, which is the net value. 
     While only two portions of different dopant concentrations are shown in the schematic illustration of  FIG.  2 A , in other embodiments, more portions of different dopant concentrations may be included in each of the S/D regions  216 , as long as the dopant concentration gradually decreases from the portion of the S/D region  216  that is the farthest away from the gate stack  244 , towards the gate stack  244 . In some embodiments, the dopant concentrations described herein may be seen as average values for certain portions of a given S/D region  216  (e.g., an average value for the first portion  216 - 1  and an average value for the second portion  216 - 2 ). 
     In some embodiments, the portion of the S/D region  216  closest to the gate stack  244  may overlap with a portion of the gate stack  244 . The overlap is indicated in  FIG.  2 A  as a distance  232  (only one overlap is labeled with the reference numeral  232  in  FIG.  2 A —the one between the second portion  216 - 2  of the S/D region  216  on the left side of the first TFT  104 A- 1 —the second portions  216 - 2  of other S/D regions  216  shown in  FIG.  2 A  also have similar overlaps, but those are not labeled in order to not clutter the drawing). In some embodiments, the distance  232  may be less than about 10 percent of a gate length of the TFT  104 A, including all values and ranges therein, e.g., anywhere between 0.1 and 8 percent or anywhere between 0.1 and 3 percent of the gate length. 
     While  FIG.  2 A  illustrates both S/D regions  216  of both of the TFTs  104 A to have graded dopant concentrations, in other embodiments, only one of the S/D regions  216  may include graded dopant concentrations, while other S/D regions of the TFTs  104 A may be doped substantially uniformly (e.g., as shown with uniformly doped S/D regions  216  in  FIGS.  2 B and  2 C ). 
     To summarize, for a PMOS TFT  104 A (e.g., the TFT  104 A- 1 ), the TFT channel material  230  is an N-type material (i.e., a material having dopant concentration of N-type dopants higher than that of P-type dopants), while various portions of the S/D regions  216  are P-type materials (i.e., material having dopant concentration of P-type dopants higher than that of N-type dopants) that may have horizontal dopant concentration gradient as described herein. On the other hand, for an NMOS TFT  104 A (e.g., the TFT  104 A- 2 ), the TFT channel material  230  is a P-type material, while various portions of the S/D regions  216  are N-type materials that may have horizontal dopant concentration gradient as described herein. 
     Optimized TFTs with Dopant Concentration Grading in Channel Regions 
       FIG.  2 B  provides a cross-sectional side view illustrating an IC structure  200 B that may be a second example of the IC structure  100  of  FIG.  1   , with the TFT  104  having a vertical dopant concentration gradient in a channel region, according to some embodiments of the present disclosure. Similar to  FIG.  2 A ,  FIG.  2 B  illustrates two examples of the TFT  104  of  FIG.  1   , one being a PMOS TFT having a vertical dopant concentration gradient in its&#39; channel region and another one being an NMOS TFT having a vertical dopant concentration gradient in its&#39; channel region, according to some embodiments of the present disclosure. The IC structure  200 B may be substantially the same as the IC structure  200 A, with the TFTs  104 B being substantially the same as the TFTs  104 A, except for the vertical dopant concentration gradient in the channel regions of one or both of the TFTs  104 B and except that none of the S/D regions of the TFTs  104 B may implement horizontal dopant concentration gradient as described with reference to  FIG.  2 A . In view of this, in the interests of brevity, descriptions provided with reference to the IC structure  200 A of  FIG.  2 A  are assumed to be applicable to the IC structure  200 B of  FIG.  2 B  and are not repeated, and only the differences are described. 
     The TFTs  104 B are shown in  FIG.  2 B  to have S/D regions  216  of substantially uniform dopant concentration, but in some embodiments (not shown in the present figures), one or more of the S/D regions  216  of the TFTs  104 B in the IC structure  200 B may have horizontal dopant concentration gradients as described with reference to  FIG.  2 A . 
     In contrast to  FIG.  2 A ,  FIG.  2 B  illustrates that the TFT channel material  230  of a given TFT  104 B may include two portions, shown as a first portion  230 - 1  and a second portion  230 - 2 , which are example portions of different dopant concentrations in the TFT channel material  230 . In particular, the portion of the TFT channel material  230  that is further away from the gate stack  244  may have a higher dopant concentration than the portion of the TFT channel material  230  that is closer to the gate stack  244 . Thus, the first portion  230 - 1  has a higher dopant concentration of dopants than the second portion  230 - 2 , for each of the TFTs  104 B where vertical grading in channel region is implemented. In some embodiments, the dopant concentration in the first portion  230 - 1  may be at least about 5×10 17  cm −3 , including all values and ranges therein, e.g., at least about 1×10 19  cm −3  or at least about 1×10 20  cm −3 . In some embodiments, the dopant concentration in the second portion  230 - 2  may be below about 1×10 17  cm −3 , including all values and ranges therein, e.g., below about 1×10 16  cm −3  or below about 1×10 15  cm −3 . It should be noted that the dopant concentrations are net values given for the majority dopant type, and which type of dopants is a majority dopant type in the channel material  230  would be different depending on whether the TFT  104 A is a PMOS or an NMOS transistor. Namely, dopant concentrations in different portions of the TFT channel material  230  as described herein are dopant concentrations of N-type dopants if the TFT  104 B is a PMOS transistor, and are dopant concentrations of P-type dopants if the TFT  104 B is an NMOS transistor. 
     While only two portions of different dopant concentrations are shown in the schematic illustration of  FIG.  2 B , in other embodiments, more portions of different dopant concentrations may be included in the TFT channel material  230  of any of the TFTs  104 B, as long as the dopant concentration gradually increases from the portion of the TFT channel material  230  that is the closest to the gate stack  244  to the portion of the TFT channel material  230  farther away from the gate stack  244 . In some embodiments, the dopant concentrations described herein may be seen as average values for certain portions of the TFT channel material  230  (e.g., an average value for the first portion  230 - 1  and an average value for the second portion  230 - 2 ). 
     In some embodiments, the portions of vertical dopant concentration gradient in the TFT channel material  230  may be directly under the gate stack  244 , as shown in the examples of  FIG.  2 B . In other embodiments, the portions may slightly extend beyond the edges of the gate stack  244 , or may be under the middle portion of the gate stack  244  but not quite come to the edges of the gate stack  244 . In some embodiments, a thickness (or a depth) of the portion of the TFT channel material  230  with the lowest dopant concentration of the majority dopants (e.g., a depth of the second portion  230 - 2 ) may be between about 1 and 15 nanometers, including all values and ranges therein, e.g., between about 1 and 10 nanometers, or between about 1 and 5-7 nanometers. Such a shallow layer of lower dopant concentration is intended to create a quantum well in the portion of the TFT channel material  230  closest to the gate stack, which may improve confinement of charge carriers in that portion and may lead to improvements in terms of hot carrier effects and device reliability. 
     While  FIG.  2 B  illustrates the channel material  230  of each of the TFTs  104 B to have a graded dopant concentration, in other embodiments, only one of the TFTs  104 B may include graded dopant concentration in the channel material  230 , while the channel materials  230  of other TFTs  104 B may be doped substantially uniformly (e.g., as shown with uniformly doped channel materials  230  in  FIGS.  2 A and  2 C ). 
     To summarize, for a PMOS TFT  104 B (e.g., the TFT  104 B- 1 ), the TFT channel material  230  is an N-type material that may have vertical dopant concentration gradient as described herein, while the S/D regions  216  are P-type materials. On the other hand, for an NMOS TFT  104 B (e.g., the TFT  104 B- 2 ), the TFT channel material  230  is a P-type material that may have vertical dopant concentration gradient as described herein, while various portions of the S/D regions  216  are N-type materials. 
     Optimized TFTs with Composite Gate Dielectrics 
       FIG.  2 C  provides a cross-sectional side view illustrating an IC structure  200 C that may be a third example of the IC structure  100  of  FIG.  1   , with the TFT  104  having a composite gate dielectric in a gate stack, according to some embodiments of the present disclosure. Similar to  FIGS.  2 A and  2 B ,  FIG.  2 C  illustrates two examples of the TFT  104  of  FIG.  1   , one being a PMOS TFT and another one being an NMOS TFT, each having a composite gate dielectric in its&#39; gate stack, according to some embodiments of the present disclosure. The IC structure  200 C may be substantially the same as the IC structure  200 A or the IC structure  200 B, with the TFTs  104 C being substantially the same as the TFTs  104 A or the TFTs  104 B, except for the composite gate dielectrics in the gate stacks of one or both of the TFTs  104 C and except that none of the S/D regions  216  of the TFTs  104 C may implement horizontal dopant concentration gradient as described with reference to  FIG.  2 A  and/or none of the TFT channel materials  230  of the TFTs  104 C may implement vertical dopant concentration gradient as described with reference to  FIG.  2 B . In view of this, in the interests of brevity, descriptions provided with reference to the IC structure  200 A of  FIG.  2 A  and/or with reference to the IC structure  200 B of  FIG.  2 B  are assumed to be applicable to the IC structure  200 C of  FIG.  2 C  and are not repeated, and only the differences are described. 
     The TFTs  104 C are shown in  FIG.  2 C  to have S/D regions  216  of substantially uniform dopant concentration, but in some embodiments (not shown in the present figures), one or more of the S/D regions  216  of the TFTs  104 C in the IC structure  200 C may have horizontal dopant concentration gradients as described with reference to  FIG.  2 A . The TFTs  104 C are shown in  FIG.  2 C  to TFT channel materials  230  of substantially uniform dopant concentration, but in some embodiments (not shown in the present figures), the TFT channel material  230  of one or more of the TFTs  104 C in the IC structure  200 C may have vertical dopant concentration gradients as described with reference to  FIG.  2 B . In some embodiments, one or more of the TFTs  104 C may include both the horizontal dopant concentration gradients in one or more S/D regions  216  as described with reference to  FIG.  2 A  and the vertical dopant concentration gradients in the channel material  230  as described with reference to  FIG.  2 B . 
     In contrast to  FIGS.  2 A and  2 B ,  FIG.  2 C  illustrates that the gate dielectric material  220  of a given TFT  104 C may include two portions, shown as a first portion  220 - 1  and a second portion  220 - 2 , which are example portions of different dielectric constant values in the gate dielectric material  220 . The second portion  220 - 2  may be a portion between the first portion  220 - 1  and the TFT channel material  230 . The first portion  220 - 1  may be a portion between the second portion  220 - 2  and the gate electrode material  122 . In particular, the portion of the gate dielectric material  220  that is farther away from the TFT channel material  230  may have a higher dielectric constant than the portion of the gate dielectric material  220  that is closer to the TFT channel material. Thus, the first portion  220 - 1  has a higher dielectric constant than the second portion  220 - 2 , for each of the TFTs  104 C where composite gate dielectric is implemented. In some embodiments, the dielectric constant of the first portion  220 - 1  of the gate dielectric may be greater than a dielectric constant of silicon dioxide. In some embodiments, the dielectric constant of the second portion  220 - 2  of the gate dielectric may be lower than a dielectric constant of silicon dioxide. In some embodiments, a thickness of each of the first portion  220 - 1  of the gate dielectric and the second portion  220 - 2  of the gate dielectric may be between about 1 and 5 nanometers, including all values and ranges therein, e.g., between about 1 and 4 nanometers, or between about 1 and 3 nanometers. In some embodiments, the thicknesses of the first portion  220 - 1  and the second portion  220 - 2  may be substantially equal. In other embodiments, the thicknesses of the first portion  220 - 1  and the second portion  220 - 2  may be different. 
     While only two portions of different dielectric constants are shown in the schematic illustration of  FIG.  2 C , in other embodiments, more portions of different dielectric constants may be included in the gate dielectric material  220  of any of the TFTs  104 C, as long as the dielectric constant value gradually increases from the portion of the gate dielectric material  220  that is the closest to the channel material  230  to the portion of the gate dielectric material  220  farther away from the channel material  230 . In some embodiments, the dielectric constants described herein may be seen as average values for certain portions of the gate dielectric material  220  (e.g., an average value for the first portion  220 - 1  and an average value for the second portion  220 - 2 ). 
     While  FIG.  2 C  illustrates the gate dielectric material  220  of each of the TFTs  104 C to have a graded dielectric constant, in other embodiments, only one of the TFTs  104 C may include a graded dielectric constant in the gate dielectric material  220 , while the gate dielectric material  220  of other TFTs  104 C may have a substantially uniform dielectric constant throughout (e.g., as shown with uniform gate dielectric materials  220  in  FIGS.  2 B and  2 C ). 
     The IC structures  100  illustrated in  FIGS.  1 - 2    do not represent an exhaustive set of assemblies in which one or more III-N transistors  102  may be integrated with one or more optimized TFTs  104  over a single support structure  108  (e.g., a substrate), as described herein, but merely provide examples of such structures/assemblies. Although particular arrangements of materials are discussed with reference to  FIGS.  1 - 2   , intermediate materials may be included in various portions of these figures. Note that  FIGS.  1 - 2    are intended to show relative arrangements of some of the components therein, and that various device components of these figures may include other components that are not specifically illustrated, e.g., various interfacial layers or various additional layers or elements. For example, although not specifically shown, the IC structure  100  may include a solder resist material (e.g., polyimide or similar material) and one or more bond pads formed on upper-most interconnect layer of the IC structure, e.g., at the top of the IC structures  100 / 200  shown in  FIGS.  1 - 2   . The bond pads may be electrically coupled with a further interconnect structure and configured to route the electrical signals between the III-N transistor  102  and other external devices, and/or between the TFT  104  and other external devices. For example, solder bonds may be formed on the one or more bond pads to mechanically and/or electrically couple a chip including the IC structure  100  with another component (e.g., a circuit board). The IC structure  100  may have other alternative configurations to route the electrical signals from the interconnect layers, e.g., the bond pads described above may be replaced by or may further include other analogous features (e.g., posts) that route the electrical signals to external components. 
     Additionally, although some elements of the IC structures are illustrated in  FIGS.  1 - 2    as being planar rectangles or formed of rectangular solids, this is simply for ease of illustration, and embodiments of various ones of these elements may be curved, rounded, or otherwise irregularly shaped as dictated by, and sometimes inevitable due to, the manufacturing processes used to fabricate semiconductor device assemblies. For example, while  FIGS.  1 - 2    may illustrate various elements, e.g., the S/D regions  116 / 216 , the S/D electrodes  142 / 242 , etc., as having perfectly straight sidewall profiles, i.e., profiles where the sidewalls extend perpendicularly to the support structure  108 , these idealistic profiles may not always be achievable in real-world manufacturing processes. Namely, while designed to have straight sidewall profiles, real-world openings that may be formed as a part of fabricating various elements of the IC structures shown in  FIGS.  1 - 2    may end up having either so-called “re-entrant” profiles, where the width at the top of the opening is smaller than the width at the bottom of the opening, or “non-re-entrant” profile, where the width at the top of the opening is larger than the width at the bottom of the opening. Oftentimes, as a result of a real-world opening not having perfectly straight sidewalls, imperfections may form within the materials filling the opening. For example, typical for re-entrant profiles, a void may be formed in the center of the opening, where the growth of a given material filling the opening pinches off at the top of the opening. Therefore, descriptions of various embodiments of integrating one or more III-N transistors with one or more optimized TFTs provided herein are equally applicable to embodiments where various elements of such integrated structures look different from those shown in the figures due to manufacturing processes used to form them. 
     Inspection of layout and mask data and reverse engineering of parts of a device to reconstruct the circuit using e.g., optical microscopy, TEM, or SEM, and/or inspection of a cross-section of a device to detect the shape and the location of various device elements described herein using e.g., Physical Failure Analysis (PFA) would allow determination of the integration of one or more III-N transistors with one or more TFTs as described herein. 
     Manufacturing Optimized TFTs Integrated with III-N Transistors 
     The IC structures implementing one or more III-N transistors integrated with one or more optimized TFTs as described herein may be manufactured using any suitable techniques.  FIG.  3    illustrates one example of such a method. However, other examples of manufacturing any of the IC structures described herein, as well as larger devices and assemblies that include such structures (e.g., as shown in  FIGS.  6 - 9   ) are also within the scope of the present disclosure. 
       FIG.  3    is a flow diagram of an example method  300  of manufacturing an IC structure that includes a III-N transistor integrated with an optimized TFT, in accordance with various embodiments of the present disclosure. 
     Although the operations of the method  300  are illustrated once each and in a particular order, the operations may be performed in any suitable order and repeated as desired. For example, one or more operations may be performed in parallel to manufacture, substantially simultaneously, multiple III-N transistors and/or multiple optimized TFTs as described herein. In another example, the operations may be performed in a different order to reflect the structure of a particular device assembly in which one or more III-N transistors integrated with one or more optimized TFTs as described herein will be included. 
     In addition, the example manufacturing method  300  may include other operations not specifically shown in  FIG.  3   , such as various cleaning or planarization operations as known in the art. For example, in some embodiments, the support structure  108 , as well as layers of various other materials subsequently deposited thereon, may be cleaned prior to, after, or during any of the processes of the method  300  described herein, e.g., to remove oxides, surface-bound organic and metallic contaminants, as well as subsurface contamination. In some embodiments, cleaning may be carried out using e.g., a chemical solutions (such as peroxide), and/or with ultraviolet (UV) radiation combined with ozone, and/or oxidizing the surface (e.g., using thermal oxidation) then removing the oxide (e.g., using hydrofluoric acid (HF)). In another example, the structures/assemblies described herein may be planarized prior to, after, or during any of the processes of the method  300  described herein, e.g., to remove overburden or excess materials. In some embodiments, planarization may be carried out using either wet or dry planarization processes, e.g., planarization be a chemical mechanical planarization (CMP), which may be understood as a process that utilizes a polishing surface, an abrasive and a slurry to remove the overburden and planarize the surface. 
     Various operations of the method  300  may be illustrated with reference to the example embodiment shown in  FIGS.  4 A- 4 D , illustrating fabrication of an IC structure as shown in the example of  FIG.  2 A , but the method  300  may be used to manufacture any suitable IC structures having one or more III-N transistors integrated with one or more optimized TFTs according to any other embodiments of the present disclosure.  FIGS.  4 A- 4 D  illustrate cross-sectional side views similar to the view shown in  FIG.  2 A , in various example stages in the manufacture of an IC structure using the method of  FIG.  3    in accordance with some embodiments of the present disclosure. 
     The method  300  may begin with providing a support structure (process  302  shown in  FIG.  3   , a result of which is illustrated with an IC structure  402  shown in  FIG.  4 A ). The IC structure  402  illustrates that the support structure provided in  302  may be the support structure  108  as described above. 
     The method  300  may then proceed with providing a layer of a III-N semiconductor material over the support structure provided in  302  (process  304  shown in  FIG.  3   , a result of which is illustrated with an IC structure  404  shown in  FIG.  4 B ). The IC structure  404  illustrates that, first, the buffer material  124  may be provided over the support structure  108 , and then the III-N material  112  may be provided over the buffer material  124 . In some embodiments, the process  304  may also include depositing the polarization material  114  over the III-N material  112 , and, optionally, of the hard-mask material  126  over the polarization material  114 . 
     In some embodiments, the process  304  may include epitaxially growing various transistor films, e.g., for forming the buffer material  124 , the III-N material  112 , and the polarization material  114 . In this context, “epitaxial growth” refers to the deposition of crystalline overlayers in the form of the desired materials. The epitaxial growth of various layers of the process  304  may be carried out using any known gaseous or liquid precursors for forming the desired material layers. 
     The method  300  may then proceed with providing a TFT channel material for one or more of future optimized TFTs integrated over the III-N semiconductor material provided in  304  (process  306  shown in  FIG.  3   , a result of which is illustrated with an IC structure  406  shown in  FIG.  4 C ). The IC structure  406  illustrates that, first, optionally, the intermediate material  248  may be provided over the III-N channel stack provided in  304 , and then the undoped semiconductor material  246  may be provided over the intermediate material  248 . In some embodiments, the process  306  may include deposition techniques such as epitaxially growing various transistor films, or layer transfer techniques from a separate donor wafer, e.g., for forming the undoped semiconductor material  246 . 
     The method  300  may then proceed with providing various doped regions and/or composite dielectrics for one or more of future optimized TFTs provided based on the undoped semiconductor material  246  provided in  306  (process  308  shown in  FIG.  3   , a result of which is illustrated with an IC structure  408  shown in  FIG.  4 D ). The IC structure  408  illustrates that the undoped semiconductor material  246  may serve as a foundation for forming different TFT channel materials  230  based on whether the TFT channel material  230  is to be an N-type material for a PMOS TFT or a P-type material for an NMOS TFT. The IC structure  408  also illustrates that the undoped semiconductor material  246  may serve as a foundation for forming different S/D region portions  216  as described above. Although not shown in  FIGS.  4 A- 4 D , in other embodiments, the process  308  may include providing vertically doped portions in the channel material, as described with reference to  FIG.  2 B , and/or providing composite gate dielectric materials  220 , as described with reference to  FIG.  2 C . 
     In some embodiments of the process  308 , the S/D regions  216  or different portions thereof (as well as S/D regions  116  for the III-N transistor  102 ) may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the TFT channel material  230  to form the S/D regions  216  or different portions thereof. An annealing process that activates the dopants and causes them to diffuse farther into the TFT channel material  230  may follow the ion-implantation process. In some embodiments, annealing may be performed at temperatures above about 600 degrees Celsius, e.g., at temperatures between about 600 and 1200 degrees Celsius, or at temperatures between about 800 or 1000 and 1200 degrees Celsius. In the latter process, the TFT channel material  230  may first be etched to form recesses at the locations of the S/D regions  216 , or different portions thereof. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions  216 . In some implementations, the S/D regions  216  or different portions thereof may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions  216  or different portions thereof may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions  216  or different portions thereof. 
     In embodiments where  308  includes providing composite gate dielectric portions as described with reference to  FIG.  2 C , differences in the dielectric constant may be achieved by varying compositions of the chemical constituents of the gate dielectric films, for e.g., SiN has a higher dielectric constant than SiO 2  while SiO x N y  has a dielectric constant between that of SiN and SiO 2 . Another method is to introduce alternating laminates of one or more of the gate dielectric films for example, HfO 2  has a dielectric constant higher than Al 2 O 3 , and therefore a stack comprising alternating layers of Al 2 O 3  and HfO 2  will have an effective dielectric constant in between that of HfO 2  and Al 2 O 3 . 
     The method  300  may also include providing further portions of III-N transistor  102  and/or the one or more TFTs  104  (process  310  shown in  FIG.  3   , a result of which is not illustrated in  FIG.  4    because the result could be, e.g., the IC structure  100  shown in  FIG.  1    or any of the IC structures  200 A,  200 B, or  200 C, as shown in  FIG.  2   , or any combination thereof, or any further embodiments of these IC structures as described herein). 
     In various embodiments, various processes of the method  300  may include any suitable deposition and patterning techniques for fabricating portions of the III-N transistor  102  and the TFT  104 . For example, any suitable deposition techniques may be used to deposit the insulator  110 , such as, but not limited to, spin-coating, dip-coating, atomic layer deposition (ALD), physical vapor deposition (PVD) (e.g., evaporative deposition, magnetron sputtering, or e-beam deposition), or chemical vapor deposition (CVD). Examples of deposition techniques that may be used to provide various electrode materials include, but are not limited to, ALD, PVD (including sputtering), CVD, or electroplating. Examples patterning techniques that may be used in any of the processes of the method  300  may include, but are not limited to, photolithographic or electron-beam (e-beam) patterning, possibly in conjunction with a suitable etching technique, e.g., a dry etch, such as RF reactive ion etch (RIE) or inductively coupled plasma (ICP) RIE. In various embodiments, any of the etches performed in the method  300  may include an anisotropic etch, using etchants in a form of e.g., chemically active ionized gas (i.e., plasma) using e.g., bromine (Br) and chloride (CI) based chemistries. In some embodiments, during any of the etches of the method  300 , the IC structure may be heated to elevated temperatures, e.g., to temperatures between about room temperature and 200 degrees Celsius, including all values and ranges therein, to promote that byproducts of the etch are made sufficiently volatile to be removed from the surface. 
     Example Structures and Devices with III-N Devices Integrated with Optimized TFTs 
     IC structures that include at least one III-N device (e.g., at least one III-N transistor) integrated with one or more optimized TFTs as disclosed herein may be included in any suitable electronic device.  FIGS.  5 - 9    illustrate various examples of devices and components that may include one or more III-N devices integrated with one or more optimized TFTs as disclosed herein. 
       FIGS.  5 A- 5 B  are top views of a wafer  2000  and dies  2002  that may include one or more optimized TFTs (e.g., one or more TFTs with graded dopant concentrations and/or composite gate dielectrics) integrated with one or more III-N transistors in accordance with any of the embodiments disclosed herein. In some embodiments, the dies  2002  may be included in an IC package, in accordance with any of the embodiments disclosed herein. For example, any of the dies  2002  may serve as any of the dies  2256  in an IC package  2200  shown in  FIG.  6   . The wafer  2000  may be composed of semiconductor material and may include one or more dies  2002  having IC structures formed on a surface of the wafer  2000 . Each of the dies  2002  may be a repeating unit of a semiconductor product that includes any suitable IC (e.g., ICs including at least one transmission line structure integrated with one or more III-N devices as described herein). After the fabrication of the semiconductor product is complete (e.g., after manufacture of at least one optimized TFT integrated with one or more III-N devices as described herein, e.g., after manufacture of any embodiment of the IC structures  100 / 200  described herein), the wafer  2000  may undergo a singulation process in which each of the dies  2002  is separated from one another to provide discrete “chips” of the semiconductor product. In particular, devices that include one or more optimized TFTs integrated with one or more III-N devices as disclosed herein may take the form of the wafer  2000  (e.g., not singulated) or the form of the die  2002  (e.g., singulated). The die  2002  may include one or more optimized TFTs, one or more III-N devices, e.g., III-N transistors, as well as, optionally, supporting circuitry to route electrical signals to the optimized TFTs and/or the III-N devices, as well as any other IC components. In some embodiments, the wafer  2000  or the die  2002  may implement an RF FE device, a memory device (e.g., a static random-access memory (SRAM) device), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die  2002 . 
       FIG.  6    is a side, cross-sectional view of an example IC package  2200  that may include optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. In some embodiments, the IC package  2200  may be a system-in-package (SiP). 
     As shown in  FIG.  6   , the IC package  2200  may include a package substrate  2252 . The package substrate  2252  may be formed of a dielectric material (e.g., a ceramic, a glass, a combination of organic and inorganic materials, a buildup film, an epoxy film having filler particles therein, etc., and may have embedded portions having different materials), and may have conductive pathways extending through the dielectric material between the face  2272  and the face  2274 , or between different locations on the face  2272 , and/or between different locations on the face  2274 . 
     The package substrate  2252  may include conductive contacts  2263  that are coupled to conductive pathways  2262  through the package substrate  2252 , allowing circuitry within the dies  2256  and/or the interposer  2257  to electrically couple to various ones of the conductive contacts  2264  (or to other devices included in the package substrate  2252 , not shown). 
     The IC package  2200  may include an interposer  2257  coupled to the package substrate  2252  via conductive contacts  2261  of the interposer  2257 , first-level interconnects  2265 , and the conductive contacts  2263  of the package substrate  2252 . The first-level interconnects  2265  illustrated in  FIG.  6    are solder bumps, but any suitable first-level interconnects  2265  may be used. In some embodiments, no interposer  2257  may be included in the IC package  2200 ; instead, the dies  2256  may be coupled directly to the conductive contacts  2263  at the face  2272  by first-level interconnects  2265 . 
     The IC package  2200  may include one or more dies  2256  coupled to the interposer  2257  via conductive contacts  2254  of the dies  2256 , first-level interconnects  2258 , and conductive contacts  2260  of the interposer  2257 . The conductive contacts  2260  may be coupled to conductive pathways (not shown) through the interposer  2257 , allowing circuitry within the dies  2256  to electrically couple to various ones of the conductive contacts  2261  (or to other devices included in the interposer  2257 , not shown). The first-level interconnects  2258  illustrated in  FIG.  6    are solder bumps, but any suitable first-level interconnects  2258  may be used. As used herein, a “conductive contact” may refer to a portion of electrically conductive material (e.g., metal) serving as an interface between different components; conductive contacts may be recessed in, flush with, or extending away from a surface of a component, and may take any suitable form (e.g., a conductive pad or socket). 
     In some embodiments, an underfill material  2266  may be disposed between the package substrate  2252  and the interposer  2257  around the first-level interconnects  2265 , and a mold compound  2268  may be disposed around the dies  2256  and the interposer  2257  and in contact with the package substrate  2252 . In some embodiments, the underfill material  2266  may be the same as the mold compound  2268 . Example materials that may be used for the underfill material  2266  and the mold compound  2268  are epoxy mold materials, as suitable. Second-level interconnects  2270  may be coupled to the conductive contacts  2264 . The second-level interconnects  2270  illustrated in  FIG.  6    are solder balls (e.g., for a ball grid array arrangement), but any suitable second-level interconnects  22770  may be used (e.g., pins in a pin grid array arrangement or lands in a land grid array arrangement). The second-level interconnects  2270  may be used to couple the IC package  2200  to another component, such as a circuit board (e.g., a motherboard), an interposer, or another IC package, as known in the art and as discussed below with reference to  FIG.  7   . 
     The dies  2256  may take the form of any of the embodiments of the die  2002  discussed herein and may include any of the embodiments of an IC structure having at least one optimized TFT integrated with one or more III-N devices, described herein. In embodiments in which the IC package  2200  includes multiple dies  2256 , the IC package  2200  may be referred to as a multi-chip-package (MCP). The dies  2256  may include circuitry to perform any desired functionality. For example, one or more of the dies  2256  may be RF FE dies, including one or more optimized TFTs integrated with one or more III-N devices in a single die as described herein, one or more of the dies  2256  may be logic dies (e.g., silicon-based dies), one or more of the dies  2256  may be memory dies (e.g., high bandwidth memory), etc. In some embodiments, any of the dies  2256  may include at least one optimized TFT integrated with one or more III-N devices, e.g., as discussed above; in some embodiments, at least some of the dies  2256  may not include any optimized TFTs and/or not include any III-N devices as described herein. 
     The IC package  2200  illustrated in  FIG.  6    may be a flip chip package, although other package architectures may be used. For example, the IC package  2200  may be a ball grid array (BGA) package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package  2200  may be a wafer-level chip scale package (WLCSP) or a panel fan-out (FO) package. Although two dies  2256  are illustrated in the IC package  2200  of  FIG.  6   , an IC package  2200  may include any desired number of the dies  2256 . An IC package  2200  may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed on the first face  2272  or the second face  2274  of the package substrate  2252 , or on either face of the interposer  2257 . More generally, an IC package  2200  may include any other active or passive components known in the art. 
       FIG.  7    is a cross-sectional side view of an IC device assembly  2300  that may include components having one or more IC structures implementing optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. The IC device assembly  2300  includes a number of components disposed on a circuit board  2302  (which may be, e.g., a motherboard). The IC device assembly  2300  includes components disposed on a first face  2340  of the circuit board  2302  and an opposing second face  2342  of the circuit board  2302 ; generally, components may be disposed on one or both faces  2340  and  2342 . In particular, any suitable ones of the components of the IC device assembly  2300  may include any of the IC structures implementing at least one optimized TFT integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein; e.g., any of the IC packages discussed below with reference to the IC device assembly  2300  may take the form of any of the embodiments of the IC package  2200  discussed above with reference to  FIG.  6    (e.g., may include at least one optimized TFT integrated with one or more III-N devices in/on a die  2256 ). 
     In some embodiments, the circuit board  2302  may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board  2302 . In other embodiments, the circuit board  2302  may be a non-PCB substrate. 
     The IC device assembly  2300  illustrated in  FIG.  7    includes a package-on-interposer structure  2336  coupled to the first face  2340  of the circuit board  2302  by coupling components  2316 . The coupling components  2316  may electrically and mechanically couple the package-on-interposer structure  2336  to the circuit board  2302 , and may include solder balls (e.g., as shown in  FIG.  7   ), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. 
     The package-on-interposer structure  2336  may include an IC package  2320  coupled to an interposer  2304  by coupling components  2318 . The coupling components  2318  may take any suitable form for the application, such as the forms discussed above with reference to the coupling components  2316 . The IC package  2320  may be or include, for example, a die (the die  2002  of  FIG.  5 B ), an IC device (e.g., the IC structure of  FIGS.  1 - 2   ), or any other suitable component. In particular, the IC package  2320  may include one or more optimized TFTs integrated with one or more III-N devices as described herein. Although a single IC package  2320  is shown in  FIG.  7   , multiple IC packages may be coupled to the interposer  2304 ; indeed, additional interposers may be coupled to the interposer  2304 . The interposer  2304  may provide an intervening substrate used to bridge the circuit board  2302  and the IC package  2320 . Generally, the interposer  2304  may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer  2304  may couple the IC package  2320  (e.g., a die) to a BGA of the coupling components  2316  for coupling to the circuit board  2302 . In the embodiment illustrated in  FIG.  7   , the IC package  2320  and the circuit board  2302  are attached to opposing sides of the interposer  2304 ; in other embodiments, the IC package  2320  and the circuit board  2302  may be attached to a same side of the interposer  2304 . In some embodiments, three or more components may be interconnected by way of the interposer  2304 . 
     The interposer  2304  may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some implementations, the interposer  2304  may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer  2304  may include metal interconnects  2308  and vias  2310 , including but not limited to through-silicon vias (TSVs)  2306 . The interposer  2304  may further include embedded devices  2314 , including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) protection devices, and memory devices. More complex devices such as further RF devices, power amplifiers (PAs), power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer  2304 . In some embodiments, the IC structures implementing one or more optimized TFTs integrated with one or more III-N devices as described herein may also be implemented in/on the interposer  2304 . The package-on-interposer structure  2336  may take the form of any of the package-on-interposer structures known in the art. 
     The IC device assembly  2300  may include an IC package  2324  coupled to the first face  2340  of the circuit board  2302  by coupling components  2322 . The coupling components  2322  may take the form of any of the embodiments discussed above with reference to the coupling components  2316 , and the IC package  2324  may take the form of any of the embodiments discussed above with reference to the IC package  2320 . 
     The IC device assembly  2300  illustrated in  FIG.  7    includes a package-on-package structure  2334  coupled to the second face  2342  of the circuit board  2302  by coupling components  2328 . The package-on-package structure  2334  may include an IC package  2326  and an IC package  2332  coupled together by coupling components  2330  such that the IC package  2326  is disposed between the circuit board  2302  and the IC package  2332 . The coupling components  2328  and  2330  may take the form of any of the embodiments of the coupling components  2316  discussed above, and the IC packages  2326  and  2332  may take the form of any of the embodiments of the IC package  2320  discussed above. The package-on-package structure  2334  may be configured in accordance with any of the package-on-package structures known in the art. 
       FIG.  8    is a block diagram of an example computing device  2400  that may include one or more components with one or more IC structures having one or more optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the computing device  2400  may include a die (e.g., the die  2002  ( FIG.  5 B )) including at least one optimized TFT in accordance with any of the embodiments disclosed herein. Any of the components of the computing device  2400  may include an IC device (e.g., any embodiment of the IC structure of  FIGS.  1 - 2   ) and/or an IC package  2200  ( FIG.  6   ). Any of the components of the computing device  2400  may include an IC device assembly  2300  ( FIG.  7   ). 
     A number of components are illustrated in  FIG.  8    as included in the computing device  2400 , but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the computing device  2400  may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated onto a single SoC die. 
     Additionally, in various embodiments, the computing device  2400  may not include one or more of the components illustrated in  FIG.  8   , but the computing device  2400  may include interface circuitry for coupling to the one or more components. For example, the computing device  2400  may not include a display device  2406 , but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device  2406  may be coupled. In another set of examples, the computing device  2400  may not include an audio input device  2418  or an audio output device  2408 , but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device  2418  or audio output device  2408  may be coupled. 
     The computing device  2400  may include a processing device  2402  (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device  2402  may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The computing device  2400  may include a memory  2404 , which may itself include one or more memory devices such as volatile memory (e.g., DRAM), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and/or a hard drive. In some embodiments, the memory  2404  may include memory that shares a die with the processing device  2402 . This memory may be used as cache memory and may include, e.g., eDRAM, and/or spin transfer torque magnetic random-access memory (STT-M RAM). 
     In some embodiments, the computing device  2400  may include a communication chip  2412  (e.g., one or more communication chips). For example, the communication chip  2412  may be configured for managing wireless communications for the transfer of data to and from the computing device  2400 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. 
     The communication chip  2412  may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip  2412  may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip  2412  may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip  2412  may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip  2412  may operate in accordance with other wireless protocols in other embodiments. The computing device  2400  may include an antenna  2422  to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). 
     In some embodiments, the communication chip  2412  may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip  2412  may include multiple communication chips. For instance, a first communication chip  2412  may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip  2412  may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip  2412  may be dedicated to wireless communications, and a second communication chip  2412  may be dedicated to wired communications. 
     In various embodiments, IC structures as described herein may be particularly advantageous for use within the one or more communication chips  2412 , described above. For example, such IC structures, in particular one or more optimized TFTs integrated with one or more III-N devices as described herein, may be used to implement one or more of RF switches, PAs, low-noise amplifiers (LNAs), filters (including arrays of filters and filter banks), upconverters, downconverters, and duplexers, e.g., as a part of implementing the communication chips  2412 . 
     The computing device  2400  may include battery/power circuitry  2414 . The battery/power circuitry  2414  may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the computing device  2400  to an energy source separate from the computing device  2400  (e.g., AC line power). 
     The computing device  2400  may include a display device  2406  (or corresponding interface circuitry, as discussed above). The display device  2406  may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example. 
     The computing device  2400  may include an audio output device  2408  (or corresponding interface circuitry, as discussed above). The audio output device  2408  may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example. 
     The computing device  2400  may include an audio input device  2418  (or corresponding interface circuitry, as discussed above). The audio input device  2418  may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). 
     The computing device  2400  may include a GPS device  2416  (or corresponding interface circuitry, as discussed above). The GPS device  2416  may be in communication with a satellite-based system and may receive a location of the computing device  2400 , as known in the art. 
     The computing device  2400  may include an other output device  2410  (or corresponding interface circuitry, as discussed above). Examples of the other output device  2410  may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. 
     The computing device  2400  may include an other input device  2420  (or corresponding interface circuitry, as discussed above). Examples of the other input device  2420  may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. 
     The computing device  2400  may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device  2400  may be any other electronic device that processes data. 
       FIG.  9    is a block diagram of an example RF device  2500  that may include one or more components with one or more IC structures having one or more optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. For example, any suitable ones of the components of the RF device  2500  may include a die (e.g., the die  2002  as described with reference to  FIG.  5    or a die implementing the IC structure as described with reference to  FIG.  1  or  2   ) including one or more optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. Any of the components of the RF device  2500  may include an IC device (e.g., the IC structure of  FIGS.  1 - 2   ) and/or an IC package  2200  as described with reference to  FIG.  6   . Any of the components of the RF device  2500  may include an IC device assembly  2300  as described with reference to  FIG.  7   . In some embodiments, the RF device  2500  may be included within any components of the computing device  2400  as described with reference to  FIG.  8   , or may be coupled to any of the components of the computing device  2400 , e.g., be coupled to the memory  2404  and/or to the processing device  2402  of the computing device  2400 . In still other embodiments, the RF device  2500  may further include any of the components described with reference to  FIG.  8   , such as, but not limited to, the battery/power circuit  2414 , the memory  2404 , and various input and output devices as shown in  FIG.  8   . 
     In general, the RF device  2500  may be any device or system that may support wireless transmission and/or reception of signals in the form of electromagnetic waves in the RF range of approximately 3 kiloHertz (kHz) to 300 gigaHertz (GHz). In some embodiments, the RF device  2500  may be used for wireless communications, e.g., in a BS or a UE device of any suitable cellular wireless communications technology, such as GSM, WCDMA, or LTE. In a further example, the RF device  2500  may be used as, or in, e.g., a BS or a UE device of a mm-wave wireless technology such as fifth generation (5G) wireless (i.e., high frequency/short wavelength spectrum, e.g., with frequencies in the range between about 20 and 60 GHz, corresponding to wavelengths in the range between about 5 and 15 millimeters). In yet another example, the RF device  2500  may be used for wireless communications using Wi-Fi technology (e.g., a frequency band of 2.4 GHz, corresponding to a wavelength of about 12 cm, or a frequency band of 5.8 GHz, spectrum, corresponding to a wavelength of about 5 cm), e.g., in a Wi-Fi-enabled device such as a desktop, a laptop, a video game console, a smart phone, a tablet, a smart TV, a digital audio player, a car, a printer, etc. In some implementations, a Wi-Fi-enabled device may, e.g., be a node in a smart system configured to communicate data with other nodes, e.g., a smart sensor. Still in another example, the RF device  2500  may be used for wireless communications using Bluetooth technology (e.g., a frequency band from about 2.4 to about 2.485 GHz, corresponding to a wavelength of about 12 cm). In other embodiments, the RF device  2500  may be used for transmitting and/or receiving RF signals for purposes other than communication, e.g., in an automotive radar system, or in medical applications such as magneto-resonance imaging (MRI). 
     In various embodiments, the RF device  2500  may be included in frequency-division duplex (FDD) or time-domain duplex (TDD) variants of frequency allocations that may be used in a cellular network. In an FDD system, the uplink (i.e., RF signals transmitted from the UE devices to a BS) and the downlink (i.e., RF signals transmitted from the BS to the US devices) may use separate frequency bands at the same time. In a TDD system, the uplink and the downlink may use the same frequencies but at different times. 
     A number of components are illustrated in  FIG.  9    as included in the RF device  2500 , but any one or more of these components may be omitted or duplicated, as suitable for the application. For example, in some embodiments, the RF device  2500  may be an RF device supporting both of wireless transmission and reception of RF signals (e.g., an RF transceiver), in which case it may include both the components of what is referred to herein as a transmit (TX) path and the components of what is referred to herein as a receive (RX) path. However, in other embodiments, the RF device  2500  may be an RF device supporting only wireless reception (e.g., an RF receiver), in which case it may include the components of the RX path, but not the components of the TX path; or the RF device  2500  may be an RF device supporting only wireless transmission (e.g., an RF transmitter), in which case it may include the components of the TX path, but not the components of the RX path. 
     In some embodiments, some or all of the components included in the RF device  2500  may be attached to one or more motherboards. In some embodiments, some or all of these components are fabricated on a single die, e.g., on a single SoC die. 
     Additionally, in various embodiments, the RF device  2500  may not include one or more of the components illustrated in  FIG.  9   , but the RF device  2500  may include interface circuitry for coupling to the one or more components. For example, the RF device  2500  may not include an antenna  2502 , but may include antenna interface circuitry (e.g., a matching circuitry, a connector and driver circuitry) to which an antenna  2502  may be coupled. In another set of examples, the RF device  2500  may not include a digital processing unit  2508  or a local oscillator  2506 , but may include device interface circuitry (e.g., connectors and supporting circuitry) to which a digital processing unit  2508  or a local oscillator  2506  may be coupled. 
     As shown in  FIG.  9   , the RF device  2500  may include an antenna  2502 , a duplexer  2504 , a local oscillator  2506 , a digital processing unit  2508 . As also shown in  FIG.  9   , the RF device  2500  may include an RX path that may include an RX path amplifier  2512 , an RX path pre-mix filter  2514 , a RX path mixer  2516 , an RX path post-mix filter  2518 , and an analog-to-digital converter (ADC)  2520 . As further shown in  FIG.  9   , the RF device  2500  may include a TX path that may include a TX path amplifier  2522 , a TX path post-mix filter  2524 , a TX path mixer  2526 , a TX path pre-mix filter  2528 , and a digital-to-analog converter (DAC)  2530 . Still further, the RF device  2500  may further include an impedance tuner  2532 , an RF switch  2534 , and control logic  2536 . In various embodiments, the RF device  2500  may include multiple instances of any of the components shown in  FIG.  9   . In some embodiments, the RX path amplifier  2512 , the TX path amplifier  2522 , the duplexer  2504 , and the RF switch  2534  may be considered to form, or be a part of, an RF FE of the RF device  2500 . In some embodiments, the RX path amplifier  2512 , the TX path amplifier  2522 , the duplexer  2504 , and the RF switch  2534  may be considered to form, or be a part of, an RF FE of the RF device  2500 . In some embodiments, the RX path mixer  2516  and the TX path mixer  2526  (possibly with their associated pre-mix and post-mix filters shown in  FIG.  9   ) may be considered to form, or be a part of, an RF transceiver of the RF device  2500  (or of an RF receiver or an RF transmitter if only RX path or TX path components, respectively, are included in the RF device  2500 ). In some embodiments, the RF device  2500  may further include one or more control logic elements/circuits, shown in  FIG.  9    as control logic  2536 , e.g., an RF FE control interface. The control logic  2536  may be used to, e.g., enhance control of complex RF system environment, support implementation of envelope tracking techniques, reduce dissipated power, etc. Various IC structures as described herein may be particularly advantageous for realizing at least portions of such control logic elements/circuits. 
     The antenna  2502  may be configured to wirelessly transmit and/or receive RF signals in accordance with any wireless standards or protocols, e.g., Wi-Fi, LTE, or GSM, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. If the RF device  2500  is an FDD transceiver, the antenna  2502  may be configured for concurrent reception and transmission of communication signals in separate, i.e., non-overlapping and non-continuous, bands of frequencies, e.g., in bands having a separation of, e.g., 20 MHz from one another. If the RF device  2500  is a TDD transceiver, the antenna  2502  may be configured for sequential reception and transmission of communication signals in bands of frequencies that may be the same, or overlapping for TX and RX paths. In some embodiments, the RF device  2500  may be a multi-band RF device, in which case the antenna  2502  may be configured for concurrent reception of signals having multiple RF components in separate frequency bands and/or configured for concurrent transmission of signals having multiple RF components in separate frequency bands. In such embodiments, the antenna  2502  may be a single wide-band antenna or a plurality of band-specific antennas (i.e., a plurality of antennas each configured to receive and/or transmit signals in a specific band of frequencies). In various embodiments, the antenna  2502  may include a plurality of antenna elements, e.g., a plurality of antenna elements forming a phased antenna array (i.e., a communication system or an array of antennas that may use a plurality of antenna elements and phase shifting to transmit and receive RF signals). Compared to a single-antenna system, a phased antenna array may offer advantages such as increased gain, ability of directional steering, and simultaneous communication. In some embodiments, the RF device  2500  may include more than one antenna  2502  to implement antenna diversity. In some such embodiments, the RF switch  2534  may be deployed to switch between different antennas. Any of the embodiments of the IC structures with one or more optimized TFTs integrated with one or more III-N devices may be used to implement at least a portion of the RF switch  2534 . 
     An output of the antenna  2502  may be coupled to the input of the duplexer  2504 . The duplexer  2504  may be any suitable component configured for filtering multiple signals to allow for bidirectional communication over a single path between the duplexer  2504  and the antenna  2502 . The duplexer  2504  may be configured for providing RX signals to the RX path of the RF device  2500  and for receiving TX signals from the TX path of the RF device  2500 . 
     The RF device  2500  may include one or more local oscillators  2506 , configured to provide local oscillator signals that may be used for downconversion of the RF signals received by the antenna  2502  and/or upconversion of the signals to be transmitted by the antenna  2502 . 
     The RF device  2500  may include the digital processing unit  2508 , which may include one or more processing devices. In some embodiments, the digital processing unit  2508  may be implemented as the processing device  2402  shown in  FIG.  8   , descriptions of which are provided above (when used as the digital processing unit  2508 , the processing device  2402  may, but does not have to, implement any of the IC structures as described herein, e.g., IC structures having one or more optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein). The digital processing unit  2508  may be configured to perform various functions related to digital processing of the RX and/or TX signals. Examples of such functions include, but are not limited to, decimation/downsampling, error correction, digital downconversion or upconversion, DC offset cancellation, automatic gain control, etc. Although not shown in  FIG.  9   , in some embodiments, the RF device  2500  may further include a memory device, e.g., the memory device  2404  as described with reference to  FIG.  8   , configured to cooperate with the digital processing unit  2508 . When used within, or coupled to, the RF device  2500 , the memory device  2404  may, but does not have to, implement any of the IC structures as described herein, e.g., IC structures having one or more optimized TFTs integrated with one or more III-N devices in accordance with any of the embodiments disclosed herein. 
     Turning to the details of the RX path that may be included in the RF device  2500 , the RX path amplifier  2512  may include an LNA. An input of the RX path amplifier  2512  may be coupled to an antenna port (not shown) of the antenna  2502 , e.g., via the duplexer  2504 . The RX path amplifier  2512  may amplify the RF signals received by the antenna  2502 . 
     An output of the RX path amplifier  2512  may be coupled to an input of the RX path pre-mix filter  2514 , which may be a harmonic or band-pass (e.g., low-pass) filter, configured to filter received RF signals that have been amplified by the RX path amplifier  2512 . 
     An output of the RX path pre-mix filter  2514  may be coupled to an input of the RX path mixer  2516 , also referred to as a downconverter. The RX path mixer  2516  may include two inputs and one output. A first input may be configured to receive the RX signals, which may be current signals, indicative of the signals received by the antenna  2502  (e.g., the first input may receive the output of the RX path pre-mix filter  2514 ). A second input may be configured to receive local oscillator signals from one of the local oscillators  2506 . The RX path mixer  2516  may then mix the signals received at its two inputs to generate a downconverted RX signal, provided at an output of the RX path mixer  2516 . As used herein, downconversion refers to a process of mixing a received RF signal with a local oscillator signal to generate a signal of a lower frequency. In particular, the TX path mixer (e.g., downconverter)  2516  may be configured to generate the sum and/or the difference frequency at the output port when two input frequencies are provided at the two input ports. In some embodiments, the RF device  2500  may implement a direct-conversion receiver (DCR), also known as homodyne, synchrodyne, or zero-IF receiver, in which case the RX path mixer  2516  may be configured to demodulate the incoming radio signals using local oscillator signals whose frequency is identical to, or very close to the carrier frequency of the radio signal. In other embodiments, the RF device  2500  may make use of downconversion to an intermediate frequency (IF). IFs may be used in superheterodyne radio receivers, in which a received RF signal is shifted to an IF, before the final detection of the information in the received signal is done. Conversion to an IF may be useful for several reasons. For example, when several stages of filters are used, they can all be set to a fixed frequency, which makes them easier to build and to tune. In some embodiments, the RX path mixer  2516  may include several such stages of IF conversion. 
     Although a single RX path mixer  2516  is shown in the RX path of  FIG.  9   , in some embodiments, the RX path mixer  2516  may be implemented as a quadrature downconverter, in which case it would include a first RX path mixer and a second RX path mixer. The first RX path mixer may be configured for performing downconversion to generate an in-phase (I) downconverted RX signal by mixing the RX signal received by the antenna  2502  and an in-phase component of the local oscillator signal provided by the local oscillator  2506 . The second RX path mixer may be configured for performing downconversion to generate a quadrature (Q) downconverted RX signal by mixing the RX signal received by the antenna  2502  and a quadrature component of the local oscillator signal provided by the local oscillator  2506  (the quadrature component is a component that is offset, in phase, from the in-phase component of the local oscillator signal by 90 degrees). The output of the first RX path mixer may be provided to a I-signal path, and the output of the second RX path mixer may be provided to a Q-signal path, which may be substantially 90 degrees out of phase with the I-signal path. 
     The output of the RX path mixer  2516  may, optionally, be coupled to the RX path post-mix filter  2518 , which may be low-pass filters. In case the RX path mixer  2516  is a quadrature mixer that implements the first and second mixers as described above, the in-phase and quadrature components provided at the outputs of the first and second mixers respectively may be coupled to respective individual first and second RX path post-mix filters included in the filter  2518 . 
     The ADC  2520  may be configured to convert the mixed RX signals from the RX path mixer  2516  from analog to digital domain. The ADC  2520  may be a quadrature ADC that, similar to the RX path quadrature mixer  2516 , may include two ADCs, configured to digitize the downconverted RX path signals separated in in-phase and quadrature components. The output of the ADC  2520  may be provided to the digital processing unit  2508 , configured to perform various functions related to digital processing of the RX signals so that information encoded in the RX signals can be extracted. 
     Turning to the details of the TX path that may be included in the RF device  2500 , the digital signal to later be transmitted (TX signal) by the antenna  2502  may be provided, from the digital processing unit  2508 , to the DAC  2530 . Similar to the ADC  2520 , the DAC  2530  may include two DACs, configured to convert, respectively, digital I- and Q-path TX signal components to analog form. 
     Optionally, the output of the DAC  2530  may be coupled to the TX path pre-mix filter  2528 , which may be a band-pass (e.g., low-pass) filter (or a pair of band-pass, e.g., low-pass, filters, in case of quadrature processing) configured to filter out, from the analog TX signals output by the DAC  2530 , the signal components outside of the desired band. The digital TX signals may then be provided to the TX path mixer  2526 , which may also be referred to as an upconverter. Similar to the RX path mixer  2516 , the TX path mixer  2526  may include a pair of TX path mixers, for in-phase and quadrature component mixing. Similar to the first and second RX path mixers that may be included in the RX path, each of the TX path mixers of the TX path mixer  2526  may include two inputs and one output. A first input may receive the TX signal components, converted to the analog form by the respective DAC  2530 , which are to be upconverted to generate RF signals to be transmitted. The first TX path mixer may generate an in-phase (I) upconverted signal by mixing the TX signal component converted to analog form by the DAC  2530  with the in-phase component of the TX path local oscillator signal provided from the local oscillator  2506  (in various embodiments, the local oscillator  2506  may include a plurality of different local oscillators, or be configured to provide different local oscillator frequencies for the mixer  2516  in the RX path and the mixer  2526  in the TX path). The second TX path mixer may generate a quadrature phase (Q) upconverted signal by mixing the TX signal component converted to analog form by the DAC  2530  with the quadrature component of the TX path local oscillator signal. The output of the second TX path mixer may be added to the output of the first TX path mixer to create a real RF signal. A second input of each of the TX path mixers may be coupled the local oscillator  2506 . 
     Optionally, the RF device  2500  may include the TX path post-mix filter  2524 , configured to filter the output of the TX path mixer  2526 . 
     The TX path amplifier  2522  may be a PA, configured to amplify the upconverted RF signal before providing it to the antenna  2502  for transmission. Any of the embodiments of the IC structures with one or more optimized TFTs integrated with one or more III-N devices may be used to implement the TX path amplifier  2522  as a PA. 
     In various embodiments, any of the RX path pre-mix filter  2514 , the RX path post-mix filter  2518 , the TX post-mix filter  2524 , and the TX pre-mix filter  2528  may be implemented as RF filters. In some embodiments, each of such RF filters may include one or more, typically a plurality of, resonators (e.g., film bulk acoustic resonators (FBARs), Lamb wave resonators, and/or contour-wave resonators), arranged, e.g., in a ladder configuration. An individual resonator of an RF filter may include a layer of a piezoelectric material such as AlN, enclosed between a bottom electrode and a top electrode, with a cavity provided around a portion of each electrode in order to allow a portion of the piezoelectric material to vibrate during operation of the filter. In some embodiments, an RF filter may be implemented as a plurality of RF filters, or a filter bank. A filter bank may include a plurality of RF resonators that may be coupled to a switch, e.g., the RF switch  2534 , configured to selectively switch any one of the plurality of RF resonators on and off (i.e., activate any one of the plurality of RF resonators), in order to achieve desired filtering characteristics of the filter bank (i.e., in order to program the filter bank). For example, such a filter bank may be used to switch between different RF frequency ranges when the RF device  2500  is, or is included in, a BS or in a UE device. In another example, such a filter bank may be programmable to suppress TX leakage on the different duplex distances. 
     The impedance tuner  2532  may include any suitable circuitry, configured to match the input and output impedances of the different RF circuitries to minimize signal losses in the RF device  2500 . For example, the impedance tuner  2532  may include an antenna impedance tuner. Being able to tune the impedance of the antenna  2502  may be particularly advantageous because antenna&#39;s impedance is a function of the environment that the RF device  2500  is in, e.g., antenna&#39;s impedance changes depending on, e.g., if the antenna is held in a hand, placed on a car roof, etc. 
     As described above, the RF switch  2534  may be used to selectively switch between a plurality of instances of any one of the components shown in  FIG.  9   , in order to achieve desired behavior and characteristics of the RF device  2500 . For example, in some embodiments, an RF switch may be used to switch between different antennas  2502 . In other embodiments, an RF switch may be used to switch between a plurality of RF resonators (e.g., by selectively switching RF resonators on and off) of any of the filters included in the RF device  2500 . 
     In various embodiments, one or more optimized TFTs integrated with one or more III-N devices as described herein may be particularly advantageous when used in, or to provide an RF interconnect to (i.e., to provide means for supporting communication of RF signals to), any of the duplexer  2504 , RX path amplifier  2512 , RX path pre-mix filter  2514 , RX path post-mix filter  2518 , TX path amplifier  2522 , TX path pre-mix filter  2528 , TX path post-mix filter  2524 , impedance tuner  2532 , and/or RF switch  2534 . The optimized TFTs may enable more energy efficient CMOS implementations of circuits, e.g., to name a few, control logic circuitries, current mirrors, power gating circuitries, memory elements etc. 
     The RF device  2500  provides a simplified version and, in further embodiments, other components not specifically shown in  FIG.  9    may be included. For example, the RX path of the RF device  2500  may include a current-to-voltage amplifier between the RX path mixer  2516  and the ADC  2520 , which may be configured to amplify and convert the downconverted signals to voltage signals. In another example, the RX path of the RF device  2500  may include a balun transformer for generating balanced signals. In yet another example, the RF device  2500  may further include a clock generator, which may, e.g., include a suitable phased-lock loop (PLL), configured to receive a reference clock signal and use it to generate a different clock signal that may then be used for timing the operation of the ADC  2520 , the DAC  2530 , and/or that may also be used by the local oscillator  2506  to generate the local oscillator signals to be used in the RX path or the TX path. 
     SELECT EXAMPLES 
     The following paragraphs provide various examples of the embodiments disclosed herein. 
     Example 1 provides an IC structure that includes a support structure (e.g., a substrate, a die, or a chip), and a transistor (e.g., a TFT) provided over the support structure. The transistor includes a channel material, a pair of S/D regions, and a gate stack. The channel material includes a semiconductor material and dopant atoms of a first type, where the dopant atoms of the first type are either P-type dopant atoms or N-type dopant atoms. Furthermore, at least one of the pair of S/D regions includes a first portion and a second portion, where the first portion of the at least one of the pair of S/D regions includes dopant atoms of a second type, where the dopant atoms of the second type are either P-type dopant atoms or N-type dopant atoms and the second type is different from the first type, and where the dopant atoms of the second type in the first portion of the at least one of the pair of S/D regions are at a first dopant concentration, the second portion of the at least one of the pair of S/D regions includes the dopant atoms of the second type, where the dopant atoms of the second type in the second portion are at a second dopant concentration, the second portion of the at least one of the pair of S/D regions is closer to the gate stack than the first portion of the at least one of the pair of S/D regions, and the second dopant concentration is lower than the first dopant concentration. 
     Example 2 provides the IC structure according to example 1, where the first dopant concentration is at least about 5×10 19  cm −3 , including all values and ranges therein, e.g., at least about 1×10 20  Cm −3  or at least about 1×10 21  cm −3 . 
     Example 3 provides the IC structure according to examples 1 or 2, where the second dopant concentration is below about 1×10 18  cm −3 , including all values and ranges therein, e.g., below about 5×10 17  cm −3  or below about 1×10 17  cm −3 . 
     Example 4 provides the IC structure according to any one of the preceding examples, where the second portion of the at least one of the pair of S/D regions overlaps with a portion of the gate stack. 
     Example 5 provides the IC structure according to any one of the preceding examples, where the second portion overlaps with a portion of the gate stack by less than about 10 percent of a gate length of the transistor, including all values and ranges therein, e.g., by anywhere between 0.1 and 8 percent or by anywhere between 0.1 and 3 percent. 
     Example 6 provides the IC structure according to any one of the preceding examples, where, in the at least one of the pair of S/D regions, a dopant concentration of the dopant atoms of the second type decreases from a portion of the at least one of the pair of S/D regions that is farthest away from the gate stack to a portion of the at least one of the pair of S/D regions that is closest to (and possibly overlaps with a portion of) the gate stack. 
     Example 7 provides the IC structure according to any one of the preceding examples, where the channel material includes a first portion and a second portion, the second portion of the channel material is between the first portion of the channel material and the gate stack, and a dopant concentration of the dopant atoms of the first type in the second portion of the channel material is lower than a dopant concentration of the dopant atoms of the first type in the first portion of the channel material. 
     Example 8 provides the IC structure according to any one of the preceding examples, where the gate stack includes a gate dielectric including a first portion and a second portion, the second portion of the gate dielectric is between the first portion of the gate dielectric and the channel material, the first portion of the gate dielectric has a first dielectric constant, the second portion of the gate dielectric has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. 
     Example 9 provides an IC structure that includes a support structure (e.g., a substrate, a die, or a chip), and a transistor (e.g., a TFT) provided over the support structure. The transistor includes a channel material, a pair of S/D regions, and a gate stack. The channel material includes a first portion and a second portion, where the first portion of the channel material includes dopant atoms of a first type, where the dopant atoms of the first type are either P-type dopant atoms or N-type dopant atoms, and where the dopant atoms of the first type in the first portion of the channel material are at a first dopant concentration. Furthermore, the second portion of the channel material includes the dopant atoms of the first type at a second dopant concentration, where the second portion of the channel material is between the first portion of the channel material and the gate stack, and the second dopant concentration is lower than the first dopant concentration. Each S/D region of the pair of S/D regions includes dopant atoms of a second type, where the dopant atoms of the second type are either P-type dopant atoms or N-type dopant atoms and the second type is different from the first type. 
     Example 10 provides the IC structure according to example 9, where the second dopant concentration is below about 1×10 17  cm −3 , including all values and ranges therein, e.g., below about 1×10 16  cm −3  or below about 1×10 15  cm −3 . 
     Example 11 provides the IC structure according to examples 9 or 10, where the first dopant concentration is at least about 5×10 17  cm −3 , including all values and ranges therein, e.g., at least about 1×10 19  cm −3  or at least about 1×10 20  cm −3 . 
     Example 12 provides the IC structure according to any one of examples 9-11, where a thickness of the second portion of the channel material is between about 1 and 15 nanometers, including all values and ranges therein, e.g., between about 1 and 10 nanometers, or between about 1 and 5-7 nanometers. 
     Example 13 provides the IC structure according to any one of examples 9-12, where the gate stack includes a gate dielectric including a first portion and a second portion, the second portion of the gate dielectric is between the first portion of the gate dielectric and the channel material, the first portion of the gate dielectric has a first dielectric constant, the second portion of the gate dielectric has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. 
     Example 14 provides an IC structure that includes a support structure (e.g., a substrate, a die, or a chip), and a transistor (e.g., a TFT) provided over the support structure. The transistor includes a channel material, a pair of S/D regions, and a gate stack. The channel material is between the pair of S/D regions. The gate stack includes a gate dielectric including a first portion and a second portion, where the second portion of the gate dielectric is between the first portion of the gate dielectric and the channel material, the first portion of the gate dielectric has a first dielectric constant, the second portion of the gate dielectric has a second dielectric constant, and the second dielectric constant is lower than the first dielectric constant. 
     Example 15 provides the IC structure according to example 14, where a thickness of each of the first portion of the gate dielectric and the second portion of the gate dielectric is between about 1 and 5 nanometers, including all values and ranges therein, e.g., between about 1 and 4 nanometers, or between about 1 and 3 nanometers. 
     Example 16 provides the IC structure according to examples 14 or 15, where the first dielectric constant is greater than a dielectric constant of silicon dioxide. 
     Example 17 provides the IC structure according to any one of examples 14-16, where the second dielectric constant is lower than a dielectric constant of silicon dioxide. 
     Example 18 provides the IC structure according to any one of examples 14-17, where the channel material includes a semiconductor material that includes dopant atoms of a first type, where the dopant atoms of the first type are either P-type dopant atoms or N-type dopant atoms. Further, at least one of the pair of S/D regions includes a first portion and a second portion, where the first portion of the at least one of the pair of S/D regions includes dopant atoms of a second type, where the dopant atoms of the second type are either P-type dopant atoms or N-type dopant atoms and the second type is different from the first type. Still further, the dopant atoms of the second type in the first portion of the at least one of the pair of S/D regions are at a first dopant concentration, and the second portion of the at least one of the pair of S/D regions includes the dopant atoms of the second type, where the dopant atoms of the second type in the second portion are at a second dopant concentration, which is lower than the first dopant concentration. The second portion of the at least one of the pair of S/D regions is closer to the gate stack than the first portion of the at least one of the pair of S/D regions. 
     Example 19 provides the IC structure according to any one of the preceding examples, where the channel material includes a group IV semiconductor material. 
     Example 20 provides the IC structure according to any one of the preceding examples, where the channel material (as well as, in some embodiments, the S/D materials) includes one or more of a crystalline material, a polycrystalline semiconductor material, a laminate of crystalline and polycrystalline materials. 
     Example 21 provides the IC structure according to any one of the preceding examples, where the channel material includes crystalline grains larger than about 1 nanometers. 
     Example 22 provides the IC structure according to any one of the preceding examples, further including a III-N semiconductor material and a polarization material, where at least a portion of the polarization material is between the channel material of the TFT and the III-N semiconductor material, and a lattice constant of the polarization material is smaller than a lattice constant of the III-N semiconductor material. In some embodiments, Al and In content in the polarization material may be higher than that in the III-N semiconductor material. 
     Example 23 provides the IC structure according to example 22, further including a III-N transistor, where the III-N transistor is above a first portion of the III-N semiconductor material, and the TFT is above a second portion of the III-N semiconductor material. 
     Example 24 provides the IC structure according to example 23, where the III-N transistor is a part of a RF circuit. 
     Example 25 provides the IC structure according to any one of the preceding examples, where the TFT is a part of a RF switch of an RF communications device, e.g., of an RF transceiver. In other examples, the TFT may be a part of any other components of an RF communications device, such components including, e.g., a duplexer, a power amplifier, a low-noise amplifier, various filters, etc. 
     Example 26 provides the IC structure according to any one of the preceding examples, where the IC structure is included in, or used to implement at least a portion of, an RF FE. 
     Example 27 provides an IC package that includes an IC die, the IC die including the IC structure according to any one of the preceding examples (e.g., any one of examples 1-26), and a further IC component, coupled to the IC die. 
     Example 28 provides the IC package according to example 27, where the further IC component includes one of a package substrate, an interposer, or a further IC die. 
     Example 29 provides the IC package according to any one of examples 27-28, where the IC package is included in a base station of a wireless communication system. 
     Example 30 provides the IC package according to any one of examples 27-28, where the IC package is included in a UE device (e.g., a mobile device) of a wireless communication system. 
     Example 31 provides the IC package according to any one of the preceding examples, where the IC die is a part of an RF device. 
     Example 32 provides an electronic device that includes a carrier substrate and an IC die coupled to the carrier substrate. The IC die includes the IC structure according to any one of examples 1-26, and/or is included in the IC package according to any one of examples 27-31. 
     Example 33 provides the electronic device according to example 32, where the computing device is a wearable or handheld electronic device. 
     Example 34 provides the electronic device according to examples 32 or 33, where the electronic device further includes one or more communication chips and an antenna. 
     Example 35 provides the electronic device according to any one of examples 32-34, where the carrier substrate is a motherboard. 
     Example 36 provides the electronic device according to any one of examples 32-35, where the electronic device is an RF transceiver. 
     Example 37 provides the electronic device according to any one of examples 32-36, where the electronic device is one of an RF switch, a power amplifier, a low-noise amplifier, a filter, a filter bank, a duplexer, an upconverter, or a downconverter of an RF communications device, e.g., of an RF transceiver. 
     Example 38 provides the electronic device according to any one of examples 32-37, where the electronic device is included in a base station of a wireless communication system. 
     Example 39 provides the electronic device according to any one of examples 32-37, where the electronic device is included in a UE device (e.g., a mobile device) of a wireless communication system. 
     The above description of illustrated implementations of the disclosure, including what is described in the Abstract, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. While specific implementations of, and examples for, the disclosure are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as those skilled in the relevant art will recognize. These modifications may be made to the disclosure in light of the above detailed description.