Patent Publication Number: US-11047890-B2

Title: Minimizing phase mismatch and offset sensitivity in a dual-path system

Description:
RELATED APPLICATIONS 
     The present disclosure claims priority to U.S. Provisional Patent Application Ser. No. 62/632,018, filed Feb. 19, 2018 and U.S. Provisional Patent Application Ser. 62/632,293, filed Feb. 19, 2018, each of which is incorporated by reference herein in its entirety. 
    
    
     FIELD OF DISCLOSURE 
     The present disclosure relates in general to circuits for audio and haptic devices, including without limitation personal audio devices, such as wireless telephones and media players, or devices comprising a haptic module. 
     BACKGROUND 
     Personal audio devices, including wireless telephones, such as mobile/cellular telephones, cordless telephones, mp3 players, and other consumer audio devices, are in widespread use. Such personal audio devices may include circuitry for driving a pair of headphones or one or more speakers. Such circuitry often includes a power amplifier for driving an audio output signal to headphones or speakers. Generally speaking, a power amplifier amplifies an audio signal by taking energy from a power supply and controlling an audio output signal to match an input signal shape but with a larger amplitude. 
     One example of an audio amplifier is a class-D amplifier. A class-D amplifier (also known as a “switching amplifier”) may comprise an electronic amplifier in which the amplifying devices (e.g., transistors, typically metal-oxide-semiconductor field effect transistors) operate as electronic switches. In a class-D amplifier, a signal to be amplified may be converted to a series of pulses by pulse-width modulation, pulse-density modulation, or another method of modulation, such that the signal is converted into a modulated signal in which a characteristic of the pulses of the modulated signal (e.g., pulse widths, pulse density, etc.) is a function of the magnitude of the signal. After amplification with a class-D amplifier, the output pulse train may be converted to an unmodulated analog signal by passing through a passive low-pass filter, wherein such low-pass filter may be inherent in the class-D amplifier or a load driven by the class-D amplifier. Class-D amplifiers are often used due to the fact that they may be more power efficient than linear analog amplifiers, in that class-D amplifiers may dissipate less power as heat in active devices as compared to linear analog amplifiers. 
     Typically, a closed-loop PWM amplifier is chosen in order to provide accurate load voltage with desirable Total Harmonic Distortion (THD) and Power Supply Rejection Ratio (PSRR). A closed-loop PWM amplifier typically takes an analog voltage input and a sensed feedback voltage signal which are fed through a closed-loop analog PWM modulator to drive voltage on the speaker load. 
     However, an option to alternatively drive loads using a single PWM amplifier circuit in either open-loop or closed-loop depending on the specific application may be desirable. When using such a single PWM amplifier circuit, it may be critical to calibrate for mismatches in gain between the two paths. However, phase mismatches between the two paths and direct current (DC) offsets between the two paths may lead to inaccurate gain calibration unless sensitivity of the gain calibration system to phase mismatches and DC offset is reduced or eliminated. 
     SUMMARY 
     In accordance with the teachings of the present disclosure, one or more disadvantages and problems associated with existing approaches to processing signals with an amplifier may be reduced or eliminated. 
     In accordance with embodiments of the present disclosure, a method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include obtaining multiple samples of the first signal proximate to when the first signal crosses zero wherein the first signal can be approximated as linear; obtaining multiple samples of the second signal proximate to when the second signal crosses zero wherein the first signal can be approximated as linear; based on the multiple samples of the first signal, approximating a first time at which the first signal crosses zero; based on the multiple samples of the second signal, approximating a second time at which the second signal crosses zero; and determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time. 
     In accordance with these and other embodiments of the present disclosure, a method of determining a phase misalignment between a first signal generated from a first signal path and a second signal generated from a second signal path may include approximating a first time in which the first signal crosses zero; approximating a second time in which the second signal crosses zero; determining the phase misalignment between the first signal and the second signal based on a difference between the first time and the second time, wherein approximating the second time comprises approximating a rising zero cross time in which the second signal crosses zero while rising in value by interpolating between successive samples occurring before and after the second signal crosses zero while rising in value; approximating a falling zero cross time in which the second signal crosses zero while falling in value by interpolating between successive samples occurring before and after the second signal crosses zero while falling in value; and determining the second time based on the rising zero cross time and the falling zero cross time such that a difference between the first time and the second time is substantially unaffected by a difference in offset between the first signal and the second signal. 
     In accordance with these and other embodiments of the present disclosure, a method for calculating a relative gain between a first signal generated from a first signal path and second signal generated from a second signal path may include applying a time-based weighting function to the first signal within a fixed time window to generate a weighted first signal, applying the time-based weighting function to the second signal within the fixed time window to generate a weighted second signal, and calculating the relative gain based on a first signal energy of the weighted first signal in the fixed time window and a second signal energy of the second weighted signal in the fixed time window. 
     In accordance with these and other embodiments of the present disclosure, a method for calculating a relative gain between a first signal generated from a first signal path and a second signal generated from a second signal path may include using a correlation function of the first signal and the second signal to compute the gain such that the gain is substantially unaffected by a difference in offset between the first signal and the second signal. 
     Technical advantages of the present disclosure may be readily apparent to one skilled in the art from the figures, description and claims included herein. The objects and advantages of the embodiments will be realized and achieved at least by the elements, features, and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are examples and explanatory and are not restrictive of the claims set forth in this disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       A more complete understanding of the present embodiments and advantages thereof may be acquired by referring to the following description taken in conjunction with the accompanying drawings, in which like reference numbers indicate like features, and wherein: 
         FIG. 1  is an illustration of an example personal audio device, in accordance with embodiments of the present disclosure; 
         FIG. 2  is a block diagram of selected components of an example audio integrated circuit of a personal audio device, in accordance with embodiments of the present disclosure; 
         FIG. 3A  is a block diagram of selected components of an example pulse width modulation amplifier, in accordance with embodiments of the present disclosure; 
         FIG. 3B  is a block diagram of selected components of another example pulse width modulation amplifier, in accordance with embodiments of the present disclosure; 
         FIG. 4  illustrates a graph of a reference signal depicting sampling of the reference signal for approximating a zero crossing of the reference signal, in accordance with embodiments of the present disclosure; 
         FIG. 5A  illustrates a graph of a reference signal without a DC offset, in accordance with embodiments of the present disclosure; 
         FIG. 5B  illustrates a graph of a reference signal with a positive DC offset, in accordance with embodiments of the present disclosure; 
         FIG. 5C  illustrates a graph of a reference signal with a negative DC offset, in accordance with embodiments of the present disclosure; and 
         FIG. 6  illustrates a graph of a weighting function, in accordance with embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is an illustration of an example personal audio device  1 , in accordance with embodiments of the present disclosure.  FIG. 1  depicts personal audio device  1  coupled to a headset  3  in the form of a pair of earbud speakers  8 A and  8 B. Headset  3  depicted in  FIG. 1  is merely an example, and it is understood that personal audio device  1  may be used in connection with a variety of audio transducers, including without limitation, headphones, earbuds, in-ear earphones, and external speakers. A plug  4  may provide for connection of headset  3  to an electrical terminal of personal audio device  1 . Personal audio device  1  may provide a display to a user and receive user input using a touch screen  2 , or alternatively, a standard liquid crystal display (LCD) may be combined with various buttons, sliders, and/or dials disposed on the face and/or sides of personal audio device  1 . As also shown in  FIG. 1 , personal audio device  1  may include an audio integrated circuit (IC)  9  for generating an analog audio signal for transmission to headset  3  and/or another audio transducer (e.g., a loudspeaker). 
       FIG. 2  is a block diagram of selected components of an example audio IC  9  of a personal audio device, in accordance with embodiments of the present disclosure. In some embodiments, example audio IC  9  may be used to implement audio IC  9  of  FIG. 1 . As shown in  FIG. 2 , a microcontroller core  18  (e.g., a digital signal processor or “DSP”) may supply a digital audio input signal DIG_IN to a digital-to-analog converter (DAC)  14 , which may convert the digital audio input signal to an analog input signal V IN . DAC  14  may supply analog signal V IN  to an amplifier  16  which may amplify or attenuate analog input signal V IN  to provide an audio output signal V OUT , which may operate a speaker, headphone transducer, a line level signal output, and/or other suitable output. 
       FIG. 3A  is a block diagram of selected components of an example reconfigurable pulse width modulation amplifier  22 A, in accordance with embodiments of the present disclosure. In some embodiments, reconfigurable example pulse width modulation amplifier  22 A may be used to implement amplifier  16  of  FIG. 2 . As shown in  FIG. 3A , example reconfigurable pulse width modulation amplifier  22 A may include a digital PWM modulator subsystem  24  and an analog PWM modulator  26 , along with a direct bypass function implemented with a multiplexer  28 . 
     Reconfigurable PWM modulation amplifier  22 A may be configured to operate in an analog closed-loop mode through the use of analog PWM modulator  26  when the ANALOG MODULATOR BYPASS control signal received by multiplexer  28  is deasserted. In the analog closed-loop mode, input signal V IN  may be modulated by digital PWM modulator subsystem  24 , analog PWM modulator  26  may receive its input from digital PWM modulator subsystem  24 , and analog PWM modulator  26  may be utilized such that the output of analog PWM modulator  26 , as received and driven by driver stage  34 B, is driven as output signal V OUT . Driver stage  34 B may comprise a plurality of output switches configured to generate output signal V OUT  from a modulated signal generated by analog PWM modulator  26 . 
     Reconfigurable PWM modulation amplifier  22 A may also be configured to operate in a digital open-loop mode through the use of digital PWM modulator subsystem  24  when the ANALOG MODULATOR BYPASS control signal received by multiplexer  28  is asserted. In the digital open-loop mode, analog PWM modulator  26  and a driver stage  34 B driven by analog PWM modulator  26  may be bypassed by multiplexer  28 , and digital PWM modulator subsystem  24  may be utilized such that input signal V IN  is modulated by digital PWM modulator subsystem  24  and the output of digital PWM modulator subsystem  24 , as received and driven by an open-loop driver stage  34 A, is driven as output signal V OUT . Driver stage  34 A may comprise a plurality of output switches configured to generate output signal V OUT  from a modulated signal generated by digital PWM modulator subsystem  24 . 
     Changing reconfigurable PWM modulation amplifier  22 A from the analog closed-loop mode and the digital open-loop mode (and vice versa) may be achieved by, through use of multiplexer  28 , selecting which of driver stage  34 A and driver stage  34 B is to drive output signal V OUT . 
     In some embodiments, a control circuit (not shown) may be used to control multiplexer  28  in order to select a signal processing path for reconfigurable PWM modulation amplifier  22 A. For example, selection of such multiplexer control signal may be based on one or more characteristics of input signal V IN  to the amplifier (e.g., magnitude, frequency, or other characteristic of input signal V IN ). Thus, reconfigurable PWM modulation amplifier  22 A may comprise a digital pulse width modulator subsystem (e.g., digital PWM modulator subsystem  24 ), a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage (e.g., driver stage  34 A), and a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator (e.g., analog PWM modulator  26 ), wherein one of the first path and the second path is selected for processing a signal based on one or more characteristics of the signal. 
     Also as shown in  FIG. 3A , reconfigurable PWM modulation amplifier  22 A may also include a gain calibration engine  36 A configured to detect a first output signal generated by driver stage  34 A, detect a second output signal generated by driver stage  34 B, and based on the two signals, calculate a gain compensation to be applied to a gain element  38 A to compensate for the differences in signal gain between the signal path comprising driver stage  34 A and the signal path comprising driver stage  34 B. Thus, in reconfigurable PWM modulation amplifier  22 A, gain calibration engine  36 A may perform gain compensation on two forward signal paths (e.g., the signal path comprising driver stage  34 A and the signal path comprising driver stage  34 B) to compensate in differences between the two signal paths. 
     As noted in the Background section of this disclosure, accurate calculation of differences between the first output signal generated by driver stage  34 A and the second output signal generated by driver stage  34 B may be affected by a phase mismatch and/or a DC offset between the first signal and the second signal. Accordingly, as described in greater detail below, gain calibration engine  36 A may also be configured to reduce or eliminate sensitivity to phase mismatch and/or DC offset in order to calculate an accurate gain compensation. 
       FIG. 3B  is a block diagram of selected components of an example reconfigurable pulse width modulation amplifier  22 B, in accordance with embodiments of the present disclosure. In some embodiments, example pulse width modulation amplifier  22 B may be used to implement amplifier  16  of  FIG. 2 . Reconfigurable pulse width modulation amplifier  22 B of  FIG. 3B  may be similar in many material respects to reconfigurable pulse width modulation amplifier  22 A of  FIG. 3A , with differences as noted below. The main difference between reconfigurable pulse width modulation amplifier  22 A and reconfigurable pulse width modulation amplifier  22 B is that in lieu of gain calibration engine  36 A and gain element  38 A present in reconfigurable pulse width modulation amplifier  22 A, reconfigurable pulse width modulation amplifier  22 B comprises a gain calibration engine  36 B and a gain element  38 B. 
     Gain calibration engine  36 B may be configured to detect output signal V OUT , detect input signal V IN , and based on the two signals, calculate a gain compensation to be applied to input signal V IN  via gain element  38 B to compensate reconfigurable pulse width modulation amplifier  22 B in a manner such that a desired amplifier gain is maintained for reconfigurable pulse width modulation amplifier  22 B (e.g., maintains desired gain in the presence of process differences, temperature effects, aging effects, and/or other causes for variation in amplifier gain). Thus, in reconfigurable PWM modulation amplifier  22 B, gain calibration engine  36 B may perform gain compensation on a forward signal path (e.g., the signal path generating output voltage V OUT ) and a reverse calibration path or feedback path to perform compensation based on differences between the two signal paths. 
     As noted in the Background section of this disclosure, accurate calculation of differences between output signal V OUT  and input signal V IN  may be affected by a phase mismatch and/or a DC offset between output signal V OUT  and input signal V IN . Accordingly, as described in greater detail below, gain calibration engine  36 B may also be configured to reduce or eliminate sensitivity to phase mismatch and/or DC offset in order to calculate an accurate gain compensation. 
     Although  FIGS. 3A and 3B  suggest gain calibration engine  36 A and gain calibration engine  36 B as alternatives to each other, in certain embodiments of the present disclosure, a reconfigurable pulse width modulation amplifier may include both of gain calibration engine  36 A and gain calibration engine  36 B, or a single gain calibration engine that performs the functions of both of gain calibration engine  36 A and gain calibration engine  36 B. For purposes of clarity and exposition, gain calibration engine  36 A and gain calibration engine  36 B may be referred to hereinafter individually as a gain calibration engine  36  or collectively as gain calibration engine  36 . 
     In order to detect a phase mismatch between two signals to be calibrated to one another, a gain calibration engine  36  may determine a respective time in which each signal crosses zero, with the difference in times of the zero crossing representing a phase delay between the two signals expressed in the time domain. Thus, to accurately calculate a gain compensation, gain calibration engine  36  may apply a time shift to one of the signals to compensate for the phase difference, then calculate a gain compensation based on the phase-aligned, phase-corrected signals. However, because the two signals at issue may be digital signals represented by discrete digital samples, the time of a zero crossing of a signal may not be exactly determined, unless one of the digital samples was obtained at the exact zero crossing. To overcome this issue, a gain calibration engine  36  may approximate a time at which a zero crossing occurs by interpolating between one or more samples occurring before the zero crossing and one or more samples occurring after the zero crossing. 
     An example of such interpolation is described by reference to  FIG. 4 . In operation, to determine a time t 0  of a zero crossing of a continuous-time reference signal y(t) represented by digital samples of reference signal y(t), gain calibration engine  36  may obtain multiple samples  40   a  and  40   b  (which may be referred to individually as a sample  40  or collectively as samples  40 ) proximate to time t 0  such that reference signal y(t) may be approximated as linear in such region proximate to time t 0  (e.g., based on the principle that for a sinusoidal signal, for small values of x, sin x≈x), and calculate the zero crossing time of reference signal y(t) based on these samples, as described in greater detail below. A gain calibration engine  36  may calculate the respective zero-crossing time t 0  of two different signals in such manner, and then calculate a phase misalignment based on a difference in time of the zero crossing of the two signals. 
     In some embodiments, such interpolation may be performed by taking an average of the amplitude difference or delta (e.g., average of Δn 1 , Δn 2 , etc.) between successive samples  40   a  occurring when reference signal y(t) is less than zero and the average of the amplitude difference (e.g., average of Δp 1 , Δp 2 , etc.) between successive samples  40   b  occurring when reference signal y(t) is greater than zero. Although  FIG. 4  depicts the use of only two samples below zero and two samples above zero for purposes of clarity and exposition, any suitable number of samples occurring in the approximately linear region of reference signal y(t) may be used. Stated another way, for each pair of successive samples  40   b  in which reference signal y(t) is greater than zero, gain calibration engine  36  may calculate a respective above-zero delta (e.g., Δp 1 , Δp 2 , . . . , Δp N ) for such pair of successive samples, each respective above-zero delta comprising an amplitude difference of the reference signal y(t) in the pair of successive samples used to calculate the respective above-zero delta. Similarly, for each pair of successive samples  40   a  in which reference signal y(t) is less than zero, the gain calibration engine  36  may calculate a respective below-zero delta (e.g., Δn 1 , Δn 2 , . . . , Δn N ) for such pair of successive samples, and each respective below-zero delta comprises an amplitude difference of the reference signal y(t) in the pair of successive samples used to calculate the respective below-zero delta. Having calculated the various deltas, the gain calibration engine  36  may interpolate to determine the first time based on an average of the respective above-zero deltas and an average of the respective below-zero deltas. 
     A time t 0  at which a zero cross occurs in reference signal y(t) may be computed by: 
               t   0     =       t   1     -     Δ       F   s     ⁢   N               
Where t 1  is the time occurrence of the first sample immediately after the zero cross of reference signal y(t) (e.g., y p1  (t)), Δ is the phase delay from time t 0  to t 1  expressed in terms of a resolution factor N, and F s  is the sampling frequency for reference signal y(t).
 
     The delta phase delay Δ may be given by: 
             Δ   =       y         p   ⁢             1     ⁢     (   t   )           A   ⁢           ⁢   I   ⁢           ⁢   R             
As expressed in terms of resolution factor N, where AIR is an “averaged interpolation range” described in further detail below. The resolution factor N may be given as a multiple of the sampling frequency F s  needed for desired accuracy. For example, if a phase estimate is needed in terms of 3 MHz and the sampling frequency for the system is 750 KHz, then N=3 MHz/750 KHz=4.
 
     Stated computationally, the averaged interpolation range AIR may be computed as: 
               A   ⁢           ⁢   I   ⁢           ⁢   R     =       1   2     [           ∑     i   =   1     n     ⁢           ⁢     (       y     p     i   +   1         -     y     p   i         )       n     +         ∑     i   =   1     n     ⁢           ⁢     (       y     n     i   +   1         -     y     n   i         )       n       ]           
or alternatively:
 
     
       
         
           
             
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     In instances in which a DC offset exists between two signals, the presence of DC offset may lead to inaccuracy in the calculation of phase misalignment. For example, in the absence of DC offset, as shown in  FIG. 5A , a reference signal y(t) may cross zero on its rising edge at a time 0 and cross zero on its falling edge at time t c  (or vice versa). However, as shown in  FIG. 5B , the same reference signal y(t) with a positive DC offset of C may have detected zero crossings  50  for rising edges that occur a time δ earlier (e.g., at a time −δ) than the actual zero crossing  52  that would occur in the absence of DC offset and may have detected zero crossings  50  for falling edges of reference signal y(t) occur later (e.g., at a time t c +δ) than the actual zero crossing  52  that would occur in the absence of DC offset. Similarly, as shown in  FIG. 5C , the same reference signal y(t) with a negative DC offset of C may have detected zero crossings  50  for rising edges that occur a time δ later (e.g., at a time δ) than the actual zero crossing  52  that would occur in the absence of DC offset and may have detected zero crossings  50  for falling edges of reference signal y(t) occurring earlier (e.g., at a time t c −δ) than the actual zero crossing  52  that would occur in the absence of DC offset. 
     A gain calibration engine  36  may compensate for such DC offset by approximating a rising zero cross time in which a reference signal y(t) crosses zero while rising in value by interpolating between successive samples occurring before and after the reference signal y(t) crosses zero while rising in value, and also approximating a falling zero cross time in which the reference signal y(t) crosses zero while falling in value by interpolating between successive samples occurring before and after the reference signal y(t) crosses zero while falling in value. The gain calibration engine  36  may then average the rising zero cross time and the falling zero cross time, which may cancel the time difference δ between actual and detected zero cross times introduced by DC offset leaving a value equal to the time (e.g., t c  in  FIGS. 5A-5C ) between zero crossings of the reference signal y(t), from which the times of actual zero crossings of the reference signal y(t) may be determined. 
     As contemplated above, as a phase misalignment between two signals increases, accuracy in the calculation of a gain compensation to equalize the gains of the two signals may decrease. This is particularly true when gain calculation is performed by measuring the respective signal energies of the two signals within a fixed time window, as characteristics of a first signal may occur within the fixed time window but such characteristics may be phase delayed in a second signal such that those characteristics in the second signal fall outside of the fixed time measurement window. 
     To minimize this inaccuracy due to phase misalignment of signals, a gain calibration engine  36  may apply a time-based weighting function to each of a first signal and a second signal within a fixed time measurement window.  FIG. 6  depicts an example time-based weighting function w(t) that may be applied to the signals within a fixed time window W. In operation, the gain calibration engine  36  may apply time-based weighting function w(t) to a first signal (e.g., x(t)) within fixed time window W to generate a weighted first signal (e.g., w(t)x(t)), apply time-based weighting function w(t) to a second signal (e.g., y(t)) within fixed time window W to generate a weighted first signal (e.g., w(t)y(t)), and calculate a relative gain based on a first signal energy of the weighted first signal in the fixed time window and a second signal energy of the second weighted signal in the fixed time window. From such calculated relative gain, gain calibration engine  36  may determine a gain compensation to apply to compensate for such relative gain. As shown in  FIG. 6 , in some embodiments weighting function w(t) may be symmetric about a reference time t axis  defining an axis of symmetry for weighting function w(t), and weighting function w(t) may monotonically increase in amplitude as a function of time before reference time t axis , and may monotonically decrease in amplitude as a function of time after the reference time t axis . By having greater magnitude near reference time t axis  and tapering off in magnitude towards the edges of fixed time window W, signal characteristics occurring within signals x(t) and y(t) near the edges of window W may be reduced in magnitude, reducing gain calculation inaccuracy for high-energy events that may occur near the edge of window W for one signal but fall outside window W for the other signal. 
     Although  FIG. 6  shows a particular example weighting function w(t), any suitable weighting function may be used in accordance with embodiments of the present disclosure. 
     In addition to or in lieu of using one or more of the foregoing techniques, gain calibration engine  36  may also reduce computation inaccuracy due to DC offset by calculating a relative gain between a first signal (e.g., x(t)) generated from a first signal path and a second signal generated from a second signal path (e.g., y(t)) by using a correlation function of the first signal (e.g., E(x)) and the second signal (e.g., E(y)) to compute the gain such that the gain is substantially unaffected by a difference in offset between the first signal and the second signal. As used herein, a function E may represent an expected value, averaged value, estimated value, or some other value of the signal to which the function E is applied. 
     For example, in some embodiments, the relative gain may be computed by calculating a ratio of two polynomial combinations of the functions E(x 2 ), E(x), E(xy), and E(y). As a specific example, the relative gain may be computed by the correlation function (E(xy)−E(x)E(y))/(E(x 2 )−E(x) 2 ), such that a DC offset term present in first signal x(t) is cancelled out. 
     In these and other embodiments, a time-based weighting function, such as the time-based weighting function w(t) described above with respect to  FIG. 6 , may be applied to either of the first signal or the second signal to generate a corresponding weighted signal. Applying such weighting signal, the relative gain between first signal x(t) and second signal y(t) may be computed by calculating a ratio of two polynomial combinations of E(wx 2 ), E(x), E(wxy), E(xy), and E(y), wherein w represents the weighting function. As a specific example, the relative gain may be computed by the correlation function (E(wxy)−E(wx)E(y))/(E(wx 2 )−E(wx)E(x)), such that a DC offset term present in first signal x(t) is cancelled out and the weighting function reduces sensitivity to phase misalignment. 
     Although the foregoing contemplates use of reconfigurable PWM modulation amplifiers  22 A and  22 B for use in an audio amplifier for driving an audio transducer, it is understood that reconfigurable PWM modulation amplifiers  22 A and  22 B may be used in other types of amplifiers for driving other types of transducers, including without limitation an amplifier for driving a haptic transducer. 
     As used herein, when two or more elements are referred to as “coupled” to one another, such term indicates that such two or more elements are in electronic communication or mechanical communication, as applicable, whether connected indirectly or directly, with or without intervening elements. 
     This disclosure encompasses all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Similarly, where appropriate, the appended claims encompass all changes, substitutions, variations, alterations, and modifications to the example embodiments herein that a person having ordinary skill in the art would comprehend. Moreover, reference in the appended claims to an apparatus or system or a component of an apparatus or system being adapted to, arranged to, capable of, configured to, enabled to, operable to, or operative to perform a particular function encompasses that apparatus, system, or component, whether or not it or that particular function is activated, turned on, or unlocked, as long as that apparatus, system, or component is so adapted, arranged, capable, configured, enabled, operable, or operative. Accordingly, modifications, additions, or omissions may be made to the systems, apparatuses, and methods described herein without departing from the scope of the disclosure. For example, the components of the systems and apparatuses may be integrated or separated. Moreover, the operations of the systems and apparatuses disclosed herein may be performed by more, fewer, or other components and the methods described may include more, fewer, or other steps. Additionally, steps may be performed in any suitable order. As used in this document, “each” refers to each member of a set or each member of a subset of a set. 
     Although exemplary embodiments are illustrated in the figures and described below, the principles of the present disclosure may be implemented using any number of techniques, whether currently known or not. The present disclosure should in no way be limited to the exemplary implementations and techniques illustrated in the drawings and described above. 
     Unless otherwise specifically noted, articles depicted in the drawings are not necessarily drawn to scale. 
     All examples and conditional language recited herein are intended for pedagogical objects to aid the reader in understanding the disclosure and the concepts contributed by the inventor to furthering the art, and are construed as being without limitation to such specifically recited examples and conditions. Although embodiments of the present disclosure have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the disclosure. 
     Although specific advantages have been enumerated above, various embodiments may include some, none, or all of the enumerated advantages. Additionally, other technical advantages may become readily apparent to one of ordinary skill in the art after review of the foregoing figures and description. 
     To aid the Patent Office and any readers of any patent issued on this application in interpreting the claims appended hereto, applicants wish to note that they do not intend any of the appended claims or claim elements to invoke 35 U.S.C. § 112(f) unless the words “means for” or “step for” are explicitly used in the particular claim.