Patent Publication Number: US-2022224359-A1

Title: Method and apparatus for channel encoding and decoding in communication or broadcasting system

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of application Ser. No. 16/859,953, filed Apr. 27, 2020, which is a continuation of application Ser. No. 15/971,877, filed May 4, 2018, now U.S. Pat. No. 10,680,652 issued Jun. 9, 2020, which claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2017-0057072, filed on May 4, 2017, 10-2017-0071906 filed on Jun. 8, 2017, and 10-2017-0075159 filed on Jun. 14, 2017, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entirety. 
    
    
     BACKGROUND 
     1. Field 
     The present disclosure relates to a method and apparatus for channel encoding and decoding in a communication or broadcasting system. 
     2. Description of Related Art 
     To meet the demand for wireless data traffic having increased since deployment of 4G communication systems, efforts have been made to develop an improved 5G or pre-5G communication system. Therefore, the 5G or pre-5G communication system is also called a ‘Beyond 4G Network’ or a ‘Post LTE System’. 
     The 5G communication system is considered to be implemented in higher frequency (mmWave) bands, e.g., 60 GHz bands, so as to accomplish higher data rates. To decrease propagation loss of the radio waves and increase the transmission distance, the beamforming, massive multiple-input multiple-output (MIMO), Full Dimensional MIMO (FD-MIMO), array antenna, an analog beam forming, large scale antenna techniques are discussed in 5G communication systems. 
     In addition, in 5G communication systems, development for system network improvement is under way based on advanced small cells, cloud Radio Access Networks (RANs), ultra-dense networks, device-to-device (D2D) communication, wireless backhaul, moving network, cooperative communication, Coordinated Multi-Points (CoMP), reception-end interference cancellation and the like. 
     In the 5G system, Hybrid FSK and QAM Modulation (FQAM) and sliding window superposition coding (SWSC) as an advanced coding modulation (ACM), and filter bank multi carrier (FBMC), non-orthogonal multiple access (NOMA), and sparse code multiple access (SCMA) as an advanced access technology have been developed. 
     In communication or broadcasting systems, the link performance may be degraded significantly due to various noises of a channel, fading phenomena, and inter-symbol interference (ISI). Therefor, in order to realize high-speed digital communication or broadcasting systems, such as next generation mobile communication, digital broadcasting, and mobile Internet, that require high data throughput and reliability, it is desirable to develop techniques for overcoming noises, fading, and IS. As one of such techniques, an error-correcting code capable of efficiently restoring the distortion of information and improving the reliability of communication has been studied in these days. 
     SUMMARY 
     The present disclosure provides LDPC encoding and decoding methods and apparatuses capable of supporting various input lengths and coding rates. 
     The present disclosure proposes a method for designing a dedicated LDPC code suitable for a case where the number of information bits is small and a coding rate is fixed. 
     According to the present disclosure, a channel encoding method of a transmitter in a communication system comprises performing low density parity check (LDPC) encoding for a bit sequence based on first information, the first information being identified based on second information and third information; and transmitting the encoded bit sequence to a receiver, and wherein the second information indicates information on non-zero blocks in the first information, and wherein the third information indicates information on values associated with the non-zero blocks. 
     The channel encoding method may further comprise determining a size of the bit sequence to which the LDPC encoding is to be applied; determining a block size (Z), based on the bit sequence size. 
     The second information may include thirty-two rows corresponding to a sequence given below. 
       0123691011 
       034567891112 
       01348101213 
       124567891013 
       011114 
       01571115 
       05791116 
       157111317 
       011218 
       18101119 
       016720 
       0791321 
       131122 
       0181323 
       16111324 
       0101125 
       19111226 
       15111227 
       06728 
       011029 
       141130 
       081331 
       1232 
       03533 
       12934 
       0535 
       27121336 
       0637 
       12538 
       0439 
       257940 
       11341 
     The block size (Z) may be determined as one of values given below. 
         Z 1′={3,6,12,24,48,96,192,384}
 
         Z 2′={11,22,44,88,176,352}
 
         Z 3′={5,10,20,40,80,160,320}
 
         Z 4′={9,18,36,72,144,288}
 
         Z 5′={2,4,8,16,32,64,128,256}
 
         Z 6′={15,30,60,120,240}
 
         Z 7′={7,14,28,56,112,224}
 
         Z 8′={13,26,52,104,208}
 
     a non-zero block may be a circulant permutation matrix determined based on a result of a modulo operation between the block size (Z) and the exponent value indicated by the third information. The second information may be capable of indicating positions of blocks of tip to 42 rows and 52 columns. 
     In addition, a channel decoding method of a receiver in a communication system comprises performing low density parity check (LDPC) decoding for a demodulated received signal based on first information, the first information being identified based on second information and third information, and wherein the second information indicates information on non-zero blocks in the first information, and wherein the third information indicates information on values associated with the non-zero blocks. 
     In addition, a transmitter performing channel encoding in a communication system comprises a controller configured to control to: perform low density parity check (LDPC) encoding for a bit sequence based on first information, the first information being identified based on second information and third information, and a transceiver configured to transmit the encoded bit sequence to a receiver, wherein the second information indicates information on non-zero blocks in the first information, and wherein the third information indicates information on values associated with the non-zero blocks. 
     In addition, a receiver performing channel decoding in a communication system comprises a transceiver configured to receive a signal from a transmitter; and a controller configured to: perform low density parity check (LDPC) decoding for a demodulated received signal based on first information, the first information being identified based on second information and third information, and wherein the second information indicates information on non-zero blocks in the first information, and wherein the third information indicates information on values associated with the non-zero blocks. 
     According to the present disclosure, it is possible to efficiently perform LDPC encoding for variable lengths and variable rates. 
     Before undertaking the DETAILED DESCRIPTION below, it may be advantageous to set forth definitions of certain words and phrases used throughout this patent document: the terms “include” and “comprise,” as well as derivatives thereof, mean inclusion without limitation; the term “or,” is inclusive, meaning and/or; the phrases “associated with” and “associated therewith,” as well as derivatives thereof, may mean to include, be included within, interconnect with, contain, be contained within, connect to or with, couple to or with, be communicable with, cooperate with, interleave, juxtapose, be proximate to, be bound to or with, have, have a property of, or the like; and the term “controller” means any device, system or part thereof that controls at least one operation, such a device may be implemented in hardware, firmware or software, or some combination of at least two of the same. It should be noted that the functionality associated with any particular controller may be centralized or distributed, whether locally or remotely. 
     Moreover, various functions described below can be implemented or supported by one or more computer programs, each of which is formed from computer readable program code and embodied in a computer readable medium. The terms “application” and “program” refer to one or more computer programs, software components, sets of instructions, procedures, functions, objects, classes, instances, related data, or a portion thereof adapted for implementation in a suitable computer readable program code. The phrase “computer readable program code” includes any type of computer code, including source code, object code, and executable code. The phrase “computer readable medium” includes any type of medium capable of being accessed by a computer, such as read only memory (ROM), random access memory (RAM), a hard disk drive, a compact disc (CD), a digital video disc (DVD), or any other type of memory. A “non-transitory” computer readable medium excludes wired, wireless, optical, or other communication links that transport transitory electrical or other signals. A non-transitory computer readable medium includes media where data can be permanently stored and media where data can be stored and later overwritten, such as a rewritable optical disc or an erasable memory device. 
     Definitions for certain words and phrases are provided throughout this patent document, those of ordinary skill in the art should understand that in many, if not most instances, such definitions apply to prior, as well as future uses of such defined words and phrases. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       For a more complete understanding of the present disclosure and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which like reference numerals represent like parts: 
         FIG. 1  is a diagram illustrating a structure of a systematic LDPC codeword. 
         FIG. 2  is a diagram illustrating a graph representation method of an LDPC code. 
         FIGS. 3A and 3B  are diagrams illustrating cycle characteristics of a QC-LDPC code. 
         FIG. 4  is a block diagram illustrating a transmitting apparatus according to an embodiment of the present disclosure. 
         FIG. 5  is a block diagram illustrating a receiving apparatus according to an embodiment of the present disclosure. 
         FIGS. 6A and 6B  are message structure diagrams illustrating a message passing operation at a check node and a variable node for LDPC decoding. 
         FIG. 7  is a block diagram illustrating an LDPC encoder according to an embodiment of the present disclosure. 
         FIG. 8  is a block diagram illustrating an LDPC decoder according to an embodiment of the present disclosure. 
         FIG. 9  is a block diagram illustrating a configuration of a decoding apparatus according to an embodiment of the present disclosure. 
         FIG. 10  is a diagram illustrating a structure of a transport block according to an embodiment of the present disclosure. 
         FIGS. 11, 11A, and 11B  are diagrams illustrating an example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 12, 12A, and 12B  are diagrams illustrating another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 13, 13A, and 13B  are diagrams illustrating still another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 14, 14A, and 14B  are diagrams illustrating yet another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 15, 15A, and 15B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 16, 16A, and 16B  are diagrams illustrating an example of an LDPC code base matrix according to an embodiment of the present disclosure. 
         FIGS. 17, 17A, and 17B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 18, 18A, and 18B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 19, 19A, and 19B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 20, 20A, and 20B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 21, 21A, and 21B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 22, 22A, and 22B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 23, 23A, and 23B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 24, 24A, and 24B  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIGS. 25 and 25A to 25I  are diagrams illustrating another example of an LDPC code base matrix according to an embodiment of the present disclosure. 
         FIGS. 26 and 26A to 26I  are diagrams illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 27  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 28  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 29  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 30  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 31  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 32  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
         FIG. 33  is a diagram illustrating further another example of an LDPC code exponential matrix according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
       FIGS. 1 through 33 , discussed below, and the various embodiments used to describe the principles of the present disclosure in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the disclosure. Those skilled in the art will understand that the principles of the present disclosure may be implemented in any suitably arranged system or device 
     Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. In the following, the descriptions of techniques that are well known in the art and not directly related to the present disclosure are omitted. This is to clearly convey the subject matter of the present disclosure by omitting an unnecessary explanation. In addition, the terms used herein are defined in consideration of functionality and may be changed according to the intention of users, operators, or the like. Therefore, the definition should be based on the contents throughout this disclosure. 
     Also, as understood by a person skilled in the art, the subject matter of this disclosure may be applied to other systems having similar technical backgrounds without departing from the scope of the present disclosure. 
     The advantages and features of the present disclosure and the manner of achieving them will become apparent with reference to embodiments to be described in detail below with reference to the accompanying drawings. The present disclosure may, however, be embodied in many different forms and should not be construed as limited to embodiments set forth herein. Rather, these embodiments are provided to fully convey the subject matter of this disclosure to those skilled in the art. Like reference numerals refer to like elements throughout this disclosure. 
     A low density parity check (LDPC) code, first introduced by Gallager in the 1960s, has been long forgotten due to the complexity of implementation. However, as a turbo code proposed by Berrou, Glavieux, and Thitimajshima in 1993 showed performance close to the channel capacity of Shannon, many interpretations about the performance and characteristics of the turbo code were made, and also many studies of channel encoding based on iterative decoding and graph were performed. Motivated by this, the LDPC code was studied again in the late 1990s. As a result, it was found that the LDCP code as well has performance close to the channel capacity of Shannon when iterative decoding based on a sum-product algorithm is applied on the Tanner graph corresponding to the LDPC code. 
     In general, the LDPC code is defined as a parity-check matrix and may be represented using a bipartite graph, which is commonly referred to as a Tanner graph. 
       FIG. 1  is a diagram illustrating a structure of a systematic LDPC codeword. 
     Referring to  FIG. 1 , LDPC encoding is performed on input of an information word  102  composed of K ldpc  bits or symbols, so that a codeword  100  composed of N ldpc  bits or symbols is generated. Hereinafter, for convenience of explanation, it is assumed that the codeword  100  composed of N ldpc  bits is generated by receiving the information word  102  including K ldpc  bits. That is, when the information word  102  of K ldpc  input bits, I=[i 0 , i 1 , i 2 , . . . , i K     ldpc     −1 ], is subjected to LDPC encoding, the codeword  100 , c=[c 0 , c 1 , c 2 , . . . , C N     ldpc     −1 ], is generated. That is, each of the information word and the codeword is a bit string composed of a plurality of bits, and thus an information word bit or a codeword bit means each bit constituting the information word or the codeword. Typically, when a codeword includes an information word, i.e., C=[c 0 , c 1 , c 2 , . . . , c N     ldpc     −1 ]=[i 0 , i 1 , i 2 , . . . , i K     ldpc     −1 , p 0 , p 1 , p 2 , . . . , p K     ldpc     −K     ldpc     −1 ], this is referred to as a systematic code. Here, P=[p 0 , p 1 , p 2 , . . . , p N     ldpc     −K     ldpc     −1 ] is parity bits  104 , and the number of parity bits may be represented as N parity =N ldpc −K ldpc . 
     The LDPC code is a type of linear block code and includes a process of determining a codeword that satisfies the following Equation 1. 
     
       
         
           
             
               
                 
                   
                     H 
                     · 
                     
                       c 
                       T 
                     
                   
                   = 
                   
                     
                       
                         [ 
                         
                           
                             
                               
                                 h 
                                 1 
                               
                             
                             
                               
                                 h 
                                 2 
                               
                             
                             
                               
                                 h 
                                 3 
                               
                             
                             
                               … 
                             
                             
                               
                                 h 
                                 
                                   
                                     N 
                                     idpc 
                                   
                                   - 
                                   1 
                                 
                               
                             
                           
                         
                         ] 
                       
                       · 
                       
                         c 
                         T 
                       
                     
                     = 
                     
                       
                         
                           ∑ 
                           
                             i 
                             = 
                             0 
                           
                           
                             N 
                             idpc 
                           
                         
                         ⁢ 
                         
                           
                             c 
                             i 
                           
                           · 
                           
                             h 
                             i 
                           
                         
                       
                       = 
                       0 
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
               
             
           
         
       
     
     Here, c=[c 0 , c 1 , c 2 , . . . , c N     ldpc     −1 ] 
     In Equation 1, H denotes a parity check matrix, C denotes a codeword, c i  denotes the i-th bit of a codeword, and N ldpc  denotes an LDPC codeword length. Here, h i  denotes the i-th column of the parity check matrix H. 
     The parity check matrix H is composed of N ldpc  columns equal to the number of bits of the LDPC codeword. Equation 1 means that the sum of products of the i-th column h i  of the parity check matrix and the i-th codeword bit c i  is zero, thus meaning that the i-th column h i  is related to the i-th codeword bit c i . 
     Now, a graphical representation method of an LDPC code will be described with reference to  FIG. 2 . 
       FIG. 2  shows an example of a parity check matrix H 1  of an LDPC code, composed of four rows and eight columns, and a Tanner graph thereof. Referring to  FIG. 2 , the parity check matrix H 1  having eight columns generates a codeword having a length of 8. A code generated through H 1  means an LDPC code, and each column corresponds to encoded 8 bits. 
     Referring to  FIG. 2 , the Tanner graph of the LDPC code for encoding and decoding based on the parity check matrix H 1  includes eight variable nodes, i.e., x 1    202 , x 2    204 , x 3    206 , x 4    208 , x 5    210 , x 6    212 , x 7    214 , and x 8    216 , and four check nodes  218 ,  220 ,  222 , and  224 . Here, the i-th column and the j-th row of the parity check matrix H 1  of the LDPC code correspond to the variable node x i  and the j-th check node, respectively. The value of 1, that is, a value other than 0, at the intersection of the i-th column and the j-th row in the parity check matrix H 1  of the LDPC code means that there is an edge (or referred to as a segment) connecting the variable node x i  and the j-th check node in the Tanner graph. 
     In the Tanner graph of the LDPC code, the degree of each of the variable node and the check node means the number of edges connected to each node, and this is equal to the number of non-zero entries (or referred to as non-zero elements) in the column or row corresponding to a relevant node in the parity check matrix of the LDPC code. For example, in  FIG. 2 , the degrees of the variable nodes  202 ,  204 ,  206 ,  208 ,  210 ,  212 ,  214 , and  216  are 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and the degrees of the check nodes  218 ,  220 ,  222 , and  224  are 6, 5, 5, and 5, respectively. Also, in  FIG. 2 , the numbers of non-zero entries in the respective columns of the parity check matrix H 1  corresponding to the variable nodes are equal to the above degrees 4, 3, 3, 3, 2, 2, 2, and 2, respectively, and the numbers of non-zero entries in the respective rows of the parity check matrix H 1  corresponding to the check nodes are equal to the above degrees 6, 5, and 5, respectively. 
     The LDPC code may be decoded using an iterative decoding algorithm based on a sum-product algorithm on the bipartite graph shown in  FIG. 2 . Here, the sum-product algorithm is a kind of message passing algorithm, which indicates an algorithm for exchanging messages through an edge on the bipartite graph and performing update by calculating an output message from messages inputted to the variable node or the check node. 
     Here, the value of the i-th encoded bit may be determined, based on a message of the i-th variable node. The value of the i-th encoded bit is available for both a hard decision and a soft decision. Therefore, the performance of the i-th bit c i  of the LDPC codeword corresponds to the performance of the i-th variable node of the Tanner graph, and this may be determined according to the position and number of 1s in the i-th column of the parity check matrix. That is, the performance of the N ldpc  codeword bits of the codeword may depend on the position and number of Is of the parity check matrix. This means that the performance of the LDPC code is greatly affected by the parity check matrix. Therefore, a method for designing a good parity check matrix is desired to design the LDPC code with excellent performance. 
     In the communication or broadcasting systems, a quasi-cyclic LDPC code (hereinafter, a QC-LDPC code) using a parity check matrix of a quasi-cyclic form is used typically for easy implementation. 
     The QC-LDPC code is characterized by having a parity check matrix composed of zero matrices or circulant permutation matrices, which have a small square matrix form. Here, the permutation matrix means a matrix in which each row or column contains a single entry of 1 and the other entries of 0. The circulant permutation matrix means a matrix obtained by circularly shifting all entries of the identity matrix to the right. 
     Hereinafter, the QC-LDPC code will be described in detail. 
     First, a circulant permutation matrix, P=(P i,j ), having a size of L×L is defined as shown in Equation 2. Here, P i,j (0≤i, j&lt;L) denotes an entry (or referred to as an element) of the i-th row and the j-th column in the matrix P. 
     
       
         
           
             
               
                 
                   
                     P 
                     
                       i 
                       , 
                       j 
                     
                   
                   = 
                   
                     { 
                     
                       
                         
                           1 
                         
                         
                           
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 i 
                               
                               + 
                               1 
                             
                             ≡ 
                             
                               j 
                               ⁢ 
                               mod 
                               ⁢ 
                               L 
                             
                           
                         
                       
                       
                         
                           0 
                         
                         
                           
                             otherwise 
                             . 
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
               
             
           
         
       
     
     With respect to the permutation matrix P defined as above, P i (0≤i&lt;L) is a circulant permutation matrix obtained by circularly shifting respective entries of the identity matrix rightward by i times. 
     A parity check matrix H of the simplest QC-LDPC code may be represented in the form of the following Equation 3. 
     
       
         
           
             
               
                 
                   H 
                   = 
                   
                     [ 
                     
                       
                         
                           
                             P 
                             
                               a 
                               11 
                             
                           
                         
                         
                           
                             P 
                             
                               a 
                               12 
                             
                           
                         
                         
                           … 
                         
                         
                           
                             P 
                             
                               a 
                               
                                 1 
                                 ⁢ 
                                 n 
                               
                             
                           
                         
                       
                       
                         
                           
                             P 
                             
                               a 
                               21 
                             
                           
                         
                         
                           
                             P 
                             
                               a 
                               22 
                             
                           
                         
                         
                           … 
                         
                         
                           
                             P 
                             
                               a 
                               
                                 2 
                                 ⁢ 
                                 n 
                               
                             
                           
                         
                       
                       
                         
                           ⋮ 
                         
                         
                           ⋮ 
                         
                         
                           ⋱ 
                         
                         
                           ⋮ 
                         
                       
                       
                         
                           
                             P 
                             
                               a 
                               
                                 m 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 1 
                               
                             
                           
                         
                         
                           
                             P 
                             
                               a 
                               
                                 m 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                         
                         
                           … 
                         
                         
                           
                             P 
                             
                               a 
                               mn 
                             
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   3 
                 
               
             
           
         
       
     
     If P −1  is defined as a zero matrix having a size of L×L, each exponent a i,j  of the circulant permutation matrix or the zero matrix in Equation 3 has one of values {−1, 0, 1, 2, . . . , L−1}. Also, the parity check matrix H of Equation 3 has a size of mL×nL because of having n column blocks and m row blocks. 
     If the parity check matrix of Equation 3 has a full rank, the size of information bits of a QC-LDPC code corresponding to the parity check matrix becomes (n−m)*L. For convenience, (n−m) column blocks corresponding to information bits are referred to as information word column blocks, and m column blocks corresponding to the remaining parity bits are referred to as parity column blocks. 
     Normally, a binary matrix having a size of m×n obtained by replacing the circulant permutation matrix and the zero matrix by 1 and 0, respectively, in the parity check matrix of Equation 3 is referred to as a mother matrix or base matrix M(H) of the parity check matrix H. In addition, an integer matrix having a size of m×n obtained as shown in Equation 4 by selecting exponents of the circulant permutation matrix and the zero matrix is referred to as an exponential matrix E(H) of the parity check matrix H. 
     
       
         
           
             
               
                 
                   
                     E 
                     ⁡ 
                     
                       ( 
                       H 
                       ) 
                     
                   
                   = 
                   
                     [ 
                     
                       
                         
                           
                             a 
                             11 
                           
                         
                         
                           
                             a 
                             12 
                           
                         
                         
                           … 
                         
                         
                           
                             a 
                             
                               1 
                               ⁢ 
                               n 
                             
                           
                         
                       
                       
                         
                           
                             a 
                             21 
                           
                         
                         
                           
                             a 
                             22 
                           
                         
                         
                           … 
                         
                         
                           
                             a 
                             
                               2 
                               ⁢ 
                               n 
                             
                           
                         
                       
                       
                         
                           ⋮ 
                         
                         
                           ⋮ 
                         
                         
                           ⋱ 
                         
                         
                           ⋮ 
                         
                       
                       
                         
                           
                             a 
                             
                               m 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                             
                           
                         
                         
                           
                             a 
                             
                               m 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                         
                         
                           … 
                         
                         
                           
                             a 
                             mn 
                           
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   4 
                 
               
             
           
         
       
     
     As a result, one integer included in the exponential matrix corresponds to the circulant permutation matrix in the parity check matrix, so that the exponential matrix may be represented as an integer sequence for convenience. This sequence will be referred as an LDPC sequence or an LDPC code sequence to distinguish it from another sequence. In general, the parity check matrix may be represented not only as the exponential matrix but also as a sequence having the same characteristics algebraically. In this disclosure, the parity check matrix is represented as an exponential matrix or a sequence that indicates the positions of is in the parity check matrix. However, because there are various sequence notation methods for distinguishing the positions of 1s or 0s included in the parity check matrix, it is possible to alternatively represent a variety of sequence forms that exhibit the same effect algebraically. 
     In addition, a transmitting/receiving apparatus of a device may directly generate the parity check matrix to perform LDPC encoding and decoding. However, depending on characteristics of implementation, the LDPC encoding and decoding may be performed using the exponential matrix or sequence having the same algebraic effect as the parity check matrix has. Therefore, although the encoding and decoding using the parity check matrix are described for convenience in this disclosure, the present disclosure may be implemented actually in a device through various methods capable of achieving the same effect as the parity check matrix does. 
     For reference, the same algebraic effect means that two or more different representations are completely identical or converted to each other logically or mathematically. 
     Although described in this disclosure is a case where the circulant permutation matrix corresponding to one block is single, the present disclosure may be equally applied to another case where a plurality of circulant permutation matrices are included in one block. For example, when the sum of two circulant permutation matrices P a     ij       (1)   ,P a     ij       (2)    is included in one position of the i-th row block and the j-th column block as shown in Equation 5, the exponential matrix may be expressed as shown in Equation 6. As seen from Equation 6, two integers are contained in a position of the i-th row and the j-th column that correspond to the above position containing the sum of circulant permutation matrices. 
     
       
         
           
             
               
                 
                   H 
                   = 
                   
                     [ 
                     
                       
                         
                           ⋱ 
                         
                         
                           □ 
                         
                         
                           □ 
                         
                         
                           ⋰ 
                         
                       
                       
                         
                           □ 
                         
                         
                           
                             
                               P 
                               
                                 a 
                                 ij 
                                 
                                   ( 
                                   1 
                                   ) 
                                 
                               
                             
                             + 
                             
                               P 
                               
                                 a 
                                 ij 
                                 
                                   ( 
                                   2 
                                   ) 
                                 
                               
                             
                           
                         
                         
                           □ 
                         
                         
                           □ 
                         
                       
                       
                         
                           □ 
                         
                         
                           
                               
                           
                         
                         
                           □ 
                         
                         
                           □ 
                         
                       
                       
                         
                           ⋰ 
                         
                         
                           □ 
                         
                         
                           □ 
                         
                         
                           ⋱ 
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   5 
                 
               
             
             
               
                 
                   
                     E 
                     ⁡ 
                     
                       ( 
                       H 
                       ) 
                     
                   
                   = 
                   
                     [ 
                     
                       
                         
                           ⋱ 
                         
                         
                           □ 
                         
                         
                           □ 
                         
                         
                           ⋰ 
                         
                       
                       
                         
                           □ 
                         
                         
                           
                             ( 
                             
                               
                                 a 
                                 ij 
                                 
                                   ( 
                                   1 
                                   ) 
                                 
                               
                               , 
                               
                                 a 
                                 ij 
                                 
                                   ( 
                                   2 
                                   ) 
                                 
                               
                             
                             ) 
                           
                         
                         
                           □ 
                         
                         
                           □ 
                         
                       
                       
                         
                           □ 
                         
                         
                           
                               
                           
                         
                         
                           □ 
                         
                         
                           □ 
                         
                       
                       
                         
                           ⋰ 
                         
                         
                           □ 
                         
                         
                           □ 
                         
                         
                           ⋱ 
                         
                       
                     
                     ] 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   6 
                 
               
             
           
         
       
     
     Although the QC-LDPC code normally allows a plurality of circulant permutation matrices to correspond to one row/column block in the parity check matrix as described above, the present disclosure will describe a case where one circulant permutation matrix corresponds to one block. This is, however, exemplary only and is not to be construed as a limitation. For reference, a matrix having a size of L×L in which a plurality of circulant permutation matrices are overlapped in one row/column block is referred to as a circulant matrix or circulant. 
     Meanwhile, a mother matrix or a base matrix for the parity check matrix and the exponential matrix of Equations 5 and 6 means a binary matrix obtained by replacing the circulant permutation matrix and the zero matrix by 1 and 0, respectively, similarly to the definition used in Equation 3. Also, the sum of a plurality of circulant permutation matrices included in one block (i.e., a circulant matrix) is replaced simply by 1. 
     Because the performance of the LDPC code is determined according to the parity check matrix, it is desirable to design the parity check matrix for the LDPC code having excellent performance. Also, there is a desire for an LDPC encoding or decoding method capable of supporting various input lengths and coding rates. 
     Lifting refers to a method used not only for efficiently designing the QC-LDPC code but also for generating the parity check matrices or LDPC codewords of various lengths from a given exponential matrix. That is, the lifting may be applied to efficiently design a very large parity check matrix by setting an L value that determines the size of the circulant permutation matrix or the zero matrix from a given small mother matrix according to a specific rule, or is used to generate the parity check matrices or LDPC codewords having various lengths by applying an appropriate L, value to a given exponential matrix or corresponding sequence. 
     A typical lifting method and the characteristics of the QC-LDPC code designed through lifting are hereinafter described with reference to the following reference, which is incorporated by reference in its entirety
     Reference [Myung2006]   S. Myung, K. Yang, and Y. Kim, “Lifting Methods for Quasi-Cyclic LDPC Codes”, IEEE Communications Letters. vol. 10, pp. 489-491, June 2006.   

     When an LDPC code C 0  is given, it is assumed that S QC-LDPC codes to be designed through the lifting method are C 1 , . . . , C S , and that the size of a row block and a column block of a parity check matrix of each QC-LDPC code has a value of L k . Here, C 0  corresponds to the smallest LDPC code having a mother matrix of C 1 , . . . , C S  codes as a parity check matrix, and a value of L 0  corresponding to the size of a row block and a column block is 1. In addition a parity check matrix H k  of each code C k  has an exponential matrix E(H k )=(e i,j   (k) ) of a m×n size, and each exponent e i,j   (k)  is selected as one of values {−1, 0, 1, 2, . . . , L k −1}. 
     The typical lifting method consists of steps C 0 →C 1 → . . . →C S  and has characteristics that satisfy a condition L k+1 =q k+1 L k  (q k+1  is a positive integer, k=0, 1, . . . , S−1). If a parity check matrix H S  of C S  is stored according to the characteristics of the lifting process, all the QC-LDPC codes C 0 , C 1 , . . . , C S  can be represented using the following Equation 7 according to the lifting method. 
     
       
         
           
             
               
                 
                   
                     E 
                     ⁡ 
                     
                       ( 
                       
                         H 
                         k 
                       
                       ) 
                     
                   
                   ≡ 
                   
                     
                       ⌊ 
                       
                         
                           
                             L 
                             k 
                           
                           
                             L 
                             S 
                           
                         
                         ⁢ 
                         
                           E 
                           ⁡ 
                           
                             ( 
                             
                               H 
                               S 
                             
                             ) 
                           
                         
                       
                       ⌋ 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     or 
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   7 
                 
               
             
             
               
                 
                   
                     E 
                     ⁡ 
                     
                       ( 
                       
                         H 
                         k 
                       
                       ) 
                     
                   
                   ≡ 
                   
                     
                       E 
                       ⁡ 
                       
                         ( 
                         
                           H 
                           S 
                         
                         ) 
                       
                     
                     ⁢ 
                     
                       
                         mod 
                         ⁢ 
                         L 
                       
                       k 
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   8 
                 
               
             
           
         
       
     
     Not only a method of designing large QC-LDPC codes C 1 , . . . , C S  from C 0  but also a method of designing small codes C i (i=k−1, k−2, . . . , 1, 0) from a large code C k  by using a suitable technique such as Equation 7 or 8 is called lifting. 
     According to the lifting method of Equation 7 or 8, the L k  corresponding to the size of row block or column block in the parity check matrix of each QC-LDPC code C k  has a multiple relation with each other, and also an exponential matrix is selected by a specific manner. The typical lifting method improves the algebraic or graph characteristics of each parity check matrix designed through lifting, thus allowing an easy design of the QC-LDPC code with an improved error floor feature. 
     However, because respective L k  values are in a multiple relation, there is a disadvantage that the length of each code is greatly limited. For example, when it is assumed that the minimum lifting scheme such as L k+1 =2×L k  is applied to each L k  value, the size of a parity check matrix of each QC-LDPC code may have a size of 2 k m×2 k n. That is, when the lifting is applied in 10 steps (S=10), ten sizes of a parity check matrix may be generated. This means that it is possible to support the QC-LDPC codes having ten kinds of lengths. 
     For this reason, the typical lifting method is somewhat disadvantageous in designing the QC-LDPC code that supports various lengths. However, commonly used communication systems require a very high level of length compatibility in consideration of various types of data transmission. For this reason, the LDPC coding technique based on the typical lifting method has a problem that it is difficult to apply to communication systems. 
     In order to solve such a problem, the present disclosure uses the following lifting method. 
     Normally, the lifting may be considered to vary the values of entries in the exponential matrix of Equation 4 with respect to various L values in order to use it for LDPC encoding and decoding. For example, when the exponential matrix of Equation 4 is E=(a i,j ), and when the exponential matrix converted according to an L value is E L =(a i,j   (L) ), a conversion equation such as Equation 9 may be applied in general. 
     
       
         
           
             
               
                 
                   
                     a 
                     
                       i 
                       , 
                       j 
                     
                     
                       ( 
                       L 
                       ) 
                     
                   
                   = 
                   
                     { 
                     
                       
                         
                           
                             
                               a 
                               
                                 i 
                                 , 
                                 j 
                               
                             
                           
                           
                             
                               
                                 a 
                                 
                                   i 
                                   , 
                                   j 
                                 
                               
                               &lt; 
                               0 
                             
                           
                         
                         
                           
                             
                               f 
                               ⁡ 
                               
                                 ( 
                                 
                                   
                                     a 
                                     
                                       i 
                                       , 
                                       j 
                                     
                                   
                                   , 
                                   L 
                                 
                                 ) 
                               
                             
                           
                           
                             
                               
                                 a 
                                 
                                   i 
                                   , 
                                   j 
                                 
                               
                               ≥ 
                               0 
                             
                           
                         
                       
                       , 
                       
                         
                           or 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             a 
                             
                               i 
                               , 
                               j 
                             
                             
                               ( 
                               L 
                               ) 
                             
                           
                         
                         = 
                         
                           { 
                           
                             
                               
                                 
                                   a 
                                   
                                     i 
                                     , 
                                     j 
                                   
                                 
                               
                               
                                 
                                   
                                     a 
                                     
                                       i 
                                       , 
                                       j 
                                     
                                   
                                   ≤ 
                                   0 
                                 
                               
                             
                             
                               
                                 
                                   f 
                                   ⁡ 
                                   
                                     ( 
                                     
                                       
                                         a 
                                         
                                           i 
                                           , 
                                           j 
                                         
                                       
                                       , 
                                       L 
                                     
                                     ) 
                                   
                                 
                               
                               
                                 
                                   
                                     a 
                                     
                                       i 
                                       , 
                                       j 
                                     
                                   
                                   &gt; 
                                   0 
                                 
                               
                             
                           
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   9 
                 
               
             
           
         
       
     
     In Equation 9, f(x,L) may be defined in various forms. For example, definitions as shown in the following Equation 10 may be used. 
     
       
         
           
             
               
                 
                   
                     f 
                     ⁡ 
                     
                       ( 
                       
                         x 
                         , 
                         L 
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         mod 
                         ⁡ 
                         
                           ( 
                           
                             x 
                             , 
                             
                               2 
                               
                                 ⌊ 
                                 
                                   
                                     log 
                                     2 
                                   
                                   ⁢ 
                                   L 
                                 
                                 ⌋ 
                               
                             
                           
                           ) 
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       or 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         f 
                         ⁡ 
                         
                           ( 
                           
                             x 
                             , 
                             L 
                           
                           ) 
                         
                       
                     
                     = 
                     
                       
                         
                           ⌊ 
                           
                             x 
                             
                               2 
                               
                                 D 
                                 - 
                                 
                                   ⌊ 
                                   
                                     
                                       log 
                                       2 
                                     
                                     ⁢ 
                                     L 
                                   
                                   ⌋ 
                                 
                               
                             
                           
                           ⌋ 
                         
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         or 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           f 
                           ⁡ 
                           
                             ( 
                             
                               x 
                               , 
                               L 
                             
                             ) 
                           
                         
                       
                       = 
                       
                         ⌊ 
                         
                           
                             L 
                             D 
                           
                           ⁢ 
                           x 
                         
                         ⌋ 
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   10 
                 
               
             
           
         
       
     
     In Equation 10, mod(a,b) denotes a modulo-b operation for a, and D denotes a constant that is a predefined positive integer. 
       FIG. 4  is a block diagram illustrating a transmitting apparatus according to an embodiment of the present disclosure. 
     As shown in  FIG. 4 , in order to process variable-length input bits, the transmitting apparatus  400  may include a segmentation unit  410 , a zero padding unit  420 , an LDPC encoder  430 , a rate matching unit  440 , and a modulator  450 . The rate matching unit  440  may include an interleaver  441  and a puncturing/repetition/zero elimination unit  442 . 
     Elements shown in  FIG. 4  are configured to perform encoding and modulation for variable-length input bits. These elements are, however, exemplary only, and some of them may be omitted or replaced or any other element may be added. 
     Meanwhile, the transmitting apparatus  400  may determine parameters (e.g., input bit length, modulation and code rate (ModCod), parameter for zero padding (or shortening), coding rate and/or codeword length of LDPC code, parameter for interleaving, parameter for repetition and puncturing, modulation scheme), and perform encoding on the basis of the determined parameters before transmission to a receiving apparatus  500 . 
     The number of input bits is variable. Therefore, if the number of input bits is greater than a predetermined value, the input bits may be segmented to have a length equal to or smaller than the predetermined value. Also, each segmented block may correspond to one LDPC encoded block. If the number of input bits is equal to or smaller than the predetermined value, no segmentation is performed. In this case, the input bits may correspond to one LDPC encoded block. 
     The transmitting apparatus  400  may store various parameters used for encoding, interleaving, and modulation. The parameters used for encoding may be a coding rate of the LDPC code, a codeword length, and information about the parity check matrix. The parameters used for interleaving may be information about an interleaving rule, and the parameters used for modulation may be information about a modulation scheme. Further, information about puncturing may be a puncturing length, and information about repetition may be a repetition length. The information about the parity check matrix may include an exponent value of the circulant matrix when the parity matrix proposed in the present disclosure is used. 
     In this case, the respective elements constituting the transmitting apparatus  400  may perform an operation using the above-mentioned parameters. 
     Although not shown, the transmitting apparatus  400  may further include a controller (not shown) for controlling the operation of the transmitting apparatus  400 . 
       FIG. 5  is a block diagram illustrating a receiving apparatus according to an embodiment of the present disclosure. 
     As shown in  FIG. 5 , in order to process variable-length information, the receiving apparatus  500  may include a demodulator  510 , a rate dematching unit  520 , an LDPC decoder  530 , a zero elimination unit  540 , and a desegmentation unit  550 . The rate dematching unit  520  may include a log likelihood ratio (LLR) insertion unit  522 , an LLR combiner  523 , a deinterleaver  524 , and the like. 
     Elements shown in  FIG. 5  are configured to perform functions of the receiving apparatus. These elements are, however, exemplary only, and some of them may be omitted or replaced or any other element may be added. 
     The parity check matrix disclosed herein may be read using a memory, be given in advance in the transmitting apparatus or the receiving apparatus, or be directly generated by the transmitting apparatus or the receiving apparatus. In addition, the transmitting apparatus may store or generate a sequence or exponential matrix corresponding to the parity check matrix, and apply it to encoding. Similarly, the receiving apparatus may store or generate a sequence or exponential matrix corresponding to the parity check matrix, and apply it to decoding. 
     Hereinafter, a receiver operation will be described in detail with reference to  FIG. 5 . 
     The demodulator  510  demodulates a signal received from the transmitting apparatus  400 . 
     Specifically, the demodulator  510 , which is an element corresponding to the modulator  450  of the transmitting apparatus  400 , demodulates a signal received from the transmitting apparatus  400  and then generates values corresponding to bits transmitted from the transmitting apparatus  400 . 
     For this, the receiving apparatus  500  may previously store information about a modulation scheme used by the transmitting apparatus  400  depending on a mode. Therefore, depending on a mode, the demodulator  510  may demodulate a signal received from the transmitting apparatus  400  and generate values corresponding to LDPC codeword bits. 
     Meanwhile, a value corresponding to bits transmitted from the transmitting apparatus  400  may be a log likelihood ratio (LLR) value. 
     Specifically, the LLR value may be represented by the logarithm of the ratio of a probability that a bit transmitted from the transmitting apparatus  400  is zero, to a probability that the bit is one. Alternatively, the LLR value may be a bit value itself, or be a representative value determined according to an interval to which a probability that a bit transmitted from the transmitting apparatus  400  is 0 or 1 belongs. 
     The demodulator  510  further performs multiplexing (not shown) on the LLR value. Specifically, as an element corresponding to a bit deMUX (not shown) of the transmitting apparatus  400 , the demodulator  510  may perform an operation corresponding to the bit deMUX. 
     For this, the receiving apparatus  500  may previously store information about parameters used for demultiplexing and block interleaving by the transmitting apparatus  400 . Therefore, an MUX (not shown) may inversely perform the demultiplexing and block interleaving operation performed by the bit deMUX with respect to the LLR value corresponding to a cell word (i.e., information indicating a receiving symbol for the LDPC codeword as a vector value), and multiplex the LLR value corresponding to the cell word in a bit unit. 
     The rate dematching unit  520  may insert a certain LLR value into an LLR value output of the demodulator  510 . That is, the rate dematching unit  520  may insert predetermined LLR values between LLR values outputted from the demodulator  510 . 
     Specifically, the rate dematching unit  520  is an element corresponding to the rate matching unit  440  of the transmitting apparatus  400 , and may perform operations corresponding to the interleaver  441  and the puncturing/repetition/zero elimination unit  442 . 
     First, the rate dematching unit  520  may perform deinterleaving corresponding to the interleaver  441 . LLR values corresponding to zero bits in positions where the zero bits have been padded in the LDPC codeword are inserted to output value of the deinterleaver  524 . In this case, the LLR value corresponding to the padded zero bits, i.e., shortened zero bits, may be positive infinity (∞) or negative infinity (−∞). However, this is theoretical, and actually the LLR value corresponding to the padded zero bits may be the maximum or minimum value of LLR values used in the receiving apparatus  500 . 
     For this, the receiving apparatus  500  may previously store information about parameters used for padding the zero bits by the transmitting apparatus  400 . Therefore, the rate dematching unit  520  may identify the positions where the zero bits have been padded in the LDPC codeword, and then insert the LLR value corresponding to the shortened zero bits in the identified positions. 
     In addition, the LLR insertion unit  522  of the rate dematching unit  520  may insert an LLR value corresponding to punctured bits in positions of the punctured bits in the LDPC codeword. In this case, the LLR value corresponding to the punctured bits may be zero. 
     For this, the receiving apparatus  500  may previously store information about parameters used for puncturing by the transmitting apparatus  400 . Therefore, the LLR insertion unit  522  may insert the corresponding LLR value in positions where the LDPC parity bits are punctured. 
     An LLR combiner  523  of the rate dematching unit  520  may combine (i.e., sum up) the LLR values outputted from the LLR insertion unit  522  and the demodulator  510 . Specifically, the LLR combiner  523 , which is an element corresponding to the puncturing/repetition/zero elimination unit  442  of the transmitting apparatus  400 , may perform an operation corresponding to repetition. First, the LLR combiner  523  may combine an LLR value corresponding to repeated bits with other LLR value. Here, the other LLR value may be an LLR value for bits used as basis of generating the repeated bits by the transmitting apparatus  400 , namely, for LDPC parity bits that have been selected for repetition. 
     That is, as described above, the transmitting apparatus  400  selects bits from LDPC parity bits, repeats the selected bits between the LDPC information bits and the LDPC parity bits, and transmits the repeated bits to the receiving apparatus  500 . 
     Therefore, the LLR value for the LDPC parity bits may be composed of an LLR value for repeated LDPC parity bits and an LLR value for non-repeated LDPC parity bits (i.e., LDPC parity bits generated by encoding). Thus, the LLR combiner  523  may combine the LLR values with the same LDPC parity bits. 
     For this, the receiving apparatus  500  may previously store information about parameters used for repetition by the transmitting apparatus  400 . Therefore, the LLR combiner  523  may identify an LLR value for the repeated LDPC parity bits and combine the identified LLR value with an LLR value for LDPC parity bits on which the repetition is based. 
     In addition, the LLR combiner  523  may combine an LLR value corresponding to retransmission or increment redundancy (IR) bits with other LLR value. Here, the other LLR value may be an LLR value for the bits selected for the generation of LDPC codeword bits on which the generation of the retransmission or IR bits is based in the transmitting apparatus  400 . 
     That is, when a NACK occurs for HARQ, the transmitting apparatus  400  may transmit some or all of the codeword bits to the receiving apparatus  500 . 
     Therefore, the LLR combiner  523  may combine an LLR value for bits received via retransmission or IR with another LLR value for LDPC codeword bits received via the previous frame. 
     For this, the receiving apparatus  500  may previously store information about parameters used for retransmission or IR bits generation by the transmitting apparatus  400 . Therefore, the LLR combiner  523  may identify an LLR value for the number of retransmission or IR bits and combine the identified LLR value with an LLR value for the LDPC parity bits on which the generation of the retransmission bits is based. 
     A deinterleaver  524  of the rate dematching unit  520  may deinterleave an LLR value outputted from the LLR combiner  523 . 
     Specifically, the deinterleaver  524  is an element corresponding to the interleaver  441  of the transmitting apparatus  400 , and may perform an operation corresponding to the interleaver  441 . 
     For this, the receiving apparatus  500  may previously store information about parameters used for interleaving by the transmitting apparatus  400 . Therefore, the deinterleaver  524  may deinterleave an LLR value corresponding to LDPC codeword bits by inversely performing an interleaving operation performed by the interleaver  441  on the LLR values corresponding to the LDPC codeword bits. 
     The LDPC decoder  530  may perform LDPC decoding, based on the LLR value outputted from the rate dematching unit  520 . 
     Specifically, the LDPC decoder  530  is an element corresponding to the LDPC encoder  430  of the transmitting apparatus  400 , and may perform an operation corresponding to the LDPC encoder  430 . 
     For this, the receiving apparatus  500  may previously store information about parameters used for LDPC encoding by the transmitting apparatus  400  depending on a mode. Therefore, depending on a mode, the LDPC decoder  530  may perform LDPC decoding based on the LLR value outputted from the rate dematching unit  520 . 
     For example, the LDPC decoder  530  may perform LDPC decoding on the basis of the LLR value outputted from the rate dematching unit  520  in accordance with an iterative decoding scheme based on the sum-product algorithm, and output error-corrected bits according to LDPC decoding. 
     The zero elimination unit  540  may remove zero bits from the bits outputted from the LDPC decoder  530 . 
     Specifically, the zero elimination unit  540  is an element corresponding to the zero padding unit  420  of the transmitting apparatus  400  and may perform an operation corresponding to the zero padding unit  420 . 
     For this, the receiving apparatus  500  may previously store information about parameters used for padding zero bits by the transmitting apparatus  400 . Therefore, the zero elimination unit  540  may remove the zero bits padded by the zero padding unit  420  from bits outputted from the LDPC decoder  530 . 
     The desegmentation unit  550  is an element corresponding to the segmentation unit  410  of the transmitting apparatus  400  and may perform an operation corresponding to the segmentation unit  410 . 
     For this, the receiving apparatus  500  may previously store information about parameters used for segmentation by the transmitting apparatus  400 . Therefore, the desegmentation unit  550  may recover bits before segmentation by combining bits outputted from the zero elimination unit  540 , that is, segments for variable-length input bits. 
     Meanwhile, the LDPC code may be decoded using the iterative decoding algorithm based on the sum-product algorithm on the bipartite graph as shown in  FIG. 2 . As mentioned above, the sum-product algorithm is a kind of a message passing algorithm. 
     Hereinafter, a message passing operation normally used in LDPC decoding will be described with reference to  FIGS. 6A and 6B . 
       FIGS. 6A and 6B  show a message passing operation at a check node and a variable node for LDPC decoding. 
       FIG. 6A  shows a check node n  600  and a plurality of variable nodes  610 ,  620 ,  630 , and  640  connected to the check node m  600 . In addition, T n′,m  denotes a message passed from the variable node n′  610  to the check node m  600 , and E n,m  denotes a message passed from the check node m  600  to the variable node n  630 . Here, a set of all variable nodes connected to the check node m  600  is defined as N(m), and a set obtained by excluding the variable node n  630  from N(m) is defined as N(m)\n. 
     In this case, a message update rule based on the sum-product algorithm may be expressed by Equation 11 
     
       
         
           
             
               
                 
                   
                     
                        
                       
                         E 
                         
                           n 
                           , 
                           m 
                         
                       
                        
                     
                     = 
                     
                       Φ 
                       ⁡ 
                       
                         [ 
                         
                           
                             ∑ 
                             
                               
                                 n 
                                 ′ 
                               
                               ∈ 
                               
                                 
                                   N 
                                   ⁡ 
                                   
                                     ( 
                                     m 
                                     ) 
                                   
                                 
                                 ⁢ 
                                 
                                   \ 
                                   ⁢ 
                                   n 
                                 
                               
                             
                           
                           ⁢ 
                           
                             Φ 
                             ⁡ 
                             
                               ( 
                               
                                  
                                 
                                   T 
                                   
                                     
                                       n 
                                       ′ 
                                     
                                     ⁢ 
                                     m 
                                   
                                 
                                  
                               
                               ) 
                             
                           
                         
                         ] 
                       
                     
                   
                   ⁢ 
                   
                     
 
                   
                   ⁢ 
                   
                     
                       Sign 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         ( 
                         
                           E 
                           
                             n 
                             , 
                             m 
                           
                         
                         ) 
                       
                     
                     = 
                     
                       
                         ∏ 
                         
                           
                             n 
                             ′ 
                           
                           ∈ 
                           
                             
                               N 
                               ⁡ 
                               
                                 ( 
                                 m 
                                 ) 
                               
                             
                             ⁢ 
                             
                               \ 
                               ⁢ 
                               n 
                             
                           
                         
                       
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         sign 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           ( 
                           
                             T 
                             
                               
                                 n 
                                 ′ 
                               
                               , 
                               m 
                             
                           
                           ) 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   11 
                 
               
             
           
         
       
     
     Here, Sign(E n,m ) denotes the sign of a message E n,m , and |E n,m | denotes the magnitude of a message E n,m . A function Φ(x) may be expressed by Equation 12 below. 
     
       
         
           
             
               
                 
                   
                     Φ 
                     ⁡ 
                     
                       ( 
                       x 
                       ) 
                     
                   
                   = 
                   
                     - 
                     
                       log 
                       ⁡ 
                       
                         ( 
                         
                           tanh 
                           ⁡ 
                           
                             ( 
                             
                               x 
                               2 
                             
                             ) 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   12 
                 
               
             
           
         
       
     
     Meanwhile,  FIG. 6B  shows a variable node x  650  and a plurality of check nodes  660 ,  670 ,  680 , and  690  connected to the variable node x  650 . In this case, E y′,x  denotes a message passed from the check node y′  660  to the variable node x  650 , and T y,x  denotes a message passed from the variable node x  650  to the check node y  680 . Here, a set of all check nodes connected to the variable node x  650  is defined as M(x), and a set obtained by excluding the check node y  680  from M(x) is defined as M(x)\y. In this case, a message update rule based on the sum-product algorithm may be expressed by Equation 13. 
     
       
         
           
             
               
                 
                   
                     T 
                     
                       y 
                       , 
                       x 
                     
                   
                   = 
                   
                     
                       E 
                       x 
                     
                     + 
                     
                       
                         ∑ 
                         
                           
                             y 
                             ′ 
                           
                           ∈ 
                           
                             
                               M 
                               ⁡ 
                               
                                 ( 
                                 x 
                                 ) 
                               
                             
                             ⁢ 
                             \ 
                             ⁢ 
                             y 
                           
                         
                       
                       ⁢ 
                       
                         E 
                         
                           
                             y 
                             ′ 
                           
                           , 
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                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   13 
                 
               
             
           
         
       
     
     Here E x  denotes the initial message value of the variable node x. 
     In case of determining the bit value of the node x, the following Equation 14 may be used. 
     
       
         
           
             
               
                 
                   
                     P 
                     x 
                   
                   = 
                   
                     
                       E 
                       x 
                     
                     + 
                     
                       
                         ∑ 
                         
                           
                             y 
                             ′ 
                           
                           ∈ 
                           
                             M 
                             ⁡ 
                             
                               ( 
                               x 
                               ) 
                             
                           
                         
                       
                       ⁢ 
                       
                         E 
                         
                           
                             y 
                             ′ 
                           
                           , 
                           x 
                         
                       
                     
                   
                 
               
               
                 
                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   14 
                 
               
             
           
         
       
     
     In this case, the encoding bit corresponding to the node x may be determined according to the P x  value. 
     Because  FIGS. 6A and 6B  show a general decoding method, a detailed description will be omitted. In addition to the method shown in  FIGS. 6A and 6B , other methods may be applied to determine the value of a message passed between the variable node and the check node. A related description is disclosed in Frank R. Kschischang, Brendan J. Frey, and Hans-Andrea Loeliger, “Factor Graphs and the Sum-Product Algorithm”, IEEE TRANSACTIONS ON INFORMATION THEORY, Vol. 47, NO. 2, FEBRUARY 2001, pp 498-519. 
       FIG. 7  is a block diagram illustrating an LDPC encoder according to an embodiment of the present disclosure. 
     K ldpc  bits may constitute K ldpc  LDPC information bits I=(i 0 , i 1 , . . . , i K     ldpc   −1) for an LDPC encoder  710 . The LDPC encoder  710  may perform systematic LDPC encoding of K ldpc  LDPC information bits and thereby generate LDPC codewords ∀=(c 0 , c 1 , . . . , C Nldpc−1 =(i 0 , i 1 , . . . , i Kldpc−1 , p 0 , p 1 , . . . , p Nldpc−Kldpc−1 ) composed of N ldpc  bits. 
     As described above in Equation 1, a codeword is determined so that a product of the LDPC codeword and the parity check matrix becomes a zero vector. 
     Referring to  FIG. 7  an encoding apparatus  700  includes an LDPC encoder  710 . The LDPC encoder  710  may generate an LDPC codeword by performing LDPC encoding for input bits, based on a parity check matrix or a corresponding exponential matrix or sequence. In this case, the LDPC encoder  710  may perform the LDPC encoding by using a parity check matrix defined differently according to a coding rate (i.e., a coding rate of an LDPC code). 
     The encoding apparatus  700  may further include a memory (not shown) for storing a coding rate of an LDPC code, a codeword length, and information about a parity check matrix. Using such information, the LDPC encoder  710  may perform the LDPC encoding. The information about a parity check matrix may include information about an exponent value of a circulant matrix when a parity matrix proposed herein is used. 
       FIG. 8  is a block diagram illustrating an LDPC decoder according to an embodiment of the present disclosure. 
     According to  FIG. 8 , a decoding apparatus  800  may include an LDPC decoder  810 . 
     The LDPC decoder  810  performs LDPC decoding for an LDPC codeword, based on a parity check matrix or a corresponding exponential matrix or sequence. 
     For example, the LDPC decoder  810  may generate information word bits by passing a log likelihood ratio (LLR) value corresponding to LDPC codeword bits through an iterative decoding algorithm and then performing LDPC decoding. 
     Here, the LLR value is a channel value corresponding to the LDPC codeword bits, and may be expressed in various ways. 
     For example, the LLR value may be represented by the logarithm of the ratio of a probability that a bit transmitted from a transmitting side through a channel is zero, to a probability that the bit is one. Alternatively, the LLR value may be a bit value itself determined according to a hard decision, or be a representative value determined according to an interval to which a probability that a bit transmitted from the transmitting side is 0 or 1 belongs. 
     In this case, the transmitting side may generate the LDPC codeword by using the LDPC encoder  710  as shown in  FIG. 7 . 
     In addition, the LDPC decoder  810  may perform the LDPC decoding by using a parity check matrix defined differently according to a coding rate (i.e., a coding rate of an LDPC code). 
     Meanwhile, the decoding apparatus  800  may further include a memory (not shown) for storing a coding rate of an LDPC code, a codeword length, and information about a parity check matrix. Using such information, the LDPC decoder  810  may perform the LDPC decoding. However, this is exemplary only, and such information may be provided by the transmitting side. 
       FIG. 9  is a block diagram illustrating a configuration of a decoding apparatus according to another embodiment of the present disclosure. 
     As described above, the LDPC decoder  810  may perform the LDPC decoding by using the iterative decoding algorithm. In this case, the LDPC decoder  810  may be configured as shown in  FIG. 9 . The iterative decoding algorithm is already known, and a detailed configuration as shown in  FIG. 9  is exemplary only. 
     As shown in  FIG. 9 , the decoding apparatus  900  includes an input processor  901 , a memory  902 , a variable node calculator  904 , a controller  906 , a check node calculator  908 , and an output processor  910 . 
     The input processor  901  stores an input value. Specifically, the input processor  901  may store an LLR value of a signal received via a radio channel. 
     Based on a parity check matrix corresponding to a block size (i.e., a codeword length) and coding rate of the received signal, the controller  906  determines the number of values inputted to the variable node calculator  904 , an address value thereof in the memory  902 , the number of values inputted to the check node calculator  908 , and an address value thereof in the memory  902 . 
     The memory  902  stores input and output data of each of the variable node calculator  904  and the check node calculator  908 . 
     The variable node calculator  904  receives data from the memory  902 , based on information about the number and address of input data received from the controller  906 , and performs a variable node operation. Then, based on information about the number and address of output data received from the controller  906 , the variable node calculator  904  stores the result of the variable node operation in the memory  902 . Also, based on data inputted from the input processor  901  and the memory  902 , the variable node calculator  904  inputs the result of the variable node operation to the output processor  910 . Here, the variable node operation is as described above with reference to  FIGS. 6A and 6B . 
     The check node calculator  908  receives data from the memory  902 , based on information about the number and address of input data received from the controller  906 , and performs a check node operation. Then, based on information about the number and address of output data received from the controller  906 , the check node calculator  908  stores the result of the check node operation in the memory  902 . Here, the check node operation is as described above with reference to  FIGS. 6A and 6B . 
     The output processor  910  performs a hard decision, based on data received from the variable node calculator  904 , to determine whether information bits of a codeword are zero or one at a transmitting side. Then, the output processor  910  outputs the result of the hard decision, and this output value of the output processor  910  becomes a finally decoded value. In this case, the hard decision may be performed based on the sum of all message values (an initial message value and all message values inputted from a check node) inputted to one variable node in  FIGS. 6A and 6B . 
       FIG. 10  is a diagram illustrating a structure of a transport block according to another embodiment of the present disclosure. 
     Referring to  FIG. 10 , &lt;Null&gt; bits may be added so that segmented lengths are equal to each other. 
     Also, &lt;Null&gt; bits may be added to match an information length of an LDPC code. 
     Described hereinbefore is the method for applying various block sizes, based on the QC-LDPC code in the communication or broadcasting systems that support LDPC codes of various lengths. Now, a method for further improving the encoding performance in the above method will be described. 
     Normally, in case of suitably converting and using a sequence with respect to various block sizes L from a single LDPC exponential matrix or sequence, like the lifting method described in Equations 9 and 10, there are many advantages in system implementation because it only needs to be implemented with one or a few sequence. However, it is very difficult to design an LDPC code having good performance for all block sizes as the number of types of block sizes to be supported increases. 
     In order to solve such a problem, an efficient design method of the QC LDPC code is proposed as follows. Proposed in this disclosure is a method for designing a parity check matrix having excellent performance in consideration of the lifting method of Equations 9 and 10 and the parity check matrix of the LDPC code or the trapping set characteristic on the Tanner graph. For convenience, although assuming the lifting based on f(x,L)=mod(x,2 └log     2     L┘ ) of Equation 10, this disclosure is not limited thereto. 
     Now, a design method of a variable-length QC LDPC code will be described in detail. 
     A first step is to find a weight distribution (i.e., a distribution of Is contained in a row or column of a matrix) of a base matrix by performing a density evolution analysis while changing a convergence rule of a density evolution and an iteration decoding number in determining a noise threshold for a decoding success of a channel code. 
     A second step is to set, when it is possible to improve the weight distribution obtained at the first step through the Hill Climbing method, the improved weight distribution as the weight distribution of a base matrix. 
     A third step is to obtain one base matrix, based on the weight distribution obtained at the second step. At this step, a method for obtaining the base matrix may be designed through various known techniques. 
     The lifting assumes f(x,L)=mod(x,2 └log     2     L┘ ) of Equation 10. That is, it is assumed that encoding and decoding are performed using the same exponential matrix for L values satisfying a range of 2 k ≤L&lt;2 k+ 1. 
     A fourth step is to maximize the girth (i.e., the smallest value of cycle lengths on the Tanner graph) in determining the exponential matrix according to the L values satisfying the above range, and then determine the exponential matrix from which trapping sets are removed maximally in a predetermined removal order. Here, the predetermined order of removing the trapping sets is as follows. 
     First priority: (4,0) trapping set 
     Second priority: (3,1) trapping set 
     Third priority: (2,2) trapping set 
     Fourth priority: (3,2) Trapping set 
     Fifth priority: (4,1) trapping set 
     Sixth priority: (4,2) trapping set 
     A fifth step is to repeat the first to fourth steps given times, and then finally select a code having the best average performance according to the L value through a computation experiment for each obtained code. Here, the average performance may be defined in various ways. For example, it is possible to find the minimum signal-to-noise ratio (SNR) for achieving a block error rate (BLER) desired in the system while varying the L value, and then finally select a code having the smallest average SNR. 
     The above-described method of designing the variable-length QC LDPC code is exemplary only and may be modified according to requirements of a channel code. For example, the third step may be changed by considering the lifting method to be applied in the system. Also, at the fourth step, the order of removing the trapping sets may be changed according to the characteristics of a channel code desired in the system. Meanwhile, the above-described design method for the variable-length QC LDPC code may be also applied to a fixed length by removing the lifting process from the third and fourth steps. 
     For example, a code may be designed on the assumption that the number of information bits is set to a small number and that, in case of a low coding rate, some of codeword bits obtained after channel encoding are repetitively transmitted in consideration of both complexity and performance. In this case, at the first step in the above-discussed method of designing the variable-length QC LDPC code, the noise threshold is determined by increasing a part of the initial value for the density evolution analysis by the number of repetitive transmissions. Also, if the coding rate or length is fixed, the lifting process may be excluded from the third and fourth steps. 
     Meanwhile, since the density evolution analysis method and the features of the trapping set are well known in the art, a detailed description is omitted herein and replaced by the following references, which are incorporated by reference in their entirety:
     Reference [RSU2001]:   T. J. Richardson, M. A. Shokrollahi, and R. L. Urbanke, “Design of capacity-approaching irregular low-density parity-check codes”, IEEE Trans. Inf. Theory, vol. 47, no. 2, pp. 619-637, February 2001.   Reference [KaBa2012]:   M. Karimi and A. H. Banihashemi, “Efficient algorithm for finding dominant trapping sets of LDPC codes”, IEEE Trans. Inf. Theory, vol. 58, no. 11, pp. 6942-6958, November 2012.   

     Embodiments of the exponential matrix or LDPC sequence of the parity check matrix designed through the above-described design method are shown in  FIGS. 11 to 15 . 
     The parity check matrix shown in  FIG. 11  is divided into two portions, which are enlarged in  FIGS. 11A and 11B , respectively. Reference numerals denoting two portions in  FIG. 11  indicate corresponding enlarged views of matrices. That is, a combination of  FIGS. 11A and 11B  is equal to one parity check matrix shown in  FIG. 11 . This is similarly applied to  FIGS. 12 to 15 . In the exponential matrices shown in  FIGS. 11 to 15 , each empty block corresponds to a zero matrix of L×L size. 
     One feature of the exponential matrix shown in  FIG. 11  is that a partial matrix consisting of 7 upper rows and 17 front columns has a degree of 2 or more. Another feature of the exponential matrix shown in  FIG. 11  is that all columns from the 18th column to the 52nd column have a degree of 1. That is, an exponential matrix having a size of 35×52 composed of rows from the 8th row to the 42nd row corresponds to a large number of single parity-check codes. As a result, the exponential matrix shown in  FIG. 11  corresponds to an LDPC code having a parity check matrix consisting of 7 row blocks and 17 column blocks with a degree of 2 or more, and parity check matrices in the form of concatenation with a plurality of single check codes consisting of 35 row blocks and 52 column blocks. 
     The parity check matrix that applies a concatenation scheme with a single parity-check code is easy of expandability, thus being advantageous in applying the incremental redundancy (IR) technique. Because the IR technique is important for supporting the hybrid automatic repeat request (HARQ), the efficient and high-performance IR technique increases the efficiency of the HARQ system. The LDPC codes based on the parity check matrices may apply the efficient and high-performance IR technique by generating and transmitting a new parity using a portion expanded from a single parity-check code. 
     In the exponential matrix of  FIG. 11 , the front 10 columns correspond to information bits. Therefore, based on the size L of the circulant permutation matrix or circulant matrix in the parity check matrix, the information bits may be determined to have a size of 10 L, In general, information bit lengths other than 10 L may be supported through a shortening technique. In addition, the codeword bit length may be 52 L depending on the L value because there are 52 rows in the exponential matrix shown in  FIG. 11 . If the codeword bits length is not 52 L or if the coding rate is not 10/52, it can be supported by shortening and/or puncturing some of the information bits. 
     Although  FIG. 11  is designed in consideration of cases where the following L values are used, this is exemplary only and is not to be construed as a limitation: 
     L={4, 5, 6, 7} {8, 9, 10, 11, 12, 13, 14, 15} {16, 18, 20, 22, 24, 26, 28, 30} {32, 36, 40, 44, 48, 52, 56, 60} {64, 72, 80, 88, 96, 104, 112, 120} {128, 144, 160, 176, 192, 208, 224, 240} {256} 
     The exponential matrices shown in  FIGS. 12 to 15  are fixed to L=16 and also fixed to a code bit number of 880. 
     In  FIG. 12 , the front 6 columns of the exponential matrix correspond to the information bits. Similarly, the front 5 columns of the exponential matrix in  FIG. 13 , the front 4 columns of the exponential matrix in  FIG. 14 , and the front 3 columns correspond to the information bits. Therefore, based on the size L=16 of the circulant permutation matrix or circulant matrix in the parity check matrix, the information bits may be determined to have a size of 96, 80, 64, or 48. In general, information bit lengths other than 96, 80, 64, or 48 may be supported through a shortening technique. If the codeword bit length is not 880, it can be supported by shortening and/or puncturing some of the information bits. 
     As another embodiment, a method for applying a plurality of exponential matrices or LDPC sequences on a given single base matrix is proposed. That is, there is one base matrix, and an exponential matrix or sequence of LDPC codes is found on the base matrix. Then, by applying the lifting to meet a block size included in each block size group from the exponential matrix or sequence, it is possible to perform variable-length LDPC encoding and decoding. In other words, with respect to exponential matrices or sequences of a plurality of different LDPC codes, the base matrices of the corresponding parity check matrices are equal to each other. Although, in this scheme, entries or numbers constituting the exponential matrix or LDPC sequence of the LDPC codes may have different values, the corresponding entries or numbers have features of coinciding in positions. As described above, the exponential matrices or LDPC sequences means exponents of the circulant permutation matrix, i.e., a kind of circulant permutation values for bits, and it is easy to know the positions of bits corresponding to the circulant permutation matrix by setting the positions of entries or numbers to be equal to each other. 
     First, a block size Z to be supported is divided into a plurality of block size groups (or sets) as shown in the following Equation 15. Note that the block size Z is a value corresponding to the size Z×Z of a circulant permutation matrix or circulant matrix in the parity check matrix of the LDPC code. 
         Z 1={12,24,48,96,192} 
         Z 2={11,22,44,88,176} 
         Z 3={10,20,40,80,160} 
         Z 4={9,18,36,72,144} 
         Z 5={8,16,32,64,128,256} 
         Z 6={15,30,60,120,240} 
         Z 7={14,28,56,112,224} 
         Z 8={13,26,52,104,208}  Equation 15
 
     The block size groups of Equation 15 have features of different granularities and the same ratio of neighboring block sizes. That is, the block sizes included in one group are in the relation of divisors or multiples. When the exponential matrix corresponding to the p-th (p=1, 2, . . . , 8) group is E P =(e i,j   (p) ), and when the exponential matrix corresponding to a Z value included in the p-th group is E P (Z)=(e i,j (Z)), it is assumed that the sequence conversion method as shown in Equation 9 is applied using f P (x,Z)=x(mod Z). That is, for example, when the block size Z is determined as Z=28, each entry e i,j (28) of the exponential matrix E 7 (28)=(e i,j (28) for Z=28 with respect to the exponential matrix E 7 =(e i,j   (7) ) corresponding to the 7th block size group that includes Z=28 may be obtained as shown in Equation 16. 
     
       
         
           
             
               
                 
                   
                     
                       e 
                       
                         i 
                         , 
                         j 
                       
                     
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                       ( 
                       28 
                       ) 
                     
                   
                   = 
                   
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                   Equation 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   16 
                 
               
             
           
         
       
     
     The conversion as shown in Equation 16 may be simply expressed as shown in Equation 17. 
         E   p ( Z )= E   p (mod  Z ), Z∈Z   p   Equation 17
 
     The base matrix and the exponential matrix (or LDPC sequence) of the LDPC code designed in consideration of the above Equations 15 to 17 are shown in  FIGS. 16 to 24 . Although it is described above that the lifting or exponentiation matrix conversion method of Equation 9, 16, or 17 is applied to the entire exponential matrix corresponding to the parity check matrix, it is also possible to partially apply to the exponential matrix. For example, a partial matrix corresponding to a parity bit of a parity check matrix usually has a special structure for efficient encoding. In this case, the encoding method or the complexity may change due to lifting. Therefore, in order to maintain the same encoding method or complexity, no lifting may be applied to a part of an exponential matrix for a partial matrix corresponding to parity in a parity check matrix, or the lifting other than a lifting scheme applied to an exponential matrix for a partial matrix corresponding to an information bit may be applied. That is, in the exponential matrix, a lifting scheme applied to a sequence corresponding to information bits and a lifting scheme applied to a sequence corresponding to a parity bit may be set differently. Also, by applying no lifting to the entire or part of a sequence corresponding to a parity bit, a fixed value may be used without a sequence conversion. 
     Embodiments of the base matrix or exponential matrix corresponding to the parity check matrix of the LDPC code designed using the QC LDPC code design method proposed based on Equations 15 to 17 are shown sequentially in  FIGS. 16 to 24 . In the base matrix and exponential matrix as shown in  FIGS. 16 to 24 , empty blocks denote portions corresponding to a zero matrix of Z×Z size. In some cases, empty blocks in the base matrix of  FIG. 16  may be represented by zero, and empty blocks in the exponential matrix of  FIGS. 17 to 24  may be represented by a specific value such as −1. The exponential matrices of the LDPC codes shown in  FIGS. 17 to 24  have the same base matrix. 
       FIGS. 16 to 24  are diagrams showing a base matrix or LDPC exponential matrix of a 42×52 size. Also, in each exponential matrix, a partial matrix formed of upper 5 rows and front 15 columns does not have a column of degree 1. That is, this means that the parity check matrix that can be generated by applying lifting to the above partial matrix does not have a column or column block having a degree of 1. 
     In addition,  FIGS. 16A and 16B  are enlarged views showing respective portions divided from a base matrix shown in  FIG. 16 . Reference numerals denoting two portions in  FIG. 16  indicate corresponding enlarged views of matrices. Therefore, a combination of  FIGS. 16A and 16B  is equal to one base matrix shown in  FIG. 16 . 
     Also,  FIGS. 17A and 17B  are enlarged views showing respective portions divided from an exponential matrix shown in  FIG. 17 . Reference numerals denoting two portions in  FIG. 17  indicate corresponding enlarged views of matrices. Therefore, a combination of  FIGS. 17A and 17B  is equal to one exponential matrix (or one LDPC sequence) shown in  FIG. 17 . This is similarly applied to  FIGS. 18 to 24 . 
     Another feature of the exponential matrices as shown in  FIGS. 17 to 24  is that all columns from the 16th column to the 52nd column have a degree of 1. That is, the base matrix or exponential matrix of a 37×52 size composed of rows from the 6th row to the 42nd row in the exponential matrices corresponds to a single parity-check code. 
     The exponential matrices shown in  FIGS. 17 to 24  correspond to the LDPC codes designed in consideration of the block size groups defined in Equation 15. However, depending on the requirements of the system, it is not necessary to support all block sizes included in the block size group. Therefore, the exponential matrices shown in  FIGS. 17 to 24  may support block sizes corresponding to the block size groups (or sets) defined in Equation 15, and further at least support block sizes corresponding to subsets of each group (or set). 
     In addition, depending on systems, the base matrix and the exponential matrix as shown in  FIGS. 16 to 24  may be used as they are, or only a part thereof may be used. For example, in the base matrix and the exponential matrix as shown in  FIGS. 16 to 24 , a new exponential matrix may be generated to apply LDPC encoding and decoding by concatenating a 7×17 partial matrix, composed of upper 7 rows and front 17 columns, with another exponential matrix of a 35×52 size. 
     Similarly, in the base matrix and the exponential matrix as shown in  FIGS. 16 to 24 , a new exponential matrix may be generated to perform LDPC encoding and decoding by concatenating a 35×52 size partial matrix composed of rows from the 8th row to the last row and columns from the 1st column to the 52nd column with another partial matrix of a 7×17 size. 
     Normally, a partial matrix formed by appropriately selecting rows and columns in the base matrix of  FIG. 16  may be applied as a new base matrix to perform the LDPC encoding and decoding. Likewise, a partial matrix formed by appropriately selecting row blocks and column blocks in the exponential matrix of  FIGS. 17 to 24  may be applied as a new exponential matrix to perform the LDPC encoding and decoding. 
     In addition, the coding rate of the LDPC codes may be adjusted by differently applying puncturing of codeword bits according to the coding rate. When parity bits corresponding to a column of degree 1 are punctured in the LDPC codes based on the base matrix or exponential matrix shown in  FIGS. 16 to 24 , the LDPC decoder may perform decoding without using the corresponding portions in the parity check matrix. Therefore, there is an advantage of reducing the decoding complexity. However, in case of considering the coding performance, there is a method for improving the performance of the LDPC codes by adjusting the puncturing order of parity bits or the transmission order of generated LDPC codeword. 
     For example, when information bits corresponding to front two columns of the base matrix or exponential matrix corresponding to  FIGS. 16 to 24  are punctured and when all parity bits having a degree of 1 and corresponding to columns from the 18th column to the 52nd column are punctured, the LDPC codeword with a coding rate of 10/15 can be transmitted. Normally, the performance may be further improved by appropriately applying rate matching after generating the LDPC codeword by using the base matrix and exponential matrix corresponding to  FIGS. 16 to 24 . Of course, it is possible to apply to the LDPC encoding and decoding by appropriately rearranging the order of columns in the base matrix or exponential matrix in consideration of the rate matching. 
     Typically, the LDPC encoding process includes determining an input bit size (or a code block size) to which LDPC encoding will be applied, determining a block size (Z) to which the LDPC encoding will be applied, determining a suitable LDPC exponential matrix or sequence, and then performing the LDPC encoding based on the determined block size (Z) and the determined exponential matrix or LDPC sequence. At this time, the LDPC exponential matrix or sequence may be applied to the LDPC encoding without conversion, or be appropriately converted according to the block size (Z). 
     Similarly, the LDPC decoding process includes determining an input bit size (or a code block size) for a transmitted LDPC codeword, determining a block size (Z) to which LDPC decoding will be applied, determining a suitable LDPC exponential matrix or sequence, and performing the LDPC decoding based on the determined block size (Z) and the determined exponential matrix or LDPC sequence. At this time, the LDPC exponential matrix or sequence may be applied to the LDPC decoding without conversion, or be appropriately converted according to the block size (Z). 
     The base matrix shown in  FIG. 16  may be expressed in various forms. For example, it is possible to express the base matrix by using a sequence as shown in the following Equations 18 to 21. 
     Equation 18 represents the positions of an entry 1 in each row of a partial matrix having a 42×52 size in the base matrix of  FIG. 16 . For example, in Equation 18, the second value 6 of the second sequence means that an entry 1 exists at the sixth column of the second row in the base matrix. In this example, the starting order of entries in a sequence and a matrix is counted from zero. 
     The expression 19 represents the positions of an entry 1 in each column of a partial matrix having a 42×52 size in the base matrix of  FIG. 16 . For example, in Equation 19, the third value 10 of the fourth sequence means that an entry 1 exists at the tenth row of the third column in the base matrix. In this example as well, the starting order of entries in a sequence and a matrix is counted from zero. 
       023456791011 
       0181112 
       01689101213 
       023457891314 
       02345671014 
       011015 
       01691016 
       134917 
       01281018 
       05619 
       0171220 
       12621 
       0471022 
       01323 
       0581024 
       041225 
       12826 
       0191427 
       031228 
       181429 
       151230 
       06931 
       141432 
       01333 
       1121434 
       05835 
       41436 
       121237 
       0338 
       171339 
       8101240 
       13741 
       6101242 
       1543 
       291244 
       11345 
       241246 
       167847 
       0448 
       12131449 
       11050 
       381251  Equation 18
 
       03471318283141 
       0347121522263638 
       034914202533 
       0246911213237 
       0341012293137 
       123814161925303741 
       02367172134 
       0245681214303240 
       01 
       12101518202427303234363941 
       2323293539 
       34171922242639 
       5 
       6 
       7 
       8 
       9 
       10 
       11 
       12 
       13 
       14 
       16 
       17 
       18 
       19 
       21 
       23 
       24 
       26 
       27 
       28 
       29 
       30 
       31 
       32 
       33 
       34 
       35 
       36 
       37 
       38 
       39 
       40 
       41  Equation 19
 
     If there is a specific rule for the position of the column of degree 1 in the base matrix of  FIG. 16 , information about the corresponding position may be omitted as shown in Equations 20 and 21. Of course, it is assumed that the transmitting apparatus and the receiving apparatus know such a specific rule. 
     If a part of the base matrix or exponential matrix has a certain rule, the base matrix or exponential matrix may be expressed more simply. For example, in case where column blocks from the 15th column block to the last column block have a diagonal structure like the base matrix or exponential matrix shown in  FIGS. 16 to 24 , the positions of entries and their exponent values are omitted on the assumption that this rule is known. 
     For example, the following Equations 20 and 21 are obtained by omitting, from the above Equations 18 and 19, the positions of an entry 1 from the 15th column block to the last column block. 
       023456791011 
       0181112 
       01689101213 
       023457891314 
       02345671014 
       0110 
       016910 
       1349 
       012810 
       056 
       01712 
       126 
       04710 
       013 
       05810 
       0412 
       128 
       01914 
       0312 
       1814 
       1512 
       069 
       1414 
       013 
       11214 
       058 
       414 
       1212 
       03 
       1713 
       81012 
       137 
       61012 
       15 
       2912 
       113 
       2412 
       1678 
       04 
       121314 
       110 
       3812  Equation 20
 
       03471318283141 
       0347121522263638 
       034914202533 
       0246911213237 
       0341012293137 
       123814161925303741 
       02367172134 
       0245681214303240 
       01 
       12101518202427303234363941 
       2323293539 
       34171922242639  Equation 21
 
     The following Equation 22 represents each entry value in each row of an exponential matrix having a 42×52 size as shown in  FIG. 17 . For example, in Equation 22, the second value 56 of the second sequence means that the value of the second entry in the second row of the exponential matrix is 56. Further considering  FIG. 16  and Equation 18, this means that the exponent of a circulant permutation matrix corresponding to the second row block and the sixth column block in a parity check matrix is 56. 
     If a part of the exponential matrix has a certain rule, the exponential matrix may be expressed more simply. For example, in case where column blocks from the 15th column block to the last column block have a diagonal structure like the exponential matrix shown in  FIGS. 17 to 24 , the exponent values thereof are omitted on the assumption that this rule is known. 
     For example, the following Equation 23 is an example in which the exponent value 0 is omitted from the 15th column block to the last column block. 
       157771879418011216315510 
       10241700 
       24104568846000 
       691114925388662600 
       18102173451121684510 
       1571011350 
       18891185981750 
       7924861070 
       150361291071060 
       110761890 
       147161511860 
       24641000 
       7418567890 
       88581810 
       294763340 
       189172850 
       73211450 
       125112120370 
       310980 
       9154580 
       1368450 
       118891470 
       981001610 
       371430 
       1311381570 
       11841870 
       1881460 
       19015120 
       1121800 
       41191760 
       139331320 
       11081270 
       1024690 
       150920 
       82146140 
       51410 
       15483480 
       612165810 
       1511320 
       63152860 
       01510 
       79144330  Equation 22
 
       157771879418011216315510 
       10241700 
       24104568846000 
       691114925388662600 
       18102173451121684510 
       157101135 
       1889118598175 
       792486107 
       15036129107106 
       11076189 
       14716151186 
       2464100 
       741856789 
       8858181 
       29476334 
       18917285 
       7321145 
       12511212037 
       31098 
       915458 
       136845 
       11889147 
       98100161 
       37143 
       131138157 
       1184187 
       188146 
       1901512 
       112180 
       4119176 
       13933132 
       1108127 
       102469 
       15092 
       8214614 
       5141 
       1548348 
       61216581 
       151132 
       6315286 
       0151 
       7914433  Equation 23
 
     As described above, the base matrix and the exponential matrix may be expressed in various ways. If permutation of column or row is applied, the same expression is possible by appropriately changing the positions of sequences or of numbers in the sequence in Equations 18 to 23. 
     Now, examples of designing the base matrix and the exponential matrix through the design method proposed herein will be described with reference to  FIGS. 25 to 33 . The base matrix and the exponential matrix of  FIGS. 25 to 33  are generated on condition that a partial matrix composed of upper 22 rows and front 32 columns and thus having a 22×32 size is already fixed. That is, when  FIGS. 25A to 25F  are given, the base matrix of  FIG. 25  is obtained as an extended form by designing  FIGS. 25G to 25I  through the design method proposed herein. 
     Similarly, the exponential matrices shown in  FIGS. 26 to 33  are obtained through an extended design similar to that of  FIG. 25 . In this way, even when a part of the base matrix or exponential matrix is previously fixed as a specific matrix or sequence, it is possible to design an extended base matrix or exponential matrix through the method proposed herein. 
     The base matrix or exponential matrix of  FIGS. 25 to 33  has a size of 42×52, and empty blocks of the exponential matrix typically correspond to a zero matrix of a Z×Z size and may be expressed by a specific value such as −1. 
     Basically, each of the base matrices and exponential matrices is designed in consideration of conditions and methods as shown in Equations 15 to 17. However, this is exemplary only and is not to be construed as a limitation. For example, it is possible to support block size (Z) values included in block size groups of Equation 15 and also support block size groups as shown in Equation 24. In addition, it is possible to use a block size value included in any subset of Equation 24 and also add a suitable value to block size groups (or sets) of Equation 15 or 24. 
         Z 1′={3,6,12,24,48,96,192,384}
 
         Z 2′={1,22,44,88,176,352}
 
         Z 3′={5,10,20,40,80,160,320}
 
         Z 4′={9,18,36,72,144,288}
 
         Z 5′={2,4,8,16,32,64,128,256}
 
         Z 6′={15,30,60,120,240}
 
         Z 7′={7,14,28,56,112,224}
 
         Z 8′={13,26,52,104,208}  Equation 24
 
       FIGS. 26 to 33  show embodiments of an exponential matrix corresponding to a parity check matrix of a QC LDPC code designed based on Equations 15 to 17 or Equation 24. The exponential matrices of the LDPC codes shown in  FIGS. 26 to 33  have the same base matrix, which is characterized as shown in  FIG. 25 . 
       FIGS. 25A to 25I  are enlarged views showing respective portions divided from the base matrix shown in  FIG. 25 . Reference numerals denoting respective portions in  FIG. 25  indicate corresponding enlarged views of matrices. Therefore, a combination of  FIGS. 25A to 25I  forms one base matrix shown in  FIG. 25 . 
       FIGS. 26A to 26I  are enlarged views showing respective portions divided from the exponential matrix shown in  FIG. 26 . Reference numerals denoting respective portions in  FIG. 26  indicate corresponding enlarged views of matrices. Therefore, a combination of  FIGS. 26A to 26I  forms one exponential matrix shown in  FIG. 26 . 
       FIGS. 27 to 33  show portions A, D, and G of  FIG. 26 . In  FIGS. 27 to 33 , the other portions B, C, E, F, H, and I are the same as those of  FIG. 26 , that is, the same as shown in  FIGS. 26B, 26C, 26E, 26F, 26H, and 26I . Therefore, by combining the A, D, and G portions shown in each of  FIGS. 27 to 33  with  FIGS. 26A, 26B, 26C, 26E, 26F, 26I, and 26I , the exponential matrix may be formed. 
     The base matrix and the exponential matrix of  FIGS. 25 to 33  are generated, based on a partial matrix composed of upper 22 rows and front 32 columns and thus having a 22×32 size. That is, even when a part of the base matrix or exponential matrix is previously fixed as a specific matrix or sequence, it is possible to design an extended base matrix or exponential matrix through the method proposed herein. 
     The base matrix and the exponential matrix shown in  FIGS. 25 to 33  may be expressed in various forms. For example, expression using a sequence as shown in the following Equation 25 is possible. Equation 24 represents the positions of an entry 1 in each row of the base matrix of  FIG. 25 . 
       0123691011 
       0345678991112 
       01348101213 
       124567891013 
       011114 
       01571115 
       05791116 
       157111317 
       011218 
       18101119 
       016720 
       0791321 
       131122 
       0181323 
       16111324 
       0101125 
       19111226 
       15111227 
       06728 
       011029 
       141130 
       081331 
       1232 
       03533 
       12934 
       0535 
       27121336 
       0637 
       12538 
       0439 
       257940 
       11341 
       257842 
       11243 
       0344 
       25745 
       11046 
       25747 
       081248 
       25749 
       0450 
       2121351  Equation 25
 
     Equation 26 shows the positions of an entry 1 in each column of the base matrix of  FIG. 25 . 
       01245681011131518192123252729343840 
       023457891012131416171920222428313336 
       0322242628303235373941 
       012122334 
       123202940 
       13567172325283032353739 
       01310141827 
       13567101118263032353739 
       123913213238 
       013611162430 
       0239151936 
       0145679121415161720 
       128161726333841 
       23711131421263141 
       4 
       5 
       6 
       7 
       8 
       9 
       10 
       11 
       12 
       13 
       14 
       15 
       16 
       17 
       18 
       19 
       20 
       21 
       22 
       23 
       24 
       25 
       26 
       27 
       28 
       29 
       30 
       31 
       32 
       33 
       34 
       35 
       36 
       37 
       38 
       39 
       40 
       41  Equation 26
 
     If a certain rule can be found for a part of the base matrix, the base matrix may be expressed more simply. For example, in case where columns from the 15th column to the last column have a diagonal structure like the base matrix shown in  FIG. 25 , the positions of entries or their exponent values may be omitted on the assumption that the transmitting and receiving apparatuses know this rule. 
     For reference, by appropriately shortening a part of information bits and puncturing a part of codeword bits with respect to the LDPC code that can be generated based on the base matrix or exponential matrix shown in  FIGS. 25 to 33 , it is possible to support the LDPC encoding and decoding with various coding rates and various lengths. For example, various information word lengths (or code block lengths) and various coding rates can be supported by applying shortening to a part of information bits in the base matrix and exponential matrix shown in  FIGS. 25 to 33 , then puncturing information bits corresponding to the first two columns, and puncturing a part of parity. 
     In addition, when a variable information word length or a variable coding rate is supported using the shortening or zero-padding of the LDPC code, the code performance may be improved according to the order or method of shortening. If the shortening order is already set, the encoding performance may be improved by rearranging the entire or a part of the given base matrix. Also, the performance may be improved by appropriately determining a block size or a size of a column block, to which the shortening is to be applied, with respect to a specific information word length (or code block length). 
     For example, when front ten columns in  FIGS. 25 to 33  correspond to information word bits (or code blocks), and when the number of columns to be used for LDPC encoding is K b , better performance can be obtained by applying an appropriate rule for shortening as given below and thereby determining the values of K b  and a block size (Z). 
     if(CBS&gt;640)
         K b =10;       

     elseif(CBS&gt;=576)
         K b =9       

     elseif(CBS&gt;=200)
         K b =8;       

     else
         if(CBS is member of [48,96,176,184,192])   K b =7;   else   K b =6;   end       

     end 
     In the above, CBS denotes an information word length or a code block length. When the value of K b  is determined in the above, the block size (Z) value can be determined as the minimum value that satisfies Z×K b &gt;=CBS. For example, K b  and the block size are determined as shown in Equation 27. 
         CBS= 40=&gt; K   b =6=&gt; Z= 7 
         CBS= 48=&gt; K   b =7=&gt; Z= 7 
         CBS= 56=&gt; K   b =6=&gt; Z= 10 
         CBS= 64=&gt; K   b =6=&gt; Z= 11 
         CBS= 80=&gt; K   b =6=&gt; Z= 14 
         CBS= 200=&gt; K   b =8=&gt; Z= 26 
         CBS= 640=&gt; K   b =9=&gt; Z= 72 
         CBS= 1024=&gt; K   b =10=&gt; Z= 104  Equation 27
 
     Depending on systems, the base matrix or the exponential matrix as shown in  FIGS. 25 to 33  may be used as it is, or only a part thereof may be used. For example, in the base matrix or the exponential matrix as shown in  FIGS. 25 to 33 , a new exponential matrix or exponential matrix may be generated by concatenating with a 22×32 LDPC base matrix or exponential matrix other than a 22×32 partial matrix composed of upper 22 rows and front 32 columns, and be used for LDPC encoding and decoding methods and apparatuses. For example, using 20 matrices as shown in Equation 28 from Equation 25, a new base matrix may be generated by concatenating with another base matrix. 
       1232 
       03533 
       12934 
       0535 
       27121336 
       0637 
       12538 
       0439 
       257940 
       11341 
       257842 
       11243 
       0344 
       25745 
       11046 
       25747 
       081248 
       25749 
       0450 
       2121351  Equation 28
 
     As another example, by concatenating upper 32 sequences, as shown in Equation 29, from Equation 25 with other 10 LDPC base matrices or LDPC sequences, a new base matrix may be generated and applied to the LDPC encoding and decoding. For reference, as shown in Equation 29, the partial matrix of the base matrix defined by selecting upper 32 sequences from Equation 25 is the same as the partial matrix of the base matrix defined by selecting upper 32 rows in  FIG. 25 . 
     In case of defining a new base matrix by using a sequence corresponding to a partial matrix (or part of sequence) of an LDPC base matrix (or sequence) corresponding to  FIG. 25  or Equation 25 as shown in Equations 28 and 29, it is also possible to generate a new exponential matrix by using a portion corresponding to the partial matrix (or part of sequence) in an LDPC exponential matrix corresponding to  FIGS. 26 to 33 . 
       0123691011 
       034567891112 
       01348101213 
       124567891013 
       011114 
       01571115 
       05791116 
       157111317 
       011218 
       18101119 
       016720 
       0791321 
       131122 
       0181323 
       16111324 
       0101125 
       19111226 
       15111227 
       06728 
       011029 
       141130 
       081331 
       1232 
       03533 
       12934 
       0535 
       27121336 
       0637 
       12538 
       0439 
       257940 
       11341  Equation 29
 
     In general, a partial matrix formed by appropriately selecting rows and columns in the base matrix and exponential matrix of  FIGS. 25 to 33  may be applied as a new base matrix and exponential matrix and used for a method and apparatus of LDPC encoding and decoding. 
     While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be taken in conjunction with the present disclosure. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the subject matter and scope of the present disclosure. 
     Although the present disclosure has been described with various embodiments, various changes and modifications may be suggested to one skilled in the art. It is intended that the present disclosure encompass such changes and modifications as fall within the scope of the appended claims.