Patent Publication Number: US-9842526-B2

Title: Flat panel display and driving method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     Korean Patent Application No. 10-2013-0119676, filed on Oct. 8, 2013, and entitled, “FLAT PANEL DISPLAY AND DRIVING METHOD THEREOF,” is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Field 
     One or more embodiments described herein relate to a display device. 
     2. Description of the Related Art 
     A variety of flat panel displays have been developed. Examples include liquid crystal displays, organic light emitting displays, and plasma display panels. These panels are of interest because of their size, weight, and low power consumption. 
     SUMMARY 
     In accordance with one embodiment, a flat panel display including a plurality of pixels respectively positioned in areas divided by scan lines and data lines; and a signal generator configured to generate data signals supplied to respective data lines via an output terminal or a control signal for controlling switches, the signal generator including a first voltage supply unit configured to supply, to the output terminal, a voltage from one of a plurality of first voltage sources; a voltage stabilizing unit configured to raise or drop the voltage supplied to the output terminal; and a second voltage supply unit configured to supply, to the output terminal, a voltage from one of a plurality of second voltage sources, after the voltage of the output terminal is raised or dropped. 
     The voltage stabilizing unit may raise or drop the voltage supplied to the output terminal based on a voltage of one of the first voltage sources. 
     The display may include a first switch and a second switch coupled to each data line, wherein the first and second switches are to be alternately turned on and off based on the control signal. The first switch may be a PMOS transistor and the second switch may be an NMOS transistor. 
     The first voltage supply unit may include a first transistor coupled between a first high voltage source and the output terminal; and a second transistor coupled between a first low voltage source and the output terminal, the second transistor having a turn-on period which does not overlap a turn-on period of the first transistor. 
     The second voltage supply unit may include a third transistor coupled between a second high voltage source and the output terminal, the third transistor to be turned on after the first transistor is changed from a turned on state to a turned off state; and a fourth transistor coupled between a second low voltage source and the output terminal, the fourth transistor to be turned on after the second transistor is changed from the turned on state to the turned off state. 
     The second high voltage source may be set to a voltage lower than that of the first high voltage source. The second low voltage source may be set to a voltage higher than that of the first low voltage source. 
     The voltage stabilizing unit may include a first resistor and a fifth transistor coupled in series between the first high voltage source and the output terminal; and a second resistor and a sixth transistor coupled in series between the first low voltage source and the output terminal. The sixth transistor may turn on during a partial period before the third transistor is turned on, after the first transistor is turned off. The sixth transistor may turn on during a period shorter than a period during which the first transistor is turned on. 
     The fifth transistor may turn on during a partial period before the fourth transistor is turned on, after the second transistor is turned off. The fifth transistor may turn on during a period shorter than a period during which the second transistor is turned on. 
     In accordance with another embodiment, a method of driving a flat panel display includes supplying a first high voltage or a first low voltage as a pre-emphasis voltage to an output terminal, to generate a data signal or a control signal for controlling switches; raising or dropping a voltage of the output terminal based on the first high voltage or first low voltage; and supplying a second high voltage or second low voltage to the output terminal. 
     Dropping the voltage may include dropping the voltage of the output terminal based on the first low voltage after the first high voltage is supplied. The second high voltage may be supplied to the output terminal after the voltage of the output terminal drops and second high voltage may be set to a voltage lower than the first high voltage. 
     Raising the voltage of the output terminal may include raising the voltage of the output terminal based on the first high voltage after the first low voltage is supplied. The second low voltage may be supplied to the output terminal after the voltage of the output terminal is raised, and the second low voltage may be set to a voltage higher than the first low voltage. 
     In accordance with another embodiment, a controller for a display device includes a first voltage supply to supply to a first voltage to an output terminal coupled to a data line of the display device; a voltage stabilizer to change the first voltage at the output terminal to a second voltage; and a second voltage supply to supply a third voltage which to the output terminal, after the output terminal voltage is changed to the second voltage, wherein the first voltage is based on a first voltage source and the third voltage is based on a second voltage source different from the first voltage source. The second voltage may be substantially equal to the third voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will become apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG. 1  illustrates an embodiment of an organic light emitting display; 
         FIG. 2  illustrates an embodiment of a signal generator; 
         FIG. 3  illustrates an embodiment of an operating process for the signal generator; and 
         FIG. 4  is a diagram illustrating an embodiment of a liquid crystal display. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments are described more fully hereinafter with reference to the accompanying drawings; however, they may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey exemplary implementations to those skilled in the art. 
     In the drawing figures, the dimensions of layers and regions may be exaggerated for clarity of illustration. It will also be understood that when a layer or element is referred to as being “on” another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being “under” another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being “between” two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Like reference numerals refer to like elements throughout. 
       FIG. 1  illustrates an embodiment of an organic light emitting display which includes a scan driver  110 , a data driver  120 , a pixel unit  130 , and a timing controller  150 . The scan driver  110  drives scan lines S 1  to Sn. The data driver  120  drives data lines D 1  to Dm. The pixel unit  130  includes pixels  144  respectively positioned in areas defined by scan lines S 1  to Sn and data lines D 1  to Dm. The timing controller  150  controls the scan driver  110  and data driver  120 . 
     The timing controller  150  controls the scan driver  110  and data driver  120 . The timing controller  150  realigns data supplied from an external source and supplies the realigned data to data driver  120 . 
     The scan driver  110  supplies a scan signal to scan lines S 1  to Sn. For example, scan driver  110  may progressively supply a scan signal to scan lines S 1  to Sn. When the scan signal is progressively supplied to scan lines S 1  to Sn, pixels  144  are sequentially selected for each horizontal line. 
     The data driver  120  supplies data signals to respective ones of data lines D 1  to Dm. The data driver  120  supplies a first data signal to cause pixel  144  to emit light, or a second data signal to cause the pixel  144  to not emit light, in accordance with a digital driving method. For example, data driver  120  supplies data signals corresponding to emission or non-emission states of pixel  144 . 
     The data driver  120  includes a signal generator  160  for each of a plurality of channels. The signal generator  160  supplies a pre-emphasis voltage, and supplies a voltage lower or higher than the pre-emphasis voltage. For example, signal generator  160  supplies a pre-emphasis voltage, and supplies a voltage lower or higher than the pre-emphasis voltage, to thereby stabilize voltages of data lines D 1  to Dm. 
     Subsequently, signal generator  140  supplies, to data lines D 1  to Dm, a voltage corresponding to the first or second data signal. In this case, the voltage of a desired data signal may be supplied to pixels  144  by the pre-emphasis voltage. Accordingly, it is possible to improve display quality. 
     The pixel unit  130  receives first and second power sources ELVDD and ELVSS from one or more external sources, and supplies the first and second power sources ELVDD and ELVSS to each pixel  144 . Each pixel  144  emits light at a gray scale value based on current supplied to an organic light emitting diode (emission), based on a data signal. Each pixel  144  does not emit light when current is not supplied to the organic light emitting diode (non-emission), corresponding to a data signal. Additionally, pixel  144  may be implemented by various types of circuits corresponding to the digital driving method. 
       FIG. 2  illustrates an embodiment of a signal generator  160  which includes a first voltage supply unit  164  to supply voltage of a first voltage source VDD 1  or VSS 1  as a pre-emphasis voltage, a second voltage supply unit  166  to supply voltage of a second voltage source VDD 2  or VSS 2  higher or lower than the pre-emphasis voltage, and a voltage stabilizing unit  168  to raise or drop a voltage of an output terminal  162  after the pre-emphasis voltage is supplied. 
     The first voltage supply unit  164  supplies, as the pre-emphasis voltage, the voltage of a first high voltage source VDD 1  or the voltage of a first low voltage source VSS 1 . The first voltage supply unit  164  includes a first transistor M 1  coupled between first high voltage source VDD 1  and output terminal  162 , and a second transistor M 2  coupled between first low voltage source VSS 1  and output terminal  162 . 
     The first high voltage source VDD 1  may be set to a high voltage used as the pre-emphasis voltage, e.g., a positive voltage. The first low voltage source VSS 1  may be set to a low voltage used as the pre-emphasis voltage, e.g., a negative voltage. 
     The first transistor M 1  is turned on based on a first enable signal en 1 . When first transistor M 1  turns on, the voltage of the first high voltage source VDD 1  is supplied to output terminal  162 . The first transistor M 1  that supplies the voltage of the first high voltage source VDD 1  is a PMOS transistor, which stably turns on when the first enable signal en 1  is set to a low voltage. 
     The second transistor M 2  is turned on based on a second enable signal en 2 . When second transistor M 2  turns on, the voltage of first low voltage source VSS 1  is supplied to output terminal  162 . The second transistor M 2  supplying the voltage of the first low voltage source VSS 1  is an NMOS transistor, which stably turns on when second enable signal en 2  is set to a high voltage. 
     The second voltage supply unit  166  supplies the voltage of a second high voltage source VDD 2  or the voltage of a second low voltage source VSS 2 . The second voltage supply unit  166  includes a third transistor M 3  coupled between second high voltage source VDD 2  and output terminal  162 , and a fourth transistor M 4  coupled between second low voltage source VSS 2  and output terminal  162 . 
     The second high voltage source VDD 2  is set to a voltage lower than that of the first high voltage source VDD 1 . For example, the voltage of the second high voltage source VDD 2  is supplied to output terminal  162  after the voltage of first high voltage source VDD 1  is supplied as the pre-emphasis voltage. Here, the voltage of the second high voltage source VDD 2  is supplied as the second data signal (or first data signal) to a data line (any one of D 1  to Dm). 
     The second low voltage source VSS 2  is set to a voltage higher than that of the first low voltage source VSS 1 . For example, the voltage of the second low voltage source VSS 2  is supplied to output terminal  162  after the voltage of the first low voltage source VSS 1  is supplied as the pre-emphasis voltage. Here, the voltage of the second low voltage source VSS 2  is supplied as the first data signal (or second data signal) to a data line (any one of D 1  to Dm). 
     The third transistor M 3  is turned on based on a third enable signal en 3 . When third transistor M 3  turns on, the voltage of the second high voltage source VDD 2  is supplied to output terminal  162 . The third transistor M 3  is a PMOS transistor, which stably turns when the third enable signal en 3  is set to a low voltage. 
     The fourth transistor M 4  is turned on based on a fourth enable signal en 4 . When the fourth transistor M 4  turns on, the voltage of the second low voltage source VSS 2  is supplied to output terminal  162 . The fourth transistor M 4  is an NMOS transistor, which stably turns when the fourth enable signal en 4  is set to a high voltage. 
     The voltage stabilizing unit  168  raises or drops the voltage of output terminal  162 , before the voltage is supplied from the second voltage supply unit  16  to output terminal  162  and after the voltage is supplied from first voltage supply unit  164  to output terminal  162 . The voltage stabilizing unit  168  may raise or drop the voltage of output terminal  162  using first high voltage source VDD 1  or first low voltage source VSS 1 . 
     In one embodiment, voltage stabilizing unit  168  includes a first resistor R 1  and a fifth transistor M 5  coupled in series between the first high voltage source VDD 1  and output terminal  162 . The voltage stabilizing unit  168  further includes second resistor R 2  and a sixth transistor M 6  coupled in series between the first low voltage source VSS 1  and output terminal  162 . 
     The fifth transistor M 5  is turned on based on a fifth enable signal en 5 . When fifth transistor M 5  turns on, the voltage of the first high voltage source VDD 1  is supplied to output terminal  162 . The first resistor R 1  is coupled between the first high voltage source VDD 1  and fifth transistor M 5 , and serves to limit the amount of current flowing from first high voltage source VDD 1  to output terminal  152 . The fifth transistor M 5  is a PMOS transistor, and the fifth enable signal en 5  is set to a low voltage to turn on this transistor. 
     The sixth transistor M 6  is turned on based on a sixth enable signal en 6 . When sixth transistor M 6  is turned on, the voltage of the first low voltage source VSS 1  is supplied to output terminal  162 . The second resistor R 2  is coupled between the first low voltage source VSS 1  and sixth transistor M 6 , and serves to limit the amount of current flowing from output terminal  162  to first low voltage source VSS 1 . The sixth transistor M 6  is an NMOS transistor, and the sixth enable signal en 6  is set to a high voltage to turn on the sixth transistor M 6 . 
       FIG. 3  illustrating a embodiment of a process for operating the signal generator in  FIG. 2 . Referring to  FIG. 3 , the first enable signal en 1  is first supplied to turn on first transistor M 1 . When first transistor M 1  turns on, the voltage of the first high voltage source VDD 1  is supplied as a pre-emphasis voltage to the output terminal  162 . 
     After the voltage of first high voltage source VDD 1  is supplied to output terminal  162 , the sixth enable signal en 6  is supplied to turn on sixth transistor M 6 . When sixth transistor M 6  turns on, the voltage of first low voltage source VSS 1  is supplied to output terminal  162  via second resistor R 2 . In this case, current flows from output terminal  162  to first low voltage source VSS 1 . Thus, the amount of current flowing from output terminal  162  to first low voltage source VSS is limited by the second resistor R 2 . Accordingly, the voltage of output terminal  162  gradually drops from the voltage of the first high voltage source VDD 1 . 
     In the present embodiment, the turn-on period of sixth transistor M 6  is set to be shorter than that of first transistor M 1 . For example, the turn-on period of sixth transistor M 6  may be experimentally determined, so that the voltage of the output terminal  162  drops approximately to the voltage of second high voltage source VDD 2 . 
     After the voltage of output terminal  162  drops from the voltage of the first high voltage source VDD 1  to a predetermined voltage (e.g., the voltage of second high voltage source VDD 2 ), the third enable signal en 3  is supplied to turn on third transistor M 3 . When third transistor M 3  turns on, the voltage of the second high voltage source VDD 2  is supplied to output terminal  162 . 
     In the present embodiment, the voltage of the first high voltage source VDD 1  is supplied as a pre-emphasis voltage to output terminal  162 . As a result, a desired voltage of the second data signal (or first data signal) may be supplied to pixel  144 , via a data line (any one of D 1  to Dm), regardless of its forming position. 
     In the present embodiment, the voltage of output terminal  162  drops using the voltage of first low voltage source VSS 1 , after the voltage of first high voltage source VDD 1  is supplied. The voltage of second high voltage source VDD 2  is supplied after the voltage of output terminal  162  drops. In this case, the voltage of first high voltage source VDD 1  is not supplied to second high voltage source VDD 2  when third transistor M 3  is turned on. Accordingly, it is possible to ensure the driving stability. 
     The aforementioned description corresponds to the case where the second data signal (or first data signal) is supplied to data line D 1  to Dm. In a case where the first data signal (or second data signal) is supplied to data line D 1  to Dm, signal generator  160  may be driven in the following manner. 
     First, the second enable signal en 2  is supplied so that the second transistor M 2  is turned on. If the second transistor M 2  is turned on, the voltage of the first low voltage source VSS 1  is supplied as the pre-emphasis voltage to the output terminal  162 . 
     After the voltage of first low voltage source VSS 1  is supplied to output terminal  162 , the fifth enable signal en 5  is supplied to turn on fifth transistor M 5 . When the fifth transistor M 5  turns on, the voltage of the first high voltage source VDD 1  is supplied to output terminal  162  via first resistor R 1 . In this case, current flows from first high voltage source VDD 1  to output terminal  162 . Thus, the amount of current flowing from first high voltage source VDD 1  to output terminal  162  is limited. Accordingly, the voltage of output terminal  162  gradually rises from the voltage of the first low voltage source VSS 1 . 
     The turn-on period of the fifth transistor M 5  may be set shorter than that of the second transistor M 2 . For example, the turn-on period of fifth transistor M 5  may be experimentally determined, so that the voltage of output terminal  162  is raised approximately to the voltage of the second low voltage source VSS 2 . 
     After the voltage of output terminal  162  is raised from the voltage of the first low voltage source VSS 1  to a predetermined voltage (e.g., the voltage of second low voltage source VSS 2 ), the fourth enable signal en 4  is supplied to turn on fourth transistor M 4 . When fourth transistor M 4  turns on, the voltage of second low voltage source VSS 2  is supplied to output terminal  162 . 
     In the present embodiment, the voltage of the first low voltage source VSS 1  is supplied as the pre-emphasis voltage to output terminal  162 . As a result, a desired voltage of the first data signal (or second data signal) may be supplied to pixel  144 , via a data line (any one of D 1  to Dm), regardless of its forming position. In the present embodiment, the voltage of output terminal  162  is raised after the voltage of the first low voltage source VSS 1  is supplied. The voltage of the second low voltage source VSS 2  is supplied after the voltage of output terminal  162  is raised. In this case, the voltage of first low voltage source VSS 1  is not supplied to second low voltage source VSS 2  when fourth transistor M 4  turns on. Accordingly, it is possible to ensure the stability of driving. 
     In this embodiment, signal generator  160  is used in an organic light emitting display. In another embodiment, signal generator  160  may be included in a liquid crystal display driven by a digital driving method. In addition, the signal of signal generator  160  may be used as a control signal for one or more switches in the panel. 
       FIG. 4  illustrates an embodiment of a liquid crystal display which includes a data driver  120 ′, a liquid crystal panel  130 ′, and a timing controller  150 ′. The liquid crystal panel  130 ′ includes pixels in areas divided by data lines D 1  to Dm and scan lines S 1  to Sn. The data driver  120 ′ drives data lines D 1  to Dm. A scan driver  110 ′ drives scan lines S 1  to Sn. The timing controller  150  controls scan driver  110 ′ and data driver  120 ′. 
     The liquid crystal display further includes first and second switches SW 1  and SW 2  coupled to each data line D 1  to Dm, and a signal generator  160  to supply a control signal to the first and second switches SW 1  and SW 2 . 
     Although signal generator  160  and data driver  120 ′ are separated from each other in  FIG. 4 , signal generator  160  may be positioned in data driver  120 ′ or timing controller  150 ′ in another embodiment. Also, a plurality of first switches SW 1  and a plurality of second switches SW 2  may be coupled to each data line D 1  to Dm to be driven in the form of a demultiplexer (DEMUX). However, in the present embodiment, for convenience of illustration, one first switch SW 1  and one second switch SW are illustrated to be coupled to each data line D 1  to Dm. 
     The scan driver  110 ′ supplies a scan signal to scan lines S 1  to Sn. For example, scan driver  110 ′ progressively supplies a scan signal to scan lines S 1  to Sn. If the scan signal is progressively supplied to scan lines S 1  to Sn, thin film transistors  140  in respective pixels turn on in each horizontal line. 
     The data driver  120 ′ generates data signals for input into data lines D 1  to Dm for each horizontal period in which the scan signal is supplied. In this case, data signals supplied to data lines D 1  to Dm are supplied to pixels via first and second switches SW 1  and SW 2 . 
     The liquid crystal panel  130 ′ includes pixels respectively positioned at intersection portions of scan lines S 1  to Sn and data lines D 1  to Dm. 
     Each pixel includes a thin film transistor  140  and a pixel electrode  142 . The thin film transistor  140  supplies the data signal from a data line (any one of D 1  to Dm) to the pixel electrode  142 , in response to the scan signal from a scan line (any one of S 1  to Sn). The pixel electrode  142  drives liquid crystals between the pixel electrode  142  and a common electrode in response to a data signal, thereby controlling the transmittance of light. 
     The timing controller  150 ′ controls the scan driver  110 ′ and data driver  120 ′. 
     The first and second switches SW 1  and SW 2  are formed in liquid crystal panel  130 ′ and are coupled to each of the data lines D 1  to Dm. That is, the first and second switches SW 1  and SW 2  are coupled in parallel to each of the data lines D 1  to Dm between the pixels. The first and second switches SW 1  and SW 2  supply data signals from data lines D 1  to Dm to the pixels, while being alternately turned on and off based on control signal CS. For example, first and second switches SW 1  and SW 2  may supply a positive or negative data signal to the pixels, while being alternately turned on and off for each horizontal period, corresponding to an inversion driving method. 
     The first and second switches SW 1  and SW 2  may be by different conductive-type transistors so that they may be alternately turned on and off based on the control signal. For example, first switch SW 1  may be a PMOS transistor and second switch SW 2  may be an NMOS transistor. 
     The signal generator  160  generates control signal CS, and supplies the control signal CS to first and second switches SW 1  and SW 2 . The signal generator  160  supplies a pre-emphasis voltage during an initial period of the horizontal period, and supplies a voltage higher or lower than the pre-emphasis voltage so that the first or second switch SW 1  or SW 2  stably turns on. The configuration and operating process of signal generator  160  are identical to those in  FIGS. 2 and 3 . However, in signal generator  160 , first switch SW 1  may be turned on when a second low voltage VSS 2  is supplied as the control signal CS, and the second switch SW 2  may be turned on when a second high voltage VDD 2  is supplied. 
     By way of summation and review, a flat panel display generally includes pixels respectively positioned at intersection portions of scan lines and data lines, a scan driver to drive the scan lines, and a data driver to drive the data lines. 
     The scan driver selects pixels for each line, while progressively supplying a scan signal to the scan lines. The data driver supplies data signals to the data lines synchronized with the scan signal. In this case, the pixels selected by the scan signal charge a voltage corresponding ones of the data signals. The pixels display an image with a predetermined luminance based on the data signals. 
     The flat panel display supplies data signals or controls switches in a panel using a pre-emphasis voltage. However, when a voltage lower or higher than the pre-emphasis voltage is supplied after the pre-emphasis voltage is supplied, a power unit (DC-DC converter) is not normally driven. For example, over-voltage protection of a power unit may be operated by a sudden change in voltage. As a result, a desired voltage may not be generated in the power unit. 
     In accordance with one or more of the aforementioned embodiments, after a voltage of the first high voltage source or first low voltage source is supplied as a pre-emphasis voltage, the voltage of the output terminal is raised or dropped based on the voltage of the first low voltage source or the voltage of the first high voltage source. Subsequently, the voltage of the second high voltage source or the voltage of the second low voltage source is supplied to the output terminal. As a result, a power unit may be prevented from being erroneously operated by a high (or low) voltage, thereby ensuring driving stability. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.