Patent Publication Number: US-8987821-B2

Title: LDMOS with accumulation enhancement implant

Description:
PRIORITY CLAIM 
     This Application is a divisional of U.S. patent application Ser. No. 13/431,629, filed Mar. 27, 2012, to Hideaki Tsuchiko entitled “LDMOS WITH ACCUMULATION ENHANCEMENT IMPLANT”, the entire disclosures of which are incorporated by reference herein. 
    
    
     FIELD OF THE INVENTION 
     Embodiments of the present invention relate to high voltage semiconductor devices and the manufacturing process thereof and, in particular, to lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors with accumulation enhancement implant and thick accumulation oxide. 
     BACKGROUND OF THE INVENTIONS 
     Lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are commonly used in high-voltage applications (20 to 500 volts) because of their high breakdown voltage characteristics and compatibility with low voltage CMOS technology. In general, an N-type LDMOS transistor includes a polysilicon gate, an N+ source region formed in a P-type body region, and an N+ drain region. The N+ drain region is separated from the channel formed in the body region under the polysilicon gate by an N drift region. It is well known that by increasing the length of the N-drift region, the breakdown voltage of the LDMOS transistor can be accordingly increased. 
       FIG. 1  is a cross-sectional diagram showing an existing LDMOS device  100  provided as a high voltage N-channel Lateral DMOS (LDMOS). It is noted that this type of device can be formed in an N-type epitaxial layer, a P-type epitaxial layer or a P-type substrate. The N-channel LDMOS device  100  formed in either an epitaxial layer or a P-type substrate  110  includes a N+ source region  120  disposed in a P-well body region  112  and a N+ drain contact pickup region  122  disposed in N-drift drain region  114 . A P+ body pickup region  124  is also formed on a top portion of the P-well body region  112  laterally adjacent to the source region  120 . A field oxide (FOX)  116  is formed on a top portion of the N-drift drain region  114  right next to the drain contact pickup region  122  and an insulated gate  118  disposed on top of the P-well body region  112  and the N-drift drain region  114  extends from overlapping a portion of the source region  120  to overlapping a portion of the field oxide  116 . The insulated gate  118  is electrical insulated from the substrate  110  by a thin gate oxide (not shown). An active channel  126  is formed in the P-well body region underneath the gate  118  from the source region  120  to the P-N junction between the P-well body region  112  and the N-drift drain region  114  and an accumulation region  128  is region formed in the N-drift drain region  114  underneath the gate  118  from the PN junction to the first end of the field oxide  116  closer to the PN junction. 
     The existing N channel LDMOS with butting P-well body region and lightly doped N-drift drain region as described above may have poor quasi-saturation, poor hot carrier injection (HCl) performance and/or high R dsON . 
     It is within this context that embodiments of the present invention arise. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other objects and advantages of the invention will become apparent upon reading the following detailed description and upon reference to the accompanying drawings in which: 
         FIG. 1  is a cross-sectional diagram illustrating a conventional N-channel LDMOS device. 
         FIG. 2  is a cross-sectional diagram illustrating an N-channel LDMOS device according to an embodiment of the present invention. 
         FIG. 3  is a cross-sectional diagram illustrating an N-channel LDMOS device without the field oxide and with accumulation enhancement implant of the present invention. 
     
    
    
     DESCRIPTION OF THE SPECIFIC EMBODIMENTS 
     In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the figure(s) being described. Because components of embodiments of the present invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes, including changes in the order of process steps, may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. 
     According to embodiments of the present invention, quasi-saturation behavior, hot carrier injection (HCl) performance and the R dsON  may improve in LDMOS devices by implantation of an enhancement portion into the accumulation region and a long bird&#39;s beak of Local Oxidation of Silicon (LOCOS) grown in the same region. The enhancement portion has the same carrier type as the epitaxial layer.  FIG. 2  is a cross-sectional schematic diagram of an N-channel LDMOS  200  according to an embodiment of the present invention. The N-channel LDMOS device  200  formed in a P-type substrate  110  includes a N+ source region  120  disposed in a P-well body region  112  and an N+ drain contact pickup region  122  disposed in N-drift drain region  114 . A P+ body pickup region  124  is also formed on a top portion of the P-well body region  112  adjacent to the source region  120 . A field insulator, e.g., a field oxide (FOX),  116  is formed on a top portion of the N-drift drain region  114  right next to the drain contact pickup region  122  and an insulated gate electrode  118  disposed on top of the P-well body region  112  and the N-drift drain region  114  extends from overlapping a portion of the source region  120  to overlapping a portion of the field oxide  116 . The insulated gate  118  may be electrically insulated from the substrate  110  by a thin gate oxide (not shown). A P-type active channel  126  is formed in the P-well body region underneath the gate  118  from the source region  120  to the P-N junction between the P-well body region  112  and the N-drift drain region  114  and an N-type accumulation region  128  is formed in the N-drift drain region  114  underneath the gate  118  from the P-N junction to a first end of the field oxide  116  close to the P-N junction. 
     In embodiments of the present invention, additional dopants of the same conductivity type as the accumulation region may be implanted into a portion of the accumulation region to form an enhancement implant region. By way of example, and not by way of limitation, for an N-channel LDMOS, N-type dopants may be implanted at the top portion in the accumulation region  128  forming an enhancement implant region  130 . The N-type implant region  130  increases the net carrier concentration in the accumulation region and reduces the resistivity in accumulation region. Thus, the quasi-saturation at high gate bias and the high R dsON  are improved. It is noted that for a P-type LDMOS device, P-type dopants may be used to form the enhancement region  130 . 
     There is a gap g between the implant region  130  and the edge of P-well body region  112  so that the threshold voltage of the FET region is not reduced. Furthermore, the implant region  130  increases potential at a bird&#39;s beak portion  132  of the field oxide  116  when high bias is applied to the drain. Therefore, a long bird&#39;s beak  132  may be grown under the gate  118  to increase the breakdown voltage between the gate and the gate oxide. The bird&#39;s beak portion  132  of the field oxide  116  is generally thinner than the main portion  116  of the field oxide. 
     EXPERIMENTS 
     Experiments using process and device simulation have been carried out, which simulate implantation of arsenic into an accumulation region with different accumulation lengths (L acc ) cell pitch after the field oxidation is formed as shown in Table I below and in corresponding plots in the graph depicted in  FIG. 3 . The doping concentration of arsenic in these simulations was either zero or in the range of 10 12  cm −2  for each accumulation length. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE I 
               
               
                   
                   
               
               
                   
                 L acc   
                 Acc Imp 
                 R dsON  · A 
                 Quasi Sat 
               
               
                   
                   
               
             
            
               
                   
                 Short 
                 No 
                 High 
                 Poor 
               
               
                   
                 Short 
                 Yes 
                 Low 
                 Poor 
               
               
                   
                 Medium 
                 No 
                 High 
                 Good 
               
               
                   
                 Medium 
                 Yes 
                 Low 
                 Good 
               
               
                   
                 Long 
                 No 
                 High 
                 Good 
               
               
                   
                 Long 
                 Yes 
                 Low 
                 Best 
               
               
                   
                   
               
            
           
         
       
     
     An LDMOS with having an accumulation enhancement implant and a long bird&#39;s beak, e.g., as shown in  FIG. 2 , can be manufactured with the conventional method for manufacturing a conventional LDMOS, as shown in  FIG. 1 , with some additional steps. 
     In the conventional process, for an N-channel LDMOS, a starting silicon P-substrate  110  with either N-type or P-type epitaxial layer or without epitaxial layer supported on the substrate is provided. P-type implantation is carried out to form P-well body region  112  followed with an N-type implant to form N-drift drain region  114  at the top portions of the substrate  110 . 
     A field oxide  116  is then formed on a surface of the substrate  110 . The bird&#39;s beak  132  of the field oxidation may be intentionally made long. To form the bird&#39;s beak  132 , a thin layer of oxide may be formed on the surface of the substrate  110  and a nitride film may be formed on the thin oxide. As is well known, the length of the bird&#39;s beak portion  132  can be controlled by optimization of thickness of the nitride film and the underlying thin oxide. As an alternative to growing the bird&#39;s beak of the field oxide, a thick insulator, e.g., a thick oxide may be grown under the gate  118 . 
     An enhancement implant of N-type dopants is carried out, after field oxide formed, through sacrificial oxide (not shown) into the accumulation region  128  forming the enhancement implant region  130 . Drain side of the implant opening overlaps with field oxide, so that the implant is self-aligned. 
     Next, a polysilicon gate  118  can be formed on the surface of the thin gate oxide and the field oxide  116 . Source region  120  doped with the high concentration N-type dopants can be formed in a region adjacent to the P+ body contact region  124  in the surface of the P-well body region  112  and drain contact pickup region  122  also doped with the high concentration N-type dopants in the surface of the N-drift drain region  114 . As a result, the source region  120  and the drain contact pickup region  122  are formed at both sides of the field oxide  116  and isolated from each other. The gate, body, source and drain electrodes are thus formed to complete the device. 
     In an alternative embodiment, the enhancement implantation can be carried out after the formation of the poly gate with higher implant energy, e.g., using arsenic or phosphorous implantation for an N-channel LDMOS device. 
     It should be noted that the above technique can be applied to both N-type and P-type LDMOS. In addition, the enhancement implantation described above can be applied to a LDMOS transistor  300  without a field oxide as shown in  FIG. 3 . 
     While the above is a complete description of the preferred embodiments of the present invention, it is possible to use various alternatives, modifications, and equivalents. Therefore, the scope of the present invention should be determined not with reference to the above description but should, instead, be determined with reference to the appended claims, along with their full scope of equivalents. Any feature, whether preferred or not, may be combined with any other feature, whether preferred or not. In the claims that follow, the indefinite article “A” or “An” refers to a quantity of one or more of the item following the article, except where expressly stated otherwise. The appended claims are not to be interpreted as including means-plus-function limitations, unless such a limitation is explicitly recited in a given claim using the phrase “means for”. Any element in a claim that does not explicitly state “means for” performing a specified function, is not to be interpreted as a “means” or “step” clause as specified in 35 USC §112, ¶6.