Patent Publication Number: US-8120415-B2

Title: Circuit for generating a temperature-compensated voltage reference, in particular for applications with supply voltages lower than 1V

Description:
PRIORITY CLAIM 
     The present application claims the benefit of European Patent Application Serial No.: 08425331.9, filed May 13, 2008, which application is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     An embodiment of the present disclosure relates to a circuit for generating a temperature-compensated voltage reference. 
     More specifically, an embodiment of the disclosure relates to a circuit of the type comprising at least one current reference, inserted between a first and a second voltage reference and including an operational amplifier, having in turn a first and a second input terminal coupled to an input stage comprising a generator circuit of a current proportional to the temperature by means of at least one first bipolar transistor, as well as a current mirror coupled to the first supply voltage reference and inserted between the first and the second input terminal of the operational amplifier and an output terminal of the circuit suitable for supplying this temperature-compensated voltage reference. 
     An embodiment of the disclosure particularly, but not exclusively, relates to a generator circuit of a voltage of the band-gap type and the following description is made with reference to this field of application by way of illustration only. 
     BACKGROUND 
     Circuits for the generation of a voltage reference, also simply indicated as voltage references, are widely used in the integrated circuits for the most varied needs. 
     These circuits supply, in particular, at least one electric quantity having a high accuracy and stability that can be used in general as reference in several circuit blocks, such as for example, analogue/digital converters, voltage regulators, detection and/or measurement circuits, etc. 
     A voltage reference should thus be strong for the applications it is intended for and in particular be characterized by a good thermal stability and by a good noise rejection, so as to supply a constant output voltage value independent from the variations of the supply voltage and of the working temperature of the integrated circuit comprising it. 
     To this purpose, circuits are commonly used for generating a voltage reference of the band-gap type, or more simply band-gap generators, wherein, the potential jump of the silicon prohibited band (about 1.1 eV) is exploited for generating an accurate voltage reference independent from the working temperature. 
     In particular, such a band-gap generator arises from the realization that a voltage VBG almost independent from the working temperature can be obtained in a simple way by means of a bipolar transistor by implementing the following equation:
 
 VBG=VBE+nVT    (1)
 
VBG being the voltage reference independent from the temperature, or of band-gap, VBE being the voltage between the base and emitter terminals of the bipolar transistor used, VT being the thermal voltage (equal to kT/q, k being the Bolzmann constant, T being the absolute temperature and q being the electron charge) and n being a multiplicative parameter calculated to obtain the desired compensation of the variations in temperature of the voltage VBE.
 
     The voltage VBE between base and emitter of a bipolar transistor decreases when the temperature increases (˜−2.2 mV/° C.@T=300° K), while the thermal voltage VT is proportional to the temperature itself. In other words, a voltage (VBE) is to be compensated which decreases with the absolute temperature, i.e., it is CTAT (Complementary To Absolute Temperature) with a corrective coefficient (nVT) which is proportional to the absolute temperature or PTAT (Proportional To Absolute Temperature). 
     To obtain a voltage reference independent from the temperature one determines the value of the parameter n for which the derivative of the band-gap voltage VBG, with respect to the temperature, is equal to zero considering a temperature T=T* equal to a desired working temperature. For example if a null variation of the band-gap voltage reference VBG is to be obtained at the temperature of 27° C., a value of about 1.26V for VBG is found, the voltage VBE being at environment temperature equal to about 0.6V and the parameter n equal to about 26. 
     A band-gap generator may be realized in full CMOS technology realising the bipolar transistors by means of parasitic diodes. A possible implementation using an operational amplifier is shown in  FIG. 1 . 
     In particular,  FIG. 1  shows a generator  1  of a band-gap voltage reference VBG. This generator  1  comprises an operational amplifier  2  inserted between a first and a second voltage reference, in particular a supply voltage reference VDD and a ground GND. 
     The operational amplifier  2  has a first input terminal T 1 , in particular an inverting one (−), and a second input terminal T 2 , in particular a non inverting one (+), as well as an output terminal, corresponding to the output terminal OUT of the generator  1 , where the band-gap voltage reference VBG is supplied. 
     The generator  1  also comprises a bipolar stage  3  inserted between the output terminal OUT of the operational amplifier  2  and the ground GND and comprising a first Q 1  and a second bipolar transistor Q 2 , as well as a first R 1 , a second R 2 , and a third resistive element R 3 . 
     More in particular, the first bipolar transistor Q 1  is inserted between the second input terminal T 2  of the operational amplifier  2  and the ground GND and has a control or base terminal coupled to the base terminal of the second bipolar transistor Q 2  and both coupled to ground (both the bipolar transistors are diode-connected). The bipolar transistor Q 2  is also coupled, through the first resistive element R 1 , to the first input terminal T 1  of the operational amplifier  2  as well as to the ground GND. 
     The second input terminal T 2  of the operational amplifier  2  is also feedback connected to its output terminal OUT, by means of the second resistive element R 2  and the first input terminal T 1  of the operational amplifier  2  is similarly feedback connected to its output terminal OUT, by means of the third resistive element R 3 . 
     It is to be noted that the operational amplifier  2  performs the double function of realizing a current proportional to the thermal voltage VT and of ensuring the output supply of a band-gap voltage reference VBG with low impedance, which is desirable, when the generator  1  should supply current. 
     Thanks to the presence of the operational amplifier  2  it is possible to assume that the voltage values on its input terminals T 1  and T 2  are identical (V + =V − ), by putting A E2 =kA E1 , A E2 , A E1  being the areas of the emitter terminals of the first and second bipolar transistors Q 1  and Q 2 , respectively and k being a suitable project parameter calculated to obtain the desired temperature compensation. 
     Observing moreover that R 2 *IC1=R 3 *IC2, R 2  and R 3  being the resistive values of the second and third resistive elements R 2  and R 3 , respectively, and IC1, IC2 the collector currents of the first and second bipolar transistors Q 1  and Q 2 , respectively, the following is obtained: 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       C 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   = 
                   
                     
                       
                         V 
                         T 
                       
                       
                         R 
                         2 
                       
                     
                     ⁢ 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             
                               R 
                               3 
                             
                             
                               R 
                               2 
                             
                           
                           ⁢ 
                           k 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
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     Wherefrom the expression of the band-gap voltage reference VBG is easily derived: 
                     V   BG     =       V     EB   ⁢           ⁢   1       +         R   3       R   1       ⁢     V   T     ⁢     ln   ⁡     (         R   3       R   2       ⁢   k     )                   (   3   )               
V EB1  being the voltage between the base and emitter terminals of the first bipolar transistor Q 1  and R 1 , R 2 , R 3  the resistive values of the first, second and third resistive elements.
 
     It is to be noted that the minimum value of the supply voltage reference VDD of the generator  1  under examination depends on the effective physical realization of the operational amplifier  2 , but it results in any case limited below by the reference voltage value calculated for having a null variation at the environment temperature, equal to about 1.26V, as above indicated. 
     The generator  1  realized by means of the operational amplifier  2  and shown in  FIG. 1  cannot thus be used in applications having supply voltages lower than about 1.3V. 
     It is also possible to modify the generator  1  to adapt it to applications with supply voltage lower than 1.3V and to obtain the generator  5  shown in  FIG. 2 , also inserted between a first and a second voltage reference, in particular a supply voltage reference VDD and a ground GND and having an output terminal OUT where the band-gap voltage reference VBG is supplied. 
     The generator  5  also comprises an operational amplifier  2  having a first input terminal T 1 , in particular an inverting one (−), and a second input terminal T 2 , in particular a non inverting one (+), as well as an output terminal OUT. 
     The generator  5  further comprises an input stage  6  inserted between the input terminals, T 1  and T 2 , of the operational amplifier  2  and the ground GND, in turn including a first Q 1  and a second bipolar transistor Q 2 , as well as a first R 1 , a second R 2 , and a third resistive element R 3 . 
     More in particular, the first bipolar transistor Q 1  is inserted, in series with the first resistive element R 1 , between the first input terminal T 1  of the operational amplifier  2  and the ground GND and has a control or base terminal coupled to the ground GND. 
     Similarly, the second bipolar transistor Q 2  is in turn inserted, in series with the second and the third resistive element R 2 , R 3 , between the second input terminal T 2  of the operational amplifier  2  and the ground GND and has a control or base terminal coupled to the ground GND. 
     The generator  5  also comprises a current mirror  7 , inserted between the supply voltage reference VDD and an inner circuit node X′ and coupled to the input terminals T 1 , T 2  of the operational amplifier  2 , as well as with its output terminal OUT and including a first, a second and a third MOS transistor, M 1 , M 2  and M 3  as well as a first capacitor C 1 . 
     More in particular, the first MOS transistor M 1  is inserted between the supply voltage reference VDD and the first input terminal T 1  of the operational amplifier  2  and has a control or gate terminal coupled to the control or gate terminal of the second MOS transistor M 2 , and both coupled to the output terminal OUT of the operational amplifier, the second MOS transistor M 2  being in turn inserted between the supply voltage reference VDD and the second input terminal T 2  of the operational amplifier  2 . Similarly the third MOS transistor M 3  is inserted between the supply voltage reference VDD and the inner circuit node X′ and has the control or gate terminal coupled to the output terminal OUT of the operational amplifier  2  as well as with the bulk terminal of the second MOS transistor M 2 . 
     Finally, the first capacitor C 1  of the current mirror  7  is inserted between the supply voltage reference VDD and the output terminal OUT of the operational amplifier  2 . 
     In this way, the current mirror  7  is able to supply the inner circuit node X′ with a value of current IP 1  proportional to the current flowing in the first bipolar transistor Q 1  of the input stage  6 . 
     The generator  5  also comprises an output stage  8  inserted between the inner circuit node X′ and the ground GND and coupled to the output terminal OUT′ of the generator  5  and comprising a third bipolar transistor Q 3 , a fourth and a fifth resistive element R 4  and R 5  and a second capacitor C 2 . 
     More in particular, the fourth resistive element R 4  and the third bipolar transistor Q 3  are inserted, in series with each other, between the inner circuit node X′ and the ground GND, the third bipolar transistor Q 3  also having a control or base terminal in turn coupled to the ground GND. Similarly, the fifth resistive element R 5  and the second capacitor C 2  are inserted, in parallel to each other, between the inner circuit node X′ and the ground GND. 
     It is to be noted that the voltage values on the input terminals T 1  and T 2  of the operational amplifier  2  being equal (V + =V − ) and having:
         A E2 =nA E1 , R 1 =R 3 , I P1 =k 1 I P  
 
being:
       A E2 , A E1  the areas of the emitter terminals of the first and second bipolar transistors Q 1  and Q 2 , respectively, of the input stage  6  and n a suitable multiplicative coefficient calculated to obtain the desired compensation in temperature,   R 1 , R 3  the resistance values of the first and of the second resistive element of the input stage  6 , and   I P , I P1  the current values flowing in the first bipolar transistor Q 1  of the input stage  6  and in correspondence with the inner circuit node X′ at the output of the current mirror  7 , respectively, and k 1  a suitable multiplicative coefficient introduced by the dimensional ratio of the transistors M 1  and M 3  of this current mirror  7  with simple mathematical expressions, it is possible to obtain the following expression of the band-gap voltage reference VBG:   

                     V   BG     =         R   5         R   5     +     R   4         ⁢     (       V     EB   ⁢           ⁢   3       +         R   4       R   2       ⁢     V   T     ⁢     K   1     ⁢     ln   ⁡     (       I     S   ⁢           ⁢   2         I     S   ⁢           ⁢   1         )           )               (   4   )               
being:
     R 2  the resistance value of the second resistive element of the input stage  6 , R 4 , R 5  the resistance values of the fourth and fifth resistive elements of the output stage  8 ,   V EB3  the voltage value between the base and emitter terminals of the third bipolar transistor Q 3  of the output stage  8 ; and   I S1 , I S2  the inverse saturation current values of the first and second bipolar transistors Q 1  and Q 2 , respectively.   

     It thus occurs that the resistive elements R 1  and R 3  are suitable for ensuring that signals at the input of the operational amplifiers  2  are adequate also at high temperatures, when the voltage value between the base and emitter terminals V EB  of the bipolar transistors is low. 
     In fact, it is to be noted that the differential pair with which the operational amplifier is realized (not shown in the figure), for applications with low supply voltage values, should be of the n-channel type since a pair of p-channel transistors would be off for values of the supply voltage below about 1.4V. The resistive elements R 1  and R 3  put in series with the bipolar transistors Q 1  and Q 2  have the function of allowing a correct operation range at the input terminals T 1  and T 2  of the operational amplifier  2 , substantially increasing by a certain amount the voltage value at the input terminals T 1  and T 2  of the operational amplifier  2 , since the voltage VBE of these bipolar transistors Q 1  and Q 2  at high temperatures decreases too much for ensuring the turn-on of the n-channel transistors. 
     In this way, the generator  5  is able to offer good performances down to values of the supply voltage equal to about 1.1V. 
     However, for lower supply voltage values, and especially at low temperatures, when the voltage value between the base and emitter terminals V EB  of the bipolar transistors is high, it may occur that the first and the second MOS transistors M 1  and M 2  of the current mirror  7  operate with a very low voltage value between the source and drain terminals Vds, and in particular quite different from the voltage value between the source and drain terminals Vds of the third MOS transistor M 3 , this latter voltage being considered constant for the whole temperature range. 
     These different operative conditions may cause mirroring errors of the currents, which may result in a poor behavior of the generator  5  when the temperature varies. 
     SUMMARY 
     An embodiment of the present disclosure is providing a generator circuit of a voltage reference independent from the temperature and having such structural and functional characteristics as to allow to overcome limits and drawbacks still affecting the generators realized according to the prior art and in particular, in the case of applications with low values of the supply voltage, to ensure that the voltage value applied to the input terminals of the operational amplifier contained in the band-gap generator is enough to ensure the turn-on of its input n-channel pair. 
     An embodiment of the present disclosure suitably and dynamically drives the control terminals of bipolar transistors coupled to the input terminals of the operational amplifier of the band-gap generator contained in the generator circuit of a temperature-compensated voltage reference so as to maintain a voltage value applied across this operational amplifier as constant as possible when the temperature varies, thus obtaining a correct common mode voltage range applied to these input terminals and thus a correct operation of its input n-channel pair for very low values, in particular lower than 1V, of the supply voltage. 
     More in particular, an embodiment of the disclosure generates a base biasing voltage which depends on the temperature in an inverse way with respect to the base-emitter voltage of the bipolar transistors coupled to the input terminals of the operational amplifier of the band-gap circuit and is summed thereto to compensate its variations with the temperature and obtain at the input terminals of this operational amplifier a voltage having a suitable value in the whole temperature range. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Characteristics and advantages of the circuit and of the method according to one or more embodiments of the disclosure will be apparent from the following description given by way of indicative and non limiting example with reference to the annexed drawings. 
       In these drawings: 
         FIG. 1  schematically shows a possible circuit implementation of a generation circuit of a band-gap voltage reference realized according to the prior art; 
         FIG. 2  schematically shows a further implementation of a generator circuit of a band-gap voltage reference realized according to the prior art and suitable for applications with low supply voltages; 
         FIG. 3A  schematically shows a circuit for generating a temperature-compensated voltage reference realized according to an embodiment of the disclosure; 
         FIG. 3B  schematically and in further detail shows the circuit of  FIG. 3A ; 
         FIG. 4  schematically and in further detail shows the circuit of  FIG. 3A ; 
         FIG. 5  schematically shows a detail of the circuit of  FIG. 3A ; 
         FIG. 6  schematically shows a possible circuit implementation of the generator circuit of a temperature-compensated voltage reference according to an embodiment of the disclosure; 
         FIG. 7  shows the pattern of the temperature-compensated voltage reference obtained by a generation circuit according to an embodiment of the disclosure when the temperature varies; 
         FIG. 8  shows the rejection analysis on the supply or PSRR (Power Supply Rejection Ratio) of a generation circuit according to an embodiment of the disclosure carried out with a supply voltage equal to 0.9V. 
     
    
    
     DETAILED DESCRIPTION 
     With reference to these figures, and in particular to  FIG. 3A , a circuit generating a temperature-compensated voltage reference, in particular using a band-gap voltage, is schematically and globally indicated with  10 , hereafter simply indicated as generator  10 . 
     The generator  10  comprises a generator circuit  13  of a band-gap voltage VBG, indicated as band-gap circuit  13 . As seen in relation to  FIG. 2 , the band-gap circuit  13  comprises an operational amplifier having at least one first and one second bipolar transistor coupled to the input terminals of this operational amplifier and an output terminal OUT. This operational amplifier also comprises, coupled to these input terminals, a pair of differential MOS n-channel transistors. 
     An embodiment of the band-gap circuit  13  is coupled, in correspondence with a first and a second control node, Xc 1  and Xc 2 , with a control block  14 . In particular, the control block  14  is suitable for imposing, in correspondence with the first control node Xc 1 , a first biasing voltage value VBase on the base terminals of the bipolar transistors of the band-gap circuit  13 , in particular, such a voltage value that, added to the voltage value between the base and emitter terminals, V BE , of these bipolar transistors, an adequate common mode voltage is obtained being able to ensure the correct operation of the operational amplifier in the band-gap circuit  13  and in particular the turn-on of its differential pair of input n-channel MOS transistors. Moreover, the control block  14  receives, in correspondence with the second control node Xc 2 , a second biasing voltage value Vpbias. As it will be clear hereafter in the description, according to an embodiment of the disclosure, the control block  14  imposes a biasing voltage value having at least one component which increases with the temperature T to compensate the variations of the voltage between the base and emitter terminals V BE . Moreover, from the sum of these voltages, an amount is deducted constant with the temperature T to add a substantially fixed base to the voltage value as obtained and thus suitably fix the common mode voltage level at the input terminals of the operational amplifier. 
     According to an embodiment of the disclosure, the generator  10  also comprises a reference block  11  coupled to a third control node Xc 3  of the control block  14  and supplying it with a voltage value substantially constant with the temperature, Viref. 
     In an embodiment of the disclosure, the reference block  11  generates a current value constant with the temperature, Iref, starting from the value of the band-gap voltage VBG generated by the band-gap circuit  13 , which is mirrored through a reference voltage Viref. 
     In this case, as schematically shown in  FIG. 3B , the reference block  11  is inserted between a first and a second voltage reference, in particular a supply voltage reference VDD and a ground GND and includes a current reference  12  in turn including an operational amplifier OTA (transconductance amplifier). 
     The operational amplifier OTA has a first input terminal, in particular an inverting one (−), and a second input terminal, in particular a non-inverting one (+) as well as an output terminal coupled to a first inner circuit node X 1 . The second input terminal of the operational amplifier OTA is suitably coupled to the output terminal OUT of the band-gap circuit  13  and receives there from the band-gap voltage VBG. 
     In particular, the current reference  12  further comprises a first and a second MOS transistor, M 1  and M 2 , and a first resistive element R 1 . The first MOS transistor M 1  is inserted between the supply voltage reference VDD and the first input terminal of the operational amplifier OTA and has a control or gate terminal coupled to the first inner circuit node X 1 , as well as to a control or gate terminal of the second MOS transistor M 2 , in turn inserted between the supply voltage reference VDD and a second inner circuit node X 2 . The first resistive element R 1  is in turn coupled between the first inner circuit node X 1  and the ground GND. 
     Moreover, the reference block  11  comprises a third MOS transistor M 3  inserted between the second inner circuit node X 2  at the output of the current reference  12  and the ground GND and having a control or gate terminal diode-connected to the second inner circuit node X 2 . In this way, the third MOS transistor M 3  realises a mirror of a reference current Iref, this mirror mirroring a reference current Iref flowing in the first resistive element R 1  and converting it into the reference voltage value Viref, supplying it to the third control node Xc 3  of the control block  14 . 
     It is to be noted that this reference current Iref is obtained starting from the band-gap voltage VBG on a resistance R 1  and is thus stable in temperature. 
     In the embodiment shown in  FIG. 3B , the first and second transistors M 1  and M 2  are PMOS transistors and the third transistor M 3  is an NMOS transistor. 
     The generator  10  according to an embodiment of the disclosure is shown in greater detail in  FIG. 4  and in particular the band-gap circuit  13 , controlled by the control block  14 . 
     As previously seen, the generator  10  thus comprises the band-gap circuit  13  coupled to the control block  14  in correspondence with the first and second control nodes, Xc 1  and Xc 2 , as well as to the reference block  11  in correspondence with the third control node Xc 3 . 
     The band-gap circuit  13  comprises an operational amplifier OA 1  having a first input terminal T 1 , in particular an inverting one (−) and a second input terminal T 2 , in particular a non-inverting one (+), as well as an output terminal Tout. 
     More in particular, the first and second input terminals, T 1  and T 2 , are coupled, as seen in relation with  FIG. 2 , to an input stage  15  comprising a first and a second bipolar transistor, Q 1  and Q 2 , and a second resistive element R 2 . The first bipolar transistor Q 1  is inserted between the second input terminal T 2  of the operational amplifier OA 1  and the ground GND and has a control or base terminal coupled, in correspondence with the first control node Xc 1 , to the control or base terminal of the second bipolar transistor Q 2 . Moreover, the second resistive element R 2  and the second bipolar transistor Q 2  are inserted, in series with each other, between the first input terminal T 1  of the operational amplifier OA 1  and the ground GND. 
     According to an embodiment of the disclosure, the common base terminals of the first and second bipolar transistors, Q 1  and Q 2 , of the input stage  15  are coupled to the control block  14  and receive there from the first biasing voltage value VBase. 
     Further, the band-gap circuit  13  comprises a current mirror  16  coupled to the input and output terminals of the operational amplifier OA 1  and comprising a first, a second, a third and a fourth mirror MOS transistor, MS 1 , MS 2 , MS 3  and MS 4 . 
     In particular, the first mirror MOS transistor MS 1  is inserted between the supply voltage reference VDD and a third inner circuit node X 3  and has a control or gate terminal coupled to the output terminal Tout of the operational amplifier OA 1  and to the control or gate terminal of the second mirror MOS transistor MS 2 , in turn inserted between the supply voltage reference VDD and the output terminal OUT of the band-gap circuit  13 , corresponding to the output terminal of the generator  10 . Similarly, the third and fourth mirror MOS transistors MS 3  and MS 4  are inserted between the supply voltage reference VDD and the second and first input terminals T 2  and T 1  of the operational amplifier OA 1 , respectively, and have respective control or gate terminal coupled to each other and to the output terminal Tout of the operational amplifier OA 1 . In the embodiment shown in  FIG. 4 , the mirror transistors MS 1 , MS 2 , MS  3  and MS  4  are PMOS transistors. 
     Moreover, the band-gap circuit  13  comprises an output stage  17  coupled to the output terminal OUT. In particular, the output stage  17  comprises in turn a third bipolar transistor Q 3  inserted between the third inner circuit node X 3  and the ground GND and having the control or base terminal coupled to the ground GND, as well as a resistive divider  18  including a first resistive element R 1 ′ coupled between the third inner circuit node X 3  and the output terminal OUT and a second resistive element R 2 ′ coupled between the output terminal OUT and the ground GND. 
     It is to be noted that the output stage  17 , and in particular the resistive divider  18 , allows one to fix the value of the band-gap voltage VBG obtained at the output terminal OUT to the desired value, for example equal to 0.65V. 
     It is possible to consider other configurations for the output stage  17 , in particular with the third bipolar transistor Q 3  inserted in series with the first resistive element R 1 ′ between the output terminal OUT and the ground GND, in parallel with the second resistive element R 2 ′. 
     As previously said, according to an embodiment of the disclosure, the common base terminal of the bipolar transistors Q 1  and Q 2  is coupled to the first control node Xc 1  of the control block  14  suitable for imposing a first biasing voltage value VBase, in particular, such a voltage value that, added to the voltage value between the base and emitter terminals, V BE , of these bipolar transistors, an adequate common mode voltage is obtained being able to ensure the correct operation of the operational amplifier OA 1 , in particular suitable for ensuring the turn-on of the pair of input n-channel MOS transistors of this operational amplifier OA 1 . 
     It is in fact to be remembered that it may be desirable the common mode voltage applied to the input terminals of the operational amplifier OA 1  differ as little as possible with respect to the band-gap output voltage VBG for consequently reducing the systematic error introduced by the current mirror  16 , in particular comprising MOS transistors of the P type, due to the so called Early effect. 
     This nullifying effect of the current mirror is obtained, advantageously according to an embodiment of the disclosure, by the control block  14  shown in greater detail in  FIG. 5 . 
     In particular, the control block  14  is inserted between the supply voltage reference VDD and the ground GND and has an input terminal in correspondence with the third control node Xc 3  and an output terminal in correspondence with the first control node Xc 1 . 
     The control block  14  comprises a first and a second MOS transistor, M 5  and M 6 , inserted, in series with each other, between the supply voltage reference VDD and the first control node Xc 1  and interconnected in correspondence with a fourth inner circuit node X 4 , as well as a third and a fourth MOS transistor, M 10  and M 7 , inserted, in series with each other, between the supply voltage reference VDD and a fifth inner circuit node X 5 . 
     More in particular, the first transistor M 5  is a PMOS transistor and has a control or gate terminal coupled, in correspondence with the terminal Tout, which is the output terminal of the operational amplifier OA 1  of  FIG. 4 , with the control or gate terminal of the third transistor M 10 , also a PMOS transistor. Moreover, the second transistor M 6  is an NMOS transistor and has a control or gate terminal coupled to the control or gate terminal of the fourth transistor M 7 , also an NMOS transistor and diode-connected. 
     The control block  14  further comprises a fifth and a sixth MOS transistor, M 8  and M 9 , inserted, in parallel to each other, between the first control node Xc 1  and the ground GND. In particular, the fifth transistor M 8  is an NMOS transistor and has a control or gate terminal coupled to the fourth inner circuit node X 4 , while the sixth transistor M 9  is an NMOS transistor and has a control or gate terminal coupled to the third control node Xc 3 . 
     The control block  14  also comprises a seventh MOS transistor M 11  and a resistive element R 3  inserted, in parallel to each other, between the fifth inner circuit node X 5  and the ground GND. In particular, the seventh transistor M 11  is an NMOS transistor having a control or gate terminal coupled to the third control node Xc 3 . 
     As previously seen, the control block  14  receives on the third control node Xc 3  a reference voltage value Viref supplied by the reference block  11 . 
     According to an embodiment of the disclosure, the control block  14  supplies to the first control node Xc 1  a first biasing voltage value VBase, which is substantially equal to the voltage value VSource being at the fifth inner circuit node X 5  and substantially equal to:
 
 V Source= V Base=(Δ Veb/R 2 −n*VBG/R 1)* R 3   (5)
 
     In fact, it is immediate to verify that, in the branch comprising the transistors M 7  and M 10 , a current Iptat flows substantially equal to ΔVeb/R 2 , ΔVeb being the difference between the two base-emitter voltages Veb of the two bipolar transistors Q 1  and Q 2  of the input stage  15 , which is divided into a first current proportional to the reference current Iref which flows in the branch comprising the seventh transistor M 11  and a second current Ir which flows in the branch comprising the resistive element R 3 . Moreover, also in the branch comprising the sixth transistor M 9  a current flows proportional to the reference current Iref. The value of the first current Iref is obtained by the reference block  11  starting from the band-gap voltage VBG and is equal to Iref=VBG/R 1 , R 1  being the resistive element of the current reference  12  shown in  FIG. 3B . 
     The size of the seventh transistor M 11  is chosen so as to be equal to n times the size of the sixth transistor M 9 , n being a suitably chosen multiplicative parameter. 
     In this way, the common mode voltage Vcommon applied to the input terminals T 1  and T 2  of the operational amplifier  12  is given by
 
 V common= Veb+ΔVeb *( R 3 /R 2)− n*VBG* ( R 3 /R 1)   (6)
 
being
     Veb the voltage value between the emitter and base terminals of the first bipolar transistor Q 1  of the input stage  15  and ΔVeb the difference between the two base-emitter voltages Veb of the two bipolar transistors Q 1  and Q 2  of the input stage  15 ;   VBG the band-gap voltage value supplied by the band-gap circuit  13 ;   R 1  the resistive value of the resistive element of the reference block  11 ;   R 2  the resistive value of the resistive element coupled to the second bipolar transistor Q 2  in the input stage  15 ; and   R 3  the resistive value of the resistive element of the control block  14 .   

     In other words, according to an embodiment of the disclosure, the control block  14  allows to obtain a resulting voltage given by a first component which decreases with the temperature T (Veb) and by a second component which increases with the temperature T (ΔVeb*(R 3 /R 2 )), which compensates the variations of the first component, components from which a third component constant with the temperature T (n*VBG*(R 3 /R 1 )) is deducted. In particular, the third component allows to add a fixed base to the voltage value obtained and thus to suitably fix the common mode level at the input terminals of the operational amplifier. 
     The overall scheme of the generator  10  according to an embodiment of the disclosure is shown in  FIG. 6 , where, by way of simplicity, the illustration of the reference block  11  has been omitted and where a sixth inner circuit node X 6  has been further indicated corresponding to the common gate terminals of the transistors M 6  and M 7 . 
     According to an embodiment of the disclosure, as above explained, the generator  10  then supplies a band-gap voltage VBG reference sufficiently independent from the temperature and operable with supply voltages below 1V. 
     An embodiment of the disclosure also relates to a method for generating a temperature-compensated voltage reference VBG starting from a band-gap voltage obtained by a band-gap circuit  13  comprising an operational amplifier OA 1  having the input terminals coupled to at least one first and one second bipolar transistor, Q 1  and Q 2 . 
     The method thus comprises the steps of:
         generating a first component of the temperature-compensated voltage reference which decreases with the temperature, as base-emitter voltage of one of said bipolar transistors, in particular of the first bipolar transistor Q 1 ;   driving the base terminal of the first bipolar transistor Q 1  by applying the biasing voltage value VBase supplied by the control block  14  coupled to this base terminal; and   obtaining the temperature-compensated voltage value VBG on the output terminal OUT of the generator  10 .       

     Suitably, the driving step provides that the control block  14  imposes to the base terminal of the first bipolar transistor Q 1  a biasing voltage value VBase comprising at least one voltage component which increases with the temperature (ΔVeb*(R 3 /R 2 ) to compensate the variations of the voltage (VBE) inversely proportional to the temperature obtained between the base and emitter terminals VBE of the first bipolar transistor Q 1 . In this way, as previously explained, the turn-on of the pair of n-channel input transistors of the operational amplifier OA 1  is substantially ensured. 
     According to an embodiment of the disclosure, the driving step of the base terminal of the first bipolar transistor Q 1  further generates a third subtractive component of the biasing voltage value constant with the temperature (n*VBG*(R 3 /R 1 ) and able to add a fixed base to the voltage value obtained and thus a degree of freedom for the fixing of the common mode value at the input terminals of the operational amplifier. 
     One or more embodiments of the proposed generator  10  may find particular application in the memories for Smart Cards, and may also relate to a memory for Smart card of the type comprising at least one generator  10  of a temperature-compensated voltage reference as above described. 
     The results of experimental tests are shown in  FIGS. 7 and 8 . 
     In particular,  FIG. 7  shows an analysis in temperature of the generator  10  according to an embodiment of the disclosure simulated with a supply voltage equal to 0.9V and making the temperature vary from −40° C. to 125° C. 
     As it can be noted, the global variation of the band-gap voltage VBG in the whole temperature range as considered is lower than 3 mV. 
       FIG. 8  reports a rejection analysis on the supply or PSRR (Power Supply Rejection Ratio) of the generator  10  carried out with a supply voltage equal to 0.9V. It then occurs that the generator  10  according to an embodiment of the disclosure ensures a PSRR value of about 65 dB at low frequencies and a worse case of about 31 dB at a frequency of 50 kHz. 
     In conclusion, a generator  10  according to an embodiment of the disclosure has the following advantages:
         ensures a correct operation of the current reference also with supply voltages lower than 1V;   ensures a high rejection to the noise at the supply reference;   has good performances in terms of sensitivity to the variation of the supply voltage and of the temperature; and   offers a good compensation in temperature of the voltage value as obtained.       

     Suitably, an implementation of the circuit according to an embodiment of the disclosure also takes into due consideration the area occupation, a parameter that may become more and more important when the technology evolves. 
     An embodiment of the generator  10  may be included in an integrated circuit (IC) such as a memory circuit, which may be included in a system such as a computer system. The IC may be coupled to another IC (e.g., a controller) of the system, and the IC&#39;s may be on the same or different dies. 
     Naturally, in order to satisfy local and specific requirements, a person skilled in the art may apply to the solution described above many modifications and alterations. Particularly, although the present disclosure has been described with a certain degree of particularity with reference to described embodiment(s) thereof, it should be understood that various omissions, substitutions and changes in the form and details as well as other embodiments are possible. Moreover, it is expressly intended that specific elements and/or method steps described in connection with any disclosed embodiment of the disclosure may be incorporated in any other embodiment as a general matter of design choice.