Patent Publication Number: US-10790751-B2

Title: Systems and methods for real-time signal sampling in power conversion systems

Description:
1. CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 15/621,865, filed Jun. 13, 2017, which is a continuation of U.S. patent application Ser. No. 13/784,489, filed Mar. 4, 2013, which claims priority to Chinese Patent Application No. 201310058987.8, filed Feb. 25, 2013, all of these applications being commonly assigned and incorporated by reference herein for all purposes. 
    
    
     2. BACKGROUND OF THE INVENTION 
     The present invention is directed to integrated circuits. More particularly, the invention provides a control system and method for signal sampling. Merely by way of example, the invention has been applied to real-time signal sampling in power conversion systems. But it would be recognized that the invention has a much broader range of applicability. 
     Generally, a conventional power conversion system often uses a transformer to isolate the input voltage on the primary side and the output voltage on the secondary side. To regulate the output voltage, certain components, such as TL431 and an opto-coupler, can be used to transmit a feedback signal from the secondary side to a controller chip on the primary side. Alternatively, the output voltage on the secondary side can be imaged to the primary side, so the output voltage is controlled by directly adjusting some parameters on the primary side. Then, some components, such as TL431 and an opto-coupler, can be omitted to reduce the system costs. 
       FIG. 1  is a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation. The power conversion system  100  includes a primary winding  110 , a secondary winding  112 , an auxiliary winding  114 , a power switch  120 , a current sensing resistor  130 , an equivalent resistor  140  for an output cable, resistors  150  and  152 , and a rectifying diode  160 . For example, the power switch  120  is a bipolar junction transistor. In another example, the power switch  120  is a MOS transistor. 
     To regulate the output voltage within a predetermined range, information related to the output voltage and the output loading often needs to be extracted. For example, when the power conversion system  100  operates in a discontinuous conduction mode (DCM), such information can be extracted through the auxiliary winding  114 . When the power switch  120  is turned on, the energy is stored in the secondary winding  112 . Then, when the power switch  120  is turned off, the stored energy is released to the output terminal, and the voltage of the auxiliary winding  114  maps the output voltage on the secondary side as shown below. 
                     V   FB     =           R   2         R   1     +     R   2         ×     V   aux       =     k   ×   n   ×     (       V   o     +     V   F     +       I   o     ×     R   eq         )                 (     Equation   ⁢           ⁢   1     )               
where V FB  represents a voltage at a node  154 , and V aux  represents the voltage of the auxiliary winding  114 . R 1  and R 2  represent the resistance values of the resistors  150  and  152  respectively. Additionally, n represents a turns ratio between the auxiliary winding  114  and the secondary winding  112 . Specifically, n is equal to the number of turns of the auxiliary winding  114  divided by the number of turns of the secondary winding  112 . V o  and T o  represent the output voltage and the output current respectively. Moreover, V F  represents the forward voltage of the rectifying diode  160 , and R eq  represents the resistance value of the equivalent resistor  140 . Also, k represents a feedback coefficient as shown below:
 
     
       
         
           
             
               
                 
                   k 
                   = 
                   
                     
                       R 
                       2 
                     
                     
                       
                         R 
                         1 
                       
                       + 
                       
                         R 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
       FIG. 2  is a simplified diagram showing a conventional operation mechanism for the flyback power conversion system  100 . As shown in  FIG. 2 , the controller chip of the conversion system  100  uses a sample-and-hold mechanism. When the demagnetization process on the secondary side is almost completed and the current I sec  of the secondary winding  112  almost becomes zero, the voltage V aux  of the auxiliary winding  114  is sampled at, for example, point A of  FIG. 2 . The sampled voltage value is usually held until the next voltage sampling is performed. Through a negative feedback loop, the sampled voltage value can become equal to a reference voltage V ref . Therefore,
 
V FB =V ref   (Equation 3)
 
     Combining Equations 1 and 3, the following can be obtained: 
     
       
         
           
             
               
                 
                   
                     V 
                     o 
                   
                   = 
                   
                     
                       
                         V 
                         ref 
                       
                       
                         k 
                         × 
                         n 
                       
                     
                     - 
                     
                       V 
                       F 
                     
                     - 
                     
                       
                         I 
                         o 
                       
                       × 
                       
                         R 
                         eq 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ) 
                 
               
             
           
         
       
     
     Based on Equation 4, the output voltage decreases with the increasing output current. 
       FIG. 3  is a simplified diagram showing another conventional power conversion system with primary-side sensing and regulation. The power conversion system  200  includes a controller chip  202 , a primary winding  210 , a secondary winding  212 , an auxiliary winding  214 , a power switch  220 , a current sensing resistor  230 , an equivalent resistor  240  for an output cable, resistors  250  and  252 , and a rectifying diode  260 . The controller chip  202  includes a signal processing component  204 , a demagnetization detector  206 , an error amplifier  208 , a reference-signal generator  248 , an oscillator  228 , a modulation component  218 , a logic controller  224 , an over-current-protection (OCP) component  226 , and a driving component  222 . The signal processing component  204  includes a sampling component  242 , a switch  244 , and a capacitor  246 . The controller chip  202  includes terminals  282 ,  284 , and  286 . For example, the power switch  220  is a bipolar junction transistor. In another example, the power switch  220  is a MOS transistor. 
     The signal processing component  204  samples and holds a feedback signal  254  in response to a demagnetization-detection signal  256  from the demagnetization detector  206 . The error amplifier  208  receives a sampled-and-held signal  258  from the signal processing component  204  and a reference signal  272  from the reference-signal generator  248 , and outputs an amplified signal  262  to the modulation component  218 . The modulation component  218  also receives a clock signal  264  from the oscillator  228  and a current-sensing signal  268  and outputs a modulation signal  266  to the logic controller  224 . The driving component  222  outputs a drive signal  270  to the power switch  220  in order to regulate a primary current  272  flowing through the primary winding  210 . 
     But errors can occur when the signal processing component  204  samples the feedback signal  254 . Hence it is highly desirable to improve the techniques of primary-side sensing and regulation. 
     3. BRIEF SUMMARY OF THE INVENTION 
     The present invention is directed to integrated circuits. More particularly, the invention provides a control system and method for real-time signal sampling. Merely by way of example, the invention has been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability. 
     According to one embodiment, a system controller for regulating a power conversion system includes a signal processing component and a driving component. The signal processing component is configured to receive a feedback signal associated with an output signal of a power conversion system and generate a first processed signal based on at least information associated with the feedback signal. The driving component is configured to generate a drive signal based on at least information associated with the first processed signal and output the drive signal to a switch in order to affect a primary current flowing through a primary winding, the drive signal being associated with a demagnetization period corresponding to a demagnetization process of the power conversion system. The signal processing component is further configured to, sample and hold the feedback signal a plurality of times during the demagnetization period to generate a plurality of sampled and held signals, select a signal from the plurality of sampled and held signals, hold the selected signal, and generate the first processed signal based on at least information associated the selected and held signal. 
     According to another embodiment, a signal processing device for regulating a power conversion system includes a sampling and holding component and a selection and holding component. The sampling and holding component is configured to sample and hold a feedback signal a plurality of times during a demagnetization period and generate a plurality of sampled and held signals based on at least information associated with the feedback signal, the feedback signal being associated with an output signal of a power conversion system, the demagnetization period corresponding to a demagnetization process of the power conversion system. The selection and holding component is configured to select a signal from the plurality of sampled and held signals, hold the selected signal, and output a first processed signal based on at least information associated with the selected and held signal for regulating the power conversion system. 
     In one embodiment, a method for regulating a power conversion system includes receiving a feedback signal associated with an output signal of a power conversion system, generating a processed signal based on at least information associated with the feedback signal, and generating a drive signal based on at least information associated with the processed signal. The method further includes outputting the drive signal to a switch in order to affect a primary current flowing through a primary winding, the drive signal being associated with a demagnetization period corresponding to a demagnetization process of the power conversion system. The process for generating a processed signal based on at least information associated with the feedback signal includes, sampling and holding the feedback signal a plurality of times during the demagnetization period to generate a plurality of sampled and held signals, selecting a signal from the plurality of sampled and held signals, holding the selected signal, and generating the processed signal based on at least information associated the selected and held signal. 
     In another embodiment, a method for regulating a power conversion system includes sampling and holding a feedback signal a plurality of times during a demagnetization period, the feedback signal being associated with an output signal of a power conversion system, the demagnetization period corresponding to a demagnetization process of the power conversion system, generating a plurality of sampled and held signals based on at least information associated with the feedback signal, and selecting a signal from the plurality of sampled and held signals. The method further includes holding the selected signal, and outputting a processed signal based on at least information associated with the selected and held signal for regulating the power conversion system. 
     Depending upon embodiment, one or more benefits may be achieved. These benefits and various additional objects, features and advantages of the present invention can be fully appreciated with reference to the detailed description and accompanying drawings that follow. 
    
    
     
       4. BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified diagram showing a conventional flyback power conversion system with primary-side sensing and regulation. 
         FIG. 2  is a simplified diagram showing a conventional operation mechanism for the flyback power conversion system as shown in  FIG. 1 . 
         FIG. 3  is a simplified diagram showing another conventional power conversion system with primary-side sensing and regulation. 
         FIG. 4  is a simplified diagram showing certain specific error for the power conversion system as shown in  FIG. 3  according to one embodiment. 
         FIG. 5  is a simplified diagram showing a power conversion system with real-time signal sampling according to an embodiment of the present invention. 
         FIG. 6  is a simplified diagram showing the signal processing component as part of the power conversion system as shown in  FIG. 5  according to an embodiment of the present invention. 
         FIG. 7  is a simplified timing diagram for the power conversion system as shown in  FIG. 5  according to an embodiment of the present invention. 
         FIG. 8  is a simplified diagram showing the sample-and-hold component and the select-and-hold component as parts of the signal processing component as shown in  FIG. 6  according to an embodiment of the present invention. 
         FIG. 9  is a simplified diagram showing the counter component as parts of the signal processing component as shown in  FIG. 6  according to an embodiment of the present invention. 
         FIG. 10  shows a simplified timing diagram for the counter component as parts of the signal processing component as shown in  FIG. 6  according to an embodiment of the present invention. 
         FIG. 11  is a simplified diagram showing the flip-latch component as parts of the signal processing component as shown in  FIG. 6  according to an embodiment of the present invention. 
     
    
    
     5. DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is directed to integrated circuits. More particularly, the invention provides a control system and method for real-time signal sampling. Merely by way of example, the invention has been applied to power conversion systems. But it would be recognized that the invention has a much broader range of applicability. 
       FIG. 4  is a simplified diagram showing certain specific error for the power conversion system  200  according to one embodiment. The waveform  296  represents a secondary current  288  flowing through the secondary winding  212  as a function of time, and the waveform  298  represents the feedback signal  254  as a function of time. As shown in  FIG. 4 , a first switching period T sw1  includes a first on-time period T on1  and a first off-time period T off1 . The first on-time period starts at time t 0  and ends at time t 1 , and the first off-time period T off1  starts at the time t 1  and ends at time t 2 . The first off-time period T off1  includes a first demagnetization period T DEM1  which starts at the time t 1  and ends at time t dem1 . A second on-time period T on2  of a subsequent switching period starts at the time t 2  and ends at time t 3 , and a second off-time period T off2  of the subsequent switching period starts at the time t 3 . The second off-time period T off2  includes a second demagnetization period T DEM2  which starts at the time t 3  and ends at time t dem2 . 
     During the switching period T sw1 , the signal processing component  204  samples the feedback signal  254  at point B which may be determined according to the duration of a demagnetization period in a preceding switching period. As shown in  FIG. 4 , the point B corresponds to time t B , and the duration of a time period T sample1  between the time t 1  and the time t B  is equal to ⅔ of the duration of the demagnetization period of the preceding switching period. Then, during the subsequent switching period, the signal processing component  204  samples the feedback signal  254  at point B e  corresponding to time t Be . The duration of a time period T sample2  between t 3  and t Be  is determined to be equal to ⅔ of the duration of the demagnetization period T DEM1 . But because the demagnetization period T DEM2  is much shorter in duration than the demagnetization period T DEM1 , the sampling point B e  corresponding to the time t Be  is out of the demagnetization period T DEM2 . Thus, errors occur when the signal processing component  204  samples the feedback signal  254  at point B e , which may cause instability of the loop. 
       FIG. 5  is a simplified diagram showing a power conversion system with real-time signal sampling according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The power conversion system  300  includes a controller chip  302 , a primary winding  310 , a secondary winding  312 , an auxiliary winding  314 , a power switch  320 , a current sensing resistor  330 , an equivalent resistor  340  for an output cable, resistors  350  and  352 , and a rectifying diode  360 . The controller chip  302  includes a signal processing component  304 , a demagnetization detector  306 , an error amplifier  308 , a reference-signal generator  348 , an oscillator  328 , a modulation component  318 , a logic controller  324 , an over-current-protection (OCP) component  326 , and a driving component  322 . The controller chip  302  includes terminals  382 ,  384 , and  386 . For example, the power switch  320  is a bipolar junction transistor. In another example, the power switch  320  is a MOS transistor. 
     According to one embodiment, the signal processing component  304  samples and holds a feedback signal  354  in response to a demagnetization-detection signal  356  from the demagnetization detector  306 . For example, the error amplifier  308  receives a processed signal  358  from the signal processing component  304  and a reference signal  372  from the reference-signal generator  348 , and outputs an amplified signal  362  to the modulation component  318 . In another example, the modulation component  318  also receives a clock signal  364  from the oscillator  328  and a current-sensing signal  368  and outputs a modulation signal  366  to the logic controller  324 . In yet another example, the driving component  322  outputs a drive signal  370  to the power switch  320  in order to regulate a primary current  372  flowing through the primary winding  310 . 
     According to some embodiments, the signal processing component  304  performs real-time signal sampling. For example, the signal processing component  304  samples the feedback signal  354  based on information associated with a current switching period, instead of information of a preceding switching period. Thus, even if the duration of demagnetization periods varies in different switching periods, errors will not be introduced into sampling, in certain embodiments. 
       FIG. 6  is a simplified diagram showing the signal processing component  304  as part of the power conversion system  300  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The signal processing component  304  includes a sample-and-hold component  402 , a select-and-hold component  406 , a counter component  404 , a flip-latch component  408 , an encoding component  410 , and a capacitor  412 . 
       FIG. 7  is a simplified timing diagram for the power conversion system  300  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The waveform  502  represents the feedback signal  354  as a function of time, and the waveform  504  represents the demagnetization-detection signal  356  as a function of time. As shown in  FIG. 5 , a switching period T sw  includes an on-time period T on  and an off-time period T off . The on-time period T on  starts at time t 4 and ends at time t 5 , and the off-time period T off  starts at the time t 5  and ends at time t 7 . The off-time period T off  includes a demagnetization period T DEM  which starts at the time t 5  and ends at time t 6 . 
     As shown in  FIG. 4  and  FIG. 5 , if the demagnetization-detection signal  356  indicates the demagnetization period T DEM  begins (e.g., a rising edge in the demagnetization-detection signal  356  at is as shown by the waveform  504 ), the counter component  404  is triggered, and generates multiple sampling signals  414   1 ˜ 414   n  (e.g., K 1 ˜K n , where n is an integer) during the demagnetization period T DEM , in some embodiments. For example, the sample-and-hold component  402  samples the feedback signal  354  multiple times in response to the sampling signals  414   1 ˜ 414   n  and holds the sampled signals (e.g., onto one or more capacitors) until the end of the demagnetization period (e.g., at t 6 ). As shown by the waveform  502  in  FIG. 5 , during the demagnetization period T DEM , the feedback signal  354  is sampled once for every sampling period (e.g., T d ), according to some embodiments. 
     In one embodiment, if the demagnetization-detection signal  356  indicates the demagnetization period ends (e.g., a falling edge in the demagnetization-detection signal  356  at t 6  as shown by the waveform  504 ), the flip-latch component  408  receives multiple signals  416   1 ˜ 416   n  (e.g., q 1 ˜q n , where n is an integer) from the counter component  404  and generates multiple signals  418   1 ˜ 418   n  (e.g., Q 1 ˜Q n , where n is an integer). In yet another example, the encoding component  410  performs coding operations based on at least information associated with the signals  418   1 ˜ 418   n  and generates multiple selection signals  420   1 ˜ 420   n  (e.g., S 1 ˜S n , where n is an integer). In yet another example, the select-and-hold component  406  selects and holds one of the signals  422   1 ˜ 422   n  (e.g., n is an integer) associated with the sampled signals from the sample-and-hold component  402  according to the selection signals  420   1 ˜ 420   n . The select-and-hold component  406  may select and hold one of the signals  422   1 ˜ 422   n  that is associated with a particular sampled signal (e.g., sampled at point C as shown in  FIG. 7 , two sampling periods before the end of the demagnetization period), in some embodiments. For example, the selected-and-held signal is then output as the processed signal  358 . In yet another example, after a time period for sampling, the counter component  404  is reset (e.g., set to 0) until a next demagnetization period begins. 
       FIG. 8  is a simplified diagram showing the sample-and-hold component  402  and the select-and-hold component  406  as parts of the signal processing component  304  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The sample-and-hold component  402  includes switches  602   1 ˜ 602   n  (e.g., n is an integer) and capacitors  604   1 ˜ 604   n  (e.g., n is an integer). The select-and-hold component  406  includes switches  606   1 ˜ 606   n  (e.g., n is an integer) and a capacitors  608 . 
     According to one embodiment, referring back to  FIG. 4  and  FIG. 5 , during the demagnetization period T DEM , the feedback signal  354  is sampled once every sampling period (e.g., T d ), and the counter component  404  changes the sampling signals  414   1 ˜ 414   n  in response to each sampling of the feedback signal  354 . For example, one of the switches  602   1 ˜ 602   n  is closed (e.g., being turned on) in response to each sampling, and the feedback signal  354  is sampled and held at one of the capacitors  604   1 ˜ 604   n  that corresponds to the closed switch. As the number of the switches  602   1 ˜ 602   n  and the capacitors  604   1 ˜ 604   n  is predetermined, the feedback signal  354  may be sampled and held in a circular manner if the number of sampled signals exceeds the number of the switches  602   1 ˜ 602   n , in some embodiments. For example, if the feedback signal  354  is sampled n+2 times during the demagnetization period, the first n sampled signals pass through the switches  602   1 ˜ 602   n  and are held at the capacitors  604   1 ˜ 604   n  respectively. The n+1 sampled signal and the n+2 sampled signal pass through the switches  602   1  and  602   2 , and are held at the capacitors  604   1  and  604   2  respectively. 
     According to another embodiment, in response to the selection signals  420   1 ˜ 420   n  (e.g., S 1 ˜S n , where n is an integer), one of the switches  606   1 ˜ 606   n  is closed (e.g., being turned on). For example, one of the signals  422   1 ˜ 422   n  from the sample-and-hold component  402  is selected to pass through the closed switch and is held at the capacitor  608  until the selected-and-held signal is output as the processed signal  358 . 
       FIG. 9  is a simplified diagram showing the counter component  404  as parts of the signal processing component  304  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The counter component  404  includes signal generators  702 ,  704 ,  710   1 ˜ 710   n  (e.g., n is an integer), flip-flop components  708   1˜n  (e.g., n is an integer), a NOT gate  712 , and an OR gate  706 . For example, the signal generator  702  is triggered by a rising edge in the demagnetization-detection signal  356 . In another example, the signal generators  710   1˜n  (e.g., n is an integer) are triggered by a rising edge or a falling edge of the signals  416   1 ˜ 416   n  (e.g., q 1 ˜q n , n is an integer). 
       FIG. 10  shows a simplified timing diagram for the counter component  404  as parts of the signal processing component  304  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, the counter component  404  includes four flip-flop components  708   1 ˜ 708   4 . The waveform  802  represents the demagnetization-detection signal  356  as a function of time, the waveform  804  represents a signal  714  (e.g., q 4_b ) as a function of time, and the waveform  806  represents a signal  716  (e.g., K 0 ) as a function of time. In addition, the waveform  808  represents the signals  416   1  (e.g., q 1 ) as a function of time, the waveform  810  represents the signal  414   1  (e.g., K 1 ) as a function of time, the waveform  812  represents the signals  416   2  (e.g., q 2 ) as a function of time, and the waveform  814  represents the signal  414   2  (e.g., K 2 ) as a function of time. Further, the waveform  816  represents the signals  416   3  (e.g., q 3 ) as a function of time, the waveform  818  represents the signal  414   3  (e.g., K 3 ) as a function of time, the waveform  820  represents the signals  416   4  (e.g., q 4 ) as a function of time, and the waveform  822  represents the signal  414   4 (e.g., K 4 ) as a function of time. 
     As shown in  FIG. 7  and  FIG. 8 , if the demagnetization-detection signal  356  is at a logic low level (e.g., before t 8  as shown by the waveform  802 ), the signals  416   1 ˜ 416   n  (e.g., q 1 ˜q n , n is an integer) are all at the logic low level (e.g., as shown by the waveforms  808 ,  812 ,  816  and  820 ), while a signal  714  (e.g., q n_b ) generated by the NOT gate  712  is at a logic high level (e.g., as shown by the waveform  804 ). For example, if the demagnetization-detection signal  356  changes from the logic low level to the logic high level (e.g., at the beginning of a demagnetization period), the rising edge in the demagnetization-detection signal  356  (e.g., at t 8  as shown by the waveform  802 ) triggers the signal generator  702  which generates a pulse signal  716  (e.g., K 0 ) with a pulse width (e.g., T d ) as shown by the waveform  806 . In another example, a falling edge (e.g., at t 9 ) of the pulse signal  716  (e.g., K 0 ) triggers the flip-flop component  708   1  to change the signal  416   1  (e.g., q 1 ) from the logic low level to the logic high level (e.g., at t 9  as shown by the waveform  808 ). In yet another example, the rising edge in the signal  416   1  (e.g., q 1 ) triggers the signal generator  710   1  to generate a pulse in the signal  414   1  (e.g., K 1 ) with a pulse width (e.g., T d ) as shown by the waveform  810 . In yet another example, the falling edge of the pulse (e.g., at t 10 ) in the signal  414   1  (e.g., K 1 ) triggers the flip-flop component  708   2  to change the signal  416   2  (e.g., q 2 ) from the logic low level to the logic high level (e.g., at t 10  as shown by the waveform  812 ). In yet another example, the rising edge in the signal  416   2  (e.g., q 2 ) triggers the signal generator  710   2  to generate a pulse in the signal  414   2  (e.g., K 2 ) with a pulse width (e.g., T d ) as shown by the waveform  814 . Then, until the signal  416   n  (e.g., q n ) changes from the logic low level to the logic high level (e.g., at t 12  as shown by the waveform  820 ), the rising edge in the signal  416   n  (e.g., q n ) triggers the signal generator  710   n  to generate a pulse in the signal  414   n  (e.g., K n ) with a pulse width (e.g., T d ) as shown by the waveform  822 , in some embodiments. 
     According to another embodiment, if the signal  416   n  (e.g., q n ) is at the logic high level (e.g., between t 12  and t 13  as shown by the waveform  820 ), the signal  714  is at the logic low level (e.g., as shown by the waveform  804 ). For example, a falling edge of the pulse (e.g., at t 13 ) in the signal  414   n  (e.g., K n ) triggers the signal generator  708   1  to change the signal  416   1  (e.g., q 1 ) from the logic high level to the logic low level (e.g., at t 13  as shown by the waveform  808 ). In another example, the falling edge in the signal  416   1  (e.g., q 1 ) triggers the signal generator  710   1  to generate another pulse in the signal  414   1  (e.g., K 1 ) with a pulse width (e.g., T d ) as shown by the waveform  810 . In yet another example, the falling edge of the pulse (e.g., at t 14 ) in the signal  414   1  (e.g., K 1 ) triggers the flip-flop component  708   2  to change the signal  416   2  (e.g., q 2 ) from the logic high level to the logic low level (e.g., at t 14  as shown by the waveform  812 ). In yet another example, the falling edge in the signal  416   2  (e.g., q 2 ) triggers the signal generator  710   2  to generate another pulse in the signal  414   2  (e.g., K 2 ) with a pulse width (e.g., T d ) as shown by the waveform  814 . Then, until the signal  416   n  (e.g., q n ) changes from the logic high level to the logic low level (e.g., at t 15  as shown by the waveform  820 ), the falling edge in the signal  416   n  (e.g., q n ) triggers the signal generator  710   n  to generate another pulse in the signal  414   n  (e.g., K n ) with a pulse width (e.g., T d ) as shown by the waveform  822 , in certain embodiments. 
     The above-described process continues to operate until the demagnetization-detection signal  356  changes to the logic low level which indicates the end of the demagnetization period (e.g., at t 19  as shown by the waveform  802 ), according to some embodiments. For example, the signal generator  704  generates a signal  718  to reset (e.g., set to 0) the flip-flop components  708   1˜n  after a short delay (e.g., much shorter than T d  in duration). In another example, when the demagnetization-detection signal  356  changes to the logic high level again (e.g., at the beginning of a next demagnetization period), the above-described process starts again. 
       FIG. 11  is a simplified diagram showing the flip-latch component  408  as parts of the signal processing component  304  according to an embodiment of the present invention. This diagram is merely an example, which should not unduly limit the scope of the claims. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. The flip-latch component  408  includes flip-flop components  902   1 ˜ 902   n  (e.g., n is an integer). 
     According to one embodiment, if the demagnetization-detection signal  356  changes from a logic high level to a logic low level, the falling edge of the demagnetization-detection signal  356  triggers the flip-flop components  902   1 ˜ 902   n  to sample and hold the signals  416   1 ˜ 416   n  and outputs the signals  418   1 ˜ 418   n . For example, referring back to  FIG. 4  and  FIG. 6 , the signals  418   1 ˜ 418   n  are received by the encoding component  410  for generating the selection signals  420   1 ˜ 420   n  to select one of the signals  422   1 ˜ 422   n  to be held on the capacitor  608 . 
     According to another embodiment, the flip-latch component  408  includes four flip-flop components  902   1 ˜ 902   4 . For example, in response to the selection signals  420   1 ˜ 420   n , the select-and-hold component  406  is to select one of the signals  422   1 ˜ 422   n  associated with sampling the feedback signal  354  at a particular time. In another example, the select-and-hold component  406  selects one of the signals  422   1 ˜ 422   n  that is associated with sampling the feedback signal  354  two sampling periods (e.g., T d ) before the end of a demagnetization period (e.g., at point C as shown in  FIG. 7 ). A truth table representative of such selection is as follows, in some embodiments. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 Q 4   
                 Q 3   
                 Q 2   
                 Q 1   
                 S 4   
                 S 3   
                 S 2   
                 S 1   
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                   
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     According to another embodiment, a system controller for regulating a power conversion system includes a signal processing component and a driving component. The signal processing component is configured to receive a feedback signal associated with an output signal of a power conversion system and generate a first processed signal based on at least information associated with the feedback signal. The driving component is configured to generate a drive signal based on at least information associated with the first processed signal and output the drive signal to a switch in order to affect a primary current flowing through a primary winding, the drive signal being associated with a demagnetization period corresponding to a demagnetization process of the power conversion system. The signal processing component is further configured to, sample and hold the feedback signal a plurality of times during the demagnetization period to generate a plurality of sampled and held signals, select a signal from the plurality of sampled and held signals, hold the selected signal, and generate the first processed signal based on at least information associated the selected and held signal. For example, the system controller is implemented according to at least  FIG. 5 ,  FIG. 6 , and/or  FIG. 7 . 
     According to yet another embodiment, a signal processing device for regulating a power conversion system includes a sampling and holding component and a selection and holding component. The sampling and holding component is configured to sample and hold a feedback signal a plurality of times during a demagnetization period and generate a plurality of sampled and held signals based on at least information associated with the feedback signal, the feedback signal being associated with an output signal of a power conversion system, the demagnetization period corresponding to a demagnetization process of the power conversion system. The selection and holding component is configured to select a signal from the plurality of sampled and held signals, hold the selected signal, and output a first processed signal based on at least information associated with the selected and held signal for regulating the power conversion system. For example, the system controller is implemented according to  FIG. 5 ,  FIG. 6 ,  FIG. 7 ,  FIG. 8 ,  FIG. 9 ,  FIG. 10 , and/or  FIG. 11 . 
     In one embodiment, a method for regulating a power conversion system includes receiving a feedback signal associated with an output signal of a power conversion system, generating a processed signal based on at least information associated with the feedback signal, and generating a drive signal based on at least information associated with the processed signal. The method further includes outputting the drive signal to a switch in order to affect a primary current flowing through a primary winding, the drive signal being associated with a demagnetization period corresponding to a demagnetization process of the power conversion system. The process for generating a processed signal based on at least information associated with the feedback signal includes, sampling and holding the feedback signal a plurality of times during the demagnetization period to generate a plurality of sampled and held signals, selecting a signal from the plurality of sampled and held signals, holding the selected signal, and generating the processed signal based on at least information associated the selected and held signal. For example, the method is implemented according to at least  FIG. 5 ,  FIG. 6 , and/or  FIG. 7 . 
     In another embodiment, a method for regulating a power conversion system includes sampling and holding a feedback signal a plurality of times during a demagnetization period, the feedback signal being associated with an output signal of a power conversion system, the demagnetization period corresponding to a demagnetization process of the power conversion system, generating a plurality of sampled and held signals based on at least information associated with the feedback signal, and selecting a signal from the plurality of sampled and held signals. The method further includes holding the selected signal, and outputting a processed signal based on at least information associated with the selected and held signal for regulating the power conversion system. For example, the method is implemented according to  FIG. 5 ,  FIG. 6 ,  FIG. 7 ,  FIG. 8 ,  FIG. 9 ,  FIG. 10 , and/or  FIG. 11 . 
     For example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented using one or more software components, one or more hardware components, and/or one or more combinations of software and hardware components. In another example, some or all components of various embodiments of the present invention each are, individually and/or in combination with at least another component, implemented in one or more circuits, such as one or more analog circuits and/or one or more digital circuits. In yet another example, various embodiments and/or examples of the present invention can be combined. 
     Although specific embodiments of the present invention have been described, it will be understood by those of skill in the art that there are other embodiments that are equivalent to the described embodiments. Accordingly, it is to be understood that the invention is not to be limited by the specific illustrated embodiments, but only by the scope of the appended claims.