Patent Publication Number: US-7224202-B2

Title: Self-biased high voltage level shifter

Description:
FIELD OF THE INVENTION 
   The present invention relates to level shifters and, more particularly, a self-biased high voltage level shifter. 
   BACKGROUND OF THE INVENTION 
   Many integrated circuits, such as display drivers, require a combination of high-voltage driving capability (an output voltage swing up to 100V or more) and a digital control using standard 5V CMOS logic. Hence, complex level-shifting circuits are needed to convert the 5V control signals into the desired high-voltage output waveforms. Moreover, in many of those applications, the system is battery-powered and very severe constraints are put on the power consumption of the level-shifters. One application where both high-voltage driving capability and low power consumption are required in the design of driver chips is in automotive applications. 
   Level shifters, in general, are utilized in a circuit to transition from a low voltage signal to a high voltage signal. In the alternative, a level shifter may be used to transition from a high voltage signal to a low voltage signal. Level shifters are commonly used for multi-rail or multi-power supply designs, where multiple rails or multiple power supplies exist and numerous signals reference these multiple rails or power supplies. These signals interact with various logic blocks that operate on different power supplies. Thus, every time a high voltage signal is transferred to a low voltage block, the signal must be level-shifted. Similarly, in the alternative, when a low-voltage signal is transferred to a high voltage block, the signal must be level-shifted. 
   Most of the circuits in the automotive electronic systems are high voltage circuits. High voltage level shifters, however, are large. In addition, when there are a lot of signals that need to be level-shifted, it becomes very difficult to incorporate large level shifters in a system&#39;s design. Thus, to date, there has been no way of designing around the affects of incorporating high voltage level shifters in a system. In particular, high-voltage signals in a electronic system leads to high-voltage components which are larger than low-voltage components. Secondly, another deficiency of high-voltage level-shifters is that they are slow. Primarily, because the high-voltage components are large, these components cannot be switched as fast as low-voltage components. 
   Referring to known a high-voltage level-shifter  10  as is displayed  FIG. 1 , a low-voltage input signal IN 1  is level-shifted to an high voltage output signal Out 1 . Transistors, MN 1  and MN 2 , provide the level shifting function to shift a voltage applied at the input signal node IN 1  to a signal at the output node Out 1 . Transistors, MP 1  and MP 2 , protect the drain-to-source voltage V ds  and gate-to-source voltage V gs  of transistors, MP 4  and MP 3 . Diodes, D 2  and D 1 , only provide protection for the gate-to-source voltage V gs  of transistors, MP 2  and MP 1 . A high voltage reference HV ref1  is applied to gate of transistors, MP 2  and MP 1 , such that the source of each transistor, MP 2  and MP 1 , will not go one gate-to-source voltage V gs  above the HV ref1  signal. This design for a high voltage level-shifter is troublesome in that it requires a large and complex circuit to provide a high voltage reference HV ref1 . 
     FIG. 2  shows the another known level-shifter  20  that is self-biased, wherein a low-voltage input signal IN 2  is level shifted to an high voltage output signal Out 2 . Transistors, MN 3  and MN 4 , are switched on and off to provide the level-shifting feature of level-shifter  20 . Transistors, MP 6  and MP 5 , protect the drain-to-source voltage V ds  and gate-to-source voltage V gs  of transistors, MP 8  and MP 7 . As shown, a current source I 1  is pulled through two reverse bias Zener diodes, D 4  and D 3 , which have a 6.5V breakdown voltage for this particular technology. Those skilled in the art would recognize that even if a Zener diode has a 13V breakdown voltage, the only requirement is that the breakdown voltages of diodes, D 4  and D 3 , must correspond with the v gs  of transistors, MP 5  and MP 6 . Diodes, D 4  and D 3 , provide the high voltage reference signal which is applied to each gate of transistors, MP 5  and MP 6 , such that the source of each transistor, MP 5  and MP 6 , will not go one gate-to-source voltage V gs  above the high voltage reference signal. 
   The difference between the design of high voltage level-shifter  20  and the design of the level-shifter  10  in  FIG. 1  is the way in which the high voltage reference signal HV ref1  is generated. This approach, however, requires the external current source I 1 . 
   Thus, there exists a need for a self-biased high voltage level shifter that provides level shifting a low voltage signal (&lt;5V) to a high voltage signal (˜40V), with no static power dissipation while still protecting all devices. Furthermore, there exists a need for a simple, yet, cost-effective design that does not require an external current source. 
   The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above. 
   SUMMARY OF THE INVENTION 
   The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention. This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof. Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. 
   To address the above-discussed deficiencies of high voltage level shifters, the present invention teaches a high voltage level-shifter having a novel, simple design that provides level shifting a low voltage signal (&lt;5V) to a high voltage signal (˜40V), with no static power dissipation while still protecting all devices. 
   The high voltage level-shifter includes a resistor connected between a first node and a first power supply rail. An inverter couples to receive an input signal to provide an inverted input signal. A first circuit portion couples to receive the inverted input signal and connects between the first power supply rail and a second power supply rail for converting a high voltage signal into a low voltage signal. The first circuit portion includes a first clamp circuit, wherein the first circuit portion is biased through the first clamp circuit and the first node. A second circuit portion couples to receive the input signal and connects between the first power supply rail and a second power supply rail for converting a low voltage signal into a high voltage signal. The second circuit portion includes a second clamp circuit, wherein the second circuit portion is biased through the second clamp circuit and the first node. The second circuit portion provides a first internal bias for the first circuit portion and the first circuit portion provides a second internal bias for the second circuit portion. 
   The first circuit portion includes a first N-type transistor connected between a second node and a first power supply rail. The first N-type transistor is biased by the inverted input signal. A first P-type transistor connects between the second node and a fourth node. The first P-type transistor is biased by the first clamp circuit at the first node. A second P-type transistor connects between a second power supply rail and the fourth node which provides the output signal. The second P-type transistor is biased by the first internal bias provided by the second circuit portion. 
   The second circuit portion includes a first N-type transistor connected between a second node and a first power supply rail. The first N-type transistor is biased by the input signal. A first P-type transistor connects between the second node and a fourth node. The first P-type transistor is biased by the second clamp circuit at the first node. A second P-type transistor connects between a second power supply rail and the fourth node which provides the output signal. The second P-type transistor is biased by the second internal bias provided by the first circuit portion. 
   The first and second clamp circuits each may include a series connected pair of diodes, whereby the integrated bias current though each clamp circuit protects the first P-type transistor in each of the first and second circuit portions. 
   The advantages of this solution is that the implementation is smaller than previous solutions where there are fewer components tied to the power supply rail or battery. In addition, there is only static power dissipation when the voltage is above the clamp voltage. 
   The following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention. These are indicative of but a few of the various ways in which the principles of the invention may be employed. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     For a more complete understanding of the present invention and the advantages thereof, reference is now made to the following description taken in conjunction with the accompanying drawings in which like reference numbers indicate like features and wherein: 
       FIG. 1  is a known high voltage level-shifter; 
       FIG. 2  illustrates a known self-biased high voltage level-shifter; and 
       FIG. 3  displays a self-biased high voltage level-shifter in accordance with the present invention. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   One or more exemplary implementations of the present invention will now be described with reference to the attached drawings, wherein like reference numerals are used to refer to like elements throughout. The various aspects of the invention are illustrated below in a high voltage level shifter, although the invention and the appended claims are not limited to the illustrated examples. 
   The present invention is best understood by comparison with the prior art. Hence, this detailed description begins with a discussion of known high voltage level shifter as is shown in  FIG. 1 . As shown, a low-voltage input signal IN 1  is level-shifted to an high voltage output signal Out 1 . Transistors MN 2  and MN 1  are switched on and off, wherein when transistor MN 2  is on, transistor MN 1  is off. The converse is also true. In the instance, where input signal IN 1  is a high signal, transistor MN 1  will turn on. Current will flow through the drain node of transistor MN 1  which pull down the gate of transistor MP 4 . Since the gate of transistor MP 4  is pulled down, the gate-to-source voltage V gs  of transistor MP 4  opens up and turns on transistor MP 4  very hard, pulling the signal Out 1  up. Thereby, when the signal IN 1  goes high, the signal Out 1  goes up. When signal IN 1  goes low, transistor MN 2  turns on, wherein current flows through transistors, MP 2  and MP 3 . The purpose of transistors, MP 2  and MP 1 , is to protect the drain-to-source voltage V ds  and gate-to-source voltage V gs  of transistors, MP 4  and MP 3 . Diodes, D 2  and D 1 , only provide protection for the gate-to-source voltage V gs  of transistors, MP 2  and MP 1 . A high voltage reference HV ref1  is applied to gate of transistors, MP 2  and MP 1 , such that the source of each transistor, MP 2  and MP 1 , will not go one gate-to-source voltage V gs  above the HV ref1  signal. A large and complex circuit is conventional used to generate the high voltage reference HV ref1 . 
     FIG. 2  shows the another known self-biased level shifter, wherein a low-voltage input signal IN 2  is level shifted to an high voltage output signal Out 2 . Input signal IN 2  is inverted by inverter  22 . Signal IN 2  and the inverted version of signal IN 2  couples to the gate of transistors, MN 3  and MN 4 , respectively. Transistors, MN 3  and MN 4 , are switched on and off, wherein when transistor MN 3  is on, transistor MN 4  is off. Accordingly, the converse is true. When input signal IN 2  is a high signal, transistor MN 3  turns on. Current flows through the drain of transistor MN 3  which pull down the gate of transistor MP 8 . Since the gate of transistor MP 8  is pulled down, the gate-to-source voltage V gs  of transistor MP 8  opens up and turns transistor MP 8  on fully, pulling the signal Out 2  up. Thereby, when the input signal IN 2  goes high, the signal Out 2  increases. When signal IN 2  is low, transistor MN 4  turns on, wherein current flows through transistors, MP 6  and MP 7 . The purpose of transistors, MP 6  and MP 5 , is to protect the drain-to-source voltage V ds  and gate-to-source voltage V gs  of transistors, MP 8  and MP 7 . As shown a current source  11  is pulled through two reverse bias Zener diodes, D 4  and D 3 , which have a 6.5V breakdown voltage for this particular technology. Those skilled in the art would recognize that even if a Zener diode has a 13V breakdown voltage, the only requirement is that the breakdown voltages of diodes, D 4  and D 3 , must correspond with the V gs  of transistors, MP 6  and MP 5 . Diodes, D 4  and D 3 , provide the high voltage reference signal which is applied to each gate of transistors, MP 6  and MP 5 , such that the source of each transistor, MP 6  and MP 5 , will not go one gate-to-source voltage V gs  above the high voltage reference signal. The difference between this design and the design of the level-shifter in  FIG. 1  is the way in which the high voltage reference signal HV ref1  is generated. Optionally, a capacitor C 1  may AC couple the output Out 2  to ensure that there are no high voltage transients on the output signal Out 2  such that the output signal Out 2  is reflective of any changes in supply voltage V SS . This approach, however, has static power dissipation. In addition, this approach requires an external current source I 1 , wherein an ideal current source I 1  is utilized. In an actual application, however, no ideal current source exists, but rather current must be supplied external to the device. This requirement creates a substantial disadvantage for this design. 
     FIG. 3  illustrates a level shifting structure in accordance with the present invention. This high voltage level-shifter is self-biased and does not have the requirement of an external current source. This solution provides a novel circuit and method for setting up the high voltage reference. As opposed to  FIGS. 1 and 2 , this implementation does not need any external current reference nor a large amount of circuitry to set up a high voltage reference. 
   As shown, a low-voltage input signal IN 3  is level shifted to an high voltage output signal Out 3 . Input signal IN 3  is inverted by inverter  32 . Signal IN 3  and the inverted version of signal IN 3  couples to the gate of transistors, MN 5  and MN 6 , respectively. Transistors, MN 5  and MN 6 , are switched on and off, wherein when transistor MN 5  is on, transistor MN 6  is off. Accordingly, the converse is true. As such, transistors, MN 6  and MN 5 , perform the level-shifting function. The high voltage reference is set up on the gate of transistors, MP 9  and MP 10 , through diodes, D 5  and D 6 , or D 7  and Dg, respectively, which are reversed biased through the resistor R 1 . If input signal IN 3  is high, transistor MN 6  will turn on and pull the gate of transistor MP 11  low which is connected to the drain of transistor MP 12 . Thereby transistor MP 11  turns on and current flows through transistor MP 11 . This pulls the drain of transistor MP 11  high. The drain of transistor MP 11  will only increase as high as the Zener breakdown of diodes, D 5  and D 6 , allow it to increase. Once the breakdown of the transistors that make up diodes, D 5  and D 6 , are met, current begins to flow through diodes, D 5  and D 6 , which is limited by resistor R 1 . 
   In the alternative, when input signal IN 3  is low, transistor MN 11  will turn on and pull the gate of transistor MP 12  low which is connected to the drain of transistor MP 11 . Thereby, transistor MP 12  turns on and current flows through transistor MP 12 . As a result, the drain of transistor MP 12  is pulled high. The drain of transistor MP 12 , however, will only increase as high as the Zener breakdown of diodes, D 7  and D 8 , allow it to increase. Once the breakdown of the transistors that make up diodes, D 7  and D 8 , are met, current begins to flow through diodes, D 7  and D 8 , which is limited by resistor R 1 . Thereby, transistors, MP 9  and MP 10 , will always be protected because transistors, MN 5  and MN 6 , are always on and out of phase. This guarantees a high voltage reference at all times. 
   Specifically, the high voltage reference is set up using resistor R 1  connected to diodes, D 5  and D 6 , or, in the alternative, diodes, D 7  and D 8 . Particularly, as soon as the reverse breakdown of diodes, D 5  and D 6 , is met, current flows through the diodes, D 5  and D 6 , and through the resistor R 1  which sets up a voltage at the gate of transistor MP 9 . This voltage is related to the reverse breakdown of the Zener diodes, D 5  and D 6 . Therefore, as the voltage at the drain of transistor MP 1 , increases, the breakdown of the two diodes, D 5  and D 6 , is met. As a result, current begins to flow through diodes, D 5  and D 6 , and the gate of transistor MP 9  begins to rise. For example, if the voltage at the drain of transistor MP 11 , rises to 50V, the gate of transistor MP 9  would only be 13V below 50V. In the alternative, for example, if the voltage at the drain of transistor MP 11  decreases to another voltage, the gate of transistor MP 9  would only be 13V below the same voltage at the drain of transistor MP 11 . 
   In the alternative, the high voltage reference is set up using resistor R 1  connected to diodes, D 7  and D 8 . Specifically, as soon as the reverse breakdown of diodes, D 7  and D 8 , is met, current flows through the diodes, D 7  and D 8 , and through the resistor R 1  which sets up a voltage at the gate of transistor MP 10 . This voltage is related to the reverse breakdown of the Zener diodes, D 7  and D 8 . Therefore, as the voltage at the drain of transistor MP 12  increases, the breakdown of the two diodes, D 7  and D 8 , is met, current begins to flow through the diodes, D 7  and D 8 , and the gate of transistor MP 10  begins to rise. If the voltage at the drain of transistor MP 12 , for example, rises to 50V, the gate of transistor MP 10  would only be 13V below 50V. If the voltage at the drain of transistor MP 12 , for example, decreases to another voltage, the gate of transistor MP 10  would only be 13V below the same voltage at the drain of transistor MP 12 . 
   Advantages of the high voltage level shifter in accordance with the present invention include, but are not limited to, a high voltage level-shifter having a cost effective design that chip architecture (or real estate) and power. The high voltage level-shifter in accordance with the present invention is smaller than previous solutions where there are fewer components tied to the power supply rail or battery. In addition, there is only static power dissipation when the voltage is above the clamp voltage. 
   While the principles of the present invention have been demonstrated with particular regard to the structures and methods disclosed herein, it will be recognized that various departures may be undertaken in the practice of the invention. The scope of the invention is not intended to be limited to the particular structures and methods disclosed herein, but should instead be gauged by the breadth of the claims that follow. 
   Those of skill in the art will recognize that the physical location of the elements illustrated in  FIG. 3  can be moved or relocated while retaining the function described above. 
   The reader&#39;s attention is directed to all papers and documents which are filed concurrently with this specification and which are open to public inspection with this specification, and the contents of all such papers and documents are incorporated herein by reference. 
   All the features disclosed in this specification (including any accompany claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise. Thus, unless expressly stated otherwise, each feature disclosed is one example only of a generic series of equivalent or similar features. 
   The terms and expressions which have been employed in the foregoing specification are used therein as terms of description and not of limitation, and there is no intention in the use of such terms and expressions of excluding equivalents of the features shown and described or portions thereof, it being recognized that the scope of the invention is defined and limited only by the claims which follow.