Patent Publication Number: US-6987704-B2

Title: Synchronous semiconductor memory device with input-data controller advantageous to low power and high frequency

Description:
FIELD OF THE INVENTION 
   The present invention relates to a semiconductor memory device, and more particularly, to a memory device with an input-data controller, which is advantageous to low power and high-speed operation. 
   DESCRIPTION OF THE PRIOR ART 
   With the increase of semiconductor integration, semiconductor memory devices have been steadily improved in order to increase an operating speed. For the purpose of increasing the operating speed, so-called synchronous memory devices have been proposed which are operable in synchronization with clocks provided from an exterior of a memory chip. 
   An initially proposed memory device is a single data rate (SDR) synchronous memory device which inputs/outputs one data through one data pin at one cycle of clock in synchronization with a rising edge of an external clock. 
   However, such an SDR synchronous memory device is still insufficient to satisfy a desired speed in a system that requires a high-speed operation. Accordingly, a double data rate (DDR) synchronous memory device is proposed which process two data at one cycle of clock. 
   The DDR synchronous memory device inputs/outputs successively two data through data I/O pins in synchronization with both rising edges and falling edges of the external clock. Therefore, compared with a conventional SDR synchronous memory device, the DDR synchronous memory device can provide at least two times bandwidths without increasing a frequency of the clock, thereby implementing a high-speed operation as much. 
   Meanwhile, since the DDR synchronous memory device must input or output two data at one cycle of the clock, it is impossible to employ data access method that has been used to effectively perform the input or output operation in the conventional SDR synchronous memory device. 
   If a cycle of a clock is about 10 nsec, two data must be processed successively within substantially 6 nsec, which is a time except for rising and falling times (about 0.5×4=2) and other time for specification. However, it is almost hard to perform these processes within the memory device. Accordingly, the memory device inputs/outputs data at rising edges and falling edges of the clock only when inputting/outputting data from/to an exterior of the memory device, and other processes in an inside of the memory device are performed in synchronization with either rising edges or falling edges. 
   Therefore, a new method for inputting/outputting data is required in order to receive and transfer the data to an internal core area or externally output the data transferred from the core area. 
   For this purpose, a data input buffer of the DDR synchronous memory device prefetches 2-bit data synchronized with rising edges and falling edges. The prefetched 2-bit data are then synchronized as even data and odd data at rising edges of a main clock and transferred to the internal core area. Meanwhile, in order to implement an accurate timing of data input/output, data strobe signal (DQS) is inputted from a CPU or a memory controller together with the data signal when receiving data. 
   However, as a speed of a system such as a central processing unit becomes increasingly higher, the memory device needs to be operated much higher. In order to achieve this purpose, there is proposed a 4-bit prefetch data input buffer which prefetches and transfers 4-bit data to an inside of the memory device. 
     FIG. 1  is a block diagram showing a 4-bit prefetch data input unit of a conventional synchronous memory device. 
   Referring to  FIG. 1 , the 4-bit prefetch data input unit of the conventional synchronous memory device includes: a data strobe buffer unit  19  which is enabled in response to an enable signal endinds generated by a write command and outputs rising pulses dsrp 4  and falling pulses dsfp 4  generated at rising edges and falling edges of the data strobe signal DQS; a data buffer unit  10  for receiving data through a data pin DQ from an outside; a data alignment unit  80  for aligning data which are buffered in the data buffer unit  10  and inputted successively and outputting first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1 ; a global I/O line driving unit  20  for receiving the first and fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  and outputting first and second even data gio — ev 0  and gio — ev 1  or first and second odd data gio — od 0  and gio — od 1  to a global I/O line in response to even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;; and a data input strobe signal generating unit  90  for generating the even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb od 1 &lt; 0 : 3 &gt;. In  FIG. 1 , a data input strobe precharge signal dinstb — pcg&lt; 0 : 3 &gt; is a control signal for activating the global I/O line driving unit  20 . 
     FIG. 2A  is a block diagram of the data alignment unit  80  shown in  FIG. 1 . 
   Referring to  FIG. 2A , the data alignment unit  80  includes: a first rising latch  11  for latching data outputted from the data buffer unit  10  and outputting a first rising data rising — d 0  in response to the rising pulse dsrp 4 ; a second rising latch  12  for latching the first rising data rising — d 0  to output the third aligned data align — dr 1  in response to the falling pulse dsfp 4 ; a third rising latch  14  for latching the third aligned data align — dr 1  to output a second rising data rising — d 1  in response to the rising pulse dsrp 4 ; a fourth rising latch  16  for latching the second rising data rising — d 1  to output the first aligned data align — dr 0  in response to the falling pulse dsfp 4 ; a first falling latch  13  for latching data outputted from the data buffer unit  10  to output the fourth aligned data align — df 1  in response to the falling pulse dsfp 4 ; a second falling latch  15  for latching the fourth aligned data align — df 1  to output a falling data falling — d 1  in response to the rising pulse dsrp 4 ; and a third falling latch  17  for latching the falling data falling — d 1  to output the second aligned data align — df 0  in response to the falling pulse dsfp 4 . 
     FIG. 2B  is a block diagram of the global I/O line driving unit  20  shown in  FIG. 1 . 
   Referring to  FIG. 2B , the global I/O line driving unit  20  includes: a first even data global I/O line driver  20   —   1   a  for receiving the first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  to output the first even data gio — ev 0  in response to the first even and odd data input strobe signals dinstb — ev 0 &lt; 0 &gt;, dinstb — ev 1 &lt; 0 &gt;, dinstb — od 0 &lt; 0 &gt; and dinstb — od 1 &lt; 0 &gt;; a first odd data global I/O line driver  20   —   1   b  for receiving the first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  to output the first odd data gio — od 0  in response to the second even and odd data input strobe signals dinstb — ev 0 &lt; 1 &gt;, dinstb — ev 1 &lt; 1 &gt;, dinstb — od 0 &lt; 1 &gt; and dinstb — od 1 &lt; 1 &gt;; a second even data global I/O line driver  20   —   1   c  for receiving the first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  to output the second even data gio — ev 1  in response to the third even and odd data input strobe signals dinstb — ev 0 &lt; 2 &gt;, dinstb — ev 1 &lt; 2 &gt;, dinstb — od 0 &lt; 2 &gt; and dinstb — od 1 &lt; 2 &gt;; and a second odd data global I/O line driver  20   —   1   d  for receiving the first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  to output the second odd data gio — od 1  in response to the fourth even and odd data input strobe signals dinstb — ev 0 &lt; 3 &gt;, dinstb — ev 1 &lt; 3 &gt;, dinstb — od 0 &lt; 3 &gt; and dinstb — od 1 &lt; 3 &gt;. 
   Meanwhile, a typical memory device includes a plurality of input pins and receives a plurality of data in parallel at the same time. For this purpose, the memory device includes a plurality of data buffer units and data alignment units, which buffer and align data inputted through a plurality of data input pins. 
     FIG. 3  is a block diagram showing a plurality of global I/O line driving units for receiving and buffering data inputted through a plurality of data input pins to output even data and odd data in a memory device. 
   Referring to  FIG. 3 , the memory device includes: a first global I/O line driving unit  20   —   1  for receiving first to fourth aligned data align — dr 0 &lt; 0 &gt;, align — df 0 &lt; 0 &gt;, align — dr 1 &lt; 0 &gt; and align — df 1 &lt; 0 &gt;, which are inputted through a first data input pin DQ 0 , buffered by a first data buffer unit  70   —   1  and aligned by a first data alignment unit  30   —   1 , and outputting first and second even data gio — ev 0 &lt; 0 &gt; and gio — ev 1 &lt; 0 &gt; or first and second odd data gio — od 0 &lt; 0 &gt; and gio — od 1 &lt; 0 &gt; in response to even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;; a second global I/O line driving unit  20   —   2  for receiving first to fourth aligned data align — dr 0 &lt; 1 &gt;, align — df 0 &lt; 1 &gt;, align — dr 1 &lt; 1 &gt; and align — df 1 &lt; 1 &gt;, which are inputted through a second data input pin DQ 1 , buffered by a second data buffer unit  70   —   2  and aligned by a second data alignment unit  30   —   2 , and outputting first and second even data gio — ev 0 &lt; 1 &gt; and gio — ev 1 &lt; 1 &gt; or first and second odd data gio — od 0 &lt; 1 &gt; and gio — od 1 &lt; 1 &gt; in response to the even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;; and an n-th global I/O line driving unit  20   — n for receiving first to fourth aligned data align — dr 0 &lt;n&gt;, align — df 0 &lt;n&gt;, align — dr 1 &lt;n&gt; and align — df 1 &lt;n&gt;, which are inputted through an n-th data input pin DQn, buffered by an n-th data buffer unit  70   — n and aligned by an n-th data alignment unit  30   — n, and outputting first and second even data gio — ev 0 &lt;n&gt; and gio — ev 1 &lt;n&gt; or first and second odd data gio — od 0 &lt;n&gt; and gio — od 1 &lt;n&gt; in response to the even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;. 
   Here, the data alignment units  70   —   1  to  70   — n are a block that includes the rising latches and the falling latches shown in  FIG. 2A  and aligns the data, which are inputted successively through the respective data buffer units, into the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1 . 
     FIG. 4  is a block diagram of the data input strobe signal generating unit  90  shown in  FIG. 1 . 
   Referring to  FIG. 4 , the data input strobe signal generating unit  90  includes: a clock pulse signal generator  60  for receiving a clock signal CLK to generate a clock pulse signal dinclkp; a write address decoder  50  for decoding first and second address signals sosez 0   — wt and sosez 1   — wt, which are lower bit (address 0 and address 1) signals of addresses inputted corresponding to a write command for a data write operation, and outputting first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;; a first even data input strobe signal generator  41  for outputting first even and odd data input strobe signals dinstb — ev 0 &lt; 0 &gt;, dinstb — ev 1 &lt; 0 &gt;, dinstb — od 0 &lt; 0 &gt; and dinstb — od 1 &lt; 0 &gt; in response to the data select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, which are outputted from the write address decoder  50 , in synchronization with the clock pulse signal dinclkp; a first odd data input strobe signal generator  42  for outputting second even and odd data input strobe signals dinstb — ev 0 &lt; 1 &gt;, dinstb — ev 1 &lt; 1 &gt;, dinstb — od 0 &lt; 1 &gt; and dinstb — od 1 &lt; 1 &gt; in response to the data select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, which are outputted from the write address decoder  50 , in synchronization with the clock pulse signal dinclkp; a second even data input strobe signal generator  43  for outputting third even and odd data input strobe signals dinstb — ev 0 &lt; 2 &gt;, dinstb — ev 1 &lt; 2 &gt;, dinstb — od 0 &lt; 2 &gt; and dinstb — od 1 &lt; 2 &gt; in response to the data select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, which are outputted from the write address decoder  50 , in synchronization with the clock pulse signal dinclkp; and a second odd data input strobe signal generator  44  for outputting fourth even and odd data input strobe signals dinstb — ev 0 &lt; 3 &gt;, dinstb — ev 1 &lt; 3 &gt;, dinstb — od 0 &lt; 3 &gt; and dinstb — od 1 &lt; 3 &gt; in response to the data select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, which are outputted from the write address decoder  50 , in synchronization with the clock pulse signal dinclkp. 
   Here, a control signal seq — intz shown in  FIG. 4  is a signal determined by a set information of a mode register set at an initialization period of the memory device. In case of a sequential mode, the control signal seq — intz maintains a high level, and in case of an interleave mode, the control signal seq — intz maintains a low level. The “sequential” or “interleave” type represents a data input pattern. For example, if data is inputted in order of D 0 , D 1 , D 2  and D 3  in the sequential mode, data is inputted in order of D 0 , D 3 , D 2  and D 1  in the interleave mode. 
     FIG. 5  is a circuit diagram of the clock pulse signal generator shown in  FIG. 4 . 
   Referring to  FIG. 5 , the clock pulse signal generator  60  includes: an inverter I 1  for inverting the clock signal clk; a delay unit  61  for delaying an output of the inverter I 1  for a predetermined time; a NOR gate NOR 1  receiving the output of the inverter I 1  and an output of the delay unit  61 ; an inverter I 2  for inverting an output of the NOR gate NOR 1 ; and an inverter I 3  for inverting an output of the inverter I 2  to output the clock pulse signal dinclkp. 
     FIG. 6  is a circuit diagram of the write address decoder shown in  FIG. 4 . 
   Referring to  FIG. 6 , the write address decoder  50  includes: an inverter I 4  for inverting the first address signal sosez 0   — wt to output a first decoding signal sesoz 0   — wt; an inverter I 5  for inverting the second address signal sosez 1   — wt to output a second decoding signal sesoz 1   — wt; a NAND gate ND 1  receiving the first and second decoding signals sesoz 0   — wt and sesoz 1   — wt; an inverter I 6  for inverting an output of the NAND gate ND 1  to output the first data input strobe select signal sosez 01 wt&lt; 0 &gt;; a NAND gate ND 2  receiving the first address signal sosez 0   — wt and the second decoding signal sesoz 1   — wt; an inverter I 7  for inverting an output of the NAND gate ND 2  to output the second data input strobe select signal sosez 01 wt&lt; 1 &gt;; a NAND gate ND 3  receiving the first decoding signal sesoz 0   — wt and the second address signal sosez 1   — wt; an inverter I 8  for inverting an output of the NAND gate ND 3  to output the third data input strobe select signal sosez 01 wt&lt; 2 &gt;; a NAND gate ND 4  receiving the first and second address signal sosez 0   — wt and sesoz 1   — wt; and an inverter I 9  for inverting an output of the NAND gate ND 4  to output the fourth data input strobe select signal sosez 01 wt&lt; 3 &gt;. 
     FIG. 7  is a circuit diagram of the first even data input strobe signal generator  41  shown in  FIG. 4 . 
   Referring to  FIG. 7 , the first even data input strobe signal generator  41  includes: a NAND gate ND 5  receiving the first data input strobe select signal sosez 01 wt&lt; 0 &gt; and the clock pulse signal dinclkp; a NAND gate ND 6  receiving the fourth data input strobe select signal sosez 01 wt&lt; 3 &gt; and the clock pulse signal dinclkp; a NAND gate ND 9  receiving outputs of the NAND gates ND 5  and ND 6  to output a first precharge signal eo 0 ; an inverter I 10  for inverting an output of the NAND gate ND 5  to output the first even data input strobe signal dinstb — ev 0 &lt; 0 &gt;; an inverter I 11  for inverting the output of the NAND gate ND 6  to output the first odd data input strobe signal dinstb — odd 0 &lt; 0 &gt;; a NAND gate ND 7  receiving the third data input strobe select signal sosez 01 wt&lt; 2 &gt; and the clock pulse signal dinclkp; a NAND gate ND 8  receiving the second data input strobe select signal sosez 01 wt&lt; 1 &gt; and the clock pulse signal dinclkp; a NAND gate ND 10  receiving outputs of the NAND gates ND 7  and ND 8  to output a second precharge signal eo 1 ; an inverter I 12  for inverting the output of the NAND gate ND 7  to output the second even data input strobe signal dinstb — ev 1 &lt; 0 &gt;; an inverter I 13  for inverting the output of the NAND gate ND 8  to output the second odd data input strobe signal dinstb — od 1 &lt; 0 &gt;; a NOR gate NOR 2  receiving the first and second precharge signals eo 0  and eo 1 ; and an inverter I 14  for inverting an output of the NOR gate NOR 2  to output the first data input strobe precharge signal dinstb — pcg&lt; 0 &gt;. 
   Meanwhile, as shown in  FIG. 4 , the second even data input strobe signal generator  43  is configured with the same structure as the first even data input strobe signal generator  41  except for the even and odd data input strobe signals dinstb — ev 0 &lt; 2 &gt;, dinstb — od 0 &lt; 2 &gt;, dinstb — ev 1 &lt; 2 &gt; and dinstb — od 1 &lt; 2 &gt; that are outputted in a sequence of the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;. Therefore, a description and a drawing of the second even data input strobe signal generator  43  will be omitted. 
     FIG. 8  is a circuit diagram of the first odd data input strobe signal generator  42  shown in  FIG. 4 . 
   Referring to  FIG. 8 , the first odd data input strobe signal generator  42  includes: transmission gates T 1  and T 2  that are selectively turned on in response to the control signal seq — intz, which maintains a low level in the interleave mode and a high level in the sequential mode, to transmit the first data input strobe select signal sosez 01 wt&lt; 0 &gt; or the third data input strobe select signal sosez 01 wt&lt; 2 &gt;; transmission gates T 3  and T 4  that are selectively turned on in response to the control signal seq — intz to transmit the first data input strobe select signal sosez 01 wt&lt; 0 &gt; or the third data input strobe select signal sosez 01 wt&lt; 2 &gt;; a NAND gate ND 9  receiving the second data input strobe select signal sosez 01 wt&lt; 1 &gt; and the clock pulse signal dinclkp; a NAND gate ND 10  receiving the clock pulse signal dinclkp and the data input strobe select signal sosez 01 wt&lt; 0 &gt; or sosez 01 wt&lt; 2 &gt; transmitted from the transmission gate T 1  or T 2 ; a NAND gate ND 13  for receiving outputs of the NAND gates ND 10  and ND 9  to output a first precharge signal eo 2 ; an inverter I 15  for inverting the output of the NAND gate ND 9  to output the first even data input strobe signal dinstb — ev 0 &lt; 1 &gt;; an inverter I 16  for inverting the output of the NAND gate ND 10  to output the first odd data input strobe signal dinstb — od 0 &lt; 1 &gt;; a NAND gate ND 11  receiving the fourth data input strobe select signal sosez 01 wt&lt; 3 &gt; and the clock pulse signal dinclkp; a NAND gate ND 12  receiving the clock pulse signal dinclkp and the data input strobe select signal sosez 01 wt&lt; 0 &gt; or sosez 01 wt&lt; 2 &gt; transmitted from the transmission gate T 3  or T 4 ; a NAND gate ND 14  receiving outputs of the NAND gates ND 12  and ND 11  to output a second precharge signal eo 3 ; an inverter I 17  for inverting the output of the NAND gate ND 11  to output the second even data input strobe signal dinstb — ev 1 &lt; 1 &gt;; an inverter I 18  for inverting the output of the NAND gate ND 12  to output the second odd data input strobe signal dinstb — od 1 &lt; 1 &gt;; a NOR gate NOR 3  receiving the first and second precharge signals eo 2  and eo 3 ; and an inverter I 19  for inverting an output of the NOR gate NOR 3  to output the second data input strobe precharge signal dinstb — pcg&lt; 1 &gt;. 
   Meanwhile, as shown in  FIG. 4 , the second odd data input strobe signal generator  44  is configured with the same structure as the first odd data input strobe signal generator  42  except for the even and odd data input strobe signals dinstb — ev 0 &lt; 3 &gt;, dinstb — od 0 &lt; 3 &gt;, dinstb — ev 1 &lt; 3 &gt; and dinstb — od 1 &lt; 3 &gt; that are outputted in a sequence of the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;. Therefore, a description and a drawing of the second odd data input strobe signal generator  43  will be omitted. 
     FIG. 9  is a waveform showing an alignment of four data in the memory device of  FIG. 1 . Hereinafter, an operation of aligning four data inputted through one data input pin DQ will be described with reference to  FIGS. 1 to 9 . 
   First, data D 0  to D 7  are inputted in synchronization with the rising and falling edges of the clock signal CLK, and clocking data strobe signal DQS are then inputted at a timing at which the data are inputted. 
   The data strobe buffer unit  190  is enabled in response to the enable signal endinds generated by the write command and generates the rising pulse dsrp 4  and the falling pulse dsfp 4 , which are respectively outputted in pulse forms at the rising edges and the falling edges of the data strobe signal DQS. 
   Then, the first rising latch  11  latches the first, third, fifth and seventh data D 0 , D 2 , D 4  and D 6  and outputs the first rising data rising — d 0  in synchronization with the rising pulse dsrp 4 . 
   The second rising latch  12  latches the first rising data rising — d 0  and outputs the third aligned data align — dr 1  in synchronization with the falling pulse dsfp 4 , and the first falling latch  13  latches the second, fourth, sixth and eighth data D 1 , D 3 , D 5  and D 7  and outputs the fourth aligned data align — df 1  in synchronization with the falling pulse dsfp 4 . 
   Then, the third rising latch  14  latches the third aligned data align — dr 1  and outputs the second rising data rising — d 1  in synchronization with the rising pulse dsrp 4 , and the second falling latch  15  latches the fourth aligned data align — df 1  and outputs the falling data falling — d 1  in synchronization with the rising pulse dsrp 4 . 
   The fourth rising latch  16  latches the second rising data rising — d 1  and outputs the first aligned data align — dr 0  in synchronization with the falling pulse dsfp 4 , and the third falling latch  17  latches the falling data falling — d 1  and outputs the second aligned data align — df 0 . 
   Then, the global I/O line driving unit  20  receives the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  and outputs the first and second even data gio — ev 0  and gio — ev 1  or the first and second odd data gio — od 1  and gio — od 1  in response to the first and second even data strobe signals dinstb — ev 0 &lt; 0 : 3 &gt; and dinstb — ev 1 &lt; 0 : 3 &gt; and the first and second odd data strobe signals dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;. 
     FIG. 10  is a waveform showing an operation of generating the data input strobe signals and an operation of inputting the four aligned data through the global I/O line driving unit in response to the data input strobe signals in the conventional memory device. 
   Hereinafter, the operation of generating the data input strobe signals and the operation of inputting the four aligned data through the global I/O line driving unit in response to the data input strobe signals will be described with reference to  FIGS. 1 to 10 . 
   First, the write commands wt 0  and wt 1  are inputted, and the data D 0  to D 7  synchronized with the addresses and the clock signal CLK are then inputted in response to the write commands wt 0  and wt 1 . Here, the data D 0  to D 3  are inputted in response to the write command wt 0  and the data D 4  to D 7  are inputted in response to the write command wt 1 . Meanwhile, the control signal wtrzt is a signal that maintains a high level during the write operation. 
   Then, the clock pulse signal generator  60  shown in  FIG. 4  receives the clock signal CLK to generate the clock pulse signal dinclkp in a pulse form. The write address decoder  50  decodes the first and second address signals sosez 0   — wt and sosez 1   — wt to output the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;. Here, the first and second address signals sosez 0   — wt and sosez 1   — wt are signals generated by buffering last 2-bit address signals address 0  and address 1  among the addresses inputted in response to the write commands. 
   As shown, in case the first and second address signals sosez 0   — wt and sosez 1   — wt are the low level at a period “A”, the first data input strobe select signal sosez 01 wt&lt; 0 &gt; among the data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt; maintains a high level and the remaining data input strobe select signals sosez 01 wt&lt; 1 &gt; to sosez 01 wt&lt; 3 &gt; maintain the low level. 
   Here, the period “A” is a period at which the address signal inputted in response to the write command wt 0  is decoded to output the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, and the period “B” is a period at which the address signal inputted in response to the write command wt 1  is decoded to output the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;. 
   Then, the first even data input strobe signal generator  41  receives the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt; from the write address decoder  50  and outputs the first and second even data input strobe signals dinstb — ev 0 &lt; 0 &gt; and dinstb — ev 1 &lt; 0 &gt; and the first and second odd data input strobe signals dinstb — od 0 &lt; 0 &gt; and dinstb — od 1 &lt; 0 &gt; in response to the clock pulse signal dinclkp. 
   Specifically, in the first even data input strobe signal generator  41 , the four NAND gates ND 5  to ND 8  are selected in response to the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;, and the clock pulse signal dinclkp is outputted as the selected input strobe signal (e.g., the first even data input strobe signal dinstb — ev 0 &lt; 0 &gt;) through the selected NAND gate (e.g., ND 5 ). 
   Additionally, the remaining data input strobe signals dinstb — ev 1 &lt; 0 &gt;, dinstb — od 0 &lt; 0 &gt; and dinstb — od 1 &lt; 0 &gt; are maintained at the low level. 
   Here, the first data input strobe precharge signal dinstb — pcg&lt; 0 &gt; is a signal for enabling the first even data global I/O line driver  20   —   1   a  and generated by the control signals eo 0  and eo 1 . At least one of the control signals eo 0  and eo 1  maintains the high level if any one of the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt; maintains the high level. 
   Meanwhile, the first odd data input strobe signal generator  42  operates in the same manner as the first even data input strobe signal generator  41 . The first odd data input strobe signal generator  42  receives the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt; and outputs the first and second even data input strobe signals dinstb — ev 0 &lt; 1 &gt; and dinstb — ev 1 &lt; 1 &gt; and the first and second odd data input strobe signals dinstb — od 0 &lt; 1 &gt; and dinstb — od 1 &lt; 1 &gt; in response to the clock pulse signal dinclkp. 
   At this time, the first data input strobe select signal sosez 01 wt&lt; 0 &gt; of a high level is inputted and the NAND gate ND 10  is selected. Then, the clock pulse signal dinclkp is outputted as the first odd data input strobe signal dinstb — od 0 &lt; 1 &gt;. As described above, the control signal seq — intz is a signal determined by the data type. In other words, in case of the sequential mode, the control signal seq — intz maintains the high level, and in case of the interleave mode, the control signal seq — intz maintains the low level. The second data input strobe precharge signal dinstb — pcg&lt; 1 &gt; for enabling the first odd data global I/O line driver  20   —   1   b  is outputted. The second data input strobe precharge signal dinstb — pcg&lt; 1 &gt; is generated by the control signals eo 2  and eo 3 . 
   Additionally, the second even data input strobe signal generator  43  and the second odd data input strobe signal generator  44  operate in the same manner as the first even data strobe signal generator  41  and the first odd data input strobe signal generator  42  except for a sequence of the first to fourth data input strobe select signals sosez 01 wt&lt; 0 &gt; to sosez 01 wt&lt; 3 &gt;. 
   As shown in  FIG. 10 , the second even data input strobe signal generator  43  clocks the second even data input strobe signal dinstb — ev 1 &lt; 2 &gt;, and the second odd data input strobe signal generator  44  clocks the second odd data input strobe signal dinstb — od 1 &lt; 3 &gt;. Meanwhile, the first to fourth data input strobe precharge signals dinstb — pcg&lt; 0 &gt; to dinstb — pcg&lt; 3 &gt; are used as the enable signals of the global I/O line drivers  20   —   1   a  to  20   —   1   d  shown in  FIG. 2B . 
   The first even data global I/O line driver  20   —   1   a  shown in  FIG. 2B  receives the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  inputted from the first data alignment unit  30   —   1  and outputs the data D 0  as the first even data gio — ev 0 , in which the data D 0  is selected by the first even data input strobe signal dinstb — ev 0 &lt; 0 &gt;. 
   The second even data global I/O line driver  20   —   1   c  receives the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  inputted from the first data alignment unit  30   —   1  and outputs the data D 2  as the second even data gio — ev 1 , in which the data D 2  is selected by the second even data input strobe signal dinstb — ev 1 &lt; 2 &gt;. 
   In the first and second odd data global I/O line drivers  20   —   1   b  and  20   —   1   d , the data D 1  and D 3  selected by the first and second odd data input strobe signals dinstb — od 0 &lt; 1 &gt; and dinstb — od 0 &lt; 3 &gt; are outputted as the first and second odd data gio — od 0  and gio — od 1 . The first and second even data gio — ev 0  and gio — ev 1  and the first and second odd data gio — od 0  and gio — od 1  are transferred to a cell block of the memory and stored into the corresponding unit cells. 
   Additionally, the period “B” is a period at which the first and second address signals sosez 0   — wt and sosez 1   — wt corresponding to the write command wt 1  are inputted and decoded. Since the operation at the period “B” is performed in the same manner as the operation at the period “A”, a detailed description of the operation at the period “B” will be omitted. 
     FIGS. 11A and 11B  are waveforms showing a problem of the conventional memory device. Here,  FIG. 11   a  is a waveform showing a data write operation when a write command is inputted successively, and  FIG. 11B  is a waveform showing a data write operation when a write command is inputted at an interval of one clock. 
   As described above, according to the conventional memory device, the data D 0  to D 7  inputted in synchronization with the clock signal CLK during a write operation are aligned and selected as the even data gio — ev 0  and gio — ev 1  or the odd data gio — od 0  and gio — od 1  in response to the data input strobe signal dinstb — ?, and then transferred to the internal cell block. Here, the data input strobe signal dinstb — ? is one of the first and second even data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt; and dinstb — ev 1 &lt; 0 : 3 &gt; and the first and second odd data input strobe signals dinstb — od 0 &lt; 0 : 3 &gt; and dinstb — od 1 &lt; 0 : 3 &gt;. 
   Here, in  FIG. 11A , only the third and fifth data input strobe signals dinstb — ? are actually used during the data write operation, and in  FIG. 11B , only the third and sixth data input strobe signals dinstb — ? are actually used during the data write operation. 
   However, even when the data input strobe signal dinstb — ? is not required, the clocking is performed continuously, thereby causing an unnecessary power consumption. 
   Meanwhile, the data input strobe signal dinstb — ? must maintain a predetermined timing T 1  with respect to a period at which the first and second address signals sosez 0   — wt and sosez 1   — wt are inputted. However, it is very difficult to maintain the timing T 1  in the structure in which the data input strobe signal dinstb — ? is continuously clocked regularly. 
   Accordingly, in order to solve the problem, the first and second address signals sosez 0   — wt and sosez 1   — wt are delayed for a predetermined time to match them with the timing of the data input strobe signal dinstb — ?. However, as the operating frequency of the memory device becomes higher, it is more difficult to match the first and second address signals sosez 0   — wt and sosez 1   — wt with the timing of the data input strobe signal dinstb — ?. Therefore, the possibility of malfunctions increases much more. 
   Additionally, as shown in  FIG. 4 , the first and second even and odd data input strobe signals dinstb — ev 0 &lt; 0 : 3 &gt;, dinstb — ev 1 &lt; 0 : 3 &gt;, dinstb — od 0 &lt; 0 : 3 &gt; and dinstb —   01 &lt; 0 : 3 &gt; are divided and outputted to the global I/O line drivers  20   —   1  to  20   — n, so that the data input circuit for receiving the data becomes complicated. Particularly, there occurs a problem that the circuit occupies a large area in view of a layout. 
   SUMMARY OF THE INVENTION 
   It is, therefore, a primary object of the present invention to provide a synchronous memory device having a simplified data input unit for receiving and transferring data to an internal memory cell block compared with the related art, which is adapted to high frequency and can reduce a power consumption. 
   In accordance with a preferred embodiment of the present invention, there is provided a synchronous memory device which comprises: a data alignment means for aligning in parallel a plurality of data sequentially inputted through one data input pin as many as the number of prefetched data to generate a plurality of aligned data; a global I/O line driving means for receiving the plurality of aligned data and outputting the even data or the odd data to a memory core area in response to a data input strobe signal; a data input strobe signal generating means for buffering the clock signal to output the data input strobe signal; and a data input strobe signal control means for generating a data input strobe control signal used to allow the data input strobe signal generating means to output the data input strobe signal only at a period when an operation corresponding to the write command is carried out. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: 
       FIG. 1  is a block diagram of a conventional semiconductor memory device; 
       FIG. 2A  is a block diagram of a data alignment unit shown in  FIG. 1 ; 
       FIG. 2B  is a block diagram of a global I/O line driving unit shown in  FIG. 1 ; 
       FIG. 3  is a block diagram of a plurality of global I/O line driving units, in which data inputted through a plurality of data pins are aligned and outputted as even data and odd data; 
       FIG. 4  is a block diagram of a data input strobe signal generating unit shown in  FIG. 1 ; 
       FIG. 5  is a circuit diagram of a clock pulse signal generating unit shown in  FIG. 4 ; 
       FIG. 6  is a circuit diagram of a write address detecting unit shown in  FIG. 4 ; 
       FIG. 7  is a circuit diagram of a first even data input strobe signal generating unit shown in  FIG. 4 ; 
       FIG. 8  is a circuit diagram of a first odd data input strobe signal generating unit shown in  FIG. 4 ; 
       FIG. 9  is a waveform showing an alignment of four data in a semiconductor memory device of  FIG. 1 ; 
       FIG. 10  is a waveform showing an operation of generating a data input strobe signal and an operation of receiving four aligned data in response of the data input strobe signal in a conventional memory device; 
       FIGS. 11A and 11B  are waveforms showing a problem of a conventional memory device; 
       FIG. 12  is a block diagram of a memory device in accordance with a preferred embodiment of the present invention; 
       FIG. 13  is a block diagram of a global I/O line driving unit shown in  FIG. 12 ; 
       FIG. 14  is a block diagram of a plurality of global I/O line driving units that receive data inputted through a plurality of data pins in a memory device in accordance with the present invention; 
       FIG. 15  is a circuit diagram of a data input strobe signal control unit shown in  FIG. 12 ; 
       FIG. 16  is a circuit diagram of a data input strobe signal generating unit shown in  FIG. 12 ; 
       FIG. 17  is a circuit diagram of a data input multiplexer; 
       FIG. 18  is a waveform illustrating an operation of a memory device shown in  FIG. 12 ; 
       FIG. 19  is a waveform illustrating a process of receiving data in a sequential mode in a memory device of  FIG. 12 ; and 
       FIG. 20  is a waveform illustrating a process of receiving data in an interleave mode in a memory device of  FIG. 12 . 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
   The preferred embodiments will be described below in detail with reference to accompanying drawings. 
     FIG. 12  is a block diagram of a memory device in accordance with an embodiment of the present invention. 
   Referring to  FIG. 12 , the memory device in accordance with the present invention includes: a data alignment unit  400  for receiving data, which are inputted in response to a write command, in synchronization with a clock signal and aligning in parallel a plurality of data, which are sequentially inputted through one data input pin DQ, as many as the number of prefetched data to thereby output four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1 ; a global I/O line driving unit  600  for receiving the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  to output even data gio — ev 0  and gio — ev 1  or odd data gio — od 0  and gio — od 1  to a memory core area in response to data input strobe signals dinstb — od 0 , dinstb — ev 0 , dinstb — ev 1  and dinstb — od 1 ; a data input strobe signal generating unit  200  for buffering a clock signal CLK to output the data input strobe signals dinstb — od 0 , dinstb — ev 0 , dinstb — ev 1  and dinstb — od 1 ; and a data input strobe signal control unit  100  for outputting a data input strobe control signal dinstb — ctr 1  used to control the data input strobe signal generating unit  200  to output the data input strobe signals dinstb — od 0 , dinstb — ev 0 , dinstb — ev 1  and dinstb — od 1  only at a period an operation corresponding to the write command is carried out. The memory device further includes a data buffer unit  300  for buffering data inputted through the data input pin and transferring the buffered data to the data alignment unit  400 . 
   In accordance with an embodiment of the present invention, the memory device further includes a data input multiplexer  500  for receiving the aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  from the data alignment unit  400  to output data dint — r 0 , dint — f 0 , dint — r 1  and dint — f 1 , which are re-aligned according to an interleave mode or a sequential mode, to the global I/O line driving unit  600 . 
   Additionally, according to the memory device of the present invention, the number of prefetched data is 4 bits, and the data input strobe signal generating unit  200  buffers the clock signal CLK to generate the first and second even data input strobe signals dinstb — ev 0  and dinstb — ev 1  and the first and second odd data input strobe signals dinstb — od 0  and dinstb — od 1  so that the global I/O line driving unit  600  can select the four re-aligned data dint — r 0 , dint — f 0 , dint — r 1  and dint — f 1 , which are outputted from the data input multiplexer  500 , and output the first and second even data gio — ev 0  and gio — ev 1  and the first and second odd data gio — od 0  and gio — od 1 . 
     FIG. 13  is a block diagram of the global I/O line driving unit shown in  FIG. 12 . 
   Referring to  FIG. 13 , the global I/O line driving unit  600  includes first and second even data global I/O line drivers  610  and  620  and first and second odd data global I/O line drivers  630  and  640 , each of which has first to four control signal input terminals A to D. Each of the first and second even data global I/O line drivers  610  and  620  and the first and second odd data global I/O line drivers  630  and  640  receives the first and second even data input strobe signals dinstb — ev 0  and dinstb — ev 1  and the first and second odd data input strobe signals dinstb — od 0  and dinstb — od 1  through the first to four control signal input terminals A to D. At this time, the first and second even data global I/O line drivers  610  and  620  and the first and second odd data global I/O line drivers  630  and  640  receive the even data input strobe signals and the odd data input strobe signals in differently-aligned sequence and exclusively select the 4-bit data dint — r 0 , dint — r 1 , dint — f 0  and dint — f 1  re-aligned by the data input multiplexer  500  one by one to thereby output the first even data gio — ev 0 , the second even data gio — ev 1 , the first odd data gio — od 0  and the second odd data gio — od 1 , respectively. 
     FIG. 14  is a block diagram of a plurality of global I/O line driving units that receive data inputted through a plurality of data pins in the memory device in accordance with the present invention. 
   As described above, the general memory device receives a plurality of data through a plurality of data input pins in parallel. As shown in  FIG. 14 , the memory device in accordance with an embodiment of the present invention includes N numbers of global I/O line driving units  600   —   1 ,  600   —   2  and  600   — n for receiving a plurality of aligned 4-bit data dint — r 0 &lt; 0 &gt;, dint — f 0 &lt; 0 &gt;, dint — r 1 &lt; 0 &gt;, dint — f 1 &lt; 0 &gt;. . . , dint — r 0 &lt;n&gt;, dint — f 0 &lt;n&gt;, dint — r 1 &lt;n&gt;, dint — f 1 &lt;n&gt;, which are inputted through first to N-th data input pins and then aligned, and outputting a first group of first and second even data and first and second odd data gio — ev 0 &lt; 0 &gt;, gio — ev 1 &lt; 0 &gt;, gio — od 0 &lt; 0 &gt; and gio — od 1 &lt; 0 &gt;, a second group of first and second even data and first and second odd data gio — ev 0 &lt; 1 &gt;, gio — ev 1 &lt; 1 &gt;, gio — od 0 &lt; 1 &gt; and gio — od 1 &lt; 1 &gt;, and an N-th group of first and second even data and first and second odd data gio — ev 0 &lt;n&gt;, gio — ev 1 &lt;n&gt;, gio — od 0 &lt;n&gt; and gio — od 1 &lt;n&gt;, respectively.  FIG. 12  illustrates the data input unit connected to one data input pin. 
     FIG. 15  is a circuit diagram of the data input strobe signal control unit shown in  FIG. 12 . 
   Referring to  FIG. 15 , the data input strobe signal control unit  100  includes a data input enable detecting unit  110  and a data input strobe control signal generating unit  120 . The data input enable detecting unit  110  detects a period at which an operation corresponding to the write command is carried out to activate a data input enable signal idinclk. The data input strobe control signal generating unit  120  generates a data input strobe control signal dinclk — ctr 1  provided by dividing the clock signal CLK by N periods (where, N is a positive integer greater than 2 and in this embodiment, N is 2) during a period at which the data input enable signal idinclk is activated. 
   Additionally, the data input strobe control signal generating unit  120  includes dividers  121  to  124  for dividing the clock signal CLK by 2 during the period at which the data input enable signal idinclk is activated to thereby output the data input strobe control signal dinclk — ctrl. 
   The data input strobe control signal generating unit  120  includes: a first logic combination unit  124  for buffering the clock signal CLK during the period at which the data input enable signal idinclk is activated; a first latch unit  121  for buffering and outputting a control signal IN if an output of the first logic combination unit  124  (i.e., an output of an inverter I 25 ) is a high level, and for latching the control signal IN if the output of the first logic combination unit  124  is a low level; a second latch unit  122  for receiving and inverting the latched control signal of the first latch unit  121  to output the control signal IN if the output of the first combination unit  124  is a low level, and for latching again the control signal IN if the output of the first logic combination unit  124  is a high level; and a second logic combination unit for combining the control signal IN and the inverted data input enable signal to output the data input strobe control signal dinclk — ctrl. 
   The data input enable detecting unit  110  includes a data input period signal generator  113 , a first data input enable detector  110   —   1  and a second data input enable detector  110   —   2 . The data input period signal generator  113  generates a data input period signal wt — stdby — p that is activated as much as period at which all data (e.g., D 0  to D 3 ) corresponding to the write command are inputted. The first data input enable detector  110   —   1  is activated in response to a power-up signal pwrup for detecting a stable power supply and a write enable signal wtrzt that maintains an active state at a data write operation, and delays the data input period signal wt — stdby — p for a predetermined period (in this embodiment, 2 periods) of the clock signal CLK. The second data input enable detector  110   —   2  is activated in response to the write enable signal wtrzt, and synchronizes a delayed data input period signal wt — stdby — p 2  with a timing of the clock signal CLK when the last data among the data inputted in response to the write command is inputted, thereby outputting the data input enable signal idinclk. 
     FIG. 16  is a circuit diagram of the data input strobe signal generating unit shown in  FIG. 12 . 
   Referring to  FIG. 16 , data input strobe signal generating unit  200  includes an address decoding unit  210  and a data input strobe signal output unit  220 . The address decoding unit  220  decodes lower address signals sosez 0   — wt and sosez 1   — wt corresponding to the number of data inputted in response to the write command among addresses inputted in response to the write command. The data input strobe signal output unit  220  buffers the clock signal CLK in response to the decoded result of the address decoding unit  210  and outputs the data input strobe signals dinstb — od 0 , dinstb — ev 0 , dinstb — ev 1  and dinstb — od 1 , in which the data input strobe signal output unit  220  is enabled in response to the data input strobe control signal dinclk — ctrl outputted from the data input strobe control unit  110 . 
   Additionally, the address decoding unit  210  includes: inverters I 35  and I 36  receiving the first and second address signals sosez 0   — wt and sosez 1   — wt, which are lower 2-bit address signals, among the addresses inputted in response to the write command, respectively; a first AND logic gate circuit consisting of a NAND gate ND 16  and an inverter I 37 , for receiving output signals sesoz 0   — wt and sosoz 1   — wt of the inverters I 35  and I 36  to output a first decoding signal stb — ev 0   — en; a second AND logic gate circuit consisting of a NAND gate ND 17  and an inverter I 38 , for receiving the first address signal sosez 0   — wt and the output signal sesoz 0   — wt of the inverter I 36  to output a second decoding signal stb — od 0   — en; a third AND logic gate circuit consisting of a NAND gate ND 18  and an inverter I 39 , for receiving the output signal sesoz 0   — wt of the inverter I 35  and the second address signal sosez 1   — wt to output a third decoding signal stb — ev 1   — en; and a fourth AND logic gate circuit consisting of a NAND gate ND 19  and an inverter I 40 , for receiving the first and second address signals sosez 0   — wt and sosez 1   — wt to output a fourth decoding signal stb — od 1   — en. 
   The data input strobe signal output unit  220  includes: a fifth AND logic gate circuit consisting of a NAND gate ND 20  and inverters I 41  and I 42 , for receiving the clock signal CLK, the first decoding signal stb — ev 0   — en and the data input strobe control signal dinclk — ctrl to output the first even data input strobe signal dinstb — ev 0 ; a sixth AND logic gate circuit consisting of a NAND gate ND 21  and inverters I 43  and I 44 , for receiving the clock signal CLK, the second decoding signal stb — od 0   — en and the data input strobe control signal dinclk — ctrl to output the first odd data input strobe signal dinstb — od 0 ; a seventh AND logic gate circuit consisting of a NAND gate ND 22  and inverters I 45  and I 46 , for receiving the clock signal CLK, the third decoding signal stb — ev 1   — en and the data input strobe control signal dinclk — ctrl to output the second even data input strobe signal dinstb — ev 1 ; and a eighth AND logic gate circuit consisting of a NAND gate ND 23  and inverters I 47  and I 48 , for receiving the clock signal CLK, the fourth decoding signal stb — od 1   — en and the data input strobe control signal dinclk — ctrl to output the second odd data input strobe signal dinstb — od 1 . 
   Additionally, the data input strobe signal generating unit  200  includes a multiplexer control unit  230 . The multiplexer control unit  230  receives a data input mode control signal seq — intz, which is determined according to the interleave mode or the sequential mode, in response to the write command and allows the data input multiplexer to be realigned to the data input mode corresponding to the write command. 
   The data input multiplexer control unit  230  includes: an inverter I 33  for inverting the data input mode control signal seq — intz that maintains a low level in the interleave mode and a high level in the sequential mode; and an AND logic gate circuit consisting of a NAND gate ND 15  and an inverter I 34 , for receiving an output of the inverter I 33  and the address signal sosez 0   — wt of a least significant bit (LSB) among the addresses inputted in response to the write command to output a data input multiplexer control signal seqz — int — wt. 
     FIG. 17  is a circuit diagram of the data input multiplexer. 
   Referring to  FIG. 17 , the data input multiplexer  500  includes: transmission gates T 3  and T 4  for receiving the first to fourth aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1 , which are aligned by the data alignment unit  400 , and being turned on in response to the data input multiplexer control signal seqz — int — wt to thereby transmit the first aligned data align — dr 0  to the global I/O line driving unit  600 ; transmission gates T 5  and T 6  which are selectively turned on in response to the data input multiplexer control signal seqz — int — wt to transmit the second aligned data align — df 0  or the fourth aligned data align — df 1  to the global I/O line driving unit  600 , respectively; transmission gates T 7  and T 8  which are turned on in response to the data input multiplexer control signal seqz — int — wt to transmit the third aligned data align — dr 1  to the global I/O line driving unit  600 ; and transmission gates T 9  and T 10  which are selectively turned on in response to the data input multiplexer control signal seqz — int — wt to transmit the fourth aligned data align — df 1  or the second aligned data align — df 0  to the global I/O line driving unit  600 , respectively. Here, the transmission gates T 7  and T 9  and the transmission gates T 8  and T 10  are turned on exclusively each other. 
     FIG. 18  is a waveform illustrating an operation of the memory device shown in  FIG. 12 . Hereinafter, an operation of the memory device in accordance with an embodiment of the present invention will be described with reference to  FIGS. 12 to 18 . 
   As shown in  FIG. 18 , if the write commands wt 0  and wt 1  are inputted while the memory device is operating, corresponding addresses and data D 0  to D 7  are inputted in synchronization with the clock signal CLK. Here, the data D 0  to D 3  are inputted in response to the clock signal wt 0 , and the data D 4  to D 7  are inputted in response to the write command wt 1 . Meanwhile, the control signal wtrzt is a signal that maintains a high level during the write operation. Additionally, in  FIG. 18 , a waveform “A” is a waveform corresponding to the write command wt 0  and a waveform “B” is a waveform corresponding to the write command wt 1 . 
   To begin with, an operation of the data input strobe signal control unit  100  will be described with reference to  FIG. 15 . 
   If the write commands wt 0  and wt 1  to be executed are inputted, the data input period signal generator  113  of the data input strobe signal control unit  100  activates the data input period signal wt — stdby — p that is a signal being activated during the data input period. In this manner, if four data are respectively inputted in response to the write commands wt 0  and wt 1 , the data input period signal wt — stdby — p is outputted in an activated state of a high level for four clocks because two data are inputted for one clock period in the DDR synchronous memory device. 
   Then, the first data input enable detecting unit  110   —   1  of the data input strobe signal control unit  100  receives and shifts the data input period signal wt — stdby — p for two periods of the clock signal CLK. The first data input enable detecting unit  110   —   1  includes two flip-flops  111  and  112 . The flip-flops  111  and  112  are reset by the power-up signal pwrup and the write enable signal wtrzt. 
   The power-up signal pwrup is a signal for detecting an input of a stable voltage to the memory device, and the write enable signal wtrzt is a signal activated when the memory device is in a data write mode. 
   Then, the second data input enable detecting unit  110   —   2  buffers the 2-clock-shifted data input period signal wt — stdby — p 2  outputted from the first data input enable detecting unit  110   —   1  and generates the buffered signal to the data input strobe control signal generating unit  120 . 
   At this time, if the clock signal CLK is a low level, the transmission gate T 1  is turned on so that the 2-clock-shifted data input period signal wt — stdby — p 2  is generated as the data input enable signal idinclk through the latch units I 23  and I 24  and outputted to the data input strobe control signal generating unit  120 . 
   Here, in order to turn on the transmission gate T 1  of the second data input enable detecting unit  110   —   2 , a clock signal falling at a second time after the input of the write command wt 0  is used. To turn on the transmission gate T 1  after about two and a half clocks is for the purpose of turning on the transmission gate T 1  after a necessary time when data is aligned after the input of the write command wt 0  and then transferred to the internal core circuit. 
   If the last data D 3  is inputted in response to the write command wt 0 , the data alignment unit  400  aligns the four data D 0  to D 3 , and the aligned four data D 0  to D 4  are inputted to the global I/O line driving unit  600  through the data input multiplexer  500 . After this timing (second falling of the clock signal CLK), the aligned data must be inputted to the memory core area. In order for that, the data input strobe signal generating unit  200  must output the data strobe signals dinstb — od 0 , dinstb — ev 0 , dinstb — od 1  and dinstb — ev 1  to the global I/O line driving unit  600 . 
   Accordingly, from this timing (second falling of the clock signal CLK), the second data input enable detecting unit  110   —   2  activates the data input enable signal idinclk to a high level. Thereafter, the data input enable signal idinclk maintains an active state during the period at which the data input period signal wt — stdby — p is activated. Here, the data input enable signal maintains the activated state for four clocks in response to the successive two write commands wt 0  and wt 1 . 
   Then, the data input strobe control signal generating unit  120  is first clocked at a timing when the data input enable signal idinclk is activated, and generates a signal that is obtained by dividing the clock signal CLK by two and then clocking the dividing clock signal. Then, the signal is outputted as the data input strobe control signal dinclk — ctrl to the data input strobe signal generating unit  200 . 
   In other words, the data input strobe control signal dinclk — ctrl is a clocking signal that is obtained by dividing the clock signal by two at a period when the data input enable signal idinclk is activated. 
   The second data input enable detecting unit  110   —   2  is configured to receive a control signal ybst. Here, the control signal ybst is a signal that maintains a high level at a timing when the last data among data inputted successively in response to the write command is inputted. 
   The second data input enable detecting unit  110   —   2  receives the control signal ybst in order to maintain (for four clocks) the data input enable signal idinclk even in case when eight data are sequentially inputted in response to the write command. 
   Since the data input period signal wt — stdby — p 2  is a signal that is sustained for two clocks, the data input strobe signal is generated two times in order to align four data and transmit the aligned data to the internal core area, in case eight data are sequentially inputted in response to the write command. Therefore, the data input strobe control signal dinclk — ctrl must be generated two times. 
   Accordingly, since the data input enable signal idinclk must be sustained for four clocks, the control signal ybst is received in order to prevent the data input enable signal idinclk from being inactivated after two clocks due to the data input period signal wt — stdby — p 2  that is sustained for two clocks. 
   Hereinafter, an operation of the data input strobe signal generating unit  100  will be described in detail with reference to  FIG. 16 . 
   First, the inverters I 35  and I 36  provided in the address decoding unit  210  of the data input strobe signal generating unit  200  receives and inverts the first and second address signals sosez 0   — wt and sosez 1   — wt, which are generated by buffering the address signal that corresponds to the last two bits among the addresses inputted in response to the write command. Then, two signals among the first and second address signals sosez 0   — wt and sosez 1   — wt and the outputs sesoz 0   — wt and sosez 1   — wt are inputted to the four AND logic gate circuits consisting of the NAND gates ND 16  to ND 19  and the inverters I 37  to I 40 . Therefore, one of the first to fourth decoding signals stb — ev 0   — en, stb — od 0   — en, stb — ev 1   — en and stb — od 1   — en is activated in response to levels of the first and second address signals sosez 0   — wt and sosez 1   — wt. 
   Then, one of the four NAND gates ND 20  to ND 24  provided in the data input strobe signal output unit  220  is selected by one of the first to fourth decoding signals stb — ev 0   — en, stb — od 0   — en, stb — ev 1   — en and stb — od 1   — en. 
   A following Table 1 shows the first to fourth decoding signals stb — ev 0   — en, stb — od 0   — en, stb — ev 1   — en and stb — od 1   — en that are decoded with respect to the signal levels of the first and second address signals sosez 0  wt and sosez 1  wt. 
   
     
       
         
             
             
             
             
             
             
           
             
               TABLE 1 
             
             
                 
             
             
               sosez0 — wt 
               sosez — wt 
               stb — ev0 — en 
               stb — od0 — en 
               stb — evl — en 
               stb — odl — en 
             
             
                 
             
           
          
             
               0 
               0 
               1 
               0 
               0 
               0 
             
             
               1 
               0 
               0 
               1 
               0 
               0 
             
             
               0 
               1 
               0 
               0 
               1 
               0 
             
             
               1 
               1 
               0 
               0 
               0 
               1 
             
             
                 
             
          
         
       
     
   
   Then, the clock signal CLK is inputted to the selected NAND gate and buffered during the data input strobe control signal dinclk — ctrl is activated to a high level to thereby output one of the first and second even data input strobe signals dinstb — ev 0  and dinstb — ev 1  and the first and second — odd data input strobe signals dinstb — od 0  and dinstb — od 1 . 
   The global I/O line driving unit  20  receives the aligned data dint — r 0 , dint — f 0 , dint — r 1  and dint — f 1  and outputs the first and second even data gio — ev 9  and gio — ev 1  and the first and second odd data gio — od 0  and gio — od 1  in response to the data input strobe signals dinstb — ev 0 , dinstb — ev 1 , dinstb — od 0  and dinstb — od 1 . 
   The global input I/O line driving unit  20  shown in  FIG. 13  includes the first and second even data global I/O line drivers  610  and  620  and the first and second odd data global I/O line drivers  630  and  640 . At this time, the four line drivers  610  to  640  have the same configuration. 
   However, the four line drivers  610  to  640  receives the different combinations of the data input strobe signals dinstb — ev 0 , dinstb — ev 1 , dinstb — od 0  and dinstb — od 1  through their input terminals A to D and outputs one of the inputted four aligned data as the first even data gio — ev 0 , the second even data gio — ev 1 , the first odd data gio — od 0  or the second even data gio — od 1 . 
   Meanwhile, the data multiplexer  500  re-aligns the four data align — dr 0 , align — df 0 , align — dr 1  and align — df 1 , which are aligned in the data alignment unit  400 , in response to the data input multiplexer control signal seqz — int — wt determined according to the interleave mode or the sequential mode of the data corresponding to the write command, and then outputs the re-aligned data to the global I/O line driving unit. 
   The data input multiplexer control signal seqz — int — wt is a signal outputted from the data input strobe signal generating unit  200 , and the multiplexer control unit  230  of the data input strobe signal generating unit  200  receives the first address signal sosez 0   — wt and the data mode select signal seq — intz to output the data input multiplexer control signal seqz — int — wt that maintains a low level at the interleave mode and a high level at the sequential mode. 
   The data input multiplexer  500  outputs the four data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  aligned in the data alignment unit  400  in response to the data input multiplexer control signal seqz — int — wt as it is, or re-aligns the four data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  and outputs the re-aligned data to the global I/O line driving unit  600 . 
   For example, in case the data input multiplexer control signal seqz — int — wt is in a low level, the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  are outputted as the re-aligned data dint — r 0 , dint — f 0 , dint — r 1  and dint — f 1 . In case the data input multiplexer control signal seqz — int — wt is in a high level, the re-aligned data generated by exchanging the second and fourth data of the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  are outputted to the global I/O line driving unit. 
     FIG. 19  is a waveform illustrating an operation of inputting the data to the memory device of  FIG. 12  at the sequential mode, and  FIG. 20  is a waveform illustrating an operation of inputting the data to the memory device of  FIG. 12  at the interleave mode. 
   In  FIG. 19 , in case the data input multiplexer control signal seqz — int — wt is in a low level, the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align — df 1  are outputted as the re-aligned data dint — r 0 , dint — f 0 , dint — r 1  and dint — f 1 . 
   In  FIG. 20 , in case the data input multiplexer control signal seqz — int — wt is in a high level, the re-aligned data generated by exchanging the second and fourth data of the four aligned data align — dr 0 , align — df 0 , align — dr 1  and align  — df 1  are outputted to the global I/O line driving unit. 
   According to the present invention, since the data input strobe signal generated in order to transmit the inputted data to the internal core area are generated only at a timing when the data are actually transmitted to the internal core area, the power consumption of the data input unit can be remarkably reduced compared with the conventional memory device in which the data input strobe signal is always generated. 
   Additionally, since the memory device in accordance with the present invention generates the data input strobe signal only at a timing when the data are actually transmitted to the internal core area, a timing margin in a generation of the data input strobe signal is increased, thereby improving an entire operating speed (more than 500 MHz). 
   Further, since the memory device in accordance with the present invention remarkably simplifies the signals that are inputted to the data alignment unit for receiving the aligned data and outputting the first and second even data and the first and second odd data, a circuit area of the data input unit is reduced much more compared with the conventional memory device, thereby reducing greatly an entire layout area of the memory device. 
   While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims.