Patent Publication Number: US-9891250-B2

Title: Bidirectional voltage differentiator circuit

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application from U.S. application for patent Ser. No. 14/966,129 filed Dec. 11, 2015, which is a divisional application from U.S. application for patent Ser. No. 13/648,412 filed Oct. 10, 2012, which claims priority from Chinese Application for Patent No. 201110461949.8 filed Dec. 31, 2011 and from Chinese Application for Patent No. 201210268942.9 filed Jul. 27, 2012, the disclosures of which are hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to voltage sensing circuitry and, more particularly, to an integrated circuit operable to sense bidirectional variation of an input voltage and produce an output signal indicating the occurrence of said voltage variation. 
     BACKGROUND 
     Traditional voltage sensing circuits require circuitry for sensing a first voltage variation in one direction (e.g., rising) and additional circuitry for sensing a second voltage variation in another direction (e.g., falling). The additional circuitry required to sense a voltage change reduces efficiency of the circuit and requires additional components, thereby increasing manufacturing costs. Additionally, many traditional voltage sensing circuits consider a DC component of the sensed voltage, which may otherwise be unnecessary and further reduce efficiency of the circuit. Accordingly, there exists a need for voltage sensing circuitry with improved efficiency that may be manufactured at reduced expense. 
     SUMMARY 
     An integrated bidirectional voltage differentiator circuit is presented for sensing bidirectional variation of an input voltage and producing an output signal indicating the occurrence of said voltage variation. In one embodiment, the bidirectional voltage differentiator circuit comprises: first circuitry operable to sense a change in an input voltage; second circuitry operable, in response to said first circuitry sensing a first change in said input voltage, to change a state of a first logic signal and, in response to said first circuitry sensing a second change in said input voltage, to change a state of a second logic signal; and third circuitry operable, in response to a change in said first logic signal state or a change in said second logic signal state, to produce a third signal indicative of said first circuitry sensing said change in said input voltage. 
     In another embodiment, the bidirectional voltage differentiator circuit comprises: a voltage differentiator circuit operable to sense and respond to a positive change in an input voltage by increasing current applied to first circuitry operable to generate a state change of a first output signal, and further operable to sense and respond to a negative change in said input voltage by decreasing said current applied to said first circuitry operable to generate a state change of a second output signal; and second circuitry operable, in response to said first and second output signals, to produce a third signal indicative of a sensed change in said input voltage. 
     In yet another embodiment, the bidirectional voltage differentiator circuit comprises: a current generator circuit comprising: an input node capacitively coupled to a first circuit leg; a first internal output node coupled to said first circuit leg; and a second internal output node coupled to a second circuit leg; first pull-down circuitry having a first control node coupled to said first internal output node; second pull-down circuitry having a second control node coupled to said second internal output node; and logic circuitry coupled to said first pull-down circuitry at a first logic output node, and coupled to said second pull-down circuitry at a second logic output node. 
     The foregoing and other features and advantages of the present disclosure will become further apparent from the following detailed description of the embodiments, read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of the disclosure, rather than limiting the scope of the invention as defined by the appended claims and equivalents thereof. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments are illustrated by way of example in the accompanying figures not necessarily drawn to scale, in which like reference numbers indicate similar parts, and in which: 
         FIG. 1  illustrates a first example embodiment of a bidirectional voltage differentiator circuit in accordance with the present disclosure; 
         FIG. 2  illustrates a timing diagram corresponding to the disclosed bidirectional voltage differentiator circuit illustrated in  FIG. 1 ; 
         FIG. 3  illustrates simulation results for the bidirectional voltage differentiator circuit shown in  FIG. 1 ; 
         FIGS. 4A and 4B  illustrate additional example embodiments of a bidirectional voltage differentiator circuit in accordance with the present disclosure; 
         FIG. 5  illustrates an application of the bidirectional voltage differentiator circuit to sense voltage of an LED panel; and 
         FIG. 6  illustrates a waveform for a typical panel voltage Vpanel in an AMOLED panel and a timing diagram for the logic states of the output signals for the bidirectional voltage differentiator circuit. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a bidirectional voltage differentiator circuit  100  in accordance with an example embodiment of the present disclosure. The disclosed bidirectional voltage differentiator circuit  100  comprises start-up circuitry  110 , sensing circuitry  130 , and output circuitry  150  coupled to logic circuitry  170 . The start-up circuitry  110  acts to start-up the sensing circuitry  130  in a current-generating state when the circuit  100  is powered on, and accelerates the response of the sensing circuitry  130  thereafter. The sensing circuitry  130  senses variation in an input voltage VIN applied to an input node IN. Responsive to the voltage variation sensed by the sensing circuitry  130 , the output circuitry  150  produces a state change at a first output node OUT 1  or at a second output node OUT 2 . The logic circuitry  170  receives the states of OUT 1  and OUT 2  and produces a logic output signal OUTZ to indicate the occurrence of the variation sensed in the input voltage VIN. The disclosed voltage sensing circuit  100  is operable to sense variation of the input voltage VIN regardless of whether the voltage VIN is rising or falling and without regard to the DC value of the input voltage VIN. 
     The components comprising the respective start-up circuitry  110 , sensing circuitry  130 , output circuitry  150 , and logic circuitry  170  are briefly described in the following paragraphs with reference to the circuit  100  illustrated in  FIG. 1 , wherein the operation of the circuit  100  is described in greater detail thereafter. The start-up circuitry  110  includes a first current mirror  112  comprised of transistors MS 4  and MS 5 . Transistor MS 5  is coupled to a current sink (not shown) at a biasing node  113  to provide a biasing current I Bias  from transistor MS 5 . Transistor MS 4  may be sized to transistor MS 5  to set a mirrored bias current I Bias ′, which is supplied to node  115 . The current supplied to node  115  produces a voltage VA 1  for turning on acceleration circuitry  116 . The acceleration circuitry  116  is comprised of series-connected transistors MR 1 , MR 2 , MR 3 , and MR 4 . The voltage VA 1  is applied to the gates of the respective transistors MR 1 , MR 2 , MR 3 , and MR 4 . Accordingly, the bias current I Bias  from transistor MS 5  should be great enough to generate a voltage VA 1  large enough to turn on transistors MR 1 -MR 4 , thus activating the acceleration circuitry  116 . When activated, the acceleration circuitry  116  supplies a current I A  at node  120  to supply additional current to accelerate response of the sensing circuitry  130 , as further explained below. In an example embodiment of the circuit  100 , I Bias =2.5 uA, (W/L) MS5 =(10 u/5 u)*2, (W/L) MS4 =(10 u/5 u)*2, and the combined size of transistors MR 1  through MR 4  may be represented as (W/L) MR1-MR4 =(1 u/35 u). 
     The circuit  100  further includes a second current mirror  114  comprised of transistors MS 2  and MS 3 , wherein the drain of transistor MS 3  is coupled to node  115 , and the drain of transistor MS 2  is coupled to a transistor MS 1 . Transistor MS 1  is responsive to the voltage at node  120  to control a current I MS2  at transistor MS 2 , wherein transistor MS 2  may be sized to transistor MS 3  to set current I MS3 , which is drawn from node  115 . At start-up, the transistor MS 1  is turned off, which results in a low I MS3 . When the voltage at node  120  produces a V GS  voltage greater than the threshold voltage of transistor MS 1 , transistor MS 1  is activated and the current I MS3  is drawn from the node  115 . Accordingly, the current I Bias ′ should be large enough to provide sufficient voltage VA 1  to activate the acceleration circuitry  116  when transistor MS 1  is initially off at start-up, and to maintain activation of the acceleration circuitry  116  thereafter. Therefore, after start-up of the circuit  100 , the acceleration circuitry  116  will continue to draw current from node  120 . In an example embodiment of the circuit  100  illustrated in  FIG. 1 , (W/L) MS3 =(10 u/5 u)*2, (W/L) MS2 =(10 u/5 u)*2, and (W/L) MS1 =(10 u/5 u)*10. 
     As illustrated in  FIG. 1 , the sensing circuitry  130  comprises transistors M 1 , M 2 , M 3 , and M 4 , resistor R 1 , and a sensing capacitor CS 1  coupled to the input node IN. The sensing capacitor CS 1  blocks the DC component of the input voltage VIN applied to the input node IN, and passes variation of the input voltage VIN to the circuit  100  as voltage VCS 1 . In accordance with the present disclosure, the sensing circuit  130  has two operating states. The first operating state (i.e., the quiescent state) occurs when there is no variation in the input voltage VIN. In this quiescent state, an initial sensing capacitor voltage VCS 1  is applied to transistors M 1 -M 4  and substantially no additional current is applied to transistors M 1 -M 4  from the input node IN. The second operating state occurs when there is a variation in the input voltage VIN and a corresponding change in the voltage VCS 1  causes a change in the current flowing through transistors M 1 -M 4 . In accordance with an embodiment of the present disclosure, when the sensing capacitor CS 1  senses a positive change, or increase, in the input voltage VIN, the currents across respective transistors M 1 -M 4  increase. When the sensing capacitor CS 1  senses a negative change, or decrease, in the input voltage VIN, the currents across respective transistors M 1 -M 4  decrease. 
     Transistors M 2  and M 4  are coupled together to form a first leg of the sensing circuitry  130 , wherein the sensing capacitor CS 1  is coupled to a node located between the drain of transistor M 2  and the drain of transistor M 4  as illustrated in  FIG. 1 . Additionally, transistor M 2  is coupled to transistors M 5  and M 11  to form a third current mirror  132 , and transistor M 4  is coupled to transistors M 3 , M 6 , M 9 , and MS 1  to form a fourth current mirror  134 , wherein the fourth current mirror  134  is coupled to node  120  at the drain of transistor M 3  and the gate of transistor MS 1 . 
     Transistors M 1  and M 3  are coupled together to form a second leg of the sensing circuitry  130 . The drain of transistor M 1  is coupled to node  120  which, as previously mentioned, is coupled to the acceleration circuitry  116  and to the gate of transistor MS 1 . The gate of transistor M 1  is coupled to the gate of transistor M 2 , and the source of transistor M 1  is coupled to resistor R 1 . Resistor R 1  sets the current across transistor M 1  (I M1 ), which is reflected about the third and fourth current mirrors  132  and  134 . Accordingly, the resistor R 1  regulates the DC current of transistors M 1 -M 4  to provide a quiescent state current at each of the transistors M 1 -M 4 . In the embodiment illustrated in  FIG. 1 , the resistor R 1  regulates the current of transistors M 1 -M 4  such that a change in current across transistor M 2  is greater than a change in current across transistor M 3  (i.e., ΔI M2 &gt;ΔI M3 ). It should be appreciated that, in other embodiments, the resistor R 1  may alternatively be coupled to other components such as, for example, the source of transistor M 4 . In an example embodiment of the circuit  100  illustrated in  FIG. 1 , CS 1 =16 pF, R 1 =120 kOhms, (W/L) M1 =(10 u/5 u)*14, (W/L) M2 =(10 u/5 u)*8, (W/L) M3 =(10 u/5 u)*10, and (W/L) M4 =(10 u/5 u)*10. 
     The output circuitry  150  includes a fifth current mirror  152  comprised of transistors M 7  and M 8 , a sixth current mirror  154  comprised of transistors M 10  and M 12 , transistors M 6  and M 9  (which are included in the fourth current mirror  134 ), transistors M 5  and M 11  (which are included in the third current mirror  132 ), the first output node OUT 1 , and the second output node OUT 2 . The drain of transistor M 5  is coupled to the drain of transistor M 6  at the first output node OUT 1 . In the embodiment illustrated in  FIG. 1 , the size of transistor M 6  is equal to the size of transistor M 4  (e.g., (W/L) M6 =(W/L) M4 =(10 u/5 u)*10), the size of transistor M 2  is larger than the size of transistor M 5  (e.g., (W/L) M2 =(10 u/5 u)*8 and (W/L) M5 =(10 u/5 u)*6), and the size of transistor M 4  is larger than the size of transistor M 9  (e.g., (W/L) M4 =(10 u/5 u)*10 and (W/L) M9 =(10 u/5 u)*8). During the quiescent state, I M3 =I M4 =I M2 , and the current across M 6  (I M6 ) is driven higher than the current across M 5  (I M5 ), thereby driving the state of the first output node OUT 1  high during the quiescent state. 
     The drain of transistor M 9  is coupled to the fifth current mirror  152  at the drain and gate of transistor M 7 , wherein transistor M 7  may be sized to transistor M 8  to set current I M8 . The drain of transistor M 11  is coupled to the sixth current mirror  154  at the drain and gate of transistor M 12 , wherein transistor M 12  may be sized to transistor M 10  to set current I M10 . The second output node OUT 2  is coupled between transistor M 8  of the fifth current mirror  152  and transistor M 10  of the sixth current mirror  154 . During the quiescent state, the current across transistor M 11  (I M11 ) is greater than the current across transistor M 9  (I M9 ). Therefore, during the quiescent state, I M10  drives the state of the second output node OUT 2  high. In an example embodiment of the circuit  100  illustrated in  FIG. 1 , (W/L) M7 =(10 u/5 u)*4, (W/L) M8 =(10 u/5 u)*4, (W/L) M10 =(10 u/5 u)*4, (W/L) M11 =(10 u/5 u)*8, and (W/L) M12 =(10 u/5 u)*4. 
     As shown in  FIG. 1 , the logic circuitry  170  comprises a NAND gate  172  having inputs coupled to respective output nodes OUT 1  and OUT 2 , and producing an active high output logic signal OUTZ. As described in greater detail below, the output logic signal OUTZ is provided to indicate the occurrence of a variation or transition of the input voltage VIN applied at the input node IN. Although a NAND gate producing an active high output signal is provided in the embodiment described herein, it should be understood that alternative embodiments may comprise other circuitry that may be active high or low without departing from the spirit and scope of the present disclosure as set forth in the claims provided below. 
     Operation of the circuit  100  is now described in greater detail with reference to both the circuit  100  illustrated in  FIG. 1  and the corresponding timing diagram  200  illustrated in  FIG. 2 . The timing diagram  200  illustrates operation of the circuit  100  by providing logic states of the OUT 1 , OUT 2 , and OUTZ signals in response to an example VIN signal  205 . The timing diagram  200  shows a first stage  202  wherein the voltage VIN is low with no variation, a second stage  204  wherein VIN is increasing, a third stage  206  wherein VIN is high with no variation, a fourth stage  208  wherein VIN is decreasing, and a fifth stage  210  wherein VIN is low with no variation. 
     During the first stage  202 , the voltage VIN is low with no variation and the circuit  100  is in the quiescent state. During the quiescent state, both the first output node OUT 1  and the second output node OUT 2  are high, therefore, the output logic signal OUTZ is low. 
     During the second stage  204 , the voltage VIN increases (i.e., changes from a lower voltage to a higher voltage). The sense capacitor CS 1  senses the variation in the voltage VIN, which causes a corresponding change in the current across respective transistors M 1 -M 4 . As the voltage VIN increases, the currents across transistors M 2  (I M2 ) and M 3  (I M3 ) increase. The change in current across M 2  is larger than the change in current across M 3  (i.e., ΔI M2 &gt;ΔI M3 ), and the current across transistor M 5  (I MS ) becomes greater than the current across transistor M 6  (I M6 ), which pulls output node OUT 1  low. Therefore, as the voltage VIN transitions from low to high, OUT 1  goes low while OUT 2  remains high, thus causing OUTZ to go high during the second stage  204 . 
     During the third stage  206 , the voltage VIN remains high with no variation. Accordingly, I M6  again becomes greater than I M5 , and the circuit  100  returns to the quiescent state. Since there is no variation of VIN during the third stage  206 , OUT 1  returns to a high state, and OUTZ returns to a low state. 
     During the fourth stage  208 , the voltage VIN decreases (i.e., changes from a higher voltage to a lower voltage). As the voltage VIN decreases, I M2  and I M3  decrease. The change in I M2  is greater than the change in I M3 , and the current across transistor M 8  (I M8 ) becomes larger than the current across transistor M 10  (I M10 ), which pulls output node OUT 2  low. Therefore, as the voltage VIN transitions from high to low, OUT 2  goes low while OUT 1  remains high, thus causing OUTZ to go high during the fourth stage  208 . 
     During the fifth stage  210 , the voltage VIN remains low with no variation. As further described below, the acceleration circuitry  116  accelerates the recovery of the sensing circuitry  130 , and the circuit  100  again returns to the quiescent state. Accordingly, OUT 2  returns to a high state, and OUTZ returns to a low state. As illustrated in  FIG. 2 , the OUTZ signal is low when there is no variation of the voltage VIN on the input node IN, and is high when the voltage VIN is varying or transitioning, regardless of the DC value of the voltage on IN. Thus, the logic output signal OUTZ may be used to indicate the occurrence of a variation of the input voltage VIN. 
     Recovery of the sensing circuitry  130  is further described herein with reference to the start-up circuitry  110  and sensing circuitry  130  illustrated in  FIG. 1 . As previously mentioned, the start-up circuitry  110  is operable to start-up the sensing circuitry  130  (in a current-sensing mode) once the circuit  100  is powered on, and is further operable to accelerate the response of the sensing circuitry  130  thereafter. As the voltage VIN on the input node IN decreases (see e.g., fourth stage  208  in  FIG. 2 ), current flows out of the input node IN, thus causing the voltage VCS 1  to decrease. As VCS 1  decreases, I M2  and I M3  decrease, which causes I M8  to become greater than I M10  and pulls OUT 2  low as described above. Once the voltage VIN has finished decreasing, no current flows from the input node IN. At this point, I M3  and I M4  try to recharge the capacitor CS 1  at the current set by transistor M 1  to drive the voltage VCS 1  back to its quiescent state, which also drives OUT 2  from low to high. However, since the capacitor CS 1  may be relatively large, this recovery may be slow and the transition of OUT 2  from low to high may be significantly delayed. The delayed transition of OUT 2  results in a delayed change in the logic output signal OUTZ, wherein during this delayed transition period, the logic output signal OUTZ is incorrectly indicating a voltage variation at the input node IN. Therefore, in order to accelerate the recovery of the capacitor CS 1  and voltage VCS 1 , the start-up circuitry  110  uses acceleration circuitry  116  to increase the currents across resistors M 3  and M 4  (I M3  and I M4 , respectively) to charge capacitor CS 1  and thereby decrease the recovery time. By decreasing the recovery time, the start-up circuitry  110  reduces the delay from when the input voltage VIN stops decreasing and the second output node OUT 2  returns to its quiescent state. Thus, the duration of the incorrect output of the logic output signal OUTZ is significantly reduced. 
     In order to accelerate the recovery of sensing capacitor CS 1 , the acceleration circuitry  116  draws additional current I A  from node  120 . The additional current I A  is mirrored by the fourth current mirror  134 , which causes I M3  and I M4  to supply additional current to the sensing capacitor CS 1 , thereby accelerating the charging of CS 1  and reducing the time required for VCS 1  to reach its quiescent state. 
     Operation of the disclosed bidirectional voltage differentiator circuit  100 , including the acceleration functionality, is further illustrated by the simulation results  300  illustrated in  FIG. 3 . In the simulation shown in  FIG. 3 , VIN increases from zero to 12V with a 64 us rising time and decreases from 12V to 8V with a 20 us falling time. In general, when VIN is increasing or decreasing, OUTZ is logic high, and when VIN is constant, OUTZ is logic low. As shown in  FIG. 3 , the logic output signal OUTZ changes states when the input voltage varies by approximately 0.12V. Additionally, after VIN increases, the falling OUTZ signal is delayed by approximately 2 us while OUT 1  returns to its quiescent state, and after VIN decreases, the falling OUTZ signal is delayed by approximately 7 us while OUT 2  returns to its quiescent state. 
     It should be appreciated by one of ordinary skill in the art that the embodiment disclosed herein is provided to illustrate one example for implementing a bidirectional voltage differentiator circuit in accordance with the present disclosure. As such, variations to the circuit illustrated in  FIG. 1  may be made without departing from the spirit or scope of the present disclosure as set forth in the claims provided below. For example,  FIGS. 4A and 4B  illustrate additional implementations of the disclosed bidirectional voltage differentiator circuit. 
     Reference is now made to  FIG. 5  which illustrates an application of the bidirectional voltage differentiator circuit ( FIG. 1, 4A or 4B ) to sense voltage of an LED panel. A circuit  300  for use with an LED panel  302  (such as an AMOLED (active-matrix organic light-emitting diode) panel known to those skilled in the art) comprises a power MOSFET  304  having a drain terminal coupled to a supply voltage Vsupply. The MOSFET  304  includes a gate terminal coupled to receive a control signal. The source terminal of the MOSFET  304  produces a panel voltage Vpanel and is coupled to the LED panel  302  (which those skilled in the art will recognize has an associated panel capacitance Cpanel). 
     It is important in operation of the LED panel  302  to determine the finish of power transmission. This occurs, for example, when the panel voltage Vpanel equals the supply voltage Vsupply, or when the panel voltage Vpanel equal some other known voltage. Prior art configurations inserted a sense resistor between the panel voltage Vpanel node and the source terminal of the MOSFET  304  in order to sense current flow to/from the panel. However, with an AMOLED panel there is a large current in the power MOSFET  304  which makes it difficult to add the prior art sense resistor configuration. 
     The bidirectional voltage differentiator circuit, in any of the implementations discussed above in  FIGS. 1, 4A and 4B , can be advantageously used to sense voltage of the LED panel. The VIN input node of the bidirectional voltage differentiator circuit is coupled to the source terminal of the MOSFET  304  which produces the panel voltage Vpanel. Thus, VIN will equal Vpanel. The state transitions of the OUT 1 , OUT 2  and OUTZ signals will then provide information indicative of the turning on of the MOSFET  304 , power transmission to/from the panel  302 , and finish of power transmission with respect to the panel  302 . 
     Reference is now made to  FIG. 6  which illustrates a waveform for a typical panel voltage Vpanel in an AMOLED panel and the timing diagram for logic states of the output signals for the bidirectional voltage differentiator circuit. As discussed above, the bidirectional voltage differentiator circuit operates as a slope detector. The OUT 1  signal transitions from a first logic state to a second logic state in response to an increase in voltage at the input VIN (positive slope detection), and transitions from the second logic state to the first logic state in response to termination of voltage increase. Thus, where VIN=Vpanel, a transition of the OUT 1  signal from the first logic state to the second logic state indicates an increase in the panel voltage Vpanel, while a transition in the OUT 1  signal from the second logic state to the first logic state indicates that the increase in panel voltage has terminated. In an AMOLED panel configuration with MOSFET  304 , the transition of the OUT 1  signal from the first logic state to the second logic state accordingly indicates the start of power transmission to the panel, while the transition in the OUT 1  signal from the second logic state to the first logic state indicates the finish of power transmission to the panel, such as when Vpanel=Vsupply. The OUTZ signal will accordingly transition from the second logic state to the first logic state at the beginning of power transmission to the panel, and transition from the first logic state to the second logic state at the finish of power transmission to the panel. 
     The foregoing describes operation in connection with a power transmission with a positive slope.  FIG. 6  further illustrates that the bidirectional voltage differentiator circuit will also operate to make power transmission detection when the power transition has a negative slope. The OUT 2  signal transitions from a first logic state to a second logic state in response to a decrease in voltage at the input VIN (negative slope detection), and transitions from the second logic state to the first logic state in response to termination of voltage decrease. Thus, where VIN=Vpanel, a transition of the OUT 2  signal from the first logic state to the second logic state indicates a decrease in the panel voltage Vpanel, while a transition in the OUT 2  signal from the second logic state to the first logic state indicates that the decrease in panel voltage has terminated. In an AMOLED panel configuration with MOSFET  304 , the transition of the OUT 2  signal from the first logic state to the second logic state accordingly indicates the start of power transmission from the panel, while the transition in the OUT 2  signal from the second logic state to the first logic state indicates the finish of power transmission from the panel, such as when Vpanel=VIN 2 . The OUTZ signal will accordingly transition from the second logic state to the first logic state at the beginning of power transmission from the panel, and transition from the first logic state to the second logic state at the finish of power transmission from the panel. 
     When there is no variation in panel voltage Vpanel, the OUTZ signal is stays at the second logic level. The OUTZ signal can thus be used to trigger detection of power transmission completion. However, during any variation in panel voltage (positive or negative, and indicative of power transmission with respect to the panel), the OUTZ signal transitions to the first logic level and stays at the first logic level for as long as panel voltage variation (power transmission) continues. The OUTZ signal can thus be used to trigger slope control operations for the panel. Specifically, when the OUTZ signal transitions to the first logic level (indicative of a sensed slope change at the VIN node), this logic state can be detected by a control circuit for the panel and used to trigger actions taken to control the rate of change (i.e., a slope control mode of operation).