Patent Publication Number: US-2023143829-A1

Title: Page buffer circuit and memory device including the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application Nos. 10-2021-0154254, filed on Nov. 10, 2021, and 10-2022-0066917, filed on May 31, 2022, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties. 
     BACKGROUND 
     The inventive concept relates to a memory device, and more particularly, to a page buffer circuit and a memory device including the page buffer circuit. 
     Recently, along with the multifunctionalization of information and communication devices, memory devices with larger capacity and higher integration are demanded. A memory device may include a page buffer for storing data in or outputting data from memory cells, and the page buffer may include semiconductor devices like transistors. Sizes of semiconductor devices included in a page buffer may be reduced according to a demand for reducing the size of a page buffer according to an increase in the degree of integration of a memory device and a development of process technology, and thus, the layout of wires connected to semiconductor devices may become complicated. 
     SUMMARY 
     Aspects of the inventive concept provides a page buffer circuit and a memory device including the page buffer circuit, wherein the sensing reliability of the memory device is increased by reducing the size of a page buffer. 
     According to an aspect of the inventive concept, a memory device includes a memory cell array including a plurality of memory cells connected to bit lines, and a page buffer circuit connected to the bit lines, wherein the page buffer circuit includes page buffer units comprising a first set of page buffer units arranged in a first direction and a second set of page buffer units arranged in the first direction; and cache units arranged, in the first direction, between the first set of page buffer units and the second set of page buffer units, the cache units comprising first cache units respectively corresponding to the first set of page buffer units and second cache units respectively corresponding to the second set of page buffer units. Each of the page buffer units comprises a sensing node and a pass transistor connected to the sensing node and configured to be selectively turned on during a data transmission period, the first cache units share a first combined sensing node, and the first combined sensing node is connected to a pass transistor included in an first page buffer unit adjacent to the first cache units from among the first set of page buffer units, the second cache units share a second combined sensing node, and the second combined sensing node is connected to a pass transistor included in a second page buffer unit adjacent to the second cache units from among the second set of page buffer units, and, the sensing nodes respectively corresponding to the page buffer units are configured to, during the data transmission period, be electrically connected to one another through serial connections of pass transistors respectively included in the page buffer units. 
     According to another aspect of the inventive concept, a memory device includes a memory cell array including a plurality of memory cells connected to bit lines, and a page buffer circuit connected to the bit lines and arranged in first to fourth regions arranged in a first direction, wherein the page buffer circuit include upper page buffer units arranged in the first region in the first direction and each including an upper pass transistor and an upper sensing node line, lower page buffer units arranged in the fourth region in the first direction and each including a lower pass transistor and a lower sensing node line, upper cache units arranged in the second region in the first direction and commonly connected to a first combined sensing node, and lower cache units arranged in the third region in the first direction and commonly connected to a second combined sensing node. The memory device is configured such that, in a data transmission period, upper sensing node lines respectively included in the upper page buffer units are connected to the first combined sensing node as upper pass transistors respectively included in the upper page buffer units are turned on and lower sensing node lines respectively included in the lower page buffer units are connected to the second combined sensing node as lower pass transistors respectively included in the lower page buffer units are turned on. The upper sensing node lines and the lower sensing node lines are arranged along a line in the first direction. 
     According to another aspect of the inventive concept, there memory device includes a memory cell array including a plurality of memory cells connected to bit lines, a page buffer circuit comprising first page buffer units, second page buffer units, and cache units, which are arranged between the first page buffer units and the second page buffer units and comprise first cache units and second cache units. The memory device is configured such that, in a data transmission period, first data transmission operations between the first page buffer units and the first cache units are performed simultaneously with second data transmission operations between the second page buffer units and the second cache units, in a first period of a pass/fail determination period after the data transmission period, first pass/fail determination operations regarding the first page buffer units are sequentially performed, and, in a second period of the pass/fail determination period, second pass/fail determination operations regarding the second page buffer units are sequentially performed. 
     According to another aspect of the inventive concept, a page buffer circuit includes upper page buffer units arranged in a first region in a first direction and each including an upper pass transistor and an upper sensing node line, upper cache units arranged in a second region in the first direction and commonly connected to a first combined sensing node, lower cache units arranged in a third region in the first direction and commonly connected to a second combined sensing node, and lower page buffer units arranged in a fourth region in the first direction and each including a lower pass transistor and a lower sensing node line. The page buffer circuit is configured such that, in a data sensing period, upper pass transistors respectively included in the upper page buffer units and lower pass transistors respectively included in the lower page buffer units are turned off, in a data transmission period after the data sensing period, upper sensing node lines respectively included in the upper page buffer units are connected to the first combined sensing node as the upper pass transistors are turned on and lower sensing node lines respectively included in the lower page buffer units are connected to the second combined sensing node as the lower pass transistors are turned on. The first to fourth regions are arranged in the first direction, and the upper sensing node lines and the lower sensing node lines are arranged along a line in the first direction. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG.  1    is a block diagram showing a memory device according to an embodiment; 
         FIG.  2    is a diagram schematically showing the structure of the memory device of  FIG.  1   , according to an embodiment; 
         FIG.  3    is a diagram showing an example of a memory cell array of  FIG.  1   , according to an embodiment; 
         FIGS.  4 A and  4 B  are perspective views of a memory block of  FIG.  3   , according to some embodiments; 
         FIG.  5    is a diagram showing an example of a connection between a memory cell array and a page buffer circuit according to an embodiment; 
         FIG.  6    is a diagram showing a page buffer of  FIG.  1    in detail, according to an embodiment; 
         FIGS.  7  and  8    are timing diagrams showing examples of voltage levels of a pass control signal according to a core operation sequence, according to an embodiment; 
         FIG.  9    is a diagram showing a page buffer circuit and a page buffer decoder according to an embodiment; 
         FIG.  10    is a diagram showing a page buffer circuit and a page buffer decoder according to an embodiment in more details; 
         FIG.  11    is a plan view of a partial area of a page buffer circuit according to an embodiment; 
         FIG.  12    is a circuit diagram showing the partial area of a page buffer circuit according to an embodiment; 
         FIG.  13    is a circuit diagram showing a page buffer circuit according to an embodiment; 
         FIG.  14    is a circuit diagram showing a cache unit according to an embodiment; 
         FIG.  15    is a timing diagram showing an example of a data transmission operation according to an embodiment; 
         FIG.  16    is a timing diagram showing an example of a pass/fail determination operation according to an embodiment; 
         FIG.  17    is a diagram showing a page buffer circuit and a page buffer decoder according to an embodiment; 
         FIG.  18    is a diagram showing a page buffer circuit and a page buffer decoder according to an embodiment in more details; 
         FIG.  19    is a circuit diagram showing the partial area of a page buffer circuit according to an embodiment; 
         FIG.  20    is a circuit diagram showing a partial region of a page buffer circuit and a page buffer decoder according to an embodiment; 
         FIG.  21    is a timing diagram showing an example of a data transmission operation according to an embodiment; 
         FIG.  22    is a timing diagram showing an example of a pass/fail determination operation according to an embodiment; 
         FIG.  23    is a circuit diagram showing a page buffer according to an embodiment; 
         FIG.  24    is a diagram showing a page buffer decoder and a mass bit counter according to an embodiment; and 
         FIG.  25    is a cross-sectional view of a memory device having a bonding vertical NAND (B-VNAND) structure, according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG.  1    is a block diagram showing the memory device  10  according to an embodiment. Referring to  FIG.  1   , the memory device  10  may include a memory cell array  100  and a peripheral circuit  200 , and the peripheral circuit  200  may include a page buffer circuit  210 , a control circuit  220 , a voltage generator  230 , a row decoder  240 , a page buffer decoder (PBDEC)  213 , a mass bit counter (MBC)  214 , and a pass/fail checking unit  215 . 
     The memory cell array  100  may be connected to the page buffer circuit  210  through bit lines BL and may be connected to the row decoder  240  through word lines WL, string select lines SSL, and ground select lines GSL. The memory cell array  100  may include a plurality of memory cells. For example, the memory cells may be flash memory cells. Hereinafter, embodiments of the inventive concept will be described in detail based on an example case where the memory cells are nonvolatile memory cells such as NAND flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be resistive memory cells like resistive RAM (ReRAM) cells, phase change RAM (PRAM) cells, or magnetic RAM (MRAM) cells. 
     In an embodiment, the memory cell array  100  may include a 3-dimensional memory cell array. The 3-dimensional memory cell array may include a plurality of NAND strings, and each NAND string may include memory cells respectively connected to word lines vertically stacked on a substrate. Detailed descriptions thereof will be given later with reference to  FIGS.  3 ,  4 A , and  4 B. U.S. Pat. Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application No. 2011/0233648 disclose detailed suitable configurations for a 3-dimensional memory array including multiple levels and in which word lines and/or bit lines are shared between the levels, and are incorporated herein by reference in their entirety. 
     The control circuit  220  may output various control signals, e.g., a voltage control signal CTRL_vol, a row address X_ADDR, and a column address Y_ADDR, for programming data to the memory cell array  100 , reading data from the memory cell array  100 , or erasing data stored in the memory cell array  100 , based on a command CMD, an address ADDR, and a control signal CTRL. Therefore, the control circuit  220  may overall control various operations within the memory device  10 . 
     The voltage generator  230  may generate various types of voltages for performing a program operation, a read operation, and an erase operation on the memory cell array  100  based on the voltage control signal CTRL_Vol. In detail, the voltage generator  230  may generate a word line voltage VWL, e.g., a program voltage, a read voltage, a pass voltage, an erase verify voltage, or a program verify voltage. The row decoder  240  may select one of a plurality of memory blocks in response to the row address X_ADDR, may select one of the word lines WL of a selected memory block, and may select one of the string select lines SSL. The page buffer circuit  230  may select at least some bit lines from among the bit lines BL in response to the column address Y_ADDR. In detail, the page buffer circuit  210  operates as a write driver or a sense amplifier depending on an operation mode. 
     The page buffer circuit  210  may include a plurality of page buffers PB respectively connected to a plurality of bit lines BL. Page buffer units (e.g., PBU 0  to PBUn of  FIG.  5   ) respectively included in the page buffers PB and cache latches (e.g., CL 0  to CLn of  FIG.  5   ) respectively included in the page buffers PB may be spaced apart from each other and have separate structures. Therefore, the degree of freedom for the wires arranged above the page buffer units may be improved and the complexity of the layout may be reduced. Also, since the cache latches are arranged adjacent to data input/output lines, a distance between the cache latches and the data input/output lines may be reduced, thereby improving a data input/output speed. Also, the page buffer units may be divided into two groups each including upper page buffer units, upper page buffer units and lower page buffer units, or lower page buffer units, and cache latches may be arranged between the upper page buffer units and the lower page buffer units. 
     According to an embodiment, each page buffer unit may include a pair of pass transistors (e.g., TR 0  and TR 0 ′ of  FIG.  11   ) and a sensing node line (e.g., MT 0   a  of  FIG.  11   ) for electrically connecting the pair of pass transistors to each other. Here, the sensing node line may be implemented as one track of a lower metal layer (e.g., LM 0  of  FIG.  11   ) and may correspond to a sensing node. A “track” as described herein, refers to a straight segment of material extending lengthwise in only one horizontal direction. An item, layer, or portion of an item or layer described as extending “lengthwise” in a particular direction has a length in the particular direction and a width perpendicular to that direction, where the length is greater than the width. During a data sensing period, pass transistors respectively included in the page buffer units may not be electrically connected to each other, and thus sensing node lines respectively included in the page buffer units may not be electrically connected to each other. Meanwhile, during a data transmission period, the pass transistors respectively included in the page buffer units may be connected to each other in series, and thus the sensing node lines respectively included in the page buffer units may be electrically connected to each other and used as data transmission lines. Therefore, since the page buffer circuit  210  does not need to separately provide a plurality of data transmission lines for respectively connecting the page buffer units and the cache latches, the area occupied by the page buffer circuit  210  may be reduced. 
     The PBDEC  213  may generate a decoder output signal DS corresponding to the number of fail bits from a page buffer signal PBS received from the page buffer circuit  210 . For example, when the page buffer signal PBS is logic low, it may be determined that programming to a corresponding memory cell has failed, and data of the corresponding memory cell may be determined as a fail bit. In detail, the PBDEC  213  may receive a reference current from a current generator (not shown) and generate the decoder output signal DS based on the received reference current. 
     The MBC  214  may receive the decoder output signal DS from the PBDEC  213  and generate a count result CNT from the decoder output signal DS. For example, the MBC  214  may be an analog-to-digital converter that converts the decoder output signal DS that is an analog signal into a count result CNT that is a digital signal. In detail, the MBC  214  may receive a reference current from the current generator (not shown) and generate the count result CNT based on the received reference current. 
     The pass/fail checking unit  215 , which may be a circuit, may receive the count result CNT from the MBC  214 , generate a pass signal PASS or a fail signal FAIL based on the count result CNT, and provide the pass signal PASS or the fail signal FAIL to the control circuit  220 . For example, when the count result CNT is less than or equal to a reference number, the pass/fail checking unit  215  may generate the pass signal PASS. When the count result CNT is greater than the reference number, the pass/fail checking unit  215  may generate the fail signal FAIL. 
       FIG.  2    is a diagram schematically showing the structure of the memory device  10  of  FIG.  1   , according to an embodiment. Referring to  FIG.  2   , the memory device  10  may include a first semiconductor layer L  1  and a second semiconductor layer L 2 , and the first semiconductor layer L 1  may be stacked in a vertical direction VD with respect to the second semiconductor layer L 2 . In detail, the second semiconductor layer L 2  may be disposed below the first semiconductor layer L 1  in the vertical direction VD. According to an embodiment, the memory cell array  100  of  FIG.  1    may be formed in the first semiconductor layer L 1 , and the peripheral circuit  200  of  FIG.  1    may be formed in the second semiconductor layer L 2 . Therefore, the memory device  10  may have a structure in which the memory cell array  100  is disposed above the peripheral circuit  200 , that is, a cell-over-periphery (COP) structure. The COP structure may reduce a horizontal area and improve the degree of integration of the memory device  10 . 
     In an embodiment, the second semiconductor layer L 2  may include a substrate, and the peripheral circuit  200  may be formed in the second semiconductor layer L 2  by forming transistors and metal patterns (e.g., first and third lower metal layers LM 0  and LM 2  of  FIG.  11   ) for wiring the transistors on the substrate. After the peripheral circuit  200  is formed on the second semiconductor layer L 2 , the first semiconductor layer L 1  including the memory cell array  100  may be formed, and metal patterns for electrically connecting the word lines WL and the bit lines BL of the memory cell array  100  to the peripheral circuit  200  formed in the second semiconductor layer L 2  may be formed. For example, the bit lines BL may extend in a first horizontal direction or a first direction HD 1 , and the word lines WL may extend in a second horizontal direction or a second direction HD 2 . 
     As the number of stacks of memory cells arranged in the memory cell array  100  increases (i.e., as the number of stacks of the word lines WL increases) with the development of semiconductor processing technology, the area of the memory cell array  100  is reduced, and thus the area of the peripheral circuit  200  is also reduced. According to the present embodiment, the page buffer circuit  210  has a structure in which page buffer units and cache latches are separated from each other, and, by connecting sensing nodes included in the respective page buffer units in common to a combined sensing node, the area occupied by the page buffer circuit  210  may be reduced. Detailed descriptions thereof will be given later with reference to  FIG.  11   . 
       FIG.  3    is a diagram showing an example of the memory cell array  100  of  FIG.  1   , according to an embodiment. Referring to  FIG.  3   , the memory cell array  100  may include a plurality of memory blocks BLK 0  to BLKi, and i may be a positive integer. The memory blocks BLK 1  to BLKi may each have a 3-dimensional structure (or a vertical structure). The memory blocks BLK 0  to BLKi may each include a plurality of NAND strings extending in the vertical direction VD. Here, the NAND strings may be provided to be a particular distance spaced apart from one another in the first direction HD 1  and the second direction HD 2 . 
       FIG.  4 A  is a perspective view of a memory block BLKa according to an embodiment. Referring to  FIG.  4 A , the memory block BLKa may correspond to one of the memory blocks BLK 1  to BLKi of  FIG.  3   . The memory block BLKa is formed in the vertical direction VD with respect to a substrate SUB having a first conductivity type (e.g., p-type). According to an embodiment, the common source line CSL doped with impurities of a second conductivity type (e.g., n-type) may be provided on the substrate SUB. According to an embodiment, the substrate SUB may be implemented by using polysilicon, and a plate-type common source line CSL may be disposed on the substrate SUB. On the substrate SUB, a plurality of insulation layers IL extending in the second direction HD 2  are sequentially provided in the vertical direction VD, and the insulation layers IL are spaced apart from one another by a certain distance in the vertical direction VD. For example, the insulation layers IL may include or may be formed of an insulating material like silicon oxide. 
     A plurality of pillars P connected to each bit line, which pillars are sequentially arranged in the first direction HD 1  and penetrate through the insulation layers IL in the vertical direction VD, are provided on the substrate SUB. For example, the pillars P will contact the substrate SUB by penetrating through the insulation layers IL. In detail, a surface layer S of each pillar P may include or be formed of a silicon-based material doped with impurities of the first conductivity type and function as a channel region. Therefore, the pillars P may be referred to as a vertical channel structure. An internal layer I of each pillar P may include an insulating material like silicon oxide or an air gap. 
     A charge storage layer CS is provided along exposed surfaces of the insulation layers IL, the pillars P, and the substrate SUB. The charge storage layer CS may include a gate insulation layer, a charge trapping layer, and a blocking insulation layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. Also, on an exposed surface of the charge storage layer CS, gate electrodes GE such as a ground select line GSL, a string select line SSL, and word lines WL 1  to WL 8  are provided. Drains DR are provided on the pillars P, respectively. For example, the drains DR may include or be formed of a silicon-based material doped with impurities of the second conductivity type. Bit lines BL 1  to BL 3  extending in a first direction HD 1  and being a certain distance apart from one another in the second direction HD 2  may be provided on the drains DR. 
       FIG.  4 B  is a perspective view of a memory block BLKb according to an embodiment. Referring to  FIG.  4 B , the memory block BLKb may correspond to one of the memory blocks BLK 1  to BLKi of  FIG.  3   . Also, the memory block BLKb corresponds to a modified example of the memory block BLKa of  FIG.  4 A , and the descriptions given above with reference to  FIG.  4 A  may also be applied to the present embodiment. The memory block BLKb may include a first memory stack ST 1  and a second memory stack ST 2  stacked in the vertical direction VD. However, the inventive concept is not limited thereto, and the memory block BLKb may include three or more memory stacks. 
       FIG.  5    is a diagram showing an example of the connection between the memory cell array  100  and the page buffer circuit  210  according to an embodiment. 
     Referring to  FIG.  5   , the memory cell array  100  may include first to n+1-th NAND strings NS 0  to NSn, the first to n+1-th NAND strings NS 0  to NSn may each include a ground select transistor GST connected to a ground select line GSL, a plurality of memory cells MC respectively connected to a plurality of word lines WL 0  to WLm, and a string select transistor SST connected to a string select line SSL, and the ground select transistor GST, the memory cells MC, and the string select transistor SST may be connected to one another in series and may be arranged in a vertical direction. Here, m is a positive integer. 
     The page buffer circuit  210  may include first to n+1-th page buffer units PBU 0  to PBUn. A first page buffer unit PBU 0  is connected to a first NAND string NS 0  through a first bit line BL 0 , and an n+1-th page buffer unit PBUn may be connected to an n+1-th NAND string NSn through an n+1th bit line BLn. Here, n is a positive integer. For example, n may be 7, and the first to n+1-th page buffer units PBU 0  to PBUn of the page buffer circuit  210  may be divided into an upper page buffer group and a lower page buffer group, wherein page buffer units included in the upper page buffer group may be arranged along a line, and page buffer units included in the lower page buffer group may be arranged along a line. Each page buffer unit may be described as a page buffer segment, since it is part of the page buffer circuit as a whole. Each page buffer unit may include a circuit that outputs a data bit corresponding to data being written to or read from a memory cell. 
     The page buffer circuit  210  may further include first to n+1-th cache latches CL 0  to CLn respectively corresponding to the first to n+1-th page buffer units PBU 0  to PBUn. For example, n may be  7 , and the page buffer circuit  210  may have a structure in which eight cache latches CL 0  to CLn are arranged along a line. For example, the first to n+1-th cache latches CL 0  to CLn may be arranged along a line in a direction in which first to n+1-th bit lines BL 0  to BLn extend between the upper page buffer group and the lower page buffer group. 
     Sensing nodes of the first to n+1-th page buffer units PBU 0  to PBUn may be commonly connected to a combined sensing node SOC, and the first to n+1-th cache latches CL 0  to CLn may also be commonly connected to the SOC. Therefore, the first to n+1-th page buffer units PBU 0  to PBUn may be connected to the first to n+1-th cache latches CL 0  to CLn through the combined sensing node SOC. 
       FIG.  6    is a diagram showing a page buffer PB according to an embodiment. 
     Referring to  FIG.  6   , the page buffer PB may correspond to an example of the page buffer PB of  FIG.  1   . The page buffer PB may include a page buffer unit PBU and a cache unit CU. Since the cache unit CU includes a cache latch CL (C-LATCH), and the cache latch CL is connected to a data input/output line, the cache unit CU may be disposed adjacent to the data input/output line. Therefore, the page buffer unit PBU and the cache unit CU may be disposed to be spaced apart from each other, and thus the page buffer PB may have a structure in which the page buffer unit PBU and the cache unit CU are separated from each other. 
     The page buffer unit PBU may include a main unit MU, and the main unit MU may include major transistors in the page buffer PB. The page buffer unit PBU may further include a bit line select transistor TR_hv connected to a bit line BL and driven by a bit line select signal BLSLT. The bit line selection transistor TR_hv may be implemented as a high-voltage transistor and may be disposed in a well region different from the main unit MU, that is, in a high-voltage unit HVU. 
     The main unit MU may include a sensing latch SL (S-LATCH), a force latch FL (F-LATCH), an upper bit latch or most-significant-bit latch ML (M-LATCH), and a lower bit latch or a least-significant-bit latch LL (L-LATCH). According to some embodiments, the sensing latch SL, the force latch FL, the more-significant-bit latch ML, or the less-significant-bit latch LL may be referred to as a “main latch”. The main unit MU may further include a pre-charge circuit PC capable of controlling a pre-charge operation for the bit line BL or a sensing node SO based on a bit line clamping control signal BLCLAMP and may further include a transistor PM′ driven by a bit line setup signal BLSETUP. 
     The sensing latch SL may store data stored in a memory cell or a result of sensing a threshold voltage of a memory cell during a read operation or a program verification operation. Also, the sensing latch SL may be used to apply a program bit line voltage or a program inhibit voltage to the bit line BL during a program operation. The force latch FL may be used to store force data and improve threshold voltage distribution during a program operation. The force data may be initially set to ‘1’ and then inverted to ‘0’ when the threshold voltage of a memory cell enters a forcing region that is less than a target region. The more-significant-bit latch ML, the less-significant-bit latch LL, and the cache latch CL may be used to store data input from the outside during a program operation. The cache latch CL may receive data read from a memory cell during a read operation from the sensing latch SL and output the data to the outside through a data input/output line. 
     The main unit MU may further include first to fourth transistors NM 1  to NM 4 . A first transistor NM 1  may be connected between the sensing node SO and the sensing latch SL and may be driven by a ground control signal SOGND. A second transistor NM 2  may be connected between the sensing node SO and the force latch FL and may be driven by a forcing monitoring signal MON_F. A third transistor NM 3  may be connected between the sensing node SO and the more-significant-bit latch ML and may be driven by a more-significant-bit monitoring signal MON_M. A fourth transistor NM 4  may be connected between the sensing node SO and the less-significant-bit latch LL and may be driven by a less-significant-bit monitoring signal MON_L. 
     The main unit MU may further include a fifth transistor NM 5  and a sixth transistor NM 6  connected in series between the bit line select transistor TR_hv and the sensing node SO. A fifth transistor NM 5  may be driven by a bit line shut-off signal BLSHF, and a sixth transistor NM 6  may be driven by a bit line connection control signal CLBLK. Also, the main unit MU may further include a pre-charge transistor PM. The pre-charge transistor PM is connected to the sensing node SO, is driven by a load signal LOAD, and pre-charges the sensing node SO to a pre-charge level during a pre-charge period. 
     The main unit MU may further include a pair of pass transistors connected to the sensing node SO, that is, a first pass transistor TR and a second pass transistor TR′. According to some embodiments, the first pass transistor TR and the second pass transistors TR′ may be referred to as “a first sensing node connecting transistor and a second sensing node connecting transistor”, respectively. The first pass transistor TR and the second pass transistors TR′ may be driven according to a pass control signal SO_PASS. According to some embodiments, the pass control signal SO_PASS may be referred to as a “sensing node connection control signal”. A first pass transistor TR may be connected between a first terminal SOC_U and the sensing node SO, and a second pass transistor TR′ may be connected between the sensing node SO and a second terminal SOC_D. 
     For example, when the page buffer unit PBU is a second page buffer unit PBU 1  of  FIG.  5   , the first terminal SOC_U may be connected to one end of a pass transistor included in the first page buffer unit PBU 0 , and the second terminal SOC_D may be connected to one end of a pass transistor included in a third page buffer unit PBU 2 . Therefore, the sensing node SO may be electrically connected to the combined sensing node SOC through pass transistors respectively included in third to n+1-th page buffer units PBU 2  to PBUn. 
       FIG.  7    is a timing diagram showing an example of voltage levels of a pass control signal according to a core operation sequence, according to an embodiment. Referring to  FIGS.  6  and  7    together, the core operation sequence represents the operation of the page buffer PB. For example, the core operation sequence may include a data sensing period  71  in which a data sensing operation is performed and a data dumping period or a data transmission period  72  in which a data dumping operation or a data transmission operation is performed. 
     In the data sensing period  71 , the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the combined sensing node SOC, and the page buffer unit PBU may not be electrically connected to the cache unit CU. Also, the page buffer unit PBU may not be electrically connected to an adjacent page buffer unit PBU. For example, the data sensing period  71  may include a pre-charge period for pre-charging the voltage of the bit line BL or the sensing node SO to a pre-charge level, a develop period for electrically connecting the bit line BL to the sensing node SO to develop the voltage of the sensing node SO, and a sensing period for sensing the voltage of the sensing node SO. 
     In the data transmission period  72 , the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. Therefore, the page buffer unit PBU may be electrically connected to the combined sensing node SOC, and the page buffer unit PBU may be electrically connected to the cache unit CU. Also, the page buffer unit PBU may be electrically connected to an adjacent page buffer unit PBU. For example, the data transmission period  72  may include a period in which an operation of dumping read data stored in the sensing latch SL to the cache latch CL is performed, a period in which an operation of dumping program data stored in the cache latch CL to the sensing latch SL is performed, or a period in which data stored in the cache latch CL is transmitted to a data input/output circuit. 
       FIG.  8    is a timing diagram showing another example of voltage levels of a pass control signal according to a core operation sequence, according to an embodiment. Referring to  FIGS.  6  and  8    together, the core operation sequence represents the operation of the page buffer PB. For example, the core operation sequence may include a bit line setup period  81 , a forcing dumping period  82 , a bit line forcing period  83 , a data dumping period or a data transmission period  84 , and an MBC period  85 . 
     In the bit line setup period  81 , the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. At this time, as the sensing node SO and the combined sensing node SOC are electrically connected, data may be dumped from the main latch (e.g., the sensing latch SL, the force latch FL, the more-significant-bit latch ML, or the less-significant-bit latch LL) included in the page buffer unit PBU to the cache latch CL. 
     In the forcing dumping period  82  and the bit line forcing period  83 , the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the cache unit CU and may not be electrically connected to an adjacent page buffer unit PBU. In the forcing dumping period  82 , a dumping operation may be performed to select a bit line to be forced to a bias lower than a power voltage level when a program operation is performed. For example, data may be dumped from the force latch FL to the sensing latch SL. In the bit line forcing period  83 , a voltage applied to the bit line BL may be changed according to a value stored in the force latch FL during a program operation. 
     In the data transmission period  84 , the pass control signal SO_PASS may be activated, and the first pass transistor TR and the second pass transistors TR′ may be turned on. For example, in the data transmission period  84 , a dumping operation of marking data stored in the sensing latch SL connected to memory cells, which failed as a result of a program verification, from among memory cells, which are to be programmed to a target program state when a program operation is performed, as logic low may be performed. Here, as the sensing node SO and the combined sensing node SOC are electrically connected, data may be dumped from the cache latch CL to the main latch (e.g., the sensing latch SL). 
     In the MBC period  85 , the pass control signal SO_PASS may be deactivated, and the first pass transistor TR and the second pass transistors TR′ may be turned off. Therefore, the page buffer unit PBU may not be electrically connected to the cache unit CU and may not be electrically connected to an adjacent page buffer unit PBU. In the MBC period  85 , the number of sensing latches marked as logic low in the previous data transmission period  84  may be counted. 
       FIG.  9    is a diagram showing the page buffer circuit  210  and the PBDEC  213  according to an embodiment. Referring to  FIG.  9   , the page buffer circuit  210  may have a structure having multiple stages in the first direction HD 1 , e.g., 8-stages STAGE 0  to STAGE 7 . The page buffer circuit  210  includes first to fourth page buffer circuits PGBUFa to PGBUFd arranged along the second direction HD 2 , and the first to fourth page buffer circuits PGBUFa to PGBUFd may be referred to as “first to fourth page buffer columns”. The first to fourth page buffer circuits PGBUFa to PGBUFd may each include first to eighth page buffer units PBU 0  to PBU 7  and first to eighth cache units CU 0  to CU 7  arranged in the first direction HD 1 . Here, the number of page buffer columns included in the page buffer circuit  210  and the number of page buffer units and the number of cache units included in each page buffer column may be variously changed according to embodiments. It should be noted that the first direction HD 1  and second direction HD 2  refer to horizontal directions, in relation to the vertical direction VD described, for example, in connection with  FIGS.  2 ,  3 ,  4 A, and  4 B . 
     Since the size of the first to eighth page buffer units PBU 0  to PBU 7  in the second direction HD 2  decreases as the width of a transistor decreases, more page buffer units can be included in the same row in the page buffer circuit  210  (e.g., a row extends in the HD 2  direction). Therefore, the page buffer circuit  210  may be implemented as a page buffer array including the first to fourth page buffer circuits PGBUFa to PGBUFd. Hereinafter, the configuration of a first page buffer circuit PGBUFa will be described. Descriptions of the first page buffer circuit PGBUFa may also be applied to second to fourth page buffer circuits PGBUFb to PGBUFd. 
     The first to eighth page buffer units PBU 0  to PBU 7  may be separated into two groups. First to fourth page buffer units PBU 0  to PBU 3  corresponding to first to fourth stages STAGE 0  to STAGE 3  may be referred to as upper page buffer units PBU 0  to PBU 3 , or a first set of page buffer units, and fifth to eighth page buffer units PBU 4  to PBU 7  corresponding to fifth to eighth stages STAGE 4  to STAGE 7  may be referred to as lower page buffer units PBU 4  to PBU 7 , or a second set of page buffer units. Each set of page buffer units may include a plurality of page buffer units directly and consecutively adjacent to each other in a particular direction (e.g., the HD 1  direction). 
     The first to eighth cache units CU 0  to CU 7  may be arranged between the upper page buffer units, e.g., the first to fourth page buffer units PBU 0  to PBU 3 , and the lower page buffer units, e.g., the fifth to eighth page buffer units PBU 4  to PBU 7 . For example, along the direction that the page buffer units are consecutively arranged (e.g., the HD 1  direction), the first to eighth cache units CU 0  to CU 7  may be arranged also along the same direction, and all of the first to eighth cache units CU 0  to CU 7  may be positioned between a first set of page buffer units and a second set of page buffer units. Here, the first to eighth cache units CU 0  to CU 7  may be separated into two groups, or sets. First to fourth cache units CU 0  to CU 3  may be arranged adjacent to the first to fourth page buffer units PBU 0  to PBU 3  in correspondence to the first to fourth page buffer units PBU 0  to PBU 3 , respectively, and may be referred to as upper cache units CU 0  to CU 3 , or a first set of cache units. Meanwhile, fifth to eighth cache units CU 4  to CU 7  may be arranged adjacent to the fifth to eighth page buffer units PBU 4  to PBU 7  in correspondence to the fifth to eighth page buffer units PBU 4  to PBU 7 , respectively, and may be referred to as or lower cache units CU 4  to CU 7 , or a second set of cache units. Ordinal numbers such as “first,” “second,” “third,” etc. may be used simply as labels of certain elements, steps, etc., to distinguish such elements, steps, etc. from one another. Terms that are not described using “first,” “second,” etc., in the specification, may still be referred to as “first” or “second” in a claim. In addition, a term that is referenced with a particular ordinal number (e.g., “first” in a particular claim) may be described elsewhere with a different ordinal number (e.g., “second” in the specification or another claim). Also, the terms “upper” and “lower” in the context of page buffer units and cache units and their related components as discussed in connection with  FIGS.  5 - 12    for example, may be used as a naming convention to refer to a set of units that are all at a particular location in relation to a second set of units. 
     In the first page buffer circuit PGBUFa, sensing nodes of the first to fourth page buffer units PBU 0  to PBU 3  may be commonly connected to a first combined sensing node SOC 1 , the first to fourth cache units CU 0  to CU 3  may be commonly connected to the first combined sensing node SOC 1 , sensing nodes of the fifth to eighth page buffer units PBU 4  to PBU 7  may be commonly connected to a second combined sensing node SOC 1 ′, and the fifth to eighth cache units CU 4  to CU 7  may be commonly connected to the second combined sensing node SOC 1 ′. Similarly, a second page buffer circuit PGBUFb may include a first combined sensing node SOC 2  and a second combined sensing node SOC 2 ′, a third page buffer circuit PGBUFc may include a first combined sensing node SOC 3  and a second combined sensing node SOC 3 ′, and a fourth page buffer circuit PGBUFd may include a first combined sensing node SOC 4  and a second combined sensing node SOC 4 ′. 
     The PBDEC  213  may be disposed between the first to fourth cache units CU 0  to CU 3  and the fifth to eighth cache units CU 4  to CU 7 . The PBDEC  213  may include first to fourth PBDECs PBDECa to PBDECd arranged in the second direction HD 2 , and the first to fourth PBDECs PBDECa to PBDECd may be connected to the first to fourth page buffer circuits PGBUFa to PGBUFd, respectively. A first PBDEC PBDECa may be connected to the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3  and may also be connected to the fifth to eighth page buffer units PBU 4  to PBU 7  and the fifth to eighth cache units CU 4  to CU 7 . 
       FIG.  10    is a diagram showing the page buffer circuit  210  and the PBDEC  213  according to an embodiment in more detail. Referring to  FIG.  10   , the page buffer circuit  210  may include first to fourth areas AR 1  to AR 4  arranged in the first direction HD 1 . The first to fourth page buffer units PBU 0  to PBU 3  may be arranged in a first area AR 1 , the first to fourth cache units CU 0  to CU 3  may be arranged in a second area AR 2 , the fifth to eighth cache units CU 4  to CU 7  may be arranged in a third area AR 3 , and the fifth to eighth page buffer units PBU 4  to PBU 7  may be arranged in a fourth area AR 4 . The PBDEC  213  may be disposed between the second area AR 2  and the third area AR 3 . 
     As described above with reference to  FIG.  6   , each page buffer unit PBU may include the main unit MU and the high-voltage unit HVU, and redundant descriptions thereof will be omitted. The first page buffer unit PBU 0  may include a main unit MU 0  and a high-voltage unit HVU 0 , the second page buffer unit PBU 1  may include a main unit MU 1  and a high-voltage unit HVU 1 , and a contact area THVa may be disposed between the first page buffer unit PBU 0  and the second page buffer unit PBU 1 . Similarly, a fifth page buffer unit PBU 4  may include a main unit MU 4  and a high-voltage unit HVU 4 , a sixth page buffer unit PBU 5  may include a main unit MU 5  and a high-voltage unit HVU 5 , and a contact area THVc may be disposed between the fifth page buffer unit PBU 4  and the sixth page buffer unit PBU 5 . 
     Main units MU 0  to MU 7  may each include a sensing node, and the sensing node is indicated by a dot in  FIG.  10   . The PBDEC  213  may be connected to sensing nodes included in main units MU 0  to MU 3  through an upper node and may be connected to sensing nodes included in main units MU 4  to MU 7  through a lower node. 
       FIG.  11    is a plan view of a partial area of a page buffer circuit PGBUF according to an embodiment.  FIG.  12    is a circuit diagram showing the partial area of a page buffer circuit PGBUF according to an embodiment. 
     Referring to  FIGS.  11  and  12    together, the page buffer circuit PGBUF may correspond to one of the first to fourth page buffer circuits PGBUFa to PGBUFd of  FIG.  9   . The page buffer circuit PGBUF may include the first to fourth page buffer units PBU 0  to PBU 3  arranged in the first area AR 1  and the first to fourth cache units CU 0  to CU 3  arranged in the second area AR 2 . Although  FIGS.  11  and  12    show only portions corresponding to the first area AR 1  and the second area AR 2  for convenience of illustration, the fifth to eighth cache units CU 4  to CU 7  and the fifth to eighth page buffer units PBU 4  to PBU 7  arranged in the third area AR 3  and the fourth area AR 4  may also be implemented similarly. 
     The first to fourth page buffer units PBU 0  to PBU 3  may each include two pass transistors, and thus the first to fourth page buffer units PBU 0  to PBU 3  may include total eight pass transistors TR 0 , TR 0 ′ to TR 3 , and TR 3 ′, wherein the eight pass transistors TR 0 , TR 0 ′ to TR 3 , and TR 3 ′ may be connected in series. For example, the first page buffer unit PBU 0  may include a first pass transistor TR 0  and a second pass transistor TR 0 ′ connected in series. For example, the first pass transistor TR 0  may be disposed adjacent to a first boundary of the first page buffer unit PBU 0 , the second pass transistor TR 0 ′ may be disposed adjacent to a second boundary of the first page buffer unit PBU 0 , and the first boundary and the second boundary may be opposite each other. For example, the first pass transistor TR 0  and the second pass transistor TR 0 ′ may be implemented as NMOS transistors, and thus the first pass transistor TR 0  and the second pass transistor TR 0 ′ may be arranged at opposite ends of a P well of the first page buffer unit PBU 0 . However, the inventive concept is not limited thereto. Meanwhile, another semiconductor device, e.g., a PM 0 S transistor or an NMOS transistor, may be further disposed between the first boundary of the first page buffer unit PBU 0  and the first pass transistor TR 0 . Similarly, another semiconductor device, e.g., a PM 0 S transistor or an NMOS transistor, may be further disposed between the second boundary of the first page buffer unit PBU 0  and the second pass transistor TR 0 ′. 
     For example, the first page buffer unit PBU 0  may further include a plurality of transistors (e.g., transistors included in the sensing latch SL, the force latch FL, the more-significant-bit latch ML, and the less-significant-bit latch LL of  FIG.  6   , first to sixth transistors NM 1  to NM 6 , etc.) arranged in the first direction HD 1  between the first pass transistor TR 0  and the second pass transistor TR 0 ′. Descriptions below will focus on the configuration of the first page buffer unit PBU 0 , and second to fourth page buffer units PBU 1  to PBU 3  may have substantially the same configuration as that of the first page buffer unit PBU 0 . 
     The first pass transistor TR 0  may include a source S 0 , a drain D 0 , and a gate G 0 , the source S 0  may be connected to a first terminal (e.g., SOC_U of  FIG.  6   ), the drain D 0  may be connected to a first sensing node SO 0 , and a first pass control signal SO_PASS 0  may be applied to the gate G 0 . The second pass transistor TR 0 ′ may include a source S 0 ′, a drain D 0 ′, and a gate G 0 ′, the source S 0 ′ may be connected to the first sensing node SO 0 , the drain D 0 ′ may be connected to a second terminal (e.g., SOC_D of  FIG.  6   ), and the first pass control signal SO_PASS 0  may be applied to the gate G 0 ′. 
     Similarly, the second page buffer unit PBU 1  may include a first pass transistor TR 1  and a second pass transistor TR 1 ′ connected in series. The first pass transistor TR 1  may include a source S 1 , a drain D 1 , and a gate G 1 , the second pass transistor TR 1 ′ may include a source S 1 ′, a drain D 1 ′, and a gate G 1 ′, and a second pass control signal SO_PASS 1  may be applied to gates G 1  and G 1 ′. The third page buffer unit PBU 2  may include a first pass transistor TR 2  and a second pass transistor TR 2 ′ connected in series. The first pass transistor TR 2  may include a source S 2 , a drain D 2 , and a gate G 2 , the second pass transistor TR 2 ′ may include a source S 2 ′, a drain D 2 ′, and a gate G 2 ′, and a third pass control signal SO_PASS 2  may be applied to gates G 2  and G 2 ′. The fourth page buffer unit PBU 3  may include a first pass transistor TR 3  and a second pass transistor TR 3 ′ connected in series. The first pass transistor TR 3  may include a source S 3 , a drain D 3 , and a gate G 3 , the second pass transistor TR 3 ′ may include a source S 3 ′, a drain D 3 ′, and a gate G 3 ′, and a fourth pass control signal SO_PASS 3  may be applied to gates G 3  and G 3 ′. However, the inventive concept is not limited thereto, and, according to some embodiments, a combined sensing node pass control signal SOC_PASS may be applied to the gate G 3 ′. 
     A first cache unit CU 0  may include a monitor transistor NM 7   a,  the monitor transistor NM 7   a  may include a source S, a drain D, and a gate G, the source S may be connected to the first combined sensing node SOC 1 , and a cache monitoring signal MON_C 0  may be applied to the gate G. For example, the monitor transistor NM 7   a  may correspond to a transistor NM 7  of  FIG.  6   . The first cache unit CU 0  may further include a plurality of transistors arranged in the first direction HD 1  (e.g., a plurality of transistors included in the cache latch CL of  FIG.  6   ). Second to fourth cache units CU 1  to CU 3  may each have substantially the same configuration as that of the first cache unit CU 0 . Monitor transistors NM 7   a  to NM 7   d  respectively included in the first to fourth cache units CU 0  to CU 3  may be commonly connected in parallel to the first combined sensing node SOC 1 . In detail, sources of the monitor transistors NM 7   a  to NM 7   d  may be commonly connected to the first combined sensing node SOC 1 . 
     In the first page buffer unit PBU 0 , the drain D 0  of the first pass transistor TR 0  and the source S 0 ′ of the second pass transistor TR 0 ′ may be connected to each other through a first conductive line or a first metal pattern MT 0   a.  Since the first metal pattern MT 0   a  may correspond to the first sensing node SO 0 , the first metal pattern MT 0   a  may be referred to as a “first sensing node line”. In the second page buffer unit PBU 1 , the drain D 1  of the first pass transistor TR 1  and the source S 1 ′ of the second pass transistor TR 1 ′ may be connected to each other through a first metal pattern MT 0   b.  Since the first metal pattern MT 0   b  may correspond to a second sensing node SO 1 , the first metal pattern MT 0   b  may be referred to as a “second sensing node line”. In the third page buffer unit PBU 2 , the drain D 2  of the first pass transistor TR 2  and the source S 2 ′ of the second pass transistor TR 2 ′ may be connected to each other through a first metal pattern MT 0   c.  Since the first metal pattern MT 0   c  may correspond to a third sensing node SO 2 , the first metal pattern MT 0   c  may be referred to as a “third sensing node line”. In the fourth page buffer unit PBU 3 , the drain D 3  of the first pass transistor TR 3  and the source S 3 ′ of the second pass transistor TR 3 ′ may be connected to each other through a first metal pattern MT 0   d.  Since the first metal pattern MT 0   d  may correspond to a fourth sensing node SO 3 , the first metal pattern MT 0   d  may be referred to as a “fourth sensing node line”. Here, first to fourth sensing node lines may be arranged in a line in the first direction HD 1 . 
     The drain D 3 ′ of the second pass transistor TR 3 ′ of the fourth page buffer unit PBU 3  and the source S of the monitor transistor NM 7   a  of the first cache unit CU 0  may be connected to each other through a first metal pattern MT 0   e.  Here, the first metal pattern MT 0   e  may also be connected to a pre-charge circuit SOC_PRE. The first metal pattern MT 0   e  may correspond to the first combined sensing node SOC 1 , and thus the first metal pattern MT 0   e  may be referred to as a “first combined sensing node line”. Here, the first to fourth sensing node lines and the first combined sensing node line may be arranged in a line in the first direction HD 1 . According to an embodiment, first metal patterns MT 0   a,  MT 0   b,  MT 0   c,  MT 0   d,  and MT 0   e  may be implemented as a first lower metal layer LM 0  and each occupy one track (e.g., along a straight line) of the first lower metal layer LM 0 . Each metal pattern and metal layer may be formed, for example, by an electroplating process, or other metal deposition process. 
     The drain D 0 ′ of the second pass transistor TR 0 ′ of the first page buffer unit PBU 0  and the source S 1  of the first pass transistor TR 1  of the second page buffer unit PBU 1  may be connected to each other through a second conductive line or a second metal pattern MT 1   a,  and the second metal pattern MT 1   a  may be referred to as a “first node connecting line”. The drain D 1 ′ of the second pass transistor TR 1 ′ of the second page buffer unit PBU 1  and the source S 2  of the first pass transistor TR 2  of the third page buffer unit PBU 2  may be connected to each other through a second metal pattern MT 1   b,  and the second metal pattern MT 1   b  may be referred to as a “second node connecting line”. The drain D 2 ′ of the second pass transistor TR 2 ′ of the third page buffer unit PBU 2  and the source S 3  of the first pass transistor TR 3  of the fourth page buffer unit PBU 3  may be connected to each other through a second metal pattern MT 1   c,  and the second metal pattern MT 2   c  may be referred to as a “third node connecting line”. For example, second metal patterns MT 1   a,  MT 1   b,  and MT 1   c  may be implemented as a third lower metal layer LM 2  and each occupy one track (e.g., along a straight line) of the third lower metal layer LM 2 . However, the inventive concept is not limited thereto, and the second metal pattern MT 1   a  may be implemented as a second lower metal layer. Also, according to some embodiments, the second metal patterns MT 1   a,  MT 1   b,  and MT 1   c  may be implemented as the first lower metal layer LM 0  and may occupy one track of the first lower metal layer LM 0 . As discussed herein, a “track” refers to an area formed along a straight line. 
     According to the present embodiment, when the pass control signal SO_PASS is activated, first pass transistors TR 0  to TR 3  and second pass transistors TR 0 ′ to TR 3 ′ are turned on, and thus first and second pass transistors TR 0  to TR 3 ′ included in the first to fourth page buffer units PBU 0  to PBU 3  may be connected to each other in series, and first to fourth sensing nodes SO 0  to SO 3  may be connected to the first combined sensing node SOC 1 . In detail, first and second sensing nodes SO 0  and SO 1  may be connected to each other through first metal patterns MT 0   a  and MT 0   b  and the second metal pattern MT 1   a,  second and third sensing nodes SO 1  and SO 2  may be connected to each other through first metal patterns MT 0   b  and MT 0   c  and a second metal pattern MT 1   b,  third and fourth sensing nodes SO 2  and SO 3  may be connected to each other through first metal patterns MT 0   c  and MT 0   d  and a second metal pattern MT 1   c,  and the fourth sensing node SO 3  and the first combined sensing node SOC 1  may be connected to each other through first metal patterns MT 0   d  and MT 0   e.    
     First metal patterns MT 0   a,  MT 0   b,  MT 0   c,  and MT 0   d  corresponding to the first to fourth sensing node lines, the second metal patterns MT 1   a,  MT 1   b,  and MT 1   c  corresponding to node connecting lines, and the first metal pattern MT 0   e  corresponding to the combined sensing node line may constitute “data transmission lines”. As described above, according to the present embodiment, it is not necessary to separately provide four data transmission lines for connecting the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3 , and sensing node lines included in the first to fourth page buffer units PBU 0  to PBU 3  may be used as data transmission lines. Therefore, since the number of metal lines needed for wiring of the page buffer circuit PGBUF may be reduced, the complexity of a layout may be reduced and the size of the page buffer circuit PGBUF may be reduced. 
     The first to fourth page buffer units PBU 0  to PBU 3  may further include pre-charge transistors PM 0  to PM 3 , respectively. In the first page buffer unit PBU 0 , a pre-charge transistor PM 0  is connected between the first sensing node SO 0  and a voltage terminal to which a pre-charge voltage is applied and may include a gate to which a load signal LOAD 0  is applied. The pre-charge transistor PM 0  may pre-charge the first sensing node SO 0  to the pre-charge level corresponding to the pre-charge voltage in response to the load signal LOAD 0 . 
     The page buffer circuit PGBUF may include contact areas THVa and THVb. The contact area THVa may be disposed between the first page buffer unit PBU 0  and the second page buffer unit PBU 1 , and a contact area THVb may be disposed between the third page buffer unit PBU 2  and the fourth page buffer unit PBU 3 . First and second bit line contacts CT 0  and CT 1  respectively connected to first and second bit lines may be arranged in the contact area THVa. A first bit line contact CT 0  may be connected to the first page buffer unit PBU 0 , and a second bit line contact CT 1  may be connected to the second page buffer unit PBU 1 . For example, the first bit line contact CT 0  may be connected to a high-voltage transistor (e.g., TR_hv of  FIG.  6   ) included in a high-voltage unit (e.g., HVU 0  of  FIG.  10   ), and the second bit line contact CT 1  may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU 1  of  FIG.  10   ). Third and fourth bit line contacts CT 2  and CT 3  respectively connected to third and fourth bit lines may be arranged in the contact area THVb. A third bit line contact CT 2  may be connected to the third page buffer unit PBU 2 , and a fourth bit line contact CT 3  may be connected to the fourth page buffer unit PBU 3 . For example, the third bit line contact CT 2  may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU 2  of  FIG.  10   ), and the fourth bit line contact CT 3  may be connected to a high-voltage transistor included in a high-voltage unit (e.g., HVU 3  of  FIG.  10   ). The bit line contacts and other conductive contacts described herein may be formed, for example, of conductive material such as metal, extending vertically between a device (e.g., transistor) to which it is connected, and a conductive pattern at a different vertical level from the device. As can be seen in  FIG.  11   , the second metal patterns MT 1   a,  MT 1   b,  MT 1   c,  and MT 1   d  may be at a particular level and may connect to devices at a different level through conductive contacts. 
     The page buffer circuit PGBUF may further include a pre-charge circuit SOC_PRE between the fourth page buffer unit PBU 3  and the first cache unit CU 0 . The pre-charge circuit SOC_PRE may include a pre-charge transistor PMa for pre-charging the first combined sensing node SOC 1  and a shielding transistor NMa. The pre-charge transistor PMa is driven by a combined sensing node load signal SOC_LOAD, and, when the pre-charge transistor PMa is turned on, the first combined sensing node SOC 1  may be pre-charged to a pre-charge level. The shielding transistor NMa is driven by a combined sensing node shielding signal SOC_SHLD, and, when the shielding transistor NMa is turned on, the first combined sensing node SOC 1  may be discharged to a ground level. 
     As a transistor width WD decreases according to the process miniaturization, the area occupied by the page buffer circuit PGBUF may decrease. For example, the transistor width WD may correspond to the size of the gate G 0  of the first pass transistor TR 0  in the second direction HD 2 . In detail, as the transistor width WD decreases, the size of the first page buffer unit PBU 0  in the second direction HD 2  may decrease. However, despite the decrease in the transistor width WD, the pitch of the first lower metal layer LM 0  may not decrease. Therefore, the number of wires (i.e., the number of metal patterns) of the first lower metal layer LM 0  disposed on the first page buffer unit PBU 0  having a reduced size in the second direction HD 2  is also reduced. For example, the number of metal patterns of the first lower metal layer LM 0  corresponding to the first page buffer unit PBU 0  may be reduced from 6 to 4. 
     As described above, when the number of metal patterns of the first lower metal layer LM 0  corresponding to the first page buffer unit PBU 0  is reduced, the sensing reliability of the first page buffer unit PBU 0  may be deteriorated. For example, during a sensing operation, to prevent coupling between the first sensing node S 00  and an adjacent node, a metal pattern adjacent to the first sensing node SO 0  may be used as a shielding line to which a fixed bias is applied. However, when a metal pattern corresponding to a shielding line is removed due to the reduction of metal patterns, the voltage variation at the first sensing node SO 0  may increase due to the coupling between the first sensing node SO 0  and an adjacent node, and thus the sensing reliability of the first page buffer unit PBU 0  may be deteriorated. 
     However, according to the present embodiment, by arranging the first page buffer unit PBU 0  and the first cache unit CU 0  separately, the degree of freedom regarding first and third lower metal layers LM 0  and LM 2  arranged above the first page buffer unit PBU 0  increases, and at least one of metal patterns included in the first and third lower metal layers LM 0  and LM 2  may be used as a shielding line for the first sensing node SO 0 . Therefore, it is possible to prevent an increase in the voltage variation at the first sensing node SO 0 , thereby preventing deterioration of the sensing reliability of the first page buffer unit PBU 0 . 
     Meanwhile, in a structure in which the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3  are separated, when eight signal lines are arranged to respectively connect the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3 , the size of the page buffer circuit PGBUF in the second direction HD 2  may increase again. However, according to the present embodiment, the first to fourth sensing nodes SO 0  to SO 3  may be connected to one another by using the first pass transistors TR 0  to TR 3  and the second pass transistors TR 0 ′ to TR 3 ′ included in the first to fourth page buffer units PBU 0  to PBU 3 , and the first to fourth sensing nodes SO 0  to SO 3  may be connected to the first to fourth cache units CU 0  to CU 3  through the first combined sensing node SOC 1 . Here, since sensing node lines for connecting first and second pass transistors included in page buffer units to each other are implemented by using metal patterns (e.g., MT 0   a,  MT 0   b,  MT 0   c,  and MT 0   d ) of one track of the first lower metal layer LM 0 , the increase in the size of the page buffer circuit PGBUF in the second direction HD 2  may be prevented. 
     A PBDEC PBDECa may include a first inverter IVT 0 , a second inverter IVT 1 , and transistors N 0 , N 0 ′, N 0 ″, and N 1 . The first inverter IVT 0  may receive a first page buffer signal PBS 0  from the first to fourth page buffer units PBU 0  to PBU 3 , and an output of the first inverter IVT 0  may be provided to a gate of a transistor N 0 . The second inverter IVT 1  may receive a second page buffer signal PB Si from the fifth to eighth page buffer units PBU 4  to PBU 7 , and an output of the second inverter IVT 1  may be provided to a gate of a transistor N 1 . Sources of transistors N 0  and N 1  may be connected to a ground terminal, and drains of the transistors N 0  and N 1  may be commonly connected to a transistor N 0 ′. The transistors N 0 ′ and N 0 ″ are connected in series, a reference current signal REF_CUR is applied to a gate of the transistor N 0 ″, and a control signal nCR is applied to a gate of the transistor N 0 ′. 
     For example, when a program operation with respect to a memory cell connected to the first page buffer unit PBU 0  has failed, a logic low level may be stored in a sensing latch of the first page buffer unit PBU 0 , and, in this case, the voltage level of the first page buffer signal PBS 0  may be logic low corresponding to the voltage level of the first sensing node SO 0 , and the voltage level of the first combined sensing node SOC 1  may also be logic low. In this case, the first inverter IVT 0  may output a logic high signal, and thus the transistor N 0  may be turned on and the PBDEC PBDECa may operate as a current sink. The transistor N 0 ″ may output a first signal, that is, a reference current, to a wired OR terminal WOR_OUT based on the reference current signal REF_CUR. Here, the reference current may correspond to a current flowing through the transistor N 0 ″ when the transistor N 0 ″ is turned on according to the reference current signal REF_CUR. 
     For example, the PBDEC  213  may include an input/output driver, a WOR latch, and an MBC current branch. The input/output driver may control input/output signals for cache latches respectively included in the first to eighth cache units CU 0  to CU 7 . The WOR latch may store column repair information. For example, the column repair information may be column repair information corresponding to the first page buffer circuit PGBUFa. The MBC current branch may provide a value corresponding to the number of pieces of latch data (logic high or logic low) of each page buffer unit to an MBC (e.g.,  214  of  FIG.  1   ), and thus the MBC  214  may perform digital-to-analog conversion. 
       FIG.  13    is a circuit diagram showing the page buffer circuit PGBUF according to an embodiment. Referring to  FIG.  13   , the page buffer circuit PGBUF may correspond to one of the first to fourth page buffer circuits PGBUFa to PGBUFd of  FIG.  9   . The page buffer circuit PGBUF may include the first to eighth page buffer units PBU 0  to PBU 7  and the first to eighth cache units CU 0  to CU 7 . The fifth to eighth cache units CU 4  to CU 7  may be disposed in the third area AR 3  of  FIG.  10   , and the fifth to eighth page buffer units PBU 4  to PBU 7  may be disposed in the fourth area AR 4  of  FIG.  10   . The descriptions of the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3  given above with reference to  FIGS.  11  and  12    may also be applied to the fifth to eighth page buffer units PBU 4  to PBU 7  and the fifth to eighth cache units CU 4  to CU 7 , and thus redundant descriptions will be omitted. 
     The fifth page buffer unit PBU 4  may include a fifth sensing node SO 4  and first and second pass transistors TR 4  and TR 4 ′ connected in series, the sixth page buffer unit PBU 5  may include a sixth sensing node SO 5  and first and second pass transistors TR 5  and TR 5 ′ connected in series, a seventh page buffer unit PBU 6  may include a seventh sensing node SO 6  and first and second pass transistors TR 6  and TR 6 ′ connected in series, an eighth page buffer unit PBU 7  may include an eighth sensing node SO 7  and first and second pass transistors TR 7  and TR 7 ′ connected in series, and a pass control signal SO_PASS[ 7 : 4 ] may be applied to gates of first pass transistors TR 4  to TR 7  and second pass transistors TR 4 ′ to TR 7 ′. 
     A fifth cache unit CU 4  may include a monitor transistor NM 7   e,  a sixth cache unit CU 5  may include a monitor transistor NM 7   f,  a seventh cache unit CU 6  may include a monitor transistor NM 7   g,  and an eighth cache unit CU 7  may include a monitor transistor NM 7   h.  Sources of monitor transistors NM 7   e  to NM 7   h  may be connected to the second combined sensing node SOC 1 ′, and a cache monitoring signal MON_C[ 7 : 4 ] may be applied to gates of the monitor transistors NM 7   e  to NM 7   h.    
       FIG.  14    is a circuit diagram showing the cache unit CU according to an embodiment. 
     Referring to  FIGS.  6  and  14    together, the cache unit CU may include a monitor transistor NM 7  and the cache latch CL, and the cache latch CL may include a dump transistor  132 , transistors  131  and  133  to  135 , a first inverter  136 , and a second inverter  137 . The monitor transistor NM 7  is driven according to a cache monitoring signal MON_C and may control the connection between the combined sensing node SOC and the cache latch CL. The cache unit CU may correspond to one of the first to eighth cache units CU 0  to CU 7  of  FIG.  9   . 
     The first inverter  136  is connected between a first node ND 1  and a second node ND 2 , the second inverter  137  is connected between the second node ND 2  and the first node ND 1 , and the first inverter  136  and the second inverter  137  may constitute a latch. A transistor  131  includes a gate connected to the combined sensing node SOC. The dump transistor  132  may be driven by a dump signal DUMP _C and may transmit data stored in the cache latch CL to a main latch in the page buffer unit PBU, e.g., the sensing latch SL. A transistor  133  may be driven by a data signal DI, a transistor  134  may be driven by a data inversion signal nDI, and a transistor  135  may be driven by a write control signal DIO_W. When the write control signal DIO_W is activated, voltage levels of the first node ND 1  and the second node ND 2  may be determined according to the data signal DI and the data inversion signal nDI, respectively. 
     The cache unit CU may be connected to an input/output terminal RDi through transistors  138  and  139 . A transistor  138  includes a gate connected to the second node ND 2  and may be turned on or turned off according to a voltage level of the second node ND 2 . A transistor  139  may be driven by a read control signal DIO_R. When the control signal DIO_R is activated and the transistor  139  is turned on, the voltage level of the input/output terminal RDi may be determined as ‘1’ or ‘0’ according to the state of the cache latch CL. 
       FIG.  15    is a timing diagram showing an example of a data transmission operation according to an embodiment. Referring to  FIGS.  12 ,  13 , and  15    together, pass control signals SO_PASS 0  to SO_PASS 3  (i.e., SO_PASS[ 3 : 0 ]) may be applied to pass transistors TR 0  to TR 3  and TR 0 ′ to TR 3 ′ included in the first to fourth page buffer units PBU 0  to PBU 3 , respectively, and pass control signals SO_PASS 4  to SO_PASS 7  (i.e., SO_PASS[ 7 : 4 ]) may be applied to pass transistors TR 4  to TR 7  and TR 4 ′ to TR 7 ′ included in the fifth to eighth page buffer units PBU 4  to PBU 7 , respectively. 
     The core operation sequence may include a data transmission period  161  in which a data dumping operation is performed. When the page buffer circuit PGBUF has a multi-stage structure, the data transmission period  161  may be divided into the number of data transmission periods corresponding to half of the total number of stages. For example, when the page buffer circuit PGBUF has an 8-stage structure, the data transmission period  161  may be divided into four data transmission periods, e.g., first to fourth data transmission periods  1611  to  1614 . First data transmission operations between upper page buffer units and upper cache units and second data transmission operations between lower page buffer units and lower cache units may be simultaneously performed. Here, the first data transmission operations may be sequentially performed, and the second data transmission operations may also be sequentially performed. Specifically, in each of the first to fourth data transmission periods  1611  to  1614 , a data transmission operation between an upper page buffer unit and a upper cache unit corresponding thereto and a data transmission between a lower page buffer unit and a lower cache unit corresponding thereto may be performed simultaneously. 
     In a data transmission section  161 , the first pass transistors TR 0  to TR 3  and the second pass transistors TR 0 ′ to TR 3 ′ respectively included in the first to fourth page buffer units PBU 0  to PBU 3  may be selectively turned on to individually control connections between the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3 . Also, in the data transmission section  161 , the first pass transistors TR 4  to TR 7  and the second pass transistors TR 4 ′ to TR 7 ′ respectively included in the fifth to eighth page buffer units PBU 4  to PBU 7  may be selectively turned on to individually control connections between the fifth to eighth page buffer units PBU 4  to PBU 7  and the fifth to eighth cache units CU 4  to CU 7 . Therefore, an amount of a current consumed in for a data dumping operation may be reduced. 
     In detail, in the first data transmission period  1611 , all of first to eighth pass control signals SO_PASS 0  to SO_PASS 7  may be activated, and thus all of the first pass transistors TR 0  to TR 3  and the second pass transistors TR 0 ′ to TR 3 ′ respectively included in the first to fourth page buffer units PBU 0  to PBU 3  may be turned on and connected in series, and all of the first pass transistors TR 4  to TR 7  and the second pass transistors TR 4 ′ to TR 7 ′ respectively included in the fifth to eighth page buffer units PBU 4  to PBU 7  may be turned on and connected in series. Here, the first sensing node SO 0  may be connected to the first combined sensing node SOC 1  through second to fourth sensing nodes SO 1  to SO 3 , and the eighth sensing node SO 7  may be connected to the second combined sensing node SOC 1 ′ through fifth to seventh sensing nodes SO 4  to SO 6 . 
     At the start of the first data transmission period  1611 , load signals LOAD 0  to LOAD 7  may transition to logic low, which is an enable level, all of pre-charge transistors PM 0  to PM 7  respectively included in the first to eighth page buffer units PBU 0  to PBU 7  may be turned on, and first to eighth sensing nodes SO 0  to SO 7  may be pre-charged to a pre-charge level. Also, at the start of the first data transmission period  1611 , the combined sensing node load signal SOC_LOAD may transition to logic low, which is an enable level, the pre-charge transistor PMa included in a pre-charge circuit SOC_PRE 1  may be turned on, and the first combined sensing node SOC 1  may be pre-charged to a pre-charge level. Similarly, the second combined sensing node SOC 1 ′ may also be pre-charged to a pre-charge level. 
     Subsequently, the load signals LOAD 0  to LOAD 7  and the combined sensing node load signal SOC_LOAD transition to logic high, and ground control signals SOGND 0  and SOGND 7 , which are respectively applied to first and eighth page buffer units PBU 0  and PBU 7 , may transition to logic high, which is an enable level. Here, the first sensing node SO 0  and a sensing latch included in the first page buffer unit PBU 0  may be electrically connected, and the eighth sensing node SO 7  and a sensing latch included in the eighth page buffer unit PBU 7  may be electrically connected. 
     Subsequently, the ground control signals SOGND 0  and SOGND 7  respectively applied to the first page buffer unit PBU 0  and the eighth page buffer unit PBU 7  transition to logic low, and dump signals DUMP_C 0  and DUMP_C 7  respective applied to the first cache unit CU 0  and the eighth cache unit CU 7  may transition to logic high, which is an enable level. Here, data may be dumped between the sensing latch included in the first page buffer unit PBU 0  and the first cache unit CU 0 , and at the same time, data may be dumped between the sensing latch included in the eighth page buffer unit PBU 7  and the eighth cache unit CU 7 . The above descriptions of the first data transmission period  1611  may also be applied to second to fourth data transmission periods  1612  to  1614 . 
     In a second data transmission section  1612 , the first pass control signal SO_PASS 0  and an eighth pass control signal SO_PASS 7  may be deactivated and second to seventh pass control signals SO_PASS 1  to SO_PASS 6  may be activated, and thus all of first pass transistors TR 1  to TR 3  and second pass transistors TR 1  to TR 3 ′ included in second to fourth page buffer units PBU 1  to PBU 3  may be turned on and connected in series, and all of first pass transistors TR 4  to TR 6  and second pass transistors TR 4 ′ to TR 6 ′ included in fifth to seventh page buffer units PBU 4  to PBU 6  may be turned on and connected in series. Here, the second sensing node SO 1  may be connected to the first combined sensing node SOC 1  through the third sensing node SO 2  and the fourth sensing node SO 3 , and data dumping may be performed between the main latch in the second page buffer unit PBU 1  and a cache latch in a second cache unit CU 1 . Here, the seventh sensing node SO 6  may be connected to the second combined sensing node SOC 1 ′ through the fifth sensing node SO 4  and the sixth sensing node SO 5 , and data dumping may be performed between the main latch in the seventh page buffer unit PBU 6  and a cache latch in the seventh cache unit CU 6 . Here, since first and second pass transistors TR 0 , TR 0 ′, TR 7 , and TR 7 ′ included in the first page buffer unit PBU 0  and the eighth page buffer unit PBU 7  are turned off, current consumption may be reduced. 
     In a third data transmission section  1613 , first, second, seventh, and eighth pass control signals SO_PASS 0 , SO_PASS 1 , SO_PASS 6 , and SO_PASS 7  may be deactivated and third to sixth pass control signals SO_PASS 2  to SO_PASS 5  may be activated, and thus all of first and second pass transistors TR 2 , TR 3 , TR 2 ′, and TR 3 ′ included in the third page buffer unit PBU 2  and the fourth page buffer unit PBU 3  may be turned on and connected in series, and all of first and second pass transistors TR 4 , TR 5 , TR 4 ′, and TR 5 ′ included in the fifth page buffer unit PBU 4  and the sixth page buffer unit PBU 5  may be turned on and connected in series. Here, the third sensing node SO 2  may be connected to the first combined sensing node SOC 1  through the fourth sensing node SO 3 , and data dumping may be performed between the main latch in the third page buffer unit PBU 2  and a cache latch in a third cache unit CU 2 . Also, the sixth sensing node SO 5  may be connected to the second combined sensing node SOC 1 ′ through the fifth sensing node SO 4 , and data dumping may be performed between the main latch in the sixth page buffer unit PBU 5  and a cache latch in a sixth cache unit CU 5 . Here, since first and second pass transistors TR 0 , TR 0 ′, TR 1 , TR 1 ′, TR 6 , TR 6 ′, TR 7 , and TR 7 ′ included in first, second, seventh, and eighth page buffer units PBU 0 , PBU 1 , PBU 6 , and PBU 7  are turned off, current consumption may be reduced. 
     In a fourth data transmission section  1614 , first to third and sixth to eighth pass control signals SO_PASS 0  to SO_PASS 2  and SO_PASS 5  to SO_PASS 7  may be deactivated and fourth and fifth pass control signals SO_PASS 3 , SO_PASS 4  may be activated, and thus the first pass transistor TR 3  and the second pass transistor TR 3 ′ included in the fourth page buffer unit PBU 3  may be turned on and connected in series, and a first pass transistor TR 4  and a second pass transistor TR 4 ′ included in the fifth page buffer unit PBU 4  may be turned on and connected in series. In this case, the fourth sensing node SO 3  is connected to the first combined sensing node SOC 1 , and data dumping may be performed between the main latch in the fourth page buffer unit PBU 3  and the cache latch in a fourth cache unit CU 3 . Also, the fifth sensing node SO 4  is connected to the second combined sensing node SOC 1 ′, and data dumping may be performed between the main latch in the fifth page buffer unit PBU 4  and the cache latch in the fifth cache unit CU 4 . Here, since first and second pass transistors TR 0  to TR 2 , TR 5  to TR 7 , TR 0 ′ to TR 2 ′, and TR 5 ′ to TR 7 ′ included in first to third and sixth to eighth page buffer units PBU 0  to PBU 2  and PBU 5  to PBU 7  are turned off, current consumption may be reduced. 
     Meanwhile, in a data sensing period in which a data sensing operation is performed in the core operation sequence, all of the first to eighth pass control signals SO_PASS 0  to SO_PASS 7  may be deactivated, and all the pass transistors TR 0  to TR 7  and TR 0 ′ to TR 7 ′ included in the first to eighth page buffer units PBU 0  to PBU 7  may be turned off. Therefore, the first to eighth page buffer units PBU 0  to PBU 7  may not be electrically connected to one another, and the first to eighth sensing nodes SO 0  to SO 7  may be insulated from one another. Here, the first to fourth sensing nodes SO 0  to SO 3  may not be electrically connected to the first combined sensing node SOC 1 , and the first to fourth page buffer units PBU 0  to PBU 3  may not be connected to the first to fourth cache units CU 0  to CU 3 . Here, fifth to eighth sensing nodes SO 4  to SO 7  may not be electrically connected to the second combined sensing node SOC 1 ′, and the fifth to eighth page buffer units PBU 4  to PBU 7  may not be electrically connected to the fifth to eighth cache units CU 4  to CU 7 . 
       FIG.  16    is a timing diagram showing an example of a pass/fail determination operation according to an embodiment. 
     Referring to  FIGS.  13  and  16    together, the core operation sequence may include a pass/fail determination period  171  in which a pass/fail determination operation is performed on data. For example, the pass/fail determination period  171  may be performed after the data transmission period  161  of  FIG.  15   . When the page buffer circuit PGBUF has a multi-stage structure, the pass/fail determination period  171  may be divided into pass/fail determination periods corresponding to respective stages. For example, when the page buffer circuit PGBUF has an 8-stage structure, the pass/fail determination period  171  may be divided into eight pass/fail determination periods, e.g., first to eighth pass/fail determination periods  1711  to  1718 . 
     According to an embodiment, first pass/fail determination operations respectively corresponding to upper page buffer units may be sequentially performed, and then second pass/fail determination operations respectively corresponding to lower page buffer units may be sequentially performed. For example, first to fourth pass/fail determination periods  1711  to  1714  may correspond to a first period, and in the first period, first pass/fail determination operations for upper page buffer units may be sequentially performed. For example, fifth to eighth pass/fail determination periods  1715  to  1718  may correspond to a second period, and in the second period, second pass/fail determination operations for lower page buffer units may be sequentially performed. 
     In detail, in a first pass/fail determination section  1711 , first to fourth pass control signals SO_PASS 0  to SO_PASS 3  may be activated, and fifth to eighth pass control signals SO_PASS 4  to SO_PASS 7  may be deactivated, and thus the first pass transistors TR 0  to TR 3  and the second pass transistors TR 0 ′ to TR 3 ′ included in the first to fourth page buffer units PBU 0  to PBU 3  may be turned on and connected in series, and the first pass transistors TR 4  to TR 7  and the second pass transistors TR 4 ′ to TR 7 ′ included in the fifth to eighth page buffer units PBU 4  to PBU 7  may be turned off. Here, the first sensing node SO 0  is connected to the first combined sensing node SOC 1  through the second to fourth sensing nodes SO 1  to SO 3 , and a pass/fail determination operation regarding data stored in the sensing latch in the first page buffer unit PBU 0  may be performed. 
     At the start of the first pass/fail determination period  1711 , load signals LOAD 0  to LOAD 3  may transition to logic low, which is an enable level, all of pre-charge transistors PM 0  to PM 3  respectively included in the first to fourth page buffer units PBU 0  to PBU 3  may be turned on, and the first to fourth sensing nodes SO 0  to SO 3  may be pre-charged to a pre-charge level. Also, at the start of the first pass/fail determination period  1711 , the combined sensing node load signal SOC_LOAD may transition to logic low, which is an enable level, the pre-charge transistor PMa included in the pre-charge circuit SOC_PRE 1  may be turned on, and the first combined sensing node SOC 1  may be pre-charged to a pre-charge level. Subsequently, the load signals LOAD 0  to LOAD 3  and the combined sensing node load signal SOC_LOAD transition to logic high, and a ground control signal SOGND 0 , which is applied to the first page buffer unit PBU 0 , may transition to logic high, which is an enable level. At this time, the first sensing node SO 0  and the sensing latch included in the first page buffer unit PBU 0  may be electrically connected. The above descriptions of the first pass/fail determination period  1711  may also be applied to second to eighth pass/fail determination periods  1712  to  1718 . 
     In a second pass/fail determination section  1712 , second to fourth pass control signals SO_PASS 1  to SO_PASS 3  may be activated, and first and fifth to eighth pass control signals SO_PASS 0  and SO_PASS 4  to SO_PASS 7  may be deactivated, and thus first pass transistors TR 1  to TR 3  and the second pass transistors TR 1 ′ to TR 3 ′ included in the second to fourth page buffer units PBU 1  to PBU 3  may be turned on and connected in series, and the first pass transistors TR 0  and TR 4  to TR 7  and the second pass transistors TR 0 ′ and TR 4 ′ to TR 7 ′ included in the first and fifth to eighth page buffer units PBU 0  and PBU 4  to PBU 7  may be turned off. Here, the second sensing node SO 1  is connected to the first combined sensing node SOC 1  through the third and fourth sensing nodes SO 2  and SO 3 , and a pass/fail determination operation regarding data stored in the sensing latch in the second page buffer unit PBU 1  may be performed. 
     In a third pass/fail determination section  1713 , third and fourth pass control signals SO_PASS 2  and SO_PASS 3  may be activated, and first, second, and fifth to eighth pass control signals SO_PASS 0 , SO_PASS 1 , and SO_PASS 4  to SO_PASS 7  may be deactivated, and thus first pass transistors TR 2  and TR 3  and the second pass transistors TR 2 ′ and TR 3 ′ included in the third and fourth page buffer units PBU 2  to PBU 3  may be turned on and connected in series, and the first pass transistors TR 0 , TR 1 , and TR 4  to TR 7  and the second pass transistors TR 0 ′, TR 1 ′, and TR 4 ′ to TR 7 ′ included in the first, second, and fifth to eighth page buffer units PBU 0 , PBU 1 , and PBU 4  to PBU 7  may be turned off. Here, the third sensing node SO 2  is connected to the first combined sensing node SOC 1  through the fourth sensing node SO 3 , and a pass/fail determination operation regarding data stored in the sensing latch in the third page buffer unit PBU 2  may be performed. 
     In a fourth pass/fail determination section  1714 , a fourth pass control signal SO_PASS 3  may be activated, and first to third and fifth to eighth pass control signals SO_PASS 0  to SO_PASS 2  and SO_PASS 4  to SO_PASS 7  may be deactivated, and thus the first pass transistor TR 3  and the second pass transistor TR 3 ′ included in the fourth page buffer unit PBU 3  may be turned on and connected in series, and first pass transistors TR 0  to TR 2  and TR 4  to TR 7  and second pass transistors TR 0 ′ to TR 2 ′ and TR 4 ′ to TR 7 ′ included in the first to third and fifth to eighth page buffer units PBU 0  to PBU 2  and PBU 4  to PBU 7  may be turned off. Here, the fourth sensing node SO 3  is connected to the first combined sensing node SOC 1 , and a pass/fail determination operation regarding data stored in the sensing latch in the fourth page buffer unit PBU 3  may be performed. 
     In a fifth pass/fail determination period  1715 , the first to fourth pass control signals SO_PASS 0  to SO_PASS 3  may be deactivated and the fifth to eighth pass control signals SO_PASS 4  to SO_PASS 7  may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the eighth page buffer unit PBU 7  may be performed. In a sixth pass/fail determination period  1716 , first to fourth and eighth pass control signals SO_PASS 0  to SO_PASS 4  and SO_PASS 7  may be deactivated and fifth to seventh pass control signals SO_PASS 4  to SO_PASS 6  may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the seventh page buffer unit PBU 6  may be performed. 
     In a seventh pass/fail determination period  1717 , first to fourth, seventh, and eighth pass control signals SO_PASS 0  to SO_PASS 3 , SO_PASS 6 , and SO_PASS 7  may be deactivated and fifth and sixth pass control signals SO_PASS 4  and SO_PASS 5  may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the sixth page buffer unit PBU 5  may be performed. In an eighth pass/fail determination period  1718 , first to fourth and sixth to eighth pass control signals SO_PASS 0  to SO_PASS 3  and SO_PASS 5  to SO_PASS 7  may be deactivated and a fifth pass control signal SO_PASS 4  may be activated, and thus a pass/fail determination operation regarding data stored in the sensing latch in the fifth page buffer unit PBU 4  may be performed. 
       FIG.  17    is a diagram showing a page buffer circuit  210   a  and a PBDEC  213   a  according to an embodiment. The present embodiment corresponds to an modified example of  FIG.  10   , and the descriptions given above with reference to  FIG.  10    may also be applied to the present embodiment. 
     Referring to  FIG.  17   , the PBDEC  213   a  may include first to fourth PBDECs PBDECa′ to PBDECd′, and the first to fourth PBDECs PBDECa′ to PBDECd′ may be arranged to correspond to first page buffer units PBU 0  of first to fourth page buffer circuits PGBUFa′ to PGBUFd′, respectively. An input/output driver  213   b  may be disposed at the center of the page buffer circuit  210   a,  and more particularly, between the fourth cache unit CU 3  and the fifth cache unit CU 4  of each of the first to fourth page buffer circuits PGBUFa′ to PGBUFd′. The input/output driver  213   b  may control input/output signals for cache latches included in the first to eighth cache units CU 0  to CU 7 . 
     For example, the input/output driver  213   b  may include transistors NM_DIVa to NM_DIVd driven by a segmentation control signal or a division control signal DIV_SOC. When the division control signal DIV_SOC is at a logic high level, the transistors NM_DIVa to NM_DIVd may be turned on, and thus the fifth to eighth cache units CU 4  to CU 7  and the fifth to eighth page buffer units PBU 4  to PBU 7  may be connected to the PBDEC  213   a  together with the first to fourth page buffer units PBU 0  to PBU 3  and the first to fourth cache units CU 0  to CU 3 . Meanwhile, when the division control signal DIV_SOC is at a logic low level, the transistors NM_DIVa to NM_DIVd may be turned off, and thus the fifth to eighth cache units CU 4  to CU 7  and the fifth to eighth page buffer units PBU 4  to PBU 7  may not be connected to the PBDEC  213   a.    
     A first PBDEC PBDECa′ may be connected to the first combined sensing node SOC 1  and/or the second combined sensing node SOC 1 ′ through an upper combined sensing node SOC_T 1 . A second PBDEC PBDECb′ may be connected to the first combined sensing node SOC 2  and/or the second combined sensing node SOC 2 ′ through an upper combined sensing node SOC_T 2 . A third PBDEC PBDECc′ may be connected to the first combined sensing node SOC 3  and/or the second combined sensing node SOC 3 ′ through an upper combined sensing node SOC_T 3 . A fourth PBDEC PBDECd′ may be connected to the first combined sensing node SOC 4  and/or the second combined sensing node SOC 4 ′ through an upper combined sensing node SOC_T 4 . 
       FIG.  18    is a diagram showing the page buffer circuit  210   a  and the PBDEC  213   a  according to an embodiment in more details. The present embodiment corresponds to a modified example of  FIGS.  11  and  17   , and redundant descriptions will be omitted. Referring to  FIG.  18   , transistors PM_WORa to PM_WORd driven by a load WOR control signal LOAD_WOR may be arranged between the PBDEC  213   a  and the page buffer circuit  210   a.  When the load WOR control signal LOAD_WOR is at a logic low level, the transistors PM_WORa to PM_WORd may be turned on, and the page buffer circuit  210   a  and the PBDEC  213   a  may be connected. On the other hand, when the load WOR control signal LOAD_WOR is at a logic high level, the transistors PM_WORa to PM_WORd may be turned off, and the page buffer circuit  210   a  and the PBDEC  213   a  may not be connected. 
       FIG.  19    is a circuit diagram showing a partial region of the page buffer circuit PGBUFa′ and the PBDEC PBDECa′ according to an embodiment. 
     Referring to  FIG.  19   , the PBDEC PBDECa′ may include an MBC current branch  191  and a WOR latch  192 . The WOR latch  192  may store column repair information. Here, the column repair information may be column repair information corresponding to the first page buffer circuit PGBUFa′. The MBC current branch  191  may provide a value corresponding to the number of pieces of latch data (logic high or logic low) of each page buffer unit to the MBC  214 , and thus the MBC  214  may perform digital-to-analog conversion. 
     The MBC current branch  191  may include transistors TR 1 , TR 2 , and TR 3  connected in series and an inverter IV 0 , and an input terminal of the inverter IV 0  may be connected to the upper combined sensing node SOC_T 1 . The WOR latch  192  may include inverters IV 1  and IV 2  and transistors TR 4 , TR 5  and TR 6 , wherein the inverters IV 1  and IV 2  may constitute a latch. A gate of a transistor TR 1  may be connected to the MBC  214  and may receive a control signal from the MBC  214 . A gate of the transistor TR 2  may be connected to an input terminal of the inverter IV 1  and an output terminal of the inverter IV 2 . Gates of transistors TR 4  and TR 5  may be connected to a Y driver  216  and each receive a control signal from the Y driver  216 . A gate of a transistor TR 6  may be connected to the upper combined sensing node SOC_T 1 . 
       FIG.  20    is a circuit diagram showing a partial region of the page buffer circuit  210   a  and the PBDEC  213   a  according to an embodiment. Referring to  FIG.  20   , the MBC current branch  191  may include current branches CB 0  to CB 3 , and the current branches CB 0  to CB 3  may be connected to the MBC  214 . The WOR latch  192  may include latches LAT 0  to LAT 3 , and the latches LAT 0  to LAT 3  may transmit latch information W_LAT 0  to W_LAT 3  to the current branches CB 0  to CB 3 , respectively. WOR latch information may be updated in one (e.g., CU 3 ) of the first to fourth cache units CU 0  to CU 3  through the input/output driver  213   b,  and WOR latch information may be transmitted to a WOR latch (e.g., LAT 0 ) through the first combined sensing node SOC 1 . 
       FIG.  21    is a timing diagram showing an example of a data transmission operation according to an embodiment. The present embodiment corresponds to a modified example of  FIG.  15   , and redundant descriptions will be omitted. Referring to  FIGS.  17  to  21   , the core operation sequence may include a data transmission period  211  in which a data dumping operation is performed. The data transmission period  211  may include first to fourth data transmission periods  2111  to  2114 . The first to fourth data transmission periods  2111  to  2114  may correspond to the first to fourth data transmission periods  1611  to  1614  of  FIG.  15   , respectively. In the first to fourth data transmission periods  2111  to  2114 , the division control signal DIV_SOC may maintain a logic low level, and thus all of the transistors NM_DIVa to NM_DIVd may be turned off. In the first to fourth data transmission periods  2111  to  2114 , a WOR control signal LOAD_WOR may maintain a logic high level, and thus all of transistors NM_WORa to NM_WORd may be turned off. 
       FIG.  22    is a timing diagram showing an example of a pass/fail determination operation according to an embodiment. The present embodiment corresponds to a modified example of  FIG.  16   , and redundant descriptions will be omitted. Referring to  FIGS.  17  to  20  and  22    together, the core operation sequence may include a pass/fail determination period  221  in which a pass/fail determination operation is performed on data. For example, the pass/fail determination period  2211  may be performed after the data transmission period  211  of  FIG.  21   . The pass/fail determination period  221  may include first to eighth pass/fail determination periods  2211  to  2218 . The first to eighth pass/fail determination periods  2211  to  2218  may correspond to the first to eighth pass/fail determination periods  1711  to  1718  of  FIG.  16   , respectively. 
     In the first to fourth pass/fail determination periods  2211  to  2214 , the division control signal DIV_SOC may maintain a logic low level, and thus all of the transistors NM_DIVa to NM_DIVd may be turned off. Meanwhile, in each of fifth to eighth pass/fail determination periods  2215  to  2218 , the division control signal DIV_SOC may be activated. For example, in a fifth pass/fail determination section  2215 , the division control signal DIV_SOC may transition to a logic high level when pass control signals SO_PASS&lt; 4 &gt; to SO_PASS&lt; 7 &gt; transition from a logic low level to a logic high level and may transition to the logic high level when a ground control signal SOGND&lt; 7 &gt; transitions from the logic high level to the logic low level. The transistors NM_DIVa to NM_DIVd are turned on while the division control signal DIV_SOC is maintaining the logic high level, and thus the fifth to eighth page buffer units PBU 4  to PBU 7  may be connected to the PBDEC  213   a,  and a pass/fail determination operation corresponding to the eighth page buffer unit PBU 7  may be performed. 
     At the start of a first pass/fail determination period  2211 , the WOR control signal LOAD_WOR may transition to a logic low level, which is an enable level, and the transistors PM_WORa to PM_WORd may be turned on. At this time, the first combined sensing node SOC 1  and the upper combined sensing node SOC_T 1  may be electrically connected. Subsequently, the WOR control signal LOAD_WOR may transition to a logic high level, which is a disable level, and the transistors PM_WORa to PM_WORd may be turned off. 
       FIG.  23    is a circuit diagram showing a page buffer PB′ according to an embodiment. Referring to  FIG.  23   , the page buffer PB′ may include a page buffer unit PBU′ and the cache unit CU, and the page buffer unit PBU′ may include a main unit MU′ and the high-voltage unit HVU. The page buffer PB′ may correspond to a modified example of the page buffer PB of  FIG.  6   . The page buffer unit PBU of  FIG.  6    includes first and second pass transistors TR and TR′, whereas the page buffer unit PBU′ according to the present embodiment may include one pass transistor TR″. The pass transistor TR″ may be driven according to the pass control signal SO_PASS and may be connected between the first terminal SOC_U and the second terminal SOC_D. 
     For example, a source of the pass transistor TR″ may be connected to the first terminal SOC_U, and a drain of the pass transistor TR″ may be connected to the sensing node SO and the second terminal SOC_D. However, the inventive concept is not limited thereto, and the source of the pass transistor TR″ may be connected to the first terminal SOC_U and the sensing node SO, and the drain of the pass transistor TR″ may be connected to the second terminal SOC_D. According to an embodiment, a pass transistor included in one of two page buffer units adjacent to each other in the first direction HD 1  may be connected between the first terminal SOC_U and the sensing node SO, and a pass transistor included in the other one page buffer unit may be connected between the sensing node SO and the second terminal SOC_D. 
       FIG.  24    is a diagram showing the PBDEC  213  and the MBC  214  according to an embodiment. Referring to  FIGS.  1 ,  9 , and  24    together, the PBDEC  213  may include N PBDECs. Here, N is a positive integer and may correspond to the number of page buffer columns included in a page buffer circuit. Each PBDEC may include inverters IVT 0  and IVT 1  and transistors N 0 , N 0 ′, N 0 ″, and N 1 , and the transistor N 0 ′ may be referred to as a column enable transistor. Descriptions given above with reference to  FIGS.  12  and  13    may be applied to the present embodiment. The MBC  214  may be connected to the wired OR terminal WOR_OUT connected to the N PBDECs. 
     The MBC  214  may generate count results CNT (i.e., OUT&lt; 0 &gt; to OUT&lt; 9 &gt;), which are digital values corresponding to the number of fail bits, from the analog level decoder output signal DS, that is, a current signal IWOR. In detail, the MBC  214  may include a plurality of transistors P 11 , P 12 , P 21 , P 22 , P 31 , P 32 , N 11 , N 12 , N 21 , N 22 , and N 23 , a resistor R, and a differential amplifier  2141  constituting a reference current generator. Also, the MBC  214  may further include a plurality of transistors P 1 , P 1   a,  P 2 , P 2   a,  P 9 , P 9   a,  N 1 , N 1   a,  N 2 , N 2   a,  N 2   b,  N 2   c,  N 9 , N 9   a,  N 9   b,  and N 9   c  constituting a counter and a plurality of comparators  2142  and  2143 . In a period in which the operation of the MBC  214  is enabled, the transistors P 11 , P 21 , P 31 , N 12 , N 23 , P 1   a,  P 2   a,  P 9   a,  N 1   a,  N 2   a,  N 2   c,  N 9   a,  and N 9   c  may be turned on. On the other hand, in a period in which the operation of the MBC  214  is disabled, the transistors P 11 , P 21 , P 31 , N 12 , N 23 , P 1   a,  P 2   a,  P 9   a,  N 1   a,  N 2   a,  N 2   c,  N 9   a,  and N 9   c  may be turned off. 
     A reference voltage Vref may be input to a first input terminal of the differential amplifier  2141 , and a voltage across the resistor R may be input to a second input terminal of the differential amplifier  2141 . Transistors P 11  and P 12  and the resistor R may constitute a feedback variable resistor, and a bias current Ibias may flow through the resistor R. Transistors P 21 , P 22 , N 12 , and N 21  may constitute a first reference current generator generating a first reference current Iref 1 , and transistors P 31 , P 32 , N 21 , N 22 , and N 23  may constitute a second reference current generator generating a second reference current Iref 2 . A node voltage between transistors P 32  and N 21  may be provided from the second reference current generator to the PBDEC  213  as the reference current signal REF_CUR. 
       FIG.  25    is a cross-sectional view of a memory device  500  having a bonding vertical NAND (B-VNAND) structure, according to an embodiment. When a non-volatile memory included in a memory device is implemented as a bonding vertical NAND (B-VNAND) type flash memory, the non-volatile memory may have the structure shown in  FIG.  25   . 
     Referring to  FIG.  25   , a cell region CELL of a memory device  500  may correspond to a first semiconductor layer L 1 , and a peripheral circuit region PERI may correspond to a second semiconductor layer L 2 . The peripheral circuit region PERI and the cell region CELL of the memory device  500  may each include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. For example, the word lines WL, the string select lines SSL, the ground select lines GSL, and the memory cell array  110  of  FIG.  2    may be formed on the first semiconductor layer L 1 , whereas the control logic circuit  120 , the page buffer circuit  130 , the voltage generator  140 , and the row decoder  150  may be formed on the second semiconductor layer L 2 . 
     The peripheral circuit region PERI may include a first substrate  610 , an interlayer insulating layer  615 , a plurality of circuit elements  620   a,    620   b,  and  620   c  formed on the first substrate  610 , first metal layers  630   a,    630   b,  and  630   c  respectively connected to the plurality of circuit elements  620   a,    620   b,  and  620   c,  and second metal layers  640   a,    640   b,  and  640   c  formed on the first metal layers  630   a,    630   b,  and  630   c.  In an embodiment, the first metal layers  630   a,    630   b,  and  630   c  may be formed of tungsten having relatively high resistivity, and the second metal layers  640   a,    640   b,  and  640   c  may be formed of copper having relatively low resistivity. 
     In an embodiment, although only the first metal layers  630   a,    630   b,  and  630   c  and the second metal layers  640   a,    640   b,  and  640   c  are shown and described, the embodiment is not limited thereto, and one or more additional metal layers may be further formed on the second metal layers  640   a,    640   b,  and  640   c.  At least a portion of the one or more additional metal layers formed on the second metal layers  640   a,    640   b,  and  640   c  may be formed of aluminum or the like having a lower resistivity than those of copper forming the second metal layers  640   a,    640   b,  and  640   c.    
     The interlayer insulating layer  615  may be disposed on the first substrate  610  and cover the plurality of circuit elements  620   a,    620   b,  and  620   c,  the first metal layers  630   a,    630   b,  and  630   c,  and the second metal layers  640   a,    640   b,  and  640   c.  The interlayer insulating layer  615  may include or be formed of an insulating material such as silicon oxide, silicon nitride, or the like. 
     Lower bonding metals  671   b  and  672   b  may be formed on the second metal layer  640   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  671   b  and  672   b  in the peripheral circuit region PERI may be electrically bonded to upper bonding metals  571   b  and  572   b  of the cell region CELL. The lower bonding metals  671   b  and  672   b  and the upper bonding metals  571   b  and  572   b  may be formed of aluminum, copper, tungsten, or the like. Further, the upper bonding metals  571   b  and  572   b  in the cell region CELL may be referred as first metal pads and the lower bonding metals  671   b  and  672   b  in the peripheral circuit region PERI may be referred as second metal pads. 
     The cell region CELL may include at least one memory block. The cell region CELL may include a second substrate  510  and a common source line  520 . On the second substrate  510 , a plurality of word lines  531  to  538  (i.e.,  530 ) may be stacked in a vertical direction VD, perpendicular to an upper surface of the second substrate  510 . At least one string select line and at least one ground select line may be arranged on and below the plurality of word lines  530 , respectively, and the plurality of word lines  530  may be disposed between the at least one string select line and the at least one ground select line. 
     In the bit line bonding area BLBA, a channel structure CH may extend in the vertical direction VD, perpendicular to the upper surface of the second substrate  510 , and pass through the plurality of word lines  530 , the at least one string select line, and the at least one ground select line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like, and the channel layer may be electrically connected to a first metal layer  550   c  and a second metal layer  560   c.  For example, the first metal layer  550   c  may be a bit line contact, and the second metal layer  560   c  may be a bit line. In an embodiment, the bit line  560   c  may extend in a second horizontal direction HD 2 , parallel to the upper surface of the second substrate  510 . 
     In an embodiment, an area in which the channel structure CH, the bit line  560   c,  and the like are disposed may be defined as the bit line bonding area BLBA. In the bit line bonding area BLBA, the bit line  560   c  may be electrically connected to the circuit elements  620   c  providing a page buffer  593  in the peripheral circuit region PERI. The bit line  560   c  may be connected to upper bonding metals  571   c  and  572   c  in the cell region CELL, and the upper bonding metals  571   c  and  572   c  may be connected to lower bonding metals  671   c  and  672   c  connected to the circuit elements  620   c  of the page buffer  593 . 
     In the word line bonding area WLBA, the plurality of word lines  530  may extend in a first horizontal direction HD 1 , parallel to the upper surface of the second substrate  510 , and may be connected to a plurality of cell contact plugs  541  to  547  (i.e.,  540 ). The plurality of word lines  530  and the plurality of cell contact plugs  540  may be connected to each other in pads provided by at least a portion of the plurality of word lines  530  extending in different lengths in the second horizontal direction HD 2 . A first metal layer  550   b  and a second metal layer  560   b  may be connected to an upper portion of the plurality of cell contact plugs  540  connected to the plurality of word lines  530 , sequentially. The plurality of cell contact plugs  540  may be connected to the peripheral circuit region PERI by the upper bonding metals  571   b  and  572   b  of the cell region CELL and the lower bonding metals  671   b  and  672   b  of the peripheral circuit region PERI in the word line bonding area WLBA. 
     The plurality of cell contact plugs  540  may be electrically connected to the circuit elements  620   b  providing a row decoder  594  in the peripheral circuit region PERI. In an embodiment, operating voltages of the circuit elements  620   b  of the row decoder  594  may be different from operating voltages of the circuit elements  620   c  providing the page buffer  593 . For example, operating voltages of the circuit elements  620   c  providing the page buffer  593  may be greater than operating voltages of the circuit elements  620   b  providing the row decoder  594 . 
     A common source line contact plug  580  may be disposed in the external pad bonding area PA. The common source line contact plug  580  may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like, and may be electrically connected to the common source line  520 . A first metal layer  550   a  and a second metal layer  560   a  may be stacked on an upper portion of the common source line contact plug  580 , sequentially. For example, an area in which the common source line contact plug  580 , the first metal layer  550   a,  and the second metal layer  560   a  are disposed may be defined as the external pad bonding area PA. 
     Input-output pads  605  and  505  may be disposed in the external pad bonding area PA. A lower insulating film  601  covering a lower surface of the first substrate  610  may be formed below the first substrate  610 , and a first input-output pad  605  may be formed on the lower insulating film  601 . The first input-output pad  605  may be connected to at least one of the plurality of circuit elements  620   a,    620   b,  and  620   c  disposed in the peripheral circuit region PERI through a first input-output contact plug  603 , and may be separated from the first substrate  610  by the lower insulating film  601 . In addition, a side insulating film may be disposed between the first input-output contact plug  603  and the first substrate  610  to electrically separate the first input-output contact plug  603  and the first substrate  610 . 
     An upper insulating film  501  covering the upper surface of the second substrate  510  may be formed on the second substrate  510 , and a second input-output pad  505  may be disposed on the upper insulating layer  501 . The second input-output pad  505  may be connected to at least one of the plurality of circuit elements  620   a,    620   b,  and  620   c  disposed in the peripheral circuit region PERI through a second input-output contact plug  503 . 
     According to embodiments, the second substrate  510  and the common source line  520  may not be disposed in an area in which the second input-output contact plug  503  is disposed. Also, the second input-output pad  505  may not overlap the word lines  530  in the vertical direction VD. The second input-output contact plug  503  may be separated from the second substrate  510  in a direction, parallel to the upper surface of the second substrate  510 , and may pass through an interlayer insulating layer of the cell region CELL to be connected to the second input-output pad  505 . 
     According to embodiments, the first input-output pad  605  and the second input-output pad  505  may be selectively formed. For example, the memory device  400  may include only the first input-output pad  605  disposed on the first substrate  610  or the second input-output pad  505  disposed on the second substrate  510 . Alternatively, the memory device  400  may include both the first input-output pad  605  and the second input-output pad  505 . 
     A metal pattern provided on an uppermost metal layer may be provided as a dummy pattern or the uppermost metal layer may be absent, in each of the external pad bonding area PA and the bit line bonding area BLBA, respectively included in the cell region CELL and the peripheral circuit region PERI. 
     In the external pad bonding area PA, the memory device  500  may include a lower metal pattern  673   a,  corresponding to an upper metal pattern  572   a  formed in an uppermost metal layer of the cell region CELL, and having the same cross-sectional shape as the upper metal pattern  572   a  of the cell region CELL so as to be connected to each other, in an uppermost metal layer of the peripheral circuit region PERI. In the peripheral circuit region PERI, the lower metal pattern  673   a  formed in the uppermost metal layer of the peripheral circuit region PERI may not be connected to a contact. Similarly, in the external pad bonding area PA, an upper metal pattern, corresponding to the lower metal pattern formed in an uppermost metal layer of the peripheral circuit region PERI, and having the same shape as a lower metal pattern of the peripheral circuit region PERI, may be formed in an uppermost metal layer of the cell region CELL. 
     The lower bonding metals  671   b  and  672   b  may be formed on the second metal layer  640   b  in the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals  671   b  and  672   b  of the peripheral circuit region PERI may be electrically connected to the upper bonding metals  571   b  and  572   b  of the cell region CELL by a Cu-to-Cu bonding. 
     Further, in the bit line bonding area BLBA, an upper metal pattern  592 , corresponding to a lower metal pattern  652  formed in the uppermost metal layer of the peripheral circuit region PERI, and having the same cross-sectional shape as the lower metal pattern  652 , may be formed in an uppermost metal layer of the cell region CELL. A contact may not be formed on the upper metal pattern  592  formed in the uppermost metal layer of the cell region CELL. 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.