Patent Publication Number: US-11664741-B2

Title: System and method for AC power control

Description:
RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 62/878,640, filed Jul. 25, 2019, and incorporated herein by reference in its entirety for all purposes. 
    
    
     FIELD OF THE DISCLOSURE 
     The field of the present disclosure includes systems for providing AC power control, such as control of power from a utility-generated sine wave to a load that may be resistive, inductive, capacitive or a mixed load. The field includes a power control device that may operate as a dimmer switch. 
     BACKGROUND OF THE DISCLOSURE 
     Prior devices for power control used conduction-angle modulation of utility-generated sine wave voltage for power control. Such modulation has been, and continues to be, one of the most widely employed methods of variable power control used worldwide due to its simplicity and high efficiency, which is typically on the order of 99%. Applications include heating, lighting, motor control, etc. 
     Conduction-angle modulation for power control generally uses a Pulse Width Modulated (PWM) control signal that drives a power-control switching device to enable energy transfer from a utility-generated sine wave V AC  to a load only during specific portions of the period of the sine wave waveform. Variable power control is provided by varying the on/off time of the PWM control signal. Thyristors (e.g., Silicon Controlled Rectifiers (SCRs) and Triodes for Alternating Current (TRIACs)) have historically been used as the power-control switching devices. 
     Thyristors are simple devices and offer very little control. Once a thyristor has been triggered to turn on, the thyristor remains on until the current through the thyristor falls to zero. which generally occurs at the next zero crossing of the input sine wave. As such, the conduction angle utilized must always be lagging, that is, at the “back” portion of each sine wave half cycle so that the next zero crossing turns the thyristor off. 
     There is an abrupt transition of power transferred to a load that occurs for lagging conduction-angle control when a thyristor turns on. The abrupt transition of voltage and current creates detrimental EMI effects that often cause interference with other electronic equipment. The traditional technique for reducing the effects of EMI has been to add an inductor in the current path to slow the rate of current rise to the load. 
       FIG.  1    depicts a conventional thyristor-based power-control device  100  that includes a choke circuit for reducing EMI. A utility-generated sine wave voltage V AC  is applied between a V LINE  terminal and a Neutral (NEU) terminal and is switched on/off to a load R L  through a TRIAC Q 101 . A PWM control signal W PWM  is applied through a driver D 101  to control when TRIAC Q 101  is triggered. A choke circuit CH 101  is coupled to the output of TRIAC Q 101  and comprises a choke inductor L 101  and a resistance R 101 . A choke circuit is often added to a power-control device  100  to controllably slow the voltage and current rise to the load R L , to mitigate EMI-related problems. A snubber circuit SN 101  is coupled across TRIAC Q 101  and comprises a resistor R 102  and a capacitor C 102 . A snubber circuit is often coupled across a thyristor to manage problematic behavior with reactive loads. 
       FIG.  2    depicts conceptualized conduction-angle modulation waveforms for V LINE , V LOAD , and W PWM  for the conventional power-control device  100  of  FIG.  1   . In particular, the conduction-angle modulation waveform for W PWM  depicts a conduction angle control signal of nominally 50%. TRIAC Q 101  is triggered at the peak of the V LINE  sinewave by W PWM . TRIAC Q 101  remains on for the duration of a half cycle, and the voltage V LOAD  is transferred to load R L . The shaded areas of the V LINE  waveform shown in  FIG.  2    represent the portion of the V AC  voltage in which the half-cycle modulation of W PWM  is applied. The “lagging-angle” PWM modulation depicted in  FIG.  2    causes thyristor Q 101  to turn on “hard” during the middle of the V LINE  waveform and causes a severe shock and abrupt voltage transition for load R L . Inductor L 101  of choke circuit CH 101  reduces the inherently fast rise time of the V LOAD  output from TRIAC Q 101  to decrease any generated EMI, as depicted by the dashed line in the V LINE  and V LOAD  waveforms. Often this causes the inductor of a choke circuit or lighting filaments of a load to audibly sing or buzz. 
       FIGS.  3 A- 3 C  respectively depict simulated TRIAC signal waveforms for the conventional power-control device  100  for a resistive load. The abscissa for each of  FIG.  3 A- 3 C  is time in milliseconds (ms), and the ordinate for each of  FIGS.  3 A- 3 C  is voltage in Volts (V). The simulation conditions for  FIGS.  3 A- 3 C  are V AC =120 V RMS , R L =14.4Ω, I L =8.33 A RMS  for 100% duty cycle. Thus, PL=1000 Watts. At 50% duty cycle the load power becomes PL=VAC×IL×50%=500 W. It should be noted that although the time begins at t=0 ms in each of  FIGS.  3 A- 3 C , it should be understood that the specific times indicated are relative and have been selected for convenience, and that the waveforms depicted are in a steady-state condition. Also, although the frequency of V LINE  is 50 Hz, other frequencies for V LINE  are possible. 
       FIG.  3 A  depicts the waveform for the voltage V TRIAC  across TRIAC Q 101 , which is indicated as a solid line.  FIG.  3 A  also depicts the waveform for the voltage V LOAD  across the load, which is indicated as a dotted line.  FIG.  3 B  depicts the waveform for the voltage V INDUCTOR  across choke inductor L 101 , which is indicated as a solid line superimposed on the voltage across the load V LOAD , which is indicated as a dotted line.  FIG.  3 C  depicts the waveform for the PWM control signal W PWM . 
     At time t=5 ms in  FIGS.  3 A- 3 C , the W PWM  signal ( FIG.  3 C ) turns on at the peak of the positive half cycle of V LINE , and TRIAC Q 101  begins to conduct. In  FIG.  3 A , TRIAC Q 101  turns on at t=5 ms and the voltage V TRIAC  (solid line) across TRIAC Q 101  drops to 0 V (neglecting the internal resistance of TRIAC Q 101 ). The voltage V LOAD  (dotted line) across the load R L  increases to V LINE . In  FIG.  3 B , the voltage V INDUCTOR  (solid line) across choke inductor L 101  rises to V LINE  and decays based on the time constant of L 101  and R 101 , and the voltage V LOAD  (dotted line) across the load R L  increases to V LINE . At time t=10 ms, V LINE  begins a negative half cycle, the W PWM  signal ( FIG.  3 C ) turns off, and TRIAC Q 101  turns off. 
     At time t=15 ms, the W PWM  signal turns on for the negative half cycle of V LINE , and TRIAC Q 101  begins to conduct. In  FIG.  3 A , the voltage V TRIAC  (solid line) across TRIAC Q 101  drops to 0 V, and the voltage V LOAD  (dotted line) across the load R L  decreases to V LINE . In  FIG.  3 B , the voltage V INDUCTOR  (solid line) across choke inductor L 101  drops to V LINE  and decays based on the time constant of L 101  and R 101 . The voltage V LOAD  (dotted line) across the load R L  drops to V LINE . At time t=20 ms, V LINE  begins another positive half cycle, the W PWM  signal ( FIG.  3 C ) turns off, and TRIAC Q 101  turns off. 
     The signal waveforms for a resistive load shown in  FIGS.  3 A- 3 C  appear similar to the conceptualized waveforms of  FIGS.  2 A- 2 C . Thyristor power control, however, has notorious problems with reactive complex loads due to the voltage and current no longer being in phase, and because a thyristor turns off only when the current through the thyristor goes to zero. 
       FIGS.  4 A- 4 C  respectively depict simulated TRIAC signal waveforms for the conventional power-control device  100  for an inductive load (Z L =+45°. The abscissa for each of  FIG.  4 A- 4 C  is time in milliseconds (ms), and the ordinate for each of  FIGS.  4 A- 4 C  is voltage in Volts (V). The simulation conditions for  FIGS.  4 A- 4 C  are V AC =120 V RMS , Z L =14.4Ω at +45°, and I L =8.33 A RMS . For a Z L  of 14.4Ω at +45° and 50 Hz, the resistive component R L  is 10.18Ω and the inductive component X L  is j10.18Ω (i.e., 32.41 mH at 50 Hz). For reasons described below, the power delivered to the resistive-inductive load is greater than the desired power of P L =353 W at 50% duty cycle, so the desired 50% dimming does not occur. It should be understood that, compared to the power that was delivered to the purely resistive load, with a 14.4 ohm reactive load with a real part of 10.18 ohms, the maximum power that can be delivered to the load is 706.34 watts. Again, it should be noted that although the time begins at t=0 ms in each of  FIGS.  4 A- 4 C , it should be understood that the specific times indicated are relative and have been selected for convenience, and that the waveforms depicted are in a steady-state condition. Also, although the frequency of V LINE  is 50 Hz, other frequencies for V LINE  are possible. 
     An oscillatory behavior of TRIAC Q 101  driving an inductive load can be seen in  FIGS.  4 A- 4 C . In particular, TRIAC Q 101  is on for 75% of the half cycles in contrast to the 50% duty cycle of the W PWM  waveform. In  FIG.  4 A , the voltage V TRIAC  (solid line) across TRIAC Q 101  exhibits the oscillatory behavior during the positive half cycle of V LINE  (0-10 ms) prior to the W PWM  signal turning on at t=5 ms (see  FIG.  4 C ). At t=5 ms, TRIAC Q 101  begins to conduct and the voltage V TRIAC  across TRIAC Q 101  drops to 0 V (neglecting the internal resistance of TRIAC Q 101 ). In  FIG.  4 B , the voltage V LOAD  (solid line) across the inductive load also exhibits an oscillatory behavior during the positive half cycle of V LINE  prior to the W PWM  signal turning on. At time t=10 ms, VLINE begins a negative half cycle (10-20 ms) and the W PWM  signal turns off. 
     Prior to the W PWM  signal turning on during the negative half cycle of VLINE at time t=15 ms, the voltage V TRIAC  across TRIAC Q 101  (solid line,  FIG.  4 A ) again exhibits an oscillatory behavior. At t=15 ms, TRIAC Q 101  begins to conduct in response to W PWM  turning on and the voltage V TRIAC  across TRIAC Q 101  drops to 0 V. In  FIG.  4 B , the voltage V LOAD  across the inductive load drops to V LINE  (solid line) at t=15 ms. At time t=20 ms, V LINE  begins another positive half cycle and the W PWM  signal turns off. 
       FIGS.  5 A- 5 C  respectively depict simulated TRIAC signal waveforms for power-control device  100  for a capacitive load (Z L =−45°. The abscissa for each of  FIG.  5 A- 5 C  is time in milliseconds (ms), and the ordinate for each of  FIGS.  5 A- 5 C  is voltage in Volts (V). The simulation conditions for  FIGS.  5 A- 5 C  are V AC =120 V RMS , Z L =14.4Ω at −45°, and I L =8.3 A RMS . For a Z L  of 14.4Ω at −45° and 50 Hz, the resistive component R L  is 10.18Ω and the capacitive component X L  is −j10.18Ω (i.e., 312.7 μF at 50 Hz). For reasons described below, the power delivered to the resistive-capacitive load is not the P L =500 W at 50% duty cycle that was delivered to the purely resistive load, but rather the power is not reduced at all from the nominal power, and so no dimming occurs. Again, it should be noted that although the time begins at t=0 ms in each of  FIGS.  5 A- 5 C , it should be understood that the specific times indicated are relative and have been selected for convenience, and that the waveforms depicted are in a steady-state condition. Also, although the frequency of V LINE , is 50 Hz, other frequencies for V LINE  are possible. 
     The waveforms of  FIGS.  5 A- 5 C  for the capacitive load depict complete power-control failure in which TRIAC Q 101  remains turned on for the entire period and completely unable to follow the W PWM  control signal. As depicted in  FIG.  5 A , the voltage V TRIAC  (solid line) across TRIAC Q 101  is equal to 0 V at all times. In  FIG.  5 B , the voltage V LOAD  (solid line) across the resistive-capacitive load is the same as V LINE  throughout the cycle of W PWM  depicted in  FIG.  5 C , i.e., the TRIAC is not providing any reduction of the power delivered to the load. 
     SUMMARY OF THE DISCLOSURE 
     The subject matter disclosed herein relates to a power-control device that enables energy transfer from a utility-generated sine wave V AC  to a load in which the load can be resistive, inductive or capacitive. The subject matter disclosed herein also enables a power control device to transfer energy stored into the load back to its source, i.e., energy transfer is bidirectional. 
     One exemplary embodiment provides a power-control device that comprises a V LINE  terminal, a load terminal, a neutral (NEU) terminal, an energy-import portion, and an energy-export portion. The energy-import portion is coupled between the V LINE  terminal and the load terminal. The energy-import is capable of importing energy to the load terminal during a first portion and a third portion of an alternating voltage V AC  waveform if the alternating voltage V AC  is coupled between the V LINE  terminal and the NEU terminal. The energy-export portion is coupled between the load terminal and the NEU terminal. The energy-import portion is capable of exporting energy from the load terminal during a second portion and a fourth portion of the alternating voltage V AC  waveform if the alternating voltage V AC  is coupled between the V LINE  terminal and the NEU terminal. The sum of the first, second, third and fourth portions of the alternating voltage V AC  waveform are equal to a period of the alternating voltage V AC  waveform and respectively are consecutive during the period of the alternating voltage V AC  waveform. 
     In one exemplary embodiment, the energy-import portion comprises a first MOSFET and a second MOSFET. The first MOSFET comprises a first terminal, a second terminal and a control terminal in which the first terminal of the first MOSFET is coupled to the V LINE  terminal. The second MOSFET comprises a first terminal, a second terminal and a control terminal in which the second terminal of the second MOSFET is coupled to the second terminal of the first MOSFET and the first terminal of the second MOSFET is coupled to the load terminal. The term MOSFET is used in a generic sense and is represents any two or more terminal electronic devices used to control the flow of current that can be wither voltage controlled, current controlled or field controlled. 
     In one exemplary embodiment, the energy-export section comprises a third MOSFET and a fourth MOSFET. The third MOSFET comprises a first terminal, a second terminal and a control terminal in which the first terminal of the third MOSFET is coupled to the load terminal. The fourth MOSFET comprises a first terminal, a second terminal and a control terminal in which the second terminal of the fourth MOSFET being coupled to the second terminal of the third MOSFET and the first terminal of the fourth MOSFET being coupled to the NEU terminal. 
     In one exemplary embodiment, the energy-import section further comprises a first driver and a second driver, and the energy-export section further comprises a third driver and a fourth driver. The first driver comprises an output coupled to the control terminal of the first MOSFET. The first driver is capable of outputting a first drive signal in response to a first pulse width modulation (PWM) control signal in which the first PWM signal corresponds to the first portion of alternating voltage V AC  waveform. The second driver comprises an output coupled to the control terminal of the second MOSFET. The second driver is capable of outputting a second drive signal in response to a second PWM control signal in which the second PWM signal corresponds to the third portion of the alternating voltage V AC  waveform. The third driver comprises an output coupled to the control terminal of the third MOSFET. The third driver is capable of outputting a third drive signal in response to a third PWM control signal in which the third PWM signal corresponds to the second portion of the alternating voltage V AC  waveform. The fourth driver comprises an output coupled to the control terminal of the fourth MOSFET. The fourth driver is capable of outputting a fourth drive signal in response to a fourth PWM control signal in which the fourth PWM signal corresponds to the fourth portion of the alternating voltage V AC  waveform. 
     In one exemplary embodiment, the first driver is capable of outputting a first synchronous rectification drive signal in response to a first synchronous rectification control signal in which the first synchronous rectification control signal corresponds to the third and fourth portions of the alternating voltage V AC  waveform. In one exemplary embodiment, the second driver is capable of outputting a second synchronous rectification drive signal in response to a second synchronous rectification control signal in which the second synchronous rectification control signal corresponds to the first and second portions of the alternating voltage V AC  waveform. In one exemplary embodiment, the third driver is capable of outputting a third synchronous rectification drive signal in response to a third synchronous rectification control signal in which the third synchronous rectification control signal corresponds to the third and fourth portions of the alternating voltage V AC  waveform. In one exemplary embodiment, the fourth driver is capable of outputting a fourth synchronous rectification drive signal in response to a fourth synchronous rectification control signal in which the fourth synchronous rectification control signal corresponds to the first and second portions of the alternating voltage V AC  waveform. It will be understood that each drive signal includes two components: A PWM control signal, and a synchronous rectifier signal that turns on the device in question. 
     In one exemplary embodiment, the energy-import section further comprises a first optical isolator and a second optical isolator, and the energy-export section further comprises a third optical isolator and a fourth optical isolator. The first optical isolator comprises an input and an output in which the input of the first optical isolator is configured to receive the first PWM control signal and the first synchronous rectification control signal, and the output of the first optical isolator is coupled to the first driver. The second optical isolator comprises an input and an output in which the input of the second optical isolator is configured to receive the second PWM control signal and the second synchronous rectification control signal, and the output of the second optical isolator is coupled to the second driver. The third optical isolator comprises an input and an output in which the input of the third optical isolator is configured to receive the third PWM control signal and the third synchronous rectification control signal, and the output of the third optical isolator is coupled to the third driver. The fourth optical isolator comprises an input and an output in which the input of the fourth optical isolator is configured to receive the fourth PWM control signal and the fourth synchronous rectification control signal, and the output of the fourth optical isolator is coupled to the fourth driver. 
     In one exemplary embodiment, the energy-import section further comprises a first power source, and the energy-export section further comprises a second power source. The first power source comprises a first terminal and a second terminal in which the first terminal of the first power source is coupled to the second terminal of the first MOSFET and the second terminal of the second MOSFET, and the second terminal of the first power source is coupled to the first and second drivers and the first and second optical isolators. The second power source comprises a first terminal and a second terminal in which the first terminal of the second power source is coupled to the second terminal of the third MOSFET and the second terminal of the fourth MOSFET, and the second terminal of the second power source is coupled to the third and fourth drivers and the third and fourth optical isolators. 
     In one exemplary embodiment, the power-control device further comprises a processing and power source section. The processing and power source section comprises a PWM waveform processor and a transformer. The PWM waveform processor is capable of receiving a main PWM control signal and generating the first through fourth PWM control signals and the first through fourth synchronous rectification control signals. The transformer comprises a primary winding and a first and second secondary windings in which the primary winding is capable of being coupled to the alternating voltage V AC , the first secondary winding is capable of being coupled to the first power source and the second secondary winding is capable of being coupled to the second power source. 
     One exemplary embodiment provides a power-control device, comprising a V LINE  terminal, a load terminal, a neutral (NEU) terminal, and a first linear-switching device. The first linear-switching device is coupled between the V LINE  terminal and the load terminal. The first linear-switching device comprises a first MOSFET, a first voltage supply, a first driver, a second MOSFET and a second driver. The first MOSFET comprises a first terminal, a second terminal and a control terminal. The first terminal of the first MOSFET is coupled to the V LINE  terminal. The first MOSFET is turned on in response to a first portion of a first control signal that is coupled to the control terminal and is turned off in response to a second portion of the first control signal. The first voltage supply is isolated from the NEU terminal, and comprises a first terminal coupled to the second terminal of the first MOSFET and a second terminal of the second MOSFET. The first driver is isolated from the NEU terminal. The first driver comprises an input, an output and a power terminal. The output of the first driver couples the first control signal to the control terminal of the first MOSFET in response to a main control signal received from a signal source that is isolated from the first driver. The first driver power terminal is coupled to the second terminal of the first voltage supply. The second MOSFET comprises a first terminal, a second terminal and a control terminal. The first terminal of the second MOSFET is coupled to the load terminal, and the second terminal of the second MOSFET is coupled to the second terminal of the first MOSFET. The second MOSFET is turned on in response to a first portion of a second control signal that is coupled to the control terminal and is turned off in response to a fourth portion of the second control signal. The second driver is isolated from the NEU terminal. The second driver comprises an input, an output and a power terminal. The output of the second driver couples the second control signal to the control terminal of the second MOSFET in response to the main control signal received from the signal source, which is isolated from the second driver. The power terminal of the second driver is coupled to the second terminal of the first voltage supply. The first linear-switching device is capable of sourcing energy to the load terminal during a first portion and a third portion of an alternating voltage V AC  waveform if the alternating voltage V AC  is coupled between the V LINE  terminal and the NEU terminal in which the first portion of the first control signal corresponds to the first portion of the alternating voltage V AC , and the second portion of the second control signal corresponds to the third portion of the alternating voltage V AC . 
     As noted above, each drive control signal has two components: a synchronous rectifier portion which is on for portions 1 &amp; 2 or portions 3 &amp; 4 of the sine wave and a PWM control signal for one of the half cycles. The sequence of either the synchronous rectifier or PWM signals is driver position dependent as shown in  FIG.  10   . In  FIG.  10    drive signal W 1  consists of a PWM signal first, and a synchronous rectifier signal second in a timed sequence from t=0. Generally, the synchronous rectification signal forces the MOSFETS into full conduction over the requisite half cycles 
     In one exemplary embodiment, the power-control device further comprises a second linear-switching device coupled between the load terminal and the NEU terminal. The second linear-switching device comprises a third MOSFET, a second voltage supply, a third driver, a fourth MOSFET and a fourth driver. The third MOSFET comprises a first terminal, a second terminal and a control terminal. The first terminal of the third MOSFET is coupled to the V LOAD  terminal. The third MOSFET is turned on in response to a first portion of a third control signal that is coupled to the control terminal. The second voltage supply is isolated from the NEU terminal. The second voltage supply comprises a first terminal coupled to the second terminal of the third MOSFET and a second terminal. The third driver is isolated from the NEU terminal. The third driver comprises an input, an output and a power terminal. The output of the third driver couples the third control signal to the control terminal of the third MOSFET in response to the main control signal received from the signal source, which is isolated from the third driver. The power terminal of the third driver is coupled to the second terminal of the second voltage supply. The fourth MOSFET comprises a first terminal, a second terminal and a control terminal. The first terminal of the fourth MOSFET is coupled to the load terminal. The second terminal of the fourth MOSFET is coupled to the second terminal of the third MOSFET. The fourth MOSFET is turned on in response to a first portion of a fourth control signal that is coupled to the control terminal and is turned off in response to a second portion of the fourth control signal. The fourth driver is isolated from the NEU terminal. The fourth driver comprises an input, an output, and a power terminal. The output of the fourth driver couples the fourth control signal to the control terminal of the fourth MOSFET in response to the main control signal received from the signal source, which is isolated from the fourth driver. The fourth driver power terminal is coupled to the second terminal of the second voltage supply. The second linear-switching device is capable of sinking energy from the load terminal during a second portion and a fourth portion of the alternating voltage V AC  waveform if the alternating voltage V AC  is coupled between the V LINE  terminal and the NEU terminal in which the first, second, third and fourth portions of the alternating voltage V AC  waveform span a period of the alternating voltage V AC  waveform and respectively being consecutive during the period of the alternating voltage V AC  waveform. 
     In one exemplary embodiment, the first linear-switching device further comprises a first feedback network and a second feedback network. The first feedback network is coupled between the first terminal and the control terminal of the first MOSFET. The first feedback network couples a first voltage transition at the first terminal of the first MOSFET to the control terminal of the first MOSFET. The first voltage transition is caused by the first MOSFET being turned off in response to the turning off of the first portion (PWM) of the first control signal. The second feedback network is coupled between the first terminal and the control terminal of the second MOSFET. The second feedback network couples a second voltage transition at the first terminal of the second MOSFET to the control terminal of the second MOSFET. The second voltage transition is caused by the second MOSFET being turned off in response to the second portion of the third control signal. 
     In one exemplary embodiment, the second linear-switching device further comprises a third feedback network and a fourth feedback network. The third feedback network is coupled between the first terminal and the control terminal of the third MOSFET. The third feedback network couples a third voltage transition at the first terminal of the third MOSFET to the control terminal of the third MOSFET. The third voltage transition is caused by the third MOSFET being turned off in response to the second portion of the third control signal. The fourth feedback network is coupled between the first terminal and the control terminal of the fourth MOSFET. The fourth feedback network couples a fourth voltage transition at the first terminal of the fourth MOSFET to the control terminal of the fourth MOSFET. The fourth voltage transition is caused by the fourth MOSFET being turned off in response to the fourth portion of the fourth control signal. 
     In one exemplary embodiment, the first control signal comprises a first pulse width modulation (PWM) control signal which controls the first portion of the alternating voltage VAC waveform and a first synchronous rectification drive signal that controls the third and fourth portions of the alternating voltage VAC waveform. In one exemplary embodiment, the second control signal comprises a first synchronous rectifier control signal which controls the first and second portions of the alternating voltage VAC waveform and a second pulse width modulation (PWM) control signal that controls the third portion of the alternating voltage VAC waveform. In one exemplary embodiment, the third control signal comprises a third pulse width (PWM) control signal which controls the third portion of the alternating voltage VAC waveform and a third pulse synchronous rectifier control signal that controls the second portion of the alternating voltage VAC waveform. In one exemplary embodiment, the fourth control signal comprises a first synchronous rectifier control signal which controls the first and second portions of the alternating voltage VAC waveform and a fourth pulse width modulation (PWM) control signal that controls the fourth portion of the alternating voltage VAC waveform. 
     In one exemplary embodiment, the first linear-switching device further comprises a first optical isolator and a second optical isolator. The first optical isolator comprises an input and an output. The input of the first optical isolator is configured to receive the first control signal, and the output of the first optical isolator is coupled to the first driver. The second optical isolator comprises an input and an output. The input of the second optical isolator is configured to receive the second control signal, and the output of the second optical isolator is coupled to the input of the second driver. In one exemplary embodiment, the second linear-switching device further comprises a third optical isolator and a fourth optical isolator. The third optical isolator comprises an input and an output. The input of the third optical isolator is configured to receive the third control signal, and the output of the third optical isolator is coupled to the input of the third driver. The fourth optical isolator comprises an input and an output. The input of the fourth optical isolator is configured to receive the fourth control signal, and the output of the fourth optical isolator is coupled to the input of the fourth driver. 
     In one exemplary embodiment, the power-control device further comprises a processing and power source section. The processing and power source section comprises a control waveform processor capable of receiving the main control signal and generating the first through fourth control signals. The transformer comprises a primary winding and first, second, and third secondary windings. The primary winding is capable of being coupled to the alternating voltage V AC . The first secondary winding is capable of being coupled to the first voltage supply and the second secondary winding is capable of being coupled to the second voltage supply. The third winding supplies power to the processing and power source section. 
     Yet another exemplary embodiment provides a power-control device comprising a V LINE  terminal, a load terminal, and a first linear-switching device. The first linear-switching device is coupled between the V LINE  terminal and the load terminal. The first linear-switching device comprises a first MOSFET and a second MOSFET. The first MOSFET comprises a first terminal, a second terminal and a control terminal. The first terminal of the first MOSFET is coupled to the V LINE  terminal. The second MOSFET comprises a first terminal, a second terminal and a control terminal. The second terminal of the second MOSFET is coupled to the second terminal of the first MOSFET and the first terminal of the second MOSFET is coupled to the load terminal. The first linear-switching device is capable of sourcing energy to the load terminal during a first portion and a third portion of an alternating voltage V AC  waveform if the alternating voltage V AC  is coupled to the V LINE  terminal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter disclosed herein is illustrated by way of example and not by limitation in the accompanying figures in which like reference numerals indicate similar elements and in which: 
         FIG.  1    depicts a conventional thyristor-based power-control device that includes a choke circuit for reducing EMI; 
         FIG.  2    depicts conceptualized conduction-angle modulation waveforms for V LINE , V LOAD  and W PWM  for the conventional power-control device of  FIG.  1   ; 
         FIGS.  3 A- 3 C  respectively depict simulated TRIAC signal waveforms for the conventional power-control device of  FIG.  1    for a resistive load; 
         FIGS.  4 A- 4 C  respectively depict simulated TRIAC signal waveforms for the conventional power-control device of  FIG.  1    for a resistive-inductive load (Z L  at +45°); 
         FIGS.  5 A- 5 C  respectively depict simulated TRIAC signal waveforms for the conventional power-control device of  FIG.  1    for a resistive-capacitive load (Z L  at −45°); 
         FIG.  6    depicts a functional block diagram of a first exemplary embodiment of a power-control circuit according to the subject matter disclosed herein; 
         FIG.  7    depicts conceptualized conduction-angle modulation waveforms for V LINE , V LOAD , W 0 , W 1  and W 2  for the power-control circuit of  FIG.  6   ; 
         FIGS.  8 A- 8 C  depict a simulation of internal waveforms of the power-control device of  FIG.  6    during a full sine wave period of V LINE  for a conduction duty cycle of 50% for a resistive load; 
         FIGS.  8 D- 8 F  respectively depict the simulated waveforms of  FIGS.  8 A- 8 C  for t=4.5 ms to t=5.5 ms; 
         FIG.  9    depicts a functional block diagram of a second exemplary embodiment of a power-control device according to the subject matter disclosed herein; 
         FIG.  10    depicts conceptualized conduction-angle modulation waveforms for the power-control device of  FIG.  9   ; 
         FIGS.  11 A- 11 C  respectively depict a simulation of load current I LOAD  waveforms output from the power-control device of  FIG.  9    during a full sine wave period for a conduction duty cycle of 50% for a resistive load (I LOADR ), a resistive-inductive load (I LOADL ), and a resistive-capacitive load (I LOAOC ); 
         FIG.  12 A  depicts the resulting output voltage V LOAD  as a percentage of V LINE  for the power-control device of  FIG.  9    as a function of the percentage PWM modulation (PWM %); 
         FIG.  12 B  depicts the PWM % modulation as a function of the output voltage V LOAD  as a percentage of V LINE  for the power-control device of  FIG.  9   ; 
         FIG.  13    depicts a functional block diagram of an exemplary embodiment of a general processing and power supply circuit for a power-control device according to the subject matter disclosed herein; 
         FIG.  14    depicts a functional block diagram of a power-control device having current-sensing and temperature-sensing capability according to the subject matter disclosed herein; 
         FIG.  15 A  depicts a simulated RMS output voltage V RMS  for the power-control device of  FIG.  9    as a function of percentage modulation (% Modulation) of the input voltage V LINE  for each of a resistive load, an inductive load and a capacitive load; 
         FIG.  15 B  depicts a simulated RMS output current I RMS  for the power-control device of  FIG.  9    as a function of percentage modulation (% Modulation) of the input voltage V LINE  for the same simulation conditions as  FIG.  15 A ; and 
         FIG.  15 C  depicts a simulated total power dissipation for the power-control device of  FIG.  9    as a function of percentage modulation (% Modulation) of the input voltage V LINE  for the same simulation conditions as  FIG.  15 A . 
     
    
    
     DETAILED DESCRIPTION OF THE DISCLOSURE 
     As used herein, the word “exemplary” means “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not to be construed as necessarily preferred or advantageous over other embodiments. Additionally, it will be appreciated that for simplicity and/or clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for illustrative clarity. Further, in some figures only one or two of a plurality of similar elements are indicated by reference characters for illustrative clarity of the figure, whereas less than all of the similar elements may be indicated by reference characters. Further still, it should be understood that although some portions of components and/or elements of the subject matter disclosed herein have been omitted from the figures for illustrative clarity, good engineering, construction and assembly practices are intended. 
     The subject matter disclosed herein relates to a power-control device that enables energy transfer from a utility-generated sine wave V AC  to a load in which the load can be resistive, inductive or capacitive. One exemplary embodiment of the subject matter disclosed herein provides variable power control to a load in response to a variable on/off time of a PWM control signal. 
     Energy should be supplied to a reactive load during a PWM “on” time, and be removed from the load during the PWM “off” time. One exemplary embodiment of the subject matter disclosed herein provides active charge and discharge control to two distinct circuit structures; one circuit structure handles the charging of a reactive load (i.e., the PWM “on” time) and the other circuit structure handles the discharging of the reactive load (i.e., the PWM “off” time). 
       FIG.  6    depicts a functional block diagram of a first exemplary embodiment of a power-control circuit  600  according to the subject matter disclosed herein. Power-control circuit  600  is configured to drive a resistive load, and may comprise two linear-switching stages  601  and  602  that are connected back-to-back between V LINE  and load Z L . 
     Linear-switching stage  601  comprises a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Q 601 , a driver D 601 , and an optical isolator I 601 . The output of optical isolator I 601  is coupled to the input of driver D 601 . The output of driver D 601  is coupled to the gate of MOSFET Q 601  through a resistor R 601 . A capacitor C 601  is coupled between the drain and gate of MOSFET Q 601  and provides closed-loop feedback around MOSFET Q 601 . In particular, capacitor C 601  reduces the high-frequency gain of MOSFET Q 601 , thereby attenuating the frequency components generated by MOSFET Q 601  as MOSFET Q 601  switches between on/off states. Use of capacitor C 601  as a feedback element along with resistor R 601  linearizes the switching transition of MOSFET Q 601  without affecting the static saturation characteristics of MOSFET Q 601 . 
     Linear-switching stage  602 , which is paired with linear-switching stage  601 , comprises a MOSFET Q 602 , a driver D 602 , and an optical isolator I 602 . The output of optical isolator I 602  is coupled to the input of driver D 602 . The output of driver D 602  is coupled to the gate of MOSFET Q 602  through a resistor R 602 . A capacitor C 602  is coupled between the drain and gate of MOSFET Q 602  and provides closed-loop feedback around MOSFET Q 602 . As with switching stage  601 , capacitor C 602  and resistor R 602  linearize the switching transition of MOSFET Q 602  without affecting the static saturation characteristics MOSFET Q 602 . 
     The drain of MOSFET Q 601  is coupled to V LINE , and the drain of MOSFET Q 602  is coupled to load R L . The sources of MOSFETs Q 601  and Q 602  are coupled together. A floating, isolated voltage supply V 1  is connected to the sources of MOSFETs Q 601  and Q 602 . Voltage supply V 1  powers the gate drivers D 601  and D 602  and isolators I 601  and I 602 . Supply V 1  tracks and floats with the changing voltage conditions across MOSFETs Q 601  and Q 602  to thereby maintain and facilitate a linear-switching feedback characteristic for MOSFETs Q 601  and Q 602 . 
     Gate resistors R 601  and Q 602  are respectively driven from drivers D 601  and D 602 , which in turn are respectively driven by isolators I 601  and I 602 . PWM control waveforms W 1  and W 2  set the on/off periods of MOSFETs Q 601  and Q 602 . The linear-switching characteristics and slope or turn-on time for MOSFETs Q 601  and Q 602  are respectively determined by the time constants of R 601  and C 601 , and R 602  and C 602 . 
     The time constants may be selected in accordance with known methodology for optimizing the linear-switching characteristics and slope or turn-on time for the MOSFETS. For example, as described below for  FIGS.  8 D- 8 F , the circuit component characteristics may be selected for a linear switching characteristic that is smooth and linear and with an adequate turn-off transition rate suited to the specifications for the particular application of the power-control device. For  FIGS.  8 D- 8 F  the slew rate is limited to a rate of approximately 3V/usec. 
       FIG.  7    depicts conceptualized conduction-angle modulation waveforms for V LINE , V LOAD , W 0 , W 1  and W 2  for power-control circuit  600  of  FIG.  6   . The shaded areas in  FIG.  7    represent the portion of V AC  in which the half-cycle modulation is applied. Unlike the conceptualized thyristor conduction angle depicted in  FIG.  2   , which was lagging modulation, a leading-conduction angle modulation is depicted in  FIG.  7   . That is, the transition occurs as a turn-off transition instead of a turn-on transition, as was the case for device  100  in  FIG.  1   . A leading-conduction angle modulation allows the load voltage V LOAD  to rise gradually with the relatively slow-moving sine wave of the low-frequency utility voltage V AC  at the start of each half cycle, thereby reducing stress in all components including the load R L . MOSFETs Q 601  and Q 602  turn on at the start of each half cycle and turn off at the end of the PWM “on” time. The linear transitions at the trailing edges of the V LINE  and V LOAD  waveforms have a reduced harmonic content in comparison to an abrupt transition. 
     In  FIG.  7   , waveform W 0  is the master PWM control signal and repeats every half cycle. Waveform W 0  is respectively divided in a well-known manner during the positive and negative half cycles of V LINE  into waveforms W 1  and W 2  for alternating control of MOSFET Q 601  and Q 602 . While one MOSFET is conducting in response to a PWM control drive signal, the internal substrate diode of the other MOSFET conducts because it is forward biased, and also in response to a PWM synchronous rectification (sync rect) drive signal to reduce the losses within the MOSFET to be less than that of the internal substrate diode alone by using the parallel R ds  of the “other” MOSFET. 
     The resulting total power loss in the current path to the load is twice the MOSFET R ds  multiplied by the square of the load current. No other diodes or bridge rectifiers are required in circuit  600 , thus providing very high efficiency. The isolated, floating local supply V 1 , the input isolators I 601  and I 602 , and the gate-drive system of the MOSFET pair is entirely floating, thereby enabling proper linear-switching characteristics for power-control circuit  600 . 
     During the positive half cycle of V LINE , current flows from the V LINE  terminal to the NEU terminal. Transistor Q 601  operates as the controlling MOSFET in response to the PWM “on” time, while transistor Q 602  operates as a synchronous rectifier enabled for the entire half cycle. During the negative half cycle of V LINE , current flows from the NEU terminal to the V LINE  terminal. MOSFET Q 602  operates as the controlling MOSFET programmed with the PWM “on” time, while MOSFET Q 601  operates as a synchronous rectifier enabled for the entire half cycle. 
       FIGS.  8 A- 8 C  depict a simulation of internal waveforms of power-control device  600  during a full sine wave period of V LINE  for a conduction duty cycle of 50% for a resistive load. The simulation conditions for  FIGS.  8 A- 8 C  are V AC =120 V RMS , R L =14.4Ω, I L =8.3 A RMS , and power delivered to R L  is P L =500 W. The abscissa for each of  FIG.  8 A- 8 C  is in milliseconds (ms), and the ordinate for each of  FIGS.  8 A- 8 C  in Volts (V). It should be noted that the abscissas for  FIGS.  8 A- 8 C  begin at t=0 ms. The specific time reference has been selected for convenience and that the waveforms are depicted in a steady state condition. The frequency of V LINE  is 50 Hz. 
       FIG.  8 A  depicts the waveform for V LINE  (solid line) superimposed over the waveform for V LOAD  (dotted line).  FIG.  8 B  depicts the waveform for voltage V ds Q601  from drain to source of MOSFET Q 601  (solid line) superimposed over the voltage V ds Q602  from drain to source of MOSFET Q 602  (dotted line). The linear-switching characteristics of the turn-off transition are smooth and linear. In this particular example, the turn-off transition requires about 55 μsec to slew about 170 V. This is about a slew rate of 3 V/μsec, and is comparable to what is generally seen in conventional thyristor and choke designs.  FIG.  8 C  depicts the waveform for the voltage V gs Q601  from gate to source of MOSFET Q 601  (solid line) superimposed over the voltage V gs Q602  from gate to source of MOSFET Q 602  (dotted line). 
       FIGS.  8 D- 8 F  respectively depict the simulated waveforms of  FIGS.  8 A- 8 C  for t=4.5 ms to t=5.5 ms. Although the time scale has been expanded around t=5 ms and only the simulated waveform transitions associated with MOSFET Q 601  are visible, the simulated waveforms associated with MOSFET Q 602  are similar. The linear switching characteristic of MOSFET Q 601  for the turn-off transition ( FIG.  8 D , V LOAD ; and  FIG.  8 E , V ds Q601 ) is smooth and linear. In this particular example, the turn-off transition requires about 55 μs to slew about 170 V, which is a slew rate of about 3 V/μs. 
       FIG.  9    depicts a functional block diagram of a second exemplary embodiment of a power control device  900  according to the subject matter disclosed herein. Power-control device  900  is configured to drive any type of load—resistive, inductive or capacitive. Power control device  900  comprises an energy-import section  910  and an energy-export section  920 . Energy-import section  910  charges a load Z L  from V LINE  during a PWM on time, and energy-export section  920  discharges the load Z L  into the NEU terminal during the PWM off time. 
     Energy-import section  910  comprises two linear-switching stages  901  and  902  that are connected back-to-back between V LINE  and Z L . Energy-export section  920  comprises two linear-switching stages  903  and  904  that are connected back-to-back between load Z L  and NEU. 
     Linear-switching stage  901  comprises a MOSFET Q 901 , a driver D 901 , and an optical isolator I 901 . The output of optical isolator I 901  is coupled to the input of driver D 901 . The output of driver D 901  is coupled to the gate of MOSFET Q 901  through a resistor R 901 . A capacitor C 901  is coupled between the drain and gate of MOSFET Q 901  and provides closed-loop feedback around MOSFET Q 901 . In particular, capacitor C 901  reduces the high-frequency gain of MOSFET Q 901 , thereby attenuating the frequency components generated by MOSFET Q 901  as MOSFET Q 901  switches between on/off states. Use of capacitor C 901  as a feedback element along with resistor R 901  linearizes the switching transition of MOSFET Q 901  without affecting the static saturation characteristics Q 901 . 
     Linear-switching stage  902 , which is paired with linear-switching stage  901 , comprises a MOSFET Q 902 , a driver D 902 , and an optical isolator I 902 . The output of optical isolator I 902  is coupled to the input of driver D 902 . The output of driver D 902  is coupled to the gate of MOSFET Q 902  through a resistor R 902 . A capacitor C 902  is coupled between the drain and gate of MOSFET Q 902  and provides closed-loop feedback around MOSFET Q 902 . As with switching stage  901 , capacitor C 902  and resistor R 902  linearizes the switching transition of MOSFET Q 902  without affecting the static saturation characteristics of MOSFET Q 902 . 
     The drain of MOSFET Q 901  is coupled to V LINE , and the drain of MOSFET Q 902  is coupled to load Z L . The sources of MOSFETs Q 901  and Q 902  are coupled together. A floating, isolated voltage supply V 1  is connected to the sources of MOSFETs Q 901  and Q 902 . Voltage supply V 1  powers the gate drivers D 901  and D 902  and isolators I 901  and I 902 . Supply V 1  tracks and floats with the changing voltage conditions across MOSFETs Q 901  and Q 902  to thereby maintain and facilitate a linear-switching feedback characteristic for MOSFETs Q 901  and Q 902 . 
     Gate resistors R 901  and R 902  are respectively driven from drivers D 901  and D 902 , which in turn are respectively driven by isolators I 901  and I 902 . PWM control waveforms W 1  and W 2  set the on/off periods of MOSFETs Q 901  and Q 902 . The linear-switching characteristics and slope for MOSFETs Q 901  and Q 902  are respectively determined by the time constants of R 901  and C 901 , and R 902  and C 902 . The time constants may be selected in accordance with known methodology for optimizing the linear-switching characteristics and slope for the MOSFETS. For example, the circuit component characteristics may be selected for a linear switching characteristic that is smooth and linear and with an adequate turn-off transition rate suited to the specifications for the particular application of the power-control device. 
     Linear-switching stage  903  comprises a MOSFET Q 903 , a driver D 903 , and an optical isolator I 903 . The output of optical isolator I 903  is coupled to the input of driver D 903 . The output of driver D 903  is coupled to the gate of MOSFET Q 903  through a resistor R 903 . A capacitor C 903  is coupled between the drain and gate of MOSFET Q 903  and provides closed-loop feedback around MOSFET Q 903 . Capacitor C 903  reduces the high-frequency gain of MOSFET Q 903 , thereby attenuating the frequency components generated by MOSFET Q 903  as MOSFET Q 903  switches between on/off states. The use of capacitor C 903  as a feedback element along with resistor R 903  linearizes the switching transition of MOSFET Q 903  without affecting the static saturation characteristics. 
     Linear-switching stage  904 , which is paired with linear-switching stage  903 , comprises a MOSFET Q 904 , a driver D 904 , and an optical isolator I 904 . The output of optical isolator I 904  is coupled to the input of driver D 904 . The output of driver D 904  is coupled to the gate of MOSFET Q 904  through a resistor R 904 . A capacitor C 904  is coupled between the drain and gate of MOSFET Q 904  and provides closed-loop feedback around MOSFET Q 904 . As with switching stage  903 , capacitor C 904  and resistor R 904  linearizes the switching transition of MOSFET Q 904  without affecting the static saturation characteristics. 
     The drain of MOSFET Q 903  is coupled to Z L , and the drain of MOSFET Q 904  is coupled to the NEU terminal. The sources of MOSFETs Q 903  and Q 904  are coupled together. A floating, isolated voltage supply V 2  is also connected to the sources of MOSFETs Q 903  and Q 904 . Voltage supply V 2  powers the gate drivers D 903  and D 904  and isolators I 903  and I 904 . Supply V 2  tracks and floats with the changing voltage conditions across MOSFETs Q 903  and Q 904  to thereby maintain and facilitate a linear-switching feedback characteristic. 
     Gate resistors R 903  and R 904  are respectively driven from drivers D 903  and D 904 , which in turn are respectively driven by isolators I 903  and I 904 . PWM control waveforms W 3  and W 4  set the on/off periods of MOSFETs Q 903  and Q 904 . The linear-switching characteristic and slope is determined by the time constants of R 903  and C 903 , and R 904  and C 904 . The time constants may be selected in accordance with known methodology for optimizing the linear-switching characteristics and slope for the MOSFETS. For example, the circuit component characteristics may be selected for a linear switching characteristic that is smooth and linear and with an adequate turn-off transition rate suited to the specifications for the particular application of the power-control device. 
     The substrate diodes of MOSFETs Q 903  and Q 904  provide a commutation function for energy-export section  920 . Any inductive EMF voltage from the load will be suppressed by the conduction of the substrate diodes, thereby protecting both MOSFETs Q 901  and Q 902  from being driven below the NEU voltage. When the PWM off time begins, both MOSFETs Q 903  and Q 904  are placed into full conduction, thereby enabling discharge of a capacitive load reactance. 
       FIG.  10    depicts conceptualized conduction-angle modulation waveforms for power-control device  900 . In  FIG.  10   , the Energy waveform represents portions of a conceptualized waveform for V LINE  in which energy-import section  910  imports, or sources, energy into load Z L , and in which energy-export section  920  exports, or sinks, energy from load Z L . That is, energy-import section  911  charges load Z L , from V LINE  during the on time of PWM signal W 0 , and energy-export section  920  discharges load Z L , into the NEU during the off time of PWM signal W 0 . 
     Waveform W 0  is the master or main PWM control signal and repeats every half cycle. Waveform W 0  is respectively divided into waveforms W 1  and W 2  during the positive and negative half cycles for alternating control of MOSFETs Q 901  and Q 902 . That is, while MOSFET Q 901  is conducting under a PWM control drive signal, the internal substrate diode of MOSFET Q 902  conducts as it is forward biased, and Q 902  is forced into conduction in response to a PWM synchronous rectification (sync rect) drive signal in order to reduce the losses, which are less than that of the substrate diode alone because R ds  of MOSFET Q 902  is in parallel with the substrate diode. Similarly, while MOSFET Q 902  is conducting in response to a PWM control drive signal, the internal substrate diode of MOSFET Q 901  conducts as it is forward biased and Q 901  is forced into conduction in response to a PWM synchronous rectification drive signal. 
     The complement of waveform W 0  (/W 0 ) is similarly divided into waveforms W 3  and W 4  during the positive and negative half cycles for alternating control of MOSFETs Q 903  and Q 904 . While MOSFET Q 903  is conducting in response to the /PWM control drive signal W 3 , the internal substrate diode of MOSFET Q 904  conducts as it is forward biased and also in response to a /PWM synchronous rectification (sync rect) drive signal, and while MOSFET Q 904  is conducting in response to a /PWM control drive signal W 4 , the internal substrate diode of MOSFET Q 903  conducts as it is forward biased and also in response to a /PWM synchronous rectification drive signal. 
     Any potential issue of simultaneous conduction between energy-import section  910  and energy-export section  920  is managed using an RC time constant (R 903 /C 903 , R 904 /C 904 ) for energy-export section  920  that typically is about twice that of the RC time constant (R 901 /C 901 , R 902 /C 902 ) of energy-import section  910 . 
     In operation, power control device  900  provides an output voltage V LOAD  across load Z L  that is identical for all three load-impedance conditions. Moreover, power-control device  900  provides that the voltages across the MOSFETs Q 901 -Q 904  also remain identical or substantially identical in all three load-impedance cases. 
       FIGS.  11 A- 11 C  respectively depict a simulation of load current I LOAD  waveforms output from power-control device  900  during a full sine wave period for a conduction duty cycle of 50% for a resistive load (I LOADR ), an inductive load (I LOADL ), and a capacitive load (I LOADC ). 
     The resistive load current waveform I LOADR  shown in  FIG.  11 A  is intuitively easy to understand because the current waveform in a resistive load is proportional to and in phase with to the voltage waveform appearing across the resistive load. The same, however, cannot be said for reactive loads. A non-sinusoidal voltage waveform contains harmonics, and when applied to a reactive load, the harmonics produce current waveforms that appear entirely different from the voltage waveform. For the inductive and the capacitive reactive-load cases, respectively shown in  FIGS.  11 B and  11 C , the load current remains active during all portions of the PWM on/off times, which is necessary for properly driving reactive loads. Only for the resistive load, shown in  FIG.  11 A , does the load current I LOAD  abruptly fall to zero. 
       FIG.  12 A  depicts the resulting output voltage V LOAD  as a percentage of V LINE  for power control device  600  or  900  as a function of the percentage PWM modulation (PWM %). The relationship between the PWM % modulation and V LOAD /V LINE % is nonlinear and shown by curve  1201 .  FIG.  12 B  depicts the PWM % modulation as a function of output voltage V LOAD  as a percentage of V LINE  for power-control device  600  or  900 . Curve  1202  in  FIG.  12 B  is the PWM transfer function for producing a linear voltage output relative to a linear input control signal. 
       FIG.  13    depicts a functional block diagram of an exemplary embodiment of a general processing and power supply circuit  1300  for power-control device  900  according to the subject matter disclosed herein. General processing and power supply circuit  1300  comprises a signal processing section  1301  and a power supply section  1302 . 
     In one exemplary embodiment, signal processing section  1301  comprises a PWM transfer function device  1303 , a positive and negative cycle detector  1304  and a waveform processor  1305 . PWM transfer function device  1303  receives a main PWM control signal that communicates a desired percentage of modulation, and generates in a well-known manner a PWM output control signal that is based on the transfer function depicted in  FIG.  12 B . The main PWM control signal received by PWM transfer function device  1303  may be analog, digital, or even a simple potentiometer. In one exemplary embodiment, PWM transfer function device  1303  outputs a W 0  depicted in  FIG.  10   . Positive and negative cycle detector  1304  receives a signal corresponding to V AC  (i.e., V LINE ) and generates in a well-known manner a positive cycle detection (PCD) signal and a negative cycle detection (NCD) signal that respectively correspond to the positive portion and the negative portion of V AC . Waveform processor  1305  receives the PWM output control signal from PWM transfer function device  1303  and the PCD and NCD signals and generates in a well-known manner PWM controls signals that control the operation of, for example, power-control device  900 . In one exemplary embodiment, waveform processor  1305  generates PWM control signals W 1 -W 4 , which are depicted in  FIG.  10   . In one exemplary embodiment, PWM control signals W 1 -W 4  are respectively coupled to I 901 -I 904 . 
     In one exemplary embodiment, power supply section  1302  includes two floating DC supplies  1306  and  1307 , which respectively produce V 1  and V 2 , depicted in  FIG.  9   . More specifically, power supply section  1302  comprises a transformer T 1308  having a primary winding that is coupled to V AC  and secondary windings coupled to DC supplies  1306  and  1307 . DC supplies  1306  and  1307  generate V 1  and V 2  in a well-known manner. In one exemplary embodiment, the power requirements for power supply section  1302  are small, generally less than one watt. In one exemplary alternative embodiment, power supply section  1302  comprises a DC power supply  1309  that powers signal processing section  1301 . For this exemplary alternative embodiment, PWM transfer function device  1303  receives the PWM control signal that communicates a desired percentage of modulation through, for example, an optical isolator, in which case, the W 1 -W 4  outputs from waveform processor  1305  are respectively coupled directly into drivers D 901 -D 904 . 
     In one exemplary embodiment, general processing and power supply circuit  1300  is configured to generate PWM control signals W 1  and W 2  for controlling the operation of, for example, power-control circuit  600 . In one exemplary embodiment, general processing and power supply circuit  1300  is configured to generate floating DC supply V 1  for power-control circuit  600 . 
       FIG.  14    depicts a functional block diagram of a power-control device  1400  having current-sensing and temperature-sensing capability according to the subject matter disclosed herein. In one exemplary embodiment, current flow through MOSFETs Q 901  and Q 902  can be detected by including a low-value shunt resistor R S  between the sources of MOSFETs Q 901  and Q 902 , as depicted in  FIG.  14   . Shunt resistor R S  is also coupled to a local common provided by voltage source V 1 . The voltage drop across shunt resistor R S  is detected in a well-known manner by a current-sensing circuit  1401 . Drivers D 901  and D 902  are also coupled to the local common and can be disabled as desired when a short-circuit condition is detected. Current flow through MOSFETS Q 901  and Q 902  may also be sensed by measuring the voltage across the MOSFETS R ds  on by well-established methods for over current protection. 
     In one exemplary embodiment, thermal protection is provided by sensing the temperature of MOSFETs Q 901  and Q 902  and/or of a heatsink coupled to MOSFETs Q 901  and Q 902  by, for example, a thermistor (not shown). A temperature-sensing circuit  1402  can disable MOSFET drivers D 901  and D 902 . It should be noted that current-sensing circuit  1401  and temperature-sensing circuit  1402  are depicted as being coupled to energy-import section  910  of power-control device  900  because after an over-current condition and/or an overtemperature condition has been sensed and drivers D 901  and D 902  have been disabled, energy-export section  920  of power-control device  900  remains enabled to export from Z L  any remaining reactive energy. It should also be noted that the over-current and over-temperature sensing circuits depicted in  FIG.  14    could be incorporated into power-control device  600  of  FIG.  6   . 
       FIG.  15 A  depicts a simulated RMS output voltage V RMS  for power-control device  900  as a function of the Control Signal ( FIG.  13   ) (% Control Signal) for each of a resistive load, an inductive load and a capacitive load. The linear relationship between % Control Signal and V RMS  may be achieved by use of the circuit of  FIG.  13   . For the simulation of  FIG.  15 A , V LINE  was set to be 120 V RMS  at a frequency of 50 Hz. Input current was 8.33 A RMS , and input power was 1000 W for 100% modulation. For the simulation, the resistive load was 14.4Ω; the inductive load was 10.18Ω+32.41 mH; and the capacitive load was 10.18Ω+312.7 μF. The RMS output voltages for the different three loads are essentially superimposed on each other. 
       FIG.  15 B  depicts a simulated RMS output current for power-control device  900  as a function of the Control Signal ( FIG.  13   ) (% Control Signal) for the same simulation conditions as  FIG.  15 A . The substantially linear relationship between % Control Signal and I RMS  may be achieved by use of the circuit of  FIG.  13   . The RMS output current I RMS  for the three different loads are indicated in  FIG.  15 B . Output current for the inductive load is shown as being bowed downward, while output current for the capacitive load is shown as being bowed upward. Output current for the resistive load is shown between the curves for the inductive load and the capacitive load. 
       FIG.  15 C  depicts a simulated total power dissipation for power-control device  900  as a function of the Control Signal ( FIG.  13   ) (% Control Signal) for the same simulation conditions as  FIG.  15 A .  FIG.  15 C  also depicts for comparison a simulated power dissipation for the conventional thyristor or TRIAC power-control device  100  under the same conditions. Device  900  provides an efficiency of 99.4%, while the conventional thyristor power-control device  100  provides an efficiency of 98.8%. It should be understood that 99.4% efficiency is predicated on the R ds  for a suitable MOSFET for example 40 milli-ohms. 
     The efficiency for both power-control device  900  and conventional power-control device  100  is very high; however, the real significant difference is the actual power dissipation of device  900  and that of device  100 . In particular, for the simulation conditions, circuit  900  consumes 6 W while device  100  consumes 12 W. Thus, device  900  provides a 50% reduction in heatsinking and thermal management relative to device  100 . That difference is important as the size and structure of any heatsinking, airflow, and thermal load requirements would be cut by half. 
     It should be understood that although the transistors of power-control devices  600  ( FIG.  6   ) and  900  ( FIG.  9   ) are depicted as MOSFETS, Insulated-Gate Bipolar Transistors (IGBTs) could replace the MOSFETs. IGBTs, however, do not have substrate diodes, so separate diodes would need to be coupled across the collector and emitter terminals of the IGBTs, resulting in a larger physical size and a greater power dissipation than associated with the MOSFETs. Nevertheless, IGBTs and diodes could replace the MOSFETS in  FIGS.  6  and  9   . 
     Although the foregoing disclosed subject matter has been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications may be practiced that are within the scope of the appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the subject matter disclosed herein is not to be limited to the details given herein, but may be modified within the scope and equivalents of any claims in this or a subsequent application.