Patent Publication Number: US-8983409-B2

Title: Auto configurable 2/3 wire serial interface

Description:
The present application is a continuation-in-part of U.S. patent application Ser. No. 13/090,663, filed Apr. 20, 2011, entitled “QUADRATURE POWER AMPLIFIER ARCHITECTURE,” which claims the benefit of U.S. Provisional Patent Application Ser. No. 61/325,859, filed Apr. 20, 2010; Ser. No. 61/325,659, filed Apr. 19, 2010; Ser. No. 61/359,487, filed Jun. 29, 2010; Ser. No. 61/370,554, filed Aug. 4, 2010; Ser. No. 61/380,522, filed Sep. 7, 2010; Ser. No. 61/410,071, filed Nov. 4, 2010; and Ser. No. 61/417,633, filed Nov. 29, 2010; the disclosures of which are hereby incorporated herein by reference in their entireties. Further, this application claims the benefits of U.S. Provisional Patent Application Ser. No. 61/359,487, filed Jun. 29, 2010; Ser. No. 61/370,554, filed Aug. 4, 2010; Ser. No. 61/380,522, filed Sep. 7, 2010; Ser. No. 61/410,071, filed Nov. 4, 2010; and Ser. No. 61/417,633, filed Nov. 29, 2010; the disclosures of which are hereby incorporated herein by reference in their entireties. 
    
    
     FIELD OF THE DISCLOSURE 
     Embodiments of the present disclosure relate to radio frequency (RF) power amplifier (PA) circuitry, which may be used in RF communications systems. 
     BACKGROUND OF THE DISCLOSURE 
     As wireless communications technologies evolve, wireless communications systems become increasingly sophisticated. As such, wireless communications protocols continue to expand and change to take advantage of the technological evolution. As a result, to maximize flexibility, many wireless communications devices must be capable of supporting any number of wireless communications protocols, including protocols that operate using different communications modes, such as a half-duplex mode or a full-duplex mode, and including protocols that operate using different frequency bands. Further, the different communications modes may include different types of RF modulation modes, each of which may have certain performance requirements, such as specific out-of-band emissions requirements or symbol differentiation requirements. In this regard, certain requirements may mandate operation in a linear mode. Other requirements may be less stringent that may allow operation in a non-linear mode to increase efficiency. Wireless communications devices that support such wireless communications protocols may be referred to as multi-mode multi-band communications devices. The linear mode relates to RF signals that include amplitude modulation (AM). The non-linear mode relates to RF signals that do not include AM. Since non-linear mode RF signals do not include AM, devices that amplify such signals may be allowed to operate in saturation. Devices that amplify linear mode RF signals may operate with some level of saturation, but must be able to retain AM characteristics sufficient for proper operation. 
     A half-duplex mode is a two-way mode of operation, in which a first transceiver communicates with a second transceiver; however, only one transceiver transmits at a time. Therefore, the transmitter and receiver in such a transceiver do not operate simultaneously. For example, certain telemetry systems operate in a send-then-wait-for-reply manner. Many time division duplex (TDD) systems, such as certain Global System for Mobile communications (GSM) systems, operate using the half-duplex mode. A full-duplex mode is a simultaneous two-way mode of operation, in which a first transceiver communicates with a second transceiver, and both transceivers may transmit simultaneously. Therefore, the transmitter and receiver in such a transceiver must be capable of operating simultaneously. In a full-duplex transceiver, signals from the transmitter should not overly interfere with signals received by the receiver; therefore, transmitted signals are at transmit frequencies that are different from received signals, which are at receive frequencies. Many frequency division duplex (FDD) systems, such as certain wideband code division multiple access (WCDMA) systems or certain long term evolution (LTE) systems, operate using a full-duplex mode. 
     As a result of the differences between full duplex operation and half duplex operation, RF front-end circuitry may need specific circuitry for each mode. Additionally, support of multiple frequency bands may require specific circuitry for each frequency band or for certain groupings of frequency bands.  FIG. 1  shows a traditional multi-mode multi-band communications device  10  according to the prior art. The traditional multi-mode multi-band communications device  10  includes a traditional multi-mode multi-band transceiver  12 , traditional multi-mode multi-band PA circuitry  14 , traditional multi-mode multi-band front-end aggregation circuitry  16 , and an antenna  18 . The traditional multi-mode multi-band PA circuitry  14  includes a first traditional PA  20 , a second traditional PA  22 , and up to and including an N TH  traditional PA  24 . 
     The traditional multi-mode multi-band transceiver  12  may select one of multiple communications modes, which may include a half-duplex transmit mode, a half-duplex receive mode, a full-duplex mode, a linear mode, a non-linear mode, multiple RF modulation modes, or any combination thereof. Further, the traditional multi-mode multi-band transceiver  12  may select one of multiple frequency bands. The traditional multi-mode multi-band transceiver  12  provides an aggregation control signal ACS to the traditional multi-mode multi-band front-end aggregation circuitry  16  based on the selected mode and the selected frequency band. The traditional multi-mode multi-band front-end aggregation circuitry  16  may include various RF components, including RF switches; RF filters, such as bandpass filters, harmonic filters, and duplexers; RF amplifiers, such as low noise amplifiers (LNAs); impedance matching circuitry; the like; or any combination thereof. In this regard, routing of RF receive signals and RF transmit signals through the RF components may be based on the selected mode and the selected frequency band as directed by the aggregation control signal ACS. 
     The first traditional PA  20  may receive and amplify a first traditional RF transmit signal FTTX from the traditional multi-mode multi-band transceiver  12  to provide a first traditional amplified RF transmit signal FTATX to the antenna  18  via the traditional multi-mode multi-band front-end aggregation circuitry  16 . The second traditional PA  22  may receive and amplify a second traditional RF transmit signal STTX from the traditional multi-mode multi-band transceiver  12  to provide a second traditional RF amplified transmit signal STATX to the antenna  18  via the traditional multi-mode multi-band front-end aggregation circuitry  16 . The N TH  traditional PA  24  may receive an amplify an N TH  traditional RF transmit signal NTTX from the traditional multi-mode multi-band transceiver  12  to provide an N TH  traditional RF amplified transmit signal NTATX to the antenna  18  via the traditional multi-mode multi-band front-end aggregation circuitry  16 . 
     The traditional multi-mode multi-band transceiver  12  may receive a first RF receive signal FRX, a second RF receive signal SRX, and up to and including an M TH  RF receive signal MRX from the antenna  18  via the traditional multi-mode multi-band front-end aggregation circuitry  16 . Each of the RF receive signals FRX, SRX, MRX may be associated with at least one selected mode, at least one selected frequency band, or both. Similarly, each of the traditional RF transmit signals FTTX, STTX, NTTX and corresponding traditional amplified RF transmit signals FTATX, STATX, NTATX may be associated with at least one selected mode, at least one selected frequency band, or both. 
     Portable wireless communications devices are typically battery powered, need to be relatively small, and have low cost. As such, to minimize size, cost, and power consumption, multi-mode multi-band RF circuitry in such a device needs to be as simple, small, and efficient as is practical. Thus, there is a need for multi-mode multi-band RF circuitry in a multi-mode multi-band communications device that is low cost, small, simple, efficient, and meets performance requirements. 
     SUMMARY OF THE EMBODIMENTS 
     The present disclosure relates to an automatically configurable 2-wire/3-wire serial communications interface (AC23SCI), which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, an SOS detection signal, which is indicative of the detection of the SOS, is provided to the sequence processing circuitry from the SOS detection circuitry. In this regard, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention. 
     Since some 2-wire serial communications buses have only the serial data signal and the serial clock signal, some type of special encoding of the serial data signal and the serial clock signal is used to represent the SOS. However, some 3-wire serial communications buses have a dedicated signal, such as the CS signal, to represent the SOS. As such, some 3-wire serial communications devices, such as test equipment, RF transceivers, baseband controllers, or the like, may not be able to provide the special encoding to represent the SOS, thereby mandating use of the CS signal. As a result, the first AC23SCI must be capable of detecting the SOS based on either the CS signal or the special encoding. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  shows a traditional multi-mode multi-band communications device according to the prior art. 
         FIG. 2  shows an RF communications system according to one embodiment of the RF communications system. 
         FIG. 3  shows the RF communications system according to an alternate embodiment of the RF communications system. 
         FIG. 4  shows the RF communications system according to an additional embodiment of the RF communications system. 
         FIG. 5  shows the RF communications system according to another embodiment of the RF communications system. 
         FIG. 6  shows the RF communications system according to a further embodiment of the RF communications system. 
         FIG. 7  shows the RF communications system according to one embodiment of the RF communications system. 
         FIG. 8  shows details of RF power amplifier (PA) circuitry illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry. 
         FIG. 9  shows details of the RF PA circuitry illustrated in  FIG. 5  according to an alternate embodiment of the RF PA circuitry. 
         FIG. 10  shows the RF communications system according to one embodiment of the RF communications system. 
         FIG. 11  shows the RF communications system according to an alternate embodiment of the RF communications system. 
         FIG. 12  shows details of a direct current (DC)-DC converter illustrated in  FIG. 11  according to an alternate embodiment of the DC-DC converter. 
         FIG. 13  shows details of the RF PA circuitry illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry. 
         FIG. 14  shows details of the RF PA circuitry illustrated in  FIG. 6  according to an alternate embodiment of the RF PA circuitry. 
         FIG. 15  shows details of a first RF PA and a second RF PA illustrated in  FIG. 14  according to one embodiment of the first RF PA and the second RF PA. 
         FIG. 16  shows details of a first non-quadrature PA path and a second non-quadrature PA path illustrated in  FIG. 15  according to one embodiment of the first non-quadrature PA path and the second non-quadrature PA path. 
         FIG. 17  shows details of a first quadrature PA path and a second quadrature PA path illustrated in  FIG. 15  according to one embodiment of the first quadrature PA path and the second quadrature PA path. 
         FIG. 18  shows details of a first in-phase amplification path, a first quadrature-phase amplification path, a second in-phase amplification path, and a second quadrature-phase amplification path illustrated in  FIG. 17  according to one embodiment of the first in-phase amplification path, the first quadrature-phase amplification path, the second in-phase amplification path, and the second quadrature-phase amplification path. 
         FIG. 19  shows details of the first quadrature PA path and the second quadrature PA path illustrated in  FIG. 15  according to an alternate embodiment of the first quadrature PA path and the second quadrature PA path. 
         FIG. 20  shows details of the first in-phase amplification path, the first quadrature-phase amplification path, the second in-phase amplification path, and the second quadrature-phase amplification path illustrated in  FIG. 19  according to an alternate embodiment of the first in-phase amplification path, the first quadrature-phase amplification path, the second in-phase amplification path, and the second quadrature-phase amplification path. 
         FIG. 21  shows details of the first RF PA and the second RF PA illustrated in  FIG. 14  according an alternate embodiment of the first RF PA and the second RF PA. 
         FIG. 22  shows details of the first non-quadrature PA path, the first quadrature PA path, and the second quadrature PA path illustrated in  FIG. 21  according to an additional embodiment of the first non-quadrature PA path, the first quadrature PA path, and the second quadrature PA path. 
         FIG. 23  shows details of a first feeder PA stage and a first quadrature RF splitter illustrated in  FIG. 16  and  FIG. 17 , respectively, according to one embodiment of the first feeder PA stage and the first quadrature RF splitter. 
         FIG. 24  shows details of the first feeder PA stage and the first quadrature RF splitter illustrated in  FIG. 16  and  FIG. 17 , respectively, according to an alternate embodiment of the first feeder PA stage and the first quadrature RF splitter. 
         FIG. 25  is a graph illustrating output characteristics of a first output transistor element illustrated in  FIG. 24  according to one embodiment of the first output transistor element. 
         FIG. 26  illustrates a process for matching an input impedance to a quadrature RF splitter to a target load line of a feeder PA stage. 
         FIG. 27  shows details of the first RF PA illustrated in  FIG. 14  according an alternate embodiment of the first RF PA. 
         FIG. 28  shows details of the second RF PA illustrated in  FIG. 14  according an alternate embodiment of the second RF PA. 
         FIG. 29  shows details of a first in-phase amplification path, a first quadrature-phase amplification path, and a first quadrature RF combiner illustrated in  FIG. 22  according to one embodiment of the first in-phase amplification path, the first quadrature-phase amplification path, and the first quadrature RF combiner. 
         FIG. 30  shows details of a first feeder PA stage, a first quadrature RF splitter, a first in-phase final PA impedance matching circuit, a first in-phase final PA stage, a first quadrature-phase final PA impedance matching circuit, and a first quadrature-phase final PA stage illustrated in  FIG. 29  according to one embodiment of the first feeder PA stage, the first quadrature RF splitter, the first in-phase final PA impedance matching circuit, the first in-phase final PA stage, the first quadrature-phase final PA impedance matching circuit, and the first quadrature-phase final PA stage. 
         FIG. 31  shows details of the first feeder PA stage, the first quadrature RF splitter, the first in-phase final PA impedance matching circuit, the first in-phase final PA stage, the first quadrature-phase final PA impedance matching circuit, and the first quadrature-phase final PA stage illustrated in  FIG. 29  according to an alternate embodiment of the first feeder PA stage, the first quadrature RF splitter, the first in-phase final PA impedance matching circuit, the first in-phase final PA stage, the first quadrature-phase final PA impedance matching circuit, and the first quadrature-phase final PA stage. 
         FIG. 32  shows details of first phase-shifting circuitry and a first Wilkinson RF combiner illustrated in  FIG. 29  according to one embodiment of the first phase-shifting circuitry and the first Wilkinson RF combiner. 
         FIG. 33  shows details of the second non-quadrature PA path illustrated in  FIG. 16  and details of the second quadrature PA path illustrated in  FIG. 18  according to one embodiment of the second non-quadrature PA path and the second quadrature PA path. 
         FIG. 34  shows details of a second feeder PA stage, a second quadrature RF splitter, a second in-phase final PA impedance matching circuit, a second in-phase final PA stage, a second quadrature-phase final PA impedance matching circuit, and a second quadrature-phase final PA stage illustrated in  FIG. 33  according to one embodiment of the second feeder PA stage, the second quadrature RF splitter, the second in-phase final PA impedance matching circuit, the second in-phase final PA stage, the second quadrature-phase final PA impedance matching circuit, and the second quadrature-phase final PA stage. 
         FIG. 35  shows details of second phase-shifting circuitry and a second Wilkinson RF combiner illustrated in  FIG. 33  according to one embodiment of the second phase-shifting circuitry and the second Wilkinson RF combiner. 
         FIG. 36  shows details of a first PA semiconductor die illustrated in  FIG. 30  according to one embodiment of the first PA semiconductor die. 
         FIG. 37  shows details of the RF PA circuitry illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry. 
         FIG. 38  shows details of the RF PA circuitry illustrated in  FIG. 5  according to an alternate embodiment of the RF PA circuitry. 
         FIG. 39  shows details of the RF PA circuitry illustrated in  FIG. 5  according to an additional embodiment of the RF PA circuitry. 
         FIG. 40  shows details of the first RF PA, the second RF PA, and PA bias circuitry illustrated in  FIG. 13  according to one embodiment of the first RF PA, the second RF PA, and the PA bias circuitry. 
         FIG. 41  shows details of driver stage current digital-to-analog converter (IDAC) circuitry and final stage IDAC circuitry illustrated in  FIG. 40  according to one embodiment of the driver stage IDAC circuitry and the final stage IDAC circuitry. 
         FIG. 42  shows details of driver stage current reference circuitry and final stage current reference circuitry illustrated in  FIG. 41  according to one embodiment of the driver stage current reference circuitry and the final stage current reference circuitry. 
         FIG. 43  shows the RF communications system according to one embodiment of the RF communications system. 
         FIG. 44  shows details of a PA envelope power supply and a PA bias power supply illustrated in  FIG. 43  according to one embodiment of the PA envelope power supply and the PA bias power supply. 
         FIG. 45  shows details of the PA envelope power supply and the PA bias power supply illustrated in  FIG. 43  according to an alternate embodiment of the PA envelope power supply and the PA bias power supply. 
         FIG. 46  shows details of the PA envelope power supply and the PA bias power supply illustrated in  FIG. 43  according to an additional embodiment of the PA envelope power supply and the PA bias power supply. 
         FIG. 47  shows a first automatically configurable 2-wire/3-wire serial communications interface (AC23SCI) according to one embodiment of the first AC23SCI. 
         FIG. 48  shows the first AC23SCI according an alternate embodiment of the first AC23SCI. 
         FIG. 49  shows details of SOS detection circuitry illustrated in  FIG. 47  according to one embodiment of the SOS detection circuitry. 
         FIGS. 50A ,  50 B,  50 C, and  50 D are graphs illustrating the chip select signal, the SOS detection signal, the serial clock signal, and the serial data signal, respectively, of the first AC23SCI illustrated in  FIG. 49  according to one embodiment of the first AC23SCI. 
         FIGS. 51A ,  51 B,  51 C, and  51 D are graphs illustrating the chip select signal, the SOS detection signal, the serial clock signal, and the serial data signal, respectively, of the first AC23SCI illustrated in  FIG. 49  according to an alternate embodiment of the first AC23SCI. 
         FIGS. 52A ,  52 B,  52 C, and  52 D are graphs illustrating the chip select signal, the SOS detection signal, the serial clock signal, and the serial data signal, respectively, of the first AC23SCI illustrated in  FIG. 49  according to an additional embodiment of the first AC23SCI. 
         FIG. 53  shows the RF communications system according to one embodiment of the RF communications system. 
         FIG. 54  shows details of the RF PA circuitry illustrated in  FIG. 6  according to an additional embodiment of the RF PA circuitry. 
         FIG. 55  shows details of multi-mode multi-band RF power amplification circuitry illustrated in  FIG. 54  according to one embodiment of the multi-mode multi-band RF power amplification circuitry. 
         FIGS. 56A and 56B  show details of the PA control circuitry illustrated in  FIG. 55  according to one embodiment of the PA control circuitry. 
         FIG. 57  shows details of the RF PA circuitry illustrated in  FIG. 6  according to another embodiment of the RF PA circuitry. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the disclosure and illustrate the best mode of practicing the disclosure. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
       FIG. 2  shows an RF communications system  26  according to one embodiment of the RF communications system  26 . The RF communications system  26  includes RF modulation and control circuitry  28 , RF PA circuitry  30 , and a DC-DC converter  32 . The RF modulation and control circuitry  28  provides an envelope control signal ECS to the DC-DC converter  32  and provides an RF input signal RFI to the RF PA circuitry  30 . The DC-DC converter  32  provides a bias power supply signal BPS and an envelope power supply signal EPS to the RF PA circuitry  30 . The envelope power supply signal EPS may be based on the envelope control signal ECS. As such, a magnitude of the envelope power supply signal EPS may be controlled by the RF modulation and control circuitry  28  via the envelope control signal ECS. The RF PA circuitry  30  may receive and amplify the RF input signal RFI to provide an RF output signal RFO. The envelope power supply signal EPS may provide power for amplification of the RF input signal RFI to the RF PA circuitry  30 . The RF PA circuitry  30  may use the bias power supply signal BPS to provide biasing of amplifying elements in the RF PA circuitry  30 . 
     In a first embodiment of the RF communications system  26 , the RF communications system  26  is a multi-mode RF communications system  26 . As such, the RF communications system  26  may operate using multiple communications modes. In this regard, the RF modulation and control circuitry  28  may be multi-mode RF modulation and control circuitry  28  and the RF PA circuitry  30  may be multi-mode RF PA circuitry  30 . In a second embodiment of the RF communications system  26 , the RF communications system  26  is a multi-band RF communications system  26 . As such, the RF communications system  26  may operate using multiple RF communications bands. In this regard, the RF modulation and control circuitry  28  may be multi-band RF modulation and control circuitry  28  and the RF PA circuitry  30  may be multi-band RF PA circuitry  30 . In a third embodiment of the RF communications system  26 , the RF communications system  26  is a multi-mode multi-band RF communications system  26 . As such, the RF communications system  26  may operate using multiple communications modes, multiple RF communications bands, or both. In this regard, the RF modulation and control circuitry  28  may be multi-mode multi-band RF modulation and control circuitry  28  and the RF PA circuitry  30  may be multi-mode multi-band RF PA circuitry  30 . 
     The communications modes may be associated with any number of different communications protocols, such as Global System of Mobile communications (GSM), Gaussian Minimum Shift Keying (GMSK), IS-136, Enhanced Data rates for GSM Evolution (EDGE), Code Division Multiple Access (CDMA), Universal Mobile Telecommunications System (UMTS) protocols, such as Wideband CDMA (WCDMA), Worldwide Interoperability for Microwave Access (WIMAX), Long Term Evolution (LTE), or the like. The GSM, GMSK, and IS-136 protocols typically do not include amplitude modulation (AM). As such, the GSM, GMSK, and IS-136 protocols may be associated with a non-linear mode. Further, the GSM, GMSK, and IS-136 protocols may be associated with a saturated mode. The EDGE, CDMA, UMTS, WCDMA, WIMAX, and LTE protocols may include AM. As such, the EDGE, CDMA, UMTS, WCDMA, WIMAX, and LTE protocols may be associated with a linear mode. 
     In one embodiment of the RF communications system  26 , the RF communications system  26  is a mobile communications terminal, such as a cell phone, smartphone, laptop computer, tablet computer, personal digital assistant (PDA), or the like. In an alternate embodiment of the RF communications system  26 , the RF communications system  26  is a fixed communications terminal, such as a base station, a cellular base station, a wireless router, a hotspot distribution node, a wireless access point, or the like. The antenna  18  may include any apparatus for conveying RF transmit and RF receive signals to and from at least one other RF communications system. As such, in one embodiment of the antenna  18 , the antenna  18  is a single antenna. In an alternate embodiment of the antenna  18 , the antenna  18  is an antenna array having multiple radiating and receiving elements. In an additional embodiment of the antenna  18 , the antenna  18  is a distribution system for transmitting and receiving RF signals. 
       FIG. 3  shows the RF communications system  26  according to an alternate embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 3  is similar to the RF communications system  26  illustrated in  FIG. 2 , except in the RF communications system  26  illustrated in  FIG. 3 , the RF modulation and control circuitry  28  provides a first RF input signal FRFI, a second RF input signal SRFI, and a PA configuration control signal PCC to the RF PA circuitry  30 . The RF PA circuitry  30  may receive and amplify the first RF input signal FRFI to provide a first RF output signal FRFO. The envelope power supply signal EPS may provide power for amplification of the first RF input signal FRFI to the RF PA circuitry  30 . The RF PA circuitry  30  may receive and amplify the second RF input signal SRFI to provide a second RF output signal SRFO. The envelope power supply signal EPS may provide power for amplification of the second RF output signal SRFO to the RF PA circuitry  30 . Certain configurations of the RF PA circuitry  30  may be based on the PA configuration control signal PCC. As a result, the RF modulation and control circuitry  28  may control such configurations of the RF PA circuitry  30 . 
       FIG. 4  shows the RF communications system  26  according to an additional embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 4  is similar to the RF communications system  26  illustrated in  FIG. 3 , except in the RF communications system  26  illustrated in  FIG. 4 , the RF PA circuitry  30  does not provide the first RF output signal FRFO and the second RF output signal SRFO. Instead, the RF PA circuitry  30  may provide one of a first alpha RF transmit signal FATX, a second alpha RF transmit signal SATX, and up to and including a P TH  alpha RF transmit signal PATX based on receiving and amplifying the first RF input signal FRFI. Similarly, the RF PA circuitry  30  may provide one of a first beta RF transmit signal FBTX, a second beta RF transmit signal SBTX, and up to and including a Q TH  beta RF transmit signal QBTX based on receiving and amplifying the second RF input signal SRFI. The one of the transmit signals FATX, SATX, PATX, FBTX, SBTX, QBTX that is selected may be based on the PA configuration control signal PCC. Additionally, the RF modulation and control circuitry  28  may provide a DC configuration control signal DCC to the DC-DC converter  32 . Certain configurations of the DC-DC converter  32  may be based on the DC configuration control signal DCC. 
       FIG. 5  shows the RF communications system  26  according to another embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 5  shows details of the RF modulation and control circuitry  28  and the RF PA circuitry  30  illustrated in  FIG. 4 . Additionally, the RF communications system  26  illustrated in  FIG. 5  further includes transceiver circuitry  34 , front-end aggregation circuitry  36 , and the antenna  18 . The transceiver circuitry  34  includes down-conversion circuitry  38 , baseband processing circuitry  40 , and the RF modulation and control circuitry  28 , which includes control circuitry  42  and RF modulation circuitry  44 . The RF PA circuitry  30  includes a first transmit path  46  and a second transmit path  48 . The first transmit path  46  includes a first RF PA  50  and alpha switching circuitry  52 . The second transmit path  48  includes a second RF PA  54  and beta switching circuitry  56 . The front-end aggregation circuitry  36  is coupled to the antenna  18 . The control circuitry  42  provides the aggregation control signal ACS to the front-end aggregation circuitry  36 . Configuration of the front-end aggregation circuitry  36  may be based on the aggregation control signal ACS. As such, configuration of the front-end aggregation circuitry  36  may be controlled by the control circuitry  42  via the aggregation control signal ACS. 
     The control circuitry  42  provides the envelope control signal ECS and the DC configuration control signal DCC to the DC-DC converter  32 . Further, the control circuitry  42  provides the PA configuration control signal PCC to the RF PA circuitry  30 . As such, the control circuitry  42  may control configuration of the RF PA circuitry  30  via the PA configuration control signal PCC and may control a magnitude of the envelope power supply signal EPS via the envelope control signal ECS. The control circuitry  42  may select one of multiple communications modes, which may include a first half-duplex transmit mode, a first half-duplex receive mode, a second half-duplex transmit mode, a second half-duplex receive mode, a first full-duplex mode, a second full-duplex mode, at least one linear mode, at least one non-linear mode, multiple RF modulation modes, or any combination thereof. Further, the control circuitry  42  may select one of multiple frequency bands. The control circuitry  42  may provide the aggregation control signal ACS to the front-end aggregation circuitry  36  based on the selected mode and the selected frequency band. The front-end aggregation circuitry  36  may include various RF components, including RF switches; RF filters, such as bandpass filters, harmonic filters, and duplexers; RF amplifiers, such as low noise amplifiers (LNAs); impedance matching circuitry; the like; or any combination thereof. In this regard, routing of RF receive signals and RF transmit signals through the RF components may be based on the selected mode and the selected frequency band as directed by the aggregation control signal ACS. 
     The down-conversion circuitry  38  may receive the first RF receive signal FRX, the second RF receive signal SRX, and up to and including the M TH  RF receive signal MRX from the antenna  18  via the front-end aggregation circuitry  36 . Each of the RF receive signals FRX, SRX, MRX may be associated with at least one selected mode, at least one selected frequency band, or both. The down-conversion circuitry  38  may down-convert any of the RF receive signals FRX, SRX, MRX to baseband receive signals, which may be forwarded to the baseband processing circuitry  40  for processing. The baseband processing circuitry  40  may provide baseband transmit signals to the RF modulation circuitry  44 , which may RF modulate the baseband transmit signals to provide the first RF input signal FRFI or the second RF input signal SRFI to the first RF PA  50  or the second RF PA  54 , respectively, depending on the selected communications mode. 
     The first RF PA  50  may receive and amplify the first RF input signal FRFI to provide the first RF output signal FRFO to the alpha switching circuitry  52 . Similarly, the second RF PA  54  may receive and amplify the second RF input signal SRFI to provide the second RF output signal SRFO to the beta switching circuitry  56 . The first RF PA  50  and the second RF PA  54  may receive the envelope power supply signal EPS, which may provide power for amplification of the first RF input signal FRFI and the second RF input signal SRFI, respectively. The alpha switching circuitry  52  may forward the first RF output signal FRFO to provide one of the alpha transmit signals FATX, SATX, PATX to the antenna  18  via the front-end aggregation circuitry  36 , depending on the selected communications mode based on the PA configuration control signal PCC. Similarly, the beta switching circuitry  56  may forward the second RF output signal SRFO to provide one of the beta transmit signals FBTX, SBTX, QBTX to the antenna  18  via the front-end aggregation circuitry  36 , depending on the selected communications mode based on the PA configuration control signal PCC. 
       FIG. 6  shows the RF communications system  26  according to a further embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 6  is similar to the RF communications system  26  illustrated in  FIG. 5 , except in the RF communications system  26  illustrated in  FIG. 6 , the transceiver circuitry  34  includes a control circuitry digital communications interface (DCI)  58 , the RF PA circuitry  30  includes a PA-DCI  60 , the DC-DC converter  32  includes a DC-DC converter DCI  62 , and the front-end aggregation circuitry  36  includes an aggregation circuitry DCI  64 . The front-end aggregation circuitry  36  includes an antenna port AP, which is coupled to the antenna  18 . In one embodiment of the RF communications system  26 , the antenna port AP is directly coupled to the antenna  18 . In one embodiment of the RF communications system  26 , the front-end aggregation circuitry  36  is coupled between the alpha switching circuitry  52  and the antenna port AP. Further, the front-end aggregation circuitry  36  is coupled between the beta switching circuitry  56  and the antenna port AP. The alpha switching circuitry  52  may be multi-mode multi-band alpha switching circuitry and the beta switching circuitry  56  may be multi-mode multi-band beta switching circuitry. 
     The DCIs  58 ,  60 ,  62 ,  64  are coupled to one another using a digital communications bus  66 . In the digital communications bus  66  illustrated in  FIG. 6 , the digital communications bus  66  is a uni-directional bus in which the control circuitry DCI  58  may communicate information to the PA-DCI  60 , the DC-DC converter DCI  62 , the aggregation circuitry DCI  64 , or any combination thereof. As such, the control circuitry  42  may provide the envelope control signal ECS and the DC configuration control signal DCC via the control circuitry DCI  58  to the DC-DC converter  32  via the DC-DC converter DCI  62 . Similarly, the control circuitry  42  may provide the aggregation control signal ACS via the control circuitry DCI  58  to the front-end aggregation circuitry  36  via the aggregation circuitry DCI  64 . Additionally, the control circuitry  42  may provide the PA configuration control signal PCC via the control circuitry DCI  58  to the RF PA circuitry  30  via the PA-DCI  60 . 
       FIG. 7  shows the RF communications system  26  according to one embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 7  is similar to the RF communications system  26  illustrated in  FIG. 6 , except in the RF communications system  26  illustrated in  FIG. 7 , the digital communications bus  66  is a bi-directional bus and each of the DCIs  58 ,  60 ,  62 ,  64  is capable of receiving or transmitting information. In alternate embodiments of the RF communications system  26 , any or all of the DCIs  58 ,  60 ,  62 ,  64  may be uni-directional and any or all of the DCIs  58 ,  60 ,  62 ,  64  may be bi-directional. 
       FIG. 8  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry  30 . Specifically,  FIG. 8  shows details of the alpha switching circuitry  52  and the beta switching circuitry  56  according to one embodiment of the alpha switching circuitry  52  and the beta switching circuitry  56 . The alpha switching circuitry  52  includes an alpha RF switch  68  and a first alpha harmonic filter  70 . The beta switching circuitry  56  includes a beta RF switch  72  and a first beta harmonic filter  74 . Configuration of the alpha RF switch  68  and the beta RF switch  72  may be based on the PA configuration control signal PCC. In one communications mode, such as an alpha half-duplex transmit mode, an alpha saturated mode, or an alpha non-linear mode, the alpha RF switch  68  is configured to forward the first RF output signal FRFO to provide the first alpha RF transmit signal FATX via the first alpha harmonic filter  70 . In another communications mode, such as an alpha full-duplex mode or an alpha linear mode, the alpha RF switch  68  is configured to forward the first RF output signal FRFO to provide any of the second alpha RF transmit signal SATX through the P TH  alpha RF transmit signal PATX. When a specific RF band is selected, the alpha RF switch  68  may be configured to provide a corresponding selected one of the second alpha RF transmit signal SATX through the P TH  alpha RF transmit signal PATX. 
     In one communications mode, such as a beta half-duplex transmit mode, a beta saturated mode, or a beta non-linear mode, the beta RF switch  72  is configured to forward the second RF output signal SRFO to provide the first beta RF transmit signal FBTX via the first beta harmonic filter  74 . In another communications mode, such as a beta full-duplex mode or a beta linear mode, the beta RF switch  72  is configured to forward the second RF output signal SRFO to provide any of the second beta RF transmit signal SBTX through the Q TH  beta RF transmit signal QBTX. When a specific RF band is selected, beta RF switch  72  may be configured to provide a corresponding selected one of the second beta RF transmit signal SBTX through the Q TH  beta RF transmit signal QBTX. The first alpha harmonic filter  70  may be used to filter out harmonics of an RF carrier in the first RF output signal FRFO. The first beta harmonic filter  74  may be used to filter out harmonics of an RF carrier in the second RF output signal SRFO. 
       FIG. 9  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to an alternate embodiment of the RF PA circuitry  30 . Specifically,  FIG. 9  shows details of the alpha switching circuitry  52  and the beta switching circuitry  56  according to an alternate embodiment of the alpha switching circuitry  52  and the beta switching circuitry  56 . The alpha switching circuitry  52  includes the alpha RF switch  68 , the first alpha harmonic filter  70 , and a second alpha harmonic filter  76 . The beta switching circuitry  56  includes the beta RF switch  72 , the first beta harmonic filter  74 , and a second beta harmonic filter  78 . Configuration of the alpha RF switch  68  and the beta RF switch  72  may be based on the PA configuration control signal PCC. In one communications mode, such as a first alpha half-duplex transmit mode, a first alpha saturated mode, or a first alpha non-linear mode, the alpha RF switch  68  is configured to forward the first RF output signal FRFO to provide the first alpha RF transmit signal FATX via the first alpha harmonic filter  70 . In another communications mode, such as a second alpha half-duplex transmit mode, a second alpha saturated mode, or a second alpha non-linear mode, the alpha RF switch  68  is configured to forward the first RF output signal FRFO to provide the second alpha RF transmit signal SATX via the second alpha harmonic filter  76 . In an alternate communications mode, such as an alpha full-duplex mode or an alpha linear mode, the alpha RF switch  68  is configured to forward the first RF output signal FRFO to provide any of a third alpha RF transmit signal TATX through the P TH  alpha RF transmit signal PATX. When a specific RF band is selected, the alpha RF switch  68  may be configured to provide a corresponding selected one of the third alpha RF transmit signal TATX through the P TH  alpha RF transmit signal PATX. 
     In one communications mode, such as a first beta half-duplex transmit mode, a first beta saturated mode, or a first beta non-linear mode, the beta RF switch  72  is configured to forward the second RF output signal SRFO to provide the first beta RF transmit signal FBTX via the first beta harmonic filter  74 . In another communications mode, such as a second beta half-duplex transmit mode, a second beta saturated mode, or a second beta non-linear mode, the beta RF switch  72  is configured to forward the second RF output signal SRFO to provide the second beta RF transmit signal SBTX via the second beta harmonic filter  78 . In an alternate communications mode, such as a beta full-duplex mode or a beta linear mode, the beta RF switch  72  is configured to forward the second RF output signal SRFO to provide any of a third beta RF transmit signal TBTX through the Q TH  beta RF transmit signal QBTX. When a specific RF band is selected, the beta RF switch  72  may be configured to provide a corresponding selected one of the third beta RF transmit signal TBTX through the Q TH  beta RF transmit signal QBTX. The first alpha harmonic filter  70  or the second alpha harmonic filter  76  may be used to filter out harmonics of an RF carrier in the first RF output signal FRFO. The first beta harmonic filter  74  or the second beta harmonic filter  78  may be used to filter out harmonics of an RF carrier in the second RF output signal SRFO. 
       FIG. 10  shows the RF communications system  26  according to one embodiment of the RF communications system  26 . The RF communications system  26  shown in  FIG. 10  is similar to the RF communications system  26  shown in  FIG. 4 , except the RF communications system  26  illustrated in  FIG. 10  further includes a DC power supply  80  and the DC configuration control signal DCC is omitted. Additionally, details of the DC-DC converter  32  are shown according to one embodiment of the DC-DC converter  32 . The DC-DC converter  32  includes first power filtering circuitry  82 , a charge pump buck converter  84 , a buck converter  86 , second power filtering circuitry  88 , a first inductive element L 1 , and a second inductive element L 2 . The DC power supply  80  provides a DC power supply signal DCPS to the charge pump buck converter  84 , the buck converter  86 , and the second power filtering circuitry  88 . In one embodiment of the DC power supply  80 , the DC power supply  80  is a battery. 
     The second power filtering circuitry  88  is coupled to the RF PA circuitry  30  and to the DC power supply  80 . The charge pump buck converter  84  is coupled to the DC power supply  80 . The first inductive element L 1  is coupled between the charge pump buck converter  84  and the first power filtering circuitry  82 . The buck converter  86  is coupled to the DC power supply  80 . The second inductive element L 2  is coupled between the buck converter  86  and the first power filtering circuitry  82 . The first power filtering circuitry  82  is coupled to the RF PA circuitry  30 . One end of the first inductive element L 1  is coupled to one end of the second inductive element L 2  at the first power filtering circuitry  82 . 
     In one embodiment of the DC-DC converter  32 , the DC-DC converter  32  operates in one of multiple converter operating modes, which include a first converter operating mode, a second converter operating mode, and a third converter operating mode. In an alternate embodiment of the DC-DC converter  32 , the DC-DC converter  32  operates in one of the first converter operating mode and the second converter operating mode. In the first converter operating mode, the charge pump buck converter  84  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the charge pump buck converter  84 , and the first inductive element L 1 . In the first converter operating mode, the buck converter  86  is inactive and does not contribute to the envelope power supply signal EPS. In the second converter operating mode, the buck converter  86  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the buck converter  86  and the second inductive element L 2 . In the second converter operating mode, the charge pump buck converter  84  is inactive, such that the charge pump buck converter  84  does not contribute to the envelope power supply signal EPS. In the third converter operating mode, the charge pump buck converter  84  and the buck converter  86  are active, such that either the charge pump buck converter  84 ; the buck converter  86 ; or both may contribute to the envelope power supply signal EPS. As such, in the third converter operating mode, the envelope power supply signal EPS is based on the DC power supply signal DCPS either via the charge pump buck converter  84 , and the first inductive element L 1 ; via the buck converter  86  and the second inductive element L 2 ; or both. 
     The second power filtering circuitry  88  filters the DC power supply signal DCPS to provide the bias power supply signal BPS. The second power filtering circuitry  88  may function as a lowpass filter by removing ripple, noise, and the like from the DC power supply signal DCPS to provide the bias power supply signal BPS. As such, in one embodiment of the DC-DC converter  32 , the bias power supply signal BPS is based on the DC power supply signal DCPS. 
     In the first converter operating mode or the third converter operating mode, the charge pump buck converter  84  may receive, charge pump, and buck convert the DC power supply signal DCPS to provide a first buck output signal FBO to the first inductive element L 1 . As such, in one embodiment of the charge pump buck converter  84 , the first buck output signal FBO is based on the DC power supply signal DCPS. Further, the first inductive element L 1  may function as a first energy transfer element of the charge pump buck converter  84  to transfer energy via the first buck output signal FBO to the first power filtering circuitry  82 . In the first converter operating mode or the third converter operating mode, the first inductive element L 1  and the first power filtering circuitry  82  may receive and filter the first buck output signal FBO to provide the envelope power supply signal EPS. The charge pump buck converter  84  may regulate the envelope power supply signal EPS by controlling the first buck output signal FBO based on a setpoint of the envelope power supply signal EPS provided by the envelope control signal ECS. 
     In the second converter operating mode or the third converter operating mode, the buck converter  86  may receive and buck convert the DC power supply signal DCPS to provide a second buck output signal SBO to the second inductive element L 2 . As such, in one embodiment of the buck converter  86 , the second buck output signal SBO is based on the DC power supply signal DCPS. Further, the second inductive element L 2  may function as a second energy transfer element of the buck converter  86  to transfer energy via the first power filtering circuitry  82  to the first power filtering circuitry  82 . In the second converter operating mode or the third converter operating mode, the second inductive element L 2  and the first power filtering circuitry  82  may receive and filter the second buck output signal SBO to provide the envelope power supply signal EPS. The buck converter  86  may regulate the envelope power supply signal EPS by controlling the second buck output signal SBO based on a setpoint of the envelope power supply signal EPS provided by the envelope control signal ECS. 
     In one embodiment of the charge pump buck converter  84 , the charge pump buck converter  84  operates in one of multiple pump buck operating modes. During a pump buck pump-up operating mode of the charge pump buck converter  84 , the charge pump buck converter  84  pumps-up the DC power supply signal DCPS to provide an internal signal (not shown), such that a voltage of the internal signal is greater than a voltage of the DC power supply signal DCPS. In an alternate embodiment of the charge pump buck converter  84 , during the pump buck pump-up operating mode, a voltage of the envelope power supply signal EPS is greater than the voltage of the DC power supply signal DCPS. During a pump buck pump-down operating mode of the charge pump buck converter  84 , the charge pump buck converter  84  pumps-down the DC power supply signal DCPS to provide the internal signal, such that a voltage of the internal signal is less than a voltage of the DC power supply signal DCPS. In an alternate embodiment of the charge pump buck converter  84 , during the pump buck pump-down operating mode, the voltage of the envelope power supply signal EPS is less than the voltage of the DC power supply signal DCPS. During a pump buck pump-even operating mode of the charge pump buck converter  84 , the charge pump buck converter  84  pumps the DC power supply signal DCPS to the internal signal, such that a voltage of the internal signal is about equal to a voltage of the DC power supply signal DCPS. One embodiment of the DC-DC converter  32  includes a pump buck bypass operating mode of the charge pump buck converter  84 , such that during the pump buck bypass operating mode, the charge pump buck converter  84  by-passes charge pump circuitry (not shown) using by-pass circuitry (not shown) to forward the DC power supply signal DCPS to provide the internal signal, such that a voltage of the internal is about equal to a voltage of the DC power supply signal DCPS. 
     In one embodiment of the charge pump buck converter  84 , the pump buck operating modes include the pump buck pump-up operating mode, the pump buck pump-down operating mode, the pump buck pump-even operating mode, and the pump buck bypass operating mode. In an alternate embodiment of the charge pump buck converter  84 , the pump buck pump-even operating mode is omitted. In an additional embodiment of the charge pump buck converter  84 , the pump buck bypass operating mode is omitted. In another embodiment of the charge pump buck converter  84 , the pump buck pump-down operating mode is omitted. In a further embodiment of the charge pump buck converter  84 , any or all of the pump buck pump-up operating mode, the pump buck pump-down operating mode, the pump buck pump-even operating mode, and the pump buck bypass operating mode are omitted. In a supplemental embodiment of the charge pump buck converter  84 , the charge pump buck converter  84  operates in only the pump buck pump-up operating mode. In an additional embodiment of the charge pump buck converter  84 , the charge pump buck converter  84  operates in one of the pump buck pump-up operating mode and at least one other pump buck operating mode of the charge pump buck converter  84 . The at least one other pump buck operating mode of the charge pump buck converter  84  may include any or all of the pump buck pump-up operating mode, the pump buck pump-down operating mode, the pump buck pump-even operating mode, and the pump buck bypass operating mode. 
       FIG. 11  shows the RF communications system  26  according to an alternate embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 11  is similar to the RF communications system  26  illustrated in  FIG. 10 , except in the RF communications system  26  illustrated in  FIG. 11 , the DC-DC converter  32  further includes DC-DC control circuitry  90  and a charge pump  92 , and omits the second inductive element L 2 . Instead of the second power filtering circuitry  88  being coupled to the DC power supply  80  as shown in  FIG. 10 , the charge pump  92  is coupled to the DC power supply  80 , such that the charge pump  92  is coupled between the DC power supply  80  and the second power filtering circuitry  88 . Additionally, the RF modulation and control circuitry  28  provides the DC configuration control signal DCC and the envelope control signal ECS to the DC-DC control circuitry  90 . 
     The DC-DC control circuitry  90  provides a charge pump buck control signal CPBS to the charge pump buck converter  84 , provides a buck control signal BCS to the buck converter  86 , and provides a charge pump control signal CPS to the charge pump  92 . The charge pump buck control signal CPBS, the buck control signal BCS, or both may indicate which converter operating mode is selected. Further, the charge pump buck control signal CPBS, the buck control signal BCS, or both may provide the setpoint of the envelope power supply signal EPS as provided by the envelope control signal ECS. The charge pump buck control signal CPBS may indicate which pump buck operating mode is selected. 
     In one embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the DC-DC control circuitry  90 . In an alternate embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the RF modulation and control circuitry  28  and may be communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In an additional embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the control circuitry  42  ( FIG. 5 ) and may be communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In general, selection of the converter operating mode is made by control circuitry, which may be any of the DC-DC control circuitry  90 , the RF modulation and control circuitry  28 , and the control circuitry  42  ( FIG. 5 ). 
     In one embodiment of the DC-DC converter  32 , selection of the pump buck operating mode is made by the DC-DC control circuitry  90 . In an alternate embodiment of the DC-DC converter  32 , selection of the pump buck operating mode is made by the RF modulation and control circuitry  28  and communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In an additional embodiment of the DC-DC converter  32 , selection of the pump buck operating mode is made by the control circuitry  42  ( FIG. 5 ) and communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In general, selection of the pump buck operating mode is made by control circuitry, which may be any of the DC-DC control circuitry  90 , the RF modulation and control circuitry  28 , and the control circuitry  42  ( FIG. 5 ). As such, the control circuitry may select one of the pump buck pump-up operating mode and at least one other pump buck operating mode of the charge pump buck converter  84 . The at least one other pump buck operating mode of the charge pump buck converter  84  may include any or all of the pump buck pump-down operating mode, the pump buck pump-even operating mode, and the pump buck bypass operating mode. 
     The charge pump  92  may operate in one of multiple bias supply pump operating modes. During a bias supply pump-up operating mode of the charge pump  92 , the charge pump  92  receives and pumps-up the DC power supply signal DCPS to provide the bias power supply signal BPS, such that a voltage of the bias power supply signal BPS is greater than a voltage of the DC power supply signal DCPS. During a bias supply pump-down operating mode of the charge pump  92 , the charge pump  92  pumps-down the DC power supply signal DCPS to provide the bias power supply signal BPS, such that a voltage of the bias power supply signal BPS is less than a voltage of the DC power supply signal DCPS. During a bias supply pump-even operating mode of the charge pump  92 , the charge pump  92  pumps the DC power supply signal DCPS to provide the bias power supply signal BPS, such that a voltage of the bias power supply signal BPS is about equal to a voltage of the DC power supply signal DCPS. One embodiment of the DC-DC converter  32  includes a bias supply bypass operating mode of the charge pump  92 , such that during the bias supply bypass operating mode, the charge pump  92  by-passes charge pump circuitry (not shown) using by-pass circuitry (not shown) to forward the DC power supply signal DCPS to provide the bias power supply signal BPS, such that a voltage of the bias power supply signal BPS is about equal to a voltage of the DC power supply signal DCPS. The charge pump control signal CPS may indicate which bias supply pump operating mode is selected. 
     In one embodiment of the charge pump  92 , the bias supply pump operating modes include the bias supply pump-up operating mode, the bias supply pump-down operating mode, the bias supply pump-even operating mode, and the bias supply bypass operating mode. In an alternate embodiment of the charge pump  92 , the bias supply pump-even operating mode is omitted. In an additional embodiment of the charge pump  92 , the bias supply bypass operating mode is omitted. In another embodiment of the charge pump  92 , the bias supply pump-down operating mode is omitted. In a further embodiment of the charge pump  92 , any or all of the bias supply pump-up operating mode, the bias supply pump-down operating mode, the bias supply pump-even operating mode, and the bias supply bypass operating mode are omitted. In a supplemental embodiment of the charge pump  92 , the charge pump  92  operates in only the bias supply pump-up operating mode. In an additional embodiment of the charge pump  92 , the charge pump  92  operates in the bias supply pump-up operating mode and at least one other operating mode of the charge pump  92 , which may include any or all of the bias supply pump-down operating mode, the bias supply pump-even operating mode, and the bias supply bypass operating mode. 
     In one embodiment of the DC-DC converter  32 , selection of the bias supply pump operating mode is made by the DC-DC control circuitry  90 . In an alternate embodiment of the DC-DC converter  32 , selection of the bias supply pump operating mode is made by the RF modulation and control circuitry  28  and communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In an additional embodiment of the DC-DC converter  32 , selection of the bias supply pump operating mode is made by the control circuitry  42  ( FIG. 5 ) and communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In general, selection of the bias supply pump operating mode is made by control circuitry, which may be any of the DC-DC control circuitry  90 , the RF modulation and control circuitry  28 , and the control circuitry  42  ( FIG. 5 ). As such, the control circuitry may select one of the bias supply pump-up operating mode and at least one other bias supply operating mode. The at least one other bias supply operating mode may include any or all of the bias supply pump-down operating mode, the bias supply pump-even operating mode, and the bias supply bypass operating mode. 
     The second power filtering circuitry  88  filters the bias power supply signal BPS. The second power filtering circuitry  88  may function as a lowpass filter by removing ripple, noise, and the like to provide the bias power supply signal BPS. As such, in one embodiment of the DC-DC converter  32 , the bias power supply signal BPS is based on the DC power supply signal DCPS. 
     Regarding omission of the second inductive element L 2 , instead of the second inductive element L 2  coupled between the buck converter  86  and the first power filtering circuitry  82  as shown in  FIG. 10 , one end of the first inductive element L 1  is coupled to both the charge pump buck converter  84  and the buck converter  86 . As such, in the second converter operating mode or the third converter operating mode, the buck converter  86  may receive and buck convert the DC power supply signal DCPS to provide the second buck output signal SBO to the first inductive element L 1 . As such, in one embodiment of the charge pump buck converter  84 , the second buck output signal SBO is based on the DC power supply signal DCPS. Further, the first inductive element L 1  may function as a first energy transfer element of the buck converter  86  to transfer energy via the second buck output signal SBO to the first power filtering circuitry  82 . In the first converter operating mode, the second converter operating mode, or the third converter operating mode, the first inductive element L 1  and the first power filtering circuitry  82  receive and filter the first buck output signal FBO, the second buck output signal SBO, or both to provide the envelope power supply signal EPS. 
       FIG. 12  shows details of the DC-DC converter  32  illustrated in  FIG. 11  according to an alternate embodiment of the DC-DC converter  32 . The DC-DC converter  32  illustrated in  FIG. 12  is similar to the DC-DC converter  32  illustrated in  FIG. 10 , except the DC-DC converter  32  illustrated in  FIG. 12  shows details of the first power filtering circuitry  82  and the second power filtering circuitry  88 . Further, the DC-DC converter  32  illustrated in  FIG. 12  includes the DC-DC control circuitry  90  and the charge pump  92  as shown in  FIG. 11 . 
     The first power filtering circuitry  82  includes a first capacitive element C 1 , a second capacitive element C 2 , and a third inductive element L 3 . The first capacitive element C 1  is coupled between one end of the third inductive element L 3  and a ground. The second capacitive element C 2  is coupled between an opposite end of the third inductive element L 3  and ground. The one end of the third inductive element L 3  is coupled to one end of the first inductive element L 1 . Further, the one end of the third inductive element L 3  is coupled to one end of the second inductive element L 2 . In an additional embodiment of the DC-DC converter  32 , the second inductive element L 2  is omitted. The opposite end of the third inductive element L 3  is coupled to the RF PA circuitry  30 . As such, the opposite end of the third inductive element L 3  and one end of the second capacitive element C 2  provide the envelope power supply signal EPS. In an alternate embodiment of the first power filtering circuitry  82 , the third inductive element L 3 , the second capacitive element C 2 , or both are omitted. 
       FIG. 13  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 13  is similar to the RF PA circuitry  30  illustrated in  FIG. 5 , except the RF PA circuitry  30  illustrated in  FIG. 13  further includes PA control circuitry  94 , PA bias circuitry  96 , and switch driver circuitry  98 . The PA bias circuitry  96  is coupled between the PA control circuitry  94  and the RF PAs  50 ,  54 . The switch driver circuitry  98  is coupled between the PA control circuitry  94  and the switching circuitry  52 ,  56 . The PA control circuitry  94  receives the PA configuration control signal PCC, provides a bias configuration control signal BCC to the PA bias circuitry  96  based on the PA configuration control signal PCC, and provides a switch configuration control signal SCC to the switch driver circuitry  98  based on the PA configuration control signal PCC. The switch driver circuitry  98  provides any needed drive signals to configure the alpha switching circuitry  52  and the beta switching circuitry  56 . 
     The PA bias circuitry  96  receives the bias power supply signal BPS and the bias configuration control signal BCC. The PA bias circuitry  96  provides a first driver bias signal FDB and a first final bias signal FFB to the first RF PA  50  based on the bias power supply signal BPS and the bias configuration control signal BCC. The PA bias circuitry  96  provides a second driver bias signal SDB and a second final bias signal SFB to the second RF PA  54  based on the bias power supply signal BPS and the bias configuration control signal BCC. The bias power supply signal BPS provides the power necessary to generate the bias signals FDB, FFB, SDB, SFB. A selected magnitude of each of the bias signals FDB, FFB, SDB, SFB is provided by the PA bias circuitry  96 . In one embodiment of the RF PA circuitry  30 , the PA control circuitry  94  selects the magnitude of any or all of the bias signals FDB, FFB, SDB, SFB and communicates the magnitude selections to the PA bias circuitry  96  via the bias configuration control signal BCC. The magnitude selections by the PA control circuitry  94  may be based on the PA configuration control signal PCC. In an alternate embodiment of the RF PA circuitry  30 , the control circuitry  42  ( FIG. 5 ) selects the magnitude of any or all of the bias signals FDB, FFB, SDB, SFB and communicates the magnitude selections to the PA bias circuitry  96  via the PA control circuitry  94 . 
     In one embodiment of the RF PA circuitry  30 , the RF PA circuitry  30  operates in one of a first PA operating mode and a second PA operating mode. During the first PA operating mode, the first transmit path  46  is enabled and the second transmit path  48  is disabled. During the second PA operating mode, the first transmit path  46  is disabled and the second transmit path  48  is enabled. In one embodiment of the first RF PA  50  and the second RF PA  54 , during the second PA operating mode, the first RF PA  50  is disabled, and during the first PA operating mode, the second RF PA  54  is disabled. In one embodiment of the alpha switching circuitry  52  and the beta switching circuitry  56 , during the second PA operating mode, the alpha switching circuitry  52  is disabled, and during the first PA operating mode, the beta switching circuitry  56  is disabled. 
     In one embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via the first driver bias signal FDB. In an alternate embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via the first final bias signal FFB. In an additional embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via both the first driver bias signal FDB and the first final bias signal FFB. In one embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via the second driver bias signal SDB. In an alternate embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via the second final bias signal SFB. In an additional embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via both the second driver bias signal SDB and the second final bias signal SFB. 
     In one embodiment of the RF PA circuitry  30 , the PA control circuitry  94  selects the one of the first PA operating mode and the second PA operating mode. As such, the PA control circuitry  94  may control any or all of the bias signals FDB, FFB, SDB, SFB via the bias configuration control signal BCC based on the PA operating mode selection. Further, the PA control circuitry  94  may control the switching circuitry  52 ,  56  via the switch configuration control signal SCC based on the PA operating mode selection. The PA operating mode selection may be based on the PA configuration control signal PCC. In an alternate embodiment of the RF PA circuitry  30 , the control circuitry  42  ( FIG. 5 ) selects the one of the first PA operating mode and the second PA operating mode. As such, the control circuitry  42  ( FIG. 5 ) may indicate the operating mode selection to the PA control circuitry  94  via the PA configuration control signal PCC. In an additional embodiment of the RF PA circuitry  30 , the RF modulation and control circuitry  28  ( FIG. 5 ) selects the one of the first PA operating mode and the second PA operating mode. As such, the RF modulation and control circuitry  28  ( FIG. 5 ) may indicate the operating mode selection to the PA control circuitry  94  via the PA configuration control signal PCC. In general, selection of the PA operating mode is made by control circuitry, which may be any of the PA control circuitry  94 , the RF modulation and control circuitry  28  ( FIG. 5 ), and the control circuitry  42  ( FIG. 5 ). 
       FIG. 14  shows details of the RF PA circuitry  30  illustrated in  FIG. 6  according to an alternate embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 14  is similar to the RF PA circuitry  30  illustrated in  FIG. 13 , except the RF PA circuitry  30  illustrated in  FIG. 14  further includes the PA-DCI  60 , which is coupled to the PA control circuitry  94  and to the digital communications bus  66 . As such, the control circuitry  42  ( FIG. 6 ) may provide the PA configuration control signal PCC via the control circuitry DCI  58  ( FIG. 6 ) to the PA control circuitry  94  via the PA-DCI  60 . 
       FIG. 15  shows details of the first RF PA  50  and the second RF PA  54  illustrated in  FIG. 13  according one embodiment of the first RF PA  50  and the second RF PA  54 . The first RF PA  50  includes a first non-quadrature PA path  100  and a first quadrature PA path  102 . The second RF PA  54  includes a second non-quadrature PA path  104  and a second quadrature PA path  106 . In one embodiment of the first RF PA  50 , the first quadrature PA path  102  is coupled between the first non-quadrature PA path  100  and the antenna port AP ( FIG. 6 ), which is coupled to the antenna  18  ( FIG. 6 ). In an alternate embodiment of the first RF PA  50 , the first non-quadrature PA path  100  is omitted, such that the first quadrature PA path  102  is coupled to the antenna port AP ( FIG. 6 ). The first quadrature PA path  102  may be coupled to the antenna port AP ( FIG. 6 ) via the alpha switching circuitry  52  ( FIG. 6 ) and the front-end aggregation circuitry  36  ( FIG. 6 ). The first non-quadrature PA path  100  may include any number of non-quadrature gain stages. The first quadrature PA path  102  may include any number of quadrature gain stages. In one embodiment of the second RF PA  54 , the second quadrature PA path  106  is coupled between the second non-quadrature PA path  104  and the antenna port AP ( FIG. 6 ). In an alternate embodiment of the second RF PA  54 , the second non-quadrature PA path  104  is omitted, such that the second quadrature PA path  106  is coupled to the antenna port AP ( FIG. 6 ). The second quadrature PA path  106  may be coupled to the antenna port AP ( FIG. 6 ) via the beta switching circuitry  56  ( FIG. 6 ) and the front-end aggregation circuitry  36  ( FIG. 6 ). The second non-quadrature PA path  104  may include any number of non-quadrature gain stages. The second quadrature PA path  106  may include any number of quadrature gain stages. 
     In one embodiment of the RF communications system  26 , the control circuitry  42  ( FIG. 5 ) selects one of multiple communications modes, which include a first PA operating mode and a second PA operating mode. During the first PA operating mode, the first PA paths  100 ,  102  receive the envelope power supply signal EPS, which provides power for amplification. During the second PA operating mode, the second PA paths  104 ,  106  receive the envelope power supply signal EPS, which provides power for amplification. During the first PA operating mode, the first non-quadrature PA path  100  receives the first driver bias signal FDB, which provides biasing to the first non-quadrature PA path  100 , and the first quadrature PA path  102  receives the first final bias signal FFB, which provides biasing to the first quadrature PA path  102 . During the second PA operating mode, the second non-quadrature PA path  104  receives the second driver bias signal SDB, which provides biasing to the second non-quadrature PA path  104 , and the second quadrature PA path  106  receives the second final bias signal SFB, which provides biasing to the second quadrature PA path  106 . 
     The first non-quadrature PA path  100  has a first single-ended output FSO and the first quadrature PA path  102  has a first single-ended input FSI. The first single-ended output FSO may be coupled to the first single-ended input FSI. In one embodiment of the first RF PA  50 , the first single-ended output FSO is directly coupled to the first single-ended input FSI. The second non-quadrature PA path  104  has a second single-ended output SSO and the second quadrature PA path  106  has a second single-ended input SSI. The second single-ended output SSO may be coupled to the second single-ended input SSI. In one embodiment of the second RF PA  54 , the second single-ended output SSO is directly coupled to the second single-ended input SSI. 
     During the first PA operating mode, the first RF PA  50  receives and amplifies the first RF input signal FRFI to provide the first RF output signal FRFO, and the second RF PA  54  is disabled. During the second PA operating mode, the second RF PA  54  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO, and the first RF PA  50  is disabled. In one embodiment of the RF communications system  26 , the first RF input signal FRFI is a highband RF input signal and the second RF input signal SRFI is a lowband RF input signal. In one exemplary embodiment of the RF communications system  26 , a difference between a frequency of the highband RF input signal and a frequency of the lowband RF input signal is greater than about 500 megahertz, such that the frequency of the highband RF input signal is greater than the frequency of the lowband RF input signal. In an alternate exemplary embodiment of the RF communications system  26 , a ratio of a frequency of the highband RF input signal divided by a frequency of the lowband RF input signal is greater than about 1.5. 
     In one embodiment of the first RF PA  50 , during the first PA operating mode, the first non-quadrature PA path  100  receives and amplifies the first RF input signal FRFI to provide a first RF feeder output signal FFO to the first quadrature PA path  102  via the first single-ended output FSO. Further, during the first PA operating mode, the first quadrature PA path  102  receives and amplifies the first RF feeder output signal FFO via the first single-ended input FSI to provide the first RF output signal FRFO. In one embodiment of the second RF PA  54 , during the second PA operating mode, the second non-quadrature PA path  104  receives and amplifies the second RF input signal SRFI to provide a second RF feeder output signal SFO to the second quadrature PA path  106  via the second single-ended output SSO. Further, during the second PA operating mode, the second quadrature PA path  106  receives and amplifies the second RF feeder output signal SFO via the second single-ended input SSI to provide the second RF output signal SRFO. 
     Quadrature PA Architecture 
     A summary of quadrature PA architecture is presented, followed by a detailed description of the quadrature PA architecture according to one embodiment of the present disclosure. One embodiment of the RF communications system  26  ( FIG. 6 ) relates to a quadrature RF PA architecture that utilizes a single-ended interface to couple a non-quadrature PA path to a quadrature PA path, which may be coupled to the antenna port ( FIG. 6 ). The quadrature nature of the quadrature PA path may provide tolerance for changes in antenna loading conditions. An RF splitter in the quadrature PA path may present a relatively stable input impedance, which may be predominantly resistive, to the non-quadrature PA path over a wide frequency range, thereby substantially isolating the non-quadrature PA path from changes in the antenna loading conditions. Further, the input impedance may substantially establish a load line slope of a feeder PA stage in the non-quadrature PA path, thereby simplifying the quadrature RF PA architecture. One embodiment of the quadrature RF PA architecture uses two separate PA paths, either of which may incorporate a combined non-quadrature and quadrature PA architecture. 
     Due to the relatively stable input impedance, RF power measurements taken at the single-ended interface may provide high directivity and accuracy. Further, by combining the non-quadrature PA path and the quadrature PA path, gain stages may be eliminated and circuit topology may be simplified. In one embodiment of the RF splitter, the RF splitter is a quadrature hybrid coupler, which may include a pair of tightly coupled inductors. The input impedance may be based on inductances of the pair of tightly coupled inductors and parasitic capacitance between the inductors. As such, construction of the pair of tightly coupled inductors may be varied to select a specific parasitic capacitance to provide a specific input impedance. Further, the RF splitter may be integrated onto one semiconductor die with amplifying elements of the non-quadrature PA path, with amplifying elements of the quadrature PA path, or both, thereby reducing size and cost. Additionally, the quadrature PA path may have only a single quadrature amplifier stage to further simplify the design. In certain embodiments, using only the single quadrature amplifier stage provides adequate tolerance for changes in antenna loading conditions. 
       FIG. 16  shows details of the first non-quadrature PA path  100  and the second non-quadrature PA path  104  illustrated in  FIG. 15  according to one embodiment of the first non-quadrature PA path  100  and the second non-quadrature PA path  104 . The first non-quadrature PA path  100  includes a first input PA impedance matching circuit  108 , a first input PA stage  110 , a first feeder PA impedance matching circuit  112 , and a first feeder PA stage  114 , which provides the first single-ended output FSO. The first input PA stage  110  is coupled between the first input PA impedance matching circuit  108  and the first feeder PA impedance matching circuit  112 . The first feeder PA stage  114  is coupled between the first feeder PA impedance matching circuit  112  and the first quadrature PA path  102 . The first input PA impedance matching circuit  108  may provide at least an approximate impedance match between the RF modulation circuitry  44  ( FIG. 5 ) and the first input PA stage  110 . The first feeder PA impedance matching circuit  112  may provide at least an approximate impedance match between the first input PA stage  110  and the first feeder PA stage  114 . In alternate embodiments of the first non-quadrature PA path  100 , any or all of the first input PA impedance matching circuit  108 , the first input PA stage  110 , and the first feeder PA impedance matching circuit  112 , may be omitted. 
     During the first PA operating mode, the first input PA impedance matching circuit  108  receives and forwards the first RF input signal FRFI to the first input PA stage  110 . During the first PA operating mode, the first input PA stage  110  receives and amplifies the forwarded first RF input signal FRFI to provide a first RF feeder input signal FFI to the first feeder PA stage  114  via the first feeder PA impedance matching circuit  112 . During the first PA operating mode, the first feeder PA stage  114  receives and amplifies the first RF feeder input signal FFI to provide the first RF feeder output signal FFO via the first single-ended output FSO. The first feeder PA stage  114  may have a first output load line having a first load line slope. During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first input PA stage  110  and to the first feeder PA stage  114 . During the first PA operating mode, the first driver bias signal FDB provides biasing to the first input PA stage  110  and the first feeder PA stage  114 . 
     The second non-quadrature PA path  104  includes a second input PA impedance matching circuit  116 , a second input PA stage  118 , a second feeder PA impedance matching circuit  120 , and a second feeder PA stage  122 , which provides the second single-ended output SSO. The second input PA stage  118  is coupled between the second input PA impedance matching circuit  116  and the second feeder PA impedance matching circuit  120 . The second feeder PA stage  122  is coupled between the second feeder PA impedance matching circuit  120  and the second quadrature PA path  106 . The second input PA impedance matching circuit  116  may provide at least an approximate impedance match between the RF modulation circuitry  44  ( FIG. 5 ) and the second input PA stage  118 . The second feeder PA impedance matching circuit  120  may provide at least an approximate impedance match between the second input PA stage  118  and the second feeder PA stage  122 . In alternate embodiments of the second non-quadrature PA path  104 , any or all of the second input PA impedance matching circuit  116 , the second input PA stage  118 , and the second feeder PA impedance matching circuit  120 , may be omitted. 
     During the second PA operating mode, the second input PA impedance matching circuit  116  receives and forwards the second RF input signal SRFI to the second input PA stage  118 . During the second PA operating mode, the second input PA stage  118  receives and amplifies the forwarded second RF input signal SRFI to provide a second RF feeder input signal SFI to the second feeder PA stage  122  via the second feeder PA impedance matching circuit  120 . During the second PA operating mode, the second feeder PA stage  122  receives and amplifies the second RF feeder input signal SFI to provide the second RF feeder output signal SFO via the second single-ended output SSO. The second feeder PA stage  122  may have a second output load line having a second load line slope. During the second PA operating mode, the envelope power supply signal EPS provides power for amplification to the second input PA stage  118  and to the second feeder PA stage  122 . During the second PA operating mode, the second driver bias signal SDB provides biasing to the second input PA stage  118  and the second feeder PA stage  122 . 
       FIG. 17  shows details of the first quadrature PA path  102  and the second quadrature PA path  106  illustrated in  FIG. 15  according to one embodiment of the first quadrature PA path  102  and the second quadrature PA path  106 . The first quadrature PA path  102  includes a first quadrature RF splitter  124 , a first in-phase amplification path  126 , a first quadrature-phase amplification path  128 , and a first quadrature RF combiner  130 . The first quadrature RF splitter  124  has a first single-ended input FSI, a first in-phase output FIO, and a first quadrature-phase output FQO. The first quadrature RF combiner  130  has a first in-phase input FII, a first quadrature-phase input FQI, and a first quadrature combiner output FCO. The first single-ended output FSO is coupled to the first single-ended input FSI. In one embodiment of the first quadrature PA path  102 , the first single-ended output FSO is directly coupled to the first single-ended input FSI. The first in-phase amplification path  126  is coupled between the first in-phase output FIO and the first in-phase input FII. The first quadrature-phase amplification path  128  is coupled between the first quadrature-phase output FQO and the first quadrature-phase input FQI. The first quadrature combiner output FCO is coupled to the antenna port AP ( FIG. 6 ) via the alpha switching circuitry  52  ( FIG. 6 ) and the front-end aggregation circuitry  36  ( FIG. 6 ). 
     During the first PA operating mode, the first quadrature RF splitter  124  receives the first RF feeder output signal FFO via the first single-ended input FSI. Further, during the first PA operating mode, the first quadrature RF splitter  124  splits and phase-shifts the first RF feeder output signal FFO into a first in-phase RF input signal FIN and a first quadrature-phase RF input signal FQN, such that the first quadrature-phase RF input signal FQN is nominally phase-shifted from the first in-phase RF input signal FIN by about 90 degrees. The first quadrature RF splitter  124  has a first input impedance presented at the first single-ended input FSI. In one embodiment of the first quadrature RF splitter  124 , the first input impedance establishes the first load line slope. During the first PA operating mode, the first in-phase amplification path  126  receives and amplifies the first in-phase RF input signal FIN to provide the first in-phase RF output signal FIT. The first quadrature-phase amplification path  128  receives and amplifies the first quadrature-phase RF input signal FQN to provide the first quadrature-phase RF output signal FQT. 
     During the first PA operating mode, the first quadrature RF combiner  130  receives the first in-phase RF output signal FIT via the first in-phase input FII, and receives the first quadrature-phase RF output signal FQT via the first quadrature-phase input FQI. Further, the first quadrature RF combiner  130  phase-shifts and combines the first in-phase RF output signal FIT and the first quadrature-phase RF output signal FQT to provide the first RF output signal FRFO via the first quadrature combiner output FCO, such that the phase-shifted first in-phase RF output signal FIT and first quadrature-phase RF output signal FQT are about phase-aligned with one another before combining. During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first in-phase amplification path  126  and the first quadrature-phase amplification path  128 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first in-phase amplification path  126  and the first quadrature-phase amplification path  128 . 
     The second quadrature PA path  106  includes a second quadrature RF splitter  132 , a second in-phase amplification path  134 , a second quadrature-phase amplification path  136 , and a second quadrature RF combiner  138 . The second quadrature RF splitter  132  has a second single-ended input SSI, a second in-phase output SIO, and a second quadrature-phase output SQO. The second quadrature RF combiner  138  has a second in-phase input SII, a second quadrature-phase input SQI, and a second quadrature combiner output SCO. The second single-ended output SSO is coupled to the second single-ended input SSI. In one embodiment of the second quadrature PA path  106 , the second single-ended output SSO is directly coupled to the second single-ended input SSI. The second in-phase amplification path  134  is coupled between the second in-phase output SIO and the second in-phase input SII. The second quadrature-phase amplification path  136  is coupled between the second quadrature-phase output SQO and the second quadrature-phase input SQI. The second quadrature combiner output SCO is coupled to the antenna port AP ( FIG. 6 ) via the alpha switching circuitry  52  ( FIG. 6 ) and the front-end aggregation circuitry  36  ( FIG. 6 ). 
     During the second PA operating mode, the second quadrature RF splitter  132  receives the second RF feeder output signal SFO via the second single-ended input SSI. Further, during the second PA operating mode, the second quadrature RF splitter  132  splits and phase-shifts the second RF feeder output signal SFO into a second in-phase RF input signal SIN and a second quadrature-phase RF input signal SQN, such that the second quadrature-phase RF input signal SQN is nominally phase-shifted from the second in-phase RF input signal SIN by about 90 degrees. The second quadrature RF splitter  132  has a second input impedance presented at the second single-ended input SSI. In one embodiment of the second quadrature RF splitter  132 , the second input impedance establishes the second load line slope. During the second PA operating mode, the second in-phase amplification path  134  receives and amplifies the second in-phase RF input signal SIN to provide the second in-phase RF output signal SIT. The second quadrature-phase amplification path  136  receives and amplifies the second quadrature-phase RF input signal SQN to provide the second quadrature-phase RF output signal SQT. 
     During the second PA operating mode, the second quadrature RF combiner  138  receives the second in-phase RF output signal SIT via the second in-phase input SII, and receives the second quadrature-phase RF output signal SQT via the second quadrature-phase input SQI. Further, the second quadrature RF combiner  138  phase-shifts and combines the second in-phase RF output signal SIT and the second quadrature-phase RF output signal SQT to provide the second RF output signal SRFO via the second quadrature combiner output SCO, such that the phase-shifted second in-phase RF output signal SIT and second quadrature-phase RF output signal SQT are about phase-aligned with one another before combining. During the second PA operating mode, the envelope power supply signal EPS provides power for amplification to the second in-phase amplification path  134  and the second quadrature-phase amplification path  136 . During the second PA operating mode, the second final bias signal SFB provides biasing to the second in-phase amplification path  134  and the second quadrature-phase amplification path  136 . 
     In one embodiment of the RF PA circuitry  30  ( FIG. 13 ), the second transmit path  48  ( FIG. 13 ) is omitted. As such, the first feeder PA stage  114  ( FIG. 16 ) is a feeder PA stage and the first single-ended output FSO ( FIG. 16 ) is a single-ended output. The first RF feeder input signal FFI ( FIG. 16 ) is an RF feeder input signal and the first RF feeder output signal FFO ( FIG. 16 ) is an RF feeder output signal. The feeder PA stage receives and amplifies the RF feeder input signal to provide the RF feeder output signal via the single-ended output. The feeder PA stage has an output load line having a load line slope. The first quadrature RF splitter  124  is a quadrature RF splitter and the first single-ended input FSI is a single-ended input. As such, the quadrature RF splitter has the single-ended input. In one embodiment of the first RF PA  50 , the single-ended output is directly coupled to the single-ended input. 
     In the embodiment in which the second transmit path  48  ( FIG. 13 ) is omitted, the first in-phase RF input signal FIN is an in-phase RF input signal and the first quadrature-phase RF input signal FQN is a quadrature-phase RF input signal. The quadrature RF splitter receives the RF feeder output signal via the single-ended input. Further, the quadrature RF splitter splits and phase-shifts the RF feeder output signal into the in-phase RF input signal and the quadrature-phase RF input signal, such that the quadrature-phase RF input signal is nominally phase-shifted from the in-phase RF input signal by about 90 degrees. The quadrature RF splitter has an input impedance presented at the single-ended input. The input impedance substantially establishes the load line slope. The first in-phase amplification path  126  is an in-phase amplification path and the first quadrature-phase amplification path  128  is a quadrature-phase amplification path. The first in-phase RF output signal FIT is an in-phase RF output signal and the first quadrature-phase RF output signal FQT is a quadrature-phase RF output signal. As such, the in-phase amplification path receives and amplifies the in-phase RF input signal to provide the in-phase RF output signal. The quadrature-phase amplification path receives and amplifies the quadrature-phase RF input signal to provide the quadrature-phase RF output signal. 
     In the embodiment in which the second transmit path  48  ( FIG. 13 ) is omitted, the first RF output signal FRFO is an RF output signal. As such, the quadrature RF combiner receives, phase-shifts, and combines the in-phase RF output signal and the quadrature-phase RF output signal to provide the RF output signal. In one embodiment of the quadrature RF splitter, the input impedance has resistance and reactance, such that the reactance is less than the resistance. In a first exemplary embodiment of the quadrature RF splitter, the resistance is greater than two times the reactance. In a second exemplary embodiment of the quadrature RF splitter, the resistance is greater than four times the reactance. In a third exemplary embodiment of the quadrature RF splitter, the resistance is greater than six times the reactance. In a fourth exemplary embodiment of the quadrature RF splitter, the resistance is greater than eight times the reactance. In a first exemplary embodiment of the quadrature RF splitter, the resistance is greater than ten times the reactance. 
     In alternate embodiments of the first quadrature PA path  102  and the second quadrature PA path  106 , any or all of the first quadrature RF splitter  124 , the first quadrature RF combiner  130 , the second quadrature RF splitter  132 , and the second quadrature RF combiner  138  may be any combination of quadrature RF couplers, quadrature hybrid RF couplers; Fisher couplers; lumped-element based RF couplers; transmission line based RF couplers; and combinations of phase-shifting circuitry and RF power couplers, such as phase-shifting circuitry and Wilkinson couplers; and the like. As such, any of the RF couplers listed above may be suitable to provide the first input impedance, the second input impedance, or both. 
       FIG. 18  shows details of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , the second in-phase amplification path  134 , and the second quadrature-phase amplification path  136  illustrated in  FIG. 17  according to one embodiment of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , the second in-phase amplification path  134 , and the second quadrature-phase amplification path  136 . The first in-phase amplification path  126  includes a first in-phase driver PA impedance matching circuit  140 , a first in-phase driver PA stage  142 , a first in-phase final PA impedance matching circuit  144 , a first in-phase final PA stage  146 , and a first in-phase combiner impedance matching circuit  148 . The first in-phase driver PA impedance matching circuit  140  is coupled between the first in-phase output FIO and the first in-phase driver PA stage  142 . The first in-phase final PA impedance matching circuit  144  is coupled between the first in-phase driver PA stage  142  and the first in-phase final PA stage  146 . The first in-phase combiner impedance matching circuit  148  is coupled between the first in-phase final PA stage  146  and the first in-phase input FII. 
     The first in-phase driver PA impedance matching circuit  140  may provide at least an approximate impedance match between the first quadrature RF splitter  124  and the first in-phase driver PA stage  142 . The first in-phase final PA impedance matching circuit  144  may provide at least an approximate impedance match between the first in-phase driver PA stage  142  and the first in-phase final PA stage  146 . The first in-phase combiner impedance matching circuit  148  may provide at least an approximate impedance match between the first in-phase final PA stage  146  and the first quadrature RF combiner  130 . 
     During the first PA operating mode, the first in-phase driver PA impedance matching circuit  140  receives and forwards the first in-phase RF input signal FIN to the first in-phase driver PA stage  142 , which receives and amplifies the forwarded first in-phase RF input signal to provide an amplified first in-phase RF input signal to the first in-phase final PA stage  146  via the first in-phase final PA impedance matching circuit  144 . The first in-phase final PA stage  146  receives and amplifies the amplified first in-phase RF input signal to provide the first in-phase RF output signal FIT via the first in-phase combiner impedance matching circuit  148 . During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first in-phase driver PA stage  142  and the first in-phase final PA stage  146 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first in-phase driver PA stage  142  and the first in-phase final PA stage  146 . 
     The first quadrature-phase amplification path  128  includes a first quadrature-phase driver PA impedance matching circuit  150 , a first quadrature-phase driver PA stage  152 , a first quadrature-phase final PA impedance matching circuit  154 , a first quadrature-phase final PA stage  156 , and a first quadrature-phase combiner impedance matching circuit  158 . The first quadrature-phase driver PA impedance matching circuit  150  is coupled between the first quadrature-phase output FQO and the first quadrature-phase driver PA stage  152 . The first quadrature-phase final PA impedance matching circuit  154  is coupled between the first quadrature-phase driver PA stage  152  and the first quadrature-phase final PA stage  156 . The first quadrature-phase combiner impedance matching circuit  158  is coupled between the first quadrature-phase final PA stage  156  and the first quadrature-phase input FQI. 
     The first quadrature-phase driver PA impedance matching circuit  150  may provide at least an approximate impedance match between the first quadrature RF splitter  124  and the first quadrature-phase driver PA stage  152 . The first quadrature-phase final PA impedance matching circuit  154  may provide at least an approximate impedance match between the first quadrature-phase driver PA stage  152  and the first quadrature-phase final PA stage  156 . The first quadrature-phase combiner impedance matching circuit  158  may provide at least an approximate impedance match between the first quadrature-phase final PA stage  156  and the first quadrature RF combiner  130 . 
     During the first PA operating mode, the first quadrature-phase driver PA impedance matching circuit  150  receives and forwards the first quadrature-phase RF input signal FQN to the first quadrature-phase driver PA stage  152 , which receives and amplifies the forwarded first quadrature-phase RF input signal to provide an amplified first quadrature-phase RF input signal to the first quadrature-phase final PA stage  156  via the first quadrature-phase final PA impedance matching circuit  154 . The first quadrature-phase final PA stage  156  receives and amplifies the amplified first quadrature-phase RF input signal to provide the first quadrature-phase RF output signal FQT via the first quadrature-phase combiner impedance matching circuit  158 . During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first quadrature-phase driver PA stage  152  and the first quadrature-phase final PA stage  156 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first quadrature-phase driver PA stage  152  and the first quadrature-phase final PA stage  156 . 
     The second in-phase amplification path  134  includes a second in-phase driver PA impedance matching circuit  160 , a second in-phase driver PA stage  162 , a second in-phase final PA impedance matching circuit  164 , a second in-phase final PA stage  166 , and a second in-phase combiner impedance matching circuit  168 . The second in-phase driver PA impedance matching circuit  160  is coupled between the second in-phase output SIO and the second in-phase driver PA stage  162 . The second in-phase final PA impedance matching circuit  164  is coupled between the second in-phase driver PA stage  162  and the second in-phase final PA stage  166 . The second in-phase combiner impedance matching circuit  168  is coupled between the second in-phase final PA stage  166  and the second in-phase input SII. 
     The second in-phase driver PA impedance matching circuit  160  may provide at least an approximate impedance match between the second quadrature RF splitter  132  and the second in-phase driver PA stage  162 . The second in-phase final PA impedance matching circuit  164  may provide at least an approximate impedance match between the second in-phase driver PA stage  162  and the second in-phase final PA stage  166 . The second in-phase combiner impedance matching circuit  168  may provide at least an approximate impedance match between the second in-phase final PA stage  166  and the second quadrature RF combiner  138 . 
     During the second PA operating mode, the second in-phase driver PA impedance matching circuit  160  receives and forwards the second in-phase RF input signal SIN to the second in-phase driver PA stage  162 , which receives and amplifies the forwarded second in-phase RF input signal to provide an amplified second in-phase RF input signal to the second in-phase final PA stage  166  via the second in-phase final PA impedance matching circuit  164 . The second in-phase final PA stage  166  receives and amplifies the amplified second in-phase RF input signal to provide the second in-phase RF output signal SIT via the second in-phase combiner impedance matching circuit  168 . During the second PA operating mode, the envelope power supply signal EPS provides power for amplification to the second in-phase driver PA stage  162  and the second in-phase final PA stage  166 . During the second PA operating mode, the second final bias signal SFB provides biasing to the second in-phase driver PA stage  162  and the second in-phase final PA stage  166 . 
     The second quadrature-phase amplification path  136  includes a second quadrature-phase driver PA impedance matching circuit  170 , a second quadrature-phase driver PA stage  172 , a second quadrature-phase final PA impedance matching circuit  174 , a second quadrature-phase final PA stage  176 , and a second quadrature-phase combiner impedance matching circuit  178 . The second quadrature-phase driver PA impedance matching circuit  170  is coupled between the second quadrature-phase output SQO and the second quadrature-phase driver PA stage  172 . The second quadrature-phase final PA impedance matching circuit  174  is coupled between the second quadrature-phase driver PA stage  172  and the second quadrature-phase final PA stage  176 . The second quadrature-phase combiner impedance matching circuit  178  is coupled between the second quadrature-phase final PA stage  176  and the second quadrature-phase input SQI. 
     The second quadrature-phase driver PA impedance matching circuit  170  may provide at least an approximate impedance match between the second quadrature RF splitter  132  and the second quadrature-phase driver PA stage  172 . The second quadrature-phase final PA impedance matching circuit  174  may provide at least an approximate impedance match between the second quadrature-phase driver PA stage  172  and the second quadrature-phase final PA stage  176 . The second quadrature-phase combiner impedance matching circuit  178  may provide at least an approximate impedance match between the second quadrature-phase final PA stage  176  and the second quadrature RF combiner  138 . 
     During the second PA operating mode, the second quadrature-phase driver PA impedance matching circuit  170  receives and forwards the second quadrature-phase RF input signal SQN to the second quadrature-phase driver PA stage  172 , which receives and amplifies the forwarded second quadrature-phase RF input signal to provide an amplified second quadrature-phase RF input signal to the second quadrature-phase final PA stage  176  via the second quadrature-phase final PA impedance matching circuit  174 . The second quadrature-phase final PA stage  176  receives and amplifies the amplified second quadrature-phase RF input signal to provide the second quadrature-phase RF output signal SQT via the second quadrature-phase combiner impedance matching circuit  178 . During the second PA operating mode, the envelope power supply signal EPS provides power for amplification to the second quadrature-phase driver PA stage  172  and the second quadrature-phase final PA stage  176 . During the second PA operating mode, the second final bias signal SFB provides biasing to the second quadrature-phase driver PA stage  172  and the second quadrature-phase final PA stage  176 . 
     In alternate embodiments of the first in-phase amplification path  126 , any or all of the first in-phase driver PA impedance matching circuit  140 , the first in-phase driver PA stage  142 , the first in-phase final PA impedance matching circuit  144 , and the first in-phase combiner impedance matching circuit  148  may be omitted. In alternate embodiments of the first quadrature-phase amplification path  128 , any or all of the first quadrature-phase driver PA impedance matching circuit  150 , the first quadrature-phase driver PA stage  152 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase combiner impedance matching circuit  158  may be omitted. In alternate embodiments of the second in-phase amplification path  134 , any or all of the second in-phase driver PA impedance matching circuit  160 , the second in-phase driver PA stage  162 , the second in-phase final PA impedance matching circuit  164 , and the second in-phase combiner impedance matching circuit  168  may be omitted. In alternate embodiments of the second quadrature-phase amplification path  136 , any or all of the second quadrature-phase driver PA impedance matching circuit  170 , the second quadrature-phase driver PA stage  172 , the second quadrature-phase final PA impedance matching circuit  174 , and the second quadrature-phase combiner impedance matching circuit  178  may be omitted. 
       FIG. 19  shows details of the first quadrature PA path  102  and the second quadrature PA path  106  illustrated in  FIG. 15  according to an alternate embodiment of the first quadrature PA path  102  and the second quadrature PA path  106 . The first quadrature PA path  102  and the second quadrature PA path  106  illustrated in  FIG. 19  are similar to the first quadrature PA path  102  and the second quadrature PA path  106  illustrated in  FIG. 17 , except in the first quadrature PA path  102  and the second quadrature PA path  106  illustrated in  FIG. 19 , during the first PA operating mode, the first driver bias signal FDB provides further biasing to the first in-phase amplification path  126  and the first quadrature-phase amplification path  128 , and during the second PA operating mode, the second driver bias signal SDB provides further biasing to the second in-phase amplification path  134  and the second quadrature-phase amplification path  136 . 
       FIG. 20  shows details of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , the second in-phase amplification path  134 , and the second quadrature-phase amplification path  136  illustrated in  FIG. 19  according to an alternate embodiment of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , the second in-phase amplification path  134 , and the second quadrature-phase amplification path  136 . The amplification paths  126 ,  128 ,  134 ,  136  illustrated in  FIG. 20  are similar to the amplification paths  126 ,  128 ,  134 ,  136  illustrated in  FIG. 18 , except in the amplification paths  126 ,  128 ,  134 ,  136  illustrated in  FIG. 20 , during the first PA operating mode, the first driver bias signal FDB provides biasing to the first in-phase driver PA stage  142  and the first quadrature-phase driver PA stage  152  instead of the first final bias signal FFB, and during the second PA operating mode, the second driver bias signal SDB provides biasing to the second in-phase driver PA stage  162  and the second quadrature-phase driver PA stage  172  instead of the second final bias signal SFB. 
       FIG. 21  shows details of the first RF PA  50  and the second RF PA  54  illustrated in  FIG. 14  according an alternate embodiment of the first RF PA  50  and the second RF PA  54 . The first RF PA  50  shown in  FIG. 21  is similar to the first RF PA  50  illustrated in  FIG. 15 . The second RF PA  54  shown in  FIG. 21  is similar to the second RF PA  54  illustrated in  FIG. 15 , except in the second RF PA  54  illustrated in  FIG. 21  the second quadrature PA path  106  is omitted. As such, during the second PA operating mode, the second RF input signal SRFI provides the second RF feeder output signal SFO to the second quadrature PA path  106 . In this regard, during the second PA operating mode, the second quadrature PA path  106  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO. During the second PA operating mode, the second quadrature PA path  106  receives the envelope power supply signal EPS, which provides power for amplification. Further, during the second PA operating mode, the second quadrature PA path  106  receives the second driver bias signal SDB and the second final bias signal SFB, both of which provide biasing to the second quadrature PA path  106 . 
       FIG. 22  shows details of the first non-quadrature PA path  100 , the first quadrature PA path  102 , and the second quadrature PA path  106  illustrated in  FIG. 21  according to an additional embodiment of the first non-quadrature PA path  100 , the first quadrature PA path  102 , and the second quadrature PA path  106 . The second quadrature PA path  106  illustrated in  FIG. 22  is similar to the second quadrature PA path  106  illustrated in  FIG. 20 . The first quadrature PA path  102  illustrated in  FIG. 22  is similar to the first quadrature PA path  102  illustrated in  FIG. 20 , except in the first quadrature PA path  102  illustrated in  FIG. 22 , the first in-phase driver PA impedance matching circuit  140 , the first in-phase driver PA stage  142 , the first quadrature-phase driver PA impedance matching circuit  150 , and the first quadrature-phase driver PA stage  152  are omitted. In this regard, the first in-phase final PA impedance matching circuit  144  is coupled between the first in-phase output FIO and the first in-phase final PA stage  146 . The first in-phase combiner impedance matching circuit  148  is coupled between the first in-phase final PA stage  146  and the first in-phase input FII. The first in-phase final PA impedance matching circuit  144  may provide at least an approximate impedance match between the first quadrature RF splitter  124  and the first in-phase final PA stage  146 . The first in-phase combiner impedance matching circuit  148  may provide at least an approximate impedance match between the first in-phase final PA stage  146  and the first quadrature RF combiner  130 . 
     During the first PA operating mode, the first in-phase final PA impedance matching circuit  144  receives and forwards the first in-phase RF input signal FIN to the first in-phase final PA stage  146 , which receives and amplifies the forwarded first in-phase RF input signal to provide the first in-phase RF output signal FIT via the first in-phase combiner impedance matching circuit  148 . During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first in-phase final PA stage  146 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first in-phase final PA stage  146 . 
     The first quadrature-phase final PA impedance matching circuit  154  is coupled between the first quadrature-phase output FQO and the first quadrature-phase final PA stage  156 . The first quadrature-phase combiner impedance matching circuit  158  is coupled between the first quadrature-phase final PA stage  156  and the first quadrature-phase input FQI. The first quadrature-phase final PA impedance matching circuit  154  may provide at least an approximate impedance match between the first quadrature RF splitter  124  and the first quadrature-phase final PA stage  156 . The first quadrature-phase combiner impedance matching circuit  158  may provide at least an approximate impedance match between the first quadrature-phase final PA stage  156  and the first quadrature RF combiner  130 . 
     During the first PA operating mode, the first quadrature-phase final PA impedance matching circuit  154  receives and forwards the first quadrature-phase RF input signal FQN to the first quadrature-phase final PA stage  156 , which receives and amplifies the forwarded first quadrature-phase RF input signal to provide the first quadrature-phase RF output signal FQT via the first quadrature-phase combiner impedance matching circuit  158 . During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first quadrature-phase final PA stage  156 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first quadrature-phase final PA stage  156 . 
     The first non-quadrature PA path  100  illustrated in  FIG. 22  is similar to the first non-quadrature PA path  100  illustrated in  FIG. 16 , except in the first non-quadrature PA path  100  illustrated in  FIG. 22 , the first input PA impedance matching circuit  108  and the first input PA stage  110  are omitted. As such, the first feeder PA stage  114  is coupled between the first feeder PA impedance matching circuit  112  and the first quadrature PA path  102 . The first feeder PA impedance matching circuit  112  may provide at least an approximate impedance match between the RF modulation circuitry  44  ( FIG. 5 ) and the first feeder PA stage  114 . During the first PA operating mode, the first feeder PA impedance matching circuit  112  receives and forwards the first RF input signal FRFI to provide the first RF feeder input signal FFI to the first feeder PA stage  114 . During the first PA operating mode, the first feeder PA stage  114  receives and amplifies the first RF feeder input signal FFI to provide the first RF feeder output signal FFO via the first single-ended output FSO. During the first PA operating mode, the envelope power supply signal EPS provides power for amplification to the first feeder PA stage  114 . During the first PA operating mode, the first final bias signal FFB provides biasing to the first feeder PA stage  114 . 
     In one embodiment of the first quadrature PA path  102 , the first quadrature PA path  102  has only one in-phase PA stage, which is the first in-phase final PA stage  146 , and only one quadrature-phase PA stage, which is the first quadrature-phase final PA stage  156 . In one embodiment of the second quadrature PA path  106 , the second in-phase driver PA impedance matching circuit  160 , the second in-phase driver PA stage  162 , the second quadrature-phase driver PA impedance matching circuit  170 , and the second quadrature-phase driver PA stage  172  are omitted. As such, the second quadrature PA path  106  has only one in-phase PA stage, which is the second in-phase final PA stage  166 , and only one quadrature-phase PA stage, which is the second quadrature-phase final PA stage  176 . 
       FIG. 23  shows details of the first feeder PA stage  114  and the first quadrature RF splitter  124  illustrated in  FIG. 16  and  FIG. 17 , respectively, according to one embodiment of the first feeder PA stage  114  and the first quadrature RF splitter  124 .  FIGS. 23 and 24  show only a portion of the first feeder PA stage  114  and the first quadrature RF splitter  124 . The first feeder PA stage  114  includes a first output transistor element  180 , an inverting output inductive element LIO, and the first single-ended output FSO. The first output transistor element  180  has a first transistor inverting output FTIO, a first transistor non-inverting output FTNO, and a first transistor input FTIN. The first transistor non-inverting output FTNO is coupled to a ground and the first transistor inverting output FTIO is coupled to the first single-ended output FSO and to one end of the inverting output inductive element LIO. An opposite end of the inverting output inductive element LIO receives the envelope power supply signal EPS. 
     The first quadrature RF splitter  124  has the first single-ended input FSI, such that the first input impedance is presented at the first single-ended input FSI. Since the first input impedance may be predominantly resistive, the first input impedance may be approximated as a first input resistive element RFI coupled between the first single-ended input FSI and the ground. The first single-ended output FSO is directly coupled to the first single-ended input FSI. Therefore, the first input resistive element RFI is presented to the first transistor inverting output FTIO. 
       FIG. 24  shows details of the first feeder PA stage  114  and the first quadrature RF splitter  124  illustrated in  FIG. 16  and  FIG. 17 , respectively, according to an alternate embodiment of the first feeder PA stage  114  and the first quadrature RF splitter  124 . The first output transistor element  180  is an NPN bipolar transistor element, such that an emitter of the NPN bipolar transistor element provides the first transistor non-inverting output FTNO ( FIG. 23 ), a base of the NPN bipolar transistor element provides the first transistor input FTIN ( FIG. 23 ), and a collector of the NPN bipolar transistor element provides the first transistor inverting output FTIO ( FIG. 23 ). The inverting output inductive element LIO has an inverting output inductor current IDC, the collector of the NPN bipolar transistor element has a collector current IC, and the first input resistive element RFI has a first input current IFR. The NPN bipolar transistor element has a collector-emitter voltage VCE between the emitter and the collector of the NPN bipolar transistor element. 
     In general, the first feeder PA stage  114  is the feeder PA stage having the single-ended output and an output transistor element, which has an inverting output. In general, the first quadrature RF splitter  124  is the quadrature RF splitter having the single-ended input, such that the input impedance is presented at the single-ended input. The inverting output may provide the single-ended output and may be directly coupled to the single-ended input. The inverting output may be a collector of the output transistor element and the output transistor element has the output load line. 
       FIG. 25  is a graph illustrating output characteristics of the first output transistor element  180  illustrated in  FIG. 24  according to one embodiment of the first output transistor element  180 . The horizontal axis of the graph represents the collector-emitter voltage VCE of the NPN bipolar transistor element and the vertical axis represents the collector current IC of the NPN bipolar transistor element. Characteristic curves  182  of the NPN bipolar transistor element are shown relating the collector-emitter voltage VCE to the collector current IC at different base currents (not shown). The NPN bipolar transistor element has a first output load line  184  having a first load line slope  186 . The first output load line  184  may be represented by an equation for a straight line having the form Y=mX+b, where X represents the horizontal axis, Y represents the vertical axis, b represents the Y-intercept, and m represents the first load line slope  186 . As such, Y=IC, X=VCE, and b=ISAT, which is a saturation current ISAT of the NPN bipolar transistor element. Further, an X-intercept occurs at an off transistor voltage VCO. Substituting into the equation for a straight line provides EQ. 1, as shown below.
 
 IC=m ( VCE )+ ISAT.   EQ. 1:
 
     EQ. 2 illustrates Ohm&#39;s Law as applied to the first input resistive element RFI, as shown below.
 
 VCE =( IFR )( RFI ).  EQ. 2:
 
     EQ. 3 illustrates Kirchhoff&#39;s Current Law applied to the circuit illustrated in  FIG. 24  as shown below.
 
 IDC=IC+IFR.   EQ. 3:
 
     The inductive reactance of the inverting output inductive element LIO at frequencies of interest may be large compared to the resistance of the first input resistive element RFI. As such, for the purpose of analysis, the inverting output inductor current IDC may be treated as a constant DC current. Therefore, when VCE=0, the voltage across the first input resistive element RFI is zero, which makes IFR=0. From EQ. 3, if IFR=0, then IC=IDC. However, from EQ. 1, when VCE=0 and IC=IDC, then ISAT=IDC, which is a constant. Substituting into EQ. 1 provides EQ. 1A as shown below.
 
 IC=m ( VCE )+ IDC.   EQ. 1A:
 
     From  FIG. 25 , when IC=0, VCE=VCO. Substituting into EQ. 1A, EQ. 2, and EQ. 3 provides EQ. 1B, EQ. 2A, and EQ. 3A as shown below.
 
0= m ( VCO )+ IDC.   EQ. 1B:
 
 VCO =( IFR )( RFI ).  EQ. 2A:
 
 IDC= 0 +IFR.   EQ. 3A:
 
     EQ. 3A may be substituted into EQ. 2A, which may be substituted into EQ. 1B to provide EQ. 1C as shown below.
 
0 =m ( VCO )+ IDC=m ( IDC )( RFI )+ IDC.   EQ. 1C:
 
     Therefore, m=−1/RFI. As a result, the first load line slope  186 , which is represented by m is determined by the first input resistive element RFI, such that there is a negative inverse relationship between the first load line slope  186  and the first input resistive element RFI. In general, the first load line slope  186  is based on the first input impedance, such that the first input impedance substantially establishes the first load line slope  186 . Further, there may be a negative inverse relationship between the first load line slope  186  and the first input impedance. 
       FIG. 26  illustrates a process for matching an input impedance, such as the first input impedance to the first quadrature RF splitter  124  ( FIG. 16 ) to a target load line slope for a feeder PA stage, such as the first feeder PA stage  114  ( FIG. 17 ). The first step of the process is to determine an operating power range of an RF PA, which has the feeder PA stage feeding a quadrature RF splitter (Step A 10 ). The next step of the process is to determine the target load line slope for the feeder PA stage based on the operating power range (Step A 12 ). A further step is to determine the input impedance to the quadrature RF splitter that substantially provides the target load line slope (Step A 14 ). The final step of the process is to determine an operating frequency range of the RF PA, such that the target load line slope is further based on the operating frequency range (Step A 16 ). In an alternate embodiment of the process for matching the input impedance to the target load line slope, the final step (Step A 16 ) is omitted. 
       FIG. 27  shows details of the first RF PA  50  illustrated in  FIG. 14  according an alternate embodiment of the first RF PA  50 . The first RF PA  50  illustrated in  FIG. 27  is similar to the first RF PA  50  illustrated in  FIG. 15 , except the first RF PA  50  illustrated in  FIG. 27  further includes a first non-quadrature path power coupler  188 . As previously mentioned, the first quadrature PA path  102  may present a first input impedance at the first single-ended input FSI that is predominantly resistive. Further, the first input impedance may be stable over a wide frequency range and over widely varying antenna loading conditions. As a result, coupling RF power from the first single-ended output FSO may be used for RF power detection or sampling with a high degree of accuracy and directivity. Since the first single-ended input FSI may be directly coupled to the first single-ended output FSO, coupling RF power from the first single-ended output FSO may be equivalent to coupling RF power from the first single-ended input FSI. 
     The first non-quadrature path power coupler  188  is coupled to the first single-ended output FSO and couples a portion of RF power flowing though the first single-ended output FSO to provide a first non-quadrature path power output signal FNPO. In an additional embodiment of the first RF PA  50 , the first non-quadrature path power coupler  188  is coupled to the first single-ended input FSI and couples a portion of RF power flowing though the first single-ended input FSI to provide the first non-quadrature path power output signal FNPO. 
       FIG. 28  shows details of the second RF PA  54  illustrated in  FIG. 14  according an alternate embodiment of the second RF PA  54 . The second RF PA  54  illustrated in  FIG. 28  is similar to the second RF PA  54  illustrated in  FIG. 15 , except the second RF PA  54  illustrated in  FIG. 28  further includes a second non-quadrature path power coupler  190 . As previously mentioned, the second quadrature PA path  106  may present a second input impedance at the second single-ended input SSI that is predominantly resistive. Further, the second input impedance may be stable over a wide frequency range and over widely varying antenna loading conditions. As a result, coupling RF power from the second single-ended output SSO may be used for RF power detection or sampling with a high degree of accuracy and directivity. Since the second single-ended input SSI may be directly coupled to the second single-ended output SSO, coupling RF power from the second single-ended output SSO may be equivalent to coupling RF power from the second single-ended input SSI. 
     The second non-quadrature path power coupler  190  is coupled to the second single-ended output SSO and couples a portion of RF power flowing though the second single-ended output SSO to provide a second non-quadrature path power output signal SNPO. In an additional embodiment of the second RF PA  54 , the second non-quadrature path power coupler  190  is coupled to the second single-ended input SSI and couples a portion of RF power flowing though the second single-ended input SSI to provide the second non-quadrature path power output signal SNPO. 
       FIG. 29  shows details of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , and the first quadrature RF combiner  130  illustrated in  FIG. 22  according to one embodiment of the first in-phase amplification path  126 , the first quadrature-phase amplification path  128 , and the first quadrature RF combiner  130 . The first in-phase combiner impedance matching circuit  148  and the first quadrature-phase combiner impedance matching circuit  158  have been omitted from the first in-phase amplification path  126  and the first quadrature-phase amplification path  128 , respectively. The first quadrature RF combiner  130  includes first phase-shifting circuitry  192  and a first Wilkinson RF combiner  194 . The first phase-shifting circuitry  192  has the first in-phase input FII and the first quadrature-phase input FQI. The first Wilkinson RF combiner  194  has the first quadrature combiner output FCO. 
     During the first PA operating mode, the first phase-shifting circuitry  192  receives and phase-aligns RF signals from the first in-phase final PA stage  146  and the first quadrature-phase final PA stage  156  via the first in-phase input FII and the first quadrature-phase input FQI, respectively, to provide phase-aligned RF signals to the first Wilkinson RF combiner  194 . The first Wilkinson RF combiner  194  combines phase-aligned RF signals to provide the first RF output signal FRFO via the first quadrature combiner output FCO. The first phase-shifting circuitry  192  and the first Wilkinson RF combiner  194  may provide stable input impedances presented at the first in-phase input FII and the first quadrature-phase input FQI, respectively, which allows elimination of the first in-phase combiner impedance matching circuit  148  and the first quadrature-phase combiner impedance matching circuit  158 . 
       FIG. 30  shows details of the first feeder PA stage  114 , the first quadrature RF splitter  124 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156  illustrated in  FIG. 29  according to one embodiment of the first feeder PA stage  114 , the first quadrature RF splitter  124 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156 . Further,  FIG. 30  shows a portion of the first phase-shifting circuitry  192  illustrated in  FIG. 29 . 
     The first in-phase final PA stage  146  includes a first in-phase final transistor element  196 , first in-phase biasing circuitry  198 , and a first in-phase collector inductive element LCI. The first quadrature-phase final PA stage  156  includes a first quadrature-phase final transistor element  200 , first quadrature-phase biasing circuitry  202 , and a first quadrature-phase collector inductive element LCQ. The first in-phase final PA impedance matching circuit  144  includes a first in-phase series capacitive element CSI 1 , a second in-phase series capacitive element CSI 2 , and a first in-phase shunt inductive element LUI. The first quadrature-phase final PA impedance matching circuit  154  includes a first quadrature-phase series capacitive element CSQ 1 , a second quadrature-phase series capacitive element CSQ 2 , and a first quadrature-phase shunt inductive element LUQ. 
     The first quadrature RF splitter  124  includes a first pair  204  of tightly coupled inductors and a first isolation port resistive element RI 1 . The first pair  204  of tightly coupled inductors has first parasitic capacitance  206  between the first pair  204  of tightly coupled inductors. Additionally, the first quadrature RF splitter  124  has the first single-ended input FSI, the first in-phase output FIO, and the first quadrature-phase output FQO. The first feeder PA stage  114  includes the first output transistor element  180 , first feeder biasing circuitry  208 , a first DC blocking capacitive element CD 1 , a first base resistive element RB 1 , and a first collector inductive element LC 1 . Additionally, the first feeder PA stage  114  has the first single-ended output FSO. 
     The first output transistor element  180  shown is an NPN bipolar transistor element. Other embodiments of the first output transistor element  180  may use other types of transistor elements, such as field effect transistor elements (FET) elements. The first DC blocking capacitive element CD 1  is coupled between the first feeder PA impedance matching circuit  112  ( FIG. 22 ) and the first base resistive element RB. A base of the first output transistor element  180  and the first feeder biasing circuitry  208  are coupled to the first base resistive element RB 1 . In alternate embodiments of the first feeder PA stage  114 , the first base resistive element RB 1 , the first DC blocking capacitive element CD 1 , or both may be omitted. The first feeder biasing circuitry  208  receives the first driver bias signal FDB. An emitter of the first output transistor element  180  is coupled to a ground. A collector of the first output transistor element  180  is coupled to the first single-ended output FSO. One end of the first collector inductive element LC 1  is coupled to the first single-ended output FSO. An opposite end of the first collector inductive element LC 1  receives the envelope power supply signal EPS. The first single-ended output FSO is coupled to the first single-ended input FSI. 
     During the first PA operating mode, the first output transistor element  180  receives and amplifies an RF signal from the first feeder PA impedance matching circuit  112  ( FIG. 22 ) via the first DC blocking capacitive element CD 1  and the first base resistive element RB 1  to provide the first RF feeder output signal FFO ( FIG. 29 ) to the first single-ended input FSI via the first single-ended output FSO. The envelope power supply signal EPS provides power for amplification via the first collector inductive element LC 1 . The first feeder biasing circuitry  208  biases the first output transistor element  180 . The first driver bias signal FDB provides power for biasing the first output transistor element  180  to the first feeder biasing circuitry  208 . 
     The first quadrature RF splitter  124  illustrated in  FIG. 30  is a quadrature hybrid coupler. In this regard, the first pair  204  of tightly coupled inductors, the first parasitic capacitance  206 , and the first isolation port resistive element RI 1  provide quadrature hybrid coupler functionality. As such, the first single-ended input FSI functions as an input port to the quadrature hybrid coupler, the first in-phase output FIO functions as a zero degree output port from the quadrature hybrid coupler, and the first quadrature-phase output FQO functions as a 90 degree output port from the quadrature hybrid coupler. One of the first pair  204  of tightly coupled inductors is coupled between the first single-ended input FSI and the first in-phase output FIO. Another of the first pair  204  of tightly coupled inductors has a first end coupled to the first quadrature-phase output FQO and a second end coupled to the first isolation port resistive element RI 1 . As such, the second end functions as an isolation port of the quadrature hybrid coupler. In this regard, the first isolation port resistive element RI 1  is coupled between the isolation port and the ground. The first in-phase output FIO is coupled to the first in-phase series capacitive element CSI 1  and the first quadrature-phase output FQO is coupled to the first quadrature-phase series capacitive element CSQ 1 . 
     During the first PA operating mode, the first pair  204  of tightly coupled inductors receives, splits, and phase-shifts the first RF feeder output signal FFO ( FIG. 29 ) from the first single-ended output FSO via the first single-ended input FSI to provide split, phase-shifted output signals to the first in-phase series capacitive element CSI 1  and the first quadrature-phase series capacitive element CSQ 1 . As previously mentioned, the first input impedance is presented at the first single-ended input FSI. As such, the first input impedance is substantially based on the first parasitic capacitance  206  and inductances of the first pair  204  of tightly coupled inductors. 
     The first in-phase series capacitive element CSI 1  and the second in-phase series capacitive element CSI 2  are coupled in series between the first in-phase output FIO and a base of the first in-phase final transistor element  196 . The first in-phase shunt inductive element LUI is coupled between the ground and a junction between the first in-phase series capacitive element CSI 1  and the second in-phase series capacitive element CSI 2 . The first quadrature-phase series capacitive element CSQ 1  and the second quadrature-phase series capacitive element CSQ 2  are coupled in series between the first quadrature-phase output FQO and a base of the first quadrature-phase final transistor element  200 . The first quadrature-phase shunt inductive element LUQ is coupled between the ground and a junction between the first quadrature-phase series capacitive element CSQ 1  and the second quadrature-phase series capacitive element CSQ 2 . 
     The first in-phase series capacitive element CSI 1 , the second in-phase series capacitive element CSI 2 , and the first in-phase shunt inductive element LUI form a “T” network, which may provide at least an approximate impedance match between the first in-phase output FIO and the base of the first in-phase final transistor element  196 . Similarly, the first quadrature-phase series capacitive element CSQ 1 , the second quadrature-phase series capacitive element CSQ 2 , and the first quadrature-phase shunt inductive element LUQ form a “T” network, which may provide at least an approximate impedance match between the first quadrature-phase output FQO and the base of the first quadrature-phase final transistor element  200 . 
     During the first PA operating mode, the first in-phase final PA impedance matching circuit  144  receives and forwards an RF signal from the first in-phase output FIO to the base of the first in-phase final transistor element  196  via the first in-phase series capacitive element CSI 1  and the second in-phase series capacitive element CSI 2 . During the first PA operating mode, the first quadrature-phase final PA impedance matching circuit  154  receives and forwards an RF signal from the first quadrature-phase output FQO to the base of the first quadrature-phase final transistor element  200  via the first quadrature-phase series capacitive element CSQ 1  and the second quadrature-phase series capacitive element CSQ 2 . 
     The first in-phase final transistor element  196  shown is an NPN bipolar transistor element. Other embodiments of the first in-phase final transistor element  196  may use other types of transistor elements, such as FET elements. The base of the first in-phase final transistor element  196  and the first in-phase biasing circuitry  198  are coupled to the second in-phase series capacitive element CSI 2 . The first in-phase biasing circuitry  198  receives the first final bias signal FFB. An emitter of the first in-phase final transistor element  196  is coupled to the ground. A collector of the first in-phase final transistor element  196  is coupled to the first in-phase input FII. One end of the first in-phase collector inductive element LCI is coupled to the collector of the first in-phase final transistor element  196 . An opposite end of the first in-phase collector inductive element LCI receives the envelope power supply signal EPS. 
     During the first PA operating mode, the first in-phase final transistor element  196  receives and amplifies an RF signal from the second in-phase series capacitive element CSI 2  to provide an RF output signal to the first in-phase input FII. The envelope power supply signal EPS provides power for amplification via the first in-phase collector inductive element LCI. The first in-phase biasing circuitry  198  biases the first in-phase final transistor element  196 . The first final bias signal FFB provides power for biasing the first in-phase final transistor element  196  to the first in-phase biasing circuitry  198 . 
     The first quadrature-phase final transistor element  200  shown is an NPN bipolar transistor element. Other embodiments of the first quadrature-phase final transistor element  200  may use other types of transistor elements, such as FET elements. The base of the first quadrature-phase final transistor element  200  and the first quadrature-phase biasing circuitry  202  are coupled to the second quadrature-phase series capacitive element CSQ 2 . The first quadrature-phase biasing circuitry  202  receives the first final bias signal FFB. An emitter of the first quadrature-phase final transistor element  200  is coupled to the ground. A collector of the first quadrature-phase final transistor element  200  is coupled to the first quadrature-phase input FQI. One end of the first quadrature-phase collector inductive element LCQ is coupled to the collector of the first quadrature-phase final transistor element  200 . An opposite end of the first quadrature-phase collector inductive element LCQ receives the envelope power supply signal EPS. 
     During the first PA operating mode, the first quadrature-phase final transistor element  200  receives and amplifies an RF signal from the second quadrature-phase series capacitive element CSQ 2  to provide an RF output signal to the first quadrature-phase input FQI. The envelope power supply signal EPS provides power for amplification via the first quadrature-phase collector inductive element LCQ. The first quadrature-phase biasing circuitry  202  biases the first quadrature-phase final transistor element  200 . The first final bias signal FFB provides power for biasing the first quadrature-phase final transistor element  200  to the first quadrature-phase biasing circuitry  202 . 
     In one embodiment of the RF PA circuitry  30  ( FIG. 5 ), the RF PA circuitry  30  includes a first PA semiconductor die  210 . In one embodiment of the first PA semiconductor die  210 , the first PA semiconductor die  210  includes the first output transistor element  180 , the first in-phase final transistor element  196 , the first in-phase biasing circuitry  198 , the first quadrature-phase final transistor element  200 , the first quadrature-phase biasing circuitry  202 , the first pair  204  of tightly coupled inductors, the first feeder biasing circuitry  208 , the first in-phase series capacitive element CSI 1 , the second in-phase series capacitive element CSI 2 , the first quadrature-phase series capacitive element CSQ 1 , the second quadrature-phase series capacitive element CSQ 2 , the first isolation port resistive element RI 1 , the first base resistive element RB 1 , and the first DC blocking capacitive element CD 1 . 
     In alternate embodiments of the first PA semiconductor die  210 , the first PA semiconductor die  210  may not include any or all of the first output transistor element  180 , the first in-phase final transistor element  196 , the first in-phase biasing circuitry  198 , the first quadrature-phase final transistor element  200 , the first quadrature-phase biasing circuitry  202 , the first pair  204  of tightly coupled inductors, the first feeder biasing circuitry  208 , the first in-phase series capacitive element CSI 1 , the second in-phase series capacitive element CSI 2 , the first quadrature-phase series capacitive element CSQ 1 , the second quadrature-phase series capacitive element CSQ 2 , the first isolation port resistive element RI 1 , the first base resistive element RB 1 , and the first DC blocking capacitive element CD 1 . 
       FIG. 31  shows details of the first feeder PA stage  114 , the first quadrature RF splitter  124 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156  illustrated in  FIG. 29  according to an alternate embodiment of the first feeder PA stage  114 , the first quadrature RF splitter  124 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156 . Further,  FIG. 31  shows a portion of the first phase-shifting circuitry  192  illustrated in  FIG. 29 . 
     The first feeder PA stage  114 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156  illustrated in  FIG. 31  are similar to the first feeder PA stage  114 , the first in-phase final PA impedance matching circuit  144 , the first in-phase final PA stage  146 , the first quadrature-phase final PA impedance matching circuit  154 , and the first quadrature-phase final PA stage  156  illustrated in  FIG. 30 . The first quadrature RF splitter  124  illustrated in  FIG. 31  is similar to the first quadrature RF splitter  124  illustrated in  FIG. 30 , except the first quadrature RF splitter  124  illustrated in  FIG. 31  further includes a first coupler capacitive element CC 1  coupled between the first pair  204  of tightly coupled inductors and a second coupler capacitive element CC 2  coupled between the first pair  204  of tightly coupled inductors. Specifically, the first coupler capacitive element CC 1  is coupled between the first in-phase output FIO and the first isolation port resistive element RI 1 . The second coupler capacitive element CC 2  is coupled between the first single-ended input FSI and the first quadrature-phase output FQO. 
     The first input impedance is substantially based on the first parasitic capacitance  206 , inductances of the first pair  204  of tightly coupled inductors, the first coupler capacitive element CC 1 , and the second coupler capacitive element CC 2 . In general, the first input impedance is based on the first parasitic capacitance  206  and inductances of the first pair  204  of tightly coupled inductors. The first input impedance is further based on at least one coupler capacitive element, such as the first coupler capacitive element CC 1 , the second coupler capacitive element CC 2 , or both, coupled between the first pair  204  of tightly coupled inductors. In an alternate embodiment of the first quadrature RF splitter  124 , either the first coupler capacitive element CC 1  or the second coupler capacitive element CC 2  is omitted. 
       FIG. 32  shows details of the first phase-shifting circuitry  192  and the first Wilkinson RF combiner  194  illustrated in  FIG. 29  according to one embodiment of the first phase-shifting circuitry  192  and the first Wilkinson RF combiner  194 . The first phase-shifting circuitry  192  includes a first in-phase phase-shift capacitive element CPI 1 , a first quadrature-phase phase-shift capacitive element CPQ 1 , a first in-phase phase-shift inductive element LPI 1 , and a first quadrature-phase phase-shift inductive element LPQ 1 . The first Wilkinson RF combiner  194  includes a first Wilkinson resistive element RW 1 , a first Wilkinson capacitive element CW 1 , a first Wilkinson in-phase side capacitive element CWI 1 , a first Wilkinson quadrature-phase side capacitive element CWQ 1 , a first Wilkinson in-phase side inductive element LWI 1 , a first Wilkinson quadrature-phase side inductive element LWQ 1 , a second DC blocking capacitive element CD 2 , a third DC blocking capacitive element CD 3 , and a fourth DC blocking capacitive element CD 4   
     The first in-phase phase-shift capacitive element CPI 1  is coupled between the first in-phase input FII and a first internal node (not shown). The first in-phase phase-shift inductive element LPI 1  is coupled between the first internal node and the ground. The first quadrature-phase phase-shift inductive element LPQ 1  is coupled between the first quadrature-phase input FQI and a second internal node (not shown). The first quadrature-phase phase-shift capacitive element CPQ 1  is coupled between the second internal node and the ground. The second DC blocking capacitive element CD 2  and the first Wilkinson resistive element RW 1  are coupled in series between the first internal node and the second internal node. The first Wilkinson in-phase side capacitive element CWI 1  is coupled between the first internal node and the ground. The first Wilkinson quadrature-phase side capacitive element CWQ 1  is coupled between the first internal node and the ground. The first Wilkinson in-phase side inductive element LWI 1  is coupled in series with the third DC blocking capacitive element CD 3  between the first internal node and the first quadrature combiner output FCO. The first Wilkinson quadrature-phase side inductive element LWQ 1  is coupled in series with the fourth DC blocking capacitive element CD 4  between the second internal node and the first quadrature combiner output FCO. The first Wilkinson capacitive element CW 1  is coupled between the first quadrature combiner output FCO and the ground. 
       FIG. 33  shows details of the second non-quadrature PA path  104  illustrated in  FIG. 16  and details of the second quadrature PA path  106  illustrated in  FIG. 18  according to one embodiment of the second non-quadrature PA path  104  and the second quadrature PA path  106 . Further,  FIG. 33  shows details of the second quadrature RF combiner  138  illustrated in  FIG. 18  according to one embodiment of the second quadrature RF combiner  138  illustrated in  FIG. 18 . The second input PA impedance matching circuit  116 , the second input PA stage  118 , the second in-phase driver PA impedance matching circuit  160 , the second in-phase driver PA stage  162 , the second in-phase combiner impedance matching circuit  168 , the second quadrature-phase driver PA impedance matching circuit  170 , the second quadrature-phase driver PA stage  172 , and the second quadrature-phase combiner impedance matching circuit  178  have been omitted from the second non-quadrature PA path  104  and the second quadrature PA path  106 . 
     The second quadrature RF combiner  138  includes second phase-shifting circuitry  212  and a second Wilkinson RF combiner  214 . The second phase-shifting circuitry  212  has the second in-phase input SII and the second quadrature-phase input SQI, and the second Wilkinson RF combiner  214  has the second quadrature combiner output SCO. 
     During the second PA operating mode, the second phase-shifting circuitry  212  receives and phase-aligns RF signals from the second in-phase final PA stage  166  and the second quadrature-phase final PA stage  176  via the second in-phase input SII and the second quadrature-phase input SQI, respectively, to provide phase-aligned RF signals to the second Wilkinson RF combiner  214 . The second Wilkinson RF combiner  214  combines phase-aligned RF signals to provide the second RF output signal SRFO via the second quadrature combiner output SCO. The second phase-shifting circuitry  212  and the second Wilkinson RF combiner  214  may provide stable input impedances presented at the second in-phase input SII and the second quadrature-phase input SQI, respectively, which allows elimination of the second in-phase combiner impedance matching circuit  168  and the second quadrature-phase combiner impedance matching circuit  178 . 
       FIG. 34  shows details of the second feeder PA stage  122 , the second quadrature RF splitter  132 , the second in-phase final PA impedance matching circuit  164 , the second in-phase final PA stage  166 , the second quadrature-phase final PA impedance matching circuit  174 , and the second quadrature-phase final PA stage  176  illustrated in  FIG. 33  according to one embodiment of the second feeder PA stage  122 , the second quadrature RF splitter  132 , the second in-phase final PA impedance matching circuit  164 , the second in-phase final PA stage  166 , the second quadrature-phase final PA impedance matching circuit  174 , and the second quadrature-phase final PA stage  176 . Further,  FIG. 34  shows a portion of the second phase-shifting circuitry  212  illustrated in  FIG. 33 . 
     The second in-phase final PA stage  166  includes a second in-phase final transistor element  216 , second in-phase biasing circuitry  218 , and a second in-phase collector inductive element LLI. The second quadrature-phase final PA stage  176  includes a second quadrature-phase final transistor element  220 , a second quadrature-phase biasing circuitry  222 , and a second quadrature-phase collector inductive element LLQ. The second in-phase final PA impedance matching circuit  164  includes a third in-phase series capacitive element CSI 3 , a fourth in-phase series capacitive element CSI 4 , and a second in-phase shunt inductive element LNI. The second quadrature-phase final PA impedance matching circuit  174  includes a third quadrature-phase series capacitive element CSQ 3 , a fourth quadrature-phase series capacitive element CSQ 4 , and a second quadrature-phase shunt inductive element LNQ. 
     The second quadrature RF splitter  132  includes a second pair  224  of tightly coupled inductors and a second isolation port resistive element R 12 . The second pair  224  of tightly coupled inductors has second parasitic capacitance  226  between the second pair  224  of tightly coupled inductors. Additionally, the second quadrature RF splitter  132  has the second single-ended input SSI, the second in-phase output SIO, and the second quadrature-phase output SQO. The second feeder PA stage  122  includes a second output transistor element  228 , second feeder biasing circuitry  230 , a fifth DC blocking capacitive element CD 5 , a second base resistive element RB 2 , and a second collector inductive element LC 2 . Additionally, the second feeder PA stage  122  has the second single-ended output SSO. 
     The second output transistor element  228  shown is an NPN bipolar transistor element. Other embodiments of the second output transistor element  228  may use other types of transistor elements, such as field effect transistor elements (FET) elements. The fifth DC blocking capacitive element CD 5  is coupled between the second feeder PA impedance matching circuit  120  ( FIG. 33 ) and the second base resistive element RB 2 . A base of the second output transistor element  228  and the second feeder biasing circuitry  230  are coupled to the second base resistive element RB 2 . In alternate embodiments of the second feeder PA stage  122 , the second base resistive element RB 2 , the fifth DC blocking capacitive element CD 5 , or both may be omitted. The second feeder biasing circuitry  230  receives the second driver bias signal SDB. An emitter of the second output transistor element  228  is coupled to a ground. A collector of the second output transistor element  228  is coupled to the second single-ended output SSO. One end of the second collector inductive element LC 2  is coupled to the second single-ended output SSO. An opposite end of the second collector inductive element LC 2  receives the envelope power supply signal EPS. The second single-ended output SSO is coupled to the second single-ended input SSI. 
     During the second PA operating mode, the second output transistor element  228  receives and amplifies an RF signal from the second feeder PA impedance matching circuit  120  ( FIG. 33 ) via the fifth DC blocking capacitive element CD 5  and the second base resistive element RB 2  to provide the second RF feeder output signal SFO ( FIG. 33 ) to the second single-ended input SSI via the second single-ended output SSO. The envelope power supply signal EPS provides power for amplification via the second collector inductive element LC 2 . The second feeder biasing circuitry  230  biases the second output transistor element  228 . The second driver bias signal SDB provides power for biasing the second output transistor element  228  to the second feeder biasing circuitry  230 . 
     The second quadrature RF splitter  132  illustrated in  FIG. 34  is a quadrature hybrid coupler. In this regard, the second pair  224  of tightly coupled inductors, the second parasitic capacitance  226 , and the second isolation port resistive element R 12  provide quadrature hybrid coupler functionality. As such, the second single-ended input SSI functions as an input port to the quadrature hybrid coupler, the second in-phase output SIO functions as a zero degree output port from the quadrature hybrid coupler, and the second quadrature-phase output SQO functions as a 90 degree output port from the quadrature hybrid coupler. One of the second pair  224  of tightly coupled inductors is coupled between the second single-ended input SSI and the second in-phase output SIO. Another of the second pair  224  of tightly coupled inductors has a first end coupled to the second quadrature-phase output SQO and a second end coupled to the second isolation port resistive element R 12 . As such, the second end functions as an isolation port of the quadrature hybrid coupler. In this regard, the second isolation port resistive element R 12  is coupled between the isolation port and the ground. The second in-phase output SIO is coupled to the third in-phase series capacitive element CSI 3  and the second quadrature-phase output SQO is coupled to the third quadrature-phase series capacitive element CSQ 3 . 
     During the second PA operating mode, the second pair  224  of tightly coupled inductors receives, splits, and phase-shifts the second RF feeder output signal SFO ( FIG. 33 ) from the second single-ended output SSO via the second single-ended input SSI to provide split, phase-shifted output signals to the third in-phase series capacitive element CSI 3  and the third quadrature-phase series capacitive element CSQ 3 . As previously mentioned, the second input impedance is presented at the second single-ended input SSI. As such, the second input impedance is substantially based on the second parasitic capacitance  226  and inductances of the second pair  224  of tightly coupled inductors. 
     The third in-phase series capacitive element CSI 3  and the fourth in-phase series capacitive element CSI 4  are coupled in series between the second in-phase output SIO and a base of the second in-phase final transistor element  216 . The second in-phase shunt inductive element LNI is coupled between the ground and a junction between the third in-phase series capacitive element CSI 3  and the fourth in-phase series capacitive element CSI 4 . The third quadrature-phase series capacitive element CSQ 3  and the fourth quadrature-phase series capacitive element CSQ 4  are coupled in series between the second quadrature-phase output SQO and a base of the second quadrature-phase final transistor element  220 . The second quadrature-phase shunt inductive element LNQ is coupled between the ground and a junction between the third quadrature-phase series capacitive element CSQ 3  and the fourth quadrature-phase series capacitive element CSQ 4 . 
     The third in-phase series capacitive element CSI 3 , the fourth in-phase series capacitive element CSI 4 , and the second in-phase shunt inductive element LNI form a “T” network, which may provide at least an approximate impedance match between the second in-phase output SIO and the base of the second in-phase final transistor element  216 . Similarly, the third quadrature-phase series capacitive element CSQ 3 , the fourth quadrature-phase series capacitive element CSQ 4 , and the second quadrature-phase shunt inductive element LNQ form a “T” network, which may provide at least an approximate impedance match between the second quadrature-phase output SQO and the base of the second quadrature-phase final transistor element  220 . 
     During the second PA operating mode, the second in-phase final PA impedance matching circuit  164  receives and forwards an RF signal from the second in-phase output SIO to the base of the second in-phase final transistor element  216  via the third in-phase series capacitive element CSI 3  and the fourth in-phase series capacitive element CSI 4 . During the second PA operating mode, the second quadrature-phase final PA impedance matching circuit  174  receives and forwards an RF signal from the second quadrature-phase output SQO to the base of the second quadrature-phase final transistor element  220  via the third quadrature-phase series capacitive element CSQ 3  and the fourth quadrature-phase series capacitive element CSQ 4 . The second in-phase final transistor element  216  shown is an NPN bipolar transistor element. Other embodiments of the second in-phase final transistor element  216  may use other types of transistor elements, such as FET elements. The base of the second in-phase final transistor element  216  and the second in-phase biasing circuitry  218  are coupled to the fourth in-phase series capacitive element CSI 4 . 
     The second in-phase biasing circuitry  218  receives the second final bias signal SFB. An emitter of the second in-phase final transistor element  216  is coupled to the ground. A collector of the second in-phase final transistor element  216  is coupled to the second in-phase input SII. One end of the second in-phase collector inductive element LLI is coupled to the collector of the second in-phase final transistor element  216 . An opposite end of the second in-phase collector inductive element LLI receives the envelope power supply signal EPS. 
     During the second PA operating mode, the second in-phase final transistor element  216  receives and amplifies an RF signal from the fourth in-phase series capacitive element CSI 4  to provide an RF output signal to the second in-phase input SII. The envelope power supply signal EPS provides power for amplification via the second in-phase collector inductive element LLI. The second in-phase biasing circuitry  218  biases the second in-phase final transistor element  216 . The second final bias signal SFB provides power for biasing the second in-phase final transistor element  216  to the second in-phase biasing circuitry  218 . 
     The second quadrature-phase final transistor element  220  shown is an NPN bipolar transistor element. Other embodiments of the second quadrature-phase final transistor element  220  may use other types of transistor elements, such as FET elements. The base of the second quadrature-phase final transistor element  220  and the second quadrature-phase biasing circuitry  222  are coupled to the fourth quadrature-phase series capacitive element CSQ 4 . The second quadrature-phase biasing circuitry  222  receives the second final bias signal SFB. An emitter of the second quadrature-phase final transistor element  220  is coupled to the ground. A collector of the second quadrature-phase final transistor element  220  is coupled to the second quadrature-phase input SQI. One end of the second quadrature-phase collector inductive element LLQ is coupled to the collector of the second quadrature-phase final transistor element  220 . An opposite end of the second quadrature-phase collector inductive element LLQ receives the envelope power supply signal EPS. 
     During the second PA operating mode, the second quadrature-phase final transistor element  220  receives and amplifies an RF signal from the fourth quadrature-phase series capacitive element CSQ 4  to provide an RF output signal to the second quadrature-phase input SQI. The envelope power supply signal EPS provides power for amplification via the second quadrature-phase collector inductive element LLQ. The second quadrature-phase biasing circuitry  222  biases the second quadrature-phase final transistor element  220 . The second final bias signal SFB provides power for biasing the second quadrature-phase final transistor element  220  to the second quadrature-phase biasing circuitry  222 . 
     In one embodiment of the RF PA circuitry  30  ( FIG. 5 ), the RF PA circuitry  30  includes a second PA semiconductor die  232 . In one embodiment of the second PA semiconductor die  232 , the second PA semiconductor die  232  includes the second output transistor element  228 , second in-phase final transistor element  216 , second in-phase biasing circuitry  218 , the second quadrature-phase final transistor element  220 , second quadrature-phase biasing circuitry  222 , the second pair  224  of tightly coupled inductors, the second feeder biasing circuitry  230 , the third in-phase series capacitive element CSI 3 , the fourth in-phase series capacitive element CSI 4 , the third quadrature-phase series capacitive element CSQ 3 , the fourth quadrature-phase series capacitive element CSQ 4 , the second isolation port resistive element R 12 , the second base resistive element RB 2 , and the fifth DC blocking capacitive element CD 5 . 
     In alternate embodiments of the second PA semiconductor die  232 , the second PA semiconductor die  232  may not include any or all of the second output transistor element  228 , the second in-phase final transistor element  216 , the second in-phase biasing circuitry  218 , the second quadrature-phase final transistor element  220 , the second quadrature-phase biasing circuitry  222 , the second pair  224  of tightly coupled inductors, the second feeder biasing circuitry  230 , the third in-phase series capacitive element CSI 3 , the fourth in-phase series capacitive element CSI 4 , the third quadrature-phase series capacitive element CSQ 3 , the fourth quadrature-phase series capacitive element CSQ 4 , the second isolation port resistive element R 12 , the second base resistive element RB 2 , and the fifth DC blocking capacitive element CD 5 . 
       FIG. 35  shows details of the second phase-shifting circuitry  212  and the second Wilkinson RF combiner  214  illustrated in  FIG. 33  according to one embodiment of the second phase-shifting circuitry  212  and the second Wilkinson RF combiner  214 . The second phase-shifting circuitry  212  includes a second in-phase phase-shift capacitive element CPI 2 , a second quadrature-phase phase-shift capacitive element CPQ 2 , a second in-phase phase-shift inductive element LPI 2 , and a second quadrature-phase phase-shift inductive element LPQ 2 . The second Wilkinson RF combiner  214  includes a second Wilkinson resistive element RW 2 , a second Wilkinson capacitive element CW 2 , a second Wilkinson in-phase side capacitive element CWI 2 , a second Wilkinson quadrature-phase side capacitive element CWQ 2 , a second Wilkinson in-phase side inductive element LWI 2 , a second Wilkinson quadrature-phase side inductive element LWQ 2 , a sixth DC blocking capacitive element CD 6 , a seventh DC blocking capacitive element CD 7 , and a eighth DC blocking capacitive element CD 8 . 
     The second in-phase phase-shift capacitive element CPI 2  is coupled between the second in-phase input SII and a third internal node (not shown). The second in-phase phase-shift inductive element LPI 2  is coupled between the third internal node and the ground. The second quadrature-phase phase-shift inductive element LPQ 2  is coupled between the second quadrature-phase input SQI and a fourth internal node (not shown). The second quadrature-phase phase-shift capacitive element CPQ 2  is coupled between the fourth internal node and the ground. The sixth DC blocking capacitive element CD 6  and the second Wilkinson resistive element RW 2  are coupled in series between the third internal node and the fourth internal node. The second Wilkinson in-phase side capacitive element CWI 2  is coupled between the third internal node and the ground. The second Wilkinson quadrature-phase side capacitive element CWQ 2  is coupled between the third internal node and the ground. The second Wilkinson in-phase side inductive element LWI 2  is coupled in series with the seventh DC blocking capacitive element CD 7  between the third internal node and the second quadrature combiner output SCO. The second Wilkinson quadrature-phase side inductive element LWQ 2  is coupled in series with the eighth DC blocking capacitive element CD 8  between the fourth internal node and the second quadrature combiner output SCO. The second Wilkinson capacitive element CW 2  is coupled between the second quadrature combiner output SCO and the ground. 
       FIG. 36  shows details of the first PA semiconductor die  210  illustrated in  FIG. 30  according to one embodiment of the first PA semiconductor die  210 . The first PA semiconductor die  210  includes a first substrate and functional layers  234 , multiple insulating layers  236 , and multiple metallization layers  238 . Some of the insulating layers  236  may be used to separate some of the metallization layers  238  from one another. In one embodiment of the metallization layers  238 , each of the metallization layers  238  is about parallel to at least another of the metallization layers  238 . In this regard the metallization layers  238  may be planar. In an alternate embodiment of the metallization layers  238 , the metallization layers  238  are formed over a non-planar structure, such that spacing between pairs of the metallization layers  238  is about constant. In one embodiment of the metallization layers  238 , each of the first pair  204  of tightly coupled inductors ( FIG. 30 ) is constructed using at least one of the metallization layers  238 . 
     Linear Mode and Non-Linear Mode Quadrature PA Circuitry 
     A summary of linear mode and non-linear mode quadrature PA circuitry is presented, followed by a detailed description of the linear mode and non-linear mode quadrature PA circuitry according to one embodiment of the present disclosure. Multi-mode multi-band RF PA circuitry includes a multi-mode multi-band quadrature RF PA coupled to multi-mode multi-band switching circuitry via a single output. The switching circuitry provides at least one non-linear mode output and multiple linear mode outputs. The non-linear mode output may be associated with at least one non-linear mode RF communications band and each linear mode output may be associated with a corresponding linear mode RF communications band. The outputs from the switching circuitry may be coupled to an antenna port via front-end aggregation circuitry. The quadrature nature of the quadrature PA path may provide tolerance for changes in antenna loading conditions. 
     One embodiment of the RF PA circuitry includes a highband multi-mode multi-band quadrature RF PA coupled to highband multi-mode multi-band switching circuitry and a lowband multi-mode multi-band quadrature RF PA coupled to lowband multi-mode multi-band switching circuitry. The highband switching circuitry may be associated with at least one highband non-linear mode RF communications band and multiple highband linear mode RF communications bands. The lowband switching circuitry may be associated with at least one lowband non-linear mode RF communications band and multiple lowband linear mode RF communications bands. 
       FIG. 37  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to one embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 37  is similar to the RF PA circuitry  30  illustrated in  FIG. 8 , except in the RF PA circuitry  30  illustrated in  FIG. 37 , the first RF PA  50  is a first multi-mode multi-band quadrature RF PA; the second RF PA  54  is a second multi-mode multi-band quadrature RF PA; the alpha switching circuitry  52  is multi-mode multi-band RF switching circuitry; the first RF PA  50  includes a single alpha PA output SAP; the second RF PA  54  includes a single beta PA output SBP; the alpha switching circuitry  52  further includes a first alpha non-linear mode output FANO, a first alpha linear mode output FALO, and up to and including an R TH  alpha linear mode output RALO; and the beta switching circuitry  56  further includes a first beta non-linear mode output FBNO, a first beta linear mode output FBLO, and up to and including an S TH  beta linear mode output SBLO. In general, the alpha switching circuitry  52  includes a group of alpha linear mode outputs FALO, RALO and the beta switching circuitry  56  includes a group of beta linear mode outputs FBLO, SBLO. 
     The first RF PA  50  is coupled to the alpha switching circuitry  52  via the single alpha PA output SAP. The second RF PA  54  is coupled to the beta switching circuitry  56  via the single beta PA output SBP. In one embodiment of the first RF PA  50 , the single alpha PA output SAP is a single-ended output. In one embodiment of the second RF PA  54 , the single beta PA output SBP is a single-ended output. In one embodiment of the alpha switching circuitry  52 , the first alpha non-linear mode output FANO is associated with a first non-linear mode RF communications band and each of the group of alpha linear mode outputs FALO, RALO is associated with a corresponding one of a first group of linear mode RF communications bands. In one embodiment of the beta switching circuitry  56 , the first beta non-linear mode output FBNO is associated with a second non-linear mode RF communications band and each of the group of beta linear mode outputs FBLO, SBLO is associated with a corresponding one of a second group of linear mode RF communications bands. 
     In an alternate embodiment of the alpha switching circuitry  52 , the first alpha non-linear mode output FANO is associated with a first group of non-linear mode RF communications bands, which includes the first non-linear mode RF communications band. In an alternate embodiment of the beta switching circuitry  56 , the first beta non-linear mode output FBNO is associated with a second group of non-linear mode RF communications bands, which includes the second non-linear mode RF communications band. 
     In one embodiment of the RF communications system  26  ( FIG. 5 ), the RF communications system  26  operates in one of a group of communications modes. Control circuitry, which may include the control circuitry  42  ( FIG. 5 ), the PA control circuitry  94  ( FIG. 13 ), or both, selects one of the group of communications modes. In one embodiment of the RF communications system  26 , the group of communications modes includes a first alpha non-linear mode and a group of alpha linear modes. In an alternate embodiment of the RF communications system  26 , the group of communications modes includes the first alpha non-linear mode, the group of alpha linear modes, a first beta non-linear mode, and a group of beta non-linear modes. In an additional embodiment of the RF communications system  26 , the group of communications modes includes a group of alpha non-linear modes, the group of alpha linear modes, a group of beta non-linear modes, and the group of beta non-linear modes. Other embodiments of the RF communications system  26  may omit any or all of the communications modes. In one embodiment of the first alpha non-linear mode, the first alpha non-linear mode is a half-duplex mode. In one embodiment of the first beta non-linear mode, the beta alpha non-linear mode is a half-duplex mode. In one embodiment of the group of alpha linear modes, each of the group of alpha linear modes is a full-duplex mode. In one embodiment of the group of beta linear modes, each of the group of beta linear modes is a full-duplex mode. 
     In one embodiment of the first RF PA  50 , during the first alpha non-linear mode and during each of the group of alpha linear modes, the first RF PA  50  receives and amplifies the first RF input signal FRFI to provide the first RF output signal FRFO via the single alpha PA output SAP. Further, during the first beta non-linear mode and during each of the group of beta linear modes, the first RF PA  50  does not receive or amplify the first RF input signal FRFI to provide the first RF output signal FRFO. 
     In one embodiment of the second RF PA  54 , during the first beta non-linear mode and during each of the group of beta linear modes, the second RF PA  54  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO via the single beta PA output SBP. Further, during the first alpha non-linear mode and during each of the group of alpha linear modes, the second RF PA  54  does not receive or amplify the second RF input signal SRFI to provide the second RF output signal SRFO. 
     In one embodiment of the alpha switching circuitry  52 , during the first alpha non-linear mode, the alpha switching circuitry  52  receives and forwards the first RF output signal FRFO to provide the first alpha RF transmit signal FATX via the first alpha non-linear mode output FANO. During a first alpha linear mode, the alpha switching circuitry  52  receives and forwards the first RF output signal FRFO to provide the second alpha RF transmit signal SATX via the first alpha linear mode output FALO. During an R TH  alpha linear mode, the alpha switching circuitry  52  receives and forwards the first RF output signal FRFO to provide the P TH  alpha RF transmit signal PATX. In general, during each of the group of alpha linear modes, the alpha switching circuitry  52  receives and forwards the first RF output signal FRFO to provide a corresponding one of a group of alpha RF transmit signals SATX, PATX via a corresponding one of the group of alpha linear mode outputs FALO, RALO. 
     In one embodiment of the beta switching circuitry  56 , during the first beta non-linear mode, the beta switching circuitry  56  receives and forwards the second RF output signal SRFO to provide the first beta RF transmit signal FBTX via the first beta non-linear mode output FBNO. During a first beta linear mode, the beta switching circuitry  56  receives and forwards the second RF output signal SRFO to provide the second beta RF transmit signal SBTX via the first beta linear mode output FBLO. During an S TH  beta linear mode, the beta switching circuitry  56  receives and forwards the second RF output signal SRFO to provide the Q TH  beta RF transmit signal QBTX. In general, during each of the group of beta linear modes, the beta switching circuitry  56  receives and forwards the second RF output signal SRFO to provide a corresponding one of a group of beta RF transmit signals SBTX, QBTX via a corresponding one of the group of beta linear mode outputs FBLO, SBLO. 
       FIG. 38  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to an alternate embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 38  is similar to the RF PA circuitry  30  illustrated in  FIG. 9 , except in the RF PA circuitry  30  illustrated in  FIG. 38 , the first RF PA  50  is the first multi-mode multi-band quadrature RF PA; the second RF PA  54  is the second multi-mode multi-band quadrature RF PA; the alpha switching circuitry  52  is multi-mode multi-band RF switching circuitry; the first RF PA  50  includes the single alpha PA output SAP; the second RF PA  54  includes the single beta PA output SBP; the alpha switching circuitry  52  further includes the first alpha non-linear mode output FANO, a second alpha non-linear mode output SANO, the first alpha linear mode output FALO, and up to and including the R TH  alpha linear mode output RALO; and the beta switching circuitry  56  further includes the first beta non-linear mode output FBNO, a second beta non-linear mode output SBNO, the first beta linear mode output FBLO, and up to and including the S TH  beta linear mode output SBLO. In general, the alpha switching circuitry  52  includes the group of alpha linear mode outputs FALO, RALO and the beta switching circuitry  56  includes the group of beta linear mode outputs FBLO, SBLO. 
       FIG. 39  shows details of the RF PA circuitry  30  illustrated in  FIG. 5  according to an additional embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 39  is similar to the RF PA circuitry  30  illustrated in  FIG. 37 , except the RF PA circuitry  30  illustrated in  FIG. 39  further includes the switch driver circuitry  98  ( FIG. 13 ) and shows details of the alpha RF switch  68  and the beta RF switch  72 . The alpha RF switch  68  includes a first alpha switching device  240 , a second alpha switching device  242 , and a third alpha switching device  244 . The beta RF switch  72  includes a first beta switching device  246 , a second beta switching device  248 , and a third beta switching device  250 . Alternate embodiments of the alpha RF switch  68  may includes any number of alpha switching devices. Alternate embodiments of the beta RF switch  72  may include any number of beta switching devices. 
     The first alpha switching device  240  is coupled between the single alpha PA output SAP and the first alpha harmonic filter  70 . As such, the first alpha switching device  240  is coupled between the single alpha PA output SAP and the first alpha non-linear mode output FANO via the first alpha harmonic filter  70 . The second alpha switching device  242  is coupled between the single alpha PA output SAP and the first alpha linear mode output FALO. The third alpha switching device  244  is coupled between the single alpha PA output SAP and the R TH  alpha linear mode output RALO. In general, the alpha RF switch  68  includes the first alpha switching device  240  and a group of alpha switching devices, which includes the second alpha switching device  242  and the third alpha switching device  244 . As previously mentioned, the alpha switching circuitry  52  includes the group of alpha linear mode outputs FALO, RALO. As such, each of the group of alpha switching devices  242 ,  244  is coupled between the single alpha PA output SAP and a corresponding one of the group of alpha linear mode outputs FALO, RALO. Additionally, each of the alpha switching devices  240 ,  242 ,  244  has a corresponding control input, which is coupled to the switch driver circuitry  98 . 
     The first beta switching device  246  is coupled between the single beta PA output SBP and the first beta harmonic filter  74 . As such, the first beta switching device  246  is coupled between the single beta PA output SBP and the first beta non-linear mode output FBNO via the first beta harmonic filter  74 . The second beta switching device  248  is coupled between the single beta PA output SBP and the first beta linear mode output FBLO. The third beta switching device  250  is coupled between the single beta PA output SBP and the S TH  beta linear mode output SBLO. In general, the beta RF switch  72  includes the first beta switching device  246  and a group of beta switching devices, which includes the second beta switching device  248  and the third beta switching device  250 . As previously mentioned, the beta switching circuitry  56  includes the group of beta linear mode outputs FBLO, SBLO. As such, each of the group of beta switching devices  248 ,  250  is coupled between the single beta PA output SBP and a corresponding one of the group of beta linear mode outputs FBLO, SBLO. Additionally, each of the beta switching devices  246 ,  248 ,  250  has a corresponding control input, which is coupled to the switch driver circuitry  98 . 
     In one embodiment of the alpha RF switch  68 , the first alpha switching device  240  includes multiple switching elements (not shown) coupled in series. Each of the group of alpha switching devices  242 ,  244  includes multiple switching elements (not shown) coupled in series. In one embodiment of the beta RF switch  72 , the first beta switching device  246  includes multiple switching elements (not shown) coupled in series. Each of the group of beta switching devices  248 ,  250  includes multiple switching elements (not shown) coupled in series. 
     PA Bias Supply Using Boosted Voltage 
     A summary of a PA bias supply using boosted voltage is presented, followed by a detailed description of the PA bias supply using boosted voltage according to one embodiment of the present disclosure. An RF PA bias power supply signal is provided to RF PA circuitry by boosting a voltage from a DC power supply, such as a battery. In this regard, a DC-DC converter receives a DC power supply signal from the DC power supply. The DC-DC converter provides the bias power supply signal based on the DC power supply signal, such that a voltage of the bias power supply signal is greater than a voltage of the DC power supply signal. The RF PA circuitry has an RF PA, which has a final stage that receives a final bias signal to bias the final stage, such that the final bias signal is based on the bias power supply signal. Boosting the voltage from the DC power supply may provide greater flexibility in biasing the RF PA. 
     In one embodiment of the DC-DC converter, the DC-DC converter includes a charge pump, which may receive and pump-up the DC power supply signal to provide the bias power supply signal. Further, the DC-DC converter may operate in one of a bias supply pump-up operating mode and at least one other operating mode, which may include any or all of a bias supply pump-even operating mode, a bias supply pump-down operating mode, and a bias supply bypass operating mode. Additionally, the DC-DC converter provides an envelope power supply signal to the RF PA, which uses the envelope power supply signal to provide power for amplification. In one embodiment of the RF PA circuitry, the RF PA circuitry includes PA bias circuitry, which receives the bias power supply signal to provide the final bias signal. The PA bias circuitry may include a final stage current analog-to-digital converter (IDAC) to receive and use the bias power supply signal in a digital-to-analog conversion to provide the final bias signal. 
     In an alternate embodiment of the RF PA circuitry, the RF PA circuitry includes a first RF PA and a second RF PA, which include a first final stage and a second final stage, respectively. The first RF PA may be used to receive and amplify a highband RF input signal and the second RF PA may be used to receive and amplify a lowband RF input signal. The RF PA circuitry operates in one of a first PA operating mode and a second PA operating mode, such that during the first PA operating mode, the first RF PA is active and the second RF PA is disabled. Conversely, during the second PA operating mode, the first RF PA is disabled and the second RF PA is active. The PA bias circuitry may include the final stage IDAC and a final stage multiplexer. The final stage IDAC receives and uses the bias power supply signal in a digital-to-analog conversion to provide a final stage bias signal to the final stage multiplexer. During the first PA operating mode, the final stage multiplexer receives and forwards the final stage bias signal to provide a first final bias signal to the first RF PA to bias the first final stage. During the second PA operating mode, the final stage multiplexer receives and forwards the final stage bias signal to provide a second final bias signal to the second RF PA to bias the second final stage. 
       FIG. 40  shows details of the first RF PA  50 , the second RF PA  54 , and the PA bias circuitry  96  illustrated in  FIG. 13  according to one embodiment of the first RF PA  50 , the second RF PA  54 , and the PA bias circuitry  96 . The first RF PA  50  includes a first driver stage  252  and a first final stage  254 . The second RF PA  54  includes a second driver stage  256  and a second final stage  258 . The PA bias circuitry  96  includes driver stage IDAC circuitry  260  and final stage IDAC circuitry  262 . In general, the first RF PA  50  receives and amplifies the first RF input signal FRFI to provide the first RF output signal FRFO. Similarly, the second RF PA  54  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO. Specifically, the first driver stage  252  receives and amplifies the first RF input signal FRFI to provide a first final stage input signal FFSI, and the first final stage  254  receives and amplifies the first final stage input signal FFSI to provide the first RF output signal FRFO. Similarly, the second driver stage  256  receives and amplifies the second RF input signal SRFI to provide a second final stage input signal SFSI, and the second final stage  258  receives and amplifies the second final stage input signal SFSI to provide the second RF output signal SRFO. 
     The first driver stage  252  receives the envelope power supply signal EPS, which provides power for amplification; the first final stage  254  receives the envelope power supply signal EPS, which provides power for amplification; the second driver stage  256  receives the envelope power supply signal EPS, which provides power for amplification; and the second final stage  258  receives the envelope power supply signal EPS, which provides power for amplification. In general, the first RF PA  50  receives the first driver bias signal FDB to bias first driver stage  252  and receives the first final bias signal FFB to bias the first final stage  254 . Specifically, the first driver stage  252  receives the first driver bias signal FDB to bias the first driver stage  252  and the first final stage  254  receives the first final bias signal FFB to bias the first final stage  254 . Similarly, the second RF PA  54  receives the second driver bias signal SDB to bias the second driver stage  256  and receives the second final bias signal SFB to bias the second final stage  258 . Specifically, the second driver stage  256  receives the second driver bias signal SDB to bias the second driver stage  256  and the second final stage  258  receives the second final bias signal SFB to bias the second final stage  258 . 
     In general, the PA bias circuitry  96  provides the first driver bias signal FDB based on the bias power supply signal BPS, the first final bias signal FFB based on the bias power supply signal BPS, the second driver bias signal SDB based on the bias power supply signal BPS, and the second final bias signal SFB based on the bias power supply signal BPS. Specifically, the driver stage IDAC circuitry  260  provides the first driver bias signal FDB based on the bias power supply signal BPS and provides the second driver bias signal SDB based on the bias power supply signal BPS. Similarly, the final stage IDAC circuitry  262  provides the first final bias signal FFB based on the bias power supply signal BPS and provides the second final bias signal SFB based on the bias power supply signal BPS. 
     In one embodiment of the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262 , the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262  receive the bias power supply signal BPS and the bias configuration control signal BCC. The driver stage IDAC circuitry  260  provides the first driver bias signal FDB and the second driver bias signal SDB based on the bias power supply signal BPS and the bias configuration control signal BCC. The final stage IDAC circuitry  262  provides the first final bias signal FFB and the second final bias signal SFB based on the bias power supply signal BPS and the bias configuration control signal BCC. The bias power supply signal BPS provides the power necessary to generate the bias signals FDB, FFB, SDB, SFB. A selected magnitude of each of the bias signals FDB, FFB, SDB, SFB is provided by the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262 . In one embodiment of the RF PA circuitry  30 , the PA control circuitry  94  selects the magnitude of any or all of the bias signals FDB, FFB, SDB, SFB and communicates the magnitude selections to the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262  via the bias configuration control signal BCC. The magnitude selections by the PA control circuitry  94  may be based on the PA configuration control signal PCC. In an alternate embodiment of the RF PA circuitry  30 , the control circuitry  42  ( FIG. 5 ) selects the magnitude of any or all of the bias signals FDB, FFB, SDB, SFB and communicates the magnitude selections to the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262  via the PA control circuitry  94 . 
     As previously discussed, in one embodiment of the RF PA circuitry  30 , the RF PA circuitry  30  operates in one of the first PA operating mode and the second PA operating mode. During the first PA operating mode, the first RF PA  50  receives and amplifies the first RF input signal FRFI to provide the first RF output signal FRFO, and the second RF PA  54  is disabled. During the second PA operating mode, the second RF PA  54  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO, and the first RF PA  50  is disabled. 
     In one embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via the first driver bias signal FDB. As such, the first driver stage  252  is disabled. In an alternate embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via the first final bias signal FFB. As such, the first final stage  254  is disabled. In an additional embodiment of the first RF PA  50 , during the second PA operating mode, the first RF PA  50  is disabled via both the first driver bias signal FDB and the first final bias signal FFB. As such, both the first driver stage  252  and the first final stage  254  are disabled. 
     In one embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via the second driver bias signal SDB. As such, the second driver stage  256  is disabled. In an alternate embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via the second final bias signal SFB. As such, the second final stage  258  is disabled. In an additional embodiment of the second RF PA  54 , during the first PA operating mode, the second RF PA  54  is disabled via both the second driver bias signal SDB and the second final bias signal SFB. As such, both the second driver stage  256  and the second final stage  258  are disabled. 
     In one embodiment of the RF PA circuitry  30 , the PA control circuitry  94  selects the one of the first PA operating mode and the second PA operating mode. As such, the PA control circuitry  94  may control any or all of the bias signals FDB, FFB, SDB, SFB via the bias configuration control signal BCC based on the PA operating mode selection. The PA operating mode selection may be based on the PA configuration control signal PCC. In an alternate embodiment of the RF PA circuitry  30 , the control circuitry  42  ( FIG. 5 ) selects the one of the first PA operating mode and the second PA operating mode. As such, the control circuitry  42  ( FIG. 5 ) may indicate the operating mode selection to the PA control circuitry  94  via the PA configuration control signal PCC. In an additional embodiment of the RF PA circuitry  30 , the RF modulation and control circuitry  28  ( FIG. 5 ) selects the one of the first PA operating mode and the second PA operating mode. As such, the RF modulation and control circuitry  28  ( FIG. 5 ) may indicate the operating mode selection to the PA control circuitry  94  via the PA configuration control signal PCC. In general, selection of the PA operating mode is made by control circuitry, which may be any of the PA control circuitry  94 , the RF modulation and control circuitry  28  ( FIG. 5 ), and the control circuitry  42  ( FIG. 5 ). 
     Further, during the first PA operating mode, the control circuitry selects a desired magnitude of the first driver bias signal FDB, a desired magnitude of the first final bias signal FFB, or both. During the second PA operating mode, the control circuitry selects a desired magnitude of the second driver bias signal SDB, a desired magnitude of the second final bias signal SFB, or both As such, during the first PA operating mode, the PA control circuitry  94  provides the bias configuration control signal BCC to the PA bias circuitry  96  in general and to the driver stage IDAC circuitry  260  in particular based on the desired magnitude of the first driver bias signal FDB, and the PA control circuitry  94  provides the bias configuration control signal BCC to the PA bias circuitry  96  in general and to the final stage IDAC circuitry  262  in particular based on the desired magnitude of the first final bias signal FFB. During the second PA operating mode, the PA control circuitry  94  provides the bias configuration control signal BCC to the PA bias circuitry  96  in general and to the driver stage IDAC circuitry  260  in particular based on the desired magnitude of the second driver bias signal SDB, and the PA control circuitry  94  provides the bias configuration control signal BCC to the PA bias circuitry  96  in general and to the final stage IDAC circuitry  262  in particular based on the desired magnitude of the second final bias signal SFB. In one embodiment of the PA control circuitry  94 , the bias configuration control signal BCC is a digital signal. 
       FIG. 41  shows details of the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262  illustrated in  FIG. 40  according to one embodiment of the driver stage IDAC circuitry  260  and the final stage IDAC circuitry  262 . The driver stage IDAC circuitry  260  includes a driver stage IDAC  264 , a driver stage multiplexer  266 , and driver stage current reference circuitry  268 . The final stage IDAC circuitry  262  includes a final stage IDAC  270 , a final stage multiplexer  272 , and final stage current reference circuitry  274 . 
     The driver stage IDAC  264  receives the bias power supply signal BPS, the bias configuration control signal BCC, and a driver stage reference current IDSR. As such, the driver stage IDAC  264  uses the bias power supply signal BPS and the driver stage reference current IDSR in a digital-to-analog conversion to provide a driver stage bias signal DSBS. A magnitude of the digital-to-analog conversion is based on the bias configuration control signal BCC. The driver stage current reference circuitry  268  provides the driver stage reference current IDSR to the driver stage IDAC  264 , such that during the first PA operating mode, the first driver bias signal FDB is based on the driver stage reference current IDSR, and during the second PA operating mode, the second driver bias signal SDB is based on the driver stage reference current IDSR. The driver stage current reference circuitry  268  may be disabled based on the bias configuration control signal BCC. The driver stage current reference circuitry  268  and the driver stage multiplexer  266  receive the bias configuration control signal BCC. The driver stage multiplexer  266  receives and forwards the driver stage bias signal DSBS, which is a current signal, to provide either the second driver bias signal SDB or the first driver bias signal FDB based on the bias configuration control signal BCC. During the first PA operating mode, the driver stage multiplexer  266  receives and forwards the driver stage bias signal DSBS to provide the first driver bias signal FDB based on the bias configuration control signal BCC. During the second PA operating mode, the driver stage multiplexer  266  receives and forwards the driver stage bias signal DSBS to provide the second driver bias signal SDB based on the bias configuration control signal BCC. 
     In this regard, during the first PA operating mode, the driver stage IDAC  264  provides the first driver bias signal FDB via the driver stage multiplexer  266 , such that a magnitude of the first driver bias signal FDB is about equal to the desired magnitude of the first driver bias signal FDB. During the second PA operating mode, the driver stage IDAC  264  provides the second driver bias signal SDB via the driver stage multiplexer  266 , such that a magnitude of the second driver bias signal SDB is about equal to the desired magnitude of the second driver bias signal SDB. 
     In one embodiment of the driver stage multiplexer  266 , during the first PA operating mode, the driver stage multiplexer  266  disables the second RF PA  54  via the second driver bias signal SDB. In one embodiment of the second RF PA  54 , the second RF PA  54  is disabled when the second driver bias signal SDB is about zero volts. In one embodiment of the driver stage multiplexer  266 , during the second PA operating mode, the driver stage multiplexer  266  disables the first RF PA  50  via the first driver bias signal FDB. 
     In one embodiment of the first RF PA  50 , the first RF PA  50  is disabled when the first driver bias signal FDB is about zero volts. As such, in one embodiment of the driver stage multiplexer  266 , during the first PA operating mode, the driver stage multiplexer  266  provides the second driver bias signal SDB, which is about zero volts, such that the second RF PA  54  is disabled, and during the second PA operating mode, the driver stage multiplexer  266  provides the first driver bias signal FDB, which is about zero volts, such that the first RF PA  50  is disabled. 
     The final stage IDAC  270  receives the bias power supply signal BPS, the bias configuration control signal BCC, and a final stage reference current IFSR. As such, the final stage IDAC  270  uses the bias power supply signal BPS and the final stage reference current IFSR in a digital-to-analog conversion to provide a final stage bias signal FSBS. A magnitude of the digital-to-analog conversion is based on the bias configuration control signal BCC. The final stage current reference circuitry  274  provides the final stage reference current IFSR to the final stage IDAC  270 , such that during the first PA operating mode, the first final bias signal FFB is based on the final stage reference current IFSR, and during the second PA operating mode, the second final bias signal SFB is based on the final stage reference current IFSR. The final stage current reference circuitry  274  and the final stage IDAC  270  receive the bias configuration control signal BCC. The final stage current reference circuitry  274  may be disabled based on the bias configuration control signal BCC. The final stage multiplexer  272  receives and forwards the final stage bias signal FSBS, which is a current signal, to provide either the second final bias signal SFB or the first final bias signal FFB based on the bias configuration control signal BCC. During the first PA operating mode, the final stage multiplexer  272  receives and forwards the final stage bias signal FSBS to provide the first final bias signal FFB based on the bias configuration control signal BCC. During the second PA operating mode, the final stage multiplexer  272  receives and forwards the final stage bias signal FSBS to provide the second final bias signal SFB based on the bias configuration control signal BCC. 
     In this regard, during the first PA operating mode, the final stage IDAC  270  provides the first final bias signal FFB via the final stage multiplexer  272 , such that a magnitude of the first final bias signal FFB is about equal to the desired magnitude of the first final bias signal FFB. During the second PA operating mode, the final stage IDAC  270  provides the second final bias signal SFB via the final stage multiplexer  272 , such that a magnitude of the second final bias signal SFB is about equal to the desired magnitude of the second final bias signal SFB. 
     In one embodiment of the final stage multiplexer  272 , during the first PA operating mode, the final stage multiplexer  272  disables the second RF PA  54  via the second final bias signal SFB. In one embodiment of the second RF PA  54 , the second RF PA  54  is disabled when the second final bias signal SFB is about zero volts. In one embodiment of the final stage multiplexer  272 , during the second PA operating mode, the final stage multiplexer  272  disables the first RF PA  50  via the first final bias signal FFB. In one embodiment of the first RF PA  50 , the first RF PA  50  is disabled when the first final bias signal FFB is about zero volts. As such, in one embodiment of the final stage multiplexer  272 , during the first PA operating mode, the final stage multiplexer  272  provides the second final bias signal SFB, which is about zero volts, such that the second RF PA  54  is disabled, and during the second PA operating mode, the final stage multiplexer  272  provides the first final bias signal FFB, which is about zero volts, such that the first RF PA  50  is disabled. 
       FIG. 42  shows details of the driver stage current reference circuitry  268  and the final stage current reference circuitry  274  illustrated in  FIG. 41  according to one embodiment of the driver stage current reference circuitry  268  and the final stage current reference circuitry  274 . The driver stage current reference circuitry  268  includes a driver stage temperature compensation circuit  276  to temperature compensate the driver stage reference current IDSR. The final stage current reference circuitry  274  includes a final stage temperature compensation circuit  278  to temperature compensate the final stage reference current IFSR. 
     Charge Pump Based PA Envelope Power Supply and Bias Power Supply 
     A summary of a charge pump based PA envelope power supply and bias power supply is presented, followed by a detailed description of the charge pump based PA envelope power supply according to one embodiment of the present disclosure. The present disclosure relates to a DC-DC converter, which includes a charge pump based RF PA envelope power supply and a charge pump based PA bias power supply. The DC-DC converter is coupled between RF PA circuitry and a DC power supply, such as a battery. As such, the PA envelope power supply provides an envelope power supply signal to the RF PA circuitry and the PA bias power supply provides a bias power supply signal to the RF PA circuitry. Both the PA envelope power supply and the PA bias power supply receive power via a DC power supply signal from the DC power supply. The PA envelope power supply includes a charge pump buck converter and the PA bias power supply includes a charge pump. 
     By using charge pumps, a voltage of the envelope power supply signal may be greater than a voltage of the DC power supply signal, a voltage of the bias power supply signal may be greater than the voltage of the DC power supply signal, or both. Providing boosted voltages may provide greater flexibility in providing envelope power for amplification and in biasing the RF PA circuitry. The charge pump buck converter provides the functionality of a charge pump feeding a buck converter. However, the charge pump buck converter requires fewer switching elements than a charge pump feeding a buck converter by sharing certain switching elements. 
     The charge pump buck converter is coupled between the DC power supply and the RF PA circuitry. The charge pump is coupled between the DC power supply and the RF PA circuitry. In one embodiment of the PA envelope power supply, the PA envelope power supply further includes a buck converter coupled between the DC power supply and the RF PA circuitry. The PA envelope power supply may operate in one of a first envelope operating mode and a second envelope operating mode. During the first envelope operating mode, the charge pump buck converter is active, and the buck converter is inactive. Conversely, during the second envelope operating mode, the charge pump buck converter is inactive, and the buck converter is active. As such, the PA envelope power supply may operate in the first envelope operating mode when a voltage above the voltage of the DC power supply signal may be needed. Conversely, the PA envelope power supply may operate in the second envelope operating mode when a voltage above the voltage of the DC power supply signal is not needed. 
     In one embodiment of the charge pump buck converter, the charge pump buck converter operates in one of a pump buck pump-up operating mode and at least one other pump buck operating mode, which may include any or all of a pump buck pump-down operating mode, a pump buck pump-even operating mode, and a pump buck bypass operating mode. In one embodiment of the charge pump, the charge pump operates in one of a bias supply pump-up operating mode and at least one other bias supply operating mode, which may include any or all of a bias supply pump-down operating mode, a bias supply pump-even operating mode, and a bias supply bypass operating mode. 
     In one embodiment of the RF PA circuitry, the RF PA circuitry has an RF PA, which is biased based on the bias power supply signal and receives the envelope power supply signal to provide power for amplification. In one embodiment of the RF PA circuitry, the RF PA has a final stage that receives a final bias signal to bias the final stage, such that the final bias signal is based on the bias power supply signal. Additionally, the DC-DC converter provides the envelope power supply signal to the RF PA, which uses the envelope power supply signal to provide power for amplification. In one embodiment of the RF PA circuitry, the RF PA circuitry includes PA bias circuitry, which receives the bias power supply signal to provide the final bias signal. In one embodiment of the PA bias circuitry, the PA bias circuitry includes a final stage IDAC to receive and use the bias power supply signal in a digital-to-analog conversion to provide the final bias signal. 
     In one embodiment of the RF PA circuitry, the RF PA circuitry includes a first RF PA and a second RF PA, which may include a first final stage and a second final stage, respectively. The first RF PA is used to receive and amplify a highband RF input signal and the second RF PA is used to receive and amplify a lowband RF input signal. The RF PA circuitry may operate in one of a first PA operating mode and a second PA operating mode, such that during the first PA operating mode, the first RF PA is active and the second RF PA is disabled. Conversely, during the second PA operating mode, the first RF PA is disabled and the second RF PA is active. The PA bias circuitry includes the final stage IDAC and a final stage multiplexer. The final stage IDAC receives and uses the bias power supply signal in a digital-to-analog conversion to provide a final stage bias signal to the final stage multiplexer. During the first PA operating mode, the final stage multiplexer receives and forwards the final stage bias signal to provide a first final bias signal to the first RF PA to bias the first final stage. During the second PA operating mode, the final stage multiplexer receives and forwards the final stage bias signal to provide a second final bias signal to the second RF PA to bias the second final stage. 
       FIG. 43  shows the RF communications system  26  according to one embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 43  is similar to the RF communications system  26  illustrated in  FIG. 11 ; except in the RF communications system  26  illustrated in  FIG. 43 ; the DC-DC converter  32  shows a PA envelope power supply  280  instead of showing the first power filtering circuitry  82 , the charge pump buck converter  84 , the buck converter  86 , and the first inductive element L 1 ; and shows a PA bias power supply  282  instead of showing the second power filtering circuitry  88  and the charge pump  92 . The PA envelope power supply  280  is coupled to the RF PA circuitry  30  and the PA bias power supply  282  is coupled to the RF PA circuitry  30 . Further, the PA envelope power supply  280  is coupled to the DC power supply  80  and the PA bias power supply  282  is coupled to the DC power supply  80 . 
     The PA bias power supply  282  receives the DC power supply signal DCPS from the DC power supply  80  and provides the bias power supply signal BPS based on DC-DC conversion of the DC power supply signal DCPS. The PA envelope power supply  280  receives the DC power supply signal DCPS from the DC power supply  80  and provides the envelope power supply signal EPS based on DC-DC conversion of the DC power supply signal DCPS. 
       FIG. 44  shows details of the PA envelope power supply  280  and the PA bias power supply  282  illustrated in  FIG. 43  according to one embodiment of the PA envelope power supply  280  and the PA bias power supply  282 . The PA envelope power supply  280  includes the charge pump buck converter  84 , the first inductive element L 1 , and the first power filtering circuitry  82 . The PA bias power supply  282  includes the charge pump  92 . In general, the charge pump buck converter  84  is coupled between the RF PA circuitry  30  and the DC power supply  80 . Specifically, the first inductive element L 1  is coupled between the charge pump buck converter  84  and the first power filtering circuitry  82 . The charge pump buck converter  84  is coupled between the DC power supply  80  and the first inductive element L 1 . The first power filtering circuitry  82  is coupled between the first inductive element L 1  and the RF PA circuitry  30 . The charge pump  92  is coupled between the RF PA circuitry  30  and the DC power supply  80 . 
     The charge pump buck converter  84  receives and converts the DC power supply signal DCPS to provide the first buck output signal FBO, such that the envelope power supply signal EPS is based on the first buck output signal FBO. The charge pump  92  receives and charge pumps the DC power supply signal DCPS to provide the bias power supply signal BPS. 
       FIG. 45  shows details of the PA envelope power supply  280  and the PA bias power supply  282  illustrated in  FIG. 43  according to an alternate embodiment of the PA envelope power supply  280  and the PA bias power supply  282 . The PA envelope power supply  280  illustrated in  FIG. 45  is similar to the PA envelope power supply  280  illustrated in  FIG. 44 , except the PA envelope power supply  280  illustrated in  FIG. 45  further includes the buck converter  86  coupled across the charge pump buck converter  84 . The PA bias power supply  282  illustrated in  FIG. 45  is similar to the PA bias power supply  282  illustrated in  FIG. 44 , except the PA bias power supply  282  illustrated in  FIG. 45  further includes the second power filtering circuitry  88  coupled between the RF PA circuitry  30  and ground. 
     In one embodiment of the DC-DC converter  32 , the DC-DC converter  32  operates in one of multiple converter operating modes, which include the first converter operating mode, the second converter operating mode, and the third converter operating mode. In an alternate embodiment of the DC-DC converter  32 , the DC-DC converter  32  operates in one of the first converter operating mode and the second converter operating mode. In the first converter operating mode, the charge pump buck converter  84  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the charge pump buck converter  84 . In the first converter operating mode, the buck converter  86  is inactive and does not contribute to the envelope power supply signal EPS. In the second converter operating mode, the buck converter  86  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the buck converter  86 . In the second converter operating mode, the charge pump buck converter  84  is inactive, such that the charge pump buck converter  84  does not contribute to the envelope power supply signal EPS. In the third converter operating mode, the charge pump buck converter  84  and the buck converter  86  are active, such that either the charge pump buck converter  84 ; the buck converter  86 ; or both may contribute to the envelope power supply signal EPS. As such, in the third converter operating mode, the envelope power supply signal EPS is based on the DC power supply signal DCPS via the charge pump buck converter  84 , via the buck converter  86 , or both. 
     In one embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the DC-DC control circuitry  90 . In an alternate embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the RF modulation and control circuitry  28  and may be communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In an additional embodiment of the DC-DC converter  32 , selection of the converter operating mode is made by the control circuitry  42  ( FIG. 5 ) and may be communicated to the DC-DC converter  32  via the DC configuration control signal DCC. In general, selection of the converter operating mode is made by control circuitry, which may be any of the DC-DC control circuitry  90 , the RF modulation and control circuitry  28 , and the control circuitry  42  ( FIG. 5 ). 
       FIG. 46  shows details of the PA envelope power supply  280  and the PA bias power supply  282  illustrated in  FIG. 43  according to an additional embodiment of the PA envelope power supply  280  and the PA bias power supply  282 . The PA envelope power supply  280  illustrated in  FIG. 46  is similar to the PA envelope power supply  280  illustrated in  FIG. 44 , except the PA envelope power supply  280  illustrated in  FIG. 46  further includes the buck converter  86  and the second inductive element L 2  coupled in series to form a first series coupling  284 . The charge pump buck converter  84  and the first inductive element L 1  are coupled in series to form a second series coupling  286 , which is coupled across the first series coupling  284 . The PA bias power supply  282  illustrated in  FIG. 45  is similar to the PA bias power supply  282  illustrated in  FIG. 44 , except the PA bias power supply  282  illustrated in  FIG. 45  further includes the second power filtering circuitry  88  coupled between the RF PA circuitry  30  and ground. 
     In the first converter operating mode, the charge pump buck converter  84  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the charge pump buck converter  84 , and the first inductive element L 1 . In the first converter operating mode, the buck converter  86  is inactive and does not contribute to the envelope power supply signal EPS. In the second converter operating mode, the buck converter  86  is active, such that the envelope power supply signal EPS is based on the DC power supply signal DCPS via the buck converter  86  and the second inductive element L 2 . In the second converter operating mode, the charge pump buck converter  84  is inactive, such that the charge pump buck converter  84  does not contribute to the envelope power supply signal EPS. In the third converter operating mode, the charge pump buck converter  84  and the buck converter  86  are active, such that either the charge pump buck converter  84 ; the buck converter  86 ; or both may contribute to the envelope power supply signal EPS. As such, in the third converter operating mode, the envelope power supply signal EPS is based on the DC power supply signal DCPS either via the charge pump buck converter  84 , and the first inductive element L 1 ; via the buck converter  86  and the second inductive element L 2 ; or both. 
     Automatically Configurable 2-Wire/3-Wire Serial Communications Interface 
     A summary of an automatically configurable 2-wire/3-wire serial communications interface (AC23SCI) is presented, followed by a detailed description of the AC23SCI according to one embodiment of the present disclosure. The present disclosure relates to the AC23SCI, which includes start-of-sequence (SOS) detection circuitry and sequence processing circuitry. When the SOS detection circuitry is coupled to a 2-wire serial communications bus, the SOS detection circuitry detects an SOS of a received sequence based on a serial data signal and a serial clock signal. When the SOS detection circuitry is coupled to a 3-wire serial communications bus, the SOS detection circuitry detects the SOS of the received sequence based on a chip select (CS) signal. The SOS detection circuitry provides an indication of detection of the SOS to the sequence processing circuitry, which initiates processing of the received sequence using the serial data signal and the serial clock signal upon the detection of the SOS. As such, an SOS detection signal, which is indicative of the detection of the SOS, is provided to the sequence processing circuitry from the SOS detection circuitry. In this regard, the AC23SCI automatically configures itself for operation with some 2-wire and some 3-wire serial communications buses without external intervention. 
     Since some 2-wire serial communications buses have only the serial data signal and the serial clock signal, some type of special encoding of the serial data signal and the serial clock signal is used to represent the SOS. However, some 3-wire serial communications buses have a dedicated signal, such as the CS signal, to represent the SOS. As such, some 3-wire serial communications devices, such as test equipment, RF transceivers, baseband controllers, or the like, may not be able to provide the special encoding to represent the SOS, thereby mandating use of the CS signal. As a result, the first AC23SCI must be capable of detecting the SOS based on either the CS signal or the special encoding. 
       FIG. 47  shows a first AC23SCI  300  according to one embodiment of the first AC23SCI  300 . The first AC23SCI  300  includes SOS detection circuitry  302  and sequence processing circuitry  304 . In this regard, the SOS detection circuitry  302  and the sequence processing circuitry  304  provide the first AC23SCI  300 . The SOS detection circuitry  302  has a CS input CSIN, a serial clock input SCIN, and a serial data input SD IN. The SOS detection circuitry  302  is coupled to a 3-wire serial communications bus  306 . The SOS detection circuitry  302  receives a CS signal CSS, a serial clock signal SCLK, and a serial data signal SDATA via the 3-wire serial communications bus  306 . As such, the SOS detection circuitry  302  receives the CS signal CSS via the CS input CSIN, receives the serial clock signal SCLK via the serial clock input SCIN, and receives the serial data signal SDATA via the serial data input SDIN. 
     The serial clock signal SCLK is used to synchronize to data provided by the serial data signal SDATA. A received sequence is provided to the first AC23SCI  300  by the serial data signal SDATA. The SOS is the beginning of the received sequence and is used by the sequence processing circuitry  304  to initiate processing the received sequence. In one embodiment of the SOS detection circuitry  302 , the SOS detection circuitry  302  detects the SOS based on the CS signal CSS. In an alternate embodiment of the SOS detection circuitry  302 , the SOS detection circuitry  302  detects the SOS based on special encoding of the serial data signal SDATA and the serial clock signal SCLK. In either embodiment of the SOS detection circuitry  302 , the SOS detection circuitry  302  provides an SOS detection signal SSDS, which is indicative of the SOS. The sequence processing circuitry  304  receives the SOS detection signal SSDS, the serial data signal SDATA, and the serial clock signal SCLK. As such, the sequence processing circuitry  304  initiates processing of the received sequence using the serial data signal SDATA and the serial clock signal SCLK upon detection of the SOS. In one embodiment of the 3-wire serial communications bus  306 , the 3-wire serial communications bus  306  is the digital communications bus  66 . In one embodiment of the 3-wire serial communications bus  306 , the 3-wire serial communications bus  306  is a bi-directional bus, such that the sequence processing circuitry  304  may provide the serial data input SDIN, the serial clock signal SCLK, or both. 
       FIG. 48  shows the first AC23SCI  300  according an alternate embodiment of the first AC23SCI  300 . The first AC23SCI  300  illustrated in  FIG. 48  is similar to the first AC23SCI  300  illustrated in  FIG. 47 , except in the first AC23SCI  300  illustrated in  FIG. 48 , the SOS detection circuitry  302  is coupled to a 2-wire serial communications bus  308  instead of the 3-wire serial communications bus  306  ( FIG. 47 ). The SOS detection circuitry  302  receives the serial clock signal SCLK and the serial data signal SDATA via the 2-wire serial communications bus  308 . As such, the SOS detection circuitry  302  receives the serial clock signal SCLK via the serial clock input SCIN, and receives the serial data signal SDATA via the serial data input SDIN. The 2-wire serial communications bus  308  does not include the CS signal CSS ( FIG. 47 ). As such, the CS input CSIN may be left unconnected as illustrated. 
     The serial clock signal SCLK is used to synchronize to data provided by the serial data signal SDATA. A received sequence is provided to the first AC23SCI  300  by the serial data signal SDATA. The SOS is the beginning of the received sequence and is used by the sequence processing circuitry  304  to initiate processing the received sequence. The SOS detection circuitry  302  detects the SOS based on the special encoding of the serial data signal SDATA and the serial clock signal SCLK. The SOS detection circuitry  302  provides the SOS detection signal SSDS, which is indicative of the SOS. The sequence processing circuitry  304  receives the SOS detection signal SSDS, the serial data signal SDATA, and the serial clock signal SCLK. As such, the sequence processing circuitry  304  initiates processing of the received sequence using the serial data signal SDATA and the serial clock signal SCLK upon detection of the SOS. In one embodiment of the 2-wire serial communications bus  308 , the 2-wire serial communications bus  308  is the digital communications bus  66 . In one embodiment of the 2-wire serial communications bus  308 , the 2-wire serial communications bus  308  is a bi-directional bus, such that the sequence processing circuitry  304  may provide the serial data input SDIN, the serial clock signal SCLK, or both. 
     In one embodiment of the SOS detection circuitry  302 , when the SOS detection circuitry  302  is coupled to the 2-wire serial communications bus  308 , the SOS detection circuitry  302  receives the serial data signal SDATA and receives the serial clock signal SCLK via the 2-wire serial communications bus  308 , and the SOS detection circuitry  302  detects the SOS based on the serial data signal SDATA and the serial clock signal SCLK. When the SOS detection circuitry  302  is coupled to the 3-wire serial communications bus  306  ( FIG. 47 ), the SOS detection circuitry  302  receives the CS signal CSS ( FIG. 47 ), receives the serial data signal SDATA, and receives the serial clock signal SCLK via the 3-wire serial communications bus  306 ; and the SOS detection circuitry  302  detects the SOS based on the CS signal CSS ( FIG. 47 ). 
     In an alternate embodiment of the SOS detection circuitry  302 , when the SOS detection circuitry  302  is coupled to the 3-wire serial communications bus  306  ( FIG. 47 ), the SOS detection circuitry  302  receives the CS signal CSS ( FIG. 47 ), receives the serial data signal SDATA, and receives the serial clock signal SCLK via the 3-wire serial communications bus  306 ; and the SOS detection circuitry  302  detects the SOS based on either the CS signal CSS ( FIG. 47 ) or the serial data signal SDATA and the serial clock signal SCLK. 
       FIG. 49  shows details of the SOS detection circuitry  302  illustrated in  FIG. 47  according to one embodiment of the SOS detection circuitry  302 . The SOS detection circuitry  302  includes a sequence detection OR gate  310 , CS detection circuitry  312 , start sequence condition (SSC) detection circuitry  314 , and a CS resistive element RCS. The CS resistive element RCS is coupled to the CS input CSIN. In one embodiment of the SOS detection circuitry  302 , the CS resistive element RCS is coupled between the CS input CSIN and a ground. As such, when the CS input CSIN is left unconnected, the CS input CSIN is in a LOW state. In an alternate embodiment of the SOS detection circuitry  302 , the CS resistive element RCS is coupled between the CS input CSIN and a DC power supply (not shown). 
     The CS detection circuitry  312  is coupled to the serial clock input SCIN and the CS input CSIN. As such, the CS detection circuitry  312  receives the serial clock signal SCLK and the CS signal CSS via the serial clock input SCIN and the CS input CSIN, respectively. The CS detection circuitry  312  feeds one input to the sequence detection OR gate  310  based on the serial clock signal SCLK and the CS signal CSS. In an alternate embodiment of the CS detection circuitry  312 , the CS detection circuitry  312  is not coupled to the serial clock input SCIN. As such, the CS detection circuitry  312  feeds one input to the sequence detection OR gate  310  based on only the CS signal CSS. In an alternate embodiment of the SOS detection circuitry  302 , the CS detection circuitry  312  is omitted, such that the CS input CSIN is directly coupled to one input to the sequence detection OR gate  310 . 
     The SSC detection circuitry  314  is coupled to the serial clock input SCIN and the serial data input SDIN. As such, the SSC detection circuitry  314  receives the serial clock signal SCLK and the serial data signal SDATA via the serial clock input SCIN and the serial data input SDIN, respectively. The SSC detection circuitry  314  feeds another input to the sequence detection OR gate  310  based on the serial clock signal SCLK and the serial data signal SDATA. An output from the sequence detection OR gate  310  provides the SOS detection signal SSDS to the sequence processing circuitry  304  based on signals received from the CS detection circuitry  312  and the SSC detection circuitry  314 . In this regard, the CS detection circuitry  312 , the SSC detection circuitry  314 , or both may detect an SOS of a received sequence. 
       FIGS. 50A ,  50 B,  50 C, and  50 D are graphs illustrating the chip select signal CSS, the SOS detection signal SSDS, the serial clock signal SCLK, and the serial data signal SDATA, respectively, of the first AC23SCI  300  illustrated in  FIG. 49  according to one embodiment of the first AC23SCI  300 . The serial clock signal SCLK has a serial clock period  316  ( FIG. 50C ) and the serial data signal SDATA has a data bit period  318  ( FIG. 50D ) during a received sequence  320  ( FIG. 50D ). In one embodiment of the first AC23SCI  300 , the serial clock period  316  is about equal to the data bit period  318 . As such, the serial clock signal SCLK may be used to sample data provided by the serial data signal SDATA. An SOS  322  of the received sequence  320  is shown in  FIG. 50D . 
     The SOS detection circuitry  302  may detect the SOS  322  based on a LOW to HIGH transition of the CS signal CSS as shown in  FIG. 50A . The CS detection circuitry  312  may use the CS signal CSS and the serial clock signal SCLK, such that the SOS detection signal SSDS is a pulse. A duration of the pulse may be about equal to the serial clock period  316 . The pulse may be a positive pulse as shown in  FIG. 50B . In an alternate embodiment (not shown) of the CS detection circuitry  312 , the CS detection circuitry  312  may use the CS signal CSS and the serial clock signal SCLK, such that the SOS detection signal SSDS is a negative pulse. In an alternate embodiment (not shown) of the SOS detection circuitry  302 , the SOS detection circuitry  302  may detect the SOS  322  based on a HIGH to LOW transition of the CS signal CSS. 
       FIGS. 51A ,  51 B,  51 C, and  51 D are graphs illustrating the chip select signal CSS, the SOS detection signal SSDS, the serial clock signal SCLK, and the serial data signal SDATA, respectively, of the first AC23SCI  300  illustrated in  FIG. 49  according to one embodiment of the first AC23SCI  300 . The CS signal CSS illustrated in  FIG. 51A  is LOW during the received sequence  320  ( FIG. 51D ). As such, the CS signal CSS is not used to detect the SOS  322  ( FIG. 51D ). Instead, detection of the SOS  322  is based on the special encoding of the serial data signal SDATA and the serial clock signal SCLK. Specifically, the SOS detection circuitry  302  uses the SSC detection circuitry  314  to detect the SOS  322  based on a pulse of the serial data signal SDATA, such that during the pulse of the serial data signal SDATA, the serial clock signal SCLK does not transition. The pulse of the serial data signal SDATA may be a positive pulse as shown in  FIG. 51D . A duration of the serial data signal SDATA may be about equal to the data bit period  318 . 
     The SSC detection circuitry  314  may use the serial data signal SDATA and the serial clock signal SCLK, such that the SOS detection signal SSDS is a pulse. A duration of the pulse may be about equal to the serial clock period  316 . The pulse may be a positive pulse as shown in  FIG. 51B . In an alternate embodiment (not shown) of the SSC detection circuitry  314 , the SSC detection circuitry  314  may use the serial data signal SDATA and the serial clock signal SCLK, such that the SOS detection signal SSDS is a negative pulse. In an alternate embodiment (not shown) of the SOS detection circuitry  302 , the SOS detection circuitry  302  may detect the SOS  322  based on a negative pulse of the serial data signal SDATA while the serial clock signal SCLK does not transition. 
     In one embodiment of the sequence processing circuitry  304 , if another SOS  322  is detected before processing of the received sequence  320  is completed; the sequence processing circuitry  304  will abort processing of the received sequence  320  in process and initiate processing of the next received sequence  320 . In one embodiment of the first AC23SCI  300 , the first AC23SCI  300  is a mobile industry processor interface (MiPi). In an alternate embodiment of the first AC23SCI  300 , the first AC23SCI  300  is an RF front-end (FE) interface. In an additional embodiment of the first AC23SCI  300 , the first AC23SCI  300  is a slave device. In another embodiment of the first AC23SCI  300 , the first AC23SCI  300  is a MiPi RFFE interface. In a further embodiment of the first AC23SCI  300 , the first AC23SCI  300  is a MiPi RFFE slave device. In a supplemental embodiment of the first AC23SCI  300 , the first AC23SCI  300  is a MiPi slave device. In an alternative embodiment of the first AC23SCI  300 , the first AC23SCI  300  is an RFFE slave device. 
       FIGS. 52A ,  52 B,  52 C, and  52 D are graphs illustrating the chip select signal CSS, the SOS detection signal SSDS, the serial clock signal SCLK, and the serial data signal SDATA, respectively, of the first AC23SCI  300  illustrated in  FIG. 49  according to one embodiment of the first AC23SCI  300 .  FIGS. 52A ,  52 C, and  52 D are duplicates of  FIGS. 50A ,  50 C, and  50 D, respectively for clarity. The SOS detection circuitry  302  may detect the SOS  322  based on the LOW to HIGH transition of the CS signal CSS as shown in  FIG. 52A . The CS detection circuitry  312  may uses the CS signal CSS, such that the SOS detection signal SSDS follows the CS signal CSS as shown in  FIG. 52B . In an alternate embodiment of the SOS detection circuitry  302 , the CS detection circuitry  312  is omitted, such that the CS input CSIN is directly coupled to the sequence detection OR gate  310 . As such, the SOS detection signal SSDS follows the CS signal CSS as shown in  FIG. 52B . 
       FIG. 53  shows the RF communications system  26  according to one embodiment of the RF communications system  26 . The RF communications system  26  illustrated in  FIG. 53  is similar to the RF communications system  26  illustrated in  FIG. 6 , except in the RF communications system  26  illustrated in  FIG. 53 , the RF PA circuitry  30  further includes the first AC23SCI  300 , the DC-DC converter  32  further includes a second AC23SCI  324 , and the front-end aggregation circuitry  36  further includes a third AC23SCI  326 . In one embodiment of the RF communications system  26 , the first AC23SCI  300  is the PA-DCI  60 , the second AC23SCI  324  is the DC-DC converter DCI  62 , and the third AC23SCI  326  is the aggregation circuitry DCI  64 . In an alternate embodiment (not shown) of the RF communications system  26 , the first AC23SCI  300  is the DC-DC converter DCI  62 . In an additional embodiment (not shown) of the RF communications system  26 , the first AC23SCI  300  is the aggregation circuitry DCI  64 . 
     In one embodiment of the RF communications system  26 , the S-wire serial communications bus  306  ( FIG. 47 ) is the digital communications bus  66 . The control circuitry  42  is coupled to the SOS detection circuitry  302  ( FIG. 47 ) via the 3-wire serial communications bus  306  ( FIG. 47 ) and via the control circuitry DCI  58 . As such, the control circuitry  42  provides the CS signal CSS ( FIG. 47 ) via the control circuitry DCI  58 , the control circuitry  42  provides the serial clock signal SCLK ( FIG. 47 ) via the control circuitry DCI  58 , and the control circuitry  42  provides the serial data signal SDATA ( FIG. 47 ) via the control circuitry DCI  58 . 
     In an alternate embodiment of the RF communications system  26 , the 2-wire serial communications bus  308  ( FIG. 48 ) is the digital communications bus  66 . The control circuitry  42  is coupled to the SOS detection circuitry  302  ( FIG. 48 ) via the 2-wire serial communications bus  308  ( FIG. 48 ) and via the control circuitry DCI  58 . As such, the control circuitry  42  provides the serial clock signal SCLK ( FIG. 48 ) via the control circuitry DCI  58  and the control circuitry  42  provides the serial data signal SDATA ( FIG. 48 ) via the control circuitry DCI  58 . 
       FIG. 54  shows details of the RF PA circuitry  30  illustrated in  FIG. 6  according to an additional embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 54  is similar to the RF PA circuitry  30  illustrated in  FIG. 14 , except the RF PA circuitry  30  illustrated in  FIG. 54  shows multi-mode multi-band RF power amplification circuitry  328  in place of the first transmit path  46  and the second transmit path  48  that are shown in  FIG. 14 . The PA control circuitry  94  is coupled between the multi-mode multi-band RF power amplification circuitry  328  and the PA-DCI  60 . The PA-DCI  60  is coupled to the digital communications bus  66 . 
       FIG. 55  shows details of the multi-mode multi-band RF power amplification circuitry  328  illustrated in  FIG. 54  according to one embodiment of the multi-mode multi-band RF power amplification circuitry  328 . The multi-mode multi-band RF power amplification circuitry  328  includes the first transmit path  46  and the second transmit path  48 . The first transmit path  46  and the second transmit path  48  illustrated in  FIG. 55  are similar to the first transmit path  46  and the second transmit path  48  illustrated in  FIG. 37 , except in the first transmit path  46  and the second transmit path  48  illustrated in  FIG. 55 , the first RF PA  50  has a first RF input FRI and the second RF PA  54  has a second RF input SRI. The first RF PA  50  receives and amplifies the first RF input signal FRFI to provide the first RF output signal FRFO. The second RF PA  54  receives and amplifies the second RF input signal SRFI to provide the second RF output signal SRFO. As such, the first RF PA  50  receives the first RF input signal FRFI via the first RF input FRI and provides the first RF output signal FRFO via the single alpha PA output SAP. The second RF PA  54  receives the second RF input signal SRFI via the second RF input SRI and provides the second RF output signal SRFO via the single beta PA output SBP. 
     In general, the multi-mode multi-band RF power amplification circuitry  328  has at least the first RF input FRI and a group of RF outputs FANO, FALO, RALO, FBNO, FBLO, SBLO. Configuration of the multi-mode multi-band RF power amplification circuitry  328  associates one of the RF inputs FRI, SRI with one of the group of RF outputs FANO, FALO, RALO, FBNO, FBLO, SBLO. 
       FIGS. 56A and 56B  show details of the PA control circuitry  94  illustrated in  FIG. 54  according to one embodiment of the PA control circuitry  94 . The PA control circuitry  94  stores at least a first look-up table (LUT)  330  as shown in  FIG. 56A . The first LUT  330  provides configuration information  332  as shown in  FIG. 56B . The configuration information  332  may be defined by at least a first defined parameter set. The configuration of the multi-mode multi-band RF power amplification circuitry  328  is correlated with the configuration information  332 . 
       FIG. 57  shows details of the RF PA circuitry  30  illustrated in  FIG. 6  according to another embodiment of the RF PA circuitry  30 . The RF PA circuitry  30  illustrated in  FIG. 57  is similar to the RF PA circuitry  30  illustrated in  FIG. 14 , except in the RF PA circuitry  30  illustrated in  FIG. 57 , the first RF PA  50  and the second RF PA  54  are similar to the first RF PA  50  and the second RF PA  54  illustrated in  FIG. 40 , except the first driver stage  252  has a first driver bias input FDBI, the first final stage  254  has a first final bias input FFBI, the second driver stage  256  has a second driver bias input SDBI, and the second final stage  258  has a second final bias input SFBI. The PA bias circuitry  96  illustrated in  FIG. 40  includes the driver stage IDAC circuitry  260  ( FIG. 40 ) and the final stage IDAC circuitry  262  ( FIG. 40 ). However, the driver stage IDAC circuitry  260  ( FIG. 41 ) illustrated in  FIG. 41  includes the driver stage IDAC  264  ( FIG. 41 ). The final stage IDAC circuitry  262  ( FIG. 41 ) illustrated in  FIG. 41  includes the final stage IDAC  270  ( FIG. 41 ). 
     In this regard, the final stage IDAC  270  ( FIG. 41 ) is coupled between the PA control circuitry  94  and the first final bias input FFBI. The final stage IDAC  270  ( FIG. 41 ) is coupled between the PA control circuitry  94  and the second final bias input SFBI. The driver stage IDAC  264  ( FIG. 41 ) is coupled between the PA control circuitry  94  and the first driver bias input FDBI. The driver stage IDAC  264  ( FIG. 41 ) is coupled between the PA control circuitry  94  and the second driver bias input SDBI. 
     The PA-DCI  60  is coupled between the digital communications bus  66  and the PA control circuitry  94 . The PA control circuitry  94  receives information from the digital communications bus  66  via the PA-DCI  60 . The final stage IDAC  270  ( FIG. 41 ) biases the first final stage  254  via the first final bias input FFBI based on the information. The final stage IDAC  270  ( FIG. 41 ) biases the second final stage  258  via the second final bias input SFBI based on the information. The driver stage IDAC  264  ( FIG. 41 ) biases the first driver stage  252  via the first driver bias input FDBI based on the information. The driver stage IDAC  264  ( FIG. 41 ) biases the second driver stage  256  via the second driver bias input SDBI based on the information. 
     Some of the circuitry previously described may use discrete circuitry, integrated circuitry, programmable circuitry, non-volatile circuitry, volatile circuitry, software executing instructions on computing hardware, firmware executing instructions on computing hardware, the like, or any combination thereof. The computing hardware may include mainframes, micro-processors, micro-controllers, DSPs, the like, or any combination thereof. 
     None of the embodiments of the present disclosure are intended to limit the scope of any other embodiment of the present disclosure. Any or all of any embodiment of the present disclosure may be combined with any or all of any other embodiment of the present disclosure to create new embodiments of the present disclosure. 
     LIST OF ELEMENTS 
     traditional multi-mode multi-band communications device  10   
     traditional multi-mode multi-band transceiver  12   
     traditional multi-mode multi-band PA circuitry  14   
     traditional multi-mode multi-band front-end aggregation circuitry  16   
     antenna  18   
     first traditional PA  20   
     second traditional PA  22   
     N TH  traditional PA  24   
     RF communications system  26   
     RF modulation and control circuitry  28   
     RF PA circuitry  30   
     DC-DC converter  32   
     transceiver circuitry  34   
     front-end aggregation circuitry  36   
     down-conversion circuitry  38   
     baseband processing circuitry  40   
     control circuitry  42   
     RF modulation circuitry  44   
     first transmit path  46   
     second transmit path  48   
     first RF PA  50   
     alpha switching circuitry  52   
     second RF PA  54   
     beta switching circuitry  56   
     control circuitry DCI  58   
     PA-DCI  60   
     DC-DC converter DCI  62   
     aggregation circuitry DCI  64   
     digital communications bus  66   
     alpha RF switch  68   
     first alpha harmonic filter  70   
     beta RF switch  72   
     first beta harmonic filter  74   
     second alpha harmonic filter  76   
     second beta harmonic filter  78   
     DC power supply  80   
     first power filtering circuitry  82   
     charge pump buck converter  84   
     buck converter  86   
     second power filtering circuitry  88   
     DC-DC control circuitry  90   
     charge pump  92   
     PA control circuitry  94   
     PA bias circuitry  96   
     switch driver circuitry  98   
     first non-quadrature PA path  100   
     first quadrature PA path  102   
     second non-quadrature PA path  104   
     second quadrature PA path  106   
     first input PA impedance matching circuit  108   
     first input PA stage  110   
     first feeder PA impedance matching circuit  112   
     first feeder PA stage  114   
     second input PA impedance matching circuit  116   
     second input PA stage  118   
     second feeder PA impedance matching circuit  120   
     second feeder PA stage  122   
     first quadrature RF splitter  124   
     first in-phase amplification path  126   
     first quadrature-phase amplification path  128   
     first quadrature RF combiner  130   
     second quadrature RF splitter  132   
     second in-phase amplification path  134   
     second quadrature-phase amplification path  136   
     second quadrature RF combiner  138   
     first in-phase driver PA impedance matching circuit  140   
     first in-phase driver PA stage  142   
     first in-phase final PA impedance matching circuit  144   
     first in-phase final PA stage  146   
     first in-phase combiner impedance matching circuit  148   
     first quadrature-phase driver PA impedance matching circuit  150   
     first quadrature-phase driver PA stage  152   
     first quadrature-phase final PA impedance matching circuit  154   
     first quadrature-phase final PA stage  156   
     first quadrature-phase combiner impedance matching circuit  158   
     second in-phase driver PA impedance matching circuit  160   
     second in-phase driver PA stage  162   
     second in-phase final PA impedance matching circuit  164   
     second in-phase final PA stage  166   
     second in-phase combiner impedance matching circuit  168   
     second quadrature-phase driver PA impedance matching circuit  170   
     second quadrature-phase driver PA stage  172   
     second quadrature-phase final PA impedance matching circuit  174   
     second quadrature-phase final PA stage  176   
     second quadrature-phase combiner impedance matching circuit  178   
     first output transistor element  180   
     characteristic curves  182   
     first output load line  184   
     first load line slope  186   
     first non-quadrature path power coupler  188   
     second non-quadrature path power coupler  190   
     first phase-shifting circuitry  192   
     first Wilkinson RF combiner  194   
     first in-phase final transistor element  196   
     first in-phase biasing circuitry  198   
     first quadrature-phase final transistor element  200   
     first quadrature-phase biasing circuitry  202   
     first pair  204  of tightly coupled inductors 
     first parasitic capacitance  206   
     first feeder biasing circuitry  208   
     first PA semiconductor die  210   
     second phase-shifting circuitry  212   
     second Wilkinson RF combiner  214   
     second in-phase final transistor element  216   
     second in-phase biasing circuitry  218   
     second quadrature-phase final transistor element  220   
     second quadrature-phase biasing circuitry  222   
     second pair  224  of tightly coupled inductors 
     second parasitic capacitance  226   
     second output transistor element  228   
     second feeder biasing circuitry  230   
     second PA semiconductor die  232   
     first substrate and functional layers  234   
     insulating layers  236   
     metallization layers  238   
     first alpha switching device  240   
     second alpha switching device  242   
     third alpha switching device  244   
     first beta switching device  246   
     second beta switching device  248   
     third beta switching device  250   
     first driver stage  252   
     first final stage  254   
     second driver stage  256   
     second final stage  258   
     driver stage IDAC circuitry  260   
     final stage IDAC circuitry  262   
     driver stage IDAC  264   
     driver stage multiplexer  266   
     driver stage current reference circuitry  268   
     final stage IDAC  270   
     final stage multiplexer  272   
     final stage current reference circuitry  274   
     driver stage temperature compensation circuit  276   
     final stage temperature compensation circuit  278   
     PA envelope power supply  280   
     PA bias power supply  282   
     first series coupling  284   
     second series coupling  286   
     first AC23SCI  300   
     SOS detection circuitry  302   
     sequence processing circuitry  304   
     3-wire serial communications bus  306   
     2-wire serial communications bus  308   
     sequence detection OR gate  310   
     CS detection circuitry  312   
     SSC detection circuitry  314   
     serial clock period  316   
     data bit period  318   
     received sequence  320   
     SOS  322   
     second AC23SCI  324   
     third AC23SCI  326   
     multi-mode multi-band RF power amplification circuitry  328   
     first LUT  330   
     configuration information  332   
     first input resistive element RFI 
     first isolation port resistive element RI 1   
     first base resistive element RB 1   
     first Wilkinson resistive element RW 1   
     second isolation port resistive element RI 2   
     second base resistive element RB 2   
     second Wilkinson resistive element RW 2   
     CS resistive element RCS 
     first inductive element L 1   
     second inductive element L 2   
     third inductive element L 3   
     inverting output inductive element LIO 
     first in-phase collector inductive element LCI 
     first quadrature-phase collector inductive element LCQ 
     first in-phase shunt inductive element LUI 
     first quadrature-phase shunt inductive element LUQ 
     first collector inductive element LC 1   
     second collector inductive element LC 2   
     first in-phase phase-shift inductive element LPI 1   
     first quadrature-phase phase-shift inductive element LPQ 1   
     first Wilkinson in-phase side inductive element LWI 1   
     first Wilkinson quadrature-phase side inductive element LWQ 1   
     second in-phase collector inductive element LLI 
     second quadrature-phase collector inductive element LLQ 
     second in-phase shunt inductive element LNI 
     second quadrature-phase shunt inductive element LNQ 
     second in-phase phase-shift inductive element LPI 2   
     second quadrature-phase phase-shift inductive element LPQ 2   
     second Wilkinson in-phase side inductive element LWI 2   
     second Wilkinson quadrature-phase side inductive element LWQ 2   
     first capacitive element C 1   
     second capacitive element C 2   
     third capacitive element C 3   
     first in-phase series capacitive element CSI 1   
     second in-phase series capacitive element CSI 2   
     first quadrature-phase series capacitive element CSQ 1   
     second quadrature-phase series capacitive element CSQ 2   
     first DC blocking capacitive element CD 1   
     first coupler capacitive element CC 1   
     second coupler capacitive element CC 2   
     first in-phase phase-shift capacitive element CPI 1   
     first quadrature-phase phase-shift capacitive element CPQ 1   
     first Wilkinson capacitive element CW 1   
     first Wilkinson in-phase side capacitive element CWI 1   
     first Wilkinson quadrature-phase side capacitive element CWQ 1   
     second DC blocking capacitive element CD 2   
     third DC blocking capacitive element CD 3   
     fourth DC blocking capacitive element CD 4   
     third in-phase series capacitive element CSI 3   
     fourth in-phase series capacitive element CSI 4   
     third quadrature-phase series capacitive element CSQ 3   
     fourth quadrature-phase series capacitive element CSQ 4   
     fifth DC blocking capacitive element CD 5   
     second in-phase phase-shift capacitive element CPI 2   
     second quadrature-phase phase-shift capacitive element CPQ 2   
     second Wilkinson capacitive element CW 2   
     second Wilkinson in-phase side capacitive element CWI 2   
     second Wilkinson quadrature-phase side capacitive element CWQ 2   
     sixth DC blocking capacitive element CD 6   
     seventh DC blocking capacitive element CD 7   
     eighth DC blocking capacitive element CD 8   
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.