Patent Publication Number: US-4484312-A

Title: Dynamic random access memory device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device, more particularly, to a dynamic random access memory (RAM) device comprising one-transistor, one-capacitor-type memory cells. 
     2. Description of the Prior Art 
     In a MOS dynamic RAM device, one-transistor, one-capacitor-type memory cells have been put to practical use, and, in addition, such memory cells are often used since they are advantageous in respect to integration density. In this type of memory cell, each cell comprises a capacitor and a transistor which serves as a switching element for charging and discharging the capacitor. Therefore, the presence or absence of charges in the capacitor represents data &#34;1&#34; or &#34;0&#34;, respectively. The memory cells are arranged at intersections between word lines and bit lines. In addition, dummy cells are arranged at intersections between dummy word lines and bit lines. 
     In the prior art, these dummy cells are similar in construction to the one-transistor, one-capacitor-type memory cells in that they comprise a capacitor, a transistor, and an additional transistor for resetting the capacitor. However, in recent years, dummy cells comprising only one capacitor have been developed (See: IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 184-189, April 1980). A dynamic RAM including such one-capacitor dummy cells is advantageous in respect to integration density and reduces the load of the operation clock generator. 
     In a dynamic RAM device including the above-mentioned one-capacitor-type dummy cells, a discharging transistor and a charging transistor are provided in series between two power supplies (V CC , V SS ), and their connection node is connected to a dummy word line connected to the dummy cells. The control of this device is carried out as follows. First, the dummy word line is discharged by the discharging transistor clocked by a reset clock generator. In this state, the dummy word line is at level V SS . Then, the dummy word line is charged by the charging transistor clocked by an operation clock generator so that the potential of the dummy word line is pushed up to the power supply voltage (V CC ). 
     In the above-mentioned dynamic RAM device, however, in order to push up the potential of the dummy word line, the operation clock generator must generate a potential higher than V CC  +V th , where V th  is the threshold voltage value of the charging transistor. As a result, the operation clock generator has to incorporate a charge-pumping circuit or a bootstrap circuit for generating such a higher potential. Therefore, the operation clock generator becomes complex, and, accordingly, the operation speed of the operation clock generator, that is, the access speed of the device, becomes low. 
     SUMMARY OF THE INVENTION 
     It is, therefore, a principle object of the present invention to provide a dynamic RAM device comprising one-transistor, one-capacitor-type memory cells in which the access speed is high. 
     It is another object of the present invention to provide a dynamic RAM device comprising one-transistor, one-capacitor-type memory cells in which correct data can be read out even if a fluctuation in the power supply voltage is generated. 
     According to the present invention, there is provided a dynamic RAM device; first and second power supplies, the potential of the first power supply being lower than that of the second power supply; a first clock generator for generating a first clock signal having a potential higher than that of the second power supply and a second clock signal having a potential lower than or equal to the potential of the second power supply; a second clock generator for generating a third clock signal having a potential higher than the potential of the second power supply alternately with the first and second clock signals; a plurality of word lines selectively driven by the first clock signal; a plurality of pairs of bit lines precharged by the second power supply in response to the third clock signal; a plurality of sense amplifiers, each sense amplifier being arranged between one pair of the pairs of bit lines, for sensing the difference in potential between the pairs of bit lines; a plurality of one-transistor, one-capacitor-type memory cells in rows and columns, each memory cell being connected to one of the word lines and to one of the bit lines; a plurality of dummy cells, each dummy cell comprising a capacitor and a connection node, the capacitor having an electrode connected to one of the bit lines and another electrode connected to one of the connection nodes; at least one charging means, each means being connected to each of the connection nodes of the dummy cells respectively and driven by the third clock generator, for charging the capacitor of each of the dummy cells; and at least one discharging means, each means being connected to each of the connection nodes of the dummy cells respectively and driven by the second clock signal, for discharging the capacitor of each of the dummy cells. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The present invention will be more clearly understood from the description as set forth below contrasting the present invention with the prior art and referring to the accompanying drawings, wherein: 
     FIG. 1 is a block circuit diagram of a prior art dynamic RAM device; 
     FIG. 2 is a partial circuit diagram of the circuit of FIG. 1; 
     FIG. 3 is a circuit diagram of another prior art dynamic RAM device; 
     FIGS. 4A and 4B are timing diagrams of the signals appearing in the circuit of FIG. 3; 
     FIG. 5 is a circuit diagram of a first embodiment of the dynamic RAM device according to the present invention; 
     FIGS. 6A and 6B are timing diagrams of the signals appearing in the circuit of FIG. 5; 
     FIG. 7 is a circuit diagram of a second embodiment of the dynamic RAM device according to the present invention; 
     FIGS. 8A and 8B are also timing diagrams of the signals appearing in the circuit of FIG. 5; and 
     FIG. 9 is a circuit diagram of a third embodiment of the dynamic RAM device according to the present invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     First, the prior art dynamic RAM devices will be explained with reference to FIGS. 1, 2, 3, 4A, and 4B. In FIG. 1, for example, a 16 kbit (precisely, 16,384 bit) RAM device is illustrated. In the figure, one-transistor, one-capacitor-type memory cells C 00 , C 01 , . . . , C 0 ,127, C 63 ,0, C 63 ,1, . . . , C 63 ,127, C 64 ,0, C 64 ,1, . . . , C 64 ,127, C 127 ,0, C 127 ,1, . . . , and C 127 ,127 in rows and columns are arranged at intersections between word lines WL 0 , . . . , WL 63 , WL 64 , . . . , and WL 127  and bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL 127 , and BL 127 , and sense amplifiers S 0 , S 1 , . . . , and S 127  in a row are arranged between bit line pairs BL 0 , BL 0 , BL 1 , BL 1  , . . . , BL 127 , and BL 127 . Further, dummy cells DC 10 , DC 11 , . . . , and DC 1 ,127 in a row are connected to the terminals of bit lines BL 0 , BL 1 , . . . , and BL 127  and to dummy word line DWL 1  while dummy cells DC 20 , DC 21 , . . . , and DC 2 ,127 in a row are connected to the terminals of bit lines BL 0 , BL 1 , . . . , and BL 127  and to dummy word line DWL 2 . 
     In FIG. 1, φ WL  is an operation clock signal for driving word lines WL 0 , . . . , WL 63 , WL 64 , . . . , and WL 127  and dummy word lines DWL 1  and DWL 2 . φ R  is a reset clock signal for resetting capacitor Q R  (not shown in FIG. 1 but shown in FIG. 2) of each dummy cell and for precharging bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL 127  and BL 127 . 
     The selection of word lines WL 0 , WL 1 , . . . , and WL 127  is carried out by word decoders DEC, and, simultaneously, the selection of dummy word lines DWL 1  and DWL 2  is also carried out by row decoders DEC. For example, when one of the word lines WL 0  through WL 63  is selected, dummy word line DWL 2  is selected while when one of word lines WL 64  through WL 127  is selected, dummy word line DWL 1  is selected. Such selection is carried out by transfer gates TG -1 , TG 0 , . . . , TG 63 , TG 64 , . . . , TG 127 , and TH 128  which are switched on by word decoders DEC so as to transfer the clock signal φ WL . In more detail, word decoders DEC decode row address signals A 0 , A 0 , A 1 , A 1 , . . . , A 5  and A 5  so that one of the transfer gates TG 0  through TG 127 , that is, one of the word lines WL 0  through WL 127 , is selected, and, in addition, row decoders DEC decode row address signal A 6  or A 6  so that one of the transfer gates TG -1  and TG 128 , that is, one of the dummy word lines DWL 1  and DWL 2 , is selected. 
     In FIG. 2, which is a partial circuit diagram of the circuit of FIG. 1, word line WL 0  and dummy word line DWL 2  of FIG. 1 are illustrated in detail while the other word lines and dummy word line DWL 1  are omitted. That is, if word line WL 0  is selected, dummy word line DWL 2  on the opposite side regarding the sense amplifiers is always selected. 
     Each of memory cells C 00 , C 01 , . . . , and C 0 ,127 comprises capacitor C m  and transistor Q m  while each of the dummy cells DC 20 , DC 21 , . . . , and DC 2 ,127 comprises capacitor C d , transistor Q d , and transistor Q R . In this case, the capacitance of each capacitor C d  of the dummy memory cells is set to be about half the capacitance of each capacitor C m  of the memory cells. During the standby mode, reset clock generator CK 2  generates reset clock signal φ R  having a potential higher than V CC  +V th , where V th  is the common threshold voltage value of the enhancement transistors. As a result, capacitors C d  of the dummy cells D 20 , D 21 , . . . , and DC 2 ,127 are discharged, and, simultaneously, bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL 127 , and BL 127  are precharged to a potential V CC . Next, during the selecting mode, operation clock generator CK 1  supplies a clock signal φ WL  through on-state transfer gates TG 0  and TG 128  to a word line WL 0  and a dummy word line DWL 2 , which means that the word line WL 0  and the dummy word line DWL 2  are selected. As a result, for example, when the potential of capacitor C m  of the memory cell C 00  is high (which corresponds to data &#34;1&#34;, for example), the potential of the bit line BL 0  does not decrease while when the potential of the capacitor C m  of the memory cell C 00  is low (which corresponds to data &#34;0&#34; ), the potential bit line BL 0  decreases. On the other hand, in the dummy cell DC 20 , since capacitor C d  is charged, bit line BL 0  decreases. In any case, since the capacitance of the capacitor C m  is different from that of the capacitor C d , there is generated a difference in potential between bit lines BL 0  and BL 0 . Such difference in potential is sensed, that is, enlarged, by the sense amplifier S 0 , and the difference is then read out. 
     In FIG. 2, however, the load of operation clock generator CK 1  is dependent on not only the capacity of the word line WL 0 , the capacity of the gates of the transistors Q m  of the memory cells C 00 , C 01 , . . . , and C 0 ,127, and the like, but also is dependent upon the capacity of the dummy word line DWL 2 , the capacity of the gates of the dummy cells DC 20 , DC 21 , . . . , DC 2 ,127, and the like. Therefore, the load of the operation clock generator CK 1  is large, so that the operation speed of the device is reduced. 
     FIG. 3 is a circuit diagram illustrating another prior art dynamic RAM device which is disclosed in FIG. 8 of the IEEE Journal of Solid-State Circuits, vol. SC-15, No. 2, pp. 184-189, April 1980. In FIG. 3, word lines WL 0  and dummy word line DWL 1  are illustrated in detail while the other word lines and dummy word line DWL 2  are omitted. That is, if word line WL 0  is selected, dummy word line DWL 1  on the same side regarding sense amplifiers S 0  &#39;, S 1  &#39;, S 2  &#39;, . . . , and S 63  &#39; is always selected. 
     Each of dummy cells DC 10  &#39;, DC 11  &#39;, . . . , and DC 1 ,127 &#39; comprises only one capacitor C d , thereby remarkably reducing the area occupied by the dummy cells in the chip as compared with the dummy memory cells of FIG. 2. Q A  and Q B  are charging and discharging transistors, respectively, for dummy word line DWL 1 , that is, for capacitors C d . Charging transistor Q A  is clocked by the clock signal φ WL  generated by the operation clock generator CK 1 , while discharging transistor Q B  is clocked by the clock signal φ R  generated by the reset clock generator CK 2 . Therefore, the load of the operation clock generator CK 1  is dependent on the capacity of the charging transistor Q A  in addition to the capacity of the word line WL 0 , the capacity of the gates of transistors Q m  of the memory cells C 00 , C 01 , . . . , and C 0 ,127, and the like, thereby reducing the load of the operation clock generator CK 1 . 
     The operation of the circuit of FIG. 3 will now be explained with reference to FIG. 4A regarding only bit lines BL 0  and BL 1  since the sense amplifier S 0  &#39; responds to the pair of bit lines BL 0  and BL 1 . Assuming memory cell C 00  stores data &#34;1&#34;, that is, that the capacitor C m  of memory cell C 00  is charged, during the standby mode, the reset clock signal is high (V CC  +V th  +α), discharging transistor Q B  is turned on so that the capacitors C d  of the dummy cells DC 10  &#39;, DC 11  &#39;, . . . , DC 1 ,126 &#39;, and DC 1 ,127 &#39; are discharged, and, accordingly, the potential of the dummy word line DWL 1  remains low (V SS  =ground level). Simultaneously, bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL 126 , BL 126 , BL 127 , and BL 127  are precharged to level V CC . Next, during the selecting mode, the potential of clock signal φ R  is changed from the level V CC  +V th  +α to the level V SS , and, in addition, the potential of the clock signal φ WL  is changed from the level V SS  to the level V CC  +V th  +α. As a result, the potential of the word line WL 0  selected by the decorder DEC is changed in common phase with the potential of the clock signal φ WL . In addition, discharging transistor Q B  is turned off while charging transistor Q A  is turned on. As a result, the potential of the selected dummy word line DWL 1  is changed in common phase with the potential of the clock signal φ WL . Simultaneously, the bit lines assume a floating state. In this case, since bit line BL 0  is connected to dummy word line DWL 1  by the capacitive coupling of capacitors C d , the potential of the bit line BL 0  is pulled up in proportion to the capacitance ratio of the bit line BL 0  to the dummy word line DWL 1 . That is, the potential of dummy word line DWL 1  causes the potential of bit line BL 0  to be slightly positive relative to the potential of bit line BL 1 . Thus, a difference ΔV BL  in potential is generated between bit lines BL 0  and BL 1  , and, during the sensing mode, such difference is sensed by sense amplifier S 0  &#39;. As a result, the lower-side potential of bit line BL 1  is decreased to V SS . 
     Similarly, assuming that the memory cell C 00  stores data &#34;0&#34;, that is, that capacitor C m  of the memory cell C 00  is discharged, the potential of dummy word line DWL 1  also causes the potential of bit line BL 0  to be high. However, current flows from the bit line BL 0  into the capacitor C m  of the memory cell C 00 , and, accordingly, the potential of the bit line BL 0  is pulled down in proportion to the capacitance ratio of the capacitor C m  of the memory cell C 00  to the bit line BL 0 . Then, as illustrated in FIG. 4B, the potential of the bit line BL 0  becomes slightly negative relative to the potential of bit line BL 1 . Thus, a difference ΔV BL  &#39; in potential is generated between bit lines BL 0  and BL 1 , and, during the sensing mode, such difference ΔV BL  &#39; in potential is sensed by the sense amplifier S 0  &#39;. As a result, the lower-side potential of bit line BL 0  is decreased to V SS . 
     In the dynamic RAM device of FIG. 3, however, in order to push up the potential of the dummy word line DWL 1  to the level V CC , the operation clock generator CK 1  must generate a potential higher than V CC  +V th , that is, a potential of V CC  +V th  +α, and, the accordingly, operation clock generator CK 1  must incorporate a charge-pumping circuit or a bootstrap circuit each of which is not provided with the capability of quickly driving a heavy load including both the dummy word line DWL 1  and the word line WL 0 . Therefore, the operation speed of row selection, that is, the access speed of the device, becomes low. 
     FIG. 5 is a circuit diagram of a first embodiment of the dynamic RAM device according to the present invention. In FIG. 5 the elements which are the same as those of FIG. 3 are denoted by the same reference numerals as in FIG. 3. As the figure shows, if word line WL 0  is selected, dummy word line DWL 2  on the opposite side regarding the sense amplifiers S 0 , S 1 , . . . , and S 127  is selected. In addition, the charging transistor Q A  is connected to the reset clock generating circuit CK 2  while the discharging transistor Q B  is connected through transfer gate TG 128  to the operation clock signal generating circuit CK 1  which generates clock pulses φ WL  and φ WL  &#39; in reciprocal phase with the reset pulse φ R . 
     The operation of the circuit of FIG. 5 regarding only bit lines BL 0  and BL 0  will now be explained with reference to FIG. 6A. Assuming that memory cell C 00  stores data &#34;1&#34;, that is, that capacitor C m  of memory cell C 00  is charged, during the standby mode, the reset clock signal φ R  is high (V CC  +V th  +α), charging transistor Q A  is turned on so that capacitors C d  of dummy cells DC 20  &#39;, DC 21  &#39;, . . . , DC 2 ,126 &#39;, and DC 2 ,127 &#39; are charged, and, accordingly, the potential of dummy word line DWL 2  remains high (V CC ). Simultaneously, bit lines BL 0 , BL 0 , BL 1 , BL 1 , . . . , BL 126 , BL 126 , BL 127 , and BL 127  are precharged to level V CC . Next, during the selecting mode, the potential of clock signal φ R  is changed from the level V.sub. CC +V th  +α to the level V SS , however, the potential of clock signal φ WL  is changed from the level V SS  to the level V CC  +V th  +α. As a result, the potential of a selected word line WL 0  is changed in response to the potential of the clock signal φ WL . When clock signal φ WL  is changed, clock generator CK 1  simultaneously generates the clock signal φ WL  &#39; which is changed from V SS  to V CC  in common phase with the clock signal φ WL . Thus, charging transistor Q A  is turned off while discharging transistor Q B  is turned on. As a result, the potential of dummy word line DWL 2  is changed in opposite phase to the potential of clock signal φ WL  &#39;. Simultaneously, the bit lines assume a floating state. In this case, since bit line BL 0  is connected to dummy word line DWL 2  by the capacitive coupling of capacitors C d , the potential of bit line BL 0  is pulled down by an amount in proportion to the capacitance ratio of dummy cell capacitor C d  to bit line BL 0 . That is, the potential of dummy word line DWL 2  pulls down the potential of bit line BL 0  so that it is slightly negative relative to the potential of bit line BL 0 . Thus, a difference ΔV BL  in potential is generated between bit lines BL 0  and BL 0 , and, during the sensing mode, such difference is sensed by sense amplifier S 0 . As a result, the lower-side potential of bit line BL 0  is decreased to V SS . 
     Similarly, assuming that memory cell C 00  stores data &#34;0&#34;, that is, the capacitor C m  of memory cell C 00  is discharged and the potential of dummy word line DWL 2  also pulls down the potential of bit line BL 0 . However, current flows from bit line BL 0  into capacitor C m  of memory cell C 00  and, accordingly, the potential of bit line BL 0  is also pulled down by the capacity ratio of capacitor C m  of memory cell C 00  to bit line BL 0 . Dummy cell capacitor C d  is designed to have about half of the capacitance of one memory cell capacitor C m . Then, as illustrated in FIG. 6B, the potential of bit line BL 0  becomes slightly negative relative to the potential of bit line BL 0 . Thus, a difference in potential ΔV BL  &#39; is generated between bit lines BL 0  and BL 0 , and, during the sensing mode, such difference in potential is sensed by sense amplifier S 0 . As a result, the lower-side potential of bit line BL 0  is decreased to V SS . 
     In the dynamic RAM device of FIG. 5, operation clock generator CK 1  generates clock signals φ WL  having level V CC  +V th  +α and φ WL  &#39; having level V CC . However, it should be noted that the load driven by the clock signal φ WL  which requires a high level V CC  +V th  +α is reduced. As stated above, a clock signal having a level higher than V CC  is generated by a charge-pumping circuit, bootstrap circuit, or the like which usually has only an ability to drive a small load. Therefore, if the load which requires a clock signal having a level higher than V CC  is small, the operation speed of the operation clock generator CK 1  becomes high. As a result, the access speed of the device becomes high. 
     Note that generally in a memory device, the highest priority of design is to reduce the access time. Therefore, although reset clock generator CK 2  incorporates a charge-pumping circuit or a bootstrap circuit for generating a potential higher than V CC , this is not disadvantageous since the reset operation does not affect the access speed. 
     FIG. 7 is a circuit diagram of a second embodiment of the dynamic RAM according to the present invention. In FIG. 7, each of dummy cells DC 20  &#34;&#39;, DC 21  &#34;&#39;, . . . , and DC 2 ,127 &#34;&#39; comprises a discharging transistor Q B  &#39;, for discharging capacitor C d , instead of the discharging transistor Q B  of FIG. 5. In this case, discharging transistors Q B  &#39; are smaller than discharging transistor Q B  of FIG. 5. However, the operation of the circuit of FIG. 7 is substantially the same as that of the circuit of FIG. 5. Note that, in this case, dummy word line DWL 2  &#39; is not directly connected to capacitors C d  of dummy cells DC 20  &#34;, DC 21  &#34;, . . . , and DC 2 ,127 &#34;. In addition, the potential at node N 0 , N 1 , . . . , or N 127  of FIG. 7 corresponds to the potential of dummy word line DWL 2  of FIG. 5. 
     FIGS. 8A and 8B are also timing diagrams of the signals appearing in the circuit of FIG. 5 (or 7). In FIGS. 8A and 8B, it is assumed that the potential of the power supply V CC  fluctuates at the transition from the standby mode to the selecting mode. That is, since charging transistor Q A  is relatively large, the potential of dummy word line DWL 2  rapidly follows the fluctuation of the power supply potential V CC . However, since the bit lines have a large capacitance and, in addition, the precharging transistors are relatively small so as to limit current therethrough, the potential of the bit lines responds very slowly to fluctuation of the power supply voltage V CC . 
     In FIG. 8A, which corresponds to FIG. 6A, the power supply potential is decreased from V CC  to V CC  -ΔV CC . In this case, the potential of bit line BL 0  is not as decreased as in FIG. 6A. That is, in the case of reading data &#34;1&#34;, the difference ΔV BL  in potential becomes small. Consequently, the sensing speed is reduced, and an erroneous read operation may result. However, in FIG. 8B, which corresponds to FIG. 6B, the power supply potential is increased from V CC  to V CC  +ΔV CC . In this case, the potential of bit line BL 0  is decreased greatly as compared with FIG. 6B. That is, in the case of reading data &#34;0&#34;, the difference ΔV BL  &#39; in potential also becomes small. Consequently, the sensing speed is reduced, and an erroneous read operation may result. 
     In order to avoid fluctuation of the potential of the bit lines due to fluctuation of a power supply potential, according to the present invention, capacitor C d  of the dummy cell can also be charged by using the potential of the corresponding bit line. 
     FIG. 9 is a circuit diagram of a third embodiment of the dynamic RAM device according to the present invention. In FIG. 9, each of dummy cells DC 20  &#34;&#39;, DC 21  &#34;&#39;, . . . , and DC 2 ,127 &#34;&#39; comprises a charging transistor Q A  &#39; instead of charging transistor Q A  of the FIG. 7. That is, charging transistor Q A  &#39; of dummy cell DC 20  &#34;&#39; is connected between bit line BL 0  and node N O . Therefore, during the standby mode, even when power supply potential V CC  fluctuates rapidly, the potential at node N 0 , N 1 , . . . , or N 127  of capacitors C d  remains stable since the potential at node N 0 , N 1 , . . . , or N 127  follows the potential of bit line BL 0 , BL 1 , . . . , or E,ovs/BL/  127 , which potential does not fluctuate as much. Therefore, the above-mentioned unfavorable difference in potential, which reduces the sensing speed and may result in an erroneous read operation is not generated. 
     As explained hereinbefore, the dynamic RAM device according to the present invention is advantageous, as compared with the prior art as illustrated in FIG. 3, in that the access speed is high since it is unnecessary that the operation clock generator CK 1  drive a heavy load requiring a potential higher than V CC  during the selecting operation.