Patent Publication Number: US-2021193575-A1

Title: Manufacturing method of connection structure of semiconductor device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a division of application Ser. No. 15/730,744 filed on Oct. 12, 2017, now allowed, which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a connection structure of a semiconductor device and a manufacturing method thereof, and more particularly, to a connection structure including a top metal structure and a manufacturing method thereof. 
     2. Description of the Prior Art 
     In the semiconductor manufacturing related field, the size of functional devices (such as transistors) in the integrated circuits becomes smaller continuously for enhancing the performance of the chip. However, as the density of the functional devices increased, resistive-capacitive delay (RC delay) becomes an important issue influencing the performance of the devices. Accordingly, the RC delay has to be reduced by lowering the resistance of the metal interconnect structure and/or reducing the capacitance of the inter-layer dielectric (ILD) material. 
     In the metal interconnect structure, a protection layer may be formed on a top metal at a top portion of the metal interconnect structure and cover the top metal and the ILD. However, problems such as poor covering condition of the protection layer and cracks generated in the protection layer may occur because the top metal is much thicker than the protection layer generally. The metal interconnect structure disposed in the ILD or even the semiconductor devices under the ILD may be affected by the problems mentioned above, and the product manufacturing yield and the reliability may be deteriorated accordingly. 
     SUMMARY OF THE INVENTION 
     A connection structure of a semiconductor device and a manufacturing method thereof are provided in the present invention. A top metal structure including two sidewall sections with different slopes is used to improve covering condition of a passivation layer formed on the top metal structure and an interlayer dielectric, cracks in the passivation layer may be avoided, and the manufacturing yield and the reliability of the products may be enhanced accordingly. 
     According to an embodiment of the present invention, a connection structure of a semiconductor device is provided. The connection structure includes an interlayer dielectric, a top metal structure, and a passivation layer. The interlayer dielectric is disposed on a substrate. The top metal structure is disposed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. The passivation layer is conformally disposed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric. 
     According to an embodiment of the present invention, a manufacturing method of a connection structure of a semiconductor device is provided. The manufacturing method includes the following steps. Firstly, a substrate is provided. An interlayer dielectric is formed on the substrate. A top metal structure is formed on the interlayer dielectric. The top metal structure includes a bottom portion and a top portion disposed on the bottom portion. The bottom portion includes a first sidewall, and the top portion includes a second sidewall. A slope of the first sidewall is larger than a slope of the second sidewall. A passivation layer is conformally formed on the second sidewall, the first sidewall, and a top surface of the interlayer dielectric. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic drawing illustrating a connection structure of a semiconductor device according to an embodiment of the present invention. 
         FIGS. 2-4  are schematic drawings illustrating a manufacturing method of a connection structure of a semiconductor device according to an embodiment of the present invention, wherein  FIG. 3  is a flow chart of an etching process, and  FIG. 4  is a schematic drawing in a step subsequent to  FIG. 2 . 
     
    
    
     DETAILED DESCRIPTION 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic drawing illustrating a connection structure of a semiconductor device according to an embodiment of the present invention. As shown in  FIG. 1 , the connection structure  100  of the semiconductor device includes an interlayer dielectric (ILD)  20 , a top metal structure  40 P, and a passivation layer  60 . The interlayer dielectric  20  is disposed on a substrate  10 . The substrate may include a semiconductor substrate such as a silicon substrate, a silicon germanium substrate, or a silicon-on-insulator (SOI) substrate, but not limited thereto. In some embodiments, semiconductor units (such as silicon based field effect transistors, not shown) may be formed on the substrate  10  before the step of forming the interlayer dielectric  20 , and the interlayer dielectric  20  may be formed after the step of forming the semiconductor units and cover the semiconductor units, but not limited thereto. The material of the interlayer dielectric  20  may include silicon oxynitride, silicon oxide, or other appropriate dielectric materials. The top metal structure  40 P is disposed on the interlayer dielectric  20 . The top metal structure  40 P includes a bottom portion  41  and a top portion  42 . The top portion  42  is disposed on the bottom portion  41 , and the bottom portion  41  may be disposed between the interlayer dielectric  20  and the top portion  42  in a thickness direction (such as a first direction D 1  shown in  FIG. 1 ) of the substrate  10 . The bottom portion  41  includes a first sidewall SW 1 , and the top portion  42  includes a second sidewall SW 2 . A slope of the first sidewall SW 1  is larger than a slope of the second sidewall SW 2 . It is worth noting that a top surface (such as a first top surface S 20  shown in  FIG. 1 ) of the interlayer dielectric  20  is regarded as a horizontal surface in the calculation of the slope of the first sidewall SW 1  and the slope of the second sidewall SW 2 , but not limited thereto. In some embodiments, an included angle between the first sidewall SW 1  and the first top surface S 20  of the interlayer dielectric  20  may be larger than 45 degrees and smaller than 90 degrees, and the slope of the first sidewall SW 1  may be larger than 1, but not limited thereto. The material of the top metal structure  40 P may include aluminum (Al), silver (Ag), chromium (Cr), titanium (Ti), molybdenum (Mo), a compound of the above-mentioned materials, a stack layer of the above-mentioned materials, an alloy of the above-mentioned materials, or other suitable metal conductive materials. The passivation layer  60  is conformally disposed on the second sidewall SW 2 , the first sidewall SW 1 , the first top surface S 20  of the interlayer dielectric  20 , and a top surface (such as a second top surface S 42  shown in  FIG. 1 ) of the top metal structure  40 P. 
     In some embodiments, the passivation layer  60  may include a single layer structure or a multiple layer structure of insulation materials such as silicon nitride, silicon oxynitride, silicon oxide, or phosphosilicate glass (PSG), but not limited thereto. For example, the passivation layer  60  may include a first layer  61  and a second layer  62 . The first layer  61  may be conformally formed on the second sidewall SW 2 , the first sidewall SW 1 , the first top surface S 20  of the interlayer dielectric, and the second top surface S 42  of the top metal structure  40 P, and the second layer  62  may be conformally formed on the first layer  61 . Additionally, in some embodiments, the first layer  61  may be a PSG layer, and the second layer  62  may be a silicon nitride layer, but not limited thereto. 
     As shown in  FIG. 1 , in some embodiments, the top portion  42  of the top metal structure  40 P may be directly connected with the bottom portion  41  of the top metal structure  40 P, the second sidewall SW 2  of the top portion  42  may be directly connected with and directly contact the first sidewall SW 1  of the bottom portion  41 , and the first sidewall SW 1  of the bottom portion  41  may be directly connected with and directly contact the first top surface S 20  of the interlayer dielectric  20 . Additionally, the second sidewall SW of the top portion  42  may be directly connected with and directly contact the second top surface S 42 , and the top metal structure may be regarded as a narrow top and wide bottom structure. A cross-sectional shape of the top portion  42  and a cross-sectional shape of the bottom portion  41  may be a trapezoid respectively, and the bottom line of the trapezoid of the top portion  42  may be the top line of the trapezoid of the bottom portion  41 , but not limited thereto. Additionally, the top metal structure  40 P requires a specific thickness for reducing the bulk resistance of the top metal structure  40 P. For example, in some embodiments, a thickness (such as a first thickness T 40  shown in  FIG. 1 ) of the top metal structure  40 P may be larger than or equal to 14000 angstroms, but not limited thereto. Therefore, the first thickness T 40  of the top metal structure  40 P will be relatively larger than a thickness (such as a fourth thickness T 60  shown in  FIG. 1 ) of the passivation layer  60 . Compared with a top metal structure including a single slope sidewall only, the top metal structure  40 P in the present invention includes at least two sidewalls with different slopes for improving the covering condition of the passivation layer  60  formed on the top metal structure  40 P and the interlayer dielectric  20 . The stress of the passivation layer  60  at corners (such as a corner between the second sidewall SW 2  and the second top surface S 42  and/or a corner between the first sidewall SW 1  and the first top surface S 20 ) may be mitigated and released because the included angle between the second top surface S 42  and the second sidewall SW 2  becomes larger relatively. Cracks in the passivation layer  60  may be avoided, and the product manufacturing yield and the product reliability may be improved accordingly. 
     In some embodiments, for lowering the influence of the top portion  42  of the top metal structure  40 P on the bulk resistance of the top metal structure  40 P, a thickness (such as a second thickness T 41  shown in  FIG. 1 ) of the bottom portion  41  of the top metal structure  40 P may be larger than a thickness (such as a third thickness T 42  shown in  FIG. 1 ) of the top portion  42  of the top metal structure  40 P, but not limited thereto. In some embodiments, the third thickness T 42  of the top portion  42  of the top metal structure  40 P may be larger than the second thickness T 41  of the bottom portion  41  of the top metal structure  40 P for further improving the covering condition of the passivation layer  60  and reducing the probability of cracks generated in the passivation layer  60 . Additionally, in some embodiments, the connection structure  100  of the semiconductor device may further include an interconnection structure  30  disposed in the interlayer dielectric  20 , and the top metal structure may be electrically connected with the interconnection structure  30 . Semiconductor units (not shown) formed on the substrate  10  may be electrically connected with the top metal structure  40 P via the interconnection structure  30 . The interlayer dielectric  20 , the interconnection structure  30 , and the top metal structure  40 P may belong to the back end of line (BEOL) process of the semiconductor manufacturing process, but not limited thereto. In some embodiments, the interconnection structure  30  may include a metal layer  31  and a via plug  32 . The via plug  32  may be disposed between the metal layer  31  and the top metal structure  40 , and the top metal structure  40 P may be electrically connected with the metal layer  31  by the via plug  32 . In addition, a width (such as a first width W 31  shown in  FIG. 1 ) of the metal layer  31  in a horizontal direction (such as a second direction D 2  shown in  FIG. 1 ) may be smaller than a width (such as a second width W 41  shown in  FIG. 1 ) of the top metal structure  40 P in the horizontal direction, and the first thickness T 40  of the top metal structure  40 P may be larger than a thickness (such as a fifth thickness T 31  shown in  FIG. 1 ) of the metal layer  31  of the interconnection structure  30 , but not limited thereto. The metal layer  31  and the via plug  32  may be formed by forming recesses in the interlayer dielectric  20  and filling the recesses with a barrier layer and a conductive material, but not limited thereto. The barrier layer mentioned above may include titanium nitride, tantalum nitride, or other suitable barrier materials, and the conductive material mentioned above may include materials with relatively lower resistivity, such as copper, aluminum, or tungsten, but not limited thereto. In some embodiments, the interconnection structure  30  may be composed of a plurality of the metal layers  31  and a plurality of the via plugs  32  alternately disposed and connected with one another, but not limited thereto. 
     Please refer to  FIGS. 1-4 .  FIGS. 2-4  are schematic drawings illustrating a manufacturing method of a connection structure of a semiconductor device according to an embodiment of the present invention.  FIG. 3  is a flow chart of an etching process,  FIG. 4  is a schematic drawing in a step subsequent to  FIG. 2 , and  FIG. 1  may be regarded as a schematic drawing in a step subsequent to  FIG. 4 . As shown in  FIG. 1 , the manufacturing method of the connection structure  100  of the semiconductor device in this embodiment may include the following steps. Firstly, the substrate  10  is provided. The interlayer dielectric  20  is formed on the substrate  10 . The top metal structure  40 P is formed on the interlayer dielectric  20 . The top metal structure  40 P includes the bottom portion  41  and the top portion  42  disposed on the bottom portion  41 . The bottom portion  41  includes the first sidewall SW 1 , and the top portion  42  includes the second sidewall SW 2 . The slope of the first sidewall SW 1  is larger than the slope of the second sidewall SW 2 . The passivation layer  60  is conformally formed on the second sidewall SW 2 , the first sidewall SW 1 , and the first top surface S 20  of the interlayer dielectric  10 . 
     Specifically, the method of forming the top metal structure  40 P in this embodiment may include but is not limited to the following steps. As shown in  FIG. 2 , a top metal layer  40  is formed on the interlayer dielectric  20 , and a patterned photoresist layer  40  is then formed on the top metal layer  40 . Subsequently, an etching process  91  is performed to the top metal layer  40  with the patterned photoresist layer  40  as a mask for forming the top metal structure  40 P shown in  FIG. 1 . As shown in  FIG. 2  and  FIG. 3 , in some embodiments, the etching process  91  may include a main etching step performed at step SP 1  and an over etching step performed at step SP 2 . In other words, the over etching step may be performed after the main etching step. 
     As shown in  FIGS. 2-4 , the main etching step may be used to etch the top metal layer  40  which is not covered by the patterned photoresist layer  50  and expose at least a part of the first top surface S 20  of the interlayer dielectric  20 , and the over etching step may be used to further etch the top metal layer  40  for forming the demanded distribution of the first sidewall SW 1  and the second sidewall SW 2 . In some embodiments, the main etching step may have a first etching rate (may be regarded as R 1 , for example) to the patterned photoresist layer  50 , the over etching step may have a second etching rate (may be regarded as R 2 , for example) to the patterned photoresist layer  50 , and the first etching rate is higher than the second etching rate. Additionally, the main etching step may have a third etching rate (may be regarded as R 3 , for example) to the top metal layer  40 , the over etching step may have a fourth etching rate (may be regarded as R 4 , for example) to the top metal layer  40 , and a ratio of the third etching rate to the first etching rate (such as R 3 /R 1 ) is lower than a ratio of the fourth etching rate to the second etching rate (such as R 4 /R 2 ). In other words, the main etching step has a more significant etching effect on the photoresist layer  50  in compared with the over etching step, and the etching selectivity to the top metal layer  40  in the main etching step is lower than the etching selectivity to the top metal layer  40  in the over etching step. In some embodiments, the etching characteristics of the main etching step mentioned above may be achieved by lowering the manufacturing pressure and increasing the ion bombardment effect, and the top metal layer  40  adjoining the patterned photoresist layer  50  may be etched by the main etching step for forming the condition similar to the second sidewall SW 2 , but not limited thereto. Additionally, in some embodiments, more polymers may be generated to protect the sidewall by modifying the ratio of the process gas in the over etching step, and the first sidewall SW which is steeper may be formed accordingly, but not limited thereto. It is worth noting that the thickness of the patterned photoresist layer  50  has to be increased relatively for ensuring the effect of being a mask in the etching process  91  because the etching rate to the patterned photoresist layer  50  is increased relatively in the main etching step. For instance, the thickness of the patterned photoresist layer  50  may be larger than or equal to 35000 angstroms, but not limited thereto. 
     As shown in  FIG. 2  and  FIG. 4 , the patterned photoresist layer  50  may be removed after the etching process  91 . Subsequently, as shown in  FIG. 1 , the passivation layer  60  is conformally formed on and covers the first top surface S 20  of the interlayer dielectric  20 , the first sidewall SW 1 , the second sidewall SW 2 , and the second top surface S 42  of the top metal structure  40 P. Additionally, the manufacturing method of the connection structure  100  of the semiconductor device may further include forming the interconnection structure  30  in the interlayer dielectric  20 . The interconnection structure  30  may be formed before the step of forming the top metal structure  40 P, and the top metal structure  40 P may be electrically connected with the interconnection structure  30 . 
     To summarize the above descriptions, in the connection structure of the semiconductor device and the manufacturing method thereof according to the present invention, the top metal structure including at least two sidewalls with different slopes may be formed by the etching process, and the covering condition of the passivation layer formed on the top metal structure and the interlayer dielectric may be improved accordingly. In addition, the stress of the passivation layer at the corners covered by the passivation layer may be mitigated for avoiding cracks in the passivation layer, and the purpose of improving the product manufacturing yield and the product reliability may be achieved accordingly. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.