Patent Publication Number: US-8116143-B2

Title: Method of erasing memory cell

Description:
RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 12/614,750, titled “MEMORY ARRAY SEGMENTATION AND METHODS,” filed Nov. 9, 2009 now U.S. Pat. No. 7,903,464 (allowed), which application is a divisional of U.S. application Ser. No. 11/349,854, titled “MEMORY ARRAY SEGMENTATION AND METHODS,” filed Feb. 8, 2006, and issued as U.S. Pat. No. 7,616,489 on Nov. 10, 2009, both of which applications are commonly assigned and incorporated entirely herein by reference. 
    
    
     FIELD 
     The present invention relates generally to memory devices and in particular the present invention relates to segmented memory arrays. 
     BACKGROUND 
     Memory devices are typically provided as internal storage areas in computers. The term memory identifies data storage that comes in the form of integrated circuit chips. In general, memory devices contain an array of memory cells for storing data, and row and column decoder circuits coupled to the array of memory cells for accessing the array of memory cells in response to an external address. 
     One type of memory is a non-volatile memory known as flash memory. A flash memory is a type of EEPROM (electrically-erasable programmable read-only memory) that can be erased and reprogrammed in blocks. Many modern personal computers (PCs) have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in wireless electronic devices because it enables the manufacturer to support new communication protocols as they become standardized and to provide the ability to remotely upgrade the device for enhanced features. 
     A typical flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge on the floating gate. 
     A NAND flash memory device is a common type of flash memory device, so called for the logical form the basic memory cell configuration. The control gate of each memory cell of a row of the array is connected to a word-select line. The memory cells of the array are arranged together in strings (often termed NAND strings), typically of 32 each, with the memory cells coupled together in series, source to drain, between a source line and a column bit line. The memory array for NAND flash memory devices is then accessed by a row decoder activating a row of memory cells by selecting the word-select line coupled to a control gate of a memory cell. In addition, the word-select lines coupled to the control gates of unselected memory cells of each string are driven to operate the unselected memory cells of each string as pass transistors, so that they pass current in a manner that is unrestricted by their stored data values. Current then flows from the source line to the column bit line through each series coupled string, restricted only by the selected memory cells of each string. This places the current-encoded data values of the row of selected memory cells on the column bit lines. 
     Sometimes a portion of the memory cells coupled to a selected word line is targeted for programming. This involves applying a programming voltage to the word line and thus to the control gate of each memory cell coupled to the selected word line, regardless of whether a memory cell is targeted or untargeted for programming. While the programming voltage is applied to the selected word line, a potential, such as a ground potential, is applied to the substrate on which the memory cells are formed and thus to the channels of these memory cells. This produces voltage differences that can disturb the threshold voltages Vt of the untargeted memory cells coupled to the selected word line and partially program these memory cells. This is commonly referred to as a programming-voltage disturbance (or stress). Successive programming operations may have a cumulative effect in that each programming operation partially programs the untargeted cells until the untargeted cells become programmed undesirably. 
     Moreover, a voltage that is not sufficient for programming the memory cells, typically referred to as a pass voltage, is applied to the remaining (or unselected) word lines to turn on the memory cells coupled to these word lines so that these memory cells can operate as pass transistors. The voltage difference between the pass voltage applied to the unselected word lines and the channels of the memory cells coupled to the unselected word lines can disturb the threshold voltages of these memory cells and partially program them. This is commonly referred to a pass-voltage disturbance (or stress). Successive applications of the pass voltage may have a cumulative effect in that each application partially programs the cells until they become programmed undesirably. 
     For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for alternative memory array structures and programming operations. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustration of an integrated circuit device, according to an embodiment of the invention. 
         FIG. 2  illustrates a NAND memory array in accordance with another embodiment of the invention. 
         FIG. 3  is a cross-sectional view of a structure suitable for use in fabricating a memory array, according to another embodiment of the invention. 
         FIG. 4  is an illustration of an exemplary memory module. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description of the invention, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, specific embodiments in which the invention may be practiced. In the drawings, like numerals describe substantially similar components throughout the several views. These embodiments are described in sufficient detail to enable those skilled in the art to practice the invention. Other embodiments may be utilized and structural, logical, and electrical changes may be made without departing from the scope of the present invention. Use the following if applicable: The term wafer or substrate used in the following description includes any base semiconductor structure. Both are to be understood as including silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin film transistor (TFT) technology, doped and undoped semiconductors, epitaxial layers of a silicon supported by a base semiconductor structure, as well as other semiconductor structures well known to one skilled in the art. Furthermore, when reference is made to a wafer or substrate in the following description, previous process steps may have been utilized to form regions/junctions in the base semiconductor structure, and terms wafer or substrate include the underlying layers containing such regions/junctions. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims and equivalents thereof. 
       FIG. 1  is a block diagram illustration of an integrated circuit device, such as a processor, a memory device  102 , etc., according to an embodiment of the invention. The memory device  102  may be fabricated as semiconductor device on a semiconductor substrate. 
     For one embodiment, memory device  102  includes an array of flash memory cells  104 , an address decoder  106 , row access circuitry  108 , column access circuitry  110 , control circuitry  112 , Input/Output (I/O) circuitry  114 , and an address buffer  116 . Column access circuitry  110  includes multiplexing circuitry in accordance with embodiments of the invention. Control circuitry  112  is adapted to perform operations of the invention. 
     Memory device  102  may be coupled an external microprocessor  120 , or memory controller, for memory accessing as part of an electronic system. The memory device  102  receives control signals from the processor  120  over a control link  122 . The memory cells are used to store data that are accessed via a data (DQ) link  124 . Address signals are received via an address link  126  that are decoded at address decoder  106  to access the memory array  104 . Address buffer circuit  116  latches the address signals. The memory cells are accessed in response to the control signals and the address signals. 
     The memory array  104  includes memory cells arranged in row and column fashion and having a NAND architecture. For one embodiment, each of the memory cells includes a floating-gate field-effect transistor capable of holding a charge. The cells may be grouped into blocks. Each of the cells within a block can be electrically programmed on an individual basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. Memory array  104  is formed in accordance with embodiments of the invention. It will be appreciated by those skilled in the art that additional circuitry and control signals can be provided, and that the memory device of  FIG. 1  has been simplified to help focus on the invention. Memory array  104  can further include other types of memory cells that can define a data value by a change in threshold voltage. 
       FIG. 2  illustrates a NAND memory array  200  as a portion of memory array  102  in accordance with another embodiment of the invention. For one embodiment, memory array  200  includes one or more memory blocks  201 . For another embodiment, memory array includes memory sectors  203 , each including portions of the one or more memory blocks  201 . 
     As shown in  FIG. 2 , the memory array  200  includes word lines  202   1  to  202   N  and intersecting local bit lines  204   1  to  204   M . Memory array  200  includes NAND strings  206   1  to  206   M . Each NAND string includes floating gate transistors  208   1  to  208   N , each located at an intersection of a word line  202  and a local bit line  204 . The floating gate transistors  208  represent non-volatile memory cells for storage of data. The floating gate transistors  208  of each NAND string  206  are connected in series, source to drain, between a source select gate  210 , e.g., a field effect transistor (FET), and a drain select gate  212 , e.g., an FET. Each source select gate  210  is located at an intersection of a local bit line  204  and a source select line  214 , while each drain select gate  212  is located at an intersection of a local bit line  204  and a drain select line  215 . 
     A source of each source select gate  210  of a sector  203  is connected to a common source line  216  for that sector  203 . Note that a separate source line  216  is formed in each sector  203  and that source line  203  is electrically isolated from the other source lines  203 . For example source lines  216   1 - 216   L  are respectively formed in sectors  203   1 - 203   L , as shown in  FIG. 2 . The drain of each source select gate  210  is connected to the source of the first floating gate transistor  208  of the corresponding NAND string  206 . For example, the drain of source select gate  210   1  is connected to the source of floating gate transistor  208   1  of the corresponding NAND string  206   1 . A control gate  220  of each source select gate  210  is connected to source select line  214 . It is common for a common source line to be connected between source select gates for NAND strings of two different NAND arrays. As such, the two NAND arrays share the common source line. 
     The drain of each drain select gate  212  is connected to the local bit line  204  for the corresponding NAND string at a drain contact  228 . For example, the drain of drain select gate  212   1  is connected to the local bit line  204   1  for the corresponding NAND string  206   1  at drain contact  228   1 . The source of each drain select gate  212  is connected to the drain of the last floating gate transistor  208   N  of the corresponding NAND string  206 . For example, the source of drain select gate  212   1  is connected to the drain of floating gate transistor  208   N  of the corresponding NAND string  206   1 . It is common for two NAND strings to share the same drain contact. 
     Typical construction of floating gate transistors  208  includes a source  230  and a drain  232 , a floating gate  234 , and a control gate  236 , as shown in  FIG. 2 . Floating gate transistors  208  have their control gates  236  coupled to a word line  202 . A column of memory array includes a source select gate  210 , a drain select gate  212 , and a NAND string  206  of memory cells  208  coupled therebetween and thereby coupled to a given local bit line  204 . A row of the floating gate transistors  208  are those transistors commonly coupled to a given word line  202 . 
     Note that although a separate source line  216  is formed in each sector  203 , drain select line  215 , source select line  214 , and the word lines  208  are common to each of sectors  203 . That is, drain select gates  212  of the respective sectors  203  are commonly coupled to drain select line  215 ; source select gates  210  of the respective sectors  203  are commonly coupled to source select line  214 ; and the memory cells  208  of corresponding rows of memory cells  208  of the respective sectors  203  are commonly coupled to a word line  202 . 
       FIG. 3  is a cross-sectional view of a structure suitable for use in fabricating a memory array, such as memory array  200  of  FIG. 2 , according to another embodiment of the invention. Formation of such structures is well understood in the arts and will not be detailed herein. A substrate  300  has a first conductivity type, e.g., a p-type conductivity. Substrate  300  includes a well region  302  as a semiconductor region having a second conductivity type different from the first conductivity type. For example, the second conductivity type may be opposite the first conductivity type, e.g., an n-type conductivity opposite the p-type conductivity. Well region  302  may be formed in substrate  300  through such processing methods as doping a portion of substrate  300  to the appropriate conductivity by implantation or diffusion of dopant ions. Substrate  300  further includes well regions  304  as semiconductor regions having the first conductivity type. Each well region  304  may be formed in well region  302 . For example, well regions  304  may be formed, for one embodiment, by forming a mask layer (not shown) overlying well region  302 , subsequently patterning the mask layer for exposing portions of well region  302  corresponding to the future well regions  304 , and doping the exposed regions with the appropriate dopant ions. 
     Each well region  304  is electrically isolated from other portions of the substrate  300  having the first conductivity type and from each other by the well region  302 . Well region  302  is interposed between substrate  300  and well region  304 . Well regions  304   1 - 304   L  respectively have one or more contacts  308   1 - 308   L  for coupling to other potential nodes. 
     For one embodiment, the structure of  FIG. 3  may include an n-well as well region  302  formed in a p-type substrate as the substrate  300 . P-wells may be formed in the n-well as the respective well regions  304 . Note that well regions  304  are separated from each other as well as other areas of substrate  300  having the same conductivity type by an interposing region of the different conductivity type, e.g., well region  302 . 
     Note that  FIG. 3  is along a row direction of a memory array, such as memory array  200  of  FIG. 2 . Therefore, columns of memory cells run perpendicular to the drawing of  FIG. 3 . Memory sectors, such as memory sectors  203   1 - 203   L  of  FIG. 2 , respectively include well regions  304   1 - 304   L . Source and drain regions of the memory cells, e.g., source regions  230  and drain regions  232  of memory cells  208  of  FIG. 2 , are formed in well regions  304 , and gate stacks of memory cells  208 , e.g., including floating gates  234  and control gates  236  of  FIG. 2 , are formed on well regions  304 . Well regions  304  form the channel regions of the memory cells for one embodiment, as is known in the art. Note further that a source line, such as a source line  216  of  FIG. 2 , is formed in each of well regions  304  and that the source lines respectively formed in well regions  304  are electrically isolated from each other. 
     One or more target memory cells  208 , e.g., circled memory cell  208   1  of  FIG. 2 , corresponding to a selected word line  202 , e.g., word line  202   1  of  FIG. 2 , and formed in a memory sector  203 , e.g., memory sector  203   1  of  FIG. 2 , may be programmed according to the following example for one embodiment: To program targeted memory cell  208   1 , a programming voltage WL S , e.g., about 20 volts, is applied to selected word line  202   1 , and a pass voltage WL US , e.g., about 10 volts, is applied to the remaining (or unselected) word lines not coupled to target memory cell  208   1 . The pass voltage WL US  is not sufficient for programming the memory cells and has the effect of turning the memory cells of the unselected word lines to an ON condition, regardless of the programmed state of their internal floating gate. Turning the memory cells of the unselected word lines to an ON condition allows them to pass a bit line voltage BL 1 , e.g., Vss or about zero volts, of the bit line, e.g., bit line  204   1 , coupled to the NAND string, e.g., NAND string  206   1 , that includes target memory cell  208   1 . 
     In addition, a voltage SG(D), e.g., about 1 volt, is applied to drain select line  215  and thus to the control gates of each of drain select gates  212 . A voltage SG(S), e.g., Vss or about zero volts, is applied to source select line  214  and thus to the control gates of each of source select gates  210 . An inhibit voltage BL, such as Vcc, e.g., about 1.8 volts, is applied to the bit lines, e.g., bit lines  204   2  to  204   M , respectively coupled to the NAND strings not including target memory cell  208   1 . Inhibit voltage BL acts prevent programming of untargeted memory cells of the selected word line to keep them in an erased state and thus leave them unchanged, e.g., at a logic high. A voltage SL( 1 ), such as Vcc, e.g., about 1.8 volts, is applied to source line  216   1  of sector  203   1 . Optionally, voltages SL( 2 ) to SL(L), such as Vcc, e.g., about 1.8 volts, may applied to the remaining source lines, e.g., source lines  216   2  to  216   L  respectively of sectors  203   2  to  203   L , for one embodiment. 
     Note that an inherent boosting of the channel voltage of the untargeted memory cells occurs when a voltage, such as programming voltage WL S  or pass voltage WL US , is applied to the word lines and when an inhibit voltage BL is applied to the bit lines coupled to the NAND strings not including memory cells targeted for programming. For example, the voltage of the channel voltage of the untargeted memory cells may be boosted to about 30 percent of the difference between a voltage (programming or pass voltage) applied to a word line and a voltage applied to the wells  304  ( FIG. 3 ) corresponding to the sectors  203  that do not include any targeted memory cells  208 . 
     For some conventional programming operations, the difference between the word line voltage (programming or pass voltage) and the channel voltage is sufficiently high to partially program the untargeted memory cells. Successive applications of the word line voltage may also have a cumulative effect in that each application partially programs the untargeted memory cells until they become fully programmed. Note that the difference between a programming voltage applied to selected word lines and a channel voltage of untargeted memory cells coupled to the selected word lines is often referred to as a programming-voltage disturbance (or stress) that acts to disturb the threshold voltages Vts of the untargeted memory cells. The difference between a pass voltage applied to unselected word lines and a channel voltage of the memory cells coupled to the unselected word lines is often referred to as a pass-voltage disturbance (or stress) that acts to disturb the threshold voltages Vts of the memory cells. 
     To reduce the likelihood of partially or fully programming untargeted memory cells coupled to selected and unselected word lines, e.g., to reduce the programming- and pass-voltage disturbances, a voltage is applied to wells  304   2  to  304   L  ( FIG. 3 ) respectively corresponding to sectors  203   2  to  203   L  that do not include any targeted memory cells. When a voltage is applied to the word lines, the voltage of the channels of the untargeted memory cells of memory sectors  203   2  to  203   L  coupled to the word lines is boosted above the voltage applied to the corresponding wells  304   2  to  304   L  by a percentage of the difference between the voltage applied to the word lines and the voltage applied to a well. Note that inhibit voltage BL is applied to the NAND strings that include these memory cells. 
     For one embodiment, the voltage applied to wells  304   2  to  304   L  is substantially equal to the pass voltage pass voltage WL US  applied to the unselected word lines. This acts to cause the voltage of the channels of the untargeted memory cells of memory sectors  203   2  to  203   L  to be substantially the pass voltage WL US  and thus acts to substantially eliminate the pass-voltage disturbance of the memory cells coupled to the unselected word lines. Moreover, the programming-voltage disturbance of the untargeted memory cells coupled to the selected word line is substantially reduced. 
     In one example, when a voltage applied to the wells  304   2  to  304   1 , ( FIG. 3 ), respectively corresponding to sectors  203   2  to  203   L  ( FIG. 2 ) that do not include any targeted memory cells is substantially equal to the pass voltage WL US  of about 10 volts applied to the unselected word lines, the difference between the pass voltage WL US  applied to the unselected word lines and the channels of the untargeted memory cells of sectors  203   2  to  203   L  is substantially zero and the pass-voltage disturbance is substantially eliminated. Note that the NAND strings that include untargeted memory cells of sectors  203   2  to  203   L  are coupled to inhibit voltage BL. 
     With a programming voltage WL S  of about 20 volts applied to selected word line  202   1 , the channels of the untargeted memory cells of sectors  203   2  to  203   L  coupled to selected word line  202   1  get boosted to some fraction, e.g., about 30 percent, of the difference between programming voltage WL s  and the voltage applied to wells  304   2  to  304   L , or to about 3 volts, above the voltage (10 volts) applied to wells  304   2  to  304   L , e.g., the channel voltage is about 13 volts. Therefore, the difference between the programming voltage WL S  of about 20 volts and the channel voltage of about 13 volts is about 7 volts. 
     Note that when a well is grounded, as often occurs for conventional programming, the channel voltage is about 6 volts for 20 volts applied to a selected word line, and the difference between the programming voltage WL S  of about 20 volts and the channel voltage of about 6 volts is about 14 volts. Therefore, applying a voltage to the wells corresponding to memory sectors having no targeted memory cells acts to substantially reduce the programming-voltage disturbance of these memory cells. 
     To erase selected memory cell  208   1 , the selected word line  202   1  coupled to selected memory cell  208   1  is grounded, and an erase voltage, e.g., substantially equal to the programming voltage WL s , such as about 20 volts, is applied to the well  304   1  ( FIG. 3 ) corresponding to the memory sector  203   1  that includes the selected memory cell  208   1 . The erase voltage is applied to the remaining (or unselected) word lines, and for one embodiment, a voltage, e.g., substantially equal to the pass voltage WL US , such as about 10 volts, is applied to the wells  304  ( FIG. 3 ) corresponding to the memory sectors  203  that do not include any the selected memory cells. 
       FIG. 4  is an illustration of an exemplary memory module  400 . Memory module  400  is illustrated as a memory card, although the concepts discussed with reference to memory module  400  are applicable to other types of removable or portable memory, e.g., USB flash drives, and are intended to be within the scope of “memory module” as used herein. In addition, although one example form factor is depicted in  FIG. 4 , these concepts are applicable to other form factors as well. 
     In some embodiments, memory module  400  will include a housing  405  (as depicted) to enclose one or more memory devices  410 , though such a housing is not essential to all devices or device applications. At least one memory device  410  may be a NAND flash memory device having a memory array formed in accordance with the methods of the invention. At least one memory device  410  includes isolation regions formed in accordance with the invention. Where present, the housing  405  includes one or more contacts  415  for communication with a host device. Examples of host devices include digital cameras, digital recording and playback devices, PDAs, personal computers, memory card readers, interface hubs and the like. For some embodiments, the contacts  415  are in the form of a standardized interface. For example, with a USB flash drive, the contacts  415  might be in the form of a USB Type-A male connector. For some embodiments, the contacts  415  are in the form of a semi-proprietary interface, such as might be found on CompactFlash™ memory cards licensed by SanDisk Corporation, Memory Stick™ memory cards licensed by Sony Corporation, SD Secure Digital™ memory cards licensed by Toshiba Corporation and the like. In general, however, contacts  415  provide an interface for passing control, address and/or data signals between the memory module  400  and a host having compatible receptors for the contacts  415 . 
     The memory module  400  may optionally include additional circuitry  420  which may be one or more integrated circuits and/or discrete components. For some embodiments, the additional circuitry  420  may include a memory controller for controlling access across multiple memory devices  410  and/or for providing a translation layer between an external host and a memory device  410 . For example, there may not be a one-to-one correspondence between the number of contacts  415  and a number of I/O connections to the one or more memory devices  410 . Thus, a memory controller could selectively couple an I/O connection (not shown in  FIG. 4 ) of a memory device  410  to receive the appropriate signal at the appropriate I/O connection at the appropriate time or to provide the appropriate signal at the appropriate contact  415  at the appropriate time. Similarly, the communication protocol between a host and the memory module  400  may be different than what is required for access of a memory device  410 . A memory controller could then translate the command sequences received from a host into the appropriate command sequences to achieve the desired access to the memory device  410 . Such translation may further include changes in signal voltage levels in addition to command sequences. 
     The additional circuitry  420  may further include functionality unrelated to control of a memory device  410  such as logic functions as might be performed by an ASIC (application specific integrated circuit). Also, the additional circuitry  420  may include circuitry to restrict read or write access to the memory module  400 , such as password protection, biometrics or the like. The additional circuitry  420  may include circuitry to indicate a status of the memory module  400 . For example, the additional circuitry  420  may include functionality to determine whether power is being supplied to the memory module  400  and whether the memory module  400  is currently being accessed, and to display an indication of its status, such as a solid light while powered and a flashing light while being accessed. The additional circuitry  420  may further include passive devices, such as decoupling capacitors to help regulate power requirements within the memory module  400 . 
     CONCLUSION 
     Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement that is calculated to achieve the same purpose may be substituted for the specific embodiments shown. Many adaptations of the invention will be apparent to those of ordinary skill in the art. Accordingly, this application is intended to cover any adaptations or variations of the invention. It is manifestly intended that this invention be limited only by the following claims and equivalents thereof.