Patent Publication Number: US-7215581-B2

Title: Triple redundant latch design with low delay time

Description:
FIELD OF THE INVENTION 
   This invention relates generally to latch design. More particularly, this invention relates to improving soft error immunity in latches. 
   BACKGROUND OF THE INVENTION 
   High-energy neutrons lose energy in materials mainly through collisions with silicon nuclei that lead to a chain of secondary reactions. These reactions deposit a dense track of electron-hole pairs as they pass through a p-n junction. Some of the deposited charge will recombine, and some will be collected at the junction contacts. When a particle strikes a sensitive region of a latch, the charge that accumulates could exceed the minimum charge that is needed to “flip” the value stored on the latch, resulting in a soft error. 
   The smallest charge that results in a soft error is called the critical charge of the latch. The rate at which soft errors occur (SER) is typically expressed in terms of failures in time (FIT). 
   A common source of soft errors are alpha particles which may be emitted by trace amounts of radioactive isotopes present in packing materials of integrated circuits. “Bump” material used in flip-chip packaging techniques has also been identified as a possible source of alpha particles. 
   Other sources of soft errors include high-energy cosmic rays and solar particles. High-energy cosmic rays and solar particles react with the upper atmosphere generating high-energy protons and neutrons that shower to the earth. Neutrons can be particularly troublesome as they can penetrate most man-made construction (a neutron can easily pass through five feet of concrete). This effect varies with both latitude and altitude. In London, the effect is two times worse than on the equator. In Denver, Colo. with its mile-high altitude, the effect is three times worse than at sea-level San Francisco. In a commercial airplane, the effect can be 100–800 times worse than at sea-level. 
   Radiation induced soft errors are becoming one of the main contributors to failure rates in microprocessors and other complex ICs (integrated circuits). Several approaches have been suggested to reduce this type of failure. Adding ECC (Error Correction Code) or parity in data paths approaches this problem from an architectural level. Adding ECC or parity in data paths can be complex and costly. 
   At the circuit level, SER may be reduced by increasing the ratio of capacitance created by oxides to the capacitance created by p/n junctions. The capacitance in a latch, among other types, includes capacitance created by p/n junctions and capacitance created by oxides. Since electron/holes pairs are created as high-energy neutrons pass through a p/n junction, a reduction in the area of p/n junctions in a latch typically decreases the SER. Significant numbers of electron/hole pairs are not created when high-energy neutrons pass through oxides. As a result, the SER may typically be reduced by increasing the ratio of oxide capacitance to p/n junction capacitance in a SRAM cell. 
   There is a need in the art to reduce the SER in latches. An embodiment of this invention reduces the SER in latches while adding only a small increase in physical size of the latch and a small increase in the delay time through the latch. 
   SUMMARY OF THE INVENTION 
   In a preferred embodiment, the invention provides a circuit and method for a smaller and faster triple redundant latch. Three settable memory elements set an identical logical value into each settable memory element. After the settable memory elements are set, a voting structure with inputs from the first settable memory element, the second memory element, and control to the settable memory elements determines the logical value held on the third settable memory element. The propagation delay through the third settable memory element is the only propagation delay of the triple redundant latch. 
   Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a schematic of a triple redundant latch. Prior Art 
       FIG. 2  is a block diagram of an embodiment of an improved triple redundant latch. 
       FIG. 3  is a block diagram of an improved triple redundant latch. 
       FIG. 4  is a schematic of an improved triple redundant latch. 
   

   DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT 
     FIG. 1  is a schematic of a triple redundant latch. The input,  100 , to the triple redundant latch is connected to the input of transfer gates, TG 1 , TG 2 , and TG 3 . Control signal,  102 , is connected to transfer gates, TG 1 , TG 2 , and TG 3 . Control signal,  102 , controls when the signal on the input of transfer gates, TG 1 , TG 2 , and TG 3  is transferred to the outputs,  104 ,  106 , and  108  of transfer gates, TG 1 , TG 2 , and TG 3  respectively. The signal presented to outputs,  104 ,  106 , and  108 , is stored in LATCH 1 , LATCH 2 , and LATCH 3  respectively. 
   After control signal,  102 , is turned off, the signal on LATCH 1  drives the input of inverter, INV 1 . After control signal,  102 , is turned off, the signal on LATCH 2  drives the input of inverter, INV 2 . After control signal,  102 , is turned off, the signal on LATCH 3  drives the input of inverter, INV 3 . The output,  110 , of inverter, INV 1 , drives an input to AND 1  and an input to AND 2 . The output,  112 , of inverter, INV 2 , drives an input to AND 1  and an input to AND 3 . The output,  114 , of inverter, INV 3 , drives an input to AND 2  and an input to AND 3 . The output,  116 , of AND 1  drives an input of OR 1 . The output,  118 , of AND 2  drives an input of OR 1 . The output,  120 , of AND 3  drives an input of OR 1 . The output of the triple redundant latch is the output,  122  of OR 1 . 
   A triple redundant latch reduces soft errors by storing the same data in three different latches. For example, when the control signal,  102  is on, a logical high value may be driven from the inputs,  100 , of transfer gates, TG 1 , TG 2 , and TG 3  to the outputs,  104 ,  106 , and  108 , of transfer gates, TG 1 , TG 2 , and TG 3  respectively. After turning control signal  102  off, a logical high value is stored in latches, LATCH 1 , LATCH 2 , and LATCH 3 . The stored logical high value on LATCH 1  drives the input of inverter, INV 1 , and produces a logical low value on the output,  110 , of inverter, INV 1 . The stored logical high value on LATCH 2  drives the input of inverter, INV 2 , and produces a logical low value on the output,  112 , of inverter, INV 2 . The stored logical high value on LATCH 3  drives the input of inverter, INV 3 , and produces a logical low value on the output,  114 , of inverter, INV 3 . 
   Since the output,  110 ,  112 , and  114  of inverters, INV 1 , INV 2 , and INV 3 , respectively, are low, all the inputs,  110 ,  112 , and  114  to AND 1 , AND 2 , and AND 3  respectively are a logical low value. Since all the inputs,  110 ,  112 , and  114 , to AND 1 , AND 2 , and AND 3  respectively are a logical low value, the output,  116 ,  118 , and  120  of AND 1 , AND 2 , and AND 3  respectively are a logical low value. Since the output,  116 ,  118 , and  120  of AND 1 , AND 2 , and AND 3 , respectively are a logical low value, all the inputs of OR 1  are a logical low value. Since all the inputs,  116 ,  118 , and  120  to OR 1  are logical low value, the output,  122 , is logical low value. 
   If a soft error occurs, for example, in LATCH 2 , and changes the stored logical value from a logical high value to a logical low value, a logical low value is now presented to the input,  106 , of inverter, INV 2 . The output,  112 , of inverter, INV 2 , presents a logical high value to an input of AND 1  and AND 3 . Since, in this example, the other input,  110  to AND 1  and the other input,  114 , to AND 3 , is a logical low value, the output,  116  and  120  of AND 1  and AND 3  respectively remains a logical low value and the output,  122 , does not change. This example illustrates how a single soft error in one latch does not change the original stored value in a triple redundant latch. 
   As a further example, assume, in addition to the soft error in LATCH 2 , there is an additional soft error in LATCH 3 . Now, the input,  108 , to inverter, INV 3 , is a logical low value and as a result, the output,  114 , of inverter, INV 3 , is a logical high value. A logical high value in now presented to an input,  114 , of AND 2 , and to an input,  114 , of AND 3 . Since a logical low and logical high value are presented on the inputs of AND 1 , the output,  116  of AND 1  is still a logical low value. Since a logical low and logical high value are presented on the inputs of AND 2 , the output,  118  of AND 2  is still a logical low value. However, since inputs,  112  and  114 , to AND 3  are a logical high value, the output,  120 , is a logical high value. Since input,  120 , to OR 1  is a logical high value, the output,  122 , changes from a logical low value to a logical high value. This example illustrates how soft errors in two latches of a triple redundant latch do change the original stored value of the triple redundant latch. 
   A triple redundant latch prevents a single soft error from changing the original value stored in the latch. However, this comes at the cost of additional circuitry which results in a physically larger latch. In addition, a triple redundant may introduce time delay in the delay path of the latch. As consequence, a triple redundant latch is usually larger and slower than a single latch. 
     FIG. 2  is a block diagram of an embodiment of an improved triple redundant latch. In this embodiment, an identical logical value,  210 , is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , by controlling signal  204 . After an identical logical value,  210 , is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , by controlling signal  204 , the identical logical value is held in all three settable memory elements, SME 1 , SME 2 , and SME 3 . The voting structure, VS, after an identical logical value,  210 , is set into settable memory element 1 , SME 1 , settable memory element 2 , SME 2 , and settable memory element 3 , SME 3 , determines the logical value,  218 , stored in settable memory element three, SME 3 , based on the logical values presented to input,  214 , input,  216 , and control signal,  204 . 
   If the logical value,  218 , stored in settable memory element three, SME 3 , is disturbed by a soft error event, the voting structure, VS, will restore the original logical value stored in settable memory element three, SME 3 . If the logical value stored in settable memory element one, SME 1 , is disturbed by a soft error event, the voting structure, VS, will tri-state its output,  218 , leaving the original logical value stored in settable memory element three, SME 3 . If the logical value stored in settable memory element two, SME 2 , is disturbed by a soft error event, the voting structure, VS, will tri-state its output,  218 , leaving the original logical value stored in settable memory element three, SME 3 . If any two settable memory elements are disturbed by a soft error event, the logical value original stored in the triple redundant latch may fail. 
   The delay time through the triple redundant latch shown in  FIG. 2  is determined by a small amount of capacitance added by the voting structure, VS, and the propagation delay of the settable memory element 3 , SME 3 . This embodiment of the invention significantly improves the delay time of a triple redundant latch. The delay time through the prior art shown in  FIG. 1 , for example, includes the propagation delay through the slowest latch among latches LATCH 1 , LATCH 2 , and LATCH 3 , the propagation delay through an inverter, INV 2 , the propagation delay through an AND gate, AND 2 , and the propagation delay through an OR gate, OR 1 . 
     FIG. 3  is a block diagram of a triple redundant latch with improved delay and size. The input of the triple redundant latch shown in this example is connected to the inputs,  302 , of transfer gates, TG 1 , TG 2 , and TG 3 . In addition, a tristatable input inverter, a cross-coupled NAND gate, and a cross-coupled NOR gate may used in place of a transfer gate. If the control signals,  304  and  306 , are on, the signal at the input,  302 , of transfer gates, TG 1 , TG 2 , and TG 3 , is transferred to the output,  308 , of transfer gate, TG 1 , the output,  310 , of transfer gate, TG 2 , and the output,  312  of transfer gate, TG 3 . The logical value presented on the output,  308 , of transfer gate TG 1 , is also an input to latch 1 , L 1 . The logical value presented on the output,  312 , of transfer gate TG 3 , is also an input to latch 2 , L 2 . The logical value presented on the output,  310 , of transfer gate TG 2 , is also connected to the output,  310 , of the majority voter, MAJVT, and the input/output,  310 , of latch 3 , L 3 . 
   The output,  314 , of latch 1 , L 1 , is connected to an input,  314 , of the majority voter, MAJVT. The output,  316 , of latch 2 , L 2 , is connected to an input,  316 , of the majority voter, MAJVT. Control signals,  304 , and  306 , are also connected to inputs of the majority voter, MAJVT. 
   As an example of how redundancy applies for this embodiment, assume that a logical high value is stored. Storage nodes  308 ,  310 , and  312  each have a logical high value stored in this example. The output,  314 , of latch 1 , L 1 , provides a logical low value to an input of the majority voter, MAJVT. The output,  316 , of latch 1 , L 2 , provides a logical low value to an input of the majority voter, MAJVT. The control signals,  304  and  306 , provide a logical low value and a logical high value respectively to two inputs of the majority voter, MAJVT. As a result of the logical values presented to the majority voter, MAJVT, the output,  310 , of the majority voter, MAJVT, is driven high to match the logical high value stored on latch 3 , L 3 . 
   If, in this example, a soft error event changes the logical value stored on latch 1 , L 1 , from a logical high value to a logical low value, the logical value stored on latch 3 , L 3 , will retain its logical high value because the output,  310 , of the majority voter, MAJVT, is tri-stated. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error. 
   If in this example a soft error event changes the logical value stored on latch 1 , L 2 , from a logical high value to a logical low, the logical value stored on latch 3 , L 3 , will retain its logical high value because the output,  310 , of the majority voter, MAJVT, is tri-stated. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error. 
   If in this example a soft error event changes the logical value stored on latch 1 , L 3 , from a logical high value to a logical low, the majority voter, MAJVT, will drive input/out,  310 , of latch 3 , L 3 , back to a logical high value. As a result, the triple redundant latch retains the original logical value stored on it despite a single soft error. 
   If, however, in this example, a soft error event changes the values stored on nodes  308  and  312 , the triple redundant latch will change from its original value. If a soft error event changes the logical values stored on nodes  308  and  312 , from logical high values to a logical low values, the inputs,  314  and  316 , to the majority voter, MAJVT, change from logical low values to logical high values. As a result of having logical high values on the inputs,  314  and  316 , the majority vote is a logical low value. As a result, the logical value stored on node  310  is changed from the original logical high value to a logical low value. In this example, the original value stored in the triple redundant latch is changed from a logical high value to a logical low value. 
   In addition to improving the soft error rate of a latch, the triple redundant latch shown in  FIG. 3 , also reduces the physical size of a triple redundant latch because it uses fewer transistors. The triple redundant latch shown in  FIG. 3  also reduces the delay time through a triple redundant latch because the number of logic delays is reduced. 
     FIG. 4  is a schematic of an improved triple redundant latch.  FIG. 4  contains the same basic blocks that  FIG. 3  contains; transfer gate  1 , TG 1 , transfer gate  2 , TG 2 , transfer gate  3 , TG 3 , latch 1 , L 1 , latch 2 , L 2 , latch 3 , L 3 , and majority voter, MAJVT. 
   An embodiment of a transfer gate  1 , TG 1 , for the triple redundant latch contains a PFET, MP 2  and an NFET MN 2 . In this embodiment, the drains of PFET, MP 2 , and NFET, MN 2 , are connected to the input,  402 , of transfer gate  1 , TG 1 . The sources of PFET, MP 2 , and NFET, MN 2 , are connected to the output,  408 , of transfer gate  1 , TG 1 . The gate of PFET, MP 2 , is connected to the control input,  406 , of transfer gate  1 , TG 1 . The gate of NFET, MN 2 , is connected to the control input,  404 , of transfer gate  1 , TG 1 . 
   An embodiment of a transfer gate  2 , TG 2 , for the triple redundant latch contains a PFET, MP 3  and an NFET MN 3 . In this embodiment, the drains of PFET, MP 3 , and NFET, MN 3 , are connected to the input,  402 , of transfer gate  2 , TG 2 . The sources of PFET, MP 3 , and NFET, MN 3 , are connected to the output,  416 , of transfer gate  2 , TG 2 . The gate of PFET, MP 3 , is connected to the control input,  406 , of transfer gate  2 , TG 2 . The gate of NFET, MN 3 , is connected to the control input,  404 , of transfer gate  2 , TG 2 . 
   An embodiment of a transfer gate  3 , TG 3 , for the triple redundant latch contains a PFET, MP 4  and an NFET MN 4 . In this embodiment, the drains of PFET, MP 4 , and NFET, MN 4 , are connected to the input,  402 , of transfer gate  3 , TG 3 . The sources of PFET, MP 4 , and NFET, MN 4 , are connected to the output,  412 , of transfer gate  3 , TG 3 . The gate of PFET, MP 4 , is connected to the control input,  406 , of transfer gate  3 , TG 3 . The gate of NFET, MN 4 , is connected to the control input,  404 , of transfer gate  3 , TG 3 . 
   An embodiment of latch 1 , L 1 , for the triple redundant latch contains PFET, MP 5 , NFET, MN 5 , PFET, MP 6 , and NFET, MN 6 . In this embodiment, the gate of PFET, MP 5 , and the gate of NFET, MN 5 , is connected to the drain of PFET, MP 6  and to the drain of NFET, MN 6 , the input,  408 , of latch 1 , L 1 . The drain of PFET, MP 5 , and the drain of NFET, MN 5 , is connected to the gate of PFET, MP 6  and to the gate of NFET, MN 6 , the output,  410 , of latch 1 , L 1 . The sources of PFET, MP 5  and PFET, MP 6  are connected to VDD. The sources of NFET, MN 5 , and NFET, MN 6  are connected to GND. 
   An embodiment of latch 2 , L 2 , for the triple redundant latch contains PFET, MP 7 , NFET, MN 7 , PFET, MP 8 , and NFET, MN 8 . In this embodiment, the gate of PFET, MP 7 , and the gate of NFET, MN 7 , is connected to the drain of PFET, MP 8  and to the drain of NFET, MN 8 , the input,  412 , of latch 2 , L 2 . The drain of PFET, MP 7 , and the drain of NFET, MN 7 , is connected to the gate of PFET, MP 8  and to the gate of NFET, MN 8 , the output,  414 , of latch 2 , L 2 . The sources of PFET, MP 7  and PFET, MP 8  are connected to VDD. The sources of NFET, MN 7 , and NFET, MN 8  are connected to GND. 
   An embodiment of latch 3 , L 3 , for the triple redundant latch contains PFET, MP 12 , NFET, MN 12 , PFET, MP 13 , and NFET, MN 13 . In this embodiment, the gate of PFET, MP 12 , and the gate of NFET, MN 12 , is connected to the drain of PFET, MP 13  and to the drain of NFET, MN 13 , the input/output,  416 , of latch 3 , L 3 . The drain of PFET, MP 12 , and the drain of NFET, MN 12 , is connected to the gate of PFET, MP 13  and to the gate of NFET, MN 13 , node  426 , of latch 3 , L 3 . The sources of PFET, MP 12  and PFET, MP 13  are connected to VDD. The sources of NFET, MN 12 , and NFET, MN 13  are connected to GND. 
   An embodiment of a majority voter, MAJVT, for the triple redundant latch contains PFET, MP 9 , PFET, MP 10 , PFET, MP 11 , NFET, MN 9 , NFET, MN 10 , and NFET, MN 11 . In this embodiment, the gates of PFET, MP 10 , and NFET, MN 10 , are connected to the first input,  410 , of the majority voter, MAJVT. The gates of PFET, MN 9 , and NFET, MNI 1 , are connected to the second input,  414 , of the majority voter, MAJVT. The gate of PFET, MP 11 , is connected to the third input,  404 , of the majority voter, MAJVT. The gate of NFET, MN 9 , is connected to the fourth input,  406 , of the majority voter, MAJVT. The source of PFET, MP 9 , is connected to VDD. The source of NFET, MN 11 , is connected to GND. The drain,  418 , of PFET, MP 9 , is connected to the source of PFET, MP 10 ,  418 . The drain,  420 , of PFET, MP 10 , is connected to the source of PFET, MP 11 ,  420 . The drain of PFET, MP 1  and the drain of NFET, MN 9  are connected to the output,  416 , of the majority voter, MAJVT. The source,  422 , of NFET, MP 9 , is connected to the drain of NFET, MN 10 ,  422 . The source,  424 , of NFET, MN 10 , is connected to the drain of NFET, MN 11 ,  424 . 
     FIG. 4  is a schematic of an improved triple redundant latch. An input signal drives the inputs,  402 , of transfer gate  1 , TG 1 , transfer gate  2 , TG 2 , and transfer gate  3 , TG 3 . If control signal,  404  is a logical high value and control signal,  406 , is a logical low value, the signal at the input,  402 , of transfer gate  1 , TG 1 , transfer gate  2 , TG 2 , and transfer gate  3 , TG 3  is transferred to the output,  408 , of transfer gate  1 , TG 1 , the output,  416 , of transfer gate  2 , TG 2 , and the output,  412 , of transfer gate  3 , TG 3 . 
   The signal transferred to nodes  408 ,  416 , and  412  is also presented to the input,  408 , of latch 1 , L 1 , the input,  412 , of latch 2 , L 2 , the input/output,  416 , of latch 3 , L 3 , and the output,  416  of the majority voter, MAJVT. Latches L 1 , L 2 , and L 3  store the same signal. The outputs,  410  and  414 , of latches, L 1  and L 2  respectively, output the opposite sense of the signal stored. The outputs,  410  and  414 , of latches, L 1  and L 2  respectively, along with the first,  404 , and second,  406 , control signals are inputs to the majority voter, MAJVT. The inputs,  404 ,  406 ,  410 , and  414 , into the majority voter, MAJVT, cause the majority voter, MAJVT, to reinforce the signal presented at the output,  416 , of transfer gate  2 , TG 2 . 
   After control input,  404 , is driven to a logical low value, and control input,  406 , is driven to a logical high value, latch 1 , L 1 , latch 2 , L 2 , and latch 3 , L 3  store the original logical value presented on nodes  408 ,  412 , and  416 , respectively. If none of the nodes,  408 ,  412 , and  416 , is disturbed, then a signal of the same sense is presented on the output,  416 , of the majority voter, MAJVT. 
   For example, if a logical high value is stored on nodes  408 ,  412 , and  416 , then a logical high value is presented on the output,  416 , of the majority voter, MAJVT. A logical low value on the output,  410 , of latch 1 , L 1 , is applied to the first input of the majority voter, MAJVT. A logical low value on the output,  414 , of latch 2 , L 2 , is applied to the second input of the majority voter, MAJVT. Since in this example, the transfer gates are turned off, control signal  404 , is low and control signal  406 , is high. Because control signal  404  is low, a logical low value is applied to the third input of the majority voter, MAJVT. Because control signal  406  is high, a logical high value is applied to the fourth input of the majority voter, MAJVT. With these logical values applied to the majority voter, MAJVT, the output,  416 , of majority voter, MAJVT, remains a high logical value. 
   If in this example where a logical high value is stored on nodes,  408 ,  412 , and  416 , node  408  is changed to a logical low value by a soft error event, a logical high value is then presented to input,  410 , of the majority voter, MAJVT. Inputs,  414 , and  404 , remain a logical low value while input  406  remains a logical high value. Since input,  410 , has changed from a low logical value to a high logical value, node  416 , is no longer actively driven high by the majority voter, MAJVT. However, since latch 3 , L 3  has not been disturbed, latch 3 , L 3 , actively holds node  416  at a logical high value. As a consequence, despite latch 1 , L 1 , being disturbed by a soft error event to a logical low value, the value on the output,  428 , of the triple redundant latch remains a logical high value. 
   If, however, a soft error event changes the value stored on node,  408  and node,  412 , the triple redundant latch will change from its original value. For example, if a logical high value is stored on nodes  408 ,  412 , and  416 , a logical high value is presented on the output,  416 , of the majority voter, MAJVT. If a soft error event changes the logical value stored on nodes,  408  and  412 , from a logical high value to a logical low value, inputs,  410  and  414 , into the majority voter, MAJVT, change from logical low values to logical high values. Since inputs,  410  and  414 , of the majority voter, MAJVT, are a logical high value, and control signal,  406 , remains a logical high value, the majority voter output,  416 , is pulled to a logical low value. The high logical value stored on latch 3 , L 3 , is then flipped to a logical low value. The output,  428 , of the triple redundant latch, is then changed from a logical low value to a logical high value. 
   If a single soft error event temporally changes the logical value stored in latch 3 , L 3 , the majority voter, MAJVT, will reset the logical value on latch 3 , L 3 , to its original value. The logical state on latch 3 , L 3 , is reset to its original value because none of the inputs,  404 ,  406 ,  310 , and  414 , on the majority voter, MAJVT, has changed as a consequence of latch 3 , L 3 , changing its logical value. Therefore, the output,  416 , of the majority voter, MAJVT, drives latch 3 , L 3 , back to its original value. 
   The foregoing description of the present invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed, and other modifications and variations may be possible in light of the above teachings. The embodiment was chosen and described in order to best explain the principles of the invention and its practical application to thereby enable others skilled in the art to best utilize the invention in various embodiments and various modifications as are suited to the particular use contemplated. It is intended that the appended claims be construed to include other alternative embodiments of the invention except insofar as limited by the prior art.