Patent Publication Number: US-11049458-B1

Title: Pixel driving circuit, driving method and organic light emitting display panel

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority to Chinese Patent Application No. 202010275697.9, filed on Apr. 9, 2020, the content of which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to the field of display technologies, and particularly, to a pixel driving circuit, a driving method and an organic light emitting display panel. 
     BACKGROUND 
     Organic light emitting display is currently a mainstream technology for displays in e.g., mobile phones, televisions, computers, and the like. Compared with the conventional liquid crystal display, the organic light emitting display has advantages such as low power consumption, low cost, auto-luminescence, wide viewing angle and high response speed. As a result, the organic light emitting display has gradually become the mainstream display technology. 
     Since the organic light emitting display is current-driven, a stable current is required for controlling its light emission. An amplitude and stability of a driving current of the organic light emitting display mainly depend on an amplitude and stability of a voltage transmitted to an organic light emitting device from a driving transistor in an organic light emitting display pixel circuit. In the related art, due to a current leakage problem with other transistors connected to a gate of the driving transistor, a potential at the gate of the driving transistor may be unstable, and thus a voltage it transmits to the organic light emitting device may be unstable, resulting in a flicker problem with the organic light emitting display. 
     SUMMARY 
     In view of the above, the present disclosure provides a pixel driving circuit, a driving method and an organic light emitting display panel, to solve the above problem. 
     In a first aspect, a pixel driving circuit is provided according to an embodiment of the present disclosure. The pixel driving circuit includes: a light emitting display module, including an Organic Light Emitting Diode (OLED); a light emission driving module, including a first control terminal, a first input terminal and a first output terminal, the first output terminal being electrically connected to the light emitting display module; a connection control module, including a second input terminal and a second output terminal, the second output terminal being connected to the first control terminal of the light emission driving module; and a first initializing module, including a third input terminal and a third output terminal, the third input terminal being connected to a first reference voltage signal line and the third output terminal being connected to the second input terminal. 
     In a second aspect, a driving method for a pixel driving circuit is provided according to an embodiment of the present disclosure. The pixel driving circuit includes: a light emitting display module, including an Organic Light Emitting Diode (OLED); a light emission driving module, including a first control terminal, a first input terminal and a first output terminal, the first output terminal being electrically connected to the light emitting display module; a connection control module, including a second input terminal and a second output terminal, the second output terminal being connected to the first control terminal of the light emission driving module; and a first initializing module, including a third input terminal and a third output terminal, the third input terminal being connected to a first reference voltage signal line and the third output terminal being connected to the second input terminal. The driving method includes: in an initializing phase, connecting the third input terminal and the third output terminal of the first initializing module with each other, connecting the second input terminal and the second output terminal of the connection control module with each other, and transmitting a reference voltage on the first reference voltage signal line, the reference voltage being transmitted to the first control terminal through the first initializing module and the connection control module; and in a light emitting phase, disconnecting the third input terminal and the third output terminal of the first initializing module from each other, disconnecting the second input terminal and the second output terminal of the connection control module from each other, and the light emission driving module transmitting a light emission driving voltage to the light emitting display module. 
     In a third aspect, an organic light emitting display panel is provided according to an embodiment of the present disclosure. The organic light emitting display panel includes the pixel driving circuit according to the first aspect. 
     A connection control module is provided between the third output terminal of the first initializing module and the first control terminal of the light emission driving module. The input terminal and the output terminal of the first initializing module can be disconnected from each other and the input terminal and the output terminal of the connection control module can be disconnected from each other in the light emitting phase of the pixel driving circuit, so as to avoid a current leakage due to the first initializing module not being completely turned off in the light emitting phase, which would otherwise affect the voltage at the first control terminal of the light emission driving module. In this way, the stability of light emission from the OLED in the light emission driving circuit can be guaranteed. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
       In order to illustrate technical solutions of embodiments of the present disclosure, the accompanying drawings used in the embodiments or the prior art are introduced hereinafter. These drawings illustrate some embodiments of the present disclosure. On the basis of these drawings, those skilled in the art can also obtain other drawings. 
         FIG. 1  is a schematic diagram showing a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 2  is a schematic diagram showing another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 3  is a schematic diagram showing yet another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 4  is a schematic diagram showing still another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 5  shows a driving timing sequence of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 6  shows a driving timing sequence of another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 7  shows a driving timing sequence of yet another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 8  is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 9  is an equivalent circuit diagram of another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 10  is an equivalent circuit diagram of yet another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 11  is an equivalent circuit diagram of still another pixel driving circuit according to an embodiment of the present disclosure; 
         FIG. 12  is an operation timing diagram of the pixel driving circuit shown in  FIG. 8 ; 
         FIG. 13  is an operation timing diagram of the pixel driving circuit shown in  FIG. 9 ; 
         FIG. 14  is an operation timing diagram of the pixel driving circuit shown in  FIG. 10 ; 
         FIG. 15  is an operation timing diagram of the pixel driving circuit shown in  FIG. 11 ; 
         FIG. 16  is a timing sequence of a driving method for a pixel driving circuit according to an embodiment of the present disclosure; and 
         FIG. 17  is a schematic diagram showing an organic light emitting display panel according to an embodiment of the present disclosure. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     In order to better understand technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail with reference to the drawings. 
     It should be clear that the described embodiments are merely part of the embodiments of the present disclosure rather than all the embodiments. All other embodiments obtained by those skilled in the art shall fall into the protection scope of the present disclosure. 
     The terms used in the embodiments of the present disclosure are merely for the purpose of describing specific embodiments, rather than limiting the present disclosure. The singular form “a”, “an”, “the” and “said” used in the embodiments and claims shall be interpreted as also including the plural form, unless indicated otherwise in the context. 
     It should be understood that, the term “and/or” is used in the present disclosure merely to describe relations between associated objects, and thus includes three types of relations. That is, A and/or B can represent: (a) A exists alone; (b) A and B exist at the same time; or (c) B exists alone. In addition, the character “/” generally indicates “or”. 
     It is to be noted that, while transistors may be described using terms such as “first”, “second” and “third” in the embodiments of the present disclosure, they are not limited by these terms which are used for distinguishing the transistors from one another only. For example, a first transistor may be referred to as a second transistor, without departing from the scope of the embodiments of the present disclosure. Likewise, a second transistor may be referred to as a first transistor. 
     The inventors of the present disclosure have studied the problems with the related art to provide a solution. 
       FIG. 1  is a schematic diagram showing a pixel driving circuit according to an embodiment of the present disclosure. As shown in  FIG. 1 , the pixel driving circuit according to the embodiment of the present disclosure includes a light emitting display module  00 , a light emission driving module  01 , a connection control module  02 , and a first initializing module  03 . 
     The light emitting display module  00  includes an Organic Light Emitting Diode (OLED) for light emitting and displaying. 
     The light emission driving module  01  includes a first control terminal CR 1 , a first input terminal IN 1  and a first output terminal OUT 1 . The first output terminal OUT 1  is electrically connected to the light emitting display module  00 . Specifically, the light emission driving module  01  may provide an anode voltage for an anode of the OLED in the light emitting display module  00 , while a cathode of the OLED receives a cathode voltage transmitted on a cathode signal line PVEE. The OLED emits light in response to the anode voltage and the cathode voltage. 
     The connection control module  02  includes a second input terminal IN 2  and a second output terminal OUT 2 . The second output terminal OUT 2  is connected to the first control terminal CR 1  of the light emission driving module  01 . In addition, the connection control module  02  may further include a second control terminal CR 2  connected to a first scan line S 2  and used to control the connected/disconnected state between the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02 . When the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  are connected with each other, the first control terminal CR 1  of the light emission driving module  01  can receive a signal through the connection control module  02 . When the second input terminal IN 2  and the second output terminal OUT 2  of the connection control terminal  02  are disconnected from each other, the connection control module  02  can cut off the signal transmission between the first control terminal CR 1  of the light emission driving module  01  and other signal lines and/or other transistors. 
     The first initializing module  03  includes a third input terminal IN 3  and a third output terminal OUT 3 . The third input terminal IN 3  is connected to a first reference voltage signal line Ref 1 , and the third output terminal OUT 3  is connected to the second input terminal IN 2 . In addition, the first initializing module  03  further includes a third control terminal CR 3 , which is connected to a second scan line S 3  and used to control the connected/disconnected state between the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03 . When the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03  are connected with each other, a reference voltage transmitted on the first reference voltage signal line Ref 1  can be transmitted to the turned-on connection control module  02  through the turned-on first initializing module  03 , and then transmitted to the first control terminal CR 1  of the light emission driving module  01 , so as to complete initialization of the first control terminal CR 1  of the light emission driving module  01 . 
     The connection control module  02  is provided between the third output terminal OUT 3  of the first initializing module  03  and the first control terminal CR 1  of the light emission driving module  01 . In the light emitting phase of the pixel driving circuit, the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03  can be disconnected from each other and the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  can be disconnected from each other, so as to avoid a current leakage due to the first initializing module  03  not being completely turned off in the light emitting phase, which would otherwise affect the voltage at the first control terminal CR 1  of the light emission driving module  01 . In this way, the stability of light emission from the OLED in the light emission driving circuit can be guaranteed. 
     In the following, the operation principles of the pixel driving circuit according to the embodiment of the present disclosure will be explained with reference to the timing sequence. 
       FIG. 2  is a schematic diagram showing another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 3  is a schematic diagram showing yet another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 4  is a schematic diagram showing still another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 5  shows a driving timing sequence of a pixel driving circuit according to an embodiment of the present disclosure.  FIG. 6  shows a driving timing sequence of another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 7  shows a driving timing sequence of yet another pixel driving circuit according to an embodiment of the present disclosure. Here,  FIG. 5  shows the driving timing sequence of the pixel driving circuit shown in  FIG. 2 ;  FIG. 6  shows the driving timing sequence of the pixel driving circuit shown in  FIG. 3 ; and  FIG. 7  shows the driving timing sequence of the pixel driving circuit shown in  FIG. 4 . 
     As shown in  FIGS. 5-7 , an operation period of the pixel driving circuit includes a plurality of cycles, each including an initializing phase t 1  and a light emitting phase t 4 . For illustration, this embodiment will be described with reference to an example where a low level is used as an “on” signal (enabling level) and a high level is used as an “off” signal (disabling level). In fact, alternatively, for each module, a high level can be used as an on signal and a low level can be used as an off signal. It is to be noted here that the on signal is a signal that controls the input terminal and the output terminal of each module to be connected with each other, and the off signal is a signal that controls the input terminal and the output terminal of each module to be disconnected from each other. 
     In the initializing phase t 1 , the first scan line S 2  receives an on signal, and the second control terminal CR 2  of the connection control module  02  receives the on signal and controls the second input terminal IN 2  and the second output terminal OUT 2  to be connected with each other. That is, a signal at the second input terminal IN 2  can be transmitted to the second output terminal OUT 2 . At the same time, the second scan line S 3  receives an on signal, and the third control terminal CR 3  of the first initializing module  03  receives the on signal and controls the third input terminal IN 3  and the third output terminal OUT 3  to be connected with each other. That is, a signal at the third input terminal IN 3  can be transmitted to the third output terminal OUT 3 . At the same time, a reference voltage is transmitted on the first reference voltage signal line Ref 1  connected to the third input terminal IN 3  of the first initializing module  03 , and the reference voltage is transmitted to the first control terminal CR 1  of the light emission driving module  01  through the turned-on first initializing module  03  and connection control module  02 , so as to initialize the first control terminal CR 1  of the light emission driving module  01 . 
     In the light emitting phase t 4 , both the first scan line S 2  and the second scan line S 3  receive an off signal. The second control terminal CR 2  of the connection control module  02  receives the off signal and controls the second input terminal IN 2  and the second output terminal OUT 2  to be disconnected from each other, and the third control terminal CR 3  of the first initializing module  03  receives the off signal and controls the third input terminal IN 3  and the third output terminal OUT 3  to be disconnected from each other. 
     Since in the light emitting phase the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  are disconnected from each other and the third output terminal OUT 3  of the first initializing module  03  and the first control terminal CR 1  of the light emission driving module  01  are also disconnected from each other, even if the first initializing module  03  is not completely turned off, the connection control module  02  disconnects the first initializing module  03  from the first control terminal CR 1  of the light emission driving module  01 , thereby guaranteeing the stability of the voltage at the first control terminal CR 1  of the light emission driving module  01 . 
     In an embodiment of the present disclosure, referring to  FIGS. 2-4  again, the pixel driving circuit according to an embodiment of the present disclosure may further include a second initializing module  04 , which includes a fourth input terminal IN 4  and a fourth output terminal OUT 4 . The fourth input terminal IN 4  is connected to a second reference voltage signal line Ref 2 , and the fourth output terminal OUT 4  is connected to an anode of the OLED. In addition, the second initializing module  04  further includes a fourth control terminal CR 4 , which is connected to a third scan line S 4  and used to control connection/disconnection between the fourth input terminal IN 4  and the fourth output terminal OUT 4  of the second initializing module  04 . When the fourth input terminal IN 4  and the fourth output terminal OUT 4  of the second initializing module  04  are connected with each other, a reference voltage transmitted on the second reference voltage signal line Ref 2  can be transmitted to the anode of the OLED through the turned-on second initializing module  04 , so as to complete the initialization of the anode of the OLED. 
     Referring to  FIGS. 5-7  again, in the initializing phase t 1 , the third scan line S 4  receives an on signal, and the fourth control terminal CR 4  of the second initializing module  04  receives an on signal and controls the fourth input terminal IN 4  and the fourth output terminal OUT 4  to be connected with each other. That is, a signal at the fourth input terminal IN 4  can be transmitted to the fourth output terminal OUT 4 . At the same time, a reference voltage is transmitted on the second reference voltage signal line Ref 2  connected to the fourth input terminal IN 4  of the second initializing module  04 , and the reference voltage is transmitted to the anode of the OLED through the turned-on second initializing module  04 , so as to complete the initialization of the anode of the OLED. 
     In the light emitting phase t 4 , the third scan line S 4  receives an off signal, and the fourth control terminal CR 4  of the second initializing module  04  receives an off signal and controls the fourth input terminal IN 4  and the fourth output terminal OUT 4  to be disconnected from each other. 
     It should be noted that, as shown in  FIGS. 5 and 7 , the initialization of the first control terminal CR 1  of the light emission driving module  01  by the first initializing module  03  and the initialization of the anode of the OLED by the second initializing module  03  can be performed simultaneously, i.e., they can be completed in one initializing phase t 1 . However, according to a different operation timing requirement, the initialization of the first control terminal CR 1  of the light emission driving module  01  by the first initializing module  03  and the initialization of the anode of the OLED by the second initializing module  03  can be performed separately. For example, the first control terminal CR 1  can be initialized first and then the anode of the OLED can be initialized. 
     Referring to  FIG. 2  to  FIG. 3 , the pixel driving circuit according to the embodiment of the present disclosure may further include a threshold voltage capturing module  05  and a first capacitor C 1 . The threshold voltage capturing module  05  includes a fifth input terminal IN 5  and a fifth output terminal OUT 5 . The fifth input terminal IN 5  is connected to the first output terminal OUT 1  of the light emission driving module  01 , and the fifth output terminal OUT 5  is connected to the second input terminal IN 2  of the connection control module  02 . In addition, the threshold voltage capturing module  05  further includes a fifth control terminal CR 5 , which is connected to a fourth scan line S 5  and used to control connection/disconnection between the fifth input terminal IN 5  and the fifth output terminal OUT 5  of the threshold voltage capturing module  05 . A first electrode plate of the first capacitor C 1  is electrically connected to the first control terminal CR 1  of the light emission driving module  01 . 
     The purpose of providing the threshold voltage capturing module  05  is to store the voltage at the first input terminal IN 1  of the light emission driving module  01  to the first control terminal CR 1  of the light emission driving module  01  in a threshold voltage capturing phase before the light emitting phase. In the light emitting phase, while the light emission driving module  01  is outputting a light emission driving voltage, the impact of the threshold voltage of the light emission driving module  01  on the light emission driving voltage is eliminated, thereby achieving a threshold compensation. Since the light emission driving voltage of the light emission driving module  01  is determined by a power supply voltage and a data voltage, one of the power supply voltage and the data voltage can be stored to the first control terminal CR 1  of the light emission driving module  01  in the threshold voltage capturing phase. That is, in the threshold voltage capturing phase, the threshold voltage capturing module  05  may store the power supply voltage or the data voltage at the first input terminal IN 1  to the first control terminal CR 1 . The function of the first capacitor C 1  includes storing the voltage at the first control terminal CR 1  of the light emission driving module  01  connected thereto. 
     In the following, a circuit structure corresponding to the threshold voltage capturing module  05  storing the power supply voltage and the data voltage to the first control terminal CR 1  of the light emission driving module  01  in the threshold voltage capturing phase will be described. 
     Referring to  FIG. 2 , when the threshold voltage capturing module  05  stores the power supply voltage to the first control terminal CR 1  of the light emission driving module  01  in the threshold voltage capturing phase, the pixel driving circuit according to the embodiment of the present disclosure may further include a data signal writing module  06 . The data signal writing module  06  includes a sixth input terminal IN 6  and a sixth output terminal OUT 6 . The sixth input terminal IN 6  is connected to a data voltage line Data, and the sixth output terminal OUT 6  is electrically connected to a second electrode plate of the first capacitor C 1 . The first input terminal IN 1  of the light emission driving module  01  is connected to a power supply voltage signal line PVDD. In addition, the data signal writing module  06  further includes a sixth control terminal CR 6  connected to a fifth scan line S 6  and used to control connection/disconnection between the sixth input terminal IN 6  and the sixth output terminal OUT 6  of the data signal writing module  06 . 
     Referring to  FIG. 2  and  FIG. 5  again, in the threshold voltage capturing phase t 2 , the first scan line S 2  and the fourth scan line S 5  receive an on signal, and the second control terminal CR 2  of the connection control module  02  receives the on signal and controls the second input terminal IN 2  and the second output terminal OUT 2  to be connected with each other. That is, the signal at the second input terminal IN 2  can be transmitted to the second output terminal OUT 2 . The fifth control terminal CR 5  of the threshold voltage capturing module  05  receives the on signal and controls the fifth input terminal IN 5  and the fifth output terminal OUT 5  to be connected with each other. That is, the signal at the fifth input terminal IN 5  can be transmitted to the fifth output terminal OUT 5 . At the same time, in the threshold voltage capturing phase t 2 , the first input terminal IN 1  and the first output terminal OUT 1  of the light emission driving module  01  are connected with each other and a power supply voltage is transmitted on the power supply voltage signal line PVDD. The power supply voltage is transmitted through the light emission driving module  01 , the threshold voltage capturing module  05  and the connection control module  02  and stored to the first control terminal CR 1  of the light emission driving module  01 . 
     Referring to  FIG. 2  and  FIG. 5  again, in a data signal writing phase t 3 , the fifth scan line S 6  receives an on signal, and the sixth control terminal CR 6  of the data signal writing module  06  receives the on signal and controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  to be connected with each other. That is, the signal at the sixth input terminal IN 6  can be transmitted to the sixth output terminal OUT 6 . A data voltage is transmitted on the data voltage line Data, and the data voltage is transmitted through the data signal writing module  06  and stored in the first capacitor, equivalently stored to the first control terminal CR 1  of the light emission driving module  01 . 
     Referring to  FIG. 2  and  FIG. 5  again, in the light emitting phase t 4 , the fourth scanning line S 5  and the fifth scanning line S 6  receive an off signal, the fifth control terminal CR 5  of the threshold voltage capturing module  05  receives the off signal and controls the fifth input terminal IN 5  and the fifth output terminal OUT 5  to be disconnected from each other, and the sixth control terminal CR 6  of the data signal writing module  06  receives the off signal and controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  to be disconnected from each other. 
     The connection control module  02  is provided between the third output terminal OUT 3  of the first initializing module  03  and the first control terminal CR 1  of the light emission driving module  01 , and between the first output terminal OUT 1  and the first control terminal CR 1  of the light emission driving module  01 . In the light emitting phase of the pixel driving circuit, the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  are disconnected from each other, and the third output terminal OUT 3  of the first initializing module  03  and the first output terminal OUT 1  of the light emission driving module  01  are disconnected simultaneously and effectively from the first control terminal CR 1  of the light emission driving module  01 , so as to avoid a current leakage and guarantee the stability of the voltage at the first control terminal CR 1  of the light emission driving module  01 , thereby guaranteeing the stability of light emission from the OLED in the light emission driving circuit. 
     Referring to  FIG. 3  and  FIG. 6 , when the threshold voltage capturing module  05  stores the data voltage to the first control terminal CR 1  of the light emission driving module  01  in the threshold voltage capturing phase t 2 , the pixel driving circuit according to the embodiment of the present disclosure may further include a data signal writing module  06  and a power supply voltage writing module  07 . 
     Referring to  FIG. 3  again, the data signal writing module  06  includes a sixth input terminal IN 6  and a sixth output terminal OUT 6 . The sixth input terminal IN 6  is connected to a data voltage line Data, and the sixth output terminal OUT 6  is connected to the first input terminal IN 1  of the light emission driving module  01 . In addition, the data signal writing module  06  further includes a sixth control terminal CR 6  connected to a fifth scan line S 6  and used to control connection/disconnection between the sixth input terminal IN 6  and the sixth output terminal OUT 6  of the data signal writing module  06 . 
     Referring to  FIG. 3  again, the power supply voltage writing module  07  includes a seventh input terminal IN 7  and a seventh output terminal OUT 7 . The seventh input terminal IN 7  is connected to a power supply voltage signal line PVDD, and the seventh output terminal OUT 7  is connected to the first input terminal IN 1  of the light emission driving module  01 . In addition, the power supply voltage writing module  07  further includes a seventh control terminal CR 7  connected to a sixth scan line S 7  and used to control connection/disconnection between the seventh input terminal IN 7  and the seventh output terminal OUT 7  of the power supply voltage writing module  07 . 
     Referring to  FIG. 3  and  FIG. 6  again, in the threshold voltage capturing phase t 2 , the first scan line S 2  and the fifth scan line S 6  receive an on signal, the second control terminal CR 2  of the connection control module  02  receives the on signal and controls the second input terminal IN 2  and the second output terminal OUT 2  to be connected with each other. That is, the signal at the second input terminal IN 2  can be transmitted to the second output terminal OUT 2 . The sixth control terminal CR 6  of the data signal writing module  06  receives the on signal and controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  to be connected with each other. That is, the signal at the sixth input terminal IN 6  can be transmitted to the sixth output terminal OUT 6 . At the same time, in the threshold voltage capturing phase t 2 , the first input terminal IN 1  and the first output terminal OUT 1  of the light emission driving module  01  are connected with each other and a data voltage is transmitted on the data voltage line Data. The data voltage is transmitted through the data signal writing module  06 , the light emission driving module  01 , the threshold voltage capturing module  05  and the connection control module  02  and stored to the first control terminal CR 1  of the light emission driving module  01 . 
     It should be noted that the threshold voltage capturing phase t 2  in this embodiment completes writing the data voltage to the first control terminal CR 1  of the light emission driving module  01 . That is, this phase equivalently completes both the writing of the data signal and the capturing of the threshold voltage. Thus, the pixel circuit corresponding to the embodiment of the present disclosure does not need to perform a separate data signal writing phase in operation, which shortens the scanning period of the pixel driving circuit for each row. 
     Referring to  FIG. 3  and  FIG. 6  again, in the light emitting phase t 4 , the fourth scan line S 5  and the fifth scan line S 6  receive an off signal, the fifth control terminal CR 5  of the threshold voltage capturing module  05  receives the off signal and controls the fifth input terminal IN 5  and the fifth output terminal OUT 5  to be disconnected from each other, and the sixth control terminal CR 6  of the data signal writing module  06  receives the off signal and controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  to be disconnected from each other. In addition, the sixth scan line S 7  receives an on signal and a power supply voltage is transmitted on the power supply voltage signal line PVDD. The seventh control terminal CR 7  of the power supply voltage writing module  07  receives the on signal and controls the seventh input terminal IN 7  and the seventh output terminal OUT 7  to be connected with each other. That is, the signal at the seventh input terminal IN 7  can be transmitted to the seventh output terminal OUT 7 . The power supply voltage can be transmitted through the power supply voltage writing module  07  to form a light emission driving voltage to be transmitted to the light emitting display module  01 . 
     The connection control module  02  is provided between the third output terminal OUT 3  of the first initializing module  03  and the first control terminal CR 1  of the light emission driving module  01 , and between the first output terminal OUT 1  and the first control terminal CR 1  of the light emission driving module  01 . In the light emitting phase of the pixel driving circuit, the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  are disconnected from each other. The third output terminal OUT 3  of the first initializing module  03  and the first output terminal OUT 1  of the light emission driving module  01  can be disconnected simultaneously and effectively from the first control terminal CR 1  of the light emission driving module  01 , so as to avoid a current leakage and guarantee stability of voltage at the first control terminal CR 1  of the light emission driving module  01 , thereby guaranteeing stability of light emission from the OLED in the light emission driving circuit. 
     The pixel driving circuit shown in  FIG. 4  differs from the pixel driving circuit shown in  FIG. 3  only in that the threshold voltage capturing module is not included, so that the second input terminal IN 2  of the connection control module  02  is connected to the first output terminal OUT 1  of the light emission driving module  01  directly. 
     Referring to  FIG. 4  and  FIG. 7 , in the threshold voltage capturing phase t 2 , the first scan line S 2  and the fifth scan line S 6  receive an on signal, the second control terminal CR 2  of the connection control module  02  receives the on signal and controls the second input terminal IN 2  and the second output terminal OUT 2  to be connected with each other. That is, the signal at the second input terminal IN 2  can be transmitted to the second output terminal OUT 2 . The sixth control terminal CR 6  of the data signal writing module  06  receives the on signal and controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  to be connected with each other. That is, the signal at the sixth input terminal IN 6  can be transmitted to the sixth output terminal OUT 6 . At the same time, in the threshold voltage capturing phase t 2 , the first input terminal IN 1  and the first output terminal OUT 1  of the light emission driving module  01  are connected with each other and a data voltage is transmitted on the data voltage line Data. The data voltage is transmitted through the data signal writing module  06 , the light emission driving module  01  and the connection control module  02  and stored to the first control terminal CR 1  of the light emission driving module  01 . It can be seen that the connection control module  02  can function as the threshold voltage capturing module  02  in the threshold voltage capturing phase t 2 . The stability of the voltage at the first control terminal CR 1  of the light emission driving module  01  can be effectively maintained by setting the position of the connection control module  02 , while reducing the number of transistors and increasing the aperture area for transmissive display. 
       FIG. 8  is an equivalent circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure.  FIG. 9  is an equivalent circuit diagram of another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 10  is an equivalent circuit diagram of yet another pixel driving circuit according to an embodiment of the present disclosure.  FIG. 11  is an equivalent circuit diagram of still another pixel driving circuit according to an embodiment of the present disclosure. The specific circuit structure of the pixel driving circuit according to the present disclosure will be described below with reference to  FIGS. 8-11 . 
     As shown in  FIGS. 8-11 , the light emission driving module  01  includes a first transistor T 1  having a gate connected to the first control terminal CR 1 , a source connected to the first input terminal IN 1 , and a drain connected to the first output terminal OUT 1 . The connection control module  02  includes a second transistor T 2  having a gate connected to the second control terminal CR 2 , a source connected to the second input terminal IN 2 , and a drain connected to the second output terminal OUT 2 . The first initializing module  03  includes a third transistor T 3  having a gate connected to the third control terminal CR 3 , a source connected to the third input terminal IN 3 , and a drain connected to the third output terminal OUT 3 . The second initializing module  04  includes a fourth transistor T 4  having a gate connected to the fourth control terminal CR 4 , a source connected to the fourth input terminal IN 4 , and a drain connected to the fourth output terminal OUT 4 . The threshold voltage capturing module  05  includes a fifth transistor T 5  having a source connected to the fifth input terminal IN 5  and a drain connected to the fifth output terminal OUT 5 . The data signal writing module  06  includes a sixth transistor T 6  having a source connected to the sixth input terminal IN 6  and a drain connected to the sixth output terminal OUT 6 . The power supply voltage writing module  07  includes a seventh transistor T 7  having a source connected to the seventh input terminal IN 7  and a drain connected to the seventh output terminal OUT 7 . 
     In addition, as shown in  FIGS. 8-11 , in one embodiment of the present disclosure, the light emitting display module  00  may further include a light emission control transistor T 0  having a gate connected to a light emission control signal line EM, a source connected to the first output terminal OUT 1  of the light emission driving module  01 , and a drain connected to the anode of the OLED. 
     Referring to  FIG. 8 , in an embodiment of the present disclosure, the first input terminal IN 1  of the light emission driving module  01  is connected to the power supply voltage signal line PVDD, and the first output terminal OUT 1  is electrically connected to the light emitting display module  00 . The second control terminal CR 2  of the connection control module  02  is connected to the first scan line S 2 , and the second output terminal OUT 2  is connected to the first control terminal CR 1  of the light emission driving module  01 . The third control terminal CR 3  of the first initializing module  03  is connected to the second scan line S 3 , the third input terminal IN 3  is connected to the first reference voltage signal line Ref 1 , and the third output terminal OUT 3  is connected to the second input terminal IN 2  of the connection control module  02 . The fourth control terminal CR 4  of the second initializing module  04  is connected to the third scan line S 4 , the fourth input terminal IN 4  is connected to the second reference voltage signal line Ref 2 , and the fourth output terminal OUT 4  is connected to the anode of the OLED. The fifth control terminal CR 5  of the threshold voltage capturing module  05  is connected to the fourth scan line S 5 , the fifth input terminal IN 5  is connected to the first output terminal OUT 1  of the light emission driving module  01 , and the fifth output terminal OUT 5  is connected to the second input terminal IN 2  of the connection control module  02 . The sixth control terminal CR 6  of the data signal writing module  06  is connected to the fifth scan line S 6 , the sixth output terminal OUT 6  is electrically connected to the second electrode plate of the first capacitor C 1 , and the sixth input terminal IN 6  is connected to the data voltage line Data. The first electrode plate of the first capacitor C 1  is electrically connected to the first control terminal CR 1  of the light emission driving module  01 . 
     That is, as shown in  FIG. 8 , in this embodiment, the gate of the light emission control transistor T 0  is electrically connected to the light emission control signal line EM, and the drain of the light emission control transistor T 0  is electrically connected to the anode of the OLED. The gate of the first transistor T 1  is electrically connected to the drain of the second transistor T 2 , the source of the first transistor T 1  is electrically connected to the power supply voltage signal line PVDD, and the drain of the first transistor T 1  is connected to the source of the light emission control transistor T 0 . The gate of the second transistor T 2  is electrically connected to the first scan line S 2 , and the source of the second transistor T 2  is electrically connected to the drain of the third transistor T 3 . The gate of the third transistor T 3  is electrically connected to the second scan line S 3 , and the source of the third transistor T 2  is electrically connected to the first reference voltage signal line Ref 1 . The gate of the fourth transistor T 4  is electrically connected to the third scan line S 4 , the source of the fourth transistor T 4  is electrically connected to the second reference voltage signal line Ref 2 , and the drain of the fourth transistor T 4  is electrically connected to the anode of the OLED. The gate of the fifth transistor T 5  is electrically connected to the fourth scan line S 5 , the source of the fifth transistor T 5  is electrically connected to the drain of the first transistor T 1 , and the drain of the fifth transistor T 5  is electrically connected to the source of the second transistor T 2 . The first electrode plate of the first capacitor C 1  is electrically connected to the gate of the first transistor T 1  and the drain of the second transistor T 2 . The gate of the sixth transistor T 6  is electrically connected to the fifth scan line S 6 , the source of the sixth transistor T 6  is electrically connected to the data voltage line Data, and the drain of the sixth transistor T 6  is electrically connected to the second electrode plate of the first capacitor C 1 . 
     Since the first initializing module  03  and the second initializing module  04  can simultaneously initialize the first control terminal CR 1  of the light emission driving module  01  and the anode of the OLED, respectively, the second scan line S 3  can be reused as the third scan line S 4 , and the first reference voltage signal line Ref 1  can be reused as the second reference voltage signal line Ref 2 . 
     In addition, in this embodiment, the sixth input terminal IN 6  and the sixth output terminal OUT 6  of the data signal writing module  06  are not connected to the signal lines of other transistors, and the data voltage line Data only writes signals in the data signal writing phase. Therefore, the data signal writing module  06  can share the signal lines with the control terminals of the modules that do not operate at the same time. As shown in  FIG. 8 , the first scan line S 2  can be reused as the fifth scan line S 6 . 
     The pixel driving circuit according to this embodiment may further include a second capacitor C 2  having a first electrode plate electrically connected to the second electrode plate of the first capacitor C 1  and a second electrode plate electrically connected to the power supply voltage signal line PVDD. The second capacitor can stabilize the potential at the second electrode plate of the first capacitor C 1 . 
       FIG. 12  is an operation timing sequence diagram of the pixel driving circuit shown in  FIG. 8 . The operational principle of the pixel driving circuit shown in  FIG. 8  will be described below with reference to  FIG. 12 . 
     As shown in  FIG. 12 , one display cycle of the pixel driving circuit shown in  FIG. 8  includes an initializing phase t 1 , a threshold voltage capturing phase t 2 , a data signal writing phase t 3 , and a light emitting phase t 4  that occur sequentially. In the following, an example will be given, in which each transistor is a P-type transistor. 
     In the initializing phase t 1 , the first scan line S 2  is reused as the fifth scan line S 6  and an on signal, i.e., a low-level signal, is transmitted thereon. Both the second transistor T 2  and the sixth transistor T 6  are turned on. The second scan line S 3  is reused as the third scan line S 4  and an on signal, i.e., a low-level signal, is transmitted thereon. Both the third transistor T 3  and the fourth transistor T 4  are turned on. The first reference voltage signal line Ref 1  is reused as the second reference voltage signal line Ref 2  and a reference voltage is transmitted thereon. Then, the reference voltage is transmitted to the gate of the first transistor T 1  through the turned-on third transistor T 3  and second transistor T 2 , such that the gate of the first transistor T 1  is reset. The reference voltage is transmitted to the anode of the OLED through the turned-on fourth transistor T 4 , such that the anode of the OLED is reset. It should be noted that, since no data voltage or any other signal is transmitted on the data voltage line Data at this time, the sixth transistor T 6 , though turned on, will not affect the initialization. 
     In the threshold voltage capturing phase t 2 , the first scan line S 2  is reused as the fifth scan line S 6  and an on signal, i.e., a low-level signal, is transmitted thereon. Both the second transistor T 2  and the sixth transistor T 6  are turned on. An on signal, i.e., a low-level signal, is transmitted on the fourth scan line S 5 , and the fifth transistor T 5  is turned on. At this time, a power supply voltage is transmitted on the power supply voltage signal line PVDD. Since the initializing phase t 1 , the potential at the gate of the first transistor T 1  has been maintained at the same as the reference voltage and the power supply voltage is higher than the reference voltage, and thus the first transistor T 1  is turned on, and the power supply voltage starts to be gradually stored to the gate of the light emission driving transistor T 1 . When the difference between the potential at the gate and the potential at the source of the first transistor T 1  becomes greater than the threshold voltage, the first transistor T 1  starts to be turned off. 
     In the data signal writing phase t 3 , the fifth scan line S 6  is reused as the first scan line S 2 , and an on signal, i.e., a low-level signal, is transmitted thereon. Both the sixth transistor T 6  and the second transistor T 2  are turned on. At this time, since the third transistor T 3  and the fifth transistor T 5  that are electrically connected to the second transistor T 2  are both turned off, the second transistor T 2 , though turned on, will not affect the writing of the data signal. 
     In the light emitting phase t 4 , an on signal, i.e., a low-level signal, is transmitted on the light emission control signal line EM, and the light emission control transistor T 0  is turned on. A power supply voltage is transmitted on the power supply voltage signal line PVDD. As the difference between the potential at the gate of the first transistor T 1  and the power supply voltage becomes smaller than the threshold voltage, the first transistor T 1  is turned on, and the power supply voltage passes through the first transistor T 1  to form a light emission driving voltage, which is transmitted to the anode of the OLED through the light emission control transistor T 0 . 
     Referring to  FIG. 9 , in an embodiment of the present disclosure, the first input terminal IN 1  of the light emission driving module  01  is connected to the seventh output terminal OUT 7  of the power supply voltage writing module  07 , and the first output terminal OUT 1  is electrically connected to the light emitting display module  00 . The second control terminal CR 2  of the connection control module  02  is connected to the first scan line S 2 , and the second output terminal OUT 2  is connected to the first control terminal CR 1  of the light emission driving module  01 . The third control terminal CR 3  of the first initializing module  03  is connected to the second scan line S 3 , the third input terminal IN 3  is connected to the first reference voltage signal line Ref 1 , and the third output terminal OUT 3  is connected to the second input terminal IN 2  of the connection control module  02 . The fourth control terminal CR 4  of the second initializing module  04  is connected to the third scan line S 4 , the fourth input terminal IN 4  is connected to the second reference voltage signal line Ref 2 , and the fourth output terminal OUT 4  is connected to the anode of the OLED. The fifth control terminal CR 5  of the threshold voltage capturing module  05  is connected to the fourth scan line S 5 , the fifth input terminal IN 5  is connected to the first output terminal OUT 1  of the light emission driving module  01 , and the fifth output terminal OUT 5  is connected to the second input terminal IN 2  of the connection control module  02 . The sixth control terminal CR 6  of the data signal writing module  06  is connected to the fifth scan line S 6 , the sixth output terminal OUT 6  is connected to the first input terminal IN 1  of the light emission driving module  01 , and the sixth input terminal IN 6  is connected to the data voltage line Data. The seventh control terminal CR 7  of the power supply voltage writing module  07  is connected to the sixth scan line S 7 , and the seventh input terminal IN 1  is connected to the power supply voltage signal line PVDD. The first electrode plate of the first capacitor C 1  is electrically connected to the first control terminal CR 1  of the light emission driving module  01 , and the second electrode plate of the first capacitor C 1  is connected to the power supply voltage signal line PVDD. 
     That is, as shown in  FIG. 9 , in this embodiment, the gate of the light emission control transistor T 0  is electrically connected to the light emission control signal line EM, and the drain of the light emission control transistor T 0  is electrically connected to the anode of the OLED. The gate of the first transistor T 1  is electrically connected to the drain of the second transistor T 2 , the source of the first transistor T 1  is electrically connected to the drain of the seventh transistor T 7 , and the drain of the first transistor T 1  is connected to the source of the light emission control transistor T 0 . The gate of the second transistor T 2  is electrically connected to the first scan line S 2 , and the source of the second transistor T 2  is electrically connected to the drain of the third transistor T 3 . The gate of the third transistor T 3  is electrically connected to the second scan line S 3 , and the source of the third transistor T 2  is electrically connected to the first reference voltage signal line Ref 1 . The gate of the fourth transistor T 4  is electrically connected to the third scan line S 4 , the source of the fourth transistor T 4  is electrically connected to the second reference voltage signal line Ref 2 , and the drain of the fourth transistor T 4  is electrically connected to the anode of the OLED. The gate of the fifth transistor T 5  is electrically connected to the fourth scan line S 5 , the source of the fifth transistor T 5  is electrically connected to the drain of the first transistor T 1 , and the drain of the fifth transistor T 5  is electrically connected to the source of the second transistor T 2 . The gate of the sixth transistor T 6  is electrically connected to the fifth scan line S 6 , the source of the sixth transistor T 6  is electrically connected to the data voltage line Data, and the drain of the sixth transistor T 6  is electrically connected to the source of the first transistor T 1 . The gate of the seventh transistor T 7  is electrically connected to the sixth scan line S 7 , and the source of the seventh transistor T 7  is electrically connected to the power supply voltage signal line PVDD. The first electrode plate of the first capacitor C 1  is electrically connected to the gate of the first transistor T 1  and the drain of the second transistor T 2 , and the second electrode plate of the first capacitor C 1  is electrically connected to the power supply voltage signal line PVDD. 
     Since the first initializing module  03  and the second initializing module  04  can simultaneously initialize the first control terminal CR 1  of the light emission driving module  01  and the anode of the OLED, respectively, the second scan line S 3  can be reused as the third scan line S 4 , and the first reference voltage signal line Ref 1  can be reused as the second reference voltage signal line Ref 2 . 
     In addition, in the present embodiment, the power supply voltage writing module  07  and the light emission control transistor T 0  only operate in the light emitting phase, so the sixth scan line S 7  can be reused as the light emission control signal line EM. The data signal writing module  06  and the threshold voltage capturing module  05  only operate in the threshold voltage capturing phase, so the fourth scan line S 5  can be reused as the fifth scan line S 6 . 
       FIG. 13  is an operation timing sequence diagram of the pixel driving circuit shown in  FIG. 9 . The operation principle of the pixel driving circuit shown in  FIG. 9  will be described below with reference to  FIG. 13 . 
     As shown in  FIG. 13 , one display cycle of the pixel driving circuit shown in  FIG. 9  includes an initializing phase t 1 , a threshold voltage capturing phase t 2 , and a light emitting phase t 4  that occur sequentially. In the following, an example will be given, in which each transistor is a P-type transistor. 
     In the initializing phase t 1 , an on signal, i.e., a low-level signal, is transmitted on the first scan line S 2 , and the second transistor T 2  is turned on. The second scan line S 3  is reused as the third scan line S 4 , and an on signal, i.e., a low-level signal, is transmitted thereon. Both the third transistor T 3  and the fourth transistor T 4  are turned on. The first reference voltage signal line Ref 1  is reused as the second reference voltage signal line Ref 2 , and a reference voltage is transmitted thereon. Then, the reference voltage is transmitted to the gate of the first transistor T 1  through the turned-on third transistor T 3  and second transistor T 2 , such that the gate of the first transistor T 1  is reset. The reference voltage is transmitted to the anode of the OLED through the turned-on fourth transistor T 4 , such that the anode of the OLED is reset. 
     In the threshold voltage capturing phase t 2 , an on signal, i.e., a low-level signal, is transmitted on the first scan line S 2 , and the second transistor T 2  is turned on. An on signal, i.e., a low-level signal, is transmitted on the fourth scan line S 5  and the fifth scan line S 6 , and the fifth transistor T 5  and the sixth transistor T 6  are turned on. At this time, a data voltage is transmitted on the data voltage line Data, and the data voltage is transmitted to the source of the first transistor T 1  through the turned-on sixth transistor T 6 . Since the initializing phase t 1 , the potential at the gate of the first transistor T 1  has been maintained at the same as the reference voltage and the potential at the gate of the first transistor T 1  is the data voltage which is higher than the reference voltage, the first transistor T 1  is turned on, and the power supply voltage starts to be gradually stored to the gate of the light emission driving transistor T 1 . When the difference between the potential at the gate and the potential at the source of the first transistor T 1  becomes greater than the threshold voltage, the first transistor T 1  starts to be turned off. It is to be noted that, in the threshold voltage capturing phase t 2 , the data voltage is in fact written into the first control terminal CR 1  of the light emission driving module  01 , so equivalently both the writing of the data signal and the capturing of the threshold voltage are completed in the threshold voltage capturing phase t 2 . 
     In the light emitting phase, an on signal, i.e., a low-level signal, is transmitted on the sixth scan line S 7  and the light emission control signal line EM, and the seventh transistor T 7  and the light emission control transistor T 0  are turned on. A power supply voltage is transmitted on the power supply voltage signal line PVDD, and the power supply voltage is transmitted to the source of the first transistor T 1  through the turned-on seventh transistor T 7 . Since the difference between the potential at the gate of the first transistor T 1  and the power supply voltage is smaller than the threshold voltage, the first transistor T 1  is turned on and the power supply voltage passes through the first transistor T 1  to form a light emission driving voltage, which is transmitted to the anode of the OLED through the light emission control transistor T 0 . 
     The above has been described with reference to the example in which the first reference voltage signal line Ref 1  is reused as the second reference voltage signal line Ref 2  in the initializing phase t 1 .  FIG. 10  shows a case where the first reference voltage signal line Ref 1  is not reused as the second reference voltage signal line Ref 2  in the initializing phase t 1 . As known, the pixel driving circuits are arranged in multiple rows and columns to implement the display. As shown in  FIG. 10 , a pixel driving circuit has other pixel driving circuits in adjacent rows. 
     The pixel driving circuit shown in  FIG. 10  differs from the pixel driving circuit shown in  FIG. 9  mainly in that the first reference voltage signal line Ref 1  is not reused as the second reference voltage signal line Ref 2  in one pixel driving circuit, but the first reference voltage signal line Ref 1  in one pixel driving circuit is connected to the anode of the OLED in the pixel driving circuit at a previous stage. Here, the pixel driving circuit at the previous stage refers to the pixel driving circuit that is initialized and emits light earlier than the one pixel driving circuit. 
     In addition, as shown in  FIG. 10 , the pixel driving circuit is completely the same as the pixel driving circuit shown in  FIG. 9  in terms of connections among the transistors, and the difference between them includes the reusing schemes of the scan lines corresponding to the respective transistors. Specifically, the third scan line S 4 /S 4 ′ electrically connected to the gate of the fourth transistor T 4  is reused as the fourth scan line S 5 /S 5 ′ electrically connected to the gate of the fifth transistor T 5  and the fifth scan line S 6 /S 6 ′ electrically connected to the gate of the sixth transistor T 6 . 
       FIG. 14  is an operation timing sequence diagram of the pixel driving circuit shown in  FIG. 10 , and the operation principle of the pixel driving circuit shown in  FIG. 10  will be described below with reference to  FIG. 14 . It should be noted that, as there are some differences between the operation timing sequence of a pixel driving circuit and that of a pixel driving circuit at the previous stage, for the purpose of illustration, in the pixel driving circuit at the previous stage, the first scan line is denoted as S 2 ′, the second scan line is denoted as S 3 ′, the third scanning line is denoted as S 4 ′, the fourth scanning line is denoted as S 5 ′, the fifth scanning line is denoted as S 6 ′, the sixth scanning line is denoted as S 7 ′, and the light emission control signal line is denoted as EM′. 
     As shown in  FIG. 14 , one cycle of the pixel driving circuit at the current stage and one cycle of the pixel driving circuit at the previous stage each include two phases, an initializing phase t 1 /t 1 ′ and a light emitting phase t 4 /t 4 ′. 
     During the operation of the pixel driving circuit at the current stage, in the initializing phase t 1 , an on signal is transmitted on the first scan line S 2 . The third scan line S 4  is reused as the fourth scan line S 5  and the fifth scan line S 6 , and an on signal is transmitted thereon. Thus, the second transistor T 2 , the fourth transistor T 4 , the fifth transistor T 5 , and the sixth transistor T 6  are turned on. A data voltage is transmitted on the data voltage line Data, and the data voltage is transmitted to the gate of the first transistor T 1  through the sixth transistor T 6 , the first transistor T 1 , the fifth transistor T 5 , and the second transistor T 2  and stored in the first capacitor C 1 . At the same time, a reference voltage is transmitted on the second reference voltage signal line Ref 2 , and the reference voltage is transmitted to the anode of the OLED through the turned-on fourth transistor T 4  to initialize the OLED. 
     The initializing phase t 1 ′ and the light emitting phase t 4 ′ of the pixel driving circuit at the previous stage are similar. However, it should be noted that in the initializing phase t 1 ′ of the pixel driving circuit at the previous stage, the process for initializing the anode of the corresponding OLED is also the process of initializing the light emission driving module  01  (i.e., the first transistor T 1 ) of the pixel driving circuit at the current stage. Specifically, in the initializing phase t 1 ′ of the pixel driving circuit at the previous stage, an on signal is transmitted on the first scan line S 2  and the third scan line of the pixel driving circuit at the current stage, that is, the second transistor T 2  and the third transistor T 3  are turned on. The reference voltage received by the anode of the OLED in the pixel driving circuit at the previous stage is transmitted to the gate of the first transistor T 1  through the third transistor T 3  and the second transistor T 2  in the pixel driving circuit at the current stage, so that the gate of the first transistor T 1  is initialized. 
     In this embodiment, for pixel driving circuits at two adjacent stages, the first reference voltage signal line in the pixel driving circuit at one stage is connected to the anode of the OLED in the pixel driving circuit at the previous stage. In the process for initializing the pixel driving circuit at the previous stage, the first control terminal CR 1  of the light emission driving module  01  in the pixel driving circuit at the current stage can be initialized. At the same time, the writing of the data voltage and the capturing of the threshold voltage can be completed in the process for initializing the pixel driving circuit at the current stage, thereby shortening the cycle and increasing the refresh frequency. 
     It is to be noted that the scheme in this embodiment in which, for pixel driving circuits at two adjacent stages, the first reference voltage signal line in the pixel driving circuit at one stage is connected to the anode of the OLED in the pixel driving circuit at the previous stage, can also be applied to other pixel driving circuits and pixel driving circuits according to the present disclosure. 
     The pixel driving circuit shown in  FIG. 11  differs from the pixel driving circuit shown in  FIG. 9  in that it does not include a threshold voltage capturing module, and the second input terminal IN 2  of the connection control module  02  and the first output terminal OUT 2  of the light emission driving module  01 . That is, in an embodiment of the present disclosure, the drain of the first transistor T 1  is directly electrically connected to the source of the second transistor T 2 . In addition, the second transistor T 2  in the pixel driving circuit shown in  FIG. 11  is an N-type transistor. 
       FIG. 15  is an operation timing sequence diagram of the pixel driving circuit of  FIG. 11 . The operation timing sequence of the pixel driving circuit shown in  FIG. 15  is basically the same as the operation timing sequence of the pixel driving circuit of  FIG. 8  as shown in  FIG. 13 , except that the second transistor T 2  is an N-type transistor while the other transistors are P-type transistors. Thus, in the initializing phase, the on signal that turns on the second transistor T 2  should be a high level. 
     In order to better avoid current leakage, the second transistor T 2  is an N-type transistor and its active layer is a metal oxide active layer with better stability. 
     It is to be noted that the scheme in this embodiment in which the second transistor T 2  is provided as an N-type transistor can also be applied to other pixel driving circuits and pixel driving circuits according to the present disclosure. In addition, in order to better prevent the potential at the gate of the first transistor T 1  from becoming unstable due to current leakage, the third transistor T 3  and the fifth transistor T 5  may also be N-type transistors and their active layers may also be metal oxide active layers. 
     According to an embodiment of the present disclosure, a driving method for a pixel driving circuit is also provided.  FIG. 16  is a timing sequence diagram of a driving method for a pixel driving circuit according to an embodiment of the present disclosure. The driving method can be used to drive the pixel driving circuit according to any of the above embodiments. 
     Referring to  FIG. 1 , the pixel driving circuit according to the embodiment of the present disclosure includes a light emitting display module  00 , a light emission driving module  01 , a connection control module  02 , and a first initializing module  03 . The light emitting display module  00  includes an OLED for light emitting and displaying. The light emission driving module  01  includes a first control terminal CR 1 , a first input terminal IN 1  and a first output terminal OUT 1 . The first output terminal OUT 1  is electrically connected to the light emitting display module  00 . The connection control module  02  includes a second input terminal IN 2  and a second output terminal OUT 2 . The second output terminal OUT 2  is connected to the first control terminal CR 1  of the light emission driving module  01 . In addition, the connection control module  02  may further include a second control terminal CR 2  connected to a first scan line S 2  and used to control the connected/disconnected state between the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02 . The first initializing module  03  includes a third input terminal IN 3  and a third output terminal OUT 3 . The third input terminal IN 3  is connected to a first reference voltage signal line Ref 1 , and the third output terminal OUT 3  is connected to the second input terminal IN 2 . In addition, the first initializing module  03  further includes a third control terminal CR 3 , which is connected to a second scan line S 3  and used to control the connected/disconnected state between the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03 . 
     Referring to  FIG. 16 , the driving method includes the following. 
     In the initializing phase t 1 , the second scan line S 3  receives an on signal, and the third control terminal CR 3  connected to the second scan line S 3  controls the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03  to be connected with each other. The first scan line S 2  receives an on signal, the second control terminal CR 2  connected to the first scan line S 2  controls the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  to be connected with each other. A reference voltage is transmitted on the first reference voltage signal line Ref 1 , and the reference voltage is transmitted to the first control terminal CR 1  through the first initializing module  03  and the connection control module  02  to initialize the first control terminal CR 1 . 
     In the light emitting phase t 4 , the second scan line S 3  receives an off signal, and the third control terminal CR 3  connected to the second scan line S 3  controls the third input terminal IN 3  and the third output terminal OUT 3  of the first initializing module  03  to be disconnected from each other. The first scan line S 2  receives an off signal, and the second control terminal CR 2  connected to the first scan line S 2  controls the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  to be disconnected from each other. The light emission driving module  01  transmits a light emission driving voltage to the light emitting display module  01 . 
     Since the connection control module  02  is provided between the third output terminal OUT 3  of the first initializing module  03  and the first control terminal CR 1  of the light emission driving module  01 , in the light emitting phase of the pixel driving circuit, the first initializing module  03  is disconnected from both the input terminal and the output terminal of the connection control module  02 , so as to avoid a current leakage due to the first initializing module  03  not being completely turned off in the light emitting phase, which would otherwise affect the voltage at the first control terminal CR 1  of the light emission driving module  01 . In this way, the stability of light emission from the OLED in the light emission driving circuit can be guaranteed. 
     In an embodiment of the present disclosure, referring to  FIGS. 2-7 , the pixel driving circuit may further include a second initializing module  04 , which includes a fourth input terminal IN 4  and a fourth output terminal OUT 4 . The fourth input terminal IN 4  is connected to the second reference voltage signal line Ref 2 , and the fourth output terminal OUT 4  is connected to the anode of the OLED; 
     The driving method further includes the following. 
     In the initializing phase t 1 , the fourth control terminal CR 4  connected to the third scan line S 4  controls the fourth input terminal IN 4  and the fourth output terminal OUT 4  of the second initializing module  04  to be connected with each other. A reference voltage is transmitted on the second reference voltage signal line Ref, and the reference voltage is transmitted to the anode of the OLED through the second initializing module  04 . 
     It is to be noted that the first reference voltage signal line Ref 1  can be reused as the second reference voltage signal line Ref 2 . That is, in the initializing phase, the first control terminal CR 1  of the light emission driving module  01  and the anode of the OLED can be initialized simultaneously. Alternatively, the first reference voltage signal line Ref 1  may not be reused as the second reference voltage signal line Ref 2 . The initializing phase can include one phase for initializing the first control terminal CR 1  of the light emission driving module  01  and another phase for initializing the anode of the OLED. 
     In an embodiment of the present disclosure, referring to  FIG. 2 ,  FIG. 3 ,  FIG. 5  and  FIG. 6 , the pixel driving circuit may further include a threshold voltage capturing module  05  and a first capacitor C 1 . The threshold voltage capturing module  05  includes a fifth input terminal IN 5  and a fifth output terminal OUT 5 . The fifth input terminal IN 5  is connected to the first output terminal OUT 1 , and the fifth output terminal OUT 5  is connected to the second input terminal IN 2 . The first capacitor C 1  has a first electrode plate electrically connected to the first control terminal CR 1 . 
     The driving method further includes the following. 
     In the threshold voltage capturing phase t 2 , the fifth control terminal CR 5  connected to the fourth scan line S 5  controls the fifth input terminal IN 5  and the fifth output terminal OUT 5  of the threshold voltage capturing module  05  to be connected with each other. The second control terminal CR 2  connected to the first scan line S 2  controls the second input terminal IN 2  and the second output terminal OUT 2  of the connection control module  02  to be connected with each other. A power supply voltage or the data voltage is written into the first control terminal CR 1  of the light emission driving module  01  through the connection control module  02  and the threshold voltage capturing module  05 . 
     In the light emitting phase t 4 , the fifth control terminal CR 5  connected to the fourth scan line S 5  controls the fifth input terminal IN 5  and the fifth output terminal OUT 5  of the threshold voltage capturing module  05  to be disconnected from each other. 
     In an embodiment of the present disclosure, referring to  FIGS. 2 and 5 , the pixel driving circuit may further include a data signal writing module  06 , which includes a sixth input terminal IN 6  and a sixth output terminal OUT 6 . The sixth input terminal IN 6  is connected to the data voltage line Data, and the sixth output terminal OUT 6  is connected to the second electrode plate of the first capacitor C 1 . The first input terminal IN 1  is connected to the power supply voltage signal line PVDD. 
     The driving method further includes the following. 
     In the threshold voltage capturing phase t 2 , a power supply voltage is transmitted on the power supply voltage signal line PVDD, and the power supply voltage is stored in the first capacitor C 1  through the light emission driving module  01 , the threshold voltage capturing module  05 , and the connection control module  02 . 
     In the data signal writing phase t 3 , the sixth control terminal CR 6 , which is connected to the fifth scan line S 6  and controls the sixth input terminal IN 6 , and the sixth output terminal OUT 6  of the data signal writing module  06  are to be connected with each other. A data voltage is transmitted on the data voltage line Data, and the data voltage is stored in the first capacitor C 1  through the data signal writing module  06 . 
     In an embodiment of the present disclosure, referring to  FIGS. 3 and 6 , the pixel driving circuit may further include a data signal writing module  06  and a power supply voltage writing module  07 . The data signal writing module  06  includes a sixth input terminal IN 6  and a sixth output terminal OUT 6 . The sixth input terminal IN 6  is connected to the data voltage line Data, and the sixth output terminal OUT 6  is connected to the first input terminal IN 1 . The power supply voltage writing module  07  includes a seventh input terminal IN 7  and a seventh output terminal OUT 7 . The seventh input terminal IN 7  is connected to the power supply voltage signal line PVDD, and the seventh output terminal OUT 7  is connected to the first input terminal IN 1 . 
     The driving method includes the following. 
     In the threshold voltage capturing phase t 2 , the sixth control terminal CR 6 , which is connected to the fifth scanning line S 6  and controls the sixth input terminal IN 6 , and the sixth output terminal OUT 6  of the data signal writing module  06  are to be connected with each other. A data voltage is transmitted on the data voltage line Data, and the data voltage is stored in the first capacitor C 1  through the data signal writing module  06 , the light emission driving module  01 , the threshold voltage capturing module  05 , and the connection control module  02 . 
     In the light emitting phase t 4 , the sixth input terminal IN 6  and the sixth output terminal OUT 6  of the data signal writing module  06  are disconnected from each other, and the seventh control terminal CR 7  connected to the sixth scanning line S 7  controls the seventh input terminal IN 7  and the seventh output terminal OUT 7  of the power supply voltage writing module  07  are to be connected with each other. 
     Referring to  FIGS. 4 and 7 , the second input terminal IN 2  is connected to the first output terminal OUT 1 . The pixel driving circuit further includes a data signal writing module  06  and a power supply voltage writing module  07 . The data signal writing module  06  includes a sixth input terminal IN 6  and a sixth output terminal OUT 6 . The sixth input terminal IN 6  is connected to the data voltage line Data, and the sixth output terminal OUT 6  is connected to the first input terminal IN 1 . The power supply voltage writing module  07  includes a seventh input terminal IN 7  and a seventh output terminal OUT 7 . The seventh input terminal IN 7  is connected to the power supply voltage signal line PVDD, and the seventh output terminal OUT 7  is connected to the first input terminal IN 1 . 
     In the threshold voltage capturing phase t 2 , the sixth control terminal CR 6 , which is connected to the fifth scan line S 6  and controls the sixth input terminal IN 6 , and the sixth output terminal OUT 6  of the data signal writing module  06  are to be connected with each other. A data voltage is transmitted on the data voltage line Data, and the data voltage is stored in the first capacitor C 1  through the data signal writing module  06 , the light emission driving module  01 , and the connection control module  02 . 
     In the light emitting phase t 4 , the sixth control terminal CR 6  connected to the fifth scan line S 6  controls the sixth input terminal IN 6  and the sixth output terminal OUT 6  of the data signal writing module  06  to be disconnected from each other. The seventh control terminal CR 7 , which is connected to the sixth scanning line S 7  and controls the seventh input terminal IN 7 , and the seventh output terminal OUT 7  of the power supply voltage writing module  07  are to be connected with each other. 
     In the driving method for the pixel driving circuit according to the embodiment of the present disclosure, the first initializing module  01  and/or the threshold voltage capturing module  05  are connected to the first control terminal CR 1  of the light emission driving module  01  through the connection control module  01 . In the light emitting phase of the pixel driving circuit, the input terminal and the output terminal of the connected control module  02  are disconnected from each other, that is, the first initializing module  03  and/or the threshold voltage capturing module  05  is disconnected from the first control terminal CR 1  of the light emission driving module  01  simultaneously, so as to avoid the current leakage due to the first initializing module  03  and/or the threshold voltage capturing module  05  not being completely turned off in the light emitting phase, which would otherwise affect the voltage at the first control terminal CR 1  of the light emission driving module  01 , thereby guaranteeing the stability of light emission from the OLED in the light emission driving circuit. 
       FIG. 17  is a schematic diagram of an organic light emitting display panel according to an embodiment of the present disclosure. The organic light emitting display panel according to the embodiment of the present disclosure includes the pixel driving circuit according to any of the above embodiments. As shown in  FIG. 17 , the organic light emitting display panel according to the embodiment of the present disclosure includes a plurality of pixel units P, each corresponding to a pixel driving circuit. In addition, the OLED and the transistors in the pixel driving circuit are located in different film layers. The light emission control transistor T 0  and the OLED are electrically connected with each other through a via. 
     In the organic light emitting display panel according to the embodiment of the present disclosure, the voltage at the first control terminal of the light emission driving module in the pixel driving circuit is stable, and the light emission driving voltage transmitted from the light emission driving module to the light emitting display module is stable. Therefore, the display quality of the organic light emitting display panel is good. 
     In addition, the organic light emitting display panel according to the embodiment of the present disclosure can be applied to organic light emitting display devices, such as mobile phones, computers, and televisions. The organic light emitting display device includes a display area and a non-display area surrounding the display area, and correspondingly the pixel driving circuit is provided in the display area. 
     While the preferred embodiments of the present disclosure have been described above, the scope of the present disclosure is not limited thereto. Various modifications, equivalent alternatives or improvements can be made by those skilled in the art without departing from the scope of the present disclosure. These modifications, equivalent alternatives and improvements are to be encompassed by the scope of the present disclosure.