Patent Publication Number: US-11043893-B1

Title: Bias regulation system

Description:
BACKGROUND 
     Field 
     This disclosure relates generally to electronic circuits, and more specifically, to a bias regulation system. 
     Related Art 
     Integrated circuits today may have hundreds of thousands to hundreds of millions of transistors which contribute to the overall power consumption of these integrated circuits. In CMOS technologies, a body, or well terminal of P-channel transistors is typically connected to a positive rail supply and a body, or well terminal of N-channel transistors is typically connected to ground rail supply. In some CMOS circuits, it may be desirable to bias body or well terminals at voltages other than rail voltages to reduce leakage current and thus reduce power consumption. However, challenges exist in performance, cost, and power consumption tradeoffs when designing a bias generation circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. 
         FIG. 1  illustrates, in simplified block diagram form, an example low power bias regulation system in accordance with an embodiment. 
         FIG. 2A  and  FIG. 2B  illustrate, in simplified schematic diagram form, an example level shifter circuit implementation in accordance with an embodiment. 
         FIG. 2C  illustrates, in plot diagram form, example level shifter switch timing in accordance with an embodiment. 
         FIG. 3A  illustrates, in simplified schematic diagram form, example comparator circuit implementation in accordance with an embodiment. 
         FIG. 3B  illustrates, in plot diagram form, example comparator switch timing in accordance with an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Generally, there is provided, a low power bias regulator circuit. The low power bias regulator includes circuitry configured to provide back biasing voltages which extend beyond typical operational voltage ranges without using high voltage transistors. Level shifted reference voltages allow a feedback path from a charge pump output to a comparator input to have minimum delay and thus more stable voltage regulation. Utilizing switched capacitor technology in the reference voltage level shifter and comparator provide low power consumption and highly responsive voltage regulation. 
       FIG. 1  illustrates, in simplified block diagram form, an example low power bias regulation system  100  in accordance with an embodiment. Bias regulation system  100  is implemented as an integrated circuit and has a first input terminal labeled VREF 1  for receiving a first input voltage signal VREF 1 , a second input terminal labeled VREF 2  for receiving a second input voltage signal VREF, a third input terminal labeled RCLK for receiving a refresh clock RCLK, voltage supply terminals labeled VDDA, VSUP, and VSS, a first output terminal labeled VBB 1  for providing a first bias voltage VBB 1 , and a second output terminal labeled VBB 2  for providing a second bias voltage VBB 2 . In this embodiment, an analog operating voltage (e.g., operating voltage for analog circuitry) is supplied at the VDDA supply terminal, an alternative voltage (e.g., offset voltage or voltage for operating digital circuitry) is supplied at the VSUP supply terminal, and a ground voltage is supplied at the VSS supply terminal. In this embodiment, bias regulation system  100  includes level shifter circuits  102  and  108 , comparator circuits  104  and  110 , charge pump circuits  106  and  112 , load circuit  114 , clock circuit  116 - 122 , discharge circuits  124  and  126 , and capacitors  128  and  130 . 
     In this embodiment, the level shifter circuits  102  and  108 , labeled LS 1  and LS 2  respectively, are characterized as high voltage tolerant level shifter circuits. The level shifter circuits  102  and  108  each have inputs to receive a reference voltage (e.g., VREF 1 , VREF 2 ), the refresh clock RCLK, a digital feedback signal (e.g., COUT 1 , COUT 2 ), and an output to provide a level shifted voltage (e.g., SVREF 1 , SVREF 2 ). Each of the level shifters  102  and  108  is configured to generate the level shifted voltage based on the received reference voltage. For example, level shifter  102  is configured to generate the SVREF 1  voltage by shifting the VREF 1  voltage by a VSUP voltage amount such that SVREF 1  substantially equals VREF 1 +VSUP, and level shifter  108  is configured to generate the SVREF 2  voltage by shifting the VREF 2  voltage such that SVREF 2  substantially equals −VREF 2 . In this embodiment, the generated SVREF 1  may exceed a maximum rail voltage (e.g., SVREF 1 &gt;VDDA) and the generated SVREF 2  voltage may exceed a minimum rail voltage (e.g., SVREF 2 &lt;VSS). In some embodiments, level shifter  102  may be bypassed or may be configured to pass the VREF 1  voltage through to the SVREF 1  output when the desired SVREF 1  voltage is within a normal operating rail voltage range such that SVREF 1  equals VREF 1 . The voltages SVREF 1  and SVREF 2  from the level shifters  102  and  108  are provided to respective inputs of the comparator circuits  104  and  110 . Each of the level shifters  102  and  108  is further configured to refresh the voltages SVREF 1  and SVREF 2  based on the RCLK and respective feedback signals COUT 1  and COUT 2  output from comparator circuits  104  and  110 . 
     In this embodiment, the comparator circuits  104  and  110 , labeled CMP 1  and CMP 2  respectively, are characterized as high voltage tolerant comparator circuits. The comparator circuits  104  and  110  each have a first input to receive a first input voltage (e.g., VBB 1 , VBB 2 ), a second input to receive a second input voltage (e.g., SVREF 1 , SVREF 2 ), and an output to provide a digital value (e.g., COUT 1 , COUT 2  signals). Each of the comparators  104  and  110  is configured to compare the first input voltage at the first input with the second input voltage at the second input and in turn, generate the digital value based on a difference between the first input voltage and the second input voltage. For example, when the first input voltage is greater than the second input voltage, the digital value output signal will be at a first logic level, and when the first input voltage is less than the second input voltage, the digital value output signal will be at a second logic value. In this embodiment, each of the comparator output signals COUT 1  and COUT 2  is fed back to respective digital feedback signal inputs of level shifters  102  and  108  by way of feedback paths  132  and  134 . 
     The charge pump circuits  106  and  112 , labeled CHARGE PUMP 1  and CHARGE PUMP 2  respectively, each have inputs to receive a clock signal (e.g., CPCK 1 , CPCK 2 ), a first input voltage (e.g., VDDA), a second input voltage (e.g., VSUP, VSS), and an output to provide a charge pumped output voltage (e.g., VBB 1 , VBB 2 ). Each of the charge pumps  106  and  112  is configured to generate a desired charge pumped output voltage based on the clock signal and input voltages. For example, charge pump  106  is configured to generate the first bias voltage VBB 1 , and charge pump  112  is configured to generate the second bias voltage VBB 2 . In this embodiment, the generated VBB 1  voltage is fed back to the first input of comparator  104  by way of feedback path  136 , and the generated VBB 2  voltage is fed back to the first input of comparator  110  by way of feedback path  138 . 
     In this embodiment, charge pumps  106  and  112  are coupled to the load circuit  114  and configured to provide respective bias voltages for devices of the load circuit. For example, the output of charge pump  106  may be coupled to N-wells of P-channel transistors in the load circuit  114  such that the generated VBB 1  voltage serves as a back bias voltage for the P-channel transistors. Likewise, the output of charge pump  112  may be coupled to P-wells of N-channel transistors in the load circuit  114  such that the generated VBB 2  voltage serves as a back bias voltage for the N-channel transistors. In this embodiment, the P-channel and N-channel transistors of the load circuit  114  may be supplied by rail voltages VSUP and VSS. The generated VBB 1  voltage may exceed a maximum rail voltage (e.g., VBB 1 &gt;VSUP) and the generated VBB 2  voltage may exceed a minimum rail voltage (e.g., VBB 2 &lt;VSS). In this embodiment, the load circuit  114  may include any suitable circuitry having a well or body which may be coupled to receive the charge pumped output voltage as a back bias voltage. 
     The clock circuit of the bias regulation system  100  is configured to generate charge pump clocks CPCK 1  and CPCK 2  based on the comparator output signals COUT 1  and COUT 2  respectively. For example, when the VBB 1  voltage drops below the SVREF 1  voltage, the resulting COUT 1  signal serves to enable the CPCK 1  clock generation. The charge pump  106  resumes pumping based on the CPCK 1  clock, and in turn, increases the VBB 1  voltage to the desired value (e.g., SVREF 1 ). In this embodiment, an example implementation of the clock circuit includes an OR gate  116 , an oscillator clock circuit  118  labeled OSC, and AND gates  120  and  122 . 
     A first input of OR gate  116  is coupled to the output of the comparator  104  to receive the COUT 1  signal, and a second input of OR gate  116  is coupled to the output of the comparator  110  to receive the COUT 2  signal. An output of the OR gate  116  labeled CKEN is coupled to an input of the oscillator  118  and serves as an enable signal to the oscillator  118 . For example, in the clock circuit configuration depicted in  FIG. 1 , when either of the comparator output signals COUT 1  and COUT 2  is at a logic high state, the CKEN signal is at a logic high state enabling the oscillator  118  to generate an oscillator clock signal OCLK at an output labeled OCLK. In other embodiments, other clock circuit configurations may be implemented to enable and generate the CPCK 1  and CPCK 2  clock signals. 
     A first input of AND gate  120  is coupled to the output of the comparator  104  to receive the COUT 1  signal, and a second input of AND gate  120  is coupled to the output of the oscillator  118  to receive the OCLK signal. An output of the AND gate  120  labeled CPCK 1  is coupled to an input of the charge pump  106  to provide the charge pump clock signal CPCK 1 . Likewise, a first input of AND gate  122  is coupled to the output of the comparator  110  to receive the COUT 2  signal, and a second input of AND gate  122  is coupled to the output of the oscillator  118  to receive the OCLK signal. An output of the AND gate  122  labeled CPCK 2  is coupled to an input of the charge pump  1112  to provide the charge pump clock signal CPCK 2 . 
     The discharge circuits  124  and  126 , labeled DCHG 1  and DCHG 2  respectively, are coupled at the VBB 1  and VBB 2  outputs. Each of the discharge circuits  124  and  126  are configured to be enabled during voltage change transitions (e.g., VREF 1 , VREF 2  changes). For example, to facilitate an on-the-fly change to a lower VBB 1  voltage, the discharge circuit  124  may be enabled to assist a more rapid transition to the lower VBB 1  voltage. In this embodiment, each of the discharge circuits  124  and  126  are configured to be enabled based on the respective comparator output signals COUT 1  and COUT 2 . 
     The capacitors  128  and  130  are coupled at the VBB 1  and VBB 2  outputs, respectively. A first terminal of capacitor  128  is coupled at the VBB 1  output and the second terminal of capacitor  128  is coupled at the VSUP supply terminal. A first terminal of capacitor  130  is coupled at the VBB 2  output and the second terminal of capacitor  130  is coupled at the VSS supply terminal. In this embodiment, capacitors  128  and  130  serve to filter and stabilize the respective generated VBB 1  and VBB 2  voltages. 
       FIG. 2A  and  FIG. 2B  illustrate, in simplified schematic diagram form, example level shifter circuit implementations  200  and  210  in accordance with an embodiment. Level shifters  200  and  210  correspond to the level shifters  102  and  108  of  FIG. 1 , respectively. In this embodiment, the level shifter  200  and  210  are characterized as high voltage tolerant level shifter circuits. For example, level shifter  200  is configured to generate a level shifted reference voltage (e.g., SVREF 1 ) that may exceed a maximum rail voltage and level shifter  210  is configured to generate a level shifted reference voltage (e.g., SVREF 2 ) that may exceed a minimum rail voltage. 
     The level shifter  200  includes a switch control circuit  202 , switches S 11 -S 14 , and capacitors  204  and  206 . The switch control circuit  202  includes inputs to receive the COUT 1  digital signal and the RCLK signal, and outputs for providing switch control signals S 11 -S 14 . In this embodiment, the switch control circuit  202  is configured to generate a predetermined switch control signal timing sequence as depicted in  FIG. 2C  based on the COUT 1  and RCLK signals. In operation, the control signal timing sequence is used for refreshing or updating the level shifted voltage SVREF 1  based on the VREF 1  voltage. For example, the COUT 1  signal may trigger the switch control timing sequence to run for a predetermined number of cycles sufficient to refresh or update the SVREF 1  voltage. Alternatively, the switch control timing sequence may run continuously or periodically, by way of the RCLK, to refresh or update the SVREF 1  voltage. 
     In this embodiment, the switches S 11 -S 14  and capacitors  204  and  206  are configured and arranged to form a switched capacitor level shifting circuit. A first terminal of switch S 11  is coupled to the VREF 1  input and a second terminal of switch S 11  is coupled to a first terminal of switch S 13  and a first terminal of capacitor  204  at node N 1 . A first terminal of switch S 12  is coupled to the VSS supply terminal and a second terminal of switch S 12  is coupled to a first terminal of switch S 14  and a second terminal of capacitor  204  at node N 2 . A second terminal of switch S 13  is coupled to the SVREF 1  output and a first terminal of capacitor  206 , and a second terminal of capacitor  206  is coupled to the VSS supply terminal. A second terminal of switch S 14  is coupled to the VSUP supply terminal. 
     In operation, when switches S 11  and S 12  are closed (e.g., conducting) and switches S 13  and S 14  are open (e.g., non-conducting), capacitor  204  is charged to the VREF 1  voltage level while capacitor  206  is kept in a hold state. When switches S 11  and S 12  are open and switches S 13  and S 14  are closed, capacitor  204  is coupled to capacitor  206  such that capacitor  206  to charged to a VREF 1 +VSUP voltage level to generate the level shifted output voltage SVREF 1 . In some embodiments, level shifter  200  may be configured to pass the VREF 1  voltage through to the SVREF 1  output (e.g., switches S 11 -S 13  closed, S 14  opened) when the desired SVREF 1  voltage is within a normal operating rail voltage range such that SVREF 1  equals VREF 1 . 
     The level shifter  210  includes a switch control circuit  212 , switches S 21 -S 24 , and capacitors  214  and  216 . The switch control circuit  212  includes inputs to receive the COUT 2  digital signal and the RCLK signal, and outputs for providing switch control signals S 21 -S 24 . In this embodiment, the switch control circuit  212  is configured to generate a predetermined switch control signal timing sequence as depicted in  FIG. 2C  based on the COUT 1  and RCLK signals. In operation, the control signal timing sequence is used for refreshing or updating the level shifted voltage SVREF 2  based on the VREF 2  voltage. For example, the COUT 2  signal may trigger the switch control timing sequence to run for a predetermined number of cycles sufficient to refresh or update the SVREF 2  voltage. Alternatively, the switch control timing sequence may run continuously or periodically, by way of the RCLK, to refresh or update the SVREF 1  voltage. 
     In this embodiment, the switches S 21 -S 24  and capacitors  214  and  216  are configured and arranged to form a switched capacitor level shifting circuit. A first terminal of switch S 21  is coupled to the VSS supply terminal and a second terminal of switch S 21  is coupled to a first terminal of switch S 23  and a first terminal of capacitor  214  at node N 3 . A first terminal of switch S 22  is coupled to the VREF 2  input and a second terminal of switch S 22  is coupled to a first terminal of switch S 24  and a second terminal of capacitor  214  at node N 4 . A second terminal of switch S 23  is coupled to the SVREF 2  output and a first terminal of capacitor  216 , and a second terminal of capacitor  216  is coupled to the VSS supply terminal. A second terminal of switch S 24  is coupled to the VSS supply terminal. 
     In operation, when switches S 21  and S 22  are closed (e.g., conducting) and switches S 23  and S 24  are open (e.g., non-conducting), capacitor  214  is charged to a negative VREF 2  voltage level while capacitor  216  is kept in a hold state. When switches S 21  and S 22  are open and switches S 23  and S 24  are closed, capacitor  214  is coupled to capacitor  216  such that capacitor  216  is charged to the negative voltage level to generate the level shifted output voltage SVREF 2 . 
       FIG. 2C  illustrates, in plot diagram form, example level shifter switch control signal timing sequence  220  in accordance with an embodiment. In this embodiment, the timing sequence  220  includes control signal timing waveforms S 11 -S 14  and S 21 -S 24  corresponding to respective switches S 11 -S 14  and S 21 -S 24  depicted in  FIG. 2A  and  FIG. 2B . For illustration purposes, each control signal waveform shown in the timing sequence  220  is representative of two controls signals. For example, the waveform labeled S 11 ,S 21  is representative of each of the S 11  and S 21  control signal timing waveforms, and likewise for waveforms labeled S 12 ,S 22 -S 14 ,S 24 . The waveforms S 11 ,S 21 -S 14 ,S 24  illustrated in  FIG. 2C  are shown with logic high and logic low values versus time. For example, the waveform logic high time corresponds to a closed switch state period and the waveform logic low time corresponds to an open switch state period of respective switches S 11 -S 14  and S 21 -S 24 . 
     In this embodiment, control signals S 11 ,S 21 -S 14 ,S 24  may be formed as non-overlapping signals to facilitate sequencing of respective switches S 11 -S 14  and S 21 -S 24  (e.g., opening and closing transitions) in a manner sufficient to maximize charge conservation. For example, a first sequencing of control signals S 11 ,S 21 -S 14 ,S 24  is depicted during a transition from PHASE 1  (e.g., charging capacitors  204  and  214 ) to PHASE 2  (e.g., transferring charge to capacitors  206  and  216 ) and a second sequencing of control signals S 11 ,S 21 -S 14 ,S 24  is depicted during a transition from PHASE 2  to PHASE 1 . In the PHASE 1  to PHASE 2  control signal sequence of the level shifters  200  and  210 , the S 11  and S 21  switches are opened at time t 0 . At time t 1 , the S 12  and S 22  switches are opened and the S 14  and S 24  switches are closed. At time t 2 , the S 13  and S 22  switches are closed. In the PHASE 2  to PHASE 1  control signal sequence of the level shifters  200  and  210 , the S 13  and S 23  switches are opened at time t 3 . At time t 4 , the S 12  and S 22  switches are closed and the S 14  and S 24  switches are opened. At time t 5 , the S 11  and S 21  switches are closed. 
       FIG. 3A  illustrates, in simplified schematic diagram form, example comparator circuit implementation  300  in accordance with an embodiment. The comparator circuit  300  is an example implementation of each of the comparators  104  and  110  of  FIG. 1 . In this embodiment, the comparator circuit  300  is characterized as high voltage tolerant comparator circuit  300 . For example, comparator circuit  300  is configured to generate a digital value based on a difference between input signals which may exceed a maximum rail voltage (e.g., comparator  104 ) or may exceed a minimum rail voltage (e.g., comparator  110 ). The comparator circuit  300  has a first input terminal labeled VBB for receiving a charge pump output voltage signal (e.g., VBB 1 , VBB 2 ), a second input terminal labeled SVREF for receiving a level shifted reference voltage signal (e.g., SVREF 1 , SVREF 2 ), an output terminal labeled COUT (e.g., COUT 1 , COUT 2 ). In this embodiment, the comparator circuit  300  includes a P-channel transistor  302 , an N-channel transistor  304 , a capacitor  306 , and switches S 1 -S 4 . 
     The input terminals VBB and SVREF are selectively coupled to an input of an inverter stage by way of capacitor  306  and switches S 2  and S 3 . In this embodiment, the transistors  302  and  304  are configured and arranged to form the inverter stage. A first current electrode of transistor  302  is coupled to a VC supply terminal to receive an operating voltage VC for the inverter stage. A second current electrode of transistor  302  is coupled to a first current electrode of transistor  304  at node C 3  and a second current electrode of transistor  304  is coupled at the VSS supply terminal. A control electrode of transistor  302  is coupled to a control electrode of transistor  304  and a first terminal of capacitor  306  at input node C 2 . A second terminal of capacitor  306  is coupled to a first terminal of switch S 2  and a first terminal of switch S 3  at node C 1 . A second terminal of switch S 2  is coupled at the VBB terminal and a second terminal of switch S 3  is coupled at the SVREF terminal. A first terminal of switch S 4  is coupled at the node C 2  and a second terminal of switch S 4  is coupled at the node C 3 . An output of the inverter stage is coupled to a first terminal of switch S 1  at node C 3  and a second terminal of switch S 1  is coupled at the COUT terminal 
     In operation, the inverter stage along with the switches S 1 -S 4  are configured to compare the first input voltage VBB with the second input voltage SVREF and in turn, generate a digital value at the COUT output based on the difference between the first input voltage VBB and the second input voltage SVREF. The comparator circuit  300  may include one or more gain stages coupled to the output of the inverter stage to propagate the COUT signal with fast transition times and minimal power. In this embodiment, the VC operating voltage may be generated by way of a voltage generation circuit configured to limit short circuit current or peak currents in the transistors of the inverter stage. 
       FIG. 3B  illustrates, in plot diagram form, example comparator switch control signal timing sequence  310  of the example comparator circuit  300  in accordance with an embodiment. The switch timing  304  includes control signal timing waveforms S 1 -S 4  corresponding to switches S 1 -S 4  as depicted in  FIG. 3A . The waveforms S 1 -S 4  illustrated in  FIG. 3B  are shown with logic high and logic low values versus time. For example, the waveform logic high time corresponds to a closed switch state period and the waveform logic low time corresponds to an open switch state period of switches S 1 -S 4 . 
     In this embodiment, control signals S 1 -S 4  may be formed as non-overlapping signals to facilitate sequencing of switches S 1 -S 4  (e.g., opening and closing transitions) in a manner sufficient to minimize charge injection, redistribution, and/or cross-conduction. For example, a first sequencing of control signals S 1 -S 4  is depicted during a transition from PHASE 1  (e.g., monitoring state) to PHASE 2  (e.g., calibration state) and a second sequencing of control signals S 1 -S 4  is depicted during a transition from PHASE 2  to PHASE 1 . In the PHASE 1  to PHASE 2  control signal sequence of the comparator circuit  300 , the S 1  switch is opened at time t 0 . At time t 1 , the S 2  switch is opened, and at time t 2 , the S 3  and S 4  switches are closed. In the PHASE 2  to PHASE 1  control signal sequence of the comparator core circuit  300 , the S 4  switch is opened at time t 3 . At time t 4 , the S 3  switch is opened, and at time t 5 , the S 2  switch is closed. At time t 6 , the S 1  switch is closed. 
     Generally, there is provided, a bias circuit including a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output; a level shifter circuit coupled to the comparator circuit, the level shifter configured to receive a reference voltage at an input and generate the second voltage at an output; and a charge pump circuit coupled to the comparator circuit, the charge pump circuit configured to generate the first voltage at an output based on the digital value. The level shifter circuit may be further configured to receive the digital value and refresh the second voltage based on the digital value. The level shifter circuit may be configured to generate the second voltage by level shifting the reference voltage to a voltage value exceeding a supply voltage. The level shifter circuit may include a switched capacitor circuit configured to generate the second voltage. The comparator circuit may include a switched capacitor circuit configured to sample the first voltage during a first phase and sample the second voltage during a second phase. The comparator circuit may be further configured to generate the digital value based on a difference between the first voltage and the second voltage. The charge pump circuit may be configured to generate the first voltage as a body bias voltage for a load circuit. The bias circuit may further include a clock circuit configured to generate a clock signal for the charge pump circuit, the clock signal enabled based on the digital value. The bias circuit may further include a discharge circuit coupled at the output of the charge pump circuit, the discharge circuit configured to assist a transition from the first voltage to a third voltage. 
     In another embodiment, there is provided, a bias circuit including a charge pump circuit configured to generate a bias voltage at an output; a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output based on a difference between the first voltage and the second voltage, the output of the comparator circuit coupled to an input of the charge pump circuit; a first feedback path coupled between the output of the charge pump circuit and the first input of the comparator circuit, the first feedback path configured to provide the bias voltage as the first voltage; and a level shifter circuit coupled to the comparator circuit, the level shifter configured to receive a reference voltage at a first input and generate the second voltage at an output. The bias circuit may further include a second feedback path coupled between the output of the comparator circuit and a second input of the level shifter circuit, the second feedback path configured to provide the digital value to the level shifter circuit and refresh the second voltage based on the digital value. The level shifter circuit may be configured to generate the second voltage by level shifting the reference voltage to a voltage value exceeding a supply voltage. The level shifter circuit may include a switched capacitor circuit configured to generate the second voltage. The comparator circuit may include a switched capacitor circuit configured to sample the first voltage during a first phase and sample the second voltage during a second phase. The charge pump circuit may be configured to generate the bias voltage as a body bias voltage for a load circuit. The bias circuit may further include a clock circuit configured to generate a clock signal for the charge pump circuit, the clock signal enabled based on the digital value. 
     In yet another embodiment, there is provided, a bias circuit including a charge pump circuit configured to generate a bias voltage at an output; a comparator circuit configured to compare a first voltage at a first input with a second voltage at a second input and generate a digital value at an output, the output of the comparator circuit coupled to an input of the charge pump circuit; a first feedback path coupled between the output of the charge pump circuit and the first input of the comparator circuit, the first feedback path configured to provide the bias voltage as the first voltage; and a level shifter circuit coupled to the comparator circuit, the level shifter configured to receive a reference voltage at a first input and generate the second voltage at an output. The bias circuit may further include a second feedback path coupled between the output of the comparator circuit and a second input of the level shifter circuit, the second feedback path configured to provide the digital value to the level shifter circuit and refresh the second voltage based on the digital value. The level shifter circuit may include a switched capacitor circuit configured to generate the second voltage. The comparator circuit may include a switched capacitor circuit configured to sample the first voltage during a first phase and sample the second voltage during a second phase. 
     By now it should be appreciated that there has been provided, a low power bias regulator circuit. The low power bias regulator includes circuitry configured to provide back biasing voltages which extend beyond typical operational voltage ranges without using high voltage transistors. Level shifted reference voltages allow a feedback path from a charge pump output to a comparator input to have minimum delay and thus more stable voltage regulation. Utilizing switched capacitor technology in the reference voltage level shifter and comparator provide low power consumption and highly responsive voltage regulation. 
     Because the apparatus implementing the present invention is, for the most part, composed of electronic components and circuits known to those skilled in the art, circuit details will not be explained in any greater extent than that considered necessary as illustrated above, for the understanding and appreciation of the underlying concepts of the present invention and in order not to obfuscate or distract from the teachings of the present invention. 
     Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims. 
     Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles. 
     Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.