Patent Publication Number: US-2009236698-A1

Title: Method of fabricating a semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 11/926,520, filed Oct. 29, 2007, now pending, which is a continuation of U.S. application Ser. No. 11/731,415, filed Mar. 30, 2007, now U.S. Pat. No. 7,473,971, which is a continuation of U.S. application Ser. No. 10/914,357, filed Aug. 9, 2004, now U.S. Pat. No. 7,476,576, which is a continuation of U.S. application Ser. No. 09/808,162, filed Mar. 13, 2001, now U.S. Pat. No. 6,803,264, which is a divisional of U.S. application Ser. No. 09/386,782, filed Aug. 31, 1999, now U.S. Pat. No. 6,335,231, which claims the benefit of a foreign priority application filed in Japan as Serial No. 10-251635 on Sep. 4, 1998, all of which are incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor device fabricated by using an SOI (Silicon on Insulator) substrate and a method of fabricating the same. Specifically, the invention relates to a semiconductor device including a thin film transistor (hereinafter referred to as TFT) formed on an SOI substrate. 
     Incidentally, in the present specification, the semiconductor device indicates any device capable of functioning by using semiconductor characteristics. Thus, the semiconductor device includes not only a TFT but also an electro-optical device typified by a liquid crystal display device or a photoelectric conversion device, a semiconductor circuit in which TFTs are integrated, and an electronic equipment containing such an electro-optical device or a semiconductor circuit as a part. 
     2. Description of the Related Art 
     In recent years, VLSI techniques have been remarkably developed, and attention has been paid to an SOI (Silicon on Insulator) structure for realizing low power consumption. This technique is such a technique that an active region (channel formation region) of an FET, which has been conventionally formed of bulk single crystal silicon, is made thin film single crystal silicon. 
     In an SOI substrate, a buried oxide film made of silicon oxide exists on single crystal silicon, and a single crystal silicon thin film is formed thereon. Various methods of fabricating such SOI substrates are known. As a typical SOI substrate, an SIMOX substrate is known. The term SIMOX is an abbreviation for Separation-by-Implanted Oxygen, and oxygen is ion implanted into a single crystal silicon substrate to form a buried oxide layer. The details of the SIMOX substrate are disclosed in [K. Izumi, M. Docken and H. Ariyoshi: “C.M.O.S. devices fabrication on buried SiO 2  layers formed by oxygen implantation into silicon”, Electron. Lett., 14, 593-594 (1978)]. 
     Recently, attention has also been paid to a bonded SOI substrate. The bonded SOI substrate realizes the SOI structure by bonding two silicon substrates as suggested by its name. If this technique is used, a single crystal silicon thin film can be formed also on a ceramic substrate or the like. 
     Among the bonded SOI substrates, in recent years, attention has been especially paid to a technique called ELTRAN (registered trademark by Canon K.K.). This technique is a method of fabricating an SOI substrate using selective etching of a porous silicon layer. The particular technique of the ELTRAN method is disclosed in, K. Sakaguchi et al., “Current Progress in Epitaxial Layer Transfer (ELTRAN)”, IEICE TRANS. ELECTRON. Vol. E80 C. No. 3 pp. 378-387 March 1997, in detail. 
     As another SOI technique attracting attention, there is a technique called Smart-Cut (registered trademark of SOITEC Co.). The Smart-Cut method is a technique developed by SOITEC Co. in France in 1996, and is a method of fabricating a bonded SOI substrate using hydrogen embrittlement. The particular technique of the Smart-Cut method is disclosed in “Industrial Research Society (Kogyo Chosa Kai); Electronic Material, August, pp. 83-87, 1977” in detail. 
     When the foregoing SOI substrate is fabricated, a single crystal silicon substrate having a main surface of a crystal face of a {100} plane (crystal orientation is &lt;100&gt; orientation) has been used in any technique. The reason is that the {100} plane has lowest interface state density (Qss) and is suitable for a field effect transistor that is sensitive to interface characteristics. 
     However, with respect to the SOI substrate used for a TFT, since a single crystal silicon thin film must be formed on an insulating layer, higher priority must be given to adhesion to the insulating layer than the interface state density. That is, even if the interface state density is low, it is meaningless if the single crystal silicon thin film peels off. 
     SUMMARY OF THE INVENTION 
     The present invention has been made in view of such problems, and an object thereof is to provide a semiconductor device with high reliability by fabricating an SOI substrate suitable for a TFT and by forming TFTs on the substrate. 
     The structure of the present invention disclosed in the present specification is characterized by comprising the steps of: 
     forming a hydrogen-containing layer at a predetermined depth in a single crystal semiconductor substrate having a main surface of a {110} plane; 
     bonding the single crystal semiconductor substrate and a supporting substrate to each other; 
     splitting the single crystal semiconductor substrate by a first heat treatment along the hydrogen-containing layer; 
     carrying out a second heat treatment at a temperature of 900 to 1200° C.; 
     grinding a single crystal semiconductor layer remaining on the supporting substrate and having a main surface of a {110} plane; and 
     forming a plurality of TFTs each having an active layer of the single crystal semiconductor layer. 
     Further, another structure of the present invention is characterized by comprising the steps of: 
     forming a porous semiconductor layer by anodization of a single crystal semiconductor substrate having a main surface of a {110} plane; 
     carrying out a heat treatment to the porous semiconductor layer in a reducing atmosphere; 
     carrying out epitaxial growth of a single crystal semiconductor layer having a main surface of a {110} plane on the porous semiconductor layer; 
     bonding the single crystal semiconductor substrate and a supporting substrate to each other; 
     carrying out a heat treatment at a temperature of 900 to 1200° C.; 
     grinding the single crystal semiconductor substrate until the porous semiconductor layer is exposed; 
     removing the porous semiconductor layer to expose the single crystal semiconductor layer; and 
     forming a plurality of TFTs each having an active layer of the single crystal semiconductor layer on the supporting substrate. 
     Still further, another structure of the present invention is characterized by comprising the steps of: 
     forming an oxygen-containing layer at a predetermined depth in a single crystal semiconductor substrate having a main surface of a {110} plane; 
     changing the oxygen-containing layer into a buried insulating layer by a heat treatment; and 
     forming a plurality of TFTs each having an active layer of a single crystal semiconductor layer having a main surface of a {110} plane on the buried insulating layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1F  are views showing fabricating steps of an SOI substrate of Embodiment 1. 
         FIGS. 2A to 2E  are views showing fabricating steps of a TFT of Embodiment 1. 
         FIGS. 3A to 3F  are views showing fabricating steps of an SOI substrate of Embodiment 2. 
         FIGS. 4A to 4C  are views showing fabricating steps of an SOI substrate of Embodiment 3. 
         FIGS. 5A to 5C  are views showing a structure of a semiconductor device (electro-optical device) of Embodiment 4. 
         FIG. 6  is view showing a structure of a semiconductor device (semiconductor circuit) of Embodiment 5. 
         FIGS. 7A to 7F  are views showing structures of semiconductor devices (electronic equipments) of Embodiment 6. 
         FIGS. 8A to 8D  are views showing structures of semiconductor devices (electronic equipments) of Embodiment 6. 
         FIGS. 9A and 9B  are photographs showing a crystal structure of single crystal silicon of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     The gist of the present invention is to use a single crystal semiconductor substrate having a main surface of a {110} plane (crystal face is a {110} plane) as a forming material of a single crystal semiconductor layer finally formed on a supporting substrate when an SOI substrate is fabricated by using an SOI technique such as SIMOX, ELTRAN, or Smart-Cut. 
     Incidentally, although the semiconductor mentioned here typically indicates silicon, the term also includes other semiconductors such as silicon germanium. 
     The reason why a single crystal semiconductor substrate having a main surface of a {110} plane is used as a forming material of a single crystal semiconductor layer will be described below. Incidentally, this description will be made using single crystal silicon as an example. 
     As single crystal silicon, although that formed by an FZ method and that formed by a CZ method exist, in the present invention, it is preferable to use single crystal silicon formed by the FZ method. In the CZ method which is the main stream at present, oxygen of about 2×10 18  atoms/cm 3  is contained for the purpose of relieving stress, so that there is a fear that an electron or hole mobility is lowered. Particularly, in the case where a minute TFT is formed, this comes to appear remarkably. 
     However, in the case where single crystal silicon is used for the SOI substrate as in the present invention, since there are many cases where the thickness of a single crystal silicon layer required for an active layer of a TFT is as very thin as 10 to 50 nm, it is not quite necessary to take stress into consideration. Thus, even if the FZ method (oxygen content is 1×10 17  atoms/cm 3  or less), which can form single crystal silicon more inexpensively than the inexpensive CZ method, is used, satisfactory effects can be obtained. 
     In a general SOI substrate, a single crystal silicon layer is formed on a silicon oxide film. Thus, adhesion and conformity between the silicon oxide layer and the single crystal silicon layer become important. From such a viewpoint, in the SOI substrate, when the single crystal silicon layer comes in contact with the silicon oxide layer, it is ideal that the contact of the single crystal silicon layer is realized with the most stable plane. 
     The plane which is in contact with the silicon oxide layer with most stably is a {110} plane. Because, in the case of the {110} plane, the plane is in contact with the silicon oxide layer through three silicon atoms. This state will be explained with reference to photographs shown in  FIGS. 9A and 9B . 
       FIG. 9A  is a photograph of a crystal structure model showing the state where two unit lattices of single crystal silicon are placed side by side. Here, a noticeable point is a portion indicated by an arrow in the drawing. In the portion indicated by the arrow, three silicon atoms are placed side by side. Any of the three silicon atoms is contained in a plane of the {110} plane. 
     That is, when a single crystal silicon layer having a crystal face of the {110} plane is formed on an insulating layer, it is understood that the number of silicon atoms coming in contact with the insulating layer is three. 
       FIG. 9B  is a photograph showing the state of  FIG. 9A  seen in a different angle. In  FIG. 9B , although three silicon atoms exist in a portion indicated by an arrow, these are the same as the three silicon atoms indicated by the arrow in  FIG. 9A . 
     Like this, it is understood that three silicon atoms are contained in the {110} plane, and are adjacently arranged in a substantially triangular shape. That is, in such an arrangement state, the single crystal silicon layer is in contact with an insulating layer as an under layer, and forms stable contact which is realized through “surface”. This indicates that the single crystal silicon layer is in contact with the insulating layer as an under layer with very high adhesion. 
     On the other hand, in the case where the single crystal silicon comes in contact with the silicon oxide layer through another plane, for example, a {100} plane or a {111} plane, the number of silicon atoms coming in contact with the silicon oxide layer is at most two, and unstable contact is formed in which the contact is realized through “line”. 
     Further, as a great merit of using the single crystal silicon layer having the main surface of the {110} plane, it is possible to mention that a silicon surface is very flat. In the case where the main surface is the {110} plane, a cleavage plane appears lamellarly, and it is possible to form a surface with very few asperities. 
     Like this, in the present invention, first priority is given to adhesion of a single crystal silicon layer to an under layer (silicon oxide layer) in the SOI substrate, and the invention is characterized by using the single crystal silicon substrate having the crystal face of the {100} plane which has not been conventionally used. That is, the invention is characterized in that the single crystal semiconductor substrate having the main surface (crystal face) of the {110} plane is used as a material, and the SOI technique such as SIMOX, ELTRAN, or Smart-Cut is fully used, so that the SOI substrate with high reliability is formed. Incidentally, an oriental flat of the single crystal semiconductor substrate having the main surface of the {110} plane may be made a {111} plane. 
     Then such an SOI substrate is used, and a plurality of TFTs each having an active layer of a single crystal semiconductor thin film are formed on the same substrate, so that a semiconductor device having high reliability can be realized. 
     The present invention will next be described in detail with preferred embodiments described below. 
     Embodiment 1   
     In this embodiment, with reference to  FIGS. 1A to 1F  and  2 A to  2 E, a description will be made on a case where when an SOI substrate is fabricated by a Smart-Cut method. a single crystal silicon substrate having a main surface of a {110} plane is used, and a semiconductor device is fabricated by using the SOI substrate. 
     First, a single crystal silicon substrate  101  as a forming material of a single crystal silicon layer is prepared. Here, although a P-type substrate having a main surface of a crystal face of a {110} plane is used, an N-type substrate may be used. Of course, a single crystal silicon germanium substrate may be used. 
     Next, a thermal oxidation treatment is carried out, so that a silicon oxide film  102  is formed on the main surface (corresponding to an element forming surface). Although a film thickness may be suitably determined by a user, the thickness is made 10 to 500 nm (typically 20 to 50 nm). This silicon oxide film  102  functions later as a part of a buried insulating layer of an SOI substrate ( FIG. 1A ). 
     At this time, the adhesion between the single crystal silicon substrate  101  and the silicon oxide film  102  becomes very high. Because, the silicon oxide film  102  is formed on the {110} plane in this invention, so that an interface with very high conformity can be realized. Since this interface is an interface between an active layer and an under film in a final TFT, it is very advantageous that the adhesion (conformity) is high. 
     The reason why the thickness of the silicon oxide film  102  can be made as thin as 20 to 50 nm is that the crystal face of the single crystal silicon substrate  101  has the {110} plane, so that the silicon oxide film having high adhesion can be formed even though it is thin. 
     Incidentally, the {110} plane has a problem that when an oxidation reaction proceeds, undulation (asperity) of the silicon surface gradually becomes large. However, in the case where a thin silicon oxide film is provided as in this embodiment, since the amount of oxidation is small, a problem of such undulation can be eliminated to the utmost. This is an advantage that is common to all embodiments disclosed in the present specification. 
     Thus, the single crystal silicon layer formed by using this invention has a very flat surface. For example, a distance between the top and top of the undulation is 10 times or less (preferably 20 times or less) as long as a distance between adjacent atoms of the three atoms contained in the {110} plane. That is, it is about 5 nm or less (preferably 10 nm or less). 
     Next, hydrogen is added through the silicon oxide film  102  from the side of the main surface of the single crystal silicon substrate  101 . In this case, the hydrogen addition may be carried out as the form of hydrogen ions using an ion implantation method. Of course, the addition step of hydrogen may be carried out by other means. In this way, a hydrogen-containing layer  103  is formed. In this embodiment, a hydrogen ion with a dosage of 1×10 16  to 1×10 17  atom/cm 2  is added ( FIG. 1B ). 
     Since the depth where the hydrogen-containing layer is formed determines the thickness of the single crystal silicon layer later, precise control is required. In this embodiment, control of a hydrogen addition profile in the depth direction is made so that the single crystal silicon layer with a thickness of 50 nm remains between the main surface of the single crystal silicon substrate  101  and the hydrogen-containing layer  103 . 
     Since the {110} plane is a plane which has the lowest atomic density, even if hydrogen ions are added, a probability of collision with silicon atoms is lowest. That is, it is possible to suppress damage at the time of ion addition to the minimum. 
     Next, the single crystal silicon substrate  101  and a supporting substrate are bonded to each other. In this embodiment, a silicon substrate  104  is used as the supporting substrate, and a silicon oxide film  105  for bonding is provided on its surface. As the silicon substrate  104 , it is satisfactory if an inexpensive silicon substrate formed by the FZ method is prepared. Of course, it does not matter if a polycrystal silicon substrate is used. Besides, if only flatness can be assured, a highly refractory substrate such as a quartz substrate, a ceramic substrate, or a crystallized glass substrate may be used ( FIG. 1C ). 
     At this time, since a bonding interface is formed of highly hydrophilic silicon oxide films, they are adhered to each other with hydrogen bonds by reaction of moisture contained in both the surfaces. 
     Next, a heat treatment (first heat treatment) at 400 to 600° C. (typically 500° C.) is carried out. By this heat treatment, in the hydrogen-containing layer  103 , a volume change of a minute vacancy occurs, and a broken surface is produced along the hydrogen-containing layer  103 . By this, the single crystal silicon substrate  101  is split, so that the silicon oxide film  102  and a single crystal silicon layer  106  are made to remain on the supporting substrate ( FIG. 1D ). 
     Next, as a second heat treatment, a furnace annealing step is carried out in a temperature range of 1050 to 1150° C. In this step, at the bonded interface, stress relaxation of Si—O—Si bonds occurs, so that the boned interface becomes stable. That is, this becomes a step of completely bonding the single crystal silicon layer  106  to the supporting substrate. In this embodiment, this step is carried out at 1100° C. for 2 hours. 
     The bonded interface is stabilized in this way, so that a buried insulating layer  107  is defined. In  FIG. 1E , a dotted line in the buried insulating layer  107  indicates the bonded interface, and means that adhesion of the interface has become strong. 
     Next, the surface of the single crystal silicon layer  106  is flattened. For flattening, a polishing step called CMP (Chemical Mechanical Polishing) or a furnace annealing treatment at high temperature (about 900 to 1200° C.) in a reducing atmosphere may be carried out. 
     The final thickness of the single crystal silicon layer  106  may be made 10 to 200 nm (preferably 20 to 100 nm). 
     Next, the single crystal silicon layer  106  is patterned to form an island-like silicon layer  108  which becomes an active layer of a TFT. In this embodiment, although only one island-like silicon layer is shown, a plurality of layers are formed on the same substrate ( FIG. 1F ). 
     In the manner as described above, the island-like silicon layer  108  having the main surface of the {110} plane is obtained. The present invention is characterized in that the island-like silicon layer obtained in this way is used as an active layer of a TFT, and a plurality of TFTs are formed on the same substrate. 
     Next, a method of forming a TFT will be described with reference to  FIGS. 2A to 2E . First, steps up to the state of  FIG. 1F  are completed. In  FIG. 2A , although a supporting substrate  201  is actually divided into the silicon substrate  104  and the buried insulating layer  107  in  FIG. 1 , they are shown in an integrated state for simplicity. An island-like silicon layer  202  of  FIG. 2A  corresponds to the island-like silicon layer  108  of  FIG. 1F . 
     Next, a thermal oxidation step is carried out so that a silicon oxide film  203  with a thickness of 10 nm is formed on the surface of the island-like silicon layer  202 . This silicon oxide film  203  functions as a gate insulating film. After the gate insulating film  203  is formed, a polysilicon film having conductivity is formed thereon, and a gate wiring line  204  is formed by patterning ( FIG. 2A ). 
     Incidentally, in this embodiment, although the polysilicon film having N-type conductivity is used as the gate wiring line, the material is not limited to this. Particularly, for the purpose of decreasing the resistance of the gate wiring line, it is also effective to use a metal material such as tantalum, tantalum alloy, or a laminate film of tantalum and tantalum nitride. Moreover, for the purpose of obtaining the gate wiring line with further low resistance, it is also effective to use copper or copper alloy. 
     After the state of  FIG. 2A  is obtained, an impurity to give N-type conductivity or P-type conductivity is added to form an impurity region  205 . The impurity concentration at this time determines the impurity concentration of an LDD region later. In this embodiment, although arsenic with a concentration of 1×10 18  atoms/cm 3  is added, neither an impurity nor a concentration is not required to be limited to this embodiment. 
     Next, a thin silicon oxide film  206  with a thickness of about 5 to 10 nm is formed on the surface of the gate wiring line. This may be formed by using a thermal oxidation method or a plasma oxidation method. The formation of the silicon oxide film  206  has an object to make it function as an etching stopper in a next side wall forming step. 
     After the silicon oxide film  206  as an etching stopper is formed, a silicon nitride film is formed and etch back is carried out, so that a side wall  207  is formed. In this way the state of  FIG. 2B  is obtained. 
     In this embodiment, although the silicon nitride film is used as the side wall  207 , a polysilicon film or an amorphous silicon film may be used. Of course, it is needless to say that if the material of the gate wiring line is changed, room for choice of a material which can be used as the side wall is widened. 
     Next, an impurity having the same conductivity as the former step is added again. The concentration of the impurity added at this time is made higher than that at the former step. In this embodiment, arsenic is used as the impurity, and the concentration is made 1×10 21  atoms/cm 3 . However, it is not necessary to make limitation to this. By the addition step of the impurity, a source region  208 , a drain region  209 , an LDD region  210 , and a channel formation region  211  are defined ( FIG. 2C ). 
     In this way, after the respective impurity regions are formed, activation of the impurity is carried out by furnace annealing, laser annealing, lamp annealing, or the like. 
     Next, silicon oxide films formed on the surfaces of the gate wiring line  204 , the source region  208 , and the drain region  209  are removed to expose their surfaces. Then a cobalt film  212  with a thickness of about 5 nm is formed and a thermal treatment step is carried out. By this heat treatment, a reaction of cobalt and silicon occurs, so that a silicide layer (cobalt silicide layer)  213  is formed ( FIG. 2D ). 
     This technique is a well-known salicide technique. Thus, it does not matter if titanium or tungsten is used instead of cobalt, and a heat treatment condition and the like may be referred to the well-known technique. In this embodiment, the heat treatment step is carried out by using lamp annealing. 
     After the silicide layer  213  is formed in this way, the cobalt film  212  is removed. Thereafter, an interlayer insulating film  214  with a thickness of 1 μm is formed. As the interlayer insulating film  214 , a silicon oxide film, a silicon nitride film, a silicon nitride oxide film, or a resin film, such as polyamide, polyimide, acryl, etc., may be used. Alternatively, these insulating films may be laminated. 
     Next, contact holes are formed in the interlayer insulating film  214 , and a source wiring line  215  and a drain wiring line  216  made of a material containing aluminum as its main ingredient are formed. Finally, the entire component is subjected to furnace annealing at 300° C. for 2 hours in a hydrogen atmosphere, and hydrogenating is completed. 
     In this way, a TFT as shown in  FIG. 2E  is obtained. Incidentally, the structure described in this embodiment is merely an example, and a TFT structure to which the present invention can be applied is not limited to this. Thus, the invention can be applied to a TFT of any well-known structure. Besides, the step condition of this embodiment is merely an example, and a user may properly determine an optimum condition other than the essential portion of the invention. 
     Besides, in this embodiment, although the description has been made with the N-channel TFT as an example, it is also easy to fabricate a P-channel TFT. Further, it is also possible to form a CMOS circuit by forming an N-channel TFT and a P-channel TFT on the same substrate and by complementarily combining them. 
     Further, in the structure of  FIG. 2E , if a pixel electrode (not shown) electrically connected to the drain wiring line  216  is formed by well-known means, it is also easy to form a pixel switching element of an active matrix type display device. 
     That is, the invention is also a very effective technique as a method of fabricating an electro-optical device typified by a liquid crystal display device, an EL (electroluminescence) display device, an EC (electrochromic) display device, a photoelectric conversion device (optical sensor), and the like. 
     Embodiment 2   
     In this embodiment, a description will be made of an example in which an SOI substrate different from that of embodiment 1 is fabricated by using a single crystal silicon substrate having a main surface of a {110} plane, and a semiconductor device is fabricated by using the SOI substrate using  FIGS. 3A to 3F . Specifically, a case where a technique called ELTRAN is used will be described. 
     First, a single crystal silicon substrate  301  having a main surface (crystal face) of a {110} plane is prepared. Next, the main surface is subjected to anodization to form a porous silicon layer  302 . The anodization step may be carried out in a mixed solution of hydrofluoric acid and ethanol. The porous silicon layer  302  is regarded as a single crystal silicon layer provided with columnar surface holes at a surface density of about 10 11  holes/cm 3 , and succeeds to the crystal state (orientation, etc.) of the single crystal silicon substrate  301  as it is. Incidentally, since the ELTRAN method itself is well known, the detailed description will be omitted here. 
     After the porous silicon layer  302  is formed, it is preferable to carry out a heat treatment step in a reducing atmosphere and within a temperature range of 900 to 1200° C. (preferably 1000 to 1150° C.). In this embodiment, a heat treatment at 1050° C. for 2 hours is carried out in a hydrogen atmosphere. 
     As the reducing atmosphere, although a hydrogen atmosphere, an ammonia atmosphere, or an inert gas atmosphere containing hydrogen or ammonia (mixed atmosphere of hydrogen and nitrogen, or hydrogen and argon, etc.)is preferable, flattening of the surface of the crystalline silicon film can be made even in an inert gas atmosphere. However, when a reduction of a natural oxidation film is carried out by using a reducing action, many silicon atoms with high energy are generated and the flattening effect is resultantly increased. Thus, use of the reducing atmosphere is preferable. 
     However, attention needs to be especially paid to the point that the concentration of oxygen or an oxygen compound (for example, OH radical) contained in the atmosphere must be 10 ppm or less (preferably 1 ppm or less). Otherwise, the reducing reaction by hydrogen comes not to occur. 
     At this time, in the vicinity of the surface of the porous silicon layer  302 , the surface holes are filled up by movement of silicon atoms, so that a very flat silicon surface can be obtained. 
     Next, a single crystal silicon layer  303  is epitaxially grown on the porous silicon layer  302 . At this time, since the epitaxially grown single crystal silicon layer  303  reflects the crystal structure of the single crystal silicon substrate  301  as it is, its main surface becomes a {110} plane. The film thickness may be 10 to 200 nm (preferably 20 to 100 nm) ( FIG. 3A ). 
     Next, the single crystal silicon layer  303  is oxidized to form a silicon oxide layer  304 . As a forming method, it is possible to use thermal oxidation, plasma oxidation, laser oxidation, or the like. At this time, a single crystal silicon layer  305  remains ( FIG. 3B ). 
     Next, as a supporting substrate, a polycrystal silicon substrate  306  provided with a silicon oxide layer on its surface is prepared. Of course, a ceramic substrate, a quartz substrate, or a glass ceramic substrate each provided with an insulating film on its surface may be used. 
     After the preparation of the single crystal silicon substrate  301  and the supporting substrate (polycrystal silicon substrate  306 ) is completed in this way, both of the substrates are bonded to each other in such a manner that the respective main surfaces are opposite to each other. In this case, the silicon oxide layer provided on each of the substrates functions as an adhesive ( FIG. 3C ). 
     After bonding is ended, a heat treatment step at a temperature of 1050 to 1150° C. is next carried out, and the bonded interface made of both the silicon oxide layers is stabilized. In this embodiment, this heat treatment step is carried out at 1100° C. for 2 hours. Incidentally, a portion indicated by a dotted line in  FIG. 3C  is the bonded interface after adhering has been completely performed. The silicon oxide layers provided on both the substrates are integrated by the heat treatment to become a buried insulating layer  307 . 
     Next, the single crystal silicon substrate  301  is ground from the rear surface side by mechanical polishing such as CMP, and the grinding step is ended when the porous silicon layer  302  is exposed. In this way, the state shown in  FIG. 3D  is obtained. 
     Next, the porous silicon layer  302  is subjected to wet etching and is selectively removed. As an etchant to be used, a mixed solution of a hydrofluoric acid solution and a hydrogen peroxide solution is preferable. It is reported that a solution of a mixture of 49% HF and 30% H 2 O 2  at a ratio of 1:5 has a selecting ratio of a hundred thousand times or more between a single crystal silicon layer and a porous silicon layer. 
     The state shown in  FIG. 3E  is obtained in this way. In this state, the buried insulating layer  307  is provided on the polycrystal silicon substrate  306 , and a single crystal silicon layer  308  is formed thereon. 
     Although the SOI substrate is completed at this time, since minute asperities exist on the surface of the single crystal silicon layer  308 , it is desirable to carry out a heat treatment step in a hydrogen atmosphere to perform flattening. This flattening phenomenon occurs due to speed-increasing surface diffusion of silicon atoms by reduction of a natural oxidation film. 
     At this time, since there is also an effect that boron contained in the single crystal silicon layer  308  (that contained in a P-type silicon substrate) is released into a vapor phase by hydrogen atoms, the heat treatment step is also effective in decrease of impurities. 
     Next, the obtained single crystal silicon layer  308  is patterned to form an island-like silicon layer  309 . Although only one layer is shown in the drawings, it is needless to say that a plurality of island-like silicon layers may be formed. 
     Thereafter, a TFT can be fabricated in accordance with the same steps as those described in embodiment 1 with reference to  FIGS. 2A to 2E . The TFT may be formed by other well-known means. In this embodiment, the detailed description will be omitted. 
     Embodiment 3   
     In this embodiment, a description will be made on an example in which a single crystal silicon substrate having a main surface of a {110} plane is used to fabricate an SOI substrate different from that of embodiment 1 or embodiment 2, and a semiconductor device is fabricated by using the substrate using  FIGS. 4A to 4C . Specifically, a case in which an SOI substrate called SIMOX is fabricated will be described. 
     In  FIG. 4A , reference numeral  401  designates a single crystal silicon substrate. In this embodiment, an oxygen ion is first added to the single crystal silicon substrate  401  to form an oxygen-containing layer  402  at a predetermined depth. The oxygen ion with a dosage of about 1×10 18  atoms/cm 2  may be added. 
     At this time, since the {110} plane has small atomic density, a probability of collision of the oxygen ion and silicon atom becomes lower. That is, it is possible to suppress damage of the silicon surface due to the addition of oxygen to the minimum. Of course, if the substrate temperature is raised at 400 to 600° C. during the ion addition, the damage can be further decreased. 
     Next, a heat treatment at a temperature of 800 to 1200° C. is carried out, so that the oxygen-containing layer  402  is changed into a buried insulating layer  403 . The width of the oxygen-containing layer  402  in the depth direction is determined by a distribution of the oxygen ion at the ion addition, and has a distribution with a gentle tail. However, by this heat treatment, the interface between the single crystal silicon substrate  401  and the buried insulating layer  403  becomes very steep ( FIG. 4B ). 
     The thickness of this buried insulating layer  403  is 10 to 500 nm (typically 20 to 50 nm). The reason why the buried insulating layer as thin as 20 to 50 nm can be realized is that the interface between the single crystal silicon substrate  401  and the buried insulating layer  403  is stably coupled, which is the very result of the fact that the single crystal silicon substrate having the main surface of the {110} plane is used as the material of the single crystal silicon layer. 
     When the buried insulating layer  403  is formed in this way, a single crystal silicon layer  404  remains on the buried insulating layer  403 . That is, in this embodiment, since the single crystal silicon substrate having the main surface of the {110} plane is used, the main surface (crystal face) of the single crystal silicon layer  404  obtained after the buried insulating layer is formed comes to have the {110} plane as well. Incidentally, adjustment may be made so that the thickness of the single crystal silicon layer  404  becomes 10 to 200 nm (preferably 20 to 100 nm). 
     After the single crystal silicon layer  404  is obtained in this way, patterning is carried out to obtain an island-like silicon layer  405 . A plurality of island-like silicon layers may be formed. 
     Thereafter, a plurality of TFTs may be completed in accordance with the steps described in embodiment 1 using  FIGS. 2A to 2E . The TFTs may be formed by other well-known means. In this embodiment, the detailed description will be omitted. 
     Embodiment 4   
     In this embodiment, an example of a reflection type liquid crystal display device as a semiconductor device of the present invention will be shown in  FIGS. 5A to 5C . Since a fabricating method of a pixel TFT (pixel switching element) and a cell assembling step may be made by using well-known means, the detailed description will be omitted. 
     In  FIG. 5A , reference numeral  11  designates a substrate having an insulating surface,  12  designates a pixel matrix circuit,  13  designates a source driver circuit,  14  designates a gate driver circuit,  15  designates an opposite substrate,  16  designates an FPC (Flexible Printed Circuit), and  17  designates a signal processing circuit. As the signal processing circuit  17 , a circuit performing processing for which an IC has been conventionally substituted, such as a D/A converter, a γ-correction circuit, or a signal dividing circuit, can be formed. Of course, it is also possible to provide an IC chip on a glass substrate and to perform signal processing on the IC chip. 
     Further, although the description in this embodiment has been made on the liquid crystal display device as an example, it is needless to say that the present invention can be applied to an EL (electroluminescence) display device or an EC (electrochromic) display device as long as the display device is an active matrix type display device. 
     Here, an example of a circuit constituting the driver circuits  13  and  14  of  FIG. 5A  is shown in  FIG. 5B . Since a TFT portion has been described in embodiment 1, only necessary portions will be described here. 
     In  FIG. 5B , reference numerals  501  and  502  designate N-channel TFTs,  503  designates a P-channel TFT, and the TFTs  501  and  503  constitute a CMOS circuit. Reference numeral  504  designates an insulating layer made of a laminate film of a silicon nitride film/silicon oxide film/resin film, and a titanium wiring line  505  is provided thereon. The CMOS circuit and the TFT  502  are electrically connected to each other. The titanium wiring line is further covered with an insulating layer  506  made of a resin film. The two insulating films  504  and  506  also have a function as a flattening film. 
     A part of circuits constituting the pixel matrix circuit  12  of  FIG. 5A  is shown in  FIG. 5C . In  FIG. 5C , reference numeral  507  designates a pixel TFT made of a double gate structure N-channel TFT, and a drain wiring line  508  is formed to widely extend into a pixel region. 
     The insulating layer  504  is provided thereon, and the titanium wiring line  505  is provided thereon. At this time, a recess portion is formed in a part of the insulating layer  504 , and only silicon nitride and silicon oxide of the lowermost layer are made to remain. By this, auxiliary capacitance is formed between the drain wiring line  508  and the titanium wiring line  505 . 
     Besides, the titanium wiring line  505  provided in the pixel matrix circuit has an electric field shielding effect between the source/drain wiring line and a subsequent pixel electrode. Further, it also functions as a black mask at gaps between a plurality of pixel electrodes provided. 
     Then, the insulating layer  506  is provided to cover the titanium wiring line  505 , and a pixel electrode  509  made of a reflective conductive film is formed thereon. Of course, it does not matter if contrivance to raise reflectivity may be made on the surface of the pixel electrode  509 . 
     Actually, although an orientation film or a liquid crystal layer is provided on the pixel electrode  509 , the description will be omitted here. 
     The reflection type liquid crystal display device having the structure as described above can be fabricated by using the present invention. Of course, when combined with a well-known technique, it is also possible to easily fabricate a transmission type liquid crystal display device. Further, when combined with a well-known technique, it is also possible to easily fabricate an active matrix type EL display device. 
     Embodiment 5   
     The present invention can be applied to all conventional IC techniques. That is, the present invention can be applied to all semiconductor circuits presently available on the market. For example, the present invention may be applied to a microprocessor such as a RISC processor integrated on one chip or an ASIC processor, and may be applied to circuits from a signal processing circuit such as a D/A converter to a high frequency circuit for a portable equipment (portable telephone, PHS, mobile computer). 
       FIG. 6  shows an example of a microprocessor. The microprocessor is typically constituted by a CPU core  21 , a RAM  22 , a clock controller  23 , a cache memory  24 , a cache controller  25 , a serial interface  26 , an I/O port  27 , and the like. 
     Of course, the microprocessor shown in  FIG. 6  is a simplified example, and various circuit designs are made for actual microprocessors according to their use. 
     However, in any microprocessor with any function, it is an IC (Integrated Circuit)  28  that functions as a central part. The IC  28  is a functional circuit in which an integrated circuit formed on a semiconductor chip  29  is protected with ceramic or the like. 
     An N-channel TFT  30  and a P-channel TFT  31  having the structure of this invention constitute the integrated circuit formed on the semiconductor chip  29 . Note that when a basic circuit is constituted by a CMOS circuit as a minimum unit, power consumption can be suppressed. 
     Besides, the microprocessor shown in this embodiment is mounted on various electronic equipments and functions as a central circuit. As typical electronic equipments, a personal computer, a portable information terminal equipment, and other all household electric appliances can be enumerated. Besides, a computer for controlling a vehicle (automobile, electric train, etc.) can also be enumerated. 
     Embodiment 6   
     A CMOS circuit and a pixel matrix circuit formed through carrying out the present invention may be applied to various electro-optical devices (active matrix type liquid crystal display devices, active matrix type EL display devices, active matrix type EC display devices). Namely, the present invention may be embodied in all the electronic equipments that incorporate those electro-optical devices as display media. 
     As such an electronic equipment, a video camera, a digital camera, a projector (rear-type projector or front-type projector), a head mount display (goggle-type display), a navigation system for vehicles, a personal computer, and a portable information terminal (a mobile computer, a cellular phone, or an electronic book) may be enumerated. Examples of those are shown in  FIGS. 7A to 8D . 
       FIG. 7A  shows a personal computer comprising a main body  2001 , an image inputting unit  2002 , a display device  2003 , and a key board  2004 . The present invention is applicable to the image inputting unit  2002 , the display device  2003 , and other signal control circuits. 
       FIG. 7B  shows a video camera comprising a main body  2101 , a display device  2102 , a voice input unit  2103 , an operation switch  2104 , a battery  2105 , and an image receiving unit  2106 . The present invention is applicable to the display device  2102 , the voice input unit  2103 , and other signal control circuits. 
       FIG. 7C  shows a mobile computer comprising a main body  2201 , a camera unit  2202 , an image receiving unit  2203 , an operation switch  2204 , and a display device  2205 . The present invention is applicable to the display device  2205  and other signal control circuits. 
       FIG. 7D  shows a goggle-type display comprising a main body  2301 , a display device  2302  and an arm portion  2303 . The present invention is applicable to the display device  2302  and other signal control circuits. 
       FIG. 7E  shows a player that employs a recoding medium in which programs are recorded (hereinafter referred to as recording medium), and comprises a main body  2401 , a display device  2402 , a speaker unit  2403 , a recording medium  2404 , and an operation switch  2405 . Incidentally, this player uses as the recoding medium a DVD (digital versatile disc), a CD and the like to serve as a tool for enjoying music or movies, for playing games and for connecting to the Internet. The present invention is applicable to the display device  2402  and other signal control circuits. 
       FIG. 7F  shows a digital camera comprising a main body  2501 , a display device  2502 , an eye piece section  2503 , an operation switch  2504 , and an image receiving unit (not shown). The present invention is applicable to the display device  2502  and other signal control circuits. 
       FIG. 8A  shows a front-type projector comprising a display device  2601  and a screen  2602 . The present invention is applicable to the display device and other signal control circuits. 
       FIG. 8B  shows a rear-type projector comprising a main body  2701 , a display device  2702 , a mirror  2703 , and a screen  2704 . The present invention is applicable to the display device and other signal control circuits. 
       FIG. 8C  is a diagram showing an example of the structure of the display devices  2601  and  2702  in  FIGS. 8A and 8B . The display device  2601  or  2702  comprises a light source optical system  2801 , mirrors  2802  and  2805  to  2807 , dichroic mirrors  2803  and  2804 , optical lenses  2808 ,  2809  and  2811 , liquid crystal display devices  2810 , and a projection optical system  2812 . The projection optical system  2812  consists of an optical system including a projection lens. This embodiment shows an example of “three plate type” using three liquid crystal display devices  2810 , but not particularly limited thereto. For instance, the invention may be applied also to “single plate type”. Further, in the light path indicated by an arrow in  FIG. 8C , an optical system such as an optical lens, a film having a polarization function, a film for adjusting a phase difference, an IR film may be provided on discretion of a person who carries out the invention. 
       FIG. 8D  is a diagram showing an example of the structure of the light source optical system  2801  in  FIG. 8C . In this embodiment, the light source optical system  2801  comprises light sources  2813  and  2814 , synthetic prism  2815 , collimator lenses  2816  and  2820 , lens arrays  2817  and  2818 , polarizing converter element  2819 . 
     The light source optical system shown in  FIG. 8D  employs two light sources, but may employ three to four of light sources, or more. Of course, it may employ one light source. 
     Further, on discretion of a person who carries out the invention, the light source optical system may be provided with an optical system such as an optical lens, a film having a polarization function, a film for adjusting the phase difference, and an IR film. 
     As described above, the scope of application of the present invention is very wide, and the invention can be applied to electronic equipments of any fields. The electronic equipment of this embodiment can be realized even if any combination of embodiments 1 to 5 is used.