Patent Publication Number: US-2019180825-A1

Title: Memory device and operation method thereof

Description:
TECHNICAL FIELD 
     The disclosure relates in general to a memory device and an operation method thereof. 
     BACKGROUND 
     Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Common uses for flash memory include personal computers, personal digital assistants, digital cameras, and cellular telephones. 
     Read is required in various operations such as erase verify, program verify. During read operation, drain read disturb may be occurred if the drain side voltage is too high. Drain read disturb is an intrinsic reliability concern. Read operation is typically executed at low operation voltage, such as 1V. The cell disturb induced by low drain bias is expected to be small. As flash cell continues to scale down and the read window continues to narrow, drain read window is becoming a critical element for the memory array design. 
     Thus, setting an appropriate drain voltage is essential to sustain the product functionality and reliability. The application provide a memory device and an operation method thereof to improve drain read disturb. 
     SUMMARY 
     According to one embodiment, a memory device is provided. The memory device includes: a memory array having a plurality of cells; a regulator, coupled to the memory, the regulator being configured to provide a bit line voltage to a selected cell of the memory array and to provide a bias voltage; and a controllable current source, coupled to the memory array, the controllable current source being configured to conduct a controllable current in the controllable current source until a cell current of the selected cell reaches a threshold. 
     According to another embodiment, an operation method for a memory device is provided. The operation method includes: providing a bit line voltage to a selected cell of the memory device; conducting a controllable current in the memory device to maintain the bit line voltage and shutting down the controllable current when a cell current of the selected cell reaches a threshold. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a functional block diagram for a memory device according to one embodiment of the application. 
         FIG. 2  shows a circuit diagram for a memory device according to one embodiment of the application. 
         FIGS. 3A and 3B  shows overshoot of the bit line voltage without and with applying the embodiment of the application. 
     
    
    
     In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the disclosed embodiments. It will be apparent, however, that one or more embodiments may be practiced without these specific details. In other instances, well-known structures and devices are schematically shown in order to simplify the drawing. 
     DESCRIPTION OF THE EMBODIMENTS 
     Technical terms of the disclosure are based on general definition in the technical field of the disclosure. If the disclosure describes or explains one or some terms, definition of the terms is based on the description or explanation of the disclosure. Each of the disclosed embodiments has one or more technical features. However, it does not mean that implementation of the disclosure needs every technical feature of any embodiment of the disclosure or combination of the embodiments of the disclosure is prohibited. In other words, in possible implementation, one skilled person in the art would selectively implement part or all technical features of any embodiment of the disclosure or selectively combine part or all technical features of the embodiments of the disclosure. 
       FIG. 1  shows a functional block diagram for a memory device according to one embodiment of the application. The memory device  100  according to one embodiment of the application includes a memory array  110 , a regulator  120 , a control circuit  130  and a controllable current source  140 . 
     The memory array  110  is coupled to the regulator  120  and the controllable current source  140 . The memory array  110  may be a reference cell array having a plurality of reference cells and/or a data cell array having a plurality of data cells. Also, the memory array  110  includes a plurality of word lines and a plurality of bit lines. The cells are on the intersections of the word lines and the bit lines. 
     The regulator  120  is configured for regulating a voltage applied cross a load so as to make the applied voltage insensitive against changes in the current drawn by the load. An ideal voltage regulator delivers a voltage that does not depend on the resistance of the load. The regulator  120  is coupled to the control circuit  130  and the memory array  110 . The regulator  120  is configured to provide a drain side voltage (i.e. a bit line voltage) to a selected cell of the memory array  110 . Also, the regulator  120  is configured to provide a bias voltage to the control circuit  130 . 
     The control circuit  130  is coupled to the regulator  120  and the controllable current source  140  for controlling the controllable current source  140 . Also, the control circuit  130  may maintain the drain side voltage of the selected cell of the memory array  110 . 
     The controllable current source  140  is coupled to the memory array  110  and the control circuit  130 . The controllable current source  140  is used to conduct a controllable current in the controllable current source  140  until a cell current of the selected cell reaches a threshold. Also, the control circuit  130  and the controllable current source  140  are configured to maintain the bit line voltage of the selected cell of the memory array via conduction of the controllable current in the controllable current source. 
       FIG. 2  shows a circuit diagram for a memory device according to one embodiment of the application.  FIG. 2  shows one cell MC in the memory array  110  and the number of the cells is for description purpose only, not for limiting the invention. The regulator  120  of the memory device  100  includes a reference voltage generator  210 , operation amplifiers OPAMP 0  and OPAMP 1 , PMOS transistors MP 0 , MP 1 , NMOS transistors MN 0 , MN 1 , MN 2 , and resistors R 1 , R 2 , R 3 , R 4  and R 5 . The control circuit  130  of the memory device  100  includes PMOS transistors MP 2  and MP 3  and a NMOS transistor MN 3 . The controllable current source  140  of the memory device  100  includes a PMOS transistor MP 4 . 
     In the regulator  120  of the memory device  100 , the reference voltage generator  210 , for example but not limited by, a bandgap circuit, may generate a reference voltage REF which is resistive to process, voltage and temperature variations. The reference voltage generator  210  provides the reference voltage REF (for example but not limited by 1 V), to the operation amplifier OPAMP 0 . 
     The operation amplifier OPAMP 0  receives the reference voltage REF from the reference voltage generator  210 . Further, the input terminal of the operation amplifier OPAMP 0  is coupled to the node N 1  between the resistors R 3  and R 4 . The operation amplifier OPAMP 0  has an output terminal coupled to the gates of the PMOS transistors MP 0  and MP 1 . 
     The operation amplifier OPAMP 1  receives a bias voltage BGBUF. Further, the input terminal of the operation amplifier OPAMP 1  is coupled to the node N 2  between the resistor R 5  and the NMOS transistor MN 1 . The operation amplifier OPAMP 1  has an output terminal for providing a bias voltage VBLR to the gates of the NMOS transistors MN 1  and MN 2 . 
     The PMOS transistor MP 0  has a gate coupled to the output of the operation amplifier OPAMP 0 , a source coupled to VDD and a drain coupled to the resistor R 1 . The PMOS transistor MP 1  has a gate coupled to the output of the operation amplifier OPAMP 0 , a source coupled to VDD and a drain coupled to the drain of the NMOS transistor MN 0 . The PMOS transistor MP 1  provides a bias NBIAS at the drain. The PMOS transistors MP 0  and MP 1  act as a current mirror. 
     The NMOS transistor MN 0  is diode-connected. The NMOS transistor MN 0  has a gate and a drain coupled to the bias voltage NBIAS and a source coupled to ground GND. The NMOS transistors MN 0  and MN 3  also act as a current mirror. 
     The NMOS transistor MN 1  has a gate coupled to the output VBLR of the operation amplifier OPAMP 1 , a drain coupled to VDD and a source coupled to the node N 2  which is coupled to the input terminal of the operation amplifier OPAMP 1 . 
     The NMOS transistor MN 2  has a gate coupled to the output of the operation amplifier OPAMP 1 , a drain coupled to the drain of the PMOS transistor MP 2  and a source for providing a bit line voltage RGBL. 
     The resistors R 1 , R 2 , R 3  and R 4  are series connected between the drain of the PMOS transistor MP 0  and ground GND. The resistor R 5  is connected between the node N 2  and ground GND. 
     Via the operation amplifier OPAMP 0 , the node voltage FB of the node N 1  is equal to the reference voltage REF (i.e. FB=REF). Thus, the current I 1  flows through the resistors R 1 , R 2 , R 3  and R 4  would be I 1 =(REF/R 4 ). Via voltage division, the voltage BGBUF would be BGBUF=REF*(R 2 +R 3 +R 4 )/R 4 , which is for example but not limited by 0.88V. The PMOS transistors MP 0  and MP 1  act as a current mirror, and thus the current I 2  flowing into the NMOS transistor MN 0  is equal to I 2 =I 1 =REF/R 4 . Thus, the currents I 1  and I 2  are stable current sources. 
     Via the operation amplifier OPAMP 1 , the node voltage of the node N 2  is equal to the voltage BGBUF, and thus the output voltage VBLR of the operation amplifier OPAMP 1  is about equal to VBLR≈BGBUF+Vth, which is for example 0.88V+Vth (Vth is the threshold of the NMOS transistor MN 1 ). Current flow into the resistor R 5  is trimmed to equal to normal cell current (ex: 16 μA). The NMOS transistors MN 1  and MN 2  act as replica bias. As for the NMOS transistor MN 2 , the bit line voltage RGBL is the source voltage of the NMOS transistor MN 2 , and thus the bit line voltage RGBL is equal to the gate voltage (i.e. VBLR) minus the threshold voltage. Therefore, the bit line voltage RGBL is equal to around RGBL≈VBLR−Vth≈(BGBUF+Vth)−Vth≈BGBUF, which is for example 0.88V. 
     Thus, from the above description, in the embodiment of the application, the regulator  120  provides the bit line voltage RGBL to the selected cell MC of the memory array  110  and provides the bias voltage NBIAS to the control circuit  130 . 
     In the control circuit  130  of the memory device  100 , the NMOS transistor MN 3  of the control circuit  130  and the NMOS transistor MN 0  of the regulator  120  also act as a current mirror. Thus, the current I 3  flows through the NMOS transistor MN 3  is the same as the current flowing through the NMOS transistor MN 0 , i.e. I 3 =I 2 . In one possible example, the normal current I 3  flows into the NMOS transistor MN 3  is around 5 μA. 
     The PMOS transistors MP 2  and MP 3  act as a current mirror. Also, the current flows through the PMOS transistor MP 2  is equal to the current flowing through the PMOS transistor MP 3  and the NMOS transistor MN 3 . 
     In general, if the memory array  110  has large circuit size (i.e. a lot of word lines, a lot of bit lines and a lot of cells), then during setup procedure, the word line voltage (RWL in  FIG. 2 ), which is a high voltage, will have a slow setup speed. That is to say, when the corresponding cell is selected for reading, transition of the corresponding word line voltage RWL from low logic to high logic will be slow, but transition of the corresponding bit line voltage RGBL from low logic to high logic is fast (because the bit line voltage RGBL is not a high voltage). However, if the bit line voltage RGBL is not maintained, then a read disturbance will be likely to occur due to overshoot of RGBL. 
     Thus, in the application, when the cell current flowing through the selected cell MC of the memory array  110  is gradually increased, the bit line voltage RGBL is gradually pulled down. Thus, the current I 4  is also lowered (thus the node voltage at the node N 3  will be gradually pulled up) but the current I 3  is substantially fixed. When the cell current of the selected cell MC substantially reaches or is substantially close to the current I 3  (the value of the current I 3  may be also referred as a threshold), the node voltage at the node N 3  will be raised high enough to shut down the PMOS transistor MP 4  of the controllable current source  140  (i.e. the PMOS transistor MP 4  of the controllable current source  140  will be shut down by the control circuit  130 ). That is to say, the timing to shut down the PMOS transistor MP 4  of the controllable current source  140  may be related to the value of the current I 3 , i.e. the timing to shut down the PMOS transistor MP 4  of the controllable current source  140  may be adjusted by adjusting the bias NBIAS provided to the gate of the NMOS transistor MN 3 . 
     In more detail, at initial transition of the corresponding word line voltage RWL from low logic to high logic, the selected cell MC is not turned on yet (because the word line voltage RWL is not high enough) and thus there is no cell current flowing through the selected cell MC. Thus, because the bias voltage NBIAS provided from the regulator  110  turns on the NMOS transistor MN 3 , the current I 3  flowing through the NMOS transistor MN 3  and the PMOS transistor MP 3  will be mirrored by the PMOS transistor MP 2 . Therefore, the current I 4  flowing through the PMOS transistor MP 4  is the same as the current flowing through the PMOS transistor MP 2  (i.e. I 4 =I 3 ) because there is no cell current (i.e. the current flowing through the PMOS transistor MP 2  totally flows into the PMOS transistor MP 4 ). By this, the node voltage at the node N 3  (i.e. the gate voltage of the PMOS transistor MP 4 ) and the bit line voltage RGBL are maintained. 
     Then, during the word line voltage RWL is slightly raised and before the selected cell MC is completed turned on, the selected cell is slightly turned on and thus a slight cell current flows through the selected cell MC (i.e. the cell current flowing through the selected cell MC of the memory array  110  is gradually increased). Therefore, the bit line voltage RGBL is gradually lowered. Also, the current flowing through the transistor MP 4  (i.e. I 4 ) is also lowered but the current I 3  is substantially fixed, and accordingly, the node voltage at the node N 3  (which is also the gate voltage of the PMOS transistor MP 4 ) is slightly raised (but the gate voltage of the PMOS transistor MP 4  is not enough to turn off the PMOS transistor MP 4 ). 
     When the cell current of the selected cell MC substantially reaches or is substantially close to the current I 3 , the node voltage N 3  (which is the gate voltage of the PMOS transistor MP 4 ) is high enough to turn off the PMOS transistor MP 4 . That is to say, the timing to shut down the PMOS transistor MP 4  of the controllable current source  140  may be related to the value of the current I 3 , i.e. the timing to shut down the PMOS transistor MP 4  of the controllable current source  140  may be adjusted by adjusting the bias NBIAS provided to the gate of the NMOS transistor MN 3 . In other words, in the memory device  100 , the controllable current source  140  is shut down by the control circuit  130 . 
     Thus, in the embodiment of the application, the transistors MP 3 , MP 4  and MN 3  may be used to reduce the overshoot of the bit line voltage RGBL during the word line voltage RWL slowly ramps up via conduction of the current I 4  flowing through the PMOS transistor MP 4 . In other words, because a part of the current flowing through the NMOS transistor MN 2  is drawn by the PMOS transistor MP 4 , overshoot on the bit line voltage RGBL is reduced. 
       FIGS. 3A and 3B  shows overshoot of the bit line voltage RGBL when without and with the transistors MP 3 , MP 4  and MN 3 , respectively (if the bit line voltage RGBL is around 0.88V). As shown in  FIG. 3A  and  FIG. 3B , when the voltage VBLR is transited from low logic to high logic, the bit line voltage RGBL and the word line voltage RWL are also transited from low logic to high logic, but the bit line voltage RGBL is transited faster than the word line voltage RWL. 
     As shown in  FIG. 3A , without the transistors MP 3 , MP 4  and MN 3 , the overshoot of the bit line voltage RGBL may be 1.2V during the word line voltage RWL slowly ramps up. On the contrary, as shown in  FIG. 3B , with the transistors MP 3 , MP 4  and MN 3 , the overshoot of the bit line voltage RGBL may be reduced from 1.2V to 0.93V during the word line voltage RWL slowly ramps up. 
     Thus, in the embodiment of the application, the overshoot of the bit line voltage RGBL during the word line voltage RWL slowly ramps up is reduced via the control circuit  130  and the controllable current source  140 . 
     Thus, the read disturbance will be also improved. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed embodiments. It is intended that the specification and examples be considered as exemplary only, with a true scope of the disclosure being indicated by the following claims and their equivalents.