Patent Publication Number: US-2022231027-A1

Title: Semiconductor memory devices having contact plugs

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 16/993,394, filed Aug. 14, 2020, which claims the benefit of priority under 35 U.S.C. § 119 of Korean Patent Application No. 10-2019-0170203, filed on Dec. 18, 2019, in the Korean Intellectual Property Office, the entire disclosures of both of which are incorporated herein by reference. 
    
    
     BACKGROUND 
     The inventive concept relates to semiconductor memory devices, and more particularly, to a semiconductor memory device having contact plugs. 
     With rapid developments in the electronic industry and demands of users, electronic devices are becoming more compact and lighter. Accordingly, semiconductor memory devices used in electronic devices are typically needed to have a high degree of integration, and thus design rules for the components of semiconductor memory devices have been decreased. Therefore, it is difficult to secure the reliability of electrical connection between the components of semiconductor memory devices. 
     SUMMARY 
     The inventive concept provides a semiconductor memory device having contact plugs capable of providing a reliable electrical connection. 
     According to an aspect of the inventive concept, there is provided a semiconductor memory device. A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined, and a peripheral circuit region where at least one logic active region is defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug, wherein a lateral surface of the word line contact plug between a top surface and a bottom surface of the upper word line layer is entirely surrounded by the upper word line layer. 
     A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined, and a peripheral circuit region where at least one logic active region is defined; a word line having a stack structure of a lower word line layer and an upper word line layer and extending over the plurality of active regions in a first horizontal direction, and a buried insulation layer on the word line; a bit line structure arranged on the plurality of active regions, extending in a second horizontal direction perpendicular to the first horizontal direction, and having a bit line; and a word line contact plug electrically connected to the lower word line layer by penetrating the buried insulation layer and the upper word line layer and having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug, wherein a lateral surface of the word line contact plug between a top surface and a bottom surface of the upper word line layer is entirely surrounded by the upper word line layer. 
     A semiconductor memory device includes a substrate having a memory cell region where a plurality of active regions are defined, and a peripheral circuit region where at least one logic active region is defined; a plurality of word lines that fill a plurality of word line trenches each extending in a first horizontal direction over the plurality of active regions to be parallel to each other and each have a stack structure of a lower word line layer and an upper word line layer, and a plurality of buried insulation layers on the plurality of word lines; a plurality of bit line structures arranged on the plurality of active regions, each extending in a second horizontal direction perpendicular to the first horizontal direction to be parallel to each other, and each having a bit line and an insulation capping line covering the bit line; a filling insulation layer that fills a space between the plurality of bit line structures; a word line contact plug having a plug extension in an upper portion of the word line contact plug, the plug extension having a greater horizontal width than a lower portion of the word line contact plug, being connected to the lower word line layer by penetrating the filling insulation layer, the buried insulation layer, and the upper word line layer, and having a lateral surface at a level between a top surface and a bottom surface of the upper word line layer that is entirely covered by the upper word line layer; a plurality of buried contacts that fills a lower portion of a space between the plurality of bit line structures and is connected to the plurality of active regions; and a plurality of landing pads filling an upper portion of the space between the plurality of bit line structures, extending over the plurality of bit line structures, and including the same material as a material included in the word line contact plug. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Exemplary embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which like numbers refer to like elements throughout. In the drawings: 
         FIG. 1  is a schematic planar layout for explaining main components of a semiconductor memory device, according to example embodiments of the inventive concept; 
         FIGS. 2A to 2G, 3A to 3G, 4A to 4G, 5A to 5G, 6A to 6G, 7A to 7G, 8A to 8G, and 9A to 9G  are cross-sectional views showing stages in a method of manufacturing a semiconductor memory device, according to example embodiments of the inventive concept; 
         FIGS. 10A to 10G  are cross-sectional views illustrating a semiconductor memory device in stages, according to example embodiments of the inventive concept; and 
         FIG. 11  is a cross-sectional view for comparing the cross-sections of contact plugs of semiconductor memory devices, according to example embodiments of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
       FIG. 1  is a schematic planar layout for explaining main components of a semiconductor memory device, according to example embodiments of the inventive concept. 
     Referring to  FIG. 1 , a semiconductor memory device  1  may include a memory cell region CR and a peripheral circuit region PR. The semiconductor memory device  1  may include a plurality of active regions ACT in the memory cell region CR, and a plurality of logic active regions ACTP in the peripheral circuit region PR. 
     According to some embodiments, the plurality of active regions ACT in the memory cell region CR may be arranged to have a long axis in a diagonal direction to a first horizontal direction (X direction) and a second horizontal direction (Y direction). 
     A plurality of word lines WL may each extend lengthwise in the X direction across the plurality of active regions ACT to be parallel to each other in the memory cell region CR. A plurality of bit lines BL may each extend lengthwise above the plurality of word lines WL in the second horizontal direction (Y direction) intersecting the first horizontal direction (X direction) to be parallel to each other. The plurality of bit lines BL may be connected to the plurality of active regions ACT via direct contacts DC. 
     According to some embodiments, a plurality of buried contacts BC may be formed between two adjacent bit lines BL adjacent to each other among the plurality of bit lines BL. According to some embodiments, the plurality of buried contacts BC may be arranged in lines in the first horizontal direction (X direction) and the second horizontal direction (Y direction). 
     A plurality of landing pads LP may be formed on the plurality of buried contacts BC. The plurality of landing pads LP may be arranged to at least partially overlap the plurality of buried contacts BC in the vertical direction (Z direction). In some embodiments, each of the plurality of landing pads LP may extend to above one of two bit lines BL adjacent thereto. 
     A plurality of storage nodes SN may be formed above the plurality of landing pads LP. The plurality of storage nodes SN may be formed above the plurality of bit lines BL. The plurality of storage nodes SN may be respective lower electrodes of a plurality of capacitors, respectively. The plurality of storage nodes SN may be connected to the plurality of active regions ACT through the plurality of landing pads LP and the plurality of buried contacts BC. 
     A plurality of gate line patterns GLP may be arranged on the plurality of logic active regions ACTP in the peripheral circuit region PR. According to some embodiments, some of the plurality of gate line patterns GLP may each extend lengthwise in the first horizontal direction (X direction) on logic active regions ACTP to be parallel with each other, and the remaining ones of the plurality of gate line patterns GLP may each extend lengthwise in the second horizontal direction (Y direction) on the logic active region ACTP to be parallel with each other. However, embodiments are not limited thereto. For example, each of the plurality of gate line patterns GLP may have various widths or may have a curve or may extend in various horizontal directions with a variable width. 
     For convenience of illustration, other components than the plurality of logic active regions ACTP and the plurality of gate line patterns GLP are omitted from the peripheral circuit region PR. Although the plurality of gate line patterns GLP are arranged only on the plurality of logic active regions ACTP in  FIG. 1 , embodiments are not limited thereto. For example, at least some of the plurality of gate line patterns GLP may extend to outside of the logic active regions ACTP, namely, to over a logic device isolation layer  115  of  FIGS. 2E through 2G . 
     The plurality of gate line patterns GLP may be formed at the same level as the plurality of bit lines BL. According to some embodiments, the plurality of gate line patterns GLP and the plurality of bit lines BL may include the same materials or at least partially include the same materials. For example, a process of forming the whole or a portion of the plurality of gate line patterns GLP may be the same as the whole or a portion of a process of forming the plurality of bit lines BL. 
       FIGS. 2A to 2G, 3A to 3G, 4A to 4G, 5A to 5G, 6A to 6G, 7A to 7G, 8A to 8G, and 9A to 9G  are cross-sectional views showing stages in a method of manufacturing a semiconductor memory device, according to example embodiments of the inventive concept, and  FIGS. 10A to 10G  are cross-sectional views illustrating a semiconductor memory device in stages, according to example embodiments of the inventive concept.  FIGS. 2A, 3A, 4A, 5A, 6A, 7A, 8A, 9A, and 10A  are cross-sectional views of the stages taken along line A-A′ in  FIG. 1 ;  FIGS. 2B, 3B, 4B, 5B, 6B, 7B, 8B, 9B, and 10B  are cross-sectional views of the stages taken along line B-B′ in  FIG. 1 ;  FIGS. 2C, 3C, 4C, 5C, 6C, 7C, 8C, 9C, and 10C  are cross-sectional views of the stages taken along line C-C′ in  FIG. 1 ;  FIGS. 2D, 3D, 4D, 5D, 6D, 7D, 8D, 9D , and  10 D are cross-sectional views of the stages taken along line D-D′ in  FIG. 1 ;  FIGS. 2E, 3E, 4E, 5E, 6E, 7E, 8E, 9E, and 10E  are cross-sectional views of the stages taken along line E-E′ in  FIG. 1 ;  FIGS. 2F, 3F, 4F, 5F, 6F, 7F, 8F, 9F, and 10F  are cross-sectional views of the stages taken along line F-F′ in  FIG. 1 ; and  FIGS. 2G, 3G, 4G, 5G, 6G, 7G, 8G, 9G, and 10G  are cross-sectional views of the stages taken along line G-G′ in  FIG. 1 . 
     Referring to  FIGS. 2A through 2G , a device isolation trench  116 T and a logic device isolation trench  115 T may be formed in a substrate  110 , and a device isolation layer  116  filling the device isolation trench  116 T and a logic device isolation layer  115  filling the logic device isolation trench  115 T may be formed. Top surfaces of the substrate  110 , the device isolation layer  116 , and the logic device isolation layer  115  may be at the same vertical level. 
     For example, the substrate  110  may include silicon (Si), e.g., crystalline Si, polycrystalline Si, or amorphous Si. Alternatively, the substrate  110  may include a semiconductor element, such as, germanium (Ge), or at least one compound semiconductor selected from silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). The substrate  110  may have a silicon-on-insulator (SOI) structure. For example, the substrate  110  may include a buried oxide (BOX) layer. The substrate  110  may include a conductive region, for example, an impurity-doped well or an impurity-doped structure. 
     The device isolation layer  116  and the logic device isolation layer  115  may include a material including, for example, at least one selected from a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The device isolation layer  116  may be a single layer including one type of insulation layer, a dual layer including two types of insulation layers, or a multi-layer including at least three types of insulation layers. For example, the device isolation layer  116  may be a dual layer or multi-layer including an oxide layer and a nitride layer. However, embodiments of the inventive concept are not limited to the above-described structure of the device isolation layer  116 . A plurality of active regions  118  may be defined by the device isolation layer  116  in the memory cell region CR (see active regions ACT of  FIG. 1 ) of the substrate  110 , and a plurality of logic active regions  117  may be defined by the logic device isolation layer  115  in the peripheral circuit region PR (see logic active regions ACTP of  FIG. 1 ) of the substrate  110 . 
     In this specification, a portion of the substrate  110  where the plurality of active regions  118  are arranged and an adjacent portion thereof are referred to as the cell region CR, and a portion of the substrate  110  where the plurality of logic active regions  117  are arranged and an adjacent portion thereof are referred to as the peripheral circuit region PR. 
     According to some embodiments, the device isolation layer  116  and the logic device isolation layer  115  may be formed together and both may be referred to as a device isolation structure. For example, the device isolation layer  116  and the logic device isolation layer  115  may be formed at the same time in the same process and of the same material. The device isolation layer  116  may be a portion of the device isolation structure that defines the plurality of active regions  118 , and the logic device isolation layer  115  may be a portion of the device isolation structure that defines the plurality of logic active regions  117 . A portion of the device isolation structure that is located at a boundary between the cell region CR and the peripheral circuit region PR may be the device isolation layer  116  or may be the logic device isolation layer  115 . The device isolation layer  116  and the logic device isolation layer  115  may not be clearly distinguished from each other at the boundary between the cell region CR and the peripheral circuit region PR. 
     Like the active regions ACT in  FIG. 1 , each of the active regions  118  may have a relatively long island shape having a short axis and a long axis according to a planar view. Like the logic active regions ACTP in  FIG. 1 , each of the logic active regions  117  may have a rectangular shape according to a planar view. However, embodiments are not limited thereto, and each of the logic active regions  117  may have any of various other planar shapes 
     A plurality of word line trenches  120 T may be formed in the substrate  110 . A plurality of word line trenches  120 T may have line shapes, which extend lengthwise in the first horizontal direction (X direction) to be parallel with one another and are arranged at equal intervals across the active regions  118  in the second horizontal direction (Y direction). According to some embodiments, there may be a step on the bottom surface of the plurality of word line trenches  120 T. For example, a height in the vertical direction (Z direction) of each of the plurality of word line trenches  120 T may vary along the first horizontal direction (X direction). According to some embodiments, to form the plurality of word line trenches  120 T each having a step at a bottom surface thereof, the device isolation layer  116  and the substrate  110  may be respectively etched by separate etching processes, and thus have different etch depths. For example, an etch depth of the substrate  110  may be greater than an etch depth of the device isolation layer  116 , such that a depth of each of the plurality of word line trenches  120 T may be at a higher vertical level over the substrate  110  and at a lower vertical level over the device isolation layer  116 . According to some embodiments, to form the plurality of word line trenches  120 T each having a step at a bottom surface thereof, the device isolation layer  116  and the substrate  110  may be etched simultaneously but have different etch depths due to a difference between the respective etch rates of the device isolation layer  116  and the substrate  110 . 
     After a resultant structure in which the plurality of word line trenches  120 T are formed is cleaned, a plurality of gate dielectric layers  122 , a plurality of word lines  120 , and a plurality of buried insulation layers  124  may be formed in this stated order within the plurality of word line trenches  120 T. The plurality of word lines  120  may constitute the plurality of word lines WL of  FIG. 1 . The plurality of word lines  120  may have line shapes, which extend lengthwise in the first horizontal direction (X direction) to be parallel with one another and are arranged at equal intervals across the active regions  118  in the second horizontal direction (Y direction). The top surfaces of the plurality of word lines  120  may be at a lower level than the top surface of the substrate  110 . The bottom surfaces of the plurality of word lines  120  may have irregular shapes, and a transistor having a saddle fin structure, e.g., a saddle fin field effect transistor (FinFET), may be formed in the plurality of active regions  118 . 
     In this specification, the term “level” refers to a height from the main surface or the top surface of the substrate  110  in the vertical direction (Z direction). For example, “being at the same level” or “being at a certain level” refers to “having the same height from the main or top surface of the substrate  110  in the vertical direction (Z direction)” or “being at a certain position with respect to the main or top surface of the substrate  110  in the vertical direction (Z direction)”, and “being at a lower/higher level” refers to “being at a lower/higher position with respect to the main or top surface of the substrate  110  in the vertical direction (Z direction)”. 
     Each of the plurality of word lines  120  may be a stack including a lower word line layer  120   a  and an upper word line layer  120   b . For example, the lower word line layer  120   a  may be formed of a metal material, a conductive metal nitride, or a combination thereof. According to some embodiments, the lower word line layer  120   a  may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or a combination thereof. For example, the upper word line layer  120   b  may include doped polysilicon. A lower surface of the upper word line layer  120   b  may contact an upper surface of the lower word line layer  120   a . According to some embodiments, the lower word line layer  120   a  may include a core layer, and a barrier layer arranged between the core layer and a gate dielectric layer  122 . For example, the core layer may include a metal material or conductive metal nitride, such as W, WN, TiSiN, or WSiN, and the barrier layer may include a metal material or conductive metal nitride, such as Ti, TiN, Ta, or TaN. As used herein, when an element is referred to as “contacting” or “in contact with” another element, there are no intervening elements present at the point of contact. 
     According to some embodiments, before or after the plurality of word lines  120  are formed, impurity ions may be injected into the active regions  118  of the substrate  110  on both sides of each of the plurality of word lines  120 , thereby forming source regions and drain regions within the plurality of active regions ACT. 
     Each of the plurality of gate dielectric layers  122  may be formed of at least one selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, oxide/nitride/oxide (ONO), or a high-k dielectric film having a higher dielectric constant than a silicon oxide layer. For example, each of the plurality of gate dielectric layers  122  may have a dielectric constant of about 10 to about 25. According to some embodiments, the plurality of gate dielectric layers  122  may be formed of at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). For example, the plurality of gate dielectric layers  122  may be formed of HfO 2 , Al 2 O 3 , HfAlO 3 , Ta 2 O 3 , or TiO 2 . 
     The top surfaces of the plurality of buried insulation layers  124  may be substantially at the same level as the top surface of the substrate  110 . Each of the plurality of buried insulation layers  124  may include at least one material layer selected from a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and a combination thereof. A bottom surface of each of the plurality of buried insulation layers  124  may contact top surfaces of corresponding ones of the plurality of word lines  120 . 
     Referring to  FIGS. 3A through 3G , an insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) is formed to cover the device isolation layer  116 , the plurality of active regions  118 , the plurality of buried insulation layers  124 , the logic device isolation layer  115 , and the plurality of logic active regions  117 . For example, the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a metal dielectric layer, or a combination thereof. According to some embodiments, the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) may be formed by stacking a plurality of insulation layers including the first insulation layer pattern  112  and the second insulation layer pattern  114 . According to some embodiments, the first insulation layer pattern  112  may include a silicon oxide layer, and the second insulation layer pattern  114  may include a silicon nitride layer. 
     According to some embodiments, the first insulation layer pattern  112  may include a nonmetal dielectric layer, and the second insulation layer pattern  114  may include a metal dielectric layer. For example, the first insulation layer pattern  112  may include a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, or a combination thereof. For example, the second insulation layer pattern  114  may include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). 
     Thereafter, a plurality of direct contact holes  134 H are formed to penetrate the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) and expose a source region in a corresponding active region  118 . According to some embodiments, the direct contact holes  134 H may extend inside the corresponding active region  118 , i.e., the source region. For example, each direct contact hole  134 H may extend to a level lower than that of the top surfaces of the corresponding active regions  118  and device isolation layers  116 . 
     Referring to  FIGS. 4A through 4G , a direct contact conductive layer is formed on the plurality of active regions  118  and the device isolation layer  116  to fill the direct contact holes  134 H and cover the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ). The direct contact conductive layer may include, for example, Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or a combination thereof. According to some embodiments, the direct contact conductive layer may include an epitaxial silicon layer. According to some embodiments, the direct contact conductive layer may include doped polysilicon. 
     Thereafter, a metal conductive layer and an insulation capping layer, which are for forming bit line structures  140 , are sequentially formed to cover the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) and the direct contact conductive layer. 
     According to some embodiments, the metal conductive layer may have a stack structure in which a first metal conductive layer and a second metal conductive layer are stacked. The metal conductive layer may have a conductive layer stack structure having a double-layer structure, but this is just an example and embodiments are not limited thereto. For example, the metal conductive layer may include a single layer or a stack structure including at least three layers. 
     The first metal conductive layer, the second metal conductive layer, and the insulation capping layer are etched, thereby forming a plurality of bit lines  147  each including a first metal conductive pattern  145  and a second metal conductive pattern  146 , which have a line shape, and a plurality of insulation capping lines  148 . 
     According to some embodiments, the first metal conductive pattern  145  may include a TiN or Ti—Si—N (TSN), and the second metal conductive pattern  146  may include tungsten (W) or W and tungsten silicide (WSix). According to some embodiments, the first metal conductive pattern  145  may function as a diffusion barrier. According to some embodiments, the plurality of insulation capping lines  148  may include a silicon nitride layer. 
     One bit line  147  and one insulation capping line  148  covering the bit line  147  may constitute one bit line structure  140 . A plurality of bit line structures  140  including a plurality of bit lines  147  and a plurality of insulation capping lines  148  may each extend lengthwise in the second horizontal direction (Y direction) parallel to the main surface of the substrate  110  to be parallel with each other. The plurality of bit lines  147  may constitute the plurality of bit lines BL of  FIG. 1 . According to some embodiments, each of the plurality of bit line structures  140  may further include a conductive semiconductor pattern  132  between the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) and the first metal conductive pattern  145 . The conductive semiconductor pattern  132  may include doped polysilicon. According to some embodiments, the conductive semiconductor pattern  132  may be omitted. 
     During an etching process of forming the plurality of bit lines  147 , portions of the direct contact conductive layer that do not vertically overlap the plurality of bit lines  147  may also be etched, thereby forming a plurality of direct contact conductive patterns  134 . At this time, the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) may function as an etch stop layer during the etching process of forming the plurality of bit lines  147  and the plurality of direct contact conductive patterns  134 . The plurality of direct contact conductive patterns  134  may constitute the plurality of direct contacts DC of  FIG. 1 . The plurality of bit lines  147  may be electrically connected to the plurality of active regions  118  via plurality of direct contact conductive patterns  134 . 
     According to some embodiments, the conductive semiconductor patterns  132  may also be formed during a process of removing the portions of the direct contact conductive layer to form the direct contact conductive patterns  134 . For example, the conductive semiconductor patterns  132  may be portions of the direct contact conductive layer that vertically overlap the bit lines  147  but do not vertically overlap the direct contact holes  134 H and are located on the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ), and the direct contact conductive patterns  134  may be portions of the direct contact conductive layer that vertically overlap the direct contact holes  134 H and are in contact with active regions  118 . 
     An insulation spacer structure  150  may cover both sidewalls of each of the plurality of bit line structures  140 . Each of the plurality of insulation spacer structures  150  may include a first insulation spacer  152 , a second insulation spacer  154 , and a third insulation spacer  156 . The second insulation spacer  154  may include a material having a lower permittivity than the first insulation spacer  152  and the third insulation spacer  156 . According to some embodiments, the first insulation spacer  152  and the third insulation spacer  156  may include a nitride layer, and the second insulation spacer  154  may include an oxide layer. According to some embodiments, the first insulation spacer  152  and the third insulation spacer  156  may include a nitride layer, and the second insulation spacer  154  may include a material having an etch selectivity with respect to the first insulation spacer  152  and the third insulation spacer  156 . For example, when the first insulation spacer  152  and the third insulation spacer  156  include a nitride layer, the second insulation spacer  154  may include an oxide layer and may be removed during a subsequent process to be an air spacer. 
     A plurality of buried contact holes  170 H may be formed between each of the plurality of bit lines  147 . The inner space of each of the plurality of buried contact holes  170 H may be defined by insulation spacer structures  150  respectively covering respective sidewalls of two adjacent bit lines  147  from among the plurality of bit lines  147  and an active region  118  between the two adjacent bit lines  147 . In addition, the inner space of each of the plurality of buried contact holes  170 H may be further defined by side surfaces of the first and second insulation layer patterns  112  and  114  of one of the two adjacent bit lines  147 . 
     The plurality of buried contact holes  170 H may be formed by partially removing the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) and the active regions  118  by using, as etching masks, the plurality of insulation spacer structures  150 , each covering both sidewalls of each of the plurality of bit line structures  140 , and the plurality of insulation capping lines  148 . According to some embodiments, the plurality of buried contact holes  170 H may be formed by first performing an anisotropic etching process of partially removing the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) and the active regions  118  by using, as etching masks, the insulation spacer structures  150 , each covering both side walls of each of the plurality of bit line structures  140 , and the plurality of insulation capping lines  148  and then performing an isotropic etching process of further partially removing the active regions  118  such that the respective spaces of the buried contact holes  170 H, which are defined by the active regions  118 , may be extended. 
     A plurality of gate line structures  140 P may be formed on the logic active regions  117 . According to some embodiments, at least one dummy bit line structure  140 D may be arranged between each bit line structure  140  and each gate line structure  140 P. 
     Each of the plurality of gate line structures  140 P may include a gate line  147 P and an insulation capping line  148  covering the gate line  147 P. The plurality of gate lines  147 P included in the plurality of gate line structures  140 P may be formed together with the plurality of bit lines  147 . For example, the plurality of gate lines  147 P may be a stack of the first metal conductive pattern  145  and the second metal conductive pattern  146 . A gate insulation layer pattern  142  may be disposed between each gate line  147 P and each logic active region  117 . According to some embodiments, each of the plurality of gate line structures  140 P may further include a conductive semiconductor pattern  132  between the gate insulation layer pattern  142  and the first metal conductive pattern  145 . The plurality of gate lines  147 P may constitute the plurality of gate line patterns GLP of  FIG. 1 . 
     A gate insulation spacer  150 P may cover both sidewalls of each gate line structure  140 P. The gate insulation spacer  150 P may include, for example, a nitride layer. According to some embodiments, the gate insulation spacer  150 P may include a single layer, but embodiments are not limited thereto. The gate insulation spacer  150 P may have a stack structure including two or more layers. 
     Each dummy bit line structure  140 D may extend lengthwise in the second horizontal direction (Y direction) to be parallel with the bit line structures  140 . Each dummy bit line structure  140 D may have a substantially similar structure to each bit line structure  140 . Each dummy bit line structure  140 D may include a dummy bit line  147 D including the first metal conductive pattern  145  and the second metal conductive pattern  146 , and an insulation capping line  148 . Both sidewalls of the dummy bit line structure  140 D may be covered by at least one of the insulation spacer structure  150  and the gate insulation spacer  150 P. 
     According to some embodiments, a horizontal width of the dummy bit line  147 D in the first horizontal direction (X direction) may be greater than a horizontal width of each of the bit lines  147  in the first horizontal direction (X direction). According to some other embodiments, the horizontal width of the dummy bit line  147 D in the first horizontal direction (X direction) may be equal to the horizontal width of each of the bit lines  147  in the first horizontal direction (X direction). According to some embodiments, a plurality of dummy bit line structures  140 D may be included, and the dummy bit lines  147 D of some of the plurality of dummy bit line structures  140 D may have horizontal widths in the first horizontal direction (X direction) that are greater than the horizontal width of each bit line  147  and the dummy bit lines  147 D of the others of the plurality of dummy bit line structures  140 D may have horizontal widths in the first horizontal direction (X direction) that are equal to the horizontal width of each bit line  147 . 
     Referring to  FIGS. 5A through 5G , a plurality of buried contacts  170  and a plurality of insulation fences  180  are formed in spaces among the plurality of insulation spacer structures  150  respectively covering the sidewalls of the plurality of bit line structures  140 . The plurality of buried contacts  170  and the plurality of insulation fences  180  may be alternately arranged between every two adjacent insulation spacer structures  150  among the plurality of insulation spacer structures  150 , which respectively cover the sidewalls of the plurality of bit line structures  140 , in the second horizontal direction (Y direction). For example, the plurality of buried contacts  170  may include polysilicon. For example, the plurality of insulation fences  180  may include a nitride layer. 
     According to some embodiments, the plurality of buried contacts  170  may be arranged in a line in each of the first horizontal direction (X direction) and a line in the second horizontal direction (Y direction). Each of the plurality of buried contacts  170  may extend from an active region  118  in the vertical direction (Z direction) perpendicular to the substrate  110 . The plurality of buried contacts  170  may constitute the plurality of buried contacts BC of  FIG. 1 . 
     The plurality of buried contacts  170  may be arranged in spaces defined by the plurality of insulation spacer structures  150 , respectively covering the sidewalls of the plurality of bit line structures  140 , and the plurality of insulation fences  180 . The plurality of buried contacts  170  may fill a lower portion of the spaces between the plurality of insulation spacer structures  150 , respectively covering the sidewalls of the plurality of bit line structures  140 . 
     The top surfaces of the plurality of buried contacts  170  may be at a lower level than the top surfaces of the plurality of insulation capping lines  148 . The top surfaces of the plurality of insulation fences  180  may be at the same level as the top surfaces of the plurality of insulation capping lines  148  in the vertical direction (Z direction). 
     A plurality of landing pad holes  190 H may be defined by the plurality of insulation spacer structures  150  and the plurality of insulation fences  180 . The plurality of landing pad holes  190 H may vertically overlap the plurality of buried contacts  170 . The plurality of buried contacts  170  may be exposed at the bottoms of the plurality of landing pad holes  190 H. 
     A filling insulation layer (including first and second filling insulation layers  172  and  174 ) may be formed on the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) around the plurality of gate line structures  140 P. According to some embodiments, the filling insulation layer (including first and second filling insulation layers  172  and  174 ) may have a stack structure in which the first filling insulation layer  172  and the second filling insulation layer  174  are stacked. According to some embodiments, the first filling insulation layer  172  may include oxide, and the second filling insulation layer  174  may include nitride. The top surface of the filling insulation layer (including first and second filling insulation layers  172  and  174 ), that is, the top surface of the second filling insulation layer  174 , may be at the same level as the top surface of each gate line structure  140 P. 
     While the plurality of buried contacts  170  and/or the plurality of insulation fences  180  are being formed, the respective upper portions of the insulation capping line  148  included in the bit line structures  140 , the dummy bit line structures  140 D, and the gate line structures  140 P, the insulation spacer structures  150 , and the gate insulation spacer  150 P may be partially removed, and thus the levels of the top surfaces of the bit line structures  140 , the dummy bit line structures  140 D, and the gate line structures  140 P may be decreased. 
     Referring to  FIGS. 6A through 6G , a plurality of contact holes CPHE, CPHF, and CPHG penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) and the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) are formed. The plurality of contact holes CPHE, CPHF, and CPHG may include a first contact hole CPHE, a second contact hole CPHF, and third contact holes CPHG. The third contact holes CPHG may include a gate line contact hole CPHG 1  and a bit line contact hole CPHG 2 . The first contact hole CPHE and the second contact hole CPHF may be referred to as a word line contact hole CPHE and a logic active region contact hole CPHF, respectively. 
     The word line contact hole CPHE may extend to a lower word line layer  120   a  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ), the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ), a buried insulation layer  124 , and an upper word line layer  120   b . According to some embodiments, the word line contact hole CPHE may stretch into the lower word line layer  120   a.    
     The logic active region contact hole CPHF may extend to the logic active region  117  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) and the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ). According to some embodiments, the logic active region contact holes CPHF may stretch into the logic active region  117 . 
     According to some embodiments, the third contact holes CPHG, namely, the gate line contact hole CPHG 1  and the bit line contact hole CPHG 2 , may extend to the first metal conductive patterns  145  by penetrating the insulation capping lines  148  and the second metal conductive patterns  146 . According to some embodiments, the third contact holes CPHG, namely, the gate line contact hole CPHG 1  and the bit line contact hole CPHG 2 , may stretch into the first metal conductive patterns  145 . According to some other embodiments, the third contact holes CPHG, namely, the gate line contact hole CPHG 1  and the bit line contact hole CPHG 2 , may extend to the second metal conductive patterns  146  by penetrating the insulation capping lines  148 . According to some other embodiments, the third contact holes CPHG, namely, the gate line contact hole CPHG 1  and the bit line contact hole CPHG 2 , may stretch into the second metal conductive patterns  146 . 
     For example, the gate line contact hole CPHG 1  may extend to a gate line  147 P by penetrating an insulation capping line  148 , and the bit line contact hole CPHG 2  may extend to a bit line  147  by penetrating an insulation capping line  148 . According to some embodiments, the gate line contact holes CPHG 1  may stretch into the gate line  147 P by penetrating the insulation capping line  148 , and the bit line contact holes CPHG 2  may stretch into the bit line  147  by penetrating the insulation capping line  148 . 
     According to some embodiments, the first contact hole CPHE, the second contact hole CPHF, and the third contact holes CPHG may be formed simultaneously by using the same etching process. According to some other embodiments, at least one of the first contact hole CPHE, the second contact hole CPHF, and the third contact holes CPHG may be sequentially formed by using separate etching processes. 
     Referring to  FIGS. 7A through 7G , an extended mask pattern MKE having an extended opening MKEO that exposes the first contact hole CPHE and portions of the filling insulation layer (including first and second filling insulation layers  172  and  174  that are adjacent to the first contact hole CPHE) is formed. The extended mask pattern MKE may cover the remaining portions of the filling insulation layer (including first and second filling insulation layers  172  and  174 ). The extended mask pattern MKE may fill the second contact hole CPHF and the third contact holes CPHG and may cover the bit line structures  140 , the dummy bit line structures  140 D, the gate line structures  140 P, the buried contacts  170 , and the insulation fences  180 . 
     Thereafter, a hole extension HE may be formed in an upper portion of the first contact hole CPHE by removing the portions of the filling insulation layer (including first and second filling insulation layers  172  and  174 ) exposed via the extended opening MKEO by using the extended mask pattern MKE as an etching mask. After the hole extension HE is formed, the extended mask pattern MKE may be removed. While the hole extension HE is being formed, the vertical level of the bottom surface of the first contact hole CPHE may decrease. 
     Referring to  FIGS. 8A through 8G , after the hole extension HE is formed and the extended mask pattern MKE is removed, a landing pad material layer  190 P is formed to fill the plurality of landing pad holes  190 H and the plurality of contact holes CPHE, CPHF, and CPHG and cover the plurality of bit line structures  140 , the plurality of gate line structures  140 P and the at least one dummy bit line structure  140 D. 
     The hole extension HE may be formed by partially removing the filling insulation layer (including first and second filling insulation layers  172  and  174 ). Due to the hole extension HE, a horizontal width and a horizontal cross-section of the upper portion of the first contact hole CPHE may be increased. For example, a horizontal width of the upper portion of the first contact hole CPHE adjacent to the second filling insulation layer  174  may be wider than a horizontal width of a lower portion of the first contact hole CPHE adjacent to a lower portion of the first filling insulation layer  172 . The bottom surface of the hole extension HE may have a higher vertical level than a first vertical level LV 1  of the top surface of the bit line  147  or the gate line  147 P, namely, the top surface of the second metal conductive pattern  146 . For example, the vertical level of the bottom surface of the hole extension HE may be higher than the first vertical level LV 1  of the top surface of the second metal conductive pattern  146 , and may be lower than a second vertical level LV 2  of the top surface of the insulation capping line  148  or the top surface of the filling insulation layer (including first and second filling insulation layers  172  and  174 ), namely, the top surface of the second filling insulation layer  174 . In some embodiments, the vertical level of the bottom surface of the hole extension HE may be lower than a top surface of the first filling insulation layer  172 . 
     According to some embodiments, the landing pad material layer  190 P may include a conductive barrier layer and a conductive pad material layer disposed on the conductive barrier layer. For example, the conductive barrier layer may include metal, conductive metal nitride, or a combination thereof. According to some embodiments, the conductive barrier layer may have a Ti/TiN stack structure. According to some embodiments, the conductive pad material layer may include tungsten (W). 
     According to some embodiments, before the landing pad material layer  190 P is formed, a metal silicide layer may be formed on the plurality of buried contacts  170 . The metal silicide layer may be arranged between the plurality of buried contacts  170  and the landing pad material layer  190 P. The metal silicide layer may include, but is not limited to, cobalt silicide (CoSi x ), nickel silicide (NiSi x ), or manganese silicide (MnSi x ). 
     A plurality of hard mask patterns HMKC and HMKP are formed on the landing pad material layer  190 P. According to some embodiments, the plurality of hard mask patterns HMKC and HMKP may be formed by extreme ultraviolet (EUV) lithography. The plurality of hard mask patterns HMKC and HMKP may include a cell hard mask pattern HMKC arranged on the plurality of landing pad holes  190 H and portions of the landing pad material layer  190 P around the plurality of landing pad holes  190 H and a logic hard mask patterns HMKP arranged on the plurality of contact holes CPHE, CPHF, and CPHG and portions of the landing pad material layer  190 P around the plurality of contact holes CPHE, CPHF, and CPHG. In some embodiments, the cell hard mask pattern HMKC may at least partially overlap the landing pad holes  190 H, and the logic hard mask pattern HMKP may vertically overlap the contact holes CPHE, CPHF, and CPHG. 
     Referring to  FIGS. 9A through 9G , a plurality of landing pads  190  at least partially filling the plurality of landing pad holes  190 H and extending over the plurality of bit line structures  140  are formed by removing portions of the plurality of bit line structures  140  and portions of the landing pad material layer  190 P of  FIGS. 8A through 8G  around the plurality of landing pad holes  190 H by using the cell hard mask pattern HMKC as an etching mask. The plurality of landing pads  190  may be separated from each other with recesses  190 R therebetween. Referring to  FIG. 9C , portions of each of the plurality of insulation fences  180  may also be removed by using the cell hard mask pattern HMKC as an etching mask. 
     The plurality of landing pads  190  may be arranged on the plurality of buried contacts  170  and may extend over the plurality of bit line structures  140 . According to some embodiments, the plurality of landing pads  190  may extend over the plurality of bit lines  147 . The plurality of landing pads  190  may be arranged on the plurality of buried contacts  170  to be electrically connected to the plurality of buried contacts  170 , respectively. The plurality of landing pads  190  may be connected to the active regions  118  via the plurality of buried contacts  170 , respectively. The plurality of landing pads  190  may constitute the plurality of landing pads LP of  FIG. 1 . 
     Each buried contact  170  may be between two adjacent bit line structures  140 , and each landing pad  190  may extend from between the two adjacent bit line structures  140  to above one of the two adjacent bit line structures  140 , wherein the two adjacent bit line structures  140  have the buried contact  170  therebetween. 
     A plurality of logic bit lines BLP, and a plurality of contact plugs CPE, CPF, and CPG respectively filling the plurality of contact holes CPHE, CPHF, and CPHG are formed by removing the portions of the landing pad material layer  190 P around the plurality of contact holes CPHE, CPHF, and CPHG by using the logic hard mask pattern HMKP as an etch mask. The plurality of logic bit lines BLP may be a portion of the landing pad material layer  190 P on the plurality of contact plugs CPE, CPF, and CPG that is at a higher level than the second vertical level LV 2 . 
     The plurality of contact plugs CPE, CPF, and CPG may include a plurality of first contact plugs CPE, a plurality of second contact plugs CPF, and a plurality of third contact plugs CPG. The plurality of third contact plugs CPG may include a plurality of gate line contact plugs CPG 1  and a plurality of bit line contact plugs CPG 2 . The first contact plug CPE and the second contact plug CPF may be referred to as a word line contact plug CPE and a logic active region contact plug CPF, respectively. 
     The word line contact plug CPE may extend to the lower word line layer  120   a  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) covering a portion of the top surface of each word line  120 , the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ), the buried insulation layer  124 , and the upper word line layer  120   b.    
     Each word line contact plug CPE may have a plug extension PE. The plug extension PE may be a portion of the word line contact plug CPE that fills the hole extension HE. Due to the plug extension PE, a horizontal width and a horizontal cross-section of the upper portion of the word line contact plug CPE may be increased. The bottom surface of the plug extension PE may have a higher vertical level than the first vertical level LV 1  of the top surface of the second metal conductive pattern  146 . For example, the vertical level of the bottom surface of the plug extension PE may be higher than the first vertical level LV 1  of the top surface of the second metal conductive pattern  146 , and may be lower than the second vertical level LV 2  of the top surface of the insulation capping line  148 . In some embodiments, the vertical level of the bottom surface of the plug extension PE may be lower than a top surface of the first filling insulating layer  172 . 
     The lateral surface of a portion of the word line contact plug CPE that is adjacent to the top surface of the lower word line layer  120   a  may be surrounded by the upper word line layer  120   b . For example, the lateral surface of a portion of the word line contact plug CPE at a level corresponding to the upper word line layer  120   b , namely, a level between the top surface and the bottom surface of the upper word line layer  120   b , may be completely covered by the upper word line layer  120   b.    
     The logic active region contact plug CPF may extend to the logic active region  117  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) and the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ). 
     According to some embodiments, the third contact plugs CPG, namely, the gate line contact plug CPG 1  and the bit line contact hole CPG 2 , may extend to the first metal conductive patterns  145  by penetrating the insulation capping lines  148  and the second metal conductive patterns  146 . According to some other embodiments, the third contact plugs CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , may extend to the second metal conductive patterns  146  by penetrating the insulation capping lines  148 . For example, the gate line contact plug CPG 1  may extent to a gate line  147 P by penetrating an insulation capping line  148 , and the bit line contact plug CPG 2  may extend to a bit line  147  by penetrating an insulation capping line  148 . 
     The plurality of landing pads  190 , the plurality of logic bit lines BLP, the first contact plugs CPE, the second contact plugs CPF, and the third contact plugs CPG may be simultaneously formed using the same etching process using both the cell hard mask pattern HMKC and the logic hard mask pattern HMKP as etching masks. 
     Referring to  FIGS. 10A through 10D , the semiconductor memory device  1  including a plurality of capacitor structures  200  may be formed by sequentially forming a plurality of lower electrodes  210 , a capacitor dielectric layer  220 , and an upper electrode  230  on the plurality of landing pads  190 . The plurality of lower electrodes  210  may be electrically connected to the plurality of landing pads  190 , respectively. The capacitor dielectric layer  220  may conformally cover the plurality of lower electrodes  210 . The upper electrode  230  may cover the capacitor dielectric layer  220 . The upper electrode  230  may face the plurality of lower electrodes  210  with the capacitor dielectric layer  220  between the upper electrode  230  and the plurality of lower electrodes  210 . The capacitor dielectric layer  220  and the upper electrode  230  may be integrally formed to cover the plurality of lower electrodes  210  in a certain region, e.g., one memory cell region CR. The plurality of lower electrodes  210  may constitute the plurality of storage nodes SN illustrated in  FIG. 1 . 
     Each of the plurality of lower electrodes  210  may have, but is not limited to, a solid pillar shape having a circular horizontal cross-section. According to some embodiments, each of the plurality of lower electrodes  210  may have a cylindrical shape with a closed bottom. According to some embodiments, when viewed from the top down, the plurality of lower electrodes  210  may be arranged to zigzag in the first horizontal direction (X direction) or the second horizontal direction (Y direction) in a honeycomb pattern. According to some other embodiments, the plurality of lower electrodes  210  may be arranged in lines in the first horizontal direction (X direction) and the second horizontal direction (Y direction) in a matrix pattern. The plurality of lower electrodes  210  may include, for example, impurity-doped silicon, a metal such as tungsten or copper, or a conductive metal compound such as titanium nitride. Although not shown particularly, the semiconductor memory device  1  may further include at least one support pattern that contacts sidewalls of the plurality of lower electrodes  210 . 
     The capacitor dielectric layer  220  may include, for example, TaO, TaAlO, TaON, AlO, AlSiO, HfO, HfSiO, ZrO, ZrSiO, TiO, TiAlO, BST((Ba,Sr)TiO), STO(SrTiO), BTO(BaTiO), PZT(Pb(Zr,Ti)O), (Pb,La)(Zr,Ti)O, Ba(Zr,Ti)O, Sr(Zr,Ti)O, or a combination thereof. The upper electrode  230  may include, for example, doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO(SrRuO), BSRO((Ba,Sr)RuO), CRO(CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. 
     Before the plurality of capacitor structures  200  are formed, insulation structures  195  filling the recesses  190 R may be formed. According to some embodiments, each of the insulation structures  195  may include an interlayer insulation layer and an etch stop layer. For example, the interlayer insulation layer may include an oxide layer and the etch stop layer may include a nitride layer. Although the top surfaces of the insulation structures  195  is at the same level as the bottom surfaces of the plurality of lower electrodes  210  in  FIGS. 10A and 10C , embodiments are not limited thereto. For example, the top surfaces of the insulation structures  195  may be at a higher level than the bottom surfaces of the plurality of lower electrodes  210 , and the plurality of lower electrodes  210  may each extend inside the insulation structures  195  toward the substrate  110 . 
     The plurality of logic bit lines BLP may be filled with a covering insulation layer  250  to be level with the plurality of capacitor structures  200 . The covering insulation layer  250  may include, for example, an oxide layer or an ultra-low K (ULK) layer. The oxide layer may be a layer selected from a borophosphosilicate glass (BPSG) layer, a phosphosilicate glass (PSG) layer, a borosilicate glass (BSG) layer, an un-doped silicate glass (USG) layer, a tetra-ethyl-ortho-silicate (TEOS) layer, and a high density plasma (HDP) layer. The ULK layer may be a layer selected from, for example, a SiOC layer and a SiCOH layer, each having an ultra low dielectric constant K of about 2.2 to about 2.4. 
     The semiconductor memory device  1  includes the substrate  110  having the plurality of active regions  118  and the plurality of logic active regions  117 , the plurality of gate dielectric layers  122 , the plurality of word lines  120 , and the plurality of buried insulation layers  124  sequentially formed within the plurality of word line trenches  120 T traversing the plurality of active regions  118  within the substrate  110 , the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ) covering the device isolation layer  116 , the plurality of active regions  118 , and the plurality of buried insulation layers  124 , the plurality of bit line structures  140  on the insulation layer pattern (including first and second insulation layer patterns  112  and  114 , the plurality of insulation spacer structures  150  respectively covering respective both sidewalls of the plurality of bit line structures  140 , the plurality of gate line structures  140 P on the plurality of logic active regions  117 , the plurality of gate insulation spacers  150 P respectively covering respective both sidewalls of the plurality of gate line structures  140 P, the plurality of buried contacts  170  filling lower portions of the spaces defined by the plurality of insulation fences  180  and the plurality of insulation spacer structures  150  and being connected to the plurality of active regions  118 , the plurality of landing pads  190  filling upper portions of the spaces defined by the plurality of insulation fences  180  and the plurality of insulation spacer structures  150  and each extending to the upper portion of each bit line structure  140 , and the plurality of capacitor structures  200  including the plurality of lower electrodes  210 , the capacitor dielectric layer  220 , and the upper electrode  230 , the plurality of capacitor structures  200  being connected to the plurality of landing pads  190 . 
     The plurality of insulation fences  180  may be arranged apart from each other between every two adjacent insulation spacer structures  150  among the plurality of insulation spacer structures  150 , which respectively cover the sidewalls of the plurality of bit line structures  140 , in the second horizontal direction (Y direction). Each of the plurality of insulation fences  180  may extend from between the plurality of buried contacts  170  to between the plurality of landing pads  190 . 
     The semiconductor memory device  1  may further include the word line contact plug CPE, the logic active region contact plug CPF, the gate line contact plug CPG 1 , and the bit line contact plug CPG 2 . The word line contact plug CPE, the logic active region contact plug CPF, the gate line contact plug CPG 1 , and the bit line contact plug CPG 2  may be formed of the same material. 
       FIGS. 10A through 10G  illustrate one word line contact plug CPE, one gate line contact plug CPG 1 , and one bit line contact plug CPG 2  and two logic active region contact plugs CPF. However, embodiments are not limited thereto. For example, the semiconductor memory device  1  may include a plurality of word line contact plugs CPE, a plurality of gate line contact plugs CPG 1 , a plurality of bit line contact plugs CPG 2 , and a plurality of logic active region contact plugs CPF to correspond to the plurality of word lines  120 , the plurality of gate lines  147 P, the plurality of bit lines  147 , and the plurality of logic active regions  117 . 
     Each word line contact plug CPE may extend to the lower word line layer  120   a  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ), the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ), the buried insulation layer  124 , and the upper word line layer  120   b . Each logic active region contact plug CPF may be connected to the logic active region  117  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) and the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ). 
     Each gate line contact plug CPG 1  may be connected to a gate line  147 P by penetrating an insulation capping line  148 , and each bit line contact plug CPG 2  may extend to a bit line  147  by penetrating an insulation capping line  148 . According to some embodiments, each gate line contact plug CPG 1  and each bit line contact plug CPG 2  may be connected to the first metal conductive patterns  145  by penetrating the insulation capping lines  148  and the second metal conductive patterns  146 . According to some other embodiments, each gate line contact plug CPG 1  and each bit line contact plug CPG 2  may be connected to the second metal conductive patterns  146  by penetrating the insulation capping lines  148 . 
     The plurality of logic bit lines BLP may be arranged on the insulation capping lines  148  and the filling insulation layers (including first and second filling insulation layers  172  and  174 ). Each of the word line contact plug CPE, the logic active region contact plug CPF, the gate line contact plug CPG 1 , and the bit line contact plug CPG 2  may be connected to at least one of the plurality of logic bit lines BLP. According to some embodiments, the word line contact plug CPE, the logic active region contact plug CPF, the gate line contact plug CPG 1 , and the bit line contact plug CPG 2  may include the same material as that material included in the plurality of logic bit lines BLP and may be integrally formed with the plurality of logic bit lines BLP. According to some embodiments, the word line contact plug CPE, the logic active region contact plug CPF, the gate line contact plug CPG 1 , and the bit line contact plug CPG 2  may include the same material as that material included in the plurality of landing pads  190 . 
     Because the word line contact plug CPE of the semiconductor memory device  1  according to an example embodiment of the inventive concept includes, as an upper portion thereof, the plug extension PE having a greater horizontal width and a greater horizontal area than a lower portion thereof, electrical connection between the word line contact plug CPE and the logic bit line BLP may provide improved reliability. While the hole extension HE is being formed to form the plug extension PE, the bottom surface of the word line contact hole CPHE may be lowered, and thus a not open problem in which the word line  120  is not exposed at the bottom of the word line contact hole CPHE may be prevented. 
     Moreover, because the word line contact hole CPHE extends to the lower word line layer  120   a , the word line contact plug CPE may contact both the upper word line layer  120   b  and the lower word line layer  120   a  and accordingly may be electrically connected to the upper word line layer  120   b  and the lower word line layer  120   a . Therefore, the reliability of electrical connection between the word line contact plug CPE and the word line  120  may improve. 
       FIG. 11  is a cross-sectional view for comparing the cross-sections of contact plugs of semiconductor memory devices according to embodiments of the inventive concept. 
     Referring to  FIG. 11  and  FIGS. 10A through 10G , the semiconductor memory device  1  may include the first contact plug CPE, the second contact plug CPF, and the third contact plug CPG. The first contact plug CPE and the second contact plug CPF may be referred to as a word line contact plug CPE and a logic active region contact plug CPF, respectively. The third contact plug CPG may include the gate line contact plugs CPG 1  and the bit line contact plug CPG 2 . The gate line contact plug CPG 1  and the bit line contact plug CPG 2  are substantially the same as each other in terms of shape except that they are connected to the gate line  147 P and the bit line  147 , respectively, or  FIG. 11  illustrates the cross-section of the bit line contact plug CPG 2  to describe the third contact plug CPG and does not illustrate and describe the gate line contact plug CPG 1 . 
     The word line contact plug CPE may extend from the logic bit line BLP to the lower word line layer  120   a  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) covering a portion of the top surface of each word line  120 , the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ), the buried insulation layer  124 , and the upper word line layer  120   b.    
     The word line contact plug CPE may have a plug extension PE. Due to the plug extension PE, a horizontal width and a horizontal cross-section of the upper portion of the word line contact plug CPE may be increased. The bottom surface of the plug extension PE may have a higher vertical level than the first vertical level LV 1  of the top surface of the second metal conductive pattern  146 . For example, the vertical level of the bottom surface of the plug extension PE may be higher than the first vertical level LV 1  of the top surface of the second metal conductive pattern  146 , and may be lower than the second vertical level LV 2  of the top surface of the insulation capping line  148 . 
     The lateral surface of a portion of the word line contact plug CPE that is adjacent to the top surface of the lower word line layer  120   a  may be entirely surrounded by the upper word line layer  120   b . For example, the lateral surface of a portion of the word line contact plug CPE at a level corresponding to the upper word line layer  120   b , namely, a level between the top surface and the bottom surface of the upper word line layer  120   b , may be completely covered by the upper word line layer  120   b . For example, the upper word line layer  120   b  may contact the lateral surface of the portion of the word line contact plug CPE that is adjacent to the top surface of the lower word line layer  120   a , extending around the circumference of the word line contact plug CPE. 
     The logic active region contact plug CPF may extend from the logic bit line BLP to the logic active region  117  by penetrating the filling insulation layer (including first and second filling insulation layers  172  and  174 ) and the insulation layer pattern (including first and second insulation layer patterns  112  and  114 ). 
     The third contact plug CPG, namely, the gate line contact plug CPG 1 , may extend to a gate line  147 P by penetrating an insulation capping line  148 , and the bit line contact plug CPG 2  may extend to a bit line  147  by penetrating an insulation capping line  148 . According to some embodiments, the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , may extend from the logic bit line BLP to the first metal conductive patterns  145  by penetrating the insulation capping lines  148  and the second metal conductive patterns  146 . According to some other embodiments, the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , may extend from the logic bit line BLP to the second metal conductive patterns  146  by penetrating the insulation capping lines  148 . 
     A ratio WEH/WEL of a horizontal width WEH of the word line contact plug CPE at the second vertical level LV 2  to a horizontal width WEL of the word line contact plug CPE at the first vertical level LV 1  may be greater than each of a ratio WFH/WFL of a horizontal width WFH of the logic active region contact plug CPF at the second vertical level LV 2  to a horizontal width WFL of the logic active region contact plug CPF at the first vertical level LV 1  and a ratio WGH/WGL of a horizontal width WGH of the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , at the second vertical level LV 2  to a horizontal width WGL of the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , at the first vertical level LV 1 . 
     According to some embodiments, an extension length of the word line contact plug CPE from the logic bit line BLP to the substrate  110  may be greater than that of the logic active region contact plug CPF, and an extension length of the logic active region contact plug CPF may be greater than that of the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 . For example, the word line contact plug CPE may extend to a lower vertical level than the logic active region contact plug CPF, and the logic active region contact plug CPF may extend to a lower vertical level than the gate line contact plug CPG 1  and the bit line contact plug CPG 2 . 
     According to some embodiments, the horizontal width WFL of the logic active region contact plug CPF at the first vertical level LV 1  may be greater than the horizontal width WEL of the word line contact plug CPE at the first vertical level LV 1 , and the horizontal width WEL of the word line contact plug CPE at the first vertical level LV 1  may be greater than the horizontal width WGL of the third contact plug CPG, namely, the gate line contact plug CPG 1  and the bit line contact plug CPG 2 , at the first vertical level LV 1 . However, embodiments are not limited thereto. 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.