Patent Publication Number: US-11393682-B2

Title: Nanowire with reduced defects

Description:
FIELD OF THE DISCLOSURE 
     The present disclosure is related to nanowires, and in particular to nanowires with reduced defects and methods for manufacturing the same. 
     BACKGROUND 
     Nanowires show great promise for applications in quantum computing. Unfortunately, it is difficult to manufacture high quality nanowires. Conventional processes for manufacturing nanowires include selective-area-growth (SAG) wherein nanowires are selectively grown directly on a substrate through a patterned mask layer. To function properly, nanowires must be a conducting semiconductor material such as indium arsenide, indium antimonide, or indium arsenide antimonide. The substrate on which the nanowires are grown must be an insulating material such as gallium arsenide, gallium antimonide, indium phosphide, gallium phosphide, silicon, or germanium. There is often a large difference in the crystal lattice constant of the substrate and the nanowires. This crystal lattice mismatch causes crystalline defects in the nanowires during growth such as dislocations and stacking faults. The crystalline defects can penetrate the nanowires and in turn decrease the performance of the resulting nanowires. 
     In light of the above, there is a need for nanowires with reduced crystalline defects and methods of manufacturing the same. 
     SUMMARY 
     In one embodiment, a nanowire structure includes a substrate, a patterned mask layer on the substrate, and a nanowire. The patterned mask layer includes an opening through which the substrate is exposed. The nanowire is on the substrate in the opening of the patterned mask layer. The nanowire includes a buffer layer on the substrate, a defect filtering layer on the buffer layer, and an active layer on the defect filtering layer. The defect filtering layer is a strained layer. By providing the defect filtering layer between the buffer layer and the active layer of the nanowire, defects present in the buffer layer can be prevented from propagating into the active layer. Accordingly, defects in the active layer of the nanowire are reduced, thereby improving the performance of the nanowire structure. 
     In one embodiment, a thickness of the defect filtering layer is between 2 ML (monolayers) and 10 nm. The defect filtering layer may comprise one or more of indium gallium arsenide (InGaAs), aluminum arsenide (AIAs), and aluminum antimonide (AlSb). The buffer layer may comprise one or more of gallium arsenide antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), and aluminum gallium antimonide arsenide (AlGaSbAs). The active layer may comprise one or more of indium arsenide (InAs), indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The substrate may comprise one or more of gallium arsenide (GaAs), gallium antimonide (GaSb), gallium arsenide antimonide (GaAsSb), indium phosphide (InP), gallium phosphide (GaP), silicon (Si), and germanium (Ge). A thickness of the buffer layer may be between 20 nm and 200 nm. A thickness of the active layer may be between 10 nm and 200 nm. A thickness of the substrate may be between 200 μm and 500 μm The buffer layer, the defect filtering layer, and the active layer may be grown via a selective area growth process. The defect filtering layer may be configured to prevent defects in the buffer layer from propagating into the active layer. The buffer layer may include any number of buffer layers and the defect filtering layer may include any number of defect filtering layers. The buffer layers may be alternated with the defect filtering layers to further decrease the likelihood of defect propagation. 
     Those skilled in the art will appreciate the scope of the present disclosure and realize additional aspects thereof after reading the following detailed description of the preferred embodiments in association with the accompanying drawing figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       The accompanying drawing figures incorporated in and forming a part of this specification illustrate several aspects of the disclosure, and together with the description serve to explain the principles of the disclosure. 
         FIG. 1  is a diagram illustrating a nanowire structure according to one embodiment of the present disclosure. 
         FIG. 2  is a diagram illustrating a nanowire structure according to one embodiment of the present disclosure. 
         FIG. 3  is a flow diagram illustrating a method for manufacturing a nanowire structure according to one embodiment of the present disclosure. 
         FIGS. 4A through 4F  are diagrams illustrating a method for manufacturing a nanowire structure according to one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments. Upon reading the following description in light of the accompanying drawing figures, those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein. It should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. 
     It will be understood that when an element such as a layer, region, or substrate is referred to as being “on” or extending “onto” another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements present. Likewise, it will be understood that when an element such as a layer, region, or substrate is referred to as being “over” or extending “over” another element, it can be directly over or extend directly over the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly over” or extending “directly over” another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     Relative terms such as “below” or “above” or “upper” or “lower” or “horizontal” or “vertical” may be used herein to describe a relationship of one element, layer, or region to another element, layer, or region as illustrated in the Figures. It will be understood that these terms and those discussed above are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes,” and/or “including” when used herein specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
       FIG. 1  shows a nanowire structure  10  according to one embodiment of the present disclosure. The nanowire structure  10  includes a substrate  12 , a patterned mask layer  14  on the substrate  12 , and a nanowire  16  on the substrate  12  through an opening in the patterned mask layer  14 . The nanowire  16  includes a buffer layer  18  on the substrate  12 , a defect filtering layer  20  on the buffer layer  18 , and an active layer  22  on the defect filtering layer  20 . A superconductor layer  24  is on the active layer  22 . The defect filtering layer  20  is a strained layer. As discussed herein, a strained layer is a layer in which the atoms of the material thereof are stretched beyond their normal interatomic distance. Due to the material properties and thickness of the defect filtering layer  20 , it prevents the defects that may occur in the buffer layer  18  from propagating into the active layer  22 . Fewer defects in the active layer  22  results in improved performance of the nanowire structure  10 , for example, when the nanowire structure  10  is operated as part of a quantum computing device such as a qubit. 
     In various embodiments, the substrate  12  may comprise one or more of gallium arsenide, gallium antimonide, gallium arsenide antimonide, indium phosphide, gallium phosphide, silicon, and germanium. The patterned mask layer  14  may comprise a dielectric such as silicon dioxide. While shown as a single layer, the buffer layer  18  may comprise several different layers. These layers may comprise one or more of gallium arsenide antimonide (GaAsSb), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), and aluminum gallium antimonide arsenide (AlGaSbAs). The defect filtering layer  20  may comprise one of indium gallium arsenide (InGaAs), aluminum arsenide (AlAs), and aluminum antimonide (AlSb). The active layer  22  may comprise one of indium arsenide (InAs), indium antimonide (InSb), and indium arsenide antimonide (InAsSb). The superconductor layer  24  may comprise one of aluminum (Al), lead (Pb), niobium (Nb), indium (In), tin (Sn), and vanadium (V). A thickness of the superconductor layer  24  may be between 3 nm and 30 nm. 
     In various embodiments, a thickness of the buffer layer  18  may be between 20 nm and 200 nm. A thickness of the defect filtering layer  20  may be between 2 ML (monolayers) and 10 nm. A thickness of the active layer  22  may be between 10 nm and 200 nm. A thickness of the substrate  12  may be between 200 μm and 500 μm. The nanowire  16  may have a thickness between 20 nm and 300 nm. Further, the nanowire  16  may have a diameter on the order of a nanometer (10 −9  meters) or a ratio of length to width greater than 1000. 
     In some embodiments, the nanowire  16  includes more than one defect filtering layer  20 . When the nanowire  16  includes more than one defect filtering layer  20 , each one of the layers may be alternated with a buffer layer  18  as shown in  FIG. 2 . While only two buffer layers  18  and two defect filtering layers  20  are shown alternating between the substrate  12  and the active layer  22  in  FIG. 2 , the nanowire  16  may include any number of buffer layers  18  and defect filtering layers  20  without departing from the principles of the present disclosure. 
       FIG. 3  is a flow diagram illustrating a method for manufacturing the nanowire structure  10  according to one embodiment of the present disclosure.  FIGS. 4A through 4F  illustrate the method and thus are discussed in conjunction with the flow diagram in  FIG. 3 . The substrate  12  is provided (block  100  and  FIG. 4A ). The patterned mask layer  14  is provided on the substrate  12  (block  102  and  FIG. 4B ). In various embodiments, providing the patterned mask layer  14  may comprise depositing a mask layer over the entirety of the substrate  12  as a blanket layer and then patterning the layer, for example, by a lithography process. The buffer layer  18  is provided on the substrate  12  through an opening in the patterned mask layer  14  (block  104  and  FIG. 4C ). The defect filtering layer  20  is provided on the buffer layer  18  (block  106  and  FIG. 4D ). The active layer  22  is provided on the defect filtering layer  20  (block  108  and  FIG. 4E ). The buffer layer  18 , the defect filtering layer  20 , and the active layer  22  may be provided by a growth process such as a selective area growth (SAG) process. The superconductor layer  24  is provided on the active layer  22 , and, in some embodiments extends over a portion of the patterned mask layer  14  (block  110  and  FIG. 4F ). The superconductor layer  24  may be provided by any suitable deposition process. 
     The completed nanowire structure  10  may form part of a quantum computing device such as a qubit. By using the defect filtering layer  20  to reduce the number of defects in the active layer  22 , the performance of the nanowire structure  10  and thus the resulting quantum computing device may be improved. 
     Those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure. All such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow.