Patent Publication Number: US-7903447-B2

Title: Method, apparatus and computer program product for read before programming process on programmable resistive memory cell

Description:
CROSS-REFERENCE TO OTHER APPLICATIONS 
     The subject matter of this patent application is related to the subject matter of the following U.S. patent applications of the same inventor: Ser. No. 11/621,431, filed on Jan. 9, 2007, entitled “Method, Apparatus and Computer Program Product for Read Before Programming Process on Multiple Programmable Resistive Memory Cells,” and U.S. patent application Ser. No. 11/621,455, filed on Jan. 9, 2007, entitled “Method, Apparatus and Computer Program Product for Stepped Reset Programming Process on Programmable Resistive Memory Cell.” 
     PARTIES TO A JOINT RESEARCH AGREEMENT 
     International Business Machines Corporation, a New York corporation; Macronix International Corporation, Ltd., a Taiwan corporation, and Infineon Technologies A. G., a German corporation, are parties to a Joint Research Agreement. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to high density memory devices based on memory materials, for example resistor random access memory (RRAM) devices, and to methods for programming such devices. The memory material is switchable between electrical property states by the application of energy. The memory materials may be phase change based memory materials, including chalcogenide based materials, and other materials. 
     2. Description of Related Art 
     Phase change based memory materials are widely used in read-write optical disks. These materials have at least two solid phases, including for example a generally amorphous solid phase and a generally crystalline solid phase. Laser pulses are used in read-write optical disks to switch between phases and to read the optical properties of the material after the phase change. 
     Phase change based memory materials, like chalcogenide based materials and similar materials, also can be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state; this difference in resistance can be readily sensed to indicate data. These properties have generated interest in using programmable resistive material to form nonvolatile memory circuits, which can be read and written with random access. 
     In phase change memory, data is stored by causing transitions between amorphous and crystalline states in the phase change material using current. Current heats the material and causes transitions between the states. The change from the amorphous to the crystalline state is generally a lower current operation. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. 
     Each memory cell of a phase change memory device is coupled to a bit line and an access device, such as a transistor, wherein the access device is coupled to a word line. The method by which the resistance of a phase change memory cell is read, set or reset involves the application of bias voltages to the bit line and word line for the memory cell. In order to apply a set voltage pulse or a reset voltage pulse to a phase change memory cell, the word and bit lines must be connected to circuitry providing the set voltage pulse or the reset voltage pulse. The creation of these connections for setting or resetting a phase change memory cell is referred to as “bit line set up” and “word line set up.” There is a time and resource expenditure associated with the steps taken during bit line setup and word line setup. Therefore, there is a desire to reduce the number of steps taken during bit line setup and word line setup. Furthermore, when handling the programming of successive phase change memory cells in an array of phase change memory cells, word line setup and bit line setup for a first memory cell may necessitate a change if the set/reset programming for a memory cell is different from the set/reset programming of the immediately preceding memory cell. Changing a word line setup or a bit line setup when sequentially programming memory cells also expends time and resources. Therefore, there is a further desire to reduce the number of times a word line setup or a bit line setup is changed when programming successive phase change memory cells in an array of phase change memory cells. 
     Accordingly, an opportunity arises to devise methods and structures that reduce the steps taken in a bit line setup and a word line setup when programming a phase change memory cell or programming successive phase change memory cells in an array of phase change memory cells. 
     BRIEF SUMMARY OF THE INVENTION 
     A first aspect of the present invention relates to a method for programming a plurality of programmable resistive memory cells. One exemplary method comprises executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The method further comprises executing the following for each memory cell: programming the memory cell to a lower resistance (SET) state if the resistance is at a higher resistance state and the input data corresponds to a first (SET) state, and programming the memory cell to a higher resistance (RESET) state if the resistance is at a lower resistance state and the input data corresponds to a second (RESET) state. 
     A second aspect of the present invention relates to a programmable resistive memory system that in one example comprises a memory cell device comprising a plurality of programmable resistive memory cells and a controller for programming the memory cell device. The controller is configured for executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The controller is further configured for executing the following for each memory cell: programming the memory cell to a lower resistance (SET) state if the resistance is at a higher resistance state and the input data corresponds to a first (SET) state and programming the memory cell to a higher resistance (RESET) state if the resistance is at a lower resistance state and the input data corresponds to a second (RESET) state. 
     A third aspect of the present invention relates to a computer program product including computer instructions for programming a memory cell device event in one example comprises a plurality of programmable resistive memory cells. The computer instructions include instructions for executing the following for each memory cell: reading a resistance of a memory cell and reading input data corresponding to the memory cell. The computer instructions further include instructions for executing the following for each memory cell: programming the memory cell to a lower resistance (SET) state if the resistance is at a higher resistance state and the input data corresponds to a first (SET) state and programming the memory cell to a higher resistance (RESET) state if the resistance is at a lower resistance state and the input data corresponds to a second (RESET) state. 
     Various features and advantages of the invention will appear from the following description in which the preferred embodiments have been set forth in detail in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram of an integrated circuit device in accordance with the present invention. 
         FIG. 2  is a partial schematic diagram of a representative memory array as shown in  FIG. 1 . 
         FIG. 3  is a graph of voltage and temperature versus time for pulses used for programming programmable resistive memory cells, according to one embodiment of the present invention. 
         FIG. 4  is a flowchart showing the control flow of a general process for programming a single memory cell comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 5  is a flowchart showing the control flow of the process for programming a single memory cell comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 6  is a flowchart showing the control flow of the process for sequentially programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 7  is a flowchart showing the control flow of the process for group programming of a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 8  is a flowchart showing the control flow of the process for group programming of a plurality of memory cells comprising a phase change material, in accordance with another embodiment of the present invention. 
         FIG. 9  is a flowchart showing the control flow of the group set process for programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 10  is a flowchart showing the control flow of the group reset process for programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. 
         FIG. 11  is a flowchart showing the control flow of the process for reset programming a memory cell comprising a phase change material, in accordance with one embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The following description of the invention will typically be with reference to specific structural embodiments and methods. It is to be understood that there is no intention to limit the invention to the specifically disclosed embodiments and methods but that the invention may be practiced using other features, elements, methods and embodiments. Preferred embodiments are described to illustrate the present invention, not to limit its scope, which is defined by the claims. Those of ordinary skill in the art will recognize a variety of equivalent variations on the description that follows. Like elements in various embodiments are commonly referred to with like reference numerals. 
     Referring to  FIG. 1 , shown is a simplified block diagram of an integrated circuit  10  in which the present invention may be implemented. Circuit  10  includes a memory array  12  implemented using phase change memory cells (not shown) on a semiconductor substrate, discussed more fully below. A word line decoder  14  is in electrical communication with a plurality of word lines  16 . A bit line decoder  18  is in electrical communication with a plurality of bit lines  20  to read data from, and write data to, the phase change memory cells (not shown) in array  12 . Addresses are supplied on bus  22  to word line decoder and drivers  14  and bit line decoder  18 . Sense amplifiers and data-in structures in block  24  are coupled to bit line decoder  18  via data bus  26 . Data is supplied from an input buffer  27  via a data-in line  28  from input/output ports on integrated circuit  10 , or from other data sources internal or external to integrated circuit  10 , to data-in structures in block  24 . Other circuitry  30  may be included on integrated circuit  10 , such as a general purpose processor or special purpose application circuitry, or a combination of modules providing system-on-a-chip functionality supported by array  12 . Data is supplied via a data-out line  32  from the sense amplifiers in block  24  to input/output ports on integrated circuit  10 , or to other data destinations internal or external to integrated circuit  10 . 
     A controller  34  implemented in this example, using a bias arrangement state machine, controls the application of bias arrangement supply voltages  36 , such as read, program, erase, erase verify and program verify voltages. Controller  34  may be implemented using special-purpose logic circuitry as known in the art. In alternative embodiments, controller  34  comprises a general-purpose processor, which may be implemented on the same integrated circuit to execute a computer program to control the operations of the device. In yet other embodiments, a combination of special-purpose logic circuitry and a general-purpose processor may be utilized for implementation of controller  34 . 
     As shown in  FIG. 2  each of the memory cells of array  12  includes an access transistor (or other access device such as a diode), four of which are shown as  38 ,  40 ,  42  and  44 , and a memory element, typically a phase change element, shown as  46 ,  48 ,  50  and  52 . Sources of each of access transistors  38 ,  40 ,  42  and  44  are connected in common to a source line  54  that terminates in a source line termination  55 . In another embodiment the source lines of the select devices are not electrically connected, but independently controllable. A plurality  16  of word lines including word lines  56  and  58  extend parallel along a first direction. Word lines  56  and  58  are in electrical communication with word line decoder  14 . The gates of access transistors  38  and  42  are connected to a common word line, such as word line  56 , and the gates of access transistors  40  and  44  are connected in common to word line  58 . A plurality  20  of bit lines including bit lines  60  and  62  have one end of phase change elements  46  and  48  connected to bit line  60  via separate connections  88 . Specifically, phase change element  46  is connected between the drain of access transistor  38  and bit line  60 , and phase change element  48  is connected between the drain of access transistor  40  and bit line  60 . Similarly, phase change element  50  is connected between the drain of access transistor  42  and bit line  62 , and phase change element  52  is connected between the drain of access transistor  44  and bit line  62 . It should be noted that four memory cells are shown for convenience of discussion and in practice array  12  may comprise thousands to millions of such memory cells. Also, other ray structures may be used, e.g. the phase change memory element is connected to source. 
     Useful characteristics of a programmable resistive type of memory material, like a phase change material, include the material having a resistance which is programmable, and preferably in a reversible manner, such as by having at least two solid phases that can be reversibly induced by electrical current. These at least two phases include an amorphous phase and a crystalline phase. However, in operation, the programmable resistive material may not be fully converted to either an amorphous or crystalline phase. Intermediate phases or mixtures of phases may have a detectable difference in material characteristics. The two solid phases should generally be bistable and have different electrical properties. The programmable resistive material may be a chalcogenide material. A chalcogenide material may include GST. In following sections of the disclosure, the phase change or other memory material is often referred to as GST, and it will be understood that other types of phase change materials can be used. A material useful for implementation of a memory cell as described herein is Ge 2 Sb 2 Te 5 . 
     A memory cell device  10  as described herein is readily manufacturable using standard lithography and thin film deposition technologies, without requiring extraordinary steps to form sub-lithographic patterns, while achieving very small dimensions for the region of the cell that actually changes resistivity during programming. In embodiments of the invention, the memory material may be a programmable resistive material, typically a phase change material, such as Ge 2 Sb 2 Te 5  or other materials described below. The region in the memory element  16  that changes phase is small; and accordingly, the magnitude of the reset current required for changing the phase is very small. 
     Embodiments of memory cell device  10  include phase change based memory materials, including chalcogenide based materials and other materials, for memory element  16 . Chalcogens include any of the four elements oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), forming part of group VI of the periodic table. Chalcogenides comprise compounds of a chalcogen with a more electropositive element or radical. Chalcogenide alloys comprise combinations of chalcogenides with other materials such as transition metals. A chalcogenide alloy usually contains one or more elements from group IV of the periodic table of elements, such as germanium (Ge) and tin (Sn). Often, chalcogenide alloys include combinations including one or more of antimony (Sb), gallium (Ga), indium (In), and silver (Ag). Many phase change based memory materials have been described in technical literature, including alloys of: Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te, Ge/Sb/Se/Te and Te/Ge/Sb/S. In the family of Ge/Sb/Te alloys, a wide range of alloy compositions may be workable. The compositions can be characterized as Te a Ge b Sb 100−(a+b) , where a and b represent atomic percentages that total 100% of the atoms of the constituent elements. One researcher has described the most useful alloys as having an average concentration of Te in the deposited materials well below 70%, typically below about 60% and ranged in general from as low as about 23% up to about 58% Te and most preferably about 48% to 58% Te. Concentrations of Ge were above about 5% and ranged from a low of about 8% to about 30% average in the material, remaining generally below 50%. Most preferably, concentrations of Ge ranged from about 8% to about 40%. The remainder of the principal constituent elements in this composition was Sb. (Ovshinsky &#39;112 patent, cols 10-11.) Particular alloys evaluated by another researcher include Ge 2 Sb 2 Te 5 , GeSb 2 Te 4  and GeSb 4 Te 7 . (Noboru Yamada, “Potential of Ge—Sb—Te Phase-Change Optical Disks for High-Data-Rate Recording”, SPIE v. 3109, pp. 28-37 (1997).) More generally, a transition metal such as chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), palladium (Pd), platinum (Pt) and mixtures or alloys thereof may be combined with Ge/Sb/Te to form a phase change alloy that has programmable resistive properties. Specific examples of memory materials that may be useful are given in Ovshinsky &#39;112 at columns 11-13, which examples are hereby incorporated by reference. 
     Phase change materials are capable of being switched between a first structural state in which the material is in a generally amorphous solid phase, and a second structural state in which the material is in a generally crystalline solid phase in its local order in the active channel region of the cell. These phase change materials are at least bistable. The term amorphous is used to refer to a relatively less ordered structure, more disordered than a single crystal, which has the detectable characteristics such as higher electrical resistivity than the crystalline phase. The term crystalline is used to refer to a relatively more ordered structure, more ordered than in an amorphous structure, which has detectable characteristics such as lower electrical resistivity than the amorphous phase. Typically, phase change materials may be electrically switched between different detectable states of local order across the spectrum between completely amorphous and completely crystalline states. Other material characteristics affected by the change between amorphous and crystalline phases include atomic order, free electron density and activation energy. The material may be switched either into different solid phases or into mixtures of two or more solid phases, providing a gray scale between completely amorphous and completely crystalline states The electrical properties in the material may vary accordingly. 
     Phase change materials can be changed from one phase state to another by application of electrical pulses. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state, and is referred to as a reset pulse. A longer, lower amplitude pulse tends to change the phase change material to a generally crystalline state, and is referred to as a program pulse. The energy in a shorter, higher amplitude pulse is high enough to allow for bonds of the crystalline structure to be broken and short enough to prevent the atoms from realigning into a crystalline state. Appropriate profiles for pulses can be determined empirically, without undue experimentation, specifically adapted to a particular phase change material and device structure. 
     The following are short summaries describing four types of resistive memory materials. 
     1. Chalcogenide Material
         Ge x Sb y Te z      x:y:z=2:2:5   Or other compositions with x: 0˜5; y: 0˜5; z: 0˜10   GeSbTe with doping, such as N—, Si—, Ti—, or other element doping may also be used.       

     Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , and/or He, etc chalcogenide @ the pressure of 1 mtorr˜100 mtorr. The deposition is usually done at room temperature. The collimator with aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously. 
     The post deposition annealing treatment with vacuum or N2 ambient is sometimes needed to improve the crystallize state of chalcogenide material. The annealing temperature typically ranges 100 C to 400 C with an anneal time of less than 30 minutes. 
     The thickness of chalcogenide material depends on the design of cell structure. In general, a chalcogenide material with thickness of higher than 8 nm can have a phase change characterization so that the material exhibits at least two stable resistance states. 
     2. CMR (Colossal Magneto Resistance) Material
         Pr x Ca y MnO 3      x:y=0.5:0.5   Or other compositions with x: 0˜1; y: 0˜1   Another CMR material that includes Mn oxide may be used       

     Formation method: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , O 2 , and/or He, etc. at the pressure of 1 mtorr˜100 mtorr. The deposition temperature can range from room temperature to ˜600 C, depending on the post deposition treatment condition. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. On the other hand, the combination of DC bias and the collimator can be used simultaneously. A magnetic field of several ten gauss to 10,000 gauss may be applied to improve the magnetic crystallized phase. 
     The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient may be needed to improve the crystallized state of CMR material. The annealing temperature typically ranges 400 C to 600 C with an anneal time of less than 2 hours. 
     The thickness of CMR material depends on the design of cell structure. The CMR thickness of 10 nm to 200 nm can be used to be the core material. 
     A buffer layer of YBCO (YBaCuO3, a kind of high temperature superconductor material) is often used to improve the crystallized state of CMR material. The YBCO is deposited before the deposition of CMR material. The thickness of YBCO ranges 30 nm to 200 nm. 
     3. 2-Element Compound
         Ni x O y ; Ti x O y ; Al x O y ; W x O y ; Zn x O y ; Zr x O y ; Cu x O y ; etc   x:y=0.5:0.5   Other compositions with x: 0˜1; y: 0˜1   Formation method:       

     A. Deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar, N 2 , O 2 , and/or He, etc. at the pressure of 1 mtorr 100 mtorr, using a target of metal oxide, such as Ni x O y ; Ti x O y ; Al x O y ; W x O y ; Zn x O y ; Zr x O y ; C x O y ; etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, the DC bias of several ten to several hundred volts is also used. If desired, they combination of DC bias and the collimator can be used simultaneously. 
     The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient as sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours. 
     B. Reactive deposition: By PVD sputtering or magnetron-sputtering method with reactive gases of Ar/O 2 , Ar/N 2 /O 2 , pure O 2 , He/O 2 , He/N 2 /O 2  etc. at the pressure of 1 mtorr˜100 mtorr, using a target of metal oxide, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The deposition is usually done at room temperature. A collimator with an aspect ratio of 1˜5 can be used to improve the fill-in performance. To improve the fill-in performance, a DC bias of several ten to several hundred volts is also used. If desired, the combination of DC bias and the collimator can be used simultaneously. 
     The post deposition annealing treatment with vacuum or N 2  ambient or O 2 /N 2  mixed ambient is sometimes needed to improve the oxygen distribution of metal oxide. The annealing temperature ranges 400 C to 600 C with an anneal time of less than 2 hours. 
     C. Oxidation: By a high temperature oxidation system, such as furnace or RTP system. The temperature ranges from 200 C to 700 C with pure O 2  or N 2 /O 2  mixed gas at a pressure of several mtorr to 1 atm. The time can range several minute to hours. Another oxidation method is plasma oxidation. An RF or a DC source plasma with pure O 2  or Ar/O 2  mixed gas or Ar/N 2 /O 2  mixed gas at a pressure of 1 mtorr to 100 mtorr is used to oxidize the surface of metal, such as Ni, Ti, Al, W, Zn, Zr, or Cu etc. The oxidation time ranges several seconds to several minutes. The oxidation temperature ranges room temperature to 300 C, depending on the degree of plasma oxidation. 
     4. Polymer Material
         TCNQ with doping of Cu, C 60 , Ag etc.   PCBM-TCNQ mixed polymer   Formation method:       

     A. Evaporation: By thermal evaporation, e-beam evaporation, or molecular beam epitaxy (MBE) system. A solid-state TCNQ and dopant pellets are co-evaporated in a single chamber. The solid-state TCNQ and dopant pellets are put in a W-boat or a Ta-boat or a ceramic boat. A high electrical current or an electron-beam is applied to melt the source so that the materials are mixed and deposited on wafers. There are no reactive chemistries or gases. The deposition is done at a pressure of 10-4 torr to 10-10 torr. The wafer temperature ranges from room temperature to 200 C. 
     The post deposition annealing treatment with vacuum or N 2  ambient is sometimes needed to improve the composition distribution of polymer material. The annealing temperature ranges room temperature to 300 C with an anneal time of less than 1 hour. 
     B. Spin-coat: By a spin-coater with the doped-TCNQ solution @ the rotation of less than 1000 rpm. After spin-coating, the wafer is put to wait the solid-state formation @ room temperature or temperature of less than 200 C. The waiting time ranges from several minutes to days, depending on the temperature and on the formation conditions. 
       FIG. 3  is a graph  300  of voltage and temperature versus time for pulses used for programming programmable resistive memory cells, according to one embodiment of the present invention. As explained above, in phase change memory, data is stored by causing transitions between amorphous and crystalline states in the phase change material using current. Current heats the phase change material and causes transitions between the states.  FIG. 3  describes the electrical pulses used to cause the transitions. Specifically,  FIG. 3  describes the bias voltages that are applied to bit lines and word lines of a memory cell. The y-axis of graph  300  indicates the magnitude of the bias voltage applied to a phase change material, as well as the temperature to which the phase change material is heated by each pulse. The x-axis of graph  300  indicates the passage of time as the voltage applied to a phase change material and as the temperature of the phase change material increases and decrease over time. 
     Line  302  indicates the beginning of a RESET pulse  312 , which converts a phase change material into an amorphous, high resistance state. The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt the crystalline structure, after which the phase change material cools quickly, quenching the phase change process, allowing at least a portion of the phase change structure to stabilize in the amorphous state. Line  304  indicates the temperature at which the phase change material transforms into an amorphous state. Note that pulse  312  increases the temperature past line  304 . The quenching phase is indicated by the set of lines  308 , wherein the phase change process that transforms the phase change material from crystalline to amorphous is quenched or supplied with the appropriate energy. 
     Line  316  indicates the beginning of a SET pulse  314 , which converts a phase change material into a crystalline, low resistance state. The change from the amorphous to the crystalline state is generally a longer pulse but a lower current operation. Line  306  indicates the temperature at which the phase change material transforms into a crystalline state, sometimes called a breakdown transformation, which is lower than the temperature for a amorphous state, indicated by line  304 . Note that pulse  314  increases the temperature past line  304 . Also shown is interim  310 , which indicates the wait time that must be tolled between the activation of SET pulse  314  after the RESET pulse  312  completes the quench process. Line  306  corresponds to the threshold voltage of the phase change elements  46 - 52 , discussed in more detail below, above which the bit line voltage is set to achieve set pulse  314 . 
       FIG. 4  is a flowchart showing the control flow of a general process for programming a single memory cell comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 4  describes that process that takes place when a controller, such as controller  34 , programs (that is, sets or resets) a single memory cell of a phase change memory device comprising a plurality of memory cells.  FIG. 4  begins with step  402  and proceeds directly to step  404 . In step  404 , the resistance of the memory cell is read. In step  406 , input data, representing the data that must be reflected by the state of the memory cell, is read. In step  408 , it is determined whether the resistance of the memory cell is in a state that reflects the input data. For example, if the resistance of the memory cell is high and the input data indicates a “0,” or if the memory cell is low and the input data indicates a “1,” then the resistance of the memory cell is in a state that reflects the input data. Otherwise, the resistance of the memory cell is not in a state that reflects the input data. 
     If the result of step  408  is positive, then control flows to step  410 . If the result of step  408  is negative, then control flows to step  412 . In step  412 , the memory cell is either set or reset, depending on the programming process that is taking place. In step  410 , the programming process of the flowchart of  FIG. 4  ends. 
       FIG. 5  is a flowchart showing the control flow of the process for programming a single memory cell comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 5  describes that process that takes place when a controller, such as controller  34 , programs (that is, sets or resets) a single memory cell of a phase change memory device comprising a plurality of memory cells.  FIG. 5  provides more detail for the general process described by the flowchart of  FIG. 4 . 
       FIG. 5  begins with step  502  and proceeds directly to step  504 . In step  504 , the resistance of a memory cell at an address is read. In one embodiment of the present invention, the reading step comprises applying a voltage to a bit line coupled to the memory cell and applying a voltage to a word line coupled to an access device, the access device being coupled to the memory cell. If the result of step  504  is that a high resistance is read, indicating the memory cell is in an at least partial amorphous state, then control flows to step  506 . If the result of step  504  is that a low resistance is read, indicating the memory cell is in a crystalline state, then control flows to step  508 . 
     In step  506 , input data, representing the data that must be reflected by the state of the memory cell, is read. In one embodiment of the present invention, this reading step comprises receiving input data, such as from an input buffer, and evaluating a value of the input data. The input data can be, for example, a single bit value indicating a “0” or a “1.” If the result of step  506  is that a first bit value is read, indicating a “0,” then control flows to step  510 . If the result of step  504  is that a second bit value is read, indicating a “1,” then control flows to step  512 . 
     In step  512 , the memory cell is set. In an embodiment of the present invention, the step of setting the memory cell comprises applying bias voltages to the bit line and the word line of the memory cell so as to change the memory cell to a crystalline, low resistance state. This step takes place using a lower current via the bit line. This is described in greater detail above with reference to  FIG. 3 . 
     In step  508 , input data, representing the data that must be reflected by the state of the memory cell, is read. If the result of step  508  is that a first bit value is read, indicating a “0,” then control flows to step  514 . If the result of step  508  is that a second bit value is read, indicating a “1,” then control flows to step  510 . 
     In step  514 , the memory cell is reset. In an embodiment of the present invention, the step of resetting the memory cell comprises applying bias voltages to the bit line and the word line of the memory cell so as to change the memory cell to an amorphous, high resistance state. This is described in greater detail above with reference to  FIG. 3 . In step  510 , the programming process of the flowchart of  FIG. 5  ends. 
       FIG. 6  is a flowchart showing the control flow of the process for sequentially programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 6  describes that process that takes place when a controller, such as controller  34 , sequentially programs (that is, sets or resets) a plurality of memory cells of a phase change memory device. The process of  FIG. 6  is the extension of the process of  FIG. 5  to a plurality of memory cells. 
       FIG. 6  begins with step  601  and proceeds directly to step  602 . In step  602 , the programming sequence moves to the next available memory cell that is slated for programming in a plurality of memory cells that will be programmed. In step  604 , the resistance of a memory cell at an address is read. If the result of step  604  is that a high resistance is read, indicating the memory cell is in an at least partial amorphous state, then control flows to step  606 . If the result of step  604  is that a low resistance is read, indicating the memory cell is in a crystalline state, then control flows to step  608 . 
     In step  606 , input data, representing the data that must be reflected by the state of the memory cell, is read. In one embodiment of the present invention, this reading step comprises receiving input data, such as from the input buffer, and evaluating a value of the input data. The input data can be, for example, a single bit value indicating a “0” or a “1.” If the result of step  606  is that a first bit value is read, indicating a “0,” then control flows to step  610 . If the result of step  604  is that a second bit value is read, indicating a “1,” then control flows to step  612 . 
     In step  612 , the memory cell is set. In step  608 , input data, representing the data that must be reflected by the state of the memory cell, is read. If the result of step  608  is that a first bit value is read, indicating a “0,” then control flows to step  614 . If the result of step  608  is that a second bit value is read, indicating a “1,” then control flows to step  610 . 
     In step  614 , the memory cell is reset. In step  610 , it is determined whether there are any additional memory cells that are slated for programming in a plurality of memory cells that will be programmed. If the result of step  610  is negative, then control flows to step  616 . If the result of step  610  is positive, then control flows to step  602 , where the process of the flowchart of  FIG. 6  continues until all memory cells slated for programming have been programmed. In step  616 , the programming process of the flowchart of  FIG. 6  ends. 
       FIG. 7  is a flowchart showing the control flow of the process for group programming of a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 7  describes that process that takes place when a controller, such as controller  34 , programs (that is, sets or resets) a plurality of memory cells of a phase change memory device using a grouping method. 
       FIG. 7  begins with step  702  and proceeds directly to step  704 . In step  704 , the controller initiates a group set method wherein a set function is sequentially applied to each memory cell in a group of memory cells. The group set method is described in greater detail below with reference to  FIG. 9 . In step  706 , the controller initiates a group reset method wherein a reset function is sequentially applied to each memory cell in the group of memory cells. The group reset method is described in greater detail below with reference to  FIG. 10 . In step  708 , the process of the flowchart of  FIG. 7  ends. 
       FIG. 8  is a flowchart showing the control flow of the process for group programming of a plurality of memory cells comprising a phase change material, in accordance with another embodiment of the present invention. Like the flowchart of  FIG. 7 , the flowchart of  FIG. 8  describes that process that takes place when a controller, such as controller  34 , programs (that is, sets or resets) a plurality of memory cells of a phase change memory device using a grouping method.  FIG. 8  begins with step  802  and proceeds directly to step  804 . In step  804 , the controller initiates a group reset method wherein a reset function is sequentially applied to each memory cell in a group of memory cells. The group reset method is described in greater detail below with reference to  FIG. 10 . In step  806 , the controller initiates a group set method wherein a set function is sequentially applied to each memory cell in the group of memory cells. The group set method is described in greater detail below with reference to  FIG. 9 . In step  808 , the process of the flowchart of  FIG. 8  ends. 
       FIG. 9  is a flowchart showing the control flow of the group set process for programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 9  describes that process that takes place when a controller, such as controller  34 , sequentially applies a set process to a group of memory cells in a phase change memory device.  FIG. 9  begins with step  902  and proceeds directly to step  904 . In step  904 , the programming sequence moves to the next available memory cell in the group of memory cells to which the group set method is being applied. 
     In step  906 , the resistance of a memory cell at an address is read. If the result of step  906  is that a high resistance is read, indicating the memory cell is in an at least partial amorphous state, then control flows to step  908 . If the result of step  906  is that a low resistance is read, indicating the memory cell is in a crystalline state, then control flows to step  910 . 
     In step  908 , input data, representing the data that must be reflected by the state of the memory cell, is read. The input data can be, for example, a single bit value indicating a “0” or a “1.” If the result of step  908  is that a first bit value is read, indicating a “0,” then control flows to step  910 . If the result of step  908  is that a second bit value is read, indicating a “1,” then control flows to step  912 . In step  912 , the memory cell is set. 
     In step  910 , it is determined whether the current memory cell is the last memory cell in the group of memory cells to which the group set method is being applied. If the result of step  910  is negative, then control flows to step  904 , where the process of the flowchart of  FIG. 9  continues until all memory cells in the group have experienced the group set method. If the result of step  910  is positive, then control flows to step  914 , where the group set process of the flowchart of  FIG. 9  ends. 
       FIG. 10  is a flowchart showing the control flow of the group reset process for programming a plurality of memory cells comprising a phase change material, in accordance with one embodiment of the present invention Specifically, the flowchart of  FIG. 10  describes that process that takes place when a controller, such as controller  34 , sequentially applies a reset method to a group of memory cells in a phase change memory device.  FIG. 10  begins with step  1002  and proceeds directly to step  1004 . In step  1004 , the programming sequence moves to the next available memory cell in the group of memory cells to which the group reset process is being applied. 
     In step  1006 , the resistance of a memory cell at an address is read. If the result of step  1006  is that a high resistance is read, indicating the memory cell is in an at least partial amorphous state, then control flows to step  1010 . If the result of step  1006  is that a low resistance is read, indicating the memory cell is in a crystalline state, then control flows to step  1008 . 
     In step  1008 , input data, representing the data that must be reflected by the state of the memory cell, is read. The input data can be, for example, a single bit value indicating a “0” or a “1.” If the result of step  1008  is that a first bit value is read, indicating a “0,” then control flows to step  1012 . If the result of step  1008  is that a second bit value is read, indicating a “1,” then control flows to step  1010 . In step  1012 , the memory cell is reset. 
     In step  1010 , it is determined whether the current memory cell is the last memory cell in the group of memory cells to which the group reset method is being applied. If the result of step  1010  is negative, then control flows to step  1004 , where the process of the flowchart of  FIG. 10  continues until all memory cells in the group have experienced the group reset method. If the result of step  1010  is positive, then control flows to step  1014 , where the group reset process of the flowchart of  FIG. 10  ends. 
       FIG. 11  is a flowchart showing the control flow of the process for reset programming a memory cell comprising a phase change material, in accordance with one embodiment of the present invention. Specifically, the flowchart of  FIG. 11  describes that process that takes place when a controller, such as controller  34 , reset programs a memory cell of a phase change memory device comprising a plurality of memory cells. 
       FIG. 11  begins with step  1102  and proceeds directly to step  1104 . In step  1104 , the resistance of a memory cell at an address is read. In one embodiment of the present invention, the reading step may comprise applying a voltage to a word line coupled to an access device, such as a pair of MOSFETs, the access device being coupled to the memory cell. The access device further has a threshold voltage (referred to as “VtMOSFET” in  FIG. 11 ). 
     If the result of step  1104  is that a high resistance is read, indicating the memory cell is in an at least partial amorphous state, then control flows to step  1106 . If the result of step  1104  is that a low resistance is read, indicating the memory cell is in a crystalline state, then control flows to step  1108 . In step  1106 , the reset programming process ends. In step  1108 , the memory cell is reset. In an embodiment of the present invention, the step of resetting the memory cell comprises applying bias voltages to the bit line and the word line of the memory cell so as to change the memory cell to an amorphous, high resistance state. This step takes place using a higher current, which includes a short high current density pulse to melt the crystalline structure into an amorphous state. Specifically, the voltage applied to the bit line (referred to as “Vbl” in  FIG. 11 ) is greater than the threshold voltage of the memory element (referred to as “Vtcell” in  FIG. 11 ) and the voltage V applied to the word line is greater than the access device threshold voltage. 
     In step  1110 , the resistance of the memory cell is read again, as described for step  1104  above. If the result of step  1110  is that a high resistance is read, then control flows to step  1106 . If the result of step  1110  is that a low resistance is read, then control flows to step  1112 . In step  1112 , the memory cell is reset once more. In this step, the voltage V is increased by an amount (referred to as “ε” in  FIG. 11 ) and then a voltage greater than the memory element threshold voltage is applied to the bit line and the increased voltage V is applied to the word line. Control then flows back to step  1110  where the process of checking the resistance of the memory cell (step  1110 ), increasing the word line voltage V (step  1112 ) and applying the voltage V to the word line (step  1112 ) is executed until the resistance of the memory cell is high, indicating an amorphous state of the memory cell. 
     While the present invention is disclosed by reference to the preferred embodiments and examples detailed above, it is to be understood that these examples are intended in an illustrative rather than in a limiting sense. It is contemplated that modifications and combinations will occur to those skilled in the art, which modifications and combinations will be within the spirit of the invention and the scope of the following claims. Any and all patents, patent applications and printed publications referred to above are hereby incorporated by reference.