Patent Publication Number: US-2022224229-A1

Title: Power converter

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     Under 35 USC 120, this application is a divisional of U.S. application Ser. No. 15/590,562, filed May 9, 2017, which under 35 USC 119, claims the benefit of the priority date of U.S. Provisional Application 62/333,432, filed on May 9, 2016 and U.S. Provisional Application 62/333,402, filed on May 9, 2016, and under 35 USC 120, this application is a continuation-in-part of U.S. application Ser. No. 15/138,692, filed on Apr. 26, 2016, which is a continuation of Ser. No. 14/513,747, filed on Oct. 14, 2014, which is a continuation of U.S. application Ser. No. 13/771,904, filed on Feb. 20, 2013 and issued as U.S. Pat. No. 8,860,396 on Oct. 14, 2014, which is a continuation of international application PCT/US2012/036455, filed on May 4, 2012, which, under 35 USC 119, claims the benefit of the priority dates of U.S. Provisional Application No. 61/482,838, filed May 5, 2011, U.S. Provisional Application No. 61/548,360, filed Oct. 18, 2011, and U.S. Provisional Application No. 61/577,271, filed Dec. 19, 2011, the contents of which are all incorporated herein by reference. 
    
    
     FIELD OF INVENTION 
     This disclosure relates to power supplies, and in particular to power converters. 
     BACKGROUND 
     Many power converters include switches and one or more capacitors that are used, for example, to power portable electronic devices and consumer electronics. Switch-mode power converters regulate the output voltage or current by switching energy storage elements (i.e. inductors and capacitors) into different electrical configurations using a switch network. 
     Switched-capacitor converters are switch-mode power converters that primarily use capacitors to transfer energy. These converters transfer energy from an input to an output by using switches to cycle a network of capacitors through different topological states. A common converter of this type, known as a “charge pump,” is commonly used to produce the high voltages in FLASH memories and other reprogrammable memories. Charge pumps have also been used in connection with overcoming the nuclear strong force to transform one element into another. 
     In a switched-capacitor converter, the number of capacitors and switches increases as the transformation ratio increases. Switches in the switch network are usually active devices that are implemented with transistors. The switch network may be integrated on a single or on multiple monolithic semiconductor substrates, or formed using discrete devices. Furthermore, since each switch in a power converter normally carries high current, it may be composed of numerous smaller switches connected in parallel. 
     SUMMARY 
     Typical DC-DC converters perform voltage transformation and output regulation. This is usually done in a single-stage converter such as a buck converter. However, it is possible to split these two functions into two specialized stages, namely a transformation stage, such as a switching network, and a separate regulation stage, such as a regulating circuit. The transformation stage transforms one voltage into another, while the regulation stage ensures that the voltage and/or current output of the transformation stage maintains desired characteristics. 
     In those cases where the transformation stage and the regulating stage are close together, a direct connection is possible. However, in other cases, the regulating stage may be far from the transformation stage. Under these circumstances, it is useful to filter the output of the transformation stage to reduce loss. 
     In one aspect, the invention features a transformation stage for transforming a first voltage into a second voltage. Such a transformation stage includes a switching network, a filter, and a controller. The filter is configured to connect the transformation stage to a regulator, and the controller controls the switching network. 
     In some embodiments, the filter includes an LC filter. 
     In other embodiments, the filter includes an inductance that, in operation at a particular switching frequency, sustains a peak-to-peak voltage ripple and supports an inductor current that passes into a load, the inductor current defining an average inductor current. Among these are embodiments in which the inductance is selected by dividing the peak-to-peak voltage ripple by a product of the average inductor current and the switching frequency multiplied by 13/24. 
     Some embodiments include the regulating circuit. 
     Also among the embodiments are those in which the filter is configured to connect the transformation stage to more than one regulator. 
     Yet other embodiments include plural regulating circuits, wherein the filter connects the transformation stage to all of the regulators. 
     Also among the embodiments are those in which the transformation stage includes plural switching networks. In these embodiments, the filter connects to all of the switching networks to a regulating circuit. 
     Other embodiments include those in which the transformation stage includes a plurality of units in series. Each unit includes a switching network in series with a filter. 
     Typical DC-DC converters perform voltage transformation and output regulation. This is usually done in a single-stage converter such as a buck converter. However, it is possible to split these two functions into two specialized stages, namely a transformation stage, such as a switching network, and a separate regulation stage, such as a regulating circuit. The transformation stage transforms one voltage into another, while the regulation stage ensures that the voltage and/or current output of the transformation stage maintains desired characteristics. 
     In those cases where the transformation stage and the regulating stage are close together, a direct connection is possible. However, in other cases, the regulating stage may be far from the transformation stage. Under these circumstances, it is useful to filter the output of the transformation stage to reduce loss. 
     In one aspect, the invention includes an apparatus having phase and stack switches for operating a switched-capacitor converter. The phase and stack switches are on respective first and second dies. 
     Some embodiments include a first controller that controls the switches on the first die and a second controller that controls switches on the second die. An inter-controller commissure provides a link between the first and second controllers to permit operation of the first switches to depend at least in part on operation of the second switches, and to permit operation of the second switches to depend at least in part on operation of the first switches. Among these are embodiments in which the first controller is on the first die, the second controller is on the second die, and the inter-controller commissure extends between the first die and the second die. Also among the embodiments are those that include a third die and a fourth die. In these embodiments, the first controller is on the third die, the second controller is on the fourth die, and the inter-controller commissure extends between the third die and the fourth die. 
     In some embodiments, the switched-capacitor converter is a two-phase converter. Some of these embodiments have third and fourth dies. The stack switches comprise first and second sets, each of which is associated with one of the two phases. The first set of stack switches is on the second die and the second set of stack switches is on the fourth die. Meanwhile, the phase switches comprise first and second sets of phase switches, each of which is associated with one of the two phases. The first set of phase switches is on the first die and the second set of phase switches is on the third die. 
     Also among the embodiments are those that include charge-transfer capacitors connected to the stack switches and to the phase switches. Among these are embodiments having a third die in which the charge-transfer capacitors are integrated. Also among these are embodiments in which the charge-transfer capacitors are discrete capacitors that connect to the first and second dies. In some of these embodiments, the first die and the second die are connected via an inter-die commissure having a length that corresponds to a distance between positive and negative terminals of the charge-transfer capacitors. Also among the embodiments are those that have an interdie commissure connecting the first and second dies, wherein the first and second dies have first terminals for connection to positive terminals of the charge-transfer capacitors, and second terminals for connection to negative terminals of the charge-transfer capacitors, with the first and second terminals and the second terminals being disposed on opposite ends of the interdie commissure, and with the charge-transfer capacitors being oriented such that positive terminals thereof lie closer to the first terminals than they do to the second terminals and negative terminals thereof lie closer to the second terminals than to the first terminals. Also among the embodiments are those in which interdie commissure has first and second regions such that, during operation, the first region carries more current than the second region. In these embodiments, the first region is wider than the second region. 
     In some embodiments, the charge-transfer capacitors have capacitances that are a function of voltage applied across the charge-transfer capacitors. In operation, the charge-transfer capacitors sustain different maximum voltages. The charge-transfer capacitors are selected such that, when at their respective maximum voltages, the charge-transfer capacitors all have the same capacitance. 
     Some embodiments include an interdie commissure connecting the first and second dies. As a result of a fold in the interdie commissure, the first and second dies lie on different planes. Other embodiments feature coplanar first and second dies. 
     Embodiments include those in which the switched-capacitor converter is a multi-phase converter, and the apparatus has a third die. In these embodiments, the phase switches comprise a first set of phase switches associated with a first phase and a second set of phase switches associated with a second phase, with the first set being on the first die and the second set on the second die. Among these are embodiments that have first and second sets of charge-transfer capacitors, with the first set of charge-transfer capacitors being connected between the first die and the second die, and the second set of charge-transfer capacitors being connected between the third die and the second die. 
     Other embodiments include a substrate and charge-transfer capacitors. In these embodiments, the substrate supports the charge-transfer capacitors, the first die, and the second die. Among these are embodiments in which the device faces of the first and second dies face the substrate, and conducting bumps between the device face and the substrate provide electrical communication between the dies and the charge-transfer capacitors. Also among these are embodiments that have a package, with the first and second dies being in the package and oriented so that they are either coplanar or non-coplanar. 
     Other embodiments include a substrate, a package, a third die, and charge-transfer capacitors. In these embodiments, the charge-transfer capacitors are integrated into the third die, the substrate supports the package, the package includes the first die, the second die, and the third die, and the first, second, and third dies are distributed among different layers of the package. Among these are embodiments in which the package comprises a first layer and a second layer. In these embodiments, the first and second dies are in the first layer and the third die is in the second layer. Also among these are embodiments in which the package comprises a first layer and a second layer. In these embodiments, the first and third dies are in the first layer and the second die is in the second layer. Also among these are embodiments in which the package comprises a first layer, a second layer, and a third layer. In these embodiments, each layer contains at most one die. In some of these embodiments, the second layer is between the first and third layers, and the third die is in the second layer. 
     Some embodiments include a substrate that supports a package. The package has an upper layer and a lower layer, with the lower layer being closer to the substrate than the upper layer. The lower layer contains a die and the upper layer contains charge-transfer capacitors. The inductor is on the substrate outside the package. Among these are embodiments in which the die&#39;s device face faces the substrate. The apparatus further includes first and second interconnect layers, and electrically conducting bumps. The first interconnect layer connects the charge-transfer capacitors to the die, and the second interconnect layer connects the die to the charge-transfer capacitors and to the electrical bumps. The electrical bumps connect the package with the inductor. 
     Also among these are embodiments in which a device face of the die faces away from the substrate. These embodiments include a heat sink, thermally-conducting bumps, a first interconnect layer, a second interconnect layer, and electrically-conducting bumps. The first interconnect layer connects the charge-transfer capacitors to the die. The second interconnect layer connects the die to the charge-transfer capacitors and to the electrically-conducting bumps. The electrically-conducting bumps connect the package with the inductor. In these embodiments, the heat sink faces the substrate, and the thermally-conducting bumps connect the heat sink to the substrate. These thermally-conducting bumps carry only heat. They are electrically disconnected from the circuit. 
     Also among these are embodiments in which a device face of the die faces away from the substrate. In these embodiments, a first interconnect layer connects charge-transfer capacitors to the die, and a second interconnect layer connects the die to the charge-transfer capacitors and to electrically conducting pads. The electrically conducting pads connect the package with the inductor. The thermally-conducting pad connects the heat sink, which faces the substrate, to the substrate. This thermally-conducting pad carries only heat. It is electrically isolated from the inductor, the charge-transfer capacitor, and the die. 
     Other embodiments also include a substrate that supports a package having upper and lower layers, with the lower layer being closer to the substrate that the upper layer. The inductor is in the package. The lower layer contains a die and upper layer contains charge-transfer capacitors are in the upper layer. Among these are embodiments in which the inductor is disposed in the upper layer. Also among these embodiments are those in which conductive traces around an inductor core in the layer form the inductor. 
     Among the foregoing embodiments are those in which a device face of the chip faces away from the substrate. In these embodiments, thermally-conducting bumps connect a heat sink to the substrate. These thermally-conducting bumps only carry heat. They are electrically isolated from the die, the charge-transfer capacitors, and the inductor. 
     Yet other embodiments include regulator switches in the first die. 
     These and other features of the invention will be apparent from the following detailed description and the accompanying figures, in which: 
    
    
     
       DESCRIPTION OF THE FIGURES 
         FIG. 1  shows a power converter with a separable transformation stage and regulation stage; 
         FIG. 2  shows a power converter similar to that shown in  FIG. 1  but with an isolated transformation stage; 
         FIGS. 3 to 10  show different ways of connecting transformation and regulation stages; 
         FIG. 11  shows a DC-DC converter with a separate regulating circuit and switching network; 
         FIG. 12  shows a power converter with a filter between the switching network and the regulation stage; 
         FIG. 13  shows the power converter of  FIG. 12  but without the regulation stage; 
         FIG. 14  explicitly shows control circuitry associated with a converter as shown in  FIG. 11 ; 
         FIG. 15  shows details of the control circuitry shown in  FIG. 14 ; 
         FIG. 16  shows signals present during operation of the control circuitry of  FIG. 15 ; 
         FIG. 17  is a close-up of four signals from  FIG. 12  showing the dead-time interval; 
         FIG. 18  shows details of switch layout in a converter similar to that shown in  FIG. 1 ; 
         FIGS. 19 and 20  show dependence of switching period and peak-to-peak ripple as a function of output load current in two embodiments of the control circuitry as shown in  FIG. 14 ; 
         FIG. 21  shows a multi-phase converter similar to that shown in  FIG. 14 ; 
         FIGS. 22 and 23  show signals present during operation of the control circuitry of  FIG. 21 ; 
         FIG. 24  shows another power converter similar to that shown in  FIG. 14  but with one regulator and plural switching networks; 
         FIG. 25  shows another power converter similar to that shown in  FIG. 14  but with one switching network and plural regulators; 
         FIG. 26  shows a power converter similar to that shown in  FIG. 25  but with a filter between the switching network and the regulators; 
         FIG. 27  shows a power converter similar to that shown in  FIG. 24  but with a filter between the switching networks and the regulator; 
         FIG. 28  shows a bidirectional version of  FIG. 11 ; 
         FIGS. 29-30  show DC-DC converters with alternate configurations of regulating circuits and switching networks; 
         FIG. 31  shows a DC-DC converter like that shown in  FIG. 30  with a controller; 
         FIG. 32  shows another configuration of a DC-DC converter; 
         FIG. 33  shows a particular implementation of the power converter illustrated in  FIG. 32 ; 
         FIG. 34  shows an embodiment with multiple regulating circuits; 
         FIG. 35  shows an RC circuit; 
         FIG. 36  shows a model of a switched capacitor DC-DC converter; 
         FIG. 37  shows an isolated variant of  FIG. 36 ; 
         FIG. 38  shows output resistance of a switched-capacitor network as a function of switching frequency; 
         FIGS. 39-40  show a series-parallel SC converter operating in charge phase and discharge phase respectively; 
         FIG. 41  shows a series pumped symmetric cascade multiplier with diodes; 
         FIG. 42  shows a parallel pumped symmetric cascade multiplier with diodes; 
         FIG. 43  shows charge pump signals; 
         FIG. 44  shows a two-phase symmetric series pumped cascade multiplier with switches; 
         FIG. 45  shows a two-phase symmetric parallel pumped cascade multiplier with switches; 
         FIG. 46  shows four cascade multipliers along with corresponding half-wave versions; 
         FIG. 47  shows the circuit of  FIG. 35  with an auxiliary converter used to reduce loss associated with charging a capacitor; 
         FIG. 48  shows an implementation of the circuit of  FIG. 47 ; 
         FIG. 49  shows a cascade multiplier with clocked current sources; 
         FIG. 50  shows output impedance of a switched-capacitor converter as a function of frequency; 
         FIGS. 51, 52, and 53  show clocked current sources; 
         FIG. 54  shows a cascade multiplier with the clocked current source of  FIG. 52 ; 
         FIG. 55  shows an embodiment of the circuit shown in  FIG. 54 ; 
         FIG. 56  shows current and voltage at selected locations in the circuit of  FIG. 55 ; 
         FIG. 57  shows a particular implementation of the DC-DC converter illustrated in  FIG. 28  with a full-wave adiabatically charged switching network; 
         FIG. 58  shows the DC-DC converter illustrated in  FIG. 54  during phase A; 
         FIG. 59  shows the DC-DC converter illustrated in  FIG. 54  during phase B; 
         FIG. 60  shows various waveforms associated with a 4:1 adiabatically charged converter; 
         FIG. 61  shows adiabatic charging of series connected stages; 
         FIG. 62  shows a particular implementation of the power converter illustrated in  FIG. 61 ; 
         FIG. 63  shows adiabatic charging of series connected stages with filters between each stage; 
         FIG. 64  shows a particular implementation of the power converter illustrated in  FIG. 63 ; 
         FIG. 65  shows an AC-DC power converter architecture; 
         FIG. 66  shows an AC voltage rectified using a reconfigured switched-capacitor stage; 
         FIG. 67  shows an embodiment of the AC-DC power converter architecture in  FIG. 65 , which includes an AC switching network; 
         FIG. 68  shows a particular implementation of the AC-DC converter illustrated in  FIG. 67 ; 
         FIGS. 69-70  shows the AC-DC converter in  FIG. 68  during the positive and negative portions of the AC cycle respectively; 
         FIG. 71  shows an AC-DC power converter architecture with power-factor correction; 
         FIG. 72  shows a converter having an isolated controller; 
         FIG. 73  shows an alternative architecture of the converter in  FIG. 72  where the switching network is loaded by an LC filter; 
         FIG. 74  shows a converter in which a control signal for the regulating circuit is isolated from a control signal for the switching network; 
         FIG. 75  shows a configuration of  FIG. 29  with an isolated controller as shown in  FIG. 74 ; 
         FIG. 76  shows a configuration of  FIG. 32  with an isolated controller as shown in  FIG. 74 ; 
         FIG. 77  shows an implementation of the rectifier shown in  FIG. 65 ; 
         FIG. 78  shows an alternative implementation of the rectifier shown in  FIG. 65 ; 
         FIG. 79  shows an EMI filter from the rectifiers shown in  FIGS. 77 and 78 ; 
         FIG. 80  shows an alternative EMI filter from the rectifiers shown in  FIGS. 77 and 78 ; 
         FIG. 81  shows an AC bridge for use in the embodiments shown in  FIGS. 77 and 78 ; 
         FIG. 82  shows one transformation stage driving two parallel regulation stages; 
         FIG. 83  shows a transformation stage providing filtered output to parallel regulating stages; 
         FIGS. 84 and 85  show implementations of the DC-DC converter illustrated in  FIG. 28 ; 
         FIGS. 86 and 87  show implementations of the DC-DC converter illustrated in  FIG. 30 ; 
         FIGS. 88 and 89  show implementations of the DC-DC converter illustrated in  FIG. 29 ; 
         FIGS. 90 and 91  show implementations of the DC-DC converter illustrated in  FIG. 32 ; 
         FIG. 92  shows a switching network implemented as a stack of layers; 
         FIGS. 93-96  are cross-sections of the stack in  FIG. 92  with different orders of passive and active layers; 
         FIGS. 97-100  show different locations of active and passive device faces for the two-layer stack shown in  FIG. 93 ; 
         FIGS. 101-104  show different locations of active and passive device faces for the two-layer stack shown in  FIG. 94 ; 
         FIG. 105  shows an implementation of  FIG. 93  in which the passive device layer has a planar capacitor; 
         FIG. 106  shows an implementation of  FIG. 93  in which the passive device layer has a trench capacitor; 
         FIG. 107  shows an implementation of  FIG. 105  with wafer-to-wafer bonding instead of die-to-die bonding; 
         FIG. 108  shows an implementation of  FIG. 107  but with the device face of the active layer being its upper face instead of its lower face; 
         FIG. 109  shows three partitioned current paths of a switching network; 
         FIG. 110  shows an active layer with eight switches superimposed on eight capacitors on a passive layer below it; 
         FIG. 111  shows one of the switches in  FIG. 110  that has been partitioned into nine partitions; 
         FIG. 112  shows a divided switching but not partitioned switch and capacitor; 
         FIG. 113  shows a partitioned switch and capacitor; 
         FIG. 114  shows a capacitor partitioned in two dimensions; 
         FIG. 115  is a functional block diagram of one embodiment of the switching network shown in  FIGS. 13 and 12 ; 
         FIG. 116  shows an exemplary circuit of the switching network shown in  FIG. 115 ; 
         FIG. 117  shows a particular terminal layout for implementation of the switching network shown in  FIG. 115 ; 
         FIG. 118  is a functional block diagram of another embodiment of the switching network shown in  FIGS. 13 and 12 ; 
         FIG. 119  shows an exemplary circuit of the switching network shown in  FIG. 118 ; 
         FIG. 120  shows a particular terminal layout for implementation of the switching network shown in  FIG. 118 ; 
         FIG. 121  shows the terminal layout for the phase-die in  FIG. 120  with the locations of the phase switches in  FIG. 119  explicitly shown therein; 
         FIG. 122  is a functional block diagram of another embodiment of the switching network shown in  FIGS. 13 and 12 , but the inclusion of switches for a regulator to which the switching network is to be connected; 
         FIG. 123  shows a substrate bearing components for implementing a switching network; 
         FIG. 124  shows the phase die and stack die of  FIG. 123  within the same package; 
         FIG. 125  shows a stacked phase die and stack die; 
         FIG. 126  shows the circuit of  FIG. 124  but with the charge-transfer capacitors now being on their own capacitor die and included on their own layer in the package. 
         FIG. 127  shows the circuit of  FIG. 124  but with the charge-transfer capacitors now being on their own capacitor die, included in the package, and occupying the same layer as the phase die. 
         FIG. 128  shows a package in which the charge-transfer capacitor die is sandwiched between the phase die and the stack die; and 
         FIGS. 129-133  show embodiments of a circuit that also includes an inductor. 
     
    
    
     DETAILED DESCRIPTION 
     Some power converters carry out both regulation and transformation with a limited number of circuit components by comingling these functions into a single stage. As a result, certain components are used both for regulation and transformation. Sometimes the regulation stage is referred to as a regulating circuit and the transformation stage is referred to as a switching network. As used herein, these terms mean the same thing. 
       FIG. 1  shows a modular multi-stage power converter that separates the converter&#39;s transformation and regulation functions. These functions are no longer accomplished together as they would be in a single-stage converter design. As a result, in a multi-stage power converter, as shown in  FIG. 1 , it is possible to optimize a transformation stage and a regulation stage for their specific functions. The transformation stage and the regulation stage can be treated as either independent entities or coupled entities. 
     In the power converter of  FIG. 1 , a transformation stage receives an input voltage V IN  across its two input terminals and outputs an intermediate voltage V X  across its two output terminals at a fixed voltage conversion ratio. Therefore, the intermediate voltage V X  changes in response to changes in the input voltage V IN . The transformation stage is thus regarded as “variable” if the voltage conversion ratio can be varied. However, it is not required that a transformation stage be “variable”. 
     In the particular embodiment shown in  FIG. 1 , there exists an electrical connection between the transformation stage&#39;s negative input terminal and its negative output terminal. In this configuration, the transformation stage is said to be “non-isolated.” In contrast, the embodiment shown in  FIG. 2 , no such connection exists between the transformation stage&#39;s negative input and its negative output. An example of such a transformation stage is shown in  FIG. 37  with a voltage conversion ratio of N 1 :N 2 . 
     In general, two functional components of a circuit or system are said to be isolated, in a galvanic sense, if no direct conduction path exists between those two components, and yet energy and information can still be communicated between those components. The communication of such energy and information can be carried out in a variety of ways that do not require actual current flow. Examples include communication via waves, whether electromagnetic, mechanical, or sonic. Electromagnetic waves in this context include waves in the visible range, as well as just outside the visible range. Such communication can also be implemented via static or quasi-static electric or magnetic fields, capacitively, inductively, or by mechanical means. 
     Galvanic isolation is particularly useful for cases in which the two functional components have grounds that are at different potentials. Through galvanic isolation of components, it is possible to essentially foreclose the occurrence of ground loops. It is also possible to reduce the likelihood that current will reach ground through an unintended path, such as through a person&#39;s body. 
     The transformation stage efficiently provides an intermediate voltage V X  that differs from the input voltage V IN  and that varies over a much smaller range than the input voltage V IN . In practice, the intermediate voltage V X  varies during operation if there are changes at either the input or output of the transformation stage. These variations require correction to achieve the desired output voltage V O . It is for this reason that a regulation stage is necessary. As shown in  FIGS. 1 and 28 , a regulation stage receives the intermediate voltage V X  across its input terminals and provides a regulated voltage V O  across its output terminals. 
     The architecture shown in  FIG. 1  is flexible enough to permit designs with different requirements. For example, if magnetic isolation is required, a magnetic isolated fly-back converter can be used. Designs that require multiple regulated output voltages can be accomplished by using two separate regulation stages and a single transformation stage. 
     The architecture shown in  FIG. 1  in effect creates a modular architecture for power converters in which fundamental building blocks can be mixed and matched in a variety of ways to achieve particular goals. 
       FIGS. 3-10  are block diagrams showing different ways to arrange the transformation stage and the regulation stage relative to a source or a load. The fact that these can even be represented as block diagrams at all stems from the modularity of the architecture. Such modularity is not present in a conventional single-stage converter. In such a converter, the functions of regulation and transformation are so intimately comingled that it is not possible to extract two separate circuits and to say that one carries out regulation and the other carries out transformation. Instead, in a conventional converter, if one attempts to extract two circuits, one of which is a regulator and the other of which is a voltage transformer, the usual result is two circuits that do not work. 
       FIG. 3  shows a generic architecture in which a pair of transformation stages sandwiches a regulation stage. Each transformation stage includes one or more switched-capacitor networks. Similarly, each regulation stage includes one or more regulating circuits. It is also possible to have more than one source and more than one load. The double-headed arrows in  FIG. 3  and in other figures indicate bidirectional power flow. 
       FIG. 4  shows a source-regulating configuration in which power flows from a source to a transformation stage. The transformation stage then provides the power to a regulation stage, which then passes it to a load. Thus, in this configuration, the load ultimately receives power from the regulation stage. 
     In contrast,  FIG. 5  shows a load-regulating configuration. In a load-regulating configuration, power flows from a source to a regulation stage, which then regulates it and passes it to a transformation stage. In this embodiment, the load receives power directly from the transformation stage instead of directly from the regulation stage. 
       FIG. 6  shows a reverse source-regulating configuration similar to that shown in  FIG. 4 , but with power flowing in the opposite direction. 
       FIG. 7  shows a reverse load-regulating configuration similar to that shown  FIG. 5 , but with power flowing in the other direction. 
     In the embodiments shown in  FIGS. 8 and 9 , two transformation stages bracket a regulation stage. These are distinguished by direction of current flow.  FIG. 8  shows a source/load-regulating configuration in which power flows from the source to the load via a first transformation stage, a regulation stage, and a second transformation stage, and  FIG. 9  shows a reverse source/load-regulating configuration in which power flows from the load to the source via a first transformation stage, a regulation stage, and a second transformation stage. 
     In another embodiment, shown in  FIG. 10 , several regulating circuits rely on the same switched-capacitor converter. Note that of the three power paths, a first and second power path are in the load-regulating configuration whereas the third power path is in the source/load-regulating configuration. An embodiment having several regulating circuits is particularly useful since it enables different output voltages to be provided to different loads. 
       FIG. 11  shows a power converter  10  assembled by combining two modules using the principles suggested by  FIG. 1 . The illustrated power converter  10  includes a switching network  12 A, a voltage source  14 , a regulating circuit  16 A, and an inter-module link  11 A that connects an output of the switching network  12 A to an input of the regulating circuit  16 A. A load  18 A connects to an output of the regulating circuit  16 A. Power flows between the voltage source  14  and the load  18 A in the direction indicated by the arrows. To simplify representation, the separation of the connection into positive and negative lines has been omitted. 
     In the embodiment shown in  FIG. 11 , the regulating circuit  16 A can be at some distance from the switching network  12 A. In such cases, it is useful to include a filter at the output of the switching network  12 A. 
       FIG. 12  shows a power converter  10  that, like the embodiment shown in  FIG. 11 , has a voltage source  14  that provides a first voltage V 1  to a switching network  12 A. However, in this embodiment, the switching network  12 A provides a second voltage V 2  to an inductance L 1 . In the illustrated embodiment, there is also a capacitance C 1  across a load  18 A. The inductance L 1  and the capacitance C 1  together define an LC filter that outputs a third voltage V 3  that ultimately makes its way to the regulating circuit  16 A shown in  FIG. 11 . The regulating circuit  16 A adjusts the unregulated third voltage V 3  to yield a regulated fourth voltage V 4 , which it then provides to the load  18 A. 
     An alternative embodiment, shown in  FIG. 13 , connects the third voltage V 3  directly to the load  18 A. In this embodiment, the filter formed by the combination of the capacitor C 1  and inductor L 1  regulates the third voltage V 3  without the need for a regulating circuit  16 A. The various configurations shown above have switches that need to be opened and closed at certain times. Thus, they all implicitly require one or more controllers to provide control signals that open and close these switches. The structure and operation of such a controller  20 A is described in connection with  FIGS. 14-23 . 
       FIG. 14  shows the power converter  10  of  FIG. 11 , but with a controller  20 A explicitly shown. The controller  20 A features three sensor inputs: an intermediate-voltage input for an intermediate voltage V X , an output-voltage input for the output voltage V O , and an optional input-voltage input for the input voltage V IN . The controller  20 A has two other inputs: a clock input to receive a clock signal CLK and a reference input to receive a reference voltage V REF . Examples of the various signals above, as well as others to be described below, can be seen in  FIG. 16 . 
     Based on the aforementioned inputs, the controller  20 A provides a first control signal ϕ to control switches in the switched-capacitor element  12 A and a second control signal PWM to control switching of the regulating circuit  16 A. The first control signal is a two-dimensional vector having first and second complementary phases ϕ,  ϕ . In some embodiments, the first control signal is a vector having higher dimensionality. In the illustrated embodiment, the second control signal PWM is a scalar. However, in multi-phase embodiments described below, the second control signal PWM is also a vector. 
     The controller  20 A relies on the clock signal CLK and the intermediate voltage V X  to set the period of the second control signal PWM for controlling the regulating circuit  16 A. A comparison between the reference voltage V REF  and the output voltage V O  provides a basis for controlling the output voltage V O . 
     The controller  20 A synchronizes operation of the switching network  12 A and the regulating circuit  16 A. It does so by synchronizing a ripple on the intermediate voltage V X  with the second control signal PWM. Such synchronization relaxes the requirement of running the regulation circuit  16 A at a significantly higher frequency than the switching network  12 A in an attempt to achieve effective feed-forward control. 
     The control method described herein also avoids glitches inherent in changing the switching frequency of the switching network  12 A. It does so by making use of a regulating circuit  16 A that draws discontinuous input current. An example of such a regulating circuit  16 A is one that uses a buck converter. 
     Referring now to  FIG. 15 , the controller  20 A has a switched-capacitor section  301  and a regulator section  302 . These can be on the same die or on different dies. 
     The switched-capacitor section  301  outputs the first control signal ϕ. The complementary first and second phases ϕ,  ϕ  that make up the first control signal are shown as the last two traces in  FIG. 16 . 
     The switched-capacitor section  301  has an undershoot limiter  36  that receives the input voltage V IN  and the intermediate voltage V X . Based on these, the undershoot limiter  36  determines a trigger level V X_L . The trigger level V X_L  is shown as a dashed horizontal line superimposed on the sixth trace on  FIG. 16 . The switched capacitor section  301  ultimately uses this trigger level V X_L  to determine when it is time to generate the first control signal  41 ). The details of how this is done are described below. 
     After having generated the trigger level V X_L  based on the input voltage V IN  and the intermediate voltage V X , the undershoot limiter  36  provides it to a first comparator  35 . The first comparator  35  then compares the trigger level V X_L  with the intermediate signal V X . Based on the comparison, the first comparator  35  provides a first trigger signal to a first control signal generator  34 , which ultimately outputs the first control signal ϕ. 
     The switched capacitor section  301  thus forms a first feedback loop that manipulates the first control signal ϕ in an effort to control the intermediate voltage V X  based on the combination of the intermediate voltage V X  and the input voltage V IN . 
     The first control signal generator  34  does not generate the first control signal ϕ immediately. Instead, the first control signal generator  34  waits for an opportune moment to do so. The occurrence of this opportune moment depends on what the regulator section  302  is doing. 
     While the switched capacitor section  301  is busy providing the first trigger signal to the first control signal generator  34 , the regulator section  302  is also busy generating the second control signal PWM. The regulator section  302  begins this process with a voltage compensator  31  that receives a voltage output V O  and a reference voltage V REF . From these, the voltage compensator  31  generates an error voltage V ERR . 
     Some implementations of the voltage compensator  31  include linear voltage-mode control and peak current-mode control. However, other modes are possible. Assuming linear voltage-mode control for the regulation circuit  16 A, the voltage compensator  31  compares the output voltage V O  of the power converter  10  with a reference voltage V REF  and provides an error signal V ERR  to a second comparator  32 . This error signal V ERR  is shown in  FIG. 16  superimposed on a serrated waveform V SAW  on the second trace shown in  FIG. 16 . 
     The regulator section  302  thus forms a second feedback loop that manipulates the second control signal PWM in an effort to control the output voltage V O  based on the combination of a reference signal V REF  and the output voltage V O . However, for reasons discussed in more detail below, the switched capacitor section  301  and the regulator section  302  do not operate independently. Instead, the controller  20 A synchronizes their operation. 
     To provide a basis for such synchronization, the regulator section  302  includes a saw-tooth generator  30 . The saw-tooth generator  30  generates the serrated waveform V SAW  based on a clock signal CLK and the intermediate voltage V X . This serrated waveform V SAW  ultimately provides a way to synchronize the first control signal ϕ and the second control signal PWM. 
     The second comparator  32  compares the error voltage V ERR  with the serrated waveform V SAW  and outputs a second trigger signal based on this comparison. As shown in  FIG. 16 , the second control signal PWM changes state in response to a change in the sign of the difference between the error voltage V ERR  and the serrated waveform V SAW . Since the serrated waveform V SAW  is ultimately based on the intermediate voltage V X , this provides a basis for synchronizing the operation of the switched-capacitor section  301  and the regulator section  302 . 
     The second control signal generator  33  receives the second trigger signal from the second comparator  32  and uses it as a basis for generating the second control signal PWM. 
     This second control signal PWM ultimately serves as a gate drive to actually drive the gate of a transistor that implements a main switch  152  in a regulating circuit  16 A, details of which are seen in  FIG. 18 . This main switch  152  ultimately controls an inductor voltage V L  and an inductor current IL across and through an inductor  154  within the regulating circuit  16 A, as shown by the fourth and fifth traces in  FIG. 16 . 
     The particular configuration shown illustrates feed-forward control of the regulation circuit  16 A implemented in the saw-tooth generator  30 . However, such control could also be implemented in the voltage compensator  31 . 
     The switched-capacitor section  301  implements a hysteretic control system in which a controlled variable, namely the intermediate voltage V X , switches abruptly between two states based upon a hysteresis band. The intermediate voltage V X  is a piecewise linear approximation of a serrated waveform. 
     Synchronization between the regulator section  302  and the switched capacitor section  301  is important to enable the dead-time interval of the switching network  12 A to occur when no current is being drawn by the regulating circuit  16 A. 
     In a practical switching network  12 A, the first control signal ϕ will actually cycle through three states, not just two. In the first state, the first control signal ϕ opens a first set of switches and closes a second set of switches. In the second state, the first control signal ϕ closes the first set of switches and opens the second set of switches. 
     A practical difficulty that arises is that switches cannot open and close instantly. Nor can they be guaranteed to operate simultaneously. Thus, the first control signal ϕ cycles through a third state, which lasts for a dead-time interval DT. During this third state, all switches open. This minimizes the unpleasant possibility that a switch in the second set will not have opened by the time the switches in the first set have closed. 
     Meanwhile, certain regulating circuits  16 A, such as buck converters and the like, draw input current discontinuously. In particular, such regulating circuits  16 A have short intervals during which they are drawing zero current. 
     The controller  20 A avoids glitches by synchronizing the operation of the switching network  12 A and the regulating circuit  16 A such that the regulating circuit  16 A draws zero current during the dead-time interval DT. 
     A further benefit of such synchronization is the ability to cause switches in the switching network  12 A to change state when there is no current flowing through them. This reduces commutation losses. Causing the dead-time interval DT to occur when the regulating circuit  16 A is not drawing current, and causing switches in the switching network  12 A to only change state at the beginning and the end of the dead-time interval DT thus ensures zero-current switching, as shown in  FIG. 17 . 
     In operation, the regulator section  302  and the switched capacitor section  301  cooperate to ensure that the length of one cycle of the first control signal ϕ will be equal to an integral number of cycles of the second control signal PWM. In  FIG. 16 , this constraint is met because the one cycle of the first control signal ϕ is equal to an integral number of cycles of the second control signal PWM. 
     The first control signal generator  34  receives a first trigger signal from the first comparator  35  indicating that the intermediate voltage V X  has fallen below the trigger level V X_L . However, as alluded to above, the first control signal generator  34  does not act immediately. Instead, it waits until there is an opportune time to make a state change. Meanwhile, as the first control signal generator  34  waits, the intermediate voltage V X  continues to fall, as shown in  FIG. 16 . 
     As shown in  FIG. 16 , by the time the first control signal generator  34  acts, the intermediate voltage will already have fallen to an undershoot ΔV d  below the trigger level V X_L . In most cases, the undershoot ΔV d  is small and capped by an undershoot cap of ½ΔV X , which only occurs when the switching frequency of the regulator section  302  and the switched capacitor section  301  are equal. This undershoot cap depends on load current and input voltage V IN . 
     Large variations in undershoot ΔV d  are undesirable because they stress the regulating circuit  18 A. The undershoot limiter  36  selects a suitable trigger level V X_L  to limit this undershoot ΔV d  by indirectly controlling the undershoot cap ½ΔV X . The undershoot limiter  36  uses the intermediate voltage V X  and the input voltage V IN  to select an appropriate value of the trigger level V X_L . 
       FIG. 17  shows a close up of selected waveforms in  FIG. 16  at a scale that is actually large enough to show a dead-time interval DT between the two phases ϕ,  ϕ  that make up the first control signal ϕ. To assist in discussion, it is useful to consider the circuit shown in  FIG. 18 , which was introduced earlier in a discussion of the function of the second control signal PWM. 
       FIG. 18  shows a first set of switches  141 ,  143 ,  146 ,  148 , which is controlled by the first phase ϕ, and a second set of switches  142 ,  144 ,  145 ,  147 , which is controlled by the second phase  ϕ .  FIG. 18  also shows the main switch  152  that connects the regulating circuit  16 A to the switching network  12 A. The main switch  152  has already been discussed above. 
     During this dead-time interval DT, the phases ϕ,  ϕ  open all switches  141 ,  143 ,  146 ,  148 ,  142 ,  144 ,  145 ,  147 . This dead-time interval DT must occur while the main switch  152  is open. This requirement sets a maximum possible duty cycle D max  for the regulating circuit  16 A during the switching transition of the first control signal ϕ: 
     
       
         
           
             
               D 
               max 
             
             = 
             
               
                 
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                   sw 
                 
                 - 
                 
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     As is apparent from the above relationship, the dead-time DT places a limit on the maximum possible duty cycle D max . It is therefore desirable to reduce the dead-time DT as much as possible to increase the range of possible transformation ratios for the regulating circuit  16 A. 
     For many practical power converters, a desire for electromagnetic compatibility dictates that the regulating circuit  16 A should operate at a constant switching frequency. In these cases, the above constraint on the maximum possible duty cycle D max  is not overly burdensome, especially, if the feed-back controller for the regulation circuit  16 A would otherwise have a maximum duty cycle requirement. 
     The control strategy as described above and implemented by the controller  20 A in  FIG. 15  is one of many possible implementations. In general, the switching frequency for switches  141 ,  143 ,  146 ,  148 ,  142 ,  144 ,  145 ,  147  in the switching network  12 A will change in discrete steps as the load current of the power converter  10  varies. 
       FIG. 19  shows how the output current affects both the period with which the switches  141 ,  143 ,  146 ,  148 ,  142 ,  144 ,  145 ,  147  of the switching network  12 A change state and the corresponding ΔV X  ripple. 
     For this particular control strategy, the ripple magnitude ΔV X  varies as a function of load current. In particular, the ripple magnitude ΔV X  defines a serrated waveform having a peak-to-peak amplitude that decreases with load current. As the load current approaches zero, the peak-to-peak amplitude approaches half of the maximum peak-to-peak amplitude. With a few modifications to the controller, it is also possible to get the ΔV X  ripple to approach the maximum peak-to-peak amplitude as the load current approaches zero, as shown in  FIG. 20 . 
     As is apparent from both  FIGS. 19 and 20 , as the load current increases, the switching period for the switches  141 ,  143 ,  146 ,  148 ,  142 ,  144 ,  145 ,  147  stays the same for a range of output currents. Within this range of output currents, the converter relies on the regulating circuit  16 A to make up the difference between the voltage that the switching network  12 A provides whatever voltage is required. At some point, the regulating circuit  16 A can no longer make the necessary correction. At that point, the period takes a step down. 
     The controller  20 A shown in  FIG. 14  is a single-phase converter. As such, the first control signal ϕ is a two-dimensional vector and the second control signal PWM is a scalar. In the case of an N-phase converter, the first control signal ϕ is a 2N-dimensional vector and the second control signal PWM is an N-dimensional vector having components PWM 1 , PWM 2 , . . . PWM n  that are phase shifted relative to each other. Typically, the phase shift between these components is 360/N degrees. 
       FIG. 21  shows an example of an N-phase converter having plural regulation circuits  16 A,  16 B. Each regulation circuit  16 A,  16 B has a corresponding switching network  12 A,  12 B. Each regulation circuit  16 A,  16 B is also driven by its own control signal, hence the need for an N-dimensional second control signal PWM. Each switching network  12 A,  12 B is driven by a pair of phases, hence the need for a 2N-dimensional first control signal. 
     An N-phase controller  20 A controls the N-phase converter. The N-phase controller  20 A is similar to the single-phase controller in  FIG. 14  but with additional inputs for the N intermediate voltages V X1 , V X2 , . . . V XN . 
       FIG. 22  shows waveforms similar to those shown in  FIG. 16  but for a three-phase version of the controller shown in  FIG. 14 . 
     As shown in  FIG. 22 , the second control signal PWM consists of second control signal elements PWM 1 , PWM 2 , PWM 3  that are separated from each other by a delay time that corresponds to a 120° phase shift between them. The three intermediate voltages V X1 , V X2 , V X3  are shifted from each other by an integer multiple of this delay time. In  FIG. 22 , the integer is unity. However, as shown in  FIG. 23 , other integers are possible. 
     Because the periods of the intermediate voltages V X1 , V X2 , V X3  are longer than those of the second control signal elements PWM 1 , PWM 2 , PWM 3 , shifting them by the delay time will not cause them to be 120 degrees out of phase with each other. In fact, because their period is so much longer, a shift by this delay time only causes a very small phase shift in the intermediate voltages V X1 , V X2 , V X3 . 
       FIG. 23  shows an alternative method of operation similar to that shown in  FIG. 22 , but with the intermediate voltages V X1 , V X2 , V X3  having been shifted by a larger multiple of the delay time. This results in a more significant phase shift between the intermediate voltages V X1 , V X2 , V X3 , a result of which is a reduced ripple in the output voltage V O . 
     A multi-phase controller  20 A for controlling the N-phase converter shown in  FIG. 21  can be thought of as N single-phase controllers  20 A as shown in  FIG. 15  operating in parallel but with a specific phase relationship between them. A multi-phase controller  20 A would thus look very similar to the one in  FIG. 15 , but with an additional input and output signals. In general, the intermediate voltages (V X1 , V X2 , . . . V XN ) and the output voltage V O  are required for proper operation of the controller  20 A. 
       FIG. 24  shows a converter similar to that shown in  FIG. 21 , but having only one regulation circuit  16 A that is connected to plural switching networks  12 A,  12 B. Since there is only one regulation circuit  16 A, only a 1-dimensional second control signal PWM is required. Each switching network  12 A,  12 B is driven by a pair of phases, hence the need for a 2N-dimensional first control signal. 
       FIG. 25  shows a converter that is essentially the converse of  FIG. 24 . In  FIG. 25 , the converter has plural regulation circuits  16 A,  16 B, all of which are coupled to the same switching network  12 A. Each regulation circuit  16 A,  16 B is driven by its own control signal, hence the need for an N-dimensional second control signal PWM. The sole switching network  12 A is driven by a pair of phases, hence the need for a 2-dimensional first control signal. 
       FIG. 26  shows a converter similar to that shown in  FIG. 25 , but with an inductance L 1  connected to both the output of the switching network  12 A and to the inputs of the regulating circuits  16 A, 16 B. A grounded capacitor C 1  provides a place to store excess charge during operation. The N-phase controller  20 A observes both a switching-network&#39;s output voltage V Y  and a regulating circuits&#39; input voltage V X . 
       FIG. 27  shows a converter similar to that shown in  FIG. 24  but with an inductance L 1  . . . L N  connected to the outputs of each of the switching networks  12 A,  12 B and to the input of the regulating circuit  16 A. A grounded capacitor C 1  provides a place to store excess charge during operation. The N-phase controller  20 A uses the switching-networks&#39; output voltages V Y1  . . . V YN  and the regulating circuit&#39;s input voltage V X  to generate suitable control signals. 
     In  FIG. 14 , a non-capacitive regulating circuit  16 A loads down the switching network  12 A. This regulating circuit  16 A is switched at a high frequency. The components from the high-frequency switching of the regulating circuit  16 A are ultimately superimposed on the lower frequency serrated waveform of the intermediate voltage V X , as shown in sixth trace on  FIG. 16 . The duty cycle of the saw-tooth approximation waveform depends on the topology of the switching network  12 A. In general, the frequency of the complementary switching-network control signals varies with changes in response to changes in the slope of the intermediate signal. These changes, in turn, arise as a result of changes in the power converter&#39;s operating point. 
     The switching network  12 A and the regulating circuit  16 A are essentially modular and can be mixed and matched in a variety of different ways. As such, the configuration shown in  FIG. 11  represents only one of multiple ways to configure one or more switching networks  12 A with one or more regulating circuits  16 A to form a multi-stage converter  10 . 
     For example,  FIG. 28  shows a bidirectional version of  FIG. 11  in which power can flow either from a voltage source  14  to a load  18 A or from the load  18 A to the voltage source  14  as indicated by the arrows. 
     There are two fundamental elements described in connection with the following embodiments: switching networks  12 A and regulating circuits  16 A. Assuming series connected elements of the same type are combined, there are a total of four basic building blocks. These are shown  FIGS. 28, 29, 30, and 32 . The power converters disclosed herein include at least one of the four basic building blocks. More complex converter can be realized by combining the fundamental building blocks. 
     The first building block, shown in  FIG. 28 , features a switching network  12 A whose output connects to an input of a regulating circuit  16 A. The second building block, shown in  FIG. 29 , features a first switching network  12 A whose output connects to a regulating circuit  16 A via a first intermodule link  11 A, an output of which connects to an input of a second switching network  12 B via a second intermodule link  11 B. In the third building block shown in  FIG. 30 , an output of a regulating circuit  16 A connects to an input of a switching network  12 A via an intermodule link  11 B. A fourth building block, shown in  FIG. 33 , features a first regulating circuit  300 A having an output that connects to an input of a first switching network  200 , an output of which connects to an input of a second regulating circuit  300 B. 
     Additional embodiments further contemplate the application of object-oriented programming concepts to the design of power converters by enabling switching networks  12 A and regulating circuits  16 A to be “instantiated” in a variety of different ways so long as their inputs and outputs continue to match in a way that facilitates modular assembly of power converters having various properties. 
     The switching network  12 A in many embodiments is instantiated as a switched-capacitor network. Among the more useful switched capacitor topologies are: Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler, all of which can be adiabatically charged and configured into multi-phase networks. A particularly useful switching capacitor network is an adiabatically charged version of a full-wave cascade multiplier. However, diabatically charged versions can also be used. 
     As used herein, changing the charge on a capacitor “adiabatically” means causing an amount of charge stored in that capacitor to change by passing the charge through a non-capacitive element. A positive adiabatic change in charge on the capacitor is considered adiabatic charging while a negative adiabatic change in charge on the capacitor is considered adiabatic discharging. Examples of non-capacitive elements include inductors, magnetic elements, resistors, and combinations thereof. 
     In some cases, a capacitor can be charged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically charged. Similarly, in some cases, a capacitor can be discharged adiabatically for part of the time and diabatically for the rest of the time. Such capacitors are considered to be adiabatically discharged. 
     Diabatic charging includes all charging that is not adiabatic and diabatic discharging includes all discharging that is not adiabatic. 
     As used herein, an “adiabatically charged switching network” is a switching network having at least one capacitor that is both adiabatically charged and adiabatically discharged. A “diabatically charged switching network” is a switching network that is not an adiabatically charged switching network. 
     The regulating circuit  16 A can be instantiated as any converter with the ability to regulate the output voltage. A buck converter for example, is an attractive candidate due to its high efficiency and speed. Other suitable regulating circuits  16 A include boost converters, buck/boost converters, fly-back converters, forward converters, half-bridge converters, full-bridge converters, Cuk converters, resonant converters, and linear regulators. The fly-back converter can more specifically be a quasi-resonant fly-back converter, or an active-clamp fly-back converter, or an interleaved fly-back converter, or a two-switch fly-back converter. Likewise, the forward converter can be more specifically a multi-resonant forward converter, or an active-clamp forward converter, or an interleaved forward converter, or a two-switch forward converter. And, the half-bridge converter can more specifically be an asymmetric half-bridge converter, or a multi-resonant half-bridge converter, or a LLC resonant half-bridge. 
     In the embodiment shown in  FIG. 28 , a source voltage  14  provides an input to a first switching network  12 A, which is instantiated as a switching capacitor network. The output of the first switching network  12 A is a lower voltage than the input voltage that is provided to a regulating circuit  16 A (e.g. a buck, a boost, or a buck/boost converter). This regulating circuit  16 A provides a regulated input voltage to a second switching network  12 B, such as another switching capacitor network. A high voltage output of this second switching network  12 B is then applied to a load  18 A. 
     An embodiment such as that shown in  FIG. 28  can be configured to regulate the load  18 A or to regulate the voltage source  14  depending on the direction of energy flow. 
     In another embodiment, shown in  FIG. 30 , a low voltage source  14  connects to an input of a regulating circuit  16 A, the output of which is provided to an input of a switching network  12 A to be boosted to a higher DC value. The output of the switching network is then provided to a load  18 A. 
     An embodiment such as that shown in  FIG. 30  can be used to regulate the voltage source  14  or the load  18 A depending on the direction of energy flow. 
       FIG. 31  shows the modular DC-DC converter  10 C of  FIG. 30 , but with a controller  20 A explicitly shown. The controller  20 A is similar to that described in connection with  FIG. 15 . 
     As was discussed in connection with  FIG. 15 , the controller  20 A features three sensor inputs, one for an intermediate voltage V X , one for the output voltage V O , and an optional one for the input voltage, V IN . The controller  20 A also has two inputs that are not sensor inputs. One non-sensor input receives a clock signal CLK and the other receives a reference voltage V REF . The clock signal CLK is used to set the period of a second control signal PWM and the reference voltage V REF  is used to set the desired output voltage. Based on these inputs, the controller  20 A outputs a first control signal having two phases to the switched-capacitor element  12 A and a second control signal PWM to control switching of the regulating circuit  16 A. This second control signal PWM is a pulse-width modulated signal. 
     Referring now to  FIG. 32 , another embodiment of a converter  100  includes a first regulating circuit  300 A connected to a converter input  102  and a second regulating circuit  300 B connected to a converter output  104 . Between the first and second regulating circuits  300 A,  300 B is a switching network  200  having a switching network input  202  and a switching network output  204 . The switching network  200  includes charge storage elements  210  interconnected by switches  212 . These charge storage elements  210  are divided into first and second groups  206 ,  208 . 
     In some embodiments, the switching network  200  is a bidirectional switching capacitor network such as that shown in  FIG. 33 . 
     The switching capacitor network in  FIG. 33  features a first capacitor  20  and a second capacitor  22  in parallel. A first switch  24  selectively connects one of the first and second capacitors  20 ,  22  to a first regulating circuit  300 A, and a second switch  26  selectively connects one of the first and second capacitors  20 ,  22  to the second regulating circuit  300 B. Both the first and second switches  24 ,  26  can be operated at high frequency, thus facilitating the adiabatic charging and discharging of the first and second capacitors  20 ,  22 . 
     The particular embodiment shown in  FIG. 33  has a two-phase switching network  200 . However, other types of switching networks can be used instead. 
     In yet another embodiment, shown in  FIG. 34 , multiple regulating circuits  16 A,  16 B,  16 C are provided at an output of a first switching network  12 A for driving multiple loads  18 A- 18 C. For one of the loads  18 C, a second switching network  12 B is provided between the load  18 C and the corresponding regulating circuit  16 C thus creating a pathway similar to that shown in  FIG. 30 .  FIG. 34  thus provides an example of how the modular construction of regulating circuits and switching networks facilitates the ability to mix and match components to provide flexibility in DC-DC converter construction. 
     A switched-capacitor power converter includes a network of switches and capacitors. By cycling the network through different topological states using these switches, one can transfer energy from an input to an output of the switched-capacitor network. Some converters, known as “charge pumps,” can be used to produce high voltages in flash and other reprogrammable memories. 
     To help understand the loss mechanisms in switched capacitor converters, it is instructive to first analyze the classical capacitor charging problem, as depicted in  FIG. 35 . 
       FIG. 35  shows a capacitor C initially charged to some value V C (0). At t=0 the switch S is closed. At that instant, a brief surge of current flows as the capacitor C charges to its final value of V IN . The rate of charging can be described by a time constant τ=RC, which indicates the time it takes the voltage to either rise or fall to within 1/e of its final value. The instantaneous values for voltage across the capacitor v c (t) and current through the capacitor i c (t) are given by the following equations: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
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                             ⁡ 
                             
                               ( 
                               0 
                               ) 
                             
                           
                         
                         ] 
                       
                     
                     ⁢ 
                     
                       
                         
                           
                               
                             2 
                           
                           ⁢ 
                           C 
                         
                         ⁡ 
                         
                           [ 
                           
                             1 
                             - 
                             
                               e 
                               
                                 
                                   - 
                                   2 
                                 
                                 ⁢ 
                                 
                                   t 
                                   / 
                                   R 
                                 
                                 ⁢ 
                                 c 
                               
                             
                           
                           ] 
                         
                       
                       . 
                     
                   
                 
               
               
                 
                     
                 
               
             
           
         
       
     
     It is apparent therefore that the only term that involves the resistance is in a decaying exponential. Thus, if the transients are allowed to settle (i.e. t→∞), the total energy loss incurred in charging the capacitor is independent of its resistance R. In that case, the amount of energy loss is equal to 
     
       
         
           
             
               
                 
                   E 
                   
                     l 
                     ⁢ 
                     o 
                     ⁢ 
                     s 
                     ⁢ 
                     s 
                   
                 
                 ⁡ 
                 
                   ( 
                   ∞ 
                   ) 
                 
               
               = 
               
                 
                   1 
                   2 
                 
                 ⁢ 
                 C 
                 ⁢ 
                 Δ 
                 ⁢ 
                 
                   v 
                   c 
                   2 
                 
               
             
             . 
           
         
       
     
     A switched-capacitor converter can be modeled as an ideal transformer, as shown in  FIG. 36 , with a finite output resistance R o  that accounts for the power loss incurred in charging or discharging of the energy transfer capacitors, as shown in  FIG. 36 . The embodiment shown in  FIG. 36  is non-isolated because the negative terminals on both sides of the transformer are connected. However, this is by no means required. As an example,  FIG. 37  shows an embodiment in which the same terminals are not connected, in which case the converter is isolated. 
     It should be noted that the transformer shown is only for modeling purpose. A converter of this type would generally not have windings wrapped around an iron core. The power losses associated with charging and discharging are typically dissipated in the ON resistance of the MOSFETs and equivalent series resistance of the capacitors. 
     The output voltage of the switched-capacitor converter is given by 
     
       
         
           
             
               
                 V 
                 o 
               
               = 
               
                 
                   
                     V 
                     in 
                   
                   ⁢ 
                   
                     
                       N 
                       2 
                     
                     
                       N 
                       1 
                     
                   
                 
                 - 
                 
                   
                     I 
                     o 
                   
                   ⁢ 
                   
                     R 
                     o 
                   
                 
               
             
             . 
           
         
       
     
     There are two limiting cases where the operation of switched capacitor converters can be simplified and R o  easily found. These are referred to as the “slow-switching limit” and the “fast-switching limit.” 
     In the fast-switching limit (τ&gt;&gt;T sw ), the charging and discharging currents are approximately constant, resulting in a triangular AC ripple on the capacitors. Hence, R o  is sensitive to the series resistance of the MOSFETs and capacitors, but is not a function of the operating frequency. In this case, R o  of the converter operating in the fast-switching limit is a function of parasitic resistance and R o  is given by: 
     
       
         
           
             
               
                 
                   R 
                   o 
                 
                  
               
               
                 τ 
                 ⪢ 
                 
                   T 
                   m 
                 
               
             
             = 
             
               
                 R 
                 
                   F 
                   ⁢ 
                   S 
                   ⁢ 
                   L 
                 
               
               = 
               
                 n 
                 ⁢ 
                 
                   
                     ∑ 
                     
                       i 
                       ∈ 
                       sw 
                     
                   
                   ⁢ 
                   
                     
                       ∑ 
                       
                         j 
                         = 
                         1 
                       
                       n 
                     
                     ⁢ 
                     
                       
                         
                           
                             R 
                             i 
                           
                           ⁡ 
                           
                             ( 
                             
                               a 
                               
                                 r 
                                 , 
                                 i 
                               
                               j 
                             
                             ) 
                           
                         
                         2 
                       
                       . 
                     
                   
                 
               
             
           
         
       
     
     Although it tends to under-estimate R o , a useful approximation for R o  that serves as a good starting point in the design process is given by 
     
       
         
           
             
               
                 
                   R 
                   o 
                 
                 ⁡ 
                 
                   ( 
                   f 
                   ) 
                 
               
               ≈ 
               
                 
                   
                     R 
                     
                       F 
                       ⁢ 
                       S 
                       ⁢ 
                       L 
                     
                     2 
                   
                   + 
                   
                     R 
                     
                       S 
                       ⁢ 
                       S 
                       ⁢ 
                       L 
                     
                     2 
                   
                 
               
             
             . 
           
         
       
     
     In the slow-switching limit, the switching period T sw  is much longer than the RC time constant τ of the energy transfer capacitors. Under this condition, a systemic energy loss given by ½C×ΔV c   2  occurs regardless of the resistances of the capacitors and switches. This systemic energy loss arises in part because the root mean square (RMS) of the charging and discharging current is a function of the RC time constant. Under these circumstances, R o  is given by 
     
       
         
           
             
               
                 
                   R 
                   o 
                 
                  
               
               
                 τ 
                 ⪡ 
                 
                   T 
                   
                     s 
                     ⁢ 
                     w 
                   
                 
               
             
             = 
             
               
                 R 
                 
                   S 
                   ⁢ 
                   S 
                   ⁢ 
                   L 
                 
               
               = 
               
                 
                   ∑ 
                   
                     i 
                     ∈ 
                     caps 
                   
                 
                 ⁢ 
                 
                   
                     ∑ 
                     
                       j 
                       = 
                       1 
                     
                     n 
                   
                   ⁢ 
                   
                     
                       
                         
                           ( 
                           
                             a 
                             
                               c 
                               , 
                               i 
                             
                             j 
                           
                           ) 
                         
                         2 
                       
                       
                         2 
                         ⁢ 
                         
                           C 
                           i 
                         
                         ⁢ 
                         
                           f 
                           sw 
                         
                       
                     
                     . 
                   
                 
               
             
           
         
       
     
     The behavior of output resistance as a function of frequency can be appreciated by inspection of  FIG. 38 , which shows that as frequency increases, the output resistance drops in a manner consistent with the 1/f sw  term and that at higher frequencies, the output resistance settles down to a steady value. 
     The calculations for R SSL  and R FSL  given above are based on the charge multiplier vector concept. The vector a 1  through a n  can be obtained by inspection for any standard well posed n-phase converter. The charge multiplier vectors are computed using constraints imposed by Kirchoff&#39;s current law in each topological state along with the steady-state constraint that the n charge multiplier quantities must sum to zero on each capacitor. 
     Once R o  is known, the conduction loss P cond  can be calculated by 
     
       
         
           
             
               
                 P 
                 
                   c 
                   ⁢ 
                   o 
                   ⁢ 
                   n 
                   ⁢ 
                   d 
                 
               
               = 
               
                 
                   I 
                   o 
                   2 
                 
                 ⁢ 
                 
                   R 
                   o 
                 
               
             
             . 
           
         
       
     
     Additionally, other losses such as switching losses, driver losses, and control losses can be calculated. Preferably, the switching loss is comparable to conduction loss. These losses, which originate from charging and discharging the transistor nodes, are given by 
     
       
         
           
             
               P 
               sw 
             
             = 
             
               
                 
                   W 
                   sw 
                 
                 ⁢ 
                 
                   f 
                   sw 
                 
               
               = 
               
                 
                   ( 
                   
                     
                       W 
                       
                         d 
                         ⁢ 
                         s 
                       
                     
                     + 
                     
                       W 
                       
                         o 
                         ⁢ 
                         n 
                       
                     
                     + 
                     
                       W 
                       g 
                     
                   
                   ) 
                 
                 ⁢ 
                 
                   f 
                   
                     s 
                     ⁢ 
                     w 
                   
                 
               
             
           
         
       
     
     where W g  is the gate capacitance loss, W on  is the overlap or commutation loss, and W ds  is the output capacitance loss. Thus, the total converter loss can be calculated using 
     
       
         
           
             
               
                 P 
                 
                   l 
                   ⁢ 
                   o 
                   ⁢ 
                   s 
                   ⁢ 
                   s 
                 
               
               = 
               
                 
                   
                     I 
                     o 
                     2 
                   
                   ⁢ 
                   
                     R 
                     o 
                   
                 
                 + 
                 
                   
                     W 
                     sw 
                   
                   ⁢ 
                   
                     f 
                     sw 
                   
                 
                 + 
                 
                   P 
                   
                     e 
                     ⁢ 
                     t 
                     ⁢ 
                     c 
                   
                 
               
             
             . 
           
         
       
     
     Once R o  and the additional loss mechanisms have been determined, the total efficiency of the converter is given by 
     
       
         
           
             
               
                 η 
                 
                   s 
                   ⁢ 
                   c 
                 
               
               = 
               
                 
                   
                     P 
                     o 
                   
                   
                     
                       P 
                       o 
                     
                     + 
                     
                       P 
                       
                         l 
                         ⁢ 
                         o 
                         ⁢ 
                         s 
                         ⁢ 
                         s 
                       
                     
                   
                 
                 = 
                 
                   
                     P 
                     o 
                   
                   
                     
                       P 
                       o 
                     
                     + 
                     
                       P 
                       
                         c 
                         ⁢ 
                         o 
                         ⁢ 
                         n 
                         ⁢ 
                         d 
                       
                     
                     + 
                     
                       P 
                       
                         s 
                         ⁢ 
                         w 
                       
                     
                     + 
                     
                       P 
                       
                         e 
                         ⁢ 
                         t 
                         ⁢ 
                         c 
                       
                     
                   
                 
               
             
             . 
           
         
       
     
     To optimize efficiency of the switched-capacitor converter, the optimal switching frequency, capacitance, and device sizes must be selected. If the switching frequency is too low, then the conduction losses, P cond , dominate. On the other hand, if the switching frequency is too high, then P sw  dominates. Although doing so tends to decrease output ripple, rarely will a switched-capacitor converter operate far above the transitional region between the slow switching limit and fast switching limit. After all, operating above this region tends to increase switching losses without lowering the output resistance to compensate for those increases switching losses. Thus, there is little to gain by operating above that region. 
     If the effective resistance R eff  of the charging path is reduced, for example by reducing the RC time constant, the RMS current increases and it so happens that the total charging energy loss (E loss =I RMS   2 R eff =½C×ΔV C2 ) is independent of R eff . One solution to minimize this energy loss is to increase the size of the pump capacitors in the switched capacitor network. 
     Although many switched-capacitor networks can provide a specific voltage transformation, most of them are impractical for a variety of reasons. A practical switched-capacitor network typically has a large transformation ratio, low switch stress, low DC capacitor voltage, and low output resistance. Suitable topologies for the converters described herein include Ladder, Dickson, Series-Parallel, Fibonacci, and Doubler topologies. 
     One useful converter is a series-parallel switched capacitor converter.  FIGS. 39-40  show a 2:1 series-parallel switched-capacitor converter operating in charge phase and in discharge phase respectively. During the charge phase, the capacitors are in series. In the discharge phase, the capacitors are in parallel. In its charge phase the capacitor voltages v C1  and v C2  add up to V 1  while in its discharge phase v C1  and v C2  equal V 2 . This means that V 2 =V 1 /2. 
     Another useful topology is that shown in  FIGS. 41 and 42 . In both charge pumps, the source is located at V 1  and the load is located at V 2 . In these types of charge pumps, packets of charge are pumped along a diode chain as the coupling capacitors are successively charged and discharged. As shown in  FIG. 43 , clock signals v clk  and  v clk    with amplitude v pump  are 180 degrees out of phase. The coupling capacitors can either be pumped in series or parallel. 
     It takes n clock cycles for the initial charge to reach the output. The charge on the final pump capacitor is n times larger than the charge on the initial pump capacitor. Thus, V 2  for the converters in  FIG. 42  is V 1 +(n−1)×v pump  in both pumping configurations. 
     Although the foregoing topologies are suitable for stepping up voltage, they can also be used to step down voltage by switching the location of the source and the load. In such cases, the diodes can be replaced with controlled switches such as MOSFETs and BJTs. 
       FIGS. 41 and 42  show topologies that transfer charge during only one phase of the clock signal. Such topologies are referred to as “half-wave” topologies because charge transfer only occurs during half of a clock cycle. A disadvantage of a half-wave topology is a discontinuous input current. 
     It is possible to convert the topologies shown in  FIGS. 41 and 42  so that they transfer charge during both phases of the clock signal. This can be carried out by connecting two such topologies in parallel and driving them 180 degrees out of phase. Such a topology is referred to herein as a “full-wave” topology because charge transfer occurs in both halves of the clock cycle. 
       FIG. 44  show a topology derived from that shown in  FIG. 41 , but modified so that charge transfer occurs in both phases of the clock signal.  FIG. 45  show a topology derived from that shown in  FIG. 42 , but modified so that charge transfer occurs in both phases of the clock signals. Instead of diodes, as shown in the topologies of  FIGS. 41 and 42 , the topologies shown in  FIGS. 44 and 45  use switches. Unlike diodes, which are inherently unidirectional, the switches shown in  FIG. 44  and  FIG. 45  are bidirectional. As a result, in the topologies shown in  FIGS. 44 and 45 , power can flow either from the V 1  terminal to the V 2  terminal or vice versa. As such, these topologies can be used to step-up a voltage or step-down a voltage. 
     In the topologies shown thus far, there are two chains of switches, each of which is pumped. However, it is also possible to pump only one of the two switch chains. Such topologies are referred to as “asymmetric.” 
     In asymmetric topologies, half of the capacitors are used to support a DC voltage and not to transfer energy. However, these embodiments do not require that each switch endure such a high peak voltage. In particular, the peak voltage in the case in which only one switch chain is being pumped is only half of what it would be if both switch chains were actually being pumped. In these asymmetric topologies, the sole switch chain that is being used to transfer energy can be modified to transfer charge during both phases of the clock signal using principles set forth in connection with  FIG. 44 . 
       FIG. 46  shows eight exemplary topologies that use the principles set forth in connection with  FIGS. 41-45 . The first and second columns show half-wave topologies in both asymmetric and symmetric configurations, whereas the third and fourth columns show full-wave wave topologies in both asymmetric and symmetric configurations. The topologies shown in  FIG. 46  can be further modified to combine N phases in parallel and to run them 180 degrees/N out of phase. Doing so reduces output voltage ripple and increases output power handling capability. 
     The basic building blocks in the modular architecture shown  FIGS. 28, 29, 30, and 32  can either be connected as independent entities or coupled entities. In the situation where switching networks and regulating circuits are tightly coupled, it is possible to prevent and/or reduce the systemic energy loss mechanism of the switching networks through adiabatic charging. This generally includes using a regulating circuit to control the charging and discharging of the capacitors in the switching network. Furthermore, the output voltage of the regulating circuit and thus the total converter can be regulated in response to external stimuli. One approach to regulating the output voltage is by controlling the average DC current in the magnetic storage element. 
     In general, it is desirable for the regulating circuit to operate in a way that limits the root mean square (RMS) current through the capacitors in the switching network. The regulating circuit can do so using either resistive elements or magnetic storage elements. Because resistive elements consume power, magnetic storage elements are generally preferable for this purpose. Therefore, embodiments described herein rely on a combination of switches and a magnetic storage element in the regulating circuit to limit RMS current in the switching network. 
     To limit RMS current, the regulating circuit forces the capacitor current through the magnetic storage element in a regulating circuit that has an average DC current. The switches in the regulating circuit then operate to maintain an average DC current through the magnetic storage element. 
     The regulating circuit may limit both the RMS charging current and the RMS discharging current of at least one capacitor in the switching network. A single regulating circuit may limit the current into or out of the switching network by sinking and/or sourcing current. Therefore, there are four fundamental configurations, which are shown in  FIGS. 28, 29, 30, and 32 . 
     Assuming power flows from source to load then, in  FIG. 28 , the regulating circuit  16 A may sink both the charging and discharging current of the switching network  12 A. 
     In  FIG. 29 , the regulating circuit  16 A may source both the charging and discharging current of the switching network  12 B while also sinking both the charging and discharging current of the switching network  12 A. Furthermore, if both the switching networks and the regulating circuits allow power to flow in both directions, then bidirectional power flow is possible. 
     In  FIG. 30 , the regulating circuit  16 A may source both the charging and discharging current of the switching network  12 A. 
     In  FIG. 32 , the regulating circuit  300 A may source the charging current of switching network  200  and the regulating circuit  300 B may sink the discharging current of the same switching network  200  and vice-versa. 
     A fundamental difficulty that afflicts switched-capacitor networks is that the mere act of charging a capacitor incurs energy loss. This energy loss depends a great deal on how much the voltage across the capacitor changes as a result of the charging event. The energy loss E L  associated with using a fixed voltage source at a voltage V to charge a capacitance C from zero to Vis ½CV 2 . This loss does not depend on the parasitic series resistance R. Since this loss arises whenever voltage changes, every charging interval during operation incurs a loss equal to ½CΔV 2 , where ΔV corresponds to the difference between the initial and final value of the capacitor voltage. 
     The fixed charge-up loss cannot be reduced by employing switches with lower on-state resistance. Known ways to reduce it simply avoid causing the voltage to change very much during operation. This is why such converters operate most efficiently only at certain conversion ratios. 
     Since the amount of charge transferred into or out of a charging cycle is the product of the voltage difference and the capacitance, one way to transfer a great deal of charge with only a small voltage difference is to make the capacitance very large. However, large capacitors are not without disadvantages. For one thing, a large capacitance consumes a great deal of physical area. Additionally, switched-capacitor networks with large capacitances are not so amenable to efficient operation. 
     A converter as described herein overcomes the foregoing disadvantage by providing more efficient use of the capacitors. This means that capacitors can be made smaller and/or that there will be an overall improvement in system efficiency. Although a converter as described herein does not require a reconfigurable switched-capacitor circuit, it may nevertheless take advantage of one as described above. 
       FIG. 47  illustrates a method for improving the charge-up efficiency of the capacitor C shown in  FIG. 35  after switch S closes. The regulating circuit  16 A adiabatically charges the capacitor C. In some embodiments, the regulating circuit  16 A is a switch-mode converter that supplies an output. A suitable regulating circuit is a low-voltage magnetic based converter. 
     In the system shown in  FIG. 47 , while the capacitor C charges, most of the difference between the input voltage V IN  and the capacitor stack voltage V C  appears across the input of the regulating circuit  16 A. Instead of being dissipated as heat in a parasitic resistor R, the energy associated with charging the capacitor stack is delivered to the output of the regulating circuit  16 A instead. Therefore, a majority of the capacitor-charging energy can be recovered (i.e., redirected to the load) by making the apparent input resistance of the regulating circuit  16 A higher than the parasitic resistor R. 
     The embodiment shown in  FIG. 47  thus permits more efficient use of capacitors than that shown in  FIG. 35 . This enables reduction in the required capacitor size and/or improvement in system efficiency when extended to switched-capacitor converters. 
       FIG. 48  illustrates one implementation of the foregoing embodiment in which a switching network  12 A connects to regulating circuit  16 A that serves as both a means to adiabatically charge/discharge the capacitors in the switching network  12 A and regulate the output voltage V O . Please note, the regulating circuit  16 A need not be at a higher frequency than the switching network to promote adiabatic operation; it can even be at a lower frequency. In the particular embodiment shown, the regulating circuit  16 A is a synchronous buck converter and the switching network  12 A is a single-phase series-parallel converter. The switching network  12 A features first switches  1  that open and close together, second switches  2  that also open and close together, a first pump capacitor C 1 , and a second pump capacitor C 2 . 
     The regulating circuit  16 A includes a filter capacitor C X  that serves only as a filter and bypass for the regulating circuit  16 A. Consequently, the capacitance of the filter capacitor C X  should be much smaller than that of the first and second pump capacitors C 1  and C 2  of the switching network  12 A. 
     The switching network  12 A alternates between being in a charging state and a discharging state. During the charging state, it charges the first and second pump capacitors C 1 , C 2 . Then, during the discharging state, it discharges the first and second pump capacitors C 1 , C 2  in parallel. 
     In the charging state, the first switches  1  close and the second switches  2  open. The difference between the input voltage V IN , and the sum of the voltages across the first and second pump capacitors C 1 , C 2  appears across the input terminal of the regulating circuit  16 A. As a result, the first and second pump capacitors C 1 , C 2  charge with low loss, and at a rate determined by the power drawn from the regulating circuit  16 A to control the system output. 
     Similarly, in the discharging state, the second switches  2  close and the first switches  1  open. The switching network  12 A then discharge in parallel at a rate based on the power needed to regulate the output. 
     Another embodiment relies on at least partially adiabatically charging full-wave cascade multipliers. Cascade multipliers are a preferred switching network because of their superior fast-switching limit impedance, ease of scaling up in voltage, their two-phase operation, and low switch stress. 
     In cascade multipliers, the coupling capacitors are typically pumped with a clocked voltage source v clk  &amp;  v clk   . However, if the coupling capacitors are pumped with a clocked current source i clk  &amp;  i clk    instead, as shown in  FIG. 49 , then the RMS charging and discharging current in the coupling capacitor may be limited. In this case, the capacitors are at least partially charged adiabatically thus lowering, if not eliminating, the ½C ΔV c   2  loss that is associated with a switched-capacitor converter when operated in the slow-switching limit. This has the effect of lowering the output impedance to the fast-switching limit impedance. As shown by the black dotted line in  FIG. 50 , which depicts adiabatic operation under full adiabatic charging, the output impedance would no longer be a function of switching frequency. 
     With all else being equal, an adiabatically charged switched-capacitor converter can operate at a much lower switching frequency than a conventionally charged switched-capacitor converter, but at higher efficiency. Conversely, an adiabatically charged switched-capacitor converter can operate at the same frequency and with the same efficiency as a conventionally charged switched-capacitor converter, but with much smaller coupling capacitors, for example between four and ten times smaller. 
     Embodiments described herein can operate with two clocked current sources i clk ,  i clk     that operate 180 degrees out of phase, as shown in  FIG. 51 . One implementation, shown in  FIG. 52 , uses one current source  72 , a first switch pair  1  and a second switch pair  2 . The first and second switch pairs  1 ,  2  are best synchronized with a switch chain. A suitable implementation of the current source in  FIG. 52  is an inductance, represented in  FIG. 53  by an inductor L. 
       FIG. 54  shows the cascade multiplier of  FIG. 49  with the clocked current sources in  FIG. 52 .  FIG. 55  shows the cascade multiplier of  FIG. 49  with the clocked current sources in  FIG. 53 . There are numerous ways of implementing the current source  72 . These include buck converters, boost converters, fly-back converter, resonant converters, and linear regulators. In some embodiments, a power converter having a constant input current implements the constant current source. In other embodiments, a power converter that has a constant input current for a portion of an interval defined by the reciprocal of its switching frequency implements the constant current source. In yet other embodiments, a linear regulator implements the constant current source. 
     In the embodiment shown in  FIG. 55 , the inductor L should limit the RMS current through the coupling capacitors (to provide adiabatic operation) while also providing a relatively constant output voltage V O . This can be achieved by having a large inductance and/or a capacitance (not shown) in parallel with the load  18 A. However, a large inductance consumes considerable area. And to make matters worse, the windings necessary for a large inductance will cause considerable resistive losses. 
     By correctly choosing the inductance and capacitance (not shown) in  FIG. 55 , it is possible to constrain the current I X  while generating a relatively static output voltage V O . In particular, a proper choice of inductance will generate a rectified sinusoidal current I X  as shown in  FIG. 56  that will nevertheless result in a limited RMS current through the coupling capacitors and a relatively constant output voltage V O . 
     In  FIG. 56 , the boundary between each half-cycle of the sinusoid corresponding to a switching event of the switches of the clocked current source. Ideally, the current I X  should be zero whenever a switching event occurs. This will minimize switching losses. However, in practice it is difficult to achieve such precision. Moreover, in any attempt to achieve such precision, there is a risk that the inductance is smaller than what was expected. This will cause the current I X  to become negative, thus potentially destabilizing the circuit. 
     Accordingly, when choosing the inductance of L in  FIG. 55 , it is desirable to choose an inductance that is small enough to avoid consuming excessive area and generating loss, but that is large enough to provide some assurance that the current I X  will just graze the zero line without actually becoming negative. A suitable value of inductance can be obtained by dividing the peak-to-peak value of the voltage V X  by the product of the average value of the current I X  and the switching frequency. The result is then multiplied by a constant. A suitable constant is 13/24. 
       FIG. 57  shows a step-down converter consistent with the architecture shown in  FIG. 28 . However, in this embodiment, a switching network  12 A is adiabatically charged using a regulating circuit  16 A. The clocked current sources i clk  &amp;  i clk    are emulated by Four switches and the regulating circuit  16 A emulate the clocked current sources i clk ,  i clk   . The output capacitor C O  has also been removed so as to allow V X  to swing. In this example, the regulating circuit  16 A is a boost converter that behaves as constant source with a small AC ripple. Any power converter that has a non-capacitive input impedance at the frequency of operation would have allowed adiabatic operation. Although switch-mode power converters are attractive candidates due to their high efficiency, linear regulators are also practical. 
     In operation, closing switches labeled “ 1 ” charges capacitors C 4 , C 5 , and C 6  while discharging capacitors C 1 , C 2 , and C 3 . Similarly, closing switches “ 2 ” has the complementary effect. The first topological state (phase A) is shown in  FIG. 57 , where all switches labeled “ 1 ” are closed and all switches labeled “ 2 ” are opened. Similarly, the second topological state (phase B) is shown in  FIG. 58 , where all switches labeled “ 2 ” are closed and all switches labeled “ 1 ” are opened. 
     In this embodiment, the regulating circuit  16 A limits the RMS charge and discharging current of each capacitor. For example, capacitor C 3  is discharged through the filter inductor in the regulating circuit  16 A during phase A, while capacitor C 3  is charged through the filter inductor in regulating circuit  16 A during phase B, clearly demonstrating the adiabatic concept. Furthermore, all of the active components are implemented with switches so that the converter can process power in both directions. 
     A few representative node voltages and currents are shown in  FIG. 60 . There is a slight amount of distortion on the rising and falling edges of the two illustrated currents (I P1  and I P2 ), but for the most part, the currents resemble two clocks 180 degrees out of phase. In general, adiabatic charging occurs in cascade multipliers if at least one end of a switch stack is not loaded with a large capacitance, as is the case in this embodiment, where the V X  node is loaded down by regulating circuit  16 A. 
     In operation, different amounts of current will flow through different switches. It is therefore useful to size the switches in a manner appropriate to the currents that will be flowing through them. For example, the switches connected to V P1  and V P2  carry more current then the other switches in  FIG. 57 . By making these switches larger than the other switches, this avoids the need to have unnecessarily large switches and thus results in a smaller circuit footprint. This also avoids unnecessary additional capacitive losses, which are proportional to the size of the switch. 
     The switches shown in  FIG. 57  will transition between states at some switching frequency. It is desirable that, in order to reduce loss, the switching network  12 A operate such that the RMS current through the switches is constrained at that switching frequency. One way to ensure that this is the case is to choose the resistances of the switches such that they are so large that the RC time constant of the charge transfer between the capacitors is similar if not longer than the switching frequency. As can be seen in  FIG. 50 , by controlling the width “W” of the switches and hence their resistance and their size, the switching network  12 A can be forced into the fast-switching limit region. 
     Unfortunately, by using the resistance of the switches to constrain the RMS current, conductive power losses increase and the overall efficiency decreases. The regulating circuit  16 A, however, allows us to reduce the resistance of the switches and operate adiabatically. Therefore, the switches can be optimally sized for the highest efficiency without worrying about constraining the RMS current since it is handled by the regulating circuit  16 A (or optionally a magnetic filter). The optimal size for each switch is chosen by balancing the resistive and capacitive losses in each switch at a given switching frequency and at a given current. 
     The modular architecture with the basic building blocks shown in  FIGS. 11, 29, 30 , and  32  may be expanded to cover a wider range of applications, such as high-voltage DC, AC-DC, AC-AC, buck-boost, and multiple output voltages. Each of these applications includes separating the transformation and regulation functions. Extension of the architecture can also incorporate adiabatically charged switched-capacitor converters. 
     In many switched-capacitor converters, the number of capacitors and switches increases linearly with the transformation ratio. Thus, a large number of capacitors and switches are required if the transformation ratio is large. Alternatively, a large transformation ratio can be achieved by connecting numerous low gain stages in series, either without intervening filters, as depicted in  FIG. 61 , or with intervening filters between stages, as shown in  FIG. 63 . The transformation ratio of the total switch capacitor stack (V IN /V X ) is as follows: 
     
       
         
           
             
               
                 
                   
                     
                       V 
                       in 
                     
                     
                       V 
                       x 
                     
                   
                   = 
                   
                     
                       N 
                       1 
                     
                     × 
                     
                       N 
                       2 
                     
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     … 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     
                       N 
                       n 
                     
                   
                 
               
               
                 
                   ( 
                   2.1 
                   ) 
                 
               
             
           
         
       
     
     The main disadvantage of the series stacked configuration is that the voltage stresses on the front stages are much higher than those of the rear stages. This will normally require stages with different voltage ratings and sizes. However, the transformation ratio can be easily changed by bypassing a stage or two. 
     Adiabatic charging of a preceding series-connected switching network only occurs if the following switching network controls the charging and discharging current of the preceding stage. Thus, it is preferable to use full-wave switched-capacitor converters in the front stages or to use switched-capacitor stages such as the single-phase series-parallel switched-capacitor converters with magnetic based filters. 
       FIG. 62  shows a converter with two series-connected switching networks consistent with the architecture shown in  FIG. 61 .  FIG. 64  shows a similar architecture, but with filters between the series-connected switching networks in a manner consistent with the architecture shown in  FIG. 63 . Both switching networks  12 A,  12 D are two-phase cascade multipliers. In operation, switches labeled “ 1 ” and “ 2 ” are always in complementary states and switches labeled “ 7 ” and “ 8 ” are always in complementary states. Thus, in a first switched-state, all switches labeled “ 1 ” are open and all switches labeled “ 2 ” are closed. In a second switched-state, all switches labeled “ 1 ” are closed and all switches labeled “ 2 ” are opened. In this embodiment, closing switches  1  charges capacitors C 1 , C 2 , C 3 , while discharging capacitors C 4 , C 5 , C 6  and closing switches  2  has the complementary effect. Also, closing switches  7  charges capacitors C 7 , C 8 , C 9 , while discharging capacitors C 10 , C 11 , C 12  and closing switches  8  has the complementary effect. 
     The power converter provides a total step-down of 32:1, assuming the regulating circuit  16 A is a buck converter with a nominal step-down ratio of 2:1. Furthermore, if the input voltage is 32 V and the output voltage is 1 V, then the switches in the first switching network  12 A will need to block 8 volts while the switches in the second switching network  12 D will need to block 2 volts. 
     The modular architecture with the basic building blocks shown in  FIGS. 11, 29, 30 , and  32  may be configured to handle an AC input voltage as shown in  FIG. 65 . An AC rectification stage  19 A receives an AC waveform from an AC source  14 B and provides an average DC voltage to a converter  10 , the output of which is connected to a load  18 A. In this embodiment, the converter  10  can be isolated or otherwise. 
     One of the main attributes of switched-capacitor converters is their ability to operate efficiency over a large input range by reconfiguring the switched-capacitor network. If the AC wall voltage (i.e. 60 Hz &amp; 120 V RMS ) can be thought of as a slow-moving DC voltage, then a front-end AC switching network  13 A should be able to unfold the time-varying input voltage into a relatively stable DC voltage. 
       FIG. 66  shows a diagram of a 120 V RMS  AC waveform over a single 60 Hz cycle overlaid with the unfolded DC voltage.  FIG. 67  shows an AC switching network  13 A of the sort that can incorporate the AC rectification stage  19 A of  FIG. 65 . The AC switching network  13 A is a front-end switched-capacitor stage (i.e., switching network) in combination with a selective inverting stage (i.e., rectifying stage). The front-end switched-capacitor stage has different configurations (1/3, 1/2, 1/1) at its disposal. In the particular embodiments shown, the AC switching network  13 A keeps the DC voltage under 60 V. In some embodiments, the AC switching network  13 A is a special-purpose adiabatic switched-capacitor network. 
     Once the AC switching network  13 A has unfolded the AC voltage, a regulating circuit  16 A, shown in  FIG. 67 , produces a final output voltage. In some embodiments, another switching network  16 A between the AC switching network  13 A and the regulating circuit  16 A further conditions the voltage. If this is the case, then the caveats for series-connected stages hold true since the AC switching network  13 A is a special purpose switching network  12 A. Some form of magnetic or electric isolation is also common in AC-DC converters for safety reasons. Hence, in  FIG. 67 , voltages: V AC , V DC , and V O  are purposely defined as being agnostic to a common ground. 
       FIG. 68  shows an AC-DC converter corresponding to the architecture shown in  FIG. 67 . In this embodiment, the AC switching network  13 A is a synchronous AC bridge rectifier followed by a reconfigurable two-phase step-down cascade multiplier with three distinct conversion ratios (1/3, 1/2, 1/1) while the regulating circuit  16 A is a synchronous buck converter. In operation, switches labeled  7  and  8  are always in complementary states. During the positive portion of the AC cycle (0 to π radians) all switches labeled “ 7 ” are closed while all switches labeled “ 8 ” are opened as shown in  FIG. 69 . Similarly, during the negative portion of the AC cycle (π to 2π radians) all switches labeled  8  are closed while all switches labeled “ 7 ” are opened as shown in  FIG. 70 . 
     In addition to the inverting function provided by switches  7  and  8 , switches  1 A- 1 E and switches  2 A- 2 E may be selectively opened and closed as shown in Table 1 to provide three distinct conversion ratios of: 1/3, 1/2, and 1. 
     
       
         
           
               
               
               
               
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 V 2 /V 1   
                 1A 
                 1B 
                 1C 
                 1D 
                 1E 
                 2A 
                 2B 
                 2C 
                 2D 
                 2E 
               
               
                   
               
             
            
               
                 1/3 
                 CLK 
                 CLK 
                 CLK 
                 CLK 
                 CLK 
                 CLKB 
                 CLKB 
                 CLKB 
                 CLKB 
                 CLKB 
               
               
                 1/2 
                 CLKB 
                 CLK 
                 CLK 
                 CLK 
                 CLK 
                 CLK 
                 CLKB 
                 CLKB 
                 CLKB 
                 CLKB 
               
               
                 1/1 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
                 ON 
                 ON 
                 ON 
                 OFF 
                 OFF 
               
               
                   
               
            
           
         
       
     
     The AC switching network  13 A is provided with a digital clock signal CLK. A second signal CLKB is also generated, which may simply be the complement of CLK (i.e. is high when CLK is low and low when CLK is high), or which may be generated as a non-overlapping complement. With a switching pattern set in accordance with the first row of Table 1, the AC switching network  13 A provides a step-down ratio of one-third (⅓). With a switching pattern set in accordance with the second row of Table 1, the AC switching network  13 A provides a step-down ratio of one-half (½). With a switching pattern set in accordance with the third row of Table 1, the AC switching network  13 A provides a step-down ratio of one. 
     Most power supplies attached to the wall meet some power factor specification. Power factor is a dimensionless number between 0 and 1 that defines a ratio of the real power flowing to apparent power. A common way to control the harmonic current and thus boost the power factor is by using an active power factor corrector.  FIG. 71  shows an AC-DC converter  8  that controls harmonic current and boosts power factor towards unity. The illustrated AC-DC converter  8  features an AC switching network  13 A that receives an AC voltage from an AC source  14 B and rectifies it. An output of the AC switching network  13 A connects to an input of an active power-factor correction circuit  17 A. The AC switching network  13 A may also provide voltage transformation via a switched-capacitor circuit. The power-factor correction circuit  21 A controls its input current so that it remains, to the greatest extent possible, in-phase with the voltage waveform provided by the AC source  14 B. This drives reactive power toward zero. The output of the power-factor correction circuit  17 A is then provided to a regulating circuit  16 A that operates in the same way as shown in  FIG. 67 . 
       FIG. 72  shows a particular embodiment of  FIG. 65 &#39;s modular power converter  10  connected between first and second circuits  51 ,  52 . The first and second circuits  51 ,  52  can be a source, a load, or another circuit, such as a power converter, a PFC circuit, or an EMI filter. 
     The illustrated power converter  10  includes a regulating circuit  16 A, a switching network  12 A, and an isolated controller  60 . As used herein, a circuit having an input and an output is considered isolated if the input voltage and the output voltage do not share a common ground. Such isolation can be carried out by having the input voltage correspond to an input voltage of a transformer and having the output voltage corresponds to an output voltage of a transformer. In some embodiments, the regulating circuit  16 A is isolated. In other embodiments, it is the switching network  12 A that is isolated. Although only one of the foregoing is needed to consider the modular DC-DC converter  10  as a whole isolated, there are also embodiments in which both the switching network  12 A and the regulating circuit  16 A are isolated. 
     In some embodiments, the switching network  12 A is an unregulated switched-capacitor converter having a fixed voltage-conversion ratio. These embodiments generally include a regulating circuit  16 A to regulate the output of the switching network  12 A. Examples of a suitable regulating circuit  16 A include a boost converter, a buck converter, a fly-back converter, and a linear regulator. 
       FIG. 73  shows a variation of the converter shown in  FIG. 72  in which an LC filter  21 A is added between the switching network  12 A and the second circuit  252 . The purpose of the LC filter is to promote adiabatic charging of the switching network  12 A via the method shown in  FIG. 53 . 
       FIG. 74  shows a particular embodiment of the modular DC-DC converter  10  shown in  FIG. 73 . The regulating circuit  16 A is implemented as a fly-back converter having a switch S 1 , a diode D 1 , a capacitor C 1 , and a transformer T 1 . When operating in continuous conduction mode, the regulating circuit  16 A transitions between first and second states. In the first state, the switch S 1  is closed, and the diode D 1  does not conduct. During this first state, the capacitor C 1  acts as a charge reservoir to supply power to the output of the regulator  16 A. In the second state, the switch S 1  is opened and the diode D 1  conducts. 
     As shown in  FIG. 74 , the isolated controller  60  includes a first control signal CTR 1  that controls the switching network  12 A, a second control signal CTR 2  that controls the regulating circuit  16 A, and an isolation barrier  61  between them. As a result, the first and second control signals CRT 1 , CTR 2  have different grounds and connect to different sides of the transformer T 1 . The isolation barrier  61  can include any one or more of sonic isolation, optical isolation, capacitive isolation, inductive isolation, and mechanical isolation. 
     The embodiment shown in  FIG. 29  can be modified to operate with an AC source  14 B, as shown in  FIG. 75 , which shows a modular DC-DC converter  10  connected between first and second circuits  51 ,  52 . The modular DC-DC converter  10  includes first and second switching networks  12 A,  12 B and a regulating circuit  16 A. The first switching network  12 A receives, at its input thereof, a voltage from the first circuit  251 . The second switching network  12 B provides its output to the second circuit  252 . The regulating circuit  16 A receives an output from the first switching network  12 A and provides its own output to an input of the second switching network  12 B. An isolated controller  60  provides a first control signal to the first switching network  12 A, a second control signal to the second switching network  12 B, and a third control signal to the regulating circuit  16 A. 
     Similarly, the embodiment shown in  FIG. 32  can be modified to operate with an AC source  14 B, as shown in  FIG. 76 , which shows first and second regulating circuits  16 A,  16 B and a switching network  12 A. The first regulating circuit  16 A receives, at its input, a voltage from the first circuit  251 . The second regulating circuit  16 B provides its output to the second circuit  252 . The switching network  12 A receives an output from the first regulating circuit  16 A and provides its own output to an input of the second regulating circuit  126 . An isolated controller  60  provides a first control signal to the first regulating circuit  16 A, a second control signal to the regulating circuit  16 B, and a third control signal to the switching network  12 A. In some embodiments, as shown in  FIG. 73 , the second regulating circuit  16 B can be implemented as an LC filter  21 A. The AC rectification stage  19 A shown in  FIG. 65  can be implemented in a variety of ways. In one embodiment, shown in  FIG. 77 , the rectifier  19 A features a fuse  71 , a capacitor C 1 , an AC bridge  80 , and a first electromagnetic interference filter  70 A between the AC bridge  80  and the AC source  14 B. In another embodiment, shown in  FIG. 78 , a second EMI filter  70 B and a power-factor correction circuit  90  replaces the capacitor C 1 . 
     The first electromagnetic interference filter  70 A, implementations of which can be seen in  FIGS. 79 and 80 , reduces the common-mode and differential-mode noise produced by the AC-DC converter  8  by a desired amount. The extent to which such noise is reduced is typically set by a government body, such as the FCC. 
     The AC bridge  80  accepts an AC voltage and outputs an average DC voltage. A particular implementation of an AC bridge  80  is shown in  FIG. 81 . The bridge includes first, second, third, and fourth diodes D 1 , D 2 , D 3 , D 4 . In operation, the AC bridge  80  transitions between first and second states. In the first state, the first and third diodes D 1 , D 3  are reverse biased, and the second and fourth diodes are forward biased. In the second state, the second and fourth diodes D 2 , D 4  are forward biased and the first and third diodes D 1 , D 3  are reverse biased. 
     Many modern devices require different voltages to operate different components, such as power management integrated circuits (PMICs) in cell phones. For example, one voltage may be required to operate a processor, whereas another voltage may be needed to operate a display. In principle, one could have a separate transformation stage and regulation stage corresponding to each required output voltage. However, this solution is wasteful both of physical space and of pin count. A solution to this difficulty is that shown in  FIG. 82 , in which one transformation stage drives two or more regulation stages in parallel. Each regulation stage thus provides a separate output voltage. The regulator stage can be any of those already described, including a linear regulator. As shown in  FIG. 83 , some embodiments include a filter between the transformation stage and the regulation stages. 
     To ensure adiabatic charging of the switched-capacitor network in the transformation stage, it is preferable that the majority of the power drawn by the various regulation stages come by way of a constant current (or constrained current). This can be achieved, for example, by synchronizing the regulation stages so that they draw as constant a current as possible, thus avoiding larger resistive losses (i.e., due to higher RMS current) in the switched-capacitor network of the transformation stage. 
       FIGS. 84-80  show specific implementations of modular power converters that conform to the architectural diagrams shown in  FIGS. 28, 29, 30, and 32 . In each implementation a regulating circuit or multiple regulating circuits may limit both the RMS charging current and the RMS discharging current of at least one capacitor in each switching network so all of these switching networks are adiabatically charged switching networks. However, if decoupling capacitors  9 A or  9 B are present, then the ability of the regulating circuit to limit the RMS charging and discharging current may be diminished. Capacitors  9 A and  9 B are optional and to keep the output voltage fairly constant capacitor C O  is used. All of the stages share a common ground, however this need not be case. For example, if a regulating circuit is implemented as a fly-back converter than the ground can be separated easily, even a switching network can have separate grounds through capacitive isolation. Furthermore, for simplicity, the switching network in each implementation has a single conversion ratio. However, reconfigurable switching networks that provide power conversion at multiple distinct conversion ratios may be used instead. 
     In operation, switches labeled “ 1 ” and “ 2 ” are always in complementary states. Thus, in a first switched-state, all switches labeled “ 1 ” are open and all switches labeled “ 2 ” are closed. In a second switched-state, all switches labeled “ 1 ” are closed and all switches labeled “ 2 ” are opened. Similarly, switches labeled “ 3 ” are “ 4 ” are in complementary states, switches labeled “ 5 ” are “ 6 ” are in complementary states, and switches labeled “ 7 ” are “ 8 ” are in complementary states. Typically, the regulating circuits operate at higher switching frequencies than the switching networks. However, there is no requirement on the switching frequencies between and amongst the switching networks and regulating circuits. 
       FIG. 84  shows a step-up converter corresponding to the architecture shown in  FIG. 11 . In this embodiment, the switching network  12 A is a two-phase step-up cascade multiplier with a conversion ratio of 1:3 while the regulating circuit  16 A is a two-phase boost converter. In operation, closing switches labeled  1  and opening switches  2  charges capacitors C 3  and C 4  while discharging capacitors C 1  and C 2 . Conversely, opening switches  1  and closing switches  2  charges capacitors C 1  and C 2  while discharging capacitors C 3  and C 4 . 
       FIG. 8  shows bidirectional step-down converter corresponding to the architecture shown in  FIG. 28 . In this embodiment, the switching network  12 A is a two-phase step-down cascade multiplier with a conversion ratio of 4:1 while the regulating circuit  16 A is synchronous buck converter. In operation, closing switches  1  and opening switches  2  charges capacitors C 1 , C 2 , and C 3  while discharging capacitors C 4 , C 5 , and C 6 . Conversely, opening switches  1  and closing switches  2  charges capacitors C 4 , C 5 , and C 6  while discharging capacitors C 1 , C 2 , and C 3 . All of the active components are implemented with switches so that the converter can process power in both directions. 
       FIG. 86  shows a step-up converter consistent with the architecture shown in  FIG. 30 . In this embodiment, the regulating circuit  16 A is boost converter while the switching network  12 A is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1:2. In operation, closing switches  1  charges capacitor C 2  while discharging capacitor C 1 . Closing switches  2  has the complementary effect. 
       FIG. 87  shows a bidirectional up-down converter consistent with the architecture shown in  FIG. 30 . In this embodiment, the regulating circuit  16 A is synchronous four switch buck-boost converter while the switching network  12 A is a two-phase step-up cascade multiplier with a conversion ratio of 1:4. In operation, closing switches  1  charges capacitors C 4 , C 5 , and C 6  while discharging capacitors C 1 , C 2 , and C 3 . Closing switches  2  has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions. 
       FIG. 88  shows an inverting up-down converter consistent with the architecture shown in  FIG. 2 . In this embodiment, the first switching network  12 A is a step-down series-parallel switched-capacitor converter with a conversion ratio of 2:1, the first regulating circuit  16 A is a buck/boost converter; and the second switching network  12 B is a step-up series-parallel switched-capacitor converter with a conversion ratio of 1:2. In operation, closing switches  1  charges capacitor C 1  while closing switches  2  discharges capacitor C 1 . Similarly, closing switches  7  discharges capacitor C 2  while closing switches  8  charges capacitor C 2 . 
       FIG. 89  shows a bidirectional inverting up-down converter consistent with the architecture shown in  FIG. 29 . In this embodiment, the first switching network  12 A is a two-phase step-down series-parallel switched-capacitor converter with a conversion ratio of 2:1, the regulating circuit  16 A is a synchronous buck/boost converter and the second switching network  12 B is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1:2. In operation, closing switches  1  charges capacitor C 1  while discharging capacitor C 2 . Closing switches  2  has the complementary effect. Similarly, closing switches  7  charges capacitor C 4  while discharging capacitor C 3 . Closing switches  2  has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions. 
       FIG. 90  shows a step-down converter consistent with the block diagram shown in  FIG. 32 . In this embodiment, the first regulating circuit  300 A is a boost converter, the switching network  200  is a two-phase step-up series-parallel switched-capacitor converter with a conversion ratio of 1:2, and the second regulating circuit  300 B is a boost converter. In operation, closing switches  1  charges capacitors C 1  and C 2  while simultaneously discharging capacitors C 3  and C 4 . Closing switches  2  has the complementary effect. 
       FIG. 80  shows a bidirectional up-down converter consistent with the block diagram shown in  FIG. 32 . In this embodiment, the first regulating circuit  300 A is a synchronous boost converter, the switching network  200  is a two-phase fractional step-down series-parallel switched-capacitor converter with a conversion ratio of 3:2 and the second regulating circuit  300 B is a synchronous buck converter. In operation, closing switches  1  charges capacitors C 3  and C 4  while simultaneously discharging capacitors C 1  and C 2 . Closing switches  2  has the complementary effect. All of the active components are implemented with switches so that the converter can process power in both directions. 
     It should be understood that the topology of the regulating circuit can be any type of power converter with the ability to regulate the output voltage, including, but without limitation, synchronous buck, three-level synchronous buck, sepic, soft switched or resonant converters. Similarly, the switching networks can be realized with a variety of switched-capacitor topologies, depending on desired voltage transformation and permitted switch voltage. 
     The physical implementation of the foregoing switching networks  12 A includes four primary components: passive device layers, active device layers, interconnect structures, and thru-vias. The passive device layers have passive devices, such as capacitors. The active device layers have active devices, such as switches. 
     The separation of active and passive devices in different layers arises because active devices are made by CMOS processing. Thus, if one has passive devices on the same layer, they must be made by CMOS-compatible processing steps to avoid destroying the active devices. This constraint makes it difficult to manufacture capacitors that provide high capacitance in a small area of the chip. It also makes it difficult to make high Q inductors. To avoid these difficulties, it is preferable to produce integrated passive devices on their own wafer with a process flow that is optimized for producing such passive devices. 
     In some embodiments, the devices are integrated into a single monolithic substrate. In other embodiments, the devices are integrated into multiple monolithic substrates. The monolithic substrates are typically made of semiconductor material, such as silicon. 
     In a preferred practice, one makes passive devices on a passive device layer using an integrated passive device process and makes active devices on an active device layer using a CMOS process. These device layers are electrically connected together through a fine interconnect structure that includes thru-vias to allow electrical connections across device layers. 
       FIG. 92  shows a circuit block diagram of a modular converter that uses capacitors in a switched-capacitor circuit to transfer energy. The block diagram shows a stack of layers that includes layers for both switches and capacitors. The switches within the stack of layers include first and second switches S 1 , S 2 . The capacitors within the stack of layers includes first and second capacitors C 1 , C 2 . A discrete inductor L 1  is mounted outside the layer stack. 
     The layers within the stack of layers in  FIG. 92  can be stacked in different ways.  FIGS. 93-95  show side views of different ways of stacking layers, and placement of the interconnect structure and vias corresponding to each such configuration of layers. The active device layers (also known as switch device layer) include switches while the passive device layers include capacitors. 
     In  FIG. 93 , an active device layer connects to a printed-circuit board via a set of C4 bumps and a passive device layer is stacked above the active device layer. Thru-vias TV provide a connection between the printed-circuit board and an interconnect structure between the two layers. 
     In  FIG. 94 , this orientation is reversed, with the passive layer being connected to the printed-circuit board by the C4 bumps and the active layer above the passive layer. Once again, thru-vias TV provide a connection between the printed-circuit board and an interconnect structure between the two layers. 
       FIG. 95  shows the possibility of stacking multiple passive or active layers. In the particular embodiment shown, there are n passive devices layers and one active device layer. Through vias TV provide a path for connecting the printed-circuit board to interconnect structures between adjacent layers. 
       FIG. 96  shows an embodiment that has at least two device layers, one of which has switches and another of which has capacitors. 
     The C4 bumps are laid out along the printed-circuit board at a first pitch. An interconnect structure includes C5 bumps laid out at a second pitch that is smaller than the first pitch. An example of such C5 bumps can be seen in  FIG. 106 . 
     Each passive layer has capacitors that occupy a certain footprint on the chip. The capacitors are located such that each one is within a footprint of a switch on an active layer that is above or below the passive layer. Such an arrangement helps reduce energy loss and other parasitic losses in the interconnect structures. 
     Additional permutations arise because, as a result of the nature of known semiconductor fabrication processes, it is common to process only one face of a wafer. This face of the wafer has devices integrated into it. For this reason, it is called the “device face.” 
     For each stack configuration, there are now additional permutations concerning whether the device face is an upper face or a lower face. For a given layer, with reference to the z-axis shown in  FIGS. 93-95 , an “upper face” of that layer faces in the +z direction a “lower face” faces in the −z direction. 
     As used herein, a layer is said to “face” the +z direction if a vector that is perpendicular to a plane defined by that layer and that is directed in a direction away from that layer is directed in the +z direction. A layer is said to face in the −z direction if it does not face the +z direction. 
     For the case in which there are only two device layers,  FIGS. 97-99  show the four possible configurations of device faces when the upper layer is the passive layer, as shown in  FIG. 93 .  FIGS. 101-104  show the four possible configurations of device faces when the upper layer is the active layer, as shown in  FIG. 94 . 
     In  FIG. 97 , the active layer&#39;s device face is its upper face and the passive layer&#39;s device face is its lower face. Given that there are only two layers, this means they face each other.  FIG. 99  shows a converse case in which the passive layer&#39;s device face is its upper face and the active layer&#39;s device face is its lower face. In  FIG. 98 , both the device faces of both the active and passive layers are on upper faces, whereas in  FIG. 100  both are on lower faces. 
       FIGS. 101-104  show the converse of  FIGS. 97-100  for the case in which the active layer is now the upper layer. In  FIG. 101 , the active devices are on a lower face and the passive devices are on an upper face. Since there are only two layers, the active and passive devices face each other as they did in  FIG. 97 . In  FIG. 102 , the active devices and passive devices are on upper faces of their respective layers, whereas in  FIG. 104  they are on lower faces of their respective layers. In  FIG. 103 , the active devices are on an upper face and the passive devices are on a lower face. 
     Naturally, certain configurations are preferable to others. The choice will depend upon numerous factors, most of which relate to thru-via technology and the number of pins that are available to connect the layers to external circuitry. 
     The passive device layer and active device layer can be in any form when attached. Two common choices would be in die or wafer form. 
       FIGS. 104-106  show cross-sections of two die-to-die arrangements in which an interconnect structure connects switches in an active die to capacitors on a passive die. In  FIG. 104 , the switches connect to a planar capacitor whereas in  FIG. 106  the switches connect to a trench capacitor. The first bumps C4, which provide the electrical connections from the die stack to the printed-circuit board, and through-vias TV are omitted in  FIGS. 104-106  but can be seen in  FIGS. 107-108 . 
     Although any kind of capacitor can be used, trench capacitors are preferable to planar capacitors because trench capacitors offer greater capacitance per unit of die area than planar capacitors, sometimes by one or two orders of magnitude. Additionally, trench capacitors offer lower equivalent series resistance than planar capacitors. Both of these capacitor attributes are desirable for use in power converters that use capacitive energy transfer because they affect the efficiency of the power converter. 
     As shown in  FIGS. 104-106 , an interconnect structure connects the switches on the active die to the capacitors on the passive die. This interconnect structure can be implemented in numerous ways. In the case of  FIGS. 104-106 , the interconnect structure is the union of a multilayer interconnect structure on the passive die, a single layer of second bumps C5, and a multilayer interconnect structure on the active die. The only requirements are that the interconnect structure connects the switches on one device layer to the capacitors on the other device layer, that the two device layers are stacked one on top of the other, and that the second bumps C5 have a much finer pitch than the first bumps C4. In some embodiments, the pitch of the second bumps C5 is four times greater than the pitch of the first bumps. As used herein, “pitch” means the number of bumps per unit length. 
       FIGS. 107-108  show another embodiment implemented by wafer-to-wafer stacking. In this embodiment, there is no need for the second bumps C5. Instead, the active and passive wafers electrically connect to each other using a bonding process. In  FIG. 107 , the device face of the active layer is its lower face and in  FIG. 108 , the device face of the active layer is its upper face. Examples of suitable bonding processes are copper-copper and oxide-oxide bonding. Furthermore,  FIGS. 107-108  show the thru-vias and some of the first bumps C4, which were omitted in  FIGS. 104-106 . 
     A switched-capacitor power converter of the type discussed herein has a great many switches and capacitors in a switched-capacitor power converter. These all have to be interconnected correctly for the power converter to operate. There are many ways to physically lay out the conducting paths that interconnect these components. However, not all of these ways are equally efficient. Depending on their geometry, some of these conducting paths may introduce noticeable parasitic resistance and/or inductance. Because there are so many interconnections, it can be a daunting challenge to choose a set of interconnections that will both provide acceptable parasitic resistance and inductance for the power converter as a whole. 
     One method that can be used to control these parasitic quantities is to partition the switches and capacitors. 
     One way to reduce such parasitic quantities is to choose the shape and locations of the switches on the active layer so that they fit beneath the capacitors on the passive layer. This avoids forcing current to undertake a long journey along the faces of the layers as it travels between a switch and a capacitor. An example of this technique is shown in  FIG. 110 , in which eight switches S 1 -S 8  and a controller  20 A are disposed on an active layer that is located below a passive layer having two capacitors. Although the switches are not completely visible through the passive layer, their locations are marked by dotted lines on  FIG. 110 . The figure shows a first capacitor C 1  on top of switches S 1 , S 2 , S 5 , S 6  and a second capacitor C 2  on top of switches S 3 , S 4 , S 7 , S 8 . 
     Another way to reduce such parasitic quantities arises from recognizing that switches in a switching network  12 A are usually active devices that are implemented with transistors. The switching network  12 A may be integrated on a single monolithic semiconductor substrate or on multiple monolithic semiconductor substrates, or formed using discrete devices. Furthermore, since the device is a power converter, each switch may be expected to carry a large amount of current. A switch that carries a great deal of current is often implemented by numerous current paths connected in parallel to a common terminal. 
     In a switch as described above, the current paths that make up the switch are physically located side-by-side and thus occupy a space having a non-zero width. These current paths all connect to a terminal that is itself connected to a conducting path. An example of this configuration is shown in  FIG. 109  and  FIG. 112 . In particular,  FIG. 112  shows a transistor on a first layer and a capacitor on a lower layer. The transistor has first, second, and third current paths with the second current path being between the first and third. The three current paths extend between one source terminal and one drain terminal of the transistor. 
     Some current entering the source terminal shown in  FIG. 112  goes straight ahead into the second current path. But some of it turns left or right before turning again to proceed down the first and third current paths. At the other end of the transistor&#39;s channel, current that traversed the first and third current paths must again make a turn to reach the drain terminal. These currents are referred to as “lateral” current. 
     Similarly, the lower layer of  FIG. 112  shows a capacitor that has three separate current paths connected to first and second capacitor terminals. In the course of being charged and discharged, some lateral current is inevitable for reasons discussed in connection with the transistor in the upper layer. 
     One way to reduce this lateral current is to partition the switches and the capacitors into numerous partitions, as shown in  FIG. 109  and  FIG. 113 . This partitioning essentially involves converting an n-terminal device into an (n+m) terminal device where m depends on the number of partitions. Thus, after having been partitioned, the two-terminal capacitor of  FIG. 112  is transformed into a six-terminal capacitor in  FIG. 113 . Similarly, the source terminal and drain terminal of the transistor in  FIG. 112  is transformed into three source terminals and three drain terminals in the transistor of  FIG. 113 . 
     The difference between  FIGS. 112 and 113  is that each current path in  FIG. 113  has its own terminal. In contrast, in  FIG. 112 , all current paths share the same terminals. Thus,  FIG. 112  shows three current paths connected in parallel, whereas  FIG. 113  shows three current paths that are partitioned and therefore isolated from each other. 
     The three current paths shown collectively represent a switch on an active layer that is formed by various doping profiles along a piece of silicon to provide charge carriers and then connecting those three lines to a pair of external terminals, as shown in  FIG. 112 , or connecting each line to its own pair of external terminals, as shown in  FIG. 113 . 
     The capacitor represented by the lower layer of  FIG. 112  is a two-terminal capacitor like any conventional capacitor. Prior art converters use capacitors of this type. However, unlike prior art converters, which use two-terminal capacitors, a converter as disclosed herein uses a six-terminal capacitor as shown  FIG. 113 . Although such a capacitor is more complex because it has more terminals that need to be both made and properly aligned, it reduces parasitic effects caused by lateral current. 
     Similarly, the transistor switch represented by the upper layer of  FIG. 112  has one source terminal and one drain terminal. This is the kind of transistor that is used in conventional power converters. In contrast, the transistor represented by the upper layer of  FIG. 113  has three source terminals and three drain terminals. Although such a transistor is more complex because it has more terminals that need to be both made and properly aligned, it reduces parasitic effects caused by lateral current. 
     It should be apparent that the act of partitioning is geometry-independent. Its essence is that of turning an n-terminal device into an (n+m) terminal device in an effort to reduce parasitic effects. There is no requirement that the device be oriented in any particular way. In particular, there is no requirement that the partitioning be carried out in only one dimension as shown in  FIG. 113 . For example, it is quite possible to partition a component along x and y directions as shown in the nine-partition switch of  FIG. 111  and the six-partition capacitor shown in  FIG. 114 . 
     Both the techniques shown in  FIG. 113  and  FIG. 114  reduce the vertical and lateral distance between the active and passive devices while also providing a uniform current distribution to each individual switch and/or switched-capacitor cell. This tends to reduce the parasitic resistance and inductance of the connection between the switches and capacitors. This offers considerable advantages. Parasitic inductance limits the switching speed while parasitic resistance limits the efficiency of the power conversion process. 
       FIG. 115  shows a functional block diagram of the switching network  12 A of  FIGS. 13 and 12 . The illustrated switching network  12 A is a two-phase cascade multiplier that transforms a first voltage V 1  into a second voltage V 2 . It does so by choreographing the flow of charge into and out of charge-transfer capacitors (also known as coupling capacitors) in a first charge-transfer capacitor set  50 A. 
     Depending upon the type of capacitor, each charge-transfer capacitor may have a capacitance that is a function of the voltage across it. The charge-transfer capacitors are selected so that they all have the same capacitance at their respective operating voltages. However, at the same voltage, it may well be that the different charge-transfer capacitors will have different capacitances (e.g., MLCC have a strong capacitance dependence upon dc voltage bias). 
     The switching network  12 A includes first and second phase-switch sets  54 A,  54 B, one for each phase. The switches within each phase-switch set  54 A,  54 B will be referred to herein as “phase switches.” Similarly, the switching network  12 A includes first and second stack-switch sets  52 A,  52 B, again, one for each phase. The switches within each stack-switch set  52 A,  52 B will be referred to herein as “stack switches.” 
     Each of the switches takes up a certain amount of area on semiconductor substrate (e.g., silicon, GaAs, GaN, and SiC). The areas taken up by each switch need not be the same, however. In general, it is useful to have switches that are expected to carry considerable amounts of current be larger than those that carry less current. This permits the overall circuit to be smaller, while avoiding excessive conductive losses. 
     One or more of the switches can be partitioned to discourage lateral flow of current within the area defined by the switch. This can be carried out by having multiple terminals on each end of the switch. With such multiple terminals, current entering through any one terminal will be more likely to flow to a terminal directly opposite, thus reducing the extent of lateral current flow within the switch. 
     To control operation of the phase switches and the stack switches, the switching network  12 A features two separate and distinct controllers: a phase controller  59 A to control the phase switches and a stack controller  51  to control the stack switches. 
     The phase controller  59 A controls the phase switches based at least in part on a phase-controller input signal I O1 . It does so through a phase control path  55 B that connects the phase controller  59 A to the phase switches. Meanwhile, the stack controller  51  controls the stack switches based at least in part on a stack-controller input signal I O2 . It does so through a stack control path  55 A that connects the stack controller  51  to the stack switches. An inter-controller commissure  57  provides communication between the phase controller  59 A and the stack controller  51 . This permits the phase controller  59 A and the stack controller  51  to control the phase switches and stack switches in a coordinated fashion rather than independently. 
     An advantage of the manufacturing procedures used in integrated circuits is the ability to integrate many components on a single die. This makes it easier to manufacture many components at once, and to thus reduce the manufacturing cost per component. 
     One way to manufacture the switching network  12 A shown in  FIG. 115  is to place the first and second stack-switch sets  52 A,  52 B and the first and second phase-switch sets  54 A,  54 B on the same die. Since only one die has to be manufactured, the cost of manufacture on a per switch basis would be expected to be reduced. 
     Because of their roles in the circuit, the stack switches and the phase switches have different requirements. In particular, the phase switches do not experience such high voltages or currents. As a result, the phase switches are relatively simple and inexpensive to manufacture. On the other hand, the stack switches are regularly exposed to fairly high voltage differences across them. Because of these special needs, the stack switches require different manufacturing steps. 
     The more complex procedure used to manufacture stack switches can be used to also manufacture phase switches. Thus, it is feasible to manufacture the first and second stack-switch sets  52 A,  52 B and the first and second phase-switch sets  54 A,  54 B on the same integrated circuit. This offers the advantage of having to carry out only one manufacturing procedure. 
     The switching network  12 A shown in  FIG. 115  avoids this advantage by having the first and second stack-switch sets  52 A,  52 B and the first and second phase-switch sets  54 A,  54 B be on different dies instead of on the same die. As a result, it becomes necessary to use two manufacturing steps instead of a single manufacture step. 
     Specifically,  FIG. 115  shows a first phase-die  58 A and a stack-die  56 . The first phase-die  58 A contains the first and second phase-switch sets  54 A,  54 B and the phase controller  59 A. The stack-die  56  contains the first and second stack-switch sets  52 A,  52 B and the stack controller  51 . 
     In some embodiments, one or both of the phase controller  59 A and the stack controller  51  are also on separate controller dies, thus further increasing the number of separate manufacturing operations that must be carried out to construct the switching network  12 A. 
     In the embodiment shown in  FIG. 115 , the first and second phase-switch sets  54 A,  54 B are both on the first phase-die  58 A and the first and second stack-switch sets  52 A,  52 B are on a separate stack-die  56 . Thus, each die is associated with both phases. However, it is also possible to place each phase on its own die. 
     For example,  FIG. 116  shows a circuit that transforms a first voltage V 1  into a second voltage V 2 , which it provides to the load  18 A. The circuit has four separate dies: a first phase-die for the first phase-switch set  54 A, a second phase-die for the second phase-switch set  54 B, a first stack-die for the first stack-switch set  52 A, and a fourth stack-die for the second stack-switch set  52 B. In this embodiment, the first phase-switch set  54 A and the first stack-die are associated with the first phase, and the second phase-switch set  54 B and the second stack-switch set  52 B are associated with the second phase. 
     In  FIG. 116 , the phase controller  59 A and the stack controller  51  have been omitted to promote clarity. The switches are also shown schematically instead of as transistors. Had they been shown as transistors, the phase controller  59 A and the stack controller  51  would connect to the gate terminals of those transistors. 
     The first phase-switch set  54 A in  FIG. 115  corresponds to first and second phase switches S P1 , S P2  in  FIG. 116 . The second phase-switch set  54 B in  FIG. 115  correspond to third and fourth switches S P3 , S P4  in  FIG. 116 . These are placed together on the same first phase-die  58 A in  FIG. 115 . 
     The first stack-switch set  52 A in  FIG. 115  corresponds to the switches S 1A , S 2A , S 3A , S 4A  in  FIG. 116 . The second stack-switches  52 B in  FIG. 115  correspond to the switches S 1B , S 2B , S 3B , S 4B  in  FIG. 116 . These are all placed together on the same stack-die  56  in  FIG. 115 . 
     In connecting the various switches to the corresponding charge-transfer capacitors C 1A , C 2A , C 3A , C 4A , C 1B , C 2B , C 3B , C 4B  of the first charge-transfer capacitor set  50 A, it is useful to avoid excessive path lengths between the charge-transfer capacitors C 1A , C 2A , C 3A , C 4A , C 1B , C 2B , C 3B , C 4B  and the stack switches S 1A , S 2A , S 3A , S 4A , S 1B , S 2B , S 3B , S 4B , S P1 , S P2 , S P3 , S P4 . Excessive path lengths are undesirable because they increase resistance between components. These path lengths can be reduced by suitably arranging the dies and the locations of the terminals on each die. 
       FIG. 117  shows a particular implementation of terminals on the stack-die  56  and terminals on the first phase-die  58 A for the embodiment shown in  FIG. 115 . Charge-transfer capacitors from the first charge-transfer capacitor set  50 A extend between the stack-die  56  and the first phase-die  58 A. The terminals shown in  FIG. 116  have been configured so that those that connect to the positive terminals of the charge-transfer capacitors are all on one side and those that connect to the negative terminals of the charge-transfer capacitors are all on the other side. This reduces path length between the stack switches, the phase switches, and the charge-transfer capacitors. 
     As shown in  FIG. 115 , both the stack-die  56  and the first phase-die  58 A connect to the output of the switching network  12 A. In  FIG. 117 , a conducting interdie commissure  63  of length Y 1  connects the output terminal of the switching network  12 A to both the stack-die  56  and the first phase-die  58 A. This length Y 1  is tuned to the length of the capacitors in the first charge-transfer capacitor set  50 A. 
     The embodiment shown in  FIG. 117  results in the stack-die  56  being coplanar with the first phase-die  58 A. However, it is possible to further reduce conducting path lengths by having the stack-die  56  and first phase-die  58 A on different planes. This can be achieved by folding the layout shown in  FIG. 117  about a vertical line extending down the middle of the interdie commissure  63 . Alternatively, it is possible to have different phases on different levels by folding along a horizontal axis of symmetry. 
     In the embodiment of  FIG. 116 , each charge-transfer capacitor C 1A , C 2A , C 3A , C 4A , C 1B , C 2B , C 3B , C 4B  will at some point be connected to the first phase-switch set  54 A and to the second phase-switch set  54 B. It is possible, however, to arrange the components to form a switching network  12 A that has first and second charge-transfer capacitor sets  50 A,  50 B, each of which connects to only one of the first and second phase-switch sets  54 A,  54 B. An example of this topology can be seen in  FIG. 118 . 
       FIG. 118  shows a functional block diagram of a two-phase switching network  12 A that transforms a first voltage V 1  into a second voltage V 2 . It does so by choreographing the flow of charge into and out of charge-transfer capacitors. 
     The switching network  12 A of  FIG. 118  has first and second phase-switch sets  53 A,  53 B, one for each phase, and first and second stack-switch sets  52 A,  52 B, one for each phase. To control operation of these switches, the switching network  12 A features three separate and distinct controllers: a first phase-controller  59 A to control phase switches in the first phase-switch set  53 A, a stack controller  51  to control stack switches in the first and second stack-switch sets  52 A,  52 B, and a second phase-controller  59 B to control phase switches in the second phase-switch set  53 B. 
     The first phase-controller  59 A controls the operation of the phase switches in the first phase-switch set  53 A based in part on a first-phase-controller input signal I O1 . It does so through a first phase-control path  55 B that connects the phase controller  59 A to the phase switches. The second phase-controller  59 B controls the operation of the phase switches in the second phase-switch set  53 B based at least in part on a second-phase-controller input signal IO 3 . It does so through a second phase-control path  55 C that connects the second phase controller  59 B to the second phase-switch set  53 B. 
     The stack controller  51  receives a stack-control input signal I O2  and uses that to control the operation of the stack switches in the first and second stack-switch sets  52 A,  52 B. It does so via a stack control path  55 A. The first phase-controller  59 A, the second phase-controller  59 B, and the stack controller  51  all communicate via an inter-controller commissure  57 . 
       FIG. 119  shows a circuit with four separate dies: a first phase-die for the first phase-switch set  53 A, a second phase-die for the second phase-switch set  53 B, a first stack-die for the first stack-switch set  52 A, and a fourth stack-die for the second stack-switch set  52 B. 
     In this embodiment, the first phase-switch set  54 A and the first stack-die are associated with the first phase, and the second phase-switch set  54 B and the second stack-switch set  52 B are associated with the second phase. The first and second phase-controllers  59 A,  59 B and the stack controller  51  have been omitted to promote clarity. The switches are also shown schematically instead of as transistors. 
     The circuit shown in  FIG. 119  includes a voltage source  14  and a load  18 A. The voltage source  14  provides the first voltage V 1  in  FIG. 118 . The load  18 A connects to the second voltage V 2  in  FIG. 118 . 
     The first phase-switch set  53 A in  FIG. 118  corresponds to first, second, third, and fourth phase switches S P1 , S P2 , S P3 , S P4  in  FIG. 119 . The second phase-switch set  53 B correspond to fifth, sixth, seventh, and eighth switches S P5 , S P5 , S P7 , S P8  in  FIG. 119 . These are placed on first and second phase-dies  58 A,  58 B in  FIG. 118 . 
     The first stack-switch  52 A in  FIG. 118  corresponds to the first, second, third, fourth, and fifth switches S 1A , S 2A , S 3A , S 4A , S 5A  in  FIG. 119 . The second stack switches  52 B in  FIG. 118  correspond to the sixth, seventh, eighth, ninth, and tenth switches S 1B , S 2B , S 3B , S 4B , S 5B  in  FIG. 119 . These are all placed together on the same stack-die  56  in  FIG. 118 . 
       FIG. 120  shows a particular implementation of terminals on the stack-die  56 , terminals on the second phase-die  58 B, and the charge-transfer capacitors C 1B , C 2B , C 3B , C 4B  for the switching network  12 A shown in  FIG. 118 . The locations at which the phase switches S P5 , S P6 , S P7 , S P8  from the second phase-switch set  53 B connect to the terminals of the second phase-die  58 B can be seen in  FIG. 121 . 
     The terminals on the second phase-die  58 B are laid out in a manner similar to that shown for the first phase-die  58 A and have thus been omitted for clarity. Similarly, the interconnections between the charge-transfer capacitors C 1A , C 2A , C 3A , C 4A  and both the stack-die  56  and the first phase-die  58 A are similar to those shown in  FIG. 120  and are omitted for clarity. 
     Referring back to  FIG. 120 , an interdie commissure  63  again connects the second phase-switch die  58 B to the stack-die  56 . The interdie commissure  63  has a bridge section having a length Y 2  that depends on the physical size of the charge-transfer capacitors C 1B , C 2B , C 3B , C 4B  from the second charge-transfer capacitor set  50 B. The dimensions of the interdie commissure  63  are enlarged at selected locations to avoid excessive build-up of current density. As a result, the interdie commissure  63  is wider at locations where considerable current is expected to flow, but narrower at locations where smaller currents are expected to flow. This avoids having an excessively large footprint while also avoiding resistive losses. 
     In many cases, the switching network  12 A is to be connected to a regulator (also known as regulating circuit). Under these circumstances, it is useful to include a regulator-switch set  65  within the phase-die  58 C as shown in  FIG. 122 . It is expedient to integrate the first and second phase-switch sets  54 A,  54 B and the regulator-switch set  65  in the phase-die  58 C since the regulator switches and the phase switches have similar performance requirements. Both the phase switches and the regulator switches are intended to sustain essentially the same voltage. As such, the same manufacturing process can be used for both kinds of switch. 
     The regulator that is to be coupled to the regulator-switch set  65  introduces an inductive load, which in turn introduces considerable noise in the substrate of any die that contains the regulator-switch set  65 . Since, during operation, the substrate of the phase-die  58 C is inherently noisier than the substrate of the stack-die  56 , it is advantageous to include the regulator-switch set  65  in the phase-die  58 C so that operation of the stack-die  56  can proceed with minimal disturbance due to electrical noise. 
     In the embodiment shown in  FIG. 122 , the phase controller is replaced by a hybrid controller  59 C configured to control both the regulator-switch set  65  and the phase-switch set  54 A,  54 B via a phase control path  55 B, which extends from the hybrid controller  59 C to the phase-switch set  54 A,  54 B, and a regulator control path  55 D, which extends from the hybrid controller  59 C to the regulator-switch set  65 . 
     An advantage of placing the phase switches and stack switches on separate dies instead of integrating them into the same die is that doing so reduces the area of the die that holds the stack switches. Since this die must undergo a more expensive manufacturing process, and since the manufacturing cost is a function of die area, it is advantageous to reduce the die area. Since only the stack switches actually require the more expensive manufacturing process, it is advantageous to omit the phase switches and to place them on a separate die, which can then be manufactured more inexpensively. 
     Another advantage that arises is that having stack switches and phase switches on separate dies provides more flexibility in routing between components. This is because when all the components are on the same die, the components and the interconnections are confined to a two-dimensional space. In contrast, when a third dimension becomes available, there is an extra degree of freedom that can be used to optimize placement of the dies relative to each other to minimize path lengths. 
       FIGS. 123-128  collectively illustrate the flexibility associated with having a separate phase-die  58  and stack-die  56 . 
       FIG. 123  shows a substrate  28  supporting charge-transfer capacitors C 1A , C 2A , a first die U 1  and a second die U 2 . In the embodiment shown, the first die U 1  corresponds to the stack-die  56  and the second die U 2  corresponds to the phase-die  58 . The first and second dies U 1 , U 2  are side-by-side with their respective device faces both facing the substrate  28 . Electrically-conductive bumps  45  provide electrical communication between the first and second dies U 1 , U 2  and the charge-transfer capacitors C 1A , C 2A . 
       FIG. 124  shows a substrate  28  supporting charge-transfer capacitors C 1A , C 2A , a first die U 1 , and a second die U 2 . The first and second dies U 1 , U 2  are side-by-side inside a package  82  with their respective device faces both facing the substrate  28 . Within the package  82 , a first electrical interconnect layer  43 A provides interconnection between the first and second dies U 1 , U 2 . Electrically-conductive bumps  45  provide electrical communication between the package  82  and the charge-transfer capacitors C 1A , C 2A . 
       FIG. 125  shows the substrate  28  supporting a package  82  in which the second die U 2  is stacked on top of the first die U 1 . A first interconnect layer  43 A connects the first die U 1  with the rest of the switching network  12 A and a second interconnect layer  43 B connects the second die U 2  with the rest of the switching network  12 A. Electrically-conductive bumps  45  provide electrical communication between the package  82  and the charge-transfer capacitors C 1A , C 2A . 
       FIG. 126  shows the substrate  28  supporting a package  82  having a passive device layer  41 A and an active device layer  42 A. The charge-transfer capacitors C 1A -C 4B  are integrated into their own capacitor die  81 , which is in the passive device layer  41 A. The first and second dies U 1 , U 2  are in the active device layer  42 A. In this embodiment, the passive device layer  41 A can be viewed as a charge-transfer layer and the active device layer  42 A can be viewed as a switching layer. Electrically-conductive bumps  45  provide electrical communication between the package  82  and any external components. 
       FIG. 127  shows the substrate  28  supporting a package  82  having a mixed device layer  40 A, which is a hybrid layer that serves as both a switching layer and a charge-transfer layer, and an active device layer  42 A, which is only a switching layer. The charge-transfer capacitors C 1A -C 4B  are integrated into their own capacitor die  81 , which is in the mixed device layer  40 A, along with the second die U 2 . The first die U 1  is in the active device layer  42 A, but laterally offset from the second die U 2 . This provides a shorter path length for connections between the first and second dies U 1 , U 2 . Electrically-conductive bumps  45  provide electrical communication between the package  82  and any external components. 
     Yet another advantage of having the various components of a switched-capacitor circuit be on separate dies is that doing so can promote heat dissipation. This is because there will be more surface area available to radiate heat. The ability to efficiently dissipate heat is particularly important for a power converter, since a power converter has a tendency to run hot. An example of how to arrange dies to promote cooling is shown in  FIG. 128 . 
       FIG. 128  shows the substrate  28  supporting a package  82  having a first active device layer  42 A, a second active device layer  42 B, and a passive device layer  41 A between the first active device layer  42 A and the second active device layer  42 B. The charge-transfer capacitors C 1A -C 4B  are integrated into their own capacitor die  81 , which is in the passive device layer  41 A. The second die U 2  is in the second active device layer  42 B and the first die U 1  is in the first active device layer  42 A. In this embodiment, the passive device layer  41 A is the charge-transfer layer and the first and second active device layers  42 A,  42 B are both switching layers. Electrically-conductive bumps  45  provide electrical communication between the package  82  and any external components. 
     An advantage of the embodiment shown in  FIG. 128  is that the hottest components of the circuit, namely the active device layers  42 A,  42 B, are outside, whereas the passive device layer  41 A, which stays cooler, is in the inside. This configuration thus promotes cooling. 
       FIG. 129  shows the substrate  28  supporting an inductor L 1  and a package  82  having a passive device layer  41 A and an active device layer  42 A. Charge-transfer capacitors C 1A , C 2A  are disposed in the passive device layer  41 A. The charge-transfer capacitors C 1A , C 2A  are discrete elements that, in some embodiments, are surrounded by a matrix  74  to mechanically support them. The first die U 1  is in the active device layer  42 A with its device face facing electrically conductive bumps  45  that provide electrical communication between the package  82  and external components, including the inductor L 1 . In this embodiment, the passive device layer  41 A is the charge-transfer layer and the active device layer  42 A is the switching layer. First and second interconnect layers  43 A,  43 B provide electrical communication between the charge-transfer capacitors C 1A , C 2A  and the first die U 1 . 
       FIG. 130  shows the substrate  28  supporting an inductor L 1  and a package  82 . The package  82  has a passive device layer  41 A and an active device layer  42 A. A first interconnect layer  43 A resting on electrically-conductive bumps  45  provides electrical communication between the package  82  and external components, including the inductor L 1 . Charge-transfer capacitors C 1A , C 2A  are disposed in the passive device layer  41 A. These charge-transfer capacitors C 1A , C 2A  are discrete elements that, in some embodiments, are surrounded by a matrix  74  to mechanically support them. The first die U 1  is in the active device layer  42 A with its device face facing a second interconnect layer  43 B at the passive device layer  41 A. The switching layer thus corresponds to the active device layer  42 A and the charge-transfer layer is the passive device layer  41 A. The second interconnect layer  43 B provides electrical communication between the first die U 1  and the charge-transfer capacitors C 1A , C 2A . A heatsink  76  opposite the device face contacts thermally-conductive bumps  46 . Unlike the electrically-conductive bumps  45 , which conduct both heat and electricity, the thermally-conductive bumps  46  are dedicated to heat transfer only. 
       FIG. 131  shows the substrate  28  supporting an inductor L 1  and a package  82 . The package  82  has a passive device layer  41 A, which serves as the charge-transfer layer, and an active device layer  42 A, which serves as a switching layer. A first interconnect layer  43 A rests on an electrically-conductive pad  45 B. This first interconnect layer  43 A provides electrical communication between the package  82  and external components, including the inductor L 1 . Charge-transfer capacitors C 1A , C 2A  are disposed in the passive device layer  41 A. These charge-transfer capacitors C 1A , C 2A  are discrete elements that, in some embodiments, are surrounded by a matrix  74  to mechanically support them. The first die U 1  is in the active device layer  42 A with its device face facing a second interconnect layer  43 B at the passive device layer  41 A. This second interconnect layer  43 B provides electrical communication between the first die U 1  and the charge-transfer capacitors C 1A , C 2A . A heatsink  76  opposite the device face contacts a thermally-conductive pad  46 B. Unlike the electrically-conductive pad  45 B, which conducts both heat and electricity, the thermally-conductive pad  46 B is dedicated to heat transfer only. 
       FIG. 132  shows the substrate  28  supporting a package  82  having a passive device layer  41 A and an active device layer  42 A. The pass device layer  41 A serves as the charge-transfer layer, and the active device layer  42 A serves as a switching layer. A first interconnect layer  43 A resting on electrically-conductive bumps  45  provides electrical communication between the package  82  and external components. An inductor L 1  and charge-transfer capacitors C 1A , C 2A  are disposed in the passive device layer  41 A. These are discrete elements that, in some embodiments, are surrounded by a matrix  74  to mechanically support them. The first die U 1  is in the active device layer  42 A with its device face facing a second interconnect layer  43 B at the passive device layer  41 A. This second interconnect layer  43 B provides electrical communication between the first die U 1 , the charge-transfer capacitors C 1A , C 2A , and the inductor L 1 . A heatsink  76  opposite the device face contacts thermally-conductive bumps  46 . Unlike the electrically-conductive bumps  45 , which conduct both heat and electricity, the thermally-conductive bumps  46  are dedicated to heat transfer only. 
       FIG. 133  shows the substrate  28  supporting a package  82  having a passive device layer  41 A and a mixed device layer  40 A. The passive device layer  41 A serves as the charge-transfer layer, and the mixed device layer  40 A serves as a switching layer. A first interconnect layer  43 A resting on electrically-conductive bumps  45  provides electrical communication between the package  82  and external components. Charge-transfer capacitors C 1A , C 2A  are disposed in the passive device layer  41 A. These are discrete elements that, in some embodiments, are surrounded by a matrix  74  to mechanically support them. An inductor L 1  and the first die U 1  are side-by-side in the mixed device layer  40 A. The inductor L 1  is formed by metallic traces wound around a core in the mixed device layer  40 A. The first die U 1  has its device face facing a second interconnect layer  43 B at the passive device layer  41 A. This second interconnect layer  43 B provides electrical communication between the first die U 1 , the charge-transfer capacitors C 1A , C 2A , and the inductor L 1 . A heatsink  76  opposite the device face contacts thermally-conductive bumps  46 . Unlike the electrically-conductive bumps  45 , which conduct both heat and electricity, the thermally-conductive bumps  46  are dedicated to heat transfer only. 
     Another advantage of using different dies to build a switching network  12 A is that come components are not good neighbors on the same die. 
     Since all components on a die share a common substrate, all components are inherently coupled. This means that activity at one end of the die may significantly affect activity at the other end of the die. 
     The stack switches handle considerable amounts of power. As a result, the stack switches do not always make good neighbors on the same die. In particular, when the stack switches and phase switches are on the same die, the phase switch operation can be adversely affected by stack switch operation. 
     In some embodiments, the stack controller  51  is integrated into the stack-die. This reduces overall pin count and also avoids the need to fabricate a separate die. However, the very high currents associated with the operation of the stack switches may interfere with operation of the stack controller  51 , both because of EMI and because of electrical coupling. Thus, in some embodiments, the stack controller  51  is on a separate die. 
     Among other advantages, the arrangements described above avoid the component and pin count penalty, reduce the energy loss in the parasitic interconnect structures, and reduces the total footprint of power converters that use capacitors to transfer energy. 
     In some implementations, a computer accessible storage medium includes a database representative of one or more components of the converter. For example, the database may include data representative of a switching network that has been optimized to promote low-loss operation of a charge pump. 
     Generally speaking, a computer accessible storage medium may include any non-transitory storage media accessible by a computer during use to provide instructions and/or data to the computer. For example, a computer accessible storage medium may include storage media such as magnetic or optical disks and semiconductor memories. 
     Generally, a database representative of the system may be a database or other data structure that can be read by a program and used, directly or indirectly, to fabricate the hardware comprising the system. For example, the database may be a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high level design language (HDL) such as Verilog or VHDL. The description may be read by a synthesis tool that may synthesize the description to produce a netlist comprising a list of gates from a synthesis library. The netlist comprises a set of gates that also represent the functionality of the hardware comprising the system. The netlist may then be placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks may then be used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits corresponding to the system. In other examples, Alternatively, the database may itself be the netlist (with or without the synthesis library) or the data set. 
     Having described one or more preferred embodiments, it will be apparent to those of ordinary skill in the art that other embodiments incorporating these circuits, techniques and concepts may be used. Accordingly, it is submitted that the scope of the patent should not be limited to the described embodiments, but rather, should be limited only by the spirit and scope of the appended claims.