Patent Publication Number: US-9425058-B2

Title: Simplified litho-etch-litho-etch process

Description:
FIELD 
     Embodiments of the invention relate to efficient multi-patterning. 
     BACKGROUND 
     Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate is enabled by controlled methods for removal of exposed material. Chemical etching is used for a variety of purposes including transferring a pattern in photoresist into underlying layers, thinning layers or thinning lateral dimensions of features already present on the surface. Pattern transfers require etch process which removes one material faster than another. Such an etch process is said to be selective of the first material relative to the second material. As a result of the diversity of materials, circuits and processes, etch processes have been developed with a selectivity towards a variety of materials. 
     Dry etch processes are desirable for selectively removing material from semiconductor substrates. The desirability stems from the ability to gently remove material from miniature structures with minimal physical disturbance. Dry etch processes also allow the etch rate to be abruptly stopped by removing the gas phase reagents. Some dry-etch processes involve the exposure of a substrate to remote plasma by-products formed from one or more precursors. The remote plasma by-products may be ionically filtered to increase selectivity or may be further excited in a local plasma to enhance etch rate or directionality. These selective gas-phase etch processes can enable new patterning process flows. New process flows are needed to take advantage of these selective gas-phase etch processes. 
     SUMMARY 
     Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several layers above the target etch layer. The compound pattern, made from multiple patterning steps, is later transferred in one set of operations through the stack to save process steps. 
     Embodiments of the invention include methods of patterning a substrate. The methods includes forming a first layer of photoresist on a stack of materials on the substrate. The stack of materials includes a blanket top mask layer over a blanket etch stop layer over an anti-reflective coating over a target etch layer. The methods further include patterning the first layer of photoresist to form a first pattern. The methods further include etching the first pattern into the blanket top mask layer to form a first patterned top mask layer. The methods further include removing any remaining material from the first layer of photoresist. The methods further include forming a second layer of photoresist on the first patterned top mask layer. The methods further include patterning the second layer of photoresist to form a second pattern. The methods further include etching the second pattern into the first patterned top mask layer to form a second patterned top mask layer. The methods further include etching the first pattern and the second pattern into the stack of materials. The first pattern and the second pattern are formed in the stack of materials during the same etching operations. 
     Embodiments of the invention include methods of patterning a substrate. The methods include forming a first layer of photoresist on a stack of materials on the substrate. The stack of materials includes a blanket top mask layer over a blanket etch stop layer over an anti-reflective coating over a target etch layer. The methods further include patterning the first layer of photoresist to form a first pattern. The methods further include etching the first pattern into the blanket top mask layer to form a first patterned top mask layer. The methods further include forming a second layer of photoresist on the first patterned top mask layer. The methods further include patterning the second layer of photoresist to form a second pattern. The methods further include etching the second pattern into the first patterned top mask layer to form a second patterned top mask layer. The methods further include forming a third layer of photoresist on the second patterned top mask layer. The methods further include patterning the third layer of photoresist to form a third pattern. The methods further include etching the third pattern into the second patterned top mask layer to form a third patterned top mask layer. The methods further include etching the first pattern, the second pattern and the third pattern into the stack of materials. The first pattern, the second pattern and the third pattern are formed in the stack of materials during the same etching operations. 
     Additional embodiments and features are set forth in part in the description that follows, and in part will become apparent to those skilled in the art upon examination of the specification or may be learned by the practice of the embodiments. The features and advantages of the embodiments may be realized and attained by means of the instrumentalities, combinations, and methods described in the specification. 
    
    
     
       DESCRIPTION OF THE DRAWINGS 
       A further understanding of the nature and advantages of the embodiments may be realized by reference to the remaining portions of the specification and the drawings. 
         FIGS. 1A, 1B, 1C, 1D, 1E, 1F and 1G  show cross-sectional views of a substrate at various stages during multi-patterning. 
         FIG. 2  is a flow chart of a multi-patterning process according to embodiments. 
         FIGS. 3A, 3B, 3C, 3D, 3E, 3F, 3G and 3H  show cross-sectional views of a substrate at various stages during multi-patterning according to embodiments. 
     
    
    
     In the appended figures, similar components and/or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a dash and a second label that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the second reference label. 
     DETAILED DESCRIPTION 
     Methods of patterning a blanket layer (a target etch layer) on a substrate are described. The methods involve multiple patterning steps of a mask layer several layers above the target etch layer. The compound pattern, made from multiple patterning steps, is later transferred in one set of operations through the stack to save process steps. 
     Embodiments of the present invention pertain to a method of multi-patterning a stack of layers while reducing the cost associated with the production sequence. In order to provide contrast, reference is now made to  FIGS. 1A, 1B, 1C, 1D, 1E, 1F and 1G , which are cross-sectional views of a substrate at various stages during multi-patterning according to a prior art process. A substrate  101  has a silicon oxide layer  105  deposited on substrate  101  and a titanium nitride layer  110  is deposited on silicon oxide layer  105 . Another silicon oxide layer  115 - 1  is deposited on the titanium nitride layer  110  as shown in  FIG. 1A . Patterning titanium nitride layer multiple times has been accomplished in the past by multiply-patterning silicon oxide layer  115 - 1  and later transferring the multiple-pattern into an underlying layer, e.g. titanium nitride layer  110 , at the same time. The first of the multiple patterns involved depositing silicon anti-reflective coating  120 - 1  on silicon oxide layer  115 - 1  and carbon anti-reflective coating  125 - 1  on silicon anti-reflective coating  120 - 1 . Photoresist  130 - 1  is deposited on carbon anti-reflective coating  125 - 1  and patterned. The pattern of photoresist  130 - 1  is transferred down into the carbon anti-reflective coating  125 - 1 , then into the silicon anti-reflective coating  120 - 1  and then again into silicon oxide layer  115 - 1  to form silicon oxide layer  115 - 2 . After patterning and removal of all the patterned layers above silicon oxide layer  115 - 2 , a schematic side view is shown in  FIG. 1C . 
     The process is repeated with another pattern using photoresist  130 - 2 , carbon anti-reflective coating  125 - 2 , silicon anti-reflective coating  120 - 2 . The second pattern is depicted in  FIG. 1D  in the photoresist  130 - 2  right before the pattern is transferred into the stack.  FIG. 1E  shows a side view of silicon oxide  115 - 3  after the second pattern is transferred into silicon oxide  115 - 2 . The second pattern creates holes in different locations or sizes across the substrate surface. The pattern of silicon oxide  115 - 3  shows that the second pattern is shifted one third of a pitch relative to the first pattern depicted in  FIGS. 1B and 1C . A third pattern, depicted in  FIGS. 1F and 1G , uses photoresist  130 - 3  to ultimately pattern silicon oxide  115 - 4 . The third pattern completes the process of reducing the pitch by a factor of three relative to the initial pitch shown in  FIG. 1C . The process shown represents an example of a prior art litho-etch-litho-etch (LELE) process. 
     Each pattern described in the example of  FIGS. 1A-1G  involves etching through a thick stack of material to get to (and pattern) the target etch layer  110 . The present invention reduces the number of times a multi-layer stack needs to be etched through and therefore reduces cost and processing complexity. The process sequence is enabled by recently developed remote plasma etch processes which offer the necessary etch selectivities. 
     In order to better understand and appreciate the invention, reference is now made to  FIG. 2  which is a flow chart of a multi-patterning process  201  according to embodiments. Reference will concurrently be made to  FIGS. 3A-3H  which are cross-sectional views of a substrate at stages during multi-patterning during a multi-patterning process according to embodiments. A substrate is provided in operation  210 . The substrate initially has a blanket top mask layer  355 - 1  over a blanket etch stop layer  350  over a silicon anti-reflective coating  320  over a target etch layer  310 . Blanket top mask layer  355 - 1  may contact blanket etch stop layer  350  in embodiments. Blanket etch stop layer  350  may contact silicon anti-reflective coating  320  according to embodiments. Finally, silicon anti-reflective coating  320  may contact target etch layer  310  in embodiments. 
     Photoresist  360 - 1  is deposited and patterned in operation  220  to achieve the cross-sectional view of  FIG. 3B . Patterning photoresist  360 - 1  may involve exposing photoresist  360 - 1  to light of a well-defined wavelength in the form of an image focused at the plane of photoresist  360 - 1  in embodiments. Patterning photoresist  360 - 1  may further involve developing the latent image using a chemical which preferentially removes either the exposed regions or the unexposed regions in embodiments. Blanket top mask layer  355 - 1  is then patterned in operation  230  using patterned photoresist  360 - 1  as a mask template and the patterned photoresist may then be removed to achieve the cross-sectional view of  FIG. 3C . After patterning, the layer will be referred to as first patterned top mask layer  355 - 2 . 
     Another layer of photoresist  360 - 2  is formed on first patterned top mask layer  355 - 2  and patterned (with a different image from photoresist  360 - 1 ) in operation  240 . First patterned top mask layer  355 - 2  is then patterned in operation  250  to form second patterned top mask layer  355 - 3 . Patterned photoresist  360 - 2  is used as a mask template to achieve the cross-sectional view of  FIG. 3E  following optional removal of patterned photoresist  360 - 2 . In this example, a third layer of photoresist  360 - 3  is also formed on second patterned top mask layer  355 - 3  and patterned in operation  260 . The pattern of third layer of photoresist  360 - 3  is transferred into second patterned top mask layer  355 - 3  to form third patterned top mask layer  355 - 4  in operation  270 . Third patterned top mask layer  355 - 4  is shown in  FIG. 3G  following removal of third layer of photoresist  360 - 3 . 
     Third patterned top mask layer  355 - 4  embodies three independent patterns from each of patterned photoresist  360 - 1 ,  360 - 2  and  360 - 3 . A combination of patterns in the manner may be referred to herein as a compound pattern. Generally speaking, a compound pattern may include a combination of two, three, four, five or any integer other than one according to embodiments. In the example, the compound pattern has a higher density of features in a dimension of the pattern compared to the corresponding density with any single photoresist pattern. In other words, the pitch of the compound pattern is decreased compared to any single photoresist pattern. In embodiments, the compound pattern may have half the pitch/twice the density, one third the pitch/thrice the density, one fourth the pitch/four times the density or one fifth the pitch/five times the density. The linear density of features along a direction of the second or third patterned top mask layers may be an integer greater than one (e.g. two or three) times a linear density of features along the direction of the first patterned top mask layer in embodiments. 
     The compound pattern of the top mask layer (e.g. third patterned top mask layer  355 - 4 ) may then be used to pattern (operation  280 ) the underlying film stack including etch stop  350 , silicon anti-reflective coating  320 , target etch layer  310  and/or silicon oxide  305  according to embodiments. The dotted lines of  FIG. 3H  show vertical demarcation which may be used to perform a directional etch into the film stack. Only one instance of etching into the completed stack is necessary when using the process sequences outlined herein and the resulting process flow has fewer steps as a consequence. Etching through the stack in operation  280  may include etching through target etch layer  310  or through silicon oxide  305  or even into substrate  301  according to embodiments. 
     Target etch layer  310  may be titanium nitride in embodiments. The anti-reflective coating  320  may comprise silicon oxynitride according to embodiments. Anti-reflective coating  320  may comprise or consist of silicon, oxygen and nitrogen in embodiments. Target etch layer  310  may be a conductor or may be dielectric in embodiments. Target etch layer  310  may comprise a metallic element, in other words an element which would form a conductor in a material consisting predominantly or only of the metallic element. 
     In embodiments, top mask layer  355  (including blanket top mask layer, first patterned top mask layer, second patterned top mask layer and/or third patterned top mask layer) are transparent for optical radiation from 20 nm to 700 nm to facilitate the measurement of overlay registration. Top mask layer  355  may have a relatively high extinction coefficient (the imaginary part of the index of refraction) at the photolithography wavelength(s) in order to avoid back-reflections. The extinction coefficient of the top mask layer may be greater than 0.05, greater than 0.1 or greater than 0.15 according to embodiments. 
     Remote plasma excitation is used to create the diverse set of selectivities needed to enable the new process sequences described herein. A local plasma in the substrate processing region is used in tandem with the remote plasma in embodiments. In other embodiments, a local plasma is not used and the ions excited in the remote plasma are filtered out from the plasma effluents entering the substrate processing region. Ion suppression techniques will be described first, followed by the local plasma and exemplary hardware which may be used for all etch processes described herein. 
     An ion suppression element may be included in the remote etch processes described herein. When included, the ion suppression element functions to reduce or eliminate ionic/charged species traveling from the plasma generation region to the substrate. Uncharged neutral and radical species may pass through the openings in the ion suppressor to react at the substrate. The ion suppressor helps control the concentration of ionic species in the reaction region at a level that increases selectivity. 
     In accordance with some embodiments of the invention, an ion suppressor described further in the exemplary equipment section may be used to provide radical and/or neutral species for selectively etching substrates. In one embodiment, for example, an ion suppressor is used to provide fluorine-containing plasma effluents to selectively etch the target etch layer. The ion suppressor may be used to provide a reactive gas having a higher concentration of radicals than ions. Because most (or essentially all in embodiments) of the charged particles of a plasma are filtered or removed by the ion suppressor, the substrate is not necessarily biased during the etch process. By filtering ions from the plasma effluents before they reach the substrate processing region, a high etch rate selectivity may be achieved. Embodiments of the present invention are also advantageous over conventional wet etch processes where surface tension of liquids can cause bending and peeling of small features. 
     When a local plasma is used, multi-patterning process  201  includes applying energy to plasma-effluents (including radical-fluorine or radical-chlorine) while in the substrate processing region to selectively etch layers in a directional manner. The plasma may be generated using known techniques (e.g., radio frequency excitations, capacitively-coupled power or inductively coupled power). In an embodiment, the energy is applied using a capacitively-coupled plasma unit. The local plasma power may be between about 10 watts and about 500 watts, between about 20 watts and about 400 watts, between about 30 watts and about 300 watts, or between about 50 watts and about 200 watts in embodiments of the invention. Higher powers in combination with higher operating pressures enable a reduction in force of impact of accelerated ions and preserve the integrity of patterned features other than material to-be-removed on the exposed silicon on the patterned substrate surface. 
     A DC accelerating voltage may be applied such that positive ions formed in the local plasma are accelerated in the direction of the patterned substrate. In other words, the local plasma may be formed by applying a DC bias power such that the local plasma power comprises both an AC portion and a DC portion. The DC bias power supplies a DC accelerating voltage which may be greater than 400 volts, greater than 500 volts, greater than 600 volts, or greater than 700 volts in embodiments of the invention. The DC voltage may be less than 2000 volts, less than 1500 volts, less than 1300 volts or less than 1100 volts to preserve the integrity of non-silicon components. The pressure in the substrate processing region may be between about 0.5 mTorr and about 500 mTorr, between about 2 mTorr and about 200 mTorr or between about 5 mTorr and about 100 mTorr in embodiments. 
     The multi-patterning process  201  includes applying energy to the fluorine-containing precursor while in the remote plasma region to generate the plasma effluents regardless of whether a local plasma is excited. As would be appreciated by one of ordinary skill in the art, the plasma may include a number of charged and neutral species including radicals and ions. The plasma may be generated using known techniques (e.g., radio frequency excitations, capacitively-coupled power, inductively coupled power, and the like). In an embodiment, the energy is applied using a capacitively-coupled plasma unit. The remote plasma source power may be between about 300 watts and about 5000 watts, between about 500 watts and about 3000 watts, between about 750 watts and about 2000 watts, or between about 900 watts and about 1500 watts in embodiments of the invention. As with all complementary ranges provided herein, upper limits may be combined with any suitable lower limits to obtain additional embodiments. The pressure in the remote plasma region may be such that the pressure in the substrate processing region ends up between about 0.01 Torr and about 50 Torr or between about 0.1 Torr and about 5 Torr in embodiments. The pressure in the remote plasma region and the substrate processing region may be roughly the same according to embodiments. The capacitively-coupled plasma unit may be disposed remote from a substrate processing region of the processing chamber. For example, the capacitively-coupled plasma unit and the plasma generation region may be separated from the gas reaction region by a showerhead. 
     The RF frequency applied for either the local or remote plasmas described herein may be low RF frequencies less than about 200 kHz, high RF frequencies between about 10 MHz and about 15 MHz, or microwave frequencies greater than or about 1 GHz in embodiments. 
     A halogen-containing precursor (e.g. a fluorine-containing precursor or a chlorine-containing precursor) is flowed into the remote plasma region during all etch processes described herein. The flow of the halogen-containing precursor may further include one or more relatively inert gases such as He, N 2 , Ar. The inert gas can be used to improve plasma stability, process uniformity and the like. Argon is helpful, as an additive, to promote the formation of a stable plasma, however, current experimentation has established that inclusion of argon results in a nonuniform (bumpy) post etch surface. Process uniformity is generally increased when helium is included. In one embodiment, helium does not cause the bumpiness associated with argon. These additives are present in embodiments throughout this specification. Flow rates and ratios of the different gases may be used to control etch rates and etch selectivity. 
     In embodiments, the halogen-containing precursor (chlorine-containing precursor, fluorine-containing precursor e.g. NF 3 ) is supplied at a flow rate of between about 5 sccm (standard cubic centimeters per minute) and 400 sccm, He at a flow rate of between about 0 slm (standard liters per minute) and 3 slm, and N 2  at a flow rate of between about 0 slm and 3 slm. The chlorine-containing precursor or fluorine-containing precursor may be flowed into chamber plasma region  1015  at rates between about 5 sccm and about 500 sccm, between about 10 sccm and about 150 sccm, or between about 25 sccm and about 125 sccm in embodiments. One of ordinary skill in the art would recognize that other gases and/or flows may be used depending on a number of factors including processing chamber configuration, substrate size, geometry and layout of features being etched, and the like. The temperature of the substrate may be between about −20° C. and about 200° C. during both the any of the etch processes described herein. 
     In embodiments, an ion suppressor (which may be the showerhead) may be used to provide radical and/or neutral species for gas-phase etching. The ion suppressor may also be referred to as an ion suppression element. In embodiments, for example, the ion suppressor is used to filter etching plasma effluents (including radical-fluorine) en route from the remote plasma region to the substrate processing region. The ion suppressor may be used to provide a reactive gas having a higher concentration of radicals than ions. Plasma effluents pass through the ion suppressor disposed between the remote plasma region and the substrate processing region. The ion suppressor functions to dramatically reduce or substantially eliminate ionic species traveling from the plasma generation region to the substrate. The ion suppressors described herein are simply one way to achieve a low electron temperature in the substrate processing region during the silicon nitride etch and/or the silicon oxide etch described above. 
     In embodiments, an electron beam is passed through the substrate processing region in a plane parallel to the substrate to reduce the electron temperature of the plasma effluents. A simpler showerhead may be used if an electron beam is applied in this manner. The electron beam may be passed as a laminar sheet disposed above the substrate in embodiments. The electron beam provides a source of neutralizing negative charge and provides a more active means for reducing the flow of positively charged ions towards the substrate and increasing the selectivity of silicon nitride in embodiments. The flow of plasma effluents and various parameters governing the operation of the electron beam may be adjusted to lower the electron temperature measured in the substrate processing region. 
     The electron temperature may be measured using a Langmuir probe in the substrate processing region during excitation of a plasma in the remote plasma. In embodiments, the electron temperature may be less than 0.5 eV, less than 0.45 eV, less than 0.4 eV, or less than 0.35 eV. These extremely low values for the electron temperature are enabled by the presence of the electron beam, showerhead and/or the ion suppressor. Uncharged neutral and radical species may pass through the electron beam and/or the openings in the ion suppressor to react at the substrate. Such a process using radicals and other neutral species can reduce plasma damage compared to conventional plasma etch processes that include sputtering and bombardment. Embodiments of the present invention are also advantageous over conventional wet etch processes where surface tension of liquids can cause bending and peeling of small features. 
     The substrate processing region may be described herein as “plasma-free” during the etch processes described herein. “Plasma-free” does not necessarily mean the region is devoid of plasma. Ionized species and free electrons created within the plasma region may travel through pores (apertures) in the partition (showerhead) at exceedingly small concentrations. The borders of the plasma in the chamber plasma region are hard to define and may encroach upon the substrate processing region through the apertures in the showerhead. Furthermore, a low intensity plasma may be created in the substrate processing region without eliminating desirable features of the etch processes described herein. All causes for a plasma having much lower intensity ion density than the chamber plasma region during the creation of the excited plasma effluents do not deviate from the scope of “plasma-free” as used herein. 
     During film etching, e.g., titanium nitride, tantalum nitride, tungsten, silicon, polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc., a halogen-containing precursor may be flowed into a remote plasma region through a gas inlet assembly. A remote plasma system (RPS) may optionally be included in the system, and may process the halogen-containing precursor which then travels through the gas inlet assembly into the remote plasma region. The halogen-containing precursor may be delivered to the processing chamber in an unexcited state. The halogen-containing precursor may be excited within the RPS prior to entering the remote plasma region located inside the substrate processing chamber. The halogen-containing precursor may pass through RPS or bypass the RPS unit in embodiments. 
     A cooling plate, faceplate, ion suppressor, showerhead, and a substrate support (also known as a pedestal), having a substrate disposed thereon, are shown and may each be included according to embodiments. The pedestal may have a heat exchange channel through which a heat exchange fluid flows to control the temperature of the substrate. This configuration may allow the substrate temperature to be cooled or heated to maintain relatively low temperatures, such as between about −20° C. to about 200° C., or there between. The wafer support platter of the pedestal  1065 , which may comprise aluminum, ceramic, or a combination thereof, may also be resistively heated to relatively high temperatures, such as from up to or about 100° C. to above or about 1100° C., using an embedded resistive heater element. 
     The ion suppressor may comprise a plate or other geometry that defines a plurality of apertures throughout the structure that are configured to suppress the migration of ionically-charged species out of chamber plasma region while allowing uncharged neutral or radical species to pass through the ion suppressor into an activated gas delivery region between the ion suppressor and the showerhead. In embodiments, the ion suppressor may comprise a perforated plate with a variety of aperture configurations. These uncharged species may include highly reactive species that are transported with less reactive carrier gas through the apertures. As noted above, the migration of ionic species through the holes may be significantly reduced as quantified earlier. Controlling the amount of ionic species passing through the ion suppressor may provide increased control over the gas mixture brought into contact with the underlying wafer substrate, which in turn may increase control of the etch characteristics of the gas mixture. For example, adjustments in the ion concentration of the gas mixture can significantly alter its etch selectivity. 
     The plurality of holes in the ion suppressor may be configured to control the passage of the activated gas, i.e., the ionic, radical, and/or neutral species, through the ion suppressor. For example, the aspect ratio of the holes, or the hole diameter to length, and/or the geometry of the holes may be controlled so that the flow of ionically-charged species in the activated gas passing through the ion suppressor is reduced. The holes in the ion suppressor may include a tapered portion that faces chamber plasma region, and a cylindrical portion that faces the showerhead. The cylindrical portion may be shaped and dimensioned to control the flow of ionic species passing to the showerhead. An adjustable electrical bias may also be applied to the ion suppressor as an additional means to control the flow of ionic species through the suppressor. 
     Showerhead in combination with ion suppressor may allow a plasma present in chamber plasma region to avoid directly exciting gases in substrate processing region, while still allowing excited species to travel from chamber plasma region into substrate processing region. In this way, the chamber may be configured to prevent the plasma from contacting a substrate being etched. This may advantageously protect a variety of intricate structures and films patterned on the substrate, which may be damaged, dislocated, or otherwise warped if directly contacted by a generated plasma. 
     The gas distribution assemblies (e.g. the showerhead) for use in the processing chamber section may be referred to as dual channel showerheads (DCSH). The dual channel showerhead may provide for etching processes that allow for separation of etchants outside of the processing region to provide limited interaction with chamber components and each other prior to being delivered into the processing region. The showerhead through-holes and closed-end holes. Through-holes transmit plasma effluents whereas the closed-end holes introduce separate precursors which have not flowed through any plasma prior to entering the substrate processing region. 
     The chamber plasma region upstream from the showerhead or a region in an RPS may be referred to as a remote plasma region. In embodiments, the radical precursor, e.g., a radical-fluorine precursor, is created in the remote plasma region and travels into the substrate processing region where it may or may not combine with additional precursors. In embodiments, the additional precursors are excited only by the radical-fluorine precursor. Plasma power may essentially be applied only to the remote plasma region in embodiments to ensure that the radical-fluorine precursor provides the dominant excitation. 
     As used herein “substrate” may be a support substrate with or without layers formed thereon. The patterned substrate may be an insulator or a semiconductor of a variety of doping concentrations and profiles and may, for example, be a semiconductor substrate of the type used in the manufacture of integrated circuits. Exposed “silicon” of the patterned substrate is predominantly Si but may include minority concentrations of other elemental constituents such as nitrogen, oxygen, hydrogen, carbon and the like. Exposed “silicon” may consist of or consist essentially of silicon. Exposed “silicon nitride” of the patterned substrate is predominantly Si 3 N 4  but may include minority concentrations of other elemental constituents such as oxygen, hydrogen, carbon and the like. “Exposed silicon nitride” may consist essentially of or consist of silicon and nitrogen. Exposed “silicon oxide” of the patterned substrate is predominantly SiO 2  but may include minority concentrations of other elemental constituents such as nitrogen, hydrogen, carbon and the like. In embodiments, silicon oxide films etched using the methods taught herein consist essentially of or consist of silicon and oxygen. 
     The term “precursor” is used to refer to any process gas which takes part in a reaction to either remove material from or deposit material onto a surface. “Plasma effluents” describe gas exiting from the chamber plasma region and entering the substrate processing region. Plasma effluents are in an “excited state” wherein at least some of the gas molecules are in vibrationally-excited, dissociated and/or ionized states. A “radical precursor” is used to describe plasma effluents (a gas in an excited state which is exiting a plasma) which participate in a reaction to either remove material from or deposit material on a surface. “Radical-fluorine” are radical precursors which contain fluorine but may contain other elemental constituents. The phrase “inert gas” refers to any gas which does not form chemical bonds when etching or being incorporated into a film. Exemplary inert gases include noble gases but may include other gases so long as no chemical bonds are formed when (typically) trace amounts are trapped in a film. 
     The terms “gap” and “trench” are used throughout with no implication that the etched geometry has a large horizontal aspect ratio. Viewed from above the surface, trenches may appear circular, oval, polygonal, rectangular, or a variety of other shapes. A trench may be in the shape of a moat around an island of material. The term “via” is used to refer to a low aspect ratio trench (as viewed from above) which may or may not be filled with metal to form a vertical electrical connection. As used herein, a conformal etch process refers to a generally uniform removal of material on a surface in the same shape as the surface, i.e., the surface of the etched layer and the pre-etch surface are generally parallel. A person having ordinary skill in the art will recognize that the etched interface likely cannot be 100% conformal and thus the term “generally” allows for acceptable tolerances. 
     In the preceding description, for the purposes of explanation, numerous details have been set forth to provide an understanding of various embodiments of the present invention. It will be apparent to one skilled in the art, however, that certain embodiments may be practiced without some of these details, or with additional details. 
     Having disclosed several embodiments, it will be recognized by those of skill in the art that various modifications, alternative constructions, and equivalents may be used without departing from the spirit of the embodiments. Additionally, a number of well-known processes and elements have not been described in order to avoid unnecessarily obscuring the present technology. Accordingly, the above description should not be taken as limiting the scope of the technology. 
     Where a range of values is provided, it is understood that each intervening value, to the smallest fraction of the unit of the lower limit, unless the context clearly dictates otherwise, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any stated values or unstated intervening values in a stated range and any other stated or intervening value in that stated range is encompassed. The upper and lower limits of those smaller ranges may independently be included or excluded in the range, and each range where either, neither, or both limits are included in the smaller ranges is also encompassed within the technology, subject to any specifically excluded limit in the stated range. Where the stated range includes one or both of the limits, ranges excluding either or both of those included limits are also included. 
     As used herein and in the appended claims, the singular forms “a”, “an”, and “the” include plural references unless the context clearly dictates otherwise. Thus, for example, reference to “a trench” includes a plurality of such trenches, and reference to “the layer” includes reference to one or more layers and equivalents thereof known to those skilled in the art, and so forth. 
     Also, the words “comprise(s)”, “comprising”, “contain(s)”, “containing”, “include(s)”, and “including”, when used in this specification and in the following claims, are intended to specify the presence of stated features, integers, components, or operations, but they do not preclude the presence or addition of one or more other features, integers, components, operations, acts, or groups.