Patent Publication Number: US-2006020768-A1

Title: Vector processing apparatus, Information processing apparatus, and vector processing method

Description:
BACKGROUND OF THE INVENTION  
      The present invention relates to a vector processing apparatus, information processing apparatus, and vector processing method and, more particularly, to a vector processing apparatus, information processing apparatus, and vector processing method which reduce noise caused by simultaneous operations.  
      The number of logic circuits integrated into an LSI is increasing. If, however, the integrated logic circuits are simultaneously driven in synchronism with a single clock, noise is generated at the timing synchronized with the clock. This causes logic circuits to malfunction.  
      For example, Japanese Patent Laid-Open No. 58-149555 (reference 1) discloses a technique of improving performance by causing computing devices to sequentially execute computations as soon as element data is loaded from a main memory regardless of whether all data are loaded.  
      According to this technique, when load instructions from the main memory or store instructions to the main memory are to be executed, the respective computing devices execute computations at different timings. This produces a certain effect in reducing the occurrence of malfunction due to noise.  
      This technique, however, produces no effect in reducing the occurrence of malfunction due to noise in computations other than those for load and store processing.  
     SUMMARY OF THE INVENTION  
      The present invention has been made to solve such a problem, and has as its object to reduce noise due to simultaneous operations not only in computations for load and store processing but also other computations.  
      In order to achieve the above object, according to an aspect of the present invention, there is provided a vector processing apparatus comprising a plurality of vector pipeline computing units which operate in accordance with operation control information for instructing start and execution of processing, and an instruction control unit which generates operation control information and outputs the operation control information to the respective vector pipeline computing units at different timings.  
      According to another aspect of the present invention, there is provided an information processing apparatus comprising a plurality of computing units which operate in accordance with operation control information for instructing start and execution of processing, and an instruction control unit which generates operation control information and outputs the operation control information to the respective computing units at different timings.  
      According to still another aspect of the present invention, there is provided a vector processing method comprising the step of generating operation control information for instructing start and execution of processing and outputting the operation control information to a plurality of vector pipeline computing units at different timings, and the step of causing the vector pipeline computing units, to which the operation control information has been input at different timings, to sequentially start and execute processing. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is a block diagram showing the arrangement of a vector processing apparatus according to the first embodiment of the present invention;  
       FIG. 2  is a timing chart showing the operation of the vector processing apparatus shown in  FIG. 1 ;  
       FIG. 3  is a block diagram showing the arrangement of a vector processing apparatus according to the second embodiment of the present invention;  
       FIG. 4  is a block diagram showing the arrangement of a vector processing apparatus according to the third embodiment of the present invention;  
       FIG. 5  is a block diagram showing the arrangement of a timing adjusting unit in  FIG. 4 ;  
       FIG. 6  is a timing chart showing the operation of the vector processing apparatus shown in  FIG. 4 ;  
       FIG. 7  is a block diagram showing the arrangement of the vector processing apparatus according to the fourth embodiment of the present invention; and  
       FIG. 8  is a block diagram showing the arrangement of an operation control information generating unit in  FIG. 7 . 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS  
      The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Assume that in this case, 64 vector element data are processed per vector computation instruction. This, however, is merely an example. The number of vector element data to be processed per vector computation instruction is not limited to 64.  
      First Embodiment  
      As shown in  FIG. 1 , a vector processing apparatus  100  according to the first embodiment of the present invention includes an instruction control unit  10  and a plurality of vector pipeline computing units  160  to  167 . The number of vector pipeline computing units can be arbitrarily set.  
      The instruction control unit  10  includes an instruction execution control unit  13  which generates and outputs execution control information for a vector computation instruction, an operation designating unit  11  which holds noise reduction designation information indicating whether to execute noise reduction operation, and an operation control information generating unit  12  which receives control information from the instruction execution control unit  13 , generates various kinds of operation control information in accordance with the noise reduction designation information from the operation designating unit  11 , and outputs them to the instruction execution control unit  13  and the vector pipeline computing units  160  to  167 . Operation control information is information which instructs each of the vector pipeline computing units  160  to  167  to start and execute processing.  
      The operation designating unit  11  is comprised of, for example, an F/F (Flip-Flop) and the like. Noise reduction designation information can be externally set in the operation designating unit  11  as an initialization mode for hardware operation.  
      The vector pipeline computing units  160  to  167  operate concurrently. Each of the vector pipeline computing units  160  to  167  includes vector registers VR 0  to VRn (n=1, 2, . . . ) serving as data holding units which hold vector element data, an internal selecting unit SIN such as a cross bar which selects one of the vector registers VR 0  to VRn in which vector element data is to be written, an internal selecting unit SOUT such as a cross bar which selects one of the vector registers VR 0  to VRn from which vector element data is to be read out, element registers ER 0  and ER 1  which store vector element data from the internal selecting unit SOUT, at least one computation executing unit ALU which executes addition, subtraction, multiplication, and division for the vector element data stored in the element registers ER 0  and ER 1 , and a computation result register STR which stores the computation result obtained by the computation executing unit ALU.  
      The vector registers VR 0  to VRn are comprised of, for example, registers and the like. Each of the vector registers VR 0  to VRn stores, for example, eight vector element data.  
      The computation executing unit ALU further includes intermediate result registers AR 0  and AR 1  which store the intermediate results of computation. It is arbitrarily determined whether to mount the element registers ER 0  and ER 1 , intermediate result registers AR 0  and AR 1 , and computation result register STR and to determine where they are mounted.  
      For example, the element registers ER 0  and ER 1  are set as the first pipeline stage. The intermediate result register AR 0  can be set as the second pipeline stage. The intermediate result register AR 1  is set as the third pipeline stage. The computation result register STR is set as the fourth pipeline stage. The vector registers VR 0  to VRn are set as the fifth pipeline stage.  
      Vector element data are allocated to the vector registers VR 0  to VRn in the vector pipeline computing units  160  to  167  by an interleave scheme.  
      Vector element data a 0 , a 8 , a 16 , a 24 , a 32 , a 40 , a 48 , and a 56  are stored in the vector register VR 0  of the vector pipeline computing unit  160 . Vector element data al, a 9 , a 17 , a 25 , a 33 , a 41 , a 49 , and a 57  are stored in the vector register VR 0  of the vector pipeline computing unit  161 . Vector element data a 7 , a 15 , a 23 , a 31 , a 39 , a 47 , a 55 , and a 63  are stored in the vector register VR 0  of the vector pipeline computing unit  167 .  
      Likewise, vector element data b 0 , b 8 , b 16 , b 24 , b 32 , b 40 , b 48 , and b 56  are stored in the vector register VR 1  of the vector pipeline computing unit  160 . Vector element data b 1 , b 9 , b 17 , b 25 , b 33 , b 41 , b 49 , and b 57  are stored in the vector register VR 1  of the vector pipeline computing unit  161 . Vector element data b 7 , b 15 , b 23 , b 31 , b 39 , b 47 , b 55 , and b 63  are stored in the vector register VR 1  of the vector pipeline computing unit  167 .  
      Subsequently, other vector element data are stored in the vector registers VR 2  to VRn in the same manner.  
      The respective units of the vector processing apparatus  100  operate in accordance with clocks output from a clock generating unit  20 .  
      The operation of the vector processing apparatus  100  will be described next with reference to  FIG. 2 .  
      Assume that the vector processing apparatus  100  executes a vector computation instruction Y following a vector computation instruction X. The vector computation instruction X is, for example, an instruction to add the vector element data a 0  to a 63  in the vector registers VR 0  to the vector element data b 0  to b 63  in the vector registers VR 1  and store the resultant data as vector element data c 0  to c 63  in the vector registers VR 2 . The vector computation instruction Y is, for example, an instruction to add vector element data d 0  to d 63  in the vector registers VR 3  to vector element data e 0  to e 63  in the vector registers VR 4  and store the resultant data as vector element data f 0  to f 63  in the vector registers VR 5 .  
      The computation executing unit ALU executes computation for one element data pair per clock. Therefore, eight clocks are required for the execution of each of vector computation instructions X and Y. In the operation designating unit  11 , noise reduction designation information indicating that noise reduction operation is to be executed is set in advance.  
      The instruction execution control unit  13  generates control information for the execution of the vector computation instruction X at a clock T 0 , and outputs the information to the operation control information generating unit  12 .  
      Upon receiving control information from the instruction execution control unit  13 , the operation control information generating unit  12  generates operation control information for instructing the execution of the vector computation instruction X on the basis of the clock input from the clock generating unit  20 , and outputs the information to the vector pipeline computing units  160  to  167  at different timings. More specifically, the operation control information generating unit  12  outputs the operation control information for instructing the execution of the vector computation instruction X to the vector pipeline computing units  160  and  161  at a clock T 1 . The operation control information generating unit  12  outputs the operation control information for instructing the execution of the vector computation instruction X to the vector pipeline computing units  162  and  163  at a clock T 2 . The operation control information generating unit  12  outputs the operation control information for instructing the execution of the vector computation instruction X to the vector pipeline computing units  164  and  165  at a clock T 3 . The operation control information generating unit  12  outputs the operation control information for instructing the execution of the vector computation instruction X to the vector pipeline computing units  166  and  167  at a clock T 4 .  
      The vector pipeline computing unit  160  will be exemplified below.  
      In accordance with operation control information for the vector computation instruction X from the instruction control unit  10 , the internal selecting unit SOUT reads out vector element data a 0  from the vector register VR 0  and the vector element data b 0  from the vector register VR 1 . The readout vector element data a 0  is stored in the element register ER 0 , and the readout vector element data b 0  is stored in the element register ER 1  (the clock T 2  in  FIG. 2 ).  
      The computation executing unit ALU computes the vector element data a 0  from the element register ER 0  and the vector element data b 0  from the element register ER 1 , and stores the first intermediate result in the intermediate result register AR 0  (clock T 3 ). The computation executing unit ALU then computes the first intermediate result from the intermediate result register AR 0 , and stores the second intermediate result in the intermediate result register AR 1  (clock T 4 ). The computation executing unit ALU computes the second intermediate result from the intermediate result register AR 1 , and stores the computation result (c 0 =a 0 +b 0 ) in the computation result register STR (clock T 5 ). The computation result (c 0 =a 0 +b 0 ) from the computation result register STR is selected by the internal selecting unit SIN and stored in the vector register VR 3 .  
      The internal selecting unit SOUT reads out the vector element data a 8  from the vector register VR 0 , and the vector element data b 8  from the vector register VR 1 , and stores them respectively in the element registers ER 0  and ER 1 .  
      In this manner, computations are executed between the vector element data a 0 , a 8 , a 16 , a 24 , a 32 , a 40 , a 48 , and a 56  and the vector element data b 0 , b 8 , b 16  b 24 , b 32 , b 40 , b 48 , and b 56 , and the computation results (c 0 , c 8 , c 16 , c 24 , c 32 , c 40 , c 48 , and c 56 ) are stored in the vector register VR 3  (clocks T 6  to T 13 ).  
      The vector pipeline computing unit  161  sequentially executes computations between the vector element data a 1 , a 9 , a 17 , a 25 , a 33 , a 41 , a 49 , and a 57  and the vector element data b 1 , b 9 , b 17 , b 25 , b 33 , b 41 , b 49 , and b 57  at timings (from the clock T 2 ) similar to those in the vector pipeline computing unit  160 , and stores the computation results (c 1 , . . . , c 57 ) in the vector register VR 3  (clocks T 6  to T 13 ).  
      The vector pipeline computing unit  162  (vector pipeline computing unit  163 ) starts processing from the clock T 3  with a shift of one clock. Computations between the vector element data a 2  (a 3 ), a 10  (a 11 ), a 18  (a 19 ), a 26  (a 27 ), a 34  (a 35 ), a 42  (a 43 ), a 50  (a 5   1 ), and a 58  (a 59 ) and the vector element data b 2  (b 3 ), b 10  (b 11 ), b 18  (b 19 ), b 26  (b 27 ), b 34  (b 35 ), b 42  (b 43 ), b 50  (b 51 ), and b 58  (b 59 ) are executed, and the computation results (c 2  (c 3 ), . . . , c 58  (c 59 )) are stored in the vector register VR 3  (clocks T 7  to T 14 ).  
      The vector pipeline computing unit  164  (vector pipeline computing unit  165 ) starts processing from the clock T 4  with a shift of one clock. Computations between the vector element data a 4  (a 5 ), a 12  (a 13 ), a 20  (a 21 ), a 28  (a 29 ), a 36  (a 37 ), a 44  (a 45 ), a 52  (a 53 ), and a 60  (a 61 ) and the vector element data b 4  (b 5 ), b 12  (b 13 ), b 20  (b 21 ), b 28  (b 29 ), b 36  (b 37 ), b 44  (b 45 ), b 52  (b 53 ), and b 60  (b 61 ) are executed, and the computation results (c 4  (c 5 ), . . . , c 60  (c 61 )) are stored in the vector register VR 3  (clocks T 8  to T 15 ).  
      The vector pipeline computing unit  166  (vector pipeline computing unit  167 ) starts processing from the clock T 5  with a shift of one clock. Computations between the vector element data a 6  (a 7 ), a 14  (a 15 ), a 22  (a 23 ), a 30  (a 31 ), a 38  (a 39 ), a 46  (a 47 ), a 54  (a 55 ), and a 62  (a 63 ) and the vector element data b 6  (b 7 ), b 14  (b 15 ), b 22  (b 23 ), b 30  (b 31 ), b 38  (b 39 ), b 46  (b 47 ), b 54  (b 55 ), and b 62  (b 63 ) are executed, and the computation results (c 6  (c 7 ), . . . , c 62  (c 63 )) are stored in the vector register VR 3  (clocks T 9  to T 16 ).  
      The instruction execution control unit  13  then generates control information for the execution of the vector computation instruction Y and outputs the information to the operation control information generating unit  12  at a clock T 8 .  
      Upon receiving the control information from the instruction execution control unit  13 , the operation control information generating unit  12  generates operation control information for instructing the execution of the vector computation instruction Y on the basis of a clock input from the clock generating unit  20 , and outputs the information to the vector pipeline computing units  160  to  167  at different timings. More specifically, the operation control information generating unit  12  outputs operation control information for instructing the execution of the vector computation instruction Y to the vector pipeline computing units  160  and  161  at the clock T 9 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the vector computation instruction Y to the vector pipeline computing units  162  and  163  at the clock T 10 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the vector computation instruction Y to the vector pipeline computing units  164  and  165  at the clock T 11 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the vector computation instruction Y to the vector pipeline computing units  166  and  167  at the clock T 12 .  
      The vector pipeline computing units  160  to  167  continuously execute the vector computation instructions Y like the vector computation instructions X. That is, the vector pipeline computing unit  160  starts processing the vector computation instruction Y from the clock T 10 , adds the vector element data in the vector register VR 3  to the vector element data in the vector register VR 4 , and stores the resultant data in the vector register VR 5 .  
      As described above, the vector pipeline computing units  160  to  167  sequentially operate in pairs with a shift of a 1T clock cycle. This shifted operation can be performed not only for vector computation instructions but also for vector load instructions (instructions to load vector element data from the memory into the vector registers VR 0  to VRn through the internal selecting unit SIN), and vector store instructions (instructions to store vector element data from the vector registers VR 0  to VRn to the memory through the internal selecting unit SOUT). Vector computation instructions, vector load instructions, vector store instructions, and the like are generically called “vector instructions”.  
      Since the processing operations of the vector pipeline computing units  160  to  167  are temporarily shifted from each other, the amount of switching for the start of simultaneous operations of circuits at the start of the execution of a vector computation instruction (clocks T 2  to T 5  in particular) can be reduced. As a consequence, noise caused by simultaneous operation can be reduced. The operation of reducing noise by temporarily shifting the start and execution of processing by the vector pipeline computing units  160  to  167  will be called “noise reduction operation”.  
      This embodiment has exemplified the case wherein the operation control information generating unit  12  outputs operation control information to the vector pipeline computing units  160  and  161 , the vector pipeline computing units  162  and  163 , the vector pipeline computing units  164  and  165 , and the vector pipeline computing units  166  and  167  at timings shifted from each other by one clock. However, such information may be output at timings shifted from each other by two or more clocks. Alternatively, operation control information may be output to the vector pipeline computing units  160  to  167  at different timings.  
      Second Embodiment As shown in  FIG. 3 , in a vector processing apparatus  200  according to the second embodiment of the present invention, the internal selecting unit SIN in the vector processing apparatus  100  shown in  FIG. 1  is integrated in the internal selecting unit SOUT to become an internal selecting unit SIO. As a consequence, a computation result register STR and vector registers VR 0  to VRn are directly connected to each other. If this apparatus comprises a plurality of computation executing units ALU, a computation result selecting unit SAL may be provided at the input of the computation result register STR. The operation of the vector processing apparatus  200  is equivalent to that of the vector processing apparatus  100  described above except that the operation of the internal selecting unit SIN in the apparatus  100  becomes simple transfer operation instead of selection operation.  
      Third Embodiment  
      As shown in  FIG. 4 , a vector processing apparatus  300  according to the third embodiment of the present invention includes an external selecting unit  14  such as a cross bar and a timing adjusting unit  15  in addition to the vector processing apparatus  100  (or the vector processing apparatus  200  shown in  FIG. 3 ).  FIG. 4  shows the schematic arrangement of each of vector pipeline computing units  160  to  167 .  
      An operation control information generating unit  12  of an instruction control unit  10  also outputs the same information as operation control information output to the vector pipeline computing units  160  to  167  to the external selecting unit  14  and timing adjusting unit  15 . The external selecting unit  14  selects vector element data in accordance with operation control information from the operation control information generating unit  12 . The timing adjusting unit  15  adjusts the input timing of vector element data to the external selecting unit  14  and the output timing of vector element data from the external selecting unit  14 .  
      The external selecting unit  14  and timing adjusting unit  15  are used for instructions for processing vector element data among the vector pipeline computing units  160  to  167 . For example, such instructions include instructions to transfer vector element data between the vector pipeline computing units  160  to  167  and an instruction to calculate the sum total of all vector element data.  
      Instructions to transfer vector element data between the vector pipeline computing units  160  to  167  include, for example, right rotate instructions Z. The right rotate instructions Z are instructions to rotate vector element data a 0 , a 8 , a 16 , a 24 , a 32 , a 40 , a 48 , and a 56  stored in a vector register VR 0  in the vector pipeline computing unit  160 , vector element data a 1 , a 9 , a 17 , a 25 , a 33 , a 41 , a 49 , and a 57  stored in a vector register VR 0  in the vector pipeline computing unit  161 , . . . , and vector element data a 7 , a 15 , a 23 , a 31 , a 39 , a 47 , a 55 , and a 63  stored in a vector register VR 0  in the vector pipeline computing unit  167  to the right by seven vector element data, and store the resultant data in a vector registers VR 1 . As a result, the vector element data a 7 , a 15 , a 23 , a 31 , a 39 , a 47 , a 55 , and a 63  are stored in the vector register VR 1  in the vector pipeline computing unit  160 , the vector element data a 0 , a 8 , a 16 , a 24 , a 32 , a 40 , a 48 , and a 56  are stored in the vector register VR 1  in the vector pipeline computing unit  161 , . . . , and the vector element data a 6 , a 14 , a 22 , a 30 , a 38 , a 46 , a 54 , and a 62  are stored in the vector pipeline computing unit  167 .  
      The arrangement of the timing adjusting unit  15  will be described with reference to  FIG. 5 .  FIG. 5  shows the arrangement of the timing adjusting unit  15  provided on the input side of the external selecting unit  14 . In this case, the vector pipeline computing units  160  to  167  are directly connected to the output side of the external selecting unit  14 .  
      The timing adjusting unit  15  shown in  FIG. 5  outputs vector element data input from the vector pipeline computing units  160  to  167  at different timings to the external selecting unit  14  at the same timing. More specifically, the timing adjusting unit  15  includes delay circuits  150  to  155  and adjustment selecting units DS 0  to DS 5 .  
      The delay circuit  150  outputs vector element data input from the vector pipeline computing unit  160  upon delaying the data by a time corresponding to the vector pipeline computing unit  160 . The delay circuit  151  outputs vector element data input from the vector pipeline computing unit  161  upon delaying the data by a time corresponding to the vector pipeline computing unit  161 . The delay circuit  152  outputs vector element data input from the vector pipeline computing unit  162  upon delaying the data by a time corresponding to the vector pipeline computing unit  162 . The delay circuit  153  outputs vector element data input from the vector pipeline computing unit  163  upon delaying the data by a time corresponding to the vector pipeline computing unit  163 . The delay circuit  154  outputs vector element data input from the vector pipeline computing unit  164  upon delaying the data by a time corresponding to the vector pipeline computing unit  164 . The delay circuit  155  outputs vector element data input from the vector pipeline computing unit  165  upon delaying the data by a time corresponding to the vector pipeline computing unit  165 .  
      In this case, the times corresponding to the vector pipeline computing units  160  to  167  are times to cancel out delay times given when the instruction control unit  10  outputs operation control information to other vector pipeline computing units. More specifically, the time corresponding to the vector pipeline computing units  160  and  161  correspond to a 3T clock cycle, the time corresponding to the vector pipeline computing units  162  and  163  corresponds to a 2T clock cycle, and the time corresponding to the vector pipeline computing units  164  and  165  corresponds to a 1T clock cycle.  
      The delay circuits  150  to  155  are configured in the following manner by using adjusting registers DR by which a delay time corresponding to a 1T clock cycle is obtained. The delay circuit  150  has an arrangement in which adjusting registers DR 00 , DR 01 , and DR 02  are cascaded. The delay circuit  151  has an arrangement in which adjusting registers DR 10 , DR 11 , and DR 12  are cascaded. The delay circuit  152  has an arrangement in which adjusting registers DR 20  and DR 21  are cascaded. The delay circuit  153  has an arrangement in which adjusting registers DR 30  and DR 31  are cascaded. The delay circuit  154  comprises an adjusting register DR 40 . The delay circuit  155  comprises an adjusting register DR 50 .  
      The adjustment selecting unit DS 0  selects either vector element data from the vector pipeline computing unit  160  or vector element data from the delay circuit  150 . The adjustment selecting unit DS 1  selects vector element data from the vector pipeline computing unit  161  or vector element data from the delay circuit  151 . The adjustment selecting unit DS 2  selects vector element data from the vector pipeline computing unit  162  or vector element data from the delay circuit  152 . The adjustment selecting unit DS 3  selects vector element data from the vector pipeline computing unit  163  or vector element data from the delay circuit  153 . The adjustment selecting unit DS 4  selects vector element data from the vector pipeline computing unit  164  or vector element data from the delay circuit  154 . The adjustment selecting unit DS 5  selects vector element data from the vector pipeline computing unit  165  or vector element data from the delay circuit  155 . The adjustment selecting units DS 0  to DS 5  select vector element data depending on operation control information input from the operation control information generating unit  12  to the adjustment selecting units DS 0  to DS 5 .  
      Note that the timings of vector element data from the vector pipeline computing units  166  and  167  are not adjusted.  
      The operation of the vector processing apparatus  300  shown in  FIG. 4  will be described next with reference to  FIG. 6 .  
      Referring to  FIG. 6 , the operation control information generating unit  12  outputs operation control information for instructing the execution of the right rotate instruction Z to the vector pipeline computing units  160  and  161  at a clock T 1 . The operation control information generating unit  12  also outputs the same right rotate instruction Z to the timing adjusting unit  15  (adjustment selecting units DS 0  and DS 1 ) and external selecting unit  14 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the right rotate instruction Z to the vector pipeline computing units  162  and  163  at a clock T 2 . The operation control information generating unit  12  also outputs the same right rotate instruction Z to the timing adjusting unit  15  (adjustment selecting units DS 2  and DS 3 ) and external selecting unit  14 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the right rotate instruction Z to the vector pipeline computing units  164  and  165  at a clock T 3 . The operation control information generating unit  12  also outputs the same right rotate instruction Z to the timing adjusting unit  15  (adjustment selecting units DS 4  and DS 5 ) and external selecting unit  14 . The operation control information generating unit  12  outputs operation control information for instructing the execution of the right rotate instruction Z to the vector pipeline computing units  166  and  167  at a clock T 4 . The operation control information generating unit  12  also outputs the same right rotate instruction Z to the timing adjusting unit  15  (adjustment selecting units DS 6  and DS 7 ) and external selecting unit  14 .  
      When operation control information is input to the vector pipeline computing unit  160  (vector pipeline computing unit  161 ), an internal selecting unit SOUT (or an internal selecting unit SIO) reads out the vector element data a 0  (a 1 ) stored in the vector register VR 0 , and outputs it to the timing adjusting unit  15 . In the timing adjusting unit  15 , the vector element data a 0  (a 1 ) is stored in the adjusting register DR 00  (adjusting register DR 10 ) of the delay circuit  150  (delay circuit  151 ) (the clock T 2  in  FIG. 6 ). The vector element data a 0  (a 1 ) is stored in the adjusting register DR 00  (adjusting register DR 11  (clock T 3 ). The vector element data a 0  (a 1 ) is stored in the adjusting register DR 02  (adjusting register DR 12 ) (clock T 4 ). The vector element data a 0  (a 1 ) is selected from the adjusting register DR 02  (adjusting register DR 12 ) by the adjustment selecting unit DS 0  (adjustment selecting unit DS 1 ), and is output to the external selecting unit  14  (clock T 5 ).  
      When operation control information is input to the vector pipeline computing unit  162  (vector pipeline computing unit  163 ), the internal selecting unit SOUT (or the internal selecting unit SIO) reads out the vector element data a 2  (a 3 ) stored in the vector register VR 0 , and outputs it to the timing adjusting unit  15 . In the timing adjusting unit  15 , the vector element data a 2  (a 3 ) is stored in the adjusting register DR 20  (adjusting register DR 30 ) of the delay circuit  152  (delay circuit  153 ) (clock T 3 ). The vector element data a 2  (a 3 ) is stored in the adjusting register DR 21  (adjusting register DR 21 ) (clock T 4 ). The vector element data a 2  (a 3 ) is stored in the adjusting register DR 21  (adjusting register DR 121 ) (clock T 4 ). The vector element data a 2  (a 3 ) is selected from the adjusting register DR 21  (adjusting register DR 21 ) by the adjustment selecting unit DS 2  (adjustment selecting unit DS 3 ), and is output to the external selecting unit  14  (clock T 5 ).  
      When operation control information is input to the vector pipeline computing unit  164  (vector pipeline computing unit  165 ), the internal selecting unit SOUT (or the internal selecting unit SIO) reads out the vector element data a 4  (a 5 ) stored in the vector register VR 0 , and outputs it to the timing adjusting unit  15 . In the timing adjusting unit  15 , the vector element data a 4  (a 5 ) is stored in the adjusting register DR 40  (adjusting register DR 50 ) of the delay circuit  154  (delay circuit  155 ) (clock T 4 ). The vector element data a 4  (a 5 ) is selected from the adjusting register DR 40  (adjusting register DR 50 ) by the adjustment selecting unit DS 4  (adjustment selecting unit DS 5 ), and is output to the external selecting unit  14  (clock T 5 ).  
      When operation control information is input to the vector pipeline computing unit  166  (vector pipeline computing unit  167 ), the internal selecting unit SOUT (or the internal selecting unit SIO) reads out the vector element data a 6  (a 7 ) stored in the vector register VR 0 , and outputs it to the timing adjusting unit  15 . The vector element data a 4  (a 5 ) is output to the external selecting unit  14  through the timing adjusting unit  15  (clock T 5 ).  
      Subsequently, the external selecting unit  14  receives the vector element data a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , a 6 , and a 7  from the timing adjusting unit  15 . On the basis of operation control information from the operation control information generating unit  12 , the external selecting unit  14  outputs the vector element data a 7 , a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , and a 6  respectively to the vector pipeline computing units  160 ,  161 ,  162 ,  163 ,  164 ,  165 ,  166 , and  167  (clock T 5 ).  
      The vector element data a 7 , a 0 , a 1 , a 2 , a 3 , a 4 , a 5 , and a 6  are stored in the vector registers VR 1  through the internal selecting units SIN (or the internal selecting units SIO) of the vector pipeline computing units  160  to  167  (clock T 5 ). The vector element data a 15 , a 8 , a 9 , a 10 , a 11 , a 12 , a 13 , and a 14  are stored in the vector registers VR 1  through the internal selecting units SIN of the vector pipeline computing units  160  to  167  (clock T 6 ). In this manner, the right rotate instructions Z are sequentially executed.  
      The vector processing apparatus  300  shown in  FIG. 4  has an effect of being capable of easily executing instructions for processing of vector element data among the vector pipeline computing units  160  to  167  as compared with the vector processing apparatuses  100  and  200  shown in  FIGS. 1 and 3 .  
      Fourth Embodiment  
      As shown in  FIG. 7 , a vector processing unit  400  according to the fourth embodiment of the present invention has an arrangement equivalent to that of the vector processing apparatus  300  shown in  FIG. 4  from which the timing adjusting unit  15  is omitted. In executing instructions for processing of vector element data among vector pipeline computing units  160  to  167 , an operation control information generating unit  12 A of an instruction control unit  10 A outputs pieces of operation control information to the vector pipeline computing units  160  to  167  without shifting them. For example, in executing right rotate instructions Z, the operation control information generating unit  12 A outputs pieces of operation control information for the start of execution of the right rotate instructions Z to all the vector pipeline computing units  160  to  167  at a clock T 4  in  FIG. 6 .  
      The arrangement of the operation control information generating unit  12 A will be described with reference to  FIG. 8 .  
      The operation control information generating unit  12 A includes a shift register  121 , selection information generating unit CSS, control selecting unit CS 0 , control selecting unit CS 1 , control selecting unit CS 2 , and control selecting unit CS 3 . The shift register  121  is a four-stage shift register comprising a control register FR 0 , control register FR 1 , control register FR 2 , and control register FR 3 . Control information is input from an instruction execution control unit  13  to the first stage (control register FR 0 ) of the shift register  121 . This control information is shifted from a given stage to another stage of the shift register  121  every time a clock is input from a clock generating unit  20 . The selection information generating unit CSS generates selection information for the control selecting units CS 0  to CS 3  on the basis of control information from the instruction execution control unit  13  and noise reduction designation information from the operation designating unit  11 .  
      Selection information is generated in the following manner. 
      (1) When noise reduction designation information does not designate noise reduction operation:    

      Selection information causes the control selecting units CS 0  to CS 3  to select the control information stored in the first stage of the shift register  121 , i.e., the control information from the control register FR 0 . The control selecting units CS 0  to CS 3  may be caused to select the control information stored in a specific stage of the shift register  121  other than the first stage, i.e., the control information from any one of the control registers FR 1  to FR 3 . 
      (2) When noise reduction designation information designates noise reduction operation, and control information from the instruction execution control unit  13  does not indicate an instruction for the execution of processing of vector element data among the vector pipeline computing units  160  to  167 :    

      The control information causes the control selecting unit CSO to select the control information stored in the first stage of the shift register  121 , i.e., the control information from the control register FR 0 . The control information causes the control selecting unit CS 1  to select the control information stored in the second stage of the shift register  121 , i.e., the control information from the control register FR 1 . The control information causes the control selecting unit CS 2  to select the control information stored in the third stage of the shift register  121 , i.e., the control information from the control register FR 2 . The control information causes the control selecting unit CS 3  to select the control information stored in the last stage of the shift register  121 , i.e., the control information from the control register FR 3 . That is, the control information causes each of the control selecting units CS 0  to CS 3  to select one of the pieces of control information stored in the respective stages of the shift register  121 . 
      (3) When noise reduction designation information designates noise reduction operation, and control information from the instruction execution control unit  13  indicates an instruction for the execution of processing of vector element data among the vector pipeline computing units  160  to  167 :    

      The control information causes the control selecting units CS 0  to CS 3  to select the control information stored in the last stage of the shift register  121 , i.e., the control information from the control register FR 3 .  
      The control selecting unit CS 0  outputs the control information selected in accordance with the selection information, as operation control information, to the vector pipeline computing units  160  and  161 . The control selecting unit CS 1  outputs the control information selected in accordance with the selection information, as operation control information, to the vector pipeline computing units  162  and  163 . The control selecting unit CS 2  outputs the control information selected in accordance with the selection information, as operation control information, to the vector pipeline computing units  164  and  165 . The control selecting unit CS 3  outputs the control information selected in accordance with the selection information, as operation control information, to the vector pipeline computing units  166  and  167 .  
      In the case of (1), pieces of operation control information are output to all the vector pipeline computing units  160  to  167  at the same timing. In the case of (2), pieces of operation control information are sequentially output to the vector pipeline computing units  160  and  161 , the vector pipeline computing units  162  and  163 , the vector pipeline computing units  164  and  165 , and the vector pipeline computing units  166  and  167  at different timings. In the case of (3) as well, pieces of operation control information are output to the vector pipeline computing units  160  to  167  at the same output timing as that for the vector pipeline computing units  166  and  167  which operate at the last timing.  
      The vector processing unit  400  shown in  FIG. 7  can omit the timing adjusting unit  15  as compared with the vector processing apparatus  300  shown in  FIG. 4 , and has an effect of being capable of reducing the hardware amount.  
      The operation control information generating unit  12 A shown in  FIG. 8  is identical to the operation control information generating unit  12  shown in  FIG. 1  except for the control function in the case of (3).  
      As described above, according to the above embodiments, the processing start timings of the vector pipeline computing units  160  to  167  can be shifted regardless of whether load and store instructions are to be executed. This makes it possible to reduce noise caused by simultaneous operation and prevent the occurrence of malfunction in various kinds of computations as compared with the prior art.  
      The vector processing apparatus  100  having the vector pipeline computing units  160  to  167  which process vector element data has been described above. However, the present invention can be applied to an information processing apparatus having a plurality of computing units. Performing control to shift the computation start timings of the plurality of computing units makes it possible to reduce noise due to simultaneous operations.  
      In addition, the above vector processing apparatuses  100  to  400  or the information processing apparatus can be formed on one LSI. In addition, the vector processing apparatuses  100  to  400  or the information processing apparatus can be formed on a plurality of LSIs.