Patent Publication Number: US-6704356-B1

Title: Processing of block units, generated from a digital video signal, using block number information and color field information

Description:
This application is a continuation of Ser. No 08/347,329, file Mar. 13, 1995 U.S. Pat. No. 5,706,056, which is a 371 of PCT/JP/94/00503, filed Mar. 29, 1994. 
    
    
     TECHNICAL FIELD 
     The present invention relates to a signal processing apparatus, and more particularly to an improvement of recording or reproducing apparatus for a digital video tape recorder (D-VTR) for discrete cosine transforming (DCT) video signal in order to compress amount of information thereof and recording it. 
     BACKGROUND ART 
     Heretofore, as this type of D-VTR, there is one shown in FIG.  1 . In FIG. 1,  1  generally denotes the D-VTR. A digital video signal S 1  (FIG.  2 (B)) input from a predetermined video signal generating unit is input to a DCT shuffling circuit  2 . The DCT shuffling circuit  2  has a DCT address circuit  3  in association therewith, a vertical synchronizing signal S V  (FIG.  2 (A)) is input to the DCT address circuit  3 . 
     Accordingly, the DCT shuffling circuit  2  divides the digital video signal S 1  into DCT blocks of 8 columns×4 rows for each one field by shuffle address generated by the DCT address circuit  3  on the basis of the vertical synchronizing signal S V . The DCT shuffling circuit  2  collects 10 blocks of the DCT blocks from their respective positions discretely located from each other within a screen to generate shuffle data S 2  (FIG.  2 (C)), and outputs the shuffle data S 2  to the following DCT conversion circuit  4 . 
     Here, the DCT shuffling circuit  2  performs shuffling processing by each one field. Thereby, the shuffle data S 2  output from the DCT shuffling circuit  2  is supplied to the DCT conversion circuit  4  at a timing delayed by one field time period T 2  from the digital video signal S 1  as shown in FIG.  2 (C). 
     The DCT conversion circuit  4  performs discrete cosine transform to data of each DCT block and supplies DCT data S 3  to a quantization delay circuit  5  and a quantization level detecting circuit  6 . The quantization level detecting circuit  6  detects a quantization level (quantization width) for achieving a target compression rate for the DCT data S 3 . Since, at this time, about ten-block time period is required as the signal processing time in the quantization level detecting circuit  6 , the quantization delay circuit  5  delays the DCT data S 3  by the signal processing time, and supplies it to a quantization circuit  7  as a quantization delay output data S 5 . Accordingly, the quantization delay output data S 5  is input to the quantization circuit  7  at the same timing as quantization level data S 4  which is output from the quantization level detecting circuit  6  at a time point t 3  delayed by a 10-block time period T 3  from the shuffle data S 2  as shown in FIG.  2 (D). 
     The quantization circuit  7  quantizes the quantization delay output data S 5  supplied from the quantization delay circuit  5  based on the quantization level data S 4  supplied from the quantization level detecting circuit  6  in order to compress amount of information thereof. At this time, the quantization circuit  7  detects a maximum value, a minimum value, and a mean value etc., of quantization level within one field, on the basis of a period signal for each one field obtained from the vertical synchronizing signal S V  at a vertical counter  8  provided in association therewith, and outputs the result as detection data S 6  to a quantization monitor (not shown) to monitor the state of compression of data at the quantization circuit  7 . 
     Further, quantization data S 7  obtained from the quantization circuit  7  is supplied to a variable-length coding circuit  9 . The variable-length coding circuit  9  performs variable-length coding to the quantization data S 7  to generate variable-length coding data S 9  having a block length prescribed in a format, and outputs it to an error correcting outer coding circuit  11 . 
     The error correcting outer coding circuit  11  generates an error correcting outer code for correcting an error occurred in the manner of a burst, on the basis of a timing obtained from the vertical synchronizing signal S V  at a parity timing circuit  12  which is provided in association therewith, and the result is added to the variable-length coding data S 9  and is output to a track shuffling circuit  13 . 
     The track shuffling circuit  13  generates track shuffle data S 13  by recording the data into an order suitable for the track pattern on a magnetic tape, in accordance with shuffle address obtained from the vertical synchronizing signal S V  at a track address circuit  14  which is provided in association therewith. 
     The track shuffle data S 13  is supplied to an error correcting inner coding circuit  15 . The error correcting inner coding circuit  15  generates an error correcting inner code for correcting random error and adds to the track shuffle data S 13 . An ID counter  16  which is provided in association with the error correcting inner coding circuit  15 , obtains a block number obtained from the vertical synchronizing signal S V  and the color field signal S C , and color field information corresponding to a time period when the phase shift of carrier resulting from phase shifts by each scanning line completes a cycle. 
     The error correcting inner coding circuit  15  adds the block number and the color field information to the track shuffle data S 13  as ID information, and outputs the result to a recording circuit  17  as recording data S 12 . The recording circuit  17  converts the recording data S 12  from an 8 [bit] parallel form to 1 [bit] serial form and effects channel coding suitable for magnetic recording, and records on a magnetic tape  19  by means of a magnetic head  18  provided on a rotary drum. 
     Here, since the track shuffling circuit  13  performs re-ordering processing of data by each ⅓ field, the recording data S 12  obtained on the basis of the track shuffle data S 13  is output from the error correcting inner coding circuit  15  at a time point t 4  delayed by ⅓ field period T 4  from quantization delay output data S 5  output from the quantization delay circuit  5  as shown in FIG.  2 (E). 
     Here, in the recording data S 12  in the D-VTR  1 , a synchronizing pattern is added to the beginning of a data block as a delimiter for the block and a delimiter for restoring data recorded in 1 [bit] serial form on the magnetic tape into the original 8 [bit] parallel form. 
     Further, a block number for indicating the sequential order of each data block is added as ID information at the error correcting inner coding circuit  15 , so that an image is reproduced even when data blocks are not continuously reproduced as the reproducing head helically scans a plurality of tracks in double-speed reproducing etc. Furthermore, color field information is also added as ID information at the error correcting inner coding circuit  15 . 
     Further, video data generated through the above DCT shuffling circuit  2  to the error correcting inner coding circuit  15  is recorded subsequently to the ID information. At the beginning of the video data, the quantization level information in data compression is added at the quantization circuit  7  in accordance with the quantization level data S 4 . Furthermore, an inner parity data for correcting a random error is added at the error correcting inner coding circuit  15 . 
     In the D-VTR  1  of such construction, data is output with a delay of the time necessary for the signal processing at each signal processing circuit. For example, at the DCT shuffling circuit  2 , data is output with a delay corresponding to one field time period T 2  (FIG.  2 (C)), and at the quantization delay circuit  5 , data is delayed by 10-block time period T 3  (FIG.  2 (D)). Further, at the DCT conversion circuit  4 , the quantization circuit  7 , and the variable-length coding circuit  9 , data is delayed by about one block time period respectively, and at the track shuffling circuit  13 , data is delayed by ⅓ field time period T 4  (FIG.  2 (E)). 
     Accordingly, at the timing circuits of the vertical counter  8 , the parity timing circuit  12 , the track address circuit  14 , and the ID counter  16 , timing signals must be generated with their phase conforming to their respective delay time from the vertical synchronizing signal S V . 
     Further, while the color field information is input at the same timing as the digital video signal S 1 , data (track shuffle data S 13 ) input to the error correcting inner coding circuit  15  to which the color field information is to be added as ID information is delayed by about 1.4 field from the input point t 1  (FIGS.  2 (A) to  2 (E)) of the digital video signal S 1 . Accordingly, a latch circuit for reading the color field information with a delay corresponding to such delay time is necessary at the ID counter  16 , resulting in a problem of complicating the construction. 
     Further, all of these delay phases occur as an accumulation of processing time in the signal processing circuits up to the previous stage of that point and, when processing time of a signal processing circuit is changed in its development process, timing of all the signal processing circuits after the changed signal processing circuit must be corrected in accordance with such changed time period. 
     DISCLOSURE OF INVENTION 
     Considering the above points, the present invention provides a signal processing apparatus such that, data to be output with a delay at each signal processing circuit can securely be processed and delivered irrespective of delay time of the data due to the signal processing time of the respective signal processing circuit. 
     To solve such problems according to the present invention, a signal processing apparatus having a plurality of signal processing circuits which are sequentially connected so as to make a desired data into a predetermined unit and sequentially perform signal processing, at least one of which performs a predetermined signal processing to the desired data at the timing determined on the basis of a processing timing of the another signal processing circuits, wherein at least one of signal processing circuits outputs the desired data with adding timing data indicating the processing timing. The another signal processing circuits set the timing of signal processing for the desired data on the basis of the timing data. 
     Further, in the present invention, a signal processing apparatus having a plurality of signal processing circuits which are sequentially connected so as to make video data into a predetermined unit and sequentially perform signal processing, at least one of which performs predetermined signal processing to the video data at the timing determined on the basis of a processing timing of the another signal processing circuits, wherein at least one of signal processing circuits outputs the video data with adding timing data indicating the processing timing. The another signal processing circuits set the timing of signal processing for the video data on the basis of the timing data. 
     Further, in the present invention, a signal processing apparatus  20  for digital video signal for performing a predetermined signal processing for digital video signal S 1 , comprising: a block shuffling circuit  21  for making input digital video signal S 1  into a predetermined unit in order to perform a block conversion coding and shuffling it to obtain shuffle data S 21 , and then for outputting the shuffle data S 21  with adding a block number information D BL  and a color field information D FI  of the digital video signal S 1  as header data; a block conversion coding circuit  23  receiving the output of the block shuffling circuit  21  for performing block conversion coding for the shuffle data S 21  and obtain coding data S 22 , and for outputting the coded data S 22  with adding the header data; a quantization circuit  25  receiving the output of the block conversion coding circuit  23  for quantizing the coding data S 22  and obtain quantized data S 25 , and for outputting the quantized data S 25  with adding the header data to which quantization level information D Q  in quantizing is added to the quantized data S 25 ; a variable-length coding circuit  26  receiving the output of the quantization circuit  25  for processing variable-length coding to the quantized data S 25  to obtain variable-length coded data S 26 , and for outputting the variable-length coded data S 26  with adding the header data; an error correcting outer coding circuit  27  receiving the output of the variable-length coding circuit  26  for generating error correcting coding data in accordance with the block number information D BL  and for outputting the error correcting coding data with adding the output of the variable-length coding circuit  26 ; a shuffling circuit  28  receiving the output of the error correcting outer coding circuit  27  for shuffling the variable-length coded data in accordance with the block number information D BL , and for outputting the shuffle data with adding the header data to obtain shuffle data S 28 , and for outputting the shuffle data S 28  with adding the header data; and an error correcting inner coding circuit  29  receiving the output of the shuffling circuit  28  for generating an error correcting inner code data in accordance with the block number information D BL  and the color field information D FI , and for outputting the error correcting inner code data with adding the output of the shuffling circuit  28 . 
     When the desired data S 1  is output sequentially through each of the signal processing circuits  21  to  29 , timing data D FI , D BL , and/or D Q  are/is added to the data S 1  and processing at each signal processing circuit  21  to  29  is performed at a timing based on the timing data D FI , D BL , and/or D Q , so that the data S 1  can be delivered between the signal processing circuits  21  to  29  without regard to processing time in the respective signal processing circuits  21  to  29 . 
    
    
     BRIEF DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram showing the construction of a conventional recording and/or reproducing apparatus; 
     FIGS.  2 (A) to  2 (E) are signal waveform diagrams explaining delayed state of data due to the signal processing; 
     FIG. 3 is a schematic diagram explaining a recording format in recording and/or reproducing by a recording and/or reproducing apparatus according to the present invention; 
     FIG. 4 is a schematic diagram explaining the structure of the sync blocks; 
     FIGS.  5 (A) and  5 (B) are schematic diagrams explaining contents recorded in the identification pattern of the sync blocks; 
     FIG. 6 is a block diagram showing the construction of an embodiment of recording and/or reproducing apparatus according to the present invention; and 
     FIGS.  7 (A) to  7 (C) are schematic diagrams explaining data arrangement being used in the recording and/or reproducing apparatus. 
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     An embodiment of the present invention will be described in detail, with the accompanying drawings: 
     FIG. 3 shows a recording format on a magnetic tape which is recorded by a D-VTR according to the present invention. Digital video signal and digital audio signal for one field are made into a predetermined unit and recorded in the area of six helical recording tracks. The six recording tracks are segmented by two recording tracks and at each of which the segment number  1 ,  2 ,  3  are sequentially allocated from the head of one field. 
     Further, the track number  0  or  1  is allocated to the two recording tracks of respective segment. In one recording track, a preamble, video data of 126 sync blocks, audio data of 6 sync blocks×4 channels, and another video data of 126 sync blocks are sequentially recorded. 
     Here, as shown in FIG. 4, each sync block is 180-byte length, in which at the beginning 2 bytes, a synchronization pattern SYNC is recorded, at the succeeding 2 bytes, an identification pattern ID is recorded, at the succeeding 162 bytes, compressed video data, audio data, or these error correcting outer code parity is recorded as a recording data DATA, and at the end 14 bytes, an error correcting inner code parity IP of the identification pattern ID or recording data DATA is recorded. 
     Practically, in the synchronization pattern SYNC, for example, the value “ 2 ED 3 (H)” is recorded as a fixed pattern. At the beginning one byte, corresponding numbers of sync block are recorded as the identification pattern ID in the sequence of FIG.  5 (A). Further, at the succeeding one byte, flag information indicating the property of corresponding sync block is recorded as an identification pattern ID by sector numbers as shown in FIG.  5 (B). 
     That is, when being the value “1”, bit  0  of the LSB in this byte indicates the sector of video data, and when being the value “0”, which is an identification flag indicating the sector of audio data. At the bit  1 , the value “0” or “1” is recorded as a track number in the above segment number. At the bits  2  and  3 , the value “1”, “2”, or “3” of the above segment number is recorded in 2 bits. At the bits  4 ,  5 , and  6 , a color field information is recorded. The bit  7  of the MSB indicates a format of the digital video data, and when being component video data, the value “1” is recorded, and when being composite video data, the value “0” is recorded. 
     In the D-VTR  20  shown in FIG. 6, the corresponding part to FIG. 1 is denoted by the same numerals. A DCT address circuit  22  generates a shuffle address on the basis of the vertical synchronization signal S V , and a DCT shuffling circuit  21  shuffles digital video signal S 1  in accordance with the shuffle address to generate shuffle data S 21 , and supplies it to a DCT circuit  23 . 
     At this time, as shown in FIG.  7 (A), the DCT shuffling circuit  21  adds a block number D BL  generated by the DCT address circuit  22  and a color field information D FI  to DCT block data D SH  as header information. Here, the block number D BL  corresponds to the total of the sync block number of the first byte in the identification pattern ID which has been described accompanying with FIGS.  4  and  5 (A) and  5 (B), the data identification flag, the segment number, and the track number of the bits  0  to  3  of the second byte, and the color field information D FI  corresponds to the color field information of the bits  4  to  6  of the second byte. 
     The DCT transformation circuit  23  performs discrete cosine transformation for respective DCT block data D SH  on the basis of the block number D BL  and color field information D FI , and supplies the result as DCT data S 22  to a quantization level delay circuit  24 . The quantization level delay circuit  24  detects a quantization level for determining a quantized width at the following quantization circuit  25  while delaying the DCT data S 22 , and as shown in FIG.  7 (B), outputs the DCT data D DCT  to a quantization circuit  25  as quantization level delay output data S 23  with thus detected quantization level information D Q  added as a header information. 
     The quantization circuit  25  quantizes the DCT data D DCT  on the basis of the quantization level information D Q  added as a header information in order to compress. At this time, the head and end of the field are investigated by the block number D BL  added as a header information to calculate the mean value of the quantization levels, etc., the calculated result S 24  is output to a quantization monitor (not shown), so that the compressed state can be monitored. 
     Further, in the quantization circuit  25 , the compression-processed quantized data S 25  is supplied to a variable-length coding circuit  26  to be variable-length coded. Thus obtained variable-length coded data S 26  is supplied to an error correcting outer coding circuit  27 . 
     The error correcting outer coding circuit  27  generates a parity timing from the block number D BL  (FIGS.  7 (A) and  7 (B)) which is in association with the variable-length coded data S 26  as a header information to generate an error correcting outer code. Further, the following track shuffling circuit  28  also generates a shuffle address from the block number D BL  (FIGS.  7 (A) and  7 (B)) which is in association with the variable-length coded data S 26  in order to re-order the data, and sends it to the following error correcting inner coding circuit  29  as track shuffle data S 28 . 
     The error correcting inner coding circuit  29  generates an error correcting inner code, and adds the synchronization pattern SYNC to generate recording data S 12  shown in FIG.  7 (C). The recording data S 12  is recorded on a magnetic tape  19  through the following recording circuit  30  and magnetic head  18 . At this time, in the error correcting inner coding circuit  19 , since the block number D BL  and field information D FI  which are necessary as ID information, are previously added to the data as header information, it is unnecessary to add those again. 
     Further, in the reproducing system, reproduced data S 31  which is reproduced through a reproducing head  31  and reproducing circuit  32  is input to a correcting circuit  33  to be correction-processed by using the error correcting inner code recorded with the recording data, and is output to a de-shuffling circuit  34 . The de-shuffling circuit  34  de-shuffles the reproduced data re-ordered to the sequence corresponding to the track pattern on the magnetic tape into the original sequence, and outputs it to the following correcting circuit  35  as de-shuffle data S 34 . 
     The correcting circuit  35  corrects an error in the manner of burst of the de-shuffle data S 34  and outputs it to the following variable-length decoding circuit  36 . The variable-length decoding circuit  36  obtains variable-length decoded data S 35  from the de-shuffle data S 34  and outputs it to an inverse-quantization circuit  37  to perform inverse-quantization processing. The inverse-quantization circuit  37  outputs thus obtained inverse-quantized data S 37  to an IDCT circuit to perform inverse-transform processing for discrete cosine transformation at the DCT transforming circuit  23  described above. The IDCT circuit outputs thus obtained IDCT data S 38  to the following de-shuffling circuit  39  to re-order the DCT-blocked data in the sequence of scanning, and outputs it as reproducing digital video signal S 39 . 
     In the above configuration, the D-VTR  20  adds the block number D BL  and field number D FI  to the digital video signal S 1  as header information at the DCT shuffling circuit  21 , and further adds the quantization level information D Q  as a header information at the quantization level delay circuit  24 . By using the header information, information necessary for the signal processing can be obtained from only input data at each signal processing circuit, further the information is input at the same timing as the processing data. 
     The header information is used as a timing information at each signal processing circuit, and signal processing is performed in accordance with the timing of the above header information, so that in each signal processing circuit, signal processing can be performed at the securely timing without regard to the processing delay time of signal processing circuits connected to the previous stage or latter stage. Therefore, in each signal processing circuit, a counter circuit for generating timing in respective signal processing, a latch circuit for timing phases by delaying the information, etc. can be omitted. 
     Further, the color field information D FI  is added as a header information, so that the color field information D FI  is delayed with the data at each signal processing circuit and transmitted to the last recording data S 12 . Further, also the quantization level information D Q  detected at the quantization level delay circuit  24  is added to the data as a header information, so that at the quantization circuit  25  of next stage, the quantizing operation can be executed by investigating a quantization level from the header information. 
     In such a manner, new information is added as a header information at the signal processing circuit of halfway, so that the signal connection between complicated circuits such as the conventional D-VTR  1  described above with FIG. 1, in which the quantization level detecting data S 4  is output from the quantization level detecting circuit  6  to the quantization circuit  7  separated from the quantization delay output data S 5 , can be reduced, and transmitting the data to a latter stage of the signal processing circuit without regard to delay time at each signal processing circuit. 
     As the above configuration, when performing signal processing at each signal processing circuit, the timing necessary for respective signal processing is added for the data to be transmitted, as a header information, so that each signal processing circuit can be avoided to be complicated structure such that a circuit for obtaining the timing necessary for the signal processing is added at the respective signal processing circuits. 
     Further, in each signal processing circuit, the signal processing can be performed without generating a timing necessary for the signal processing at the respective signal processing circuits, so that the signal processing circuit can be developed without regard to delay time at each signal processing circuit. Therefore, even if processing time of each signal processing circuit is changed in its development process, the signal processing circuit provided to a latter stage of the above signal processing circuit may not be changed in accordance with the such changed time period, so can be developed more easily. 
     Note that, in the embodiment described above, it has been described the case where the present invention is being applied to a D-VTR. However, the present invention is not only limited to this, but is widely applicable to a signal processing apparatus such that data is transmitted via a plurality of signal processing circuits. 
     INDUSTRIAL APPLICABILITY 
     The present invention is being suitable to apply to a signal processing apparatus, for example, being a recording or reproducing apparatus for digital video tape recorder (DVTR) for discrete cosine transforming video signal in order to compress amount of information thereof and record.