Patent Publication Number: US-7590024-B2

Title: Nonvolatile semiconductor memory device

Description:
RELATED APPLICATIONS 
   This application is based upon and claims the benefit of priority to Korean patent application numbers 10-2005-135236 and 10-2005-135237, filed on Dec. 30, 2005, the entire contents of which are incorporated herein by reference. 
   BACKGROUND 
   The present invention generally relates to a nonvolatile semiconductor memory device, and more specifically, to a semiconductor memory device comprising a three-dimensional cell array to reduce chip size. 
   A nonvolatile ferroelectric memory, for example, a Ferroelectric Random Access Memory (FeRAM) device has attracted considerable attention as a candidate for the next generation memory device, because it has a data processing speed as fast as a Dynamic Random Access Memory (DRAM), and it conserves data even after the power is turned off. 
   An FeRAM having a structure similar to that of a DRAM includes capacitors made of a ferroelectric material, which has a high residual polarization, allowing retention of data after power is turned off. 
   A unit cell of a conventional nonvolatile FeRAM device includes a switching element and a nonvolatile ferroelectric capacitor. The switching element performs a switching operation depending on a state of a word line to connect the nonvolatile ferroelectric capacitor to a sub bit line. The nonvolatile ferroelectric capacitor is connected between a plate line and one terminal of the switching element. Here, the switching element of the conventional FeRAM is a NMOS transistor, whose switching operation is controlled by a gate control signal. 
   In the conventional FeRAM, as the cell size becomes smaller, data retention characteristics are degraded. Thus, it is difficult to perform a normal operation of cells. For example, when a voltage is applied to an adjacent cell in a read mode of the cell, data is destroyed due to an interface noise generated between the cells. Also, when a write voltage is applied to an unselected cell in a write mode of the cell, data of the unselected cells is destroyed, thus not facilitating a random access operation. 
   For Metal Ferroelectric Insulator Silicon (MFIS) and Metal Ferroelectric Metal Insulator Silicon (MFMIS), the data retention characteristics is degraded by depolarization charges. The degradation of data retention characteristics caused by smaller cell size is also a problem for other well-known nonvolatile memory devices such as a phase-change RAM (PRAM) device, a magnetoresistive RAM (MRAM) device, or a resistive RAM (ReRAM) device. 
   SUMMARY 
   Various embodiments consistent with the present invention are directed to providing a nonvolatile semiconductor memory device including a plurality of vertically multi-layered unit block cell arrays, which are arranged in row and column directions to reduce a chip size, and which are divided into banks for the read/write operations to be performed by the banks. 
   According to an embodiment consistent with the present invention, a nonvolatile semiconductor memory device comprises a unit block cell array including a plurality of multi-layered cell arrays each having a plurality of unit cells arranged in row and column directions. A plurality of unit bank cell arrays, each comprising a plurality of unit block cell arrays in a given group, is arranged in directions X, Y, and Z based on a deposition direction of the plurality of cell arrays, so as perform read/write operations individually. 
   According to an embodiment consistent with the present invention, a nonvolatile semiconductor memory device comprises a first cell array including a plurality of unit cells, each being arranged in row and column directions, at least a second cell array, each including a plurality of unit cells, which are arranged in row and column directions, and in a vertical direction relative to the first cell array, a unit block cell array including the first cell array and the second cell array, and a unit bank cell array including at least one of the unit block cell arrays. The unit block cell array includes one selected from the first cell array and the second cell array according to a vertical address. 
   According to an embodiment consistent with the present invention, a nonvolatile semiconductor memory device comprises a unit block cell array including a plurality of vertically multi-layered cell arrays each having a plurality of unit cells arranged in row and column directions, a row address decoder configured to decode a row address to activate a word line of a selected one of the cell arrays, a vertical address decoding unit configured to decode a vertical address to the selected one of the cell arrays and to connect an output signal of the row address decoder to a word line of the selected cell array, and a column address decoder configured to decode a column address to activate a bit line of the selected cell array. 
   According to an embodiment consistent with the present invention, a nonvolatile semiconductor memory device comprises a unit block cell array including a plurality of vertically multi-layered cell arrays, each having a plurality of unit cells arranged in row and column directions, a column address decoder configured to decode a column address to activate a bit line of a selected one of the cell arrays, a vertical address decoding unit configured to decode a vertical address to the selected one of the cell arrays and to connect an output signal of the column address decoder to a bit line of the selected cell array, and a row address decoder configured to decode a row address to activate a word line of the selected cell array. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a diagram illustrating a unit block cell array of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
       FIG. 2  is a diagram illustrating a unit bank cell array of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
       FIG. 3  is a diagram illustrating a plurality of bank cell arrays of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
       FIG. 4  is a diagram illustrating an address decoding unit of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
       FIG. 5  is a diagram illustrating an address decoding unit of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
       FIGS. 6 through 8  are diagrams illustrating the address decoding unit of  FIG. 4 . 
       FIG. 9  is a cross-sectional diagram illustrating a cell array of  FIG. 1 . 
       FIGS. 10 and 11  are cross-sectional diagrams illustrating the cell array of  FIG. 9 . 
       FIG. 12  is a cross-sectional diagram illustrating the unit block cell array of  FIG. 1 . 
       FIG. 13  is a diagram illustrating the cell array of  FIG. 9 . 
   

   DETAILED DESCRIPTION 
   The present invention will be described in detail with reference to the accompanying drawings. 
     FIG. 1  is a diagram illustrating a unit block cell array  100  of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
   Unit block cell array  100  may include a plurality of cell arrays CA 1 ˜CAn, each of which has a two-dimensional plane structure including a row address (X) region arranged in a row direction (axis X) and a column address (Y) region arranged in a column direction (axis Y). 
   Unit block cell array  100  has a three-dimensional structure, where cell arrays CA 1 ˜CAn may be deposited in a vertical direction (axis Z). Unit block cell array  100  may select one of cell arrays CA 1 ˜CAn by a vertical address Z. 
   In cell arrays CA 1 ˜CAn, a row address X selects a word line, and a column address Y selects a bit line. Vertical address Z selects one of cell arrays CA 1 ˜CAn. 
     FIG. 2  is a diagram illustrating a unit bank cell array BCA of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
   As described above, unit block cell array  100  may include a plurality of cell arrays CA 1 ˜CAn, which are deposited in a vertical direction. Unit bank cell array BCA may include a plurality of unit block cell arrays  100 . 
   In one embodiment, cell arrays CA 1 ˜CAn are explained with one unit block cell array  100 , and unit block cell arrays  100  are explained with one unit bank cell array BCA. However, in another embodiment, one unit bank cell array BCA may include a plurality of cell arrays CA 1 ˜CAn formed in the same layer, and a plurality of unit bank cell arrays BCA may be deposited vertically. 
   As shown in  FIG. 3 , a plurality of unit bank cell arrays BCA_ 1 ˜BCA_m+m, which are arranged in row and column directions, are configured to perform read/write operations so as to improve the operation speed. 
   Although a plurality of unit bank cell arrays BCA are arranged in row and column directions in this particular embodiment, a plurality of unit bank cell arrays BCA may be arranged in directions X, Y, and Z based on the deposition direction of cell arrays CA 1 ˜CAn. One unit bank cell array BCA, which includes unit block cell arrays  100  in a given group, is configured to perform read/write operations by unit bank cell array BCA. 
     FIG. 4  is a diagram illustrating an address decoding unit of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
   Address decoding unit may include a row (X) address register  200 , a row address decoder  210 , a vertical (Z) address register  220 , a vertical address decoder  230 , a column (Y) address register  240 , a column address decoder  250 , a bank address register  260 , and a bank address decoder  270 . 
   Row address register  200  may store a row address RADD. Row address decoder  210  may decode an output signal from row address register  200 . Vertical address register  220  may store a vertical address VADD. Vertical address decoder  230  may decode an output signal from vertical address register  220 . 
   Column address register  240  may store a column address CADD. Column address decoder  250  may decode an output signal from column address register  240 . Bank address register  260  may store a bank address BADD. Bank address decoder  270  may decode an output signal from bank address register  260 . 
   Row address register  200 , vertical address register  220 , and column address register  240  may process row address RADD, vertical address VADD, and column address CADD, which may be inputted from separate pads R_PAD, V_PAD, C_PAD. Bank address register  260  may process bank address BADD inputted from each individual pad B_PAD. 
     FIG. 5  is a diagram illustrating an address decoding unit of a nonvolatile semiconductor memory device according to an embodiment consistent with the present invention. 
   In one embodiment, address decoding unit may include an address register  300 , a row address latch  310 , a row address decoder  320 , a vertical address latch  330 , a vertical address decoder  340 , a column address latch  350 , a column address decoder  360 , a bank address register  370 , and a bank address decoder  380 . 
   Address register  300  may store an input address IADD. Row address latch  310  may latch an output signal from address register  300  to a row address. Row address decoder  320  may decode an output signal from row address latch  310 . Vertical address latch  330  may latch an output signal from address register  300  to a vertical address. Vertical address decoder  340  may decode an output signal from vertical address latch  330 . 
   Column address latch  350  may latch an output signal from address register  300  to a column address. Column address decoder  360  may decode an output signal from column address latch  350 . Bank address register  370  may store a bank address BADD. Bank address decoder  380  may decode an output signal from bank address register  370 . 
   Address register  300  may process input address IADD inputted through one common pad I_PAD. Address register  300  may timeshare input address IADD to output row address RADD, vertical address VADD, and column address CADD by a timeshare multiplexing system. 
   That is, row address RADD and vertical address VADD are inputted in the first timesharing, and column address CADD is inputted in the second timesharing. Otherwise, row address RADD is inputted in the first timeslot, and vertical address VADD and column address CADD are inputted in the second timeslot. The bank address register  260  may process bank address BADD inputted from each individual pad B_PAD. 
     FIG. 6  is a diagram illustrating address decoding unit of  FIG. 4  with respect to the row addresses. 
   Address decoding unit with respect to the row addresses may include vertical address decoder  230 , row address decoder  210 , and a row decoding unit  400 . Row decoding unit  400  may include a plurality of switches SW 1 ˜SWn corresponding respectively to word lines WL in cell arrays CA 1 ˜CAn. 
   Vertical address decoder  230  may be configured to select one of cell arrays CA 1 ˜CAn, which are deposited vertically in one unit block cell array  100 . Row address decoder  210  may be configured to select one of word lines WL in one of cell arrays CA 1 ˜CAn selected by vertical address decoder  230 . 
   Switches SW 1 ˜SWn of row decoding unit  400  may be configured to selectively connect a row line ROW selected by an output signal from row address decoder  210  to a word line WL of selected one of cell arrays CA 1 ˜CAn depending on output states of vertical address decoder  230 . 
     FIG. 7  is a diagram illustrating address decoding unit of  FIG. 4  with respect to the column addresses. 
   Address decoding unit with respect to the column addresses may include vertical address decoder  230 , column address decoder  250 , and a column decoding unit  500 . Column decoding unit  500  may include a plurality of switches SW 1 ˜SWn corresponding respectively to bit lines BL in cell arrays CA 1 ˜CAn. 
   Vertical address decoder  230  may be configured to select one of cell arrays CA 1 ˜CAn, which are deposited vertically in unit block cell array  100 . Column address decoder  250  may be configured to select one of bit lines BL in one of cell arrays CA 1 ˜CAn selected by vertical address decoder  230 . 
   Switches SW 1 ˜SWn of column decoding unit  500  may be configured to selectively connect a column line COL selected by an output signal from column address decoder  250  to bit line BL of selected one of cell arrays CA 1 ˜CAn, depending on output of vertical address decoder  230 . 
   As shown in  FIG. 8 , read/write operations may be performed on unit cell C in a region where the word line WL selected by row decoding unit  400  crosses bit line BL selected by column decoding unit  500 . 
     FIG. 9  is a layout cross-sectional diagram illustrating the n-th layer cell array CAn of  FIG. 1 . 
   A plurality of word lines WL may be arranged in parallel with a plurality of bottom word lines BWL in a column direction. A plurality of bit lines BL may be arranged perpendicular to word lines WL. A plurality of unit cells C may be located in a region where word lines WL, bottom word lines BWL, and bit lines BL are crossed. 
     FIG. 10  is a cross-sectional diagram illustrating the nth layer cell array CAn of  FIG. 9  in a direction (A) parallel to word line WL. 
   The nth layer cell array CAn may include a plurality of insulating layers  12  over bottom word lines  10 , and a plurality of P-type channel regions  14  over insulating layers  12 . A plurality of ferroelectric layers  22  may be formed over P-type channel regions  14 . A plurality of word lines  24  may be formed in parallel with bottom word lines  10  over ferroelectric layers  22 . As a result, a plurality of cells C are connected between one word line WL_ 1  and one bottom word line BWL_ 1 . 
     FIG. 11  is a cross-sectional diagram illustrating the n-th layer cell array CAn in a direction (B) perpendicular to word line WL. 
   In the n-th layer cell array CAn, insulating layers  12  may be formed over bottom word lines BWL_ 1 , BWL_ 2 , and BWL_ 3 . A floating channel layer  20  including a P-type drain region  16 , a P-type channel region  14 , and a P-type source region  18  is formed over insulating layer  12 . P-type drain region  16 , P-type channel region  14 , and P-type source region  18  may be connected in series. More specifically, P-type source region  18  and P-type drain region  16  are connected on both sides of P-type channel region  14 . 
   P-type drain region  16  may be used as a source region for an adjacent cell, and P-type source region  18  may be used as a drain region for an adjacent cell. That is, P-type region  16  may be used as a common drain region and as a common source region for the two cells adjacent to P-type region  16 . 
   Drain region  16 , source region  12 , and channel region  14  of floating channel layer  20  may be formed as P-type. A semiconductor of floating channel layer  20  is selected from the group consisting of a carbon nano tube, a silicon, a germanium, and an organic semiconductor. 
   Ferroelectric layer  22  may be formed over channel region  14  of floating channel layer  20 , and word lines WL_ 1 , WL_ 2 , and WL_ 3  are formed over ferroelectric layer  22 . Bottom word line  10  and word line  24  are selectively driven by the same row address decoder (not shown). 
   Data may be read/written using a channel resistance of floating channel layer  20 , which is differentiated depending on a polarization state of ferroelectric layer  22 . That is, when the polarity of ferroelectric layer  22  induces positive (+) charges to channel region  14 , memory cell C becomes at a high resistance state so that a channel is turned “off.” When the polarity of ferroelectric layer  22  induces negative (−) charges to channel region  14 , memory cell C becomes at a low resistance state so that a channel is turned “on.” 
     FIG. 12  is a cross-sectional diagram illustrating unit block cell array  100  of  FIG. 1 . 
   Unit block cell array  100  may include a plurality of multi-layered unit cell arrays CA 1 ˜CAn, as shown in  FIG. 11 , which are separated by cell insulating layers  26 . 
   Although floating channel layer  20  may include P-type drain region  16 , P-type channel region  14 , and P-type source region  18  in one embodiment consistent with the present invention, floating channel layer  20  may include an N-type drain region  16 , an N-type channel region  14 , and an N-type source region  12 , as shown in  FIG. 13 . 
   In one embodiment, the read/write operations of high data of the nonvolatile semiconductor memory device are explained as follows. 
   When writing data “1,” a ground voltage &lt;GND&gt; may be applied to bottom word line  10 , and a negative voltage &lt;−V&gt; may be applied to word line  24 . Drain region  16  and source region  18  may be configured to be at a ground voltage &lt;GND&gt; state. 
   A voltage may be applied between ferroelectric layer  22  and P-type channel region  14  of floating channel layer  20  by voltage distribution of a capacitor between ferroelectric layer  22  and insulating layer  12 . As a result, positive charges may be induced in channel region  14  depending on the polarity of ferroelectric layer  22 , so that memory cell C may have a low resistance state. Thus, data “1” is written in all memory cells C in a write mode. 
   When reading data “1,” ground voltage &lt;GND&gt; or a read voltage &lt;+Vrd&gt; having a positive value may be applied to bottom word line  10 . Ground voltage &lt;GND&gt; may be applied to word line  17 . A depletion layer may be formed in the bottom of channel region  14  by read voltage &lt;+Vrd&gt; applied from bottom word line  10 . 
   A depletion layer may not be formed at the top of channel region  14 , because positive charges may be induced at the top of channel region  14 . Thus, channel region  14  is turned on to conduct current from source region  18  to drain region  16 . As a result, the data “1” stored in memory cell C may be read in a read mode. Even when a slight voltage difference is generated in drain region  16  and source region  18 , channel region  14  is turned on, so that a large amount of current flows. 
   In one embodiment, the read/write operations of low data of the nonvolatile semiconductor memory device are explained as follows. 
   When writing data “0,” a negative voltage &lt;−V&gt; may be applied to bottom word line  10 , and a ground voltage &lt;GND&gt; may be applied to word line  24 . Negative voltage &lt;−V&gt; may be applied to drain region  16  and source region  18 . 
   A high voltage difference is formed between a positive voltage &lt;+V&gt; applied from word line  24  and negative voltage &lt;−V&gt; of channel region  14 . As a result, negative charges are induced in channel region  14  depending on the polarity of ferroelectric layer  22 , so that memory cell C may have a high resistance state. 
   When reading data “0,” ground voltage &lt;GND&gt; or a read voltage &lt;+Vrd&gt; having a positive value may be applied to bottom word line  10 . Ground voltage &lt;GND&gt; may be applied to word line  24 . 
   A depletion layer is formed in the bottom of channel region  14  by read voltage &lt;+Vrd&gt; applied from bottom word line  10 . Negative charges are induced at the top of channel region  14 , so that a depletion layer is formed at the top of channel region  14 . A channel of channel region  14  is turned off by the depletion layers formed in channel region  14 , so that a current path is disconnected between source region  18  and drain region  16 . 
   Even when a slight voltage difference is generated between drain region  16  and source region  18 , channel region  14  is turned off, so that a small amount of current flows. Thus, the data “0” stored in memory cell C may be read in a read mode. 
   The data retention characteristics of memory cells C are improved, because word line  24  and bottom word line  10  are grounded in the read mode without applying a voltage stress to ferroelectric layer  22 . 
   As described above, in a nonvolatile ferroelectric memory device according to an embodiment consistent with the present invention, a Non-Destructive Read Out (NDRO) system may prevent cell data from being destroyed in a read mode. The nonvolatile ferroelectric memory device improves the reliability of the memory cells and the read operation speed in a low voltage operation of a nano-scaled ferroelectric cell. A plurality of ferroelectric unit cell arrays are arranged in row and column directions. Also, the ferroelectric unit cell arrays are deposited vertically to improve integration capacity of the memory cells, thereby reducing the whole size of the nonvolatile ferroelectric memory device. The vertically deposited unit block cell arrays are divided in a bank, and configured to perform read/write operations, thereby improving the operation speed of the memory cells. A vertical (Z) address decoder selects one of the unit block cell arrays to drive the cell arrays effectively, thereby improving the operation speed of the cells. 
   The foregoing embodiments consistent with the present invention has been described for purposes of illustration. It is not intended to be exhaustive, or to limit the invention to the precise form disclosed. It is appreciated that modifications and variations are possible in light of the above teachings, or may be acquired from practice of the invention. Thus, the embodiments were chosen and described in order to explain the principles of the invention and its practical applications to enable one skilled in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. For example, a person of ordinary skill in the art may select one of well-known nonvolatile memory cells, such as a PRAM cell, a MRAM cell, a ReRAM cell, and so forth, instead of the FeRAM cell described in the embodiments.