Patent Publication Number: US-8995204-B2

Title: Circuit devices and methods having adjustable transistor body bias

Description:
TECHNICAL FIELD 
     The present invention relates generally to electronic circuits, and more particularly to circuits having transistors that can be dynamically or statically biased using a body bias voltage. 
     BACKGROUND 
     Integrated circuit (IC) devices (e.g., chips) are typically manufactured with thousands, millions, or even billions of transistors in a single device. Proper operation of such devices can often require precise timing and or performance between various circuit sections. Unfortunately, the operation of such transistors can be subject to uncontrollable variation arising from numerous sources. Variations can arise from the manufacturing process used to fabricate the device, variations in device materials, changes in operating temperature, variations in power supply voltages, or even the age of an IC device, to name but a few. 
     Conventionally, IC devices are designed to try to accommodate such variations, by including extra circuits and/or higher operating voltages. Such approaches can be conceptualized as “overdesigning” a chip; as such approaches could be avoided if transistors had less variation in performance. As device features continue to shrink in size and operate at lower voltages, conventional overdesign techniques may require undesirably large amounts of device area and/or circuit power to achieve a desired circuit performance. 
     All of the above can present formidable limits to achieving faster and more efficient IC devices with conventional transistors and design approaches. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows an integrated circuit (IC) device according to an embodiment. 
         FIG. 2A  shows an IC device having inter-device body bias granularity according to an embodiment.  FIG. 2B  shows an IC device having single device body bias granularity according to an embodiment. 
         FIG. 3  shows a bias control circuit according to an embodiment. 
         FIG. 4  shows emulation circuits according to an embodiment. 
         FIG. 5  shows emulation circuits according to another embodiment. 
         FIG. 6  shows a bias control circuit according to an embodiment. 
         FIGS. 7A to 7C  show evaluation sections according to various embodiments. 
         FIGS. 8A to 8G  are tables showing body bias selection methods according to embodiments. 
         FIG. 9  shows an embodiment that determines NMOS and PMOS skew factors using a plurality of skewed ring oscillators having a predetermined ratio between the NMOS transistor size and the PMOS transistor size. 
         FIGS. 10A and 10B  show a method for determining optimal bias setting according to an embodiment. 
         FIGS. 11A to 11D  describe enhanced body effect (EBE) transistors that can be included in the embodiments. 
         FIG. 12  shows a logic circuit according to an embodiment. 
         FIG. 13  shows a conventional level shifter circuit. 
         FIG. 14  shows a level shifter circuit according to an embodiment. 
         FIG. 15A  shows a level shifter circuit according to another embodiment. 
         FIG. 15B  shows a level shifter circuit according to another embodiment. 
         FIG. 16  shows a response for level shifter circuits according to embodiments. 
         FIGS. 17A to 17C  show logic gates according to embodiments. 
         FIGS. 18A to 18D  show a static random access memory (SRAM) device and sensing circuit according to embodiments. 
         FIGS. 19A to 19C  show bias voltage generators that can be included in the embodiments. 
         FIG. 20  shows a method according to an embodiment. 
         FIG. 21  shows a method according to another embodiment. 
         FIG. 22  shows variation of threshold voltage across the wafer for EBE transistors. 
         FIG. 23  shows a method according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show circuits and related methods for biasing transistors in an integrated device to achieve a desired circuit performance despite variations in manufacturing and/or operating conditions. In particular embodiments, circuits may include enhanced body effect (EBE) transistors having an enhanced body coefficient as compared to conventional transistors, which can deliver highly effective application of body bias voltages. Alternate embodiments can include non-EBE transistors, or a mix of EBE and non-EBE transistors. 
     In the various embodiments below, like items are referred to by the same reference character but with the leading digits corresponding to the figure number. 
     Referring now to  FIG. 1  an integrated circuit (IC) device according to one embodiment is shown in a top plan view, and designated by the general reference character  100 . An IC device  100  may be formed as a “die” having substrate  102  containing the various circuits therein. An IC device  100  may include one or more biased circuit sections and one or more bias control sections.  FIG. 1  identifies four biased circuit sections as  104 - 0  to  104 - 3  and a bias control section as  106 . Any or all of biased circuit sections ( 104 - 0  to  104 - 3 ) can be formed of transistors having bodies that can be biased to a selectable body bias voltage. In very particular embodiments, such transistors can be EBE transistors having an enhanced body coefficient, which are biased by applying a selectable body bias voltage to a screening region of the EBE transistor, as described in more detail below. 
     A bias control section  106  can select which body bias voltage(s) are applied to the various biased circuit sections ( 104 - 0  to  104 - 3 ). A bias control section  106  can include one or more “emulation” circuits (one shown as  108 ) that can include circuit structures corresponding to biased circuit sections ( 104 - 0  to  104 - 3 ). Thus, application of various body bias voltages to such emulation circuits can reflect the effect of such body bias voltages on the biased circuit sections ( 104 - 0  to  104 - 3 ). 
     As will be described in conjunction with embodiments below, such a body bias voltage can be a “reverse” body bias voltage (VBBR) (e.g., the screening region reverse biased with respect to the source—of an EBE transistor) and/or a “forward” body bias voltage (VBBF) (e.g., the screening region forward biased with respect to the source of the EBE transistor). 
     Embodiments can have varying degrees of granularity with respect to body bias application. Particular examples of such variation are shown in  FIG. 2A  and  FIG. 2B . 
     Referring to  FIG. 2A , an IC device  200 -A according to an embodiment is shown in a block schematic diagram. IC device  200 -A shows a “fine” grained body biasing arrangement wherein transistors in different circuit sections of the same IC device can be independently biased by applying different body bias voltages. IC device  200 -A can include biased sections  204 - 0  to  204 - n  and a bias control section  206 -A. Biased sections  204 - 0  to  204 - n  can include circuits connected between high power supply voltage(s) (VDD 0  to VDDn) and low power supply voltages (VSS 0  to VSSn). In some embodiments such high and low power supply voltages can be the same (i.e., VDD 0 =VDDn and/or VSS 0 =VSSn), while in other embodiments such supply voltages can be different between sections. In particular embodiments, all or a portion of the transistors within each biased sections ( 204 - 0  to  204 - n ) can be EBE transistors having screening regions that can be coupled to one or more body bias voltages (VB 0   s  to VBns). 
     A control section  206 -A may include bias select circuits  210 - 0  to  210 - n  and a bias control circuit  212 . In the embodiment of  FIG. 2A , there can be a bias select circuit ( 210 - 0  to  210 - n ) corresponding to each biased section ( 204 - 0  to  204 - n ). Each bias select circuit ( 210 - 0  to  210 - n ) can receive a set of bias voltages (VBxS), and selectively connect one or more of the bias voltages to the corresponding biased section ( 204 - 0  to  204 - n ) based on selection values (VBx_SEL) generated from bias control circuit  212 . Bias control circuit  212  can generate selection values (VBx_SEL) based on the performance of one or more emulation circuits (not shown) as described above and in other embodiments herein. 
     Referring to  FIG. 2B , an IC device  200 -B according to another embodiment is shown in a block schematic diagram. IC device  200 -B shows a “medium” grained body biasing arrangement in which all, or substantially, all biased sections ( 204 - 0  to  204 - n ) receive the same body bias voltage(s). Biased sections  204 - 0  to  204 - n  can all be connected between a same high power supply voltage (VDD) and low power supply voltages (VSS). Some or all of biased sections ( 204 - 0  to  204 - n ) can also include EBE transistors having screening regions that can be coupled to one or more body bias voltages (VBs). 
     A control section  206 -B may include a bias select circuit  210  and a bias control circuit  212 . Bias select circuit  210  can receive a set of bias voltages (VBxS) and selectively connect one or more of the bias voltages to biased section  204  based on selection values (VBx_SEL) generated from bias control circuit  212 . Bias control circuit  212  can have the same structure as that shown in  FIG. 2A , or an equivalent. 
     Referring now to  FIG. 3 , a bias control circuit  312  according to one particular embodiment is shown in a block schematic diagram. Bias control circuit  312  can be included in embodiments shown herein. 
     A bias control circuit  312  can include emulation circuits  314 , an evaluation section  316 , and a bias voltage generator  318 . Emulation circuits  314  can include circuits having structures like those of biased sections on a same IC device, including EBE transistors having screening regions that may be coupled to a body bias voltage selected by an evaluation section  316 . Transistors within emulation circuits  314  can receive body bias voltages (VBxS), and in response to such biases (and optionally other signals, such as input signals), generate performance values Perf 0  to PerfM. Preferably, performance values (Perf 0  to PerfM) can be digital values. Accordingly, as different body bias voltages (VBxS) are applied to the emulation circuits  314 , different sets of performance values (Perf 0  to PerfM) can be generated. 
     Evaluation section  316  can receive sets of performance values (Perf 0  to PerfM) corresponding to different body bias conditions, and from such sets arrive at bias voltage selection values (VBx_SEL) that can be used to select body bias voltage(s) for application to other biased circuit section(s) of the same device. In the embodiment shown, evaluation section  316  may also generate emulator selection signals (EMU_SEL) for selecting body bias voltages for application to emulation circuits  314 . 
     Bias voltage generator  318  may generate a number of bias voltages and provide a selected number of such voltages (VBxS) to emulation circuits  314  in response to selection signals (EMU_SEL). In one embodiment, the emulation circuits  314  can generate multiple sets of performance values that are stored in the evaluation section  316 , where each set of performance values corresponds to the selected number of bias voltages (VBxS) provided by the bias generator in response to a particular emulator selection signal (EMU_SEL). 
     Referring to  FIG. 4 , emulation circuits  418  that can be included in the embodiments are shown in a block schematic diagram. Emulation circuits  418  can include a number of ring oscillators  420 - 0  to  420 -M, each of which can receive one or more body bias voltages VB 0   s  to VBMs. Ring oscillators ( 420 - 0  to  420 -M) can include circuit structures corresponding to other biased circuit sections of an IC. The frequency at which a ring oscillator ( 420 - 0  to  420 -M) oscillates can correspond to a speed of the circuits contained therein, as such circuits receive particular body bias voltages. Consequently, the frequency of a ring oscillator ( 420 - 0  to  420 -M) can represent a speed response of the corresponding biased circuit section in the IC. 
     In the particular embodiment shown, emulation circuits  418  can provide a count value (count 0  to countM) corresponding to each ring oscillator ( 420 - 0  to  420 -M). A count value (count 0  to countM) can represent a number of oscillation cycles within a set period of time, and hence represent the oscillation speed of an oscillator and thus the propagation delay of the constituent circuits. 
     Referring to  FIG. 5 , a further example of emulation circuits  518  that can be included in the embodiments is shown in a block schematic diagram. Emulation circuits  518  can include ring oscillators  520 - 0  to  520 -M and a counter section  522 . Each ring oscillator ( 520 - 0  to  520 -M) can generate a periodic signal (OSC_OUT 0  to OSC_OUTM) having a frequency that varies according to the construction of the ring oscillator, as well as the body bias applied. Ring oscillators ( 520 - 0  to  520 -M) can include stages (some shown as  524 - 0  to  524 - k ). Each stage ( 524 - 0  to  524 - k ) can include transistors connected to one another in a fashion that emulates biased circuit sections in the same IC. Stages ( 524 - 0  to  524 - k ) can be identical replicas of existing circuits, or may be representative of critical timing paths within an IC. As but a few examples, stages ( 524 - 0  to  524 - k ) can include a mixture of logic gate type (e.g., inverters, NAND gates, NOR gates, more complex gates) and/or can include dynamic circuits, as well as metal interconnects on different metal layers to evaluate the as-processed RC delay impact on IC critical timing paths. 
     In addition, as will be described in more detail below, stages ( 524 - 0  to  524 - k ) may also include “skewed” circuits. Skewed circuits can include transistor sizings and/or construction purposely introduced to derive other features of a circuit. As but one example, stages ( 524 - 0  to  524 - k ) may be skewed to provide slower speeds when a bias condition increases leakage. In the embodiment shown, each ring oscillator ( 520 - 0  to  520 -M) can be reset and/or disabled by control signals ENS. 
     A counter section  522  may include one or more counter circuits (one shown as  526 ) that may increment and/or decrement a count value in response to an output from a ring oscillator (OSC_OUT 0  to OSC_OUTM). Such a count value can be reset by a signal RESET. In some embodiments, a counter circuit  526  can be provided for each ring oscillator ( 520 - 0  to  520 -M). In other embodiments a counter circuit can be shared among multiple (including all) ring oscillators ( 520 - 0  to  520 -M). 
     Referring to  FIG. 6 , a bias control circuit  612  according to a particular embodiment is shown in a block schematic diagram. A bias control circuit  612  may include emulation circuits  614  and an evaluation section  616 . Emulation circuits  614  may include ring oscillators  620 - 0  to  620 -M as described above, and equivalents. In the embodiment shown, emulation circuits  614  may further include a bias voltage multiplexer (MUX)  628  and an oscillator MUX  630 . Bias voltage MUX  628  can provide any of a number of bias voltages VBB 0  to VBBN to ring oscillators ( 620 - 0  to  620 -M) in response to bias select signals VB SEL. Oscillator MUX  630  can provide outputs from any of ring oscillators ( 620 - 0  to  620 -M) to counter circuit  626  in response to oscillator select signals OSC SEL. 
     Evaluation section  616  may include a counter de-MUX  632  and a count store  634 . A counter de-MUX  632  can selectively apply count values from counter circuit  626  to storage locations within count store  634 . A count store  634  may store count values generated by emulation circuits  614  for evaluation and/or modification to arrive at selection values that determine which body bias voltages are applied to biased sections within the IC. In the very particular embodiment of  FIG. 6 , a count store  634  may include a number of storage registers for storing multi-bit count values. Storage locations within count store  634  can be accessed via a store interface (I/F)  636 . In one very particular embodiment, a store I/F  636  may include an address input and data input/output (I/O). In an alternative embodiment, the count store  634  can be part of SRAM on the IC. In other embodiments, the store I/F  636  can be a memory interface, and the count store  634  can be accessed using memory mapped I/O or direct memory interfaces (DMA). 
     Evaluation sections, according to embodiments shown herein, can receive performance values from emulation circuits biased using a number of body bias voltages, and select one or more body bias voltages for application to the transistors in a biased section of an IC. In certain embodiments, an evaluation section can select body bias voltages that provide one or more predetermined performance criteria when applied to the biased section of an IC. Such performance criteria can include speed and leakage current. In certain alternative embodiments, the performance values can include the impact of variations in resistance and capacitance of signal routing layers, and the evaluation section can select body bias voltages that provide one or more predetermined performance criteria in presence of such as-fabricated variations. In certain embodiments, the emulation circuits can use metal limited paths to emulate the resistance and capacitance of signal routing layers as fabricated in the IC, and generate performance values that include the impact of the signal routing layers on the speed of biased circuit sections of the IC. For example, emulation circuits can emulate the impact of variations in the resistance of the signal routing layer resulting from etch rates and lithography, and variations in the capacitance of the signal routing layer resulting from as-fabricated differences in line spacing both horizontally (intra-layer) and vertically (inter-layer), lithography, etch rates, and polish rates. Embodiments of evaluation sections can select body bias voltages that provide a biased section having speed and/or leakage current that are within a specified range. 
     In certain alternative embodiments, evaluation sections select body bias voltages that provide a biased section having a speed that is greater than a specified minimum speed and the lowest leakage current that can be obtained for that minimum speed. In certain embodiments, the evaluation sections can select a first body bias voltage for biasing the NMOS transistors and a second body bias voltage for biasing the PMOS transistors in the biased section. In certain alternative embodiments, the evaluation sections can select different body bias voltages for biasing the NMOS and PMOS transistors in the biased section. Evaluation sections may take various forms, a few of which are described below. 
     Referring now to  FIGS. 7A to 7C , evaluation sections that can be included in the embodiments are shown in block schematic diagrams. Such evaluation circuits are provided as examples of possible embodiments, and various equivalents would be understood by those skilled in the art. 
     Referring to  FIG. 7A , an evaluation section  716 -A may include a value store  734 , custom or ASIC logic circuits  738 , and evaluation data  740 . A value store  734  may store performance values from emulation circuits operating under different body bias voltages. 
     In particular embodiments, a value store  734  may store digital count values corresponding to oscillator speeds. Such count values may be raw, or weighted, as will be described in more detail herein. 
     Logic circuits  738  can compare performance values to evaluation data contained in an evaluation store  740 . Such evaluation data may include limits to which performance data values are compared. Utilizing such evaluation data, logic circuits  738  can derive selection values VBxSEL. Custom circuits  738  can also receive operating conditions (OP COND), and further derive body bias values from such input values. Operating conditions can include temperature and/or actual supply voltage received, as but two examples. It is understood that the logic circuits can include comparators and/or suitable state machines to derive selection values. Particular approaches to generating such values will be described in more detail below. 
     In particular embodiments, the logic circuits  738  can include a look-up table that can be used to generate the selection values from the performance values and the operating conditions. 
     Referring to  FIG. 7B , an evaluation section  716 -B according to another embodiment may include a register set  744 , a processor  742 , and a memory system  764 . A register set  744  may include a number of registers accessible by a processor through an I/O I/F  760 . A register set  744  may encompass a value store  734 , with a subset of the registers storing performance data for evaluation. A register set  744  may also include one or more control registers  754  that can store selection values (VBxSEL) which may determine body bias voltages applied to circuit sections on the device. 
     As noted above, a processor  742  may access register set  744  via I/O I/F  760 . In addition, a processor  742  may access memory system  764  via a memory I/F  762 . A memory system  764  may store evaluation data  740  as well as instruction data  748 . A processor  742  may execute instructions included in instruction data memory  748 , and using evaluation data  740 , to generate selection values VBxSEL. Selection values VBxSEL can then be written to a control register  754 , to thereby control which body bias voltages are applied to a biased circuit section. A processor  742  can also receive operating conditions (OP COND), as described above, and further modify selection values VBxSEL in response to such conditions or changes in such conditions. In alternative embodiments, the registers  734  can be memory-mapped, i.e., specific reserved memory addresses can be assigned to the registers  734 , and the processor  742  can access the registers  734  using the memory interface  762 . 
     In the particular embodiment shown, a memory system  764  may include nonvolatile memory  750  and volatile memory  752  for use by processor. Evaluation data  740  and instruction data can be stored in nonvolatile memory  750  or alternatively in RAM  752 . 
     Referring to  FIG. 7C , an evaluation section  716 -C according to a further embodiment may include a register set  744 , an IC interface  756 , and an IC tester  758 . A register set  744  can take the form of that shown in  FIG. 7B , or an equivalent. An IC interface  756  may be an interface that enables electrical communication with an IC containing register set  744 . In some embodiments, an IC interface  756  may be a package interface such as a socket for receiving a packaged IC, or a test (e.g., JTAG) interface. However, in other embodiments an IC interface  756  may be compatible with the IC in wafer or die form, including a “probe card”, as but one example. 
     A tester  758  may access register set  744  via IC interface  756 . In addition, a tester  758  may store evaluation data  740  as well as instruction data  748 . It is noted that in alternate embodiments, a tester  758  may not necessarily read data values from registers to derive performance data. As but one example, a tester  758  could do any of the following: apply different back bias voltages directly to emulation circuits and/or read performance data directly (in analog or digital form). In addition, a tester  758  may also select bias voltage values in response to additional criteria such as operating temperature of the device and/or testing environment. 
     While embodiments above have shown evaluation sections that generate selection values (VBxSEL) and/or store such values in a register, alternate embodiments may store selection values (VBxSEL) in non-volatile form, including but not limited to: the setting of fusible links, anti-fuse structures and/or the programming of nonvolatile memory cells. 
     It is also noted that depending upon known variation among fabricated devices, a derived body bias setting from a sample set could be programmed into a larger production set. As but one example, body bias settings could be common for die in like areas of a wafer, in a same wafer lot, or a same production run, as but a few examples. In certain embodiments, the body bias voltages can be selected during wafer testing, when the wafer characteristics are measured across sites on the wafers, and a wafer mean value or a weighted value based on the wafer mean value can be used to select the body bias voltages for all the dies on the wafer. In alternative embodiments, the body bias voltages for a particular die on the wafer can be selected based on measurements obtained from wafer sites near the die. 
     As noted above, performance values from emulation circuits can be utilized to derive bias voltages for corresponding circuit sections on the same IC. One very particular approach to selecting body bias voltages that meet a minimum speed requirement, while exhibiting low leakage current, will now be described. 
       FIG. 8A  is an example of a table of performance values  859  derived from ring oscillator count values generated using one or more ring oscillators having stages formed with CMOS inverters. In this example, each performance value was derived from a ring oscillator count value that was obtained from a ring oscillator biased using the NMOS reverse bias voltage (nmos VBBR) and the PMOS reverse bias voltage (pmos VBBR) listed in the table. The performance values shown in  FIG. 8A  were obtained by subtracting a count value representing a predetermined minimum speed from each ring oscillator count value, and therefore, negative performance values correspond to bias points that do not satisfy the predetermined minimum speed. It is understood the p-channel reverse body bias values (pmos VBBR) can be voltages greater than a high power supply voltage (e.g., VDD). Similarly, n-channel reverse body bias values (nmos VBBR) can be voltages less than a low power supply voltage (e.g., VSS). The body bias voltages shown in  FIG. 8A  (e.g., 0 to 0.5) are provided as examples of possible body bias voltages. In certain embodiments, the table of performance values can be generated using NMOS and PMOS body bias voltages that are different from the values shown in  FIG. 8A . In alternative embodiments, the table of performance values can be sparsely populated, i.e., the table can have performance values for only certain combinations of NMOS and PMOS body bias voltages. 
     In  FIG. 8A , the noted count values  860  (i.e., positive count values) represent bias conditions that meet the predetermined minimum speed requirement (i.e., negative values represent too slow a response). 
     As noted above, in the embodiment shown, body bias voltage values can be selected not only to meet a predetermined minimum speed requirement, but also selected to provide the lowest leakage current when operating at the predetermined minimum speed. In certain alternative embodiments, body bias voltage values are selected to provide a predetermined leakage current when operating at the predetermined minimum speed. In some embodiments, actual current leakage values can be measured for each body bias voltage combination, and the body bias voltages are selected to provide the lowest leakage current case that still meets the predetermined minimum speed. Alternative embodiments use a leakage reduction table to determine the body bias voltages that provide the lowest leakage current while meeting the predetermined minimum speed, as described below. 
       FIG. 8B  shows an example of a leakage reduction table  861  in accordance with one embodiment. The leakage reduction table  861  provides leakage reduction coefficients for various combinations of NMOS and PMOS reverse body bias voltages, as illustrated in  FIG. 8B . The leakage reduction coefficients shown in table  861  are obtained from leakage current values normalized to a no reverse body bias case (i.e., nmos VBBR=pmos VBBR=0 V) as a result of subtracting the leakage current for the reverse body bias case from the leakage current for each bias point in the table. The leakage current values used to obtain table  861  are obtained from simulations performed at nominal process conditions. However, in alternative embodiments the leakage current reduction coefficients can be obtained from measuring the leakage current or derived from equations that provide the dependence of the leakage current on the NMOS and PMOS bias voltages. It can be observed from  FIG. 8B  that increasing the NMOS and PMOS reverse bias voltage results in increased absolute values of leakage reduction coefficients, and therefore an improvement in leakage current reduction.  FIG. 8B  shows how the “frontier” cases can represent points of interest. Frontier cases are shown as  862  and represent bias conditions that exist next to those that are too slow (not in the set  860  shown in  FIG. 8A ). In the particular embodiment of  FIG. 8B , the bias conditions [nmos VBBR=0.2V; pmos VBBR=0.4V for a leakage reduction coefficient having an absolute value of 0.87], annotated by a circle in  FIG. 8B , provides a lowest leakage current case that also meets the minimum speed criterion. From the data shown, other bias conditions also provide a low leakage current that is within a certain range of the lowest leakage current, and meets the minimum speed criterion [nmos VBBR=pmos VBBR=0.3V for a leakage reduction coefficient having an absolute value of 0.84; and nmos VBBR=0.1, pmos VBBR=0.5, for for a leakage reduction coefficient having an absolute value of 0.85]. 
       FIG. 8C  shows an example of a leakage reduction table  863  in accordance with one embodiment. The leakage reduction table  863  corresponds to skewed process conditions having a slow PMOS and fast NMOS process. The leakage reduction coefficients in table  863  are obtained from leakage current values for simulations performed at the slow P-fast N process corner. It can be observed from  FIG. 8C  that for the process corner corresponding to table  863 , increasing the NMOS reverse bias voltage results in a larger increase in the absolute value of the leakage reduction coefficients as compared to the increases obtained from increasing the PMOS reverse bias voltage. Therefore, for the process corner corresponding to table  863 , increasing the NMOS reverse bias voltage results in a greater improvement in leakage current as compared to the improvement in leakage current that is obtained from increasing the PMOS reverse bias voltage. The frontier cases  864  for this process corner are obtained from a performance value table (not shown) corresponding to the slow P-fast NMOS corner. For the embodiment shown in  FIG. 8C , there are two bias conditions that provide the lowest leakage current and meet the predetermined minimum speed [nmos VBBR=pmos VBBR=0.3 for an absolute leakage reduction coefficient of 0.85; and nmos VBBR=0.4, pmos VBBR=0.2 for an absolute leakage reduction coefficient of 0.85]. These bias points are annotated with circles in  FIG. 8C . The frontier cases  864  are obtained from a performance value table analogous to the table  859  of  FIG. 8A , where the frontier cases  864  can be obtained from emulation circuits  418  for the slowP-fastN skew condition. 
     As noted above, in some embodiments the leakage reduction coefficients in the leakage reduction table can be obtained from either measurements or simulations that provide the current leakage values for each of the (or the selected) body bias cases in the table. However, in other embodiments, the leakage reduction coefficients in the table are obtained from equations that provide bias points that can be weighted based on expected leakage contribution of each device type (i.e., NMOS/PMOS) for each of the (or the selected) body bias cases in the table. In particular, the leakage reduction coefficients can be obtained based on an inverse square root relationship dependence of the leakage current with respect to the applied reverse body bias voltage.  FIGS. 8D ,  8 F, and  8 G show examples of leakage reduction tables obtained from equations relating the leakage current to the reverse body bias voltages, and associated embodiments for selecting the reverse body bias voltages that provide the lowest leakage current and meet a predetermined minimum speed. 
       FIG. 8D  shows an example of a leakage reduction table  865  in accordance with one embodiment. The leakage reduction table  865  corresponds to typical process conditions having a typical PMOS and typical NMOS process. The leakage reduction coefficients in table  865  are obtained from equations that assume equal contributions to the leakage current for the PMOS and NMOS transistors. It can be observed from  FIG. 8D  that the PMOS and NMOS reverse bias voltages result in a substantially comparable increase in the absolute values of the leakage reduction coefficients. The frontier cases  866  for this process corner are obtained from the performance value table  859 , and represent bias conditions that exist next to those that are too slow (not in the set  860  shown in  FIG. 8A ). In the embodiment shown in  FIG. 8D , the bias condition that provides the lowest leakage current and meets the predetermined minimum speed is [nmos VBBR=pmos VBBR=0.3 for an absolute leakage reduction coefficient of 1.10]. This bias condition is annotated with a circle in  FIG. 8D . 
       FIG. 8E  shows an example of a leakage reduction table  867  in accordance with one embodiment. The leakage reduction table  867  corresponds to a skewed process with fastP-slowN process conditions having a fast PMOS and slow NMOS. The leakage reduction coefficients in table  867  are obtained from simulations performed at the fast-slow process corner. It can be observed from  FIG. 8E  that the PMOS reverse bias voltage has a stronger effect on the leakage reduction coefficient than the NMOS reverse bias voltage, i.e., the increasing the PMOS reverse bias voltage provides a greater improvement in leakage current as compared to the improvement obtained from increasing the NMOS reverse bias voltage. The frontier cases  868  for this process corner are obtained from a performance value table (not shown) for the fast-slow process corner. In the embodiment shown in  FIG. 8E , the bias condition that provides the lowest leakage current and meets the predetermined minimum speed is [nmos VBBR=0.2, pmos VBBR=0.5 for an absolute leakage reduction coefficient of 0.93]. This bias point is annotated with a circle in  FIG. 8E . 
       FIG. 8F  shows an example of a leakage reduction weighting table  869  in accordance with one embodiment. The leakage reduction table  869  corresponds to a skewed process with fastP-slowN process conditions having a fast PMOS and slow NMOS. The leakage reduction coefficients in table  869  are obtained from equations that assume a greater contribution to leakage current from the PMOS transistors as compared to that from the NMOS transistors. In particular, the leakage reduction coefficients in table  869  are obtained from those in table  867  by weighting the effect of the PMOS reverse bias voltage up by 40% and by weighting the effect of the NMOS reverse bias voltage down by 40%. It can be observed from  FIG. 8F  that the PMOS reverse bias voltage has a stronger effect on the leakage reduction coefficient than the NMOS reverse bias voltage, i.e., the increasing the PMOS reverse bias voltage provides a greater improvement in leakage current as compared to the improvement obtained from increasing the NMOS reverse bias voltage. The frontier cases  870  for this process corner are obtained from a performance value table (not shown) corresponding to the fastP-slowN process corner. In the embodiment shown in  FIG. 8F , the bias condition that provides the lowest leakage current and meets the predetermined minimum speed is [nmos VBBR=0.2, pmos VBBR=0.5 for an absolute leakage reduction coefficient of 1.18]. This bias condition is annotated with a circle in  FIG. 8F . 
       FIG. 8G  shows an example of a leakage reduction weighting table  871  in accordance with one embodiment. The leakage reduction table  871  corresponds to a skewed process with slowP-fastN process conditions having a slow PMOS and fast NMOS. The leakage reduction coefficients in table  871  are obtained from equations that assume a greater contribution to leakage current from the NMOS transistors as compared to that from the PMOS transistors. In particular, the leakage reduction coefficients in table  871  are obtained from those in table  867  by weighting the effect of the PMOS reverse bias voltage down by 40% and by weighting the effect of the NMOS reverse bias voltage up by 40%. It can be observed from  FIG. 8G  that the NMOS reverse bias voltage has a stronger effect on the leakage reduction coefficient than the PMOS reverse bias voltage, i.e., the increasing the NMOS reverse bias voltage provides a greater improvement in leakage current as compared to the improvement obtained from increasing the PMOS reverse bias voltage. The frontier cases  872  for this process corner are obtained from a performance value table (not shown) corresponding to the slowP-fastN process corner. In the embodiment shown in  FIG. 8G , the bias condition that provides the lowest leakage current and meets the predetermined minimum speed is [nmos VBBR=0.4, pmos VBBR=0.2 for an absolute leakage reduction coefficient of 1.10]. This bias condition is annotated with a circle in  FIG. 8G . 
     As illustrated by the embodiments discussed above, the PMOS and NMOS transistors can make an unequal contribution to the leakage current at different process corners, and therefore, the leakage reduction coefficients can have a stronger dependence on either the PMOS reverse bias voltage or the NMOS reverse bias voltage in accordance with the process skew. For the embodiment shown in  FIG. 8F  PMOS is skewed up by a skew factor of 40% and NMOS is skewed down by a skew factor of 40%. For the embodiment shown in  FIG. 8G , PMOS is skewed down by a skew factor of 40%, and NMOS is skewed up by a skew factor of 40%. One of skill in the art would understand, that NMOS and PMOS skew factors other than 40% can be used to determine the leakage reduction coefficients in the table. In certain embodiments, the performance value weights can be adjusted based on the relative NMOS and/or PMOS transistor content (e.g., total transistor width) in a particular IC. In alternative embodiments, the performance value weights can also be adjusted based on differences in leakage current attributable to stack effects, i.e., stacked transistors (such as stacked PMOS transistors in NOR or stacked NMOS transistors in NAND gates) as they occur in the design and affect the overall leakage current of the IC. 
     As noted above, performance values can be weighted. In particular, performance values can be weighted to favor leakage control when one type of device (i.e., NMOS or PMOS) dominates due to the as-fabricated NMOS to PMOS skew of the IC. In embodiments having ring oscillators, weighted values can be extracted by purposely designing transistor size (channel width/length (Z)) ratios. The effect of each device can then be derived with linear algebra. A very particular example is shown in  FIG. 9 . 
       FIG. 9  illustrates an embodiment that determines the NMOS and PMOS skew factors using a plurality of skewed ring oscillators, where each ring oscillator consists of inverters having a predetermined ratio of the PMOS transistor size to the NMOS transistor size.  FIG. 9  shows three differently skewed inverters  974 ,  976  and  978  having corresponding delays d 1 , d 2  and d 3 , respectively. The delay d 1  can be determined from a ring oscillator that uses inverter  974 . Similarly, delays d 2  and d 3  can be determined from ring oscillators that use inverters  976  and  978 , respectively. Sizing of transistors corresponds to the delay contribution of the transistor, as shown in equations Eq. 1 to Eq. 3. The resulting relationships, shown in equations Eq. 4 and Eq. 5 can be solved to derive the delay contribution of the PMOS and NMOS transistors, and therefore the PMOS and NMOS skew factor.  FIG. 9  shows but one example at determining device contribution. 
     The PMOS and NMOS skew factors can determine the leakage reduction coefficients for a particular process skew. In certain embodiments the PMOS and NMOS skew factors are used to calculate the leakage reduction table corresponding to the process skew by using the NMOS and PMOS skew factors to weight the leakage reduction table obtained for a typical-typical process corner (as illustrated by the embodiments illustrated in  FIGS. 8F and 8G ). The leakage reduction table for the typical-typical process corner can be obtained from measurements, simulations, or equations that provide the NMOS and PMOS leakage current contributions at the typical-typical process corner. In certain alternative embodiments, the leakage reduction table corresponding to the skewed process is obtained from applying the NMOS and PMOS skew factors to a leakage reduction table for a predetermined process skew. The leakage reduction table for the predetermined process skew can be obtained from measurements, simulations, or equations that provide the NMOS and PMOS leakage current contributions at the predetermined process skew. 
     In certain other embodiments, a number of leakage reduction tables can be available, where each leakage reduction table corresponds to a process skew. In this embodiment, the leakage reduction table used to select the bias voltages can be determined by interpolating between the available leakage reduction tables based on the NMOS and PMOS skew factors. 
     Referring to  FIGS. 10A and 10B , a method for arriving at an optimal bias value according to one embodiment is shown.  FIG. 10A  is a flow diagram of the method  1080 .  FIG. 10B  represents data values usable by the method, and shows bias setting of a data array by coordinate values. The method assumes operation on a set of leakage reduction coefficients like those of  FIG. 8F  or  8 G. 
     A method  1080  can include starting at one corner of the data array ( 1082 ), which can be the upper right corner (data point 5, 0). If a performance feature (in this example speed) is not satisfactory at this point (N from  1084 ), the method can decrease a pmos VBBR  1086  and return to  1084 . If a performance feature is satisfactory (Y from  1084 ), the method can determine if a maximum value nmos VBBR has been reached ( 1088 ). In one embodiment, a set of performance values like those in  FIG. 8A  can be used to determine if the performance feature is satisfactory in step  1084 . If a maximum value nmos VBBR has been reached (Y from  1088 ), method  1080  can be complete ( 1090 ) and the current data point can correspond to the selected bias values to be applied to the operational circuits on the IC. However, if a maximum value nmos VBBR has not been reached (N from  1088 ), the method can increase an nmos VBBR ( 1092 ). An absolute leakage reduction coefficient at a current position can then be compared to a previous absolute leakage reduction coefficient ( 1094 ). If a leakage reduction coefficient has not increased (N from  1094 ), method  1080  can be complete ( 1090 ) and the previous data point can correspond to the selected bias values. However, if a leakage reduction coefficient has increased (Y from  1094 ), the method can return to  1084 . 
     While the above embodiments have shown selection of reverse body bias voltages to arrive at an optimal speed and leakage case, other embodiments may include different types of biasing for different features. As but one example, forward body biases can be applied to arrive at some optimized set. In embodiments using forward body bias voltages, the performance value tables and the leakage reduction tables discussed in the embodiments above can be extended to negative VBBR values to select forward body bias voltages to be applied to biased sections of the IC. 
     In this way, a performance value (in this case oscillator speed) can be weighed by known responses (in this case current leakage), to arrive at an optimal body bias selection for both features (speed and leakage). 
     The various embodiments shown herein can include n-channel EBE transistors, and/or p-channel EBE transistors, as well as conventional transistors. N-channel EBE transistors will be represented in this disclosure by the symbol shown as  1196 - 0  in  FIG. 11A , and p-channel EBE transistors will be represented in this disclosure by the symbol shown as  1196 - 1  in  FIG. 11A . 
     Referring now to  FIG. 11B , one exemplary representation of an EBE transistor is shown in a side cross sectional view, and designated by the general reference character  1196 . EBE transistor  1196  is formed on a substrate  1101  and includes a gate  1198 , source and drain regions  1113 , and a gate insulator  1103  positioned over a channel  1105 . The channel  1105  is positioned above a highly doped screening region  1107 . The screening region  1107  can be formed below channel region  1105 . It is understood that certain embodiments of the EBE transistor can include other optional layers that are positioned between channel region  1105  and screening region  1107  (e.g., a threshold voltage set region  1109 ). In certain embodiments the substrate  1101  may be formed of more than one semiconductor layer. As but one example, a substrate may include one or more “epitaxial” layers formed on a bulk semiconductor substrate. 
     A screening layer  1107  may be doped to an opposite conductivity type of the transistor channel type (e.g., an n-channel EBE transistor will have a p-doped screening layer). The screening layer  1107  doping concentration may be greater than a concentration of a body region  1111  to which screening layer  1107  is coupled. In certain embodiments the screening layer  1107  can be adjacent to a well having the same dopant type as the screening layer  1107 . In certain embodiments, dopant concentration profile of the screening layer  1107  is the result of using a method in which the objective is to form a substantially uniform dopant concentration profile laterally across the channel. Such methods can include doped epitaxial growth, precision ion implantation, atomic layer deposition or other methods, as will be understood by persons skilled in the art.  FIG. 11B  also shows source and drain regions  1113  on opposing lateral sides of channel region  1105 . Source and drain regions  1113  may include a source and drain diffusion. More particular types of EBE source and drain structures, relative to the channel region  1105  will be described in more detail below. 
     As described above, certain embodiments of the EBE transistor can optionally also include a threshold voltage set region  1109  with a dopant concentration less than the screening region  1107 , positioned between the gate dielectric  1103  and the screening region  1107 . The threshold voltage set region permits small adjustments in operational threshold voltage of the EBE transistor  1196  and can be formed by out diffusion from the screen layer, in-situ or delta doping during epitaxial growth, or with tightly controlled implants. In particular, that portion of the channel adjacent to the gate should remain undoped. In still other embodiments, in-situ epitaxial growth, screen layer out-diffusion, or other dopant positioning method can be used to place a significant amount of dopants throughout the channel, including doping a portion of the channel adjacent to the gate. Such slightly doped channel transistors can provide better matching to conventional or legacy transistors, which can be advantageous when interfacing with various transistor types or limiting required circuit redesign when substituting improved transistors as disclosed for conventional transistors. 
     Referring now to  FIG. 11C , an EBE transistor according to another particular embodiment is shown in a side cross sectional view. The EBE transistor  1196 ′ may include a gate  1198 ′ separated from a substrate  1101  by a gate insulator  1103 . A gate  1198 ′ may include insulating sidewalls  1115  formed on its sides. Source and drain regions may include lightly doped drain (LDD) structures  1113 ′ formed over deep source/drain diffusions  1119  to extend towards each other under a portion of the gate. An EBE stacked channel structure may be formed by a low-doped or substantially undoped channel region  1105 ′ preferably formed using epitaxial growth, a threshold voltage (Vt) set layer  1109 ′ formed by epitaxial growth and implant, or alternatively, by controlled out-diffusion from a screening layer  1107 ′ positioned below the undoped channel region  1105 ′. The screening layer  1107 ′ acts to define termination of the depletion zone below the gate, while the Vt set layer  1109 ′ adjusts Vt to meet transistor design specifications. In the embodiment shown, screening layer  1107 ′ may be implanted into body/bulk region  1101  so that it extends between and in contact with the source and drain diffusions  1119 . 
     An EBE transistor according to a further embodiment is shown in  FIG. 11D , and designated by the general reference character  1196 ″. An EBE transistor  1196 ″ may include items like those shown in  FIG. 11C , and like items are referred to by the same reference character. EBE transistor  1196 ″ differs from that of  FIG. 11C  in that screening layer  1109 ″ may be implanted into body/bulk region  1101  so that it extends below the gate without contacting the source and drain diffusions  1119 . 
     The above EBE transistors are but particular implementations of an EBE transistor, and should not construed as unduly limiting the circuit elements included within the various analog or digital circuit embodiments shown herein. 
     In certain embodiments, the EBE transistor can be a N-channel transistor having a source and a drain made of N-type dopant material, formed upon a substrate such as a P-type doped silicon substrate providing a P-well  1111  formed on substrate  1101 . However, it will be understood that, with appropriate change to substrate or dopant material, a non-silicon P-type semiconductor transistor can be formed from other suitable substrates, such as Gallium Arsenide materials can be substituted. 
     As will be understood, various devices can be created by providing suitable doping to the EBE transistor structure of  FIG. 11B , using ion implantation, diffusion, deposition, or other techniques suitable for introducing dopants into a material. These modifications can be made before epitaxial layer growth, during epitaxial growth (by in-situ growth or the like), or after epitaxial growth. In one embodiment the highly doped screening region structure  1107  is implanted as a thin layer in well  1111 . Such a screening region can increase body bias efficacy by providing a dopant plane/region that more effectively couples body bias circuitry to the EBE transistor structure, and thereby, advantageously modifies transistor operation. 
     Position, dopant concentration, and thickness of the screening region  1107  can be important factors in EBE transistor design. In certain embodiments, peak concentration of the screening region defines the edge of the depletion region under the gate and the screening region is located below the bottom of the source and drain junctions. In other embodiments the screening region may be located close to a gate, and contact the source and drain junctions. Typically, in operation, the channel  1105  is deeply depleted, with the screening region  1107  acting in whole or in part to define termination of a depletion region under a gate. The screening region can be formed using a variety of precision doping techniques including, delta doping, broad implantation, or in-situ substitutional doping. Typically the screening region has a finite thickness of about 5 to 50 nanometers, although thicker layers are possible. When transistors are configured to have such screening regions, the transistor can simultaneously have good threshold voltage matching, high mobility, high output resistance, low junction leakage, good short channel effects, and still have an independently controlled and strong body effect. 
     In certain embodiments, the screening region  1107  is doped to have a concentration between about 5×10 18  dopant atoms per cm 3  and about 1×10 20  dopant atoms per cm 3  of dopant material of the opposite type from the source and drain dopants, significantly more than the dopant concentration of the channel region  1105 , and at least slightly greater than the dopant concentration of the optional voltage threshold set region  1109 . As will be appreciated, exact dopant concentrations, screening region thicknesses and screening region depths can be modified to improve desired operating characteristics of EBE transistor  1196 , or to take in to account available transistor manufacturing processes and process conditions. 
     Together the structures and methods of making the structures allow for EBE transistors having an enhanced body coefficient as compared to conventional nanoscale devices. Thus, the response of the EBE transistor can vary within a wider range to a change in the body bias voltage applied to the screening region. More specifically, the enhanced body coefficient of the EBE transistor can allow a broad range of ON-current and the OFF-current that depends on the body bias voltage applied to the screening region, as compared to the body bias voltage applied to a conventional device. In addition, the EBE transistors have a lower σV T  (threshold voltage variation) than conventional devices. The lower σV T  provides a lower minimum operating voltage VDD and a wider range of available nominal values of V T . The enhanced body coefficient of the EBE transistor can also allow a broad range of threshold voltage that depends on the body bias voltage applied to the screening region, as compared to the body bias voltage applied to a conventional device. The screening region allows effective body biasing for enhanced control of the operating conditions of a device or a group of devices to be set by controlling the applied body bias voltage. In addition, different operating conditions can be set for devices or groups of devices as result of applying different body bias voltages. 
     Advantageously, EBE transistors created in accordance with the foregoing embodiments, structures, and processes, can have a reduced mismatch arising from scattered or random dopant variations as compared to conventional MOS transistors. In certain embodiments, the reduced variation results from the adoption of structures such as the screening region, the optional threshold voltage set region, and the epitaxially grown channel region. In certain alternative embodiments, mismatch between EBE transistors can be reduced by implanting the screening layer across multiple EBE transistors before the creation of transistor isolation structures, and forming the channel region as a blanket epitaxial layer that is grown before the creation of transistor epitaxial structures. In certain embodiments, the screening region has a substantially uniform concentration of dopants in a lateral plane. The EBE transistor can be formed using a semiconductor process having a thermal budget that allows for a reasonable throughput while managing the diffusivities of the dopants in the channel. Further examples of transistor structure and manufacture suitable for use in EBE transistors are disclosed in U.S. patent application, Ser. No. 12/708,497, filed on Feb. 18, 2010, titled ELECTRONIC DEVICES AND SYSTEMS, AND METHODS FOR MAKING AND USING THE SAME, by Scott E. Thompson et al., as well as U.S. patent application Ser. No. 12/971,884, filed on Dec. 17, 2010 titled Low Power Semiconductor Transistor Structure and Method of Fabrication Thereof and U.S. patent application Ser. No. 12/971,955 filed on Dec. 17, 2010 titled Transistor with Threshold Voltage Set Notch and Method of Fabrication Thereof the respective contents of which are incorporated by reference herein. 
     Static and/or dynamic body biasing as described herein can be applied to various types of circuits. It is noted that the embodiments for selecting body bias voltages described above can be used to select body bias voltages for EBE transistors, conventional transistors, or a combination of EBE and conventional transistors. For embodiments that select body bias voltages for EBE transistors, the selected body bias voltages are applied to the screening region of the EBE transistor. For embodiments that select body bias voltages for conventional transistors, the selected body bias voltages are applied to the body or substrate of the conventional transistor. Particular examples of body biased circuits that can be biased using the selected body bias voltages include operational circuits (e.g., circuits biased with a selected body bias) and/or emulation circuits will now be described. It is noted that in the embodiments described below, the body biased circuits are shown to include only EBE transistors. It is understood that alternate embodiments could include a mix of EBE transistors and conventional transistors, or no EBE transistors. 
       FIG. 12  shows a complementary device logic circuit  1223  according to an embodiment. The particular embodiment of  FIG. 12  shows an inverter formed by a p-channel EBE transistor P 00  and an n-channel EBE transistor N 00  having source, drain and gate connections like a CMOS inverter. Unlike a conventional CMOS inverter, in which a PMOS device has a body connected to a high power supply voltage VDD and an NMOS device has a body connected to a low power supply voltage VSS, the transistors of logic circuit  1223  have bodies connected to different bias nodes (VBP and VBN). Body bias voltages for application to such nodes can be selected, as described herein, to optimize one or more device performance features. 
     While  FIG. 12  shows an inverter, in other embodiments, the same body biasing arrangement can be applied to other types of circuits, including but not limited to, other logic circuits (e.g., NAND gates, NOR gates). 
     The separate body biasing of both n-channel and p-channel EBE devices can allow for greater adjustment than conventional approaches. In CMOS circuits using conventional transistors, as the transistors scale to smaller sizes, the body coupling coefficient diminishes. In contrast, due in part to its highly doped screening layer (noted above), an EBE transistor can have an enhanced body coupling coefficient, enabling greater changes in transistor performance parameters, e.g., threshold voltage and leakage current, per unit change in body bias. 
     The enhanced body coefficient of EBE transistors can be used to improve device performance over that achievable with conventional transistors. As but a few examples, if process or operating conditions result in p-channel EBE transistors with threshold voltages (Vtp) that are too high when body biased with VDD (which can make the device too slow), a forward body bias (VBPF&lt;VDD) can be applied to arrive at the desired speed. Similarly, if n-channel EBE transistors have threshold voltages (Vtn) that are too low when body biased with VSS (which can make the device fast but leaky), a reverse body bias (VBNR&lt;VSS) can be applied to reduce the leakage, while maintaining an adequate speed. 
     Still further, in some embodiments, body biasing techniques as described herein can be used to set the threshold voltage of the transistors. In particular, transistors can be manufactured with a process having a target threshold voltage (assuming zero body bias conditions) that is lower than a desired operational threshold voltage. Reverse body biasing may then be used to arrive at desired threshold voltages and performance of the device. One very particular example of a target processing (absolute) threshold voltage can be 0.3 V under zero body bias conditions. Reverse body biasing can raise such threshold voltages as needed to meet performance targets. 
     Biased transistors as described herein can be applied to circuits other than standard logic circuits, and the body bias voltages can be selectively applied with even finer granularity, such different body bias voltages being applied to different NMOS and PMOS transistors in the same circuit. As additional examples, according to embodiments, level shifter circuits may be modified to enable lower operating voltages. 
       FIG. 13  shows a conventional level shifter circuit  1323 . Conventional level shifter  1323  can span two high voltage domains: VDD and VDDL, where VDDL&lt;VDD. In the conventional case, gates of NMOS devices N 10  and N 11  will receive input signals that vary between VSS and VDDL. The PMOS devices P 10  and P 11  operate with a gate-to-source voltage (VGS) with respect to the high VDD. In the conventional level shifter  1323 , device sizes are ratioed with respect to one another to enable NMOS devices (N 10  and N 11 ) to overpower cross-coupled PMOS devices (P 10  and P 11 ). However, when VDDL is very low, NMOS devices may not capable of such an operation. 
       FIG. 14  shows a level shifter according to an embodiment. A level shifter  1423  may include EBE devices connected in a fashion like that of  FIG. 13 . However, n-channel devices N 20 /N 21  can have screening regions that are coupled to a forward body bias voltage (VBNF). In addition or alternatively, p-channel devices P 20 /P 21  can have screening regions that are coupled to a reverse body bias voltage (VBPR). In alternate embodiments, some or all of the transistors in level shifter  1423  may be non-EBE transistors. 
     In such an arrangement, a level shifter  1423  may operate at lower VDDL levels than conventional approaches, as n-channel devices (N 20  and N 21 ) can have increased drive strength at such a lower VDDL, as compared to the conventional case. Further, p-channel devices (P 20  and P 21 ) can be overpowered by the n-channel pull down devices to switch at lower VDDL voltage levels. 
     Body bias voltages VBNF and/or VBPR can be static, or dynamically applied to the level shifter. 
       FIG. 15A  shows a level shifter according to a further embodiment. A level shifter  1523  may include some sections like that shown in  FIG. 14 . However, unlike  FIG. 14 , level shifter  1523  further includes n-channel EBE transistors N 32 /N 36  that switch the body bias voltage applied to the n-channel EBE transistor N 30 , and N 34 /N 38  which switch the body bias voltage applied to the EBE transistor N 31 . In certain embodiments, N 32 -N 38  can have either zero or reverse body bias applied as required to obtain the most compact layout. Optionally, n-channel transistors N 32 /N 36 /N 34 /N 38  can be forward biased using a forward body bias voltage (VBNF). In addition or alternatively, p-channel devices P 30 /P 31  can be reverse biased using a reverse body bias voltage (VBPR). 
       FIG. 16  is a graph showing delays of level shifter circuits described above. Response  1501  shows a level shifter like that of  FIG. 15  (no p-channel VBPR applied). Response  1502  shows a “zero body bias” case (a level shifter with n-channel devices at zero body bias). Response  1503  shows a response for a level shifter like that of  FIG. 14 . Corresponding leakage values (Ileak) are also shown.  FIG. 16  shows good level shifter performance at VDDL levels that can cause conventional level shifters to fail. 
     In this way, biased EBE transistors can enable level shifters to operate at lower voltage supply levels, with leakage currents similar to level shifters using conventional transistors. In another embodiment, PMOS transistors P 30  and P 31 , and NMOS transistors N 30  and N 31  can be thick gate oxide devices, where PMOS transistors P 30  and P 31  can be coupled to a higher voltage VDDIO supply that exceeds the core transistor reliable voltage tolerance. In such embodiments, the VDDL can be the core VDD, and the operation of such an embodiment is similar to the embodiment discussed with reference to  FIG. 15A . In other embodiments, the PMOS transistors P 30  and P 31  can be either conventional thick gate oxide transistors or EBE thick gate oxide transistors. 
       FIG. 15B  shows a level shifter according to a further embodiment. The level shifter  1523 ′ includes two PMOS transistors P 40  and P 41  connected to the higher voltage VDDIO supply. In certain embodiments, P 40  and P 41  can be conventional thick oxide transistors. In certain alternative embodiments, P 40  and P 41  can be EBE thick oxide transistors. The level shifter  1523 ′ also includes four NMOS transistors N 50 , N 51 ,N 52 , and N 53  with their gates connected to VDD. Embodiments of the level shifter  1523 ′ can user either EBE or conventional transistors as the NMOS transistors N 50 -N 53 . The cascode configuration of these transistors protects the remaining NMOS transistors in the level shifter  1523 ′ from the high VDDIO voltage at NODE 60  and NODE 61 , as the voltage at the source of N 50 -N 53  is set to VDD less the threshold voltage of the corresponding transistor. The level shifter  1523 ′ further includes n-channel EBE transistors N 64 /N 68  that switch the body bias voltage applied to the n-channel EBE transistor N 60 , and N 66 /N 70  which switch the body bias voltage applied to the EBE transistor N 62 . In certain embodiments, N 64 , N 66 , N 68 , and N 70  can have either zero or reverse body bias applied as required to obtain the most compact layout. Optionally, n-channel transistors N 64 , N 66 , N 68 , and N 70  can be forward biased using a forward body bias voltage (VBNF). 
     According to other embodiments, techniques using fine-grained biased EBE transistors can increase a response speed of logic circuits while at the same time maintaining low levels of leakage. More particularly, for logic circuits having more than one of the same type transistor in series, one of the transistors can have zero or very low body bias voltage, and the remaining transistors in the series can have a forward or reverse body bias voltage. 
       FIG. 17A  shows a logic gate  1723  according to an embodiment. A logic gate  1723  can include 
     p-channel transistors P 40 /P 41  and n-channel transistors N 40 /N 41  connected in a NOR type gate arrangement. As noted above, while  FIG. 17  shows EBE type transistors, alternate embodiments can be composed of all, or in part, of conventional NMOS/PMOS transistors. Transistors P 40  and P 41  are connected in series. However, unlike a conventional approach, transistor P 40  can have a forward body bias VFBP. In one very particular embodiment, such a forward body bias can be a low power supply voltage VSS. While the forward body biased transistor P 40  could have some increased leakage, series connected transistor P 41  is biased using supply voltage VDD to minimize any leakage through P 40 . 
     As also described above, such a biasing may be static or dynamic. 
       FIG. 17B  shows responses for embodiments shown by  FIG. 17A . In particular,  FIG. 17B  shows input signals (INa/b) going low, resulting in output OUT going high.  FIG. 17B  also shows three output responses  1701 ,  1702  and  1703 . Response  1701  shows a response for an embodiment like that shown in  FIG. 17A  that includes EBE transistors. Response  1702  shows a response for an embodiment like that shown in  FIG. 17A , but without EBE transistors. Finally, response  1703  shows a conventional CMOS NOR gate response. As shown, body biasing can increase a signal propagation speed of a logic gate. 
       FIG. 17C  shows the same general approach for the embodiment of  FIG. 17A , but applied to a NAND gate  1723 ′. Within the series connected n-channel transistors N 50  and N 51 , transistor N 51  can have a forward body bias voltage (VBNF), which in a very particular embodiment can be a high power supply VDD. 
     According to further embodiments, techniques using biased EBE transistors can increase a response speed of sensing circuits, such as those used to sense data values in a static random access memory (SRAM) device. An SRAM device according to one very particular embodiment will now be described with reference to  FIGS. 18A to 18D . 
       FIG. 18A  shows an SRAM device  1825  in a block schematic diagram according to one embodiment. An SRAM device  1825  may include a number of memory cells (one shown as  1827 ), each connected to bit lines (one shown as BL) and a word line (WL 0  to WLy). Memory cells (e.g.,  1827 ) can be connected to bit lines by activation of a word line. Sensing circuits (one shown as  1829 ) can be activated by one or more sense enable signals SA_SEL to sense data values stored in selected SRAM cells. Sensing circuits (e.g.,  1829 ) can use biased EBE transistors to increase sensing speed as described below. 
       FIG. 18B  shows a sensing circuit  1829 ′ according to one particular embodiment. Sensing circuit  1829 ′ can sense a voltage change on a bit line (BL or BLB). In a sensing operation, p-channel devices P 60 /P 61  can be enabled (e.g., have VDD applied to their sources) by a signal SA_SEL_P (which is active low in this embodiment). In addition, in a sensing operation, n-channel devices N 60 /N 61  can be enabled (e.g., have VSS applied to their sources) by a signal SA_SEL_N (which is active high in this embodiment). 
     As shown in  FIG. 18B , p-channel devices P 60 /P 61  can receive a forward body bias voltage VBFP. In a particular embodiment, such a forward body bias voltage can be the same voltage as signal SA_SEL_N, and hence provide dynamic body biasing. In such a case, p-channel EBE transistors P 60 /P 61  can have screening regions that are biased to VSS during the sense operation, but are subsequently biased to VDD after the sense operation. 
       FIG. 18C  is a circuit  1829 ″ illustrating an inverter based single-ended SRAM sensing circuit. Such SRAM sensing circuits can be slower than differential sense circuits, but they can be simpler to design and can have a smaller size. The sensing speed of such single-ended SRAM sense circuits can be substantially improved in certain embodiments that use EBE transistors and use fine grained biasing to selectively control the body bias voltage applied to individual transistors. In the embodiment shown in  FIG. 18C , a variable body bias voltage is applied to the PMOS transistor P 60 , thereby resulting in a smaller layout size since only a separate N-well is required in the layout. This N-well can be shared across multiple sense circuits that use a variable PMOS transistor bias activated with the same SA_SEL_N signal to achieve further reductions in layout size. The NMOS transistor N 60  can have a zero body bias voltage, or it can be biased using the body bias voltage applied to other NMOS transistors in a common well arrangement. 
       FIG. 18D  is a graph showing a response of the circuit of  FIG. 18C .  FIG. 18D  includes an input waveform  1801  (VBL) which can represent a voltage signal development on a bit line sensed by the sensing circuit.  FIG. 18D  also shows two output responses  1802  and  1803 . Response  1802  shows a response for an embodiment like that shown in  FIG. 18C  that includes a dynamic forward body biasing of a p-channel EBE transistor. Response  1803  shows a response when such a p-channel EBE transistor does not include forward body biasing (e.g., the body bias voltage is maintained at VDD). The forward body biasing can be limited by cascode arrangements as discussed above with reference to embodiments of level shifter circuits. 
     As shown from the figures, biasing of a memory sensing circuit according to the embodiment can achieve measurable speed advantages. 
     As understood from the various embodiments herein, an IC device may include multiple bias voltages that may be selected for application to circuits, which serve as emulation circuits used to derive optimal body bias values, or operational circuits to which such optimal values are applied. Examples of bias voltage generator circuits will now be described. 
       FIG. 19A  shows a bias voltage generator circuit  1935  that can be included in embodiments. Generator circuit  1935  can receive a high voltage (VHI_Source) from a source external to the IC device. In addition or alternatively, a low voltage (VLO_Source) can also be received from an external source. A high divider/regulator  1937  can voltage divide and/or regulate voltages to arrive at bias voltages VBxS as well as a high power supply voltage VDD (and if needed, a reduced high power supply voltage VDDL). If voltages lower than a low power supply (VSS) are needed, a low divider/regulator  1939  can be included. The VHI source can be a higher supply voltage, e.g., used for compatible I/O, VDDIO, on the same IC, where VDD&lt;VDDIO. 
       FIG. 19B  shows how different bias voltages can be generated relative to source voltages VHI_Source and VLO_Source. 
     While some embodiments can utilize externally provided voltages, alternative embodiments can generate voltages outside supply ranges on the IC device containing the emulation circuits and biased sections. One example of such an arrangement is shown in  FIG. 19C . 
       FIG. 19C  shows another bias voltage generator circuit  1941  that can be included in embodiments. Generator circuit  1941  can receive a high power supply voltage (VDD), low power supply voltage (VSS), and clock signal (CLK). A high charge pump  1943  can generate voltages greater than a high power supply voltage (VDD) to serve as reverse body bias voltages for p-channel devices (VBPR). A low charge pump  1945  can generate voltages less than a low power supply voltage (VDD) to serve as reverse body bias voltages for n-channel devices (VBNR). Forward body bias voltages for both n-channel and p-channel devices (VBN/F) and a reduced power supply voltage (VDDL) can be generated by voltage divider/regulator  1947  by voltage dividing between high and low power supply voltages. 
     It is understood that other embodiments can mix the various approaches shown in  FIGS. 19A to 19C , including switched capacitor voltage level converters or low drop-out level converters operating at high efficiency. 
     Referring now to  FIG. 20 , a method according to an embodiment is shown in a flow diagram and designated by the general reference character  2081 . A method  2081  can include applying different body bias voltages to emulation circuits on an IC ( 2075 ). The performance of such emulation circuits can be evaluated ( 2077 ). Body bias voltages to apply to operational circuits on the same IC can be selected based on such evaluation results ( 2079 ). 
     Referring now to  FIG. 21 , a method according to a further embodiment is shown in flow diagram and designated by the general reference character  2183 . A method  2183  may include applying different body bias voltages to ring oscillators that emulate operational circuits formed on the same IC ( 2185 ). Speed values for the ring oscillators under such different body bias conditions may be stored ( 2187 ). Such speed values can be weighted according to other IC performance data to generate weighted speed data values ( 2189 ). Optimal body bias voltages can be determined from weighted speed data values ( 2191 ). Such optimal body bias voltages can be applied to the operational circuits ( 2193 ). 
     Referring now to  FIG. 22 , a representative wafer level variation of the EBE transistor threshold voltage is shown for a number of wafers. The threshold voltage values shown in  FIG. 22  are representative of threshold voltage values that can be obtained from fab E-test data measurements performed across sites on the wafer. It can be observed from  FIG. 22  that the EBE transistors exhibit a high degree of uniformity across the wafer, and therefore, in certain embodiments, the body bias voltage can be selected based on a mean value, or some other statistically relevant value that can be determined from the fab E-test data, as discussed in further detail below. 
     Referring now to  FIG. 23 , a method according to a further embodiment is shown in flow diagram and designated by the general reference character  2300 . A method  2300  may include obtaining fab e-test data by performing measurements across sites on the wafers after fabrication ( 2305 ). The Fab E-test data can be used to determine appropriate NMOS and PMOS body bias voltage values ( 2310 ). In certain embodiments, a mean value determined from the fab E-test data can be used to select the body bias voltage for all the dies on the wafer. This approach is effective for embodiments using EBE transistors because the electrical characteristics of EBE transistors across the wafer exhibit a high degree of uniformity. In certain alternative embodiments, the mean value can be weighted to select the body bias voltage for all the dies on the wafer. In certain embodiments, the mean value can weighted to account for the NMOS and PMOS transistor content of the IC (i.e. the die), and/or the stacked transistor effect. The selected body bias voltages are programmed into the IC during wafer sort testing ( 2315 ). In one embodiment, the selected body bias voltages can be programmed into non-volatile storage on the IC, such as read-only-memory (ROM). In an alternative embodiment, the IC can have a configuration of fuses that can be selectively blown to program the selection of a selected body bias voltage for the IC. 
     The method  2300  can either be used by itself or in combination with embodiments of the other methods for selecting body bias voltages described above. In one embodiment, the method  2183  can be optionally used by a user of the IC in conjunction with the method  2300 . In one such embodiment, the method  2300  can be the default method for selecting body bias voltages, and the method  2183  can be used when the default method  2300  is overridden by user selection or as a result of predetermined criteria. For example, the method  2183  can be used to select the body bias voltages and override the method  2300 , if the leakage current of the IC is measured to exceed a certain predetermined value. In alternative embodiments, the method  2183  can be the default method it can be overridden by the method  2300  either by user selection or as a result of predetermined criteria. Other embodiments can use a combination of the methods  2081 ,  2183 , and  2300 , where the body bias voltage is determined using one of these methods as either a result of user selection, or in accordance with predetermined criteria. 
     For embodiments that use a leakage reduction table obtained from simulation, the leakage reduction coefficients in the table can be obtained by using a circuit simulation program such as the BERKELEY-SPICE simulation program, the H-SPICE simulation program, the P-SPICE simulation program, or any other circuit simulation program with similar capabilities using transistor parameters and variations in those transistor parameters that reflect the as-manufactured transistor variability for various skewed processes (or process corners). In certain embodiments, some of the leakage reduction coefficients in the leakage reduction table can be obtained from simulation, while the remainder of the leakage reduction coefficients can be obtained from measurements, calculations based on equations governing leakage current as a function of NMOS and PMOS body bias voltages, or from interpolation between leakage reduction coefficients obtained from leakage reduction coefficients available for other available process corners. In certain embodiments the leakage reduction tables can be sparsely populated such that leakage reduction coefficients are only provided for certain combinations of bias voltages. 
     Circuits and IC devices according to embodiments shown herein, and equivalents, may provide improved performance over conventional circuits by providing body bias conditions optimized for multiple performance parameters. When EBE transistors are employed, the enhanced body coefficient of such transistors can enable greater transistor control with body biasing as compared to conventional transistors. Possible improvements can include faster signal propagation times, lower operating voltages, and/or lower power consumption. 
     Embodiments may also provide greater threshold voltage control as compared to methods relying on manufacturing processes. Transistor threshold voltages can be tightly tuned to accommodate variations arising from process and/or temperature. As noted above, devices can be fabricated with intentionally low (magnitude) threshold voltages, and precise reverse body bias voltages and be used to arrive at a desired operating threshold voltage. 
     It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention. 
     It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element. 
     Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.