Patent Publication Number: US-2022238446-A1

Title: Semiconductor package structure and method for forming the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of U.S. Provisional Application No. 62/770,861 filed on Nov. 23, 2018, the entirety of which is incorporated by reference herein. 
    
    
     BACKGROUND 
     Technical Field 
     The disclosure relates to a semiconductor package, and more particularly to a semiconductor package that includes an inter-die connector. 
     Description of the Related Art 
     The semiconductor packaging process is an important step in the fabrication of electronic products. Semiconductor packages not only protect the semiconductor dies therein from outer environmental contaminants but also provide electrical connection paths between the electronic components inside and those outside of the semiconductor packages. For example, a semiconductor package contains wires that may be used to form conductive paths. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g. transistors, diodes, resistors, capacitors, and so on.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. These smaller electronic components also use a smaller package that utilizes less area or a smaller height, in some applications. When the semiconductor packages become denser, the crosstalk generated between conductive paths increases correspondingly. 
     While existing semiconductor package structures have been generally adequate for their intended purposes, they have not been satisfactory in all respects. There is a particular need for further improvements in the reduction of the crosstalk between electronic components. 
     SUMMARY 
     In one embodiment of the present disclosure, a semiconductor package structure is provided, wherein the semiconductor package structure includes a first semiconductor die and a second semiconductor die neighboring the first semiconductor die. The first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge. The second semiconductor includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge. The first metal layer of the first semiconductor die is electrically connected to the second metal layer of the second semiconductor die. 
     In one embodiment of the present disclosure, a method for forming a semiconductor package structure is provided, wherein the method for forming a semiconductor package structure includes providing a first semiconductor die on a carrier substrate, wherein the first semiconductor die includes a first edge, a second edge opposite the first edge, and a first metal layer exposed from the second edge, wherein the first metal layer is disposed in an interconnection layer of the first semiconductor die; and providing a second semiconductor die neighboring the first semiconductor die on the carrier substrate, wherein the second semiconductor die includes a third edge neighboring the second edge of the first semiconductor die, a fourth edge opposite the third edge, and a second metal layer exposed from the third edge, wherein the second metal layer is disposed in an interconnection layer of the second semiconductor die; and forming an electrical connection between the first metal layer of the first semiconductor die and the second metal layer of the second semiconductor die. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of this disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with common practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1-8  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure, according to some embodiments of the present disclosure. 
         FIGS. 9-15  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure, according to other embodiments of the present disclosure. 
         FIGS. 16-22  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure, according to other embodiments of the present disclosure. 
         FIG. 23  is a perspective view illustrating an exemplary semiconductor package structure, according to some embodiments of the present disclosure. 
         FIG. 24  is a perspective view illustrating an exemplary semiconductor package structure, according to other embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Furthermore, spatially relative terms, such as “over”, “below,” “lower,” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The terms “about”, “approximately”, and “substantially” used herein generally refer to the value of an error or a range within 20 percent, preferably within 10 percent, and more preferably within 5 percent, within 3 percent, within 2 percent, within 1 percent, or within 0.5 percent. If there is no specific description, the values mentioned are to be regarded as an approximation that is an error or range expressed as “about”, “approximate”, or “substantially”. 
     Although some embodiments are discussed with operations performed in a particular order, these operations may be performed in another logical order. Additional features can be provided to the semiconductor structures in embodiments of the present disclosure. Some of the features described below can be replaced or eliminated for different embodiments. 
     Embodiments of the present disclosure provide a semiconductor package structure which includes an inter-die connector to form an electrical connection between two adjacent dies. The inter-die connector is disposed between two adjacent dies to make an electrical connection between the metal layers respectively exposed from edges of the two adjacent die. By setting the inter-die connector, the grounding lines of the two adjacent dies can be electrically connected directly through the inter-die connector without through additional redistribution layers, such that the conductive path between the two adjacent dies can be effectively reduced, thereby reducing the crosstalk and parasitic inductance between the additional redistribution layers in the semiconductor package structure with high integration density. 
       FIGS. 1-7  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure  800 A (as shown in  FIG. 8 ), according to some embodiments of the present disclosure. Referring to  FIG. 1 , a wafer  101  with various devices (not shown) fabricated thereon is provided. The various devices (or components) on the wafer  101  are electrically connected to each other by an interconnection layer  102  to form functional circuit. As shown in  FIG. 1 , the interconnection layer  102  is embedded in inter-metal dielectric (IMD) layers (not shown) and disposed closely adjacent to a top surface  101 T of the wafer  101 . A plurality of conductive pads  103  and a passivation layer  104  are sequentially formed on the front side  101 T of the wafer  101 , wherein each of the conductive pads  103  is partially exposed from the passivation layer  104 . 
     In some embodiments, the wafer  101  may include integrated circuits, such as logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, power integrated circuits, or memory circuits; micro-electro mechanical systems (MEMS); opto-electronic devices; sensors, such as light sensors or fingerprint sensor; or the like. In some embodiments, the wafer  101  includes an active element (not shown) formed therein, such as a transistor, a metal oxide semiconductor field effect transistor (MOSFET), a metal insulator semiconductor FET (MISFET), a junction field effect transistor (FET), an insulated gate bipolar transistor (IGBT), a combination thereof, or the like. It should be noted that  FIG. 1  does not illustrate the components of the wafer  101  under the interconnection layer  102  for the purpose of simplicity and clarity. 
     In some embodiments, the interconnection layer  102  may include contact plugs formed in an interlayer dielectric (ILD) layer and/or vias and metal lines formed in inter-metal dielectric (IMD) layers (not shown), wherein a portion of the interconnection layer  102  may serve as a seal-ring structure to prevent mechanical damage to the semiconductor dies during the dicing process and prevent the invasion of moisture and chemical contaminants. For example, the interconnection layer  102  may be formed by a single damascene process or a dual damascene process. 
     Referring to  FIG. 2 , in some embodiments, a plurality of bumps  105  are correspondingly formed on top surfaces of the plurality of conductive pads  103  exposed from the passivation layer  104 , and an insulating layer  106  (e.g. a polyimide layer) is formed to cover the plurality of bumps  105  and the passivation layer  104 . In some embodiments, the passivation layer  104  may include SiO 2 , SiN 3 , SiON, Al 2 O 3 , AlN, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), other suitable materials, or a combination thereof. In some embodiments, the passivation layer  104  may be formed by chemical vapor deposition (CVD), spin-coating, other suitable methods, or a combination thereof. In some embodiments, the bumps  105  are copper pillars which are used to form an electrical connection between the active elements (not shown) in the wafer  101  and a redistribution layer (e.g. a redistribution layer  620  shown in  FIG. 6 ) to be electrically coupled with external circuits. 
     Referring to  FIG. 3 , a planarization process, such as a chemical mechanical polish (CMP) process or other suitable planarization processes, is performed to the insulating layer  106  to expose the top surfaces  105 T of the plurality of bumps  105 , and a dicing process is performed after the planarization process to divide the wafer  101  into a plurality of individual semiconductor dies (e.g. semiconductor dies  100 A/ 100 B/ 100 C/ 100 D). As shown in  FIG. 3 , after the dicing process, the semiconductor dies  100 A/ 100 B/ 100 C/ 100 D are disposed with intervals on a dicing tape TP with the interconnection layer  102  exposed from the die edges. More specifically, a metal layer  310  in the interconnection layer  102  of the semiconductor die  100 A and a metal layer  320  in the interconnection layer  102  of the semiconductor die  100 B are exposed to the gap between the semiconductor die  100 A and the semiconductor die  100 B. In some embodiments, the metal layer  310  and the metal layer  320  may serve as a seal-ring structure to prevent mechanical damage to the semiconductor dies during the dicing process. 
     In some embodiments, the metal layers  310  and  320  may include Cu, W, Ag, Sn, Ni, Co, Cr, Ti, Pb, Au, Bi, Sb, Zn, Zr, Mg, In, Te, Ga, other suitable metal materials, an alloy thereof, or a combination thereof. In some embodiments, metal layers may be deposited by a process such as a physical vapor deposition (PVD) process, plating, an atomic layer deposition (ALD) process, other suitable processes, or a combination thereof. 
     Subsequently, referring to  FIG. 4 , the plurality of semiconductor dies (e.g. semiconductor dies  100 A/ 100 B/ 100 C/ 100 D) with the conductive pads  103 , the passivation layer  104 , the bumps  105 , and the insulating layer  106  formed on front sides of the semiconductor dies are picked from the dicing tape TP and placed on a carrier substrate  400 . For example, the front sides of the semiconductor dies may be a front side  100 AT of the semiconductor die  100 A, a front side  100 BT of the semiconductor die  100 B, and so on. Specifically, back sides of the semiconductor dies, such as the back side  100 AB of the semiconductor die  100 A and the back side  100 BB of the semiconductor die  100 B, are attached to a top surface of the carrier substrate  400 . 
     Referring to  FIG. 5 , in some embodiments, the semiconductor die  100 A and the semiconductor die  100 B which will be combined into the semiconductor package structure  800 A later (as shown in  FIG. 8 ) are disposed on the carrier substrate  400  with a first gap G 1  therebetween, the semiconductor die  100 C and the semiconductor die  100 D which will be combined into the semiconductor package structure  800 B later (as shown in  FIG. 8 ) are also disposed on the carrier substrate  400  with a first gap G 1  therebetween. Meanwhile, the semiconductor die  100 B and the semiconductor die  100 C, which will not be combined into the same package structure, are disposed with a second gap G 2  therebetween greater than the first gap G 1 . The second gap G 2  may be regarded as “an inter-package gap”. For example, the width of the first gap G 1  may be in a range from about 10 micrometers to about 1000 micrometer, and the width of the second gap G 2  may be in a range from about 10 micrometers to about 1000 micrometer, wherein a subsequent dicing process (as shown in  FIG. 8 ) may be performed through the second gap G 2 . Furthermore, the difference between the width of the first gap G 1  and the width of the second gap G 2  may be in a range from about 10 micrometers to about 1000 micrometer. 
     Still referring to  FIG. 5 , the semiconductor die  100 A includes a first edge  501  and a second edge  502  opposite the first edge  501 , wherein the metal layer  310  is exposed from the second edge  502  to the first gap G 1  between the semiconductor die  100 A and the semiconductor die  100 B. The semiconductor die  100 B includes a third edge  503  neighboring the second edge  502  of the semiconductor die  100 A and a fourth edge  504  opposite the third edge  503 , wherein the metal layer  320  is exposed from the third edge  503  to the first gap G 1  between the semiconductor die  100 A and the semiconductor die  100 B. In some embodiments, the conductive pad  103 A and the metal layer  310  are disposed on opposite sides of the front side  100 AT of the semiconductor die  100 A, and the conductive pad  103 B and the metal layer  320  are disposed on opposite sides of the front side  100 BT of the semiconductor die  100 B. 
     According to some embodiments of the present disclosure, as shown in  FIG. 5 , an inter-die connector  500  is formed between the metal layer  310  of the semiconductor die  100 A and the metal layer  320  of the semiconductor die  100 B to provide their electrical connection. The inter-die connector  500  includes a first surface  500   a  adjacent to the front side  100 AT of the semiconductor die  100 A and the front side  100 BT of the semiconductor die  100 B and a second surface  500   b  away from the front side  100 AT of the semiconductor die  100 A and front side  100 BT of the semiconductor die  100 B. 
     In some embodiments, the material of the inter-die connector  500  may include metal (e.g. tungsten, aluminum, or copper), metal alloy, other suitable conductive materials, or a combination thereof. For example, the conductive materials may be deposited in the first gap G 1  by a process such as a physical vapor deposition (PVD) process, electroplating, electroless plating, metal organic chemical-vapor deposition (MOCVD), an atomic layer deposition (ALD) process, other suitable processes, or a combination thereof. 
     Specifically, according to some embodiments of the present disclosure, the inter-die connector  500  is made of copper and is formed by a plating process. For example, the plating process for forming the inter-die connector  500  may include a sputtering process to blanketly form a metallic seed layer (not shown) on the carrier substrate  400 , a photolithography process to form a patterned photoresist (not shown) with an opening corresponding to the first gap G 1 , an electro-plating process by connecting the previously formed seed layer to an electrode (not shown) to plate copper in the first gap G 1  through the opening of the patterned photoresist, and removing the patterned photoresist and the seed layer which is covered by the patterned photoresist. In other embodiments, the inter-die connector  500  may be formed by applying metal paste in the first gap G 1  to form the electrical connection between the metal layers  310  and  320 . The material of the metal paste may include metal (e.g. tungsten, aluminum, or copper), metal alloy, other suitable conductive materials, or a combination thereof. For example, as shown in the cross-sectional view illustrating in  FIG. 5 , the aspect ratio of the inter-die connector  500  may be in a range from about 10 micrometers to about 1000 micrometers, for example, about 200 micrometers. 
     Still referring to  FIG. 5 , in some embodiments, the inter-die connector  500  partially fills the first gap G 1 , wherein the first surface  500   a  of the inter-die connector  500  is substantially level with a top surface  310 T of the metal layer  310  and a top surface  320 T of the metal layer  320 , and the second surface  500   b  of the inter-die connector  500  is lower than a bottom surface  310 B of the metal layer  310  and a bottom surface  320 B of the metal layer  320 . Specifically, the second surface  500   b  of the inter-die connector  500  may be coplanar with the back side  100 AB of the semiconductor die  100 A and the back side  100 BB of the semiconductor die  100 B. In other words, the second surface  500   b  of the inter-die connector  500  abuts the top surface of the carrier substrate  400  that supports the semiconductor dies (e.g. semiconductor dies  100 A/ 100 B/ 100 C/ 100 D). 
     Referring to  FIG. 6 , a molding compound layer  610  is formed to encapsulate the semiconductor dies (e.g. the semiconductor dies  100 A/ 100 B/ 100 C/ 100 D) after the formation of the inter-die connector  500 . The molding compound layer  610  fills the first gap G 1  not filled by the inter-die connector  500  and fills the second gap G 2  (inter-package gap) between the semiconductor die  100 B and the semiconductor die  100 C. Thus, the first surface  500   a  of the inter-die connector  500  is in contact with the molding compound layer  610 . After the formation of the molding compound layer  610 , a redistribution layer  620  is formed on the molding compound layer  610  and electrically connected to the semiconductor die  100 A and the semiconductor die  100 B respectively by the plurality of bumps  105  (e.g. the copper pillars) (which are disposed on the front side  100 AT of the semiconductor die  100 A and the front side  100 BT of the semiconductor die  100 B). A portion of the molding compound layer  610  is disposed between the redistribution layer  620  and the first surface  500   a  of the inter-die connector  500 . 
     For example, the molding compound layer  610  may be formed of a resin, a moldable polymer, or the like. The molding compound layer  610  may be a resin (e.g. an epoxy resin) which is applied while substantially liquid and then may be cured to transform in the solid. In other embodiments, the molding compound layer  610  may be an ultraviolet (UV) or thermally cured polymer applied as a gel or malleable solid capable of being disposed around the semiconductor dies (e.g. the semiconductor dies  100 A/ 100 B/ 100 C/ 100 D), and then may be cured through a UV or thermal curing process. The molding compound layer  610  may be cured with a mold (not shown). 
     In some embodiments, the redistribution layer  620  includes one or more conductive traces  622  disposed in an inter-metal dielectric (IMD) layer  621 . For example, at least one of the conductive traces  622  is electrically coupled to the semiconductor die  100 A, and at least one of the conductive traces  622  is electrically coupled to the semiconductor die  100 B. For example, the inter-metal dielectric layer  621  may be a single layer or a multi-layer structure. Moreover, the inter-metal dielectric layer  621  may be formed of organic materials, which include a polymer base material, non-organic materials, which include silicon nitride (SiN X ), silicon oxide (SiO X ), graphene, or the like. In some embodiments, the inter-metal dielectric layer  621  is a low-k dielectric layer (k is the dielectric constant of the dielectric layer). In other embodiments, the inter-metal dielectric layer  621  may be formed of a photo sensitive material, which includes a dry film photoresist, or a taping film. 
     For example, the conductive traces  622  may include aluminum, copper, gold, platinum, nickel, tin, a combination thereof, a conductive polymer material, a conductive ceramic material (such as indium tin oxide or indium zinc oxide), or another suitable conductive material. In some embodiments, the conductive traces  622  may be formed by a deposition process, such as a physical vapor deposition (PVD) process, electroplating, electroless plating, metal organic chemical-vapor deposition (MOCVD), an atomic layer deposition (ALD) process, other suitable processes, or a combination thereof. 
     Referring to  FIG. 7 , a plurality of conductive structures  700  are formed on the redistribution layer  620  by a ball placement process, a screen printing process, an electroplating process, or other suitable processes, and followed by a reflow process. In some embodiments, the conductive structures  700  may be solder balls, conductive bumps, conductive pillars, or other suitable conductive structures. Specifically, according to some embodiments of the present disclosure, the conductive structures  700  are solder balls, wherein each of the solder balls includes a first conductive material  701  and a second conductive material  702  formed on the first conductive material  701 . The material of the first conductive material  701  is different from the material of the second conductive material  702 . For example, the materials of the first conductive material  701  and the second conductive material  702  may be selected from tin, lead, copper, gold, nickel, a combination thereof, or another suitable conductive material. More specifically, in some embodiments, the first conductive material  701  is copper and covered by the second conductive material  702  which is tin to be advantageous to a subsequent soldering process. 
     Referring to  FIG. 8 , the carrier substrate  400  is removed and a dicing process is performed with a dicing saw tape (not shown) to form individual semiconductor package structures  800 A/ 800 B by cutting through the redistribution layer  620  and a portion of the molding compound layer  610  which fills the second gap G 2 . As shown in  FIG. 8 , the semiconductor package structure  800 A includes the semiconductor die  100 A and the semiconductor die  100 B, and the semiconductor package structure  800 B includes the semiconductor die  100 C and the semiconductor die  100 D. According to some embodiments of the present disclosure, the semiconductor die  100 A and the semiconductor die  100 B may have the same functionalities. In other embodiments, the semiconductor die  100 A and the semiconductor die  100 B may have different functionalities. 
     Referring to  FIG. 8  along with  FIG. 23 .  FIG. 23  is a perspective view illustrating the semiconductor package structure  800 A, according to some embodiments of the present disclosure. It should be noted that  FIG. 23  does not illustrate all of the elements of the semiconductor package structure  800 A for the purpose of simplicity and clarity. In such embodiments, the semiconductor die  100 A and the semiconductor die  100 B which is in the electrical connection with the semiconductor die  100 A by the inter-die connector  500  included in the semiconductor package structure  800 A are homogeneous dies which may have the same functionalities. 
     On the other hand, referring to  FIG. 8  along with  FIG. 24 .  FIG. 24  is a perspective view illustrating the semiconductor package structure  800 A, according to other embodiments of the present disclosure. It should be noted that  FIG. 24  also does not illustrate all of the elements of the semiconductor package structure  800 A for the purpose of simplicity and clarity. In such embodiments, the semiconductor die  100 A and the semiconductor dies  100 B which are in the electrical connection with each other included in the semiconductor package structure  800 A are heterogeneous dies which may have different functionalities. As shown in  FIG. 24 , the four edges of the semiconductor die  100 A are surrounded by the inter-die connector  500  to form electrical connections with the semiconductor dies  100 B disposed adjacent to the four edges of the semiconductor die  100 A. Furthermore, the four semiconductor dies  100 B disposed around the semiconductor die  100 A may have or may not have the same functionality. It should be noted that the arrangement of the semiconductor dies and the inter-die connector disposed therebetween may vary depending on the product design, and the embodiments of the present disclosure are not limited thereto. 
     As described above, according to the embodiments of the present disclosure, by the arrangement of the inter-die connector to form an electrical connection between two adjacent dies, the grounding lines of the two adjacent dies can be electrically connected directly through the inter-die connector without through additional redistribution layers, such that the conductive path between the two adjacent dies can be effectively reduced, thereby reducing the crosstalk and parasitic inductance between the additional redistribution layers in the semiconductor package structure with high integration density. 
       FIGS. 9-15  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure  800 A′ according to other embodiments of the present disclosure. Specifically, the embodiments provided in  FIGS. 9-15  are with respect to a semiconductor package type which is different from the semiconductor package type provided in the embodiments in  FIGS. 1-8 . According to some embodiments of the present disclosure, the semiconductor package type provided in  FIGS. 1-8  includes a redistribution layer electrically coupled to conductive pads of semiconductor dies through copper pillars, and the semiconductor package type provided in  FIGS. 9-15  includes a redistribution layer directly electrically coupled to conductive pads of semiconductor dies without through copper pillars. Referring to  FIG. 9 , the structure may be formed sequentially after the step illustrated in  FIG. 1 . According to some embodiments of the present disclosure, the structure illustrated in  FIG. 9  is similar to the structure illustrated in  FIG. 3 , except that none of the plurality of bumps  105  and the insulating layer  106  is formed on the plurality of conductive pads  103  and the passivation layer  104  in the structure illustrated in  FIG. 9 . Thus, the details are not repeated for brevity. 
     Referring to  FIG. 10 , the plurality of semiconductor dies (e.g. semiconductor dies  100 A′/ 100 B′/ 100 C′/ 100 D′) with the conductive pads  103  (e.g. the conductive pads  103 A/ 103 B/ 103 C/ 103 D) and the passivation layer  104  formed on front sides of the semiconductor dies are picked from the dicing tape TP and flipped upside down to place on a carrier substrate  400 . For example, the front sides of the semiconductor dies may be a front side  100 A′T of the semiconductor die  100 A′, a front side  100 B′T of the semiconductor die  100 B′, and so on. Specifically, the passivation layer  104  formed on the front sides of the semiconductor dies are attached to a top surface of the carrier substrate  400 . 
     Referring to  FIG. 11 , in some embodiments, the semiconductor die  100 A′ and the semiconductor die  100 B′ which will be combined into the semiconductor package structure  800 A′ later are disposed on the carrier substrate  400  with a first gap G 1  therebetween, the semiconductor die  100 C′ and the semiconductor die  100 D′ which will be combined into the semiconductor package structure  800 B′ later are also disposed on the carrier substrate  400  with a first gap G 1  therebetween, and there is a second gap G 2  larger than first gap G 1  remaining between the semiconductor die  100 B′ and the semiconductor die  100 C′. In some embodiments, a subsequent dicing process (as shown in  FIG. 15 ) may be performed through the second gap G 2 . 
     Still referring to  FIG. 11 , the semiconductor die  100 A′ includes a first edge  501 ′ and a second edge  502 ′ opposite the first edge  501 ′, wherein the metal layer  310 ′ in the interconnection layer  102 ′ is exposed from the second edge  502 ′ to the first gap G 1  between the semiconductor die  100 A′ and the semiconductor die  100 B′. The semiconductor die  100 B′ includes a third edge  503 ′ neighboring the second edge  502 ′ of the semiconductor die  100 A′ and a fourth edge  504 ′ opposite the third edge  503 ′, wherein the metal layer  320 ′ in the interconnection layer  102 ′ is exposed from the third edge  503 ′ to the first gap G 1  between the semiconductor die  100 A′ and the semiconductor die  100 B′. In some embodiments, the conductive pad  103 A and the metal layer  310 ′ are disposed on opposite sides of the front side  100 A′T of the semiconductor die  100 A′, and the conductive pad  103 B and the metal layer  320 ′ are disposed on opposite sides of the front side  100 B′T of the semiconductor die  100 B′. In some embodiments, the metal layer  310 ′ and the metal layer  320 ′ may serve as a seal-ring structure to prevent mechanical damage to the semiconductor dies during the dicing process and prevent the invasion of moisture and chemical contaminants. 
     According to some embodiments of the present disclosure, as shown in  FIG. 11 , an inter-die connector  500 ′ is formed between the metal layer  310 ′ of the semiconductor die  100 A′ and the metal layer  320 ′ of the semiconductor die  100 B′ to form the electrical connection, wherein the inter-die connector  500 ′ includes a first surface  500 ′ a  adjacent to the front side  100 A′T of the semiconductor die  100 A′ and the front side  100 B′T of the semiconductor die  100 B′ and a second surface  500 ′ b  away from the front side  100 A′T of the semiconductor die  100 A′, the front side  100 B′T of the semiconductor die  100 B′, and the top surface of the carrier substrate  400 . The inter-die connector  500 ′ partially fills the first gap G 1  between the semiconductor die  100 A′ and the semiconductor die  100 B′. In some embodiments, the first surface  500 ′ a  of the inter-die connector  500 ′ protrudes beyond the front side  100 A′T of the semiconductor die  100 A′ and the front side  100 B′T of the semiconductor die  100 B′. The material and method for forming the inter-die connector  500 ′ may be selected from those of the above-mentioned inter-die connector  500 . The details are not repeated for brevity. 
     Referring to  FIG. 12 , a molding compound layer  610 ′ is formed to encapsulate the semiconductor dies (e.g. the semiconductor dies  100 A′/ 100 B′/ 100 C′/ 100 D′) after the formation of the inter-die connector  500 ′, wherein the second surface  500 ′ b  of the inter-die connector  500 ′ is in contact with the molding compound layer  610 ′. Specifically, the molding compound layer  610 ′ encapsulates the sidewall surfaces and the back side  100 A′B of the semiconductor die  100 A′ and the sidewall surface and the back side  100 B′B of the semiconductor die  100 B′. The molding compound layer  610 ′ fills the first gap G 1  not filled by the inter-die connector  500 ′ and is in contact with the second surface  500 ′ b  of the inter-die connector  500 ′. 
     Referring to  FIG. 13 , the structure illustrated in  FIG. 12  is flipped upside down, and the carrier substrate  400  is removed to form a redistribution layer  620 ′ over the front side  100 A′T of the semiconductor die  100 A′ and the front side  100 B′T of the semiconductor die  100 B′. According to some embodiments of the present disclosure, the redistribution layer  620 ′ is respectively electrically coupled to the semiconductor dies (e.g. the semiconductor dies  100 A′/ 100 B′/ 100 C′/ 100 D′) through the plurality of conductive pads  103  (e.g. the conductive pads  103 A/ 103 B/ 103 C/ 103 D) formed on the front sides of the semiconductor dies. 
     It should be noted that the material and method for forming the molding compound layer  610 ′ and the redistribution layer  620 ′ respectively may be selected from those of the above-mentioned molding compound layer  610  and redistribution layer  620 . The details are not repeated for brevity. 
     Referring to  FIG. 14 , a plurality of conductive structures  700  are formed on the redistribution layer  620 ′ by a ball placement process, a screen printing process, an electroplating process, or other suitable processes, and followed by a reflow process. In some embodiments, the conductive structures  700  may be solder balls, conductive bumps, conductive pillars, or other suitable conductive structures. It should be noted that the material of the plurality of conductive structures  700  may be selected from that of the above-mentioned conductive structures  700 . The details are not repeated for brevity. 
     Referring to  FIG. 15 , a dicing process is performed to form individual semiconductor package structures  800 A′/ 800 B′ by cutting through the redistribution layer  620 ′ and a portion of the molding compound layer  610 ′ which fills the second gap G 2 . As shown in  FIG. 15 , the semiconductor package structure  800 A′ includes the semiconductor die  100 A′ and the semiconductor die  100 B′, and the semiconductor package structure  800 B′ includes the semiconductor die  100 C′ and the semiconductor die  100 D′. According to some embodiments of the present disclosure, the semiconductor die  100 A′ and the semiconductor die  100 B′ may have the same functionalities (as discussed with respect to  FIG. 25 ). In other embodiments, the semiconductor die  100 A′ and the semiconductor die  100 B′ may have different functionalities (as discussed with respect to  FIG. 26 ). 
     As described above, the arrangement of the inter-die connector is also applicable to the embodiments provided in  FIGS. 9-15  of the present disclosure. By the arrangement of the inter-die connector to form an electrical connection between two adjacent dies, the grounding lines of the two adjacent dies can be electrically connected directly through the inter-die connector without through additional redistribution layers, such that the conductive path between the two adjacent dies can be effectively reduced, thereby reducing the crosstalk and parasitic inductance between the additional redistribution layers in the semiconductor package structure with high integration density. 
       FIGS. 16-22  are cross-sectional views illustrating various steps in the process of manufacturing a semiconductor package structure  800 A″ according to other embodiments of the present disclosure. Specifically, the embodiments provided in  FIGS. 16-22  are with respect to a semiconductor package type which is different from the semiconductor package type provided in the embodiments in  FIGS. 1-8  and the semiconductor package type provided in the embodiments in  FIGS. 9-15 . According to some embodiments of the present disclosure, the semiconductor package type provided in  FIGS. 1-8  includes a redistribution layer electrically coupled to conductive pads of semiconductor dies through copper pillars, the semiconductor package type provided in  FIGS. 9-15  includes a redistribution layer directly electrically coupled to conductive pads of semiconductor dies, and the semiconductor package type provided in  FIGS. 16-22  includes a redistribution layer electrically coupled to conductive pads of semiconductor dies through micro-bumps. 
     Referring to  FIG. 16 , the structure may be formed sequentially after the step illustrated in  FIG. 1 . As shown in  FIG. 16 , a plurality of bumps  1800  are respectively formed on top surfaces of the plurality of conductive pads  103  exposed from the passivation layer  104 . In some embodiments, the bumps  1800  are micro-bumps which are used to form an electrical connection between the active elements in the wafer  101  and a redistribution layer (e.g. a redistribution layer  620 ″ shown in  FIG. 18 ) to be electrically coupled with external circuits. In such embodiments, each of the bumps  1800  includes a first conductive material  1801  and a second conductive material  1802  formed on the first conductive material  1801 . The material of the first conductive material  1801  is different from the material of the second conductive material  1802 . For example, the materials of the first conductive material  1801  and the second conductive material  1802  may be selected from tin, lead, copper, gold, nickel, a combination thereof, or another suitable conductive material. 
     Referring to  FIG. 17 , a dicing process is performed to divide the wafer  101  into a plurality of semiconductor dies (e.g. semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″). As shown in  FIG. 17 , after the dicing process, the semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″ are disposed with intervals on a dicing tape TP, wherein a metal layer  310 ″ in the interconnection layer  102 ″ of the semiconductor die  100 A″ and a metal layer  320 ″ in the interconnection layer  102 ″ of the semiconductor die  100 B″ are exposed to the gap between the semiconductor die  100 A″ and the semiconductor die  100 B″. 
     Referring to  FIG. 18 , the plurality of semiconductor dies (e.g. semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″) with the conductive pads  103  (e.g. conductive pads  103 A/ 103 B/ 103 C/ 103 D), the passivation layer  104 , and bumps  1800  formed on front sides of the semiconductor dies are picked from the dicing tape TP and flipped upside down to place on a redistribution layer  620 ″ provided on a carrier substrate  400 . For example, the front sides of the semiconductor dies may be a front side  100 A″T of the semiconductor die  100 A″, a front side  100 B″T of the semiconductor die  100 B″, and so on. Specifically, the plurality of first bumps  1800  on the front sides of the semiconductor dies are bonded to the redistribution layer  620 ″ on the carrier substrate  400 . 
     As shown in  FIG. 18 , in some embodiments, the semiconductor die  100 A″ and the semiconductor die  100 B″ which will be combined into the semiconductor package structure  800 A″ later are disposed on the carrier substrate  400  with a first gap G 1  therebetween, the semiconductor die  100 C″ and the semiconductor die  100 D″ which will be combined into the semiconductor package structure  800 B″ later are also disposed on the carrier substrate  400  with a first gap G 1  therebetween, and there is a second gap G 2  larger than first gap G 1  remaining between the semiconductor die  100 B″ and the semiconductor die  100 C″. In some embodiments, a subsequent dicing process (as shown in  FIG. 22 ) may be performed through the second gap G 2 . 
     Still referring to  FIG. 18 , the semiconductor die  100 A″ includes a first edge  501 ″ and a second edge  502 ″ opposite the first edge  501 ″, wherein the metal layer  310 ″ in the interconnection layer  102 ″ is exposed from the second edge  502 ″ to the first gap G 1  between the semiconductor die  100 A″ and the semiconductor die  100 B″. The semiconductor die  100 B″ includes a third edge  503 ″ neighboring the second edge  502 ″ of the semiconductor die  100 A″ and a fourth edge  504 ″ opposite the third edge  503 ″, wherein the metal layer  320 ″ in the interconnection layer  102 ″ is exposed from the third edge  503 ″ to the first gap G 1  between the semiconductor die  100 A″ and the semiconductor die  100 B″. In some embodiments, the conductive pad  103 A and the metal layer  310 ″ are disposed on opposite sides of the front side  100 A″T of the semiconductor die  100 A″, and the conductive pad  103 B and the metal layer  320 ″ are disposed on opposite sides of the front side  100 B″T of the semiconductor die  100 B″. In some embodiments, the metal layer  310 ″ and the metal layer  320 ″ may serve as a seal-ring structure to prevent mechanical damage to the semiconductor dies during the dicing process and prevent the invasion of moisture and chemical contaminants. 
     Still referring to  FIG. 18 , after boding the semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″ on the redistribution layer  620 ″, an underfill material  2000  is formed to surround the plurality of bumps  1800 . In some embodiments, the underfill material  2000  is made of or includes a polymer material. The underfill material  2000  may include an epoxy-based resin. In some embodiments, the formation of the underfill material  2000  includes a dispensing process, an application process, other applicable processes, or a combination thereof. In some embodiments, a thermal curing process is used during the formation of the underfill material  2000 . 
     Referring to  FIG. 19 , according to some embodiments of the present disclosure, an inter-die connector  500 ″ is formed between the metal layer  310 ″ of the semiconductor die  100 A″ and the metal layer  320 ″ of the semiconductor die  100 B″ to form the electrical connection, wherein the inter-die connector  500 ″ includes a first surface  500 ″ a  adjacent to the front side  100 A″T of the semiconductor die  100 A″ and the front side  100 B″T of the semiconductor die  100 B″ and a second surface  500 ″ b  away from the front side  100 A″T of the semiconductor die  100 A″ and front side  100 B″T of the semiconductor die  100 B″. In some embodiments, the inter-die connector  500 ″ is formed on the underfill material  2000 , wherein the first surface  500 ″ a  of the inter-die connector  500 ″ is in contact with the underfill material  2000 . The material and method for forming the inter-die connector  500 ″ may be selected from those of the above-mentioned inter-die connector  500 . The details are not repeated for brevity. 
     Referring to  FIG. 20 , a molding compound layer  610 ″ is formed to encapsulate the semiconductor dies (e.g. the semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″) after the formation of the inter-die connector  500 ″, wherein the second surface  500 ″ b  of the inter-die connector  500 ″ is in contact with the molding compound layer  610 ″. Specifically, the molding compound layer  610 ″ encapsulates the sidewall surfaces and the back side  100 A″B of the semiconductor die  100 A″, the sidewall surface and the back side  100 B″B of the semiconductor die  100 B″, and the underfill material  2000 , wherein the molding compound layer  610 ″ fills the first gap G 1  not filled by the inter-die connector  500 ″ and is in contact with the second surface  500 ″ b  of the inter-die connector  500 ″. 
     Referring to  FIG. 21 , the structure illustrated in  FIG. 20  is flipped upside down, and the carrier substrate  400  is removed to form a plurality of conductive structures  700  over the front sides of the semiconductor dies and in contact with the redistribution layer  620 ″ which is respectively electrically coupled to the semiconductor dies (e.g. the semiconductor dies  100 A″/ 100 B″/ 100 C″/ 100 D″) through the plurality of conductive bumps  1800  formed on the front sides of the semiconductor dies. It should be noted that the material and method for forming the conductive structures  700  may be selected from those of the conductive structures  700  with respect to  FIG. 7 . The details are not repeated for brevity. 
     Referring to  FIG. 22 , a dicing process is performed to form individual semiconductor package structures  800 A″/ 800 B″ by cutting through the redistribution layer  620 ″ and a portion of the molding compound layer  610 ″ which fills the second gap G 2 . As shown in  FIG. 22 , the semiconductor package structure  800 A″ includes the semiconductor die  100 A″ and the semiconductor die  100 B″, and the semiconductor package structure  800 B″ includes the semiconductor die  100 C″ and the semiconductor die  100 D″. According to some embodiments of the present disclosure, the semiconductor die  100 A″ and the semiconductor die  100 B″ may have the same functionalities (as discussed with respect to  FIG. 25 ). In other embodiments, the semiconductor die  100 A″ and the semiconductor die  100 B″ may have different functionalities (as discussed with respect to  FIG. 26 ). 
     As described above, the arrangement of the inter-die connector is also applicable to the embodiments provided in  FIGS. 16-22  of the present disclosure. By the arrangement of the inter-die connector to form an electrical connection between two adjacent dies, the grounding lines of the two adjacent dies can be electrically connected directly through the inter-die connector without through additional redistribution layers, such that the conductive path between the two adjacent dies can be effectively reduced, thereby reducing the crosstalk and parasitic inductance between the additional redistribution layers in the semiconductor package structure with high integration density. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.