Patent Publication Number: US-2022216319-A1

Title: Semiconductor integrated circuit device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of International Application No. PCT/JP2020/039062 filed on Oct. 16, 2020, which claims priority to Japanese Patent Application No. 2019-191324 filed on Oct. 18, 2019. The entire disclosures of these applications are incorporated by reference herein. 
    
    
     BACKGROUND 
     The present disclosure relates to a semiconductor integrated circuit device provided with nanosheet (nanowire) field effect transistors (FETs). 
     As a method for forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method is a method in which basic units (e.g., inverters, latches, flipflops, and full adders) having specific logical functions are prepared in advance as standard cells, and a plurality of such standard cells are placed on a semiconductor substrate and connected through interconnects, thereby designing an LSI chip. 
     As for transistors as basic constituents of an LSI, improvement in integration degree, reduction in operating voltage, and improvement in operating speed have been achieved thanks to scaling of the gate length. Recently, however, increase in off current due to excessive scaling and the resulting significant increase in power consumption have raised a problem. To solve this problem, three-dimensional transistors having a three-dimensional structure changed from the conventional planar structure have been vigorously studied. As one type of such three-dimensional transistors, nanosheet (nanowire) FETs have received attention. 
     P. Weckx et al., “Stacked nanosheet fork architecture for SRAM design and device co-optimization toward 3 nm,” 2017 IEEE International Electron Devices Meeting (IEDM), December 2017, IEDM17-505-508 discloses a layout of an SRAM memory cell using nanosheet FETs where the gate electrode is shaped like a fork. 
     Note that the nanosheet FET having a fork-shaped gate electrode is hereinafter called a forksheet FET following the prior art. 
     Thus far, there have been no documents that disclose a layout structure of a standard cell using forksheet FETs nor a layout of a semiconductor integrated circuit using forksheet FETs. 
     An objective of the present disclosure is providing a small-area layout structure of a semiconductor integrated circuit device using forksheet FETs. 
     SUMMARY 
     According to the first mode of the present disclosure, a semiconductor integrated circuit device includes standard cells arranged in a first direction, in each of the standard cells, a p-type region in which p-type transistors are formed and an n-type region in which n-type transistors are formed being disposed adjacently in a second direction vertical to the first direction, the standard cell including: a first nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the p-type region; a second nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the n-type region; a first gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the first nanosheet group in the second direction and a third direction perpendicular to the first and second directions; and a second gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the second nanosheet group in the second and third directions, wherein in the first nanosheet group, a first nanosheet farthest from the n-type region has a face exposed from the first gate interconnect on a side away from the n-type region in the second direction, and a second nanosheet closest to the n-type region has a face exposed from the first gate interconnect on a side closer to the n-type region in the second direction, and in the second nanosheet group, a third nanosheet farthest from the p-type region has a face exposed from the second gate interconnect on a side away from the p-type region in the second direction, and a fourth nanosheet closest to the p-type region has a face exposed from the second gate interconnect on a side closer to the p-type region in the second direction. 
     According to the above mode, in the first nanosheet group in the p-type region, the first nanosheet farthest from the n-type region has a face exposed from the first gate interconnect on the side away from the n-type region in the second direction. In the second nanosheet group in the n-type region, the third nanosheet farthest from the p-type region has a face exposed from the second gate interconnect on the side away from the p-type region in the second direction. That is, the first gate interconnect does not protrude from the first nanosheet group toward the outside of the standard cell, and the second gate interconnect does not protrude from the second nanosheet group toward the outside of the standard cell. Also, in the first nanosheet group in the p-type region, the second nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the second direction. In the second nanosheet group in the n-type region, the fourth nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the second direction. That is, the first gate interconnect does not protrude from the first nanosheet group toward the second nanosheet group, and the second gate interconnect does not protrude from the second nanosheet group toward the first nanosheet group. This can reduce the size in the second direction of the standard cell, whereby a small-area layout structure can be achieved. 
     According to the second mode of the present disclosure, a semiconductor integrated circuit device includes: a first power line extending in a first direction for supplying a first power supply voltage; and a second power line extending in the first direction for supplying a second power supply voltage, a p-type region in which p-type transistors are formed and an n-type region in which n-type transistors are formed being disposed adjacently in a second direction vertical to the first direction between the first and second power lines, the device further including: a first nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the p-type region; a second nanosheet group including two or more nanosheets, each extending in the first direction, arranged in the second direction in the n-type region; a first gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the first nanosheet group in the second direction and a third direction perpendicular to the first and second directions; and a second gate interconnect extending in the second direction, formed to surround peripheries of the nanosheets of the second nanosheet group in the second and third directions, wherein in the first nanosheet group, a first nanosheet farthest from the n-type region has a face exposed from the first gate interconnect on a side away from the n-type region in the second direction, and a second nanosheet closest to the n-type region has a face exposed from the first gate interconnect on a side closer to the n-type region in the second direction, and in the second nanosheet group, a third nanosheet farthest from the p-type region has a face exposed from the second gate interconnect on a side away from the p-type region in the second direction, and a fourth nanosheet closest to the p-type region has a face exposed from the second gate interconnect on a side closer to the p-type region in the second direction. 
     According to the above mode, in the first nanosheet group in the p-type region, the first nanosheet farthest from the n-type region has a face exposed from the first gate interconnect on the side away from the n-type region in the second direction. In the second nanosheet group in the n-type region, the third nanosheet farthest from the p-type region has a face exposed from the second gate interconnect on the side away from the p-type region in the second direction. That is, the first gate interconnect does not protrude from the first nanosheet group toward the power line side, and the second gate interconnect does not protrude from the second nanosheet group toward the power line side. Also, in the first nanosheet group in the p-type region, the second nanosheet closest to the n-type region has a face exposed from the first gate interconnect on the side closer to the n-type region in the second direction. In the second nanosheet group in the n-type region, the fourth nanosheet closest to the p-type region has a face exposed from the second gate interconnect on the side closer to the p-type region in the second direction. That is, the first gate interconnect does not protrude from the first nanosheet group toward the second nanosheet group, and the second gate interconnect does not protrude from the second nanosheet group toward the first nanosheet group. This can reduce the size in the second direction of the semiconductor integrated circuit device, whereby a small-area layout structure can be achieved. 
     According to the present disclosure, a small-area layout structure can be achieved for a semiconductor integrated circuit device using forksheet FETs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are a plan view and a cross-sectional view, respectively, showing an example of the basic structure of a standard cell having forksheet FETs according to an embodiment. 
         FIG. 2A  is a plan view showing a layout structure of a 2-input NAND cell, and  FIG. 2B  is a circuit diagram of a 2-input NAND. 
         FIGS. 3A and 3B  are cross-sectional views of the 2-input NAND cell of  FIG. 2A . 
         FIG. 4A  is a plan view showing a layout structure of a tristate inverter cell, and 
         FIG. 4B  is a circuit diagram of a tristate inverter. 
         FIGS. 5A and 5B  are cross-sectional views of the tristate inverter cell of  FIG. 4A . 
         FIG. 6A  is a plan view showing a layout structure of an inverter cell, and  FIG. 6B  is a circuit diagram of an inverter. 
         FIG. 7A  is a plan view showing a layout structure of a 2-input NOR cell, and  FIG. 7B  is a circuit diagram of a 2-input NOR. 
         FIGS. 8A and 8B  are a plan view and a cross-sectional view, respectively, showing a basic structure of a standard cell having forksheet FETs according to an alteration. 
         FIGS. 9A and 9B  are a plan view and a cross-sectional view, respectively, showing a basic structure of a standard cell having forksheet FETs according to another alteration. 
         FIGS. 10A and 10B  are a plan view and a cross-sectional view, respectively, showing a basic structure of a forksheet FET. 
     
    
    
     DETAILED DESCRIPTION 
     An embodiment of the present disclosure will be described hereinafter with reference to the accompanying drawings. In the following embodiment, it is assumed that the semiconductor integrated circuit device includes a plurality of standard cells (hereinafter simply called cells as appropriate), and at least some of the standard cells include nanosheet field effect transistors (FETs). The nanosheet FET is a FET using a thin sheet (nanosheet) through which a current flows. Such a nanosheet is formed of silicon, for example. In the semiconductor integrated circuit device, it is assumed that some of the nanosheet FETs are forksheet FETs having a fork-shaped gate electrode. 
     In the present disclosure, a semiconductor layer portion formed on each end of a nanosheet to constitute a terminal that is to be the source or drain of a nanosheet FET is called a “pad.” Also, hereinafter, in the plan views such as  FIG. 1 , the horizontal direction is called an X direction (corresponding to the first direction), the vertical direction is called a Y direction (corresponding to the second direction), and the direction perpendicular to the substrate plane is called a Z direction (corresponding to the third direction). 
     First, the basic structure of the forksheet FET will be described. 
       FIGS. 10A-10B  are views showing a basic structure of a forksheet FET, where  FIG. 10A  is a plan view and  FIG. 10B  is a cross-sectional view taken along line Y-Y′ in  FIG. 10A . In the basic structure of  FIGS. 10A-10B , two transistors TR 1  and TR 2  are placed side by side with space S between them in the Y direction. A gate interconnect  531  that is to be the gate of the transistor TR 1  and a gate interconnect  532  that is to be the gate of the transistor TR 2  extend in the Y direction and are at the same position in the X direction. 
     A channel portion  521  that is to be the channel region of the transistor TR 1  and a channel portion  526  that is to be the channel region of the transistor TR 2  are constituted by nanosheets. In  FIGS. 10A-10B , the channel portions  521  and  526  are each constituted by three nanosheets overlapping one another as viewed in plan. Pads  522   a  and  522   b  that are to be the source and drain regions of the transistor TR 1  are formed on both sides of the channel portion  521  in the X direction. Pads  527   a  and  527   b  that are to be the source and drain regions of the transistor TR 2  are formed on both sides of the channel portion  526  in the X direction. The pads  522   a  and  522   b  are formed by epitaxial growth from the nanosheets constituting the channel portion  521 . The pads  527   a  and  527   b  are formed by epitaxial growth from the nanosheets constituting the channel portion  526 . 
     The gate interconnect  531  surrounds the peripheries of the nanosheets constituting the channel portion  521  in the Y and Z directions via a gate insulating film (not shown). Note however that the faces of the nanosheets constituting the channel portion  521  on the side closer to the transistor TR 2  in the Y direction are exposed, not covered with the gate interconnect  531 . That is, in the cross-sectional view of  FIG. 10B , the gate interconnect  531  does not cover the right side faces of the nanosheets constituting the channel portion  521  but covers the upper, lower, and left side faces of the nanosheets. The gate interconnect  531  protrudes from the nanosheets constituting the channel portion  521  by a length OL toward the side away from the transistor TR 2  in the Y direction. 
     The gate interconnect  532  surrounds the peripheries of the nanosheets constituting the channel portion  526  in the Y and Z directions via a gate insulating film (not shown). Note however that the faces of the nanosheets constituting the channel portion  526  on the side closer to the transistor TR 1  in the Y direction are exposed, not covered with the gate interconnect  532 . That is, in the cross-sectional view of  FIG. 10B , the gate interconnect  532  does not cover the left side faces of the nanosheets constituting the channel portion  526  but covers the upper, lower, and right side faces of the nanosheets. The gate interconnect  532  protrudes from the nanosheets constituting the channel portion  526  by a length OL toward the side away from the transistor TR 1  in the Y direction. 
     Here, the gate effective width Weff of each nanosheet is represented by 
       Weff=2× W+H  
 
     where W is the width (size in the Y direction) of the nanosheet, and H is the height (size in the Z direction) thereof. Since the channel portions  521  and  526  of the transistors TR 1  and TR 2  are each constituted by three nanosheets, the gate effective width of each of the transistors TR 1  and TR 2  is 
       3×(2× W+H ).
 
     In the structure of  FIGS. 10A-10B , the gate interconnect  531  does not protrude from the nanosheets constituting the channel portion  521  toward the transistor TR 2  in the Y direction. Also, the gate interconnect  532  does not protrude from the nanosheets constituting the channel portion  526  toward the transistor TR 1  in the Y direction. This can bring the transistors TR 1  and TR 2  closer to each other and thus achieve area reduction. 
     The number of nanosheets constituting the channel portion of each transistor is not limited to three. The channel portion may be constituted by one nanosheet, or may be constituted by a plurality of nanosheets overlapping each other as viewed in plan. Also, while the cross-sectional shape of the nanosheets is illustrated as rectangular in  FIG. 10B , it is not limited to this. For example, the shape may be square, circular, or oval. 
     The semiconductor integrated circuit device may include both forksheet FETs and nanosheet FETs where a gate interconnect surrounds the entire peripheries of nanosheets, in a mixed manner. 
     As used herein, “VDD” and “VSS” refer to the power supply voltages or the power supplies themselves. Also, as used herein, an expression indicating that widths, etc. are identical, such as the “same wiring width,” is to be understood as including a range of manufacturing variations. 
     Embodiment 
       FIGS. 1A-1B  are views showing a basic structure of a standard cell having forksheet FETs according to the embodiment, where  FIG. 1A  is a plan view and  FIG. 1B  is a cross-sectional view taken along line Y-Y′ in  FIG. 1A . In  FIG. 1A , CL defines the cell bounds of the standard cell, which also applies to the subsequent plan views. 
     The standard cell of  FIGS. 1A-1B  and other standard cells are arranged in the X direction with the cell bounds CL of adjacent standard cells touching each other, forming a cell row. A plurality of such cell rows are arranged in the Y direction with the cell bounds CL of standard cells in adjacent cell rows touching each other. Note that these cell rows are inverted vertically every other row. 
     As shown in  FIGS. 1A-1B , a power line  11  and a power line  12  extending in the X direction are formed on opposite ends of the standard cell in the Y direction. The power lines  11  and  12  are both buried power rails (BPRs) formed in a buried interconnect layer. The power line  11  supplies the power supply voltage VDD and the power line  12  supplies the power supply voltage VSS. The power lines  11  and  12  are shared by other cells arranged in line in the X direction, forming power lines extending between adjacent cell rows. 
     P-type transistors P 11 , P 12 , P 21 , and P 22  are formed in a p-type region on an N-well, and n-type transistors N 11 , N 12 , N 21 , and N 22  are formed in an n-type region on a P-substrate. The transistors P 11 , P 12 , N 11 , and N 12  are arranged in line in the Y direction, and the transistors P 21 , P 22 , N 21 , and N 22  are arranged in line in the Y direction. 
     The transistors P 11 , P 12 , P 21 , and P 22  have nanosheets  21   a ,  23   a ,  21   b , and  23   b , respectively, each formed of three sheets, as their channel portions. That is, the transistors P 11 , P 12 , P 21 , and P 22  are nanosheet FETs. 
     As shown in  FIG. 1A , pads  22   a ,  22   b , and  22   c  each made of an integral semiconductor layer connected to three sheets are formed on the left side of the nanosheets  21   a , between the nanosheets  21   a  and  21   b , and on the right side of the nanosheets  21   b , respectively, as viewed in the figure. The pads  22   a  and  22   b  are to be the source and drain regions of the transistor P 11 , and the pads  22   b  and  22   c  are to be the source and drain regions of the transistor P 21 . 
     Pads  24   a ,  24   b , and  24   c  each made of an integral semiconductor layer connected to three sheets are formed on the left side of the nanosheets  23   a , between the nanosheets  23   a  and  23   b , and on the right side of the nanosheets  23   b , respectively, as viewed in the figure. The pads  24   a  and  24   b  are to be the source and drain regions of the transistor P 12 , and the pads  24   b  and  24   c  are to be the source and drain regions of the transistor P 22 . 
     The transistors N 11 , N 12 , N 21 , and N 22  have nanosheets  26   a ,  28   a ,  26   b , and  28   b , respectively, each made of three sheets, as their channel portions. That is, the transistors N 11 , N 12 , N 21 , and N 22  are nanosheet FETs. 
     As shown in  FIG. 1A , pads  27   a ,  27   b , and  27   c  each made of an integral semiconductor layer connected to three sheets are formed on the left side of the nanosheets  26   a , between the nanosheets  26   a  and  26   b , and on the right side of the nanosheets  26   b , respectively, as viewed in the figure. The pads  27   a  and  27   b  are to be the source and drain regions of the transistor N 11 , and the pads  27   b  and  27   c  are to be the source and drain regions of the transistor N 21 . 
     Pads  29   a ,  29   b , and  29   c  each made of an integral semiconductor layer connected to three sheets are formed on the left side of the nanosheets  28   a , between the nanosheets  28   a  and  28   b , and on the right side of the nanosheets  28   b , respectively, as viewed in the figure. The pads  29   a  and  29   b  are to be the source and drain regions of the transistor N 12 , and the pads  29   b  and  29   c  are to be the source and drain regions of the transistor N 22 . 
     Gate interconnects  31  and  32  extending in parallel in the Y direction are formed in the p-type region. Dummy gate interconnects  35   a  and  35   b  are formed over the cell bounds CL on both sides of the gate interconnects  31  and  32  in the X direction. The gate interconnects  31  and  32  and the dummy gate interconnects  35   a  and  35   b , having the same width, are placed at the same pitch. 
     Gate interconnects  33  and  34  extending in parallel in the Y direction are formed in the n-type region. Dummy gate interconnects  35   c  and  35   d  are formed over the cell bounds CL on both sides of the gate interconnects  33  and  34  in the X direction. The gate interconnects  33  and  34  and the dummy gate interconnects  35   c  and  35   d , having the same width, are placed at the same pitch. 
     The gate interconnect  31  surrounds the peripheries of the nanosheets  21   a  of the transistor P 11  and the nanosheets  23   a  of the transistor P 12  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  31  is to be the gates of the transistors P 11  and P 12 . The gate interconnect  32  surrounds the peripheries of the nanosheets  21   b  of the transistor P 21  and the nanosheets  23   b  of the transistor P 22  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  32  is to be the gates of the transistors P 21  and P 22 . 
     The gate interconnect  33  surrounds the peripheries of the nanosheets  26   a  of the transistor N 11  and the nanosheets  28   a  of the transistor N 12  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  33  is to be the gates of the transistors N 11  and N 12 . The gate interconnect  34  surrounds the peripheries of the nanosheets  26   b  of the transistor N 21  and the nanosheets  28   b  of the transistor N 22  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  34  is to be the gates of the transistors N 21  and N 22 . 
     Here, the faces of the nanosheets  21   a  and  21   b  on the side away from the n-type region in the Y direction (the side closer to the power line  11 ) are exposed, not covered with the gate interconnects  31  and  32 . The faces of the nanosheets  23   a  and  23   b  on the side closer to the n-type region in the Y direction are exposed, not covered with the gate interconnects  31  and  32 . For example, the nanosheets  21   a  and  23   a  constitute the first nanosheet group, in which the nanosheets  21   a  correspond to the first nanosheet farthest from the n-type region and the nanosheets  23   a  correspond to the second nanosheet closest to the n-type region. 
     Also, the faces of the nanosheets  26   a  and  26   b  on the side closer to the p-type region in the Y direction are exposed, not covered with the gate interconnects  33  and  34 . The faces of the nanosheets  28   a  and  28   b  on the side away from the p-type region in the Y direction (the side closer to the power line  12 ) are exposed, not covered with the gate interconnects  33  and  34 . For example, the nanosheets  26   a  and  28   a  constitute the second nanosheet group, in which the nanosheets  28   a  correspond to the third nanosheet farthest from the P-type region and the nanosheets  26   a  correspond to the fourth nanosheet closest to the p-type region. 
     Based on such a basic structure, vias and interconnects (local interconnects and metal interconnects) for connection between transistors are formed, whereby a standard cell implementing a logical function is provided. 
     While the power lines  11  and  12  are buried power rails in this embodiment, the configuration is not limited to this. For example, the power lines may be formed in an upper metal interconnect layer. 
     Also, while each two transistors are arranged in the X direction in this embodiment, the configuration is not limited to this. For example, only one transistor may be placed in the X direction, or three or more transistors may be placed in the X direction. 
     Examples of standard cells implementing a logical function, formed based on the basic structure described above, will be described hereinafter. 
     Example 1: 2-Input NAND 
       FIG. 2A  is a plan view showing a layout structure of a 2-input NAND cell,  FIG. 2B  is a circuit diagram of a 2-input NAND,  FIG. 3A  is a cross-sectional view taken along line Y 1 -Y 1 ′ in  FIG. 2A , and  FIG. 3B  is a cross-sectional view taken along line Y 2 -Y 2 ′ in  FIG. 2A . 
     Local interconnects  41 ,  42 ,  43 ,  44 , and  45  extending in the Y direction are formed in a local interconnect layer. The local interconnect  41  is connected with the pads  22   a  and  24   a . The local interconnect  42  is connected with the pads  22   b  and  24   b  and also connected with the power line  11  through a via. The local interconnect  43  is connected with the pads  22   c ,  24   c ,  27   c , and  29   c . The local interconnect  44  is connected with the pads  27   a  and  29   a  and also connected with the power line  12  through a via. The local interconnect  45  is connected with the pads  27   b  and  29   b.    
     The gate interconnects  31  and  33  arranged in line in the Y direction are mutually connected through a bridge  36   a  formed between them. The gate interconnects  32  and  34  arranged in line in the Y direction are mutually connected through a bridge  36   b  formed between them. The bridges  36   a  and  36   b  are an example of gate connecting portions. 
     Metal interconnects  51 ,  52 , and  53  extending in the X direction are formed in an M 1  interconnect layer. The metal interconnect  51  is connected with the local interconnects  41  and  43  through vias. The metal interconnect  52  is connected with the gate interconnects  32  and  34  through a via, and the metal interconnect  53  is connected with the gate interconnects  31  and  33  through a via. The metal interconnects  51 ,  52 , and  53  correspond to output Y and inputs A and B, respectively, of the 2-input NAND. 
     Example 2: Tristate Inverter 
       FIG. 4A  is a plan view showing a layout structure of a tristate inverter cell,  FIG. 4B  is a circuit diagram of a tristate inverter,  FIG. 5A  is a cross-sectional view taken along line Y 1 -Y 1 ′ in  FIG. 4A , and  FIG. 5B  is a cross-sectional view taken along line Y 2 -Y 2 ′ in  FIG. 4A . 
     Local interconnects  61 ,  62 ,  63 ,  64 , and  65  extending in the Y direction are formed in a local interconnect layer. The local interconnect  61  is connected with the pads  22   a  and  24   a  and also connected with the power line  11  through a via. The local interconnect  62  is connected with the pads  22   b  and  24   b . The local interconnect  63  is connected with the pads  22   c ,  24   c ,  27   c , and  29   c . The local interconnect  64  is connected with the pads  27   a  and  29   a  and also connected with the power line  12  through a via. The local interconnect  65  is connected with the pads  27   b  and  29   b.    
     The gate interconnects  31  and  33  arranged in line in the Y direction are mutually connected through a bridge  37  formed between them. The gate interconnects  32  and  34  arranged in line in the Y direction are not mutually connected but kept separated from each other. 
     Metal interconnects  71 ,  72 ,  73 , and  74  extending in the X direction are formed in an M 1  interconnect layer. The metal interconnect  71  is connected with the gate interconnect  32  through a via. The metal interconnect  72  is connected with the gate interconnects  31  and  33  through a via. The metal interconnect  73  is connected with the gate interconnect  34  through a via. The metal interconnect  74  is connected with the local interconnect  63  through a via. The metal interconnects  71 ,  72 ,  73 , and  74  correspond to inputs NE, A, and E and output Y, respectively, of the tristate inverter. 
     Example 3: Inverter 
       FIG. 6A  is a plan view showing a layout structure of an inverter cell, and  FIG. 6B  is a circuit diagram of an inverter. This inverter cell is based on a basic structure where only one transistor is placed in the X direction. In this basic structure, assume that only the transistors P 11 , P 12 , N 11 , and N 12  in  FIGS. 1A-1B  are used. 
     Local interconnects  81 ,  82 , and  83  extending in the Y direction are formed in a local interconnect layer. The local interconnect  81  is connected with the pads  22   a  and  24   a  and also connected with the power line  11  through a via. The local interconnect  82  is connected with the pads  22   b ,  24   b ,  27   b , and  29   b . The local interconnect  83  is connected with the pads  27   a  and  29   a  and also connected with the power line  12  through a via. 
     The gate interconnects  31  and  33  arranged in line in the Y direction are mutually connected through a bridge  38  formed between them. 
     Metal interconnects  91  and  92  extending in the X direction are formed in an M 1  interconnect layer. The metal interconnect  91  is connected with the gate interconnects  31  and  33  through a via. The metal interconnect  92  is connected with the local interconnect  82  through a via. The metal interconnects  91  and  92  correspond to input A and output Y, respectively, of the inverter. 
     Example 4: 2-Input NOR 
       FIG. 7A  is a plan view showing a layout structure of a 2-input NOR cell, and  FIG. 7B  is a circuit diagram of a 2-input NOR. 
     Local interconnects  101 ,  102 ,  103 ,  104 , and  105  extending in the Y direction are formed in a local interconnect layer. The local interconnect  101  is connected with the pads  22   a  and  24   a  and also connected with the power line  11  through a via. The local interconnect  102  is connected with the pads  22   b  and  24   b . The local interconnect  103  is connected with the pads  22   c ,  24   c ,  27   c , and  29   c . The local interconnect  104  is connected with the pads  27   a  and  29   a . The local interconnect  105  is connected with the pads  27   b  and  29   b  and also connected with the power line  12  through a via. 
     The gate interconnects  31  and  33  arranged in line in the Y direction are mutually connected through a bridge  39   a  formed between them. The gate interconnects  32  and  34  arranged in line in the Y direction are mutually connected through a bridge  39   b  formed between them. 
     Metal interconnects  111 ,  112 , and  113  extending in the X direction are formed in an M 1  interconnect layer. The metal interconnect  111  is connected with the gate interconnects  31  and  33  through a via. The metal interconnect  112  is connected with the gate interconnects  32  and  34  through a via. The metal interconnect  113  is connected with the local interconnects  103  and  104  through vias. The metal interconnects  111 ,  112 , and  113  correspond to inputs B and A and output Y, respectively, of the 2-input NOR. 
     According to this embodiment, in the standard cell having forksheet FETs, the faces of the nanosheets  21   a  and  21   b  on the side away from the n-type region in the Y direction are exposed from the gate interconnects  31  and  32 . In other words, the gate interconnects  31  and  32  do not protrude from the nanosheets  21   a  and  21   b  toward the power line  11  side in the Y direction. Also, the faces of the nanosheets  28   a  and  28   b  on the side away from the p-type region in the Y direction are exposed from the gate interconnects  33  and  34 . In other words, the gate interconnects  33  and  34  do not protrude from the nanosheets  28   a  and  28   b  toward the power line  12  side in the Y direction. Therefore, in the boundary portion between cells adjacent in the Y direction, the space required between nanosheets of one of the cells and nanosheets of the other cell can be smaller. 
     Also, the faces of the nanosheets  23   a  and  23   b  on the side closer to the n-type region in the Y direction are exposed from the gate interconnects  31  and  32 . In other words, the gate interconnects  31  and  32  do not protrude from the nanosheets  23   a  and  23   b  toward the n-type region. Also, the faces of the nanosheets  26   a  and  26   b  on the side closer to the p-type region in the Y direction are exposed from the gate interconnects  33  and  34 . In other words, the gate interconnects  33  and  34  do not protrude from the nanosheets  26   a  and  26   b  toward the p-type region. Therefore, in the boundary portion between the p-type region and the n-type region, the space required between nanosheets in the p-type region and nanosheets in the n-type region can be smaller. 
     It is therefore possible to effectively reduce the size in the Y direction of the semiconductor integrated circuit device having forksheet FETs. 
     (Alteration 1) 
       FIGS. 8A-8B  are views showing a basic structure of a standard cell having forksheet FETs, where  FIG. 8A  is a plan view and  FIG. 8B  is a cross-sectional view taken along line Y-Y′ in  FIG. 8A . 
     In the example of  FIGS. 8A-8B , transistors are placed in three rows in the Y direction in a p-type region on an N-well, and transistors are placed in three rows in the Y direction in an n-type region on a P-substrate. That is, p-type transistors P 11 , P 12 , P 13 , P 21 , P 22 , and P 23  are formed in the p-type region, and n-type transistors N 11 , N 12 , N 13 , N 21 , N 22 , and N 23  are formed in the n-type region. The transistors P 11 , P 12 , P 13 , N 11 , N 12 , and N 13  are arranged in line in the Y direction, and the transistors P 21 , P 22 , P 23 , N 21 , N 22 , and N 23  are arranged in line in the Y direction. 
     The transistors P 11 , P 12 , P 13 , P 21 , P 22 , and P 23  have nanosheets  121   a ,  122   a ,  123   a ,  121   b ,  122   b , and  123   b , respectively, each made of three sheets, as their channel portions. The transistors N 11 , N 12 , N 13 , N 21 , N 22 , and N 23  have nanosheets  124   a ,  125   a ,  126   a ,  124   b ,  125   b , and  126   b , respectively, each made of three sheets, as their channel portions. 
     Gate interconnects  131  and  132  extending in parallel in the Y direction are formed in the p-type region. The gate interconnect  131  surrounds the peripheries of the nanosheets  121   a  of the transistor P 11 , the nanosheets  122   a  of the transistor P 12 , and the nanosheets  123   a  of the transistor P 13  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  131  is to be the gates of the transistors P 11 , P 12 , and P 13 . The gate interconnect  132  surrounds the peripheries of the nanosheets  121   b  of the transistor P 21 , the nanosheets  122   b  of the transistor P 22 , and the nanosheets  123   b  of the transistor P 23  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  132  is to be the gates of the transistors P 21 , P 22 , and P 23 . 
     Gate interconnects  133  and  134  extending in parallel in the Y direction are formed in the n-type region. The gate interconnect  133  surrounds the peripheries of the nanosheets  124   a  of the transistor N 11 , the nanosheets  125   a  of the transistor N 12 , and the nanosheets  126   a  of the transistor N 13  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  133  is to be the gates of the transistors N 11 , N 12 , and N 13 . The gate interconnect  134  surrounds the peripheries of the nanosheets  124   b  of the transistor N 21 , the nanosheets  125   b  of the transistor N 22 , and the nanosheets  126   b  of the transistor N 23  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  134  is to be the gates of the transistors N 21 , N 22 , and N 23 . 
     Here, the faces of the nanosheets  121   a  and  121   b  on the side away from the n-type region in the Y direction (the side closer to the power line  11 ) are exposed, not covered with the gate interconnects  131  and  132 . The faces of the nanosheets  123   a  and  123   b  on the side closer to the n-type region in the Y direction are exposed, not covered with the gate interconnects  131  and  132 . For example, the nanosheets  121   a ,  122   a , and  123   a  constitute the first nanosheet group, in which the nanosheets  121   a  correspond to the first nanosheet farthest from the n-type region and the nanosheets  123   a  correspond to the second nanosheet closest to the n-type region. 
     Also, the faces of the nanosheets  124   a  and  124   b  on the side closer to the p-type region in the Y direction are exposed, not covered with the gate interconnects  133  and  134 . The faces of the nanosheets  126   a  and  126   b  on the side away from the p-type region in the Y direction (the side closer to the power line  12 ) are exposed, not covered with the gate interconnects  133  and  134 . For example, the nanosheets  124   a ,  125   a , and  126   a  constitute the second nanosheet group, in which the nanosheets  126   a  correspond to the third nanosheet farthest from the p-type region and the nanosheets  124   a  correspond to the fourth nanosheet closest to the p-type region. 
     The nanosheets  122   a  and  122   b  are entirely surrounded by the gate interconnects  131  and  132 , and the nanosheets  125   a  and  125   b  are entirely surrounded by the gate interconnects  133  and  134 . 
     In this alteration, also, similar effects to those obtained in the above embodiment are obtained. That is, in the boundary portion between cells adjacent in the Y direction, the space required between nanosheets of one of the cells and nanosheets of the other cell can be smaller. Also, in the boundary portion between the p-type region and the n-type region, the space required between nanosheets in the p-type region and nanosheets in the n-type region can be smaller. It is therefore possible to effectively reduce the size in the Y direction of the semiconductor integrated circuit device having forksheet FETs. 
     (Alteration 2) 
       FIGS. 9A-9B  are views showing a basic structure of a standard cell having forksheet FETs, where  FIG. 9A  is a plan view and  FIG. 9B  is a cross-sectional view taken along line Y-Y′ in  FIG. 9A . 
     In the example of  FIGS. 9A-9B , transistors are placed in four rows in the Y direction in a p-type region on an N-well, and transistors are placed in four rows in the Y direction in an n-type region on a P-substrate. That is, p-type transistors P 11 , P 12 , P 13 , P 14 , P 21 , P 22 , P 23 , and P 24  are formed in the p-type region, and n-type transistors N 11 , N 12 , 
     N 13 , N 14 , N 21 , N 22 , N 23 , and N 24  are formed in the n-type region. The transistors P 11 , P 12 , P 13 , P 14 , N 11 , N 12 , N 13 , and N 14  are arranged in line in the Y direction, and the transistors P 21 , P 22 , P 23 , P 24 , N 21 , N 22 , N 23 , and N 24  are arranged in line in the Y direction. 
     The transistors P 11 , P 12 , P 13 , P 14 , P 21 , P 22 , P 23 , and P 24  have nanosheets  221   a ,  222   a ,  223   a ,  224   a ,  221   b ,  222   b ,  223   b , and  224   b , respectively, each made of three sheets, as their channel portions. The transistors N 11 , N 12 , N 13 , N 14 , N 21 , N 22 , N 23 , and N 24  have nanosheets  225   a ,  226   a ,  227   a ,  228   a ,  225   b ,  226   b ,  227   b , and  228   b , respectively, each made of three sheets, as their channel portions. 
     Gate interconnects  231  and  232  extending in parallel in the Y direction are formed in the p-type region. The gate interconnect  231  surrounds the peripheries of the nanosheets  221   a  of the transistor P 11  and the nanosheets  222   a  of the transistor P 12  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  231  is to be the gates of the transistors P 11  and P 12 . The gate interconnect  232  surrounds the peripheries of the nanosheets  221   b  of the transistor P 21  and the nanosheets  222   b  of the transistor P 22  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  232  is to be the gates of the transistors P 21  and P 22 . 
     Also, gate interconnects  233  and  234  extending in parallel in the Y direction are formed in the p-type region. The gate interconnect  233  is at the same position in the X direction as the gate interconnect  231 , and the gate interconnect  234  is at the same position in the X direction as the gate interconnect  232 . The gate interconnect  233  surrounds the peripheries of the nanosheets  223   a  of the transistor P 13  and the nanosheets  224   a  of the transistor P 14  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  233  is to be the gates of the transistors P 13  and P 14 . The gate interconnect  234  surrounds the peripheries of the nanosheets  223   b  of the transistor P 23  and the nanosheets  224   b  of the transistor P 24  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  234  is to be the gates of the transistors P 23  and P 24 . 
     Gate interconnects  235  and  236  extending in parallel in the Y direction are formed in the n-type region. The gate interconnect  235  surrounds the peripheries of the nanosheets  225   a  of the transistor N 11  and the nanosheets  226   a  of the transistor N 12  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  235  is to be the gates of the transistors N 11  and N 12 . The gate interconnect  236  surrounds the peripheries of the nanosheets  225   b  of the transistor N 21  and the nanosheets  226   b  of the transistor N 22  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  236  is to be the gates of the transistors N 21  and N 22 . 
     Also, gate interconnects  237  and  238  extending in parallel in the Y direction are formed in the n-type region. The gate interconnect  237  is at the same position in the X direction as the gate interconnect  235 , and the gate interconnect  238  is at the same position in the X direction as the gate interconnect  236 . The gate interconnect  237  surrounds the peripheries of the nanosheets  227   a  of the transistor N 13  and the nanosheets  228   a  of the transistor N 14  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  237  is to be the gates of the transistors N 13  and N 14 . The gate interconnect  238  surrounds the peripheries of the nanosheets  227   b  of the transistor N 23  and the nanosheets  228   b  of the transistor N 24  in the Y and Z directions via a gate insulating film (not shown). The gate interconnect  238  is to be the gates of the transistors N 23  and N 24 . 
     Here, the faces of the nanosheets  221   a  and  221   b  on the side away from the n-type region in the Y direction (the side closer to the power line  11 ) are exposed, not covered with the gate interconnects  231  and  232 . The faces of the nanosheets  224   a  and  224   b  on the side closer to the n-type region in the Y direction are exposed, not covered with the gate interconnects  233  and  234 . For example, the nanosheets  221   a ,  222   a ,  223   a , and  224   a  constitute the first nanosheet group, in which the nanosheets  221   a  correspond to the first nanosheet farthest from the n-type region and the nanosheets  224   a  correspond to the second nanosheet closest to the n-type region. The gate interconnects  231  and  233  correspond to the first gate interconnect, although in this alteration, the first gate interconnect is separated into two at a position between the nanosheets  222   a  and  223   a.    
     Also, the faces of the nanosheets  225   a  and  225   b  on the side closer to the p-type region in the Y direction are exposed, not covered with the gate interconnects  235  and  236 . The faces of the nanosheets  228   a  and  228   b  on the side away from the n-type region in the Y direction (the side closer to the power line  12 ) are exposed, not covered with the gate interconnects  237  and  238 . For example, the nanosheets  225   a ,  226   a ,  227   a , and  228   a  constitute the second nanosheet group, in which the nanosheets  228   a  correspond to the third nanosheet farthest from the p-type region and the nanosheets  225   a  correspond to the fourth nanosheet closest to the p-type region. The gate interconnects  235  and  237  correspond to the second gate interconnect, although in this alteration, the second gate interconnect is separated into two at a position between the nanosheets  226   a  and  227   a.    
     In this alteration, also, similar effects to those obtained in the above embodiment are obtained. That is, in the boundary portion between cells adjacent in the Y direction, the space required between nanosheets of one of the cells and nanosheets of the other cell can be smaller. Also, in the boundary portion between the p-type region and the n-type region, the space required between nanosheets in the p-type region and nanosheets in the n-type region can be smaller. It is therefore possible to effectively reduce the size in the Y direction of the semiconductor integrated circuit device having forksheet FETs. 
     Moreover, in this alteration, the faces of the nanosheets  222   a  and  222   b  on the side opposed to the nanosheets  223   a  and  223   b  are exposed, not covered with the gate interconnects  231  and  232 . The faces of the nanosheets  223   a  and  223   b  on the side opposed to the nanosheets  222   a  and  222   b  are exposed, not covered with the gate interconnects  233  and  234 . For example, the nanosheets  222   a  and  223   a  correspond to the fifth and sixth nanosheets adjacent to each other in the Y direction lying between the first and second nanosheets in the first nanosheet group. 
     Also, the faces of the nanosheets  226   a  and  226   b  on the side opposed to the nanosheets  227   a  and  227   b  are exposed, not covered with the gate interconnects  235  and  236 . The faces of the nanosheets  227   a  and  227   b  on the side opposed to the nanosheets  226   a  and  226   b  are exposed, not covered with the gate interconnects  237  and  238 . For example, the nanosheets  226   a  and  227   a  correspond to the seventh and eighth nanosheets adjacent to each other in the Y direction lying between the third and fourth nanosheets in the second nanosheet group. 
     With the configuration described above, since the gate interconnects  231  and  233  are separated, different signals can be supplied to the gates between the transistors P 11  and P 12  and the transistors P 13  and P 14 . Since the gate interconnects  232  and  234  are separated, different signals can be supplied to the gates between the transistors P 21  and P 22  and the transistors P 23  and P 24 . Also, since the gate interconnects  235  and  237  are separated, different signals can be supplied to the gates between the transistors N 11  and N 12  and the transistors N 13  and N 14 . Since the gate interconnects  236  and  238  are separated, different signals can be supplied to the gates between the transistors N 21  and N 22  and the transistors N 23  and N 24 . This enhances the degree of freedom of configurable logical circuits. 
     In addition, only small space is required between the transistors P 12  and P 22  and the transistors P 13  and P 23 , i.e., between the nanosheets  222   a  and  222   b  and the nanosheets  223   a  and  223   b . Also, only small space is required between the transistors N 12  and N 22  and the transistors N 13  and N 23 , i.e., between the nanosheets  226   a  and  226   b  and the nanosheets  227   a  and  227   b . It is therefore possible to further effectively reduce the size in the Y direction of the semiconductor integrated circuit device having forksheet FETs. 
     In the configuration of  FIGS. 9A-9B , it is acceptable to form the gate interconnects  231  and  233 , the gate interconnects  232  and  234 , the gate interconnects  235  and  237 , and the gate interconnects  236  and  238  as respective integral interconnects, not separated. 
     According to the present disclosure, a small-area layout structure can be achieved for a semiconductor integrated circuit device using forksheet FETs. The present disclosure is therefore useful for downsizing and improved integrity of semiconductor chips.