Patent Publication Number: US-2006010282-A1

Title: Method and apparatus to boot a system by monitoring an operating status of a NAND flash memory

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS  
      This application claims priority from Korean Patent Application No. 2004-53367, filed on Jul. 9, 2004, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.  
     BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The present general inventive concept relates to a system including a NAND flash memory. More particularly, the general inventive concept relates to a method and apparatus to boot a system including a NAND flash memory, which monitors an operating status of the NAND flash memory using a signal monitor to prevent the NAND flash memory from being erroneously operated and to safely boot the system.  
      2. Description of the Related Art  
      A boot code, such as a BIOS (Basic Input/Output System), used to boot a system, is generally stored in a ROM (Read Only Memory). However, the boot code can also be stored in a nonvolatile memory, such as a flash memory. A NAND flash memory may be preferable, since it is less expensive and physically smaller than A NOR flash memory.  
       FIG. 1  is a block diagram illustrating a conventional system  150  including a NAND flash memory  120 , and  FIG. 2  is a timing diagram illustrating signals for booting the conventional system  150  of  FIG. 1 . The process of booting the conventional system  150  including the NAND flash memory  120  will now be explained with reference to  FIGS. 1 and 2 .  
      In order to boot the conventional system  150  using the NAND flash memory  120 , a boot code must be stored in the NAND flash memory  120 . When the system is powered on, a NAND flash memory controller  102  holds the operation of a CPU core  101 . Simultaneously, the NAND flash memory controller  102  outputs CLE (Command Latch enable), CE# (Chip Enable), WE# (Write Enable) and ALE (Address Latch Enable) signals in addition to a command code OOH and start address to the NAND flash memory  120  through a line  106 . Here, “#” represents “active low” and refers to a signal that is active when it is at a low level (i.e.,  0 ).  
      The NAND flash memory  120  outputs a signal R/B# through a line  108  and sequentially outputs a boot code after a TR period  201  to the NAND flash memory controller  102 . The NAND flash memory controller  102  then stores the boot code in an internal memory  103  of the conventional system  150 . Then, the NAND flash memory controller  102  cancels the hold of the CPU core  101  so that the CPU core  101  reads the boot code from the internal memory  103  and executes the boot code. Signals in the conventional system  150  are transmitted through an internal bus  105 , an interface  104 , and an external bus  110  having a line  107 .  
      However, the conventional system  150  has the problem that when a booting command is erroneously issued while the NAND flash memory  120  storing the boot code is not set in the system (when the system is reset, for example), the system  150  does not operate because the CPU core  101  is on hold. In other words, the system is in a state which does not allow for even basic debugging using an emulator.  
     SUMMARY OF THE INVENTION  
      The present general inventive concept provides a system and method of monitoring an operating status of a NAND flash memory using a signal monitor and booting a system including the NAND flash memory through an external memory when the NAND flash memory does not operate normally such that a boot code used to boot the system cannot be transmitted to an internal memory of the system.  
      The present general inventive concept can set a reset address to a specific address of the internal memory when the NAND flash memory does not operate normally to enable debugging for erroneous operations, to thereby improve efficiency of circuit development.  
      Additional aspects and advantages of the present general inventive concept will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the general inventive concept.  
      The foregoing and/or other aspects and advantages of the present general inventive concept are achieved by providing a system comprising a NAND flash memory to store a boot code used to boot the system, an internal memory to store the boot code transmitted from the NAND flash memory, a NAND flash memory controller to control the transmission of the boot code from the NAND flash memory to the internal memory, a CPU core to execute the boot code stored in the internal memory, and a signal monitor to monitor an operating status of the NAND flash memory to boot the system. The NAND flash memory controller holds operation of the CPU core until the boot code is stored in the internal memory.  
      The signal monitor may be included in the NAND flash memory controller.  
      The signal monitor can monitor the operating status of the NAND flash memory by monitoring a status of signals transmitted between the NAND flash memory controller and the NAND flash memory. The signal monitor can monitor the operating status of the NAND flash memory for a plurality of predetermined periods. The predetermined periods may include a first period during which the NAND flash memory controller outputs a command and an address to the NAND flash memory, a second period during which the NAND flash memory interprets the command and the address received from the NAND flash memory controller, a third period during which the NAND flash memory prepares for execution based on the command and the address received from the NAND flash memory controller, and a fourth period during which the boot code is read from the NAND flash memory by the NAND flash memory controller.  
      The signal monitor may transmit an overtime error signal to the NAND flash memory controller when the second period or third period exceeds a predetermined length of time.  
      The NAND flash memory controller may generate an interrupt upon receiving the overtime error signal. When the interrupt is generated, the NAND flash memory controller may set a specific address of the internal memory to a reset address for debugging and permits the CPU core to operate.  
      The system may further comprise an external memory to store at least the boot code, and an external memory controller to control the external memory. The external memory controller may set a specific address of the external memory to a reset address, transmit the reset address to the NAND flash memory controller, and permit the CPU core to operate when the interrupt is generated by the NAND flash memory controller.  
      The foregoing and/or other aspects and advantages of the present general inventive concept are also achieved by providing a method of booting a system including a NAND flash memory, comprising preparing the NAND flash memory storing a boot code, monitoring an operating status of the NAND flash memory to transmit the boot code, reading and storing the boot code when the NAND flash memory operates normally and holding the operation of a CPU core while the boot code is read and stored, and executing the boot code.  
      The foregoing and/or other aspects and advantages of the present general inventive concept are also achieved by providing a NAND flash memory controller comprising a signal monitor that monitors signals transmitted between a NAND flash memory and the NAND flash memory controller to boot a system to monitor an operating status of the NAND flash memory. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
      These and/or other aspects and advantages of the present general inventive concept will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:  
       FIG. 1  is a block diagram illustrating a conventional system including a NAND flash memory;  
       FIG. 2  is a timing diagram illustrating signals for booting the conventional system of  FIG. 1 ;  
       FIG. 3  is a block diagram illustrating a system including a signal monitor according to an embodiment of the present general inventive concept;  
       FIG. 4  is a timing diagram illustrating signals used to boot the system of  FIG. 3 ;  
       FIG. 5  is a block diagram illustrating a system including a signal monitor according to another embodiment of the present general inventive concept; and  
       FIG. 6  is a flow chart illustrating a method of booting a system according to an embodiment of the present general inventive concept. 
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
      The present invention will now be described more fully with reference to the accompanying drawings, in which exemplary embodiments of the general inventive concept are shown. The general inventive concept may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. Throughout the drawings, like reference numerals refer to like elements.  
       FIG. 3  is a block diagram illustrating a system  350  including a signal monitor  330  according to an embodiment of the present general inventive concept, and  FIG. 4  is a timing diagram of signals used to boot the system  350  of  FIG. 3 . Components of the system  350  will now be explained in detail with reference to  FIG. 3 .  
      A controller  300  includes a CPU core  301 , a NAND flash memory controller  302 , an internal memory  303 , an interface  304 , and the signal monitor  330 . Signals in the system  350  are transmitted through an internal bus  305 , the interface  304 , and an external bus  310 . The signals in the system  350  may also be transmitted on lines  306 ,  307 ,  308 , or  331 .  
      The NAND flash memory controller  302  issues a hold command to the CPU core  301  of the controller  300  while a boot code is transmitted to the internal memory  303 . The CPU core  301  executes the boot code stored in the internal memory  303  when the hold command is removed.  
      The NAND flash memory controller  302  includes a status register  302   a . When the system  350  is reset, the NAND flash memory controller  302  holds the operation of the CPU core  301  and transmits the boot code from a NAND flash memory  320  to the internal memory  303 . When the transmission of the boot code is complete, the NAND flash memory controller  302  removes the hold from the CPU core  301  so that the CPU core  301  can execute the boot code.  
      When an overtime error signal is transmitted from the signal monitor  330  to the NAND flash memory controller  302 , the NAND flash memory controller  302  generates an interrupt and sets a specific address of the internal memory  303  to a reset address to enable debugging. The internal memory  303  receives the boot code from the NAND flash memory  320  and stores the boot code.  
      The signal monitor  330  monitors an operating status of the NAND flash memory  320 . Specifically, the signal monitor  330  monitors a status of signals (CLE, CE#, WE#, ALE, R/B# and RE signals illustrated in  FIG. 4 , for instance) transmitted between the NAND flash memory controller  302  and NAND flash memory  320 . A process of monitoring the operating status of the NAND flash memory  320  to boot the system will now be explained in more detail.  
      The signal monitor  330  monitors the operating status of the NAND flash memory  320  during predetermined periods t 1 , t 2 , t 3 , and t 4  illustrated in  FIG. 4 . The predetermined periods include a first period t 1  during which the NAND flash memory controller  302  outputs a command and an address to the NAND flash memory  320 , a second period t 2  during which the NAND flash memory  320  interprets the command and the address received from the NAND flash memory controller  302 , a third period t 3  during which the NAND flash memory  320  prepares for execution based on the command and the address received from the NAND flash memory controller  302 , and a fourth period t 4  during which the boot code (that is, data) is read from the NAND flash memory  302  by the NAND flash memory controller  302 .  
      Referring to  FIG. 4 , the signal R/B# falls after the second period t 2  following a falling edge  400  of the signal ALE. The signal R/B# then rises after the third period t 3 . The operating status of the NAND flash memory  320  can be monitored by monitoring a status of signals during certain periods. The present general inventive concept uses the periods t 2  and t 3  to monitor the operating status of the NAND flash memory  320 . Specifically, when the status of the signals R/B# and RE# do not change during the period t 2  or t 3 , the signal monitor  330  determines that the system  350  is operating erroneously or the NAND flash memory  320  is not present in the system  350 , and thus follow-up measures are taken.  
      The follow-up measures can include setting a specific address of the internal memory  303  to a reset address for debugging (in the system of  FIG. 3 ), setting a specific address of an external memory to the reset address to boot the system through the external memory or executing a failure diagnosis program, which will be explained below.  
      The signal monitor  330  transmits an overtime error signal to the NAND flash memory controller  302  when the period t 2  or t 3  exceeds a predetermined length of time. Then, the NAND flash memory controller  302  generates an interrupt and sets a specific bit of the status register  302   a  to “1” or “0” to indicate that an error has occurred and that follow-up measures are being taken.  
      While  FIG. 3  illustrates that the signal monitor  330  and NAND flash memory controller  302  are separate components, the signal monitor  330  can be included in the NAND flash memory controller  302 .  
      The NAND flash memory  320  stores the boot code used to boot the system  350 . The boot code is transmitted between the controller  300  and NAND flash memory  320  through an external bus  310 .  
       FIG. 5  is a block diagram illustrating a system  550  including a signal monitor  502   a  according to another embodiment of the present general inventive concept. The system  550  of  FIG. 5  differs from the system  350  of  FIG. 3  in that the signal monitor  502   a  is integrated into a NAND flash memory controller  502 , and an external memory  531  and an external memory controller  530  are added to the system  550 . Only the added components  502   a ,  531 , and  530  will be explained, since the basic operation of the system  550  is identical to that of the system  350  of  FIG. 3 .  
      Referring to  FIG. 5 , the external memory  531  stores the boot code used to boot the system  550 . The external memory  531  can store a failure diagnosis program that is executable when a NAND flash memory  520  is erroneously operated.  
      When the NAND flash memory controller  502  generates an interrupt, the external memory controller  530  sets a specific address of the external memory  531  to a reset address, transmits the reset address to the NAND flash memory controller  502 , and requests the NAND flash memory controller  502  to permit a CPU core  501  to operate. Accordingly, the CPU core  501  can execute code stored in the external memory  531 , for example, the boot code or the failure diagnosis program.  
      Consequently, the system  550  of  FIG. 5  boots through the external memory  531  while the system  350  of  FIG. 3  allows debugging through allocation of the reset address to the internal memory  303 .  
       FIG. 6  is a flow chart illustrating a method of booting a system ( 350  or  550 ), according to an embodiment of the present general inventive concept. The method will now be explained in detail with reference to  FIGS. 3, 4 ,  5 , and  6 .  
      First, the NAND flash memory ( 320  or  520 ) storing the boot code is prepared in operation S 600 . The signal monitor ( 330  or  502   a ) monitors signals transmitted between the NAND flash memory controller ( 302  or  502 ) and the NAND flash memory ( 320  or  520 ) during a predetermined period (including the first, second, third, and fourth periods t 1 , t 2 , t 3 , and t 4 ) in order to transmit the boot code to the internal memory ( 303  or  503 ) in operation S 610 . The NAND flash memory controller ( 302  or  502 ) transmits a hold command to the CPU core ( 301  or  501 ) to temporarily hold the operation of the CPU core ( 301  or  501 ).  
      If the signals are normally exchanged between the NAND flash memory controller ( 302  or  502 ) and NAND flash memory ( 320  or  520 ) during the first, second, and third periods t 1 , t 2 , and t 3 , the boot code is transmitted from the NAND flash memory ( 320  or  520 ) to the internal memory ( 303  or  503 ) during the fourth period t 4  in operation S 630 . Then, the NAND flash memory controller ( 302  or  502 ) removes the hold command used to hold the CPU core ( 301  or  501 ), and thus the CPU core ( 301  or  501 ) executes the boot code stored in the internal memory ( 303  or  503 ) in operation S 640 .  
      When it is determined that one of the second and third periods t 2  and t 3  exceeds a predetermined length of time in operation S 620 , the signal monitor ( 330  or  502   a ) generates an overtime error signal and transmits the overtime error signal to the NAND flash memory controller ( 302  or  502 ) in operation S 650 .  
      When the NAND flash memory controller ( 302  or  502 ) receives the overtime error signal, the NAND flash memory controller  502  sets a specific address of the external memory  531  to the reset address, notifies the CPU core  501  of the reset address, and cancels the hold command of the CPU core  501  in operation S 660 . Then, the CPU core  501  executes the boot code stored in the external memory  531  according to the reset address.  
      As described above, a specific address of the internal memory ( 303  or  503 ) rather than the external memory  531  can be allocated to the reset address for debugging in the operation S 660 .  
      While the present general inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present general inventive concept as defined by the following claims.  
      As described above, the present general inventive concept monitors an operating status of a NAND flash memory using a signal monitor and, when the NAND flash memory cannot normally transmit a boot code, executes the boot code using a separate external memory to cope more reliably with the abnormal state of the NAND flash memory. Furthermore, the present general inventive concept stores a program used when the system is in the abnormal state in addition to the boot code in the external memory, to cope with the abnormal state of the system and improve efficiency in board development. The NAND flash memory may be used in a BIOS chip, a memory stick, a memory card, etc.  
      Although a few embodiments of the present general inventive concept have been shown and described, it will be appreciated by those skilled in the art that changes may be made in these embodiments without departing from the principles and spirit of the general inventive concept, the scope of which is defined in the appended claims and their equivalents.