Patent Publication Number: US-9899936-B2

Title: Offset voltage generator and method for generating an offset voltage of three-phase inverter

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 10-2015-0052598, filed on Apr. 14, 2015, which is hereby incorporated by reference in its entirety. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to an offset voltage generator and a method for generating an offset voltage for controlling continuous modulation and discontinuous modulation of a three-phase inverter. 
     Description of the Related Art 
     As power semiconductor technology evolves, it has become easier to implement variable voltage and variable frequency (VVVF) driver by using power devices that can be switched at high speed. A voltage source inverter that typically receives DC voltage source to generate AC variable voltage source is commonly employed as a circuit for generating variable voltage variable frequency. Such a voltage source inverter is commonly employed by energy storage system (ESS), PV inverter, motor drive technologies. 
     In modulating voltage generated by such a voltage source inverter, a variety of types of modulation schemes may be employed. One of the most commonly used modulation scheme is pulse width modulation (PWM) scheme. The PWM scheme may be divided into continuous modulation scheme and discontinuous modulation scheme. Examples of the continuous modulation mode may include sinusoidal PWM (SPWM), space vector PWM (SVPWM), etc. Examples of the discontinuous modulation mode may include 60° discontinuous PWM (DPWM) for reducing switching loss of a power semiconductor. 
     In such continuous or discontinuous modulation modes, an offset voltage is compared to a carrier wave such as a triangular wave to modulate voltage. In doing so, different offset voltages are used in the continuous and discontinuous modulation modes. In the related art, there is a problem in that when a three-phase inverter is switched from the continuous modulation mode to the discontinuous modulation mode, an offset voltage for the discontinuous modulation mode has to be calculated according to a modulation index ML In addition, according to existing voltage modulation scheme using offset voltage, offset voltage is continuously introduced even in a period where the offset voltage is not necessary, and thus zero sequence voltage always exists in the inverter. 
     SUMMARY 
     It is an aspect of some embodiments of the present disclosure to provide an offset voltage generator and a method for generating an offset voltage of a three-phase inverter that allow the voltage modulation mode of the three-phase inverter to easily switch from a continuous modulation mode to a discontinuous modulation mode without any additional calculating process. 
     It is another aspect of some embodiments of the present disclosure to provide an offset voltage generator and a method for generating an offset voltage of a three-phase inverter that adjust the discontinuous modulation period, such that total harmonic distortion (THD) can be reduced in a period where the modulation index is low compared to the discontinuous modulation scheme in the related art, and switching loss can be reduced in a period where the modulation index is high compared to the continuous modulation scheme in the related art. 
     It is yet another aspect of some embodiments of the present disclosure to provide an offset voltage generator and a method for generating an offset voltage of a three-phase inverter that generate an offset voltage having the minimum (root mean square) RMS such that unnecessary zero sequence voltage can be reduced. 
     Other objects of the present disclosure are not limited to the above-described object and other objects and advantages can be appreciated by the following description described with reference to the embodiments of the present disclosure. Further, it will be easily appreciated that the objects and advantages of the present disclosure can be realized by means and a combination thereof recited in the appended claims. 
     In accordance with one aspect of some embodiments of the present disclosure, an offset voltage generator includes: a first limiter configured to compare a first phase-voltage signal with a maximum limit value and a minimum limit value to output a first limit-voltage signal; a second limiter configured to compare a second phase-voltage signal with the maximum limit value and the minimum limit value to output a second limit-voltage signal; a third limiter configured to compare a third phase-voltage signal with the maximum limit value and the minimum limit value to output a third limit-voltage signal; and a summer configured to add a difference between the first phase-voltage signal and the first limit-voltage signal, a difference between the second phase-voltage signal and the second limit-voltage signal, and a difference between the third phase-voltage signal and the third limit-voltage signal, to output an offset voltage. The maximum limit value and the minimum limit value are determined by DC link voltage of the three-phase inverter. 
     In accordance with another aspect of some embodiments of the present disclosure, a three-phase inverter control device for controlling switching operations of a plurality of switching elements in a three-phase inverter includes: a pole-voltage signal generator configured to compare a first phase-voltage signal, a second phase-voltage signal and a third phase-voltage signal with a maximum limit value and a minimum limit value, respectively, to generate an offset voltage, and add the offset voltage to the first phase-voltage signal, the second phase-voltage signal and the third phase-voltage signal to generate a first pole-voltage signal, a second pole-voltage signal and a third pole-voltage signal, respectively; and a control signal generator configured to compare the first pole-voltage signal, the second pole-voltage signal and the third pole-voltage signal with a carrier wave, to generate a control signal for the plurality of switching elements, wherein the maximum limit value and the minimum limit value are determined by a DC link voltage of the three-phase inverter. 
     As set forth above, according to an embodiment of the present disclosure, the voltage modulation mode of a three-phase inverter can be easily switched from the continuous modulation mode to the discontinuous modulation mode without any additional calculating process. 
     In addition, according to an embodiment of the present disclosure, a discontinuous modulation period is adjusted, such total harmonic distortion (THD) can be reduced in a period where the modulation index is low compared to the discontinuous modulation scheme in the related art, and switching loss can be reduced in a period where the modulation index is high compared to the continuous modulation scheme in the related art. 
     Moreover, according to an embodiment of the present disclosure, an offset voltage having the minimum RMS is generated, such that unnecessary zero sequence voltage can be reduced. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  shows an example of a three-phase inverter to which a method for generating an offset voltage of a three-phase inverter according to an embodiment of the present disclosure is applied; 
         FIG. 2  shows a process of generating a three-phase pole voltage signal by a pole voltage signal generator in the PWM control unit in the related art; 
         FIG. 3  shows a process that a control signal generator in the PWM control unit generates a control signal for switching elements by using three-phase pole-voltage signals in the related art; 
         FIG. 4  is a block diagram of a pole-voltage signal generator included in a PWM control unit according to an embodiment of the present disclosure; 
         FIG. 5  is block diagram of the offset voltage generator according to an embodiment of the present disclosure; 
         FIGS. 6 to 8  are graphs for comparing waveforms of offset voltages and pole-voltages according to the PWM control scheme of the present disclosure, the SPWM control scheme in the related art, the SVPWM control scheme in the related art and the 60° DPWM in the related art with one another by varying the modulation index MI; 
         FIG. 9  is a graph showing a ratio of switching loss in each of the modulation schemes with respect to switching loss in the continuous modulation scheme according to power factor, according to an embodiment of the present disclosure; and 
         FIG. 10  is a graph for comparing weighted total harmonic distortion (WTHD) in the continuous modulation scheme and discontinuous modulation scheme in the related art with WTHD in the method for generating offset voltage according to an embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The above objects, features and advantages will become apparent from the detailed description with reference to the accompanying drawings. Embodiments are described in sufficient detail to enable those skilled in the art in the art to easily practice the technical idea of the present disclosure. Detailed disclosures of well-known functions or configurations may be omitted in order not to unnecessarily obscure the gist of the present disclosure. Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Throughout the drawings, like reference numerals refer to like elements. 
       FIG. 1  shows an example of a three-phase inverter to which a method for generating an offset voltage of a three-phase inverter according to an embodiment of the present disclosure is applied. The three-phase inverter shown in  FIG. 1  is a typical two-level three-phase voltage source inverter used in driving an ESS or motor drive. 
     Referring to  FIG. 1 , the three-phase inverter includes a smoothing part  101  and a switching part  102 . The three-phase inverter rectifies a three-phase AC voltage from an external device to a DC voltage by a rectifier (not shown). The rectified DC voltage is smoothed via the smoothing part  101  shown in  FIG. 1  to DC link voltages of V dc /2 at two DC links. The symbol n in  FIG. 1  represents a virtual DC link neutral point. 
     The smoothed DC link voltages V dc /2 are converted to a three-phase AC voltage via a number of switching elements a 1 , a 2 , b 1 , b 2 , c 1  and c 2  in the switching part  102 . The switching element al and the switching element a 2  are turned on/off in a complementary fashion. Likewise, the switching element b 1  and the switching element b 2  are turned on/off in a complementary fashion, and the switching element c 1  and the switching element c 2  are turned on/off in a complementary fashion. 
     The three-phase AC voltage generated via the switching operations of the switching unit  102  is input to a load  103  such as an electric motor. 
     The switching elements a 1 , a 2 , b 1 , b 2 , c 1  and c 2  in the switching part  102  are turned on/off in a complementary fashion, respectively, to generate a three-phase AC voltage. The switching operations (on/off operations) of the switching elements a 1 , a 2 , b 1  b 2 , c 1  and c 2  are performed in accordance with control signals output from a PWM control unit  104  as shown in  FIG. 1 . The PWM control unit  104  generates control signal for controlling the switching operations of the switching elements a 1 , a 2 , b 1 , b 2 , c 1  and c 2  using a three-phase voltage signal input from an external device. 
       FIG. 2  shows a process of generating a three-phase pole voltage signal by a pole voltage signal generator in the PWM control unit  104  in the related art. 
     Referring to  FIG. 2 , the pole-voltage signal generator in the PWM control unit  104  adds three phase-voltage signals  201  including a first phase-voltage signal V* as , a second phase-voltage signal V* bs  and a third phase-voltage signal V* cs  to an offset voltage V* sn  generated in an offset voltage generator  202 , respectively, thereby generating three-phase pole-voltage signals  203  including a first pole-voltage signal V* an , a second pole-voltage signal V* bn  and a third pole-voltage signal The offset voltage V* sn  is a component that commonly exists in the pole-voltage signals  203 , and is a zero sequence voltage such that it does not affect the combination of phase-to-phase voltages. 
     Accordingly, the relationship is established among the pole-voltage signals  203 , the phase-voltage signals  201  and the offset voltage signal V* sn  as expressed in Equation 1:
 
 v*   an   =v*   as   +v*   sn  
 
 v*   bn   =v*   bs   +v*   sn  
 
 v*   cn   =v*   cs   +v*   sn    [Equation 1]
 
       FIG. 3  shows a process that a control signal generator in the PWM control unit  104  generates a control signal for switching elements by using three-phase pole-voltage signals in the related art. 
     The pole-voltage signals  301  generated via the process of  FIG. 2 , i.e., the first pole-voltage signal V* an , the second pole-voltage signal V* bn  and the third pole-voltage signal V* cn  are compared with a carrier wave  302  as shown in  FIG. 3 . Although the carrier wave  302  shown in  FIG. 3  is a triangular carrier wave, other types of carrier waves may also be used depending on the modulation scheme. As shown in  FIG. 3 , the frequency of the carrier wave  302  is equal to the switching frequency. The peak has the maximum value of V dc /2 and the minimum value of −V dc /2. 
     In the related art, as shown in  FIG. 3 , the difference between each of the pole-voltage signals  201  and the carrier wave  302  is calculated, and the value of 1 is output if the difference is equal to or greater than 0, and the value of 0 is output if the difference is less than 0 (as indicated by reference numeral  303 ). Accordingly, an on-signal is output to the switching elements a 1 , b 1  and c 1  if the difference between each of the pole-voltage signals  201  and the carrier wave  302  is greater than 0, and an on-signal is output to the switching elements a 2 , b 2  and c 2  if the difference between each of the pole-voltage signals  201  and the carrier wave  302  is less than 0 by NOT gates  304 . 
     In the processes of generating control signals by the PWM control unit  104  in the related art as shown in  FIGS. 2 and 3 , the modulation mode is finally determined based on the offset voltage V* sn  generated in the offset voltage generator  202 . For example, the offset voltage V* sn  for sinusoidal PWM (SPWM), which is a continuous modulation mode, is as follows:
 
v* sn =0   [Equation 2]
 
     In addition, the offset voltage V* sn  for space vector PWM (SVPWM) is as follows: 
                     v   sn   *     =     -         v   max     +     v   min       2               [     Equation   ⁢           ⁢   3     ]               
where V max  denotes the largest one of the first phase-voltage signal V* as , the second phase-voltage signal V* bs  and the third phase-voltage signal V* cs , and V min  denotes the smallest one thereof. The space vector PWM (SVPWM) expressed in Equation 3 is a continuous modulation scheme in which control signals for all of the switching elements are changed for a cycle of a carrier wave.
 
     In contrast, in a discontinuous modulation scheme, a control signal for a switching element in a phase does not change, in order to reduce switching loss. One of the most commonly used discontinuous voltage modulation scheme is 60° discontinuous PWM (DPWM), in which switching discontinuous periods of 60° exist around the peak of a phase-voltage signal. The 60° DPWM has the offset voltage V* sn  as follows: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           v 
                           sn 
                           * 
                         
                         = 
                         
                           
                             
                               V 
                               dc 
                             
                             2 
                           
                           - 
                           
                             v 
                             max 
                           
                         
                       
                     
                     
                       
                         ( 
                         
                           if 
                           , 
                           
                             
                               
                                 v 
                                 max 
                               
                               + 
                               
                                 v 
                                 min 
                               
                             
                             ≥ 
                             0 
                           
                         
                         ) 
                       
                     
                   
                   
                     
                       
                         
                           v 
                           sn 
                           * 
                         
                         = 
                         
                           
                             
                               V 
                               dc 
                             
                             2 
                           
                           - 
                           
                             v 
                             min 
                           
                         
                       
                     
                     
                       
                         ( 
                         
                           if 
                           , 
                           
                             
                               
                                 v 
                                 max 
                               
                               + 
                               
                                 v 
                                 min 
                               
                             
                             &lt; 
                             0 
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ] 
                 
               
             
           
         
       
     
     As described above, in the PWM control using the offset voltage, different offset voltages have to be calculated in order to switch from the continuous modulation mode to the discontinuous modulation mode, as expressed in Equations 2 to 4. 
     In addition, there is a drawback in the related art in that although switching loss is reduced, the total harmonic distortion (THD) in an output current increases. Further, there is a drawback in the related art in that although the THD in the output current is low in comparison with the discontinuous modulation mode, switching loss increases. 
     In addition, according to the existing discontinuous modulation mode using the offset voltage, the discontinuous modulation interval is always set to 120 0  of a cycle of a reference wave. Accordingly, when the modulation index MI is low, the THD in the output current is very large in the discontinuous modulation mode. As a result, there is another problem in the modulation index by which discontinuous modulation starts is restricted in order to reduce switching loss. 
     In addition, according to the above-described existing voltage modulation schemes using offset voltage, the offset voltage is continuously generated even in a period where the offset voltage is not necessary and introduced into the inverter via the PWM control unit  104 . The offset voltage is zero sequence voltage and may result in reduction in the power efficiency or malfunction of a load connected to the inverter. For example, if such zero sequence voltage is applied to an ESS using a grid connected inverter or a photovoltaic module, leakage current may be generated such that power efficiency may be reduced. In addition, in driving a typically induction motor, if zero sequence voltage becomes larger, torque in the axial direction or bearing current becomes large, possibly causing dielectric breakdown. 
     In order to overcome such problems, there are provided an offset voltage generator and a method for generating an offset voltage of a three-phase inverter that allow voltage modulation mode of the three-phase inverter to switch from a continuous modulation mode to a discontinuous modulation mode without additionally calculating another offset voltage. Moreover, in the offset voltage generator and the method for generating offset voltage according to an embodiment of the present disclosure, an offset voltage having the minimum RMS is generated to be introduced into the inverter and thus the zero sequence voltage is minimized, thereby preventing reduction in power efficiency and malfunction of a load driven by the inverter. 
       FIG. 4  is a block diagram of a pole-voltage signal generator included in a PWM control unit  104  according to an embodiment of the present disclosure. 
     Referring to  FIG. 4 , the pole-voltage signal generator adds three phase-voltage signals  401  including a first phase-voltage signal V* as , a second phase-voltage signal V* bs  and a third phase-voltage signal V* cs  to an offset voltage V* sn  generated in an offset voltage generator  402 , respectively, (as indicated by reference numeral  403 ), thereby generating three-phase pole-voltage signals  404  including a first pole-voltage signal V* an , a second pole-voltage signal V* bn  and a third pole-voltage signal V* cn . 
     In  FIG. 4 , the offset voltage generator  402  according to the embodiment of the present disclosure generates an offset voltage V* sn  by using phase-voltage signals  401  and a DC link voltage V dc  of the three-phase inverter. 
     The offset voltage V* sn  of of the inverter of  FIG. 1  has the range as expressed in Equation 5 below: 
     
       
         
           
             
               
                 
                   
                     
                       - 
                       
                         
                           V 
                           dc 
                         
                         2 
                       
                     
                     - 
                     
                       v 
                       min 
                     
                   
                   ≤ 
                   
                     v 
                     sn 
                     * 
                   
                   ≤ 
                   
                     
                       
                         V 
                         dc 
                       
                       2 
                     
                     - 
                     
                       v 
                       max 
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   ] 
                 
               
             
           
         
       
     
     If 
                 V   dc     2     &lt;     v   max           
in Equation 5,
 
                 -       V   dc     2       -     v   min       ≤     v   sn   *     ≤         V   dc     2     -     v   max       ≤   0         
is established. That is, the offset voltage having the minimum absolute value becomes
 
                 V   dc     2     -       v   max     .           
On the other hand, if
 
                 -       V   dc     2       -     v   min       ,     0   ≤       -       V   dc     2       -     v   min       ≤     v   sn   *     ≤         V   dc     2     -     v   max               
is established, such that the offset voltage having the minimum absolute value becomes
 
     
       
         
           
             
               - 
               
                 
                   V 
                   dc 
                 
                 2 
               
             
             - 
             
               
                 v 
                 min 
               
               . 
             
           
         
       
     
     Accordingly, the offset voltage generated by the offset voltage generator according to the embodiment of the present disclosure is defined as follows: 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           v 
                           sn 
                           * 
                         
                         = 
                         0 
                       
                     
                     
                       
                         ( 
                         
                           if 
                           , 
                           
                             
                               - 
                               
                                 
                                   V 
                                   dc 
                                 
                                 2 
                               
                             
                             ≤ 
                             
                               v 
                               max 
                             
                           
                           , 
                           
                             
                               v 
                               min 
                             
                             ≤ 
                             
                               
                                 V 
                                 dc 
                               
                               2 
                             
                           
                         
                         ) 
                       
                     
                   
                   
                     
                       
                         
                           v 
                           sn 
                           * 
                         
                         = 
                         
                           
                             
                               V 
                               dc 
                             
                             2 
                           
                           - 
                           
                             v 
                             max 
                           
                         
                       
                     
                     
                       
                         ( 
                         
                           if 
                           , 
                           
                             
                               
                                 V 
                                 dc 
                               
                               2 
                             
                             ≤ 
                             
                               v 
                               max 
                             
                           
                         
                         ) 
                       
                     
                   
                   
                     
                       
                         
                           v 
                           sn 
                           * 
                         
                         = 
                         
                           
                             - 
                             
                               
                                 V 
                                 dc 
                               
                               2 
                             
                           
                           - 
                           
                             v 
                             min 
                           
                         
                       
                     
                     
                       
                         ( 
                         
                           if 
                           , 
                           
                             
                               v 
                               min 
                             
                             ≤ 
                             
                               - 
                               
                                 
                                   V 
                                   dc 
                                 
                                 2 
                               
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     6 
                   
                   ] 
                 
               
             
           
         
       
     
     Hereinafter, a process of generating an offset voltage V* sn  by the offset voltage generator  402  according to Equation 6 will be described in detail with reference to  FIG. 5 . 
       FIG. 5  is block diagram of the offset voltage generator  402  according to an embodiment of the present disclosure. 
     Referring to  FIG. 5 , the offset voltage generator  402  according to the embodiment generates three-phase voltage signals V* as , V* bs  and V* cs  and corresponding limiting signals Vas, Vbs and Vcs, respectively, according to Equation 7 below:
 
 v*   sn =−( v*   as   −v   as   +v*   bs   −v   bs   +v*   cs   −v   cs )   [Equation 7]
 
where the limit signals Vas, Vbs and Vcs are defined as follows:
 
                       v   as     =     bound   ⁡     (       -       V   dc     2       ,       V   dc     2     ,     v   as   *       )         ⁢     
     ⁢       v   bs     =     bound   ⁡     (       -       V   dc     2       ,       V   dc     2     ,     v   bs   *       )         ⁢     
     ⁢       v   cs     =     bound   ⁡     (       -       V   dc     2       ,       V   dc     2     ,     v   cs   *       )                 [     Equation   ⁢           ⁢   8     ]               
where the function bound ( ) is defined as follows:
 
     
       
         
           
             
               
                 
                   
                     bound 
                     ⁡ 
                     
                       ( 
                       
                         a 
                         , 
                         b 
                         , 
                         x 
                       
                       ) 
                     
                   
                   = 
                   
                     { 
                     
                       
                         
                           a 
                         
                         
                           
                             ( 
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 x 
                               
                               &lt; 
                               a 
                             
                             ) 
                           
                         
                       
                       
                         
                           b 
                         
                         
                           
                             ( 
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 x 
                               
                               &gt; 
                               b 
                             
                             ) 
                           
                         
                       
                       
                         
                           x 
                         
                         
                           
                             ( 
                             
                               
                                 if 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 a 
                               
                               ≤ 
                               x 
                               ≤ 
                               b 
                             
                             ) 
                           
                         
                       
                     
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     9 
                   
                   ] 
                 
               
             
           
         
       
     
     The offset voltage generator  402  according to the embodiment of the present disclosure generates the offset voltage V* sn  as expressed in Equation 7 in the following manner. Referring to  FIG. 5 , the offset voltage generator  402  according to the embodiment of the present disclosure includes a first limiter  502 ( a ), a second limiter  502 ( b ) and a third limiter  502 ( c ) respectively corresponding to the first phase-voltage signal V* as , the second phase-voltage signal V* bs  and the third phase-voltage signal V* cs . 
     The first limiter  502 ( a ) receives the first phase-voltage signal V* as  and compares the received first phase-voltage signal V* as  with the maximum limit value and the minimum limit value to output the first limit signal Vas. In this embodiment, the maximum limit value may be set to 
                 V   dc     2     ,         
and the minimum limit value may be set to
 
     
       
         
           
             - 
             
               
                 
                   V 
                   dc 
                 
                 2 
               
               . 
             
           
         
       
     
     In this embodiment, the first limiter  502 ( a ) outputs the first phase voltage signal V* as  as the first limit signal Vas if the first phase voltage signal V* as  is equal to or greater than the minimum limit value and equal to or less than the maximum limit value. In addition, the first limiter  502 ( a ) outputs the minimum limit value as the first limit signal Vas if the first phase voltage signal V* as  is less than the minimum limit value. In addition, the first limiter  502 ( a ) outputs the maximum limit value as the first limit signal Vas if the first phase voltage signal V* as  is greater than the maximum limit value. 
     The second limiter  502 ( b ) and the third limiter  502 ( c ) also output the second limit signal Vbs and the third limit signal Vcs, respectively, in the same manner as the first limiter  502 ( a ) described above. 
     Then, the 402 outputs, as the offset voltage V* sn , the sum of the difference between the first limit signal Vas and the first phase voltage signal V* as , the difference between the second limit signal Vbs and the second phase voltage signal V* bs , and the difference between the third limit signal Vcs and the third phase voltage signal V* cs , as shown in  FIG. 5 . 
     In  FIG. 5 , the offset voltage V* sn  generated by the offset voltage generator  402  becomes 0 if the three phase-voltage signals  501  are between the minimum limit value and the maximum limit value. When the offset voltage V* sn  is 0, the PWM control unit  104  of  FIG. 1  operates in the SPWM mode that is a continuous modulation scheme. 
     On the other hand, if the phase-voltage signals  501  are greater than the maximum limit value or less than the minimum limit value, the offset voltage becomes 
     
       
         
           
             
               v 
               sn 
               * 
             
             = 
             
               
                 
                   
                     V 
                     dc 
                   
                   2 
                 
                 - 
                 
                   
                     v 
                     max 
                   
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   or 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   
                     v 
                     sn 
                     * 
                   
                 
               
               = 
               
                 
                   - 
                   
                     
                       V 
                       dc 
                     
                     2 
                   
                 
                 - 
                 
                   
                     v 
                     max 
                   
                   . 
                 
               
             
           
         
       
     
     Accordingly, the pole-voltage signal becomes V dc /2 or −V dc /2, such that the PWM control unit  104  is switched to the discontinuous modulation mode. 
     According to the embodiment of the present disclosure, the discontinuous operation range in which the PWM control unit  104  operates in the discontinuous modulation mode is determined by the modulation index MI. The modulation index is defined as expressed in Equation 10 below: 
                   MI   =       V   m         V   dc     /   2               [     Equation   ⁢           ⁢   10     ]               
where V m  denotes the magnitude of phase-voltage signal.
 
     Consequently, the PWM control unit  104  operates in the continuous modulation mode if the modulation index is equal to or less than a predetermined reference index, e.g., 1. Further, the PWM control unit  104  operates in the discontinuous modulation mode if the modulation index is greater than the reference index. In particular, the PWM control unit  104  operates in the 60° DPWM mode when the modulation index becomes the maximum value of the linear modulation region, e.g., 2/√{square root over (3)}(=1.1547). 
     As such, according to an embodiment of the present disclosure, the voltage modulation mode of the three-phase inverter can be easily switched from the continuous modulation mode to the discontinuous modulation mode without any additional calculating process. In addition, according to an embodiment of the present disclosure, a discontinuous modulation period is adjusted, such that total harmonic distortion (TED) can be reduced in a period where the modulation index is low compared to the discontinuous modulation scheme in the related art, and switching loss can be reduced in a period where the modulation index is high compared to the continuous modulation scheme in the related art. 
       FIGS. 6 to 8  are graphs for comparing waveforms of offset voltages and pole-voltages according to the PWM control scheme of some embodiments of the present disclosure, the SPWM control scheme in the related an, the SVPWM control scheme in the related art and the 60° DPWM in the related art with one another by varying the modulation index MI. 
     In  FIG. 6 , the modulation index MI of the PWM control scheme according to the embodiment of the present disclosure is set to 1.  FIG. 6  shows a waveform  601 ( a ) of a pole-voltage signal according to the PWM control scheme according to the embodiment of the present disclosure and the SPWM control scheme in the related art, a waveform  602 ( a ) of a pole-voltage signal according to the SVPWM control scheme in the related art, and a waveform  603 ( a ) of a pole-voltage signal according to the 60° DPWM control scheme in the related art. 
     In addition,  FIG. 6  shows a waveform  601 ( b ) of an offset voltage according to the PWM control scheme according to the embodiment of the present disclosure and the SPWM control scheme in the related art, a waveform  602 ( a ) of an offset voltage according to the SVPWM control scheme in the related art, and a waveform  603 ( a ) of an offset voltage according to the 60° DPWM control scheme in the related art. 
     As shown in  FIG. 6 , according to the PWM control scheme of an embodiment of the present disclosure, the PWM control unit  104  operates in the same manner as the SPWM control scheme in the related art if the modulation index MI is set to 1 or less. 
     In  FIG. 7 , the modulation index MI of the PWM control scheme according to the embodiment of the present disclosure is set to 1.7.  FIG. 7  shows a waveform  701 ( a ) of a pole-voltage signal according to the SPWM control scheme in the related art, a waveform  702 ( a ) of a pole-voltage signal according to the 60° DPWM control scheme in the related art, and a waveform  703 ( a ) of a pole-voltage signal according to the PWM control scheme of some embodiments of the present disclosure. 
       FIG. 7  shows a waveform  701 ( b ) of an offset voltage according to the SPWM control scheme in the related art, a waveform  702 ( b ) of an offset voltage according to the 60° DPWM control scheme in the related art, and a waveform  703 ( b ) of an offset voltage according to the PWM control scheme of some embodiments of the present disclosure. 
     As shown in  FIG. 7 , the discontinuous modulation period according to the PWM control scheme of some embodiments of the present disclosure is longer as the modulation index MI is greater than 1. 
     In  FIG. 8 , the modulation index MI of the PWM control scheme according to the embodiment of the present disclosure is set to 2/√{square root over (3)}.  FIG. 8  shows a waveform  801 ( a ) of a pole-voltage signal according to the SVPWM control scheme in the related art, and a waveform  802 ( a ) of a pole-voltage signal according to the 60° DPWM control scheme and the PWM control scheme of some embodiments of the present disclosure. 
     In addition,  FIG. 8  shows a waveform  801 ( b ) of an offset voltage according to the SVPWM control scheme in the related art, and a waveform  802 ( a ) of an offset voltage according to the 60° DPWM control scheme and the PWM control scheme of some embodiments of the present disclosure. 
     As shown in  FIG. 8 , when the modulation index MI becomes the maximum value of 2/√{square root over (3)}, the PWM control unit  104  according to the embodiment of the present disclosure operates in the same manner as in the 60° DPWM control scheme in the related art, such that it has the maximum discontinuous modulation period for a cycle. 
     In particular, as can be seen from  FIGS. 7 and 8 , according to the PWM control scheme of some embodiments of the present disclosure, an offset voltage having the minimum absolute value is generated if the modulation index MI is between 1 and the maximum value of 2/√{square root over (3)}. 
       FIG. 9  is a graph showing a ratio of switching loss in each of the modulation schemes with respect to switching loss in the continuous modulation scheme according to power factor. 
       FIG. 9  shows switching loss  901  in the continuous modulation scheme, e.g., the SPWM and SVPWM scheme, and switching loss  903  in the discontinuous modulation scheme, e.g., the 60° DPWM scheme. In addition,  FIG. 9  shows switching loss  902  as the modulation index MI is changed from 1 to 2/√{square root over (3)} according to the PWM control scheme of embodiments of the present disclosure. 
     As shown in  FIG. 9 , the switching loss  902  in the PWM control scheme of some embodiments the present disclosure is equal to that of the SPWM, e.g., the continuous voltage modulation scheme when the modulation index MI is 1, and the switching loss  902  gradually decreases as the discontinuous modulation period increases if the modulation index MI is greater than 1. In particular, it can be seen from  FIG. 9  that the switching loss  902  is equal to the switching loss  903  in the 60° DPWM when the modulation index MI is the maximum value of 2/√{square root over (3)}. 
       FIG. 10  is a graph for comparing weighted total harmonic distortion (WTHD) in the continuous modulation scheme and discontinuous modulation scheme in the related art with WTHD in the method for generating offset voltage according to an embodiment of the present disclosure. 
     The WTHD shown in  FIG. 13  is defined as follows: 
                   WTHD   =             ∑     n   =   2     ∞     ⁢           ⁢       (       V   n       n   ⁢           ⁢     ω   1     ⁢   L       )     2             V   1         ω   1     ⁢   L         =           ∑     n   =   2     ∞     ⁢           ⁢       (       V   n     n     )     2           V   1                 [     Equation   ⁢           ⁢   11     ]               
where ω 1  denotes the frequency of fundamental wave, V 1  denotes the magnitude of fundamental wave, n denotes the order of harmonic, and V n  denotes the magnitude of n-order harmonic.
 
       FIG. 10  shows WTHD 1001 in 60° DPWM scheme in the related art, WTHD  1002  in SPWM scheme in the related art, WTHD  1003  in SVPWM scheme in the related art, and WTHD  1004  in PWM control scheme according to an embodiment of the present disclosure. 
     As shown in  FIG. 13 , the WTHD  1004  in the PWM control scheme according to the embodiment of the present disclosure is identical to the WTHD  1002  in the SPWM scheme in the related art when the modulation index MI is equal to or less than the reference index of 1. However, when the modulation index MI becomes larger than the reference index of 1, the discontinuous modulation interval increases, such that the WTHD  1004  gradually increases. Even though the WTHD  1004  in PWM scheme according to the embodiment of the present disclosure increases, it always remains lower than the WTHD  1001  in the 60° DPWM scheme in the related art. 
     The PWM control scheme according to the embodiment of the present disclosure described above is a voltage modulation method in which a zero sequence voltage or an offset voltage calculated using the phase-voltage signals, the limiters and the weight are compared with a triangular wave. The smooth switching from the continuous voltage modulation mode to the discontinuous voltage modulation mode can be achieved by adding up differences between phase-voltage signals and respective limit voltage signals after having passed the limiters. In addition, the discontinuous voltage modulation period can be adjusted by adjusting the maximum limit value and the minimum limit value input to the limiters. 
     By utilizing the offset voltage thus generated, the PWM control unit operates in the continuous modulation mode when the modulation index is set to a value below the reference index of 1, whereas the PWM control unit is switched to the discontinuous modulation mode when the modulation index becomes larger than the reference index of I. By applying the PWM control scheme according to an embodiment of the present disclosure to an inverter for an ESS, an inverter for a photovoltaic module, an inverter for motor drive, etc., the discontinuous modulation period can be adjusted, such that the THD can be reduced even in a period where the modulation index is low compared to the discontinuous modulation scheme in the related art. Further, switching loss can also be reduced in a period where third modulation index is high compared to the continuous modulation scheme in the related art. Moreover, in the offset voltage generator and the method for generating offset voltage according to an embodiment of the present disclosure, an offset voltage having the minimum RMS is generated to be introduced into the inverter and thus the zero sequence voltage is minimized, thereby preventing reduction in the power efficiency or malfunction of a load driven by the inverter. 
     The present disclosure described above may be variously substituted, altered, and modified by those skilled in the art to which the present disclosure pertains without departing from the scope and sprit of the present disclosure. Therefore, the present disclosure is not limited to the described embodiments and the accompanying drawings.