Patent Publication Number: US-10770121-B1

Title: Memory device and memory writing method

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Chinese Application Serial Number 201910146939.1, filed Feb. 27, 2019, which is herein incorporated by reference. 
     BACKGROUND 
     Technical Field 
     The present disclosure relates to a memory device and a memory writing method. 
     Description of Related Art 
     In current memory technology, as the functions and the capacity of a memory are more increased, smaller chip size of the memory is required accordingly. 
     Therefore, how to store huge data in the memory device and effectively reduce the circuit area of the memory device is a very challenging design topic. 
     SUMMARY 
     An aspect of the present disclosure relates to a memory device includes: a memory array, a plurality of write drivers, and a controller. A memory array includes a plurality of memory units respectively arranged in a plurality of bit lines. A plurality of write drivers configured to generate a plurality of write bit signals respectively input to the bit lines. A controller configured to provide a voltage mode control signal and a current mode control signal. The controller is electrically coupled to the write drivers. Wherein each of the write drivers respectively generates, according to the voltage mode control signal and the current mode control signal, one of the write bit signals corresponding to each of the write drivers. In response to each of the memory units being in a set state, the controller outputs the voltage mode control signal and the current mode control signal to the write drivers. In response to each of the memory units being in a reset state, the controller outputs the voltage mode control signal to the write drivers. 
     An aspect of the present disclosure relates to a memory device. Each of the write drivers comprises a current mirror, a first transistor, and a second transistor. The current mirror comprises an input terminal, a plurality of switches, and a plurality of current branches and the current mirror is electrically coupled to the controller. The current mode control signal controls the input terminal of the current mirror, and accordingly the current mirror outputs a current mirror signal. Each one of the switches controls a corresponding one of the current branches to be turned on or off, so as to adjust the magnitude of the current mirror signal. The first transistor comprises a control terminal, and the voltage mode control signal controls the control terminal of the first transistor. The second transistor comprises a control terminal and the current mirror signal controls the control terminal of the second transistor. An output terminal of the first transistor is connected to an output terminal of the second transistor. To output one of the write bit signals, the first transistor is turned on or off according to the voltage mode control signal, and the second transistor is turned on or off according to the current mirror signal. 
     An aspect of the present disclosure relates to a memory device. Wherein, in response to each of the memory units being in the set state, the controller generates the voltage mode control signal and the current mode control signal to simultaneously turn on the first transistor and the second transistor, so that one of the write bit signals is switched from a low level to a set pulse level and sustains at the set pulse level for a first time period. Immediately after the first time period, the controller turns off the first transistor and sustains the current mode control signal, so that the second transistor is gradually turned off from the turn-on state according to the magnitude of the current mirror signal in a second time period. One of the write bit signals is gradually decreased from a high level to the low level in the second time period; and the high level is between the set pulse level and the low level. 
     An aspect of the present disclosure relates to a memory device. Wherein, in response to each of the memory units being in the reset state, the controller generates the voltage mode control signal to turn on the first transistor and switch one of the write bit signals from a low level to a reset pulse level, and the write bit signal sustains at the reset pulse level for a third time period. The controller turns off the first transistor to decrease one of the write bit signals from the reset pulse level to the low level. 
     An aspect of the present disclosure relates to a memory device, wherein the controller controls the write drivers, so that the plurality of rising edges of the write bit signals are staggered from each other. 
     Another aspect of the present disclosure relates to a memory writing method which is configured to generate a plurality of write bit signals. The write bit signals are configured to write a plurality of memory units of plurality of bit lines, the memory writing method includes as follows: The state of the memory units being written into a set state or a reset state is determined. In response to the memory units being required to be written into a set state, a voltage mode control signal and a current mode control signal are outputted to a plurality of write drivers, so that the write drivers generate the write bit signals according to the voltage mode control signal and the current mode control signal. In response to the memory units being required to be written into a reset state, the voltage mode control signal is outputted, so that the write drivers generate the write bit signals according to the voltage mode control signal. 
     An aspect of the present disclosure relates to a memory writing method, wherein each of the write drivers includes a first transistor and a second transistor, and the output terminal of the first transistor is connected to the output terminal of the second transistor. The memory writing method includes as follows: A current mirror signal is generated according to the current mode control signal, and the second transistor is turned on or off based on the current mirror signal so as to output the one of the write bit signals. The first transistor is turned on or off based on the voltage mode control signal so as to output the one of the write bit signals. 
     An aspect of the present disclosure relates to a memory writing method. Wherein, in response to the memory units required to be written into a set state, the memory writing method includes as follows: Both the voltage mode control signal and the current mode control signal are simultaneously generated to turn on the first transistor and the second transistor and switch one of the write bit signals from a low level to a set pulse level; and the write bit signal sustains at the set pulse level for a first time period. After the first time period, the current mode control signal is sustained so that the second transistor is gradually turned off from the on state according to the current mirror signal. One of the write bit signals is gradually decreased from a high level to the low level in the second time period; and the high level is between the set pulse level and the low level. 
     An aspect of the present disclosure relates to a memory writing method, wherein, in response to the memory units being required to be written into a reset state, the memory writing method further includes that the voltage mode control signal is turned off after the first time period, and the current mode control signal is sustained and inputted to the write drivers. 
     An aspect of the present disclosure relates to a memory writing method, wherein the time sequences of a plurality of write drivers are controlled, so that a plurality of rising edges of the write bit signals are staggered from each other. 
     An aspect of the present disclosure relates to a memory writing method. In response to the memory units required to be written into a reset state, the memory writing method includes as follows: The voltage mode control signal is generated to turn on the first transistor and switch one of the write bit signals from a low level to a reset pulse level; and the write bit signals is sustained at the reset pulse level for a third time period. The first transistor is turned off, and one of the write bit signals is decreased from the reset pulse level to the low level. 
     An aspect of the present disclosure relates to a memory writing method, wherein the time sequences of a plurality of write drivers time are controlled, so that a plurality of rising edges of the write bit signals are staggered from each other. 
     A further aspect of the present disclosure relates to a memory writing method, which is configured to generate a plurality of write bit signals. The write bit signals are configured to write a plurality of memory units of a plurality of bit lines. The memory writing method includes as follows: The state of the memory units being written into a set state or a reset state is determined. In response to the memory units required to be written into a set state, a first control signal is outputted to a plurality of write drivers, so that the write drivers generate the write bit signals based on the first control signal. In response to the memory units required to be written into a reset state, a second control signal is outputted, so that the write drivers generate the write bit signals based on the second control signal. The time sequences of the write drivers are controlled, so that a plurality of rising edges of the write bit signals are staggered from each other. 
     In summary, through the memory device and the memory writing method described in the above embodiments, the memory device could control memory units to be written to reset state and/or set state effectively, and the sequential time shift approach applied to the memory unit reduces the area of the charge pump in the memory device effectively. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The disclosure can be more fully understood by reading the following detailed description of the embodiments, with reference made to the accompanying drawings as follows: 
         FIG. 1  shows a schematic diagram of a memory device according to one embodiment of the present disclosure. 
         FIG. 2  shows a partial schematic diagram of a memory device in  FIG. 1 , in accordance with one embodiment of the present disclosure. 
         FIG. 3  shows a flowchart of a memory writing method in accordance with one embodiment of the present disclosure. 
         FIG. 4A  shows a schematic diagram of the current waveform of set pulse in accordance with one embodiment of the present disclosure. 
         FIG. 4B  shows a schematic diagram of the current waveform of reset pulse in accordance with one embodiment of the present disclosure. 
         FIG. 5A  shows a schematic diagram of the conventional current waveform to reset multiple memory units in accordance with one embodiment of the present disclosure. 
         FIG. 5B  shows a schematic diagram of the conventional current waveform to set multiple memory units in accordance with one embodiment of the present disclosure. 
         FIG. 6A  shows a schematic diagram of the current waveform with sequential time shift to reset multiple memory units in accordance with one embodiment of the present disclosure. 
         FIG. 6B  shows a schematic diagram of the current waveform with sequential time shift to set multiple memory units in accordance with one embodiment of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to embodiments of the present disclosure, examples of which are described herein and illustrated in the accompanying drawings. While the disclosure will be described in conjunction with embodiments, it will be understood that they are not intended to limit the disclosure to these embodiments. On the contrary, the disclosure is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the disclosure as defined by the appended claims. It is noted that, in accordance with the standard practice in the industry, the drawings are only used for understanding and are not drawn to scale. Hence, the drawings are not meant to limit the actual embodiments of the present disclosure. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts for better understanding. 
     The terms used in this specification and claims, unless otherwise stated, generally have their ordinary meanings in the art, within the context of the disclosure, and in the specific context where each term is used. Certain terms that are used to describe the disclosure are discussed below, or elsewhere in the specification, to provide additional guidance to the practitioner skilled in the art regarding the description of the disclosure. 
     In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to.” The term “coupled” may also be termed “electrically coupled,” and the term “connected” may be termed “electrically connected.” “Coupled” and “connected” may also be used to indicate that two or more elements cooperate or interact with each other. It will be understood that, although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. 
     In order to solve the problem that a large number of instantaneous write currents are required for simultaneous writing of a plurality of bits in present memories, a large-area charge pump circuit is needed in a memory circuit. The present disclosure proposes a memory device capable of effectively reducing the area of the charge pump circuit of the memory circuit. 
       FIG. 1  shows a schematic diagram of a memory device  100  according to one embodiment of the present disclosure. As shown in  FIG. 1 , the memory device  100  includes a charge pump  120 , a controller  140 , a writing module  160 , a decoder  180 , and a memory array  190 . The memory array  190  includes multiple memory units. The multiple memory units are respectively arranged in multiple bit lines. 
     Reference is made to  FIG. 1 . The charge pump  120  is electrically coupled to the controller  140 . The controller  140  is electrically coupled to the writing module  160 . The writing module  160  is electrically coupled to the decoder  180 . The decoder  180  is electrically coupled to the memory array  190 . The writing module  160  may include multiple write drivers. As the embodiments shown in  FIG. 1 , the writing module  160  includes 32 write drivers, such as write driver WR 0 , write driver WR 1 , and write driver WR 2  to write driver WR 31 . In practical applications, the number of write drivers included in the write module  160  is not limited to 32, and it may be determined according to the number of bit lines of the memory array  190 . 
     In practical applications, for example, the controller  140  may be a microcontroller unit (MCU). Various approaches with same function of data processing are within the contemplated scope of this disclosure. 
     The memory units of memory array  190  are phase change memories (PCM). The phase change memories can change the resistance value of the memory unit through the crystal phase change of the material itself and store the data with the change of the resistance value. The write drivers WR 0 -WR 31  in the write module  160  are configured to provide specific write bit signals to change the crystal phase of the materials of the memory units in the memory array  190 . When the write bit signal sets the material in the memory unit to be a crystalline state, the memory unit exhibits a low resistance value. In contrast, when the write bit signal sets the material in the memory unit to be an amorphous state, the memory unit exhibits a high resistance value; thereby logic 1 or logic 0 is stored in the memory unit. For example, a high resistance value can represent logic 1, and a low resistance value can represent logic 0. In contrast, a low resistance value can represent logic 1, and a high resistance value represents logic 0. 
     Reference is made to  FIG. 2 . The  FIG. 2  shows a partial schematic diagram of a memory device  100  in  FIG. 1 , in accordance with one embodiment of the present disclosure. The  FIG. 2  shows a more detail schematic diagram of the write module  160  of the memory device  100  in  FIG. 1 , in accordance with one embodiment of the present disclosure. As shown in  FIG. 1 , the writing module  160  includes write driver WR 0 , write driver WR 1 , and write driver WR 2  to write driver WR 31 . For the convenience of description in the embodiment of  FIG. 2 , only the write driver WR 0 , the write driver WR 1 , and the write driver WR 2  of the write module  160  are schematically illustrated. The write driver WR 0  is configured to output write bit signal IWR 0 . The write driver WR 1  is configured to output write bit signal IWR 1 . The write driver WR 2  is configured to output write bit signal IWR 2 . The write bit signals IWR 0 -IWR 2  are respectively configured to control the memory units on the three different bit lines in the memory array  190 . As shown in  FIG. 2 ,  FIG. 2  illustrates the detailed internal architecture of the write driver WR 0 . The other write drivers WR 1 -WR 31  in  FIG. 1  may have a similar structure to WR 0  in  FIG. 2 , and therefore it will not be described repeatedly. 
     Taking the write driver WR 0  as an example, the write driver WR 0  includes a current mirror CM, a first transistor TR 1 , and a second transistor TR 2 . In the connection relationship, the input terminals of the current mirror CM, the first transistor TR 1 , and the second transistor TR 2  are electrically coupled to the system voltage terminal VDD. The system voltage terminal VDD is electrically coupled to the charge pump  120  of the memory device  100 . The control terminal of the current mirror CM is electrically coupled to the controller  140  of the memory device  100 . The control terminal of the first transistor TR 1  is electrically coupled to the controller  140  of the memory device  100 . The current mirror CM outputs a current mirror signal. The output terminal of the current mirror CM is electrically coupled to the control terminal of the second transistor TR 2 . The output terminals of the first transistor TR 1  and the second transistor TR 2  are connected to a connection point, and the connection point outputs a write bit signal IWR 0 . Like the above-mentioned working theory for the write driver WR 0 , the write driver WR 1  outputs the write bit signal IWR 1 , the write driver WR 2  outputs the write bit signal IWR 2 , and the write driver WR 31  outputs the write bit signal IWR 31 . The output terminals of the write drivers WR 0  WR 31  are electrically coupled to the decoder  180  of the memory device  100 . 
     Reference is made to  FIG. 3 . The  FIG. 3  shows a flowchart of a memory writing method  300  in accordance with one embodiment of the present disclosure. As shown in  FIG. 3 , the memory writing method  300  includes steps S 320  to S 383 . Please refer to  FIG. 1  and  FIG. 2  together. 
     In step S 320 , the memory device  100  receives an external write bit signal command. In step S 340 , the controller  140  reads the current storage state of each memory unit in the memory array  190 . 
     In step S 360 , the controller  140  determines whether the memory array  190  needs to be written or not, according to the external write bit signal command and the current storage state of the memory unit. If the external write bit signal command is same with the state of memory unit currently stored, the memory unit does not need to be written, and the process jumps to step S 370  to end the write operation for the memory unit. In an embodiment, the external write bit signal command is currently expected to write “logic 1” to one of the memory units of the memory array  190 , and the current storage state of the memory unit read in step S 340  is also “logic 1”, which is the same as the “logic 1” currently expected to be written. That indicates that the current memory unit has stored the data of “logic 1”. Therefore, in this embodiment, the crystal phase state of the memory unit does not need to be changed, so the writing operation is ended. Thereby the number of write operation of the memory unit is reduced and the life time of the memory unit can be extended, but the disclosure of this document is not limited to this. 
     In another embodiment, If the external write bit signal command is currently expected to write “logic 1” to one of the memory units of the memory array  190 , which is the same as the “logic 1” written by the memory unit currently. The write operation of memory unit could still be executed. 
     If the external write bit signal command and the current write status of the memory unit are different, the memory unit needs to be written. For example, if the external write bit signal command would write “logic 1” to one of the memory units of the memory array  190 , but the current data status in the memory is “logic 0”, which is different from the external write bit signal command, so that the write operation of memory unit need to be executed. 
     Then proceeding to execute step S 380 , step S 380  includes step S 381  to step S 383 . In step S 380 , each of write bit signals generated by the write module  160  is respectively inputted to each of the bit lines. Steps S 381  to S 383  describe the detailed flow of the write bit signal for one write driver, taking the write driver WR 0  as an example. In step S 381 , the controller  140  determines that the memory must be written to the set state or the reset state according to the external write bit signal command. When the external write bit signal command is the reset state, the phase change memory device is set to a high resistance state. On the contrary, when the external write bit signal command is the set state, the phase change memory device is set to low resistance state. 
     Please refer to  FIG. 4A  together.  FIG. 4A  shows a schematic diagram of the current waveform of the set pulse in accordance with one embodiment of the present disclosure. When the memory has to be written to the set state, the voltage control mode and the current control mode are simultaneously started in step S 382 . As shown in  FIG. 4A  and  FIG. 2 , the controller  140  generates the voltage mode control signal VMC which switching from the low level to the high level, to turn on the first transistor TR 1 . The controller  140  generates the current mode control signal CMC to indirectly turn on the second transistor TR 2 . As shown in  FIG. 4A , the set state current IWR 0   s  of the write bit signal IWR 0  is generated. The set state current IWR 0   s  is switched from the low level IL to the set pulse level Iset. Set pulse level Iset is a current level that is sufficient for the phase change material of the memory being written to reach a melting state. After the pulse level Iset is set to continue for the first time period D 1 , the controller  140  switches the voltage mode control signal VMC back to the low level to turn off the first transistor TR 1 . And then, the switches in the current mirror are gradually turned off individually within the second time period D 2 , so that multiple current branches in the current mirror are gradually turned off individually. The current mirror signal outputted by the current mirror is gradually decreased within the second time period D 2 : from the high current gradually switches to the low current with the second time period D 2 , so that the output current of the second transistor TR 2  is gradually decreased from the high current state according to the current mirror signal. The set state current IWR 0   s  is gradually decreased from the high level IH to the low level IL within the second time period D 2 , wherein the high level IH is between the set pulse level Iset and the low level IL. 
     Please refer to  FIG. 4B  together.  FIG. 4B  shows a schematic diagram of the current waveform of the reset pulse in accordance with one embodiment of the present disclosure. When the memory has to be written to the reset state, proceeding to step S 383 , the controller  140  generates a voltage mode control signal VMC to turn on the first transistor TR 1 . The current mode control signal CMC generated by the controller  140  indirectly turns off the second transistor TR 2 . As shown in  FIG. 4B  and  FIG. 2 , the reset state current IWR 0   r  of the write bit signal IWR 0  is generated, and the reset state current IWR 0   r  is switched from the low level IL to the reset pulse level Ireset, wherein the reset pulse level Ireset is higher than the set pulse level Iset. After the reset pulse level Ireset is set to continue for the third time period D 3 , the controller  140  turns off the first transistor TR 1  and the second transistor TR 2 , and the write bit signal IWR 0   r  decreased from the set pulse level Iset to the low level IL. The time period of the third time period D 3  is shorter than the first time period D 1 . The pulse signal of the reset state current IWR 0  is outputted via the decoder  180 , and the write bit signals IWR 0  to WR 31  are written to the corresponding bit lines according to the bit address decoded by the decoder  180 . 
     In an embodiment, please refer to  FIG. 5A .  FIG. 5A  shows a schematic diagram of the conventional current waveform to reset multiple memory units in accordance with one embodiment of the present disclosure. In this embodiment, there are 32 memory units, but the number is not limited thereto. When the memory unit is written to the reset state, as seen in  FIG. 5A , the reset state current IWR 0   r , the reset state current IWR 1   r , and the reset state current IWR 2   r  to the reset state current IWR 31   r  are written by the memory device  100  in a conventional approach. As shown in the current waveform, the reset state current IWR 0   r , the reset state current IWR 1   r , and the reset state current IWR 2   r  to the reset state current IWR 31   r  are all written at the time point T 0 . The memory device  100  must write 32 memory units simultaneously, and the instantaneous write current is the sum of the reset state current IWR 0   r  to the reset state current IWR 31   r  (IWR 0   r -IWR 31   r ). 
     When the memory unit is written in the set state, please refer to  FIG. 5B .  FIG. 5B  shows a schematic diagram of the conventional current waveform to set multiple memory units in accordance with one embodiment of the present disclosure. As shown in  FIG. 5B , the set state current IWR 0   s , the set state current IWR 1   s , and the set state current IWR 2   s  to the set state current IWR 31   s  are written by the memory device  100  in a conventional approach. As shown in the current waveform, the set state current IWR 0   s , the set state current IWR 1   s , and the set state current IWR 2   s  to the set state current IWR 31   s  are all written at the time point T 0 . The memory device  100  must write 32 memory units simultaneously, and the instantaneous write current is the sum of the set state current IWR 0   s  to the set state current IWR 31   s  (IWR 0   s -IWR 31   s ). 
     In a conventional approach, no matter that the memory device  100  is written to the reset state or the set state will cause a large instantaneous maximum write current. In consequence, a large-area charge pump  120  must be designed in the memory device  100  to provide sufficient instantaneous maximum write current. 
     In another embodiment, please refer to  FIG. 6A .  FIG. 6A  shows a schematic diagram of the current waveform with time sequential shift to reset the multiple memory units in accordance with one embodiment of the present disclosure. In this embodiment, there are 32 memory units, but the number is not limited thereto. When the memory unit is written to the reset state, as seen in  FIG. 6A , the reset state current IWRor, the reset state current IWRir, and the reset state current IWR 2   r  to the reset state current IWR 31   r  are written by the memory device  100 . As shown in the current waveforms, the reset state current IWRor is written at the time point T 0 , the reset state current IWRir is written at the time point T 1 , the reset state current IWR 2   r  is written at the time point T 2 , the reset state current IWR 31   r  is written at the time point T 31  and the like. It can be seen that the write operation of 32 bit lines is dispersed to 32 different time points (T 0 ˜T 31 ). In this embodiment, one write cycle includes 32 different time points. The maximum current required at each time point can be reduced to 1/32 of the write at the same time, but this disclosure is not limited to this. 
     In another embodiment, the writing operation of 32 bit lines can also be dispersed to different cycle. For example, the writing operation of 32 bit lines can be dispersed to 4 different time points. At the point T 0 , the 0th, 4th, 8th, 12th, 16th, 20th, 24th, and 28th bit lines are simultaneously written. At the time point T 1 , the 1st, 5th, 9th, 13th, 17th, 21st, 25th and 29th bit line are simultaneously written. At the time point T 2 , the 2nd, 6th, 10th, 14th, 18th, 22nd, 26th, 30th bit lines are simultaneously written. And at the time point T 3 , the 3rd, 7th, 11th, 15th, 19th, 23th, 27th, 31st bit lines are simultaneously written. In this embodiment, a write cycle contains 4 different time points. In this example, the maximum current required at each time point can be reduced to ¼ of the write at the same time. This disclosure can be configured in various different cycles, and so on, for example, divided into 8 different time points, 16 different time points or other various distributions, wherein the number of time points included in one writing cycle is not limited in the above embodiments. 
     When the memory unit is written in the set state, please refer to  FIG. 6B .  FIG. 6B  shows a schematic diagram of the current waveform with sequential time shift to set the multiple memory units in accordance with one embodiment of the present disclosure. As seen in  FIG. 6B , the set state current IWR 0   s , set state current IWR 1   s , and set state current IWR 2   s  to the set state current IWR 31   s  are written by the memory device  100  in time sequential shift approach. As shown in the current waveforms, the set state current IWR 0   s  is written at the time point T 0 , the set state current IWR 1   s  is written at the time point T 1 , the set state current IWR 2   s  is written at the time point T 2 , the set state current IWR 31   s  is written at the time point T 31 , and the like. Several time points can be designed within one cycle. The memory device  100  can be programmed to shift the write time of multiple memory units, and the maximum write current is the sum of the write currents of the same cycle. 
     No matter that the memory device  100  is written to the reset state or the set state by time sequential shift, the instantaneous maximum write current is the sum of the write currents of the same cycle. Since the required instantaneous maximum write current is smaller than the write current of conventional approach, the area of the charge pump  120  designed on the memory device  100  can be effectively reduced. 
     As a result, as described in the above embodiments, the memory device can control the writing of the reset state and the set state to the memory unit through the voltage mode control signal and the current mode control signal. The memory unit written by a time sequential shift approach could effectively reduce the area of the charge pump  120  in the memory device  100 . 
     Although the disclosure has been described in considerable detail with reference to certain embodiments thereof, it will be understood that the embodiments are not intended to limit the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the disclosure. In view of the foregoing, it is intended that the present disclosure cover modifications and variations of this disclosure provided they fall within the scope of the following claims.