Patent Publication Number: US-11043252-B2

Title: Semiconductor storage device, read method thereof, and test method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation-in-part of patent application Ser. No. 16/509,954, filed on Jul. 12, 2019, which claims the benefit of priority from Japanese Patent Application No. 2018-138970, filed on Jul. 25, 2018, and Japanese Patent Application No. 2019-095244, filed on May 21, 2019. This application further claims the benefit of priority from Japanese Patent Application No. 2019-214875, filed on Nov. 28, 2019, and Japanese Patent Application No. 2020-085395, filed on May 14, 2020. All of the aforementioned applications are incorporated herein by reference in their entireties. 
    
    
     FIELD 
     The embodiments discussed herein are related to a semiconductor storage device, a read method thereof, and a test method thereof. 
     BACKGROUND 
     There is a semiconductor storage device including memory cells including capacitors. In this semiconductor storage device, the charges accumulated in a capacitor are read to a bit line, and a voltage based on the charge amount is amplified by a sense amplifier. 
     As a reading technique of a ferroelectric memory, which is one example of the above type of semiconductor storage device, there has been proposed a bit-line GND sense technique in which a voltage needed for reading is ensured even when the power supply voltage is a low voltage. See, for example, Japanese Laid-open Patent Publication No. 2002-133857, and “Bitline GND Sensing Technique for Low-Voltage Operation FeRAM” by Shoichiro Kawashima et al., IEEE Journal of Solid-State Circuits, May 2002, Vol. 37, No. 5, pp. 592-597. 
     In the bit line GND sense technique, the charges read from a memory cell to a bit line are transferred to a charge accumulation circuit via a charge transfer circuit in such a manner that the potential of the bit line does not fluctuate when a voltage is applied to a plate line. Next, the logical value of the data stored in the memory cell is determined based on the charge amount transferred to the charge accumulation circuit. The charge transfer circuit includes a p-channel type metal-oxide-semiconductor field-effect transistor (MOSFET), which will simply be referred to as a pMOS transistor. The gate-source voltage of the pMOS transistor is initially set to match the threshold voltage of the pMOS transistor before a voltage is applied to a plate line. The gate of the pMOS transistor is controlled by an inverter amplifier that drops the output voltage based on a rise in the voltage of the bit line. In a read operation, the inverter amplifier senses a slight rise in the voltage of the bit line, causes the charges to flow by opening the gate of the pMOS transistor, and sets the voltage of the bit line back to GND (ground potential). The potential difference based on the difference in the charge amount transferred to the charge accumulation circuit between when data of logical value “1” is read and when data of logical value “0” is read is amplified by a sense amplifier, and the logical value is determined. 
     See, for example, the following documents: 
     Japanese Laid-open Patent Publication No. 2007-179664 
     Japanese Laid-open Patent Publication No. 2007-220163 
     Japanese Laid-open Patent Publication No. 2008-90937 
     Japanese Laid-open Patent Publication No. 2008-140493 
     However, recent years have seen a rise in the bit line resistance along with miniaturization of semiconductor storage devices, and the rise in the bit line voltage in a read operation has been decreased. This reduces the potential difference based on the difference in the charge amount transferred to the charge accumulation circuit between when data of logical value “1” is read and when data of logical value “0” is read. As a result, the read margin is reduced. For example, in the bit line GND sense technique, when the rise in the bit line voltage is small in a read operation, the gate of the charge transfer circuit is not sufficiently opened, and the above potential difference is not sufficiently obtained. 
     SUMMARY 
     In an aspect, there is provided a semiconductor storage device including: a memory cell which includes a first capacitor that accumulates charges of a first charge amount corresponding to data of a first logical value or data of a second logical value, reading of which causes a voltage of a bit line to change more quickly than reading of the data of the first logical value; a first reference cell which includes a second capacitor that accumulates charges of a second charge amount corresponding to data of the second logical value and which is read with the memory cell when the memory cell is read; a second reference cell which includes a third capacitor that accumulates charges of a third charge amount corresponding to data of the first logical value and which is read with the memory cell when the memory cell is read; a first read circuit which is connected to the first reference cell via a first bit line, generates a first amplified signal by amplifying a first voltage of the first bit line when the memory cell is read, and outputs a stop signal that is obtained by delaying the first amplified signal; a second read circuit which is connected to the second reference cell via a second bit line, generates a second amplified signal by amplifying a second voltage of the second bit line when the memory cell is read, receives the stop signal, and drops the second voltage to a ground potential when a voltage of the stop signal reaches a threshold; a third read circuit which is connected to the memory cell via a third bit line, generates a third amplified signal by amplifying a third voltage of the third bit line when the memory cell is read, receives the stop signal, and drops the third voltage to the ground potential when the voltage of the stop signal reaches the threshold; and a determination circuit which outputs a determination result that is obtained by determining a logical value of data stored in the memory cell based on a potential difference between the first amplified signal and the third amplified signal and a potential difference between the second amplified signal and the third amplified signal. 
     The object and advantages of the invention will be realized and attained by means of the elements and combinations particularly pointed out in the claims. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are not restrictive of the invention. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG. 1  illustrates an example of a semiconductor storage device according to a first embodiment; 
         FIG. 2  illustrates an example of a semiconductor storage device according to a second embodiment; 
         FIG. 3  illustrates an example of a memory cell array; 
         FIG. 4  illustrates an example of a sense amplifier unit; 
         FIG. 5  illustrates an example of a pre-sense amplifier connected to memory cells which function as reference cells that hold data of logical value “1”; 
         FIG. 6  illustrates an example of a pre-sense amplifier connected to memory cells that hold data of logical value “0” or “1”; 
         FIG. 7  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the second embodiment; 
         FIG. 8  illustrates an example of a pre-sense amplifier of a semiconductor storage device according to a third embodiment, the pre-sense amplifier being connected to memory cells which function as reference cells that hold data of logical value “I”; 
         FIG. 9  illustrates an example of a pre-sense amplifier of the semiconductor storage device according to the third embodiment, the pre-sense amplifier being connected to memory cells that hold data of logical value “0” or “1”; 
         FIG. 10  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the third embodiment; 
         FIG. 11  is a timing chart illustrating examples of changes of voltages of a word line, a plate line, and bit lines in a write-back operation; 
         FIG. 12  illustrates an example of a semiconductor storage device according to a fourth embodiment; 
         FIG. 13  illustrates an example of a circuit that generates a signal STOP; 
         FIG. 14  illustrates an example of a circuit that generates a detection signal PDET; 
         FIG. 15  illustrates an example of a determination circuit; 
         FIG. 16  is a timing chart illustrating an example of an operation of the determination circuit; 
         FIG. 17  illustrates an example of a pre-sense amplifier connected to memory cells which function as reference cells that hold data of logical value “1”; 
         FIG. 18  illustrates an example of a pre-sense amplifier connected to memory cells that hold data of logical value “0” or “1”; 
         FIG. 19  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the fourth embodiment; 
         FIG. 20  illustrates an example of a semiconductor storage device according to a fifth embodiment; 
         FIG. 21  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the fifth embodiment; 
         FIG. 22  illustrates an example of a semiconductor storage device according to a sixth embodiment; 
         FIG. 23  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the sixth embodiment; 
         FIG. 24  illustrates an example of a semiconductor storage device according to a seventh embodiment; 
         FIG. 25  illustrates a semiconductor storage device according to a comparative example; 
         FIG. 26  illustrates timing charts of an example in which a small margin occurs; 
         FIG. 27  illustrates an example of a pre-sense amplifier of a semiconductor storage device according to an eighth embodiment; 
         FIG. 28  illustrates an example of a selection circuit; 
         FIG. 29  illustrates an example of a test system; 
         FIG. 30  illustrates timing charts of examples of data determination results based on margins about a memory cell a; 
         FIG. 31  illustrates timing charts of examples of data determination results based on margins about a memory cell b; 
         FIG. 32  illustrates timing charts of examples of data determination results based on margins about a memory cell c; 
         FIG. 33  is a flowchart illustrating an example of a test method of a semiconductor storage device; 
         FIG. 34  illustrates an example of how the difference in the number of fail bits counted changes by changing a time at which a detection signal PDETt changes; 
         FIG. 35  illustrates another example of how the difference in the number of fail bits counted changes by changing a time at which a detection signal PDETt changes; 
         FIG. 36  illustrates an example of positional dependence of fail bits; 
         FIG. 37  illustrates an example of positional dependence of an amplified signal and a determination margin; 
         FIG. 38  illustrates an example of a semiconductor storage device according to a ninth embodiment; 
         FIG. 39  illustrates an example of a pre-sense amplifier of the semiconductor storage device according to the ninth embodiment; 
         FIG. 40  illustrates a control signal generation example; 
         FIG. 41  illustrates an example of how the positional dependence of the amplified signal and the determination margin is solved; 
         FIG. 42  illustrates an example of a semiconductor storage device according to a tenth embodiment; 
         FIG. 43  illustrates an example of a plate line driver; and 
         FIG. 44  illustrates a control signal generation example. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     Several embodiments will be described below with reference to the accompanying drawings. 
     First Embodiment 
       FIG. 1  illustrates an example of a semiconductor storage device according to a first embodiment. 
     For example, this semiconductor storage device  10  is a ferroelectric random access memory (FeRAM). The semiconductor storage device  10  includes a plurality of memory cells including a memory cell  11 , a plurality of reference cells including reference cells  12  and  13 , read circuits (which will hereinafter be referred to as pre-sense amplifiers)  14  to  16 , and a determination circuit  17 . Other components such as a column decoder, a row decoder, etc. of the semiconductor storage device  10  are not illustrated in  FIG. 1 . 
     The following description assumes that the reference cells  12  and  13  hold data of logical values “1” and “0”, respectively. However, the reference cells  12  and  13  may hold data of the logical values “0” and “1”, respectively. 
     The memory cell  11  includes an n-channel type MOSFET (which will hereinafter be referred to as an nMOS transistor)  11   a  and a capacitor  11   b . The gate of the nMOS transistor  11   a  is connected to a word line WL. One of the drain and the source of the nMOS transistor  11   a  is connected to a bit line BL, and the other one of the drain and the source is connected to one end of the capacitor  11   b . The other end of the capacitor  11   b  is connected to a plate line PL. 
     The reference cell  12  includes an nMOS transistor  12   a  and a capacitor  12   b . The gate of the nMOS transistor  12   a  is connected to the word line WL. One of the drain and the source of the nMOS transistor  12   a  is connected to a bit line BLR 1 , and the other one of the drain and the source is connected to one end of the capacitor  12   b . The other end of the capacitor  12   b  is connected to the plate line PL. 
     The reference cell  13  includes an nMOS transistor  13   a  and a capacitor  13   b . The gate of the nMOS transistor  13   a  is connected to the word line WL. One of the drain and the source of the nMOS transistor  13   a  is connected to a bit line BLR 0 , and the other one of the drain and the source is connected to one end of the capacitor  13   b . The other end of the capacitor  13   b  is connected to the plate line PL. 
     When the memory cell  11  is read, the reference cells  12  and  13  are also read. 
     While not illustrated in  FIG. 1 , other than the memory cell  11 , a plurality of memory cells, each of which is connected to a different word line and plate line, are also connected to the bit line BL. In addition, a plurality of memory cells connected to different word lines and plate lines are also connected to other bit lines. These memory cells have the same configuration as that of the memory cell  11 . In addition, other than the reference cells  12  and  13 , a plurality of reference cells connected to different word lines and plate lines are connected to the bit lines BLR 1  and BLR 0 . These memory cells have the same configuration as that of the reference cell  12  or  13 . 
     While the following description assumes that the capacitors  11   b ,  12   b , and  13   b  are ferroelectric capacitors, other capacitors may alternatively be used. 
     The capacitor  11   b  in the memory cell  11  holds charges of a charge amount corresponding to data of logical value “0” or “1”. In contrast, the capacitor  12   b  in the reference cell  12  holds charges of a charge amount corresponding to data of logical value “l”. In addition, the capacitor  13   b  in the reference cell  13  holds charges of a charge amount corresponding to data of logical value “0”. Reading of the data of logical value “1” causes the voltage of a bit line to change more quickly than reading of the data of logical value “0” does. 
     The pre-sense amplifier  14  is connected to the memory cell  11  via the bit line BL and generates an amplified signal Pout by amplifying the voltage of the bit line BL when the memory cell  11  is read. In addition, when the pre-sense amplifier  14  drops the voltage of the bit line BL to GND when the voltage of a signal STOP (described later) outputted by the pre-sense amplifier  15  reaches a predetermined threshold or more. 
     The pre-sense amplifier  14  includes an initialization circuit  14   a , an amplifier circuit  14   b , and a reset circuit  14   c.    
     The initialization circuit  14   a  is connected to the bit line BL and drops the voltage of the bit line BL to GND based on a control signal BUSGND. For example, the initialization circuit  14   a  includes an nMOS transistor  14   a   1 . The gate of the nMOS transistor  14   a   1  is supplied with the control signal BUSGND. The source of the nMOS transistor  14   a   1  is connected to ground, and the drain is connected to the bit line BL. The control signal BUSGND is supplied from a timing generation circuit (not illustrated). 
     The amplifier circuit  14   b  amplifies the voltage of the bit line BL. For example, the amplifier circuit  14   b  includes capacitors  14   b   1  and  14   b   3  and inverters  14   b   2  and  14   b   4 . One end of the capacitor  14   b   1  is connected to the bit line BL, and the other end of the capacitor  14   b   1  is connected to the input terminal of the inverter  14   b   2 . The output terminal of the inverter  14   b   2  is connected to one end of the capacitor  14   b   3 , and the other end of the capacitor  14   b   3  is connected to the input terminal of the inverter  14   b   4 . The output terminal of the inverter  14   b   4  is connected to the reset circuit  14   c . In addition, in the example of the pre-sense amplifier  14  in  FIG. 1 , the output signal of the inverter  14   b   4  is the amplified signal Pout, which is an output signal of the pre-sense amplifier  14 . 
     When the voltage of the signal STOP reaches a predetermined threshold or more, the reset circuit  14   c  drops the voltage of the bit line BL to GND. The reset circuit  14   c  includes an nMOS transistor  14   c   1  and a detection circuit  14   c   2 . The gate of the nMOS transistor  14   c   1  is supplied with the signal STOP. The source of the nMOS transistor  14   c   1  is connected to ground, and the drain is connected to the bit line BL. The above threshold is the threshold voltage Vth of the nMOS transistor  14   c   1 . 
     The detection circuit  14   c   2  in the pre-sense amplifier  14  is not active. The detection circuit  14   c   2  is arranged to match the load of the pre-sense amplifier  14  and the load of the pre-sense amplifier  15  including a detection circuit  15   c   2  corresponding to the detection circuit  14   c   2 . However, the pre-sense amplifier  14  may be configured without the detection circuit  14   c   2 . 
     The other bit lines connected to a plurality of memory cells are also connected to pre-sense amplifiers having the same configuration as that of the pre-sense amplifier  14 . 
     The pre-sense amplifier  15  is connected to the reference cell  12  via the bit line BLR 1  and generates an amplified signal Pout 1  by amplifying the voltage of the bit line BLR 1  when the memory cell  11  is read. In addition, the pre-sense amplifier  15  outputs the signal STOP, which is obtained by delaying the amplified signal Pout 1 . 
     As is the case with the pre-sense amplifier  14 , the pre-sense amplifier  15  includes an initialization circuit  15   a , an amplifier circuit  15   b , and a reset circuit  15   c . For example, the initialization circuit  15   a  includes an nMOS transistor  15   a   1 , and the amplifier circuit  15   b  includes capacitors  15   b   1  and  15   b   3  and inverters  15   b   2  and  15   b   4 . For example, the reset circuit  15   c  includes an nMOS transistor  15   c   1  and a detection circuit  15   c   2 . 
     These circuit elements are connected in the same way as those in the pre-sense amplifier  14 , except the reset circuit  15   c.    
     The detection circuit  15   c   2  in the reset circuit  15   c  in the pre-sense amplifier  15  outputs the signal STOP, which is obtained by delaying the output signal (amplified signal Pout 1 ) of the amplifier circuit  15   b . For example, the detection circuit  15   c   2  may be configured by using an even number of stages of inverters or delay circuits. 
     The pre-sense amplifier  16  is connected to the reference cell  13  via the bit line BLR 0  and generates an amplified signal Pout 0  by amplifying the voltage of the bit line BLR 0  when the memory cell  11  is read. The pre-sense amplifier  16  may have the same circuit configuration as that of the pre-sense amplifier  15 . In the example of the semiconductor storage device  10  in  FIG. 1 , the pre-sense amplifier  16  does not output the signal STOP. 
     The determination circuit  17  outputs a determination result that is obtained by determining the logical value of the data of the memory cell  11  based on the potential difference between the amplified signals Pout and Pout 1  and the potential difference between the amplified signals Pout and Pout 0 . 
     For example, the determination circuit  17  includes a sense amplifier that amplifies the potential difference between the amplified signals Pout and Pout 1  and a sense amplifier that amplifies the potential difference between the amplified signals Pout and Pout 0 . These two sense amplifiers have output terminals that are short-circuited. The determination circuit  17  determines a determination result by amplifying the larger one of the potential differences more greatly first and subordinating the other sense amplifier. 
     Hereinafter, an example of a read operation of the semiconductor storage device  10  according to the first embodiment will be described. The following example assumes that the logic level of the control signal BUSGND is a low (L) level. In  FIG. 1 , how the voltages of the word line WL, the plate line PL, the bit line BL, the amplified signal Pout, and the signal STOP change over time are illustrated. 
     At timing t 1 , when a predetermined voltage (a voltage equal to or more than the threshold voltage of the nMOS transistors  11   a ,  12   a , and  13   a ) is applied to the word line WL, the nMOS transistors  11   a ,  12   a , and  13   a  are set to an on-state. 
     Next, at timing t 2 , when a predetermined voltage (a read voltage) is applied to the plate line PL, the charges based on the charge amount accumulated in the capacitor  11   b  is read to the bit line BL. As a result, the voltage of the bit line BL rises. In the example in  FIG. 1 , the case in which data of logical value “1” is stored in the memory cell  11  causes the voltage of a bit line BL to change more quickly than the case in which data of logical value “0” is stored in the memory cell  11  does. When the voltage of the bit line BL rises, the voltage of the amplified signal Pout also rises. 
     While not illustrated in  FIG. 1 , the voltage of the amplified signal Pout 1  changes in the same way as the voltage of the amplified signal Pout does when data of logical value “1” is stored in the memory cell  11 . In addition, the voltage of the amplified signal Pout 0  changes in the same way as the voltage of the amplified signal Pout does when data of logical value “0” is stored in the memory cell  11 . 
     Next, when the signal STOP supplied to the pre-sense amplifier  14  reaches the threshold voltage Vth of the nMOS transistor  14   c   1  (timing t 3 ), the nMOS transistor  14   c   1  are set to an on-state, and the voltage of the bit line BL drops to GND. 
     If the nMOS transistor  14   c   1  remains off, the voltage of the bit line BL continues to rise. In this case, as indicated by a dotted line, the amplified signal Pout rises even after timing t 3  also at the time of reading data of logical value “0”. When data of logical value “1” is read, since the rise of the amplified signal Pout is saturated at a power supply voltage VDD, the difference in the amplified signal Pout between the two logical values is reduced. As a result, the read margin is reduced. If the resistance of the bit line BL increases along with the miniaturization of the semiconductor storage device  10 , the voltage of the bit line BL rises less. Consequently, the difference in the amplified signal Pout between the two logical values is reduced further. Therefore, the determination circuit  17  could fail to obtain an accurate determination result. 
     In contrast, with the semiconductor storage device  10  according to the first embodiment, since the voltage of the bit line BL drops to GND at timing t 3 , the rise of the amplified signal Pout stops even when data of logical value “0” is read. Thus, the reduction in the difference in the amplified signal Pout when data of the two logical values is read is prevented, and the reduction in the read margin is prevented. Thus, the reliability of the semiconductor storage device  10  is improved. 
     In addition, in the example in  FIG. 1 , the delay time of the signal STOP with respect to the amplified signal Pout 1  is set in the detection circuit  15   c   2  in such a manner that the signal STOP reaches the threshold voltage Vth at the timing at which the amplified signal Pout corresponding to when data of logical value “1” is read is saturated. In this way, the read margin is widened further. 
     While the above description assumes that the pre-sense amplifier  16  does not output the signal STOP, the pre-sense amplifier  16  may also output the signal STOP, as is the case with the pre-sense amplifier  15 . In this case, for example, an OR circuit that outputs a result of an OR operation on the signals STOP outputted by the pre-sense amplifiers  15  and  16  is arranged. This configuration enables the semiconductor storage device  10  to manage a case in which data of logical values “0” and “1” is stored in the reference cells  12  and  13 , respectively. 
     Second Embodiment 
       FIG. 2  illustrates an example of a semiconductor storage device according to a second embodiment. 
     This semiconductor storage device  20  according to the second embodiment includes an address buffer  21 , a command buffer  22 , a row decoder  23 , a timing generation circuit  24 , a column decoder  25 , a plate line driver  26 , and a word line driver  27 . The semiconductor storage device  20  also includes a memory cell array  28 , a column switch  29 , a sense amplifier unit  30 , a write buffer  31 , and a read buffer  32 . 
     The address buffer  21  receives an address signal ADS supplied from the outside of the semiconductor storage device  20  via an address terminal  21   a  and supplies the received address signal ADS to the row decoder  23  and the column decoder  25 . 
     The command buffer  22  receives a chip select signal /CS, a write enable signal /WE, and an output enable signal /OE supplied from the outside of the semiconductor storage device  20  via command terminals  22   a  to  22   c . Next, the command buffer  22  supplies the received chip select signal /CS, write enable signal /WE, and output enable signal /OE to the timing generation circuit  24 . 
     The row decoder  23  generates a row decoded signal by decoding a row address included in the address signal ADS (for example, a high-order bit in the address signal ADS) and supplies the generated row decoded signal to the plate line driver  26  and the word line driver  27 . 
     The timing generation circuit  24  decodes an operation mode indicated by the chip select signal /CS, the write enable signal /WE, and the output enable signal /OE. Next, based on the result of the decoding, the timing generation circuit  24  generates various kinds of timing signals for operating the plate line driver  26 , the word line driver  27 , the sense amplifier unit  30 , etc. and supplies the generated timing signals to the corresponding units. 
     The column decoder  25  generates a column decoded signal by decoding a column address included in the address signal ADS (for example, a low-order bit in the address signal ADS) and supplies the generated column decoded signal to the column switch  29 . 
     The plate line driver  26  applies a predetermined voltage to a plate line specified by the row decoded signal among a plurality of plate lines (not illustrated in  FIG. 2 ) at timing based on the corresponding timing signal for a predetermined period. 
     The word line driver  27  applies a predetermined voltage to a word line specified by the row decoded signal among a plurality of word lines (not illustrated in FIG.  2 ) at timing based on the corresponding timing signal for a predetermined period. 
     The memory cell array  28  includes a plurality of memory cells arranged in a matrix, a plurality of bit lines, a plurality of word lines, and a plurality of plate lines (see  FIG. 3 ). 
     The column switch  29  selects a bit line to be connected to the sense amplifier unit  30  and the write buffer  31  among the plurality of bit lines in the memory cell array  28 , based on the column decoded signal. 
     The sense amplifier unit  30  reads data from the memory cell array  28  at timing based on a plurality of timing signals supplied from the timing generation circuit  24 . 
     The write buffer  31  holds write data supplied via an input-output terminal  31   a . The write buffer  31  also has a function of holding data read by the sense amplifier unit  30  for a write back operation. 
     The read buffer  32  holds read data read from the memory cell array  28  by the sense amplifier unit  30 . The read data is outputted to the outside of the semiconductor storage device  20  via the input-output terminal  31   a.    
       FIG. 3  illustrates an example of the memory cell array  28 . 
     The memory cell array  28  includes bit lines BLR 0 , BLR 1 , BL[ 0 ], . . . , BL[L−1], and BL[L], word lines WL 1  to WLm, and plate lines PL 1  to PLm. Each of the bit lines BLR 0 , BLR 1 , and BL[ 0 ] to BL[L] is connected to m memory cells. For example, the bit line BLR 0  is connected to memory cells  28   a   1  to  28   am , and the bit line BLR 1  is connected to memory cells  28   b   1  to  28   bm . Likewise, the bit line BL[ 0 ] is connected to memory cells  28   c   1  to  28   cm , and the bit line BL[L−1] is connected to memory cells  28   d   1  to  28   dm . Likewise, the bit line BL[L] is connected to memory cells  28   e   1  to  28   em.    
     Each of the memory cells is connected to one of the word lines WL 1  to WLm and one of the plates line PL 1  to PLm. For example, the memory cells  28   am ,  28   bm ,  28   cm ,  28   dm , and  28   em  are connected to the word line WLm and the plate line PLm, and the memory cells  28   a   1 ,  28   b   1 ,  28   c   1 ,  28   d   1 , and  28   e   1  are connected to the word line WL 1  and the plate line PL 1 . 
     Each of the memory cells includes an nMOS transistor (which could be referred to as an access transistor or an access gate) and a capacitor. For example, the memory cell  28   am  includes an nMOS transistor  28   am   1  and a capacitor  28   am   2 . The gate of the nMOS transistor  28   am   1  is connected to the word line WLm. One of the drain and the source of the nMOS transistor  28   am   1  is connected to the bit line BLR 0 , and the other one of the drain and the source is connected to one end of the capacitor  28   am   2 . The other end of the capacitor  28   am   2  is connected to the plate line PLm. The other memory cells have the same circuit configuration as described above. 
     While the following description will be made assuming that the capacitor included in an individual memory cell is a ferroelectric capacitor, a different capacitor other than a ferroelectric capacitor may alternatively be used. 
     In this memory cell array  28 , for example, each of the memory cells  28   a   1  to  28   am  connected to the bit line BLR 0  functions as a reference cell that holds data of logical value “0”. In addition, each of the memory cells  28   b   1  to  28   bm  connected to the bit line BLR 1  functions as a reference cell that holds data of logical value “1”. The memory cells connected to the other bit lines BL[ 0 ] to BL[L] hold data of logical value “0” or “1”. 
     When data is read, L+3 memory cells connected to one of the word lines WL 1  to WLm (or the plate lines PL 1  to PLm) and connected to the bit lines BLR 0 , BLR 1 , and BL[ 0 ] to BL[L] are simultaneously selected. Alternatively, N (N≥2) groups of memory cells, each group being formed by L+3 memory cells simultaneously selected as described above, may be connected to each of the word lines WL 1  to WLm and the plate lines PL 1  to PLm. 
       FIG. 4  illustrates an example of the sense amplifier unit  30 . 
     The sense amplifier unit  30  includes a plurality of pre-sense amplifiers (pre-sense amplifier  30   a ,  30   b ,  30   c ,  30   d , etc.) and a plurality of sense amplifiers (sense amplifiers  30   e ,  30   f ,  30   g ,  30   h , etc.). In  FIG. 4 , each of the pre-sense amplifiers is denoted by “PA”, and each of the sense amplifiers is denoted by “S/A”. 
     The pre-sense amplifier  30   a  amplifies the voltage of the bit line BLR 0 , and the pre-sense amplifier  30   b  amplifies the voltage of the bit line BLR 1 . The pre-sense amplifier  30   c  amplifies the voltage of the bit line BL[L−1], and the pre-sense amplifier  30   d  amplifies the voltage of the bit line BL[L]. In addition, the pre-sense amplifier  30   b  supplies a signal STOP to the pre-sense amplifiers  30   a ,  30   c , and  30   d.    
     Each of the sense amplifiers  30   e  and  30   f  has a first input terminal. These first input terminals are connected to each other and supplied with an output signal of the pre-sense amplifier  30   c . In addition, the sense amplifier  30   e  has a second input terminal that is supplied with an output signal of the pre-sense amplifier  30   b , and the sense amplifier  30   f  has a second input terminal that is supplied with an output signal of the pre-sense amplifier  30   a.    
     Each of the sense amplifiers  30   e  and  30   f  obtains the potential difference between the corresponding two output signals inputted to its own first and second input terminals. One of the sense amplifiers  30   e  and  30   f  that has obtained the larger potential difference performs amplification more greatly first, and the other sense amplifier is subordinated. In this way, a determination result of the logical value of the read data is determined. 
     Each of the sense amplifiers  30   g  and  30   h  has a first input terminal. These first input terminals are connected to each other and supplied with an output signal of the pre-sense amplifier  30   d . In addition, the sense amplifier  30   g  has a second input terminal that is supplied with an output signal of pre-sense amplifier  30   b , and the sense amplifier  30   h  has a second input terminal that is supplied with an output signal of the pre-sense amplifier  30   a.    
     Each of the sense amplifiers  30   g  and  30   h  obtains the potential difference between the corresponding two output signals inputted to its own first and second input terminals. One of the sense amplifiers  30   g  and  30   h  that has obtained the larger potential difference performs amplification more greatly first, and the other sense amplifier is subordinated. In this way, a determination result of the logical value of the read data is determined. 
     In addition, the sense amplifiers  30   e ,  30   f ,  30   g , and  30   h  are supplied with a signal SAON, which is one of the timing signals outputted by the timing generation circuit  24 , and a signal SAONB, which is an inverted signal of the signal SAON. 
     An example of the circuit configuration of the sense amplifier  30   g  is illustrated in  FIG. 4 . 
     The sense amplifier  30   g  includes pMOS transistors  30   g   1 ,  30   g   2 , and  30   g   3  and nMOS transistors  3094 ,  30   g   5 , and  30   g   6 . The sense amplifier  30   g  also includes switches  30   g   7  and  30   g   8 , each of which is formed by an nMOS transistor and a pMOS transistor. 
     The source of the pMOS transistor  30   g   1  is supplied with a power supply voltage VDD, and the gate of the pHOS transistor  30   g   1  is supplied with the inverted signal SAONB. The drain of the pMOS transistor  30   g   1  is connected to the sources of the pMOS transistors  30   g   2  and  30   g   3 . The drains of the pMOS transistor  30   g   3  and the nMOS transistor  30   g   5  are connected to the second input terminal of the sense amplifier  30   g  via the switch  30   g   7 . The drains of the pMOS transistor  30   g   3  and the nMOS transistor  30   g   5  are connected to the gates of the pMOS transistor  30   g   2  and the nMOS transistor  30   g   4 . The drains of the pMOS transistor  30   g   2  and the nMOS transistor  30   g   4  are connected to the first input terminal of the sense amplifier  30   g  via the switch  30   g   8 . The drains of the pMOS transistor  30   g   2  and the nMOS transistor  30   g   4  are connected to the gates of the pMOS transistor  30   g   3  and the nMOS transistor  30   g   5 . The sources of the nMOS transistors  30   g   4  and  30   g   5  are connected to the drain of the nMOS transistor  30   g   6 . The source of the nMOS transistor  30   g   6  is connected to ground, and the gate of the nMOS transistor  30   g   6  is supplied with the signal SAON. 
     The gates of the pMOS transistors of the switches  30   g   7  and  30   g   8  are supplied with the signal SAON, and the gates of the nMOS transistors of the switches  30   g   7  and  30   g   8  are supplied with the inverted signal SAONB. With the signal SAON and the inverted signal SAONB, the switches  30   g   7  and  30   g   8  are set to a conductive state before a sensing operation and to a disconnected state when the sensing operation is started. 
     The other sense amplifiers have the same circuit configuration as that of the sense amplifier  30   g . In each of the sense amplifiers  30   g  and  30   h , a switch having one end connected to its first input terminal (the switch  30   g   8  in the case of the sense amplifier  30   g ) has the other end connected to the other switch. Likewise, in each of the sense amplifiers  30   e  and  30   f , a switch having one end connected to its first input terminal has the other end connected to the other switch. 
     While not illustrated, the sense amplifier unit  30  includes pre-sense amplifiers that amplify the voltages of other bit lines and sense amplifier pairs that determine the logical values of data. 
     Next, an example of the pre-sense amplifier  30   b  will be described. 
       FIG. 5  illustrates an example of the pre-sense amplifier  30   b  connected to memory cells which function as reference cells that hold data of logical value “1”. 
     The pre-sense amplifier  30   b  is connected to the memory cell  28   bm  (including the nMOS transistor  28   bm   1  and the capacitor  28   bm   2 ) that functions as a reference cell that holds data of logical value “1” via the bit line BLR 1 . 
     The pre-sense amplifier  30   b  includes an initialization circuit  41 , an amplifier circuit  42 , a threshold voltage generation circuit  43 , a reset circuit  44 , a waveform shaping circuit  45 , and an output reset circuit  46 . 
     The initialization circuit  41  is connected to the bit line BLR 1  and drops the voltage of the bit line BLR 1  to GND based on the control signal BUSGND. The initialization circuit  41  includes an nMOS transistor  41   a . The gate of the nMOS transistor  41   a  is supplied with the control signal BUSGND. The source of the nMOS transistor  41   a  is connected to ground, and the drain of the nMOS transistor  41   a  is connected to the bit line BLR 1 . The control signal BUSGND is supplied from the timing generation circuit  24 . 
     The amplifier circuit  42  amplifies the voltage of the bit line BLR 1 . The amplifier circuit  42  includes capacitors  42   a  and  42   f , an inverter  42   b , pMOS transistors  42   c  and  42   g , nMOS transistors  42   d  and  42   h , and a switch  42   e.    
     One end of the capacitor  42   a  is connected to the bit line BLR 1 , and the other end of the capacitor  42   a  is connected to the input terminal of the inverter  42   b  and one end of the switch  42   e . The output terminal of the inverter  42   b  is connected to one end of the capacitor  42   f  and the other end of the switch  42   e . In addition, the power supply terminal of the inverter  42   b  is connected to the drain of the pMOS transistor  42   c , and the ground terminal of the inverter  42   b  is connected to the drain of the nMOS transistor  42   d . The control signal inputted to the switch  42   e  is supplied from the timing generation circuit  24 . 
     The power supply voltage VDD is applied to the source of the pMOS transistor  42   c , and the gate of the pMOS transistor  42   c  is supplied with a power control signal POWX. The source of the nMOS transistor  42   d  is connected to ground, and the gate of the nMOS transistor  42   d  is supplied with a power control signal POW. The power control signals POWX and POW are mutually complementary signals and supplied from the timing generation circuit  24 . 
     The other end of the capacitor  42   f  is connected to the gate of the pMOS transistor  42   g  and the threshold voltage generation circuit  43 . The power supply voltage VDD is applied to the source of the pMOS transistor  42   g , and the drain of the pMOS transistor  42   g  is connected to the drain of the nMOS transistor  42   h , the reset circuit  44 , and the waveform shaping circuit  45 . The voltages of the drains of the pMOS transistor  42   g  and the nMOS transistor  42   h  represent an output signal REPLICA of the amplifier circuit  42 . The source of the nMOS transistor  42   h  is connected to ground, and the gate of the nMOS transistor  42   h  is supplied with a signal INIT. The circuit formed by the pMOS transistor  42   g  and the nMOS transistor  42   h  functions as an inverter. The signal INIT is supplied from the timing generation circuit  24 . 
     The threshold voltage generation circuit  43  generates a gate voltage VTHGT of the pMOS transistor  42   g , which is equal to the threshold voltage of the pMOS transistor  42   g . The threshold voltage generation circuit  43  includes pMOS transistors  43   a  and  43   d , an nMOS transistor  43   b , a switch  43   c , and a capacitor  43   e.    
     The power supply voltage VDD is applied to the source of the pMOS transistor  43   a , and the gate of the pMOS transistor  43   a  is supplied with a voltage control signal VGENP. In addition, the drain of the pMOS transistor  43   a  is connected to the drain of the nMOS transistor  43   b  and one end of the capacitor  43   e . The gate of the nMOS transistor  43   b  is supplied with a voltage control signal VGENN, and the source of the nMOS transistor  43   b  is connected to ground. The power supply voltage VDD is applied to one end of the switch  43   c , and the other end of the switch  43   c  is connected to the source of the pMOS transistor  43   d . The gate and drain of the pMOS transistor  43   d  and the other end of the capacitor  43   e  are connected to the gate of the pMOS transistor  42   g  in the amplifier circuit  42 . The voltage control signals VGENP and VGENN and the control signal supplied to the switch  43   c  are supplied from the timing generation circuit  24 . 
     The reset circuit  44  outputs the signal STOP and drops the voltage of the bit line BLR 1  to GND when the voltage of the signal STOP reaches a predetermined threshold or more. The reset circuit  44  includes a detection circuit  44   a  and an nMOS transistor  44   b . The detection circuit  44   a  outputs the signal STOP that is obtained by delaying the output signal REPLICA of the amplifier circuit  42 . The detection circuit  44   a  may be configured by using an even number of stages of inverters or delay circuits, for example. The gate of the nMOS transistor  44   b  is supplied with the signal STOP. The source of the nMOS transistor  44   b  is connected to ground, and the drain of the nMOS transistor  44   b  is connected to the bit line BLR 1 . 
     The waveform shaping circuit  45  shapes the waveform of the output signal REPLICA of the amplifier circuit  42 . The waveform shaping circuit  45  includes an nMOS transistor  45   a  and a pMOS transistor  45   b . The power supply voltage VDD is applied to the drain of the nMOS transistor  45   a , and the drain of the pMOS transistor  45   b  is connected to ground. The gates of the nMOS transistor  45   a  and the pMOS transistor  45   b  are supplied with the output signal REPLICA. In addition, the voltage of the drain of the nMOS transistor  45   a  and the voltage of the source of the pMOS transistor  45   b , the drain and source being connected to each other, represent the output signal of the waveform shaping circuit  45 . 
     The output reset circuit  46  drops the voltage of the output signal of the pre-sense amplifier  30   b  to GND based on a reset signal RESET. The output reset circuit  46  includes an nMOS transistor  46   a . The gate of the nMOS transistor  46   a  is supplied with the reset signal RESET. The source of the nMOS transistor  46   a  is connected to ground, and the drain of the nMOS transistor  46   a  is connected to the output terminal of the waveform shaping circuit  45 . The reset signal RESET is supplied from the timing generation circuit  24 . 
     The pre-sense amplifier  30   a  illustrated in  FIG. 4  has the same circuit configuration as that of the pre-sense amplifier  30   b  illustrated in  FIG. 5 . However, the pre-sense amplifier  30   a  of the semiconductor storage device  20  according to the second embodiment may be configured not to output the signal STOP. Alternatively, as is the case with the pre-sense amplifier  30   b , the pre-sense amplifier  30   a  may be configured to output the signal STOP. In the latter case, a logic circuit (not illustrated) performs logic synthesis on the signals STOP outputted by the pre-sense amplifiers  30   a  and  30   b  and distributes the result to the other pre-sense amplifiers. 
       FIG. 6  illustrates an example of the pre-sense amplifier  30   d  connected to memory cells that hold data of logical value “0” or “l”. 
     In the example in  FIG. 6 , the pre-sense amplifier  30   d  is connected to the memory cell  28   em  (including an nMOS transistor  28   em   1  and a capacitor  28   em   2 ) via the bit line BL[L]. 
     As is the case with the pre-sense amplifier  30   b  illustrated in  FIG. 5 , the pre-sense amplifier  30   d  includes an initialization circuit  51 , an amplifier circuit  52 , a threshold voltage generation circuit  53 , a reset circuit  54 , a waveform shaping circuit  55 , and an output reset circuit  56 . 
     The initialization circuit  51  includes an nMOS transistor  51   a , and the amplifier circuit  52  includes a capacitors  52   a  and  52   f , an inverter  52   b , pMOS transistors  52   c  and  52   g , nMOS transistors  52   d  and  52   h , and a switch  52   e . The threshold voltage generation circuit  53  includes pMOS transistors  53   a  and  53   d , an nMOS transistor  53   b , a switch  53   c , and a capacitor  53   e , and the reset circuit  54  includes a detection circuit  54   a  and an nMOS transistor  54   b . The waveform shaping circuit  55  includes an nMOS transistor  55   a  and a pMOS transistor  55   b , and the output reset circuit  56  includes an nMOS transistor  56   a.    
     The circuit elements are connected in the same way as those in the pre-sense amplifier  30   b , except the reset circuit  54 . 
     The gate of the nMOS transistor  54   b  of the reset circuit  54  in the pre-sense amplifier  30   d  is supplied with the signal STOP from the pre-sense amplifier  30   b . In addition, the detection circuit  54   a  of the reset circuit  54  in the pre-sense amplifier  30   d  is not active. The detection circuit  54   a  is arranged to match the load of the pre-sense amplifier  30   d  and the load of the pre-sense amplifier  30   b . However, the pre-sense amplifier  30   d  may alternatively be configured without the detection circuit  54   a.    
     Next, an example of a read operation of the semiconductor storage device  20  according to the second embodiment will be described. 
       FIG. 7  is a timing chart illustrating an example of a read operation of the semiconductor storage device  20  according to the second embodiment. 
     In  FIG. 7 , examples of how the voltages of the word line WLm, the plate line PLm, the power control signals POW and POWX, the control signal BUSGND, the control signals SW 1  and SW 2  inputted to the switches  52   e  and  53   c , and the voltage control signals VGENP and VGENN change over time are illustrated. In  FIG. 7 , how the voltages of the signal INIT, the reset signal RESET, and the bit line BL[L], the input voltage IIN of the inverter  52   b , the output voltage IOUT of the inverter  52   b , the gate voltage VTHGT, the output signal REPLICA, and the signal STOP change over time are also illustrated. The following description assumes that the ground potential is 0 V. 
     First, in an initial state, both of the voltages of the word line WLm and the plate line PLm are at an L level (for example, 0 V). In addition, the logic level of the power control signal POW is at an L level, and the logic level of the power control signal POWX is at an H level (for example, the power supply voltage VDD). Since the pMOS transistor  52   c  and the nMOS transistor  52   d  are both in an off-state, the inverter  52   b  is not active. In addition, the logic level of the control signal BUSGND is at an H level, and the nMOS transistor  51   a  is in an on-state. Thus, the voltage of the bit line BL[L] is 0 V. 
     Based on the control signals SW 1  and SW 2 , the switches  52   e  and  53   c  are in an on-state. In addition, since both the logic levels of the voltage control signals VGENP and VGENN are at an L level, the pMOS transistor  53   a  is in an on-state, and the nMOS transistor  53   b  is in an off-state. Both of the logic levels of the signal INIT and the reset signal RESET are set at an H level, and the nMOS transistors  52   h  and  56   a  are in an on-state. Thus, the output signal REPLICA and the output signal (not illustrated) of the pre-sense amplifier  30   d  are 0 V. 
     Since the input terminal and the output terminal of the inverter  52   b  are short-circuited, both of the input voltage IIN and the output voltage IOUT are about ½ of the power supply voltage VDD. In addition, the gate voltage VTHGT is equal to the power supply voltage VDD, and the signal STOP supplied from the pre-sense amplifier  30   b  to the pre-sense amplifier  30   d  is 0 V. 
     At timing T 1 , when the logic level of the power control signal POW changes to an H level and when the logic level of the power control signal POWX changes to an L level, the inverter  52   b  is activated. Since the switch  52   e  remains in an on-state, both of the input voltage IIN and the output voltage IOUT of the inverter  52   b  are about VDD/2. In addition, at timing T 1 , both the logic levels of the signal INIT and the reset signal RESET change to an L level, and the nMOS transistors  52   h  and  56   a  are set to an off-state. 
     At timing T 2 , when both of the logic levels of the voltage control signals VGENP and VGENN change to an H level, the drain voltages of the pMOS transistor  53   a  and the nMOS transistor  53   b  drop. This voltage change causes capacitive coupling of the capacitor  53   e  and drops the gate voltage VTHGT. For example, when the power supply voltage VDD is 1.8 V, if the drain voltages of the pMOS transistor  53   a  and the nMOS transistor  53   b  drop by 1.8 V, the gate voltage VTHGT also begins to drop by 1.8 V. 
     However, since the switch  53   c  is in an on-state, the pMOS transistor  53   d  functions as a clamp circuit and clamps the gate voltage VTHGT at the threshold voltage of the pMOS transistor  52   g  (for example, VDD—0.6 V). Thus, after dropping to some extent, the gate voltage VTHGT rises back to the threshold voltage, forming a differentiated waveform. In this way, the threshold voltage generation circuit  53  functions as an initialization circuit that sets the gate voltage VTHGT to a predetermined voltage. 
     At timing T 3 , when a predetermined voltage (for example, the power supply voltage VDD) is applied to the word line WLm, the nMOS transistor  28   em   1  of the memory cell  28   em  connected to the word line WLm is set to an on-state, and the data is set to be readable. 
     At timing T 4 , when the logic level of the voltage control signal VGENN changes to an L level, the nMOS transistor  53   b  of the threshold voltage generation circuit  53  is set to an off-state. Since the pMOS transistor  53   a  has already been in an off-state, the drains of the pMOS transistor  53   a  and the nMOS transistor  53   b  are set to a floating state. 
     At timing T 4 , the switches  52   e  and  53   c  are also set to an off-state. Since the switch  52   e  is set to an off-state, the short-circuiting of the input terminal and the output terminal of the inverter  52   b  is canceled. Since the input voltage IIN of the inverter  52   b  is about VDD/2, the inverter  52   b  operates as an inversion amplifier having a high gain. In addition, since the switch  53   c  is set to an off-state, the pMOS transistor  53   d  cancels the clamping of the gate voltage VTHGT. 
     In addition, at timing T 4 , the logic level of the control signal BUSGND changes to an L level, and the bit line BL[L] is set to a floating state. As a result, if the voltage of the bit line BL[L] changes after timing T 4 , the input voltage IIN of the inverter  52   b  changes based on capacitive coupling of the capacitor  52   a . The inverter  52   b  amplifies the change of the input voltage IIN and changes the output voltage IOUT in the opposite direction to the change of the input voltage IIN. In addition, based on capacitive coupling of the capacitor  52   f , the gate voltage VTHGT changes with the change of the output voltage IOUT. 
     At timing T 5 , a predetermined voltage (for example, the power supply voltage VDD) is applied to the plate line PLm. The predetermined voltage has already been applied to the word line WLm at timing T 3 , and the nMOS transistor  28   em   1  of the memory cell  28   em  has already been in an on-state. Thus, when the predetermined voltage is applied to the plate line PLm, a positive voltage is applied to the capacitor  28   em   2 . 
     When data of logical value “1” is stored in the memory cell  28   em , since the polarity of the voltage applied to the capacitor  28   em   2 , which is a ferroelectric capacitor, is opposite to the polarity when the data is written, polarization reversal occurs. As a result, a large number of reverse charges are read to the bit line BL[L]. In contrast, when data of logical value “0” is stored in the memory cell  28   em , the polarity of the voltage applied to the capacitor  28   em   2  is the same as the polarity when the data is written, polarization reversal does not occur. As a result, a relatively small number of charges are read to the bit line BL[L]. At this point, the voltage of the bit line BL[L] begins to rise. When the voltage of the bit line BL[L] has slightly risen, the input voltage IIN of the inverter  52   b  rises based on capacitive coupling of the capacitor  52   a . The inverting amplification effect of the inverter  52   b  and the capacitive coupling of the capacitor  52   f  drop the gate voltage VTHGT and set the pMOS transistor  52   g  to an on-state. As a result, the voltage of the output signal REPLICA begins to rise. As described above, the pHOS transistor  52   g  functions as a read circuit that generates a read voltage based on the charges accumulated in the memory cell  28   em.    
     When the data in the memory cell  28   em  is read, the data in the other memory cells connected to the word line WLm is also read simultaneously. The voltage of the output signal REPLICA in the pre-sense amplifier  30   b  connected to the memory cell  28   bm  of all these memory cells rises more quickly than the voltages of the output signals REPLICA in the pre-sense amplifiers connected to any other memory cells that hold data of logical value “0”. In addition, the pre-sense amplifier  30   b  outputs the signal STOP that is obtained by delaying the output signal REPLICA. 
     In the example in  FIG. 7 , when data of logical value “1” is read, the voltage of the signal STOP reaches the threshold voltage VTH of the nMOS transistor  54   b  at timing T 6  in which the output signal REPLICA is saturated. As a result, the nMOS transistor  54   b  is set to an on-state, the voltage of the bit line BL[L] beings to drop to 0 V, and the output signal REPLICA stops to rise. 
     Next, at timing T 7 , since the logic levels of the signal INIT and the reset signal RESET change to an H level, the output signal REPLICA and the output signal (not illustrated) of the pre-sense amplifier  30   d  are reset to 0 V. As a result, after a predetermined period of time, the logic level of the signal STOP also changes to an L level (timing T 8 ). 
     For example, the timing generation circuit  24  receives the signal STOP, and supplies, when the logic level of the signal STOP is at an H level, the signal SAON and the inverted signal SAONB that enable the sense amplifiers  30   g ,  30   h , etc. to the sense amplifier unit  30 . With this configuration, between timing T 6  and T 7 , the read data is determined by the sense amplifiers  30   g ,  30   h , etc. 
     If the nMOS transistor  54   b  remained off even after the above timing T 6 , the voltage of the bit line BL[L] would continue to rise, and as indicated by a dotted line, the output signal REPLICA would rise even after the data of logical value “0” is read. When data of logical value “1” is read, since the rise of the output signal REPLICA is saturated at the power supply voltage VDD, the difference in the output signal REPLICA between two logical values would be reduced, and the read margin would be reduced. Thus, an accurate determination result could not be obtained in the data determination processing by using the sense amplifiers  30   g  and  30   h.    
     In contrast, in the case of the semiconductor storage device  20  according to the second embodiment, since the voltage of the bit line BL[L] drops to 0 V at timing T 6 , the rise of the output signal REPLICA stops even when data of logical value “0” is read. Thus, the reduction in the difference in the output signal REPLICA obtained when data of the two logical values is read is prevented, and the reduction in the read margin is consequently prevented. Therefore, the reliability of the semiconductor storage device  20  is improved. 
     Third Embodiment 
     Next, a semiconductor storage device according to a third embodiment will be described. The semiconductor storage device according to the third embodiment includes pre-sense amplifiers different from those of the semiconductor storage device  20  according to the second embodiment. 
       FIG. 8  illustrates an example of a pre-sense amplifier  60  of the semiconductor storage device according to the third embodiment, the pre-sense amplifier  60  being connected to memory cells which function as reference cells that hold data of logical value “1”. 
       FIG. 9  illustrates an example of a pre-sense amplifier  70  of the semiconductor storage device according to the third embodiment, the pre-sense amplifier  70  being connected to memory cells that hold data of logical value “0” or “1”. In  FIGS. 5, 6, 8, and 9 , like reference characters refer to like elements. 
     Amplifier circuits  61  and  71  in the pre-sense amplifiers  60  and  70  illustrated in  FIGS. 8 and 9  are different from the amplifier circuits  42  and  52  in the pre-sense amplifiers  30   b  and  30   d  of the semiconductor storage device  20  according to the second embodiment. The amplifier circuit  61  in  FIG. 8  includes an nMOS transistor  61   a  and an inverter  61   b  in addition to the elements included in the amplifier circuit  42 . Likewise, the amplifier circuit  71  in  FIG. 9  includes an nMOS transistor  71   a  and an inverter  71   b  in addition to the elements included in the amplifier circuit  52 . 
     In the amplifier circuit  61  in  FIG. 8 , the drain of the nMOS transistor  61   a  is connected to the output terminal of an inverter  42   b  and the input terminal of the inverter  61   b , and the source of the nMOS transistor  61   a  is connected to ground. The gate of the nMOS transistor  61   a  is connected to the output terminal of the inverter  61   b.    
     In amplifier circuit  71  in  FIG. 9 , the drain of the nMOS transistor  71   a  is connected to the output terminal of an inverter  52   b  and the input terminal of the inverter  71   b , and the source of the nMOS transistor  71   a  is connected to ground. In addition, the gate of the nMOS transistor  71   a  is connected to the output terminal of the inverter  71   b.    
     Since the amplifier circuits  61  and  71  include the nMOS transistors  61   a  and  71   a  and the inverters  61   b  and  71   b , the output voltages IOUT of the inverters  42   b  and  52   b  drops more quickly. 
       FIG. 10  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the third embodiment. 
     The operations at timing T 10 , T 11 , T 12 , and T 13  are the same as those at timing T 1  to T 4  in the case of the semiconductor storage device  20  illustrated in  FIG. 7 . 
     At timing T 14 , based on the rise of the input voltage IIN, the inverter  42   b  in the amplifier circuit  61  in  FIG. 8  drops the output voltage IOUT more quickly than the inverter  42   b  of the semiconductor storage device  20  according to the second embodiment. 
     As a result, the output signal REPLICA rises more quickly than that of the semiconductor storage device  20  according to the second embodiment. Thus, the signal STOP reaches the threshold voltage VTH at timing T 15  more quickly than that of the semiconductor storage device  20  according to the second embodiment. In this way, even when data of logical value “0” is read, the rise of the output signal REPLICA stops more quickly. Thus, the difference in the output signal REPLICA when data of the two logical values is read is increased further, and the read margin is widened further. 
     The operations at timing T 16  and T 17  are the same as those at timing T 7  and T 8  in the case of the semiconductor storage device  20  illustrated in  FIG. 7 . 
     (Write-Back Method) 
     Since a semiconductor storage device such as a FeRAM or a dynamic random access memory (DRAM) loses data stored in memory cells when performing a read operation, the semiconductor storage device performs a write-back operation after the read operation. 
     For example, when data of logical value “0” is written back to the memory cell  28   em  illustrated in  FIG. 3 , a voltage (for example, the power supply voltage VDD) for writing the data of logical value “0” is applied to the plate line PLm, and the voltage of the bit line BL[L] is set to 0 V. As illustrated in  FIG. 7  (or  FIG. 10 ), in the case of a read operation of the semiconductor storage device  20  according to the second embodiment (or the semiconductor storage device according to the third embodiment), when the voltage of the signal STOP reaches the threshold voltage VTH, the voltage of the bit line BL[L] begins to drop to 0 V. Even after this timing, since the plate line driver  26  continues to apply the power supply voltage VDD, which is equal to the voltage for writing data of logical value “0”, to the plate line PLm, the read period and the write-back period for the data of logical value “0” are allowed to overlap. Thus, the time needed for the write-back operation is shortened. 
     After the data of logical value “0” is written in the memory cell in which the data of logical value “1” has been stored, read data determination processing is performed, and data of logical value “1” is written back to the memory cell. 
     The data determination result that has been obtained by the sense amplifiers  30   g  and  30   h  is stored in the write buffer  31  illustrated in  FIG. 2 , and a write-back operation of the data of logical value “1” is performed based on the determination result stored in the write buffer  31 . Thus, the write buffer  31  functions as a write circuit. 
       FIG. 11  is a timing chart illustrating examples of changes of voltages of a word line, a plate line, and bit lines in a write-back operation. 
       FIG. 11  illustrates data read and write-back examples when data of logical value “0” is stored in the memory cell  28   em  and data of logical value “1” is stored in the memory cell  28   cm  in the memory cell array  28  illustrated in  FIG. 3 . 
     First, the power supply voltage VDD is applied to the word line WLm (timing T 20 ). Next, the power supply voltage VDD is also applied to the plate line PLm (timing T 21 ). As a result, the voltages of the bit lines BL[L] and BL[ 0 ] rise based on the respective data stored in the memory cells  28   em  and  28   cm . However, as illustrated in  FIGS. 7 and 10 , the voltages of the bit lines BL[L] and BL[ 0 ] begin to drop to 0 V when the signal STOP reaches the threshold voltage VTH (timing T 22 ). 
     At this point, since the power supply voltage VDD is continuously applied to the plate line PLm, data of logical value “0” is written in the memory cells  28   em  and  28   cm . In addition, since the same data is written back to the memory cell  28   cm  in which data of logical value “1” has been stored, a voltage higher than the power supply voltage VDD is applied to the word line WLm, and the power supply voltage VDD is applied to the bit line BL[ 0 ] at timing T 23 . In contrast, the voltage of the plate line PLm is dropped to 0 V. As a result, data of logical value “1” is written back to the memory cell  28   cm.    
     In the above processing, even when the data determination processing using the sense amplifiers is performed between timing T 22  and T 23 , this period between timing T 22  and T 23  is used as the write-back period for the data of logical value “0”. As a result, the time needed for the write-back operation is shortened. 
     Fourth Embodiment 
       FIG. 12  illustrates an example of a semiconductor storage device  80  according to a fourth embodiment. In  FIGS. 1 and 12 , like reference characters refer to like elements. 
     The semiconductor storage device  80  according to the fourth embodiment does not include the determination circuit  17 , unlike the semiconductor storage device  10  according to the first embodiment. In addition, pre-sense amplifiers  81  to  83  in the semiconductor storage device  80  are different from the pre-sense amplifiers  14  to  16  in the semiconductor storage device  10 . 
     In a reset circuit  81   a  in the pre-sense amplifier  81  connected to the memory cell  11  via the bit line BL, a detection circuit  81   a   1  is an inverter, for example. When the voltage of the amplified signal Pout rises and reaches a predetermined threshold, the logic level of a detection signal DET outputted by the detection circuit  81   a   1  changes from an H level to an L level. 
     In addition, the pre-sense amplifier  81  includes a determination circuit  81   b  having input terminals supplied with the detection signal DET outputted by the detection circuit  81   a   1  and a detection signal PDET. The detection signal PDET is a signal that is obtained by performing logic synthesis on detection signals DET 0  and DET 1  outputted by the pre-sense amplifiers  82  and  83 . An example of the circuit that generates the detection signal PDET will be described below. 
     The determination circuit  81   b  outputs a determination result (signal DATA) that is obtained by determining the logical value of the data stored in the memory cell  11  based on the difference between a time at which the detection signal DET changes and a time at which the detection signal PDET changes. For example, when the detection signal DET changes earlier than the detection signal POET, the determination circuit  81   b  outputs the signal DATA that indicates data of logical value “1”. In contrast, when the detection signal PDET changes earlier than the detection signal DET, the determination circuit  81   b  outputs the signal DATA that indicates data of logical value “0”. 
     The other bit lines connected to a plurality of memory cells are also connected to pre-sense amplifiers having the same configuration as that of the pre-sense amplifier  81 . 
     A detection circuit  82   a   1  in a reset circuit  82   a  in the pre-sense amplifier  82  connected to the reference cell  12  via the bit line BLR 1  is an inverter, for example. When the amplified signal Pout 1  rises and reaches a predetermined magnitude (an inverted threshold of the inverter), the logic level of the detection signal DET 1  outputted by the detection circuit  82   a   1  changes from an H level to an L level. In addition, the reset circuit  82   a  includes an inverter  82   a   2  that outputs a signal STOP 1  that is obtained by inverting the logic level of the detection signal DET 1  outputted by the detection circuit  82   a   1 . The signal STOP 1  is a signal that is obtained by delaying the amplified signal Pout 1 . 
     In addition, the pre-sense amplifier  82  includes a determination circuit  82   b  having input terminals that are supplied with the detection signal DET 1  outputted by the detection circuit  82   a   1  and the detection signal PDET. 
     The determination circuit  82   b  outputs a determination result (signal DATAR 1 ) that is obtained by determining the logical value of the data stored in the reference cell  12  based on the difference between a time at which the detection signal DET 1  changes and a time at which the detection signal PDET changes. 
     The pre-sense amplifier  83  connected to the reference cell  13  via the bit line BLR 0  has the same circuit configuration as that of the pre-sense amplifier  82 . The pre-sense amplifier  83  outputs a signal STOP 0 , the detection signal DET 0 , and a signal DATAR 0  that correspond to the signal STOP 1  and the detection signal DET 1  outputted by the pre-sense amplifier  82  and the signal DATA. 
     The determination circuits  81   b  and  82   b  may be arranged outside the pre-sense amplifiers  81  and  82 . 
       FIG. 13  illustrates an example of a circuit that generates a signal STOP. 
     For example, the circuit that generates the signal STOP is an OR circuit  84  as illustrated in  FIG. 13 . The OR circuit  84  outputs a result of an OR operation on the signals STOP 1  and STOP 0  outputted by the pre-sense amplifiers  82  and  83  as the signal STOP. When at least one of the logic levels of the signals STOP 1  and STOP 0  rises, the logic level of the signal STOP also rises. The signal STOP is supplied not only to pre-sense amplifiers  81 - 0  to  81 -L but also to the pre-sense amplifiers  82  and  83 . The pre-sense amplifiers  81 - 0  to  81 -L are the pre-sense amplifiers that read the data of the memory cells (not illustrated) connected to the bit line BL[ 0 ] to BL[L] and output signal DATA[ 0 ] to DATA[L]. The pre-sense amplifiers  81 - 0  to  81 -L have the same circuit configuration as that of the pre-sense amplifier  81  illustrated in  FIG. 12 . 
       FIG. 14  illustrates an example of a circuit that generates the detection signal PDET. 
     As illustrated in  FIG. 14 , this circuit that generates the detection signal PDET may be configured by, for example, a NAND circuit  85   a  and a delay circuit  85   b . The NAND circuit  85   a  outputs a result of a NAND operation on the detection signals DET 1  and DET 0  outputted by the pre-sense amplifiers  82  and  83 , and the delay circuit  85   b  delays the output signal of the NAND circuit  85   a  and outputs the resultant signal as the detection signal PDET. The detection signal PDET is supplied not only to the pre-sense amplifiers  81 - 0  to  81 -L but also to the pre-sense amplifiers  82  and  83 . The delay time of the delay circuit  85   b  is adjusted in such a manner that a time at which the detection signal PDET changes falls between a time at which the detection signal DET changes when data of logical value “1” is written in the memory cell  11  and a time at which the detection signal DET changes when data of logical value “0” is written in the memory cell  11 . 
     As illustrated in  FIGS. 13 and 14 , the signal STOP and the detection signal PDET are generated based on both of the outputs of the pre-sense amplifiers  82  and  83 . In this way, the functions of the pre-sense amplifiers  82  and  83  are exchangeable. Namely, the pre-sense amplifier  82  may be configured to process data of logical value “0”, and the pre-sense amplifier  83  may be configured to process data of logical value “1”. Thus, data of logical value “0” may be stored in the reference cell  12 , and data of logical value “1” may be stored in the reference cell  13 . 
     In addition, as illustrated in  FIGS. 12 to 14 , the signal DATA (DATA[ 0 ] to DATA[L]), DATAR 1 , and DATAR 0  outputted by the pre-sense amplifiers  81  ( 81 - 0  to  81 -L),  82 , and  83  may be used as read data. Thus, use of another determination circuit is not needed. 
       FIG. 15  illustrates an example of the determination circuit  81   b.    
     While  FIG. 15  illustrates an example of the determination circuit  81   b , the determination circuit  82   b  also has the same circuit configuration as that of the determination circuit  81   b.    
     The determination circuit  81   b  includes an AND circuit  81   b   1 , NOR circuits  81   b   2  and  81   b   3 , and an inverter  81   b   4 . 
     The AND circuit  81   b   1  outputs a result of an AND operation on the detection signals DET and PDET as a signal SRIN. 
     The NOR circuits  81   b   2  and  81   b   3  are connected to each other to form an SR latch, and one of the input terminals of the NOR circuit  81   b   2  is supplied with a reset signal RES from the timing generation circuit  24 , for example. One of the input terminals of the NOR circuit  81   b   3  is supplied with the signal SRIN. The output terminal of the NOR circuit  81   b   2 , which is an output terminal of the SR latch, is connected to the input terminal of the inverter  81   b   4 , and the output signal of the inverter  81   b   4  is the signal DATA. 
       FIG. 16  is a timing chart illustrating an example of an operation of the determination circuit. 
     While not illustrated in  FIG. 16 , the logic level of the reset signal RES has already changed from an H level to an L level before timing t 10 . Thus, at timing t 10 , the logic level of the signal DATA is at an H level. In addition, at timing t 10 , the logic level of the detection signal DET is at an H level, and the logic level of the detection signal PDET is at an L level. 
     When data of logical value “1” is read from the memory cell  11  (when the memory cell  11  is a cell holding “1”), the amplified signal Pout rises and reaches a predetermined magnitude at timing t 11 . The logic level of the detection signal DET consequently drops from an H level to an L level. Next, at timing t 12 , the logic level of the detection signal PDET rises from an L level to an H level. At timing t 11  and t 12 , since the logic level of the signal SRIN remains at an L level, the logic level of the signal DATA also remains at an H level. 
     In contrast, when data of logical value “0” is read from the memory cell  11  (when the memory cell  11  is a cell holding “0”), the logic level of the detection signal DET drops from an H level to an L level at timing t 13 , which is later than timing t 12 . Thus, at timing t 12 , the logic level of the signal SRIN rises from an L level to an H level, and the logic level of the signal DATA drops from an H level to an L level. While the logic level of the signal SRIN drops to an L level at timing t 13 , the state of the signal DATA is maintained by the SR latch. 
     In the case of the above semiconductor storage device  10  according to the first embodiment, the determination circuit  17  outputs a determination result that is obtained by determining the logical value of the data in the memory cell  11  based on the potential difference between the amplified signals Pout and Pout 1  and the potential difference between the amplified signals Pout and Pout 0 . In this case, if the data in the memory cell  11  is not rewritten, the ferroelectric imprint progresses, and the data in the reference cells  12  and  13  is frequently rewritten, the amplified signal Pout could represent a voltage approximately at the midpoint of the amplified signals Pout 0  and Pout 1 . As a result, an erroneous determination could be made. 
     In contrast, as described above, the semiconductor storage device  80  according to the fourth embodiment performs the data determination by using the difference between a time at which the detection signal DET changes when data of logical value “0” is read from the memory cell  11  and a time at which the detection signal DET changes when data of logical value “1” is read from the memory cell  11 . Namely, since the magnitude of the voltage of the amplified signal Pout is not used for the data determination, the data determination is stably performed without being affected by fluctuation of the charge amount of the ferroelectric capacitor such as imprint. 
     In the case of the semiconductor storage device  80  according to the fourth embodiment, while the signal STOP does not contribute to the data determination, deterioration in the characteristics of the memory cell  11  is prevented by dropping the voltage of the bit line BL to the ground potential by using the signal STOP. 
     When this effect does not need to be considered, the semiconductor storage device  80  in  FIG. 12  may be configured without the circuit configuration relating to the signal STOP. For example, the nMOS transistors  14   c   1  and  15   c   1 , the inverter  82   a   2 , etc. may be omitted. 
     In place of the pre-sense amplifiers  30   a  to  30   d  illustrated in  FIG. 4 , the pre-sense amplifiers  81  to  83  as described above may be used. In this case, the sense amplifiers  30   e  to  30   h  illustrated in  FIG. 4  are not needed. 
     By modifying the circuit configurations of the pre-sense amplifiers  30   b  and  30   d  illustrated in  FIGS. 5 and 6  as follows, the functions equivalent to those of the pre-sense amplifier  81  to  83  are achieved. 
       FIG. 17  illustrates an example of a pre-sense amplifier  91  connected to memory cells which function as reference cells that hold data of logical value “1”. In  FIGS. 5 and 17  illustrating the pre-sense amplifiers  30   b  and  91 , like reference characters refer to like elements. 
     A detection circuit  91   a   1  in a reset circuit  91   a  in the pre-sense amplifier  91  is, for example, an inverter. When the voltage of the output signal REPLICA (corresponding to the amplified signal Pout 1 ) of the amplifier circuit  42  rises and reaches a predetermined magnitude, the logic level of the detection signal DET 1  outputted by the detection circuit  91   a   1  changes from an H level to an L level. The reset circuit  91   a  also includes an inverter  91   a   2  that outputs a signal STOP 1  that is obtained by inverting the logic level of the detection signal DET 1  outputted by the detection circuit  91   a   1 . 
     In addition, the pre-sense amplifier  91  includes a determination circuit  91   b  having input terminals that are supplied with the detection signal DET 1  outputted by the detection circuit  91   a   1  and the detection signal PDET. 
     The determination circuit  91   b  outputs a determination result (signal DATAR 1 ) that is obtained by determining the logical value of the data stored in the memory cell  28   bm  based on the difference between a time at which the detection signal DET 1  changes and a time at which the detection signal PDET changes. For example, the determination circuit  91   b  is formed by the same circuit configuration as that of the determination circuit  81   b  illustrated in  FIG. 15 . 
     The pre-sense amplifier connected to memory cells which function as reference cells that hold data of logical value “0” is also formed by the same circuit configuration as that of the pre-sense amplifier  91  illustrated in  FIG. 17 . 
       FIG. 18  illustrates an example of a pre-sense amplifier  92  connected to memory cells that hold data of logical value “0” or “1”. In the pre-sense amplifiers  30   d  and  92  illustrated in  FIGS. 6 and 18 , like reference characters refer to like elements. 
     A detection circuit  92   a   1  in a reset circuit  92   a  in the pre-sense amplifier  92  is, for example, an inverter. When the voltage of the output signal REPLICA (corresponding to the amplified signal Pout) of the amplifier circuit  52  rises and reaches a predetermined magnitude, the logic level of the detection signal DET outputted by the detection circuit  92   a   1  changes from an H level to an L level. 
     In addition, the pre-sense amplifier  92  includes a determination circuit  92   b  having input terminals supplied with the detection signal DET outputted by the detection circuit  92   a   1  and the detection signal PDET. 
     The determination circuit  92   b  outputs a determination result (signal DATA[L]) that is obtained by determining the logical value of the data stored in the memory cell  28   em  based on the difference between a time at which the detection signal DET changes and a time at which the detection signal PDET changes. 
     The signal STOP and the detection signal PDET are generated by the logic circuits illustrated in  FIGS. 13 and 14 , for example. 
       FIG. 19  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the fourth embodiment.  FIG. 19  illustrates an operation example in which the pre-sense amplifiers  91  and  92  having the circuit configurations illustrated in  FIGS. 17 and 18  are used.  FIG. 19  illustrates the change of the signal DATA[L] over time, in addition to the changes of the signals illustrated in  FIG. 7  over time. The changes of the signals other than the change of the signal DATA[L] over time are the same as those in  FIG. 7  (the change of the signal STOP is simplified in  FIG. 19 ). 
     The logic level of the signal DATA[L] has been set in advance at an H level by the reset signal supplied to the determination circuit  92   b.    
     When data is read, the signal REPLICA of the pre-sense amplifier  91  rises (in the same way as the signal REPLICA changes over time when data of logical value “1” is read by the pre-sense amplifier  92  in  FIG. 19 ). Next, while not illustrated in  FIG. 19 , when the signal REPLICA reaches a predetermined threshold, the logic level of the detection signal DET 1  drops from an H level to an L level. After a predetermined delay time, the logic level of the detection signal PDET rises from an L level to an H level. Reading data of logical value “0” by the pre-sense amplifier  92  causes the voltage of the signal REPLICA to change more slowly than reading of data of logical value “1”. Thus, in this case, the logic level of the detection signal DET remains at an H level. As a result, when the logic level of the detection signal PDET reaches an H level while the logic level of the detection signal DET remains at an H level, the determination circuit  92   b  sets the logic level of the signal DATA[L] to an L level. 
     In contrast, when data of logical value “1” is read by the pre-sense amplifier  92 , the logic level of the detection signal DET changes to an L level earlier than a time at which the detection signal PDET changes. As a result, the logic level of the signal DATA[L] outputted by the determination circuit  92   b  remains at an H level. 
     In the example in  FIG. 19 , timing T 6   a  at which the logic level of the signal DATA[L] is determined is earlier than timing T 6  at which the logic level of the signal STOP rises from an L level to an H level. 
     Fifth Embodiment 
       FIG. 20  illustrates an example of a semiconductor storage device according to a fifth embodiment. In the semiconductor storage devices  80  and  100  according to the fourth and fifth embodiments illustrated in  FIGS. 12 and 20 , like reference characters refer to like elements. 
     A determination circuit  101   a  in a pre-sense amplifier  101  in the semiconductor storage device  100  according to the fifth embodiment includes an inverter  101   a   1 , a pMOS transistor  101   a   2 , a determination unit  101   a   3 , and an nMOS transistor  101   a   4 . 
     The input terminal of the inverter  101   a   1  is connected to the output terminal of the inverter  14   b   2 , and the output signal of the inverter  101   a   1  is the signal DATA. 
     The gate of the pMOS transistor  101   a   2  is supplied with a signal JR outputted by the determination unit  101   a   3 . When the logic level of the signal JR is at an L level, the pMOS transistor  101   a   2  is set to an on-state, supplies the power supply voltage VDD to the inverter  101   a   1 , and activates the inverter  101   a   1 . 
     The determination unit  101   a   3  outputs the signal JR that indicates the difference between a time at which the detection signal DET changes and a time at which the detection signal PDET changes. When the detection signal DET changes earlier than the detection signal PDET, the determination unit  101   a   3  outputs an L-level signal JR. In contrast, when the detection signal DET changes later than the detection signal PDET, the determination unit  101   a   3  outputs an H-level signal JR. The signal JR is supplied to the gates of the pMOS transistor  101   a   2  and the nMOS transistor  101   a   4  and functions as a control signal that controls on and off of the pMOS transistor  101   a   2  and the nMOS transistor  101   a   4 . For example, the determination unit  101   a   3  has the same circuit configuration as that of the determination circuit  81   b  illustrated in  FIG. 15  without the inverter  81   b   4 . 
     The gate of the nMOS transistor  101   a   4  is supplied with the signal JR, which controls on and off of the nMOS transistor  101   a   4 . The source voltage of the nMOS transistor  101   a   4  is at the ground potential, and the drain voltage of the nMOS transistor  101   a   4  indicates a determination result (signal DATA) of the read data. 
     With this determination circuit  101   a , when data reading is started, the logic level of the signal JR is set to an L level by the reset signal (not illustrated) supplied to the determination unit  101   a   3 , the pMOS transistor  101   a   2  is set to an on-state, and the inverter  101   a   1  is activated. In addition, the nMOS transistor  101   a   4  is set to an off-state. 
     When data reading is started, since the logic level of the output signal of the inverter  14   b   2  changes to an L level, the inverter  101   a   1  sets the logic level of the signal DATA, which is the drain voltage of the nMOS transistor  101   a   4 , to an H level. 
     In this way, the circuit unit including the inverter  101   a   1  and the pMOS transistor  101   a   2  previously rises the above drain voltage before the determination unit  101   a   3  outputs the signal JR that reflects the difference between a time at which the detection signal DET changes and a time at which the detection signal PDET changes. 
     When the detection signal DET changes earlier than the detection signal PDET, since the determination unit  101   a   3  continuously outputs the L-level signal JR, the logic level of the signal DATA remains at an H level. In contrast, when the detection signal DET changes later than the detection signal PDET, since the determination unit  101   a   3  outputs an H-level signal JR, the pMOS transistor  101   a   2  is set to an off-state. Thus, the inverter  101   a   1  is not activated. In addition, since the nMOS transistor  101   a   4  is set to an on-state, the logic level of the signal DATA drops to an L level. 
     Since use of this determination circuit  101   a  achieves removal of the inverter  81   b   4  from the determination circuit  81   b  illustrated in  FIG. 15 , a data determination result is obtained more quickly. 
     Other bit lines connected to a plurality of memory cells are also connected to pre-sense amplifiers having the same configuration as that of the pre-sense amplifier  101 . 
     A determination circuit  102   a  in a pre-sense amplifier  102  includes an inverter  102   a   1 , a pMOS transistor  102   a   2 , a determination unit  102   a   3 , and an nMOS transistor  102   a   4  and has the same circuit configuration as that of the determination circuit  101   a  in the pre-sense amplifier  101 . 
     A pre-sense amplifier  103  connected to the reference cell  13  via the bit line BLR 0  has the same circuit configuration as that of the pre-sense amplifier  102 . 
     The determination circuits  101   a  and  102   a  may be arranged outside the pre-sense amplifiers  101  and  102 . 
     The above determination circuits  101   a  and  102   a  may be used in place of the determination circuits  91   b  and  92   b  in the pre-sense amplifiers  91  and  92  in  FIGS. 17 and 18 . In this case, the output voltage IOUT is applied to the input terminals of the inverters  101   a   1  and  102   a   1 . 
       FIG. 21  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the fifth embodiment.  FIG. 21  illustrates an operation example in which the above determination circuits  101   a  and  102   a  are used in place of the determination circuits  91   b  and  92   b  in the pre-sense amplifiers  91  and  92  illustrated in  FIGS. 17 and 18 .  FIG. 21  illustrates the change of the signal DATA[L] over time, in addition to the changes of the signals over time illustrated in  FIG. 7 . The changes of the signals other than the change of the signal DATA[L] over time are the same as those in  FIG. 7  (the change of the signal STOP is simplified in  FIG. 21 ). 
     The logic level of the signal DATA[L] remains at an L level until the output voltage IOUT begins to drop from VDD/2. When the output voltage IOUT begins to drop from VDD/2 (timing T 5 ), the voltage of the signal DATA[L] begins to rise. 
     When the detection signal DET changes later than the detection signal PDET (when data of logical value “0” is read), the determination unit  101   a   3  outputs an H-level signal JR. As a result, since the nMOS transistor  101   a   4  is set to an on-state, the logic level of the signal DATA[L] changes to an L level (timing T 6   b ). When the detection signal DET changes earlier than the detection signal PDET (when data of logical value “1” is read), the determination unit  101   a   3  outputs an L-level signal JR. In this case, since the nMOS transistor  101   a   4  remains in an off-state, the logical level of the signal DATA[L] remains at an H level. 
     When data of logical value “0” is read, timing T 6   a  at which the logic level of the signal DATA[L] is determined is even earlier than timing T 6   a  illustrated in  FIG. 19 . 
     Sixth Embodiment 
       FIG. 22  illustrates an example of a semiconductor storage device according to a sixth embodiment. In the semiconductor storage devices  100  and  110  according to the fifth and sixth embodiments illustrated in  FIGS. 20 and 22 , like reference characters refer to like elements. 
     An amplifier circuit  11   a  in a pre-sense amplifier  111  in the semiconductor storage device  110  according to the sixth embodiment includes an nMOS transistor  11   a   1  and an inverter  111   a   2 . 
     The drain of the nMOS transistor  111   a   1  and the input terminal of the inverter  111   a   2  are connected to the output terminal of the inverter  14   b   2 , and the source of the nMOS transistor  11   a   1  is connected to ground. The gate of the nMOS transistor  111   a   1  and the output terminal of the inverter  111   a   2  are connected to a determination circuit  111   b.    
     By arranging these nMOS transistor  111   a   1  and inverter  111   a   2 , as is the case with the pre-sense amplifiers  60  and  70  in the semiconductor storage device according to the third embodiment, the output voltage of the inverter  14   b   2  drops more quickly. As a result, the amplified signal Pout rises more quickly. 
     The nMOS transistor  111   a   1  and the inverter  111   a   2  may be arranged outside the amplifier circuit  111   a.    
     The determination circuit  111   b  includes an inverter  111   b   1 . The input terminal of the inverter  111   b   1  is connected to the gate of the nMOS transistor  111   a   1  and the output terminal of the inverter  111   a   2 . The output terminal of the inverter  111   b   1  is connected to the input terminal of the inverter  101   a   1 . 
     Other bit lines connected to a plurality of memory cells are also connected to pre-sense amplifiers having the same configuration as that of the pre-sense amplifier  111 . 
     An amplifier circuit  112   a  in a pre-sense amplifier  112  includes an nMOS transistor  112   a   1  and an inverter  112   a   2  and has the same circuit configuration as that of the amplifier circuit  111   a  in the pre-sense amplifier  111 . In addition, a determination circuit  112   b  in the pre-sense amplifier  112  includes an inverter  112   b   1  and has the same circuit configuration as that of the determination circuit  111   b  in the pre-sense amplifier  111 . 
     A pre-sense amplifier  113  connected to the reference cell  13  via the bit line BLR 0  has the same circuit configuration as that of the pre-sense amplifier  112 . 
     The determination circuits  111   b  and  112   b  may be arranged outside the pre-sense amplifiers  111  and  112 . 
     The above determination circuits  11   b  and  112   b  may be used in place of the determination circuits  91   b  and  92   b  in the pre-sense amplifiers  91  and  92  illustrated in  FIGS. 17 and 18 . In this case, the output terminal of the inverter  52   b  in the pre-sense amplifier  92  is connected to the drain of the nMOS transistor  111   a   1  and the input terminal of the inverter  111   a   2 . In addition, the output terminal of the inverter  42   b  in the pre-sense amplifier  91  is connected to the drain of the nMOS transistor  112   a   1  and the input terminal of the inverter  112   a   2 . 
       FIG. 23  is a timing chart illustrating an example of a read operation of the semiconductor storage device according to the sixth embodiment. In the operation example illustrated in  FIG. 23 , the determination circuits  111   b  and  112   b  are used in place of the determination circuits  91   b  and  92   b  in the pre-sense amplifiers  91  and  92  illustrated in  FIGS. 17 and 18 . In addition, the nMOS transistors  111   a   1  and  112   a   1  and the inverters  111   a   2  and  112   a   2  as described above are used.  FIG. 23  illustrates the change of the signal DATA[L] over time, in addition to the changes of the signals illustrated in  FIG. 10  over time. The changes of the signals other than the change of the signal DATA[L] over time are the same as those in  FIG. 10  (the change of the signal STOP is simplified in  FIG. 23 ). 
     The logic level of the signal DATA[L] remains at an L level until the output voltage IOUT begins to drop from VDD/2. When the output voltage IOUT begins to drop from VDD/2 (timing T 14 ), the voltage of the signal DATA[L] begins to rise. At this point, since the nMOS transistor  111   a   1  and the inverter  111   a   2  are arranged, as is the case with the pre-sense amplifiers  60  and  70  in the semiconductor storage device according to the third embodiment, the output voltage IOUT drops more quickly. As a result, the output signal REPLICA rises more quickly. 
     Thus, when data of logical value “0” is read, the timing at which the determination unit  101   a   3  outputs an H-level signal JR (timing T 15   a  at which the signal DATA[L] changes) is earlier than that of the semiconductor storage device  100  according to the fifth embodiment. 
     Seventh Embodiment 
       FIG. 24  illustrates an example of a semiconductor storage device  120  according to a seventh embodiment. 
     While  FIG. 24  illustrates only the pre-sense amplifiers and the circuit unit that generates a detection signal PDET, the other elements are the same as those of the semiconductor storage devices  80 ,  100 , and  110  according to the fourth to sixth embodiments. 
     The semiconductor storage device  120  according to the seventh embodiment includes a plurality of pre-sense amplifiers (pre-sense amplifiers  121   a ,  121   b   1 ,  121   b   2 ,  121   c   1 ,  121   c   2 ,  121   d , etc.), AND circuits  122   a  and  122   b , a NAND circuit  123 , and a delay circuit  124 . 
     Among the plurality of pre-sense amplifiers, the pre-sense amplifiers  121   b   1  and  121   b   2  are pre-sense amplifiers connected to reference cells that hold data of logical value “0”. The pre-sense amplifiers  121   c   1  and  121   c   2  are pre-sense amplifiers connected to reference cells that hold data of logical value “1”. 
     The pre-sense amplifiers  121   b   1 ,  121   b   2 ,  121   c   1 , and  121   c   2  have the same circuit configuration as that of any one of the pre-sense amplifiers  82 ,  91 ,  102 , and  112  illustrated in  FIGS. 12, 17, 20, and 22 . The other pre-sense amplifiers have the same circuit configuration as that of any one of the pre-sense amplifiers  81 ,  92 ,  101 , and  111  illustrated in  FIGS. 12, 18, 20, and 22 . 
     Detection signals DET 00  and DET 01  outputted by the pre-sense amplifiers  121   b   1  and  121   b   2  correspond to the above detection signal DET 0 , and detection signals DET 10  and DET 11  outputted by the pre-sense amplifiers  121   c   1  and  121   c   2  correspond to the above detection signal DET 1 . 
     The AND circuit  122   a  outputs a detection signal PDET 0 , which is a result of an AND operation on the detection signals DET 00  and DET 01 , and the AND circuit  122   b  outputs a detection signal PDET 1 , which is a result of an AND operation on the detection signals DET 10  and DET 11 . The NAND circuit  123  outputs the detection signal PDET, which is a result of a NAND operation on the detection signals PDET 0  and PDET 1 . The delay circuit  124  delays the output signal of the NAND circuit  123  and outputs the resultant signal as the detection signal PDET. The detection signal PDET is supplied to each of the plurality of pre-sense amplifiers. 
     With this configuration, even when a failure occurs in a reference cell connected to one of the pre-sense amplifiers  121   b   1  and  121   b   2  or one of the pre-sense amplifiers  121   c   1  and  121   c   2 , the detection signal PDET is properly generated. 
       FIG. 25  illustrates a semiconductor storage device according to a comparative example. 
     The semiconductor storage device according to the comparative example includes a plurality of pre-sense amplifiers (pre-sense amplifiers  130   a ,  130   b ,  130   c ,  130   d ,  130   e ,  130   f ,  130   g ,  130   h , etc.) and a plurality of sense amplifiers (sense amplifiers  131   a ,  131   b ,  131   c ,  131   d , etc.). 
     Among the plurality of pre-sense amplifiers, the pre-sense amplifiers  130   b  and  130   f  are pre-sense amplifiers connected to reference cells that hold data of logical value “0”. In addition, the pre-sense amplifiers  130   c  and  130   g  are pre-sense amplifiers connected to reference cells that hold data of logical value “1”. 
     The pre-sense amplifiers  130   b  and  130   f  output signals SFR 0 [ 0 ] and SFR 0 [ 1 ] that correspond to the above amplified signal Pout 0 , and the pre-sense amplifiers  130   c  and  130   g  output signals SFR 1 [ 0 ] and SFR 1 [ 1 ] that correspond to the above amplified signal Pout 1 . 
     The sense amplifiers  131   a  and  131   b  function as twin sense amplifiers and perform data determination based on the signal SF[ 0 ] (corresponding to the above amplified signal Pout) outputted by the pre-sense amplifier  130   a  and the signals SFR 0 [ 0 ] and SFR 1 [ 0 ]. The sense amplifiers  131   c  and  131   d  also function as twin sense amplifiers and perform data determination based on the signal SF[ 1 ](corresponding to the above amplified signal Pout) outputted by the pre-sense amplifier  130   e  and the signals SFR 0 [ 1 ] and SFR 1 [ 1 ]. 
       FIG. 25  illustrates examples of how the voltages of the signal SF (the signal SF[ 0 ] or signal SF[ 1 ], for example), the signal SFR 0  (the signal SFR 0 [ 0 ] or the signal SFR 0 [ 1 ]), and the signal SFR 1  (the signal SFR 1 [ 0 ] or the signal SFR 1 [ 1 ]) change over time. 
     When both of the signals SFR 0  and SFR 1  are at a U level (a signal level that corresponds to data of logical value “0”) or at a P level (a signal level that corresponds to data of logical value “1”), the margin with respect to the signal SF could be reduced, and the data could not be determined properly. 
     In the case of the above comparative example, even if two reference cells that hold data of logical value “0” and two reference cells that hold data of logical value “1” are arranged, since the data determination is performed based on the potential difference, it is difficult to establish a configuration that properly respond to cell failure (redundant configuration). 
     In contrast, as is the case with the semiconductor storage devices  80 ,  100 , and  110 , the semiconductor storage device  120  performs data determination by using the difference between times at which the detection signals DET change when data of logical value “0” or “1” is read from the memory cells. Thus, as illustrated in  FIG. 24 , a redundant configuration is easily configured. 
     Eighth Embodiment 
     As illustrated in  FIG. 16 , in the case of the above semiconductor storage devices  80 ,  100 ,  110 , and  120 , the signal DATA is determined based on whether the timing at which the logic level of the detection signal DET drops is before the timing at which the logic level of the detection signal PDET rises. The semiconductor storage devices  80 ,  100 ,  110 , and  120  do not determine whether these two timings are close to each other (whether the margin is small). 
       FIG. 26  illustrates timing charts of an example in which a small margin occurs. 
     As in  FIG. 16 , operation examples of the determination circuit  81   b  are illustrated in  FIG. 26 . For example, when the memory cell  11  in  FIG. 12  holds “1”, the same signal DATA is outputted, whether the logic level of the detection signal DET drops at timing t 11  or at timing t 11   a  thereafter. Likewise, when the memory cell  11  holds “0”, the same signal DATA is outputted, whether the logic level of the detection signal DET drops at timing t 13  or timing t 13   a  there before. Namely, the same signal DATA is outputted, whether the margin is small or not. 
     There are cases in which lifetime evaluation is performed in a device test performed before product delivery. Those memory cells having a small margin as described above are more likely to be determined as defective cells than other memory cells, and these defective memory cells lead to shortening of the lifetime of the device. Thus, it is preferable that the margin size be evaluated when the device test is performed. 
     A semiconductor storage device according to an eighth embodiment enables evaluation of the margin size. 
       FIG. 27  illustrates an example of a pre-sense amplifier of a semiconductor storage device according to an eighth embodiment. The same reference characters as used in the pre-sense amplifier  92  illustrated in  FIG. 18  are applied to the corresponding components in the pre-sense amplifier  140  illustrated in  FIG. 27 . 
     The pre-sense amplifier  140  of the semiconductor storage device according to the eighth embodiment includes a selection circuit  141  that selects a detection signal PDET or a detection signal PDETt based on a selection signal inputted (which will be referred to as a mode selection signal SEL) and supplies the selected signal to a determination circuit  92   b.    
     The mode selection signal SEL is a signal that causes the selection circuit  141  to select and output the detection signal PDET in a normal operation and to select the detection signal PDETt in a test operation (in a test mode). The mode selection signal SEL may be supplied from a circuit arranged in the semiconductor storage device or from a test apparatus (a tester) connected to the semiconductor storage device. 
     The detection signal PDETt is inputted from the test apparatus connected to the semiconductor storage device. The time at which the logic level of the detection signal PDETt rises is controlled by the test apparatus. Thus, a plurality of detection signals PDETt, each of which changes at a different time, may be inputted. 
     When a test is performed, the determination circuit  92   b  outputs a signal DATA[L] based on the difference between a time at which the detection signal DET changes and a time at which the detection signal PDETt changes. 
       FIG. 28  illustrates an example of the selection circuit. The following example assumes that the mode selection signal SEL illustrated in  FIG. 27  is formed by signals M 1  and M 2 . In addition,  FIG. 28  assumes that the signals M 1  and M 2  are supplied from the test mode generation circuit  142  arranged in the semiconductor storage device, for example. 
     The selection circuit  141  includes pMOS transistors  141   a  and  141   b  and nMOS transistors  141   c  and  141   d . One of the drain and the source of the pMOS transistor  141   a  and one of the drain and the source of the nMOS transistor  141   c  are supplied with the detection signal PDET. The other one of the drain and the source of the pMOS transistor  141   a  and the other one of the drain and the source of the nMOS transistor  141   c  are connected to the determination circuit  92   b . One of the drain and the source of the pMOS transistor  141   b  and one of the drain and the source of the nMOS transistor  141   d  are supplied with the detection signal PDETt. The other one of the drain and the source of the pMOS transistor  141   b  and the other one of the drain and the source of the nMOS transistor  141   d  are connected to the determination circuit  92   b . In addition, the gates of the pMOS transistor  141   a  and the nMOS transistor  141   d  are supplied with the signal M 1 , and the gates of the pMOS transistor  141   b  and the nMOS transistor  141   c  are supplied with the signal M 2 . 
     When the logic level of the signal M 1  is an L level and the logic level of the signal M 2  is an H level, the selection circuit  141  outputs the detection signal PDET. When the logic level of the signal M 1  is an H level and the logic level of the signal M 2  is an L level, the selection circuit  141  outputs the detection signal PDETt. 
     The pre-sense amplifiers connected to the memory cells and the reference cells other than a memory cell  28   em  are formed by the same circuit configuration as in  FIG. 27 . In addition, the selection circuit  141  may be applied to the individual pre-sense amplifiers of the semiconductor storage devices  80 ,  100 ,  110 , and  120 . 
     For example, the semiconductor storage device is tested by a test system, which will be described below. 
       FIG. 29  illustrates an example of a test system. 
     This test system  150  includes a semiconductor storage device  151  and a test apparatus  152 . 
     This semiconductor storage device  151  is a semiconductor storage device according to the eighth embodiment and includes, for example, the pre-sense amplifier  140  illustrated in  FIG. 27 . In addition, the semiconductor storage device  151  includes input-output terminals  1511   p ,  151   p   2 , . . . , and  151   pn.    
     The test apparatus  152  is connected to at least one of the input-output terminals  151   p   1  to  151   pn  of the semiconductor storage device  151  and tests the semiconductor storage device  151  by exchanging various kinds of signals with the semiconductor storage device  151 . 
     For example, as illustrated in  FIG. 29 , a detection signal PDETt outputted by the test apparatus  152  is inputted to the input-output terminal  151   p   1 , and a chip enable signal /CE outputted by the test apparatus  152  is inputted to the input-output terminal  151   p   2 . In addition, signals DATA[ 0 ] to DATA[L] outputted by the semiconductor storage device  151  from at least one of the input-output terminals  151   p   1  to  151   pn  are inputted to the test apparatus  152 . 
     For example, the test apparatus  152  includes at least one processor (a central processing unit (CPU), a digital signal processor (DSP), or the like), a memory, a display, etc. 
       FIGS. 30 to 32  are timing charts illustrating examples of data determination results based on margins about memory cells. 
       FIGS. 30 to 32  illustrate examples of data determination results about three memory cells (memory cells a to c) having different margins, of all the memory cells in the semiconductor storage device  151 . As examples of the detection signals PDETt inputted from the test apparatus  152 ,  FIGS. 30 to 32  illustrate three detection signals PDETt(t 20 ), PDETt(t 21 ), and PDETt(t 22 ). The logic level of the individual detection signal PDETt rises from an L level to an H level at different timing. 
       FIG. 30  illustrates examples of data determination results (signal DATA) when the memory cell a holds “1” and when the memory cell a holds “0”. 
     When the memory cell a holds “1”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell a drops before timing t 20  at which the logic level of the detection signal PDETt(t 20 ) rises. Thus, at timing t 20 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell a is an H level indicating that the memory cell a holds “1”. The logic level of the signal DATA is also an H level at timing t 21  and timing t 22  when the detection signals PDETt(t 21 ) and PDETt(t 22 ) are inputted. 
     When the memory cell a holds “0”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell a drops after timing t 22  at which the logic level of the detection signal PDETt(t 22 ) rises. Thus, at timing t 20 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell a drops to an L level indicating that the memory cell a holds “0” (0 V in the example in  FIG. 30 ). When the detection signals PDETt(t 21 ) and PDETt(t 22 ) are inputted, the logic level of the signal DATA drops to an L level at timing t 21  and timing t 22 , respectively. 
     In the case of the above memory cell a, the same signal DATA is obtained when the detection signals PDETt(t 20 ), PDETt(t 21 ), and PDETt(t 22 ) are inputted. When an accurate determination result is obtained about the individual detection signal PDET, the test apparatus  152  determines that the memory cell a is a good memory cell that satisfies the margin size requested when the determination circuit  92   b  determines a logical value, for example. 
       FIG. 31  illustrates examples of data determination results (signal DATA) when the memory cell b holds “1” and when the memory cell b holds “0”. 
     When the memory cell b holds “1”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell b drops after timing t 20  at which the logic level of the detection signal PDETt(t 20 ) rises. In addition, the logic level of the detection signal DET drops before timing t 21  at which the logic level of the detection signal PDETt(t 21 ) rises. Thus, at timing t 20 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell b is an L level indicating that the memory cell b holds “0”. When the detection signals PDETt(t 21 ) and PDETt(t 22 ) are inputted, the logic level of the signal DATA indicates an H level at timing t 21  and t 22 , respectively. 
     When the memory cell b holds “0”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell b drops after timing t 22  at which the logic level of the detection signal PDETt(t 22 ) rises. Thus, at timing t 20 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell b drops to an L level (0 V in the example in  FIG. 31 ) indicating that the memory cell b holds “0”. When the detection signals PDETt(t 21 ) and PDETt(t 22 ) are inputted, the logic level of the signal DATA drops to an L level at timing t 21  and timing t 22 , respectively. 
     When the memory cell b holds “1”, at timing t 20 , the logic level of the signal DATA drops to an L level indicating that the memory cell b holds “0”. As in this case, if an erroneous determination result is obtained about any one of the detection signals PDETt, the test apparatus  152  determines that the corresponding memory cell (the memory cell b) is a poor memory cell that does not satisfy the above margin size, for example. This memory cell is more likely to be a defective cell than other memory cells determined as good memory cells. 
       FIG. 32  illustrates examples of data determination results (signal DATA) when the memory cell c holds “1” and when the memory cell c holds “0”. 
     When the memory cell c holds “1”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell c drops before timing t 20  at which the logic level of the detection signal PDETt (t 20 ) rises. Thus, at timing t 20 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell c is an H level indicating that the memory cell c holds “l”. When the detection signal PDETt(t 21 ) and PDETt(t 22 ) are inputted, the logic level of the signal DATA is also an H level at timing t 21  and timing t 22 , respectively. 
     When the memory cell c holds “0”, the logic level of the detection signal DET in the pre-sense amplifier connected to the memory cell c drops before timing t 22  at which the logic level of the detection signal PDETt(t 22 ) rises. In addition, the logic level of the detection signal DET drops after timing t 21  at which the logic level of the detection signal PDETt(t 21 ) rises. Thus, at timing t 22 , the logic level of the signal DATA outputted by the pre-sense amplifier connected to the memory cell c is an H level indicating that the memory cell c holds “1”. When the detection signals PDETt(t 20 ) and PDETt(t 21 ) are inputted, the logic level of the signal DATA drops to an L level at timing t 21  and timing t 22 , respectively. 
     When the memory cell c holds “0”, at timing t 22 , the logic level of the signal DATA is an H level indicating that the memory cell c holds “1”. As in this case, if an erroneous determination result is obtained about any one of the detection signals PDETt, the test apparatus  152  determines that the corresponding memory cell (the memory cell c) is a poor memory cell that does not satisfy the above margin size, for example. 
     The range in which the time at which the logic level of the individual detection signal PDETt rises is changed (a time width of change (t 20  to t 22  in the examples in  FIGS. 30 to 32 )) is set based on the margin size requested when the determination circuit  92   b  determines the logical value. A wider range is set when a larger margin is requested, and a narrower range is set when a smaller margin is requested. 
     Hereinafter, an example of how the test apparatus  152  tests the semiconductor storage device  151  will be described. 
       FIG. 33  is a flowchart illustrating an example of a test method of a semiconductor storage device. 
     The test apparatus  152  sets a time width of change (which is represented as a change width in  FIG. 33 ) of an individual detection signal PDETt based on a requested margin, for example, based on information inputted by the user (step S 1 ). In this step, the number of detection signals PDETt inputted to the semiconductor storage device  151  may also be set. The following description assumes that three detection signals PDETt(t 20 ), PDETt(t 21 ), and PDETt(t 22 ) whose change widths are t 20  to t 22  are used, as in  FIGS. 30 to 32 . 
     The test apparatus  152  turns on the power supply of the semiconductor storage device  151  (step S 2 ) and instructs the semiconductor storage device  151  to transition to the test mode (step S 3 ). In step S 3 , for example, the test apparatus  152  inputs an instruction signal for causing the test mode generation circuit  142  illustrated in  FIG. 28  to generate the signal M 1  whose logic level is an H level and the signal M 2  whose logic level is an L level to the semiconductor storage device  151 . 
     First, as a detection signal PDETt, the test apparatus  152  inputs the detection signal PDETt(t 20 ) illustrated in  FIGS. 30 to 32  to the semiconductor storage device  151  (step S 4 ). Next, the test apparatus  152  reads data of the individual memory cells in the semiconductor storage device  151  (step S 5 ). The test apparatus  152  may previously write “0” (or “1”) in all the memory cells in the semiconductor storage device  151 . 
     In step S 5 , the test apparatus  152  supplies various kinds of signals for a read operation to the semiconductor storage device  151 . Examples of these signals include a chip enable signal /CE, a chip select signal /CS, a write enable signal /WE, and an output enable signal /OE. As a result, the semiconductor storage device  151  performs a read operation and outputs data determination results (signal DATA) of the individual memory cells. 
     The test apparatus  152  determines whether a fail bit (an incorrect determination result) has occurred in any one of the plurality of memory cells included in the semiconductor storage device  151  (step  36 ). For example, the test apparatus  152  determines whether a fail bit has occurred by holding the data written in the individual memory cells in the semiconductor storage device  151  and comparing the data with the data determination results of the individual memory cells obtained upon inputting the detection signal PDETt(t 20 ). 
     For example, as illustrated in  FIG. 31 , if the test apparatus  152  detects a signal DATA indicating that the memory cell b holds “0” even when the memory cell b holds “1”, the test apparatus  152  determines that a fail bit has occurred. 
     If the test apparatus  152  determines that a fail bit has occurred, the processing proceeds to step S 14 . If the test apparatus  152  does not determine a fail bit has occurred, the test apparatus  152  inputs, as a detection signal PDETt, the detection signal PDETt(t 21 ) illustrated in  FIGS. 30 to 32  to the semiconductor storage device  151  (step S 7 ). Next, the test apparatus  152  reads data of the individual memory cells in the semiconductor storage device  151 , again (step S 8 ). 
     Next, the test apparatus  152  determines whether a fail bit has occurred in any one of the plurality of memory cells included in the semiconductor storage device  151  (step S 9 ). If the test apparatus  152  determines that a fail bit has occurred, the processing proceeds to step S 14 . 
     If the test apparatus  152  does not determine that a fail bit has occurred, the test apparatus  152  inputs, as a detection signal PDETt, the detection signal PDETt(t 22 ) illustrated in  FIGS. 30 to 32  to the semiconductor storage device  151  (step S 10 ). Next, the test apparatus  152  reads data of the individual memory cells in the semiconductor storage device  151 , again (step S 11 ). 
     Next, the test apparatus  152  determines whether a fail bit has occurred (step S 12 ). 
     For example, as illustrated in  FIG. 32 , when the test apparatus  152  detects a signal DATA indicating that the memory cell c holds “1” even when the memory cell c holds “0”, the test apparatus  152  determines that a fail bit has occurred. 
     If the test apparatus  152  determines that a fail bit has occurred, the processing proceeds to step S 14 . 
     If the test apparatus  152  does not determine that a fail bit has occurred, the test apparatus  152  performs a product test in which various functions of the semiconductor storage device  151  are tested (step S 13 ). Next, the test apparatus  152  outputs a test result (step S 14 ) and ends the test on the semiconductor storage device  151 . The product test in step S 13  may be performed by an apparatus different from the test apparatus  152 . 
     If the test apparatus  152  determines that a fail bit has occurred in step S 6 , S 9 , or S 12 , the test apparatus  152  outputs a test result indicating the occurrence of the fail bit in step S 14 . For example, the test apparatus  152  may output a test result indicating that the semiconductor storage device  151  is not a product to be delivered due to the occurrence of the fail bit. If the test apparatus  152  does not determine that a fail bit has occurred in step S 12  and if no problems have been detected in the product test, for example, the test apparatus  152  outputs a test result indicating that the semiconductor storage device  151  is a product to be delivered in step S 14 . For example, the test apparatus  152  may output and display these test results on a display or may output (transmit) these test results to another apparatus such as a computer or an external memory. 
     The above test may be performed on a plurality of semiconductor storage devices simultaneously. While three detection signals PDETt, each of which rises at different timing, are used in the above example, the number of detection signals PDETt is not limited to 3. Two or four or more detection signals PDETt may alternatively be used. In addition, the order of the steps in  FIG. 33  may be changed as appropriate. For example, steps S 7  and S 10  may be switched around. 
     According to this test method of the semiconductor storage device  151 , the margin about each of the memory cells included in the semiconductor storage device  151  is evaluated. This is because memory cells having various margins are detected by changing the time width of change of the individual detection signal PDETt. 
     Consequently, whether the semiconductor storage device  151  includes a memory cell having a small margin is detected. Thus, for example, devices including memory cells that could potentially be determined as defected cells due to small margins are not delivered to market, and the device reliability is improved. 
     If a relationship between the margin volume and a use period in which detective cells occur (or the number of times of use (for example, the number of times of data writing)) is previously known, a semiconductor storage device in which defective cells occur in a predetermined period (or a predetermined number of times of use) is extracted by the individual detection signal PDETt. For example, by determining the time width of change of the individual detection signal PDETt in view of the margin size that causes defective cells in the predetermined period, for example, a short-lived semiconductor storage device in which defective cells are likely occur in a short time such as one year is extracted. 
     The test method of the semiconductor storage device  151  is not limited to the above test method. The test apparatus  152  is also able to obtain a distribution indicating the change in the number of memory cells determined as holding “1” and a distribution indicating the change in the number of memory cells determined as holding “0” by changing a time at which the individual detection signal PDETt changes. 
       FIGS. 34 and 35  illustrate examples of how the difference in the number of fail bits counted changes by changing a time at which the detection signal PDETt changes. The horizontal axis represents the time at which the detection signal PDETt changes, and the vertical axis represents the difference in the number of fail bits counted. In  FIGS. 34 and 35, 40  [ns] is the timing at which the logic level of the chip enable signal /CE indicates an L level. The difference in the number of fail bits counted is the difference in the number of memory cells determined as fail bits between a certain time at which the detection signal PDETt changes and the next time at which the detection signal PDETt changes. 
     In addition, in  FIGS. 34 and 35 , the difference in the number of fail bits counted when “1” is stored in all the memory cells in the semiconductor storage device  151  and the number of fail bits counted when “0” is stored in all the memory cells are superposed. 
     The example in  FIG. 34  illustrates sharp peaks, each of which has a relatively narrow width. However, regarding the difference when “0” is stored in all the memory cells, the example in  FIG. 35  illustrates a broader peak than those in  FIG. 34 . This indicates that there is a large variation in the time at which the logic level of the detection signal DET drops per memory cell when “0” is stored in all the memory cells. 
     These distributions as illustrated in  FIGS. 34 and 35  correspond to a distribution indicating the change in the number of memory cells determined as holding “1” and a distribution indicating the change in the number of memory cells determined as holding “0”. 
     The test apparatus  152  may determine whether the semiconductor storage device  151  is a defective product, based on the distributions as illustrated in  FIGS. 34 and 35 . For example, if the width of a peak indicates a predetermined value or more, the test apparatus  152  may determine that the semiconductor storage device  151  is a defective product and exclude this defective semiconductor storage device  151  from good semiconductor storage devices  151  to be delivered. 
     Ninth Embodiment 
     In the case of the above semiconductor storage devices  80 ,  100 ,  110 , and  120 , fail bits may occur depending on their positions on the memory cell array. 
       FIG. 36  illustrates an example of positional dependence of fail bits. 
       FIG. 36  illustrates an example of a map of fail bits in the memory cell array  28 . In  FIG. 36 , “x” represents the location of a fail bit. In the example in  FIG. 36 , in the memory cell array  28 , more fail bits have occurred in an area close to the plate line driver  26 , and no fail bits have occurred in an area far from the plate line driver  26 . 
     Hereinafter, this positional dependence will be described. 
     If a memory cell is closer to the plate line driver  26 , because of the parasitic capacitance of the plate line, the voltage waveform (a PL waveform in  FIG. 36 ) of the plate line rises more sharply. In contrast, if a memory cell is farther from the plate line driver  26 , the voltage waveform of the plate line rises more gradually. Consequently, rising of the voltage waveform of the bit line is affected (a BL waveform in  FIG. 36 ). Namely, a bit line closer to the plate line driver  26  represents a voltage waveform rising more sharply, and a bit line farther from the plate line driver  26  represents a voltage waveform rising more gradually. 
     The difference between these bit line voltage waveforms also similarly affects the amplified signal Pout (or the output signal REPLICA) that determines the time at which the logic level of the detection signal DET illustrated in  FIG. 16  drops. 
       FIG. 37  illustrates an example of positional dependence of an amplified signal and a determination margin. 
     In the area close to the plate line driver  26 , the amplified signal Pout rises sharply. In the area far from the plate line driver  26 , the amplified signal Pout rises gradually. The logic level of the detection signal DET drops from an H level to an L level when the amplified signal Pout rises and reaches a predetermined level. 
     As illustrated in  FIG. 37 , the difference (determination margin) between when the detection signal DET corresponding to data of logical value “1” drops and when the detection signal DET corresponding to data of logical value “0” drops in the area close to the plate line driver  26  is smaller than the difference in the area far from the plate line driver  26 . Whether the logical value is “1” or “0” is determined based on whether the logic level of the detection signal DET drops before the logic level of the detection signal PDET rises. Thus, if the determination margin is small as is the case with the area close to the plate line driver  26 , the timing control of the detection signal PDET is difficult, and as a result, fail bits could occur. 
     Therefore, the positional dependence of fail bits as illustrated in  FIG. 36  is caused. 
     The following semiconductor storage device according to a ninth embodiment solves the above positional dependence of fail bits. 
       FIG. 38  illustrates an example of a semiconductor storage device according to the ninth embodiment. The same reference characters as used in the semiconductor storage device  20  illustrated in  FIG. 2  are applied to the corresponding components in the semiconductor storage device illustrated in  FIG. 38 . 
     This semiconductor storage device  160  according to the ninth embodiment includes a control circuit  161  and a sense amplifier unit  162  different from the sense amplifier unit  30  illustrated in  FIGS. 2 and 4 . 
     Based on the column address included in an address signal ADS (for example, a low-order bit in the address signal ADS), the control circuit  161  enables at least one of a plurality of capacitors in the pre-sense amplifier included in the sense amplifier unit  162 . 
     Unlike the sense amplifier unit  30 , the sense amplifier unit  162  includes the following pre-sense amplifier, for example. 
       FIG. 39  illustrates an example of a pre-sense amplifier in the semiconductor storage device according to the ninth embodiment. The same reference characters as used in the pre-sense amplifier  81  illustrated in  FIG. 12  are applied to the corresponding components in the pre-sense amplifier illustrated in  FIG. 39 . 
     This pre-sense amplifier  170  includes capacitors  171   a   1  to  171   a   4  and pMOS transistors  171   b   1  to  171   b   4  used as switches. 
     One end of each of the capacitors  171   a   1  to  171   a   4  is connected to a memory cell  11  via a bit line BL. For example, capacitors having the same capacitance value are used as the capacitors  171   a   1  to  171   a   4 . 
     The plurality of pMOS transistors  171   b   1  to  171   b   4  (four transistors in this example) are arranged for the respective capacitors  171   a   1  to  171   a   4 . One end (the source) of each of the pMOS transistors  171   b   1  to  171   b   4  is connected to the other end of a corresponding one of the capacitors  171   a   1  to  171   a   4 . For example, the source of the pMOS transistor  171   b   1  is connected to the other end of the capacitors  171   a   1 , and the source of the pMOS transistor  171   b   4  is connected to the other end of the capacitor  171   a   4 . The other ends of the pMOS transistors  171   b   1  to  171   b   4  are at a power supply potential. 
     In addition, the gates of the pMOS transistors  171   b   1  to  171   b   4  receive control signals LOC&lt; 0 &gt; to LOC&lt; 3 &gt; generated by the control circuit  161 . The pMOS transistors  171   b   1  to  171   b   4  are turned on or off based on the control signals LOC&lt; 0 &gt; to LOC&lt; 3 &gt;, respectively. 
     The capacitors  171   a   1  to  171   a   4  and the pMOS transistors  171   b   1  to  171   b   4  in the pre-sense amplifier  170  are also applicable to the pre-sense amplifiers  92 ,  101 , and Ill in  FIGS. 18, 20, and 22 . 
     The pre-sense amplifiers connected to the reference cells may be formed without the capacitors  171   a   1  to  171   a   4  and the pMOS transistors  171   b   1  to  171   b   4 . Namely, these pre-sense amplifiers may have the same circuit configuration as that of the pre-sense amplifier  83  illustrated in  FIG. 12 , for example. 
     In the semiconductor storage device  160  according to the ninth embodiment, when the memory cell  11  is read, the control circuit  161  generates the control signals LOC&lt; 0 &gt; to LOC&lt; 3 &gt; based on the address (the column address) of the memory cell  11 . The control circuit  161  turns on more switches (the pMOS transistors  171   b   1  to  171   b   4 ) and enables more capacitors when the memory cell  11  on the memory cell array  28  is closer to the plate line driver  26 . 
       FIG. 40  illustrates a control signal generation example. 
       FIG. 40  illustrates an example of the memory cell array  28  divided into four areas based on the distance from the plate line driver  26  and examples of the control signals LOC&lt; 0 &gt; to LOC&lt; 3 &gt; generated when the memory cells in the individual areas are read. 
     If the memory cell  11  belongs to the area closest to the plate line driver  26  among the four areas, the control circuit  161  generates the control signals LOC&lt; 0 &gt; to LOC&lt; 3 &gt; whose logic level is an L level. As a result, the pMOS transistors  171   b   1  to  171   b   4  are set to an on-state, and all the capacitors  171   a   1  to  171   a   4  are enabled. 
     If the memory cell  11  belongs to the area second-closest to the plate line driver  26 , the control circuit  161  generates the control signal LOC&lt; 0 &gt; whose logic level is an H level and the control signals LOC&lt;l&gt; to LOC&lt; 3 &gt; whose logic level is an L level. As a result, three of the pMOS transistors  171   b   1  to  171   b   4  are set to an on-state, and three of the capacitors  171   a   1  to  171   a   4  are enabled. 
     If the memory cell  11  belongs to the area third-closest to the plate line driver  26 , the control circuit  161  generates the control signals LOC&lt;C&gt; and LOC&lt;l&gt; whose logic level is an H level and the control signals LOC&lt; 2 &gt; and LOC&lt; 3 &gt; whose logic level is an L level. As a result, two of the pMOS transistors  171   b   1  to  171   b   4  are set to an on-state, and two of the capacitors  171   a   1  to  171   a   4  are enabled. 
     If the memory cell  11  belongs to the area farthest from the plate line driver  26 , the control circuit  161  generates the control signals LOC&lt; 0 &gt; to LOC&lt; 2 &gt; whose logic level is an H level and the control signal LOC&lt; 3 &gt; whose logic level is an L level. As a result, one of the pMOS transistors  171   b   1  to  171   b   4  is set to an on-state, and one of the capacitors  171   a   1  to  171   a   4  is enabled. 
     As described above, if the memory cell  11  is closer to the plate line driver  26 , more capacitors will be enabled. Consequently, whether the memory cell is close to or far from the plate line driver  26 , the voltage waveform of the bit line connected to the memory cell rises at the same rate. Namely, the voltage waveform of the bit line rises equally. The same holds true for the amplified signal Pout (or the output signal REPLICA) that determines the timing at which the logic level of the detection signal DET drops. 
       FIG. 41  illustrates an example of how the positional dependence of the amplified signal and the determination margin is solved. 
     Even if the memory cell is close to the plate line driver  26 , the amplified signal Pout rises at the same rate as in the case where the memory cell is far from the plate line driver  26 . Thus, the same determination margin is obtained as in the case where the memory cell is far from the plate line driver  26 . In this way, since the positional dependence of the occurrence of fail bits is solved, the timing control of the detection signal PDET is performed easily also on the memory cells close to the plate line driver  26 , and the occurrence of fail bits is prevented. 
     Depending on the distance from the plate line driver  26 , a certain number of capacitors may be connected to a bit line of the memory cell array  28 . However, in this case, the area of the memory cell array  28  is increased. This increase of the area is avoided by arranging the capacitors  171   a   1  to  171   a   4  in the memory cell array  28  and changing the number of capacitors enabled depending on the position of the read memory cell  11 , as illustrated in  FIG. 39 . 
     The number of capacitors  171   a   1  to  171   a   4  is at least 2. Namely, the number of capacitors  171   a   1  to  171   a   4  is not limited to the above number. The number of capacitors is suitably determined by comparing how much the accuracy in solving the positional dependence of the occurrence of fail bits is improved by increasing the number of capacitors with the increase of the circuit area. 
     Tenth Embodiment 
     Next, a semiconductor storage device according to a tenth embodiment will be described. As is the case with the semiconductor storage device  160  according to the ninth embodiment, the semiconductor storage device according to the tenth embodiment solves the positional dependence of fail bits. 
       FIG. 42  illustrates an example of the semiconductor storage device according to the tenth embodiment. The same reference characters as used in the semiconductor storage device  20  illustrated in  FIG. 2  are applied to the corresponding components in the semiconductor storage device illustrated in  FIG. 42 . 
     This semiconductor storage device  180  according to the tenth embodiment includes a control circuit  181  and a plate line driver  182  different from the plate line driver  26  in  FIG. 2 . A sense amplifier unit  183  includes pre-sense amplifiers (for example, the pre-sense amplifiers  81  to  83 , etc. in  FIG. 12 ) used in the semiconductor storage device according to the fourth and subsequent embodiments. 
     Based on the column address included in an address signal ADS (for example, a low-order bit in the address signal ADS), the control circuit  181  enables at least one of a plurality of driver circuits included in the plate line driver  182 . 
       FIG. 43  illustrates an example of the plate line driver. While  FIG. 43  illustrates a part for driving a plate line PLm, the other parts driving the other plate lines are configured in the same way. 
     The plate line driver  182  includes a buffer  182   a , NAND circuits  182   b   1  to  182   b   4 , and driver circuits  182   c   1  to  182   c   4 . 
     A row decoder  23  supplies the buffer  182   a  with a row decoded signal PLINm whose logic level indicates an H level when an individual memory cell connected to the plate line PLm is read. 
     One input terminal of each of the NAND circuits  182   b   1  to  182   b   4  is supplied with the row decoded signal PLINm. The other input terminal of the NAND circuit  182   b   1  is supplied with a control signal COL&lt; 0 &gt;, and the other input terminal of the NAND circuit  182   b   2  is supplied with a control signal COL&lt; 1 &gt;. The other input terminal of the NAND circuit  182   b   3  is supplied with a control signal COL&lt; 2 &gt;, and the other input terminal of the NAND circuit  182   b   4  is supplied with a control signal COL&lt; 3 &gt;. These control signals COL&lt; 0 &gt; to COL&lt; 3 &gt; are supplied from the control circuit  181 . 
     An output signal SEL&lt; 0 &gt; outputted from the NAND circuit  182   b   1  is inputted to the driver circuit  182   c   1 , and an output signal SEL&lt;l&gt; outputted from the NAND circuit  182   b   2  is inputted to the driver circuit  182   c   2 . An output signal SEL&lt; 2 &gt; outputted from the NAND circuit  182   b   3  is inputted to the driver circuit  182   c   3 , and an output signal SEL&lt; 3 &gt; outputted from the NAND circuit  182   b   4  is inputted to the driver circuit  182   c   4 . 
     The driver circuits  182   c   1  to  182   c   4  are enabled or disabled based on the logic levels of the control signals COL&lt; 0 &gt; to COL&lt; 3 &gt;. For example, when the logic level of the control signal COL&lt;l&gt; is an L level, irrespective of the logic level of the row decoded signal PLINm, the output signal SEL&lt; 1 &gt; of the NAND circuit  182   b   2  indicates an H level, and the driver circuit  182   c   2  is disabled. 
     If more of the driver circuits  182   c   1  to  182   c   4  are enabled, the plate line driver  182  exhibits higher output performance. In contrast, if fewer of the driver circuits  182   c   1  to  182   c   4  are enabled, the plate line driver  182  exhibits lower output performance. 
     At least one of the driver circuits  182   c   1  to  182   c   4  outputs a signal of a voltage level for reading when an individual memory cell connected to the plate line PLm is selected and outputs a signal of a voltage level (for example, 0 V) that is lower than the above voltage level when the above memory cell is not selected. The following example assumes that the driver circuit  182   c   1  outputs a signal of a voltage level for reading when an individual memory cell connected to the plate line PLm is selected and outputs a signal of 0 V when the above memory cell is not selected. 
     When enabled, the driver circuits  182   c   2  to  182   c   4  output the signal of the voltage level for reading. In contrast, when disabled, the driver circuits  182   c   2  to  182   c   4  output a signal of a high impedance level between the voltage level for reading and 0 V. 
     The output terminals of the driver circuits  182   c   1  to  182   c   4  are connected to the plate line PLm. 
     As illustrated in  FIG. 43 , each of the driver circuits  182   c   2  to  182   c   4  includes, for example, a pMOS transistor  182   d  and an nMOS transistor  182   e . A power supply voltage VDD is applied to the source of the pMOS transistor  182   d  as the voltage level for reading, and the drains of the pMOS transistor  182   d  and the nMOS transistor  182   e  are connected to the plate line PLm. The gate of the pMOS transistor  182   d  is supplied with any one of the output signals SEL&lt; 1 &gt; to SEL&lt; 3 &gt; (SEL&lt; 1 : 3 &gt;), and the gate and the source of the nMOS transistor  182   e  are connected to ground. 
     In the case of the semiconductor storage device  180  according to the tenth embodiment, when an individual memory cell connected to the plate line PLm is read, the control circuit  181  generates the control signals COL&lt; 0 &gt; to COL&lt; 3 &gt; based on the address (column address) of the memory cell. The control circuit  181  enables more driver circuits when the memory cell to be read on the memory cell array  28  is farther from the plate line driver  182 . 
       FIG. 44  illustrates a control signal generation example. 
       FIG. 44  illustrates an example of the memory cell array  28  divided into four areas based on the distance from the plate line driver  26  and examples of the control signals COL&lt; 0 &gt; to COL&lt; 3 &gt; generated when the memory cells in the individual areas are read. 
     If a memory cell belongs to the area closest to the plate line driver  182  among the four areas, the control circuit  181  generates the control signal COL&lt; 0 &gt; whose logic level is an H level and the control signals COL&lt; 1 &gt; to COL&lt; 3 &gt; whose logic level is an L level. As a result, the driver circuit  182   c   1  is enabled, and the driver circuits  182   c   2  to  182   c   4  are disabled. 
     If a memory cell belongs to the area second-closest to the plate line driver  182 , the control circuit  181  generates the control signals COL&lt; 0 &gt; and COL&lt;l&gt; whose logic level is an H level and the control signals COL&lt; 2 &gt; and COL&lt; 3 &gt; whose logic level is an L level. As a result, the driver circuits  182   c   1  and  182   c   2  are enabled, and the driver circuits  182   c   3  and  182   c   4  are disabled. 
     If a memory cell belongs to the area third-closest to the plate line driver  182 , the control circuit  181  generates the control signals COL&lt; 0 &gt; to COL&lt; 2 &gt; whose logic level is an H level and the control signal COL&lt; 3 &gt; whose logic level is an L level. As a result, the driver circuits  182   c   1  to  182   c   3  are enabled, and the driver circuit  182   c   4  is disabled. 
     If a memory cell belongs to the area farthest from the plate line driver  182 , the control circuit  181  generates the control signals COL&lt; 0 &gt; to COL&lt; 3 &gt; whose logic level is an H level. As a result, all the driver circuits  182   c   1  to  182   c   4  are enabled. In this case, the plate line driver  182  exhibits the highest output performance with respect to the plate line connected to the memory cell. 
     As described above, if the memory cell to be read is farther from the plate line driver  182 , more driver circuits are enabled. Consequently, whether the memory cell is close to or far from the plate line driver  182 , the voltage waveform of the plate line rises at the same rate. 
     Consequently, whether the memory cell is close to or far from the plate line driver  182 , the voltage waveform of the bit line connected to the memory cell rises at the same rate. Namely, the voltage waveform of the bit line rises equally. The same holds true for the amplified signal Pout (or the output signal REPLICA) that determines the timing at which the logic level of the detection signal DET drops. 
     As a result, as is the case with the semiconductor storage device  160  according to the ninth embodiment, the semiconductor storage device  180  according to the tenth embodiment solves the positional dependence of the occurrence of fail bits. 
     The number of driver circuits  182   c   1  to  182   c   4  is at least 2. Namely, the number of driver circuits  182   c   1  to  182   c   4  is not limited to the above number. The number of driver circuits is suitably determined by comparing how much the accuracy in solving the positional dependence of the occurrence of fail bits is improved by increasing the number of driver circuits with the increase of the circuit area. 
     While an aspect of the semiconductor storage devices, the read method thereof, and the test method thereof has been described based on the above embodiments, the above description is only an example, and the embodiments are not limited to the above description. 
     In one aspect, the embodiments prevent reduction of the read margin that could occur when data written in a memory cell is read and achieve stable data determination when data written in a memory cell is read. 
     All examples and conditional language provided herein are intended for the pedagogical purposes of aiding the reader in understanding the invention and the concepts contributed by the inventor to further the art, and are not to be construed as limitations to such specifically recited examples and conditions, nor does the organization of such examples in the specification relate to a showing of the superiority and inferiority of the invention. Although one or more embodiments of the present invention have been described in detail, it should be understood that various changes, substitutions, and alterations could be made hereto without departing from the spirit and scope of the invention.