Patent Publication Number: US-7586805-B2

Title: Method and system for providing directed bank refresh for volatile memories

Description:
RELATED APPLICATIONS 
     The present application claims priority from and is a continuation of U.S. patent application Ser. No. 10/982,038, filed Nov. 5, 2004, and issued as U.S. Pat. No. 7,079,440, which claims priority to U.S. Provisional Application No. 60/575,334, filed May 27, 2004. The contents of U.S. patent application Ser. No. 10/982,038 and U.S. Provisional Application No. 60/575,334 are expressly incorporated herein by reference in their entirety. 
    
    
     BACKGROUND 
     1. Field 
     The present disclosure relates generally to memory devices, and more specifically, to methods and systems for providing directed bank refresh for volatile memories. 
     2. Background 
     Volatile memory is a storage medium that is generally structured as a number of arrays (or banks). Each bank is further arranged as a matrix of “memory cells” in rows and columns, with each column being further divided by the input/output (I/O) width of the memory. Locations within the memory are uniquely specified by bank, row and column. A memory controller may be used to retrieve data from the memory by indicating the data&#39;s bank, row and column location. For example, for a quad-bank 128 Mb memory with a 16-bit external data bus, a possible logical address mapping includes a 9-bit column address, a 2-bit bank address and a 12-bit row address. 
     Prior to reading or writing a memory location, the corresponding row must first be opened. The process of opening a row requires a minimum number of clock cycles, t RCD , which represents the row-to-column delay. Once a row is open, column addresses within that row can be read or written as desired. For some dynamic random access memories (DRAMs), such as synchronous DRAMs (SDRAMs), only one row per bank can be kept open at any one time; a subsequent memory access to be performed within the same bank but at a different row requires closing the current row and opening the new one. 
     In the case of dynamic volatile memories, each cell must be refreshed, or re-energized, periodically at an average interval, t REF1 , in order to maintain data integrity. The cells have to be refreshed because they are designed around capacitors that store electrical charges, which may discharge over time. Refresh is the process of recharging the cells in memory. Cells are generally refreshed one row at a time. A number of methods currently exist that are designed to refresh volatile memories. Some, if not all, of these methods incur high cost in performance and/or power. For example, there are two common methods or techniques that are generally used to control the refresh of volatile memories in modern digital systems. One method relies on the memory to keep track of the row and bank(s) that need to be refreshed using built-in refresh mechanisms that are available on the memory; the other method relies on the memory controller to keep track of the row and bank that need to be refreshed. 
     The first commonly used method is utilized by the auto-refresh and self-refresh functions of the volatile memories. These functions use the built-in refresh address of the memory. During active use of the memory, when a refresh cycle is required, the memory controller precharges all the banks, and then uses the auto-refresh command to tell the memory to issue an internal refresh cycle. Upon receiving the auto-refresh command, the memory increments the internal refresh address counter and executes the internal refresh cycle. In auto-refresh mode, the memory uses the refresh address in its internal refresh address counter to determine which rows/banks to perform the refresh cycle and cycle through the relevant rows. In one implementation, the internal refresh address counter includes a row address register and a bank address register. The bank address register is incremented to cycle through each of the memory banks with the carry-out of the bank address register causing the row address register to increment. Other implementations do not have a bank address register as all banks are simultaneously refreshed. 
     A disadvantage of present non-simultaneous bank auto-refresh implementations is that because the memory controller does not know which internal bank will be refreshed, the memory controller is required to close all open rows in each bank prior to issuing an auto-refresh command. As a result, the memory data bus availability during an auto-refresh sequence is zero. At best, this sequence requires t RP +t RFC +t RCD  cycles, where t RFC  represents a row-precharge delay, t RFC  represents the refresh cycle time and t RCD  represents the row-to-column delay. For a 133 MHz memory, this could be 16 clock cycles (120 ns). These cycles are sometimes referred to as dead cycles since the memory data bus is not available during this period. 
     During periods of non-use, the memory controller may place the memory in the self-refresh mode. In the self-refresh mode, the memory uses its own internal clock and refresh address counter to generate refreshes to refresh the row(s) of the memory. This method is good for saving power during idle states since the self-refresh mode can be used. The self-refresh state uses a small amount of power and maintains the contents of the memory by refreshing the memory. Due to the small amount of power needed, this method is typically used for low power applications. 
     A second method is sometimes used to avoid the dead cycles on the memory data bus mentioned above. According to this second method, control of the refresh is effected via the memory controller. This method does not use any of the built-in refresh mechanisms that are available on the memory. Under this method, at regularly given intervals (t REF1 ), the memory controller explicitly generates refreshes by opening and closing rows in a sequential manner using bank/row address combinations. The refresh clock, which determines the refresh rate, and the bank/row address combinations are internal to the memory controller. This method is best for high speed/high performance applications. This method allows the memory controller to refresh a particular memory bank while permitting other memory banks to remain open for access, resulting in higher performance; reads and writes to other banks can generally continue in parallel and uninterrupted. The downside to this method is that during system power down or long idle states, when the memory controller is not refreshing the memory, the memory cannot be kept in a self-refresh state. As mentioned above, the self-refresh state is a built-in function of most volatile memories. Since the self-refresh function of the memory increments a refresh address (i.e., the row/bank address) stored in a refresh address counter in the memory, independent of the memory controller, the refresh address maintained by the memory is not consistent or synchronized with the memory controller. 
     Refresh operations can reduce performance of memory because each refresh cycle forces the memory into an idle state, during which data access is not available. For example, if a refresh cycle is required for a particular memory bank while such bank is in an active state, the bank has to be shut down to allow the refresh operation to take place. Shutting down the bank means that whatever data operations that were to be performed have to be delayed, hence, affecting system performance. 
     Some existing schemes are available to reduce the performance impact of refresh operations. Such schemes typically involve using a higher than required refresh rate, so that more memory banks can be refreshed within a predetermined refresh period. By having more memory banks refreshed, the chances of having to shut down an active memory bank for refresh are reduced. Using a higher refresh rate, however, has its drawbacks. For example, an increase in refresh rate means memory becomes unavailable for access more often which, in turn, results in lower performance. Also, merely using a higher refresh rate does not always obviate the need to shut down an active memory bank when refresh is required; in some situations, an active memory bank has to be shut down regardless, thus, negating any benefits from using a higher refresh rate. 
     Hence, it would be desirable to provide more efficient methods and systems for providing directed bank refresh for volatile memories. 
     SUMMARY 
     One aspect of a memory system is disclosed. The memory system includes a volatile memory capable of operating in an auto-refresh mode and a self-refresh mode, the volatile memory having a plurality of banks. The memory system also includes a memory controller configured to provide a target bank address to each of the banks to perform an auto-refresh operation on the target bank, while the other banks remain available for access. 
     Another aspect of a memory system is disclosed. The memory system includes a volatile memory capable of operating in an auto-refresh mode and a self-refresh mode, the volatile memory having a plurality of banks and a single refresh counter configured to provide a row address to each of the banks during an auto-refresh operation. The memory system also includes a memory controller configured to direct the volatile memory to perform an auto-refresh operation on a target bank, while the other banks remain available for access. 
     It is understood that other embodiments of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein various embodiments of the invention are shown and described by way of illustration. As will be realized, the invention is capable of other and different embodiments and its several details are capable of modification in various other respects, all without departing from the spirit and scope of the present invention. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present invention are illustrated by way of example, and not by way of limitation, in the accompanying drawings, wherein: 
         FIG. 1  is a simplified block diagram illustrating an arrangement that can be used to practice the directed refresh method according to the present disclosure; and 
         FIG. 2  is a simplified block diagram illustrating a volatile memory that can be used to practice the directed refresh method according to the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The detailed description set forth below in connection with the appended drawings is intended as a description of various embodiments of the present invention and is not intended to represent the only embodiments in which the present invention may be practiced. The detailed description includes specific details for the purpose of providing a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form in order to avoid obscuring the concepts of the present invention. 
     Various embodiments of a memory system will now be described. In one embodiment, a directed refresh method is provided which improves data availability in a memory during refresh operations.  FIG. 1  shows an arrangement  100  that can be used to practice the directed refresh method. As shown in  FIG. 1 , the directed refresh method may be practiced with a volatile memory  110  and a controller  120  configured to control the volatile memory  110 . The volatile memory  110  can be, for example, a DRAM (dynamic random access memory), a SDRAM (synchronous DRAM), and various other types of DRAM, etc. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate how to practice the concepts associated with the present disclosure with other types of memories which require refresh operations. The directed refresh method may be effected via control logic or a processor (not shown) which controls the memory controller  120  and the volatile memory  110 . It should be understood that the control logic or processor may be implemented as an independent module or integrated as part of another component, such as, the memory controller  120 . 
       FIG. 2  further shows one embodiment of the volatile memory  110  that can be used to practice the directed refresh method. The volatile memory  110  may further include a refresh counter  200  having a row address counter  250  and a row increment counter  220 , a refresh trigger  240 , a bank address latch  230  and a number of banks  210 . 
     The refresh trigger  240  may be used to control both the refresh counter  200  and the bank address latch  230 . The refresh trigger  240  is used by the volatile memory  110  to initiate a refresh operation either in the auto-refresh mode or self-refresh mode. For example, upon receiving an auto-refresh command from the memory controller  120  (see  FIG. 1 ), the volatile memory  110  may direct the refresh trigger  240  to initiate the auto-refresh operation. The refresh trigger  240  can be, for example, a clock or other timing mechanisms. 
     The row address counter  250  may be used to store the target row address for the row that is to be refreshed. The bank address latch  230  may be used to store the target bank address for the specific bank containing the row that is to be refreshed. 
     The memory controller  120  may direct the volatile memory  110  to auto-refresh a specific memory bank within the volatile memory  110  while other memory banks remain available for access. For each auto-refresh cycle initiated by the memory controller  120 , the bank address  270  may be loaded by the memory controller  120  (see  FIG. 1 ) into the bank address latch  230 . The bank address  270  is used to select one of the banks  210  for refresh. Because the memory controller  120  (see  FIG. 1 ) is aware of the specific bank to be refreshed, access to the other internal banks may continue without interruption. This tends to maximize the memory data bus utilization, reduces power consumption by avoiding unnecessary row close/open sequences, and serves to minimize transfer latency. 
     The row increment counter  220  may be initialized upon power-up or reset. The initialized value for the row increment counter  220  can be arbitrary. The row increment counter  220  causes the row address counter  250  to be incremented after a predetermined number of auto-refresh operations have been performed. The row address counter  250  contains the target row address for a row that is to be refreshed. The row address counter  250  points to the same row in all the banks  210 . 
     The memory controller  120  initiates each auto-refresh cycle by issuing an auto-refresh command to the volatile memory  110  and loading the bank address  270  for the bank to be refreshed into the bank address latch  230 . Upon receiving the auto-refresh command, the volatile memory  110  uses the refresh trigger  240  to initiate each auto-refresh operation. The refresh trigger  240  causes the row increment counter  220  to increment. Cyclically, the row address counter  250  is incremented by a carry-out signal  260  from the row increment counter  220 . For example, the row increment counter  220  may be a 2-bit counter, which means the row increment counter  220  repeats itself every four (4) refresh clock cycles; conversely, the row address counter  250  is incremented after every 4th auto-refresh operation. The target row address stored in the row address counter  250  and the bank address  270  stored in the bank address latch  230  are then used to refresh a specific row in the identified bank. 
     Since the target row address changes periodically based on the predetermined number of auto-refresh operations and the memory controller  120  does not know when the row address counter  250  will be incremented, the memory controller  120  (see  FIG. 1 ) issues auto-refresh commands in a consistent, sequential order with respect to the banks  210 ; in other words, the memory controller  120  loads the bank addresses of the banks  210  into the bank address latch  230  one at a time in a sequential manner during each auto-refresh cycle. As a result, the banks  210  are refreshed sequentially in successive auto-refresh cycles. For example, for the four (4) banks shown in  FIG. 2 , the refresh bank order could be either “3-2-1-0-3-2-1-0” or “0-1-2-3-0-1-2-3”. One order does not have an advantage over the other. Therefore, either one can be used. In one implementation, the sequence “0-1-2-3-0-1-2-3-. . . ” may be used. As will be further described below, choosing this sequence simplifies the transition into self-refresh mode. 
     The operation of the volatile memory  110  as shown in  FIG. 2  is further illustrated in an example as follows. In this example, the initial value in the row increment counter  220  is assumed to be zero (0) and the carry-out signal  260  of the row increment counter  220  is activated after every 4th auto-refresh operation. The memory controller  120  (see  FIG. 1 ) issues an auto-refresh command to the volatile memory  110  and loads the bank address  270  for the bank  210   a  into the bank address latch  230  to initiate a first auto-refresh cycle. Upon receiving the auto-refresh command, the volatile memory  110  directs the refresh trigger  240  to initiate an auto-refresh operation. During the auto-refresh operation, the row increment counter  220  is incremented to a value of one (1). In this instance, the carry-out signal  260  is not activated and the row address counter  250  is not incremented. The target row address and the bank address currently stored in the row address counter  250  and the bank address latch  230  respectively are then used to refresh a specific row in the bank  210   a.    
     Subsequently, the memory controller  120  (see  FIG. 1 ) issues another auto-refresh command to the volatile memory  110  and loads the bank address  270  for the bank  210   b  into the bank address latch  230  to initiate a second auto-refresh cycle. Similarly, upon receiving the second auto-refresh command, the volatile memory  110  directs the refresh trigger  240  to initiate another auto-refresh operation. During this auto-refresh operation, the row increment counter  220  is incremented to a value of two (2). Again, the carry-out signal  260  is not activated and the row address counter  250  is not incremented. The target row address and the bank address currently stored in the row address counter  250  and the bank address latch  230  respectively are then used to refresh a specific row in the bank  210   b . It should be noted that since the row address counter  250  is not incremented, the target row address used in this auto-refresh operation is the same as the one used in the last auto-refresh operation. However, for this auto-refresh operation, the bank address stored in the bank address latch  230  is different in that a different bank  210   b  is identified. As a result, the same row in a different bank  210   b  (as opposed to bank  210   a ) is refreshed. 
     Similarly, it will be appreciated that for the 3d and 4th auto-refresh cycles, the row address counter  250  is not incremented (since the carry-out signal  260  of the row increment counter  220  is not activated). Consequently, the same row in different banks  210   c  and  210   d  are refreshed during the 3d and 4th auto-refresh cycles. 
     For the 5th auto-refresh cycle, the bank address  270  loaded by the memory controller  120  (see  FIG. 1 ) into the bank address latch  230  points back to the bank  210   a . Furthermore, the carry-out signal  260  of the row increment counter  220  is now activated since four (4) auto-refresh operations have already been performed. The carry-out signal  260 , in turn, increments the row address counter  250  thereby moving the target row address to a new row for refresh. This same new row is then refreshed for all four (4) banks  210  during successive auto-refresh cycles. 
     When the volatile memory  110  is commanded into self-refresh mode, the volatile memory  110  begins to generate refreshes internally using the bank address currently stored in the bank address latch  230  from the point where the memory controller  120  left off issuing the last auto-refresh command to the volatile memory  110 . This is rendered possible because, as previously mentioned, the memory controller  120  issues auto-refresh commands in a sequential manner. 
     Subsequently, following each refresh in self-refresh mode, the output of the bank address latch  230  is incremented. In effect, the bank address latch  230  becomes a counter. Hence, when in the self-refresh mode, the bank address latch  230  is incremented periodically and used to cycle through the banks  210 ; and the row increment counter  220  is also incremented periodically which, in turn, increments the row address counter  250  containing the target row address for a row to be refreshed, thereby allowing rows to be cycled through in the banks  210 . 
     When exiting the self-refresh mode, the volatile memory  110  internally resets or clears the row increment counter  220 . This resynchronizes the volatile memory  110  and the memory controller  120  and ensures that the row represented by the current target row address will be refreshed in all the banks  210 . By resetting the row increment counter  220 , the volatile memory  110  ensures that the row address counter  250  is only incremented after the predetermined number of auto-refresh operations have been performed, which means that the row represented by the current target row address is refreshed in all the banks  210 . 
     Also, the memory controller  120  issues a number of auto-refresh commands within one (1) average refresh period (t REF1 ) after the volatile memory  110  exits the self-refresh mode. Since the memory controller  120  does not know which bank was last refreshed by the volatile memory  110  prior to exiting the self-refresh mode, these auto-refresh commands are used to ensure that all the banks  210  are refreshed within one (1) average refresh period (t REF1 ), which conversely ensures that data integrity is maintained and no data is lost. The number of auto-refresh commands that are to be issued within one (1) average refresh period (t REF1 ) depends on the number of banks  210  in the volatile memory  110 . For example, the number of auto-refresh commands to be issued subsequent to the self-refresh mode exit is four (4) for the volatile memory  110  shown in  FIG. 2 . The average refresh period (t REF1 ) may vary depending on a particular volatile memory. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate how to implement the row increment counter  220  and determine the appropriate number of auto-refresh commands to be issued after exit from self-refresh mode in accordance with the present disclosure. 
     It should be noted that issuing the auto-refresh commands within one (1) average refresh period (t REF1 ) after exit from the self-refresh mode is optional, if the memory controller  120  implements a refresh-ahead scheme and is at least a number of refreshes ahead prior to entering the self-refresh mode. For example, with the volatile memory  110  as shown in  FIG. 2 , there is no need to issue the auto-refresh commands within one (1) average refresh period (t REF1 ) after exit from the self-refresh mode if at least four (4) refreshes have been performed ahead prior to entering the self-refresh mode. A number of refresh-ahead schemes are known in the art. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will appreciate how to incorporate a refresh-ahead scheme for use in connection with the present disclosure. 
     The methods or algorithms described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executable by a processor, or in a combination of both, in the form of control logic, programming instructions, or other directions. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. A storage medium may be coupled to the processor such that the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. 
     The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit of scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein, but is to be accorded the full scope consistent with the claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more”. All structural and functional equivalents to the elements of the various embodiments described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. § 112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for”.