Patent Publication Number: US-9893072-B2

Title: DRAM with nanofin transistors

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional of U.S. application Ser. No. 13/357,347, filed Jan. 24, 2012, now issued as U.S. Pat. No. 9,087,730, which is a continuation of U.S. application Ser. No. 12/353,592, filed Jan. 14, 2009, now issued as U.S. Pat. No. 8,119,484, which is a divisional of U.S. application Ser. No. 11/397,413, filed Apr. 4, 2006, now issued as U.S. Pat. No. 7,491,995, all of which are incorporated herein by reference in their entirety. 
     This application is related to the following commonly assigned U.S. patent applications which are herein incorporated by reference in their entirety: “Nanowire Transistor With Surrounding Gate,” U.S. application Ser. No. 11/397,527, filed on Apr. 4, 2006 (U.S. Pub. 20070232007); “Grown Nanofin Transistors,” U.S. application Ser. No. 11/397,430, filed on Apr. 4, 2006 (U.S. Pub. 20070231985); “Etched Nanofin Transistors,” U.S. application Ser. No. 11/397,358, filed on Apr. 4, 2006 (U.S. Pub. 20070231980); and “Tunneling Transistor With Sublithographic Channel,” U.S. application Ser. No. 11/397,406, filed on Apr. 4, 2006 (U.S. Pub. 20070228491). 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to semiconductor devices, and more particularly, to DRAMs with nanofin transistors. 
     BACKGROUND 
     The semiconductor industry has a market driven need to reduce the size of devices, such as transistors, and increase the device density on a substrate. Some product goals include lower power consumption, higher performance, and smaller sizes.  FIG. 1  illustrates general trends and relationships for a variety of device parameters with scaling by a factor k. The continuous scaling of MOSFET technology to the deep sub-micron region where channel lengths are less than 0.1 micron (100 nm or 1000 Å) causes significant problems in the conventional transistor structures. For example, junction depths should be much less than the channel length. Thus, with reference to the transistor  100  illustrated in  FIG. 1 , the junctions depths  101  should be on the order of a few hundred Angstroms for channels lengths  102  that are approximately 1000 Å long. Such shallow junctions are difficult to form by conventional implantation and diffusion techniques. Extremely high levels of channel doping are required to suppress short-channel effects such as drain induced barrier lowering, threshold voltage roll off, and sub-threshold conduction. Sub-threshold conduction is particularly problematic in DRAM technology as it reduces the charge storage retention time on the capacitor cells. These extremely high doping levels result in increased leakage and reduced carrier mobility. Thus, the expected improved performance attributed to a shorter channel is negated by the lower carrier mobility and higher leakage attributed to the higher doping. 
     Leakage current is a significant issue in low voltage and lower power battery-operated CMOS circuits and systems, and particularly in DRAM circuits. The threshold voltage magnitudes are small to achieve significant overdrive and reasonable switching speeds. However, as illustrated in  FIG. 2 , the small threshold results in a relatively large sub-threshold leakage current. 
     Some proposed designs to address this problem use transistors with ultra-thin bodies, or transistors where the surface space charge region scales as other transistor dimensions scale down. Dual-gated or double-gated transistor structures also have been proposed to scale down transistors. As commonly used in the industry, “dual-gate” refers to a transistor with a front gate and a back gate which can be driven with separate and independent voltages, and “double-gated” refers to structures where both gates are driven when the same potential. An example of a double-gated device structure is the FinFET. “TriGate” structures and surrounding gate structures have also been proposed. In the “TriGate” structure, the gate is on three sides of the channel. In the surrounding gate structure, the gate surrounds or encircles the transistor channel. The surrounding gate structure provides desirable control over the transistor channel, but the structure has been difficult to realize in practice. 
       FIG. 3  illustrates a dual-gated MOSFET with a drain, a source, and front and back gates separated from a semiconductor body by gate insulators, and also illustrates an electric field generated by the drain. Some characteristics of the dual-gated and/or double-gated MOSFET are better than the conventional bulk silicon MOSFETs, because compared to a single gate, the two gates better screen the electric field generated by the drain electrode from the source-end of the channel. The surrounding gate further screens the electric field generated by the drain electrode from the source. Thus, sub-threshold leakage current characteristics are improved, because the sub-threshold current is reduced more quickly as the gate voltage is reduced when the dual-gate and/or double gate MOSFET turns off.  FIG. 4  generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, or surrounding gate MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs. 
       FIGS. 5A-C  illustrate a conventional FinFET.  FIG. 5A  illustrates a top view of the FinFET and  FIG. 5B  illustrates an end view of the FinFET along line  5 B- 5 B. The illustrated FinFET  503  includes a first source/drain region  504 , a second source drain region  505 , a silicon fin  506  extending between the first and second source/drain regions. The silicon fin functions as a transistor body, where the channel between the first and second source/drain regions is horizontal. A gate insulator  507 , such as silicon oxide, is formed over the fin, and a gate  508  is formed over the fin after the oxide is formed thereon. The fin of the illustrated conventional FinFET is formed over buried oxide  509 .  FIG. 5C  illustrates a conventional etch technique for fabricating the fin for the FINFET. As illustrated in  FIG. 5C , the fin width is defined by photolithography or e-beam lithography and etch. Thus, the fin width is initially a minimum feature size (1F). The width of the fin is subsequently reduced by oxidation or etch, as illustrated by arrows  510 . 
     SUMMARY 
     Aspects of the present subject matter provide nanofin transistors with near ideal sub-threshold characteristics and miniaturized sub-threshold leakage, and with extremely small drain region volumes to minimize drain leakage currents. One method for fabricating the nanofins involves growing the nanofins on a substrate, using solid phase epitaxial growth to recrystallize amorphous semiconductor on the substrate. Another method for fabricating the nanofins involves etching fins into single crystalline silicon substrates. The silicon nanofins are formed with dimensions smaller than lithographic dimensions by sidewall spacer techniques. The present subject matter applies these transistors in DRAM arrays as access transistors to improve DRAM retention time. The ultrathin fin shaped bodies of the fin transistors reduce sub-threshold leakage and the extremely small drain regions and surface areas reduce junction leakage. Some embodiments, for example, provide ultrathin fins within a range of thicknesses on the order of 20 nm to 50 nm. 
     One aspect of the present subject matter relates to a memory. A memory embodiment includes a nanofin transistor having a first source/drain region, a second source/drain region above the first source/drain region, and a vertically-oriented channel region between the first and second source/drain regions. The nanofin transistor also has a surrounding gate insulator around the nanofin structure and a surrounding gate surrounding the channel region and separated from the nanofin channel by the surrounding gate insulator. The memory includes a data-bit line connected to the first source/drain region, at least one word line connected to the surrounding gate of the nanofin transistor, and a stacked capacitor above the nanofin transistor and connected between the second source/drain region and a reference potential. 
     These and other aspects, embodiments, advantages, and features will become apparent from the following description of the present subject matter and the referenced drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates general trends and relationships for a variety of device parameters with scaling by a factor k. 
         FIG. 2  illustrates sub-threshold leakage in a conventional silicon MOSFET. 
         FIG. 3  illustrates a dual-gated MOSFET with a drain, a source, front and back gates separated from a semiconductor body by gate insulators, and an electric field generated by the drain. 
         FIG. 4  generally illustrates the improved sub-threshold characteristics of dual gate, double-gate, and surrounding gate MOSFETs in comparison to the sub-threshold characteristics of conventional bulk silicon MOSFETs. 
         FIGS. 5A-C  illustrate a conventional FINFET. 
         FIGS. 6A-6B  illustrate a side view and a cross-section view of along line  6 B- 6 B, respectively, of a vertically-oriented nanofin transistor, according to various embodiments of the present subject matter. 
         FIGS. 7A-7L  illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter. 
         FIGS. 8A-8L  illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter. 
         FIGS. 9A-9C  illustrate the application of FINFETs as DRAM access transistors with buried data-bit lines, according to various embodiments of the present subject matter. 
         FIGS. 10A-10B  illustrate side and top views, respectively, of another embodiment in which FINFETs function as DRAM access transistors. 
         FIG. 11  illustrates a top view of a layout of nanofins for an array of nanofin transistors, according to various embodiments. 
         FIG. 12  illustrates a method for forming a DRAM with a nanofin transistor, according to various embodiments. 
         FIG. 13  illustrates one method for connecting a first source/drain region to a bit line, according to various embodiments. 
         FIG. 14  illustrates another method for connecting a first source/drain region to a bit line, according to various embodiments. 
         FIG. 15  is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter. 
         FIG. 16  illustrates a diagram for an electronic system having a DRAM with nanofin transistors, according to various embodiments. 
         FIG. 17  depicts a diagram of an embodiment of a system having a controller and a memory. 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description refers to the accompanying drawings which show, by way of illustration, specific aspects and embodiments in which the present subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present subject matter. The various embodiments of the present subject matter are not necessarily mutually exclusive as aspects of one embodiment can be combined with aspects of another embodiment. Other embodiments may be utilised and structural, logical, and electrical changes may be made without departing from the scope of the present subject matter. In the following description, the terms “wafer” and “substrate” are interchangeably used to refer generally to any structure on which integrated circuits are formed, and also to such structures during various stages of integrated circuit fabrication. Both terms include doped and undoped semiconductors, epitaxial layers of a semiconductor on a supporting semiconductor or insulating material, combinations of such layers, as well as other such structures that are known in the art. The term “horizontal” as used in this application is defined as a plane parallel to the conventional plane or surface of a wafer or substrate, regardless of the orientation of the wafer or substrate. The term “vertical” refers to a direction perpendicular to the horizontal as defined above. Prepositions, such as “on”, “side”, “higher”, “lower”, “over” and “under” are defined with respect to the conventional plane or surface being on the top surface of the wafer or substrate, regardless of the orientation of the wafer or substrate. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
     Aspects of the present subject matter provide nanofin transistors with vertical channels, where there is a first source/drain region at the bottom of the fin and a second source/drain region at the top of the fin, and use these nanofin transistors in a DRAM device. The nanofins can be formed using a technique that recrystallizes vertical amorphous nanofins on a substrate as described in U.S. patent application Ser. No. 11/397,430, filed on Apr. 4, 2006 (U.S. Pub. 20070231985) and a technique that etches single crystalline nanofins as described in U.S. patent application Ser. No. 11/397,358, filed on Apr. 4, 2006 (U.S. Pub. 20070231980). Access transistors for DRAM arrays use these nanofin transistors to control sub-threshold leakage and improve DRAM retention time. The ultrathin fin shaped bodies of the transistors reduce sub-threshold leakage and the extremely small drain regions and surface areas reduce junction leakage. 
     Dual-gated, double-gated, and/or surrounding gate MOSFETs offer better characteristics than conventional bulk silicon MOSFETs. Whereas conventional MOSFETs have a gate only on one side of the channel, the dual-gated or double-gated MOSFETs provide a gate electrode on both sides of the channel, and the surrounding gate MOSFETs provide a gate that surrounds the channel. When there are two gates or surrounding gates, the electric field generated by the drain electrode is better screened from the source-end of the channel. This results in an improved sub-threshold leakage current characteristic and the MOSFET turns off and the sub-threshold current is reduced more quickly as the gate voltage is reduced. These transistors with thin bodies then serve to improve the sub-threshold characteristics and control sub-threshold leakage. 
     Nanofin Transistors and Methods of Formation 
       FIGS. 6A-6B  illustrate a side view and a cross-section view of along line  6 B- 6 B, respectively, of a vertically-oriented nanofin transistor  611 , according to various embodiments of the present subject matter. In the illustrated nanofin transistor, the vertically-oriented nanofin transistor is positioned over a doped region in a substrate  612  that forms a first source/drain region  613  and associated wiring  614 . A second source/drain region  615  is formed at a top portion of the nanofin  616 , and a contact  617  is formed thereon. A surrounding gate insulator  618  surrounds the nanofin, and a surrounding gate  619  surrounds and is separated from the nanofin by the gate insulator. At least one gate line  620  is positioned adjacent to the surrounding gate. The gate lines can run in the direction of a long side of the nanofin, or can run in the direction of a short side of the nanofin. As illustrated in  FIG. 6A , the width of the drain contact  617  is a minimum feature size (F), and the cross-sectional thickness of the nanofin is substantially less than the minimum feature size. As illustrated in  FIG. 6B , the cross-sectional thickness of the nanofin in a second direction orthogonal to the first direction corresponds to the minimum feature size. 
     U.S. application Ser. No. 11/397,430, filed on Apr. 4, 2006 (U.S. Pub. 20070231985) and U.S. application Ser. No. 11/397,358, filed on Apr. 4, 2006 (U.S. Pub. 20070231980) disclose techniques to fabricate nanofin transistors with reduced volumes and surface areas for the drain region. These reduced volumes and surface areas of silicon for the drain of the transistor result in minimal drain leakage currents and improved retention time of DRAMs. Other expected benefits of the minimal volumes include improved soft error immunity since there is little volume from which to collect charge generated by ionizing radiation, and reduced variable retention times due to defects in the bulk of the wafer. 
       FIGS. 7A-7L  illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter. This process grows a crystalline nanofin from an amorphous structure, as described in U.S. application Ser. No. 11/397,430, filed on Apr. 4, 2006 (U.S. Pub. 20070231985), which has been incorporated by reference in its entirety. 
       FIGS. 7A and 7B  illustrate a top view and a cross-section view along  7 B- 7 B, respectively, of a semiconductor structure  721  with a silicon nitride layer  722 , holes  723  in the silicon nitride layer, and sidewall spacers  724  of amorphous silicon along the walls of the holes. The holes are etched in the silicon nitride layer, and amorphous silicon deposited and directionally etched to leave only on the sidewalls. The holes  723  are etched through the silicon nitride layer  722  to a silicon wafer or substrate  725 . 
       FIGS. 7C and 7D  illustrate a top view and a cross-section view along line  7 D- 7 D, respectively, of the structure after the silicon nitride layer is removed. As illustrated, after the silicon nitride layer is removed, the sidewalls  724  are left as standing narrow regions of amorphous silicon. The resulting patterns of standing silicon can be referred to as “racetrack” patterns, as they have a generally elongated rectangular shape. The width of the lines is determined by the thickness of the amorphous silicon rather than masking and lithography. For example, the thickness of the amorphous silicon may be on the order of 20 nm to 50 nm, according to various embodiments. A solid phase epitaxial (SPE) growth process is used to recrystallize the standing narrow regions of amorphous silicon. The SPE growth process includes annealing, or heat treating, the structure to cause the amorphous silicon to crystallise, beginning at the interface with the silicon substrate  725  which functions as a seed for crystalline growth up through the remaining portions of the standing narrow regions of silicon. 
       FIG. 7E  illustrates a top view of the structure  721 , after a mask layer has been applied. The shaded areas are etched, leaving free-standing fins formed of crystalline silicon.  FIGS. 7F and 7G  illustrate a top view and a cross-section view along line  7 G- 7 G, respectively, of the pattern of free-standing fins  726 . A buried doped region  727  functions as a first source/drain region. According to various embodiments, the buried doped region can be patterned to form a conductive line either the row or column direction of the array of fins. 
       FIG. 7H  illustrates a top view of the structure, where the fins have been surrounded by a gate insulator  728  and a gate  729 . The gate insulator can be deposited or otherwise formed in various ways. For example, a silicon oxide can be formed on the silicon fin by a thermal oxidation process. The gate can be any gate material, such as polysilicon or metal. The gate material is deposited and directionally etched to leave the gate material only on the sidewalls of the fin structure with the gate insulator. The wiring can be oriented in either the “x-direction” or “y-direction.” 
       FIGS. 7I and 7J  illustrate a top view and a cross-section view along line  7 J- 7 J, respectively, of the structure illustrated in  FIG. 7H  after the structure is backfilled with an insulator  730  and gate wiring  731  is formed in an “x-direction” along the long sides of the fins. Various embodiments backfill the structure with silicon oxide. Trenches are formed in the backfilled insulator to pass along a side of the fins, and gate lines are formed in the trenches. In various embodiments, one gate line passes along one side of the fins, in contact with the surrounding gate of the fin structure. Some embodiments provide a first gate line on a first side of the fin and a second gate line on a second side of the fin. The gate wiring material, such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only. The gate wiring material appropriately contacts the surrounding gates for the fins. In various embodiments, the gate material and gate wiring material are etched to recess the gate and gate wiring below the tops of the fins. The whole structure can be backfilled with an insulator, such as silicon oxide, and planarized to leave only oxide on the surface. The top of the pillars or fins can be exposed by an etch. A second source/drain region  732  can be implanted in a top portion of the fins, and metal contacts  733  to the drain regions can be made by conventional techniques. The metal wiring can run, for example, in the “x-direction” and the buried source wiring can run perpendicular, in the plane of the paper in the illustration. 
       FIGS. 7K and 7L  illustrate a top view and a cross-section view along line  7 L- 7 L, respectively, of the structure after the structure is backfilled with an insulator and gate wiring is formed in an “y-direction” along the short sides of the fins. Trenches are opened up along the side of the fins in the “y-direction.” Gate wiring material  731 , such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only and contacting the gates on the fins. In various embodiments, the gate material and gate wiring material are etched to recess the gate and gate wiring below the tops of the fins. The whole structure can be backfilled with an insulator  730 , such as silicon oxide, and planarized to leave only the backfill insulator on the surface. Contact openings and drain doping regions can then be etched to the top of the pillars and drain regions implanted and metal contacts to the drain regions made by conventional techniques. The metal wiring can run, for example, perpendicular to the plane of the paper in the illustration and the buried source wiring runs in the “x-direction.” The buried source/drains are patterned and implanted before deposition of the amorphous silicon.  FIG. 7L  gives an illustration of one of the completed fin structures with drain/source regions, recessed gates, and source/drain region wiring. These nanofin FET&#39;s can have a large W/L ratio and are able to conduct more current than nanowire FET&#39;s. 
       FIGS. 8A-8L  illustrate a process for forming a nanofin transistor, according to various embodiments of the present subject matter. This process etches a crystalline nanofin from a crystalline substrate, as described in U.S. application Ser. No. 11/397,358, filed on Apr. 4, 2006 (U.S. Pub. 20070231980), which has been incorporated by reference in its entirety. 
     According to an embodiment, silicon nitride is deposited on a silicon wafer, and the silicon nitride is covered with a layer of amorphous silicon (α-silicon).  FIG. 8A  illustrates a side view of the structure  841  after holes  842  are defined in the amorphous silicon  843  and sidewall spacers  844  are formed. The holes  842  extend to the silicon nitride layer  845 , which lies over a substrate  846  such as a silicon wafer. Various embodiments form the sidewall spacers by oxidizing the amorphous silicon.  FIG. 8B  illustrates a side view of the structure  841 , after the structure is covered with a thick layer of amorphous silicon  846 .  FIG. 8C  illustrates the structure  841  after the structure is planarized, illustrated by the arrow, at least to a level to remove the oxide on top of the amorphous silicon. The structure can be planarized using a chemical mechanical polishing (CMP) process, for example. This leaves an elongated rectangular pattern, also referred to as a “racetrack” pattern, of oxide  844  exposed on the surface. The width of the pattern lines is determined by the oxide thickness rather than masking and lithography. For example, the oxide thickness can be within a range on the order of 20 nm to 50 nm, according to various embodiments. 
       FIG. 8D  illustrates a mask over the racetrack pattern, which selectively covers portions of the oxide and exposes other portions of the oxide. The exposed oxide portions, illustrated by the shaded strips, are removed. An etch process, such as a potassium hydroxide (KOH) etch, is performed to remove the amorphous silicon. The oxide, or the portions of the oxide remaining after the mask and etch illustrated in  FIG. 8D , protects the nitride during the etch. After the amorphous silicon is removed the nitride  845  can be etched, followed by a directional silicon etch that etches the wafer  846  to a predetermined depth below the nitride layer. The nitride pattern protects the local areas of silicon from the etch, resulting in silicon fins  847  of silicon protruding from the now lower surface of the silicon wafer, as illustrated in  FIG. 8E .  FIGS. 8F and 8G  illustrate top and side views of the structure, after the tops of the fins and trenches at the bottom of the fins are implanted with a dopant. As illustrated in  FIG. 8F , the dopant in the trench forms a conductive line  848  (e.g. source line). The dopant also forms a source/drain region at the bottom or a bottom portion of the fin. Because the fins are extremely thin, the doping in the trench is able to diffuse completely under the fins. The strips can be in either the row or column direction. 
       FIG. 8H  illustrates the structure  841  after a gate insulator  849  has been formed around the fin  847 , and a gate material  850  is formed around and separated from the fin by the gate insulator. For example, an embodiment oxidizes the silicon fins using a thermal oxidation process. The gate material  850  may be polysilicon or metal, according to various embodiments. 
       FIGS. 8I and 8J  illustrate a top view and a cross-section view along line  8 J- 8 J, respectively, of a first array embodiment. The structure  841  is backfilled with an insulator  851  (e.g. oxide) and trenches are created on the sides of the fins. Gate wiring material  852 , such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only and contacting the surrounding gates  850  for the fins. The gate material and gate wiring material can be etched to recess it below the tops of the fins. The whole structure can be again backfilled with oxide and planarized to leave only oxide on the surface. Contact openings and drain doping regions can then be etched to the top of the pillars and drain regions implanted and metal contacts to the drain regions made by conventional techniques. In this case, the metal wiring could run in the “x-direction” and the buried source wiring could run perpendicular to the plane of the paper in the illustration. 
       FIGS. 8K and 8L  illustrate a top view and a cross-section view along  8 L- 8 L, respectively, of a second array embodiment. The structure  841  is backfilled with an insulator  851  (e.g. oxide) and trenches are created along the side of the fins  847 , in the “y-direction”. Gate wiring material  852 , such as polysilicon or metal, can be deposited and directionally etched to leave on the sidewalls only and contacting the gates on the fins. The gate material and gate wiring material can be etched to recess it below the tops of the fins. The whole structure can be backfilled with an insulator (e.g. oxide) and planarized to leave only oxide on the surface. Contact openings and drain doping regions can then be etched to the top of the pillars and drain regions implanted and metal contacts to the drain regions made by conventional techniques. In this case, the metal wiring could run perpendicular to the plane of the paper in the illustration and the buried source wiring could run in the “x-direction”. 
     In both the first and second array embodiments, the buried source/drains can be implanted before the formation of the surrounding gate insulator and surrounding gate.  FIG. 8L  illustrates one of the completed fin structures with drain/source regions  853  and  854 , recessed gates  850 , and source/drain region wiring  848 . These nanofin FET&#39;s can have a large W/L ratio and will conduct more current than nanowire FET&#39;s. 
       FIGS. 9A-9C  illustrate the application of FINFET&#39;s as DRAM access transistors with buried data-bit lines, according to various embodiments of the present subject matter. Word lines  960  are connected to the gates  961  of the nanofin access transistors  962 , and a data-bit line  963  is connected to a first source/drain region  964  (the drain for conventional operating voltages). A second source/drain region  965  (the source for conventional operating voltages) is connected to a stacked capacitor  966 , which is connected to a common potential  967 .  FIG. 9A  illustrates a schematic of an array configuration where the word lines  960  drive the gates  961  on each side of the fin  968 , and the data-bit line  963  is a buried line (e.g. N+ implanted and diffused region) as shown in  FIG. 9B .  FIG. 9C  illustrates the application with a global bit line to reduce data-bit line series resistance, a column is sacrificed and the data-bit line signal brought to the surface under the stacked capacitors and in part over the isolation area as in a conventional stacked capacitor DRAM. The transistors in the column are used to connect the local data-bit line to the metal global data-bit line  969 . 
       FIG. 10A-10B  illustrate side and top views, respectively, of another embodiment in which FINFETs function as DRAM access transistors. Two access transistors  1070  share a first source/drain region  1071  (e.g. shared source) which is contacted by a metal data-bit line  1072  using a contact plug  1073 . This metal data-bit line is on the surface under the stacked capacitors  1074  and over in part the isolation areas. The metal bit lines have a lower series resistance than the buried bit lines  963  shown in  FIGS. 9A-9C . Also illustrated in  FIG. 10B  is a contact area  1075  between the capacitor  1074  and the transistor  1070 . 
     The present subject matter provides DRAM access transistors with ultrathin fin-shaped bodies to minimize sub-threshold leakage and junction leakage, as a result of the extremely small drain regions and surface areas. The small volume reduces soft error rates and variable retention times. Thus, the design of the present subject matter improves DRAM retention time, requires smaller stacked storage capacitors, and reduces the adverse effects of variable retention times. 
       FIG. 11  illustrates a top view of a layout of nanofins for an array of nanofin transistors, according to various embodiments. The figure illustrates two “racetracks” of sidewall spacers  1176 , and further illustrates the portions of the sidewall spacers removed by an etch. The holes used to form the sidewall spacer tracks were formed with a minimum feature size (1F). The mask strips  1177  have a width of a minimum feature size (1F) and are separated by a minimum feature size (1F). In the illustrated layout, the columns of the nanofins have an approximately 2F center-to-center spacing, and the rows of the nanofins have an approximately 1F center-to-center spacing. Also, as illustrated in  FIG. 7 , since the nanofins are formed from sidewall spacers on the walls of the holes, the center-to-center spacing between first and second rows will be slightly less than 1F size by an amount corresponding to the thickness of the nanofins (1F−ΔT), and the center-to-center spacing between second and third rows will be slightly more than 1F by an amount corresponding to the thickness of the nanofins (1F+ΔT). In general, the center-to-center spacing between first and second rows will be slightly less than a feature size interval (NF) by an amount corresponding to the thickness of the nanofins (NF−ΔT), and the center-to-center spacing between second and third rows will be slightly more than a feature size interval (NF) by an amount corresponding to the thickness of the nanofins (NF+ΔT). 
       FIG. 12  illustrates a method for forming a DRAM with a nanofin transistor, according to various embodiments. A nanofin transistor with a vertically-oriented channel is formed at  1278 . The nanofin can be grown from a substrate or etched from the substrate, as provided above. A first source/drain region for the transistor is connected to a bit line at  1279 . Embodiments for connecting the first source/drain region to a bit line are provided in  FIGS. 13-14 . At  1280 , a capacitor plate is formed to contact a second source/drain region at the top of the nanofin transistor. 
       FIG. 13  illustrates one method for connecting a first source/drain region to a bit line, according to various embodiments. The bit line is a doped line in the substrate. The substrate is doped to form a buried data-bit line that passes underneath the nanofin transistor at  1381 . The nanofin is thin, allowing the dopant to diffuse completely underneath the transistor. At  1382 , a contact to the data-bit line is formed. 
       FIG. 14  illustrates another method for connecting a first source/drain region to a bit line, according to various embodiments. A metal bit line is formed over a substrate. At  1483 , a doped region is formed in a substrate. The doped region extends from beneath the nanofin transistor to a contact area. At  1484 , a contact plug is formed that extends from the substrate at the contact area. At  1485 , a data-bit line is formed over the substrate, and the data-bit line is connected to the contact plug. 
       FIG. 15  is a simplified block diagram of a high-level organization of various embodiments of a memory device according to various embodiments of the present subject matter. The illustrated memory device  1586  includes a memory array  1587  and read/write control circuitry  1588  to perform operations on the memory array via communication line(s) or channel(s)  1589 . The illustrated memory device  1586  may be a memory card or a memory module such as a single inline memory module (SIMM) and dual inline memory module (DIMM). One of ordinary skill in the art will understand, upon reading and comprehending this disclosure, that the memory device can include the DRAM with nanofin transistors, as described above. 
     The memory array  1587  includes a number of memory cells  1590 . The memory cells in the array are arranged in rows and columns. In various embodiments, word lines  1591  connect the memory cells in the rows, and bit lines  1592  connect the memory cells in the columns. The read/write control circuitry  1588  includes word line select circuitry  1593  which functions to select a desired row, bit line select circuitry  1594  which functions to select a desired column, and read circuitry  1595  which functions to detect a memory state for a selected memory cell in the memory array  1587 . 
       FIG. 16  illustrates a diagram for an electronic system  1696  having a DRAM with nanofin transistors, according to various embodiments. Electronic system  1696  includes a controller  1697 , a bus  1698 , and an electronic device  1699 , where the bus  1698  provides communication channels between the controller  1697  and the electronic device  1699 . The illustrated electronic system  1696  may include, but is not limited to, information handling devices, wireless systems, telecommunication systems, fiber optic systems, electro-optic systems, and computers. 
       FIG. 17  depicts a diagram of an embodiment of a system  1701  having a controller  1702  and a memory  1703 . The system  1701  may include a DRAM with nanofin transistors according to various embodiments. The illustrated system  1701  also includes an electronic apparatus  1704  and a bus  1705  to provide communication channel(s) between the controller and the electronic apparatus, and between the controller and the memory. The bus may include an address, a data bus, and a control bus, each independently configured; or may use common communication channels to provide address, data, and/or control, the use of which is regulated by the controller. In an embodiment, the electronic apparatus  1701  may be additional memory configured similar to memory  1703 . An embodiment may include a peripheral device or devices  1706  coupled to the bus  1705 . Peripheral devices may include displays, additional storage memory, or other control devices that may operate in conjunction with the controller and/or the memory. In an embodiment, the controller is a processor. The system  1701  may include, but is not limited to, information handling devices, telecommunication systems, and computers. Such circuitry can further be a subcomponent of a variety of electronic systems, such as a clock, a television, a cell phone, a personal computer, an automobile, an industrial control system, an aircraft, and others. 
     This disclosure includes several processes, circuit diagrams, and cell structures. The present subject matter is not limited to a particular process order or logical arrangement. Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that any arrangement which is calculated to achieve the same purpose may be substituted for the specific embodiments shown. This application is intended to cover adaptations or variations of the present subject matter. It is to be understood that the above description is intended to be illustrative, and not restrictive. Combinations of the above embodiments, and other embodiments, will be apparent to those of skill in the art upon reviewing the above description. The scope of the present subject matter should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.