Patent Publication Number: US-7592659-B2

Title: Field effect transistor and an operation method of the field effect transistor

Description:
This application is based on an application No. 2005-58797 filed in Japan, the contents of which are hereby incorporated by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a field effect transistor having a variable gate capacitance and an operation method of the field effect transistor, and in particular relates to techniques for reduction in power consumption and reading error of the field effect transistor. 
     2. Related Art 
     A CMR (colossal magnetoresistive) material having a perovskite structure changes its properties according to external effects. For example, when a voltage pulse of an appropriate field intensity is applied at least once to a construction in which a thin film or bulk film of Pr 0.7 Ca 0.3 MnO 3  (hereafter simply referred to as “PCMO”) is sandwiched between two electrodes, the PCMO film changes its properties. The properties that can change according to external effects include an electrical resistance (resistivity) and a capacitance (relative permittivity). These properties show different changes depending on a polarity of the voltage pulse applied. Once changed, the properties are stably maintained even after the application of the voltage pulse ends. 
     Taking advantage of this feature, a device that uses a PCMO film as a variable capacitance film is conventionally developed (see U.S. Patent Application Publication No. US 2004/0065912 A1).  FIG. 1  is a sectional view showing a construction of such a device that uses a PCMO film as a variable capacitance film. In the drawing, a device  3  is formed by disposing an electrode  302 , a PCMO film  303 , and an electrode  304  on a substrate  301  in this order. The electrodes  302  and  304  are connected respectively with wires  302   a  and  304   a . The electrode  304  has a circular main surface with a radius of 0.4 mm, and the PCMO film  303  has a film thickness of 600 nm. 
     When a voltage pulse of 18 V or −18 V is applied to the PCMO film  303  via the wires  302   a  and  304   a , the PCMO film  303  changes in relative permittivity and electrical resistance.  FIGS. 2A and 2B  are graphs showing how these properties of the PCMO film  303  change upon repeated application of the voltage pulse. In detail,  FIG. 2A  shows changes in relative permittivity, whereas  FIG. 2B  shows changes in electrical resistance. In  FIGS. 2A and 2B , the vertical axes respectively represent the relative permittivity and the electrical resistance, and the horizontal axes both represent time. 
     As shown in  FIG. 2A , the relative permittivity of the PCMO film  303  changes to 405 upon application of a voltage pulse of −18 V, and changes to 135 upon application of a voltage pulse of 18 V. Also, as shown in  FIG. 2B , the electrical resistance of the PCMO film  303  changes to 3500 Ω upon application of a voltage pulse of −18 V, and changes to 200 Ω upon application of a voltage pulse of 18 V. Once changed, the relative permittivity of the PCMO film  303  is maintained stably for at least three years. Hence a nonvolatile memory can be realized by relating the high and low levels in relative permittivity of the PCMO film  303  to the two binary states 0 and 1. 
     To change a relative permittivity of a PCMO film, in general it is necessary to apply a voltage pulse of at least several V to the PCMO film, though this varies depending on film thickness. To detect the relative permittivity of the PCMO film, on the other hand, it is sufficient to apply a voltage pulse of about 0.1 V to the PCMO film so as to detect a current. Thus, in the case where the PCMO film is used as a nonvolatile memory, writing data requires largest power. 
     In the above device  3 , an area of the main surface of the electrode  304  is about 0.5 mm 2 , and the electrical resistance of the PCMO film  303  in a low resistance state is about 200 Ω. Accordingly, when a voltage pulse of 18 V is applied, a current of 90 mA flows, and 1.6 W of power is consumed. If the area of the main surface of the electrode  304  is reduced to 0.64 μm 2  (0.8 μm×0.8 μm), the electrical resistance of the PCMO film  303  in a low resistance state is 25 KΩ. This being the case, when a voltage pulse of 5 V is applied, a current of 200 μA flows, and the power consumption can be reduced to 1 mW (see Technical Digest of IEEE International Electron Device Meeting (2002), p. 193). 
     However, when compared with a volatile memory such as an SRAM (static random access memory) whose power consumption is about 1 μW, the device  3  using the PCMO film still has an extremely high power consumption, and is unsuitable for practical use. 
     SUMMARY OF THE INVENTION 
     The present invention was conceived in view of the above problems, and aims to provide a nonvolatile memory with a lower power consumption and fewer reading errors. 
     The stated aim can be achieved by a field effect transistor including: a semiconductor substrate; a gate electrode; and a gate insulator provided between the semiconductor substrate and the gate electrode, and having a capacitance that changes according to an applied voltage. 
     According to this construction, the threshold voltage can be changed by changing the capacitance of the gate insulator. As a result, the capacitance of the gate insulator can be detected based on whether or not a drain current flows upon application of an appropriate voltage to the gate insulator. This allows the field effect transistor to be used as a memory. In such a memory, a capacitance change of the gate insulator can be detected based on whether or not a drain current flows, so that data reading can be performed with high sensitivity. 
     Here, the gate insulator may include a variable capacitance film which is made of any of a colossal magnetoresistive material and a transition metal oxide. 
     Here, the colossal magnetoresistive material may be Pr X Ca 1−X MnO 3  where 0&lt;X&lt;1. 
     According to these constructions, the capacitance of the variable capacitance film changes when a voltage is applied to the gate electrode. As a result, the capacitance of the gate insulator can take two or more values. Once changed, the capacitance of the variable capacitance film which is made of a colossal magnetoresistive material or a high-temperature superconducting material is maintained stably, so that the field effect transistor is suitable as a nonvolatile memory. 
     Here, the gate insulator may further include an insulator film which is positioned between the semiconductor substrate and the variable capacitance film. 
     According to this construction, the capacitance of the variable capacitance film can be changed without a current flow to the variable capacitance film. This contributes to a lower power consumption. 
     Here, the gate insulator may further include a conductor film which is positioned between the insulator film and the variable capacitance film. 
     According to this construction, an effective area of the insulator film and an effective area of the variable capacitance film can be designed independently of each other. 
     Here, a contact area between the gate electrode and the variable capacitance film may be smaller than a contact area between the conductor film and the insulator film. 
     According to this construction, a voltage necessary for changing the capacitance of the variable capacitance film can be reduced. Also, an amount of change of the threshold voltage according to the capacitance of the variable capacitance film can be increased, with it being possible to increase a read voltage margin and thereby improve data reading sensitivity. 
     Here, the capacitance of the gate insulator may change according to at least one of a voltage level, a pulse width, and a number of applications of a voltage pulse applied to the gate insulator. 
     The stated aim can also be achieved by an operation method of a field effect transistor in which a gate insulator and a gate electrode are provided on a semiconductor substrate in the stated order, the gate insulator having a capacitance that changes according to an applied voltage, including steps of: applying an intermediate voltage between two threshold voltages corresponding to two capacitances, to the gate electrode as a read voltage; and detecting whether a drain current flows as a result of the application of the read voltage. 
     According to this method, the drain current is detected with high sensitivity, with it being possible to reduce reading errors. 
     Here, the read voltage may be below a voltage necessary for changing the capacitance of the gate insulator. 
     According to this method, the capacitance of the gate insulator will not be changed by data reading, so that data can be read without destroying stored data. This enhances memory reliability. 
     The stated aim can also be achieved by an operation method of a field effect transistor in which a gate insulator and a gate electrode are provided on a semiconductor substrate in the stated order, including a step of changing a capacitance of the gate insulator by changing at least one of a voltage level, a pulse-width, and a number of applications of a voltage pulse applied to the gate insulator. 
     According to this method, the capacitance of the variable capacitance film can be changed easily. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       These and other objects, advantages and features of the invention will become apparent from the following description thereof taken in conjunction with the accompanying drawings which illustrate a specific embodiment of the invention. 
       In the drawings: 
         FIG. 1  is a sectional view showing a construction of a conventional device that uses a PCMO film as a variable capacitance film; 
         FIGS. 2A and 2B  are graphs showing changes in property of the PCMO film shown in  FIG. 1  when a voltage pulse is repeatedly applied; 
         FIG. 3  is a sectional view showing a main part of a field effect transistor to which a first embodiment of the present invention relates; and 
         FIG. 4  is a sectional view showing a main part of a field effect transistor to which a second embodiment of the present invention relates. 
     
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENT(S) 
     The following describes embodiments of a field effect transistor and its operation method according to the present invention, with reference to drawings. 
     First Embodiment 
     A field effect transistor to which a first embodiment of the present invention relates is described below. 
     &lt;Construction of the Field Effect Transistor&gt; 
       FIG. 3  is a sectional view showing a main part of the field effect transistor of the first embodiment. In the drawing, a field effect transistor  1  includes a silicon substrate  101 , a gate insulator  102 , a gate electrode  103 , a source electrode  104 , and a drain electrode  105 . The gate insulator  102  is composed of an insulator film  102   a  and a PCMO film  102   b.    
     The silicon substrate  101  is a p-type silicon substrate, and has acceptor concentration N A  of 1×10 22  m −3 . The source electrode  104  and the drain electrode  105  are n-type silicon layers formed in upper portions of the silicon substrate  101 . The gate insulator  102  and the gate electrode  103  are disposed in this order on part of the silicon substrate  101  between the source electrode  104  and the drain electrode  105 . The gate electrode  103  is made of platinum (Pt), and has a gate length of 0.18 μm. 
     In the gate insulator  102 , the insulator film  102   a  is made of amorphous hafnium oxide (HfO 2 ), and has film thickness d I  of 7.5 nm and relative permittivity ∈ I  of 25. Meanwhile, the PCMO film  102   b  has film thickness d P  of 100 nm, and relative permittivity ∈ P  which, in the case where a frequency of a voltage pulse is no more than several tens of kHz, takes one of the two values 135 and 405. Area S I  of a main surface of the insulator film  102   a  is equal to area S P  of a main surface of the PCMO film  102   b.    
     &lt;Operation Method&gt; 
     An operation method of the field effect transistor  1  is explained below. 
     (1 ) Data Writing 
     (a) Write Voltage 
     A write voltage necessary for changing relative permittivity ∈ P  of the PCMO film  102   b  in the field effect transistor  1  is explained first. 
     According to U.S. Patent Application Publication No. US 2004/0065912 A1, a voltage pulse necessary for changing a relative permittivity of a PCMO film having a film thickness of 600 nm is 18 V, which is 3×10 7  V/m in field intensity. If a field intensity necessary for changing a relative permittivity is fixed, then relative permittivity ∈ P  of the PCMO film  102   b  having film thickness d P  of 100 nm changes with a voltage pulse of 3 V. 
     Here, suppose the gate insulator  102  is a series capacitor circuit composed of the insulator film  102   a  and the PCMO film  102   b . This being the case, write voltage V W  applied to the gate electrode  103  is divided by the insulator film  102   a  and the PCMO film  102   b . Resulting voltage V P of the PCMO film  102   b  is expressed by equation (1): 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       
                           
                       
                       ⁢ 
                       P 
                     
                   
                   = 
                   
                     
                       
                         
                             
                         
                         ⁢ 
                         
                           C 
                           
                             
                                 
                             
                             ⁢ 
                             I 
                           
                         
                       
                       
                         
                             
                         
                         ⁢ 
                         
                           
                             C 
                             
                               
                                   
                               
                               ⁢ 
                               I 
                             
                           
                           ⁢ 
                           
                               
                           
                           + 
                           
                               
                           
                           ⁢ 
                           
                             C 
                             
                               
                                   
                               
                               ⁢ 
                               P 
                             
                           
                         
                       
                     
                     × 
                     
                       V 
                       
                         
                             
                         
                         ⁢ 
                         W 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     where C I  and C P  respectively denote capacitances of the insulator film  102   a  and the PCMO film  102   b . C I  and C P  are respectively given by equations (2) and (3): 
     
       
         
           
             
               
                 
                   
                     C 
                     I 
                   
                   = 
                   
                     
                       ɛ 
                       I 
                     
                     ⁢ 
                     
                       ɛ 
                       0 
                     
                     ⁢ 
                     
                       
                         S 
                         I 
                       
                       
                         d 
                         I 
                       
                     
                   
                 
               
               
                 
                   ( 
                   2 
                   ) 
                 
               
             
             
               
                 
                   
                     C 
                     P 
                   
                   = 
                   
                     
                       ɛ 
                       P 
                     
                     ⁢ 
                     
                       ɛ 
                       0 
                     
                     ⁢ 
                     
                       
                         S 
                         P 
                       
                       
                         d 
                         P 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
     where ∈ 0  denotes a vacuum permittivity. 
     Capacitance C P  of the PCMO film  102   b  takes one of two large and small values according to relative permittivity ∈ P . When capacitance C P  is large, voltage V P  of the PCMO film  102   b  is smallest. Accordingly, by setting voltage V P  of the PCMO film  102   b  when capacitance C P  is large to 3 V, relative permittivity ∈ P  can be changed regardless of the magnitude of capacitance C P . To set voltage V P  of the PCMO film  102   b  when capacitance C P  is large to 3 V, write voltage V W  is set to 7 V. 
     In this case, however, a voltage of 4 V is applied to the insulator film  102   a , which may cause a leakage current increase and a dielectric breakdown. Therefore, if it is possible to change relative permittivity ∈ P  of the PCMO film  102   b  with a write voltage V W  less than 7 V, then such a write voltage V W  is more desirable. 
     Here, a pulse width of the voltage pulse may be 100 ns, and a number of applications of the voltage pulse may be 2. 
     (b) Threshold Voltage 
     Threshold voltage V th  of the field effect transistor  1  is explained next. Threshold voltage V th  is expressed by equation (4): 
     
       
         
           
             
               
                 
                   
                     V 
                     th 
                   
                   = 
                   
                     
                       2 
                       ⁢ 
                       
                         Φ 
                         F 
                       
                     
                     + 
                     
                       q 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         
                           N 
                           A 
                         
                         
                           C 
                           OX 
                         
                       
                       ⁢ 
                       
                         l 
                         Dm 
                       
                     
                     + 
                     
                       Φ 
                       D 
                     
                     - 
                     
                       q 
                       ⁢ 
                       
                         
                           N 
                           SS 
                         
                         
                           C 
                           OX 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     where  denotes an elementary charge, l DM  denotes a maximum depletion layer thickness, Φ F  denotes a Fermi level of the silicon substrate  101 , C OX  denotes a capacitance of the gate insulator  102 , Φ D  denotes a work function difference between the gate electrode  103  and the silicon substrate  101 , and N SS  denotes an interface state density between the gate insulator  102  and the silicon substrate  101 . Meanwhile, N A  is the acceptor concentration of the silicon substrate  101 , as mentioned earlier. Maximum depletion layer thickness l DM  and Fermi level Φ F  of the silicon substrate  101  are respectively given by equations (5) and (6): 
     
       
         
           
             
               
                 
                   
                     l 
                     Dm 
                   
                   = 
                   
                     
                       
                         4 
                         ⁢ 
                         
                           ɛ 
                           Si 
                         
                         ⁢ 
                         
                           ɛ 
                           0 
                         
                         ⁢ 
                         
                           Φ 
                           F 
                         
                       
                       
                         q 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         
                           N 
                           A 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   5 
                   ) 
                 
               
             
             
               
                 
                   
                     Φ 
                     F 
                   
                   = 
                   
                     
                       k 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       T 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       
                         ln 
                         ⁡ 
                         
                           ( 
                           
                             
                               N 
                               A 
                             
                             / 
                             
                               n 
                               i 
                             
                           
                           ) 
                         
                       
                     
                     q 
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     where ∈ Si  denotes a relative permittivity of silicon, k denotes a Boltzmann constant, T denotes an absolute temperature (K), ln denotes a natural logarithm, and n i  denotes an intrinsic Fermi level of silicon. 
     In this embodiment, interface state density N SS  is set to 5×10 14  (m −2 ). Work functions of platinum and silicon are respectively 5.2 and 4.95, so that Φ D =0.25. 
     Capacitance C OX  of the gate insulator  102  is a series combined capacitance of the insulator film  102   a  and the PCMO film  102   b , and is given by equation (7): 
     
       
         
           
             
               
                 
                   
                     C 
                     OX 
                   
                   = 
                   
                     
                       
                         C 
                         I 
                       
                       ⁢ 
                       
                         C 
                         P 
                       
                     
                     
                       
                         C 
                         I 
                       
                       + 
                       
                         C 
                         P 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
           
         
       
     
     Substituting equations (2), (3), (5), (6), and (7) into equation (4) and calculating based on the above parameter values yields the following. When relative permittivity ∈ P  of the PCMO film  102   b  is 135, threshold voltage V th  is 1.25 V. When relative permittivity ∈ P  of the PCMO film  102   b  is 405, threshold voltage V th  is 1.68 V. A difference between the two threshold voltages is 0.43 V. 
     Thus, the field effect transistor  1  can take the two threshold voltages. Since relative permittivity ∈ P  of the PCMO film  102   b  is maintained stably as mentioned above, threshold voltage V th  is maintained stably, too. This being so, a nonvolatile memory can be realized by relating the two threshold voltages to the two binary states 0 and 1. 
     (2) Reading Data 
     To read data from the field effect transistor  1 , an intermediate voltage between the two threshold voltages is applied to the gate electrode  103 , as one example. If threshold voltage V th  of the field effect transistor  1  is large, no drain current flows when the intermediate voltage is applied. If threshold-voltage V th  of the field effect transistor  1  is small, on the other hand, a drain current flows when the intermediate voltage is applied. Hence data reading can be performed based on whether or not a drain current flows. 
     The read voltage used here is smaller than the aforementioned write voltage, and therefore there is no possibility of erroneously rewriting data at the time of data reading. In this sense, the field effect transistor  1  has an excellent operational reliability as a nonvolatile memory. 
     Also, while the change in relative permittivity of the PCMO film  102   b  upon application of the write voltage is in a relatively small range of about three times, the change in drain current is in a range of ten to more than hundred or thousand times. In this sense, the field effect transistor  1  has high data reading sensitivity. 
     Also, the field effect transistor  1  is expected to be reduced in size according to a scaling law (Moore&#39;s law), which contributes to a higher packing density. Hence a large-capacity nonvolatile memory can be achieved using the field effect transistor  1 . 
     Also, the field effect transistor  1  can be manufactured by simply adding a step of forming the PCMO film  102   b  on the insulator film  102   a , to a manufacturing process of a typical MOS (metal oxide semiconductor) field effect transistor whose gate insulator does not include the PCMO film  102   b . Thus, the field effect transistor  1  can be manufactured easily, with there being no need to perform any special step. 
     Second Embodiment 
     A field effect transistor to which a second embodiment of the present invention relates is described below. The field effect transistor of the second embodiment has a similar construction to the field effect transistor of the first embodiment, but differs in the structure of the gate insulator. The following mainly focuses on this difference. 
     &lt;Construction of the Field Effect Transistor&gt; 
       FIG. 4  is a sectional view showing a main part of the field effect transistor of the second embodiment. In the drawing, a field effect transistor  2  includes a silicon substrate  201 , a gate insulator  202 , a gate electrode  203 , a source electrode  204 , and a drain electrode  205 . 
     The gate insulator  202  is composed of an insulator film  202   a , a floating gate  202   b , and a PCMO film  202   c  which are disposed in this order on the silicon substrate  201 . In more detail, the insulator film  202   a  is formed on part of the silicon substrate  201  between the source electrode  204  and the drain electrode  205 , in the same way as the insulator film  102   a  in the first embodiment. The insulator film  202   a  is made of amorphous hafnium oxide, and has film thickness d I  of 7.5 nm and relative permittivity ∈ I  of 25, as in the first embodiment. 
     The floating gate  202   b  is a conductor film made of polysilicon, and has a film thickness of 50 nm. The PCMO film  202   c  has film thickness d P  of 100 nm, and relative permittivity ∈ P  which, in the case where a frequency of a voltage pulse is no more than several tens of kHz, takes one of the two values 135 and 405. An area of a main surface of the insulator film  202   a  is different from an area of a main surface of the PCMO film  202   c.    
     In the first embodiment, the area of the main surface of the insulator film  102   a  is equal to the area of the main surface of the PCMO film  102   b . In the second embodiment, on the other hand, the floating gate  202   b  is provided to enable effective area S I  of the insulator film  202   a  and effective area S P  of the PCMO film  202   c  to be designed independently of each other. By doing so, the write voltage can be reduced and the amount of change in threshold voltage can be increased. As a result, a margin of the read voltage can be increased, with it being possible to perform data reading with higher sensitivity. 
     Suppose effective area S I  of the insulator film  202   a , i.e. a contact area between the floating gate  202   b  and the insulator film  202   a , is about twice as large as effective area S P  of the PCMO film  202   c , i.e. a contact area between the gate electrode  203  and the PCMO film  202   c . In this case, a write voltage necessary for the field effect transistor  2  is 5 V. Thus, the write voltage can be reduced when compared with the first embodiment. As a result, the field effect transistor  2  can operate with smaller power. 
     Also, threshold voltage V th  is 1.46 V when relative permittivity ∈ P  of the PCMO film  202   c  is 135, and 2.33 V when relative permittivity ∈ P  of the PCMO film  202   c  is 405. A difference between these two threshold voltages is 0.87 V, which is greater than the threshold voltage difference 0.43 V in the first embodiment. Accordingly, data reading can be performed more stably. 
     Modifications 
     Although the present invention has been described by way of the above embodiments, it should be obvious that the present invention is not limited to the above. Example modifications are given below. 
     (1) The above embodiments describe the case where a Pr 0.7 Ca 0.3 MnO 3  film is used as a variable capacitance film that varies in capacitance according to a voltage pulse, but this is not a limit for the present invention. 
     For example, other Pr X Ca 1−X MnO 3  films with X not being limited to 0.7 may be used. Also, other CMR materials such as La X Ca 1−X MnO 3 , or other transition metal oxides such as Cr-doped SrTiO 3  or NiOx may be used. The effects of the present invention can still be achieved through the use of these materials. 
     (2) The above embodiments describe the case where hafnium oxide is used as an insulator film, but this is not a limit for the present invention. For example, zirconium oxide (ZrO 2 ) or hafnium aluminum oxide (HfO 2 /Al 2 O 3 ) may equally be used. 
     (3) The above embodiments describe the case where the relative permittivity of the PCMO film is changed by changing the voltage level of the voltage pulse applied to the PCMO film, but the present invention is not limited to this. For instance, the effects of the present invention can still be achieved by changing the pulse width or the number of applications of the voltage pulse instead of the voltage level. 
     (4) The above embodiments describe the case where the voltage level of the voltage pulse is determined so that the relative permittivity of the PCMO film can take two values, but the voltage level, the pulse width, or the number of applications of the voltage pulse may be determined so that the relative permittivity of the PCMO film can take three or more values. This enables the field effect transistor to store a greater amount of information. 
     Although the present invention has been fully described by way of examples with reference to the accompanying drawings, it is to be noted that various changes and modifications will be apparent to those skilled in the art. 
     Therefore, unless such changes and modifications depart from the scope of the present invention, they should be construed as being included therein.