Patent Publication Number: US-2020287056-A1

Title: Radical oxidation process for fabricating a nonvolatile charge trap memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. patent application Ser. No. 14/605,231, filed Jan. 26, 2015, which is a continuation of U.S. patent application Ser. No. 13/539,458, filed Jul. 1, 2012, now U.S. Pat. No. 8,940,645, issued Jan. 27, 2015, which is a continuation-in-part of U.S. patent application Ser. No. 12/197,466, filed Aug. 25, 2008, now U.S. Pat. No. 8,318,608, issued Nov. 27, 2012, which is a continuation of U.S. patent application Ser. No. 12/124,855, filed May 21, 2008, now U.S. Pat. No. 8,283,261, issued Oct. 9, 2012, which claims the benefit of priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application Ser. No. 60/940,139, filed May 25, 2007, and U.S. Provisional Application No. 60/986,637, filed Nov. 9, 2007, all of which are incorporated by reference herein in their entirety. 
    
    
     TECHNICAL FIELD 
     Embodiments of the present invention are in the field of Semiconductor Fabrication and, in particular, Semiconductor Device Fabrication. 
     BACKGROUND 
     For the past several decades, the scaling of features in integrated circuits has been a driving force behind an ever-growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited real estate of semiconductor chips. For example, shrinking transistor size allows for the incorporation of an increased number of memory devices on a chip, lending to the fabrication of products with increased capacity. The drive for ever-more capacity, however, is not without issue. The necessity to optimize the performance of each device becomes increasingly significant. 
     Non-volatile semiconductor memories typically use stacked floating gate type field-effect-transistors. In such transistors, electrons are injected into a floating gate of a memory cell to be programmed by biasing a control gate and grounding a body region of a substrate on which the memory cell is formed. An oxide-nitride-oxide (ONO) stack is used as either a charge storing layer, as in a semiconductor-oxide-nitride-oxide-semiconductor (SONOS) transistor, or as an isolation layer between the floating gate and control gate, as in a split gate flash transistor.  FIG. 1  illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device. 
     Referring to  FIG. 1 , semiconductor device  100  includes a SONOS gate stack  104  including a conventional ONO portion  106  formed over a silicon substrate  102 . Semiconductor device  100  further includes source and drain regions  110  on either side of SONOS gate stack  104  to define a channel region  112 . SONOS gate stack  104  includes a poly-silicon gate layer  108  formed above and in contact with ONO portion  106 . Polysilicon gate layer  108  is electrically isolated from silicon substrate  102  by ONO portion  106 . ONO portion  106  typically includes a tunnel oxide layer  106 A, a nitride or oxynitride charge-trapping layer  106 B, and a top oxide layer  106 C overlying nitride or oxynitride layer  106 B. 
     One problem with conventional SONOS transistors is the poor data retention in the nitride or oxy-nitride layer  106 B that limits semiconductor device  100  lifetime and its use in several applications due to leakage current through the layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention are illustrated by way of example, and not limitation, in the figures of the accompanying drawings in which: 
         FIG. 1  illustrates a cross-sectional view of a conventional nonvolatile charge trap memory device. 
         FIG. 2  illustrates a cross-sectional view of an oxidation chamber of a batch-processing tool, in accordance with an embodiment of the present invention. 
         FIG. 3  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 4A  illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon, corresponding to operation  302  from the Flowchart of  FIG. 3 , in accordance with an embodiment of the present invention. 
         FIG. 4B  illustrates a cross-sectional view of a substrate having a charge trapping layer with a blocking dielectric layer formed thereon, corresponding to operation  304  from the Flowchart of  FIG. 3 , in accordance with an embodiment of the present invention. 
         FIG. 5  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 6A  illustrates a cross-sectional view of a substrate, corresponding to operation  502  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. 
         FIG. 6B  illustrates a cross-sectional view of a substrate having a first dielectric layer formed thereon, corresponding to operation  504  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. 
         FIG. 6C  illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon, corresponding to operation  508  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. 
         FIG. 6D  illustrates a cross-sectional view of a substrate having a charge trapping layer with a blocking dielectric layer formed thereon, corresponding to operation  510  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. 
         FIG. 6E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 7  A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention. 
         FIG. 7B  illustrates a cross-sectional view of the substrate including first and second crystal planes and having a dielectric layer formed thereon, in accordance with an embodiment of the present invention. 
         FIG. 8  illustrates an arrangement of process chambers in a cluster tool, in accordance with an embodiment of the present invention. 
         FIG. 9  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 10A  illustrates a cross-sectional view of a substrate, in accordance with an embodiment of the present invention. 
         FIG. 10B  illustrates a cross-sectional view of a substrate having a tunnel dielectric layer formed thereon, corresponding to operation  402  from the Flowchart of  FIG. 4 , in accordance with an embodiment of the present invention. 
         FIG. 10C  illustrates a cross-sectional view of a substrate having a charge-trapping layer formed thereon, corresponding to operation  406  from the Flowchart of  FIG. 4 , in accordance with an embodiment of the present invention. 
         FIG. 10D  illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon, corresponding to operation  408  from the Flowchart of  FIG. 4 , in accordance with an embodiment of the present invention. 
         FIG. 10E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 11  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 12A  illustrates a cross-sectional view of a substrate having a tunnel dielectric layer formed thereon, corresponding to operation  602  from the Flowchart of  FIG. 6 , in accordance with an embodiment of the present invention. 
         FIG. 12B  illustrates a cross-sectional view of a substrate having an oxygen-rich silicon oxy-nitride portion of a charge-trapping layer formed thereon, corresponding to operation  606  from the Flowchart of  FIG. 6 , in accordance with an embodiment of the present invention. 
         FIG. 12C  illustrates a cross-sectional view of a substrate having a silicon-rich silicon oxy-nitride portion of a charge-trapping layer formed thereon, corresponding to operation  610  from the Flowchart of  FIG. 6 , in accordance with an embodiment of the present invention. 
         FIG. 12D  illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon, corresponding to operation  612  from the Flowchart of  FIG. 6 , in accordance with an embodiment of the present invention. 
         FIG. 12E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
         FIG. 13A  illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention. 
         FIG. 13B  illustrates a cross-sectional view of the substrate including first and second crystal planes and having a dielectric layer formed thereon, in accordance with an embodiment of the present invention. 
         FIG. 14  illustrates a cross-sectional view of a nonvolatile charge trap memory device including an ONONO stack. 
         FIG. 15  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device including an ONONO stack, in accordance with an embodiment of the present invention. 
         FIG. 16A  illustrates a non-planar multigate device including a split charge-trapping region. 
         FIG. 16B  illustrates a cross-sectional view of the non-planar multigate device of  FIG. 16A . 
         FIGS. 17A and 17B  illustrate a non-planar multigate device including a split charge-trapping region and a horizontal nanowire channel. 
         FIG. 17C  illustrates a cross-sectional view of a vertical string of non-planar multigate devices of  FIG. 17A . 
         FIGS. 18A and 18B  illustrate a non-planar multigate device including a split charge-trapping region and a vertical nanowire channel. 
         FIG. 19A through 19F  illustrate a gate first scheme for fabricating the non-planar multigate device of  FIG. 18A . 
         FIG. 20A through 20F  illustrate a gate last scheme for fabricating the non-planar multigate device of  FIG. 18A . 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of a non-volatile charge trap memory device integrated with logic devices are described herein with reference to figures. However, particular embodiments may be practiced without one or more of these specific details, or in combination with other known methods, materials, and apparatuses. In the following description, numerous specific details are set forth, such as specific materials, dimensions and processes parameters etc. to provide a thorough understanding of the present invention. In other instances, well-known semiconductor design and fabrication techniques have not been described in particular detail to avoid unnecessarily obscuring the present invention. Reference throughout this specification to “an embodiment” means that a particular feature, structure, material, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in an embodiment” in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments. 
     Methods to fabricate a nonvolatile charge trap memory device are described herein. In the following description, numerous specific details are set forth, such as specific dimensions, in order to provide a thorough understanding of the present invention. It will be apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known processing steps, such as patterning steps or wet chemical cleans, are not described in detail in order to not unnecessarily obscure the present invention. Furthermore, it is to be understood that the various embodiments shown in the Figures are illustrative representations and are not necessarily drawn to scale. 
     Disclosed herein is a method to fabricate a nonvolatile charge trap memory device. A substrate may first be provided having a charge-trapping layer disposed thereon. In one embodiment, a portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process. 
     Formation of a dielectric layer by a radical oxidation process may provide higher quality films than processes involving steam growth, i.e. wet growth processes. Furthermore, a radical oxidation process carried out in a batch-processing chamber may provide high quality films without impacting the throughput (wafers/Hr) requirements that a fabrication facility may require. By carrying out the radical oxidation process at temperatures compatible with such a chamber, such as temperatures approximately in the range of 600-900 degrees Celsius, the thermal budget tolerated by the substrate and any other features on the substrate may not be impacted to the extent typical of processes over 1000 degrees Celsius. In accordance with an embodiment of the present invention, a radical oxidation process involving flowing hydrogen (H2) and oxygen (02) gas into a batch-processing chamber is carried out to effect growth of a dielectric layer by oxidation consumption of an exposed substrate or film. In one embodiment, multiple radical oxidation processes are carried out to provide a tunnel dielectric layer and a blocking dielectric layer for a non-volatile charge trap memory device. These dielectric layers may be of very high quality, even at a reduced thickness. In one embodiment, the tunnel dielectric layer and the blocking dielectric layer are both denser and are composed of substantially fewer hydrogen atoms/cm3 than a tunnel dielectric layer or a blocking dielectric layer formed by wet oxidation techniques. In accordance with another embodiment of the present invention, a dielectric layer formed by carrying out a radical oxidation process is less susceptible to crystal plane orientation differences in the substrate from which it is grown. In one embodiment, the cornering effect caused by differential crystal plane oxidation rates is significantly reduced by forming a dielectric layer via a radical oxidation process. 
     A portion of a nonvolatile charge trap memory device may be fabricated by carrying out a radical oxidation process in a process chamber. In accordance with an embodiment of the present invention, the process chamber is a batch-processing chamber.  FIG. 2  illustrates a cross-sectional view of an oxidation chamber of a batch-processing tool, in accordance with that embodiment. Referring to  FIG. 2 , a batch-processing chamber  200  includes a carrier apparatus  204  to hold a plurality of semiconductor wafers  202 . In one embodiment, the batch-processing chamber is an oxidation chamber. In a specific embodiment, the process chamber is a low-pressure chemical vapor deposition chamber. The plurality of semiconductor wafers  202  may be arranged in such a way as to maximize exposure of each wafer to a radical oxidation process, while enabling the inclusion of a reasonable number of wafers (e.g. 25 wafers), to be processed in a single pass. It should be understood, however, that the present invention is not limited to a batch-processing chamber. 
     In an aspect of the present invention, a portion of a nonvolatile charge trap memory device is fabricated by a radical oxidation process.  FIG. 3  depicts a Flowchart representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.  FIGS. 4A-4B  illustrate cross-sectional views representing operations in the fabrication of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
       FIG. 4A  illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon, corresponding to operation  302  from the Flowchart of  FIG. 3 , in accordance with an embodiment of the present invention. Referring to operation  302  of Flowchart  300  and corresponding  FIG. 4A , a substrate  400  is provided having a charge-trapping layer disposed thereon. In an embodiment, the charge-trapping layer has a first region  404 A and a second region  404 B disposed above substrate  400 . In one embodiment, a dielectric layer  402  is disposed between substrate  400  and the charge trapping layer, as depicted in  FIG. 4A . The charge-trapping layer may be composed of a material and have a thickness suitable to store charge and, hence, change the threshold voltage of a subsequently formed gate stack. In an embodiment, region  404 A of the charge-trapping layer will remain as an intact charge-trapping layer following subsequent process operations. However, in that embodiment, region  404 B of the as-formed charge trapping layer will be consumed to form a second dielectric layer, above region  404 A. 
       FIG. 4B  illustrates a cross-sectional view of a substrate having a charge trapping layer with a blocking dielectric layer formed thereon, corresponding to operation  304  from the Flowchart of  FIG. 3 , in accordance with an embodiment of the present invention. Referring to operation  304  of Flowchart  300  and corresponding  FIG. 4B , a blocking dielectric layer  406  is formed on charge-trapping layer  404 . In accordance with an embodiment of the present invention, blocking dielectric layer  406  is formed by oxidizing region  404 B of the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process. In that embodiment, region  404 A of the original charge trapping layer is now labeled as charge-trapping layer  404 . 
     Blocking dielectric layer  406  may be composed of a material and have a thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of a subsequently formed gate stack in a nonvolatile charge trap memory device. In a specific embodiment, region  404 B is a silicon-rich silicon oxy-nitride region having a thickness approximately in the range of 2-3 nanometers and is oxidized to form blocking dielectric layer  406  having a thickness approximately in the range of 3.5-4.5 nanometers. In that embodiment, blocking dielectric layer  406  is composed of silicon dioxide. 
     Blocking dielectric layer  406  may be formed by a radical oxidation process. In accordance with an embodiment of the present invention, the radical oxidation process involves flowing hydrogen (Hz) and oxygen (Oz) gas into a furnace, such as the batch processing chamber  200  described in association with  FIG. 2 . In one embodiment, the partial pressures of Hz and Oz have a ratio to one another of approximately 1:1. However, in an embodiment, an ignition event is not carried out which would otherwise typically be used to pyrolyze the H 2  and O 2  to form steam. Instead, H 2  and O 2  are permitted to react to form radicals at the surface of region  404 B. In one embodiment, the radicals are used to consume region  404 B to provide blocking dielectric layer  406 . In a specific embodiment, the radical oxidation process includes oxidizing with a radical such as, but not limited to, an OH radical, an H0 2  radical or an O diradical at a temperature approximately in the range of 600-900 degrees Celsius. In a particular embodiment, the radical oxidation process is carried out at a temperature approximately in the range of 700-800 degrees Celsius at a pressure approximately in the range of 0.5-5 Torr. In one embodiment, the second radical oxidation process is carried out for a duration approximately in the range of 100-150 minutes. 
     Referring to operation  306  of Flowchart  300 , blocking dielectric layer  406  may be further subjected to a nitridation process in the first process chamber. In accordance with an embodiment of the present invention, the nitridation process includes annealing blocking dielectric layer  406  in an atmosphere including nitrogen at a temperature approximately in the range of 700-800 degrees Celsius for a duration approximately in the range of 5 minutes-60 minutes. In one embodiment, the atmosphere including nitrogen is composed of a gas such as, but not limited to, nitrogen (N2), nitrous oxide (N20), nitrogen dioxide (N02), nitric oxide (NO) or ammonia (NH3). Alternatively, this nitridation step, i.e. operation  306  from Flowchart  300 , may be skipped. 
     In an aspect of the present invention, both a tunnel dielectric layer and a blocking dielectric layer may be formed by radical oxidation processes.  FIG. 5  depicts a Flowchart  500  representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.  FIGS. 6A-6E  illustrates cross-sectional views representing operations in the fabrication of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
       FIG. 6A  illustrates a cross-sectional view of a substrate, corresponding to operation  502  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. Referring to operation  502  of Flowchart  500  and corresponding  FIG. 6A , a substrate  600  is provided in a process chamber. 
     Substrate  600  may be composed of a material suitable for semiconductor device fabrication. In one embodiment, substrate  600  is a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate  600  includes a bulk layer with a top epitaxial layer. In a specific embodiment, the bulk layer is composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material or quartz, while the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate  600  includes a top epitaxial layer on a middle insulator layer which is above a lower bulk layer. The top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon (i.e. to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, silicon-germanium or a III-V compound semiconductor material. The insulator layer is composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride. The lower bulk layer is composed of a single crystal which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material or quartz. Substrate  600  may further include dopant impurity atoms. 
       FIG. 6B  illustrates a cross-sectional view of a substrate having a dielectric layer formed thereon, corresponding to operation  504  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. Referring to operation  504  of Flowchart  500  and corresponding  FIG. 6B , substrate  600  is subjected to a first radical oxidation process to form a first dielectric layer  602 . 
     First dielectric layer  602  may be composed of a material and have a thickness suitable to allow charge carriers to tunnel into a subsequently formed charge trapping layer under an applied gate bias, while maintaining a suitable barrier to leakage when a subsequently formed nonvolatile charge trap memory device is unbiased. First dielectric layer  602  may be referred to in the art as a tunnel dielectric layer. In accordance with an embodiment of the present invention, first dielectric layer  602  is formed by an oxidation process where the top surface of substrate  600  is consumed. Thus, in an embodiment, first dielectric layer  602  is composed of an oxide of the material of substrate  600 . For example, in one embodiment, substrate  600  is composed of silicon and first dielectric layer  602  is composed of silicon dioxide. In a specific embodiment, first dielectric layer  602  is formed to a thickness approximately in the range of 1-10 nanometers. In a particular embodiment, first dielectric layer  602  is formed to a thickness approximately in the range of 1.5-2.5 nanometers. 
     First dielectric layer  602  may be formed by a radical oxidation process. In accordance with an embodiment of the present invention, the radical oxidation process involves flowing hydrogen (H2) and oxygen (02) gas into a furnace, such as the batch processing chamber  200  described in association with  FIG. 2 . In one embodiment, the partial pressures of Hz and Oz have a ratio to one another of approximately 1:1. However, in an embodiment, an ignition event is not carried out which would otherwise typically be used to pyrolyze the Hz and Oz to form steam. Instead, Hz and Oz are permitted to react to form radicals at the surface of substrate  600 . In one embodiment, the radicals are used to consume the top portion of substrate  600  to provide first dielectric layer  602 . In a specific embodiment, the radical oxidation process includes oxidizing with a radical such as, but not limited to, an OH radical, an HO 2  radical or an 0 diradical at a temperature approximately in the range of 600-900 degrees Celsius. In a particular embodiment, the radical oxidation process is carried out at a temperature approximately in the range of 700-800 degrees Celsius at a pressure approximately in the range of 0.5-5 Torr. In one embodiment, the radical oxidation process is carried out for a duration approximately in the range of 100-150 minutes. In accordance with an embodiment of the present invention, first dielectric layer  602  is formed as a high-density, low-hydrogen-content film. 
     Referring to operation  506  of Flowchart  500 , subsequent to forming first dielectric layer  602 , but prior to any further processing, first dielectric layer  602  may be subjected to a nitridation process. In an embodiment, the nitridation process is carried out in the same process chamber used to form first dielectric layer  502 , without removing substrate  600  from the process chamber between process steps. In one embodiment, the annealing includes heating substrate  600  in an atmosphere including nitrogen at a temperature approximately in the range of 700-800 degrees Celsius for a duration approximately in the range of 5 minutes-60 minutes. In one embodiment, the atmosphere including nitrogen is composed of a gas such as, but not limited to, nitrogen (N 2 ), nitrous oxide (N 2 O), nitrogen dioxide (NO 2 ), nitric oxide (NO) or ammonia (NH 3 ). In one embodiment, the nitridation occurs following a nitrogen or argon purge of the process chamber following the first radical oxidation process. Alternatively, the above nitridation step may be skipped. 
       FIG. 6C  illustrates a cross-sectional view of a substrate having a charge trapping layer formed thereon, corresponding to operation  508  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. Referring to operation  508  of Flowchart  500  and corresponding  FIG. 6C , a charge-trapping layer having a first region  604 A and a second region  604 B is formed on first dielectric layer  602 . In an embodiment, the formation of the charge-trapping layer is carried out in the same process chamber used to form first dielectric layer  602 , without removing substrate  600  from the process chamber between process steps. 
     The charge-trapping layer may be composed of a material and have a thickness suitable to store charge and, hence, change the threshold voltage of a subsequently formed gate stack. In accordance with an embodiment of the present invention, the charge-trapping layer is composed of two regions  604 A and  604 B, as depicted in  FIG. 6C . In an embodiment, region  604 A of the charge-trapping layer will remain as an intact charge-trapping layer following subsequent process operations. However, in that embodiment, region  604 B of the as-formed charge-trapping layer will be consumed to form a second dielectric layer, above region  604 A. 
     The charge-trapping layer having regions  604 A and  604 B may be formed by a chemical vapor deposition process. In accordance with an embodiment of the present invention, the charge-trapping layer is composed of a material such as, but not limited to, silicon nitride, silicon oxy-nitride, oxygen-rich silicon oxy-nitride or silicon-rich silicon oxy-nitride. In one embodiment, regions  604 A and  604 B of the charge-trapping layer are formed at a temperature approximately in the range of 600-900 degrees Celsius. In a specific embodiment, the charge-trapping layer is formed by using gases such as, but not limited to, dichlorosilane (H 2 SiCl 2 ), bis-(tert-butylamino)silane (BTBAS), ammonia (NH 3 ) or nitrous oxide (N 2 0). In one embodiment, the charge trapping layer is formed to a total thickness approximately in the range of 5-15 nanometers and region  604 B accounts for a thickness approximately in the range of 2-3 nanometers of the total thickness of the charge-trapping layer. In that embodiment, region  604 A accounts for the remaining total thickness of the charge-trapping layer, i.e. region  604 A accounts for the portion of the charge-trapping layer that is not subsequently consumed to form a top or blocking dielectric layer. 
     In another aspect of the present invention, the charge-trapping layer may include multiple composition regions. For example, in accordance with an embodiment of the present invention, the charge-trapping layer includes an oxygen-rich portion and a silicon-rich portion and is formed by depositing an oxygen-rich oxy-nitride film by a first composition of gases and, subsequently, depositing a silicon-rich oxy-nitride film by a second composition of gases. In one embodiment, the charge-trapping layer is formed by modifying the flow rate of ammonia (NH3) gas, and introducing nitrous oxide (N20) and dichlorosilane (SiH2Cb) to provide the desired gas ratios to yield first an oxygen-rich oxy-nitride film and then a silicon-rich oxy-nitride film. In a specific embodiment, the oxygen-rich oxy-nitride film is formed by introducing a process gas mixture including N20, NH3 and SiH2Cb, while maintaining the process chamber at a pressure approximately in the range of 5-500 mTorr, and maintaining substrate  600  at a temperature approximately in the range of 700-850 degrees Celsius, for a period approximately in the range of 2.5-20 minutes. In a further embodiment, the process gas mixture includes N 2 O and NH 3  having a ratio of from about 8:1 to about 1:8 and SiH 2 Cl 2  and NH 3  having a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate approximately in the range of 5-200 standard cubic centimeters per minute (sccm). In another specific embodiment, the silicon-rich oxy-nitride film is formed by introducing a process gas mixture including N20, NH3 and SiH2Cb, while maintaining the chamber at a pressure approximately in the range of 5-500 mTorr, and maintaining substrate  600  at a temperature approximately in the range of 700-850 degrees Celsius, for a period approximately in the range of 2.5-20 minutes. In a further embodiment, the process gas mixture includes N 20 and NH3 having a ratio of from about 8:1 to about 1:8 and SiH2Cb and NH3 mixed in a ratio of from about 1:7 to about 7:1, introduced at a flow rate of from about 5 to about 20 seem. In accordance with an embodiment of the present invention, the charge-trapping layer comprises a bottom oxygen-rich silicon oxy-nitride portion having a thickness approximately in the range of 2.5-3.5 nanometers and a top silicon-rich silicon oxy-nitride portion having a thickness approximately in the range of 9-10 nanometers. In one embodiment, a region  504 B of charge-trapping layer accounts for a thickness approximately in the range of 2-3 nanometers of the total thickness of the top silicon-rich silicon oxy-nitride portion of the charge-trapping layer. Thus, region  604 B, which is targeted for subsequent consumption to form a second dielectric layer, may be composed entirely of silicon-rich silicon oxy-nitride. 
       FIG. 6D  illustrates a cross-sectional view of a substrate having a second dielectric layer formed thereon, corresponding to operation  510  from the Flowchart of  FIG. 5 , in accordance with an embodiment of the present invention. Referring to operation  510  of Flowchart  500  and corresponding  FIG. 6D , a second dielectric layer  606  is formed on charge-trapping layer  604 . In an embodiment, the formation of second dielectric layer  606  is carried out in the same process chamber used to form first dielectric layer  602  and the charge-trapping layer, without removing substrate  600  from the process chamber between process steps. In one embodiment, the second radical oxidation process is carried out following a nitrogen or argon purge of the process chamber following the deposition of the charge-trapping layer. 
     Second dielectric layer  606  may be composed of a material and have a thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of a subsequently formed gate stack in a nonvolatile charge trap memory device. Second dielectric layer  606  may be referred to in the art as a blocking dielectric layer or a top dielectric layer. In accordance with an embodiment of the present invention, second dielectric layer  606  is formed by consuming region  604 B of the charge-trapping layer formed in operation  508 , described in association with  FIG. 6C . Thus, in one embodiment, region  604 B is consumed to provide second dielectric layer  606 , while region  604 A remains a charge-trapping layer  604 . In a specific embodiment, region  604 B is a silicon-rich silicon oxy-nitride region having a thickness approximately in the range of 2-3 nanometers and is oxidized to form second dielectric layer  606  having a thickness approximately in the range of 3.5-4.5 nanometers. In that embodiment, second dielectric layer  606  is composed of silicon dioxide. In accordance with an embodiment of the present invention, second dielectric layer  606  is formed by a second radical oxidation process, similar to the radical oxidation process carried out to form blocking dielectric layer  406 , described in association with  FIG. 4B . In one embodiment, referring to operation  512  of Flowchart  500 , subsequent to forming second dielectric layer  606 , second dielectric layer  606  is further subjected to a nitridation process similar to the nitridation process described in association with operation  506  from Flowchart  500 . In a specific embodiment, the nitridation occurs following a nitrogen or argon purge of the process chamber following the second radical oxidation process. Alternatively, this nitridation step may be skipped. In accordance with an embodiment of the present invention, no additional deposition processes are used in the formation of second dielectric layer  606 . 
     Thus, in accordance with an embodiment of the present invention, an ONO stack including first dielectric layer  602 , charge-trapping layer  604  and second dielectric layer  606  is formed in a single pass in a process chamber. By fabricating these layers in a single pass of multiple wafers in the process chamber, high throughput requirements may be met while still ensuring the formation of very high quality films. Upon fabrication of an ONO stack including first dielectric layer  602 , charge-trapping layer  604  and second dielectric layer  606 , a nonvolatile charge trap memory device may be fabricated to include a patterned portion of the ONO stack.  FIG. 6E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 6E , a nonvolatile charge trap memory device includes a patterned portion of the ONO stack formed over substrate  600 . The ONO stack includes first dielectric layer  602 , charge-trapping layer  604  and second dielectric layer  606 . A gate layer  608  is disposed on second dielectric layer  606 . The nonvolatile charge trap memory device further includes source and drain regions  612  in substrate  600  on either side of the ONO stack, defining a channel region  614  in substrate  600  underneath the ONO stack. A pair of dielectric spacers  610  isolates the sidewalls of first dielectric layer  602 , charge-trapping layer  604 , second dielectric layer  606  and gate layer  608 . In a specific embodiment, channel region  614  is doped P-type and, in an alternative embodiment, channel region  614  is doped N-type. 
     In accordance with an embodiment of the present invention, the nonvolatile charge trap memory device described in association with  FIG. 6E  is a SONOS-type device. By convention, SONOS stands for “Semiconductor-Oxide-Nitride-Oxide-Semiconductor,” where the first “Semiconductor” refers to the channel region material, the first “Oxide” refers to the tunnel dielectric layer, “Nitride” refers to the charge-trapping dielectric layer, the second “Oxide” refers to the top dielectric layer (also known as a blocking dielectric layer) and the second “Semiconductor” refers to the gate layer. Thus, in accordance with an embodiment of the present invention, first dielectric layer  602  is a tunnel dielectric layer and second dielectric layer  606  is a blocking dielectric layer. 
     Gate layer  608  may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SON OS-type transistor. In accordance with an embodiment of the present invention, gate layer  608  is formed by a chemical vapor deposition process and is composed of doped poly-crystalline silicon. In another embodiment, gate layer  608  is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt or nickel. 
     Source and drain regions  612  in substrate  600  may be any regions having opposite conductivity to channel region  614 . For example, in accordance with an embodiment of the present invention, source and drain regions  612  are N-type doped regions while channel region  614  is a P-type doped region. In one embodiment, substrate  600  and, hence, channel region  614 , is composed of boron-doped single-crystal silicon having a boron concentration in the range of 1×10 15 -1×10 19  atoms/cm 3 . In that embodiment, source and drain regions  612  are composed of phosphorous- or arsenic doped regions having a concentration of N-type dopants in the range of 5×10 16 -5×10 19  atoms/cm 3 . In a specific embodiment, source and drain regions  612  have a depth in substrate  600  in the range of 80-200 nanometers. In accordance with an alternative embodiment of the present invention, source and drain regions  612  are P-type doped regions while channel region  614  is an N-type doped region. 
     In another aspect of the present invention, a dielectric layer formed by radical oxidation of the top surface of a substrate in an oxidation chamber may be less susceptible to crystal plane orientation differences in the substrate upon which it is grown. For example, in one embodiment, the cornering effect caused by differential crystal plane oxidation rates is significantly reduced by forming a dielectric layer by a radical oxidation process.  FIG. 7  A illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 7  A, a substrate  700  has isolation regions  702  formed thereon. Substrate  700  may be composed of a material described in association with substrate  600  from  FIG. 6A . Isolation regions  702  may be composed of an insulating material suitable for adhesion to substrate  700 . An exposed portion of substrate  700  extends above the top surface of isolation regions  702 . In accordance with an embodiment of the present invention, the exposed portion of substrate  700  has a first exposed crystal plane  704  and a second exposed crystal plane  706 . In one embodiment, the crystal orientation of first exposed crystal plane  704  is different from the crystal orientation of second exposed crystal plane  706 . In a specific embodiment, substrate  700  is composed of silicon, first exposed crystal plane  704  has &lt;100&gt; orientation, and second exposed crystal plane  706  has &lt;110&gt; orientation. 
     Substrate  700  may be subjected to a radical oxidation process to form a dielectric layer by consuming (oxidizing) the top surface of substrate  700 . In one embodiment, the oxidizing of substrate  700  by a radical oxidation process includes oxidizing with a radical selected from the group consisting of an OH radical, an H02 radical or an 0 diradical.  FIG. 7B  illustrates a cross-sectional view of substrate  700  including first and second crystal planes  704  and  706 , respectively, and having a dielectric layer  708  formed thereon, in accordance with an embodiment of the present invention. In an embodiment, first portion  708 A of dielectric layer  708  is formed on first exposed crystal plane  704  and a second portion  708 B of dielectric layer  708  is formed on second exposed crystal plane  706 , as depicted in  FIG. 7B . In one embodiment, the thickness T 1  of first portion  708 A of dielectric layer  708  is approximately equal to the thickness T 2  of second portion  708 B of dielectric layer  708 , even though the crystal plane orientation of first exposed crystal plane  704  and second exposed crystal plane  706  differ. In a specific embodiment, the radical oxidation of substrate  700  is carried out at a temperature approximately in the range of 600-900 degrees Celsius. In a specific embodiment, the radical oxidation of substrate  700  is carried out at a temperature approximately in the range of 700-800 degrees Celsius at a pressure approximately in the range of 0.5-5 Torr. 
     Thus, a method for fabricating a nonvolatile charge trap memory device has been disclosed. In accordance with an embodiment of the present invention, a substrate is provided having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process. 
     In another aspect of the present invention, it may be desirable to use a cluster tool to carry out a radical oxidation process. Accordingly, disclosed herein is a method to fabricate a nonvolatile charge trap memory device. A substrate may first be subjected to a first radical oxidation process to form a first dielectric layer in a first process chamber of a cluster tool. In one embodiment, a charge-trapping layer is then deposited above the first dielectric layer in a second process chamber of the cluster tool. The charge-trapping layer may then be subjected to a second radical oxidation process to form a second dielectric layer above the charge-trapping layer. In one embodiment, the second dielectric layer is formed by oxidizing a portion of the charge-trapping layer in the first process chamber of the cluster tool. In a specific embodiment, the cluster tool is a single-wafer cluster tool. 
     Formation of a dielectric layer in a chamber of a cluster tool may permit the growth of the dielectric layer at temperatures higher than normally achievable in batch processing chambers. Furthermore, a radical oxidation process may be carried out in the chamber of the cluster tool as the primary pathway for growing the dielectric layer. In accordance with an embodiment of the present invention, a radical oxidation process involving flowing hydrogen (H2) and oxygen (02) gas into an oxidation chamber of a cluster tool is carried out to effect growth of a dielectric layer by oxidation consumption of an exposed substrate or film. In one embodiment, multiple radical oxidation processes are carried out in an oxidation chamber of a cluster tool to provide a tunnel dielectric layer and a blocking dielectric layer for a non-volatile charge trap memory device. These dielectric layers may be of very high quality, even at a reduced thickness. In one embodiment, the tunnel dielectric layer and the blocking dielectric layer are both denser and are composed of substantially fewer hydrogen atoms/cm3 than a tunnel dielectric layer or a blocking dielectric layer formed in a batch process chamber. Furthermore, the substrate upon which a tunnel dielectric layer and a blocking dielectric layer are formed may be exposed to a shorter temperature ramp rate and stabilization time in an oxidation chamber of a cluster tool as compared with a batch process chamber. Thus, in accordance with an embodiment of the present invention embodiment, the impact on the thermal budget of the substrate is reduced by employing a radical oxidation process in an oxidation chamber of a cluster tool. In accordance with another embodiment of the present invention, a dielectric layer formed by carrying out a radical oxidation process in an oxidation chamber of a cluster tool is less susceptible to crystal plane orientation differences in the substrate from which it is grown. In one embodiment, the cornering effect caused by differential crystal plane oxidation rates is significantly reduced by forming a dielectric layer via a radical oxidation process carried out in an oxidation chamber of a cluster tool. 
     A portion of a nonvolatile charge trap memory device may be fabricated in a cluster tool.  FIG. 8  illustrates an arrangement of process chambers in a cluster tool, in accordance with an embodiment of the present invention. Referring to  FIG. 8 , an arrangement of process chambers in a cluster tool  800  includes a transfer chamber  802 , a first process chamber  804 , a second process chamber  806  and a third process chamber  808 . In an embodiment, transfer chamber  802  is for receiving a wafer from an external environment for introduction into cluster tool  800 . In one embodiment, each of the process chambers  802 ,  804  and  806  are arranged in a way such that a wafer may be passed back-and forth between these chambers and transfer chamber  802 , as depicted by the double-headed arrows in  FIG. 8 . In accordance with an additional embodiment of the present invention, although not shown, cluster tool  800  may be configured such that a wafer can be transferred directly between any pairing of process chambers  802 ,  804  or  806 . 
     Cluster tool  800  may be any cluster tool for which an outside environment is excluded in and between process chambers  804 ,  806  and  808  and transfer chamber  802 . Thus, in accordance with an embodiment of the present invention, once a wafer has entered process chamber  802 , it is protected from an external environment as it is moved into and between process chambers  804 ,  806  and  808  and transfer chamber  802 . An example of such a cluster tool is the Centura® platform commercially available from Applied Materials, Inc., located in Santa Clara, Calif. In one embodiment, once a wafer has been received by transfer chamber  802 , a vacuum of less than approximately 100 mTorr is maintained in cluster tool  800 . In accordance with an embodiment of the present invention, cluster tool  800  incorporates a chuck (or multiple chucks, e.g., one chuck for each chamber) upon which the flat surface, as opposed to the edge surface, of a wafer rests on the chuck for processing and transfer events. In one embodiment, by having the flat surface of a wafer rest on the chuck, more rapid ramp rates for heating the wafer are achievable by heating the wafer via the chuck. In a specific embodiment, cluster tool  800  is a single-wafer cluster tool. 
     Process chambers  802 ,  804  and  806  may include, but are not limited to, oxidation chambers, low-pressure chemical vapor deposition chambers, or a combination thereof. For example, in accordance with an embodiment of the present invention, first process chamber  804  is a first oxidation chamber, second process chamber  806  is a low-pressure chemical vapor deposition chamber, and third process chamber  808  is a second oxidation chamber. An example of an oxidation chamber is the In-Situ Steam Generation (ISSG) chamber from Applied Materials, Inc. Examples of low-pressure chemical vapor deposition chambers include a SiNgen™ chamber and an OXYgen™ chamber from Applied Materials, Inc. Instead of heating entire process chambers to heat a wafer, which is the case for typical batch process chambers, a chuck used for carrying a single wafer may be heated to heat the wafer. In accordance with an embodiment of the present invention, a chuck is used to heat a wafer to the desired process temperature. Thus, relatively short temperature ramp times and stabilization times may be achieved. 
     A portion of a nonvolatile charge trap memory device may be fabricated in a cluster tool.  FIG. 9  depicts a Flowchart  900  representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.  FIGS. 10A-10E  illustrates cross-sectional views representing operations in the fabrication of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 10A , a substrate  1000  is provided in a cluster tool. In one embodiment, substrate  1000  is provided in a transfer chamber, such as transfer chamber  802  described in association with  FIG. 8 . 
     Substrate  1000  may be composed of any material suitable for semiconductor device fabrication. In one embodiment, substrate  1000  is a bulk substrate composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate  1000  includes a bulk layer with a top epitaxial layer. In a specific embodiment, the bulk layer is composed of a single crystal of a material which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material or quartz, while the top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon, germanium, silicon-germanium or a III-V compound semiconductor material. In another embodiment, substrate  1000  includes a top epitaxial layer on a middle insulator layer which is above a lower bulk layer. The top epitaxial layer is composed of a single crystal layer which may include, but is not limited to, silicon (i.e. to form a silicon-on-insulator (SOI) semiconductor substrate), germanium, silicon-germanium or a III-V compound semiconductor material. The insulator layer is composed of a material which may include, but is not limited to, silicon dioxide, silicon nitride or silicon oxy-nitride. The lower bulk layer is composed of a single crystal which may include, but is not limited to, silicon, germanium, silicon-germanium, a III-V compound semiconductor material or quartz. Substrate  1000  may further include dopant impurity atoms. 
       FIG. 10B  illustrates a cross-sectional view of a substrate having a tunnel dielectric layer formed thereon, corresponding to operation  902  from the Flowchart of  FIG. 9 , in accordance with an embodiment of the present invention. Referring to operation  902  of Flowchart  900  and corresponding  FIG. 10B , substrate  1000  is subjected to a first radical oxidation process in a first process chamber of the cluster tool to form a first dielectric layer  1002 . 
     First dielectric layer  1002  may be composed of a material and have a thickness suitable to allow charge carriers to tunnel into a subsequently formed charge trapping layer under an applied gate bias, while maintaining a suitable barrier to leakage when a subsequently formed nonvolatile charge trap memory device is unbiased. In accordance with an embodiment of the present invention, first dielectric layer  1002  is formed by an oxidation process where the top surface of substrate  1000  is consumed. Thus, in an embodiment, first dielectric layer  1002  is composed of an oxide of the material of substrate  1000 . For example, in one embodiment, substrate  1000  is composed of silicon and first dielectric layer  1002  is composed of silicon dioxide. In a specific embodiment, first dielectric layer  1002  is formed to a thickness approximately in the range of 1-10 nanometers. In a particular embodiment, first dielectric layer  1002  is formed to a thickness approximately in the range of 1.5-2.5 nanometers. 
     First dielectric layer  1002  may be formed by a radical oxidation process. In accordance with an embodiment of the present invention, the radical oxidation process involves flowing hydrogen (Hz) and oxygen (Oz) gas into an oxidation chamber, such as the oxidation chambers  804  or  808  described in association with  FIG. 8 . In one embodiment, the partial pressures of Hz and Oz have a ratio to one another approximately in the range of 1:50-1:5. However, in an embodiment, an ignition event is not carried out which would otherwise typically be used to pyrolyze the Hz and Oz to form steam. Instead, Hz and Oz are permitted to react to form radicals at the surface of substrate  1000 . In one embodiment, the radicals are used to consume the top portion of substrate  1000  to provide first dielectric layer  1002 . In a specific embodiment, the radical oxidation process includes oxidizing with a radical such as, but not limited to, an OH radical, an HO 2  radical or an O diradical. In a particular embodiment, the radical oxidation process is carried out at a temperature approximately in the range of 950-1100 degrees Celsius at a pressure approximately in the range of 5-15 Torr. In one embodiment, the radical oxidation process is carried out for a duration of approximately in the range of 1-3 minutes. In accordance with an embodiment of the present invention, first dielectric layer  1002  is formed as a high-density, low-hydrogen-content film. 
     Referring to operation  904  of Flowchart  900 , subsequent to forming first dielectric layer  1002 , but prior to any further processing, first dielectric layer  1002  may be subjected to a nitridation process. In an embodiment, the nitridation process is carried out in the same process chamber used to form first dielectric layer  1002 . In one embodiment, first dielectric layer  1002  is annealed in the first process chamber, wherein the annealing includes heating substrate  1000  in an atmosphere including nitrogen at a temperature approximately in the range of 900-1100 degrees Celsius for a duration approximately in the range of 30 seconds-60 seconds. In one embodiment, the atmosphere including nitrogen is composed of a gas such as, but not limited to, nitrogen (N2), nitrous oxide (N20), nitrogen dioxide (N02), nitric oxide (NO) or ammonia (NH3). In another embodiment, the nitridation occurs in a separate process chamber. Alternatively, this nitridation step may be skipped. 
       FIG. 10C  illustrates a cross-sectional view of a substrate having a charge-trapping layer formed thereon, corresponding to operation  906  from the Flowchart of  FIG. 9 , in accordance with an embodiment of the present invention. Referring to operation  906  of Flowchart  900  and corresponding  FIG. 10C , a charge-trapping layer having a first region  1004 A and a second region  1004 B is formed on first dielectric layer  1002  in the second process chamber of a cluster tool. 
     The charge-trapping layer may be composed of a material and have a thickness suitable to store charge and, hence, change the threshold voltage of a subsequently formed gate stack. In accordance with an embodiment of the present invention, the charge-trapping layer is composed of two regions  1004 A and  1004 B, as depicted in  FIG. 10C . In an embodiment, region  1004 A of the charge-trapping layer will remain as an intact charge-trapping layer following subsequent process operations. However, in that embodiment, region  1004  B of the as-formed charge-trapping layer will be consumed to form a second dielectric layer, above region  1004 A. In one embodiment, regions  1004 A and  1004 B of the charge-trapping layer are formed in the same process step and are composed of the same material. 
     The charge-trapping layer having regions  1004 A and  1004 B may be formed by a chemical vapor deposition process. In accordance with an embodiment of the present invention, the charge-trapping layer is composed of a material such as, but not limited to, silicon nitride, silicon oxy-nitride, oxygen-rich silicon oxy-nitride or silicon-rich silicon oxynitride. In an embodiment, the charge-trapping layer is formed on first dielectric layer  1002  in a low-pressure chemical vapor deposition chamber, such as the SiNgen™ low-pressure chemical vapor deposition chamber described in association with process chamber  806  from  FIG. 8 . In one embodiment, the second process chamber is a low-pressure chemical vapor deposition chamber and regions  1004 A and  1004 B of the charge-trapping layer are formed at a temperature less than the temperature used to form first dielectric layer  1002 . In a specific embodiment, regions  1004 A and  1004 B of the charge-trapping layer are formed at a temperature approximately in the range of 700-850 degrees Celsius. In an embodiment, the second process chamber is a low-pressure chemical vapor deposition chamber and the charge-trapping layer is formed by using gases such as, but not limited to, dichlorosilane (H 2 SiCl 2 ), bis-(tert-butylamino) silane (BTBAS), ammonia (NH 3 ) or nitrous oxide (N 2 O). In accordance with an embodiment of the present invention, the charge-trapping layer is formed to a total thickness approximately in the range of 5-15 nanometers and region  1004  B accounts for a thickness approximately in the range of 2-3 nanometers of the total thickness of the charge-trapping layer. In that embodiment, region  1004 A accounts for the remaining total thickness of the charge-trapping layer, i.e. the portion of the charge-trapping layer that is not subsequently consumed to form a top or blocking dielectric layer. 
     In another aspect of the present invention, the charge-trapping layer may include multiple composition regions. For example, in accordance with an embodiment of the present invention, the charge-trapping layer includes an oxygen-rich portion and a silicon-rich portion and is formed by depositing an oxygen-rich oxy-nitride film by a first composition of gases in the second process chamber and, subsequently, depositing a silicon-rich oxy-nitride film by a second composition of gases in the second process chamber. In one embodiment, the charge-trapping layer is formed by modifying the flow rate of ammonia (NH3) gas, and introducing nitrous oxide (N20) and dichlorosilane (SiH2Cb) to provide the desired gas ratios to yield first an oxygen-rich oxy-nitride film and then a silicon-rich oxy-nitride film. In a specific embodiment, the oxygen-rich oxynitride film is formed by introducing a process gas mixture including N20, NH3 and SiH2Cb, while maintaining the chamber at a pressure approximately in the range of 0.5-500 Torr, and maintaining substrate  1000  at a temperature approximately in the range of 700-850 degrees Celsius, for a period approximately in the range of 2.5-20 minutes. In a further embodiment, the process gas mixture includes N20 and NH3 having a ratio of from about 8:1 to about 1:8 and SiH2Cb and NH3 having a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate approximately in the range of 5-200 standard cubic centimeters per minute (seem). In another specific embodiment, the silicon-rich oxy-nitride film is formed by introducing a process gas mixture including N20, NH3 and SiH2Cb, while maintaining the chamber at a pressure approximately in the range of 0.5-500 Torr, and maintaining substrate  1000  at a temperature approximately in the range of 700-850 degrees Celsius, for a period approximately in the range of 2.5-20 minutes. In a further embodiment, the process gas mixture includes N20 and NH3 having a ratio of from about 8:1 to about 1:8 and SiH2Cb and NH3 mixed in a ratio of from about 1:7 to about 7:1, introduced at a flow rate of from about 5 to about 20 seem. In accordance with an embodiment of the present invention, the charge-trapping layer comprises a bottom oxygen-rich silicon oxy-nitride portion having a thickness approximately in the range of 2.5-3.5 nanometers and a top silicon-rich silicon oxynitride portion having a thickness approximately in the range of 9-10 nanometers. In one embodiment, a region  1004 B of charge-trapping layer accounts for a thickness approximately in the range of 2-3 nanometers of the total thickness of the top silicon-rich silicon oxy-nitride portion of the charge-trapping layer. Thus, region  1004 B, which is targeted for subsequent consumption to form a second dielectric layer, may be composed entirely of silicon-rich silicon oxy-nitride. 
       FIG. 10D  illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon, corresponding to operation  908  from the Flowchart of  FIG. 9 , in accordance with an embodiment of the present invention. Referring to operation  908  of Flowchart  900  and corresponding  FIG. 10D , a second dielectric layer  1006  is formed on charge-trapping layer  1004  in the first process chamber of the cluster tool. 
     Second dielectric layer  1006  may be composed of a material and have a thickness suitable to maintain a barrier to charge leakage without significantly decreasing the capacitance of a subsequently formed gate stack in a nonvolatile charge trap memory device. In accordance with an embodiment of the present invention, second dielectric layer  1006  is formed by consuming region  1004 B of the charge trapping layer formed in operation  906 , described in association with  FIG. 10C . Thus, in one embodiment region  1004 B is consumed to provide second dielectric layer  1006 , while region  1004 A remains a charge-trapping layer  1004 . In a specific embodiment, region  1004 B is a silicon-rich silicon oxy-nitride region having a thickness approximately in the range of 2-3 nanometers and is oxidized to form second dielectric layer  1006  having a thickness approximately in the range of 3.5-4.5 nanometers. In that embodiment, second dielectric layer  1006  is composed of silicon dioxide. 
     Second dielectric layer  1006  may be formed by a second radical oxidation process. In accordance with an embodiment of the present invention, the second radical oxidation process involves flowing hydrogen (Hz) and oxygen (Oz) gas into an oxidation chamber, such as the oxidation chambers  804  or  808  described in association with  FIG. 8 . In one embodiment, the partial pressures of Hz and Oz have a ratio to one another approximately in the range of 1:50-1:5. However, in an embodiment, an ignition event is not carried out which would otherwise typically be used to pyrolyze the Hz and Oz to form steam. Instead, Hz and Oz are permitted to react to form radicals at the surface of region  1004  B. In one embodiment, the radicals are used to consume region  1004  B to provide second dielectric layer  1006 . In a specific embodiment, the second radical oxidation process includes oxidizing with a radical such as, but not limited to, an OH radical, an HO 2  radical or an O diradical. In a particular embodiment, the second radical oxidation process is carried out at a temperature approximately in the range of 950-1100 degrees Celsius at a pressure approximately in the range of 5-15 Torr. In one embodiment, the second radical oxidation process is carried out for a duration approximately in the range of 1-3 minutes. In accordance with an embodiment of the present invention, first dielectric layer  1002  is formed as a high-density, low-hydrogen content film. In one embodiment, no additional deposition step is required to form a complete second dielectric layer  1006 , as depicted in  FIG. 10D  and shown in Flowchart  900 . Depending on wafer pass-through logistics in the cluster tool, the second radical oxidation process may be carried out in the same, i.e. first, chamber as the first radical oxidation process used to form first dielectric layer  1002  or in a different, e.g. third, process chamber of the cluster tool. Thus, in accordance with an embodiment of the present invention, reference to a first process chamber can be used to mean reintroduction into the first process chamber or to mean introduction into a process chamber different from the first process chamber. 
     Referring to operation  910  of Flowchart  900 , subsequent to forming second dielectric layer  1006 , but prior to removing substrate  1000  from the cluster tool, second dielectric layer  1006  may be further subjected to a nitridation process in the first process chamber. In accordance with an embodiment of the present invention, the nitridation process includes annealing second dielectric layer  1006  in an atmosphere including nitrogen at a temperature approximately in the range of 900-1100 degrees Celsius for a duration approximately in the range of 30 seconds-60 seconds. In one embodiment, the atmosphere including nitrogen is composed of a gas such as, but not limited to, nitrogen (N2), nitrous oxide (N20), nitrogen dioxide (N02), nitric oxide (NO) or ammonia (NH3). Alternatively, this nitridation step, i.e. operation  910  from Flowchart  900 , may be skipped and the wafer unloaded from the cluster tool. 
     Thus, in accordance with an embodiment of the present invention, an ONO stack including first dielectric layer  1002 , charge-trapping layer  1004  and second dielectric layer  1006  is formed in a single pass in a cluster tool. By fabricating these layers in a single pass in the cluster tool, pristine interfaces between first dielectric layer  1002  and charge-trapping layer  1004  and between charge-trapping layer  1004  and second dielectric layer  1006  may be preserved. In one embodiment, first dielectric layer  1002 , charge-trapping layer  1004  and second dielectric layer  1006  are formed without breaking vacuum in the cluster tool. In one embodiment, each layer is formed at a different temperature to tailor film properties without incurring significant ramp time penalties. Furthermore, by fabricating these layers in a cluster tool, as opposed to fabricating in batch processing tools, the overall uniformity of the stack of layers may be optimized. For example, in accordance with an embodiment of the present invention, by fabricating layers  1002 ,  1004  and  1006  in a cluster tool, the variability in thickness of the stack of layers  1002 ,  1004  and  1006  across a single wafer may be reduced by as much as approximately 30%. In an exemplary embodiment, 1 cr is approximately in the range of 1-2% of the thickness of first dielectric layer  1002 . In a specific embodiment, the cluster tool is a single-wafer cluster tool. 
     Upon fabrication of an ONO stack including first dielectric layer  1002 , charge-trapping layer  1004  and second dielectric layer  1006 , a nonvolatile charge trap memory device may be fabricated to include a patterned portion of the ONO stack.  FIG. 10E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 10E , a nonvolatile charge trap memory device includes a patterned portion of the ONO stack formed over substrate  1000 . The ONO stack includes first dielectric layer  1002 , charge-trapping layer  1004  and second dielectric layer  1006 . A gate layer  1008  is disposed on second dielectric layer  1006 . The nonvolatile charge trap memory device further includes source and drain regions  1012  in substrate  1000  on either side of the ONO stack, defining a channel region  1014  in substrate  1000  underneath the ONO stack. A pair of dielectric spacers  1010  isolates the sidewalls of first dielectric layer  1002 , charge-trapping layer  1004 , second dielectric layer  1006  and gate layer  1008 . In a specific embodiment, channel region  1014  is doped P-type and, in an alternative embodiment, channel region  1014  is doped N-type. 
     In accordance with an embodiment of the present invention, the nonvolatile charge trap memory device described in association with  FIG. 10E  is a SONOS-type device. By convention, SONOS stands for “Semiconductor-Oxide-Nitride-Oxide-Semiconductor,” where the first “Semiconductor” refers to the channel region material, the first “Oxide” refers to the tunnel dielectric layer, “Nitride” refers to the charge-trapping dielectric layer, the second “Oxide” refers to the top dielectric layer (also known as a blocking dielectric layer) and the second “Semiconductor” refers to the gate layer. Thus, in accordance with an embodiment of the present invention, first dielectric layer  1002  is a tunnel dielectric layer and second dielectric layer  1006  is a blocking dielectric layer. 
     Gate layer  1008  may be composed of any conductor or semiconductor material suitable for accommodating a bias during operation of a SON OS-type transistor. In accordance with an embodiment of the present invention, gate layer  1008  is formed by a chemical vapor deposition process and is composed of doped poly-crystalline silicon. In another embodiment, gate layer  1008  is formed by physical vapor deposition and is composed of a metal-containing material which may include, but is not limited to, metal nitrides, metal carbides, metal silicides, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt or nickel. 
     Source and drain regions  1012  in substrate  1000  may be any regions having opposite conductivity to channel region  1014 . For example, in accordance with an embodiment of the present invention, source and drain regions  1012  are N-type doped regions while channel region  1014  is a P-type doped region. In one embodiment, substrate  1000  and, hence, channel region  1014 , is composed of boron-doped single crystal silicon having a boron concentration in the range of 1×10 15 -1×10 19  atoms/cm 3 . In that embodiment, source and drain regions  1012  are composed of phosphorous- or arsenic-doped regions having a concentration of N-type dopants in the range of 5×10 16 -5×10 19  atoms/cm 3 . In a specific embodiment, source and drain regions  1012  have a depth in substrate  1000  in the range of 80-200 nanometers. In accordance with an alternative embodiment of the present invention, source and drain regions  1012  are P-type doped regions while channel region  1014  is an-N-type doped region. 
     In another aspect of the present invention, a charge-trapping layer may include multiple composition regions, where the composition region closest to a tunnel dielectric layer is subjected to a radical oxidation process.  FIG. 11  depicts a Flowchart  1100  representing a series of operations in a method for fabricating a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention.  FIGS. 12A-12E  illustrate cross-sectional views representing operations in the fabrication of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
       FIG. 12A  illustrates a cross-sectional view of a substrate having a first dielectric layer formed thereon, corresponding to operation  1102  from the Flowchart of  FIG. 11 , in accordance with an embodiment of the present invention. Referring to operation  1102  of Flowchart  1100  and corresponding  FIG. 12A , substrate  1200  is subjected to a first radical oxidation process in a first process chamber of a cluster tool to form a first dielectric layer  1202 . Substrate  1200  and first dielectric layer  1202  may be composed of materials described in association with substrate  1000  and first dielectric layer  1002  from  FIGS. 10A and 10B , respectively. The radical oxidation process used to form first dielectric layer  1202  may be similar to the radical oxidation process used to form first dielectric layer  1002 , described in association with  FIG. 10B . 
     Referring to operation  1104  of Flowchart  1100 , subsequent to forming first dielectric layer  1202 , but prior to any further processing, first dielectric layer  1202  may be subjected to a nitridation process. The nitridation process may be similar to the nitridation process described in association with operation  904  of Flowchart  900 . In one embodiment, the nitridation process is carried out in the same process chamber used to form first dielectric layer  1202 . In another embodiment, the nitridation occurs in a separate process chamber. Alternatively, this nitridation step may be skipped. 
       FIG. 12B  illustrates a cross-sectional view of a substrate having an oxygen-rich silicon oxy-nitride portion of a charge-trapping layer formed thereon, corresponding to operation  1106  from the Flowchart of  FIG. 11 , in accordance with an embodiment of the present invention. Referring to operation  1106  of Flowchart  1100  and corresponding  FIG. 12B , an oxygen-rich silicon oxy-nitride portion  1204 A is formed on first dielectric layer  1202  in a second process chamber of the cluster tool. Oxygen-rich silicon oxy-nitride portion  1204 A may be composed of an oxygen-rich silicon oxynitride material and formed by a technique described in association with first region  1004 A from  FIG. 10C . 
     Referring to operation  1108  from Flowchart  1100 , in accordance with an embodiment of the present invention, oxygen-rich silicon oxy-nitride portion  1204 A is subjected to a second radical oxidation process in the first process chamber of the cluster tool. The second radical oxidation process may be similar to one of the radical oxidation processes used to form first dielectric layer  1002  or second dielectric layer  1006 , described in association with  FIGS. 10B and 10D , respectively. In an embodiment, carrying out the second radical oxidation process is made possible because oxygen-rich silicon oxy-nitride portion  1204 A is maintained in the environment within the tool and thus retains a pristine surface. In one embodiment, the second radical oxidation process densifies oxygen-rich silicon oxy-nitride portion  1204 A. Depending on wafer pass-through logistics in the cluster tool, the second radical oxidation process may be carried out in the same, i.e. first, chamber as the radical oxidation process used to form first dielectric layer  1202  or in a different, e.g. third, process chamber. Thus, in accordance with an embodiment of the present invention, reference to a first process chamber can be used to mean reintroduction into the first process chamber or to mean introduction into a process chamber different from the first process chamber. 
       FIG. 12C  illustrates a cross-sectional view of a substrate having a silicon-rich silicon oxy-nitride portion of a charge-trapping layer formed thereon, corresponding to operation  1110  from the Flowchart of  FIG. 11 , in accordance with an embodiment of the present invention. Referring to operation Ill  0  of Flowchart  1100  and corresponding  FIG. 12C , a silicon-rich silicon oxy-nitride portion having a first region  1204 B and a second region  1204 C is formed on oxygen-rich silicon oxy-nitride portion  1204 A in the second process chamber of the cluster tool. The silicon-rich silicon oxynitride portion may be composed of a silicon-rich silicon oxy-nitride material and formed by a technique described in association with second region  1004 B from Figure IOC. Depending on wafer pass-through logistics in the cluster tool, the deposition of silicon-rich silicon oxy-nitride portion of the charge-trapping layer may be carried out in the same, i.e. second, chamber as the deposition of oxygen-rich silicon oxy-nitride portion  1204 A of the charge-trapping layer or in a different process chamber. Thus, in accordance with an embodiment of the present invention, reference to a second process chamber can be used to mean reintroduction into the second process chamber or to mean introduction into a process chamber different from the second process chamber. 
       FIG. 12D  illustrates a cross-sectional view of a substrate having a top dielectric layer formed thereon, corresponding to operation  1112  from the Flowchart of  FIG. 11 , in accordance with an embodiment of the present invention. Referring to operation  1112  of Flowchart  1100  and corresponding  FIG. 12D , a second dielectric layer  1206  is formed on charge-trapping layer  1204  in the first process chamber of the cluster tool. In accordance with an embodiment of the present invention, second dielectric layer  1206  is formed by consuming second region  1204 C of the silicon-rich silicon oxy-nitride portion by a third radical oxidation process. Thus, in one embodiment, the remaining charge-trapping layer  1204  between first dielectric layer  1202  and second dielectric layer  1204  is composed of oxygen-rich silicon oxy-nitride portion  1204 A and first region  1204 B of the silicon-rich silicon oxy-nitride portion  1204 , as depicted in  FIG. 12D . The third radical oxidation process used to consume second region  1204 C of the silicon-rich silicon oxy-nitride portion to provide second dielectric layer  1206  may be similar to the radical oxidation process used to form second dielectric layer  1006 , described in association with  FIG. 10D . Depending on wafer pass-through logistics in the cluster tool, the third radical oxidation process may be carried out in the same, i.e. first, chamber as the radical oxidation process used to form first dielectric layer  1202  or in a different, e.g. third, process chamber. Thus, in accordance with an embodiment of the present invention, reference to a first process chamber can be used to mean reintroduction into the first process chamber or to mean introduction into a process chamber different from the first process chamber. 
     Referring to operation  1114  of Flowchart  1100 , subsequent to forming second dielectric layer  1206 , but prior to removing substrate  1200  from the cluster tool, second dielectric layer  1206  may be further subjected to a nitridation process in the first process chamber. The nitridation process may be similar to the nitridation process described in association with operation  910  from Flowchart  900 . In one embodiment, the nitridation process is carried out in the same process chamber used to form second dielectric layer  1206 . In another embodiment, the nitridation occurs in a separate process chamber. Alternatively, this nitridation step may be skipped. 
     Upon fabrication of an ONO stack including first dielectric layer  1202 , charge-trapping layer  1204  and second dielectric layer  1206 , a nonvolatile charge trap memory device may be fabricated to include a patterned portion of the ONO stack.  FIG. 12E  illustrates a cross-sectional view of a nonvolatile charge trap memory device, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 12E , a nonvolatile charge trap memory device includes a patterned portion of the ONO stack formed over substrate  1200 . The ONO stack includes first dielectric layer  1202 , charge-trapping layer  1204  and second dielectric layer  1206 . A gate layer  1208  is disposed on second dielectric layer  1206 . The nonvolatile charge trap memory device further includes source and drain regions  1212  in substrate  1200  on either side of the ONO stack, defining a channel region  1214  in substrate  1200  underneath the ONO stack. A pair of dielectric spacers  1210  isolates the sidewalls of first dielectric layer  1202 , charge-trapping layer  1204 , second dielectric layer  1206  and gate layer  1208 . In accordance with an embodiment of the present invention, charge-trapping layer  1204  is composed of an oxygen-rich silicon oxy-nitride portion  1204 A and a silicon-rich silicon oxy-nitride portion  1204 B, as depicted in  FIG. 12E . In one embodiment, the nonvolatile charge trap memory device is a SONOS-type device. Gate layer  1208 , source and drain regions  1212  and channel region  1214  may be composed of materials described in association with gate layer  1008 , source and drain regions  1012  and channel region  1014  from  FIG. 10E . 
     In another aspect of the present invention, a dielectric layer formed by radical oxidation of the top surface of a substrate in an oxidation chamber may be less susceptible to crystal plane orientation differences in the substrate upon which it is grown. For example, in one embodiment, the cornering effect caused by differential crystal plane oxidation rates is significantly reduced by forming a dielectric layer in an oxidation chamber of a cluster tool.  FIG. 13A  illustrates a cross-sectional view of a substrate including first and second exposed crystal planes, in accordance with an embodiment of the present invention. 
     Referring to  FIG. 13A , a substrate  1300  has isolation regions  1302  formed thereon. Substrate  1300  may be composed of a material described in association with substrate  1000  from  FIG. 10A . Isolation regions  1302  may be composed of an insulating material suitable for adhesion to substrate  1300 . An exposed portion of substrate  1300  extends above the top surface of isolation regions  1302 . In accordance with an embodiment of the present invention, the exposed portion of substrate  1300  has a first exposed crystal plane  1304  and a second exposed crystal plane  1306 . In one embodiment, the crystal orientation of first exposed crystal plane  1304  is different from the crystal orientation of second exposed crystal plane  1306 . In a specific embodiment, substrate  1300  is composed of silicon, first exposed crystal plane  1304  has &lt;100&gt; orientation, and second exposed crystal plane  1306  has &lt;110&gt; orientation. 
     Substrate  1300  may be subjected to a radical oxidation process in a cluster tool to form a dielectric layer by consuming (oxidizing) the top surface of substrate  1300 . In one embodiment, the oxidizing of substrate  1300  by a radical oxidation process includes oxidizing with a radical selected from the group consisting of an OH radical, an H02 radical or an 0 diradical.  FIG. 13B  illustrates a cross-sectional view of substrate  1300  including first and second crystal planes  1304  and  1306 , respectively, and having a dielectric layer  1308  formed thereon, in accordance with an embodiment of the present invention. In an embodiment, first portion  1308 A of dielectric layer  1308  is formed on first exposed crystal plane  1304  and a second portion  1308 B of dielectric layer  1308  is formed on second exposed crystal plane  1306 , as depicted in  FIG. 13B . In one embodiment, the thickness T 1  of first portion  1308 A of dielectric layer  1308  is approximately equal to the thickness T 2  of second portion  1308 B of dielectric layer  1308 , even though the crystal plane orientation of first exposed crystal plane  1304  and second exposed crystal plane  1306  differ. In a specific embodiment, the radical oxidation of substrate  1300  is carried out at a temperature approximately in the range of 950-1100 degrees Celsius at a pressure approximately in the range of 5-15 Torr. In one embodiment, subsequent to forming dielectric layer  1308 , substrate  1300  is annealed in the oxidation chamber in an atmosphere including nitrogen at a temperature approximately in the range of 900-1100 degrees Celsius for a duration approximately in the range of 30 seconds-60 seconds. 
     Implementations and Alternatives 
     In one aspect the present disclosure is directed to memory devices including an oxide split multi-layer charge storing structure.  FIG. 14  is a block diagram illustrating a cross-sectional side view of an embodiment of one such semiconductor memory device  1400 . The memory device  1400  includes a SONONOS stack  1402  including an ONONO structure  1404  formed over a surface  1406  of a substrate  1408 . Substrate  1408  includes one or more diffusion regions  1410 , such as source and drain regions, aligned to the gate stack  1402  and separated by a channel region  1412 . Generally, the SONONOS structure  1402  includes a polysilicon or metal gate layer  1414  formed upon and in contact with the ONONO structure  1404 . The gate  1414  is separated or electrically isolated from the substrate  1408  by the ONONO structure  1404 . The ONONO structure  1404  includes a thin, lower oxide layer or tunneling oxide layer  1416  that separates or electrically isolates the stack  1402  from the channel region  1412 , a top or blocking oxide layer  1420 , and a multi-layer charge storing layer  1404 . The multi-layer charge storing layer generally includes at least two nitride layers having differing compositions of silicon, oxygen and nitrogen, including a silicon-rich, nitrogen-rich, and oxygen-lean top nitride layer  1418 , a silicon-rich, oxygen-rich, the bottom nitride layer  1419 , and an oxide, anti-tunneling layer  1421 . 
     It has been found that a silicon-rich, oxygen-rich, bottom nitride layer  1419  decreases the charge loss rate after programming and after erase, which is manifested in a small voltage shift in the retention mode, while a silicon-rich, nitrogen-rich, and oxygen-lean top nitride layer  1418  improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory devices made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device. 
     It has further been found the anti-tunneling layer  1421  substantially reduces the probability of electron charge that accumulates at the boundaries of the upper nitride layer  1418  during programming from tunneling into the bottom nitride layer  1419 , resulting in lower leakage current than for the structure illustrated in  FIG. 1 . 
     The multi-layer charge storing layer can have an overall thickness of from about 50 Å to about 150 Å, and in certain embodiments less than about 100 Å, with the with the thickness of the anti-tunneling layer  1421  being from about 5 Å to about 20 Å, and the thicknesses of the nitride layers  1418 ,  1419 , being substantially equal. 
     A method or forming or fabricating a split multi-layer charge storing structure according to one embodiment will now be described with reference to the flowchart of  FIG. 15 . 
     Referring to  FIG. 15 , the method begins with forming a first oxide layer, such as a tunneling oxide layer, over a silicon containing layer on a surface of a substrate ( 1500 ). As noted above, the tunneling oxide layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the radical oxidation process involves flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a processing chamber or furnace to effect growth of a the tunneling oxide layer by oxidation consumption of a portion of the substrate. 
     Next, the first or bottom nitride or nitride containing layer of the multi-layer charge storing layer is formed on a surface of the tunneling oxide layer ( 1502 ). In one embodiment, the nitride layers are formed or deposited in a low pressure CVD process using a silicon source, such as silane (SiH 4 ), chlorosilane (SiH 3 Cl), dichlorosilane or DCS (SiH 2 Cl 2 ), tetrachlorosilane (SiCl 4 ) or Bis-TertiaryButylAmino Silane (BTBAS), a nitrogen source, such as nitrogen (N 2 ), ammonia (NH 3 ), nitrogen trioxide (NO 3 ) or nitrous oxide (N 2 O), and an oxygen-containing gas, such as oxygen (O 2 ) or N 2 O. Alternatively, gases in which hydrogen has been replaced by deuterium can be used, including, for example, the substitution of deuterated-ammonia (ND 3 ) for NH 3 . The substitution of deuterium for hydrogen advantageously passivates Si dangling bonds at the silicon-oxide interface, thereby increasing an NBTI (Negative Bias Temperature Instability) lifetime of the devices. 
     For example, the lower or bottom nitride layer can be deposited over the tunneling oxide layer by placing the substrate in a deposition chamber and introducing a process gas including N 2 O, NH 3  and DCS, while maintaining the chamber at a pressure of from about 5 milliTorr (mT) to about 500 mT, and maintaining the substrate at a temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N 2 O and NH 3  mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH 3  mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 200 standard cubic centimeters per minute (sccm). It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, oxygen-rich, bottom nitride layer. 
     Next, the anti-tunneling layer is formed or deposited on a surface of the bottom nitride layer ( 1504 ). As with the tunneling oxide layer, the anti-tunneling layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the radical oxidation process involves flowing hydrogen (H 2 ) and oxygen (O 2 ) gas into a batch-processing chamber or furnace to effect growth of the anti-tunneling layer by oxidation consumption of a portion of the bottom nitride layer. 
     The second or top nitride layer of the multi-layer charge storing layer is then formed on a surface of the anti-tunneling layer ( 1506 ). The top nitride layer can be deposited over the anti-tunneling layer  1421  in a CVD process using a process gas including N 2 O, NH 3  and DCS, at a chamber pressure of from about 5 mT to about 500 mT, and at a substrate temperature of from about 700 degrees Celsius to about 850 degrees Celsius and in certain embodiments at least about 760 degrees Celsius, for a period of from about 2.5 minutes to about 20 minutes. In particular, the process gas can include a first gas mixture of N 2 O and NH 3  mixed in a ratio of from about 8:1 to about 1:8 and a second gas mixture of DCS and NH 3  mixed in a ratio of from about 1:7 to about 7:1, and can be introduced at a flow rate of from about 5 to about 20 sccm. It has been found that an oxynitride layer produced or deposited under these condition yields a silicon-rich, nitrogen-rich, and oxygen-lean top nitride layer  1418 , which improves the speed and increases of the initial difference between program and erase voltage without compromising a charge loss rate of memory devices made using an embodiment of the silicon-oxide-oxynitride-oxide-silicon structure, thereby extending the operating life of the device. 
     In some embodiments, the silicon-rich, nitrogen-rich, and oxygen-lean top nitride layer can be deposited over the anti-tunneling layer in a CVD process using a process gas including BTBAS and ammonia (NH 3 ) mixed at a ratio of from about 7:1 to about 1:7 to further include a concentration of carbon selected to increase the number of traps therein. The selected concentration of carbon in the second oxynitride layer can include a carbon concentration of from about 5% to about 15%. 
     Finally, a top, blocking oxide layer or HTO layer is formed on a surface of the second layer of the multi-layer charge storing layer ( 1508 ). As with the tunneling oxide layer and the anti-tunneling layer the HTO layer can be formed or deposited by any suitable means, including a plasma oxidation process, In-Situ Steam Generation (ISSG) or a radical oxidation process. In one embodiment, the HTO layer is formed using a plasma oxidation performed in a plasma process chamber. Typical deposition conditions used for this process are—R.F power in the range 1500 W to 10000 W, H2 and O2 with H2 volume percent between 0% and 90%, substrate temperature between 300 C to 400 C, deposition time being 20 to 60 sec 
     Alternatively, the HTO layer is formed using an ISSG oxidation process. In one embodiment, the ISSG is performed in an RTP chamber, such as the ISSG chamber from Applied Materials described above, at pressures of from about 8 to 12 Torr and a temperature of about 1050° C. with an oxygen rich gas mixture hydrogen to which from about 0.5% to 33% hydrogen has been added. The deposition time is in the range 20 to 60 sec. 
     It will be appreciated that in either embodiment the thickness of the top nitride layer may be adjusted or increased as some of the top nitride layer will be effectively consumed or oxidized during the process of forming the HTO layer. 
     Optionally, the method may further include forming or depositing a metal or polysilicon containing layer on a surface of the HTO layer to form a gate layer of the transistor or device ( 1508 ). The gate layer can be, for example, a polysilicon layer deposited by a CVD process to form a silicon-oxide-nitride-oxide-nitride-oxide-silicon (SONOS) structure. 
     In another aspect the present disclosure is also directed to multigate or multigate-surface memory devices including charge-trapping regions overlying two or more sides of a channel formed on or above a surface of a substrate, and methods of fabricating the same. Multigate devices include both planar and non-planar devices. A planar multigate device (not shown) generally includes a double-gate planar device in which a number of first layers are deposited to form a first gate below a subsequently formed channel, and a number of second layers are deposited thereover to form a second gate. A non-planar multigate device generally includes a horizontal or vertical channel formed on or above a surface of a substrate and surrounded on three or more sides by a gate. 
       FIG. 16A  illustrates one embodiment of a non-planar multigate memory device including a charge-trapping region. Referring to  FIG. 16A , the memory device  1600 , commonly referred to as a finFET, includes a channel  1602  formed from a thin film or layer of semiconducting material overlying a surface  1604  on a substrate  1606  connecting a source  1608  and a drain  1610  of the memory device. The channel  1602  is enclosed on three sides by a fin which forms a gate  1612  of the device. The thickness of the gate  1612  (measured in the direction from source to drain) determines the effective channel length of the device. 
     In accordance with the present disclosure, the non-planar multigate memory device  1600  of  FIG. 16A  can include a split charge-trapping region.  FIG. 16B  is a cross-sectional view of a portion of the non-planar memory device of  FIG. 16A  including a portion of the substrate  1606 , channel  1602  and the gate  1612  illustrating a multi-layer charge storing layer  1614 . The gate  1612  further includes a tunnel oxide layer  1616  overlying a raised channel  1602 , a blocking dielectric  1618  and a metal gate layer  1620  overlying the blocking layer to form a control gate of the memory device  1600 . In some embodiments a doped polysilicon may be deposited instead of metal to provide a polysilicon gate layer. The channel  1602  and gate  1612  can be formed directly on substrate  1606  or on an insulating or dielectric layer  1622 , such as a buried oxide layer, formed on or over the substrate. 
     Referring to  FIG. 16B , the multi-layer charge storing layer  1614  includes at least one lower or bottom charge-trapping layer  1624  including nitride closer to the tunnel oxide layer  1616 , and an upper or top charge-trapping layer  1626  overlying the bottom charge-trapping layer. Generally, the top charge-trapping layer  1626  includes a silicon-rich, oxygen-lean nitride layer and includes a majority of a charge traps distributed in multiple charge-trapping layers, while the bottom charge-trapping layer  1624  includes an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the top charge-trapping layer to reduce the number of charge traps therein. By oxygen-rich it is meant wherein a concentration of oxygen in the bottom charge-trapping layer  1624  is from about 15 to about 40%, whereas a concentration of oxygen in top charge-trapping layer  1626  is less than about 5%. 
     In one embodiment, the blocking dielectric  1618  also includes an oxide, such as an HTO, to provide an ONNO structure. The channel  1602  and the overlying ONNO structure can be formed directly on a silicon substrate  1606  and overlaid with a doped polysilicon gate layer  1620  to provide a SONNOS structure. 
     In some embodiments, such as that shown in  FIG. 16B , the multi-layer charge storing layer  1614  further includes at least one thin, intermediate or anti-tunneling layer  1628  including a dielectric, such as an oxide, separating the top charge-trapping layer  1626  from the bottom charge-trapping layer  1624 . As noted above, the anti-tunneling layer  1628  substantially reduces the probability of electron charge that accumulates at the boundaries of the upper nitride layer  1626  during programming from tunneling into the bottom nitride layer  1624 . 
     As with the embodiments described above, either or both of the bottom charge-trapping layer  1624  and the top charge-trapping layer  1626  can include silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The top charge-trapping layer  1626  has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the bottom charge-trapping layer  1624 , and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3  and N 2 O/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer. 
     In those embodiments including an intermediate or anti-tunneling layer  1628  including oxide, the anti-tunneling layer can be formed by oxidation of the bottom oxynitride layer, to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800-900 degrees Celsius using a batch reactor tool. A mixture of H 2  and O 2  gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Torr using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min−1 hour using a batch process. 
     Finally, in those embodiments including a blocking dielectric  1618  including oxide the oxide may be formed or deposited by any suitable means. In one embodiment the oxide of the blocking dielectric  1618  is a high temperature oxide deposited in a HTO CVD process. Alternatively, the blocking dielectric  1618  or blocking oxide layer may be thermally grown, however it will be appreciated that in this embodiment the top nitride thickness may be adjusted or increased as some of the top nitride will be effectively consumed or oxidized during the process of thermally growing the blocking oxide layer. A third option is to oxidize the top nitride layer to a chosen depth using radical oxidation. 
     A suitable thickness for the bottom charge-trapping layer  1624  may be from about 30 Å to about 160 Å (with some variance permitted, for example ±10 Å), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer  1628 . A suitable thickness for the top charge-trapping layer  1626  may be at least 30 Å. In certain embodiments, the top charge-trapping layer  1626  may be formed up to 130 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric  1618 . A ratio of thicknesses between the bottom charge-trapping layer  1624  and top charge-trapping layer  1626  is approximately 1:1 in some embodiments, although other ratios are also possible. 
     In other embodiments, either or both of the top charge-trapping layer  1626  and the blocking dielectric  1618  may include a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
     In another embodiment, shown in  FIGS. 17A and 17B , the memory device can include a nanowire channel formed from a thin film of semiconducting material overlying a surface on a substrate connecting a source and a drain of the memory device. By nanowire channel it is meant a conducting channel formed in a thin strip of crystalline silicon material, having a maximum cross-sectional dimension of about 10 nanometers (nm) or less, and more preferably less than about 6 nm. Optionally, the channel can be formed to have &lt;100&gt; surface crystalline orientation relative to a long axis of the channel. 
     Referring to  FIG. 17A , the memory device  1700  includes a horizontal nanowire channel  1702  formed from a thin film or layer of semiconducting material on or overlying a surface on a substrate  1706 , and connecting a source  1708  and a drain  1710  of the memory device. In the embodiment shown, the device has a gate-all-around (GAA) structure in which the nanowire channel  1702  is enclosed on all sides by a gate  1712  of the device. The thickness of the gate  1712  (measured in the direction from source to drain) determines the effective channel length of the device. 
     In accordance with the present disclosure, the non-planar multigate memory device  1700  of  FIG. 17A  can include a split charge-trapping region.  FIG. 17B  is a cross-sectional view of a portion of the non-planar memory device of  FIG. 17A  including a portion of the substrate  1706 , nanowire channel  1702  and the gate  1712  illustrating a split charge-trapping region. Referring to  FIG. 17B , the gate  1712  includes a tunnel oxide  1714  overlying the nanowire channel  1702 , a split charge-trapping region, a blocking dielectric  1716  and a gate layer  1718  overlying the blocking layer to form a control gate of the memory device  1700 . The gate layer  1718  can comprise a metal or a doped polysilicon. The split charge-trapping region includes at least one inner charge-trapping layer  1720  comprising nitride closer to the tunnel oxide  1714 , and an outer charge-trapping layer  1722  overlying the inner charge-trapping layer. Generally, the outer charge-trapping layer  1722  comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the inner charge-trapping layer  1720  comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the outer charge-trapping layer to reduce the number of charge traps therein. 
     In some embodiments, such as that shown, the split charge-trapping region further includes at least one thin, intermediate or anti-tunneling layer  1724  comprising a dielectric, such as an oxide, separating outer charge-trapping layer  1722  from the inner charge-trapping layer  1720 . The anti-tunneling layer  1724  substantially reduces the probability of electron charge that accumulates at the boundaries of outer charge-trapping layer  1722  during programming from tunneling into the inner charge-trapping layer  1720 , resulting in lower leakage current. 
     As with the embodiment described above, either or both of the inner charge-trapping layer  1720  and the outer charge-trapping layer  1722  can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. The second nitride layer of the multi-layer charge storing structure is then formed on the middle oxide layer. The outer charge-trapping layer  1722  has a stoichiometric composition of oxygen, nitrogen and/or silicon different from that of the inner charge-trapping layer  1720 , and may also be formed or deposited by a CVD process using a process gas including DCS/NH 3  and N 2 O/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich, oxygen-lean top nitride layer. 
     In those embodiments including an intermediate or anti-tunneling layer  1724  comprising oxide, the anti-tunneling layer can be formed by oxidation of the inner charge-trapping layer  1720 , to a chosen depth using radical oxidation. Radical oxidation may be performed, for example, at a temperature of 1000-1100 degrees Celsius using a single wafer tool, or 800-900 degrees Celsius using a batch reactor tool. A mixture of H 2  and O 2  gasses may be employed at a pressure of 300-500 Tor for a batch process, or 10-15 Tor using a single vapor tool, for a time of 1-2 minutes using a single wafer tool, or 30 min−1 hour using a batch process. 
     Finally, in those embodiments in which the blocking dielectric  1716  comprises oxide, the oxide may be formed or deposited by any suitable means. In one embodiment the oxide of blocking dielectric  1716  is a high temperature oxide deposited in a HTO CVD process. Alternatively, the blocking dielectric  1716  or blocking oxide layer may be thermally grown, however it will be appreciated that in this embodiment the thickness of the outer charge-trapping layer  1722  may need to be adjusted or increased as some of the top nitride will be effectively consumed or oxidized during the process of thermally growing the blocking oxide layer. 
     A suitable thickness for the inner charge-trapping layer  1720  may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 Å), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer  1724 . A suitable thickness for the outer charge-trapping layer  1722  may be at least 30 Å. In certain embodiments, the outer charge-trapping layer  1722  may be formed up to 170 Å thick, of which 30-70 Å may be consumed by radical oxidation to form the blocking dielectric  1716 . A ratio of thicknesses between the inner charge-trapping layer  1720  and the outer charge-trapping layer  1722  is approximately 1:1 in some embodiments, although other ratios are also possible. 
     In other embodiments, either or both of the outer charge-trapping layer  1722  and the blocking dielectric  1716  may comprise a high K dielectric. Suitable high K dielectrics include hafnium based materials such as HfSiON, HfSiO or HfO, Zirconium based material such as ZrSiON, ZrSiO or ZrO, and Yttrium based material such as Y 2 O 3 . 
       FIG. 17C  illustrates a cross-sectional view of a vertical string of non-planar multigate devices  1700  of  FIG. 17A  arranged in a Bit-Cost Scalable or BiCS architecture  1726 . The architecture  1726  consists of a vertical string or stack of non-planar multigate devices  1700 , where each device or cell includes a channel  1702  overlying the substrate  1706 , and connecting a source and a drain (not shown in this figure) of the memory device, and having a gate-all-around (GAA) structure in which the nanowire channel  1702  is enclosed on all sides by a gate  1712 . The BiCS architecture reduces number of critical lithography steps compared to a simple stacking of layers, leading to a reduced cost per memory bit. 
     In another embodiment, the memory device is or includes a non-planar device comprising a vertical nanowire channel formed in or from a semiconducting material projecting above or from a number of conducting, semiconducting layers on a substrate. In one version of this embodiment, shown in cut-away in  FIG. 18A , the memory device  1800  comprises a vertical nanowire channel  1802  formed in a cylinder of semiconducting material connecting a source  1804  and drain  1806  of the device. The channel  1802  is surrounded by a tunnel oxide  1808 , a charge-trapping region  1810 , a blocking layer  1812  and a gate layer  1814  overlying the blocking layer to form a control gate of the memory device  1800 . The channel  1802  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or can include an annular layer formed over a cylinder of dielectric filler material. As with the horizontal nanowires described above, the channel  1802  can comprise polysilicon or recrystallized polysilicon to form a monocrystalline channel. Optionally, where the channel  1802  includes a crystalline silicon, the channel can be formed to have &lt;100&gt; surface crystalline orientation relative to a long axis of the channel. 
     In some embodiments, such as that shown in  FIG. 18B , the charge-trapping region  1810  can be a split charge-trapping region including at least a first or inner charge trapping layer  1816  closest to the tunnel oxide  1808 , and a second or outer charge trapping layer  1818 . Optionally, the first and second charge trapping layers can be separated by an intermediate oxide or anti-tunneling layer  1820 . 
     As with the embodiments described above, either or both of the first charge trapping layer  1816  and the second charge trapping layer  1818  can comprise silicon nitride or silicon oxynitride, and can be formed, for example, by a CVD process including N 2 O/NH 3  and DCS/NH 3  gas mixtures in ratios and at flow rates tailored to provide a silicon-rich and oxygen-rich oxynitride layer. 
     Finally, either or both of the second charge trapping layer  1818  and the blocking layer  1812  may comprise a high K dielectric, such as HfSiON, HfSiO, HfO, ZrSiON, ZrSiO, ZrO, or Y 2 O 3 . 
     A suitable thickness for the first charge trapping layer  1816  may be from about 30 Å to about 80 Å (with some variance permitted, for example ±10 Å), of which about 5-20 Å may be consumed by radical oxidation to form the anti-tunneling layer  1820 . A suitable thickness for the second charge trapping layer  1818  may be at least 30 Å, and a suitable thickness for the blocking dielectric  1812  may be from about 30-70 Å. 
     The memory device  1800  of  FIG. 18A  can be made using either a gate first or a gate last scheme.  FIGS. 19A-F  illustrate a gate first scheme for fabricating the non-planar multigate device of  FIG. 18A .  FIGS. 20A-F  illustrate a gate last scheme for fabricating the non-planar multigate device of  FIG. 18A . 
     Referring to  FIG. 19A , in a gate first scheme a first or lower dielectric layer  1902 , such as a blocking oxide, is formed over a first, doped diffusion region  1904 , such as a source or a drain, in a substrate  1906 . A gate layer  1908  is deposited over the first dielectric layer  1902  to form a control gate of the device, and a second or upper dielectric layer  1910  formed thereover. As with embodiments described above, the first and second dielectric layers  1902 ,  1910 , can be deposited by CVD, radical oxidation or be formed by oxidation of a portion of the underlying layer or substrate. The gate layer  1908  can comprise a metal deposited or a doped polysilicon deposited by CVD. Generally the thickness of the gate layer  1908  is from about 40-50 Å, and the first and second dielectric layers  1902 ,  1910 , from about 20-80 Å. 
     Referring to  FIG. 19B , a first opening  1912  is etched through the overlying gate layer  1908 , and the first and second dielectric layers  1902 ,  1910 , to the diffusion region  1904  in the substrate  1906 . Next, layers of a tunneling oxide  1914 , charge-trapping region  1916 , and blocking dielectric  1918  are sequentially deposited in the opening and the surface of the upper dielectric layer  1910  planarize to yield the intermediate structure shown in  FIG. 19C . 
     Although not shown, it will be understood that as in the embodiments described above the charge-trapping region  1916  can include a split charge-trapping region comprising at least one lower or bottom charge-trapping layer closer to the tunnel oxide  1914 , and an upper or top charge-trapping layer overlying the bottom charge-trapping layer. Generally, the top charge-trapping layer comprises a silicon-rich, oxygen-lean nitride layer and comprises a majority of a charge traps distributed in multiple charge-trapping layers, while the bottom charge-trapping layer comprises an oxygen-rich nitride or silicon oxynitride, and is oxygen-rich relative to the top charge-trapping layer to reduce the number of charge traps therein. In some embodiments, the split charge-trapping region  1916  further includes at least one thin, intermediate or anti-tunneling layer comprising a dielectric, such as an oxide, separating the top charge-trapping layer from the bottom charge-trapping layer. 
     Next, a second or channel opening  1920  is anisotropically etched through tunneling oxide  1914 , charge-trapping region  1916 , and blocking dielectric  1918 ,  FIG. 19D . Referring to  FIG. 19E , a semiconducting material  1922  is deposited in the channel opening to form a vertical channel  1924  therein. The vertical channel  1924  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material, or, as shown in  FIG. 19E , can include a separate, layer semiconducting material  1922  surrounding a cylinder of dielectric filler material  1926 . 
     Referring to  FIG. 19F , the surface of the upper dielectric layer  1910  is planarized and a layer of semiconducting material  1928  including a second, doped diffusion region  1930 , such as a source or a drain, formed therein deposited over the upper dielectric layer to form the device shown. 
     Referring to  FIG. 20A , in a gate last scheme a dielectric layer  2002 , such as an oxide, is formed over a sacrificial layer  2004  on a surface on a substrate  2006 , an opening etched through the dielectric and sacrificial layers and a vertical channel  2008  formed therein. As with embodiments described above, the vertical channel  2008  can include an annular region in an outer layer of a substantially solid cylinder of semiconducting material  2010 , such as polycrystalline or monocrystalline silicon, or can include a separate, layer semiconducting material surrounding a cylinder of dielectric filler material (not shown). The dielectric layer  2002  can comprise any suitable dielectric material, such as a silicon oxide, capable of electrically isolating the subsequently formed gate layer of the memory device  1800  from an overlying electrically active layer or another memory device. The sacrificial layer  2004  can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer  2002 , substrate  2006  and vertical channel  2008 . 
     Referring to  FIG. 20B , a second opening  2012  is etched through the etched through the dielectric and sacrificial layers  2002 ,  2004 , to the substrate  1906 , and the sacrificial layer  2004  etched or removed. The sacrificial layer  2004  can comprise any suitable material that can be etched or removed with high selectivity relative to the material of the dielectric layer  2002 , substrate  2006  and vertical channel  2008 . In one embodiment the sacrificial layer  2004  comprises that can be removed by Buffered Oxide Etch (BOE etch). 
     Referring to  FIGS. 20C and 20D , layers of a tunneling oxide  2014 , charge-trapping region  2016 , and blocking dielectric  2018  are sequentially deposited in the opening and the surface of the dielectric layer  2002  planarize to yield the intermediate structure shown in  FIG. 20C . In some embodiments, such as that shown in  FIG. 20D , the charge-trapping region  2016  can be a split charge-trapping region including at least a first or inner charge trapping layer  2016   a  closest to the tunnel oxide  2014 , and a second or outer charge trapping layer  2016   b . Optionally, the first and second charge trapping layers can be separated by an intermediate oxide or anti-tunneling layer  2020 . 
     Next, a gate layer  2022  is deposited into the second opening  2012  and the surface of the upper dielectric layer  2002  planarized to yield the intermediate structure illustrated in  FIG. 20E . As with embodiments described above, the gate layer  2022  can comprise a metal deposited or a doped polysilicon. Finally, an opening  2024  is etched through the gate layer  2022  to form control gate of separate memory devices  2026 . 
     Thus, a method for fabricating a nonvolatile charge trap memory device has been disclosed. In accordance with an embodiment of the present invention, a substrate is subjected to a first radical oxidation process to form a first dielectric layer in a first process chamber of a cluster tool. A charge-trapping layer may then be deposited above the first dielectric layer in a second process chamber of the cluster tool. In one embodiment, the charge-trapping layer is then subjected to a second radical oxidation process to form a second dielectric layer above the charge-trapping layer by oxidizing a portion of the charge-trapping layer in the first process chamber of the cluster tool. By forming all layers of an oxide-nitride-oxide (ONO) stack in a cluster tool, interface damage may be reduced between the respective layers. Thus, in accordance with an embodiment of the present invention, an ONO stack is fabricated in a single pass in a cluster tool in order to preserve a pristine interface between the layers in the ONO stack. In a specific embodiment, the cluster tool is a single-wafer cluster tool.