Patent Publication Number: US-2011069759-A1

Title: Interpolation method and video codec device using the same

Description:
BACKGROUND 
     1. Technical Field 
     Embodiments of the present disclosure relate to video codec devices, and particularly to an interpolation method and a video codec device using the same. 
     2. Description of Related Art 
     In order to improve codec performance, video codec devices usually compare full, half and quarter pixels of macro blocks of a current frame with those of reference frames so as to determine the macro blocks most similar to that of the current frame, known as “best prediction macro blocks”. 
     Referring to  FIG. 5 , a commonly used interpolation method for generating the half and quarter pixels is shown, wherein capital letters A-T indicate the full pixels, single small letters a-n indicate the half pixels, and dual small letters aa-qq indicate the quarter pixels. In order to acquire each quarter pixel, a commonly used video codec device performs a half interpolation and a quarter interpolation according to the H.264 standard. For example, in order to acquire the quarter pixel aa, the half interpolation upon the full pixels E, F, G, H, I and J is executed to generate the half pixel a, then the quarter interpolation upon the full pixel G and the half pixel a is executed to generate the quarter pixel aa. 
     It is obvious that the half pixels a, b, d and e are also required for the quarter interpolation to generate the quarter pixels of adjacent macro blocks. However, the commonly used video codec device must repeat the half interpolations to generate the half pixels a, b, d and e, then the quarter interpolations upon the half pixels a, b, d and e and the full pixels to generate the quarter pixels of adjacent macro blocks. Therefore, the half and quarter interpolations of the video codec device are often computationally complex and inefficient. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Many aspects of the embodiments can be better understood with references to the following drawings, wherein like numerals depict like parts, and wherein: 
         FIG. 1  is a schematic diagram of a video codec device in accordance with one embodiment of the present disclosure; 
         FIG. 2  is a flowchart of an interpolation method in accordance with one embodiment of the present disclosure; 
         FIG. 3  is a detailed flowchart of half interpolations of the interpolation method in accordance with one embodiment of the present disclosure; 
         FIG. 4  is a detailed flowchart of quarter interpolations of the interpolation method in accordance with one embodiment of the present disclosure; and 
         FIG. 5  illustrates a commonly used interpolation method for generating the half and quarter pixels. 
     
    
    
     DETAILED DESCRIPTION 
     Referring to  FIG. 1 , a schematic diagram of a video codec device  10  in accordance with the present disclosure is shown. The video codec device  10  performs half and quarter interpolations to generate half and quarter pixels of reference frames stored in a reference frame register  600 . In one embodiment, the video device  10  comprises a controller  100 , a full pixel register  200 , an interpolation filter array  300 , a half pixel register  400  and a result register  500 . 
     The controller  100  controls operations of the full pixel register  200 , the interpolation filter array  300 , the half pixel register  400  and the result register  500 . 
     The full pixel register  200  reads full pixels of the reference frames from the reference frame register  600 , and transmits the full pixels required for the half and quarter interpolations to the interpolation filter array  300 . 
     The interpolation filter array  300  performs the half interpolations to generate the half pixels of the reference frames to the half pixel register  400 . The interpolation filter array  300  performs the quarter interpolations to generate the quarter pixels of the reference frames to the result pixel register  500 . The interpolation filter array  300  comprises a plurality of pixel load circuits to load pixels in parallel, and a plurality of interpolation filters to perform the half or quarter interpolation in parallel correspondingly. 
     In one embodiment, the interpolation filter array  300  comprises four pixel load circuits  310 - 340  and four interpolation filters  350 - 380  correspondingly. The pixel load circuits  310 - 340  are connected to the full pixel register  200  in parallel, each of which individually loads the full pixels of the reference frames from the full pixel register  200  in a pipeline operation. Additionally, the pixel load circuits  310 - 340  are connected to the half pixel register  400  in parallel, and individually load the half pixels of the reference frames from the half pixel register  400  in a pipeline operation. The interpolation filters  350 - 380  are correspondingly connected to the pixel load circuits  310 - 340 , respectively. The interpolation filters  350 - 380  read the full pixels loaded by the corresponding pixel load circuits  310 - 340 , and perform the half interpolations upon the full pixels to generate the half pixels of the reference frames, which are stored in the half pixel register  400 . Then, the interpolation filters  350 - 380  further read the full and half pixels loaded by the corresponding pixel load circuits  310 - 340 , and perform the quarter interpolations upon the full and half pixels to generate the quarter pixels of the reference frames, which are stored in the result register  500 . 
     The half pixel register  400  receives and stores the half pixels generated by the interpolation filer array  300 . In this embodiment, the half pixel register  400  further provides the half pixels required for the subsequent quarter interpolations to the interpolation filter array  300  so as to avoid repeated half interpolations in the commonly used video codec devices. 
     The result register  500  receives and stores the quarter pixels generated by the interpolation filter array  300 . In this embodiment, when all the quarter interpolations of the reference frame are completed, the half pixel register  400  transfers the half pixels to the result register  500 , and the result register  500  receives and stores the half pixels. 
     In the embodiment, the video codec device  10  performs the half interpolations upon the full pixels to generate the half pixels of the reference frames, and stores the generated half pixels in the half pixel register  400 . When all the half interpolations of the reference frame are completed, the video codec device  10  performs the quarter interpolations upon the full pixels and the stored half pixels to generate the quarter pixels of the reference frame, and stores the generated quarter pixels in the result register  500 . 
     In the half interpolations of the reference frame, the full pixel register  200  reads the full pixels of the reference frame required for the half and quarter interpolations from the reference frame register  600 . The interpolation filter array  300  loads the full pixels required for the half interpolations from the full pixel register  200 , and performs the half interpolations to generate the half pixels in batches. 
     In the embodiment, each of the pixel load circuits  310 - 340  loads a portion of full pixels required for a half interpolation, then each of the interpolation filters  350 - 380  correspondingly reads the loaded portion of full pixels and performs the half interpolation to generate a half pixel of the reference frame to the half pixel register  400 . The controller  100  determines whether all the half interpolations of the reference frame are completed. If the half interpolations of the reference frame are not all completed, each of the pixel load circuits  310 - 340  of the interpolation filter array  300  loads the next portion of full pixels required for next half interpolation. Then, each of the interpolation filters  350 - 380  of the interpolation filter array  300  correspondingly reads the next portion of full pixels loaded by the pixel load circuits  310 - 340 , and performs the next interpolation to generate another half pixel of the reference frame to the half pixel register  400 . 
     If all the half interpolations of the reference frame are completed, the video codec device  10  begins the quarter interpolations to generate the quarter pixels of the reference frame. In this embodiment, the generated half pixels of the reference frame are stored in the half pixel register  400 . 
     To obtain the quarter pixels of the reference frame, the interpolation filter array  300  loads the full pixels from the full pixel register  200  and the half pixels from the half pixel register  400 , and performs the quarter interpolations to generate the quarter pixels of the reference frame in batches. The generated quarter pixels are stored in the result register  500 . 
     Each of the pixel load circuits  310 - 340  of the interpolation filter array  300  loads a portion of full and half pixels required for a quarter interpolation. In the embodiment, the full pixels are loaded from the full pixel register  200 , and the half pixels are loaded from the half pixel register  400 . Each of the interpolation filters  350 - 380  of the interpolation filter array  300  correspondingly reads the portion of full and half pixels loaded by the pixel load circuits  310 - 340 , and performs the quarter interpolation to generate a quarter pixel of the reference frame to the result register  500 . The controller  100  determines whether all the quarter interpolations of the reference frame are completed. If the quarter interpolations of the reference frame are not completed, each of the pixel load circuits  310 - 340  of the interpolation filter array  300  loads the next portion of full and half pixels required for next quarter interpolation. Then, each of the interpolation filters  350 - 380  of the interpolation filter array  300  correspondingly reads the next portion of full and half pixels loaded by the pixel load circuits  310 - 340 , and performs the next quarter interpolation to generate another quarter pixel of the reference frame to the result register  500 . 
     If all the quarter interpolations of the reference frame are completed, the half pixel register  300  transfers the half pixels of the reference frame to the result register  500 . Then, the half pixels and quarter pixels of the reference frame are stored in the result register  500 . 
     Referring to  FIG. 2 , a flowchart of an interpolation method to generate the half and quarter pixels in accordance with the present disclosure is shown. In the embodiment, the interpolation method comprises a plurality of steps as follows. 
     In step S 201 , the full pixel register  200  reads the full pixels required for the half interpolations and quarter interpolations of a reference frame from the reference frame register  600 . 
     In step S 202 , the interpolation filter array  300  loads the full pixels from the full pixel register  200 , and performs the half interpolations to generate the half pixels in batches. The generated half pixels of the reference frame are stored in the half pixel register  400 . 
     In step S 203 , when all the half interpolations of the reference frame are completed, the interpolation filter array  300  loads the full pixels from the full pixel register  200  and the half pixels from the half pixel register  400 , and performs the quarter interpolations to generate the quarter pixels of the reference frames in batches. The generated quarter pixels are stored in the result register  500 . 
     In step S 204 , when all the quarter interpolations of the reference frame are completed, the half pixel register  400  transfers the half pixels of the reference frame to the result pixel register  500 . 
     Referring to  FIG. 3 , a detailed flowchart of the half interpolations of the interpolation method in accordance with the present disclosure is shown. In the embodiment, the half interpolations of the interpolation method comprise a plurality of steps as follows. 
     In step S 301 , each of the pixel load circuits  310 - 340  of the interpolation filter array  300  loads a portion of full pixels required for a half interpolation from the full pixel register  200 . 
     In step S 302 , each of the interpolation filters  350 - 380  of the interpolation filter array  300  correspondingly reads the portion of full pixels loaded by the pixel load circuits  310 - 340 . 
     In step S 303 , each of the interpolation filters  350 - 380  of the interpolation filter array  300  performs the half interpolation upon the portion of full pixels to generate a half pixel to the half pixel register  400 . 
     In step S 304 , the controller  100  determines whether all the half interpolations of the reference frame are completed. If the half interpolations of the reference frame are not all completed, each of the pixel load circuits  310 - 340  of the interpolation array  300  loads the next portion of full pixels required for next half interpolation, and performs the next half interpolation to generate another half pixel to the half pixel register  300 . If all the half interpolations of the reference frame are completed, the video codec device  10  begins performing the quarter interpolations of the reference frame. In the embodiment, the generated half pixels of the reference frame are stored in the half pixel register  400 . 
     Referring to  FIG. 4 , a detailed flowchart of the quarter interpolations of the interpolation method in accordance with the present disclosure is shown. In the embodiment, the quarter interpolations of the interpolation method comprise a plurality of steps as follows. 
     In step S 401 , each of the pixel load circuits  310 - 340  of the interpolation filter array  300  loads a portion of full and half pixels required for a quarter interpolation. In the embodiment, the full pixels are loaded from the full pixel register  200 , and the half pixels are loaded from the half pixel register  400 . 
     In step S 402 , each of the interpolation filters  350 - 380  of the interpolation filter array  300  reads the portion of full and half pixels loaded by the corresponding pixel load circuits  340 - 380 . 
     In step S 403 , each of the interpolation filters  350 - 380  of the interpolation filter array  300  performs the quarter interpolation to generate a quarter pixel of the reference frame to the result register  500 . 
     In step S 404 , the controller  100  determines whether all the quarter interpolations of the reference frame are completed. If the quarter interpolations of the reference frame are not all completed, then each of the pixel load circuits  310 - 340  loads the next portion of full and half pixels required for next quarter interpolation, and performers the next quarter interpolation to generate another quarter pixel to the result register  500 . If all the quarter interpolations of the reference frame are completed, the half pixel register  400  transfers all the half pixels of the reference frame to the result register  500 . 
     It is apparent that the present disclosure provides an interpolation method and a video codec device using the same operable to perform the quarter interpolations utilizing generated half pixels stored in a half pixel register. Therefore, computational complexity and intensity of the quarter interpolations decrease with elimination of repeated half interpolations, and efficiency of the video codec devices increases. 
     While the present disclosure has been described in combination with embodiments thereof, it is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations as fall within the spirit and scope of the appended claims.