Patent Publication Number: US-2013249031-A1

Title: Quantum Efficiency Back Side Illuminated CMOS Image Sensor And Package, And Method Of Making Same

Description:
FIELD OF THE INVENTION 
     The present invention relates to CMOS image sensors, and more particularly to a back side illuminated image sensor and packaging configuration. 
     BACKGROUND OF THE INVENTION 
     The trend for semiconductor devices is smaller integrated circuit (IC) devices (also referred to as chips), packaged in smaller packages (which protect the chip while providing off chip signaling connectivity). One example are image sensors, which are IC devices that include photo-detectors which transform incident light into electrical signals (that accurately reflect the intensity and color information of the incident light with good spatial resolution). Image sensors can be front side illuminated (FSI) or back side illuminated (BSI). 
     A conventional front side illuminated (FSI) image sensor has photo-detectors formed at the surface of silicon chip at which light being imaged is incident. The supporting circuitry for the photo-detectors is formed over the photo-detectors, where apertures (i.e. lightpipes) allow light to pass through the circuitry layers to reach the photo-detectors. The color filters and micro-lens are disposed over the surface containing the photo-detectors. The drawback with FSI image sensors is that the circuitry layers limit the size of the aperture through which incident light for each pixel must travel. As pixel size shrinks due to demands for higher numbers of pixels and smaller chip sizes, the ratio of pixel area to the overall sensor area decreases. This reduces the quantum efficiency (QE) of the sensor. 
     A conventional back side illuminated (BSI) image sensor is similar to an FSI image sensor, except the photo-detectors receive light through the back surface of the chip (i.e. the light enters the back surface of the chip, and travels through the silicon substrate until it reaches the photo-detectors). The color filters and micro-lens are mounted to the back surface of the chip. With this configuration, the incident light avoids the circuitry layers. However, the drawbacks with BSI image sensors include pixel cross-talk caused by diffusion in the silicon substrate (i.e. there is no circuitry or other structure that forms apertured openings to segregate the propagating light for each pixel—blue light is especially susceptible to this diffusion phenomenon) and the need for a thicker micro-lens due to shorter optical paths. 
     Another significant issue with BSI image sensors is that the quantum efficiency of different colors of light passing through the silicon substrate varies because the amount of the light absorbed (i.e. attenuated) by the silicon varies based upon wavelength. This means that with a uniform thickness silicon substrate, the amount of absorption of red, green and blue colors headed for the photo-detectors is not the same. In order to equalize attenuation, the different colors would have to pass through different thicknesses of the silicon. The absorption coefficients for silicon, and thickness ratios of silicon for equalizing attenuation, are provided in the table below for three different colors of light: 
                                         TABLE 1                           Exemplary                       Wavelength   Absorption coefficient   Thickness           Color   (nm)   (1/cm)   ratio                                                            Blue   475   16,000   1.00           Green   510   9700   1.65           Red   650   2810   5.70                        
From the above, as an example, a silicon thickness of 1 μm for blue, 1.65 μm for green and 5.70 μm for red would yield a uniform absorption for all three color wavelengths. Another measure of absorption is “absorption depth,” which is the thickness of the substrate at which about 64% (1-1/e) of the original intensity is absorbed, and about 36% (1/e) gets through. The table shows that a silicon thickness of 0.625 μm for the blue, 1.03 μm for the green and 3.56 μm for the red would yield a uniform absorption of about 64%, with 36% of the light making it through the silicon.
 
     There is a need for an improved BSI image sensor configuration to make absorption of incident light through the silicon substrate substantially uniform for multiple wavelengths. There is also a need for an improved package and packaging technique for BSI image sensor chips that can provide a low profile wafer level packaging solution that is cost effective and reliable (i.e. provides the requisite mechanical support and electrical connectivity), which means that packaging solution will need to be able to integrate front end and back end processes. 
     BRIEF SUMMARY OF THE INVENTION 
     The aforementioned problems and needs are addressed by an improved image sensor device, which includes a substrate with front and back opposing surfaces, a plurality of photo detectors formed at the front surface, a plurality of contact pads formed at the front surface which are electrically coupled to the photo detectors, a plurality of cavities each formed into the back surface and over one of the photo detectors, absorption compensation material disposed in the cavities wherein the absorption compensation material has light absorption characteristics that differ from those of the substrate, and a plurality of color filters each disposed over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. 
     In another aspect of the present invention, a method of forming an image sensor device includes providing a substrate with front and back opposing surfaces, forming a plurality of photo detectors at the front surface, forming a plurality of contact pads at the front surface which are electrically coupled to the photo detectors, forming a plurality of cavities into the back surface wherein each of the cavities is disposed over one of the photo detectors, forming absorption compensation material in each of the cavities, wherein the absorption compensation material has light absorption characteristics that differ from those of the substrate, and attaching a plurality of color filters to the substrate wherein each of the color filters is disposed over one of the photo detectors. The plurality of photo detectors are configured to produce electronic signals in response to light incident through the color filters. 
     Other objects and features of the present invention will become apparent by a review of the specification, claims and appended figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A-1G  are cross sectional side views showing in sequence the steps in forming the packaged image sensor. 
         FIGS. 2A-2E  are cross sectional side views showing in sequence the steps in forming an alternate embodiment of the packaged image sensor. 
         FIGS. 3A-3D  are cross sectional side views showing in sequence the steps in forming a second alternate embodiment of the packaged image sensor. 
         FIGS. 4-6  are cross sectional side views of alternate embodiments of those in  FIGS. 1G ,  2 E and  3 D, respectively, where the secondary cavities are formed into the back surface of the substrate. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The present invention is an improved BSI image sensor and packaging which reduces the amount of substrate attenuation variations based upon wavelength, and method of making the same. 
     The method of fabricating the packaged image sensor involves the simultaneous manufacturing and packaging of the BSI image sensor. The method begins with a conventional BSI image sensor chip  10  illustrated in  FIG. 1A . Chip  10  includes a substrate  12  on which a plurality of photo detectors  14  and supporting circuitry  16  are formed, along with contact pads  18 . The photo detectors  14 , supporting circuitry  16  and contact pads  18  are formed at the downwardly facing (front) surface  12   a  of substrate  12 . Preferably, all the supporting circuitry  16  is formed below photo detectors  14  (closer to the front surface  12   a ) so that circuitry  16  does not obstruct light entering through the back surface  12   b  and traveling through substrate  10  toward the photo detectors  14 . The contact pads  18  are electrically coupled to the photo detectors  14  via supporting circuitry  16  for providing off chip signaling. Each photo detector  14  converts light energy incident on back surface  12   b  and reaching the photo detectors  14  to a voltage and/or current signal. Additional circuitry on the chip may be included to amplify the voltage, and/or convert it to digital data. BSI image sensors of this type are well known in the art, and not further described herein. 
     A handler  20  is affixed to the front surface  12   a  of substrate  12  using a bonding interface  22 . Handler  20  may be made of ceramic or crystalline material. Bonding interface  22  can be, for example, silicon dioxide, epoxy composites, polyamide or any other dielectric material that can withstand temperatures up to 200° C. An optional thinning process can then be used to reduce the thicknesses of substrate  12  and handler  20  (i.e. by grinding or etching back surface  12   b  of substrate  12  and the bottom surface of handler  20 ). In a preferred embodiment, the substrate  12  would preferably have a thickness equal to or greater than 10 μm and the remaining handler  20  would preferably have a thickness equal to or greater than 50 μm. The resulting structure is shown in  FIG. 1B . 
     Holes  24  (i.e. vias) are then formed into the back surface  12   b  that extend down to and expose contact pads  18 . Holes  24  can be formed by the use of a laser, a plasma etching process, a sandblasting process, a mechanical milling process, or any other similar method. Preferably holes  24  are formed by photo-lithography plasma etching, which includes forming a layer of photo resist on the back surface  12   b  of substrate  12 , patterning the photo resist layer to expose selected portions of surface  12   b , and then performing a plasma etch process (e.g. BOSCH process, which uses combination of SF6 and C4F8 gases) to remove the exposed portions of substrate  12  until contact pads  18  are exposed at the bottoms of the holes. An isolation (dielectric) layer  26  is then deposited/formed and patterned on the back surface  12   b  (including the side walls of holes  24 ). Layer  26  can be Si oxide, Si nitride, epoxy based, polyimide, resin or any other appropriate dielectric material(s). Preferably, dielectric layer  26  is SiO 2  with at least a 0.5 μm thickness, which is formed by using of a PECVD deposition technique (which is well known in the art), followed by lithography process that removes the dielectric material from select portions of surface  12   b  and the bottoms of holes  24 . The resulting structure is shown in  FIG. 1C . 
     A cavity  28  is then formed into that portion of the surface  12   b  over photo detectors  14 . Cavity  28  can be formed by the use of a laser, a plasma etching process, a sandblasting process, a mechanical milling process, or any other similar method. Preferably cavity  28  is formed by photo-lithography plasma etching which leaves a minimum thickness at the maximum depth portion of the cavity of around 10 μm (i.e. cavity  28  has a bottom surface  28   a  around 10 μm from front surface  12   a ). Alternately, the plasma etching process can be performed without a photo-lithography step by using dielectric layer  26  as the selective mechanism (i.e. the gap in dielectric layer  26  on surface  12   b  defines those portions of substrate  12  exposed to and subject to the plasma etch). Secondary cavities  30  are then formed into selected portions of the bottom surface  28   a  of cavity  28 , preferably by one or more lithography and plasma etching processes or any other similar methods. Each of the secondary cavities  30  is disposed over one or more of the photo-detectors  14 . The depth of each secondary cavity  30  will vary depending upon the color of light that the corresponding photo-detector  14  underneath will be measuring. As a non-limiting example, in the case of RGB photo detectors, secondary cavities  30  having a depth of 5 to 6 μm are formed over the red light photo detectors (i.e. those associated with a red filter described below), secondary cavities  30  having a depth of 1.5 to 2 μm are formed over the green light photo detectors (i.e. those associated with a green filter described below), and no secondary cavities are formed over the blue light photo detectors (i.e. those associated with a blue filter described below). The resulting structure is shown in  FIG. 1D . 
     An absorption compensation material  32  is deposited inside secondary cavities  30 . Material  32  can be any material that has light absorption characteristics that differ from those of silicon substrate  12  (e.g. absorption coefficients at various frequencies that differ from those of silicon). Material  32  can be a polymer, epoxy based, a resin or any other appropriate material(s) with the desired light absorption characteristics. Preferably, material  32  is polymer which is formed by using a spray deposition technique (which is well known in the art), followed by lithography removal process such that the secondary cavities  30  are filled with the material  32  (i.e. up to the bottom surface  28   a  of cavity  28 ). A color filter  34  and microlens  36  are mounted inside cavity  28  over each photo detector  14  (i.e. over each filled secondary cavity  30 ) using conventional filter/lens manufacturing processes (which are well known in the art). The microlenses  36  can be separate from each other or integrally formed together. Similarly, adjacent color filters  34  for the same color can be separate from each other or integrally formed together. While each microlenses  36  is shown as being disposed over one color filter  34  and one photo detector  14 , a single microlenses  36  could be disposed over a plurality of color filters  34  and a plurality of photo detectors  14 . An optional anti-reflective coating may be applied to or included on microlenses  36 , or between color filter  34  and either material  32  or surface  28   a . An optically transparent substrate (e.g. glass)  38  is then bonded on or over the substrate back surface  12   b  (i.e. over cavity  28 ) using a joining interface (not shown) such as polyimide, resin, epoxy based or any other appropriate joining material(s). Optical transparency means that at least one range of light wavelengths can pass through the substrate  38  with at most only tolerable absorption losses for the desired wavelengths. The resulting structure is shown in  FIG. 1E . 
     Preferably, multiple image sensor chips are fabricated as individual die on a single wafer. At this stage of processing, the wafer level assembled structures are separated (i.e. diced, singulated, etc.) to form the individual packages. This procedure can be completed by use of conventional wafer dicing and/or laser equipment, which separates the individual die along die lines  40 , as shown in  FIG. 1F . The die can be tested either before or after dicing, and known good sensor chips are then removed and placed in the trays for future assembly. 
     The known good image sensor chip  10  is next attached to a host board (e.g. a printed circuit board)  42  which includes contact pads  44  and electrical traces (not shown) for off chip signaling. Wires  46  are connected between (and provide an electrical connection between) the contact pads  18  of the image sensor chip  10  and the respective contact pads  44  of host board  42 . Wires  46  can be alloyed gold, copper or any other appropriate wire bonding material, and are formed by using any conventional wire bonding technique (which are well known in the art). A lens module assembly  48  is then affixed or assembled over the optically transparent substrate  38 , preferably using a joining material such as epoxy. The lens module assembly  48  includes one or more lenses  50  (for focusing light onto the photo detectors  14 ) and a transparent substrate  52  over the lens(es)  50 . The final structure is illustrated in  FIG. 1G . 
     In operation, incident light is focused by lens module  48 , through substrate  38 , through microlenses  36  and color filters  34 , through material  32  (if any), through any of the substrate  12  and into photo detectors  14 , which in turn provide electrical signals in response to the incident light. The electrical signals are processed by supporting circuitry  16 , and transferred off-chip via contact pads  18 , wires  46 , and contact pads  44 . 
     The main advantage of the package structure of  FIG. 1G  is that the varying depths of material  32  (which can be accurately controlled) disposed over the photo detectors  14  result in substantially the same absorption for all colors of light. For example, assuming the material  32  has higher absorption coefficients than silicon, then the thickness of material  32  over the red pixel photo detectors  14  (i.e. those photo detectors  14  with a red color filter  34 ) would be the greatest, the thickness of material  32  over the green pixel photo detectors (i.e. those photo detectors  14  with a green color filter  34 ) would be less than that for the red pixel photo detectors, and the thickness of the material  32  over the blue pixel photo detectors (i.e. those photo detectors  14  with a blue color filter  34 ) would be the least of the three or even zero (i.e. no material  32  over the blue pixel photo detectors because no secondary cavities  30  were formed over these photo detectors). With this configuration, all three colors of light would be equally or near equally attenuated as they pass through the silicon substrate  10  and any material  32  because the increased depths of material  32  would attenuate the red and green light to match the intensity of blue light reaching the photo detectors. Suitable materials  32  having absorption coefficients higher than silicon include organic and inorganic polymers or semiconductor doping materials. 
     As another example, assuming the material  32  has lower absorption coefficients than silicon, then the thickness of material  32  over the blue pixel photo detectors  14  would be the greatest, the thickness of material  32  over the green pixel photo detectors would be less than that for the blue pixel photo detectors, and the thickness of the material  32  over the red pixel photo detectors would be the least of the three or even zero (i.e. no material  32  over the red pixel photo detectors because no secondary cavities  30  were formed over these photo detectors). With this configuration, all three colors of light would be equally or near equally attenuated as they pass through the silicon substrate  10  and any material  32 . Materials  32  having absorption coefficients lower than silicon include organic and inorganic polymers. 
     Another advantage of the package structure of  FIG. 1G  is that each component can be separately fabricated and tested. Specifically, each image sensor chip  10  can be tested and verified before being affixed to board  42  and packaged with lens module assembly  48  (which are also fabricated and tested separately) so that only known good components preferably make it to final integration, thus increasing yield and pass rates, and decreasing costs. The package structure also has a low profile, provides the requisite mechanical support and electrical connectivity, and thus is more reliable and cost effective. 
       FIGS. 2A-2E  illustrate the fabrication of an alternate embodiment of the packaged image sensor. Starting with the structure illustrated in  FIG. 1C , a layer of conductive material  56  is deposited over the structure, including on the side and bottom walls of holes  24 , as illustrated in  FIG. 2A . Conductive layer  56  can be Cu, Ti/Cu, Ti/Al, Cr/Cu or other well-known conductive material(s). Deposition can be done by sputtering, plating or a combination of sputtering and plating. A patterned photo-lithography layer is deposited on top of conductive layer  56 , followed by an etch process to remove selected portions of layer  56 , leaving a plurality of conductive traces  58  each extending from contact pad  18  (at the bottom of hole  24 ), up the hole sidewall, and along subtrate back surface  12   b . The resulting structure is shown in  FIG. 2B . 
     The formation of cavity  28 , secondary cavities  30 , material  32 , color filters and microlenses  34 / 36 , and transparent substrate  38  are performed in a similar manner as that explained above with respect to  FIGS. 1D-1E , resulting in the structure shown in  FIG. 2C . A patterned encapsulation (dielectric) material is then formed on the back side of image sensor wafer by material deposition followed by selective removal via lithography, which leaves encapsulation material  60  disposed over substrate back surface  12   b  and preferably filling holes  24 . The encapsulant material  60  is also removed on selected portions of back surface  12   b  leaving selected portions of traces  58  exposed. Encapsulant material  60  is a dielectric material that can be epoxy based, polyimide, resin or any other appropriate insulation material(s). Preferably, encapsulant material  60  on back surface  12   b  is 5 μm to 40 μm in thickness, and fully encapsulates holes  24 . SMT (surface mount) interconnects  62  are next formed over back surface  12   b  in a manner such that each is in electrical contact with the exposed portion of one of the traces  58 . SMT interconnects  62  can be BGA type, and formed using a screen printing process of a solder alloy, or by a ball placement process, or by a plating process. BGA (Ball Grid Array) interconnects are rounded conductors for making physical and electrical contact with counterpart conductors, usually formed by soldering or partially melting metallic balls onto traces  58 . Alternately SMT interconnects  62  can be conductive metal posts (e.g. copper). The resulting structure is illustrated in  FIG. 2D . 
     After wafer dicing/singulation in a similar manner as discussed above with respect to  FIG. 1F , the image sensor chip  10  is attached to a host board  64 . Host board  64  includes electrical traces (not shown) with contact pads  66  that electrically connect to SMT interconnects  62  using conventional SMT or flip chip assembly techniques. Host board  64  includes an aperture  68  disposed over the photo detectors  14  through which the incident light passes. The lens module assembly  48  attaches to the host board such that the lens(es)  50  focus the incident light though aperture  68 , through transparent substrate  38 , through microlenses/color filters  36 / 34 , through material  32  (if any), through silicon substrate  12 , to photo detectors  14 . The final structure is shown in  FIG. 2E . The electrical signals from the photo detectors  14  are processed by supporting circuitry  16 , and transferred off-chip via contact pads  18 , traces  58 , SMT interconnect  62 , and contact pad  66  and traces on the host board  64 . 
       FIGS. 3A-3D  illustrate the fabrication of a second alternate embodiment of the packaged image sensor. The beginning structure is that shown in  FIG. 1E , except without the formation of holes  24  and dielectric layer  26  (as illustrated in FIG.  3 A—which instead shows the joining interface material  70  between the transparent substrate  38  and the substrate  12 ). Holes  70  are formed through handler  20  to expose contact pads  18 . Holes  70  can be formed by the use of a laser, a plasma etching process, a sandblasting process, a mechanical milling process, or any other similar method. Preferably holes  70  are formed by photo-lithography plasma etching, which includes forming a layer of photo resist on the handler, patterning the photo resist layer to expose select portions of permanent handler, and then performing a plasma etch process (e.g. BOSCH process, which uses combination of SF6 and C4F8 gases) to remove the exposed portions of the handler  20  to form holes  72 . An isolation (dielectric) layer  74  is deposited and patterned on the bottom surface of handler  20  (including inside holes  72 ). Layer  74  can be Si oxide, Si nitride, epoxy based, polyimide, resin or any other appropriate dielectric material(s). Preferably, dielectric layer is SiO 2  with a thickness at least 0.5 μm, which is formed by using a PECVD deposition technique (which is well known in the art), followed by a lithography process that removes the dielectric layer from the bottoms of holes  72  (to leave contact pads  18  exposed). The resulting structure is shown in  FIG. 3B . 
     A conductive material  76  is deposited on the dielectric layer  74 , preferably partially or fully filling holes  72 . The conductive material can be Cu, Ti/Cu, Ti/Al, Cr/Cu or other well-known conductive material(s). Deposition can be by sputtering, plating or a combination of sputtering and plating. A photo-lithography etch process is then used to selectively remove conductive material  76  except for inside holes  72  (and preferably a small portion extending out of holes  72  that form SMT compatible pads  78 ). A patterned encapsulation (dielectric) layer  80  is then deposited on the bottom surface of handler  20 , which can be epoxy based, polyimide, Fr4, resin or any other appropriate encapsulant material(s). Preferably, encapsulation layer  80  has a thickness of around 5 μm to 40 μm. Encapsulation layer  80  can be formed using any standard capsulation deposition processes (which are well known in the art). A photolithography process is then used to remove portions of the encapsulation layer  80  to expose SMT compatible pads  78 . SMT interconnects  82  are then formed on the exposed pads  78  in a similar manner as described above with respect to SMT interconnects  62 . The resulting structure is shown in  FIG. 3C . 
     After wafer dicing/singulation in a similar manner as discussed above with respect to  FIG. 1F , the lens module assembly  48  is attached to transparent substrate  38  such that the lens(es)  50  focus the incident light though transparent substrate  38 , through microlenses/color filters  36 / 34 , through material  32  (if any), through silicon substrate  12 , and to photo detectors  14 . The image sensor chip  10  is then attached to a host board (e.g. a printed circuit board)  84  which includes contact pads  86  and electrical traces (not shown) for off chip signaling. The final structure is shown in  FIG. 3D . The electrical signals from the photo detectors  14  are processed by supporting circuitry  16 , and transferred off-chip via contact pads  18 , conductive material  76 , contact pads  78 , SMT interconnects  80  and contact pads  86  and traces of host board  84 . 
       FIGS. 4-6  illustrate alternate embodiments of those illustrated in  FIGS. 1G ,  2 E and  3 D, respectively, wherein for each alternate embodiment, the formation of cavity  28  is omitted. Instead, the secondary cavities  30  are formed into the back surface  12   b  of substrate  12 . This results in material  32  extending into the substrate  12  from the back surface  12   b , and color filter  34  and microlens  36  being mounted over each photo detector  14  (i.e. over each filled secondary cavity  30 ) at or near the back surface  12   b . The transparent substrate  38  can include a cavity  38   a  as shown in  FIGS. 4-6  to accommodate the color filters  34  and microlenses  36 , or a spacer can be disposed between substrates  12  and  38  to create a gap therebetween to accommodate color filters  34  and microlenses  36 . The remaining structure and method of formation steps remain the same as previously described. 
     It is to be understood that the present invention is not limited to the embodiment(s) described above and illustrated herein, but encompasses any and all variations falling within the scope of the appended claims. For example, references to the present invention herein are not intended to limit the scope of any claim or claim term, but instead merely make reference to one or more features that may be covered by one or more of the claims. Materials, processes and numerical examples described above are exemplary only, and should not be deemed to limit the claims. Further, as is apparent from the claims and specification, not all method steps need be performed in the exact order illustrated or claimed, but rather in any order that allows the proper formation of the packaged image sensor chip of the present invention. Color filters  34  and/or micro-lenses  36  could be disposed in the secondary cavities  32  instead of in cavity  28 . Lastly, single layers of material could be formed as multiple layers of such or similar materials, and vice versa. 
     It should be noted that, as used herein, the terms “over” and “on” both inclusively include “directly on” (no intermediate materials, elements or space disposed therebetween) and “indirectly on” (intermediate materials, elements or space disposed therebetween). Likewise, the term “adjacent” includes “directly adjacent” (no intermediate materials, elements or space disposed therebetween) and “indirectly adjacent” (intermediate materials, elements or space disposed there between), “mounted to” includes “directly mounted to” (no intermediate materials, elements or space disposed there between) and “indirectly mounted to” (intermediate materials, elements or spaced disposed there between), and “electrically coupled” includes “directly electrically coupled to” (no intermediate materials or elements there between that electrically connect the elements together) and “indirectly electrically coupled to” (intermediate materials or elements there between that electrically connect the elements together). For example, forming an element “over a substrate” can include forming the element directly on the substrate with no intermediate materials/elements therebetween, as well as forming the element indirectly on the substrate with one or more intermediate materials/elements therebetween.