Patent Publication Number: US-4150367-A

Title: Encoder/decoder system employing pulse code modulation

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to signal coding for pulse code modulation systems and, more particularly, to coder and decoders for telephone communication systems using compressed pulse code modulation with logarithmic companding. 
     2. Description of the Prior Art 
     The demand for communication services has been steadily increasing. In meeting this demand, it has proven effective in some communication systems to convert signals presented to the system into encoded digital signals and then reconvert the encoded digital signals into signals corresponding to those originally entered into the system. One example of a communication system in which such transmission of encoded digital signals has proven to have particular utility is a telephone communication system. Several schemes for digitally encoding signals in a telephone system are known. Although these encoding schemes are useful for both digital and analog signals entered into the telephone system, they have particular utility with continuous, time-varying analog signals such as voice signals. 
     In one encoding scheme, the amplitude of a voice analog signal is periodically sampled and each sample is converted into a digitally encoded pulse sequence or word representing the sampled analog signal. This operation is called sampling and quantizing the analog signal. If the range of analog signal amplitudes represented by each quantum level or step of the quantizing operation is uniform for all analog signal amplitudes, the encoded signal is said to be linear pulse code modulated (hereafter LPCM). Each LPCM signal word may then be decoded to form an analog signal of an amplitude substantially corresponding to the amplitude of the analog signal sample encoded into the LPCM signal word. Since the input analog signal was periodically sampled, the resulting, periodic LPCM signal words may be reconverted into a continuous analog signal substantially corresponding to the continuous input analog signal. 
     In the quantizing process, the exact level of the entered analog signal at the sampling instant is, as described, approximated by one of a number of discrete values or quantum levels digitally encoded as the LPCM signal. The difference between the instantaneous amplitude of the input analog signal and the quantum level actually transmitted is called quantizing error and gives rise to what is variously known as quantizing noise or quantizing distortion. 
     Quantizing distortion is especially objectionable and very often intolerable when the instantaneous amplitude of the input analog signal is small, but is usually of little or no significance when the instantaneous amplitude of the input analog signal is high. This is because the low amplitude of the input signals permits a relatively low level of quantizing noise to significantly degrade the ratio of signal to noise while a higher amplitude of the input signal can tolerate greater quantizing noise within an acceptable ratio of signal to noise. It is therefore desirable to have smaller quantum levels for lower amplitudes of the input signal to achieve closer correspondence between the quantum level of the encoded signal and the actual amplitude of the input analog signal at the lower amplitudes resulting in an acceptable ratio of signal to noise. Of course the size of the quantum levels for all input signal amplitudes could be decreased, but this produces an undesirable increase in the total number of quantum levels, requiring, for example, more bits to represent the signal as a digitally encoded word. 
     The suggested non-linear redistribution of the size of the quantizing levels is called companding, a verbal contraction of the terms compression and expanding. The purpose of companding is then to reduce the quantizing impairment of the original signal without unduly increasing the total number of quantizing levels by quantizing on a non-linear rather than a linear basis. 
     It is current practice with telephone systems to compand encoded analog signals on either a &#34;μ-law&#34; or an &#34;A-Law&#34; companding scheme as described by H. Kaneko in an article entitled &#34;A Unified Formulation of Segment Companding Laws and Synthesis of Codecs and Digital Companders,&#34; published in The Bell System Technical Journal, September, 1970. The resulting signals are then called compressed pulse code modulated signals (hereafter CPCM) or companded pulse code modulated signals. The μ-law is being generally adopted in the United States. The &#34;gross&#34; continuous formulation for the μ-law is: ##EQU1## for -1 ≧ x ≧ 1. The variable x is the relative input amplitude and y the relative output amplitude, which, in turn, is encoded into a binary number expressing the magnitude of y on a linear basis. An additional bit, the &#34;sign-bit,&#34; indicates the polarity of the signal sample x being encoded. Typically, the magnitude of y is expressed as a 6 or 7 digit binary number, corresponding to what is conventionally referred to as 7 or 8 bit resolution (code). Accordingly, y is approximated to one out of 64 or 128 evenly distrubuted levels (disregarding the sign). Actually, in the &#34;standard&#34; version of CPCM adopted in the U.S., a continuous exponential (or logarithmic) companding law is not used normally. Instead, the inverse function, x = f(y), is approximated by 8 linear chords or segments, each subdivided into 8 or 16 steps, depending upon the number of bits mentioned before (7 or 8). The segmented μ-law is used to avoid implementation difficulties and to facilitate digital linearization features, but the resulting circuits are still somewhat complicated. It might be added that regardless of approach, a constant of μ = 255 has been chosen. Separate studies show that the additional distortion caused by back-to-back operation of &#34;continuous encoder&#34; and &#34;segmented decoder&#34; or vice versa is acceptable, as such, of the order of 3% or less. 
     Another important feature of the compressed PCM code adopted in the United States is the fact that the binary scale which linearly represents the compressed relative signal magnitude, y, is reversed, or complemented -- i.e. at zero signal level the corresponding binary code, excluding the sign bit, consists of a series of all ones, while maximum signal level magnitude is represented by all zeros. The reason for this arrangement is the desire to minimize the probability of long series of zeros which would make synchronization more difficult in PCM transmissions systems. Hence a preferred embodiment of the instant invention will generate a complementary encoded representation of the compressed relative signal magnitude y. 
     SUMMARY OF THE INVENTION 
     An object of this invention is to provide for conversion between analog and digital signals with simplicity, enabling low cost implementation with standard components including integrated circuits. 
     According to the invention, the analog signal is compared with the decaying voltage on a capacitor initially charged to a fixed voltage, and being discharged through a fixed resistor to another fixed voltage, the time being measured by a binary digital counter from the start of the discharge until the voltage at the capacitor terminal equals the absolute value of the analog signal sampled at the system input. With proper choice of constants and clock frequency, the content of the binary counter at the time of coincidence comprises, in complementary form, the CPCM representation of the magnitude of the sampled analog signal. The CPCM representation is completed by appending a sign bit to the counter contents, said sign bit being directly related to the polarity of the analog signal sample. 
     For analog-to-digital encoding, the binary counter is coupled to the output of a comparator to stop in response to the equality indication. For digital-to-analog decoding, a binary counter is incremented until its count equals the number specified by the CPCM representation transmitted from the encoder. Then, in response to completion of this count, a switch is opened to stop the capacitive discharge, and the voltage on the capacitor is used to provide an analog output signal with a polarity depending on the sign bit of the digital signal. 
     With reference to the μ-law, the initial capacitor voltage E may be chosen equal to the full scale analog voltage, and the discharge toward a voltage -dE, where d = 1/μ. The frequency for counting is chosen such that the full value count (64 for a 7 bit code or 128 for an 8 bit code) is reached in a time equal to RC 1n (1 + μ), where RC is the time instant of the capacitive discharge path toward -dE. 
     Thus, the continuous μ-law is implemented in a simple and attractive way according to the present invention. 
    
    
     DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a simplified block diagram for an encoding and decoding system provided by the present invention; 
     FIG. 2 is a schematic and functional block diagram of an encoder of the system of FIG. 1; 
     FIG. 3 is a schematic and functional block diagram of a decoder of the system of FIG. 1; and 
     FIG. 4 and FIG. 5 are timing diagrams depicting time-related logic levels for pertinent points of FIG. 2 and FIG. 3, respectively. 
    
    
     DESCRIPTION OF A PREFERRED EMBODIMENT 
     Referring to the drawing, FIG. 1 is a block diagram of an encoder/decoder system 10, including an encoder 12 and a decoder 14, provided by the present invention. The system 10 has particular utility in communication systems, such as telephone systems, for enabling the transmission of continuous time varying analog signals, such as voice frequency signals, in a compressed format to increase the transmission capability of a communication link 30 which interconnects the encoder 12 at the transmitting end and the decoder 14 at the receiving end. The analog signals entered into the system on path 1 are converted into digital signals by the encoder 12 at the transmitting end. The encoded digital signals are reconverted into analog signals corresponding to those originally entered into the system 10 by the decoder 14 at the receiving end and presented to output path 3. 
     In accordance with the present invention, the analog signals are encoded employing a &#34;μ-law&#34; companding scheme, such that the resulting encoded digital signals are compressed pulse code modulation signals, hereinafter referred to as CPCM signals. The continuous formulation for the &#34;μ-law&#34; is given by the following relationship: ##EQU2## 
     The variable x is the relative amplitude of the analog signal v i , and y is the relative output amplitude, which, in turn, is encoded into a multibit binary word, representing the magnitude of y on a linear basis. An additional sign bit is provided at path 74 of FIG. 1 to indicate the polarity of the signal sample being encoded. 
     According to the invention, for analog-to-digital encoding, the analog signal v i  is sampled, and the signal sample voltage v s  is compared with a time-varying reference voltage v r , which decreases from a known amplitude at a known rate. The time required for the reference signal to equal the amplitude of the signal sample voltage is measured by a binary digital counter. The binary count at the time of coincidence constitutes the compressed pulse code, in complementary form, of the analog signal. This conversion gives the encoded magnitude of the analog signal. The sign bit of the pulse code, which is related to the polarity of the analog signal, is obtained in a manner to be shown hereinafter. 
     Referring to FIG. 1, the time-varying analog signal v i  at the output of low-pass filter 17 is sampled by a sampling circuit 16 which is enabled by a timing control signal T s  on path 70 to sample the time-varying analog signal v i  for a predetermined time interval. T s  is provided by timing control logic 21 which is driven by clock circuit 22. At the end of the sampling interval, a comparator circuit 20 is operative during a holding interval to compare the signal output v s  of the sampling circuit 16 with the time varying signal v r  which is provided by a reference source 18 over path 63AB. The time varying signal v r  provided by the reference source 18 decreases from a predetermined amplitude at a predetermined rate. When the amplitude of the reference signal v r  has decreased to a value equal to the absolute value of the signal sample voltage v s , the comparator circuit 20 provides a control output on path 90 and a sign indication output on path 68. 
     During the holding interval, a digital binary counter 24 is incremented by pulses provided at path 89 from gate circuit 26. Gate circuit 26 is enabled according to the logic levels on path 90 from comparator 20 and on path 70 from timing control logic 21, thereby passing clock pulses received from clock circuit 22, over path 77, to path 89. The gate circuit 26 is disabled when the control output on path 90 is provided by the comparator circuit 20, inhibiting the passage of further clock pulses to the counter 24. At such time, the multibit output word presented to path 76 at the output of the counter 24, representing the state of the counter 24, indicates the time elapsed from the start of the holding interval until coincidence of the signal sample voltage v s  and the reference signal v r , and thus, corresponds to the desired CPCM code representing the magnitude of the analog signal v i  to which only a sign bit must be added. The sign bit is obtained by a sign circuit 72 which is controlled by the comparator circuit 20 via path 68 to provide an output at path 74 indicating the polarity of the signal sample v s . 
     The CPCM code, including the multibit word representing the state of the counter 24, and the sign bit are extended over a suitable communication link 20 to the decoder 14 at the receiving end. 
     The operation of decoder 14 is basically the inverse of the operation of encoder 12. A time varying signal v r  &#39; provided at path 124 of reference source 40 of the decoder 14 is permitted to decrease in amplitude via controlled capacitive discharge at the termination of a SYNC signal on path 82 sent from encoder 12. The amplitude continues to decrease for a time determined by code counter 32 which is initialized (or pre-programmed), via path 76, to count to a vaule represented by the transmitted CPCM code. 
     When the predetermined count is reached, the amplitude decay at reference source 40 is terminated by signal T H  on path 130. At this time, the magnitude of the reference signal v r  &#39; at path 124 corresponds to the magnitude of the originally sampled system input signal v s . 
     The resultant reference signal v r  &#39; is extended via path 124 to dual polarity network 42 wherein the signals v r  &#39; and -v r  &#39; are generated for passage via paths 121 and 122, respectively, to polarity select circuit 44. Polarity select 44 is enabled by a sign indicator signal on path 104AB from sign circuit 104 and by a timing signal T O  on path 129 from timing register 120 to pass appropriately-signed v r  &#39; on path 125 to output circuit 26 for signal conditioning and filtering. The final system analog output signal then appears at path 3. 
     In addition to the SYNC signal on path 82, the encoder 12 additionally forwards the basic system clock pulse stream via path 77 to decoder timing control logic 31. Timing control logic 31, in turn, controls timing register 120 via path 135 and code counter 32 via paths 131 and 134. 
     ENCODER 
     Referring to FIG. 2, which is a schematic representation of the encoder 12, the input signal v i  on path 1 is extended to the sampling circuit 16 via a low pass filter 17, which may, for example, be an active filter having a cutoff frequency corresponding to the upper limit frequency of the time-varying analog signal v i  to be encoded. In the present example, where it is assumed that the analog signals are voice-frequency signals, the cutoff frequency of the filter 17 may correspond to the upper limit of the voice band. 
     The sampling circuit 16 includes a holding capacitor C H  a sampling switch embodied as an FET transistor Q1, which when enabled, connects one side of the capacitor C H  to the output of the filter 17 via path 2 to receive the voice-frequency signal v i  input to the system. The enabling of transistor Q1 is controlled by a switch control circuit SC1 which is enabled by a control signal T S  provided by a timing register 52, to cause the transistor Q1 to conduct for the duration of the sampling interval. Switch control circuits SC1 and SC2 of the FIG. 2 and SC3, SC4, SC5 and SC6 of FIG. 3 may be simple transistor amplifiers, well-known in the art, which are arranged to provide the proper gate or base electrode voltage and polarity to the switching device to which they are respectively coupled. It is to be noted that, throughout the drawing, when a switching control circuit SCn receives a logic high, or ONE, level at its input, then the associated switching device Qn is rendered conductive, or ON. Conversely, receipt of a logic low, or 0, level at SCn renders switch Qn non-conductive, or OFF. 
     In the exemplary embodiment, it is assumed that a sample of the voice frequency signal v i  is to be encoded every 125 microseconds. The control signal T S , which is chosen to be 62.5 microseconds in duration, defines the sampling interval during which the input signal v i  is sampled. The remainder of the time, 62.5 microseconds, defines a holding interval during which time the comparison is made between the signal sample v s  and the reference signal v r . 
     As seen from FIG. 2, timing signal T S  is passed to switch control SC1 over path 70 from timing register 52. Timing register 52 may, for example, be an 8-bit binary counter fed at its incrementing, or CLK, input by the basic system clock pulse train presented at path 77 by clock circuit 22. With this arrangement, the timing signal T S  can be taken directly from the most significant bit of the 8-bit counter output. An 8-bit counter provides 256 counting steps, and the desired encoding period, as mentioned above, is 125 μsec. Hence, a convenient frequency for clock 22 would be 256/125 μsec., or 2.048 MHz. Then with T S  taken from the most significant counter output bit, the circuit generates equal sample and hold timing intervals of 62.5 μsec. 
     The sampling circuit 16 further includes a pair of operational amplifiers OP1 and OP2, such as the National Semiconductor types LM302 and LM318, respectively, which provide complementary output signals v s  and -v s , corresponding to the magnitude of the signal voltage across the holding capacitor C H . 
     Amplifier OP1, which is connected for operation as a voltage follower, has a non-inverting input connected at point 56 to one side of capacitor C H , the other side of which is connected to ground. The output 57 of the amplifier OP1 is connected directly to the inverting input of the amplifier OP1. 
     The output 57 of amplifier OP1 is also connected over a resistor R1 to the inverting input of amplifier OP2, which has its non-inverting input connected over a resistor R2 to ground, and its output 60 connected over a resistor R3 to the inverting input. Resistors R1 and R3 are of equal resistance, providing unity gain for the amplifier OP2 which operates in the inverting mode. 
     The output 57 and 60 of respective amplifiers OP1 and OP2 are respectively connected to inverting inputs 61 and 62 of a pair of operational amplifiers CP1 and CP2 which, along with NAND gate G1, comprise the comparator circuit 20. The non-inverting inputs 63A and 63B of the amplifiers CP1 and CP2 are commonly connected to the output of the reference circuit 18 via path 63AB. The amplifiers CP1 and CP2 may be the National Semiconductor Type LM311, a type selected for high speed and small offset voltage. 
     The reference circuit 18 comprises resistor R4, capacitor C R  and a sampling switch Q2, embodied, for example, as a type 2N2904, which, when enabled, connects one side of capacitor C R  at point 64 to a fixed reference potential +E. The other side of capacitor C R  is coupled to ground potential. Resistor R4 is connected between point 64 and a negative reference potential -dE. The enabling of transistor switch Q2 is governed by switch control circuit SC2 which is enabled by output signal T S  of timing register 52 to cause transistor Q2 to conduct for the duration of the sampling interval. 
     When the switch Q2 is closed, capacitor C R  charges to the potential +E. When the switch Q2 is opened at the end of the sampling interval, capacitor C R  discharges over resistor R4 toward the potential -dE, with the time constant being determined by the capacitor C R  and the resistor R4. 
     The voltage v r  across the capacitor C R  may be expressed by 
     
         v.sub.r = -dE + (1+d) E. e.sup.-t/T                        (2) 
    
     where T is the time constant determined by the values of capacitor C R  and resistor R4. 
     Rearranging terms, and dividing by dE yiels ##EQU3## The signal sample voltage v s  can be expressed as a relative amplitude &#34;x&#34; out of a full scale voltage v o , that is v s  = xv o . In accordance with the present invention, the voltage v r  is compared with the signal smaple voltage v s , and the time t as a function of x is determined by the time at which the capacitor voltage v r  has decreased to the value of v s  -- that is when v r  = xv o . Substituting this value into equation (3), and taking the natural logarithms results in ##EQU4## 
     The terms v o , d, and E are constants, and, accordinly, can be chosen such that v o  /dE equals μ. Substituting this value into equation (4) yields ##EQU5## 
     Transposing terms and substituting d = v o  /μE into equation (5) yields ##EQU6## Then, choosing E equal to v o , and dividing both sides of the equation (6) by 1n (1 + μ) yields ##EQU7## Introducing the time T&#39; equal to T·1n (1 + μ) gives ##EQU8## Recall from previous equation (1) that ##EQU9## Comparing equations (8) and (1), it is evident that y in the continuous companding law, equation (1), equals the complement of the relative time t/T&#39;. In other words, by choosing E equal to the full scale voltage v o  of the signal to be encoded, setting d = 1/255, and choosing the clock frequency for the digital counter or, inversely the time constant T of the RC-circuit, so that the maximum count of the counter, that is 64, 128, etc., is obtained during a time T in (1 + μ), then the content of the counter at coincidence between v o  and the absolute value of the signal sample v s  directly represents the six or seven bits of the desired CPCM code to which only a sign bit must be appended. 
     Thus, during the sampling period, capacitor C H  charges over switch Q1, and capacitor C R  charges over switch Q2 to the fixed reference potential +E. At the end of the sampling period, the signal outputs v s  and -v s  of amplifiers OP1 and OP2, which correspond to the charge on capacitor C H , represent the amplitude of the signal sample of the input signal v i . When switches Q1 and Q2 are opened at the end of the sampling period, capacitor C H  maintains its charge due to the high input impedance of the amplifier OP1. During the holding interval, capacitor C R  discharges over resistor R4 towards the potential -dE, providing the reference voltage v r  at point 64. 
     Also, during the holding interval, a gate G2 of the gate circuit 26 is enabled to extend clock pulses provided by a clock pulse source 22 on path 77 to the counter 24 via inverter G2A and path 89. The enabling of the gate G2 is controlled by the timing control signal T S  and inverter 86, which is provided over a start counter conductor 70 during the holding interval, and by the output of a further gate 85 of the gate circuit 26, which is controlled by gate G1 of comparator circuit 20. 
     The outputs 66 and 68 of the comparator circuits CP1 and CP2 respectively, are combined by gate G1, which is embodied as a NAND gate, which normally provides an enabling input via inverter 85 to NAND gate G2. Gate G2 is enabled when the timing control signal T S  is provided on the start count conductor 70 to gate the clock pulses provided by the clock pulse source 22 to the binary counter 24. The time constant R4C R  of the reference circuit 18 and the frequency of the clock pulse source 22 are coordinated to permit the counter 24 to reach its maximum count (e.g., 64 or 128 for a 6 or 7 bit code, respectively) during a time equal to T&#39; = T1n (1 + μ), which may not exceed the 62.5 μsec. holding interval. A clock frequency of approximately 1 MHz may be used when a 7 bit code is desired, and a clock frequency of approximately 2 MHz may be used for an 8 bit code. 
     If the code counter 24 of FIG. 2 is implemented with two cascaded 4-bit binary counters of the Texan Instruments type SN74193, the desired complementary code (zero magnitude corresponding to all ones and maximum magnitude corresponding to all zeros) will be obtained if the output 89 from inverter G2A is coupled to the so-called COUNT-UP terminal (designated CLK in FIG. 2), and the counter is cleared prior to the holding interval, as indicated by waveform 88 of FIG. 4 which represents the output of inverter 84 of FIG. 2. If, as described hereinabove, the timing register 52 comprises an 8-bit counter, the second-most-significant counter output bit coupled to path 78 will provide an auxiliary timing signal T S  &#39; at a 16 KHz rate which, after combination with T S  at NAND gate 83 and inversion at inverter 84, provides a clear signal to counter 24 at path 88 during the last half of the sampling period. See corresponding waveforms 70, 78, and 88 of FIG. 4. 
     The encoded magnitude information at the outputs of code counter 24 of FIG. 2 is coupled to a set of conductors 76. The sign bit is carried on conductor 74 which is coupled to the Q output of flip-flop 72. Together, conductors 76 and 74 form a communication link 30 on which the desired CPCM code appears in parallel format during a portion of the 125 μsec. operational cycle, or frame. For convenience the cummunication link 30 is supplemented with not only the CLOCK signal on path 77 but also with a combined synchronization and read signal, SYNC, on path 82, which is a logic high during the first half of the sampling period. The SYNC signal is simply derived by inverting the T S  &#39; signal at path 78 in inverter 79 and combining it with the T S  signal in NAND gate 80 and inverter 81. 
     When the voltage v r  across capacitor C R  reaches the absolute value of the sampled signal v s , one of the outputs 66 or 68 of amplifier circuits CP1 or CP2, respectively, of comparator circuit 20 is disabled thereby inhibiting gate G2 via gate G1 and inverter 85 to prevent the passage of further clock pulses to counter 24, so that the count then corresponds to the encoded level of the signal sample v s . 
     With the specific exemplary embodiment having a clock frequency of 2.048 MHz and 8-bit encoding, the time constant of the reference circuit should be chosen as 65 μsec/in(1+μ), or 11.271 μsec. for μ = 225. If capacitor C R  is chosen with a value of 0.01 μf, resistor R4 should have a value of 1127.1 ohms. The same values for C R  and R4 would apply for a 7-bit code, provided the clock frequency is halved to 1.024 MHz, in which case a 7-bit counter would be used for timing register 52 and a 6-bit counter for code counter 24. 
     The output 68 of comparator circuit amplifier CP2 is also extended to sign circuit 72 comprised of D flip-flop 72. The D input of flip-flop 72 is coupled to the output 68 of CP2. The true, or Q output of flip-flop 72 is extended over path 74, which comprises a part of communication link 30, to transmit the sign bit to decoder 14 at the receiving end of the system. The clock input CLK of flip-flop 72 is coupled to the output of NAND gate 87 which receives the inverted T S  signal via inverter 86 and the inverted output from gate G1 via inverter 85. The D flip-flop 72 will retain the value of the signal appearing at the D input during a positive-going transition of the signal appearing at the CLK input. Such a transition occurs during the encoding (or hold) interval when the absolute value of the sampled signal v s  coincides with reference capacitor voltage v r  and accordingly when the output of gate G1 is disabled. As a result, gate 87 is also disabled producing a positive-going signal at its output thus locking the flip-flop 72 to the corresponding logic level at the output 68 of CP2, which is logic ONE, or high, for positive v s . In the case of a negative polarity for v s , the output of CP2 will be logic ZERO, or low. 
     Accordingly, the Q output of flip-flop 72 will remain low to provide the proper sign information for the encoded signal sample. The inverted T s  signal at path 70A will maintain the CLK input high during the sampling interval, thus maintaining the proper sign information on path 74 for read-out, independent of any transition occuring at the comparator output 68 during this time interval. 
     OPERATION OF THE ENCODER 
     The operation of encoder 12 is best described in conjunction with the schematic diagram of FIG. 2 and the encoder timing diagram of FIG. 4. The idealized logic signal levels as a function of time are set forth in FIG. 4 for various pertinent points of the schematic of FIG. 2. The designations for each waveform of FIG. 4 correspond to identical path designations used in FIG. 2. 
     In the exemplary embodiment, where it is assumed that a sample of the voice frequency signal v i  is to be encoded every 125 μsec., the timing register 52 of FIG. 2 provides a control output signal T s  at path 70 for 62.5 μsec. at the start of each 125 μsec. encoding period. During this sampling interval, the input signal v i  is sampled, the counter 24 is reset via a positive going pulse on path 88, and the capacitor C R  is charged to the reference potential +E. The 62.5 μsec. time assures full tracking of the input signal v i , since FET transistor switch Q1 is held conductive during the sampling period by the associated switch control circuit SC1. The &#34;on&#34; resistance of Q1 and the capacitance of the holding capacitor C H  provide a charging time constant low in comparison with the highest voiceband frequency of the sampled input signal. 
     The transistor switch Q2 is also held conductive for the duration of the positive logic signal T s  by its associated switch control circuit SC2. Gate G2 is inhibited during this sampling interval by a logic low level at 70A. At the end of the 62.5 μsec. sampling interval, signal T s  goes low to turn off switches Q1 and Q2 via switch control circuits SC1 and SC2, respectively. Also at this time, gate G2 is enabled to pass clock pulses at path 77 via inverter G2A to code counter 24 at path 89. 
     The voltage sample v s  provided by capacitor C H  appears at the output of operational amplifier OP1, which exhibits a high impedance to the holding capacitor C h  thus avoiding discharge. Amplifier OP2 provides a reverse polarity voltage -v s . The signals v s  and -v s  are extended to inputs 61 and 62 of the comparator amplifiers CP1 and CP2, respectively. With polarities shown in FIG. 2, the outputs of both amplifiers CP1 and CP2 are high as long as the capacitor voltage v r  is greater than v s . Accordingly, during the holding interval, the output of NAND gate G1 at path 90 is low, which together with the low level on the start count conductor 70, enables NAND gate G2 to pass clock pulses from the clock pulse source 22 to the counter 24. When either one of the comparator amplifiers CP1 or CP2 switches due to coincidence of v s  and v r , the corresponding output goes low, enabling gate G1, which, via inverter 85, inhibits gate G2, preventing further incrementing of the counter 24. See, for example, point C of waveform 90 of FIG. 4, where the output of G1 goes high to inhibit further incrementing of counter 24 by clock pulses 89. Depending on the polarity, that is which of the amplifiers CP1 or CP2 switches, the sign bit flip-flop 72 is either set low or high. For example, when the sample v s  is of positive polarity, then at magnitude coincidence with v r  &#39; output 66 of CP1 will go low and output 68 will remain high, resulting in a logic ONE being gated to D flip-flop 72 thus setting the logic level of path 74 to ONE. Conversely, when the sample v s  is of negative polarity, then at magnitude coincidence with v r , output 68 of CP2 will go low resulting in a logic ZERO being gated to the ouput 74 of D flip-flop 72. D flip-flop 72 is activated to accept the signal presented to input D when a low-to-high signal transition is presented to input CLK at the output on NAND gate 87. As seen from FIG. 2 and FIG. 4, such a low-to-high transition occurs when output 90 of gate G1 goes high while output 70A of inverter 86 is high (specifically, see time point C of waveform 90 of FIG. 4). 
     The multibit code provided on conductors 76 at the output of the counter 24 and the sign bit provided on conductor 74 by the sign bit flip-flop 72 are transmitted to the decoder 14 at the receiving end where the CPCM code is reconverted to an analog signal, corresponding to the input signal v i  entered into the system. 
     DECODER 
     Referring to FIG. 3 which is a schematic representation of the decoder designated 14 in FIG. 1, the bits of the CPCM code, representing the resultant contents of counter 24 of FIG. 2, are transmitted over the communication link 30 and then extended at the decoder of FIG. 3 to the data inputs 132 of code counter 32 via timing control logic gates 101, 101A, 103, and 103A. Counter 32 may, for example, be comprised of two cascaded type SN54139 programmable 4-bit counters, commercially available from Texas Instruments, Inc. Such a counter will register the code presented at data inputs 132 when a low logic level is applied to the LOAD input (via path 131 in FIG. 3), decrement its output value on positive-going logic level transistion of a CLK (or COUNT-DOWN) input at path 132 of FIG. 3, and produce a low logic level (or 0) pulse at its BORROW output (connected to path 130 in FIG. 3) equal in width to the CLK (or COUNT-DOWN) input when an underflow condition exists -- i.e. when the count according to the CLK input exceeds the preset or programmed, value originally loaded into the counter at data inputs 132. 
     SN54193 counters may also be utilized to construct 8-bit timing register 120 whose most significant output bit MSB is used to provide output strobe pulse T O  at path 129 which is, in turn, coupled to enabling inputs of NAND gates 105 and 106. The incrementing pulse train for the CLK (or COUNT-UP) input of timing register 120 is furnished by the output of inverter 101A via path 135. 
     The sign circuit for the decoder is comprised of D flip-flop 104. The sign bit to be registered is coupled to the D input of 104 via path 74, and the flip-flop is enabled by a positive-going logic signal at its CLK input by the SYNC signal appearing on path 82. The Q and Q complementary outputs of sign flip-flop 104 are respectively coupled via path 104A and 104B to NAND gates 105 and 106. 
     Reference source 40 of decoder 14 is comprised of switch control circuits SC3 and SC4, transistor switches Q3 and Q4, voltage supplies +E and -dE, and discharge timing elements consisting of resistor R4&#39; and C R  &#39;. Switch control circuits SC3 has its input coupled to the SYNC signal on path 82 and its output coupled to the base of PNP transistor switch Q3. The emitter of Q3 is coupled to DC source +E while the collector of Q3 is coupled to one common terminal of resistor R4&#39;, capacitor C R  &#39;, and the non-inverting input to operational amplifier OP3 at path 124. The opposite terminal of C R  &#39; is coupled to ground potential, while the opposite terminal of R4&#39; is coupled to DC potential -dE via the collector-to-emitter path of NPN transistor switch Q4. Q4 is controlled by switch control circuit SC4 whose output is coupled to the base of Q4 and whose input is coupled to the BORROW output of code counter 32 at path 130. 
     The decoder&#39;s dual polarity network 42 is comprised of operational amplifiers OP3 and OP4 (which may, for example, be National Semiconductor types LM 302 and LM 318, respectively) and biasing resistors R5, R6, and R7. The output of OP3 at path 121 is coupled to the inverting input of OP3 and, via R6, to node 123 which is coupled to inverting input of OP4. Resistor R7 is coupled between node 123 and the output of OP4 at path 122, while resistor R5 is coupled between ground potential and the non-inverting input to OP4. The output of OP3 at path 121 is coupled via FET switch Q5 to point 125, while the output of OP4 at path 122 is coupled via FET switch Q6 to point 125. 
     The decoder&#39;s polarity select circuit 44 is comprised of gates 105, 106, 107, and 108, switch control circuits SC5 and SC6, and FET switches Q5 and Q6. NAND gate 105 and inverter 107 gate the Q output of sign flip-flop 104 to the input of switch control circuit SC5, while NAND gate 106 and invertor 108 gate the Q output of sign flip-flop 104 to the input of switch control circuit SC6. FET switches Q5 and Q6 have output electrodes commonly tied to the input of output circuit 46 at path 125. 
     The decoder&#39;s output circuit 46 is comprised of operational amplifier OP5, biasing resistors R8 and R9, and voice-band (low pass) filter 140. Resistor R8 is coupled between the input 125 of output circuit 46 and the input of buffer operational amplifier OP5 at path 126. Feedback resistor R9 is coupled between the input of OP5 at path 126 and the output of OP5 at path 127, which, in turn, is coupled via low pass filter 140 to the system output at path 3. 
     DECODER OPERATION 
     The operation of decoder 14 is best described with reference to the schematic diagram of FIG. 3 and the decoder timing diagram of FIG. 5. All waveforms in FIG. 5 are designated with the same reference numerals used to designate corresponding paths in the schematic diagram of FIG. 3. 
     Each 125 μsec. decoding cycle begins with receipt of a 31.25 μsec. positive-going SYNC signal at path 82 which performs the following function: (a) disables the timing register 120 CLK input by clamping it to a low logic level via inverter 102, NAND gate 101 and inverter 101A; (b) clears the contents of timing register 120 to zero by providing a logic ONE to the CLEAR input thereto; (c) gates the sign bit value present on path 74 into D flip-flop 104 providing a positive-going logic level transition at the CLK input thereto; (d) presets the code counter 32 to a value represented by the CPCM code at data inputs 132 by providing a logic zero via inverter 102 to the LOAD input of counter 32; (e) disables the CLK input to counter 32 at path 134 by clamping it to logic level zero via NAND gates 103 and 103A; and (f) enables switch Q3 via switch control circuit SC3, thereby recharging reference capacitor C R  &#39; to a voltage substantially equal to +E. Additionally, during the SYNC 31.25 μsec. interval, the BORROW output of counter 32 is high thereby providing via path 130 an enabling signal to switch control cirucit SC4 which renders switch Q4 conductive. 
     At the termination of the SYNC pulse on path 82, switch Q3 is opened permitting capacitor C R  &#39; to begin discharging through Q4 and R4&#39; towards the voltage -dE. The discharge time constant, R4&#39;C R  &#39;, is selected to be identical to that of the associated time constant for the encoder of FIG. 2, R4C 4 . In this way the reference discharge time constant and the clock frequency of the signal at path 77 will be coordinated at decoder 14 in a manner identical to that relationship used for the encoder of FIG. 2. Also, when the SYNC pulse goes low, timing register 120 begins counting according to the pulse repetition rate present on path 77 which is passed to the CLK (COUNT-UP) input of 120 at path 135 via NAND gate 101 and inverter 101A. Additionally at this time, code counter 32 begins counting down toward zero from the value previously set at its data inputs 132 according to the CPCM code set by the encoder over path 76. The counting function is initiated by passing the pulse train now present at path 135 to the CLK (COUNT-DOWN) input of counter 32 at path 134 via NAND gates 103 and 103A. 
     Hence, as seen from the timing diagram of FIG. 5, after the various initialization functions described above in conjunction with a logic high SYNC pulse at path 82, counters 32 and 120 begin decrementing and incrementing, respectively, according to pulses received at paths 134 and 135, respectively. Simultaneously, capacitors C R  &#39; begins to discharge from a maximum potential +E towards the minimum potential -dE for a time period determined from the value loaded into counter 32 at data inputs 132 corresponding to the CPCM code transmitted in the previous 125 μsec. cycle from the encoder of FIG. 2. When this predetermined down-count has been reached at code counter 32, then on the next positive-going logic level transition at path 134, signal T H  on path 130 goes low to open switch Q4 via SC4 and hence initiate the hold interval for capacitor C R  &#39; (see point D of waveform 130 of FIG. 5). 
     Hence, it is seen from FIG. 3 and FIG. 5 that the decoder hold interval may begin with cessation of clock 32 decrementation as early as h min . (31.25 μsec.) of FIG. 5 (corresponding to an all-zero CPCM code representing maximum analog magnitude E) and as late as h max  (93.75 μsec.) of FIG. 5 (corresponding to an all-ones CPCM code representing minimum analog magnitude 0). Let the voltage on C R  &#39; at the initiation of the hold interval be represented by v r  &#39;. Then during the hold interval, the above-discussed configuration of amplifiers OP3 and OP4 of dual polarity network 42 is such that a voltage of +v r  &#39; is developed at path 121, while a voltage of -v r  &#39; is developed at path 122. 
     As previously described hereinabove in conjunction with FIG. 3 and FIG. 5, 8-bit timing register 120 began counting from zero at the termination of the SYNC pulse, 31.25 μsec. into the decoder operation cycle. Since the counting rate at path 136 is determined by the 2.048 MHz clock rate on path 77, it is seen that the most-significant output bit, MSB, of counter 120 will go high (logic ONE) 62.5 μsec. after counting has been initiated. This results in the positive-going output strobe T O  at path 129 (shown as waveform 129 in FIG. 5) at a time 93.75 μsec. into the decoder operation cycle. Logic ONE at path 129 primes NAND gates 105 and 106 for respective enablement according to the sign bit value registered in D flip-flop 104. If the sign bit was one, indicative of a positive polarity, the switch control SC5 is enabled via NAND gate 105 and inverter 107 to render switch Q5 conductive, thereby passing +V r  to the output circuit 46 at path 126. Alternatively, if the sign bit was ZERO, indicative of a negative polarity, then switch control circuit SC6 is enabled via NAND gate 106 and inverter 108 to render switch Q6 conductive, thereby passing -v r  to the output circuit 46 at path 125. 
     Hence, at a constant time reference point in each decoder cycle of operation (i.e. at 93.75 μsec. thereof), an appropriately decoded output signal, plus or minus v r  &#39;, is presented to the system&#39;s analog output at path 3 via amplifier OP5 and voice band filter 140. Gating the output ±v r  at a fixed time reference in each operating cycle avoids deterioration of proper output signal phasing with respect to the originally sampled system input analog voltage waveform at the encoder of FIG. 2. 
     With the arrangement set out hereinabove, the output signal is available at the system output only while T o  is high -- i.e. for one-fourth of the 125 μsec. time frame. Hence, the average of the output signal extracted by filter 140 is attenuated by a factor of four, absent corrective amplification. This loss can easily be compensated for in the exemplary embodiment by choosing the value of R9 to be four times the value of R8, thereby providing operational amplifier OP5 with a gain of four. 
     It should be noted that the invention described herein has been illustrated with reference to a particular embodiment. It is to be understood that many details used to facilitate the description of such a particular embodiment are chosen for convenience only and without limitation on the scope of the invention. Other embodiments may be devised by those skilled in the art without departing from the scope and spirit of the invention. For example, for reasons set forth hereinabove, the illustrative embodiment is arranged to generate a so-called complementary CPCM code, wherein maximum analog signal magnitude is represented by all-zeros, while minimum analog signal magnitude is represented by all-one. It would be relatively simple to achieve an alternative arrangement wherein a straight binary CPCM representation is encoded -- i.e. where a minimum magnitude would correspond to the all-zero code and the maximum amplitude to the all-one code. One could merely invert the resultant contents of code counter 24 of FIG. 2 prior to transmittal to the decoder of FIG. 3 (or count-down from a preset maximum at counter 24). Code counter 32 of the decoder of FIG. 3 would then be arranged to receive counting inputs at a COUNT-UP input, and a negative-going signal at its CARRY output would be used in place of BORROW. (The CARRY output of the suggested SN54139 type counter produces the desired pulse when the counter overflows). 
     As an additional alternative arrangement, one might not wish to separately send CLOCK and SYNC pulses over separate paths from the encoder of FIG. 2 to the decoder of FIG. 3. For example, in T1-formatted data links, techniques are well-known in the art for deriving the basic system clock repetition rate and a synchronizing pulse from the incoming data stream itself. Additionally, in arrangements such as that used with R1 format, it would be obvious to one skilled in the art to arrange the system of the illustrative embodiment for transmittal of a framing bit per frame of N channels in addition to the CPCM samples corresponding to each channel. 
     Accordingly, the instant invention is intended to be limited only by the scope and spirit of the appended claims.