Patent Publication Number: US-8982646-B2

Title: Semiconductor memory device including data transfer bus and data transfer method of the device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2011-205812, filed Sep. 21, 2011, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor memory device and data transfer method of the device. 
     BACKGROUND 
     A flash memory is used as a file memory for saving data in an electronic device such as a computer or digital camera. 
     The bit cost of the flash memory has been reduced year by year by continuously increasing the capacity and advancing micropatterning. The number of applications of the flash memory has increased due to the increased capacity and scaling of the device dimension. Recently, the bit cost of the flash memory has been reduced by a bit cost scalable configuration (a three dimensional stracked array structure) in addition to the scaling of the device dimension and multilevel cell. 
     In the bit cost reducing technique like this, the signal amount of a cell basically reduces, and the capacity of a bit line for reading out a signal from the cell increases, so the read speed of each cell decreases. Also, to reduce the bit cost, it is necessary to finely perform a write operation and verify operation. This decreases the write speed as well. 
     A conventional semiconductor memory device incorporates a page register that allows high-speed read and write from an external device. The bit size of this page register is called a page length. The unit of read or write performed for memory cells at once is called a page. The bit size of the page is also called a page length. Data having the page length is read out or written at once between the page register and memory cells. The page length is much larger than the number of input/output bits of a memory chip. Accordingly, the semiconductor memory device can perform data transfer at high speed with an external device by obscuring slow operations of an internal memory cell array. 
     To process large amounts of stored data, it is necessary to improve the high-speed data access performance. The development of a speed increasing technique of increasing the bandwidth five to ten times, e.g., from 200 to 400 MBytes/sec has been advanced. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a plan block diagram showing an example of an arrangement of a semiconductor memory device according to a first embodiment; 
         FIG. 2  is a sectional block diagram showing an example of an arrangement of the semiconductor memory device according to the first embodiment; 
         FIG. 3  is a timing chart showing an example of a write operation according to the first embodiment; 
         FIG. 4  is a timing chart showing an example of a read operation according to the first embodiment; 
         FIG. 5  is a block diagram showing an example of an outline of an arrangement of a conventional semiconductor memory device; 
         FIG. 6  is a block diagram showing an example of an outline of an arrangement of the semiconductor memory device according to the first embodiment; and 
         FIG. 7  is a block diagram showing an example of data transfer control performed by transfer control circuits according to a second embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor memory device includes a memory cell array, a data bus, a transfer controller, a plurality of column blocks, and a column selector. The data bus is divided into a plurality of stages. The transfer controller serially transfers data such that the data are respectively allocated to the plurality of stages. The plurality of column blocks temporarily stores the data. The column selector selects a column block for each of the plurality of stages from the plurality of column blocks, and transfers the data parallel between the plurality of stages and the column blocks selected for the plurality of stages. The data bus extends from one end to the other in a direction in which the plurality of column blocks are arranged, and returns from the other end to the one end. 
     Each embodiment of the present invention will be explained below with reference to the accompanying drawings. Note that in the following explanation, the same reference numerals or symbols denote almost or practically the same functions and constituent elements, and a repetitive explanation will be made as needed. 
     First Embodiment 
     In this embodiment, serial data transfer is performed by a data unit such as a page. In this embodiment, a bus for receiving readout data from an internal data latch (column register) or supplying write data to the data latch is divided into a plurality of stages, and a pipeline operation is performed. This embodiment thus implements large-band-width data transfer. 
     In this embodiment, the data transfer bus extends from one end to the other in a direction in which column blocks of a memory chip are arranged, and returns from the other end to the original end. 
     Although the data size of readout data and write data is a page size in this embodiment, the data size may also be larger or smaller than a page. 
       FIG. 1  is a plan block diagram showing an example of an arrangement of a semiconductor memory device according to this embodiment. A semiconductor memory device  1  may have an arrangement almost axially symmetrical with respect to a central line C in a plane. In the following description, the semiconductor memory device  1  will be explained based on the left-side arrangement shown in  FIG. 1 . 
       FIG. 2  is a sectional block diagram showing an example of the arrangement of the semiconductor memory device  1  according to this embodiment. 
     The semiconductor memory device  1  is, e.g., a bit cost scalable semiconductor memory device (a three dimensional stracked array structure device), and performs data read and write. The semiconductor memory device  1  includes a memory cell array  2 , a plurality of column blocks C(0+4×0), . . . , C(0+4×n), C(1+4×0), . . . , C(1+4×n), C(2+4×0), . . . , C(2+4×n), and C(3+4×0), . . . , C(3+4×n), a column selector CS, a data bus DB, transfer control circuits TC 0  to TC 2 , and a clock signal line CSL. 
     The memory cell array  2  is formed above at least part of circuits on a semiconductor substrate  20 . 
     The plurality of column blocks C(0+4×0), . . . , C(0+4×n), C(1+4×0), . . . , C(1+4×n), C(2+4×0), . . . , C(2+4×n), and C(3+4×0), . . . , C(3+4×n) include an internal data latch and temporarily store data. 
     The plurality of column blocks C(+4×0), . . . , C(0+4×n), C(1+4×0), . . . , C(1+4×n), C(2+4×0), . . . , C(2+4×n), and C(3+4×0), . . . , C(3+4×n) are arranged in this order, for example, from one end to the other in a column block arrangement direction of the memory chip, wherein n is an integer of 1 or more. When i is an integer represented by 0≦i≦n and r is one of 0, 1, 2, and 3, a reference symbol of a column block is expressed by C(r+4×i). In the reference symbol C(r+4×i) of the column block, the integer i changes from 0 to n when r=0, changes from 0 to n when r=1, changes from 0 to n when r=2, and finally changes from 0 to n when r=3. 
     Of the plurality of column blocks C(0), . . . , C(3+4×n),  FIG. 1  shows the column blocks C(0+4×i), C(1+4×i), C(2+4×i), and C(3+4×i). 
     A controller  3  controls the semiconductor memory device  1 . 
     The data bus DB is divided into a plurality of stages S 0  to S 3  based on the transfer control circuits TC 0  to TC 2 . In this embodiment, the plurality of stages S 0  to S 3  are arranged in series from the output side to the input side of the data bus DB. 
     The data bus DB extends from one end to the other in the direction in which the plurality of column blocks C(0), . . . , C(3+4×n) are arranged, returns at the other end, and extends from the other end to the one end. 
     This embodiment will be explained by taking an arrangement in which the data bus DB is divided into the four stages S 0  to S 3  as an example. However, it is only necessary to divide the first half of the data bus DB which extends from one end to the other into two or more portions, and divide the second half of the data bus DB which returns from the other end to the one end into two or more portions, i.e., divide the data bus DB into four or more portions in total. 
     The memory cell array  2  and peripheral circuits such as the plurality of column blocks C(0), . . . , C(3+4×n) and the column selector CS are stacked. More specifically, the memory cell array  2  is formed above the plane of the semiconductor substrate  20 , and the peripheral circuits such as the plurality of column blocks C(0), . . . , C(3+4×n) and the column selector CS are formed for the plane of the semiconductor substrate  20  below the memory cell array  2 . That is, in this embodiment, the peripheral circuits may be formed between the memory cell array  2  and semiconductor substrate  20 . Note that it is also possible to stack the memory cell array  2  and the controller  3 , or stack the memory cell array  2  and the data bus DB and transfer control circuits TC 0  to TC 2 , i.e., form the data bus DB and transfer control circuits TC 0  to TC 2  between the memory cell array  2  and semiconductor substrate  20 . 
     The memory cell array  2  is, e.g., a NAND flash memory, a NOR flash memory, or another kind of a flash memory. The memory cell array  2  may also be a bit cost scalable cell array. 
     A plurality of memory cells of the memory cell array  2  are formed at the intersections of a plurality of word lines WL 0  to WLx and a plurality of bit lines BL 0 , . . . , BL(3+4×n). 
     The column blocks C(0), . . . , C(3+4×n) include sense amplifiers SA(0), . . . , SA(3+4×n), data latches (page registers) DL(0), . . . , DL(3+4×n), an arithmetic circuit (not shown), and a control circuit (not shown), respectively.  FIG. 1  shows the sense amplifiers SA(0+4×i), SA(1+4×i), SA(+4×i), and SA(3+4×i) of the sense amplifiers SA(0), . . . , SA(3+4×n), and the data latches DL(0+4×i), DL(1+4×i), DL(2+4×i), and DL(3+4×i) of the data latches DL(0), . . . , DL(3+4×n). 
     In this embodiment, the column blocks C(0+4×0), . . . , C(0+4×n) correspond to the stage S 0 , the column blocks C(1+4×0), . . . , C(1+4×n) correspond to the stage S 3 , the column blocks C(2+4×0), . . . , C(2+4×n) correspond to the stage S 2 , and the column blocks C(3+4×0), . . . , C(3+4×n) correspond to the stage S 1 . 
     The column selector CS selects column blocks as targets of parallel data read or write, for each of the stages S 0  to S 3 . 
     The clock signal line CSL supplies a common clock signal to the column selector CS, column blocks C(0), . . . , C(3+4×n), and transfer control circuits TC 0  to TC 2 . The column selector CS, column blocks C(0), . . . , C(3+4×n), and transfer control circuits TC 0  to TC 2  operate based on this clock signal. 
     The transfer control circuits TC 0  to TC 2  are formed between the stages S 0  to S 3 , and serially transfer data D(0+4×0), D(1+4×0), D(2+4×0), D(3+4×0), . . . , D(0+4×n), D(1+4×n), D(2+4×n), and D(3+4×n) in this order from a preceding stage to a succeeding stage. 
     A reference symbol of data is expressed by D(r+4×i). In this data number D(r+4×i), r changes to 0, 1, 2, and 3 when i=0, changes to 0, 1, 2, and 3 when i=1, and changes to 0, 1, 2, and 3 when i=n.  FIG. 1  shows the data D(0+4×i), D(1+4×i), D(2+4×i), and D(3+4×i) of the data D(0), D(1), D(2), D(3), . . . , D(3+4×n). 
     The transfer control circuits TC 0  to TC 2  set four data on the stages S 0  to S 3  by serial transfer within one write timing for the column blocks. Also, the transfer control circuits TC 0  to TC 2  output four data set to the stages S 0  to S 3  by serial transfer within one read timing for the column blocks. 
     For example, flip-flop circuits may be used as the transfer control circuits TC 0  to TC 2 . 
     The transfer control circuits TC 0  to TC 2  serially transfer four data on the stages S 0  to S 3  between the timing at which data are stored in the data latches of four column blocks designated by column addresses, and the timing at which new data are stored in the data latches of four column blocks designated by new column addresses. That is, in this embodiment, one storage cycle of four data with respect to four data latches corresponds to four transfer cycles of the data bus DB. 
     The transfer control circuits TC 0  to TC 2 , column selector CS, and column blocks C(0), . . . , C(3+4×n) perform, e.g., a pipeline operation under the control of a common clock. 
       FIG. 3  is a timing chart showing an example of a write operation according to this embodiment. 
     The transfer control circuits TC 0  to TC 2  serially transfer data D(0), D(1), D(2), and D(3) within a write timing T 1 , and allocates the data D(0), D(1), D(2), and D(3) to the stages S 0 , S 1 , S 2 , and S 3 , respectively. 
     At a next write timing T 2 , the column selector CS transfers the data D(0), D(1), D(2), and D(3) allocated to the stages S 0 , S 1 , S 2 , and S 3  parallel to the column blocks C(0), C(3), C(2), and C(1) designated (selected) by column addresses in the stages S 0 , S 1 , S 2 , and S 3 . 
     Also, at the write timing T 2 , the transfer control circuits TC 0  to TC 2  serially transfer new data D(4), D(5), D(6), and D(7), and allocate the data D(4), D(5), D(6), and D(7) to the stages S 0 , S 1 , S 2 , and S 3 , respectively. A write operation after that is the same as described above. In this write operation, the data D(0+4×i), D(1+4×i), D(2+4×i), and D(3+4×i) are respectively allocated from the stages S 0 , S 1 , S 2 , and S 3  to the column blocks C(0+4×i), C(3+4×i), C(2+4×i), and C(1+4×i). 
       FIG. 4  is a timing chart showing an example of a read operation according to this embodiment. 
     At a read timing T 3 , the column blocks C(0), C(3), C(2), and C(1) designated (selected) by column addresses on the stages S 0 , S 1 , S 2 , and S 3  respectively receive the data D(0), D(1), D(2), and D(3) read out from the memory cell array  2 . The column selector CS allocates the data D(0), D(1), D(2), and D(3) received by the column blocks C(0), C(3), C(2), and C(1) to the stages S 0 , S 1 , S 2 , and S 3 , respectively, by parallel transfer. 
     At a read timing T 4 , the transfer control circuits TC 0  to TC 2  serially (sequentially) transfer the data D(0), D(1), D(2), and D(3) allocated to the stages S 0 , S 1 , S 2 , and S 3 . At the read timing T 4 , the column blocks C(4), C(7), C(6), and C(5) designated (selected) by new column addresses respectively receive next data D(4), D(5), D(6), and D(7) read out from the memory cell array  2 . The read operation after that is the same as described above. In this read operation, the data D(0+4×i), D(1+4×i), D(2+4×i), and D(3+4×i) are respectively allocated from the column blocks C(0+4×i), C(3+4×i), C(2+4×i), and C(1+4×i) to the stages S 0 , S 1 , S 2 , and S 3 . 
     A conventional semiconductor memory device will be explained below in comparison to the semiconductor memory device  1  of this embodiment. 
       FIG. 5  is a block diagram showing an example of an outline of the arrangement of the conventional semiconductor memory device. 
     A semiconductor memory device  11  includes a memory cell array  12 , a column selector  13 , and a plurality of column blocks  140  to  14   k . The plurality of column blocks  140  to  14   k  include data latches  150  to  15   k  and sense amplifiers  160  to  16   k  respectively, and hold write data and readout data. 
     The column selector  13  selects a specific column block designated by a column address according to each block cycle of a clock signal line  17 , and stores data of a data bus  18  in a specific data latch in turn. When the semiconductor memory device  11  is a large-capacity file memory, the number of column blocks  140  to  14   k  increases, and the data bus  18  becomes longer. This makes high-speed data transfer difficult. Also, when the semiconductor memory device  11  is a bit cost scalable semiconductor memory device, the bit cost can further be decreased by forming the memory cell array  12  in a layer above transistors, and forming peripheral circuits such as the column selector  13  and column blocks  140  to  14   k  below the memory cell array  12 . However, if the memory cell array  12  is formed above the peripheral circuits, the connection between a low-resistance global interconnection formed above the memory cell array  12  and the peripheral circuits below the memory cell array  12  is limited. This makes it difficult to perform high-speed data transfer from the low-resistance global interconnection to the peripheral circuits below the memory cell array  12 . 
       FIG. 6  is a block diagram showing an example of an outline of the arrangement of the semiconductor memory device  1  according to this embodiment. Note that  FIG. 6  shows only the column blocks C(0+4×i), C(1+4×i), C(2+4×i), and C(3+4×i) of the column blocks C(0), . . . , C(3+4×n), as in  FIG. 1  described above. 
     As described above, it is difficult for the semiconductor memory device  11  shown in  FIG. 5  to perform high-speed data transfer. By contrast, in this embodiment, even when it is difficult to increase the operation speed of the circuits arranged below the memory cell array  2 , pipeline processing is applied to correct a difference between the circuits arranged below the memory cell array  2  and external high-speed data transfer. 
     In the semiconductor memory device  1  according to this embodiment, the data bus DB for transferring the data D(0+4×0), . . . , D(3+4×n) to the data latches DL(0+4×0), . . . , DL(0+4×n), DL(1+4×0), . . . , DL(1+4×n), DL(2+4×0), . . . , DL(2+4×n), and DL(3+4×0), . . . , DL(3+4×n) is divided into the stages S 0  to S 3 , and a pipeline operation is performed for the plurality of stages S 0  to S 3 . 
     The data bus DB extends from one end to the other end of a memory cell array (memory chip), returns at the other end, and extends from the other end to the one end. 
     Since the data bus DB is divided into the short stages S 0  to S 3 , high-speed data transfer can be performed. 
     The transfer control circuits TC 0  to TC 2  divide the data bus DB into two stages in each of a portion extending from one end to the other and a portion returning from the other end to the one end, i.e., into a total of four stages. The transfer control circuits TC 0  to TC 2  is controlled using a clock from the clock signal line CSL. The stages S 0  to S 3  store the data D(0+4×i), D(1+4×i), D(2+4×i), and D(3+4×i) in the data latches DL(0+4×i), DL(3+4×i), DL(2+4×i), and DL(1+4×i) or read out the data D(0+4×i), D(1+4×i), D(2+4×i), and D(3+4×i) from the data latches DL(0+4×i), DL(3+4×i), DL(2+4×i), and DL(1+4×i) parallel by a pipeline operation. 
     A column selector CS 0  selects specific column blocks in turn for the stages S 0  and S 3 , and stores data of the stages S 0  and S 3  in specific data latches in turn, or provides data stored in the specific data latches for the stages S 0  and S 3 , for every four cycles. A column selector CS 1  selects specific column blocks in turn for the stages S 1  and S 2 , and stores data of the stages S 1  and S 2  in specific data latches in turn, or provides data stored in the specific data latches for the stages S 1  and S 2 , for every four cycles. That is, the column selector CS 0  receives data from the stages S 0  and S 3  or provides data for the stages S 0  and S 3 . The column selector CS 1  receives data from the stages S 1  and S 2  or provides data for the stages S 1  and S 2 . 
     Since the column blocks C(0), . . . , C(3+4×n) operate parallel, they can operate by the number of cycles four times that when no pipeline operation is performed. 
     In addition, in this embodiment, the length of one stage of the data bus DB in the column block arrangement direction is half that of the data bus  18  of the conventional semiconductor memory device  11 . Therefore, the RC time constant of the data bus DB is ¼ that of the conventional data bus  18 . Accordingly, even when the resistance per unit length of the interconnection of an internal data bus is high or the capacitance is large, it is possible to correspond to a large bandwidth of an external data bus. 
     Note that in this embodiment, the clock signal line CSL is not divided unlike the data bus DB. To prevent a clock delay, therefore, a low-resistance global interconnection or the like is desirably applied as the clock signal line CSL. 
     In the semiconductor memory device  1  according to this embodiment explained above, the data bus DB for transferring data to the internal data latches DL(0+4×0), . . . , DL(0+4×n), DL(1+4×0), . . . , DL(1+4×n), DL(2+4×0), . . . , DL(2+4×n), and DL(3+4×0), . . . , DL(3+4×n) is divided into the stages S 0  to S 3 . In this embodiment, write from the stages S 0  to S 3  to the data latches DL(0+4×0), . . . , DL(3+4×n) and read from the data latches DL(0+4×0), . . . , DL(3+4×n) to the stages S 0  to S 3  are implemented by a pipeline operation. Accordingly, data transfer can be performed with a large bandwidth. 
     In this embodiment, the data bus DB has a returning structure. This makes it possible to transfer data in one direction in the data bus DB, and continuously perform a pipeline operation. 
     Second Embodiment 
     The above-mentioned first embodiment includes the transfer control circuits TC 0  to TC 2  controlled by a clock, as circuits for dividing the data bus DB into the stages S 0  to S 3 . 
     By contrast, transfer control circuits according to this embodiment control data transfer by exchanging (handshaking) a transmission notification signal Send and acknowledgement signal Ack. 
       FIG. 7  is a block diagram showing an example of data transfer control performed by transfer control circuits according to this embodiment. 
     Transfer control circuits  190  to  193  according to this embodiment respectively correspond to stages S 0  to S 3 . The transfer control circuits  190  to  193  are, e.g., asynchronous self-timing data transfer circuits. Adjacent transfer control circuits exchange data, the transmission notification signal Send, and acknowledgement signal Ack. 
     Data transfer control executed by the transfer control circuits  190  to  193  will be explained by using the first transfer control circuit  193 , second transfer control circuit  192 , and third transfer control circuit  191 . 
     The first transfer control circuit  193  corresponding to the stage S 3  transfers data to the second transfer control circuit  192  corresponding to the stage S 2 , and transfers the transmission notification signal Send indicating the transmission of the data to the second transfer control circuit  192 . 
     The second transfer control circuit  192  receives the data transferred from the first transfer control circuit  193 , and returns the acknowledgement signal Ack to the first transfer control circuit  193 . Also, the second transfer control circuit  192  transfers the data to the third transfer control circuit  191 , and transfers the transmission notification signal Send to the third transfer control circuit  191 . 
     The first transfer control circuit  193  having received the acknowledgement signal Ack from the second transfer control circuit  192  stops transmitting the transmission notification signal Send to the second transfer control circuit  192 . 
     Adjacent transfer control circuits alternately handshake the transmission notification signal Send and acknowledgement signal Ack, thereby performing an asynchronous pipeline operation. 
     The transfer control circuits  190  to  193  according to this embodiment require no clock from a global clock signal line CSL. Therefore, even when a data bus DB and the transfer control circuits  190  to  193  are arranged below a memory cell array  2  and the use of a low-resistance interconnection is restricted, high-speed data transfer can be performed by using a pipeline operation. 
     In this embodiment, the necessary area of the semiconductor memory device can be reduced by arranging the data bus DB and transfer control circuits  190  to  193  below the memory cell array  2 . 
     In this embodiment explained above, data transfer for a pipeline operation is asynchronously performed at a self-timing. This makes it possible to transfer data with a large bandwidth even in a high-interconnection-resistance environment below the memory cell array  2 . 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.