Patent Publication Number: US-11381164-B1

Title: Pre-charge technique for improved charge pump efficiency

Description:
TECHNICAL FIELD 
     The present disclosure relates to charge pumps in data storage systems. 
     BACKGROUND 
     Non-volatile memories, such as flash memory devices, have supported the increased portability of consumer electronics, and have been utilized in relatively low power enterprise storage systems suitable for cloud computing and mass storage. The ever-present demand for almost continual advancement in these areas is often accompanied by demand to improve data storage capacity. The demand for greater storage capacity, in turn, stokes demand for greater performance (e.g., quicker reads and writes), so that the addition of storage capacity does not slow down the memory device. As such, there is ongoing pressure to increase the capacity and the efficiency of non-volatile memories in order to further improve the useful attributes of such devices. 
     SUMMARY 
     This application describes various systems and methods for improving the efficiency of a charge pump for an array of memory cells of a storage medium. Various implementations of systems and methods within the scope of the appended claims each have several aspects, no single one of which is solely responsible for the desirable attributes described herein. Without limiting the scope of the appended claims, some prominent features are described. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of various implementations are used to improve write performance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       So that the present disclosure can be understood in greater detail, a more particular description may be had by reference to the features of various implementations, some of which are illustrated in the appended drawings. The appended drawings, however, merely illustrate the more pertinent features of the present disclosure and are therefore not to be considered limiting, for the description may admit to other effective features. 
         FIG. 1  is a block diagram of a data storage system in accordance with some implementations. 
         FIG. 2  is a block diagram of an array of memory cells and a charge pump in accordance with some implementations. 
         FIG. 3  is a circuit diagram of a charge pump in accordance with some implementations. 
         FIG. 4  depicts timing diagrams for a charge clock, a kick clock, a gate control node, an intermediate stage node, and a final stage node of the charge pump depicted in  FIG. 3  in accordance with some implementations. 
         FIG. 5  is a flow diagram of a method for charging the charge pump depicted in  FIG. 3  in accordance with some implementations. 
     
    
    
     In accordance with common practice, the various features illustrated in the drawings may not be drawn to scale. Accordingly, the dimensions of the various features may be arbitrarily expanded or reduced for clarity. In addition, some of the drawings may not depict all of the components of a given system, method or device. Finally, like reference numerals are used to denote like features throughout the specification and figures. 
     DETAILED DESCRIPTION 
       FIG. 1  is a diagram of an implementation of a data storage environment, namely data storage system  100 . While certain specific features are illustrated, those skilled in the art will appreciate from the present disclosure that various other features have not been illustrated for the sake of brevity, and so as not to obscure more pertinent aspects of the example implementations disclosed herein. To that end, as a non-limiting example, the data storage system  100  includes a data processing system (alternatively referred to herein as a computer system or host)  110 , and a storage device  120 . 
     The computer system  110  is coupled to the storage device  120  through data connections  101 . In various implementations, the computer system  110  includes the storage device  120  as a component. Generally, the computer system  110  includes any suitable computer device, such as a computer, a laptop computer, a tablet device, a netbook, an internet kiosk, a personal digital assistant, a mobile phone, a smartphone, a gaming device, a computer server, a peripheral component interconnect (PCI), a serial AT attachment (SATA), or any other computing device. In some implementations, the computer system  110  includes one or more processors, one or more types of memory, a display, and/or other user interface components such as a keyboard, a touch screen display, a mouse, a trackpad, a digital camera, and/or any number of supplemental devices to add functionality. 
     The storage device  120  includes one or more storage mediums  130  (e.g., N storage mediums  130 , where N is an integer greater than or equal to 1). The storage medium(s)  130  are coupled to a storage controller  124  through data connections of a channel  103 . In various implementations, the storage controller  124  and storage medium(s)  130  are included in the same device (e.g., storage device  120 ) as constituent components thereof, while in other embodiments, the storage controller  124  and storage medium(s)  130  are, or are in, separate devices. In some embodiments, the storage controller  124  is an application-specific integrated circuit (ASIC). The storage medium(s)  130  are optionally referred to as the NAND. 
     Each storage medium  130  includes control circuitry  132  and data storage  134 . The data storage  134  may comprise any number (i.e., one or more) of memory devices including, without limitation, non-volatile semiconductor memory devices, such as flash memory (also referred to as memory cells). Flash memory devices can be configured for enterprise storage suitable for applications such as cloud computing, and/or configured for relatively smaller-scale applications such as personal flash drives or hard-disk replacements for personal, laptop and tablet computers. 
     In some implementations, the storage controller  124  includes a management module  121 , an error control module  125 , a storage medium interface  128 , and a host interface  129 . In some implementations, the storage controller  124  includes various additional features that have not been illustrated for the sake of brevity, so as not to obscure more pertinent features of the example implementations disclosed herein. As such, a different arrangement of features may be possible. 
     The host interface  129  couples the storage device  120  and its storage controller  124  to one or more computer systems  110 . The host interface  129  typically includes data buffers (not shown) to buffer data being received and transmitted by the storage device  120  via the data connections  101 . 
     The storage medium interface  128  couples the storage controller  124  to the storage medium(s)  130 . The storage medium interface  128  provides an interface to the storage medium(s)  130  though the data connections of the channel  103 . In some implementations, the storage medium interface  128  includes read and write circuitry. 
     The error control module  125  is coupled between the storage medium interface  128  and the host interface  129 . In some implementations, the error control module  125  is provided to limit the number of uncorrectable errors inadvertently introduced into data. To that end, the error control module  125  includes an encoder  126  and a decoder  127 . The encoder  126  encodes data to produce a code word, which is subsequently stored in a storage medium  130 . When the encoded data is read from the storage medium  130 , the decoder  127  applies a decoding process to recover the data and correct errors within the error correcting capability of the error control code. Various error control codes have different error detection and correction capacities, and particular codes are selected for various applications. 
     The management module  121  typically includes one or more processors  122  (sometimes referred to herein as CPUs, processing units, hardware processors, processors, microprocessors or microcontrollers) for executing modules, programs and/or instructions stored in memory and thereby performing processing operations. However, in some implementations, the processor(s)  122  are shared by one or more components within, and in some cases, beyond the function of the storage controller  124 . The management module  121  is coupled by communication buses to the host interface  129 , the error control module  125 , and the storage medium interface  128  in order to coordinate the operation of these components. 
     The management module  121  also includes memory  123  (sometimes referred to herein as controller memory), and one or more communication buses for interconnecting the memory  123  with the processor(s)  122 . Communication buses optionally include circuitry (sometimes called a chipset) that interconnects and controls communications between system components. The controller memory  123  includes high-speed random access memory, such as DRAM, SRAM, DDR RAM or other random access solid state memory devices, and may include non-volatile memory, such as one or more magnetic disk storage devices, optical disk storage devices, flash memory devices, or other non-volatile solid state storage devices. The controller memory  123  optionally includes one or more storage devices remotely located from the one or more processors  122 . In some embodiments, the controller memory  123 , or alternatively the non-volatile memory device(s) within the controller memory  123 , comprises a non-transitory computer readable storage medium. In some embodiments, the controller memory  123 , or the non-transitory computer readable storage medium of the controller memory  123 , stores the programs, modules, and/or data structures, or a subset or superset thereof, for performing one or more of the operations described in this application with regard to any of the components associated with the storage controller  124 . 
     In some embodiments, the various operations described in this application correspond to sets of instructions for performing the corresponding functions. These sets of instructions (i.e., modules or programs) need not be implemented as separate software programs, procedures or modules, and thus various subsets of these modules may be combined or otherwise rearranged in various embodiments. In some embodiments, the memory  123  may store a subset of modules and data structures. Furthermore, the memory  123  may store additional modules and data structures. In some embodiments, the programs, modules, and data structures stored in the memory  123 , or the non-transitory computer readable storage medium of the memory  123 , provide instructions for implementing any of the methods described below. Stated another way, the programs or modules stored in the memory  123 , when executed by the one or more processors  122 , cause the storage device  120  to perform any of the operations described below. Although  FIG. 1  shows various modules,  FIG. 1  is intended more as a functional description of the various features, which may be present in the modules than as a structural schematic of the embodiments described herein. In practice, the programs, modules, and data structures shown separately could be combined, and some programs, modules, and data structures could be separated. 
       FIG. 2  depicts a block  200  of memory cells (e.g.,  202 ) in a data storage  134  of a storage medium  130  ( FIG. 1 ). The memory cells communicate with respective word lines WL 0 -WL 7  ( 210 ), respective bit lines BL 0 -Bd- 1 , and a common source line  205 . In the example provided, eight memory cells are connected in series to form a NAND string, and there are eight data word lines WL 0  through WL 7 . One terminal of each NAND string is connected to a corresponding bit line via a drain select gate (connected to select gate drain line SGD), and another terminal is connected to a common source  205  via a source select gate (connected to select gate source line SGS). Thus, the common source  205  is coupled to each NAND string. The block  200  may be one of many such blocks in a memory array of data storage  134  ( FIG. 1 ). 
     In an erase operation, a high voltage (e.g., 20 V) may be applied to a substrate on which the NAND string is formed to remove charge from the memory cells. During a programming operation, a voltage (e.g., in the range of 12-21 V) may be applied to a selected word line. In one approach, step-wise increasing program pulses are applied until a memory cell is verified to have reached an intended state. Moreover, pass voltages at a lower level may be applied concurrently to the unselected word lines. In read and verify operations, the select gates (SGD and SGS) may be connected to a voltage (e.g., in the range of 2.5 to 4.5 V) and the unselected word lines may be raised to a read pass voltage (e.g., in the range of 4.5 to 6 V) to make the transistors operate as pass gates. The selected word line is connected to a voltage, a level of which is specified for each read and verify operation, to determine whether a threshold voltage of the concerned memory cell is above or below such level. 
     The voltage levels described above may be higher than an available supply voltage of the storage device  120 . To accommodate such voltage levels, a charge pump  220  may be used. The charge pump  220  may provide such voltages at different levels during erase, program, or read operations for the memory cells of the block  200 . The output of the charge pump  220  may be used to provide different voltages concurrently to different word lines or groups of word lines. It is also possible to use multiple charge pumps  220  to supply different word line voltages. Similarly, the output from a charge pump can be provided to a bit line or other location as needed in the memory device. 
     Charge Pumps are important building blocks for memory devices as described herein. As noted above, they may be used for providing appropriate bias voltage levels for performing erase, program, and read operations. Charge pumps may convert a fixed input voltage to a higher output voltage as per the biasing requirements. Most of the power consumed by charge pumps employed to bias an array of memory cells may be during a ramp-phase. This is so because a charge pump typically needs to charge a very high capacitor from a reset voltage to a target voltage level. The charge pump  220 , as described herein, improves efficiency such that power consumption can be reduced, directly affecting the overall current consumption of the media streaming device  210  during memory operations. 
       FIG. 3  is a circuit diagram of the charge pump  220  in accordance with some implementations. The charge pump  220  includes two subsets of voltage multiplying circuitry (depicted in the left half of the figure and the right half of the figure), with each subset operating in different clock phases. Each subset multiplies an input voltage Vin by alternately charging respective high voltage capacitors C HV  and C HV ′ to provide a multiplied output voltage Vout. Since the circuitry in each subset behaves similarly (other than the phase difference of clocks K CLK  and Q CLK ), the following description is with respect to the subset depicted in the left half of the figure. The same functionality (accounting for the difference in clock phases) applies to the subset depicted in the right half of the figure. Features shared between each subset are similarly labeled, and some are not further discussed for purposes of brevity, and so as not to obscure more pertinent aspects of the example implementations disclosed herein. 
     The voltage multiplying circuitry of charge pump  220  includes a plurality of stages, such as a first stage  302 , a second stage  304 , and a third stage  306 . The first and second stages may be referred to as low voltage stages, and the third stage may be referred to as a high voltage stage. While the figure depicts three stages, more stages may be implemented without departing from the concepts described herein. The first stage  302  includes a first low voltage capacitor C LV1 , the second stage includes a second low voltage capacitor C LV2 , and the third stage includes a high voltage capacitor C HV . 
     Each capacitor may be charged to a first voltage level during a first phase (charge phase), and then charged to a higher voltage level during a subsequent phase (kick phase). During the charge phase, a given capacitor is connected across a voltage supply (e.g., Vin), charging it to that same voltage. During the kick phase, the circuitry around the capacitor is reconfigured so that the capacitor is in series with the supply and an output node. This doubles the voltage at the output node (e.g., to 2*Vin, the sum of the original voltage supply and the capacitor voltage). 
     For example, when charging C LV1 , K CLK  may be grounded and transistor M 12  may connect node KN 2  to voltage supply Vin, thereby charging C LV1  from 0 to Vin. When K CLK  goes high in the next clock phase, voltage supply Vin is disconnected by transistor M 12  and C LV1  gets kicked (the capacitor is charged to a higher level through its bottom plate) by the K CLK  signal. If the K CLK  signal is equal to Vin, then node KN 2  nodes increases from Vin to 2*Vin. In general, once a capacitor at a given stage is initially charged, and then its bottom plate is kicked, the voltage at the node at the top plate of the capacitor may increase to a higher level than is available at the storage device  120 . 
     The capacitor at a given stage may be kicked by voltage supplied by the preceding stage. The charge may keep building to the last stage in order to realize the final voltage Vout. However, by multiplying the voltage stage by stage in such a manner, an increasing amount of supply current may be lost, which may lead to significant drops in efficiency. For example, the high value capacitor C HV  in the final stage  306  realizes a desired output voltage Vout when its bottom plate (represented by C BOT ) is kicked by voltage present at node KNB. Depending on where this voltage comes from (e.g., if it is serially charged by each proceeding stage), different amounts of current required to charge C BOT  may be lost since the charge is never transferred to the output. 
     Accordingly, the charge pump  220 , as described in detail below, implements an improved technique for kicking the bottom plate of the capacitor in the final stage  306 . This improved technique kicks the bottom plate of the final stage capacitor in a plurality of steps, optimizing the voltage source for each step such that power losses are minimized. Specifically, the technique described below with reference to  FIGS. 3-5  minimizes the charge taken from the least efficient supply at node KN 3 , thereby improving efficiency. Instead of charging C BOT  directly from 0 to 3*Vin using the voltage available at node KN 3  (the least efficient supply), the technique described herein charges C BOT  (i) from 0 to Vin directly from the Vin supply (the most efficient supply), (ii) from Vin to 2*Vin from the voltage available at node KN 2  (a moderately efficient supply), and (iii) from 2*Vin to 3*Vin from the voltage available at node KN 3  (the least efficient supply). These three steps correspond to operations  502 ,  504 , and  506 , respectively, of method  500  in  FIG. 5  (described in more detail below). 
     Referring back to  FIG. 3 , circuitry  308   a  and  308   b  implement the first step (operation  502 ). Circuitry  308   a  charges C BOT  from 0 to Vin by feeding the supply voltage Vin to node KNB during the pre-charging phase (operation  502 ), and then cuts itself off from the rest of the charge pump circuitry once pre-charging is completed, as described in more detail below. 
     Circuitry  308   a  includes an inverter U 1  in series with clock signal Q CLK  and the drain of transistor M 1 . Transistor M 1  may be an NMOS having a negative threshold voltage. As such, transistor M 1  is on/conducting when the gate voltage with respect to the source is 0V (since 0V is higher than the negative threshold voltage). The drain of transistor M 1  is connected to the inverter U 1  (depicted as node M 1   d ), and the source of transistor M 1  is connected to node KNB. The gate of transistor M 1  is controlled by gate control signal M 1   g , which is controlled by circuitry  308   b.    
     Circuitry  308   b  includes an inverter U 2  in series with clock signal Q CLK  and two parallel transistors M 2  and M 3 . Transistor M 2  may be a PMOS. As such, transistor M 2  conducts current between its source and drain when Q CLK  is high and the output of inverter U 2  is low. Transistor M 3  may be a diode-connected NMOS. Since the gate and drain of transistor M 3  are shorted, transistor M 3  is automatically on/conducting until M 1   g  discharges below a threshold voltage Vth of transistor M 3 . This ensures that after C BOT  is pre-charged from 0 to Vin, there is no back current across transistor M 1 . Specifically, M 1  turns off while charge is being delivered to C BOT  by nodes KN 2  and KN 3 , so charge is not delivered by M 1  during those times. 
       FIG. 4  depicts timing diagrams for charge clock Q CLK , kick clock K CLK , gate control M 1   g  for transistor M 1 , node KN 3 , and node KNB of the charge pump  220  in accordance with some implementations. The charge clock Q CLK  and kick clock K CLK  signals are inverted, so that when one is higher (e.g., Vin), the other is low (e.g.,  0 ), and vice versa. When the charge clock Q CLK  is high, this may be referred to as a charge phase, and when the kick clock K CLK  is high, this may be referred to as a kick phase. There is a nonzero amount of time between one clock signal going low and the other clock signal going high (e.g., between times t A  and t C ). The gate control signal M 1   g  is high while charge clock Q CLK  is high, and then discharges to a threshold voltage that turns transistor M 1  off while kick clock K CLK  is high, in order to avoid contention while the low voltage stages (C LV1  and C LV2 ) are kicking node KN 3  to 3*Vin. Node KNB (the node that kicks C BOT ) is pre-charged to Vin via the highly efficient storage device supply voltage (Vcc=Vin) at time t A  (when Q CLK  goes low) (operation  502 ), then charged to 2*Vin via the moderately efficient supply available at node KN 2  at time t B  (after Q CLK  goes low and before K CLK  goes high) (operation  504 ), and then charged to 3*Vin via the inefficient supply available at node KN 3  at time t C  (when K CLK  goes high) (operation  506 ). 
       FIG. 5  is a flow diagram of a method  500  for charging the charge pump  220  in accordance with some implementations. The method  500  charges the output node Vout to a multiple of the input supply voltage Vin. While the multiplier in this example is 6 (charging Vout to 6*Vin), other multipliers may be implemented without departing from the concepts described herein. For example, additional low voltage stages may be implemented (e.g., prior to stage  302 ), or fewer low voltage stages may be implemented (e.g., only stage  304 ). Proceeding with a voltage multiplier of 6, the method  500  charges C HV  to 3*Vin and C HV ′ to 3*Vin. As such, these two voltages add up to 6*Vin at the Vout node. Since the left side and the right side of the charge pump  220  are mirrored (as described above), the following description is with reference to the charging of C HV  (on the left side). Similar operations may be executed to charge C HV ′ for alternating clock cycles as described above. 
     To charge the C HV  to 3*Vin, the charge pump  220  performs three distinct operations (or three distinct phases of a charging operation): (i) a pre-charge operation or phase  502  using the most efficient voltage supply available to the charge pump, (ii) an intermediate charging operation or phase  504 , and (iii) a final charging operation or phase  506 . These operations kick the bottom plate capacitor C BOT  of the high voltage capacitor C HV  in the final stage  306  (at node KNB) to 3*Vin while minimizing the amount of charge taken from the stage prior to the final stage (stage  304  at node KN 3 ). 
     In the pre-charging operation  502 , circuitry  308   a  charges C BOT  from 0 to Vin. This is the most efficient charging operation since all of the supply current that is used by circuitry  308   a  to charge C BOT  is passed to the output node Vout. In order to charge C BOT , transistor M 1  provides a path from Vin (provided by inverted Q CLK  signal, see  FIG. 4 ) to node KNB. Specifically, in the charge phase, Q CLK  is high. Inverter U 2  inverts Q CLK  to logic low (approximately 0V) and provides the low signal to the gate of PMOS transistor M 2 , which turns on the transistor M 2 , thereby passing Q CLK  to M 1   g . As a result, M 1   g  is biased at Vin, which allows C BOT  to be pre-charged to Vin by circuitry  308   a  at time t A . 
     Specifically, when Q CLK  goes low at the end of the charge phase (at time t A ), inverter U 2  inverts the low signal to logic high (approximately Vin) and provides the high signal to the gate of PMOS transistor M 2 , which causes transistor M 2  to turn off, which causes M 1   g  to discharge from Vin to the threshold voltage (Vth) of transistor M 3  (transistor M 3  cuts off when M 1   g  discharges to Vth, causing M 1   g  to remain at Vth). Transistor M 1  remains on because it is a negative threshold voltage device, as described above. The source of transistor M 1  was grounded during the charge phase (K CLK  was at 0). When Q CLK  transitions to 0 at time t A , inverter U 1  causes the drain of transistor M 1  (M 1   d ) to go high. This causes transistor M 1  to conduct current toward node KNB, causing C BOT  to charge from 0 to Vin (see the KNB timing diagram in  FIG. 4  at time t A ). 
     Importantly, transistor M 1  turns off when node KNB reaches very close to Vin (specifically, when the difference between the gate voltage of M 1  and Vin becomes less than the threshold voltage Vth of M 1 ). The turning off of transistor M 1  cuts off the pre-charging circuitry  308   a / 308   b  from the rest of the charge pump circuitry, thereby preventing current at node KNB from discharging through the pre-charging circuitry during subsequent operations. 
     In the next charging operation  504 , C BOT  is kicked from Vin to 2*Vin. First, when the pre-charging (operation  502 ) of C BOT  from 0 to Vin is completed, node M 1   d  (drain of transistor M 1 ) allows K CLK  to rise (at time t B ). More specifically, node M 1   d  is coupled to digital control circuitry (not shown) that controls the timing of K CLK . When pre-charging (operation  502 ) is complete, the voltage at node M 1   d  signals to the digital control circuitry that it is time for the kick clock K CLK  to rise. As such, the kick clock K CLK  will not rise until the pre-charge operation is complete, allowing for transistor M 1  to cut off the pre-charge circuitry  308   a / 308   b  before operations  504  and  506 . Stated another way, circuitry  308   a  sends a digital signal using node M 1   d , which enables K CLK  to go from 0 to 1 (see  FIG. 4 ). As such, the kick clock K CLK  may rise if and only if node M 1   d  goes high (controlled by logic, not shown). Before K CLK  rises (i.e., during the charge phase when K CLK  is still low), the charge at node KN 2  is equivalent to Vin. This charge (Vin) is passed to node KN 2   a  after Q CLK  has gone low, but before K CLK  has gone high. As a result, C LV2  has received a kick of Vin, which causes the voltage at node KN 3  (and by extension, node KNB) to increase to 2*Vin. The increased voltage at node KNB kicks C BOT  to 2*Vin. 
     In the final charging operation  506 , C BOT  is kicked from 2*Vin to 3*Vin. This is the least efficient charging operation due to the amount of supply current that is lost when charging from the kick clock K CLK  signal. However, since this operation merely charges C BOT  from 2*Vin to 3*Vin (rather than from 0 to 3*Vin), the amount of supply current that is lost may be minimized. The charge required for this operation is delivered when K CLK  goes high (equivalent to Vin) at time t C . As noted above, the kick K CLK  may rise if and only if node M 1   d  goes high. When kick clock K CLK  goes high (equivalent to Vin), this causes the voltage at nodes KN 2  and KN 2   a  to increase from Vin to 2*Vin, and the voltage at nodes KN 3  and KNB to increase from 2*Vin to 3*Vin. 
     As noted above, the kick provided to node KNB is done in three steps (operations  502 ,  504 , and  506 ) which minimizes the charge taken from node KN 3 . Hence, supply current losses are reduced as charge is taken from input supply voltage Vin (˜100% efficient supply) from 0 to Vin, and then from node KN 2  (˜45% efficient supply) from Vin to 2*Vin. Using this technique, charge taken from the least efficient supply, node KN 3 , is minimized. As a result, the charge pump  220  can more efficiently multiple the input voltage by a factor of 6 (the sum of 3*Vin at node KNB and 3*Vin at node QNB). 
     The foregoing description has been described with reference to specific implementations. However, the illustrative discussions above are not intended to be exhaustive or to limit the claims to the precise forms disclosed. Many variations are possible in view of the above teachings. The implementations were chosen and described to best explain principles of operation and practical applications, to thereby enable others skilled in the art. 
     The various drawings illustrate a number of elements in a particular order. However, elements that are not order dependent may be reordered and other elements may be combined or separated. While some reordering or other groupings are specifically mentioned, others will be obvious to those of ordinary skill in the art, so the ordering and groupings presented herein are not an exhaustive list of alternatives. 
     As used herein: the singular forms “a”, “an,” and “the” include the plural forms as well, unless the context clearly indicates otherwise; the term “and/or” encompasses all possible combinations of one or more of the associated listed items; the terms “first,” “second,” etc. are only used to distinguish one element from another and do not limit the elements themselves; the term “if” may be construed to mean “when,” “upon,” “in response to,” or “in accordance with,” depending on the context; and the terms “include,” “including,” “comprise,” and “comprising” specify particular features or operations but do not preclude additional features or operations.