Patent Publication Number: US-9430378-B2

Title: Differential delay compensation

Description:
PRIORITY APPLICATION 
     This application is a continuation of U.S. application Ser. No. 13/942,339, filed Jul. 15, 2013, now issued as U.S. Pat. No. 9,110,794, which is a continuation of U.S. application Ser. No. 13/229,455, filed Sep. 9, 2011, now issued as U.S. Pat. No. 8,488,631, which is a continuation of U.S. application Ser. No. 11/093,907, filed Mar. 30, 2005, now issued as U.S. Pat. No. 8,018,926, each of which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     The subject matter described herein relates generally to the field of electronic communication and more particularly to differential delay compensation. 
     Communication networks transmit data from an originator to a destination via a communication network that may include multiple transfer points, such as hardware routers, that receive data typically in the form of packets or data frames. Data transmission over fiber optics networks may conform to SONET and/or SDH standards. SONET and SDH are a set of related standards for synchronous data transmission over fiber optic networks. SONET is short for Synchronous Optical NETwork and SDH is an acronym for Synchronous Digital Hierarchy. 
     SONET/SDH networks may employ virtually concatenated payloads. Virtual concatenation partitions payload data into multiple virtual containers that may be assigned a single index, referred to as a Multiframe Indicator (MFI), and transmitted contemporaneously across different transmission media and/or different network paths. Because the payload data traverses different network paths, payload data transmitted contemporaneously can be received at different times, an effect referred to as differential delay. Differential delay can also result from pointer processing, or from other considerations. 
     Virtual concatenation compensates for differential delay at the receiving entity by reassembling the payload in an appropriate time-ordered sequence. Data from different members of a virtual concatenation group are stored in a memory at the receiver. Processing logic in the destination node reads payload data from members having the same MFI contemporaneously. To do this, the destination node may determine memory locations of members in the same group having the same MFI value at the same byte within the frame so that the data can be assembled correctly at the output of the data memory. Addressing data in this arrangement can be complex, as data is being received, assembled, and processed at varying points and may require data reading from or writing to the memory based on a variety of circumstances. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The detailed description is described with reference to the accompanying figures. 
         FIG. 1A  is a schematic illustration of a SONET/SDH communication system in accordance with one embodiment. 
         FIG. 1B  is a schematic illustration of a suitable system in accordance with one embodiment. 
         FIG. 2A  is a schematic illustration of write operations into a memory at a receiver. 
         FIG. 2B  is a schematic illustration of a memory at a receiver in accordance with one embodiment. 
         FIG. 3  is a flowchart illustrating operations in one embodiment of a method for writing data frames into a memory. 
         FIG. 4  is a flowchart illustrating operations in one embodiment of a method for reading data frames from a memory. 
         FIG. 5  is a schematic illustration of an eight-byte wide memory with N words in accordance with one embodiment. 
         FIG. 6  is a schematic illustration of one embodiment of a memory architecture in which M bytes of SDRAM store 64 STS-3c members. 
     
    
    
     DETAILED DESCRIPTION 
     Described herein are exemplary systems and methods for differential delay compensation in a communication system. In the following description, numerous specific details are set forth in order to provide a thorough understanding of various embodiments. However, it will be understood by those skilled in the art that the various embodiments may be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the particular embodiments. 
     The methods described herein may be embodied as logic instructions on a computer-readable medium. When executed on a processor, the logic instructions cause a processor to be programmed as a special-purpose machine that implements the described methods. The processor, when configured by the logic instructions to execute the methods described herein, constitutes structure for performing the described methods. 
       FIG. 1A  is a schematic illustration of a SONET/SDH communication switching system in accordance with one embodiment. Referring to  FIG. 1A , SONET/SDH switching system  100  includes a transmitter  110  connected through a communication pathway  115  to a switching network  120 . Switching network  120  is connected through a communication pathway  125  to a destination  130 . 
     Transmitter  110  transmits data as a series of payloads/frames to the destination  130  through the switching network  120 . Packets may pass through a variety of hardware and/or software components, such as servers, routers, switches, etc. in transmission across switching network  120 . As each frame arrives at a hardware and/or software component, the component may store the frame briefly before transmitting the frame to the next component. The frames proceed through the network until they arrive at the destination  130 . The destination  130  may contain one or more processors  135  and/or one or more memory modules  140 . 
       FIG. 1B  is a schematic illustration of a suitable system in accordance with one embodiment. The system  101  may include a line card  111 , a line card  121 , a switch fabric  141 , and a backplane interface  131 . Line card  111  may be implemented as a SONET/SDH add-drop multiplexer, a Fibre Channel compatible line input, an Ethernet line input, a SONET/SDH line input, or the like. 
     Line card  121  may be implemented as a transceiver capable of transmitting and receiving frames and/or packets to and from a network that is compatible with SONET/SDH as well as other protocols such as OTN, TFI-5, and Ethernet, although other standards may be used. For example, SONET/SDH and OTN are described for example in: ITU-T Recommendation G.709 Interfaces for the optical transport network (OTN) (2001); ANSI T1.105, Synchronous Optical Network (SONET) Basic Description Including Multiplex Structures, Rates, and Formats; Bellcore Generic Requirements, GR-253-CORE, Synchronous Optical Network (SONET) Transport Systems: Common Generic Criteria (A Module of TSGR, FR-440), Issue 1, December 1994; ITU Recommendation G.872, Architecture of Optical Transport Networks, 1999; ITU Recommendation G.825, “Control of Jitter and Wander within Digital Networks Based on SDH” March, 1993; ITU Recommendation G.957, “Optical Interfaces for Equipment and Systems Relating to SDH”, July, 1995; ITU Recommendation G.958, Digital Line Systems based on SDH for use on Optical Fibre Cables, November, 1994; and/or ITU-T Recommendation G.707, Network Node Interface for the Synchronous Digital Hierarchy (SDH) (1996). For example, an implementation of TFI-5 is described in TFI-5: TDM Fabric to Framer Interface Implementation Agreement (2003) available from the Optical Internetworking Forum (OIF). For example, IEEE 802.3 describes Ethernet standards. 
     Switching network  120  may be any network such as the Internet, an intranet, a local area network (LAN), storage area network (SAN), a wide area network (WAN). One embodiment of line card  121  may include physical layer processor  122 , framer  124 , network processor  126 , and host-control plane controller  128 . 
     Physical layer processor  122  may receive optical or electrical signals from the network and prepare the signals for processing by downstream elements such as framer  124 . For example, for frames and/or packets received from the network, physical layer processor  122  may convert an optical signal to electrical format and/or remove jitter from signals from the network. For frames and/or packets to be transmitted to the network, physical layer processor  122  may remove jitter from signals provided by upstream devices such as framer  124  and prepare signals for transmission to the network, which may be optical or electrical format. 
     Framer  124  may utilize techniques described herein to process frames and/or packets received from a network. Framer  124  may transfer overhead from frames and/or packets to a higher layer level processor such as a network processor  126 . For example, framer  124  and network processor  126  may communicate using an interface compatible for example with SPI-4 (described for example in the Optical Internetworking Forum (OIF Document) OIF-SPI4-02.1 and ITU-T G.707 2000, T1.105-2001 (draft), T1.105.02-1995, and ITU-T recommendations G.7042 and G.707), although interfaces compatible with other standards may be used. 
     Network processor  126  may perform layer 2 or layer 3 (as well as other higher layer level) processing on frames and/or packets provided by and to framer  124  in conformance with applicable link, network, transport and application protocols. Network processor  126  also may perform traffic management at the IP layer. 
     Host-control plane controller  128  may configure operation of framer  124  and network processor  126 . For example, host-control plane controller  128  may program/provision framer  124  to control the content of frames. Host-control plane controller  128  may be implemented as separate from network processor  126  and communicate with the framer  124  and network processor  126  using an interface that complies with Peripheral Component Interconnect (PCI) Local Bus Specification, Revision 2.2, Dec. 18, 1998 available from the PCI Special Interest Group, Portland, Oreg., U.S.A. (as well as revisions thereof) or PCI-X Specification Rev. 1.0a, Jul. 24, 2000, available from the aforesaid PCI Special Interest Group, Portland, Oreg., U.S.A., although other standards may be used. Host-control plane controller  128  could be implemented as part of network processor  126 , although other implementations may be used. 
     In one embodiment, one or more of physical layer processor  122 , framer  124 , or network processor  126  may be coupled to volatile and/or nonvolatile memory module  127 . For example, memory module  127  may include one or more of the following: read-only memory (ROM), programmable ROM (PROM), erasable PROM (EPROM), electrically EPROM (EEPROM), a disk drive, a floppy disk, a compact disk ROM (CD-ROM), a digital video disk (DVD), flash memory, a magneto-optical disk, or other types of nonvolatile machine-readable media suitable for storing electronic instructions and/or data. 
     In one embodiment, components of line card  121  may be implemented among the same integrated circuit. In another embodiment, components of line card  121  may be implemented among several integrated circuits that communicate using, for example, a bus or conductive leads of a printed circuit board. 
     Backplane interfaces  131  may be implemented as a single or multi-pin interface and may be used by line cards to interface with system fabric  141 . For example, backplane interfaces  131  may be compatible with TFI-5 or CSIX (described in CSIX-Ll: Common Switch Interface Specification-Ll (2000)), although other standards may be used. Switch fabric  141  may transfer IP packets or Ethernet packets (as well as other information) between line cards based on relevant address and header information. Switch fabric  141  can be implemented as a packet switch fabric or a TDM cross connect. Switch fabric  141  can be any device (or devices) that interconnect numerous dataplanes of subsystems (i.e., linecards) together. 
     SONET/SDH defines optical carrier levels and electrically equivalent synchronous transport signals (STSs) for the fiber-optic based hierarchy. In SONET, any type of service, ranging from voice to high speed data and video, can be accepted by various types of service adapters. A service adapter maps the signal into the payload envelope of the STS-1 or virtual tributary. All inputs received are converted to a base format of a synchronous signal, referred to as STS-1, which transmits at 51.84 Mbps (or higher). Several synchronous STS-1s may be multiplexed together to form a higher-level STS-n signal, which are integer multiples of an STS-1 signal. 
     SONET networks transmit data in frames, which include a transport overhead and a synchronous payload envelope (SPE). An SPE includes an STS path overhead section and a payload section, which holds the data being transported over the SONET network. Once the payload is multiplexed into the SPE and transmitted, the payload is not examined at intermediate nodes. 
     SONET/SDH architecture supports virtual concatenation. In virtual concatenation a large payload may be divided into a group of smaller payloads, which may be transmitted contemporaneously across different communication channels. Each SPE within a concatenated group contains an identifier, called a Multi-Frame Identifier, or MFI. The MFI forms part of the SONET/SDH path overhead information in the SPE and indicates the SPE&#39;s sequence and position within the group. 
     Virtual concatenation does not require intermediate node support. To compensate for differential delay, a receiver at the destination temporarily stores frames in a memory so that the payload data can be properly realigned. Applying an address calculation method that allows continuous data storage from members (i. e., time slots) in virtually concatenated groups permits the efficient use of the memory, thereby increasing the differential delay range which may be compensated for a given memory size. In one embodiment, a 1-byte wide on-chip memory is used as an example. The scheme can be extended for wider memory or for external memory modules. On-chip memory or external RAM modules can be used as a memory. 
     Exemplary operations for writing received data frames into a memory are explained with reference to  FIG. 2A  and  FIG. 3 .  FIG. 2A  is a schematic illustration of a memory at a receiver, and  FIG. 3  is a flowchart illustrating operations in one embodiment of a method for writing data frames into a memory such as the buffer illustrated in  FIG. 2A . Referring to  FIG. 3 , at operation  310  data frames are received at a destination node in a communication network. At operation  315  the payload data from the received data frames are stored in a memory. At operation  320  the physical write address at which a received frame is written in memory is recorded in a suitable memory, for example a flip-flop or other memory device. In one embodiment the physical write address corresponds to a physical location in the memory. At operation  325  a virtual write address is recorded in a suitable memory, for example a flip-flop or other memory device. In one embodiment the virtual write address includes the MFI value associated with the received data frame and the byte number for the last received byte. 
     As illustrated in  FIG. 2A , the payload data frames received at the receiver may be written into the memory continuously. The physical write address is incremented continuously as frames are received.  FIG. 2A  illustrates an embodiment in which a 2.5 KB (2560 bytes) memory is used to store STS-3c payloads, which include 2349 bytes per frame. In this example the J1 byte for a given frame i is stored at address  130 , and the J1 byte for frame i+1 and frame i+2 are stored at address  2479  and  2268 , respectively. Writing data to the memory in a continuous fashion makes efficient use of the memory. 
     To compensate for differential delay, data frames from different members having the same MFI and same byte number may be read at the same time. Exemplary operations for reading received data frames into a memory are explained with reference to  FIG. 2B  and  FIG. 4 .  FIG. 2B  is a schematic illustration of a memory at a receiver, and  FIG. 4  is a flowchart illustrating operations in one embodiment of a method for reading data frames from a memory such as the buffer illustrated in  FIG. 2B . 
     Referring to  FIG. 4 , at operation  410  a minimum write address for a group is determined from the virtual write addresses of all members belong to this group. In one embodiment the minimum write address may be determined by comparing the virtual write addresses of all members in the same group, and selecting the minimum write address. The minimum write address may be expressed using a multiframe indicator and a byte number. 
     At operation  415  a virtual read address is determined using the minimum write address. In one embodiment the virtual read address is determined by subtracting a threshold value equal to the write to read delay in memory from the minimum write address. 
     At operation  420  a physical read address is determined using the virtual read address. In one embodiment the physical read address for each member in a group may be determined using the relationship:
 
RAPhy( i )=WAPhy( i )−(WAVir( i )−RAVir)
 
where RAPhy (i) is the physical read address for member i, WAPhy (i) is the physical write address for member i, WAVir (i) is the virtual write address for member i, and RAVir is the virtual read address for the whole group.
 
     Although the virtual read address is the same for the whole group, due to the address conversion, each member may have a different physical read address. From the virtual read address, the actual byte number and MFI value can be identified easily for any follow up processing. 
     The addressing scheme is illustrated schematically in  FIG. 2B . Referring briefly to  FIG. 2B , a group of three members  240 - 244  are shown. The J1 byte for member  240  is at byte  130 , the J1 byte for member  242  is at byte  2103 , and the J1 byte for member 2 is at byte  1027 . 
     The current physical write addresses for each of members  240 ,  242 ,  244  is at byte  2105 , which is indicated by hash marks in  FIG. 2B . While in this example the physical write address for members  240 ,  242 ,  244  is the same, the physical write address may differ for members in the same group, e.g., due to different SONET pointer movements from different members. In this example:
         WAPhy (0)=2105   WAPhy (1)=2105   WAPhy (2)=2105       

     The virtual write addresses for the respective members may be expressed in the format (MFI, byte number), as follows:
         WAVir (0)=(i, 1975)   WAVir (1)=(i, 2)   WAVir (2)=(i, 1078)       

     For member  240 , the byte at the current write address is byte number 1975 in frame i, so it is denoted (i, 1975). Similarly, for member  242 , the byte at current write address is the second byte in frame i, so it is denoted as (i, 2). And for member  244 , the byte at the current write address is byte number 1078 in frame i, so it is denoted as (i, 1078). Among the members  240 ,  242 ,  244 , member  242  has the minimum virtual write address. 
     In the example presented in  FIG. 2B  the threshold between the group read address and the minimum write address of the group is 2. Thus, the current read address is at J1 byte of frame i, that is:
         RAVir=(i, 0)       

     A common virtual read address may be assigned to the whole group. However, the values of physical read address are different for different members. Applying the relationship RAPhy (i)=WAPhy (i) (WAVir (i)−RAVir), the physical read addresses of the respective member may be determined, as follows:
         RAPhy (0)=130   RAPhy (1)=2103   RAPhy (2)=1027       

     The described addressing method can be applied to memory wider than one byte, and also to external memory (e.g., SDRAM).  FIG. 5  is a schematic illustration of an eight-byte wide memory  500  with N words in accordance with an embodiment. Received data frames may be written continuously into the memory. Hence, any byte of the memory may store a J1 byte of a received data frame. The address translation described above for one-byte wide memory can be applied to an eight-byte wide memory. Further, the memory may be treated as a circular memory. Thus, when a write operation reaches the final byte of word N−1, the write operation can continue with the first byte of word zero. 
       FIG. 6  is a schematic illustration of one embodiment of a memory architecture in which M bytes of SDRAM store 64 STS-3c members (e.g., for an OC-192 device). Hence, an M-byte block of SDRAM  610  is divided into four banks identified by bank  0  ( 612 ), bank  1  ( 614 ), bank  2  ( 616 ), and bank  3  ( 618 ). Each of the four banks of SDRAM  610  stores data from sixteen members. In the embodiment depicted in  FIG. 6 , bank  0  ( 612 ) stores data from the set of members ( 0 ,  4 ,  8  . . .  60 ), bank  1  ( 614 ) stores data from the set of members (1, 5, 9 . . . 61), bank  2  ( 616 ) stores data from the set of members (2, 6, 10, . . . 62), and bank  4  ( 618 ) stores data from the set of members (3, 7, 11, . . . 63). Separating members into different banks in the SDRAM  610  improves the access efficiency when reading from and writing to SDRAM  610 . 
     In one embodiment each bank  612 ,  614 ,  616 ,  618  may be divided into chunks of 1024 bytes, illustrated in table  630 . This allocates 64 bytes of memory to each of the sixteen members assigned to the bank, as illustrated in table  640 . In turn, each 64 byte memory allocation is divided into eight words of memory, each of which is 8 bits in width, as illustrated in table  650 . The memory may be treated as a circular memory. Thus, when a write operation reaches the final byte of word M/512-1, the write operation can continue with the first byte of word zero. 
     Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least an implementation. The appearances of the phrase “in one embodiment” in various places in the specification may or may not be all referring to the same embodiment. 
     Thus, although embodiments have been described in language specific to structural features and/or methodological acts, it is to be understood that claimed subject matter may not be limited to the specific features or acts described. Rather, the specific features and acts are disclosed as sample forms of implementing the claimed subject matter.