Patent Publication Number: US-2021192287-A1

Title: Master transform architecture for deep learning

Description:
FIELD 
     At least one embodiment pertains to processing resources used to perform and facilitate artificial intelligence. For example, at least one embodiment pertains to processors or computing systems used to transform input data for training neural networks and inferencing using neural networks, according to various novel techniques described herein. 
     BACKGROUND 
     Training neural networks such that they can be used to perform inferencing often requires massive amounts of data. This data is often available in various formats, or otherwise needs to be modified before it can be used to train a neural network. Pre and post transforms to prepare data for training and inferencing are a key part of training neural networks to perform deep learning inferencing. While applying transforms to input data in order to prepare it to train a neural network is often necessary, it is also expensive both in memory encounter technical limitations (e.g., memory requirements) and formatting-based limits. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  illustrates a system for training and inferencing using a neural network, according to at least one embodiment; 
         FIG. 2  illustrates a system for training and inferencing using a neural network with acceleration by one or more parallel processing units (PPUs), according to at least one embodiment; 
         FIG. 3  illustrates a sequence of example transforms to prepare data for training and inferencing using a neural network, according to at least one embodiment; 
         FIG. 4  illustrates a percentage of time for each example transform to process data for use in training and inferencing using a neural network, according to at least one embodiment; 
         FIG. 5  illustrates a sequence of example transforms to prepare data for training and inferencing using a neural network, where a subset of example transforms are performed by one or more graphics processing units (GPUs) and remaining example transforms are performed by one or more central processing unit (CPUs), according to at least one embodiment; 
         FIG. 6  illustrates a sequence of example transforms to prepare data for training and inferencing using a neural network, where a subset of example transforms have been combined into a master transform performed by one or more GPUs, and remaining example transforms are performed individually by one or more CPUs, according to at least one embodiment; 
         FIG. 7  illustrates a system to determine one or more master transforms each containing two or more data transforms from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment; 
         FIG. 8  illustrates a process to determine one or more master transforms each containing two or more data transforms from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment; 
         FIG. 9A  illustrates inference and/or training logic, according to at least one embodiment; 
         FIG. 9B  illustrates inference and/or training logic, according to at least one embodiment; 
         FIG. 10  illustrates training and deployment of a neural network, according to at least one embodiment; 
         FIG. 11  illustrates an example data center system, according to at least one embodiment; 
         FIG. 12A  illustrates an example of an autonomous vehicle, according to at least one embodiment; 
         FIG. 12B  illustrates an example of camera locations and fields of view for the autonomous vehicle of  FIG. 12A , according to at least one embodiment; 
         FIG. 12C  is a block diagram illustrating an example system architecture for the autonomous vehicle of  FIG. 12A , according to at least one embodiment; 
         FIG. 12D  is a diagram illustrating a system for communication between cloud-based server(s) and the autonomous vehicle of  FIG. 12A , according to at least one embodiment; 
         FIG. 13  is a block diagram illustrating a computer system, according to at least one embodiment; 
         FIG. 14  is a block diagram illustrating computer system, according to at least one embodiment; 
         FIG. 15  illustrates a computer system, according to at least one embodiment; 
         FIG. 16  illustrates a computer system, according at least one embodiment; 
         FIG. 17A  illustrates a computer system, according to at least one embodiment; 
         FIG. 17B  illustrates a computer system, according to at least one embodiment; 
         FIG. 17C  illustrates a computer system, according to at least one embodiment; 
         FIG. 17D  illustrates a computer system, according to at least one embodiment; 
         FIGS. 17E and 17F  illustrate a shared programming model, according to at least one embodiment; 
         FIG. 18  illustrates exemplary integrated circuits and associated graphics processors, according to at least one embodiment; 
         FIGS. 19A and 19B  illustrate exemplary integrated circuits and associated graphics processors, according to at least one embodiment; 
         FIGS. 20A and 20B  illustrate additional exemplary graphics processor logic according to at least one embodiment; 
         FIG. 21  illustrates a computer system, according to at least one embodiment; 
         FIG. 22A  illustrates a parallel processor, according to at least one embodiment; 
         FIG. 22B  illustrates a partition unit, according to at least one embodiment; 
         FIG. 22C  illustrates a processing cluster, according to at least one embodiment; 
         FIG. 22D  illustrates a graphics multiprocessor, according to at least one embodiment; 
         FIG. 23  illustrates a multi-graphics processing unit (GPU) system, according to at least one embodiment; 
         FIG. 24  illustrates a graphics processor, according to at least one embodiment; 
         FIG. 25  is a block diagram illustrating a processor micro-architecture for a processor, according to at least one embodiment; 
         FIG. 26  illustrates a deep learning application processor, according to at least one embodiment; 
         FIG. 27  is a block diagram illustrating an example neuromorphic processor, according to at least one embodiment; 
         FIG. 28  illustrates at least portions of a graphics processor, according to one or more embodiments; 
         FIG. 29  illustrates at least portions of a graphics processor, according to one or more embodiments; 
         FIG. 30  illustrates at least portions of a graphics processor, according to one or more embodiments; 
         FIG. 31  is a block diagram of a graphics processing engine of a graphics processor in accordance with at least one embodiment; 
         FIG. 32  is a block diagram of at least portions of a graphics processor core, according to at least one embodiment; 
         FIGS. 33A and 33B  illustrate thread execution logic including an array of processing elements of a graphics processor core according to at least one embodiment; 
         FIG. 34  illustrates a parallel processing unit (“PPU”), according to at least one embodiment; 
         FIG. 35  illustrates a general processing cluster (“GPC”), according to at least one embodiment; 
         FIG. 36  illustrates a memory partition unit of a parallel processing unit (“PPU”), according to at least one embodiment; and 
         FIG. 37  illustrates a streaming multi-processor, according to at least one embodiment. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  illustrates a system for training and inferencing using one or more neural networks  110 ,  112 , according to at least one embodiment. In at least one embodiment, a training framework  108  is used to train an untrained neural network  110  to perform an operation such as a classification. In at least one embodiment, a training framework  108  is a group of software modules with instructions that, when executed, perform operations in order to train a neural network  110 , including performing computations and backpropagating or updating weight values to nodes in said neural network  110 . In at least one embodiment, an untrained neural network  110  is a feedforward neural network. In at least one embodiment, an untrained neural network  110  is a radial basis function neural network. In at least one embodiment, an untrained neural network  110  is a recurrent neural network. In at least one embodiment, an untrained neural network  110  is a convolutional neural network. In at least one embodiment, an untrained neural network  110  is a modular neural network. In at least one embodiment, an untrained neural network  110  is any other type of neural network suitable for training to perform inference and other deep learning operations. 
     In at least one embodiment, a training framework  108  trains an untrained neural network  110  containing trainable logic to determine logit values. In at least one embodiment, logit values are raw prediction values. In at least one embodiment, logit values may be any numerical, Boolean, or other value. In at least one embodiment, a training framework  108  trains an untrained neural network  110 , such as those described herein, to perform an operation such as classification. In at least one embodiment, a training framework  108  trains an untrained neural network  110  based on training data  102 . In at least one embodiment, training data  102  contains images. In at least one embodiment, training data  102  contains text. In at least one embodiment, training data  102  contains raw data. In at least one embodiment, training data  102  is any other type of data suitable for training an untrained neural network  110  using a training framework  108 . In at least one embodiment, training data  102  is supervised training data. In at least one embodiment, training data  102  is unsupervised training data. In at least one embodiment, training data  102  is a mixture of supervised and unsupervised training data. In at least one embodiment, training data  102  is any other type of supervised or unsupervised data suitable for training an untrained neural network  110 . 
     In at least one embodiment, training data  102  must be prepared and/or transformed  106  for use by a training framework  108  to train an untrained neural network  110 , described herein. In at least one embodiment, training data  102  is unformatted. In at least one embodiment, training data  102  contains variable formats not suitable for training an untrained neural network  110 . In at least one embodiment, data preparation and transformation  106  prepares data for use in training an untrained neural network  110 . In at least one embodiment, data preparation and transformation  106  applies one or more transformations or computations on training data  102  in order to place it in a format suitable for training an untrained neural network  110  by a training framework  108 . In at least one embodiment, one or more transformations or computations applied by data preparation and transformation  106  are unordered. In at least one embodiment, one or more transformations or computations applied by data preparation and transformation  106  must be specifically ordered. In at least one embodiment, one or more transformations or computations applied by data preparation and transformation  106  are reordered to optimize transformation of training data  102 . 
     In at least one embodiment, a training framework  108  trains an untrained neural network  110  using training data  102  that has been prepared and transformed  106  in order to facilitate neural network training. In at least one embodiment, a training framework  108  produces a trained neural network  112 . In at least one embodiment, a trained neural network  112  determines one or more results  114  based on new data  104  through deep learning inferencing or other inferencing. In at least one embodiment, new data  104  is prepared and transformed  106  using techniques described herein in order to perform deep learning inferencing and other inferencing suing a trained neural network  112 . 
       FIG. 2  illustrates a system for training and inferencing using a neural network with acceleration  216  by one or more parallel processing units (PPUs)  218 , according to at least one embodiment. In at least one embodiment, a training framework  208 , as described herein, is used to train an untrained neural network  210  to perform an operation or operations such as classification, as described herein. In at least one embodiment, a training framework  208  trains an untrained neural network  210  using training data  202 , further described herein, to perform operations based on information learned from said training data  202 . 
     In at least one embodiment, before a training framework  208  is able to train an untrained neural network  210 , input training data  202  is prepared and transformed  206  in order to ensure that input training data  202  is in a format usable by a training framework  208  to train an untrained neural network  210 . In at least one embodiment, in order to prepare training data  202  for use by a training framework  208  to train an untrained neural network  210 , one or more transforms are applied  206 . In at least one embodiment, in order to prepare training data  202  for use by a training framework  208  to train an untrained neural network  210 , no transforms may need to be applied  206 . In at least one embodiment, one or more transforms used for data preparation and transformation  206  apply computations and other mathematical operations to training data  202 , further described herein. In at least one embodiment, one or more transforms used for data preparation and transformation  206  apply other non-mathematical operations to training data  202 , further described herein. 
     In at least one embodiment, one or more transforms used for data preparation and transformation  206  are accelerated by one or more PPUs  218 , including graphics processing units (GPUs), as further described herein. In at least one embodiment, one or more PPUs  218 , such as GPUs, implement  216  all transforms, described herein, used to perform data preparation and transformation  206 . In at least one embodiment, one or more PPUs  218 , such as GPUs, implement  216  a portion of transforms, described herein, used to perform data preparation and transformation  206 . In at least one embodiment, one or more PPUs  218 , such as GPUs, implement  216  portions of a training framework  208  to train an untrained neural network  210 , described herein. In at least one embodiment, one or more PPUs  218 , such as GPUs, function in conjunction with one or more central processing units (CPUs) to apply one or more transforms, described herein, in order to prepare and transform  206  training data  202  to be used by a training framework  208  to train an untrained neural network  210 , described herein. 
       FIG. 3  illustrates a sequence of example transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  to prepare input data  302  for training and inferencing using a neural network, according to at least one embodiment. In at least one embodiment, input data  302 , described above, is prepared and transformed  304  in order to create transformed data  306  suitable for training an untrained neural network by a training framework, as described herein. In at least one embodiment, data preparation and transformation  304  is a collection of transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  to prepare input data  302  for use by a training framework to train an untrained neural network. In at least one embodiment, data preparation and transformation  304  is a collection of transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  to prepare input data  302  for use in inferencing using a trained neural network. 
     In at least one embodiment, example transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  demonstrate a sequence of data transforms to be applied on input data  302  in order to generate transformed data  306  suitable for training an untrained neural network. In at least one embodiment, a sequence of data transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  has a specific order. In at least one embodiment, a sequence of data transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  is unordered. 
     In at least one embodiment, example transforms include data transforms for medical imaging. In at least one embodiment, example transforms include data transforms capable of handling 2-, 3-, and 4-dimensional medical data including raw and reconstructed volumes of data. In at least one embodiment, example transforms include general transforms as well as those specific to modalities, such as imaging modalities and associated data types. In at least one embodiment, example transforms include data transforms not specific to an application space. In at least one embodiment, example transforms include transforms that load specific values related to input data  308 . In at least one embodiment, example transforms include transforms that convert 3D values to a 4D array  310 . In at least one embodiment, example transforms include transforms that adjust intensity values  312  on input data  302  such as an image. In at least one embodiment, example transforms include transforms that extract a rectangular subvolume  314  from input data  302  such as an image. In at least one embodiment, example transforms include transforms that randomly flip  316  input data  302 , such as an image, either horizontally or vertically. In at least one embodiment, example transforms include transforms that randomly rotate points on an X, Y plane  318  in input data  302 , such as an image. In at least one embodiment, example transforms include transforms that scale input data  302  intensity oscillations  320 . 
     In at least one embodiment, data input and output dimensions between each data transform in a sequence of data transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  is variable. In at least one embodiment, data input and output dimensions between each data transform in a sequence of data transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  is fixed. In at least one embodiment, each data transform in a sequence of data transforms  308 ,  310 ,  312 ,  314 ,  316 ,  318 ,  320  has variable memory and compute time requirements. 
       FIG. 4  illustrates a percentage of time for each example transform to process data for use in training an untrained neural network and inferencing using a trained neural network, according to at least one embodiment. In at least one embodiment, data transforms such as example transforms  402 ,  404 ,  406 ,  408 ,  410 ,  412 ,  414 , described herein, have variable memory and compute time requirements when executed by a central processing unit (CPU) or parallel processing unit (PPU), such as a graphics processing unit (GPU). In at least one embodiment, some transforms have high memory or compute time requirements  402 ,  408 ,  410 ,  414 . In at least one embodiment, some transforms have low memory or compute time requirements  404 ,  406 ,  412 . 
     In at least one embodiment, data transforms with high memory or compute time requirements  402 ,  408 ,  410 ,  414  are able to be accelerated by implementation on PPUs, such as GPUs. In at least one embodiment, data transforms that are accelerated by implementation on PPUs, such as GPUs, are limited by memory requirements. In at least one embodiment, data transforms are selected for implementation on PPUs, such as GPUs, based on whether their memory requirements exceed available memory on one or more PPUs, including GPUs. In at least one embodiment, one or more data transforms are selected based on their aggregate memory requirements as well as other considerations, described below, for implementation on PPUs, including GPUs, to be performed in conjunction with other transforms performed by one or more CPUs. 
       FIG. 5  illustrates a sequence of example transforms to prepare data for training a neural network and inferencing using a trained neural network, where a subset of example transforms  512 ,  516 ,  522  are performed by a graphics processing units (GPU) and remaining example transforms are performed by a central processing unit (CPU), according to at least one embodiment. In at least one embodiment, input data  502  is prepared and transformed  504  using a sequence of transforms, partially implemented on a CPU and partially implemented on one or more parallel processing units (PPUs), such as a GPU, in order to create transformed data  506  for use by a training framework to train an untrained neural network. In at least one embodiment, one or more transforms  512 ,  516 ,  522  are implemented for acceleration by one or more PPUs such as one or more GPUs. 
     In at least one embodiment, transforms implemented on one or more PPUs, such as one or more GPUs, are selected based on compute time and memory requirements. In at least one embodiment, transforms must have memory requirements that can be satisfied by available memory of one or more PPUs, including one or more GPUs. In at least one embodiment, additional considerations, as described below, determine whether transforms are implemented on one or more PPUs, such as one or more GPUs. 
     In at least one embodiment, some data transforms must be performed in sequence, where output from one input matches dimensions of input to a next transform in a sequence of transforms. In at least one embodiment, an example transform that converts 3D data points to a 4D array  508  contains a data output with dimensions supported by a subsequent transform  512 . In at least one embodiment, because a subsequent transform  512  is implemented for acceleration by one or more PPUs, including GPUs, data is copied from memory associated with one or more CPUs implementing a previous transform  508  to memory associated with one or more PPUs, including GPUs, implementing said subsequent transform  512 . In at least one embodiment, once an accelerated data transform  512  completes operation, data is copied back to memory associated with one or more CPUs  510 . 
     In at least one embodiment, if a subsequent transform  516  after data has been copied to memory associated with one or more CPUs is accelerated or performed by one or more PPUs, such as GPUs, an additional copy must be performed of results  510  from a previous data transform  512  to memory associated with one or more PPUs, such as GPUs, in order to perform a subsequent accelerated transform  516 . In at least one embodiment, results from a subsequent accelerated transform  516  are then copied back  514  to memory associated with one or more CPUs in order to be used by additional data transforms in a sequence of data transforms. 
     In at least one embodiment, additional individual data transforms  522  may be accelerated by one or more PPUs, such as GPUs, after a sequence of data transforms have been performed by one or more CPUs. In at least one embodiment, at any point in a sequence of data transforms that a subsequent individual transform  522  is performed or accelerated by one or more PPUs, such as one or more GPUs, data must be copied from memory storing results of a previous sequence of transforms  518  into memory associated with one or more PPUs, such as one or more GPUs, for use by additional individual accelerated transforms  522 . In at least one embodiment, after additional individual accelerated transforms  522  have completed processing, results are then copied  520  from memory associated with one or more PPUs, including GPUs, to memory associated with one or more CPUs. In at least one embodiment, once a sequence of ordered or unordered transforms have completed, transformed data  506  is ready for use by a training framework to train an untrained neural network. 
       FIG. 6  illustrates a sequence of example transforms to prepare data for training a neural network and inferencing using a trained neural network, where a subset of example transforms have been combined into a master transform  610  performed by one or more parallel processing units (PPUs), such as one or more graphics processing units (GPUs), and remaining example transforms are performed individually by one or more central processing units (CPUs), according to at least one embodiment. In at least one embodiment, input data  602  is prepared and transformed  604  using a sequence of data transforms, partially implemented on one or more CPUs and partially implemented on one or more PPUs, such as one or more GPUs, in order to create transformed data  606  for use by a training framework to train an untrained neural network. In at least one embodiment, one or more transforms are combined into a master transform  610  containing transforms that, when combined, meet certain requirements, described herein, in order to be processed serially by one or more PPUs, including GPUs, without transfer of execution back to one or more CPUs and without copying of intermediate data from memory associated with one or more PPUs, such as GPUs, to memory associated with one or more CPUs. In at least one embodiment, transforms  616  that are implemented for acceleration or processing by one or more PPUs, including one or more GPUs, but are not included in a master transform  610 , are processed individually by one or more PPUs, such as one or more GPUs. 
     In at least one embodiment, multiple transforms in a sequence of transforms that meet memory and data requirements are aggregated into a master transform  610  to be accelerated or processed by one or more PPUs, such as one or more GPUs. In at least one embodiment, transforms to be aggregated into a master transform  610  must have, as aggregated, memory requirements that fit within constraints imposed by one or more PPUs such as GPUs. In at least one embodiment, a master transform  610  of aggregated transforms must not require more memory than available on one or more PPUs such as GPUs. 
     In at least one embodiment, transforms to be aggregated into a master transform  610  must have data inputs and outputs that are compatible. In at least one embodiment, data inputs and outputs are compatible if they have dimensions and types that allow for one transform to be performed after another transform without further modifying data dimensions or data type. In at least one embodiment, for example, a data transform that outputs an N×N matrix cannot provide its output into a subsequent data transform that requires a K×K input without additional data processing, such as padding or trimming. In at least one embodiment, only a data transform that outputs a K×K output would match with a subsequent data transform that requires a K×K data input. 
     In at least one embodiment, a master transform  610  contains two or more data transforms from a sequence of data transforms that contain compatible data inputs and outputs. In at least one embodiment, a master transform  610  contains two or more data transforms that, in the aggregate, have memory requirements that can be satisfied by one or more PPUs, such as GPUs. In at least one embodiment, data output from an individual data transform in a sequence of data transforms being performed on one or more CPUs will be transferred  608  from memory associated with one or more CPUs to memory associated with one or more PPUs, such as one or more GPUs, and said data output will be used as input to a master transform  610 . In at least one embodiment, a master transform  610  will perform two or more aggregated data transform operations using one or more PPUs, such as one or more GPUs. In at least one embodiment, data output from a master transform  610  is transferred  612  from memory associated with one or more PPUs, such as one or more GPUs, to memory associated with one or more CPUs. In at least one embodiment, data output  612  from a master transform  610  is then used by remaining data transforms in a sequence of data transforms. 
     In at least one embodiment, additional individual data transforms  616  not included in a master transform  610  may also be accelerated by one or more PPUs, such as one or more GPUs. In at least one embodiment, at any point in a sequence of data transforms that a subsequent individual transform  616  not included in a master transform  610  is performed or accelerated by one or more PPUs, such as one or more GPUs, data must be copied or transferred  614  from memory storing results of a previous sequence of transforms into memory associated with one or more PPUs, such as one or more GPUs, for use by additional individual accelerated transforms  616 . In at least one embodiment, after additional individual accelerated transforms  616  have completed processing, results are then copied  618  from memory associated with one or more PPUs, such as one or more GPUs, to memory associated with one or more CPUs. In at least one embodiment, once a sequence of ordered or unordered transforms have completed, including one or more master transforms  610 , transformed data  606  is ready for use by a training framework to train an untrained neural network. 
       FIG. 7  illustrates a system to determine one or more master transforms each containing two or more data transforms from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. In at least one embodiment, a system configuration  702  is known indicating computing and memory resources on a system implementing one or more master transforms, as described above. In at least one embodiment, a system configuration  702  and input data  704 , described above, is used by a component, such as a system profiler  708 , in order to determine compute and resource availability for a system implementing one or more master transforms to prepare data for training one or more untrained neural networks. 
     In at least one embodiment, input data  704 , as described above and further herein, is used by an input transform designer  710 . In at least one embodiment, an input transform designer  710  is a group of software modules containing instructions that, when executed, perform operations to determine information about data transforms. In at least one embodiment, an input transform designer  710  determines total computational and memory requirements to transform input data  704  for use in training an untrained neural network, described herein. In at least one embodiment, an input transform designer  710  determines a predefined sequence of data transforms for transforming input data  704  to be used to train an untrained neural network. 
     In at least one embodiment, a transform controller  712  controls determination of one or more master transforms given profiles of available computing and memory resources as well as transforms to be applied  706 , such as those determined by a system profiler  708  and an input transform designer  710 . In at least one embodiment, a transform controller  712  contains a transform profiler  714  or other component or method to determine compute requirements by each transform implementation or kernel for specific input data  704 . In at least one embodiment, a transform controller  712  utilizes a transform profiler  714  or other component or method to determine internal PPU (or GPU) memory needs when a transform is being processed. In at least one embodiment, a transform controller  712  utilizes a transform profiler  714  or other component or method to determine input and output data dimensions for each transform in a sequence of transforms to be applied, such as those determined by an input transform designer  710 . 
     In at least one embodiment, a resource monitoring engine  716  monitors available memory used during transform profiling  714  on specific input data  704 . In at least one embodiment, a resource monitoring engine  716  imposes restrictions on transform resource usage in order to determine compute and memory performance impact of restrictions for transform profiling  714 . In at least one embodiment, a resource monitoring engine  716  provides other resource usage information utilized by a transform controller to determine resource consumption profiles for individuals and sequences of data transforms when applied to specific input data  704 . 
     In at least one embodiment, a master transform framework  718  utilizes information from a system profiler  708 , an input transform designer  710 , and a transform controller  712  to determine an optimized transform configuration, or optimized sequence of transforms given a set of transforms, system resource availability, and input data. In at least one embodiment, a master transform designer  720  combines two or more transforms in a sequence of transforms determined by a master transform framework  718  into one or more master transforms. In at least one embodiment, if multiple groups of two or more transforms in a sequence of transforms determined by a master transform framework  718  are combined independently, two or more master transforms are created. In at least one embodiment, a user explicitly allocates additional memory on one or more parallel processing units and specifies two or more data transforms that have mismatched input and output dimensions. In at least one embodiment, considerations to combine two or more data transforms with mismatching input and output dimensions allows for optimized utilization of PPU resources and effective use of PPU memory registers when transforms are unable to be matched based on input and output dimensions. 
     In at least one embodiment, a master transform designer  720  creates updated implementations or kernels for one or more master transforms each containing two or more data transforms to be processed or executed by one or more PPUs, such as one or more GPUs. In at least one embodiment, a master transform designer  720  provides implementation of an efficient memory allocation mechanism for using single GPUs to perform several transforms operating in parallel through multi-threaded CPU calls. In at least one embodiment, a master transform designer  720  merges two or more transforms into a single master transform. In at least one embodiment, a master transform designer  720  merges one or more groups of two or more transforms into multiple master transforms based on input and output data compatibility in a sequence of transforms, as well as memory and compute time requirements, as described above. In at least one embodiment, a master transform designer  720  outputs an updated pre and post transform sequence  722  containing one or more master transforms for use in training an untrained neural network, as described herein. 
       FIG. 8  illustrates a process to determine one or more master transforms each containing two or more data transforms from a sequence of transforms to be performed on one or more parallel processing units (PPUs), such as graphics processing units (GPUs), according to at least one embodiment. In at least one embodiment, a process for determining a pre and post transform sequence containing one or more master transforms begins  802  by determining a system configuration  804 , including available processing and memory resources on a system implementing data transformation in order to train an untrained neural network, as described above. In at least one embodiment, available data transforms are configured  806 , as described above, in order to determine a sequence of data transforms to apply to input data in order to prepare it for training an untrained neural network. 
     In at least one embodiment, a transform controller, described above, profiles  808  transforms in a set of data transforms on input data to determine compute time and memory resource requirements for each transform, as well as transform data input and output dimensions, as described above. In at least one embodiment, transforms in a transform sequence are optimized  810  according to techniques and information described above. Once a sequence of transforms has been optimized, in at least one embodiment, one or more master transforms are designed  812  from an optimized sequence of transforms, and optimized software implementations or kernels are generated, as described above. In at least one embodiment, after one or more master transforms, each containing two or more data transforms, have been generated by a master transform designer  812 , an optimized pre and post transform sequence containing one or more master transforms is output  814 , and a process for generating an optimized transform sequence containing one or more master transforms is complete  816 . 
     Inference and Training Logic 
       FIG. 9A  illustrates inference and/or training logic  915  used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided below in conjunction with  FIGS. 9A and/or 9B . 
     In at least one embodiment, inference and/or training logic  915  may include, without limitation, code and/or data storage  901  to store forward and/or output weight and/or input/output data, and/or other parameters to configure neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic  915  may include, or be coupled to code and/or data storage  901  to store graph code or other software to control timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic, including integer and/or floating point units (collectively, arithmetic logic units (ALUs). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which the code corresponds. In at least one embodiment code and/or data storage  901  stores weight parameters and/or input/output data of each layer of a neural network trained or used in conjunction with one or more embodiments during forward propagation of input/output data and/or weight parameters during training and/or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and/or data storage  901  may be included with other on-chip or off-chip data storage, including a processor&#39;s L1, L2, or L3 cache or system memory. 
     In at least one embodiment, any portion of code and/or data storage  901  may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or code and/or data storage  901  may be cache memory, dynamic randomly addressable memory (“DRAM”), static randomly addressable memory (“SRAM”), non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, choice of whether code and/or code and/or data storage  901  is internal or external to a processor, for example, or comprised of DRAM, SRAM, Flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and/or inferencing functions being performed, batch size of data used in inferencing and/or training of a neural network, or some combination of these factors. 
     In at least one embodiment, inference and/or training logic  915  may include, without limitation, a code and/or data storage  905  to store backward and/or output weight and/or input/output data corresponding to neurons or layers of a neural network trained and/or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and/or data storage  905  stores weight parameters and/or input/output data of each layer of a neural network trained or used in conjunction with one or more embodiments during backward propagation of input/output data and/or weight parameters during training and/or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic  915  may include, or be coupled to code and/or data storage  905  to store graph code or other software to control timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic, including integer and/or floating point units (collectively, arithmetic logic units (ALUs). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on an architecture of a neural network to which the code corresponds. In at least one embodiment, any portion of code and/or data storage  905  may be included with other on-chip or off-chip data storage, including a processor&#39;s L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and/or data storage  905  may be internal or external to on one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and/or data storage  905  may be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, choice of whether code and/or data storage  905  is internal or external to a processor, for example, or comprised of DRAM, SRAM, Flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and/or inferencing functions being performed, batch size of data used in inferencing and/or training of a neural network, or some combination of these factors. 
     In at least one embodiment, code and/or data storage  901  and code and/or data storage  905  may be separate storage structures. In at least one embodiment, code and/or data storage  901  and code and/or data storage  905  may be same storage structure. In at least one embodiment, code and/or data storage  901  and code and/or data storage  905  may be partially same storage structure and partially separate storage structures. In at least one embodiment, any portion of code and/or data storage  901  and code and/or data storage  905  may be included with other on-chip or off-chip data storage, including a processor&#39;s L1, L2, or L3 cache or system memory. 
     In at least one embodiment, inference and/or training logic  915  may include, without limitation, one or more arithmetic logic unit(s) (“ALU(s)”)  910 , including integer and/or floating point units, to perform logical and/or mathematical operations based, at least in part on, or indicated by, training and/or inference code (e.g., graph code), a result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in an activation storage  920  that are functions of input/output and/or weight parameter data stored in code and/or data storage  901  and/or code and/or data storage  905 . In at least one embodiment, activations stored in activation storage  920  are generated according to linear algebraic and or matrix-based mathematics performed by ALU(s)  910  in response to performing instructions or other code, wherein weight values stored in code and/or data storage  905  and/or data  901  are used as operands along with other values, such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and/or data storage  905  or code and/or data storage  901  or another storage on or off-chip. 
     In at least one embodiment, ALU(s)  910  are included within one or more processors or other hardware logic devices or circuits, whereas in another embodiment, ALU(s)  910  may be external to a processor or other hardware logic device or circuit that uses them (e.g., a co-processor). In at least one embodiment, ALUs  910  may be included within a processor&#39;s execution units or otherwise within a bank of ALUs accessible by a processor&#39;s execution units either within same processor or distributed between different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, data storage  901 , code and/or data storage  905 , and activation storage  920  may be on same processor or other hardware logic device or circuit, whereas in another embodiment, they may be in different processors or other hardware logic devices or circuits, or some combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation storage  920  may be included with other on-chip or off-chip data storage, including a processor&#39;s L1, L2, or L3 cache or system memory. Furthermore, inferencing and/or training code may be stored with other code accessible to a processor or other hardware logic or circuit and fetched and/or processed using a processor&#39;s fetch, decode, scheduling, execution, retirement and/or other logical circuits. 
     In at least one embodiment, activation storage  920  may be cache memory, DRAM, SRAM, non-volatile memory (e.g., Flash memory), or other storage. In at least one embodiment, activation storage  920  may be completely or partially within or external to one or more processors or other logical circuits. In at least one embodiment, choice of whether activation storage  920  is internal or external to a processor, for example, or comprised of DRAM, SRAM, Flash or some other storage type may depend on available storage on-chip versus off-chip, latency requirements of training and/or inferencing functions being performed, batch size of data used in inferencing and/or training of a neural network, or some combination of these factors. In at least one embodiment, inference and/or training logic  915  illustrated in  FIG. 9A  may be used in conjunction with an application-specific integrated circuit (“ASIC”), such as Tensorflow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and/or training logic  915  illustrated in  FIG. 9A  may be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware or other hardware, such as field programmable gate arrays (“FPGAs”). 
       FIG. 9B  illustrates inference and/or training logic  915 , according to at least one embodiment various. In at least one embodiment, inference and/or training logic  915  may include, without limitation, hardware logic in which computational resources are dedicated or otherwise exclusively used in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and/or training logic  915  illustrated in  FIG. 9B  may be used in conjunction with an application-specific integrated circuit (ASIC), such as Tensorflow® Processing Unit from Google, an inference processing unit (IPU) from Graphcore™, or a Nervana® (e.g., “Lake Crest”) processor from Intel Corp. In at least one embodiment, inference and/or training logic  915  illustrated in  FIG. 9B  may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and/or training logic  915  includes, without limitation, code and/or data storage  901  and code and/or data storage  905 , which may be used to store code (e.g., graph code), weight values and/or other information, including bias values, gradient information, momentum values, and/or other parameter or hyperparameter information. In at least one embodiment illustrated in  FIG. 9B , each of code and/or data storage  901  and code and/or data storage  905  is associated with a dedicated computational resource, such as computational hardware  902  and computational hardware  906 , respectively. In at least one embodiment, each of computational hardware  902  and computational hardware  906  comprises one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and/or data storage  901  and code and/or data storage  905 , respectively, result of which is stored in activation storage  920 . 
     In at least one embodiment, each of code and/or data storage  901  and  905  and corresponding computational hardware  902  and  906 , respectively, correspond to different layers of a neural network, such that resulting activation from one “storage/computational pair  901 / 902 ” of code and/or data storage  901  and computational hardware  902  is provided as an input to next “storage/computational pair  905 / 906 ” of code and/or data storage  905  and computational hardware  906 , in order to mirror conceptual organization of a neural network. In at least one embodiment, each of storage/computational pairs  901 / 902  and  905 / 906  may correspond to more than one neural network layer. In at least one embodiment, additional storage/computation pairs (not shown) subsequent to or in parallel with storage computation pairs  901 / 902  and  905 / 906  may be included in inference and/or training logic  915 . 
     Neural Network Training and Deployment 
       FIG. 10  illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, untrained neural network  91006  is trained using a training dataset  1002 . In at least one embodiment, training framework  1004  is a PyTorch framework, whereas in other embodiments, training framework  1004  is a Tensorflow, Boost, Caffe, Microsoft Cognitive Toolkit/CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment training framework  1004  trains an untrained neural network  1006  and enables it to be trained using processing resources described herein to generate a trained neural network  1008 . In at least one embodiment, weights may be chosen randomly or by pre-training using a deep belief network. In at least one embodiment, training may be performed in either a supervised, partially supervised, or unsupervised manner. 
     In at least one embodiment, untrained neural network  1006  is trained using supervised learning, wherein training dataset  1002  includes an input paired with a desired output for an input, or where training dataset  1002  includes input having a known output and an output of neural network  1006  is manually graded. In at least one embodiment, untrained neural network  1006  is trained in a supervised manner processes inputs from training dataset  1002  and compares resulting outputs against a set of expected or desired outputs. In at least one embodiment, errors are then propagated back through untrained neural network  1006 . In at least one embodiment, training framework  1004  adjusts weights that control untrained neural network  1006 . In at least one embodiment, training framework  1004  includes tools to monitor how well untrained neural network  1006  is converging towards a model, such as trained neural network  1008 , suitable to generating correct answers, such as in result  1014 , based on known input data, such as new data  1012 . In at least one embodiment, training framework  1004  trains untrained neural network  1006  repeatedly while adjust weights to refine an output of untrained neural network  1006  using a loss function and adjustment algorithm, such as stochastic gradient descent. In at least one embodiment, training framework  1004  trains untrained neural network  1006  until untrained neural network  1006  achieves a desired accuracy. In at least one embodiment, trained neural network  1008  can then be deployed to implement any number of machine learning operations. 
     In at least one embodiment, untrained neural network  1006  is trained using unsupervised learning, wherein untrained neural network  1006  attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset  1002  will include input data without any associated output data or “ground truth” data. In at least one embodiment, untrained neural network  1006  can learn groupings within training dataset  1002  and can determine how individual inputs are related to untrained dataset  1002 . In at least one embodiment, unsupervised training can be used to generate a self-organizing map, which is a type of trained neural network  1008  capable of performing operations useful in reducing dimensionality of new data  1012 . In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in a new dataset  1012  that deviate from normal patterns of new dataset  1012 . 
     In at least one embodiment, semi-supervised learning may be used, which is a technique in which in training dataset  1002  includes a mix of labeled and unlabeled data. In at least one embodiment, training framework  1004  may be used to perform incremental learning, such as through transferred learning techniques. In at least one embodiment, incremental learning enables trained neural network  1008  to adapt to new data  1012  without forgetting knowledge instilled within network during initial training. 
     Data Center 
       FIG. 11  illustrates an example data center  1100 , in which at least one embodiment may be used. In at least one embodiment, data center  1100  includes a data center infrastructure layer  1110 , a framework layer  1120 , a software layer  1130  and an application layer  1140 . 
     In at least one embodiment, as shown in  FIG. 11 , data center infrastructure layer  1110  may include a resource orchestrator  1112 , grouped computing resources  1114 , and node computing resources (“node C.R.s”)  1116 ( 1 )- 1116 (N), where “N” represents any whole, positive integer. In at least one embodiment, node C.R.s  1116 ( 1 )- 1116 (N) may include, but are not limited to, any number of central processing units (“CPUs”) or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), storage devices (e.g., solid state or disk drives), network input/output (“NW I/O”) devices, network switches, virtual machines (“VMs”), power modules, and cooling modules, etc. In at least one embodiment, one or more node C.R.s from among node C.R.s  1116 ( 1 )- 1116 (N) may be a server having one or more of above-mentioned computing resources. 
     In at least one embodiment, grouped computing resources  1114  may include separate groupings of node C.R.s housed within one or more racks (not shown), or many racks housed in data centers at various geographical locations (also not shown). Separate groupings of node C.R.s within grouped computing resources  1114  may include grouped compute, network, memory or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R.s including CPUs or processors may grouped within one or more racks to provide compute resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches, in any combination. 
     In at least one embodiment, resource orchestrator  1112  may configure or otherwise control one or more node C.R.s  1116 ( 1 )- 1116 (N) and/or grouped computing resources  1114 . In at least one embodiment, resource orchestrator  1112  may include a software design infrastructure (“SDI”) management entity for data center  1100 . In at least one embodiment, resource orchestrator may include hardware, software or some combination thereof. 
     In at least one embodiment, as shown in  FIG. 11 , framework layer  1120  includes a job scheduler  1132 , a configuration manager  1134 , a resource manager  1136  and a distributed file system  1138 . In at least one embodiment, framework layer  1120  may include a framework to support software  1132  of software layer  1130  and/or one or more application(s)  1142  of application layer  1140 . In at least one embodiment, software  1132  or application(s)  1142  may respectively include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud and Microsoft Azure. In at least one embodiment, framework layer  1120  may be, but is not limited to, a type of free and open-source software web application framework such as Apache Spark® (hereinafter “Spark”) that may utilize distributed file system  1138  for large-scale data processing (e.g., “big data”). In at least one embodiment, job scheduler  1132  may include a Spark driver to facilitate scheduling of workloads supported by various layers of data center  1100 . In at least one embodiment, configuration manager  1134  may be capable of configuring different layers such as software layer  1130  and framework layer  1120  including Spark and distributed file system  1138  for supporting large-scale data processing. In at least one embodiment, resource manager  1136  may be capable of managing clustered or grouped computing resources mapped to or allocated for support of distributed file system  1138  and job scheduler  1132 . In at least one embodiment, clustered or grouped computing resources may include grouped computing resource  1114  at data center infrastructure layer  1110 . In at least one embodiment, resource manager  1136  may coordinate with resource orchestrator  1112  to manage these mapped or allocated computing resources. 
     In at least one embodiment, software  1132  included in software layer  1130  may include software used by at least portions of node C.R.s  1116 ( 1 )- 1116 (N), grouped computing resources  1114 , and/or distributed file system  1138  of framework layer  1120 . One or more types of software may include, but are not limited to, Internet web page search software, e-mail virus scan software, database software, and streaming video content software. 
     In at least one embodiment, application(s)  1142  included in application layer  1140  may include one or more types of applications used by at least portions of node C.R.s  1116 ( 1 )- 1116 (N), grouped computing resources  1114 , and/or distributed file system  1138  of framework layer  1120 . One or more types of applications may include, but are not limited to, any number of a genomics application, a cognitive compute, and a machine learning application, including training or inferencing software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.) or other machine learning applications used in conjunction with one or more embodiments. 
     In at least one embodiment, any of configuration manager  1134 , resource manager  1136 , and resource orchestrator  1112  may implement any number and type of self-modifying actions based on any amount and type of data acquired in any technically feasible fashion. In at least one embodiment, self-modifying actions may relieve a data center operator of data center  1100  from making possibly bad configuration decisions and possibly avoiding underutilized and/or poor performing portions of a data center. 
     In at least one embodiment, data center  1100  may include tools, services, software or other resources to train one or more machine learning models or predict or infer information using one or more machine learning models according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using software and computing resources described above with respect to data center  1100 . In at least one embodiment, trained machine learning models corresponding to one or more neural networks may be used to infer or predict information using resources described above with respect to data center  1100  by using weight parameters calculated through one or more training techniques described herein. 
     In at least one embodiment, data center may use CPUs, application-specific integrated circuits (ASICs), GPUs, FPGAs, or other hardware to perform training and/or inferencing using above-described resources. Moreover, one or more software and/or hardware resources described above may be configured as a service to allow users to train or performing inferencing of information, such as image recognition, speech recognition, or other artificial intelligence services. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 11  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 11  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     Autonomous Vehicle 
       FIG. 12A  illustrates an example of an autonomous vehicle  1200 , according to at least one embodiment. In at least one embodiment, autonomous vehicle  1200  (alternatively referred to herein as “vehicle  1200 ”) may be, without limitation, a passenger vehicle, such as a car, a truck, a bus, and/or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle  1200  may be a semi-tractor-trailer truck used for hauling cargo. In at least one embodiment, vehicle  1200  may be an airplane, robotic vehicle, or other kind of vehicle. 
     Autonomous vehicles may be described in terms of automation levels, defined by National Highway Traffic Safety Administration (“NHTSA”), a division of US Department of Transportation, and Society of Automotive Engineers (“SAE”) “Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles” (e.g., Standard No. J3016-201806, published on Jun. 15, 2018, Standard No. J3016-201609, published on Sep. 30, 2016, and previous and future versions of this standard). In one or more embodiments, vehicle  1200  may be capable of functionality in accordance with one or more of level 1-level 5 of autonomous driving levels. For example, in at least one embodiment, vehicle  1200  may be capable of conditional automation (Level 3), high automation (Level 4), and/or full automation (Level 5), depending on embodiment. 
     In at least one embodiment, vehicle  1200  may include, without limitation, components such as a chassis, a vehicle body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of a vehicle. In at least one embodiment, vehicle  1200  may include, without limitation, a propulsion system  1250 , such as an internal combustion engine, hybrid electric power plant, an all-electric engine, and/or another propulsion system type. In at least one embodiment, propulsion system  1250  may be connected to a drive train of vehicle  1200 , which may include, without limitation, a transmission, to enable propulsion of vehicle  1200 . In at least one embodiment, propulsion system  1250  may be controlled in response to receiving signals from a throttle/accelerator(s)  1252 . 
     In at least one embodiment, a steering system  1254 , which may include, without limitation, a steering wheel, is used to steer a vehicle  1200  (e.g., along a desired path or route) when a propulsion system  1250  is operating (e.g., when vehicle is in motion). In at least one embodiment, a steering system  1254  may receive signals from steering actuator(s)  1256 . Steering wheel may be optional for full automation (Level 5) functionality. In at least one embodiment, a brake sensor system  1246  may be used to operate vehicle brakes in response to receiving signals from brake actuator(s)  1248  and/or brake sensors. 
     In at least one embodiment, controller(s)  1236 , which may include, without limitation, one or more system on chips (“SoCs”) (not shown in  FIG. 12A ) and/or graphics processing unit(s) (“GPU(s)”), provide signals (e.g., representative of commands) to one or more components and/or systems of vehicle  1200 . For instance, in at least one embodiment, controller(s)  1236  may send signals to operate vehicle brakes via brake actuators  1248 , to operate steering system  1254  via steering actuator(s)  1256 , to operate propulsion system  1250  via throttle/accelerator(s)  1252 . Controller  1236  may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals, and output operation commands (e.g., signals representing commands) to enable autonomous driving and/or to assist a human driver in driving vehicle  1200 . In at least one embodiment, controller(s)  1236  may include a first controller  1236  for autonomous driving functions, a second controller  1236  for functional safety functions, a third controller  1236  for artificial intelligence functionality (e.g., computer vision), a fourth controller  1236  for infotainment functionality, a fifth controller  1236  for redundancy in emergency conditions, and/or other controllers. In at least one embodiment, a single controller  1236  may handle two or more of above functionalities, two or more controllers  1236  may handle a single functionality, and/or any combination thereof. 
     In at least one embodiment, controller(s)  1236  provide signals for controlling one or more components and/or systems of vehicle  1200  in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example and without limitation, global navigation satellite systems (“GNSS”) sensor(s)  1258  (e.g., Global Positioning System sensor(s)), RADAR sensor(s)  1260 , ultrasonic sensor(s)  1262 , LIDAR sensor(s)  1264 , inertial measurement unit (“IMU”) sensor(s)  1266  (e.g., accelerometer(s), gyroscope(s), magnetic compass(es), magnetometer(s), etc.), microphone(s)  1296 , stereo camera(s)  1268 , wide-view camera(s)  1270  (e.g., fisheye cameras), infrared camera(s)  1272 , surround camera(s)  1274  (e.g., 360 degree cameras), long-range cameras (not shown in  FIG. 12A ), mid-range camera(s) (not shown in  FIG. 12A ), speed sensor(s)  1244  (e.g., for measuring speed of vehicle  1200 ), vibration sensor(s)  1242 , steering sensor(s)  1240 , brake sensor(s) (e.g., as part of brake sensor system  1246 ), and/or other sensor types. 
     In at least one embodiment, one or more of controller(s)  1236  may receive inputs (e.g., represented by input data) from an instrument cluster  1232  of vehicle  1200  and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display  1234 , an audible annunciator, a loudspeaker, and/or via other components of vehicle  1200 . In at least one embodiment, outputs may include information such as vehicle velocity, speed, time, map data (e.g., a High Definition map (not shown in  FIG. 12A ), location data (e.g., vehicle&#39;s  1200  location, such as on a map), direction, location of other vehicles (e.g., an occupancy grid), information about objects and status of objects as perceived by controller(s)  1236 , etc. For example, in at least one embodiment, HMI display  1234  may display information about presence of one or more objects (e.g., a street sign, caution sign, traffic light changing, etc.), and/or information about driving maneuvers vehicle has made, is making, or will make (e.g., changing lanes now, taking exit  34 B in two miles, etc.). 
     In at least one embodiment, vehicle  1200  further includes a network interface  1224  which may use wireless antenna(s)  1226  and/or modem(s) to communicate over one or more networks. For example, in at least one embodiment, network interface  1224  may be capable of communication over Long-Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile communication (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”), etc. In at least one embodiment, wireless antenna(s)  1226  may also enable communication between objects in environment (e.g., vehicles, mobile devices, etc.), using local area network(s), such as Bluetooth, Bluetooth Low Energy (“LE”), Z-Wave, ZigBee, etc., and/or low power wide-area network(s) (“LPWANs”), such as LoRaWAN, SigFox, etc. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 12A  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 12A  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 12B  illustrates an example of camera locations and fields of view for autonomous vehicle  1200  of  FIG. 12A , according to at least one embodiment. In at least one embodiment, cameras and respective fields of view are one example embodiment and are not intended to be limiting. For instance, in at least one embodiment, additional and/or alternative cameras may be included and/or cameras may be located at different locations on vehicle  1200 . 
     In at least one embodiment, camera types for cameras may include, but are not limited to, digital cameras that may be adapted for use with components and/or systems of vehicle  1200 . Camera may operate at automotive safety integrity level (“ASIL”) B and/or at another ASIL. In at least one embodiment, camera types may be capable of any image capture rate, such as 60 frames per second (fps), 1220 fps, 240 fps, etc., depending on embodiment. In at least one embodiment, cameras may be capable of using rolling shutters, global shutters, another type of shutter, or a combination thereof. In at least one embodiment, color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer sensors (“RGGB”) color filter array, a monochrome sensor color filter array, and/or another type of color filter array. In at least one embodiment, clear pixel cameras, such as cameras with an RCCC, an RCCB, and/or an RBGC color filter array, may be used in an effort to increase light sensitivity. 
     In at least one embodiment, one or more of camera(s) may be used to perform advanced driver assistance systems (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a Multi-Function Mono Camera may be installed to provide functions including lane departure warning, traffic sign assist and intelligent headlamp control. In at least one embodiment, one or more of camera(s) (e.g., all of cameras) may record and provide image data (e.g., video) simultaneously. 
     In at least one embodiment, one or more of cameras may be mounted in a mounting assembly, such as a custom designed (three-dimensional (“3D”) printed) assembly, in order to cut out stray light and reflections from within car (e.g., reflections from dashboard reflected in windshield mirrors) which may interfere with camera&#39;s image data capture abilities. With reference to wing-mirror mounting assemblies, in at least one embodiment, wing-mirror assemblies may be custom 3D printed so that camera mounting plate matches shape of wing-mirror. In at least one embodiment, camera(s) may be integrated into wing-mirror. For side-view cameras, camera(s) may also be integrated within four pillars at each corner of cabIn at least one embodiment. 
     In at least one embodiment, cameras with a field of view that include portions of environment in front of vehicle  1200  (e.g., front-facing cameras) may be used for surround view, to help identify forward facing paths and obstacles, as well as aid in, with help of one or more of controllers  1236  and/or control SoCs, providing information critical to generating an occupancy grid and/or determining preferred vehicle paths. In at least one embodiment, front-facing cameras may be used to perform many of same ADAS functions as LIDAR, including, without limitation, emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, front-facing cameras may also be used for ADAS functions and systems including, without limitation, Lane Departure Warnings (“LDW”), Autonomous Cruise Control (“ACC”), and/or other functions such as traffic sign recognition. 
     In at least one embodiment, a variety of cameras may be used in a front-facing configuration, including, for example, a monocular camera platform that includes a CMOS (“complementary metal oxide semiconductor”) color imager. In at least one embodiment, wide-view camera  1270  may be used to perceive objects coming into view from periphery (e.g., pedestrians, crossing traffic or bicycles). Although only one wide-view camera  1270  is illustrated in  FIG. 12B , in other embodiments, there may be any number (including zero) of wide-view camera(s)  1270  on vehicle  1200 . In at least one embodiment, any number of long-range camera(s)  1298  (e.g., a long-view stereo camera pair) may be used for depth-based object detection, especially for objects for which a neural network has not yet been trained. In at least one embodiment, long-range camera(s)  1298  may also be used for object detection and classification, as well as basic object tracking. 
     In at least one embodiment, any number of stereo camera(s)  1268  may also be included in a front-facing configuration. In at least one embodiment, one or more of stereo camera(s)  1268  may include an integrated control unit comprising a scalable processing unit, which may provide a programmable logic (“FPGA”) and a multi-core micro-processor with an integrated Controller Area Network (“CAN”) or Ethernet interface on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of environment of vehicle  1200 , including a distance estimate for all points in image. In at least one embodiment, one or more of stereo camera(s)  1268  may include, without limitation, compact stereo vision sensor(s) that may include, without limitation, two camera lenses (one each on left and right) and an image processing chip that may measure distance from vehicle  1200  to target object and use generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo camera(s)  1268  may be used in addition to, or alternatively from, those described herein. 
     In at least one embodiment, cameras with a field of view that include portions of environment to side of vehicle  1200  (e.g., side-view cameras) may be used for surround view, providing information used to create and update occupancy grid, as well as to generate side impact collision warnings. For example, in at least one embodiment, surround camera(s)  1274  (e.g., four surround cameras  1274  as illustrated in  FIG. 12B ) could be positioned on vehicle  1200 . Surround camera(s)  1274  may include, without limitation, any number and combination of wide-view camera(s)  1270 , fisheye camera(s), 360 degree camera(s), and/or like. For instance, in at least one embodiment, four fisheye cameras may be positioned on front, rear, and sides of vehicle  1200 . In at least one embodiment, vehicle  1200  may use three surround camera(s)  1274  (e.g., left, right, and rear), and may leverage one or more other camera(s) (e.g., a forward-facing camera) as a fourth surround-view camera. 
     In at least one embodiment, cameras with a field of view that include portions of environment to rear of vehicle  1200  (e.g., rear-view cameras) may be used for park assistance, surround view, rear collision warnings, and creating and updating occupancy grid. In at least one embodiment, a wide variety of cameras may be used including, but not limited to, cameras that are also suitable as a front-facing camera(s) (e.g., long-range cameras  1298  and/or mid-range camera(s)  1276 , stereo camera(s)  1268 ), infrared camera(s)  1272 , etc.), as described herein. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 12B  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 12B  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 12C  is a block diagram illustrating an example system architecture for autonomous vehicle  1200  of  FIG. 12A , according to at least one embodiment. In at least one embodiment, each of components, features, and systems of vehicle  1200  in  FIG. 12C  are illustrated as being connected via a bus  1202 . In at least one embodiment, bus  1202  may include, without limitation, a CAN data interface (alternatively referred to herein as a “CAN bus”). In at least one embodiment, a CAN may be a network inside vehicle  1200  used to aid in control of various features and functionality of vehicle  1200 , such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus  1202  may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus  1202  may be read to find steering wheel angle, ground speed, engine revolutions per minute (“RPMs”), button positions, and/or other vehicle status indicators. In at least one embodiment, bus  1202  may be a CAN bus that is ASIL B compliant. 
     In at least one embodiment, in addition to, or alternatively from CAN, FlexRay and/or Ethernet may be used. In at least one embodiment, there may be any number of busses  1202 , which may include, without limitation, zero or more CAN busses, zero or more FlexRay busses, zero or more Ethernet busses, and/or zero or more other types of busses using a different protocol. In at least one embodiment, two or more busses  1202  may be used to perform different functions, and/or may be used for redundancy. For example, a first bus  1202  may be used for collision avoidance functionality and a second bus  1202  may be used for actuation control. In at least one embodiment, each bus  1202  may communicate with any of components of vehicle  1200 , and two or more busses  1202  may communicate with same components. In at least one embodiment, each of any number of system(s) on chip(s) (“SoC(s)”)  1204 , each of controller(s)  1236 , and/or each computer within vehicle may have access to same input data (e.g., inputs from sensors of vehicle  1200 ), and may be connected to a common bus, such CAN bus. 
     In at least one embodiment, vehicle  1200  may include one or more controller(s)  1236 , such as those described herein with respect to  FIG. 12A . Controller  1236  may be used for a variety of functions. In at least one embodiment, controller(s)  1236  may be coupled to any of various other components and systems of vehicle  1200 , and may be used for control of vehicle  1200 , artificial intelligence of vehicle  1200 , infotainment for vehicle  1200 , and/or like. 
     In at least one embodiment, vehicle  1200  may include any number of SoCs  1204 . Each of SoCs  1204  may include, without limitation, central processing units (“CPU(s)”)  1206 , graphics processing units (“GPU(s)”)  1208 , processor(s)  1210 , cache(s)  1212 , accelerator(s)  1214 , data store(s)  1216 , and/or other components and features not illustrated. In at least one embodiment, SoC(s)  1204  may be used to control vehicle  1200  in a variety of platforms and systems. For example, in at least one embodiment, SoC(s)  1204  may be combined in a system (e.g., system of vehicle  1200 ) with a High Definition (“HD”) map  1222  which may obtain map refreshes and/or updates via network interface  1224  from one or more servers (not shown in  FIG. 12C ). 
     In at least one embodiment, CPU(s)  1206  may include a CPU cluster or CPU complex (alternatively referred to herein as a “CCPLEX”). In at least one embodiment, CPU(s)  1206  may include multiple cores and/or level two (“L2”) caches. For instance, in at least one embodiment, CPU(s)  1206  may include eight cores in a coherent multi-processor configuration. In at least one embodiment, CPU(s)  1206  may include four dual-core clusters where each cluster has a dedicated L2 cache (e.g., a 2 MB L2 cache). In at least one embodiment, CPU(s)  1206  (e.g., CCPLEX) may be configured to support simultaneous cluster operation enabling any combination of clusters of CPU(s)  1206  to be active at any given time. 
     In at least one embodiment, one or more of CPU(s)  1206  may implement power management capabilities that include, without limitation, one or more of following features: individual hardware blocks may be clock-gated automatically when idle to save dynamic power; each core clock may be gated when core is not actively executing instructions due to execution of Wait for Interrupt (“WFI”)/Wait for Event (“WFE”) instructions; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and/or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, CPU(s)  1206  may further implement an enhanced algorithm for managing power states, where allowed power states and expected wakeup times are specified, and hardware/microcode determines best power state to enter for core, cluster, and CCPLEX. In at least one embodiment, processing cores may support simplified power state entry sequences in software with work offloaded to microcode. 
     In at least one embodiment, GPU(s)  1208  may include an integrated GPU (alternatively referred to herein as an “iGPU”). In at least one embodiment, GPU(s)  1208  may be programmable and may be efficient for parallel workloads. In at least one embodiment, GPU(s)  1208 , in at least one embodiment, may use an enhanced tensor instruction set. In on embodiment, GPU(s)  1208  may include one or more streaming microprocessors, where each streaming microprocessor may include a level one (“L1”) cache (e.g., an L1 cache with at least 96 KB storage capacity), and two or more of streaming microprocessors may share an L2 cache (e.g., an L2 cache with a 512 KB storage capacity). In at least one embodiment, GPU(s)  1208  may include at least eight streaming microprocessors. In at least one embodiment, GPU(s)  1208  may use compute application programming interface(s) (API(s)). In at least one embodiment, GPU(s)  1208  may use one or more parallel computing platforms and/or programming models (e.g., NVIDIA&#39;s CUDA). 
     In at least one embodiment, one or more of GPU(s)  1208  may be power-optimized for best performance in automotive and embedded use cases. For example, in on embodiment, GPU(s)  1208  could be fabricated on a Fin field-effect transistor (“FinFET”). In at least one embodiment, each streaming microprocessor may incorporate a number of mixed-precision processing cores partitioned into multiple blocks. For example, and without limitation, 64 PF32 cores and 32 PF64 cores could be partitioned into four processing blocks. In at least one embodiment, each processing block could be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA TENSOR COREs for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and/or a 64 KB register file. In at least one embodiment, streaming microprocessors may include independent parallel integer and floating-point data paths to provide for efficient execution of workloads with a mix of computation and addressing calculations. In at least one embodiment, streaming microprocessors may include independent thread scheduling capability to enable finer-grain synchronization and cooperation between parallel threads. In at least one embodiment, streaming microprocessors may include a combined L1 data cache and shared memory unit in order to improve performance while simplifying programming. 
     In at least one embodiment, one or more of GPU(s)  1208  may include a high bandwidth memory (“HBM) and/or a 16 GB HBM2 memory subsystem to provide, in some examples, about 900 GB/second peak memory bandwidth. In at least one embodiment, in addition to, or alternatively from, HBM memory, a synchronous graphics random-access memory (“SGRAM”) may be used, such as a graphics double data rate type five synchronous random-access memory (“GDDR5”). 
     In at least one embodiment, GPU(s)  1208  may include unified memory technology. In at least one embodiment, address translation services (“ATS”) support may be used to allow GPU(s)  1208  to access CPU(s)  1206  page tables directly. In at least one embodiment, embodiment, when GPU(s)  1208  memory management unit (“MMU”) experiences a miss, an address translation request may be transmitted to CPU(s)  1206 . In response, CPU(s)  1206  may look in its page tables for virtual-to-physical mapping for address and transmits translation back to GPU(s)  1208 , in at least one embodiment. In at least one embodiment, unified memory technology may allow a single unified virtual address space for memory of both CPU(s)  1206  and GPU(s)  1208 , thereby simplifying GPU(s)  1208  programming and porting of applications to GPU(s)  1208 . 
     In at least one embodiment, GPU(s)  1208  may include any number of access counters that may keep track of frequency of access of GPU(s)  1208  to memory of other processors. In at least one embodiment, access counter(s) may help ensure that memory pages are moved to physical memory of processor that is accessing pages most frequently, thereby improving efficiency for memory ranges shared between processors. 
     In at least one embodiment, one or more of SoC(s)  1204  may include any number of cache(s)  1212 , including those described herein. For example, in at least one embodiment, cache(s)  1212  could include a level three (“L3”) cache that is available to both CPU(s)  1206  and GPU(s)  1208  (e.g., that is connected both CPU(s)  1206  and GPU(s)  1208 ). In at least one embodiment, cache(s)  1212  may include a write-back cache that may keep track of states of lines, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, L3 cache may include 4 MB or more, depending on embodiment, although smaller cache sizes may be used. 
     In at least one embodiment, one or more of SoC(s)  1204  may include one or more accelerator(s)  1214  (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, SoC(s)  1204  may include a hardware acceleration cluster that may include optimized hardware accelerators and/or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4 MB of SRAM), may enable hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, hardware acceleration cluster may be used to complement GPU(s)  1208  and to off-load some of tasks of GPU(s)  1208  (e.g., to free up more cycles of GPU(s)  1208  for performing other tasks). In at least one embodiment, accelerator(s)  1214  could be used for targeted workloads (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.) that are stable enough to be amenable to acceleration. In at least one embodiment, a CNN may include a region-based or regional convolutional neural networks (“RCNNs”) and Fast RCNNs (e.g., as used for object detection) or other type of CNN. 
     In at least one embodiment, accelerator(s)  1214  (e.g., hardware acceleration cluster) may include a deep learning accelerator(s) (“DLA). DLA(s) may include, without limitation, one or more Tensor processing units (“TPUs) that may be configured to provide an additional ten trillion operations per second for deep learning applications and inferencing. In at least one embodiment, TPUs may be accelerators configured to, and optimized for, performing image processing functions (e.g., for CNNs, RCNNs, etc.). DLA(s) may further be optimized for a specific set of neural network types and floating point operations, as well as inferencing. In at least one embodiment, design of DLA(s) may provide more performance per millimeter than a typical general-purpose GPU, and typically vastly exceeds performance of a CPU. In at least one embodiment, TPU(s) may perform several functions, including a single-instance convolution function, supporting, for example, INT8, INT16, and FP16 data types for both features and weights, as well as post-processor functions. In at least one embodiment, DLA(s) may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example and without limitation: a CNN for object identification and detection using data from camera sensors; a CNN for distance estimation using data from camera sensors; a CNN for emergency vehicle detection and identification and detection using data from microphones  1296 ; a CNN for facial recognition and vehicle owner identification using data from camera sensors; and/or a CNN for security and/or safety related events. 
     In at least one embodiment, DLA(s) may perform any function of GPU(s)  1208 , and by using an inference accelerator, for example, a designer may target either DLA(s) or GPU(s)  1208  for any function. For example, in at least one embodiment, designer may focus processing of CNNs and floating point operations on DLA(s) and leave other functions to GPU(s)  1208  and/or other accelerator(s)  1214 . 
     In at least one embodiment, accelerator(s)  1214  (e.g., hardware acceleration cluster) may include a programmable vision accelerator(s) (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, PVA(s) may be designed and configured to accelerate computer vision algorithms for advanced driver assistance system (“ADAS”)  1238 , autonomous driving, augmented reality (“AR”) applications, and/or virtual reality (“VR”) applications. PVA(s) may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA(s) may include, for example and without limitation, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and/or any number of vector processors. 
     In at least one embodiment, RISC cores may interact with image sensors (e.g., image sensors of any of cameras described herein), image signal processor(s), and/or like. In at least one embodiment, each of RISC cores may include any amount of memory. In at least one embodiment, RISC cores may use any of a number of protocols, depending on embodiment. In at least one embodiment, RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, RISC cores may be implemented using one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and/or memory devices. For example, in at least one embodiment, RISC cores could include an instruction cache and/or a tightly coupled RAM. 
     In at least one embodiment, DMA may enable components of PVA(s) to access system memory independently of CPU(s)  1206 . In at least one embodiment, DMA may support any number of features used to provide optimization to PVA including, but not limited to, supporting multi-dimensional addressing and/or circular addressing. In at least one embodiment, DMA may support up to six or more dimensions of addressing, which may include, without limitation, block width, block height, block depth, horizontal block stepping, vertical block stepping, and/or depth stepping. 
     In at least one embodiment, vector processors may be programmable processors that may be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, PVA core may include a processor subsystem, DMA engine(s) (e.g., two DMA engines), and/or other peripherals. In at least one embodiment, vector processing subsystem may operate as primary processing engine of PVA, and may include a vector processing unit (“VPU”), an instruction cache, and/or vector memory (e.g., “VMEM”). In at least one embodiment, VPU core may include a digital signal processor such as, for example, a single instruction, multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, a combination of SIMD and VLIW may enhance throughput and speed. 
     In at least one embodiment, each of vector processors may include an instruction cache and may be coupled to dedicated memory. As a result, in at least one embodiment, each of vector processors may be configured to execute independently of other vector processors. In at least one embodiment, vector processors that are included in a particular PVA may be configured to employ data parallelism. For instance, in at least one embodiment, plurality of vector processors included in a single PVA may execute same computer vision algorithm, but on different regions of an image. In at least one embodiment, vector processors included in a particular PVA may simultaneously execute different computer vision algorithms, on same image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, among other things, any number of PVAs may be included in hardware acceleration cluster and any number of vector processors may be included in each of PVAs. In at least one embodiment, PVA(s) may include additional error correcting code (“ECC”) memory, to enhance overall system safety. 
     In at least one embodiment, accelerator(s)  1214  (e.g., hardware acceleration cluster) may include a computer vision network on-chip and static random-access memory (“SRAM”), for providing a high-bandwidth, low latency SRAM for accelerator(s)  1214 . In at least one embodiment, on-chip memory may include at least 4 MB SRAM, consisting of, for example and without limitation, eight field-configurable memory blocks, that may be accessible by both PVA and DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, PVA and DLA may access memory via a backbone that provides PVA and DLA with high-speed access to memory. In at least one embodiment, backbone may include a computer vision network on-chip that interconnects PVA and DLA to memory (e.g., using APB). 
     In at least one embodiment, computer vision network on-chip may include an interface that determines, before transmission of any control signal/address/data, that both PVA and DLA provide ready and valid signals. In at least one embodiment, an interface may provide for separate phases and separate channels for transmitting control signals/addresses/data, as well as burst-type communications for continuous data transfer. In at least one embodiment, an interface may comply with International Organization for Standardization (“ISO”) 26262 or International Electrotechnical Commission (“IEC”) 61508 standards, although other standards and protocols may be used. 
     In at least one embodiment, one or more of SoC(s)  1204  may include a real-time ray-tracing hardware accelerator. In at least one embodiment, real-time ray-tracing hardware accelerator may be used to quickly and efficiently determine positions and extents of objects (e.g., within a world model), to generate real-time visualization simulations, for RADAR signal interpretation, for sound propagation synthesis and/or analysis, for simulation of SONAR systems, for general wave propagation simulation, for comparison to LIDAR data for purposes of localization and/or other functions, and/or for other uses. 
     In at least one embodiment, accelerator(s)  1214  (e.g., hardware accelerator cluster) have a wide array of uses for autonomous driving. In at least one embodiment, PVA may be a programmable vision accelerator that may be used for key processing stages in ADAS and autonomous vehicles. In at least one embodiment, PVA&#39;s capabilities are a good match for algorithmic domains needing predictable processing, at low power and low latency. In other words, PVA performs well on semi-dense or dense regular computation, even on small data sets, which need predictable run-times with low latency and low power. In at least one embodiment, autonomous vehicles, such as vehicle  1200 , PVAs are designed to run classic computer vision algorithms, as they are efficient at object detection and operating on integer math. 
     For example, according to at least one embodiment of technology, PVA is used to perform computer stereo vision. In at least one embodiment, semi-global matching-based algorithm may be used in some examples, although this is not intended to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use motion estimation/stereo matching on-the-fly (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA may perform computer stereo vision function on inputs from two monocular cameras. 
     In at least one embodiment, PVA may be used to perform dense optical flow. For example, in at least one embodiment, PVA could process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, PVA is used for time of flight depth processing, by processing raw time of flight data to provide processed time of flight data, for example. 
     In at least one embodiment, DLA may be used to run any type of network to enhance control and driving safety, including for example and without limitation, a neural network that outputs a measure of confidence for each object detection. In at least one embodiment, confidence may be represented or interpreted as a probability, or as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, confidence enables a system to make further decisions regarding which detections should be considered as true positive detections rather than false positive detections. For example, in at least one embodiment, a system may set a threshold value for confidence and consider only detections exceeding threshold value as true positive detections. In an embodiment in which an automatic emergency braking (“AEB”) system is used, false positive detections would cause vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, highly confident detections may be considered as triggers for AEB In at least one embodiment, DLA may run a neural network for regressing confidence value. In at least one embodiment, neural network may take as its input at least some subset of parameters, such as bounding box dimensions, ground plane estimate obtained (e.g. from another subsystem), output from IMU sensor(s)  1266  that correlates with vehicle  1200  orientation, distance, 3D location estimates of object obtained from neural network and/or other sensors (e.g., LIDAR sensor(s)  1264  or RADAR sensor(s)  1260 ), among others. 
     In at least one embodiment, one or more of SoC(s)  1204  may include data store(s)  1216  (e.g., memory). In at least one embodiment, data store(s)  1216  may be on-chip memory of SoC(s)  1204 , which may store neural networks to be executed on GPU(s)  1208  and/or DLA. In at least one embodiment, data store(s)  1216  may be large enough in capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, data store(s)  1212  may comprise L2 or L3 cache(s). 
     In at least one embodiment, one or more of SoC(s)  1204  may include any number of processor(s)  1210  (e.g., embedded processors). Processor  1210  may include a boot and power management processor that may be a dedicated processor and subsystem to handle boot power and management functions and related security enforcement. In at least one embodiment, boot and power management processor may be a part of SoC(s)  1204  boot sequence and may provide runtime power management services. In at least one embodiment, boot power and management processor may provide clock and voltage programming, assistance in system low power state transitions, management of SoC(s)  1204  thermals and temperature sensors, and/or management of SoC(s)  1204  power states. In at least one embodiment, each temperature sensor may be implemented as a ring-oscillator whose output frequency is proportional to temperature, and SoC(s)  1204  may use ring-oscillators to detect temperatures of CPU(s)  1206 , GPU(s)  1208 , and/or accelerator(s)  1214 . In at least one embodiment, if temperatures are determined to exceed a threshold, then boot and power management processor may enter a temperature fault routine and put SoC(s)  1204  into a lower power state and/or put vehicle  1200  into a chauffeur to safe stop mode (e.g., bring vehicle  1200  to a safe stop). 
     In at least one embodiment, processor(s)  1210  may further include a set of embedded processors that may serve as an audio processing engine. In at least one embodiment, audio processing engine may be an audio subsystem that enables full hardware support for multi-channel audio over multiple interfaces, and a broad and flexible range of audio I/O interfaces. In at least one embodiment, audio processing engine is a dedicated processor core with a digital signal processor with dedicated RAM. 
     In at least one embodiment, processor(s)  1210  may further include an always on processor engine that may provide necessary hardware features to support low power sensor management and wake use cases. In at least one embodiment, always on processor engine may include, without limitation, a processor core, a tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I/O controller peripherals, and routing logic. 
     In at least one embodiment, processor(s)  1210  may further include a safety cluster engine that includes, without limitation, a dedicated processor subsystem to handle safety management for automotive applications. In at least one embodiment, safety cluster engine may include, without limitation, two or more processor cores, a tightly coupled RAM, support peripherals (e.g., timers, an interrupt controller, etc.), and/or routing logic. In a safety mode, two or more cores may operate, in at least one embodiment, in a lockstep mode and function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, processor(s)  1210  may further include a real-time camera engine that may include, without limitation, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, processor(s)  1210  may further include a high-dynamic range signal processor that may include, without limitation, an image signal processor that is a hardware engine that is part of camera processing pipeline. 
     In at least one embodiment, processor(s)  1210  may include a video image compositor that may be a processing block (e.g., implemented on a microprocessor) that implements video post-processing functions needed by a video playback application to produce final image for player window. In at least one embodiment, video image compositor may perform lens distortion correction on wide-view camera(s)  1270 , surround camera(s)  1274 , and/or on in-cabin monitoring camera sensor(s). In at least one embodiment, in-cabin monitoring camera sensor(s) are preferably monitored by a neural network running on another instance of SoC  1204 , configured to identify in cabin events and respond accordingly. In at least one embodiment, an in-cabin system may perform, without limitation, lip reading to activate cellular service and place a phone call, dictate emails, change vehicle&#39;s destination, activate or change vehicle&#39;s infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to driver when vehicle is operating in an autonomous mode and are disabled otherwise. 
     In at least one embodiment, video image compositor may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in a video, noise reduction weights spatial information appropriately, decreasing weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, temporal noise reduction performed by video image compositor may use information from previous image to reduce noise in current image. 
     In at least one embodiment, video image compositor may also be configured to perform stereo rectification on input stereo lens frames. In at least one embodiment, video image compositor may further be used for user interface composition when operating system desktop is in use, and GPU(s)  1208  are not required to continuously render new surfaces. In at least one embodiment, when GPU(s)  1208  are powered on and active doing 3D rendering, video image compositor may be used to offload GPU(s)  1208  to improve performance and responsiveness. 
     In at least one embodiment, one or more of SoC(s)  1204  may further include a mobile industry processor interface (“MIPI”) camera serial interface for receiving video and input from cameras, a high-speed interface, and/or a video input block that may be used for camera and related pixel input functions. In at least one embodiment, one or more of SoC(s)  1204  may further include an input/output controller(s) that may be controlled by software and may be used for receiving I/O signals that are uncommitted to a specific role. 
     In at least one embodiment, one or more of SoC(s)  1204  may further include a broad range of peripheral interfaces to enable communication with peripherals, audio encoders/decoders (“codecs”), power management, and/or other devices. SoC(s)  1204  may be used to process data from cameras (e.g., connected over Gigabit Multimedia Serial Link and Ethernet), sensors (e.g., LIDAR sensor(s)  1264 , RADAR sensor(s)  1260 , etc. that may be connected over Ethernet), data from bus  1202  (e.g., speed of vehicle  1200 , steering wheel position, etc.), data from GNSS sensor(s)  1258  (e.g., connected over Ethernet or CAN bus), etc. In at least one embodiment, one or more of SoC(s)  1204  may further include dedicated high-performance mass storage controllers that may include their own DMA engines, and that may be used to free CPU(s)  1206  from routine data management tasks. 
     In at least one embodiment, SoC(s)  1204  may be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and makes efficient use of computer vision and ADAS techniques for diversity and redundancy, provides a platform for a flexible, reliable driving software stack, along with deep learning tools. In at least one embodiment, SoC(s)  1204  may be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, accelerator(s)  1214 , when combined with CPU(s)  1206 , GPU(s)  1208 , and data store(s)  1216 , may provide for a fast, efficient platform for level 3-5 autonomous vehicles. 
     In at least one embodiment, computer vision algorithms may be executed on CPUs, which may be configured using high-level programming language, such as C programming language, to execute a wide variety of processing algorithms across a wide variety of visual data. However, in at least one embodiment, CPUs are oftentimes unable to meet performance requirements of many computer vision applications, such as those related to execution time and power consumption, for example. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real-time, which is used in in-vehicle ADAS applications and in practical Level 3-5 autonomous vehicles. 
     Embodiments described herein allow for multiple neural networks to be performed simultaneously and/or sequentially, and for results to be combined together to enable Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executing on DLA or discrete GPU (e.g., GPU(s)  1220 ) may include text and word recognition, allowing supercomputer to read and understand traffic signs, including signs for which neural network has not been specifically trained. In at least one embodiment, DLA may further include a neural network that is able to identify, interpret, and provide semantic understanding of sign, and to pass that semantic understanding to path planning modules running on CPU Complex. 
     In at least one embodiment, multiple neural networks may be run simultaneously, as for Level 3, 4, or 5 driving. For example, in at least one embodiment, a warning sign consisting of “Caution: flashing lights indicate icy conditions,” along with an electric light, may be independently or collectively interpreted by several neural networks. In at least one embodiment, sign itself may be identified as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), text “flashing lights indicate icy conditions” may be interpreted by a second deployed neural network, which informs vehicle&#39;s path planning software (preferably executing on CPU Complex) that when flashing lights are detected, icy conditions exist. In at least one embodiment, flashing light may be identified by operating a third deployed neural network over multiple frames, informing vehicle&#39;s path-planning software of presence (or absence) of flashing lights. In at least one embodiment, all three neural networks may run simultaneously, such as within DLA and/or on GPU(s)  1208 . 
     In at least one embodiment, a CNN for facial recognition and vehicle owner identification may use data from camera sensors to identify presence of an authorized driver and/or owner of vehicle  1200 . In at least one embodiment, an always on sensor processing engine may be used to unlock vehicle when owner approaches driver door and turn on lights, and, in security mode, to disable vehicle when owner leaves vehicle. In this way, SoC(s)  1204  provide for security against theft and/or carjacking. 
     In at least one embodiment, a CNN for emergency vehicle detection and identification may use data from microphones  1296  to detect and identify emergency vehicle sirens. In at least one embodiment, SoC(s)  1204  use CNN for classifying environmental and urban sounds, as well as classifying visual data. In at least one embodiment, CNN running on DLA is trained to identify relative closing speed of emergency vehicle (e.g., by using Doppler effect). In at least one embodiment, CNN may also be trained to identify emergency vehicles specific to local area in which vehicle is operating, as identified by GNSS sensor(s)  1258 . In at least one embodiment, when operating in Europe, CNN will seek to detect European sirens, and when in United States CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program may be used to execute an emergency vehicle safety routine, slowing vehicle, pulling over to side of road, parking vehicle, and/or idling vehicle, with assistance of ultrasonic sensor(s)  1262 , until emergency vehicle(s) passes. 
     In at least one embodiment, vehicle  1200  may include CPU(s)  1218  (e.g., discrete CPU(s), or dCPU(s)), that may be coupled to SoC(s)  1204  via a high-speed interconnect (e.g., PCIe). In at least one embodiment, CPU(s)  1218  may include an X86 processor, for example. CPU(s)  1218  may be used to perform any of a variety of functions, including arbitrating potentially inconsistent results between ADAS sensors and SoC(s)  1204 , and/or monitoring status and health of controller(s)  1236  and/or an infotainment system on a chip (“infotainment SoC”)  1230 , for example. 
     In at least one embodiment, vehicle  1200  may include GPU(s)  1220  (e.g., discrete GPU(s), or dGPU(s)), that may be coupled to SoC(s)  1204  via a high-speed interconnect (e.g., NVIDIA&#39;s NVLINK). In at least one embodiment, GPU(s)  1220  may provide additional artificial intelligence functionality, such as by executing redundant and/or different neural networks, and may be used to train and/or update neural networks based at least in part on input (e.g., sensor data) from sensors of vehicle  1200 . 
     In at least one embodiment, vehicle  1200  may further include network interface  1224  which may include, without limitation, wireless antenna(s)  1226  (e.g., one or more wireless antennas  1226  for different communication protocols, such as a cellular antenna, a Bluetooth antenna, etc.). In at least one embodiment, network interface  1224  may be used to enable wireless connectivity over Internet with cloud (e.g., with server(s) and/or other network devices), with other vehicles, and/or with computing devices (e.g., client devices of passengers). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle  120  and other vehicle and/or an indirect link may be established (e.g., across networks and over Internet). In at least one embodiment, direct links may be provided using a vehicle-to-vehicle communication link. Vehicle-to-vehicle communication link may provide vehicle  1200  information about vehicles in proximity to vehicle  1200  (e.g., vehicles in front of, on side of, and/or behind vehicle  1200 ). In at least one embodiment, aforementioned functionality may be part of a cooperative adaptive cruise control functionality of vehicle  1200 . 
     In at least one embodiment, network interface  1224  may include an SoC that provides modulation and demodulation functionality and enables controller(s)  1236  to communicate over wireless networks. In at least one embodiment, network interface  1224  may include a radio frequency front-end for up-conversion from baseband to radio frequency, and down conversion from radio frequency to baseband. In at least one embodiment, frequency conversions may be performed in any technically feasible fashion. For example, frequency conversions could be performed through well-known processes, and/or using super-heterodyne processes. In at least one embodiment, radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and/or other wireless protocols. 
     In at least one embodiment, vehicle  1200  may further include data store(s)  1228  which may include, without limitation, off-chip (e.g., off SoC(s)  1204 ) storage. In at least one embodiment, data store(s)  1228  may include, without limitation, one or more storage elements including RAM, SRAM, dynamic random-access memory (“DRAM”), video random-access memory (“VRAM”), Flash, hard disks, and/or other components and/or devices that may store at least one bit of data. 
     In at least one embodiment, vehicle  1200  may further include GNSS sensor(s)  1258  (e.g., GPS and/or assisted GPS sensors), to assist in mapping, perception, occupancy grid generation, and/or path planning functions. In at least one embodiment, any number of GNSS sensor(s)  1258  may be used, including, for example and without limitation, a GPS using a USB connector with an Ethernet to Serial (e.g., RS-232) bridge. 
     In at least one embodiment, vehicle  1200  may further include RADAR sensor(s)  1260 . RADAR sensor(s)  1260  may be used by vehicle  1200  for long-range vehicle detection, even in darkness and/or severe weather conditions. In at least one embodiment, RADAR functional safety levels may be ASIL B. RADAR sensor(s)  1260  may use CAN and/or bus  1202  (e.g., to transmit data generated by RADAR sensor(s)  1260 ) for control and to access object tracking data, with access to Ethernet to access raw data in some examples. In at least one embodiment, wide variety of RADAR sensor types may be used. For example, and without limitation, RADAR sensor(s)  1260  may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of RADAR sensors(s)  1260  are Pulse Doppler RADAR sensor(s). 
     In at least one embodiment, RADAR sensor(s)  1260  may include different configurations, such as long-range with narrow field of view, short-range with wide field of view, short-range side coverage, etc. In at least one embodiment, long-range RADAR may be used for adaptive cruise control functionality. In at least one embodiment, long-range RADAR systems may provide a broad field of view realized by two or more independent scans, such as within a 250 m range. In at least one embodiment, RADAR sensor(s)  1260  may help in distinguishing between static and moving objects, and may be used by ADAS system  1238  for emergency brake assist and forward collision warning. Sensors  1260 ( s ) included in a long-range RADAR system may include, without limitation, monostatic multimodal RADAR with multiple (e.g., six or more) fixed RADAR antennae and a high-speed CAN and FlexRay interface. In at least one embodiment, with six antennae, central four antennae may create a focused beam pattern, designed to record vehicle&#39;s  1200  surroundings at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, other two antennae may expand field of view, making it possible to quickly detect vehicles entering or leaving vehicle&#39;s  1200  lane. 
     In at least one embodiment, mid-range RADAR systems may include, as an example, a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, short-range RADAR systems may include, without limitation, any number of RADAR sensor(s)  1260  designed to be installed at both ends of rear bumper. When installed at both ends of rear bumper, in at least one embodiment, a RADAR sensor system may create two beams that constantly monitor blind spot in rear and next to vehicle. In at least one embodiment, short-range RADAR systems may be used in ADAS system  1238  for blind spot detection and/or lane change assist. 
     In at least one embodiment, vehicle  1200  may further include ultrasonic sensor(s)  1262 . Ultrasonic sensor(s)  1262 , which may be positioned at front, back, and/or sides of vehicle  1200 , may be used for park assist and/or to create and update an occupancy grid. In at least one embodiment, a wide variety of ultrasonic sensor(s)  1262  may be used, and different ultrasonic sensor(s)  1262  may be used for different ranges of detection (e.g., 2.5 m, 4 m). In at least one embodiment, ultrasonic sensor(s)  1262  may operate at functional safety levels of ASIL B. 
     In at least one embodiment, vehicle  1200  may include LIDAR sensor(s)  1264 . LIDAR sensor(s)  1264  may be used for object and pedestrian detection, emergency braking, collision avoidance, and/or other functions. In at least one embodiment, LIDAR sensor(s)  1264  may be functional safety level ASIL B. In at least one embodiment, vehicle  1200  may include multiple LIDAR sensors  1264  (e.g., two, four, six, etc.) that may use Ethernet (e.g., to provide data to a Gigabit Ethernet switch). 
     In at least one embodiment, LIDAR sensor(s)  1264  may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available LIDAR sensor(s)  1264  may have an advertised range of approximately 100 m, with an accuracy of 2 cm-3 cm, and with support for a 100 Mbps Ethernet connection, for example. In at least one embodiment, one or more non-protruding LIDAR sensors  1264  may be used. In such an embodiment, LIDAR sensor(s)  1264  may be implemented as a small device that may be embedded into front, rear, sides, and/or corners of vehicle  1200 . In at least one embodiment, LIDAR sensor(s)  1264 , in such an embodiment, may provide up to a 120-degree horizontal and 35-degree vertical field-of-view, with a 200 m range even for low-reflectivity objects. In at least one embodiment, front-mounted LIDAR sensor(s)  1264  may be configured for a horizontal field of view between 45 degrees and 135 degrees. 
     In at least one embodiment, LIDAR technologies, such as 3D flash LIDAR, may also be used. 3D Flash LIDAR uses a flash of a laser as a transmission source, to illuminate surroundings of vehicle  1200  up to approximately 200 m. In at least one embodiment, a flash LIDAR unit includes, without limitation, a receptor, which records laser pulse transit time and reflected light on each pixel, which in turn corresponds to range from vehicle  1200  to objects. In at least one embodiment, flash LIDAR may allow for highly accurate and distortion-free images of surroundings to be generated with every laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, one at each side of vehicle  1200 . In at least one embodiment, 3D flash LIDAR systems include, without limitation, a solid-state 3D staring array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, flash LIDAR device may use a 5 nanosecond class I (eye-safe) laser pulse per frame and may capture reflected laser light in form of 3D range point clouds and co-registered intensity data. 
     In at least one embodiment, vehicle may further include IMU sensor(s)  1266 . In at least one embodiment, IMU sensor(s)  1266  may be located at a center of rear axle of vehicle  1200 , in at least one embodiment. In at least one embodiment, IMU sensor(s)  1266  may include, for example and without limitation, accelerometer(s), magnetometer(s), gyroscope(s), magnetic compass(es), and/or other sensor types. In at least one embodiment, such as in six-axis applications, IMU sensor(s)  1266  may include, without limitation, accelerometers and gyroscopes. In at least one embodiment, such as in nine-axis applications, IMU sensor(s)  1266  may include, without limitation, accelerometers, gyroscopes, and magnetometers. 
     In at least one embodiment, IMU sensor(s)  1266  may be implemented as a miniature, high performance GPS-Aided Inertial Navigation System (“GPS/INS”) that combines micro-electro-mechanical systems (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude. In at least one embodiment, IMU sensor(s)  1266  may enable vehicle  1200  to estimate heading without requiring input from a magnetic sensor by directly observing and correlating changes in velocity from GPS to IMU sensor(s)  1266 . In at least one embodiment, IMU sensor(s)  1266  and GNSS sensor(s)  1258  may be combined in a single integrated unit. 
     In at least one embodiment, vehicle  1200  may include microphone(s)  1296  placed in and/or around vehicle  1200 . In at least one embodiment, microphone(s)  1296  may be used for emergency vehicle detection and identification, among other things. 
     In at least one embodiment, vehicle  1200  may further include any number of camera types, including stereo camera(s)  1268 , wide-view camera(s)  1270 , infrared camera(s)  1272 , surround camera(s)  1274 , long-range camera(s)  1298 , mid-range camera(s)  1276 , and/or other camera types. In at least one embodiment, cameras may be used to capture image data around an entire periphery of vehicle  1200 . In at least one embodiment, types of cameras used depends vehicle  1200 . In at least one embodiment, any combination of camera types may be used to provide necessary coverage around vehicle  1200 . In at least one embodiment, number of cameras may differ depending on embodiment. For example, in at least one embodiment, vehicle  1200  could include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. Cameras may support, as an example and without limitation, Gigabit Multimedia Serial Link (“GMSL”) and/or Gigabit Ethernet. In at least one embodiment, each of camera(s) is described with more detail previously herein with respect to  FIG. 12A  and  FIG. 12B . 
     In at least one embodiment, vehicle  1200  may further include vibration sensor(s)  1242 . Vibration sensor(s)  1242  may measure vibrations of components of vehicle  1200 , such as axle(s). For example, in at least one embodiment, changes in vibrations may indicate a change in road surfaces. In at least one embodiment, when two or more vibration sensors  1242  are used, differences between vibrations may be used to determine friction or slippage of road surface (e.g., when difference in vibration is between a power-driven axle and a freely rotating axle). 
     In at least one embodiment, vehicle  1200  may include ADAS system  1238 . ADAS system  1238  may include, without limitation, an SoC, in some examples. In at least one embodiment, ADAS system  1238  may include, without limitation, any number and combination of an autonomous/adaptive/automatic cruise control (“ACC”) system, a cooperative adaptive cruise control (“CACC”) system, a forward crash warning (“FCW”) system, an automatic emergency braking (“AEB”) system, a lane departure warning (“LDW)” system, a lane keep assist (“LKA”) system, a blind spot warning (“BSW”) system, a rear cross-traffic warning (“RCTW”) system, a collision warning (“CW”) system, a lane centering (“LC”) system, and/or other systems, features, and/or functionality. 
     In at least one embodiment, ACC system may use RADAR sensor(s)  1260 , LIDAR sensor(s)  1264 , and/or any number of camera(s). In at least one embodiment, ACC system may include a longitudinal ACC system and/or a lateral ACC system. In at least one embodiment, longitudinal ACC system monitors and controls distance to vehicle immediately ahead of vehicle  1200  and automatically adjust speed of vehicle  1200  to maintain a safe distance from vehicles ahead. In at least one embodiment, lateral ACC system performs distance keeping, and advises vehicle  1200  to change lanes when necessary. In at least one embodiment, lateral ACC is related to other ADAS applications such as LC and CW. 
     In at least one embodiment, CACC system uses information from other vehicles that may be received via network interface  1224  and/or wireless antenna(s)  1226  from other vehicles via a wireless link, or indirectly, over a network connection (e.g., over Internet). In at least one embodiment, direct links may be provided by a vehicle-to-vehicle (“V2V”) communication link, while indirect links may be provided by an infrastructure-to-vehicle (“I2V”) communication link. In general, V2V communication concept provides information about immediately preceding vehicles (e.g., vehicles immediately ahead of and in same lane as vehicle  1200 ), while I2V communication concept provides information about traffic further ahead. In at least one embodiment, CACC system may include either or both I2V and V2V information sources. In at least one embodiment, given information of vehicles ahead of vehicle  1200 , CACC system may be more reliable and it has potential to improve traffic flow smoothness and reduce congestion on road. 
     In at least one embodiment, FCW system is designed to alert driver to a hazard, so that driver may take corrective action. In at least one embodiment, FCW system uses a front-facing camera and/or RADAR sensor(s)  1260 , coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and/or vibrating component. In at least one embodiment, FCW system may provide a warning, such as in form of a sound, visual warning, vibration and/or a quick brake pulse. 
     In at least one embodiment, AEB system detects an impending forward collision with another vehicle or other object, and may automatically apply brakes if driver does not take corrective action within a specified time or distance parameter. In at least one embodiment, AEB system may use front-facing camera(s) and/or RADAR sensor(s)  1260 , coupled to a dedicated processor, DSP, FPGA, and/or ASIC. In at least one embodiment, when AEB system detects a hazard, AEB system typically first alerts driver to take corrective action to avoid collision and, if driver does not take corrective action, AEB system may automatically apply brakes in an effort to prevent, or at least mitigate, impact of predicted collision. In at least one embodiment, AEB system, may include techniques such as dynamic brake support and/or crash imminent braking. 
     In at least one embodiment, LDW system provides visual, audible, and/or tactile warnings, such as steering wheel or seat vibrations, to alert driver when vehicle  1200  crosses lane markings. In at least one embodiment, LDW system does not activate when driver indicates an intentional lane departure, by activating a turn signal. In at least one embodiment, LDW system may use front-side facing cameras, coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and/or vibrating component. In at least one embodiment, LKA system is a variation of LDW system. LKA system provides steering input or braking to correct vehicle  1200  if vehicle  1200  starts to exit lane. 
     In at least one embodiment, BSW system detects and warns driver of vehicles in an automobile&#39;s blind spot. In at least one embodiment, BSW system may provide a visual, audible, and/or tactile alert to indicate that merging or changing lanes is unsafe. In at least one embodiment, BSW system may provide an additional warning when driver uses a turn signal. In at least one embodiment, BSW system may use rear-side facing camera(s) and/or RADAR sensor(s)  1260 , coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and/or vibrating component. 
     In at least one embodiment, RCTW system may provide visual, audible, and/or tactile notification when an object is detected outside rear-camera range when vehicle  1200  is backing up. In at least one embodiment, RCTW system includes AEB system to ensure that vehicle brakes are applied to avoid a crash. In at least one embodiment, RCTW system may use one or more rear-facing RADAR sensor(s)  1260 , coupled to a dedicated processor, DSP, FPGA, and/or ASIC, that is electrically coupled to driver feedback, such as a display, speaker, and/or vibrating component. 
     In at least one embodiment, conventional ADAS systems may be prone to false positive results which may be annoying and distracting to a driver, but typically are not catastrophic, because conventional ADAS systems alert driver and allow driver to decide whether a safety condition truly exists and act accordingly. In at least one embodiment, vehicle  1200  itself decides, in case of conflicting results, whether to heed result from a primary computer or a secondary computer (e.g., first controller  1236  or second controller  1236 ). For example, in at least one embodiment, ADAS system  1238  may be a backup and/or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, backup computer rationality monitor may run a redundant diverse software on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, outputs from ADAS system  1238  may be provided to a supervisory MCU. In at least one embodiment, if outputs from primary computer and secondary computer conflict, supervisory MCU determines how to reconcile conflict to ensure safe operation. 
     In at least one embodiment, primary computer may be configured to provide supervisory MCU with a confidence score, indicating primary computer&#39;s confidence in chosen result. In at least one embodiment, if confidence score exceeds a threshold, supervisory MCU may follow primary computer&#39;s direction, regardless of whether secondary computer provides a conflicting or inconsistent result. In at least one embodiment, where confidence score does not meet threshold, and where primary and secondary computer indicate different results (e.g., a conflict), supervisory MCU may arbitrate between computers to determine appropriate outcome. 
     In at least one embodiment, supervisory MCU may be configured to run a neural network(s) that is trained and configured to determine, based at least in part on outputs from primary computer and secondary computer, conditions under which secondary computer provides false alarms. In at least one embodiment, neural network(s) in supervisory MCU may learn when secondary computer&#39;s output may be trusted, and when it cannot. For example, in at least one embodiment, when secondary computer is a RADAR-based FCW system, a neural network(s) in supervisory MCU may learn when FCW system is identifying metallic objects that are not, in fact, hazards, such as a drainage grate or manhole cover that triggers an alarm. In at least one embodiment, when secondary computer is a camera-based LDW system, a neural network in supervisory MCU may learn to override LDW when bicyclists or pedestrians are present and a lane departure is, in fact, safest maneuver. In at least one embodiment, supervisory MCU may include at least one of a DLA or GPU suitable for running neural network(s) with associated memory. In at least one embodiment, supervisory MCU may comprise and/or be included as a component of SoC(s)  1204 . 
     In at least one embodiment, ADAS system  1238  may include a secondary computer that performs ADAS functionality using traditional rules of computer vision. In at least one embodiment, secondary computer may use classic computer vision rules (if-then), and presence of a neural network(s) in supervisory MCU may improve reliability, safety and performance. For example, in at least one embodiment, diverse implementation and intentional non-identity makes overall system more fault-tolerant, especially to faults caused by software (or software-hardware interface) functionality. For example, in at least one embodiment, if there is a software bug or error in software running on primary computer, and non-identical software code running on secondary computer provides same overall result, then supervisory MCU may have greater confidence that overall result is correct, and bug in software or hardware on primary computer is not causing material error. 
     In at least one embodiment, output of ADAS system  1238  may be fed into primary computer&#39;s perception block and/or primary computer&#39;s dynamic driving task block. For example, in at least one embodiment, if ADAS system  1238  indicates a forward crash warning due to an object immediately ahead, perception block may use this information when identifying objects. In at least one embodiment, secondary computer may have its own neural network which is trained and thus reduces risk of false positives, as described herein. 
     In at least one embodiment, vehicle  1200  may further include infotainment SoC  1230  (e.g., an in-vehicle infotainment system (IVI)). Although illustrated and described as an SoC, infotainment system  1230 , in at least one embodiment, may not be an SoC, and may include, without limitation, two or more discrete components. In at least one embodiment, infotainment SoC  1230  may include, without limitation, a combination of hardware and software that may be used to provide audio (e.g., music, a personal digital assistant, navigational instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and/or information services (e.g., navigation systems, rear-parking assistance, a radio data system, vehicle related information such as fuel level, total distance covered, brake fuel level, oil level, door open/close, air filter information, etc.) to vehicle  1200 . For example, infotainment SoC  1230  could include radios, disk players, navigation systems, video players, USB and Bluetooth connectivity, carputers, in-car entertainment, WiFi, steering wheel audio controls, hands free voice control, a heads-up display (“HUD”), HMI display  1234 , a telematics device, a control panel (e.g., for controlling and/or interacting with various components, features, and/or systems), and/or other components. In at least one embodiment, infotainment SoC  1230  may further be used to provide information (e.g., visual and/or audible) to user(s) of vehicle, such as information from ADAS system  1238 , autonomous driving information such as planned vehicle maneuvers, trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and/or other information. 
     In at least one embodiment, infotainment SoC  1230  may include any amount and type of GPU functionality. In at least one embodiment, infotainment SoC  1230  may communicate over bus  1202  (e.g., CAN bus, Ethernet, etc.) with other devices, systems, and/or components of vehicle  1200 . In at least one embodiment, infotainment SoC  1230  may be coupled to a supervisory MCU such that GPU of infotainment system may perform some self-driving functions in event that primary controller(s)  1236  (e.g., primary and/or backup computers of vehicle  1200 ) fail. In at least one embodiment, infotainment SoC  1230  may put vehicle  1200  into a chauffeur to safe stop mode, as described herein. 
     In at least one embodiment, vehicle  1200  may further include instrument cluster  1232  (e.g., a digital dash, an electronic instrument cluster, a digital instrument panel, etc.). Instrument cluster  1232  may include, without limitation, a controller and/or supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, instrument cluster  1232  may include, without limitation, any number and combination of a set of instrumentation such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicators, gearshift position indicator, seat belt warning light(s), parking-brake warning light(s), engine-malfunction light(s), supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and/or shared among infotainment SoC  1230  and instrument cluster  1232 . In at least one embodiment, instrument cluster  1232  may be included as part of infotainment SoC  1230 , or vice versa. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 12C  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 12C  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 12D  is a diagram of a system  1276  for communication between cloud-based server(s) and autonomous vehicle  1200  of  FIG. 12A , according to at least one embodiment. In at least one embodiment, system  1276  may include, without limitation, server(s)  1278 , network(s)  1290 , and any number and type of vehicles, including vehicle  1200 . server(s)  1278  may include, without limitation, a plurality of GPUs  1284 (A)- 1284 (H) (collectively referred to herein as GPUs  1284 ), PCIe switches  1282 (A)- 1282 (H) (collectively referred to herein as PCIe switches  1282 ), and/or CPUs  1280 (A)- 1280 (B) (collectively referred to herein as CPUs  1280 ). GPUs  1284 , CPUs  1280 , and PCIe switches  1282  may be interconnected with high-speed interconnects such as, for example and without limitation, NVLink interfaces  1288  developed by NVIDIA and/or PCIe connections  1286 . In at least one embodiment, GPUs  1284  are connected via an NVLink and/or NVSwitch SoC and GPUs  1284  and PCIe switches  1282  are connected via PCIe interconnects. In at least one embodiment, although eight GPUs  1284 , two CPUs  1280 , and four PCIe switches  1282  are illustrated, this is not intended to be limiting. In at least one embodiment, each of server(s)  1278  may include, without limitation, any number of GPUs  1284 , CPUs  1280 , and/or PCIe switches  1282 , in any combination. For example, in at least one embodiment, server(s)  1278  could each include eight, sixteen, thirty-two, and/or more GPUs  1284 . 
     In at least one embodiment, server(s)  1278  may receive, over network(s)  1290  and from vehicles, image data representative of images showing unexpected or changed road conditions, such as recently commenced road-work. In at least one embodiment, server(s)  1278  may transmit, over network(s)  1290  and to vehicles, neural networks  1292 , updated neural networks  1292 , and/or map information  1294 , including, without limitation, information regarding traffic and road conditions. In at least one embodiment, updates to map information  1294  may include, without limitation, updates for HD map  1222 , such as information regarding construction sites, potholes, detours, flooding, and/or other obstructions. In at least one embodiment, neural networks  1292 , updated neural networks  1292 , and/or map information  1294  may have resulted from new training and/or experiences represented in data received from any number of vehicles in environment, and/or based at least in part on training performed at a data center (e.g., using server(s)  1278  and/or other servers). 
     In at least one embodiment, server(s)  1278  may be used to train machine learning models (e.g., neural networks) based at least in part on training data. Training data may be generated by vehicles, and/or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is tagged (e.g., where associated neural network benefits from supervised learning) and/or undergoes other pre-processing. In at least one embodiment, any amount of training data is not tagged and/or pre-processed (e.g., where associated neural network does not require supervised learning). In at least one embodiment, once machine learning models are trained, machine learning models may be used by vehicles (e.g., transmitted to vehicles over network(s)  1290 , and/or machine learning models may be used by server(s)  1278  to remotely monitor vehicles. 
     In at least one embodiment, server(s)  1278  may receive data from vehicles and apply data to up-to-date real-time neural networks for real-time intelligent inferencing. In at least one embodiment, server(s)  1278  may include deep-learning supercomputers and/or dedicated AI computers powered by GPU(s)  1284 , such as a DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, server(s)  1278  may include deep learning infrastructure that use CPU-powered data centers. 
     In at least one embodiment, deep-learning infrastructure of server(s)  1278  may be capable of fast, real-time inferencing, and may use that capability to evaluate and verify health of processors, software, and/or associated hardware in vehicle  1200 . For example, in at least one embodiment, deep-learning infrastructure may receive periodic updates from vehicle  1200 , such as a sequence of images and/or objects that vehicle  1200  has located in that sequence of images (e.g., via computer vision and/or other machine learning object classification techniques). In at least one embodiment, deep-learning infrastructure may run its own neural network to identify objects and compare them with objects identified by vehicle  1200  and, if results do not match and deep-learning infrastructure concludes that AI in vehicle  1200  is malfunctioning, then server(s)  1278  may transmit a signal to vehicle  1200  instructing a fail-safe computer of vehicle  1200  to assume control, notify passengers, and complete a safe parking maneuver. 
     In at least one embodiment, server(s)  1278  may include GPU(s)  1284  and one or more programmable inference accelerators (e.g., NVIDIA&#39;s TensorRT 3). In at least one embodiment, combination of GPU-powered servers and inference acceleration may make real-time responsiveness possible. In at least one embodiment, such as where performance is less critical, servers powered by CPUs, FPGAs, and other processors may be used for inferencing. In at least one embodiment, hardware structure(s)  915  are used to perform one or more embodiments. Details regarding hardware structure(x)  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . 
     Computer Systems 
       FIG. 13  is a block diagram illustrating an exemplary computer system, which may be a system with interconnected devices and components, a system-on-a-chip (SOC) or some combination thereof  1300  formed with a processor that may include execution units to execute an instruction, according to at least one embodiment. In at least one embodiment, computer system  1300  may include, without limitation, a component, such as a processor  1302  to employ execution units including logic to perform algorithms for process data, in accordance with present disclosure, such as in embodiment described herein. In at least one embodiment, computer system  1300  may include processors, such as PENTIUM® Processor family, Xeon™ Itanium®, XScale™ and/or StrongARM™, Intel® Core™, or Intel® Nervana™ microprocessors available from Intel Corporation of Santa Clara, Calif., although other systems (including PCs having other microprocessors, engineering workstations, set-top boxes and like) may also be used. In at least one embodiment, computer system  1300  may execute a version of WINDOWS&#39; operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (UNIX and Linux for example), embedded software, and/or graphical user interfaces, may also be used. 
     Embodiments may be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (“DSP”), system on a chip, network computers (“NetPCs”), set-top boxes, network hubs, wide area network (“WAN”) switches, or any other system that may perform one or more instructions in accordance with at least one embodiment. 
     In at least one embodiment, computer system  1300  may include, without limitation, processor  1302  that may include, without limitation, one or more execution units  1308  to perform machine learning model training and/or inferencing according to techniques described herein. In at least one embodiment, system  13  is a single processor desktop or server system, but in another embodiment system  13  may be a multiprocessor system. In at least one embodiment, processor  1302  may include, without limitation, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, for example. In at least one embodiment, processor  1302  may be coupled to a processor bus  1310  that may transmit data signals between processor  1302  and other components in computer system  1300 . 
     In at least one embodiment, processor  1302  may include, without limitation, a Level 1 (“L1”) internal cache memory (“cache”)  1304 . In at least one embodiment, processor  1302  may have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may reside external to processor  1302 . Other embodiments may also include a combination of both internal and external caches depending on particular implementation and needs. In at least one embodiment, register file  1306  may store different types of data in various registers including, without limitation, integer registers, floating point registers, status registers, and instruction pointer register. 
     In at least one embodiment, execution unit  1308 , including, without limitation, logic to perform integer and floating point operations, also resides in processor  1302 . Processor  1302  may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macro instructions. In at least one embodiment, execution unit  1308  may include logic to handle a packed instruction set  1309 . In at least one embodiment, by including packed instruction set  1309  in instruction set of a general-purpose processor  1302 , along with associated circuitry to execute instructions, operations used by many multimedia applications may be performed using packed data in a general-purpose processor  1302 . In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using full width of a processor&#39;s data bus for performing operations on packed data, which may eliminate need to transfer smaller units of data across processor&#39;s data bus to perform one or more operations one data element at a time. 
     In at least one embodiment, execution unit  1308  may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system  1300  may include, without limitation, a memory  1320 . In at least one embodiment, memory  1320  may be implemented as a Dynamic Random Access Memory (“DRAM”) device, a Static Random Access Memory (“SRAM”) device, flash memory device, or other memory device. Memory  1320  may store instruction(s)  1319  and/or data  1321  represented by data signals that may be executed by processor  1302 . 
     In at least one embodiment, system logic chip may be coupled to processor bus  1310  and memory  1320 . In at least one embodiment, system logic chip may include, without limitation, a memory controller hub (“MCH”)  1316 , and processor  1302  may communicate with MCH  1316  via processor bus  1310 . In at least one embodiment, MCH  1316  may provide a high bandwidth memory path  1318  to memory  1320  for instruction and data storage and for storage of graphics commands, data and textures. In at least one embodiment, MCH  1316  may direct data signals between processor  1302 , memory  1320 , and other components in computer system  1300  and to bridge data signals between processor bus  1310 , memory  1320 , and a system I/O  1322 . In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH  1316  may be coupled to memory  1320  through a high bandwidth memory path  1318  and graphics/video card  1312  may be coupled to MCH  1316  through an Accelerated Graphics Port (“AGP”) interconnect  1314 . 
     In at least one embodiment, computer system  1300  may use system I/O  1322  that is a proprietary hub interface bus to couple MCH  1316  to I/O controller hub (“ICH”)  1330 . In at least one embodiment, ICH  1330  may provide direct connections to some I/O devices via a local I/O bus. In at least one embodiment, local I/O bus may include, without limitation, a high-speed I/O bus for connecting peripherals to memory  1320 , chipset, and processor  1302 . Examples may include, without limitation, an audio controller  1329 , a firmware hub (“flash BIOS”)  1328 , a wireless transceiver  1326 , a data storage  1324 , a legacy I/O controller  1323  containing user input and keyboard interfaces, a serial expansion port  1327 , such as Universal Serial Bus (“USB”), and a network controller  1334 . Data storage  1324  may comprise a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device. 
     In at least one embodiment,  FIG. 13  illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments,  FIG. 13  may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in FIG. cc may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of system  1300  are interconnected using compute express link (CXL) interconnects. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 13  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 13  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 14  is a block diagram illustrating an electronic device  1400  for utilizing a processor  1410 , according to at least one embodiment. In at least one embodiment, electronic device  1400  may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device. 
     In at least one embodiment, system  1400  may include, without limitation, processor  1410  communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor  1410  coupled using a bus or interface, such as a 1° C. bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advance Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3), or a Universal Asynchronous Receiver/Transmitter (“UART”) bus. In at least one embodiment,  FIG. 14  illustrates a system, which includes interconnected hardware devices or “chips”, whereas in other embodiments,  FIG. 14  may illustrate an exemplary System on a Chip (“SoC”). In at least one embodiment, devices illustrated in  FIG. 14  may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe) or some combination thereof. In at least one embodiment, one or more components of  FIG. 14  are interconnected using compute express link (CXL) interconnects. 
     In at least one embodiment,  FIG. 14  may include a display  1424 , a touch screen  1425 , a touch pad  1430 , a Near Field Communications unit (“NFC”)  1445 , a sensor hub  1440 , a thermal sensor  1446 , an Express Chipset (“EC”)  1435 , a Trusted Platform Module (“TPM”)  1438 , BIOS/firmware/flash memory (“BIOS, FW Flash”)  1422 , a DSP  1460 , a drive “SSD or HDD”)  1420  such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”), a wireless local area network unit (“WLAN”)  1450 , a Bluetooth unit  1452 , a Wireless Wide Area Network unit (“WWAN”)  1456 , a Global Positioning System (GPS)  1455 , a camera (“USB 3.0 camera”)  1454  such as a USB 3.0 camera, or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”)  1415  implemented in, for example, LPDDR3 standard. These components may each be implemented in any suitable manner. 
     In at least one embodiment, other components may be communicatively coupled to processor  1410  through components discussed above. In at least one embodiment, an accelerometer  1441 , Ambient Light Sensor (“ALS”)  1442 , compass  1443 , and a gyroscope  1444  may be communicatively coupled to sensor hub  1440 . In at least one embodiment, thermal sensor  1439 , a fan  1437 , a keyboard  1446 , and a touch pad  1430  may be communicatively coupled to EC  1435 . In at least one embodiment, speaker  1463 , a headphones  1464 , and a microphone (“mic”)  1465  may be communicatively coupled to an audio unit (“audio codec and class d amp”)  1464 , which may in turn be communicatively coupled to DSP  1460 . In at least one embodiment, audio unit  1464  may include, for example and without limitation, an audio coder/decoder (“codec”) and a class D amplifier. In at least one embodiment, SIM card (“SIM”)  1457  may be communicatively coupled to WWAN unit  1456 . In at least one embodiment, components such as WLAN unit  1450  and Bluetooth unit  1452 , as well as WWAN unit  1456  may be implemented in a Next Generation Form Factor (“NGFF”). 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 14  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 14  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 15  illustrates a computer system  1500 , according to at least one embodiment. In at least one embodiment, computer system  1500  is configured to implement various processes and methods described throughout this disclosure. 
     In at least one embodiment, computer system  1500  comprises, without limitation, at least one central processing unit (“CPU”)  1502  that is connected to a communication bus  1510  implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), peripheral component interconnect express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol(s). In at least one embodiment, computer system  1500  includes, without limitation, a main memory  1504  and control logic (e.g., implemented as hardware, software, or a combination thereof) and data are stored in main memory  1504  which may take form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”)  1522  provides an interface to other computing devices and networks for receiving data from and transmitting data to other systems from computer system  1500 . 
     In at least one embodiment, computer system  1500 , in at least one embodiment, includes, without limitation, input devices  1508 , parallel processing system  1512 , and display devices  1506  which can be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”), plasma display, or other suitable display technologies. In at least one embodiment, user input is received from input devices  1508  such as keyboard, mouse, touchpad, microphone, and more. In at least one embodiment, each of foregoing modules can be situated on a single semiconductor platform to form a processing system. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 15  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 15  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 16  illustrates a computer system  1600 , according to at least one embodiment. In at least one embodiment, computer system  1600  includes, without limitation, a computer  1610  and a USB stick  1620 . In at least one embodiment, computer  1610  may include, without limitation, any number and type of processor(s) (not shown) and a memory (not shown). In at least one embodiment, computer  1610  includes, without limitation, a server, a cloud instance, a laptop, and a desktop computer. 
     In at least one embodiment, USB stick  1620  includes, without limitation, a processing unit  1630 , a USB interface  1640 , and USB interface logic  1650 . In at least one embodiment, processing unit  1630  may be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, processing unit  1630  may include, without limitation, any number and type of processing cores (not shown). In at least one embodiment, processing core  1630  comprises an application specific integrated circuit (“ASIC”) that is optimized to perform any amount and type of operations associated with machine learning. For instance, in at least one embodiment, processing core  1630  is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, processing core  1630  is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations. 
     In at least one embodiment, USB interface  1640  may be any type of USB connector or USB socket. For instance, in at least one embodiment, USB interface  1640  is a USB 3.0 Type-C socket for data and power. In at least one embodiment, USB interface  1640  is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic  1650  may include any amount and type of logic that enables processing unit  1630  to interface with or devices (e.g., computer  1610 ) via USB connector  1640 . 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 16  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 16  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 17A  illustrates an exemplary architecture in which a plurality of GPUs  1710 - 1713  is communicatively coupled to a plurality of multi-core processors  1705 - 1706  over high-speed links  1740 - 1743  (e.g., buses, point-to-point interconnects, etc.). In one embodiment, high-speed links  1740 - 1743  support a communication throughput of 4 GB/s, 30 GB/s, 80 GB/s or higher. Various interconnect protocols may be used including, but not limited to, PCIe 4.0 or 5.0 and NVLink 2.0. 
     In addition, and in one embodiment, two or more of GPUs  1710 - 1713  are interconnected over high-speed links  1729 - 1730 , which may be implemented using same or different protocols/links than those used for high-speed links  1740 - 1743 . Similarly, two or more of multi-core processors  1705 - 1706  may be connected over high speed link  1728  which may be symmetric multi-processor (SMP) buses operating at 20 GB/s, 30 GB/s, 120 GB/s or higher. Alternatively, all communication between various system components shown in  FIG. 17A  may be accomplished using same protocols/links (e.g., over a common interconnection fabric). 
     In one embodiment, each multi-core processor  1705 - 1706  is communicatively coupled to a processor memory  1701 - 1702 , via memory interconnects  1726 - 1727 , respectively, and each GPU  1710 - 1713  is communicatively coupled to GPU memory  1720 - 1723  over GPU memory interconnects  1750 - 1753 , respectively. Memory interconnects  1726 - 1727  and  1750 - 1753  may utilize same or different memory access technologies. By way of example, and not limitation, processor memories  1701 - 1702  and GPU memories  1720 - 1723  may be volatile memories such as dynamic random access memories (DRAMs) (including stacked DRAMs), Graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or High Bandwidth Memory (HBM) and/or may be non-volatile memories such as 3D XPoint or Nano-Ram. In one embodiment, some portion of processor memories  1701 - 1702  may be volatile memory and another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy). 
     As described herein, although various processors  1705 - 1706  and GPUs  1710 - 1713  may be physically coupled to a particular memory  1701 - 1702 ,  1720 - 1723 , respectively, a unified memory architecture may be implemented in which a same virtual system address space (also referred to as “effective address” space) is distributed among various physical memories. For example, processor memories  1701 - 1702  may each comprise 64 GB of system memory address space and GPU memories  1720 - 1723  may each comprise 32 GB of system memory address space (resulting in a total of 256 GB addressable memory in this example). 
       FIG. 17B  illustrates additional details for an interconnection between a multi-core processor  1707  and a graphics acceleration module  1746  in accordance with one exemplary embodiment. Graphics acceleration module  1746  may include one or more GPU chips integrated on a line card which is coupled to processor  1707  via high-speed link  1740 . Alternatively, graphics acceleration module  1746  may be integrated on a same package or chip as processor  1707 . 
     In at least one embodiment, illustrated processor  1707  includes a plurality of cores  1760 A- 1760 D, each with a translation lookaside buffer  1761 A- 1761 D and one or more caches  1762 A- 1762 D. In at least one embodiment, cores  1760 A- 1760 D may include various other components for executing instructions and processing data which are not illustrated. Caches  1762 A- 1762 D may comprise level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches  1756  may be included in caches  1762 A- 1762 D and shared by sets of cores  1760 A- 1760 D. For example, one embodiment of processor  1707  includes 24 cores, each with its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one or more L2 and L3 caches are shared by two adjacent cores. Processor  1707  and graphics acceleration module  1746  connect with system memory  1714 , which may include processor memories  1701 - 1702  of  FIG. 17A . 
     Coherency is maintained for data and instructions stored in various caches  1762 A- 1762 D,  1756  and system memory  1714  via inter-core communication over a coherence bus  1764 . For example, each cache may have cache coherency logic/circuitry associated therewith to communicate to over coherence bus  1764  in response to detected reads or writes to particular cache lines. In one implementation, a cache snooping protocol is implemented over coherence bus  1764  to snoop cache accesses. 
     In one embodiment, a proxy circuit  1725  communicatively couples graphics acceleration module  1746  to coherence bus  1764 , allowing graphics acceleration module  1746  to participate in a cache coherence protocol as a peer of cores  1760 A- 1760 D. In particular, an interface  1735  provides connectivity to proxy circuit  1725  over high-speed link  1740  (e.g., a PCIe bus, NVLink, etc.) and an interface  1737  connects graphics acceleration module  1746  to link  1740 . 
     In one implementation, an accelerator integration circuit  1736  provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines  1731 ,  1732 , N of graphics acceleration module  1746 . Graphics processing engines  1731 ,  1732 , N may each comprise a separate graphics processing unit (GPU). Alternatively, graphics processing engines  1731 ,  1732 , N may comprise different types of graphics processing engines within a GPU such as graphics execution units, media processing engines (e.g., video encoders/decoders), samplers, and blit engines. In at least one embodiment, graphics acceleration module  1746  may be a GPU with a plurality of graphics processing engines  1731 - 1732 , N or graphics processing engines  1731 - 1732 , N may be individual GPUs integrated on a common package, line card, or chip. 
     In one embodiment, accelerator integration circuit  1736  includes a memory management unit (MMU)  1739  for performing various memory management functions such as virtual-to-physical memory translations (also referred to as effective-to-real memory translations) and memory access protocols for accessing system memory  1714 . MMU  1739  may also include a translation lookaside buffer (TLB) (not shown) for caching virtual/effective to physical/real address translations. In one implementation, a cache  1738  stores commands and data for efficient access by graphics processing engines  1731 - 1732 , N. In one embodiment, data stored in cache  1738  and graphics memories  1733 - 1734 , M is kept coherent with core caches  1762 A- 1762 D,  1756  and system memory  1714 . As mentioned, this may be accomplished via proxy circuit  1725  on behalf of cache  1738  and memories  1733 - 1734 , M (e.g., sending updates to cache  1738  related to modifications/accesses of cache lines on processor caches  1762 A- 1762 D,  1756  and receiving updates from cache  1738 ). 
     A set of registers  1745  store context data for threads executed by graphics processing engines  1731 - 1732 , N and a context management circuit  1748  manages thread contexts. For example, context management circuit  1748  may perform save and restore operations to save and restore contexts of various threads during contexts switches (e.g., where a first thread is saved and a second thread is stored so that a second thread can be execute by a graphics processing engine). For example, on a context switch, context management circuit  1748  may store current register values to a designated region in memory (e.g., identified by a context pointer). It may then restore register values when returning to a context. In one embodiment, an interrupt management circuit  1747  receives and processes interrupts received from system devices. 
     In one implementation, virtual/effective addresses from a graphics processing engine  1731  are translated to real/physical addresses in system memory  1714  by MMU  1739 . One embodiment of accelerator integration circuit  1736  supports multiple (e.g., 4, 8, 16) graphics accelerator modules  1746  and/or other accelerator devices. Graphics accelerator module  1746  may be dedicated to a single application executed on processor  1707  or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which resources of graphics processing engines  1731 - 1732 , N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into “slices” which are allocated to different VMs and/or applications based on processing requirements and priorities associated with VMs and/or applications. 
     In at least one embodiment, accelerator integration circuit  1736  performs as a bridge to a system for graphics acceleration module  1746  and provides address translation and system memory cache services. In addition, accelerator integration circuit  1736  may provide virtualization facilities for a host processor to manage virtualization of graphics processing engines  1731 - 1732 , interrupts, and memory management. 
     Because hardware resources of graphics processing engines  1731 - 1732 , N are mapped explicitly to a real address space seen by host processor  1707 , any host processor can address these resources directly using an effective address value. One function of accelerator integration circuit  1736 , in one embodiment, is physical separation of graphics processing engines  1731 - 1732 , N so that they appear to a system as independent units. 
     In at least one embodiment, one or more graphics memories  1733 - 1734 , M are coupled to each of graphics processing engines  1731 - 1732 , N, respectively. Graphics memories  1733 - 1734 , M store instructions and data being processed by each of graphics processing engines  1731 - 1732 , N. Graphics memories  1733 - 1734 , M may be volatile memories such as DRAMs (including stacked DRAMs), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and/or may be non-volatile memories such as 3D XPoint or Nano-Ram. 
     In one embodiment, to reduce data traffic over link  1740 , biasing techniques are used to ensure that data stored in graphics memories  1733 - 1734 , M is data which will be used most frequently by graphics processing engines  1731 - 1732 , N and preferably not used by cores  1760 A- 1760 D (at least not frequently). Similarly, a biasing mechanism attempts to keep data needed by cores (and preferably not graphics processing engines  1731 - 1732 , N) within caches  1762 A- 1762 D,  1756  of cores and system memory  1714 . 
       FIG. 17C  illustrates another exemplary embodiment in which accelerator integration circuit  1736  is integrated within processor  1707 . In this embodiment, graphics processing engines  1731 - 1732 , N communicate directly over high-speed link  1740  to accelerator integration circuit  1736  via interface  1737  and interface  1735  (which, again, may be utilize any form of bus or interface protocol). Accelerator integration circuit  1736  may perform same operations as those described with respect to  FIG. 17B , but potentially at a higher throughput given its close proximity to coherence bus  1764  and caches  1762 A- 1762 D,  1756 . One embodiment supports different programming models including a dedicated-process programming model (no graphics acceleration module virtualization) and shared programming models (with virtualization), which may include programming models which are controlled by accelerator integration circuit  1736  and programming models which are controlled by graphics acceleration module  1746 . 
     In at least one embodiment, graphics processing engines  1731 - 1732 , N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines  1731 - 1732 , N, providing virtualization within a VM/partition. 
     In at least one embodiment, graphics processing engines  1731 - 1732 , N, may be shared by multiple VM/application partitions. In at least one embodiment, shared models may use a system hypervisor to virtualize graphics processing engines  1731 - 1732 , N to allow access by each operating system. For single-partition systems without a hypervisor, graphics processing engines  1731 - 1732 , N are owned by an operating system. In at least one embodiment, an operating system can virtualize graphics processing engines  1731 - 1732 , N to provide access to each process or application. 
     In at least one embodiment, graphics acceleration module  1746  or an individual graphics processing engine  1731 - 1732 , N selects a process element using a process handle. In one embodiment, process elements are stored in system memory  1714  and are addressable using an effective address to real address translation techniques described herein. In at least one embodiment, a process handle may be an implementation-specific value provided to a host process when registering its context with graphics processing engine  1731 - 1732 , N (that is, calling system software to add a process element to a process element linked list). In at least one embodiment, a lower 16-bits of a process handle may be an offset of the process element within a process element linked list. 
       FIG. 17D  illustrates an exemplary accelerator integration slice  1790 . As used herein, a “slice” comprises a specified portion of processing resources of accelerator integration circuit  1736 . Application effective address space  1782  within system memory  1714  stores process elements  1783 . In one embodiment, process elements  1783  are stored in response to GPU invocations  1781  from applications  1780  executed on processor  1707 . A process element  1783  contains process state for corresponding application  1780 . A work descriptor (WD)  1784  contained in process element  1783  can be a single job requested by an application or may contain a pointer to a queue of jobs. In at least one embodiment, WD  1784  is a pointer to a job request queue in an application&#39;s address space  1782 . 
     Graphics acceleration module  1746  and/or individual graphics processing engines  1731 - 1732 , N can be shared by all or a subset of processes in a system. In at least one embodiment, an infrastructure for setting up process state and sending a WD  1784  to a graphics acceleration module  1746  to start a job in a virtualized environment may be included. 
     In at least one embodiment, a dedicated-process programming model is implementation-specific. In this model, a single process owns graphics acceleration module  1746  or an individual graphics processing engine  1731 . Because graphics acceleration module  1746  is owned by a single process, a hypervisor initializes accelerator integration circuit  1736  for an owning partition and an operating system initializes accelerator integration circuit  1736  for an owning process when graphics acceleration module  1746  is assigned. 
     In operation, a WD fetch unit  1791  in accelerator integration slice  1790  fetches next WD  1784  which includes an indication of work to be done by one or more graphics processing engines of graphics acceleration module  1746 . Data from WD  1784  may be stored in registers  1745  and used by MMU  1739 , interrupt management circuit  1747  and/or context management circuit  1748  as illustrated. For example, one embodiment of MMU  1739  includes segment/page walk circuitry for accessing segment/page tables  1786  within OS virtual address space  1785 . Interrupt management circuit  1747  may process interrupt events  1792  received from graphics acceleration module  1746 . When performing graphics operations, an effective address  1793  generated by a graphics processing engine  1731 - 1732 , N is translated to a real address by MMU  1739 . 
     In one embodiment, a same set of registers  1745  are duplicated for each graphics processing engine  1731 - 1732 , N and/or graphics acceleration module  1746  and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in an accelerator integration slice  1790 . Exemplary registers that may be initialized by a hypervisor are shown in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Hypervisor Initialized Registers 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 1 
                 Slice Control Register 
               
               
                 2 
                 Real Address (RA) Scheduled Processes Area Pointer 
               
               
                 3 
                 Authority Mask Override Register 
               
               
                 4 
                 Interrupt Vector Table Entry Offset 
               
               
                 5 
                 Interrupt Vector Table Entry Limit 
               
               
                 6 
                 State Register 
               
               
                 7 
                 Logical Partition ID 
               
               
                 8 
                 Real address (RA) Hypervisor Accelerator Utilization Record Pointer 
               
               
                 9 
                 Storage Description Register 
               
               
                   
               
            
           
         
       
     
     Exemplary registers that may be initialized by an operating system are shown in Table 2. 
     Table 2—Operating System Initialized Registers 
     
         
         1 Process and Thread Identification 
         2 Effective Address (EA) Context Save/Restore Pointer 
         3 Virtual Address (VA) Accelerator Utilization Record Pointer 
         4 Virtual Address (VA) Storage Segment Table Pointer 
         5 Authority Mask 
         6 Work descriptor 
       
    
     In one embodiment, each WD  1784  is specific to a particular graphics acceleration module  1746  and/or graphics processing engines  1731 - 1732 , N. It contains all information required by a graphics processing engine  1731 - 1732 , N to do work or it can be a pointer to a memory location where an application has set up a command queue of work to be completed. 
       FIG. 17E  illustrates additional details for one exemplary embodiment of a shared model. This embodiment includes a hypervisor real address space  1798  in which a process element list  1799  is stored. Hypervisor real address space  1798  is accessible via a hypervisor  1796  which virtualizes graphics acceleration module engines for operating system  1795 . 
     In at least one embodiment, shared programming models allow for all or a subset of processes from all or a subset of partitions in a system to use a graphics acceleration module  1746 . There are two programming models where graphics acceleration module  1746  is shared by multiple processes and partitions: time-sliced shared and graphics directed shared. 
     In this model, system hypervisor  1796  owns graphics acceleration module  1746  and makes its function available to all operating systems  1795 . For a graphics acceleration module  1746  to support virtualization by system hypervisor  1796 , graphics acceleration module  1746  may adhere to the following: 1) An application&#39;s job request must be autonomous (that is, state does not need to be maintained between jobs), or graphics acceleration module  1746  must provide a context save and restore mechanism. 2) An application&#39;s job request is guaranteed by graphics acceleration module  1746  to complete in a specified amount of time, including any translation faults, or graphics acceleration module  1746  provides an ability to preempt processing of a job. 3) Graphics acceleration module  1746  must be guaranteed fairness between processes when operating in a directed shared programming model. 
     In at least one embodiment, application  1780  is required to make an operating system  1795  system call with a graphics acceleration module  1746  type, a work descriptor (WD), an authority mask register (AMR) value, and a context save/restore area pointer (CSRP). In at least one embodiment, graphics acceleration module  1746  type describes a targeted acceleration function for a system call. In at least one embodiment, graphics acceleration module  1746  type may be a system-specific value. In at least one embodiment, WD is formatted specifically for graphics acceleration module  1746  and can be in a form of a graphics acceleration module  1746  command, an effective address pointer to a user-defined structure, an effective address pointer to a queue of commands, or any other data structure to describe work to be done by graphics acceleration module  1746 . In one embodiment, an AMR value is an AMR state to use for a current process. In at least one embodiment, a value passed to an operating system is similar to an application setting an AMR. If accelerator integration circuit  1736  and graphics acceleration module  1746  implementations do not support a User Authority Mask Override Register (UAMOR), an operating system may apply a current UAMOR value to an AMR value before passing an AMR in a hypervisor call. Hypervisor  1796  may optionally apply a current Authority Mask Override Register (AMOR) value before placing an AMR into process element  1783 . In at least one embodiment, CSRP is one of registers  1745  containing an effective address of an area in an application&#39;s address space  1782  for graphics acceleration module  1746  to save and restore context state. This pointer is optional if no state is required to be saved between jobs or when a job is preempted. In at least one embodiment, context save/restore area may be pinned system memory. 
     Upon receiving a system call, operating system  1795  may verify that application  1780  has registered and been given authority to use graphics acceleration module  1746 . Operating system  1795  then calls hypervisor  1796  with information shown in Table 3. 
     
       
         
           
               
             
               
                 TABLE 3 
               
               
                   
               
               
                 OS to Hypervisor Call Parameters 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 1 
                 A work descriptor (WD) 
               
               
                 2 
                 An Authority Mask Register (AMR) value (potentially masked) 
               
               
                 3 
                 An effective address (EA) Context Save/Restore Area Pointer 
               
               
                   
                 (CSRP) 
               
               
                 4 
                 A process ID (PID) and optional thread ID (TID) 
               
               
                 5 
                 A virtual address (VA) accelerator utilization record pointer (AURP) 
               
               
                 6 
                 Virtual address of storage segment table pointer (SSTP) 
               
               
                 7 
                 A logical interrupt service number (LISN) 
               
               
                   
               
            
           
         
       
     
     Upon receiving a hypervisor call, hypervisor  1796  verifies that operating system  1795  has registered and been given authority to use graphics acceleration module  1746 . Hypervisor  1796  then puts process element  1783  into a process element linked list for a corresponding graphics acceleration module  1746  type. A process element may include information shown in Table 4. 
     
       
         
           
               
             
               
                 TABLE 4 
               
               
                   
               
               
                 Process Element Information 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 1 
                 A work descriptor (WD) 
               
               
                 2 
                 An Authority Mask Register (AMR) value (potentially masked). 
               
               
                 3 
                 An effective address (EA) Context Save/Restore Area Pointer 
               
               
                   
                 (CSRP) 
               
               
                 4 
                 A process ID (PID) and optional thread ID (TID) 
               
               
                 5 
                 A virtual address (VA) accelerator utilization record pointer (AURP) 
               
               
                 6 
                 Virtual address of storage segment table pointer (SSTP) 
               
               
                 7 
                 A logical interrupt service number (LISN) 
               
               
                 8 
                 Interrupt vector table, derived from hypervisor call parameters 
               
               
                 9 
                 A state register (SR) value 
               
               
                 10 
                 A logical partition ID (LPID) 
               
               
                 11 
                 A real address (RA) hypervisor accelerator utilization record pointer 
               
               
                 12 
                 Storage Descriptor Register (SDR) 
               
               
                   
               
            
           
         
       
     
     In at least one embodiment, hypervisor initializes a plurality of accelerator integration slice  1790  registers  1745 . 
     As illustrated in  FIG. 17F , in at least one embodiment, a unified memory is used, addressable via a common virtual memory address space used to access physical processor memories  1701 - 1702  and GPU memories  1720 - 1723 . In this implementation, operations executed on GPUs  1710 - 1713  utilize a same virtual/effective memory address space to access processor memories  1701 - 1702  and vice versa, thereby simplifying programmability. In one embodiment, a first portion of a virtual/effective address space is allocated to processor memory  1701 , a second portion to second processor memory  1702 , a third portion to GPU memory  1720 , and so on. In at least one embodiment, an entire virtual/effective memory space (sometimes referred to as an effective address space) is thereby distributed across each of processor memories  1701 - 1702  and GPU memories  1720 - 1723 , allowing any processor or GPU to access any physical memory with a virtual address mapped to that memory. 
     In one embodiment, bias/coherence management circuitry  1794 A- 1794 E within one or more of MMUs  1739 A- 1739 E ensures cache coherence between caches of one or more host processors (e.g.,  1705 ) and GPUs  1710 - 1713  and implements biasing techniques indicating physical memories in which certain types of data should be stored. While multiple instances of bias/coherence management circuitry  1794 A- 1794 E are illustrated in  FIG. 17F , bias/coherence circuitry may be implemented within an MMU of one or more host processors  1705  and/or within accelerator integration circuit  1736 . 
     One embodiment allows GPU-attached memory  1720 - 1723  to be mapped as part of system memory, and accessed using shared virtual memory (SVM) technology, but without suffering performance drawbacks associated with full system cache coherence. In at least one embodiment, an ability for GPU-attached memory  1720 - 1723  to be accessed as system memory without onerous cache coherence overhead provides a beneficial operating environment for GPU offload. This arrangement allows host processor  1705  software to setup operands and access computation results, without overhead of tradition I/O DMA data copies. Such traditional copies involve driver calls, interrupts and memory mapped I/O (MMIO) accesses that are all inefficient relative to simple memory accesses. In at least one embodiment, an ability to access GPU attached memory  1720 - 1723  without cache coherence overheads can be critical to execution time of an offloaded computation. In cases with substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce an effective write bandwidth seen by a GPU  1710 - 1713 . In at least one embodiment, efficiency of operand setup, efficiency of results access, and efficiency of GPU computation may play a role in determining effectiveness of a GPU offload. 
     In at least one embodiment, selection of GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page-granular structure (i.e., controlled at a granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, a bias table may be implemented in a stolen memory range of one or more GPU-attached memories  1720 - 1723 , with or without a bias cache in GPU  1710 - 1713  (e.g., to cache frequently/recently used entries of a bias table). Alternatively, an entire bias table may be maintained within a GPU. 
     In at least one embodiment, a bias table entry associated with each access to GPU-attached memory  1720 - 1723  is accessed prior to actual access to a GPU memory, causing the following operations. First, local requests from GPU  1710 - 1713  that find their page in GPU bias are forwarded directly to a corresponding GPU memory  1720 - 1723 . Local requests from a GPU that find their page in host bias are forwarded to processor  1705  (e.g., over a high-speed link as discussed above). In one embodiment, requests from processor  1705  that find a requested page in host processor bias complete a request like a normal memory read. Alternatively, requests directed to a GPU-biased page may be forwarded to GPU  1710 - 1713 . In at least one embodiment, a GPU may then transition a page to a host processor bias if it is not currently using a page. In at least one embodiment, bias state of a page can be changed either by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of cases, a purely hardware-based mechanism. 
     One mechanism for changing bias state employs an API call (e.g. OpenCL), which, in turn, calls a GPU&#39;s device driver which, in turn, sends a message (or enqueues a command descriptor) to a GPU directing it to change a bias state and, for some transitions, perform a cache flushing operation in a host. In at least one embodiment, cache flushing operation is used for a transition from host processor  1705  bias to GPU bias, but is not for an opposite transition. 
     In one embodiment, cache coherency is maintained by temporarily rendering GPU-biased pages uncacheable by host processor  1705 . To access these pages, processor  1705  may request access from GPU  1710  which may or may not grant access right away. Thus, to reduce communication between processor  1705  and GPU  1710  it is beneficial to ensure that GPU-biased pages are those which are required by a GPU but not host processor  1705  and vice versa. 
     Hardware structure(s)  915  are used to perform one or more embodiments. Details regarding the hardware structure(x)  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . 
       FIG. 18  illustrates exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. 
       FIG. 18  is a block diagram illustrating an exemplary system on a chip integrated circuit  1800  that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, integrated circuit  1800  includes one or more application processor(s)  1805  (e.g., CPUs), at least one graphics processor  1810 , and may additionally include an image processor  1815  and/or a video processor  1820 , any of which may be a modular IP core. In at least one embodiment, integrated circuit  1800  includes peripheral or bus logic including a USB controller  1825 , UART controller  1830 , an SPI/SDIO controller  1835 , and an I.sup.2S/I.sup.2C controller  1840 . In at least one embodiment, integrated circuit  1800  can include a display device  1845  coupled to one or more of a high-definition multimedia interface (HDMI) controller  1850  and a mobile industry processor interface (MIPI) display interface  1855 . In at least one embodiment, storage may be provided by a flash memory subsystem  1860  including flash memory and a flash memory controller. In at least one embodiment, memory interface may be provided via a memory controller  1865  for access to SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine  1870 . 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in integrated circuit  1800  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in integrated circuit  1800  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIGS. 19A-19B  illustrate exemplary integrated circuits and associated graphics processors that may be fabricated using one or more IP cores, according to various embodiments described herein. In addition to what is illustrated, other logic and circuits may be included in at least one embodiment, including additional graphics processors/cores, peripheral interface controllers, or general-purpose processor cores. 
       FIGS. 19A-19B  are block diagrams illustrating exemplary graphics processors for use within an SoC, according to embodiments described herein.  FIG. 19A  illustrates an exemplary graphics processor  1910  of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment.  FIG. 19B  illustrates an additional exemplary graphics processor  1940  of a system on a chip integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor  1910  of  FIG. 19A  is a low power graphics processor core. In at least one embodiment, graphics processor  1940  of  FIG. 19B  is a higher performance graphics processor core. In at least one embodiment, each of graphics processors  1910 ,  1940  can be variants of graphics processor  1810  of  FIG. 18 . 
     In at least one embodiment, graphics processor  1910  includes a vertex processor  1905  and one or more fragment processor(s)  1915 A- 1915 N (e.g.,  1915 A,  1915 B,  1915 C,  1915 D, through  1915 N- 1 , and  1915 N). In at least one embodiment, graphics processor  1910  can execute different shader programs via separate logic, such that vertex processor  1905  is optimized to execute operations for vertex shader programs, while one or more fragment processor(s)  1915 A- 1915 N execute fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, vertex processor  1905  performs a vertex processing stage of a 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, fragment processor(s)  1915 A- 1915 N use primitive and vertex data generated by vertex processor  1905  to produce a framebuffer that is displayed on a display device. In at least one embodiment, fragment processor(s)  1915 A- 1915 N are optimized to execute fragment shader programs as provided for in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided for in a Direct 3D API. 
     In at least one embodiment, graphics processor  1910  additionally includes one or more memory management units (MMUs)  1920 A- 1920 B, cache(s)  1925 A- 1925 B, and circuit interconnect(s)  1930 A- 1930 B. In at least one embodiment, one or more MMU(s)  1920 A- 1920 B provide for virtual to physical address mapping for graphics processor  1910 , including for vertex processor  1905  and/or fragment processor(s)  1915 A- 1915 N, which may reference vertex or image/texture data stored in memory, in addition to vertex or image/texture data stored in one or more cache(s)  1925 A- 1925 B. In at least one embodiment, one or more MMU(s)  1920 A- 1920 B may be synchronized with other MMUs within system, including one or more MMUs associated with one or more application processor(s)  1805 , image processors  1815 , and/or video processors  1820  of  FIG. 18 , such that each processor  1805 - 1820  can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnect(s)  1930 A- 1930 B enable graphics processor  1910  to interface with other IP cores within SoC, either via an internal bus of SoC or via a direct connection. 
     In at least one embodiment, graphics processor  1940  includes one or more MMU(s)  1920 A- 1920 B, caches  1925 A- 1925 B, and circuit interconnects  1930 A- 1930 B of graphics processor  1910  of  FIG. 19A . In at least one embodiment, graphics processor  1940  includes one or more shader core(s)  1955 A- 1955 N (e.g.,  1955 A,  1955 B,  1955 C,  1955 D,  1955 E,  1955 F, through  1955 N- 1 , and  1955 N), which provides for a unified shader core architecture in which a single core or type or core can execute all types of programmable shader code, including shader program code to implement vertex shaders, fragment shaders, and/or compute shaders. In at least one embodiment, a number of shader cores can vary. In at least one embodiment, graphics processor  1940  includes an inter-core task manager  1945 , which acts as a thread dispatcher to dispatch execution threads to one or more shader cores  1955 A- 1955 N and a tiling unit  1958  to accelerate tiling operations for tile-based rendering, in which rendering operations for a scene are subdivided in image space, for example to exploit local spatial coherence within a scene or to optimize use of internal caches. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in integrated circuit  19 A and/or  19 B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in integrated circuit  19 A and/or  19 B for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIGS. 20A-20B  illustrate additional exemplary graphics processor logic according to embodiments described herein.  FIG. 20A  illustrates a graphics core  2000  that may be included within graphics processor  1810  of  FIG. 18 , in at least one embodiment, and may be a unified shader core  1955 A- 1955 N as in  FIG. 19B  in at least one embodiment.  FIG. 20B  illustrates a highly-parallel general-purpose graphics processing unit  2030  suitable for deployment on a multi-chip module in at least one embodiment. 
     In at least one embodiment, graphics core  2000  includes a shared instruction cache  2002 , a texture unit  2018 , and a cache/shared memory  2020  that are common to execution resources within graphics core  2000 . In at least one embodiment, graphics core  2000  can include multiple slices  2001 A- 2001 N or partition for each core, and a graphics processor can include multiple instances of graphics core  2000 . Slices  2001 A- 2001 N can include support logic including a local instruction cache  2004 A- 2004 N, a thread scheduler  2006 A- 2006 N, a thread dispatcher  2008 A- 2008 N, and a set of registers  2010 A- 2010 N. In at least one embodiment, slices  2001 A- 2001 N can include a set of additional function units (AFUs  2012 A- 2012 N), floating-point units (FPU  2014 A- 2014 N), integer arithmetic logic units (ALUs  2016 - 2016 N), address computational units (ACU  2013 A- 2013 N), double-precision floating-point units (DPFPU  2015 A- 2015 N), and matrix processing units (MPU  2017 A- 2017 N). 
     In at least one embodiment, FPUs  2014 A- 2014 N can perform single-precision (32-bit) and half-precision (16-bit) floating point operations, while DPFPUs  2015 A- 2015 N perform double precision (64-bit) floating point operations. In at least one embodiment, ALUs  2016 A- 2016 N can perform variable precision integer operations at 8-bit, 16-bit, and 32-bit precision, and can be configured for mixed precision operations. In at least one embodiment, MPUs  2017 A- 2017 N can also be configured for mixed precision matrix operations, including half-precision floating point and 8-bit integer operations. In at least one embodiment, MPUs  2017 - 2017 N can perform a variety of matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix to matrix multiplication (GEMM). In at least one embodiment, AFUs  2012 A- 2012 N can perform additional logic operations not supported by floating-point or integer units, including trigonometric operations (e.g., Sine, Cosine, etc.). 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in graphics core  2000  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in graphics core  2000  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 20B  illustrates a general-purpose processing unit (GPGPU)  2030  that can be configured to enable highly-parallel compute operations to be performed by an array of graphics processing units, in at least one embodiment. In at least one embodiment, GPGPU  2030  can be linked directly to other instances of GPGPU  2030  to create a multi-GPU cluster to improve training speed for deep neural networks. In at least one embodiment, GPGPU  2030  includes a host interface  2032  to enable a connection with a host processor. In at least one embodiment, host interface  2032  is a PCI Express interface. In at least one embodiment, host interface  2032  can be a vendor specific communications interface or communications fabric. In at least one embodiment, GPGPU  2030  receives commands from a host processor and uses a global scheduler  2034  to distribute execution threads associated with those commands to a set of compute clusters  2036 A- 2036 H. In at least one embodiment, compute clusters  2036 A- 2036 H share a cache memory  2038 . In at least one embodiment, cache memory  2038  can serve as a higher-level cache for cache memories within compute clusters  2036 A- 2036 H. 
     In at least one embodiment, GPGPU  2030  includes memory  2044 A- 2044 B coupled with compute clusters  2036 A- 2036 H via a set of memory controllers  2042 A- 2042 B. In at least one embodiment, memory  2044 A- 2044 B can include various types of memory devices including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. 
     In at least one embodiment, compute clusters  2036 A- 2036 H each include a set of graphics cores, such as graphics core  2000  of  FIG. 20A , which can include multiple types of integer and floating point logic units that can perform computational operations at a range of precisions including suited for machine learning computations. For example, in at least one embodiment, at least a subset of floating point units in each of compute clusters  2036 A- 2036 H can be configured to perform 16-bit or 32-bit floating point operations, while a different subset of floating point units can be configured to perform 64-bit floating point operations. 
     In at least one embodiment, multiple instances of GPGPU  2030  can be configured to operate as a compute cluster. In at least one embodiment, communication used by compute clusters  2036 A- 2036 H for synchronization and data exchange varies across embodiments. In at least one embodiment, multiple instances of GPGPU  2030  communicate over host interface  2032 . In at least one embodiment, GPGPU  2030  includes an I/O hub  2039  that couples GPGPU  2030  with a GPU link  2040  that enables a direct connection to other instances of GPGPU  2030 . In at least one embodiment, GPU link  2040  is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU  2030 . In at least one embodiment GPU link  2040  couples with a high speed interconnect to transmit and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU  2030  are located in separate data processing systems and communicate via a network device that is accessible via host interface  2032 . In at least one embodiment GPU link  2040  can be configured to enable a connection to a host processor in addition to or as an alternative to host interface  2032 . 
     In at least one embodiment, GPGPU  2030  can be configured to train neural networks. In at least one embodiment, GPGPU  2030  can be used within a inferencing platform. In at least one embodiment, in which GPGPU  2030  is used for inferencing, GPGPU may include fewer compute clusters  2036 A- 2036 H relative to when GPGPU is used for training a neural network. In at least one embodiment, memory technology associated with memory  2044 A- 2044 B may differ between inferencing and training configurations, with higher bandwidth memory technologies devoted to training configurations. In at least one embodiment, inferencing configuration of GPGPU  2030  can support inferencing specific instructions. For example, in at least one embodiment, an inferencing configuration can provide support for one or more 8-bit integer dot product instructions, which may be used during inferencing operations for deployed neural networks. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in GPGPU  2030  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in GPGPU  2030  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 21  is a block diagram illustrating a computing system  2100  according to at least one embodiment. In at least one embodiment, computing system  2100  includes a processing subsystem  2101  having one or more processor(s)  2102  and a system memory  2104  communicating via an interconnection path that may include a memory hub  2105 . In at least one embodiment, memory hub  2105  may be a separate component within a chipset component or may be integrated within one or more processor(s)  2102 . In at least one embodiment, memory hub  2105  couples with an I/O subsystem  2111  via a communication link  2106 . In at least one embodiment, I/O subsystem  2111  includes an I/O hub  2107  that can enable computing system  2100  to receive input from one or more input device(s)  2108 . In at least one embodiment, I/O hub  2107  can enable a display controller, which may be included in one or more processor(s)  2102 , to provide outputs to one or more display device(s)  2110 A. In at least one embodiment, one or more display device(s)  2110 A coupled with I/O hub  2107  can include a local, internal, or embedded display device. 
     In at least one embodiment, processing subsystem  2101  includes one or more parallel processor(s)  2112  coupled to memory hub  2105  via a bus or other communication link  2113 . In at least one embodiment, communication link  2113  may be one of any number of standards based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. In at least one embodiment, one or more parallel processor(s)  2112  form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. In at least one embodiment, one or more parallel processor(s)  2112  form a graphics processing subsystem that can output pixels to one of one or more display device(s)  2110 A coupled via I/O Hub  2107 . In at least one embodiment, one or more parallel processor(s)  2112  can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s)  2110 B. 
     In at least one embodiment, a system storage unit  2114  can connect to I/O hub  2107  to provide a storage mechanism for computing system  2100 . In at least one embodiment, an I/O switch  2116  can be used to provide an interface mechanism to enable connections between I/O hub  2107  and other components, such as a network adapter  2118  and/or wireless network adapter  2119  that may be integrated into platform, and various other devices that can be added via one or more add-in device(s)  2120 . In at least one embodiment, network adapter  2118  can be an Ethernet adapter or another wired network adapter. In at least one embodiment, wireless network adapter  2119  can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios. 
     In at least one embodiment, computing system  2100  can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and like, may also be connected to I/O hub  2107 . In at least one embodiment, communication paths interconnecting various components in  FIG. 21  may be implemented using any suitable protocols, such as PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or other bus or point-to-point communication interfaces and/or protocol(s), such as NV-Link high-speed interconnect, or interconnect protocols. 
     In at least one embodiment, one or more parallel processor(s)  2112  incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). In at least one embodiment, one or more parallel processor(s)  2112  incorporate circuitry optimized for general purpose processing. In at least embodiment, components of computing system  2100  may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s)  2112 , memory hub  2105 , processor(s)  2102 , and I/O hub  2107  can be integrated into a system on chip (SoC) integrated circuit. In at least one embodiment, components of computing system  2100  can be integrated into a single package to form a system in package (SIP) configuration. In at least one embodiment, at least a portion of components of computing system  2100  can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in system  FIG. 2100  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in system  FIG. 2100  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     Processors 
       FIG. 22A  illustrates a parallel processor  2200  according to at least on embodiment. In at least one embodiment, various components of parallel processor  2200  may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGA). In at least one embodiment, illustrated parallel processor  2200  is a variant of one or more parallel processor(s)  2112  shown in  FIG. 21  according to an exemplary embodiment. 
     In at least one embodiment, parallel processor  2200  includes a parallel processing unit  2202 . In at least one embodiment, parallel processing unit  2202  includes an I/O unit  2204  that enables communication with other devices, including other instances of parallel processing unit  2202 . In at least one embodiment, I/O unit  2204  may be directly connected to other devices. In at least one embodiment, I/O unit  2204  connects with other devices via use of a hub or switch interface, such as memory hub  2105 . In at least one embodiment, connections between memory hub  2105  and I/O unit  2204  form a communication link  2113 . In at least one embodiment, I/O unit  2204  connects with a host interface  2206  and a memory crossbar  2216 , where host interface  2206  receives commands directed to performing processing operations and memory crossbar  2216  receives commands directed to performing memory operations. 
     In at least one embodiment, when host interface  2206  receives a command buffer via I/O unit  2204 , host interface  2206  can direct work operations to perform those commands to a front end  2208 . In at least one embodiment, front end  2208  couples with a scheduler  2210 , which is configured to distribute commands or other work items to a processing cluster array  2212 . In at least one embodiment, scheduler  2210  ensures that processing cluster array  2212  is properly configured and in a valid state before tasks are distributed to processing cluster array  2212  of processing cluster array  2212 . In at least one embodiment, scheduler  2210  is implemented via firmware logic executing on a microcontroller. In at least one embodiment, microcontroller implemented scheduler  2210  is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on processing array  2212 . In at least one embodiment, host software can prove workloads for scheduling on processing array  2212  via one of multiple graphics processing doorbells. In at least one embodiment, workloads can then be automatically distributed across processing array  2212  by scheduler  2210  logic within a microcontroller including scheduler  2210 . 
     In at least one embodiment, processing cluster array  2212  can include up to “N” processing clusters (e.g., cluster  2214 A, cluster  2214 B, through cluster  2214 N). In at least one embodiment, each cluster  2214 A- 2214 N of processing cluster array  2212  can execute a large number of concurrent threads. In at least one embodiment, scheduler  2210  can allocate work to clusters  2214 A- 2214 N of processing cluster array  2212  using various scheduling and/or work distribution algorithms, which may vary depending on workload arising for each type of program or computation. In at least one embodiment, scheduling can be handled dynamically by scheduler  2210 , or can be assisted in part by compiler logic during compilation of program logic configured for execution by processing cluster array  2212 . In at least one embodiment, different clusters  2214 A- 2214 N of processing cluster array  2212  can be allocated for processing different types of programs or for performing different types of computations. 
     In at least one embodiment, processing cluster array  2212  can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array  2212  is configured to perform general-purpose parallel compute operations. For example, in at least one embodiment, processing cluster array  2212  can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations. 
     In at least one embodiment, processing cluster array  2212  is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array  2212  can include additional logic to support execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array  2212  can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing unit  2202  can transfer data from system memory via I/O unit  2204  for processing. In at least one embodiment, during processing, transferred data can be stored to on-chip memory (e.g., parallel processor memory  2222 ) during processing, then written back to system memory. 
     In at least one embodiment, when parallel processing unit  2202  is used to perform graphics processing, scheduler  2210  can be configured to divide a processing workload into approximately equal sized tasks, to better enable distribution of graphics processing operations to multiple clusters  2214 A- 2214 N of processing cluster array  2212 . In at least one embodiment, portions of processing cluster array  2212  can be configured to perform different types of processing. For example, in at least one embodiment, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. In at least one embodiment, intermediate data produced by one or more of clusters  2214 A- 2214 N may be stored in buffers to allow intermediate data to be transmitted between clusters  2214 A- 2214 N for further processing. 
     In at least one embodiment, processing cluster array  2212  can receive processing tasks to be executed via scheduler  2210 , which receives commands defining processing tasks from front end  2208 . In at least one embodiment, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how data is to be processed (e.g., what program is to be executed). In at least one embodiment, scheduler  2210  may be configured to fetch indices corresponding to tasks or may receive indices from front end  2208 . In at least one embodiment, front end  2208  can be configured to ensure processing cluster array  2212  is configured to a valid state before a workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated. 
     In at least one embodiment, each of one or more instances of parallel processing unit  2202  can couple with parallel processor memory  2222 . In at least one embodiment, parallel processor memory  2222  can be accessed via memory crossbar  2216 , which can receive memory requests from processing cluster array  2212  as well as I/O unit  2204 . In at least one embodiment, memory crossbar  2216  can access parallel processor memory  2222  via a memory interface  2218 . In at least one embodiment, memory interface  2218  can include multiple partition units (e.g., partition unit  2220 A, partition unit  2220 B, through partition unit  2220 N) that can each couple to a portion (e.g., memory unit) of parallel processor memory  2222 . In at least one embodiment, a number of partition units  2220 A- 2220 N is configured to be equal to a number of memory units, such that a first partition unit  2220 A has a corresponding first memory unit  2224 A, a second partition unit  2220 B has a corresponding memory unit  2224 B, and an Nth partition unit  2220 N has a corresponding Nth memory unit  2224 N. In at least one embodiment, a number of partition units  2220 A- 2220 N may not be equal to a number of memory devices. 
     In at least one embodiment, memory units  2224 A- 2224 N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units  2224 A- 2224 N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets, such as frame buffers or texture maps may be stored across memory units  2224 A- 2224 N, allowing partition units  2220 A- 2220 N to write portions of each render target in parallel to efficiently use available bandwidth of parallel processor memory  2222 . In at least one embodiment, a local instance of parallel processor memory  2222  may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory. 
     In at least one embodiment, any one of clusters  2214 A- 2214 N of processing cluster array  2212  can process data that will be written to any of memory units  2224 A- 2224 N within parallel processor memory  2222 . In at least one embodiment, memory crossbar  2216  can be configured to transfer an output of each cluster  2214 A- 2214 N to any partition unit  2220 A- 2220 N or to another cluster  2214 A- 2214 N, which can perform additional processing operations on an output. In at least one embodiment, each cluster  2214 A- 2214 N can communicate with memory interface  2218  through memory crossbar  2216  to read from or write to various external memory devices. In at least one embodiment, memory crossbar  2216  has a connection to memory interface  2218  to communicate with I/O unit  2204 , as well as a connection to a local instance of parallel processor memory  2222 , enabling processing units within different processing clusters  2214 A- 2214 N to communicate with system memory or other memory that is not local to parallel processing unit  2202 . In at least one embodiment, memory crossbar  2216  can use virtual channels to separate traffic streams between clusters  2214 A- 2214 N and partition units  2220 A- 2220 N. 
     In at least one embodiment, multiple instances of parallel processing unit  2202  can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit  2202  can be configured to inter-operate even if different instances have different numbers of processing cores, different amounts of local parallel processor memory, and/or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit  2202  can include higher precision floating point units relative to other instances. In at least one embodiment, systems incorporating one or more instances of parallel processing unit  2202  or parallel processor  2200  can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and/or embedded systems. 
       FIG. 22B  is a block diagram of a partition unit  2220  according to at least one embodiment. In at least one embodiment, partition unit  2220  is an instance of one of partition units  2220 A- 2220 N of  FIG. 22A . In at least one embodiment, partition unit  2220  includes an L2 cache  2221 , a frame buffer interface  2225 , and a ROP  2226  (raster operations unit). L2 cache  2221  is a read/write cache that is configured to perform load and store operations received from memory crossbar  2216  and ROP  2226 . In at least one embodiment, read misses and urgent write-back requests are output by L2 cache  2221  to frame buffer interface  2225  for processing. In at least one embodiment, updates can also be sent to a frame buffer via frame buffer interface  2225  for processing. In at least one embodiment, frame buffer interface  2225  interfaces with one of memory units in parallel processor memory, such as memory units  2224 A- 2224 N of  FIG. 22  (e.g., within parallel processor memory  2222 ). 
     In at least one embodiment, ROP  2226  is a processing unit that performs raster operations such as stencil, z test, blending, and like. In at least one embodiment, ROP  2226  then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP  2226  includes compression logic to compress depth or color data that is written to memory and decompress depth or color data that is read from memory. In at least one embodiment, compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. Type of compression that is performed by ROP  2226  can vary based on statistical characteristics of data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data on a per-tile basis. 
     In In at least one embodiment, ROP  2226  is included within each processing cluster (e.g., cluster  2214 A- 2214 N of  FIG. 22 ) instead of within partition unit  2220 . In at least one embodiment, read and write requests for pixel data are transmitted over memory crossbar  2216  instead of pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device, such as one of one or more display device(s)  2110  of  FIG. 21 , routed for further processing by processor(s)  2102 , or routed for further processing by one of processing entities within parallel processor  2200  of  FIG. 22A . 
       FIG. 22C  is a block diagram of a processing cluster  2214  within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is an instance of one of processing clusters  2214 A- 2214 N of  FIG. 22 . In at least one embodiment, processing cluster  2214  can be configured to execute many threads in parallel, where term “thread” refers to an instance of a particular program executing on a particular set of input data. In at least one embodiment, single-instruction, multiple-data (SIMD) instruction issue techniques are used to support parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single-instruction, multiple-thread (SIMT) techniques are used to support parallel execution of a large number of generally synchronized threads, using a common instruction unit configured to issue instructions to a set of processing engines within each one of processing clusters. 
     In at least one embodiment, operation of processing cluster  2214  can be controlled via a pipeline manager  2232  that distributes processing tasks to SIMT parallel processors. In at least one embodiment, pipeline manager  2232  receives instructions from scheduler  2210  of  FIG. 22  and manages execution of those instructions via a graphics multiprocessor  2234  and/or a texture unit  2236 . In at least one embodiment, graphics multiprocessor  2234  is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of differing architectures may be included within processing cluster  2214 . In at least one embodiment, one or more instances of graphics multiprocessor  2234  can be included within a processing cluster  2214 . In at least one embodiment, graphics multiprocessor  2234  can process data and a data crossbar  2240  can be used to distribute processed data to one of multiple possible destinations, including other shader units. In at least one embodiment, pipeline manager  2232  can facilitate distribution of processed data by specifying destinations for processed data to be distributed via data crossbar  2240 . 
     In at least one embodiment, each graphics multiprocessor  2234  within processing cluster  2214  can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. In at least one embodiment, functional execution logic supports a variety of operations including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. In at least one embodiment, same functional-unit hardware can be leveraged to perform different operations and any combination of functional units may be present. 
     In at least one embodiment, instructions transmitted to processing cluster  2214  constitute a thread. In at least one embodiment, a set of threads executing across a set of parallel processing engines is a thread group. In at least one embodiment, thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor  2234 . In at least one embodiment, a thread group may include fewer threads than a number of processing engines within graphics multiprocessor  2234 . In at least one embodiment, when a thread group includes fewer threads than a number of processing engines, one or more of processing engines may be idle during cycles in which that thread group is being processed. In at least one embodiment, a thread group may also include more threads than a number of processing engines within graphics multiprocessor  2234 . In at least one embodiment, when a thread group includes more threads than number of processing engines within graphics multiprocessor  2234 , processing can be performed over consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed concurrently on a graphics multiprocessor  2234 . 
     In at least one embodiment, graphics multiprocessor  2234  includes an internal cache memory to perform load and store operations. In at least one embodiment, graphics multiprocessor  2234  can forego an internal cache and use a cache memory (e.g., L1 cache  2248 ) within processing cluster  2214 . In at least one embodiment, each graphics multiprocessor  2234  also has access to L2 caches within partition units (e.g., partition units  2220 A- 2220 N of  FIG. 22 ) that are shared among all processing clusters  2214  and may be used to transfer data between threads. In at least one embodiment, graphics multiprocessor  2234  may also access off-chip global memory, which can include one or more of local parallel processor memory and/or system memory. In at least one embodiment, any memory external to parallel processing unit  2202  may be used as global memory. In at least one embodiment, processing cluster  2214  includes multiple instances of graphics multiprocessor  2234  can share common instructions and data, which may be stored in L1 cache  2248 . 
     In at least one embodiment, each processing cluster  2214  may include an MMU  2245  (memory management unit) that is configured to map virtual addresses into physical addresses. In at least one embodiment, one or more instances of MMU  2245  may reside within memory interface  2218  of  FIG. 22 . In at least one embodiment, MMU  2245  includes a set of page table entries (PTEs) used to map a virtual address to a physical address of a tile (talk more about tiling) and optionally a cache line index. In at least one embodiment, MMU  2245  may include address translation lookaside buffers (TLB) or caches that may reside within graphics multiprocessor  2234  or L1 cache or processing cluster  2214 . In at least one embodiment, physical address is processed to distribute surface data access locality to allow efficient request interleaving among partition units. In at least one embodiment, cache line index may be used to determine whether a request for a cache line is a hit or miss. 
     In at least one embodiment, a processing cluster  2214  may be configured such that each graphics multiprocessor  2234  is coupled to a texture unit  2236  for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within graphics multiprocessor  2234  and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. In at least one embodiment, each graphics multiprocessor  2234  outputs processed tasks to data crossbar  2240  to provide processed task to another processing cluster  2214  for further processing or to store processed task in an L2 cache, local parallel processor memory, or system memory via memory crossbar  2216 . In at least one embodiment, preROP  2242  (pre-raster operations unit) is configured to receive data from graphics multiprocessor  2234 , direct data to ROP units, which may be located with partition units as described herein (e.g., partition units  2220 A- 2220 N of  FIG. 22 ). In at least one embodiment, PreROP 2242 unit can perform optimizations for color blending, organize pixel color data, and perform address translations. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in graphics processing cluster  2214  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in graphics processing cluster  2214  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 22D  shows a graphics multiprocessor  2234  according to at least one embodiment. In at least one embodiment, graphics multiprocessor  2234  couples with pipeline manager  2232  of processing cluster  2214 . In at least one embodiment, graphics multiprocessor  2234  has an execution pipeline including but not limited to an instruction cache  2252 , an instruction unit  2254 , an address mapping unit  2256 , a register file  2258 , one or more general purpose graphics processing unit (GPGPU) cores  2262 , and one or more load/store units  2266 . GPGPU cores  2262  and load/store units  2266  are coupled with cache memory  2272  and shared memory  2270  via a memory and cache interconnect  2268 . 
     In at least one embodiment, instruction cache  2252  receives a stream of instructions to execute from pipeline manager  2232 . In at least one embodiment, instructions are cached in instruction cache  2252  and dispatched for execution by instruction unit  2254 . In at least one embodiment, instruction unit  2254  can dispatch instructions as thread groups (e.g., warps), with each thread of thread group assigned to a different execution unit within GPGPU core  2262 . In at least one embodiment, an instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, address mapping unit  2256  can be used to translate addresses in a unified address space into a distinct memory address that can be accessed by load/store units  2266 . 
     In at least one embodiment, register file  2258  provides a set of registers for functional units of graphics multiprocessor  2234 . In at least one embodiment, register file  2258  provides temporary storage for operands connected to data paths of functional units (e.g., GPGPU cores  2262 , load/store units  2266 ) of graphics multiprocessor  2234 . In at least one embodiment, register file  2258  is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file  2258 . In at least one embodiment, register file  2258  is divided between different warps being executed by graphics multiprocessor  2234 . 
     In at least one embodiment, GPGPU cores  2262  can each include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of graphics multiprocessor  2234 . GPGPU cores  2262  can be similar in architecture or can differ in architecture. In at least one embodiment, a first portion of GPGPU cores  2262  include a single precision FPU and an integer ALU while a second portion of GPGPU cores include a double precision FPU. In at least one embodiment, FPUs can implement IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. In at least one embodiment, graphics multiprocessor  2234  can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. In at least one embodiment one or more of GPGPU cores can also include fixed or special function logic. 
     In at least one embodiment, GPGPU cores  2262  include SIMD logic capable of performing a single instruction on multiple sets of data. In at least one embodiment GPGPU cores  2262  can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, SIMD instructions for GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. In at least one embodiment, multiple threads of a program configured for an SIMT execution model can executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads that perform same or similar operations can be executed in parallel via a single SIMD8 logic unit. 
     In at least one embodiment, memory and cache interconnect  2268  is an interconnect network that connects each functional unit of graphics multiprocessor  2234  to register file  2258  and to shared memory  2270 . In at least one embodiment, memory and cache interconnect  2268  is a crossbar interconnect that allows load/store unit  2266  to implement load and store operations between shared memory  2270  and register file  2258 . In at least one embodiment, register file  2258  can operate at a same frequency as GPGPU cores  2262 , thus data transfer between GPGPU cores  2262  and register file  2258  is very low latency. In at least one embodiment, shared memory  2270  can be used to enable communication between threads that execute on functional units within graphics multiprocessor  2234 . In at least one embodiment, cache memory  2272  can be used as a data cache for example, to cache texture data communicated between functional units and texture unit  2236 . In at least one embodiment, shared memory  2270  can also be used as a program managed cached. In at least one embodiment, threads executing on GPGPU cores  2262  can programmatically store data within shared memory in addition to automatically cached data that is stored within cache memory  2272 . 
     In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general purpose GPU (GPGPU) functions. In at least one embodiment, GPU may be communicatively coupled to host processor/cores over a bus or other interconnect (e.g., a high speed interconnect such as PCIe or NVLink). In at least one embodiment, GPU may be integrated on same package or chip as cores and communicatively coupled to cores over an internal processor bus/interconnect (i.e., internal to package or chip). In at least one embodiment, regardless of manner in which GPU is connected, processor cores may allocate work to GPU in form of sequences of commands/instructions contained in a work descriptor. In at least one embodiment, GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in graphics multiprocessor  2234  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in graphics multiprocessor  2234  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 23  illustrates a multi-GPU computing system  2300 , according to at least one embodiment. In at least one embodiment, multi-GPU computing system  2300  can include a processor  2302  coupled to multiple general purpose graphics processing units (GPGPUs)  2306 A-D via a host interface switch  2304 . In at least one embodiment, host interface switch  2304  is a PCI express switch device that couples processor  2302  to a PCI express bus over which processor  2302  can communicate with GPGPUs  2306 A-D. GPGPUs  2306 A-D can interconnect via a set of high-speed point to point GPU to GPU links  2316 . In at least one embodiment, GPU to GPU links  2316  connect to each of GPGPUs  2306 A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links  2316  enable direct communication between each of GPGPUs  2306 A-D without requiring communication over host interface bus  2304  to which processor  2302  is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU links  2316 , host interface bus  2304  remains available for system memory access or to communicate with other instances of multi-GPU computing system  2300 , for example, via one or more network devices. While in at least one embodiment GPGPUs  2306 A-D connect to processor  2302  via host interface switch  2304 , in at least one embodiment processor  2302  includes direct support for P2P GPU links  2316  and can connect directly to GPGPUs  2306 A-D. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in multi-GPU computing system  2300  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in multi-GPU computing system  2300  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 24  is a block diagram of a graphics processor  2400 , according to at least one embodiment. In at least one embodiment, graphics processor  2400  includes a ring interconnect  2402 , a pipeline front-end  2404 , a media engine  2437 , and graphics cores  2480 A- 2480 N. In at least one embodiment, ring interconnect  2402  couples graphics processor  2400  to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor  2400  is one of many processors integrated within a multi-core processing system. 
     In at least one embodiment, graphics processor  2400  receives batches of commands via ring interconnect  2402 . In at least one embodiment, incoming commands are interpreted by a command streamer  2403  in pipeline front-end  2404 . In at least one embodiment, graphics processor  2400  includes scalable execution logic to perform 3D geometry processing and media processing via graphics core(s)  2480 A- 2480 N. In at least one embodiment, for 3D geometry processing commands, command streamer  2403  supplies commands to geometry pipeline  2436 . In at least one embodiment, for at least some media processing commands, command streamer  2403  supplies commands to a video front end  2434 , which couples with a media engine  2437 . In at least one embodiment, media engine  2437  includes a Video Quality Engine (VQE)  2430  for video and image post-processing and a multi-format encode/decode (MFX)  2433  engine to provide hardware-accelerated media data encode and decode. In at least one embodiment, geometry pipeline  2436  and media engine  2437  each generate execution threads for thread execution resources provided by at least one graphics core  2480 A. 
     In at least one embodiment, graphics processor  2400  includes scalable thread execution resources featuring modular cores  2480 A- 2480 N (sometimes referred to as core slices), each having multiple sub-cores  2450 A- 550 N,  2460 A- 2460 N (sometimes referred to as core sub-slices). In at least one embodiment, graphics processor  2400  can have any number of graphics cores  2480 A through  2480 N. In at least one embodiment, graphics processor  2400  includes a graphics core  2480 A having at least a first sub-core  2450 A and a second sub-core  2460 A. In at least one embodiment, graphics processor  2400  is a low power processor with a single sub-core (e.g.,  2450 A). In at least one embodiment, graphics processor  2400  includes multiple graphics cores  2480 A- 2480 N, each including a set of first sub-cores  2450 A- 2450 N and a set of second sub-cores  2460 A- 2460 N. In at least one embodiment, each sub-core in first sub-cores  2450 A- 2450 N includes at least a first set of execution units  2452 A- 2452 N and media/texture samplers  2454 A- 2454 N. In at least one embodiment, each sub-core in second sub-cores  2460 A- 2460 N includes at least a second set of execution units  2462 A- 2462 N and samplers  2464 A- 2464 N. In at least one embodiment, each sub-core  2450 A- 2450 N,  2460 A- 2460 N shares a set of shared resources  2470 A- 2470 N. In at least one embodiment, shared resources include shared cache memory and pixel operation logic. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, inference and/or training logic  915  may be used in graphics processor  2400  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
     In at least one embodiment, inference and/or training logic  2  may be used in graphics processor  2400  for inferencing or predicting operations based, at least in part, on weight parameters calculated using neural network training operations, neural network functions and/or architectures, or neural network use cases described herein. 
       FIG. 25  is a block diagram illustrating micro-architecture for a processor  2500  that may include logic circuits to perform instructions, according to at least one embodiment. In at least one embodiment, processor  2500  may perform instructions, including x86 instructions, ARM instructions, specialized instructions for application-specific integrated circuits (ASICs), etc. In at least one embodiment, processor  2510  may include registers to store packed data, such as 64-bit wide MMX™ registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, Calif. In at least one embodiment, MMX registers, available in both integer and floating point forms, may operate with packed data elements that accompany single instruction, multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, 128-bit wide XMM registers relating to SSE2, SSE3, SSE4, AVX, or beyond (referred to generically as “SSEx”) technology may hold such packed data operands. In at least one embodiment, processors  2510  may perform instructions to accelerate machine learning or deep learning algorithms, training, or inferencing. 
     In at least one embodiment, processor  2500  includes an in-order front end (“front end”)  2501  to fetch instructions to be executed and prepare instructions to be used later in processor pipeline. In at least one embodiment, front end  2501  may include several units. In at least one embodiment, an instruction prefetcher  2526  fetches instructions from memory and feeds instructions to an instruction decoder  2528  which in turn decodes or interprets instructions. For example, in at least one embodiment, instruction decoder  2528  decodes a received instruction into one or more operations called “micro-instructions” or “micro-operations” (also called “micro ops” or “uops”) that machine may execute. In at least one embodiment, instruction decoder  2528  parses instruction into an opcode and corresponding data and control fields that may be used by micro-architecture to perform operations in accordance with at least one embodiment. In at least one embodiment, a trace cache  2530  may assemble decoded uops into program ordered sequences or traces in a uop queue  2534  for execution. In at least one embodiment, when trace cache  2530  encounters a complex instruction, a microcode ROM  2532  provides uops needed to complete operation. 
     In at least one embodiment, some instructions may be converted into a single micro-op, whereas others need several micro-ops to complete full operation. In at least one embodiment, if more than four micro-ops are needed to complete an instruction, instruction decoder  2528  may access microcode ROM  2532  to perform instruction. In at least one embodiment, an instruction may be decoded into a small number of micro-ops for processing at instruction decoder  2528 . In at least one embodiment, an instruction may be stored within microcode ROM  2532  should a number of micro-ops be needed to accomplish operation. In at least one embodiment, trace cache  2530  refers to an entry point programmable logic array (“PLA”) to determine a correct micro-instruction pointer for reading microcode sequences to complete one or more instructions from microcode ROM  2532  in accordance with at least one embodiment. In at least one embodiment, after microcode ROM  2532  finishes sequencing micro-ops for an instruction, front end  2501  of machine may resume fetching micro-ops from trace cache  2530 . 
     In at least one embodiment, out-of-order execution engine (“out of order engine”)  2503  may prepare instructions for execution. In at least one embodiment, out-of-order execution logic has a number of buffers to smooth out and re-order flow of instructions to optimize performance as they go down pipeline and get scheduled for execution. out-of-order execution engine  2503  includes, without limitation, an allocator/register renamer  2540 , a memory uop queue  2542 , an integer/floating point uop queue  2544 , a memory scheduler  2546 , a fast scheduler  2502 , a slow/general floating point scheduler (“slow/general FP scheduler”)  2504 , and a simple floating point scheduler (“simple FP scheduler”)  2506 . In at least one embodiment, fast schedule  2502 , slow/general floating point scheduler  2504 , and simple floating point scheduler  2506  are also collectively referred to herein as “uop schedulers  2502 ,  2504 ,  2506 .” Allocator/register renamer  2540  allocates machine buffers and resources that each uop needs in order to execute. In at least one embodiment, allocator/register renamer  2540  renames logic registers onto entries in a register file. In at least one embodiment, allocator/register renamer  2540  also allocates an entry for each uop in one of two uop queues, memory uop queue  2542  for memory operations and integer/floating point uop queue  2544  for non-memory operations, in front of memory scheduler  2546  and uop schedulers  2502 ,  2504 ,  2506 . In at least one embodiment, uop schedulers  2502 ,  2504 ,  2506 , determine when a uop is ready to execute based on readiness of their dependent input register operand sources and availability of execution resources uops need to complete their operation. In at least one embodiment, fast scheduler  2502  of at least one embodiment may schedule on each half of main clock cycle while slow/general floating point scheduler  2504  and simple floating point scheduler  2506  may schedule once per main processor clock cycle. In at least one embodiment, uop schedulers  2502 ,  2504 ,  2506  arbitrate for dispatch ports to schedule uops for execution. 
     In at least one embodiment, execution block b 11  includes, without limitation, an integer register file/bypass network  2508 , a floating point register file/bypass network (“FP register file/bypass network”)  2510 , address generation units (“AGUs”)  2512  and  2514 , fast Arithmetic Logic Units (ALUs) (“fast ALUs”)  2516  and  2518 , a slow Arithmetic Logic Unit (“slow ALU”)  2520 , a floating point ALU (“FP”)  2522 , and a floating point move unit (“FP move”)  2524 . In at least one embodiment, integer register file/bypass network  2508  and floating point register file/bypass network  2510  are also referred to herein as “register files  2508 ,  2510 .” In at least one embodiment, AGUSs  2512  and  2514 , fast ALUs  2516  and  2518 , slow ALU  2520 , floating point ALU  2522 , and floating point move unit  2524  are also referred to herein as “execution units  2512 ,  2514 ,  2516 ,  2518 ,  2520 ,  2522 , and  2524 .” In at least one embodiment, execution block b 11  may include, without limitation, any number (including zero) and type of register files, bypass networks, address generation units, and execution units, in any combination. 
     In at least one embodiment, register files  2508 ,  2510  may be arranged between uop schedulers  2502 ,  2504 ,  2506 , and execution units  2512 ,  2514 ,  2516 ,  2518 ,  2520 ,  2522 , and  2524 . In at least one embodiment, integer register file/bypass network  2508  performs integer operations. In at least one embodiment, floating point register file/bypass network  2510  performs floating point operations. In at least one embodiment, each of register files  2508 ,  2510  may include, without limitation, a bypass network that may bypass or forward just completed results that have not yet been written into register file to new dependent uops. In at least one embodiment, register files  2508 ,  2510  may communicate data with each other. In at least one embodiment, integer register file/bypass network  2508  may include, without limitation, two separate register files, one register file for low-order thirty-two bits of data and a second register file for high order thirty-two bits of data. In at least one embodiment, floating point register file/bypass network  2510  may include, without limitation, 128-bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width. 
     In at least one embodiment, execution units  2512 ,  2514 ,  2516 ,  2518 ,  2520 ,  2522 ,  2524  may execute instructions. In at least one embodiment, register files  2508 ,  2510  store integer and floating point data operand values that micro-instructions need to execute. In at least one embodiment, processor  2500  may include, without limitation, any number and combination of execution units  2512 ,  2514 ,  2516 ,  2518 ,  2520 ,  2522 ,  2524 . In at least one embodiment, floating point ALU  2522  and floating point move unit  2524 , may execute floating point, MMX, SIMD, AVX and SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating point ALU  2522  may include, without limitation, a 64-bit by 64-bit floating point divider to execute divide, square root, and remainder micro ops. In at least one embodiment, instructions involving a floating point value may be handled with floating point hardware. In at least one embodiment, ALU operations may be passed to fast ALUs  2516 ,  2518 . In at least one embodiment, fast ALUS  2516 ,  2518  may execute fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU  2520  as slow ALU  2520  may include, without limitation, integer execution hardware for long-latency type of operations, such as a multiplier, shifts, flag logic, and branch processing. In at least one embodiment, memory load/store operations may be executed by AGUS  2512 ,  2514 . In at least one embodiment, fast ALU  2516 , fast ALU  2518 , and slow ALU  2520  may perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU  2516 , fast ALU  2518 , and slow ALU  2520  may be implemented to support a variety of data bit sizes including sixteen, thirty-two, 128, 256, etc. In at least one embodiment, floating point ALU  2522  and floating point move unit  2524  may be implemented to support a range of operands having bits of various widths. In at least one embodiment, floating point ALU  2522  and floating point move unit  2524  may operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions. 
     In at least one embodiment, uop schedulers  2502 ,  2504 ,  2506 , dispatch dependent operations before parent load has finished executing. In at least one embodiment, as uops may be speculatively scheduled and executed in processor  2500 , processor  2500  may also include logic to handle memory misses. In at least one embodiment, if a data load misses in data cache, there may be dependent operations in flight in pipeline that have left scheduler with temporarily incorrect data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, dependent operations might need to be replayed and independent ones may be allowed to complete. In at least one embodiment, schedulers and replay mechanism of at least one embodiment of a processor may also be designed to catch instruction sequences for text string comparison operations. 
     In at least one embodiment, term “registers” may refer to on-board processor storage locations that may be used as part of instructions to identify operands. In at least one embodiment, registers may be those that may be usable from outside of processor (from a programmer&#39;s perspective). In at least one embodiment, registers might not be limited to a particular type of circuit. Rather, in at least one embodiment, a register may store data, provide data, and perform functions described herein. In at least one embodiment, registers described herein may be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc. In at least one embodiment, integer registers store 32-bit integer data. A register file of at least one embodiment also contains eight multimedia SIMD registers for packed data. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment portions or all of inference and/or training logic  915  may be incorporated into EXE Block  2511  and other memory or registers shown or not shown. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs illustrated in EXE Block  2511 . Moreover, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of EXE Block  2511  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment portions or all of inference and/or training logic  2  may be incorporated into EXE Block  2511  and other memory or registers shown or not shown. For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs illustrated in EXE Block  2511 . Moreover, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of EXE Block  2511  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 26  illustrates a deep learning application processor  2600 , according to at least one embodiment. In at least one embodiment, deep learning application processor  2600  uses instructions that, if executed by deep learning application processor  2600 , cause deep learning application processor  2600  to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, deep learning application processor  2600  is an application-specific integrated circuit (ASIC). In at least one embodiment, application processor  2600  performs matrix multiply operations either “hard-wired” into hardware as a result of performing one or more instructions or both. In at least one embodiment, deep learning application processor  2600  includes, without limitation, processing clusters  2610 ( 1 )- 2610 ( 12 ), Inter-Chip Links (“ICLs”)  2620 ( 1 )- 2620 ( 12 ), Inter-Chip Controllers (“ICCs”)  2630 ( 1 )- 2630 ( 2 ), high bandwidth memory second generation (“HBM2”)  2640 ( 1 )- 2640 ( 4 ), memory controllers (“Mem Ctrlrs”)  2642 ( 1 )- 2642 ( 4 ), high bandwidth memory physical layer (“HBM PHY”)  2644 ( 1 )- 2644 ( 4 ), a management-controller central processing unit (“management-controller CPU”)  2650 , a Serial Peripheral Interface, Inter-Integrated Circuit, and General Purpose Input/Output block (“SPI, I2C, GPIO”)  2660 , a peripheral component interconnect express controller and direct memory access block (“PCIe Controller and DMA”)  2670 , and a sixteen-lane peripheral component interconnect express port (“PCI Express x 16”)  2680 . 
     In at least one embodiment, processing clusters  2610  may perform deep learning operations, including inference or prediction operations based on weight parameters calculated one or more training techniques, including those described herein. In at least one embodiment, each processing cluster  2610  may include, without limitation, any number and type of processors. In at least one embodiment, deep learning application processor  2600  may include any number and type of processing clusters  2600 . In at least one embodiment, Inter-Chip Links  2620  are bi-directional. In at least one embodiment, Inter-Chip Links  2620  and Inter-Chip Controllers  2630  enable multiple deep learning application processors  2600  to exchange information, including activation information resulting from performing one or more machine learning algorithms embodied in one or more neural networks. In at least one embodiment, deep learning application processor  2600  may include any number (including zero) and type of ICLs  2620  and ICCs  2630 . 
     In at least one embodiment, HBM2s  2640  provide a total of 32 Gigabytes (GB) of memory. HBM2  2640 ( i ) is associated with both memory controller  2642 ( i ) and HBM PHY  2644 ( i ). In at least one embodiment, any number of HBM2s  2640  may provide any type and total amount of high bandwidth memory and may be associated with any number (including zero) and type of memory controllers  2642  and HBM PHYs  2644 . In at least one embodiment, SPI, I2C, GPIO  2660 , PCIe Controller and DMA  2670 , and/or PCIe  2680  may be replaced with any number and type of blocks that enable any number and type of communication standards in any technically feasible fashion. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to deep learning application processor  2600 . In at least one embodiment, deep learning application processor  2600  is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by deep learning application processor  2600 . In at least one embodiment, processor  2600  may be used to perform one or more neural network use cases described herein. 
       FIG. 27  is a block diagram of a neuromorphic processor  2700 , according to at least one embodiment. In at least one embodiment, neuromorphic processor  2700  may receive one or more inputs from sources external to neuromorphic processor  2700 . In at least one embodiment, these inputs may be transmitted to one or more neurons  2702  within neuromorphic processor  2700 . In at least one embodiment, neurons  2702  and components thereof may be implemented using circuitry or logic, including one or more arithmetic logic units (ALUs). In at least one embodiment, neuromorphic processor  2700  may include, without limitation, thousands or millions of instances of neurons  2702 , but any suitable number of neurons  2702  may be used. In at least one embodiment, each instance of neuron  2702  may include a neuron input  2704  and a neuron output  2706 . In at least one embodiment, neurons  2702  may generate outputs that may be transmitted to inputs of other instances of neurons  2702 . For example, in at least one embodiment, neuron inputs  2704  and neuron outputs  2706  may be interconnected via synapses  2708 . 
     In at least one embodiment, neurons  2702  and synapses  2708  may be interconnected such that neuromorphic processor  2700  operates to process or analyze information received by neuromorphic processor  2700 . In at least one embodiment, neurons  2702  may transmit an output pulse (or “fire” or “spike”) when inputs received through neuron input  2704  exceed a threshold. In at least one embodiment, neurons  2702  may sum or integrate signals received at neuron inputs  2704 . For example, in at least one embodiment, neurons  2702  may be implemented as leaky integrate-and-fire neurons, wherein if a sum (referred to as a “membrane potential”) exceeds a threshold value, neuron  2702  may generate an output (or “fire”) using a transfer function such as a sigmoid or threshold function. In at least one embodiment, a leaky integrate-and-fire neuron may sum signals received at neuron inputs  2704  into a membrane potential and may also apply a decay factor (or leak) to reduce a membrane potential. In at least one embodiment, a leaky integrate-and-fire neuron may fire if multiple input signals are received at neuron inputs  2704  rapidly enough to exceed a threshold value (i.e., before a membrane potential decays too low to fire). In at least one embodiment, neurons  2702  may be implemented using circuits or logic that receive inputs, integrate inputs into a membrane potential, and decay a membrane potential. In at least one embodiment, inputs may be averaged, or any other suitable transfer function may be used. Furthermore, in at least one embodiment, neurons  2702  may include, without limitation, comparator circuits or logic that generate an output spike at neuron output  2706  when result of applying a transfer function to neuron input  2704  exceeds a threshold. In at least one embodiment, once neuron  2702  fires, it may disregard previously received input information by, for example, resetting a membrane potential to 0 or another suitable default value. In at least one embodiment, once membrane potential is reset to 0, neuron  2702  may resume normal operation after a suitable period of time (or refractory period). 
     In at least one embodiment, neurons  2702  may be interconnected through synapses  2708 . In at least one embodiment, synapses  2708  may operate to transmit signals from an output of a first neuron  2702  to an input of a second neuron  2702 . In at least one embodiment, neurons  2702  may transmit information over more than one instance of synapse  2708 . In at least one embodiment, one or more instances of neuron output  2706  may be connected, via an instance of synapse  2708 , to an instance of neuron input  2704  in same neuron  2702 . In at least one embodiment, an instance of neuron  2702  generating an output to be transmitted over an instance of synapse  2708  may be referred to as a “pre-synaptic neuron” with respect to that instance of synapse  2708 . In at least one embodiment, an instance of neuron  2702  receiving an input transmitted over an instance of synapse  2708  may be referred to as a “post-synaptic neuron” with respect to that instance of synapse  2708 . Because an instance of neuron  2702  may receive inputs from one or more instances of synapse  2708 , and may also transmit outputs over one or more instances of synapse  2708 , a single instance of neuron  2702  may therefore be both a “pre-synaptic neuron” and “post-synaptic neuron,” with respect to various instances of synapses  2708 , in at least one embodiment. 
     In at least one embodiment, neurons  2702  may be organized into one or more layers. Each instance of neuron  2702  may have one neuron output  2706  that may fan out through one or more synapses  2708  to one or more neuron inputs  2704 . In at least one embodiment, neuron outputs  2706  of neurons  2702  in a first layer  2710  may be connected to neuron inputs  2704  of neurons  2702  in a second layer  2712 . In at least one embodiment, layer  2710  may be referred to as a “feed-forward layer.” In at least one embodiment, each instance of neuron  2702  in an instance of first layer  2710  may fan out to each instance of neuron  2702  in second layer  2712 . In at least one embodiment, first layer  2710  may be referred to as a “fully connected feed-forward layer.” In at least one embodiment, each instance of neuron  2702  in an instance of second layer  2712  may fan out to fewer than all instances of neuron  2702  in a third layer  2714 . In at least one embodiment, second layer  2712  may be referred to as a “sparsely connected feed-forward layer.” In at least one embodiment, neurons  2702  in second layer  2712  may fan out to neurons  2702  in multiple other layers, including to neurons  2702  in (same) second layer  2712 . In at least one embodiment, second layer  2712  may be referred to as a “recurrent layer.” Neuromorphic processor  2700  may include, without limitation, any suitable combination of recurrent layers and feed-forward layers, including, without limitation, both sparsely connected feed-forward layers and fully connected feed-forward layers. 
     In at least one embodiment, neuromorphic processor  2700  may include, without limitation, a reconfigurable interconnect architecture or dedicated hard wired interconnects to connect synapse  2708  to neurons  2702 . In at least one embodiment, neuromorphic processor  2700  may include, without limitation, circuitry or logic that allows synapses to be allocated to different neurons  2702  as needed based on neural network topology and neuron fan-in/out. For example, in at least one embodiment, synapses  2708  may be connected to neurons  2702  using an interconnect fabric, such as network-on-chip, or with dedicated connections. In at least one embodiment, synapse interconnections and components thereof may be implemented using circuitry or logic. 
       FIG. 28  is a block diagram of a processing system, according to at least one embodiment. In at least one embodiment, system  2800  includes one or more processors  2802  and one or more graphics processors  2808 , and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors  2802  or processor cores  2807 . In at least one embodiment, system  2800  is a processing platform incorporated within a system-on-a-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices. 
     In at least one embodiment, system  2800  can include, or be incorporated within a server-based gaming platform, a game console, including a game and media console, a mobile gaming console, a handheld game console, or an online game console. In at least one embodiment, system  2800  is a mobile phone, smart phone, tablet computing device or mobile Internet device. In at least one embodiment, processing system  2800  can also include, couple with, or be integrated within a wearable device, such as a smart watch wearable device, smart eyewear device, augmented reality device, or virtual reality device. In at least one embodiment, processing system  2800  is a television or set top box device having one or more processors  2802  and a graphical interface generated by one or more graphics processors  2808 . 
     In at least one embodiment, one or more processors  2802  each include one or more processor cores  2807  to process instructions which, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores  2807  is configured to process a specific instruction set  2809 . In at least one embodiment, instruction set  2809  may facilitate Complex Instruction Set Computing (CISC), Reduced Instruction Set Computing (RISC), or computing via a Very Long Instruction Word (VLIW). In at least one embodiment, processor cores  2807  may each process a different instruction set  2809 , which may include instructions to facilitate emulation of other instruction sets. In at least one embodiment, processor core  2807  may also include other processing devices, such a Digital Signal Processor (DSP). 
     In at least one embodiment, processor  2802  includes cache memory  2804 . In at least one embodiment, processor  2802  can have a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor  2802 . In at least one embodiment, processor  2802  also uses an external cache (e.g., a Level-3 (L3) cache or Last Level Cache (LLC)) (not shown), which may be shared among processor cores  2807  using known cache coherency techniques. In at least one embodiment, register file  2806  is additionally included in processor  2802  which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register file  2806  may include general-purpose registers or other registers. 
     In at least one embodiment, one or more processor(s)  2802  are coupled with one or more interface bus(es)  2810  to transmit communication signals such as address, data, or control signals between processor  2802  and other components in system  2800 . In at least one embodiment interface bus  2810 , in one embodiment, can be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, interface  2810  is not limited to a DMI bus, and may include one or more Peripheral Component Interconnect buses (e.g., PCI, PCI Express), memory busses, or other types of interface busses. In at least one embodiment processor(s)  2802  include an integrated memory controller  2816  and a platform controller hub  2830 . In at least one embodiment, memory controller  2816  facilitates communication between a memory device and other components of system  2800 , while platform controller hub (PCH)  2830  provides connections to I/O devices via a local I/O bus. 
     In at least one embodiment, memory device  2820  can be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, flash memory device, phase-change memory device, or some other memory device having suitable performance to serve as process memory. In at least one embodiment memory device  2820  can operate as system memory for system  2800 , to store data  2822  and instructions  2821  for use when one or more processors  2802  executes an application or process. In at least one embodiment, memory controller  2816  also couples with an optional external graphics processor  2812 , which may communicate with one or more graphics processors  2808  in processors  2802  to perform graphics and media operations. In at least one embodiment, a display device  2811  can connect to processor(s)  2802 . In at least one embodiment display device  2811  can include one or more of an internal display device, as in a mobile electronic device or a laptop device or an external display device attached via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device  2811  can include a head mounted display (HMD) such as a stereoscopic display device for use in virtual reality (VR) applications or augmented reality (AR) applications. 
     In at least one embodiment, platform controller hub  2830  enables peripherals to connect to memory device  2820  and processor  2802  via a high-speed I/O bus. In at least one embodiment, I/O peripherals include, but are not limited to, an audio controller  2846 , a network controller  2834 , a firmware interface  2828 , a wireless transceiver  2826 , touch sensors  2825 , a data storage device  2824  (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device  2824  can connect via a storage interface (e.g., SATA) or via a peripheral bus, such as a Peripheral Component Interconnect bus (e.g., PCI, PCI Express). In at least one embodiment, touch sensors  2825  can include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver  2826  can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, firmware interface  2828  enables communication with system firmware, and can be, for example, a unified extensible firmware interface (UEFI). In at least one embodiment, network controller  2834  can enable a network connection to a wired network. In at least one embodiment, a high-performance network controller (not shown) couples with interface bus  2810 . In at least one embodiment, audio controller  2846  is a multi-channel high definition audio controller. In at least one embodiment, system  2800  includes an optional legacy I/O controller  2840  for coupling legacy (e.g., Personal System 2 (PS/2)) devices to system. In at least one embodiment, platform controller hub  2830  can also connect to one or more Universal Serial Bus (USB) controllers  2842  connect input devices, such as keyboard and mouse  2843  combinations, a camera  2844 , or other USB input devices. 
     In at least one embodiment, an instance of memory controller  2816  and platform controller hub  2830  may be integrated into a discreet external graphics processor, such as external graphics processor  2812 . In at least one embodiment, platform controller hub  2830  and/or memory controller  2816  may be external to one or more processor(s)  2802 . For example, in at least one embodiment, system  2800  can include an external memory controller  2816  and platform controller hub  2830 , which may be configured as a memory controller hub and peripheral controller hub within a system chipset that is in communication with processor(s)  2802 . 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment portions or all of inference and/or training logic  915  may be incorporated into graphics processor  2800 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  2812 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A or 9B . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  2800  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment portions or all of inference and/or training logic  2  may be incorporated into graphics processor  2800 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  2812 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  2800  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 29  is a block diagram of a processor  2900  having one or more processor cores  2902 A- 2902 N, an integrated memory controller  2914 , and an integrated graphics processor  2908 , according to at least one embodiment. In at least one embodiment, processor  2900  can include additional cores up to and including additional core  2902 N represented by dashed lined boxes. In at least one embodiment, each of processor cores  2902 A- 2902 N includes one or more internal cache units  2904 A- 2904 N. In at least one embodiment, each processor core also has access to one or more shared cached units  2906 . 
     In at least one embodiment, internal cache units  2904 A- 2904 N and shared cache units  2906  represent a cache memory hierarchy within processor  2900 . In at least one embodiment, cache memory units  2904 A- 2904 N may include at least one level of instruction and data cache within each processor core and one or more levels of shared mid-level cache, such as a Level 2 (L2), Level 3 (L3), Level 4 (L4), or other levels of cache, where a highest level of cache before external memory is classified as an LLC. In at least one embodiment, cache coherency logic maintains coherency between various cache units  2906  and  2904 A- 2904 N. 
     In at least one embodiment, processor  2900  may also include a set of one or more bus controller units  2916  and a system agent core  2910 . In at least one embodiment, one or more bus controller units  2916  manage a set of peripheral buses, such as one or more PCI or PCI express busses. In at least one embodiment, system agent core  2910  provides management functionality for various processor components. In at least one embodiment, system agent core  2910  includes one or more integrated memory controllers  2914  to manage access to various external memory devices (not shown). 
     In at least one embodiment, one or more of processor cores  2902 A- 2902 N include support for simultaneous multi-threading. In at least one embodiment, system agent core  2910  includes components for coordinating and operating cores  2902 A- 2902 N during multi-threaded processing. In at least one embodiment, system agent core  2910  may additionally include a power control unit (PCU), which includes logic and components to regulate one or more power states of processor cores  2902 A- 2902 N and graphics processor  2908 . 
     In at least one embodiment, processor  2900  additionally includes graphics processor  2908  to execute graphics processing operations. In at least one embodiment, graphics processor  2908  couples with shared cache units  2906 , and system agent core  2910 , including one or more integrated memory controllers  2914 . In at least one embodiment, system agent core  2910  also includes a display controller  2911  to drive graphics processor output to one or more coupled displays. In at least one embodiment, display controller  2911  may also be a separate module coupled with graphics processor  2908  via at least one interconnect, or may be integrated within graphics processor  2908 . 
     In at least one embodiment, a ring based interconnect unit  2912  is used to couple internal components of processor  2900 . In at least one embodiment, an alternative interconnect unit may be used, such as a point-to-point interconnect, a switched interconnect, or other techniques. In at least one embodiment, graphics processor  2908  couples with ring interconnect  2912  via an I/O link  2913 . 
     In at least one embodiment, I/O link  2913  represents at least one of multiple varieties of I/O interconnects, including an on package I/O interconnect which facilitates communication between various processor components and a high-performance embedded memory module  2918 , such as an eDRAM module. In at least one embodiment, each of processor cores  2902 A- 2902 N and graphics processor  2908  use embedded memory modules  2918  as a shared Last Level Cache. 
     In at least one embodiment, processor cores  2902 A- 2902 N are homogenous cores executing a common instruction set architecture. In at least one embodiment, processor cores  2902 A- 2902 N are heterogeneous in terms of instruction set architecture (ISA), where one or more of processor cores  2902 A- 2902 N execute a common instruction set, while one or more other cores of processor cores  2902 A- 29 - 02 N executes a subset of a common instruction set or a different instruction set. In at least one embodiment, processor cores  2902 A- 2902 N are heterogeneous in terms of microarchitecture, where one or more cores having a relatively higher power consumption couple with one or more power cores having a lower power consumption. In at least one embodiment, processor  2900  can be implemented on one or more chips or as an SoC integrated circuit. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment portions or all of inference and/or training logic  915  may be incorporated into graphics processor  2910 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  2812 , graphics core(s)  2915 A, shared function logic  2916 , graphics core(s)  2915 B, shared function logic  2920 , or other logic in  FIG. 29 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A or 9B . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  2910  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment portions or all of inference and/or training logic  2  may be incorporated into graphics processor  2910 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  2812 , graphics core(s)  2915 A, shared function logic  2916 , graphics core(s)  2915 B, shared function logic  2920 , or other logic in  FIG. 29 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  2910  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 30  is a block diagram of a graphics processor  3000 , which may be a discrete graphics processing unit, or may be a graphics processor integrated with a plurality of processing cores. In at least one embodiment, graphics processor  3000  communicates via a memory mapped I/O interface to registers on graphics processor  3000  and with commands placed into memory. In at least one embodiment, graphics processor  3000  includes a memory interface  3014  to access memory. In at least one embodiment, memory interface  3014  is an interface to local memory, one or more internal caches, one or more shared external caches, and/or to system memory. 
     In at least one embodiment, graphics processor  3000  also includes a display controller  3002  to drive display output data to a display device  3020 . In at least one embodiment, display controller  3002  includes hardware for one or more overlay planes for display device  3020  and composition of multiple layers of video or user interface elements. In at least one embodiment, display device  3020  can be an internal or external display device. In at least one embodiment, display device  3020  is a head mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, graphics processor  3000  includes a video codec engine  3006  to encode, decode, or transcode media to, from, or between one or more media encoding formats, including, but not limited to Moving Picture Experts Group (MPEG) formats such as MPEG-2, Advanced Video Coding (AVC) formats such as H.264/MPEG-4 AVC, as well as the Society of Motion Picture &amp; Television Engineers (SMPTE) 421M/VC-1, and Joint Photographic Experts Group (JPEG) formats such as JPEG, and Motion JPEG (MJPEG) formats. 
     In at least one embodiment, graphics processor  3000  includes a block image transfer (BLIT) engine  3004  to perform two-dimensional (2D) rasterizer operations including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of graphics processing engine (GPE)  3010 . In at least one embodiment, GPE  3010  is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations. 
     In at least one embodiment, GPE  3010  includes a 3D pipeline  3012  for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act upon 3D primitive shapes (e.g., rectangle, triangle, etc.). 3D pipeline  3012  includes programmable and fixed function elements that perform various tasks and/or spawn execution threads to a 3D/Media sub-system  3015 . While 3D pipeline  3012  can be used to perform media operations, in at least one embodiment, GPE  3010  also includes a media pipeline  3016  that is used to perform media operations, such as video post-processing and image enhancement. 
     In at least one embodiment, media pipeline  3016  includes fixed function or programmable logic units to perform one or more specialized media operations, such as video decode acceleration, video de-interlacing, and video encode acceleration in place of, or on behalf of video codec engine  3006 . In at least one embodiment, media pipeline  3016  additionally includes a thread spawning unit to spawn threads for execution on 3D/Media sub-system  3015 . In at least one embodiment, spawned threads perform computations for media operations on one or more graphics execution units included in 3D/Media sub-system  3015 . 
     In at least one embodiment, 3D/Media subsystem  3015  includes logic for executing threads spawned by 3D pipeline  3012  and media pipeline  3016 . In at least one embodiment, 3D pipeline  3012  and media pipeline  3016  send thread execution requests to 3D/Media subsystem  3015 , which includes thread dispatch logic for arbitrating and dispatching various requests to available thread execution resources. In at least one embodiment, execution resources include an array of graphics execution units to process 3D and media threads. In at least one embodiment, 3D/Media subsystem  3015  includes one or more internal caches for thread instructions and data. In at least one embodiment, subsystem  3015  also includes shared memory, including registers and addressable memory, to share data between threads and to store output data. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment portions or all of inference and/or training logic  915  may be incorporated into graphics processor  3000 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3012 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A or 9B . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3000  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment portions or all of inference and/or training logic  1  may be incorporated into graphics processor  3000 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3012 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3000  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 31  is a block diagram of a graphics processing engine  3110  of a graphics processor in accordance with at least one embodiment. In at least one embodiment, graphics processing engine (GPE)  3110  is a version of GPE  3010  shown in  FIG. 30 . In at least one embodiment, media pipeline  3016  is optional and may not be explicitly included within GPE  3110 . In at least one embodiment, a separate media and/or image processor is coupled to GPE  3110 . 
     In at least one embodiment, GPE  3110  is coupled to or includes a command streamer  3103 , which provides a command stream to 3D pipeline  3012  and/or media pipelines  3016 . In at least one embodiment, command streamer  3103  is coupled to memory, which can be system memory, or one or more of internal cache memory and shared cache memory. In at least one embodiment, command streamer  3103  receives commands from memory and sends commands to 3D pipeline  3012  and/or media pipeline  3016 . In at least one embodiment, commands are instructions, primitives, or micro-operations fetched from a ring buffer, which stores commands for 3D pipeline  3012  and media pipeline  3016 . In at least one embodiment, a ring buffer can additionally include batch command buffers storing batches of multiple commands. In at least one embodiment, commands for 3D pipeline  3012  can also include references to data stored in memory, such as but not limited to vertex and geometry data for 3D pipeline  3012  and/or image data and memory objects for media pipeline  3016 . In at least one embodiment, 3D pipeline  3012  and media pipeline  3016  process commands and data by performing operations or by dispatching one or more execution threads to a graphics core array  3114 . In at least one embodiment graphics core array  3114  includes one or more blocks of graphics cores (e.g., graphics core(s)  3115 A, graphics core(s)  3115 B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources that includes general-purpose and graphics specific execution logic to perform graphics and compute operations, as well as fixed function texture processing and/or machine learning and artificial intelligence acceleration logic, including inference and/or training logic  915  in  FIG. 9A  and  FIG. 9B . 
     In at least one embodiment, 3D pipeline  3012  includes fixed function and programmable logic to process one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to graphics core array  3114 . In at least one embodiment, graphics core array  3114  provides a unified block of execution resources for use in processing shader programs. In at least one embodiment, multi-purpose execution logic (e.g., execution units) within graphics core(s)  3115 A- 3115 B of graphic core array  3114  includes support for various 3D API shader languages and can execute multiple simultaneous execution threads associated with multiple shaders. 
     In at least one embodiment, graphics core array  3114  also includes execution logic to perform media functions, such as video and/or image processing. In at least one embodiment, execution units additionally include general-purpose logic that is programmable to perform parallel general-purpose computational operations, in addition to graphics processing operations. 
     In at least one embodiment, output data generated by threads executing on graphics core array  3114  can output data to memory in a unified return buffer (URB)  3118 . URB  3118  can store data for multiple threads. In at least one embodiment, URB  3118  may be used to send data between different threads executing on graphics core array  3114 . In at least one embodiment, URB  3118  may additionally be used for synchronization between threads on graphics core array  3114  and fixed function logic within shared function logic  3120 . 
     In at least one embodiment, graphics core array  3114  is scalable, such that graphics core array  3114  includes a variable number of graphics cores, each having a variable number of execution units based on a target power and performance level of GPE  3110 . In at least one embodiment, execution resources are dynamically scalable, such that execution resources may be enabled or disabled as needed. 
     In at least one embodiment, graphics core array  3114  is coupled to shared function logic  3120  that includes multiple resources that are shared between graphics cores in graphics core array  3114 . In at least one embodiment, shared functions performed by shared function logic  3120  are embodied in hardware logic units that provide specialized supplemental functionality to graphics core array  3114 . In at least one embodiment, shared function logic  3120  includes but is not limited to sampler  3121 , math  3122 , and inter-thread communication (ITC)  3123  logic. In at least one embodiment, one or more cache(s)  3125  are in included in or couple to shared function logic  3120 . 
     In at least one embodiment, a shared function is used if demand for a specialized function is insufficient for inclusion within graphics core array  3114 . In at least one embodiment, a single instantiation of a specialized function is used in shared function logic  3120  and shared among other execution resources within graphics core array  3114 . In at least one embodiment, specific shared functions within shared function logic  3120  that are used extensively by graphics core array  3114  may be included within shared function logic  3116  within graphics core array  3114 . In at least one embodiment, shared function logic  3116  within graphics core array  3114  can include some or all logic within shared function logic  3120 . In at least one embodiment, all logic elements within shared function logic  3120  may be duplicated within shared function logic  3116  of graphics core array  3114 . In at least one embodiment, shared function logic  3120  is excluded in favor of shared function logic  3116  within graphics core array  3114 . 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment portions or all of inference and/or training logic  915  may be incorporated into graphics processor  3110 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3012 , graphics core(s)  3115 A, shared function logic  3116 , graphics core(s)  3115 B, shared function logic  3120 , or other logic in  FIG. 31 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A or 9B . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3110  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment portions or all of inference and/or training logic  1  may be incorporated into graphics processor  3110 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3012 , graphics core(s)  3115 A, shared function logic  3116 , graphics core(s)  3115 B, shared function logic  3120 , or other logic in  FIG. 31 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3110  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 32  is a block diagram of hardware logic of a graphics processor core  3200 , according to at least one embodiment described herein. In at least one embodiment, graphics processor core  3200  is included within a graphics core array. In at least one embodiment, graphics processor core  3200 , sometimes referred to as a core slice, can be one or multiple graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core  3200  is exemplary of one graphics core slice, and a graphics processor as described herein may include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core  3200  can include a fixed function block  3230  coupled with multiple sub-cores  3201 A- 3201 F, also referred to as sub-slices, that include modular blocks of general-purpose and fixed function logic. 
     In at least one embodiment, fixed function block  3230  includes a geometry/fixed function pipeline  3236  that can be shared by all sub-cores in graphics processor  3200 , for example, in lower performance and/or lower power graphics processor implementations. In at least one embodiment, geometry/fixed function pipeline  3236  includes a 3D fixed function pipeline, a video front-end unit, a thread spawner and thread dispatcher, and a unified return buffer manager, which manages unified return buffers. 
     In at least one embodiment fixed function block  3230  also includes a graphics SoC interface  3237 , a graphics microcontroller  3238 , and a media pipeline  3239 . Graphics SoC interface  3237  provides an interface between graphics core  3200  and other processor cores within a system on a chip integrated circuit. In at least one embodiment, graphics microcontroller  3238  is a programmable sub-processor that is configurable to manage various functions of graphics processor  3200 , including thread dispatch, scheduling, and pre-emption. In at least one embodiment, media pipeline  3239  includes logic to facilitate decoding, encoding, pre-processing, and/or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline  3239  implement media operations via requests to compute or sampling logic within sub-cores  3201 - 3201 F. 
     In at least one embodiment, SoC interface  3237  enables graphics core  3200  to communicate with general-purpose application processor cores (e.g., CPUs) and/or other components within an SoC, including memory hierarchy elements such as a shared last level cache memory, system RAM, and/or embedded on-chip or on-package DRAM. In at least one embodiment, SoC interface  3237  can also enable communication with fixed function devices within an SoC, such as camera imaging pipelines, and enables use of and/or implements global memory atomics that may be shared between graphics core  3200  and CPUs within an SoC. In at least one embodiment, SoC interface  3237  can also implement power management controls for graphics core  3200  and enable an interface between a clock domain of graphic core  3200  and other clock domains within an SoC. In at least one embodiment, SoC interface  3237  enables receipt of command buffers from a command streamer and global thread dispatcher that are configured to provide commands and instructions to each of one or more graphics cores within a graphics processor. In at least one embodiment, commands and instructions can be dispatched to media pipeline  3239 , when media operations are to be performed, or a geometry and fixed function pipeline (e.g., geometry and fixed function pipeline  3236 , geometry and fixed function pipeline  3214 ) when graphics processing operations are to be performed. 
     In at least one embodiment, graphics microcontroller  3238  can be configured to perform various scheduling and management tasks for graphics core  3200 . In at least one embodiment, graphics microcontroller  3238  can perform graphics and/or compute workload scheduling on various graphics parallel engines within execution unit (EU) arrays  3202 A- 3202 F,  3204 A- 3204 F within sub-cores  3201 A- 3201 F. In at least one embodiment, host software executing on a CPU core of an SoC including graphics core  3200  can submit workloads one of multiple graphic processor doorbells, which invokes a scheduling operation on an appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting a workload to a command streamer, pre-empting existing workloads running on an engine, monitoring progress of a workload, and notifying host software when a workload is complete. In at least one embodiment, graphics microcontroller  3238  can also facilitate low-power or idle states for graphics core  3200 , providing graphics core  3200  with an ability to save and restore registers within graphics core  3200  across low-power state transitions independently from an operating system and/or graphics driver software on a system. 
     In at least one embodiment, graphics core  3200  may have greater than or fewer than illustrated sub-cores  3201 A- 3201 F, up to N modular sub-cores. For each set of N sub-cores, in at least one embodiment, graphics core  3200  can also include shared function logic  3210 , shared and/or cache memory  3212 , a geometry/fixed function pipeline  3214 , as well as additional fixed function logic  3216  to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic  3210  can include logic units (e.g., sampler, math, and/or inter-thread communication logic) that can be shared by each N sub-cores within graphics core  3200 . Shared and/or cache memory  3212  can be a last-level cache for N sub-cores  3201 A- 3201 F within graphics core  3200  and can also serve as shared memory that is accessible by multiple sub-cores. In at least one embodiment, geometry/fixed function pipeline  3214  can be included instead of geometry/fixed function pipeline  3236  within fixed function block  3230  and can include same or similar logic units. 
     In at least one embodiment, graphics core  3200  includes additional fixed function logic  3216  that can include various fixed function acceleration logic for use by graphics core  3200 . In at least one embodiment, additional fixed function logic  3216  includes an additional geometry pipeline for use in position only shading. In position-only shading, at least two geometry pipelines exist, whereas in a full geometry pipeline within geometry/fixed function pipeline  3216 ,  3236 , and a cull pipeline, which is an additional geometry pipeline which may be included within additional fixed function logic  3216 . In at least one embodiment, cull pipeline is a trimmed down version of a full geometry pipeline. In at least one embodiment, a full pipeline and a cull pipeline can execute different instances of an application, each instance having a separate context. In at least one embodiment, position only shading can hide long cull runs of discarded triangles, enabling shading to be completed earlier in some instances. For example, in at least one embodiment, cull pipeline logic within additional fixed function logic  3216  can execute position shaders in parallel with a main application and generally generates critical results faster than a full pipeline, as cull pipeline fetches and shades position attribute of vertices, without performing rasterization and rendering of pixels to a frame buffer. In at least one embodiment, cull pipeline can use generated critical results to compute visibility information for all triangles without regard to whether those triangles are culled. In at least one embodiment, full pipeline (which in this instance may be referred to as a replay pipeline) can consume visibility information to skip culled triangles to shade only visible triangles that are finally passed to a rasterization phase. 
     In at least one embodiment, additional fixed function logic  3216  can also include machine-learning acceleration logic, such as fixed function matrix multiplication logic, for implementations including optimizations for machine learning training or inferencing. 
     In at least one embodiment, within each graphics sub-core  3201 A- 3201 F includes a set of execution resources that may be used to perform graphics, media, and compute operations in response to requests by graphics pipeline, media pipeline, or shader programs. In at least one embodiment, graphics sub-cores  3201 A- 3201 F include multiple EU arrays  3202 A- 3202 F,  3204 A- 3204 F, thread dispatch and inter-thread communication (TD/IC) logic  3203 A- 3203 F, a 3D (e.g., texture) sampler  3205 A- 3205 F, a media sampler  3206 A- 3206 F, a shader processor  3207 A- 3207 F, and shared local memory (SLM)  3208 A- 3208 F. EU arrays  3202 A- 3202 F,  3204 A- 3204 F each include multiple execution units, which are general-purpose graphics processing units capable of performing floating-point and integer/fixed-point logic operations in service of a graphics, media, or compute operation, including graphics, media, or compute shader programs. In at least one embodiment, TD/IC logic  3203 A- 3203 F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitate communication between threads executing on execution units of a sub-core. In at least one embodiment, 3D sampler  3205 A- 3205 F can read texture or other 3D graphics related data into memory. In at least one embodiment, 3D sampler can read texture data differently based on a configured sample state and texture format associated with a given texture. In at least one embodiment, media sampler  3206 A- 3206 F can perform similar read operations based on a type and format associated with media data. In at least one embodiment, each graphics sub-core  3201 A- 3201 F can alternately include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each of sub-cores  3201 A- 3201 F can make use of shared local memory  3208 A- 3208 F within each sub-core, to enable threads executing within a thread group to execute using a common pool of on-chip memory. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, portions or all of inference and/or training logic  915  may be incorporated into graphics processor  3210 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3210 , graphics microcontroller  3238 , geometry &amp; fixed function pipeline  3214  and  3236 , or other logic in  FIG. 29 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A or 9B . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3200  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment, portions or all of inference and/or training logic  1  may be incorporated into graphics processor  3210 . For example, in at least one embodiment, training and/or inferencing techniques described herein may use one or more of ALUs embodied in 3D pipeline  3210 , graphics microcontroller  3238 , geometry &amp; fixed function pipeline  3214  and  3236 , or other logic in  FIG. 29 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of graphics processor  3200  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIGS. 33A-33B  illustrate thread execution logic  3300  including an array of processing elements of a graphics processor core according to at least one embodiment.  FIG. 33A  illustrates at least one embodiment, in which thread execution logic  3300  is used.  FIG. 33B  illustrates exemplary internal details of an execution unit, according to at least one embodiment. 
     As illustrated in  FIG. 33A , in at least one embodiment, thread execution logic  3300  includes a shader processor  3302 , a thread dispatcher  3304 , instruction cache  3306 , a scalable execution unit array including a plurality of execution units  3308 A- 3308 N, a sampler  3310 , a data cache  3312 , and a data port  3314 . In at least one embodiment a scalable execution unit array can dynamically scale by enabling or disabling one or more execution units (e.g., any of execution unit  3308 A,  3308 B,  3308 C,  3308 D, through  3308 N- 1  and  3308 N) based on computational requirements of a workload, for example. In at least one embodiment, scalable execution units are interconnected via an interconnect fabric that links to each of execution unit. In at least one embodiment, thread execution logic  3300  includes one or more connections to memory, such as system memory or cache memory, through one or more of instruction cache  3306 , data port  3314 , sampler  3310 , and execution units  3308 A- 3308 N. In at least one embodiment, each execution unit (e.g.,  3308 A) is a stand-alone programmable general-purpose computational unit that is capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, array of execution units  3308 A- 3308 N is scalable to include any number individual execution units. 
     In at least one embodiment, execution units  3308 A- 3308 N are primarily used to execute shader programs. In at least one embodiment, shader processor  3302  can process various shader programs and dispatch execution threads associated with shader programs via a thread dispatcher  3304 . In at least one embodiment, thread dispatcher  3304  includes logic to arbitrate thread initiation requests from graphics and media pipelines and instantiate requested threads on one or more execution units in execution units  3308 A- 3308 N. For example, in at least one embodiment, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher  3304  can also process runtime thread spawning requests from executing shader programs. 
     In at least one embodiment, execution units  3308 A- 3308 N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. In at least one embodiment, execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each of execution units  3308 A- 3308 N, which include one or more arithmetic logic units (ALUs), is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. In at least one embodiment, execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. In at least one embodiment, while waiting for data from memory or one of shared functions, dependency logic within execution units  3308 A- 3308 N causes a waiting thread to sleep until requested data has been returned. In at least one embodiment, while a waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, in at least one embodiment, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. 
     In at least one embodiment, each execution unit in execution units  3308 A- 3308 N operates on arrays of data elements. In at least one embodiment, a number of data elements is “execution size,” or number of channels for an instruction. In at least one embodiment, an execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. In at least one embodiment, a number of channels may be independent of a number of physical Arithmetic Logic Units (ALUs) or Floating Point Units (FPUs) for a particular graphics processor. In at least one embodiment, execution units  3308 A- 3308 N support integer and floating-point data types. 
     In at least one embodiment, an execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored as a packed data type in a register and execution unit will process various elements based on data size of elements. For example, in at least one embodiment, when operating on a 256-bit wide vector, 256 bits of a vector are stored in a register and an execution unit operates on a vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible. 
     In at least one embodiment, one or more execution units can be combined into a fused execution unit  3309 A- 3309 N having thread control logic ( 3307 A- 3307 N) that is common to fused EUs. In at least one embodiment, multiple EUs can be fused into an EU group. In at least one embodiment, each EU in fused EU group can be configured to execute a separate SIMD hardware thread. Number of EUs in a fused EU group can vary according to various embodiments. In at least one embodiment, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit  3309 A- 3309 N includes at least two execution units. For example, in at least one embodiment, fused execution unit  3309 A includes a first EU  3308 A, second EU  3308 B, and thread control logic  3307 A that is common to first EU  3308 A and second EU  3308 B. In at least one embodiment, thread control logic  3307 A controls threads executed on fused graphics execution unit  3309 A, allowing each EU within fused execution units  3309 A- 3309 N to execute using a common instruction pointer register. 
     In at least one embodiment, one or more internal instruction caches (e.g.,  3306 ) are included in thread execution logic  3300  to cache thread instructions for execution units. In at least one embodiment, one or more data caches (e.g.,  3312 ) are included to cache thread data during thread execution. In at least one embodiment, a sampler  3310  is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler  3310  includes specialized texture or media sampling functionality to process texture or media data during sampling process before providing sampled data to an execution unit. 
     During execution, in at least one embodiment, graphics and media pipelines send thread initiation requests to thread execution logic  3300  via thread spawning and dispatch logic. In at least one embodiment, once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor  3302  is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In at least one embodiment, a pixel shader or fragment shader calculates values of various vertex attributes that are to be interpolated across a rasterized object. In at least one embodiment, pixel processor logic within shader processor  3302  then executes an application programming interface (API)-supplied pixel or fragment shader program. In at least one embodiment, to execute a shader program, shader processor  3302  dispatches threads to an execution unit (e.g.,  3308 A) via thread dispatcher  3304 . In at least one embodiment, shader processor  3302  uses texture sampling logic in sampler  3310  to access texture data in texture maps stored in memory. In at least one embodiment, arithmetic operations on texture data and input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing. 
     In at least one embodiment, data port  3314  provides a memory access mechanism for thread execution logic  3300  to output processed data to memory for further processing on a graphics processor output pipeline. In at least one embodiment, data port  3314  includes or couples to one or more cache memories (e.g., data cache  3312 ) to cache data for memory access via a data port. 
     As illustrated in  FIG. 33B , in at least one embodiment, a graphics execution unit  3308  can include an instruction fetch unit  3337 , a general register file array (GRF)  3324 , an architectural register file array (ARF)  3326 , a thread arbiter  3322 , a send unit  3330 , a branch unit  3332 , a set of SIMD floating point units (FPUs)  3334 , and In at least one embodiment a set of dedicated integer SIMD ALUs  3335 . In at least one embodiment, GRF  3324  and ARF  3326  includes a set of general register files and architecture register files associated with each simultaneous hardware thread that may be active in graphics execution unit  3308 . In at least one embodiment, per thread architectural state is maintained in ARF  3326 , while data used during thread execution is stored in GRF  3324 . In at least one embodiment, execution state of each thread, including instruction pointers for each thread, can be held in thread-specific registers in ARF  3326 . 
     In at least one embodiment, graphics execution unit  3308  has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). In at least one embodiment, architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. 
     In at least one embodiment, graphics execution unit  3308  can co-issue multiple instructions, which may each be different instructions. In at least one embodiment, thread arbiter  3322  of graphics execution unit thread  3308  can dispatch instructions to one of send unit  3330 , branch unit  3342 , or SIMD FPU(s)  3334  for execution. In at least one embodiment, each execution thread can access 128 general-purpose registers within GRF  3324 , where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In at least one embodiment, each execution unit thread has access to 4 Kbytes within GRF  3324 , although embodiments are not so limited, and greater or fewer register resources may be provided in other embodiments. In at least one embodiment, up to seven threads can execute simultaneously, although a number of threads per execution unit can also vary according to embodiments. In at least one embodiment, in which seven threads may access 4 Kbytes, GRF  3324  can store a total of 28 Kbytes. In at least one embodiment, flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures. 
     In at least one embodiment, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by message passing send unit  3330 . In at least one embodiment, branch instructions are dispatched to a dedicated branch unit  3332  to facilitate SIMD divergence and eventual convergence. 
     In at least one embodiment graphics execution unit  3308  includes one or more SIMD floating point units (FPU(s))  3334  to perform floating-point operations. In at least one embodiment, FPU(s)  3334  also support integer computation. In at least one embodiment FPU(s)  3334  can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In at least one embodiment, at least one of FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In at least one embodiment, a set of 8-bit integer SIMD ALUs  3335  are also present, and may be specifically optimized to perform operations associated with machine learning computations. 
     In at least one embodiment, arrays of multiple instances of graphics execution unit  3308  can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). In at least one embodiment execution unit  3308  can execute instructions across a plurality of execution channels. In at least one embodiment, each thread executed on graphics execution unit  3308  is executed on a different channel. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, portions or all of inference and/or training logic  915  may be incorporated into execution logic  3300 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 9A  or  9 B. In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of execution logic  3300  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
     In at least one embodiment, portions or all of inference and/or training logic  1  may be incorporated into execution logic  3300 . Moreover, in at least one embodiment, inferencing and/or training operations described herein may be done using logic other than logic illustrated in  FIG. 1 or 2 . In at least one embodiment, weight parameters may be stored in on-chip or off-chip memory and/or registers (shown or not shown) that configure ALUs of execution logic  3300  to perform one or more machine learning algorithms, neural network architectures, use cases, or training techniques described herein. 
       FIG. 34  illustrates a parallel processing unit (“PPU”)  3400 , according to at least one embodiment. In at least one embodiment, PPU  3400  is configured with machine-readable code that, if executed by PPU  3400 , causes PPU  3400  to perform some or all of processes and techniques described throughout this disclosure. In at least one embodiment, PPU  3400  is a multi-threaded processor that is implemented on one or more integrated circuit devices and that utilizes multithreading as a latency-hiding technique designed to process computer-readable instructions (also referred to as machine-readable instructions or simply instructions) on multiple threads in parallel. In at least one embodiment, a thread refers to a thread of execution and is an instantiation of a set of instructions configured to be executed by PPU  3400 . In at least one embodiment, PPU  3400  is a graphics processing unit (“GPU”) configured to implement a graphics rendering pipeline for processing three-dimensional (“3D”) graphics data in order to generate two-dimensional (“2D”) image data for display on a display device such as a liquid crystal display (“LCD”) device. In at least one embodiment, PPU  3400  is utilized to perform computations such as linear algebra operations and machine-learning operations.  FIG. 34  illustrates an example parallel processor for illustrative purposes only and should be construed as a non-limiting example of processor architectures contemplated within scope of this disclosure and that any suitable processor may be employed to supplement and/or substitute for same. 
     In at least one embodiment, one or more PPUs  3400  are configured to accelerate High Performance Computing (“HPC”), data center, and machine learning applications. In at least one embodiment, PPU  3400  is configured to accelerate deep learning systems and applications including following non-limiting examples: autonomous vehicle platforms, deep learning, high-accuracy speech, image, text recognition systems, intelligent video analytics, molecular simulations, drug discovery, disease diagnosis, weather forecasting, big data analytics, astronomy, molecular dynamics simulation, financial modeling, robotics, factory automation, real-time language translation, online search optimizations, and personalized user recommendations, and more. 
     In at least one embodiment, PPU  3400  includes, without limitation, an Input/Output (“I/O”) unit  3406 , a front-end unit  3410 , a scheduler unit  3412 , a work distribution unit  3414 , a hub  3416 , a crossbar (“Xbar”)  3420 , one or more general processing clusters (“GPCs”)  3418 , and one or more partition units (“memory partition units”)  3422 . In at least one embodiment, PPU  3400  is connected to a host processor or other PPUs  3400  via one or more high-speed GPU interconnects (“GPU interconnects”)  3408 . In at least one embodiment, PPU  3400  is connected to a host processor or other peripheral devices via an interconnect  3402 . In at least one embodiment, PPU  3400  is connected to a local memory comprising one or more memory devices (“memory”)  3404 . In at least one embodiment, memory devices  3404  include, without limitation, one or more dynamic random access memory (“DRAM”) devices. In at least one embodiment, one or more DRAM devices are configured and/or configurable as high-bandwidth memory (“HBM”) subsystems, with multiple DRAM dies stacked within each device. 
     In at least one embodiment, high-speed GPU interconnect  3408  may refer to a wire-based multi-lane communications link that is used by systems to scale and include one or more PPUs  3400  combined with one or more central processing units (“CPUs”), supports cache coherence between PPUs  3400  and CPUs, and CPU mastering. In at least one embodiment, data and/or commands are transmitted by high-speed GPU interconnect  3408  through hub  3416  to/from other units of PPU  3400  such as one or more copy engines, video encoders, video decoders, power management units, and other components which may not be explicitly illustrated in  FIG. 34 . 
     In at least one embodiment, I/O unit  3406  is configured to transmit and receive communications (e.g., commands, data) from a host processor (not illustrated in  FIG. 34 ) over system bus  3402 . In at least one embodiment, I/O unit  3406  communicates with host processor directly via system bus  3402  or through one or more intermediate devices such as a memory bridge. In at least one embodiment, I/O unit  3406  may communicate with one or more other processors, such as one or more of PPUs  3400  via system bus  3402 . In at least one embodiment, I/O unit  3406  implements a Peripheral Component Interconnect Express (“PCIe”) interface for communications over a PCIe bus. In at least one embodiment, I/O unit  3406  implements interfaces for communicating with external devices. 
     In at least one embodiment, I/O unit  3406  decodes packets received via system bus  3402 . In at least one embodiment, at least some packets represent commands configured to cause PPU  3400  to perform various operations. In at least one embodiment, I/O unit  3406  transmits decoded commands to various other units of PPU  3400  as specified by commands. In at least one embodiment, commands are transmitted to front-end unit  3410  and/or transmitted to hub  3416  or other units of PPU  3400  such as one or more copy engines, a video encoder, a video decoder, a power management unit, etc. (not explicitly illustrated in  FIG. 34 ). In at least one embodiment, I/O unit  3406  is configured to route communications between and among various logical units of PPU  3400 . 
     In at least one embodiment, a program executed by host processor encodes a command stream in a buffer that provides workloads to PPU  3400  for processing. In at least one embodiment, a workload comprises instructions and data to be processed by those instructions. In at least one embodiment, buffer is a region in a memory that is accessible (e.g., read/write) by both host processor and PPU  3400 —a host interface unit may be configured to access buffer in a system memory connected to system bus  3402  via memory requests transmitted over system bus  3402  by I/O unit  3406 . In at least one embodiment, host processor writes command stream to buffer and then transmits a pointer to start of command stream to PPU  3400  such that front-end unit  3410  receives pointers to one or more command streams and manages one or more command streams, reading commands from command streams and forwarding commands to various units of PPU  3400 . 
     In at least one embodiment, front-end unit  3410  is coupled to scheduler unit  3412  that configures various GPCs  3418  to process tasks defined by one or more command streams. In at least one embodiment, scheduler unit  3412  is configured to track state information related to various tasks managed by scheduler unit  3412  where state information may indicate which of GPCs  3418  a task is assigned to, whether task is active or inactive, a priority level associated with task, and so forth. In at least one embodiment, scheduler unit  3412  manages execution of a plurality of tasks on one or more of GPCs  3418 . 
     In at least one embodiment, scheduler unit  3412  is coupled to work distribution unit  3414  that is configured to dispatch tasks for execution on GPCs  3418 . In at least one embodiment, work distribution unit  3414  tracks a number of scheduled tasks received from scheduler unit  3412  and work distribution unit  3414  manages a pending task pool and an active task pool for each of GPCs  3418 . In at least one embodiment, pending task pool comprises a number of slots (e.g., 32 slots) that contain tasks assigned to be processed by a particular GPC  3418 ; active task pool may comprise a number of slots (e.g., 4 slots) for tasks that are actively being processed by GPCs  3418  such that as one of GPCs  3418  completes execution of a task, that task is evicted from active task pool for GPC  3418  and one of other tasks from pending task pool is selected and scheduled for execution on GPC  3418 . In at least one embodiment, if an active task is idle on GPC  3418 , such as while waiting for a data dependency to be resolved, then active task is evicted from GPC  3418  and returned to pending task pool while another task in pending task pool is selected and scheduled for execution on GPC  3418 . 
     In at least one embodiment, work distribution unit  3414  communicates with one or more GPCs  3418  via XBar  3420 . In at least one embodiment, XBar  3420  is an interconnect network that couples many of units of PPU  3400  to other units of PPU  3400  and can be configured to couple work distribution unit  3414  to a particular GPC  3418 . In at least one embodiment, one or more other units of PPU  3400  may also be connected to XBar  3420  via hub  3416 . 
     In at least one embodiment, tasks are managed by scheduler unit  3412  and dispatched to one of GPCs  3418  by work distribution unit  3414 . GPC  3418  is configured to process task and generate results. In at least one embodiment, results may be consumed by other tasks within GPC  3418 , routed to a different GPC  3418  via XBar  3420 , or stored in memory  3404 . In at least one embodiment, results can be written to memory  3404  via partition units  3422 , which implement a memory interface for reading and writing data to/from memory  3404 . In at least one embodiment, results can be transmitted to another PPU  3404  or CPU via high-speed GPU interconnect  3408 . In at least one embodiment, PPU  3400  includes, without limitation, a number U of partition units  3422  that is equal to number of separate and distinct memory devices  3404  coupled to PPU  3400 . In at least one embodiment, partition unit  3422  will be described in more detail herein in conjunction with  FIG. 36 . 
     In at least one embodiment, a host processor executes a driver kernel that implements an application programming interface (“API”) that enables one or more applications executing on host processor to schedule operations for execution on PPU  3400 . In at least one embodiment, multiple compute applications are simultaneously executed by PPU  3400  and PPU  3400  provides isolation, quality of service (“QoS”), and independent address spaces for multiple compute applications. In at least one embodiment, an application generates instructions (e.g., in form of API calls) that cause driver kernel to generate one or more tasks for execution by PPU  3400  and driver kernel outputs tasks to one or more streams being processed by PPU  3400 . In at least one embodiment, each task comprises one or more groups of related threads, which may be referred to as a warp. In at least one embodiment, a warp comprises a plurality of related threads (e.g., 32 threads) that can be executed in parallel. In at least one embodiment, cooperating threads can refer to a plurality of threads including instructions to perform task and that exchange data through shared memory. In at least one embodiment, threads and cooperating threads are described in more detail, in accordance with at least one embodiment, in conjunction with  FIG. 36 . 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to PPU  3400 . In at least one embodiment, deep learning application processor  3400  is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by PPU  3400 . In at least one embodiment, PPU  3400  may be used to perform one or more neural network use cases described herein. 
       FIG. 35  illustrates a general processing cluster (“GPC”)  3500 , according to at least one embodiment. In at least one embodiment, GPC  3500  is GPC  3418  of  FIG. 34 . In at least one embodiment, each GPC  3500  includes, without limitation, a number of hardware units for processing tasks and each GPC  3500  includes, without limitation, a pipeline manager  3502 , a pre-raster operations unit (“PROP”)  3504 , a raster engine  3508 , a work distribution crossbar (“WDX”)  3516 , a memory management unit (“MMU”)  3518 , one or more Data Processing Clusters (“DPCs”)  3506 , and any suitable combination of parts. 
     In at least one embodiment, operation of GPC  3500  is controlled by pipeline manager  3502 . In at least one embodiment, pipeline manager  3502  manages configuration of one or more DPCs  3506  for processing tasks allocated to GPC  3500 . In at least one embodiment, pipeline manager  3502  configures at least one of one or more DPCs  3506  to implement at least a portion of a graphics rendering pipeline. In at least one embodiment, DPC  3506  is configured to execute a vertex shader program on a programmable streaming multi-processor (“SM”)  3514 . In at least one embodiment, pipeline manager  3502  is configured to route packets received from a work distribution unit to appropriate logical units within GPC  3500 , in at least one embodiment, and some packets may be routed to fixed function hardware units in PROP  3504  and/or raster engine  3508  while other packets may be routed to DPCs  3506  for processing by a primitive engine  3512  or SM  3514 . In at least one embodiment, pipeline manager  3502  configures at least one of DPCs  3506  to implement a neural network model and/or a computing pipeline. 
     In at least one embodiment, PROP unit  3504  is configured, in at least one embodiment, to route data generated by raster engine  3508  and DPCs  3506  to a Raster Operations (“ROP”) unit in partition unit  3422 , described in more detail above in conjunction with  FIG. 34 . In at least one embodiment, PROP unit  3504  is configured to perform optimizations for color blending, organize pixel data, perform address translations, and more. In at least one embodiment, raster engine  3508  includes, without limitation, a number of fixed function hardware units configured to perform various raster operations, in at least one embodiment, and raster engine  3508  includes, without limitation, a setup engine, a coarse raster engine, a culling engine, a clipping engine, a fine raster engine, a tile coalescing engine, and any suitable combination thereof. In at least one embodiment, setup engine receives transformed vertices and generates plane equations associated with geometric primitive defined by vertices; plane equations are transmitted to coarse raster engine to generate coverage information (e.g., an x, y coverage mask for a tile) for primitive; output of coarse raster engine is transmitted to culling engine where fragments associated with primitive that fail a z-test are culled, and transmitted to a clipping engine where fragments lying outside a viewing frustum are clipped. In at least one embodiment, fragments that survive clipping and culling are passed to fine raster engine to generate attributes for pixel fragments based on plane equations generated by setup engine. In at least one embodiment, output of raster engine  3508  comprises fragments to be processed by any suitable entity such as by a fragment shader implemented within DPC  3506 . 
     In at least one embodiment, each DPC  3506  included in GPC  3500  comprise, without limitation, an M-Pipe Controller (“MPC”)  3510 ; primitive engine  3512 ; one or more SMs  3514 ; and any suitable combination thereof. In at least one embodiment, MPC  3510  controls operation of DPC  3506 , routing packets received from pipeline manager  3502  to appropriate units in DPC  3506 . In at least one embodiment, packets associated with a vertex are routed to primitive engine  3512 , which is configured to fetch vertex attributes associated with vertex from memory; in contrast, packets associated with a shader program may be transmitted to SM  3514 . 
     In at least one embodiment, SM  3514  comprises, without limitation, a programmable streaming processor that is configured to process tasks represented by a number of threads. In at least one embodiment, SM  3514  is multi-threaded and configured to execute a plurality of threads (e.g., 32 threads) from a particular group of threads concurrently and implements a Single-Instruction, Multiple-Data (“SIMD”) architecture where each thread in a group of threads (e.g., a warp) is configured to process a different set of data based on same set of instructions. In at least one embodiment, all threads in group of threads execute same instructions. In at least one embodiment, SM  3514  implements a Single-Instruction, Multiple Thread (“SIMT”) architecture wherein each thread in a group of threads is configured to process a different set of data based on same set of instructions, but where individual threads in group of threads are allowed to diverge during execution. In at least one embodiment, a program counter, call stack, and execution state is maintained for each warp, enabling concurrency between warps and serial execution within warps when threads within warp diverge. In another embodiment, a program counter, call stack, and execution state is maintained for each individual thread, enabling equal concurrency between all threads, within and between warps. In at least one embodiment, execution state is maintained for each individual thread and threads executing same instructions may be converged and executed in parallel for better efficiency. At least one embodiment of SM  3514  are described in more detail herein. 
     In at least one embodiment, MMU  3518  provides an interface between GPC  3500  and memory partition unit (e.g., partition unit  3422  of  FIG. 34 ) and MMU  3518  provides translation of virtual addresses into physical addresses, memory protection, and arbitration of memory requests. In at least one embodiment, MMU  3518  provides one or more translation lookaside buffers (“TLBs”) for performing translation of virtual addresses into physical addresses in memory. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to GPC  3500 . In at least one embodiment, GPC  3500  is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by GPC  3500 . In at least one embodiment, GPC  3500  may be used to perform one or more neural network use cases described herein. 
       FIG. 36  illustrates a memory partition unit  3600  of a parallel processing unit (“PPU”), in a36ordance with at least one embodiment. In at least one embodiment, memory partition unit  3600  includes, without limitation, a Raster Operations (“ROP”) unit  3602 ; a level two (“L2”) cache  3604 ; a memory interface  3606 ; and any suitable combination thereof. Memory interface  3606  is coupled to memory. Memory interface  3606  may implement 32, 64, 128, 1024-bit data buses, or like, for high-speed data transfer. In at least one embodiment, PPU incorporates U memory interfaces  3606 , one memory interface  3606  per pair of partition units  3600 , where each pair of partition units  3600  is connected to a corresponding memory device. For example, in at least one embodiment, PPU may be connected to up to Y memory devices, such as high bandwidth memory stacks or graphics double-data-rate, version 5, synchronous dynamic random a36ess memory (“GDDR5 SDRAM”). 
     In at least one embodiment, memory interface  3606  implements a high bandwidth memory second generation (“HBM2”) memory interface and Y equals half U. In at least one embodiment, HBM2 memory stacks are located on same physical package as PPU, providing substantial power and area savings compared with conventional GDDR5 SDRAM systems. In at least one embodiment, each HBM2 stack includes, without limitation, four memory dies and Y equals 4, with each HBM2 stack including two 128-bit channels per die for a total of 8 channels and a data bus width of 1024 bits. In at least one embodiment, memory supports Single-Error Correcting Double-Error Detecting (“SECDED”) Error Correction Code (“ECC”) to protect data. ECC provides higher reliability for compute applications that are sensitive to data corruption. 
     In at least one embodiment, PPU implements a multi-level memory hierarchy. In at least one embodiment, memory partition unit  3600  supports a unified memory to provide a single unified virtual address space for central processing unit (“CPU”) and PPU memory, enabling data sharing between virtual memory systems. In at least one embodiment frequency of a36esses by a PPU to memory located on other processors is traced to ensure that memory pages are moved to physical memory of PPU that is a36essing pages more frequently. In at least one embodiment, high-speed GPU interconnect  3408  supports address translation services allowing PPU to directly a36ess a CPU&#39;s page tables and providing full a36ess to CPU memory by PPU. 
     In at least one embodiment, copy engines transfer data between multiple PPUs or between PPUs and CPUs. In at least one embodiment, copy engines can generate page faults for addresses that are not mapped into page tables and memory partition unit  3600  then services page faults, mapping addresses into page table, after which copy engine performs transfer. In at least one embodiment, memory is pinned (i.e., non-pageable) for multiple copy engine operations between multiple processors, substantially reducing available memory. In at least one embodiment, with hardware page faulting, addresses can be passed to copy engines without regard as to whether memory pages are resident, and copy process is transparent. 
     Data from memory  3404  of  FIG. 34  or other system memory is fetched by memory partition unit  3600  and stored in L2 cache  3604 , which is located on-chip and is shared between various GPCs, in a36ordance with at least one embodiment. Each memory partition unit  3600 , in at least one embodiment, includes, without limitation, at least a portion of L2 cache associated with a corresponding memory device. In at least one embodiment, lower level caches are implemented in various units within GPCs. In at least one embodiment, each of SMs  3514  may implement a level one (“L1”) cache wherein L1 cache is private memory that is dedicated to a particular SM  3514  and data from L2 cache  3604  is fetched and stored in each of L1 caches for processing in functional units of SMs  3514 . In at least one embodiment, L2 cache  3604  is coupled to memory interface  3606  and XBar  3420 . 
     ROP unit  3602  performs graphics raster operations related to pixel color, such as color compression, pixel blending, and more, in at least one embodiment. ROP unit  3602 , in at least one embodiment, implements depth testing in conjunction with raster engine  3508 , receiving a depth for a sample location associated with a pixel fragment from culling engine of raster engine  3508 . In at least one embodiment, depth is tested against a corresponding depth in a depth buffer for a sample location associated with fragment. In at least one embodiment, if fragment passes depth test for sample location, then ROP unit  3602  updates depth buffer and transmits a result of depth test to raster engine  3508 . It will be appreciated that number of partition units  3600  may be different than number of GPCs and, therefore, each ROP unit  3602  can, in at least one embodiment, be coupled to each of GPCs. In at least one embodiment, ROP unit  3602  tracks packets received from different GPCs and determines which that a result generated by ROP unit  3602  is routed to through XBar  3420 . 
       FIG. 37  illustrates a streaming multi-processor (“SM”)  3700 , according to at least one embodiment. In at least one embodiment, SM  3700  is SM of  FIG. 35 . In at least one embodiment, SM  3700  includes, without limitation, an instruction cache  3702 ; one or more scheduler units  3704 ; a register file  3708 ; one or more processing cores (“cores”)  3710 ; one or more special function units (“SFUs”)  3712 ; one or more load/store units (“LSUs”)  3714 ; an interconnect network  3716 ; a shared memory/level one (“L1”) cache  3718 ; and any suitable combination thereof. In at least one embodiment, a work distribution unit dispatches tasks for execution on general processing clusters (“GPCs”) of parallel processing units (“PPUs”) and each task is allocated to a particular Data Processing Cluster (“DPC”) within a GPC and, if task is associated with a shader program, task is allocated to one of SMs  3700 . In at least one embodiment, scheduler unit  3704  receives tasks from work distribution unit and manages instruction scheduling for one or more thread blocks assigned to SM  3700 . In at least one embodiment, scheduler unit  3704  schedules thread blocks for execution as warps of parallel threads, wherein each thread block is allocated at least one warp. In at least one embodiment, each warp executes threads. In at least one embodiment, scheduler unit  3704  manages a plurality of different thread blocks, allocating warps to different thread blocks and then dispatching instructions from plurality of different cooperative groups to various functional units (e.g., processing cores  3710 , SFUs  3712 , and LSUs  3714 ) during each clock cycle. 
     In at least one embodiment, Cooperative Groups may refer to a programming model for organizing groups of communicating threads that allows developers to express granularity at which threads are communicating, enabling expression of richer, more efficient parallel decompositions. In at least one embodiment, cooperative launch APIs support synchronization amongst thread blocks for execution of parallel algorithms. In at least one embodiment, applications of conventional programming models provide a single, simple construct for synchronizing cooperating threads: a barrier across all threads of a thread block (e.g., syncthreads( ) function). However, in at least one embodiment, programmers may define groups of threads at smaller than thread block granularities and synchronize within defined groups to enable greater performance, design flexibility, and software reuse in form of collective group-wide function interfaces. In at least one embodiment, Cooperative Groups enables programmers to define groups of threads explicitly at sub-block (i.e., as small as a single thread) and multi-block granularities, and to perform collective operations such as synchronization on threads in a cooperative group. Programming model supports clean composition across software boundaries, so that libraries and utility functions can synchronize safely within their local context without having to make assumptions about convergence. In at least one embodiment, Cooperative Groups primitives enable new patterns of cooperative parallelism, including, without limitation, producer-consumer parallelism, opportunistic parallelism, and global synchronization across an entire grid of thread blocks. 
     In at least one embodiment, a dispatch unit  3706  is configured to transmit instructions to one or more of functional units and scheduler unit  3704  includes, without limitation, two dispatch units  3706  that enable two different instructions from same warp to be dispatched during each clock cycle. In at least one embodiment, each scheduler unit  3704  includes a single dispatch unit  3706  or a37itional dispatch units  3706 . 
     In at least one embodiment, each SM  3700 , in at least one embodiment, includes, without limitation, register file  3708  that provides a set of registers for functional units of SM  3700 . In at least one embodiment, register file  3708  is divided between each of functional units such that each functional unit is allocated a dedicated portion of register file  3708 . In at least one embodiment, register file  3708  is divided between different warps being executed by SM  3700  and register file  3708  provides temporary storage for operands connected to data paths of functional units. In at least one embodiment, each SM  3700  comprises, without limitation, a plurality of L processing cores  3710 . In at least one embodiment, SM  3700  includes, without limitation, a large number (e.g., 128 or more) of distinct processing cores  3710 . In at least one embodiment, each processing core  3710 , in at least one embodiment, includes, without limitation, a fully-pipelined, single-precision, double-precision, and/or mixed precision processing unit that includes, without limitation, a floating point arithmetic logic unit and an integer arithmetic logic unit. In at least one embodiment, floating point arithmetic logic units implement IEEE 754-2008 standard for floating point arithmetic. In at least one embodiment, processing cores  3710  include, without limitation, 64 single-precision (32-bit) floating point cores, 64 integer cores, 32 double-precision (64-bit) floating point cores, and 8 tensor cores. 
     Tensor cores are configured to perform matrix operations in accordance with at least one embodiment. In at least one embodiment, one or more tensor cores are included in processing cores  3710 . In at least one embodiment, tensor cores are configured to perform deep learning matrix arithmetic, such as convolution operations for neural network training and inferencing. In at least one embodiment, each tensor core operates on a 4×4 matrix and performs a matrix multiply and accumulate operation D=A×B+C, where A, B, C, and D are 4×4 matrices. 
     In at least one embodiment, matrix multiply inputs A and B are 16-bit floating point matrices and accumulation matrices C and D are 16-bit floating point or 32-bit floating point matrices. In at least one embodiment, tensor cores operate on 16-bit floating point input data with 32-bit floating point accumulation. In at least one embodiment, 16-bit floating point multiply uses 64 operations and results in a full precision product that is then accumulated using 32-bit floating point a37ition with other intermediate products for a 4×4×4 matrix multiply. Tensor cores are used to perform much larger two-dimensional or higher dimensional matrix operations, built up from these smaller elements, in at least one embodiment. In at least one embodiment, an API, such as CUDA 9 C++ API, exposes specialized matrix load, matrix multiply and accumulate, and matrix store operations to efficiently use tensor cores from a CUDA-C++ program. In at least one embodiment, at CUDA level, warp-level interface assumes 16×16 size matrices spanning all 32 threads of warp. 
     In at least one embodiment, each SM  3700  comprises, without limitation, M SFUs  3712  that perform special functions (e.g., attribute evaluation, reciprocal square root, and like). In at least one embodiment, SFUs  3712  include, without limitation, a tree traversal unit configured to traverse a hierarchical tree data structure. In at least one embodiment, SFUs  3712  include, without limitation, a texture unit configured to perform texture map filtering operations. In at least one embodiment, texture units are configured to load texture maps (e.g., a 2D array of texels) from memory and sample texture maps to produce sampled texture values for use in shader programs executed by SM  3700 . In at least one embodiment, texture maps are stored in shared memory/L1 cache  3718 . In at least one embodiment, texture units implement texture operations such as filtering operations using mip-maps (e.g., texture maps of varying levels of detail), in accordance with at least one embodiment. In at least one embodiment, each SM  3700  includes, without limitation, two texture units. 
     Each SM  3700  comprises, without limitation, N LSUs  3714  that implement load and store operations between shared memory/L1 cache  3718  and register file  3708 , in at least one embodiment. Each SM  3700  includes, without limitation, interconnect network  3716  that connects each of functional units to register file  3708  and LSU  3714  to register file  3708  and shared memory/L1 cache  3718  in at least one embodiment. In at least one embodiment, interconnect network  3716  is a crossbar that can be configured to connect any of functional units to any of registers in register file  3708  and connect LSUs  3714  to register file  3708  and memory locations in shared memory/L1 cache  3718 . 
     In at least one embodiment, shared memory/L1 cache  3718  is an array of on-chip memory that allows for data storage and communication between SM  3700  and primitive engine and between threads in SM  3700 , in at least one embodiment. In at least one embodiment, shared memory/L1 cache  3718  comprises, without limitation, 128 KB of storage capacity and is in path from SM  3700  to partition unit. In at least one embodiment, shared memory/L1 cache  3718 , in at least one embodiment, is used to cache reads and writes. In at least one embodiment, one or more of shared memory/L1 cache  3718 , L2 cache, and memory are backing stores. 
     Combining data cache and shared memory functionality into a single memory block provides improved performance for both types of memory accesses, in at least one embodiment. In at least one embodiment, capacity is used or is usable as a cache by programs that do not use shared memory, such as if shared memory is configured to use half of capacity, texture and load/store operations can use remaining capacity. Integration within shared memory/L1 cache  3718  enables shared memory/L1 cache  3718  to function as a high-throughput conduit for streaming data while simultaneously providing high-bandwidth and low-latency access to frequently reused data, in accordance with at least one embodiment. In at least one embodiment, when configured for general purpose parallel computation, a simpler configuration can be used compared with graphics processing. In at least one embodiment, fixed function graphics processing units are bypassed, creating a much simpler programming model. In general purpose parallel computation configuration, work distribution unit assigns and distributes blocks of threads directly to DPCs, in at least one embodiment. In at least one embodiment, threads in a block execute same program, using a unique thread ID in calculation to ensure each thread generates unique results, using SM  3700  to execute program and perform calculations, shared memory/L1 cache  3718  to communicate between threads, and LSU  3714  to read and write global memory through shared memory/L1 cache  3718  and memory partition unit. In at least one embodiment, when configured for general purpose parallel computation, SM  3700  writes commands that scheduler unit  3704  can use to launch new work on DPCs. 
     In at least one embodiment, PPU is included in or coupled to a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, and more. In at least one embodiment, PPU is embodied on a single semiconductor substrate. In at least one embodiment, PPU is included in a system-on-a-chip (“SoC”) along with one or more other devices such as additional PPUs, memory, a reduced instruction set computer (“RISC”) CPU, a memory management unit (“MMU”), a digital-to-analog converter (“DAC”), and like. 
     In at least one embodiment, PPU may be included on a graphics card that includes one or more memory devices. Graphics card may be configured to interface with a PCIe slot on a motherboard of a desktop computer. In at least one embodiment, PPU may be an integrated graphics processing unit (“iGPU”) included in chipset of motherboard. 
     Inference and/or training logic  915  are used to perform inferencing and/or training operations associated with one or more embodiments. Details regarding inference and/or training logic  915  are provided herein in conjunction with  FIGS. 9A and/or 9B . In at least one embodiment, deep learning application processor is used to train a machine learning model, such as a neural network, to predict or infer information provided to SM  3700 . In at least one embodiment, SM  3700  is used to infer or predict information based on a trained machine learning model (e.g., neural network) that has been trained by another processor or system or by SM  3700 . In at least one embodiment, SM  3700  may be used to perform one or more neural network use cases described herein. 
     In at least one embodiment, a single semiconductor platform may refer to a sole unitary semiconductor-based integrated circuit or chip. In at least one embodiment, multi-chip modules may be used with increased connectivity which simulate on-chip operation, and make substantial improvements over utilizing a conventional central processing unit (“CPU”) and bus implementation. In at least one embodiment, various modules may also be situated separately or in various combinations of semiconductor platforms per desires of user. 
     In at least one embodiment, computer programs in form of machine-readable executable code or computer control logic algorithms are stored in main memory  1504  and/or secondary storage. Computer programs, if executed by one or more processors, enable system  1500  to perform various functions in accordance with at least one embodiment. Memory  1504 , storage, and/or any other storage are possible examples of computer-readable media. In at least one embodiment, secondary storage may refer to any suitable storage device or system such as a hard disk drive and/or a removable storage drive, representing a floppy disk drive, a magnetic tape drive, a compact disk drive, digital versatile disk (“DVD”) drive, recording device, universal serial bus (“USB”) flash memory, etc. In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of CPU  1502 ; parallel processing system  1512 ; an integrated circuit capable of at least a portion of capabilities of both CPU  1502 ; parallel processing system  1512 ; a chipset (e.g., a group of integrated circuits designed to work and sold as a unit for performing related functions, etc.); and any suitable combination of integrated circuit(s). 
     In at least one embodiment, architecture and/or functionality of various previous figures are implemented in context of a general computer system, a circuit board system, a game console system dedicated for entertainment purposes, an application-specific system, and more. In at least one embodiment, computer system  1500  may take form of a desktop computer, a laptop computer, a tablet computer, servers, supercomputers, a smart-phone (e.g., a wireless, hand-held device), personal digital assistant (“PDA”), a digital camera, a vehicle, a head mounted display, a hand-held electronic device, a mobile phone device, a television, workstation, game consoles, embedded system, and/or any other type of logic. 
     In at least one embodiment, parallel processing system  1512  includes, without limitation, a plurality of parallel processing units (“PPUs”)  1514  and associated memories  1516 . In at least one embodiment, PPUs  1514  are connected to a host processor or other peripheral devices via an interconnect  1518  and a switch  1520  or multiplexer. In at least one embodiment, parallel processing system  1512  distributes computational tasks across PPUs  1514  which can be parallelizable—for example, as part of distribution of computational tasks across multiple graphics processing unit (“GPU”) thread blocks. In at least one embodiment, memory is shared and accessible (e.g., for read and/or write access) across some or all of PPUs  1514 , although such shared memory may incur performance penalties relative to use of local memory and registers resident to a PPU  1514 . In at least one embodiment, operation of PPUs  1514  is synchronized through use of a command such as _syncthreads( ), wherein all threads in a block (e.g., executed across multiple PPUs  1514 ) to reach a certain point of execution of code before proc15ding. 
     Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit disclosure to specific form or forms disclosed, but on contrary, intention is to cover all modifications, alternative constructions, and equivalents falling within spirit and scope of disclosure, as defined in appended claims. 
     Use of terms “a” and “an” and “the” and similar referents in context of describing disclosed embodiments (especially in context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. term “connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitation of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within range, unless otherwise indicated herein and each separate value is incorporated into specification as if it were individually recited herein. Use of term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising one or more members. Further, unless otherwise noted or contradicted by context, term “subset” of a corresponding set does not necessarily denote a proper subset of corresponding set, but subset and corresponding set may be equal. 
     Conjunctive language, such as phrases of form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with context as used in general to present that an item, term, etc., may be either A or B or C, or any nonempty subset of set of A and B and C. For instance, in illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of following sets: {A}, {B}, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain embodiments require at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). Number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, phrase “based on” means “based at least in part on” and not “based solely on.” 
     Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and/or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, when executed (i.e., as a result of being executed) by one or more processors of a computer system, cause computer system to perform operations described herein. Set of non-transitory computer-readable storage media, in at least one embodiment, comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of code while multiple non-transitory computer-readable storage media collectively store all of code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors—for example, a non-transitory computer-readable storage medium store instructions and a main central processing unit (“CPU”) executes some of instructions while a graphics processing unit (“GPU”) executes other instructions. In at least one embodiment, different components of a computer system have separate processors and different processors execute different subsets of instructions. 
     Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and/or software that enable performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations. 
     Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of disclosure and does not pose a limitation on scope of disclosure unless otherwise claimed. No language in specification should be construed as indicating any non-claimed element as essential to practice of disclosure. 
     All references, including publications, patent applications, and patents, cited herein are hereby incorporated by reference to same extent as if each reference were individually and specifically indicated to be incorporated by reference and were set forth in its entirety herein. 
     In description and claims, terms “coupled” and “connected,” along with their derivatives, may be used. It should be understood that these terms may be not intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” may be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other. 
     Unless specifically stated otherwise, it may be appreciated that throughout specification terms such as “processing,” “computing,” “calculating,” “determining,” or like, refer to action and/or processes of a computer or computing system, or similar electronic computing device, that manipulate and/or transform data represented as physical, such as electronic, quantities within computing system&#39;s registers and/or memories into other data similarly represented as physical quantities within computing system&#39;s memories, registers or other such information storage, transmission or display devices. 
     In a similar manner, term “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory and transform that electronic data into other electronic data that may be stored in registers and/or memory. As non-limiting examples, “processor” may be a CPU or a GPU. A “computing platform” may comprise one or more processors. As used herein, “software” processes may include, for example, software and/or hardware entities that perform work over time, such as tasks, threads, and intelligent agents. Also, each process may refer to multiple processes, for carrying out instructions in sequence or in parallel, continuously or intermittently. Terms “system” and “method” are used herein interchangeably insofar as system may embody one or more methods and methods may be considered a system. 
     In present document, references may be made to obtaining, acquiring, receiving, or inputting analog or digital data into a subsystem, computer system, or computer-implemented machine. Process of obtaining, acquiring, receiving, or inputting analog and digital data can be accomplished in a variety of ways such as by receiving data as a parameter of a function call or a call to an application programming interface. In some implementations, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a serial or parallel interface. In another implementation, process of obtaining, acquiring, receiving, or inputting analog or digital data can be accomplished by transferring data via a computer network from providing entity to acquiring entity. References may also be made to providing, outputting, transmitting, sending, or presenting analog or digital data. In various examples, process of providing, outputting, transmitting, sending, or presenting analog or digital data can be accomplished by transferring data as an input or output parameter of a function call, a parameter of an application programming interface or interprocess communication mechanism. 
     Although discussion above sets forth example implementations of described techniques, other architectures may be used to implement described functionality, and are intended to be within scope of this disclosure. Furthermore, although specific distributions of responsibilities are defined above for purposes of discussion, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances. 
     Furthermore, although subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.