Patent Publication Number: US-7592933-B2

Title: Techniques for 9B10B and 7B8B coding and decoding

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is a continuation of U.S. patent application Ser. No. 11/668,549, filed Jan. 30, 2007, now U.S. Pat No. 7,405,679 the complete disclosure of which is expressly incorporated by reference herein in its entirety for all purposes. 

   FIELD OF THE INVENTION 
   The present invention generally relates to communications systems and, more particularly, to encoding and decoding techniques. 
   BACKGROUND OF THE INVENTION 
   Coding is employed in communications systems for a variety of purposes Among these are the improvement of transmission reliability, DC balance, the detection of errors, and the correction of errors. U.S. Pat. Nos. 6,198,413 and 6,614,369, both to Albert X Widmer, describe the principles for the construction of a 16B16B transmission code which is partitioned into a 9B10B and a 7B8B part For high speed bus applications as described in U.S. Pat. No. 6,978,416, also to Albert X Widmer, the compatibility with an 8-bit byte format is often not an advantage or irrelevant for very wide busses with dozens of parallel lines. The higher coding efficiency and other features may outweigh the lower complexity of the traditional 8B10B code, known, for example, from Albert X Widmer, The ANSI Fibre Channel Transmission Code, IBM Research Report RC 18855, 4/23/93, and U.S. Pat. Nos. 4,486,739, of Franaszek and Widmer, and 6,977,599, of Albert X Widmer. 
   Various versions of 7B8B codes have been used by British Telecom, as known from J R. Alexander and A. S. T. Nagra, “Transformation of binary coded signals into a form having lower disparity”, British Patent 1540617, 14 Feb. 1979, and P. Cochrane, R. Brooks, and R. Dawes, “A High Reliability 565 Mbit/s Trunk Transmission System, ” IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL. SAC-4, NO. 9, December 1986, pp. 1396-1403, and by Standard Telephones and Communications plc, as known from R L Williamson and M Chown, “The NL1 Submarine System,” IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, VOL SAC-1, NO 3, April 1983, pp. 454-458. A coding table for one such version is listed in A. J. Sharland and A. Stevenson, “A simple in-service error detection scheme based on the statistical properties of line codes for optical fibre Systems,” INT. J. ELECTRONICS, 1983, VOL. 55, NO. 1, 3-33. It is not suitable for implementation with combinational logic elements. A good general introduction to this kind of line coding is given in K. W. Cattermole, “Principles of digital line coding,” INT J. ELECTRONICS, 1983, VOL 55, NO. 1, 3-33, and in R. M. Brooks and A. Jessop, “Line coding for optical fibre systems”, INT. J. ELECTRONICS, 1983, VOL 55, NO. 1, 81-120. 
   It would be desirable to provide both a 9B10B coding implementation and a 7B8B coding implementation that can be efficiently implemented in hardware. 
   SUMMARY OF THE INVENTION 
   Principles of the present invention provide techniques for implementing one or more coding and decoding schemes. An exemplary method of encoding 9-binary symbol (9B) source vectors into 10-binary symbol (10B) encoded vectors, according to one aspect of the invention, includes the steps of obtaining a plurality of 9B source vectors, and encoding the 9B source vectors into a plurality of 10B encoded vectors according to an encoding scheme. The 10B encoded vectors include at least 10B encoded data vectors (i.e., control vectors could be included in addition to the data vectors). The encoding scheme maps at least a first portion of the 9B source vectors into 10B encoded data vectors comprising disparity independent encoded vectors. The encoding scheme mapping at least a second portion of the 9B source vectors into 10B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations. The 10B encoded data vectors have one binary symbol appended thereto by the encoding scheme. A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors, the fraction not including any of the disparity dependent encoded representations. 
   In another aspect an exemplary method of decoding 10-binary symbol (10B) encoded vectors into decoded 9-binary symbol (9B) source vectors includes the steps of obtaining a plurality of 10B encoded vectors that were encoded from a plurality of 9B source vectors according to an encoding scheme of the kind just described, and decoding the 10B encoded vectors into a plurality of 9B source vectors according to decoding rules of the encoding scheme. 
   In still another aspect, an exemplary method of encoding 7-binary symbol (7B) source vectors into 8-binary symbol (8B) encoded vectors, according to one aspect of the invention, includes the steps of obtaining a plurality of 7B source vectors, and encoding the 7B source vectors into a plurality of 8B encoded vectors according to an encoding scheme. The 8B encoded vectors include at least 8B encoded data vectors (i.e., control vectors could be included in addition to the data vectors). The encoding scheme maps at least a first portion of the 7B source vectors into 8B encoded data vectors comprising disparity independent encoded vectors. The encoding scheme mapping at least a second portion of the 7B source vectors into 8B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations The 8B encoded data vectors have one binary symbol appended thereto by the encoding scheme. A fraction of the 8B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 7B source vectors, the fraction not including any of the disparity dependent encoded representations. 
   In yet another aspect, an exemplary method of decoding 8-binary symbol (8B) encoded vectors into decoded 7-binary symbol (7B) source vectors includes the steps of obtaining a plurality of 8B encoded vectors that were encoded from a plurality of 7B source vectors according to an encoding scheme of the kind just described, and decoding the 8B encoded vectors into a plurality of 7B source vectors according to decoding rules of the encoding scheme. 

   
     These and other aspects of the invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  depicts trellis diagrams similar to those of U.S. Pat. Nos. 6,198,413 and 6,614,369, modified in accordance with an aspect of the invention; 
       FIG. 2A  shows an exemplary conceptual view of the flow of 9B10B encoding, according to an aspect of the invention; 
       FIG. 2B  shows a circuit block diagram of an exemplary circuit for 9B10B encoding, according to an aspect of the invention; 
       FIG. 3A  shows an exemplary conceptual view of the flow of 9B10B decoding, according to an aspect of the invention; 
       FIG. 3B  shows a circuit block diagram of an exemplary circuit for 9B10B decoding, according to an aspect of the invention; 
       FIG. 4  depicts trellis diagrams for an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIG. 5  shows a trellis diagram and comma characters fox an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIG. 6  shows a specific exemplary implementation of a 9B10B encoding table; 
       FIGS. 7-13  show corresponding trellis diagrams; 
       FIG. 14  shows the set of 10B vectors requiring individual bit changes for encoding, in an exemplary embodiment; 
       FIGS. 15-33  depict exemplary encoding logic equations for an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIGS. 34-45  depict exemplary decoding logic equations for an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIGS. 46 and 47  depict invalid vectors for an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIGS. 48-52  address disparity checking and equations for required and running disparity for an exemplary embodiment of 9B10B code, according to an aspect of the invention; 
       FIG. 53  shows a block diagram of a specific exemplary circuit for 9B10B encoding, according to an aspect of the invention; 
       FIGS. 54A-54C  show gate level circuit diagrams of the circuit of  FIG. 53 ; 
       FIG. 55  shows a block diagram of a specific exemplary circuit for 9B10B decoding, according to an aspect of the invention; 
       FIGS. 56A-56C  show gate level circuit diagrams of the circuit of  FIG. 55 ; 
       FIG. 57  depicts trellis diagrams for an exemplary embodiment of 7B8B code, according to an aspect of the invention; 
       FIGS. 58-60  show trellis diagrams for comma sequences for an exemplary embodiment of 7B8B code, according to an aspect of the invention; 
       FIGS. 61-67  show trellis diagrams corresponding to  FIG. 68 ; 
       FIG. 68  shows a specific exemplary implementation of a 7B8B encoding table; 
       FIG. 69  shows the set of 8B vectors requiring individual bit changes for encoding, in an exemplary embodiment; 
       FIGS. 70-82  depict exemplary encoding logic equations for an exemplary embodiment of 7B8B code, according to an aspect of the invention; 
       FIGS. 83-95  depict aspects of decoding and error checking for an exemplary embodiment of 7B8B code, according to an aspect of the invention; 
       FIG. 96  shows a block diagram of a specific exemplary circuit for 7B8B encoding, according to an aspect of the invention; 
       FIGS. 97A and 97B  show gate level circuit diagrams of the circuit of  FIG. 96 ; 
       FIG. 98  shows a block diagram of a specific exemplary circuit for 7B8B decoding, according to an aspect of the invention; 
       FIGS. 99A and 99B  show gate level circuit diagrams of the circuit of  FIG. 98 ; and 
       FIG. 100  is a system diagram of an exemplary computer system on which one or more embodiments of the present invention can be implemented. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Introduction 
   Notation 
   The capital “B” in 9B10B and 7B8B refers to “Binary Symbol,” not “bit,” as a distinction from codes which use symbols with more than two levels, e.g. ternary symbols with three levels, commonly referred to by the capital letter “T” Also, the number of inputs is actually ten or 8, respectively, to accommodate control characters, and the numbers 9 and 7 refer to the data vectors only. 
   Bit Names 
   The bits of the uncoded 9B and 7B data vectors are labeled with the upper case letters ‘ABCDEFGHI’ and ‘STUVWXY,’ respectively. The control input for special non-data characters is labeled with ‘K.’ The bits of the coded 10B vectors are labeled with the lower case letters ‘abcdefghij’ and ‘stuvwxyz,’ respectively. Serial transmission is in alphabetical older starting with ‘a’ or ‘s.’ 
   In the logic equations, some capital letters have overlapping use for group classifications and for the designation of a specific uncoded input bit If the dual use can be ambiguous such as for a single letter designating a classification, the classification is referred to with bold, underlined type The bit designations are always referred to with plain type. As an example, the bold letter  S  refers to the input pattern which leads to the node  7   s  in the trellis of  FIG. 1 , and the plain letter S refers to the uncoded bit S of the 7B8B code. 
   Tables 
   In some tables, a free standing letter S in the column header alerts for some symmetry between the left and right side of the table if there is a 1 in a specific row. The symmetric relationship might be complementary or equal values for the bit positions marked by bold type or by italic type. This use is not uniform because bold type is also used to highlight bit positions with equal values on several rows or to mark encoded bit positions which are the complements of the respective uncoded positions. The Coding Labels in the right column of the tables are used to write the coding and decoding equations. 
   Logic Equations 
   In the logic equations, the EXCLUSIVE OR function (⊕) is executed first, followed by the AND (•), and then the OR (+) function. The EXOR function is defined with a single parameter on each side, i.e. x⊕y is equivalent to (x⊕y) to allow the elimination of one level of parentheses. In the coding equations and tables, some vectors are included redundantly for simplification. Redundant vector names are preceded by an asterisk. 
   In any of the Exclusive OR relationships between two groups of contiguous bits, any bit in the first and second group can be selected as the first and second input, respectively, of the XOR2 gate. The inputs have been selected to maximize commonality among the several encoding equations. 
   The expressions in parentheses at the right edge of the equations refer to the corresponding net names in the circuit diagram. An asterisk * following the net name means that the correlation is not exact because of missing or additional terms listed on the same line. In the logic labels and equations, the components are usually listed in descending order of the estimated circuit delay. 
   Net Names in the Circuit Diagrams 
   Some abbreviated signal and wire names are used in the circuits for convenience and brevity and to avoid special symbols which are not compatible with the logic design systems. 
   In the encoding circuits, the letters ‘a’ and ‘o’ within net-names refer to the Boolean AND and OR functions, respectively, but in most cases, the AND operator is omitted. The letter ‘n’ within a name negates the preceding parameter. The letters ‘e’ and ‘u’ represent the symbols ‘=’ and ‘≠’, respectively. The capital letters “ABCDEFGHI” and “STUVWXY” represent the uncoded input bits and the lower case letters “abcdefghij” and “stuvwxyz” represent the coded format, usually prefixed with C(oded) because some chip design and simulation programs do not distinguish between upper and lower case letters. The lower case letter “n” followed by a number refers to a net number. Leading capital letters “P” or “N” refer to logic functions which are true at the upper or lower logic level, respectively. Numbered net names such as n45, are true at the lower level and take a P prefix if true at the upper level, e.g. Pn45. 
   The notation used in the decoding diagrams is analogous to that of the encoding circuit but lower case letters for logic functions are exchanged for upper case and vice versa The letters ‘A’ and ‘O’ within net-names refer to the Boolean AND and OR functions, respectively. The letter ‘N’ within a name negates the preceding parameter The letters ‘E’ and ‘U’ represent the symbols ‘=’ and ‘≠’, respectively. 
   Disparity Diagrams 
   For easy reference, some of the trellis diagrams of U.S. Pat. Nos. 6,198,413 and 6,614,369, modified in accordance with the teachings of the invention (as explained below), are reproduced here. In the trellis diagrams such as shown in  FIG. 1 , an upwards sloping line for one interval represents a binary symbol with a value of one, conversely, a slope downwards represents a zero value. The horizontal coordinates on the time axis of the left trellis of  FIG. 1  are labeled by a number in ascending order from left to right. Each unit increment represents one additional binary symbol. The vertical coordinates which represent the running disparity are expressed by a lower case letter as follows:
         b (balance) indicates a disparity of 0   u (up, uni) indicates a disparity of +1 when paired with an odd preceding number and a disparity of +2 when paired with an even preceding number   m (minus) indicates a disparity of 1 when paired with an odd preceding number and a disparity of −2 when paired with an even preceding number   c (cube) indicates a disparity of +3 when paired with an odd preceding number and a disparity of +4 when paired with an even preceding number   t (three) indicates a disparity of −3 when paired with an odd preceding number and a disparity of −4 when paired with an even preceding number   v (Roman numeral V) indicates a disparity of +5 when paired with an odd preceding number and a disparity of +6 when paired with an even preceding number   q (quint) indicates a disparity of −5 when paired with an odd preceding number and a disparity of −6 when paired with an even preceding number   h (hepta) indicates a disparity of +7 when paired with an odd preceding number and a disparity of +8 when paired with an even preceding number   s (seven) indicates a disparity of −7 when paired with an odd preceding number and a disparity of −8 when paired with an even preceding number   x (Roman numeral IX) indicates a disparity of +9 when paired with an odd preceding number and a disparity of +10 when paired with an even preceding number   n (nine, negative) indicates a disparity of −9 when paired with an odd preceding number and a disparity of −10 when paired with an even preceding number.       

   As an example, the expression “ 5   c ” in the left trellis of  FIG. 1  refers to a disparity value of +3 after the end of the fifth bit and the expression “ 6   c ” refers to a disparity value of +4 after the end of the sixth bit.  FIG. 1  shows the trellis diagrams for vectors comprising up to 10 bits. The left-side trellis lists the node names and is used to define the vector classifications and the right-side trellis shows the number of different paths or vectors leading from the origin to each node. Note that these numbers are identical to the binomial coefficients. 
   Vector Classification 
   The following notation is used for names attached to sets of source vectors or encoded vectors:
         The first capital letter B, P, D, or F indicates the disparity of the coded vectors:
           B indicates disparity independent Balanced coded vectors   P indicates a complementary pair of disparity dependent balanced coded vectors which are selected based on the Polarity of the running disparity.   D indicates a complementary pair of coded vectors with a disparity of two.   F indicates a complementary pair of coded vectors with a disparity of Four.   
           A second capital letter, if present, indicates the block disparity of the uncoded vector or the vertical coordinate after bit  9  (I) or  7  (Y) in the left-side trellis of  FIG. 1  using the capital version of the disparity values listed above.   A third capital letter, if present, indicates the value of the control input bit K   Up to three leading capital letters may be followed by one or more sets of a number paired with a lower case letter to indicate trellis nodes through which the members of the class must go, or not go if negated. Vectors going through negated nodes, e.g. 4t′, must not be part of the specified class of vectors. This notation is illustrated in the left-side trellis of  FIG. 1 .       

   The third and following capital letters, other than K, mark the uncoded bits, if any, which must be complemented to obtain the respective coded primary vector. The last coded bit j or z is appended with a default value zero and complemented, if indicated by a classification name ending in J or Z, respectively 
   Conceptual and Circuit Views for Encoding and Decoding 
     FIGS. 2A and 3A  show a conceptual view of encoding and decoding, respectively, which have first been successfully applied to an 8B10B code with local parity as described in U.S. patent application Ser. No. 11/140,778 of inventor Albert X. Widmer filed May 31, 2005 and entitled “NB/MB Coding Apparatus and Method Using Both Disparity Independent and Disparity Dependent Encoded Vectors” 
     FIGS. 2B and 3B  present another view of encoding and decoding, and are more circuit oriented.  FIGS. 2A ,  2 B,  3 A and  3 B illustrate the example of the 9B10B code but are equally applicable to the 7B8B code if the numbers 10 and 9 are replace by 8 and 7, respectively. They show the parallelism in the processing of various vector classes which is significant for a simple implementation with low latency. Note that full vector complementation and changes in individual bits are completely separate and independent of each other. 
   Reference should now be had to  FIG. 2A , which depicts an exemplary apparatus  200  for encoding 9 binary symbol (9B) source data vectors into 10 binary symbol (10 B) encoded vector&#39;s, according to an aspect of the invention (and is also indicative of method steps in an exemplary encoding method according to an aspect of the invention). The apparatus  200  can include a binary symbol appending module  202 ; optionally, a disparity monitoring module  204 ; a full vector complementing module  206 ; and a binary symbol complementing module  208 . Binary symbol appending module  202  can be configured to append a binary symbol to the 9B source data vectors so as to obtain augmented vectors. Where employed, disparity monitoring module  204  can be coupled to the full vector complementing module  206 , and can be configured to determine current running disparity for use in assigning proper disparity dependent encoded vectors to given ones of the 9B source data vectors. 
   Full vector complementing module  206  can be configured to complement 10 binary symbols of a given one of the augmented vectors. The binary symbol complementing module  208  can be configured to complement less than 9 binary symbols of a given one of the 9B source data vectors to obtain a corresponding portion of another given one of the 10B encoded vectors. The binary symbol complementing module  208  and the full vector complementing module  206  can be configured to operate substantially in parallel. As used herein, “substantially in parallel” means either entirely in parallel or with sufficient parallelism that desirable enhancements in processing associated with encoding and/or decoding can be achieved. The modules  206 ,  208  can be coupled to each other and can be configured to implement any of the encoding schemes described herein. It is believed preferable that the module  208  complements appropriate individual bits of the augmented vector, but any appropriate scheme for complementing one or more individual binary symbols is encompassed within the scope of the present invention. Further, note that as used herein, “coupled” should be understood broadly to include direct coupling, indirect coupling through one or more other components, sharing of one or mole logic gates as discussed below, and the like. 
   An exemplary method of encoding 9B source vectors into 10B encoded vectors, according to an aspect of the invention, includes the steps of obtaining a plurality of 9B source vectors, as at the input to block  202 , and encoding the 9B source vectors into a plurality of 10B encoded vectors, as at the output of blocks  206  and  208 , according to an encoding scheme to be described herein. The 10B encoded vectors include at least 10B encoded data vectors (“at least” is used to indicate that, for example, control vectors could be included in addition to the data vectors). The encoding scheme maps at least a first portion of the 9B source vectors into 10B encoded data vectors comprising disparity independent encoded vectors, and at least a second portion of the 9B source vectors into 10B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations. The 10B encoded data vectors have one binary symbol appended thereto by the encoding scheme (for example, by module  202 ). 
   A fraction of the 10B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 9B source vectors. The fraction does not include any of the disparity dependent encoded representations. In the exemplary embodiment none of the encoded data vectors comprise exclusively alternating ones and zeroes (it is to be understood that in other embodiments, vector&#39;s comprising exclusively alternating ones and zeroes could be used as data vectors; for example, decision feedback equalization (DFE) typically requires a run of at least two for error recovery, but where DFE is not employed this may not be a concern so that vectors comprising exclusively alternating ones and zeroes could be used as data vectors). Optionally, the fraction of the 10B encoded vectors includes the disparity independent encoded vectors, the disparity independent encoded vectors being dc-balanced and having no alternate representations. 
   Further, the 9B source vectors can include 9B source data vectors and at least one 9B source control vector, and the encoding scheme can further map the at least one 9B source control vector into at least one 10B encoded control vector Yet further, at least some of the second portion of the 9B source vectors that are mapped into 10B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations are mapped to dc-balanced 10B encoded data vectors. 
   The first portion of the 9B source vectors can be mapped into 10B encoded vectors comprising a set of 116 disparity independent encoded vectors which does not require any bit changes during encoding, and the first portion of the 9B source vectors can include source vectors having: 
   a disparity of +1, 
   a leading run-length no greater than 3, 
   no more than 2 trailing zeros in the case of those of the source vectors having trailing zeroes, and 
   no more than 4 trailing ones in the case of those of the source vectors having trailing ones. 
   The source vectors of the first portion can be appended during encoding with a single binary symbol with a value of zero. 115 of the 116 disparity independent encoded vectors are the encoded data vectors and the remaining one of the 116 disparity independent encoded vectors, comprising alternating ones and zeros, is defined as the encoded control vector. In other embodiments, such vector could instead be defined as an invalid vector; indeed, in general, any or all control vectors can instead be defined as invalid characters (invalid vectors) and synchronization can be acquired via techniques other than the comma character. 
   The first portion of the 9B source vectors is mapped into 10B encoded vectors comprising a set of 116 disparity independent encoded vectors, a fraction of the 116 disparity independent encoded vectors requiring individual bit changes during encoding, and the set of 116 encoded vectors comprises vectors having:
         nine leading binary symbols with a disparity of −1,   a leading run-length no greater than 3,   no more than 2 trailing ones in the case of those of the source vectors having trailing ones,   no more than 4 trailing zeros in the case of those of the source vectors having trailing zeroes.       

   The first portion of the 9B source vectors becomes a 9B set, and the 9B set is appended with a single binary symbol with a value of one when being encoded to obtain the 116 encoded vectors; 115 of the 116 disparity independent encoded vectors comprising the encoded data vectors and a remaining one of the 116 disparity independent encoded vectors, comprising alternating ones and zeros, being defined as the encoded control vector In other embodiments, such vector could instead be defined as an invalid vector; indeed, in general, any or all control vectors can instead be defined as invalid characters (invalid vectors) and synchronization can be acquired via techniques other than the comma character. The terminology “9B set” is used because some of the source bits are changed before they become the first 9 bits of the encoded vector. 
   Complementary implementations are also within the inventive scope. For example, in such an implementation, the first portion of the 9B source vectors is mapped into 10B encoded vectors comprising a set of 116 disparity independent encoded vectors which does not require any bit changes during encoding, and the first portion of the 9B source vectors comprises source vectors having:
         a disparity of −1,   a leading run-length no greater than 3,   no more than 2 trailing ones in the case of those of the source vectors having trailing ones, and   no more than 4 trailing zeroes in the case of those of the source vectors having trailing zeroes.       

   The source vectors of the first position are appended during encoding with a single binary symbol with a value of one, 115 of the 116 disparity independent encoded vectors are the encoded data vectors and a remaining one of the 116 disparity independent encoded vectors, comprising alternating zeroes and ones, is defined as the encoded control vector. 
   Also by way of further details with regard to a complementary implementation, the first portion of the 9B source vectors could be mapped into 10B encoded vectors comprising a set of 116 disparity independent encoded vectors, a fraction of the 116 disparity independent encoded vectors requiring individual bit changes during encoding. The set of 116 encoded vectors could include vectors having:
         nine leading binary symbols with a disparity of +1,   a leading run-length no greater than 3,   no more than 2 trailing zeroes in the case of those of the source vectors having trailing zeroes, and   no more than 4 trailing ones in the case of those of the source vectors having trailing ones.       

   The first portion of the 9B source vectors could becoming a 9B set, and the 9B set could be appended with a single binary symbol with a value of zero when being encoded to obtain the 116 encoded vectors; 115 of the 116 disparity independent encoded vectors could be the encoded data vectors and a remaining one of the 116 disparity independent encoded vectors, comprising alternating zeroes and ones, could be defined as the encoded control vector. 
   Variations from the source to encoded vector assignments are possible, for example:
         (i) The appended binary symbol could have a default value of 1 and some or all of the specifications for the primary approach could be changed to complementary bit values and disparity polarities, or   (ii) Some or all primary and alternate vector sets could be swapped with the respective complementary sets either in combination with item (i) or independently.       

   Referring now to  FIG. 2B , a hardware-oriented view of exemplary circuit  200  includes encoder block  210 , disparity control block  212 , and exclusive OR gate  214 —further specific details are provided below with regard to  FIGS. 54A-54C . 
   Attention should now be given to  FIG. 3A , which illustrates an exemplary embodiment of apparatus  300  for decoding 10B encoded vectors into 9B source data vectors, in accordance with an aspect of the invention. Apparatus  300  includes a full vector (N=9) complementing module  302 , a binary symbol complementing module  304 , and, optionally, a validity check module  306 . Full vector complementing module  302  can be configured to complement at least 9 binary symbols of a given one of the 10B encoded vectors to recover a given one of the 9B source data vectors that corresponds to the given one of the 10B encoded vectors. 
   The binary symbol complementing binary module  304  can be coupled to the full vector complementing module  302  and can be configured to complement less than 9 binary symbols of another given one of the 10B encoded vectors to recover a corresponding portion of another given one of the 9B source data vectors corresponding to the other given one of the 913 encoded vectors. Modules  302 ,  304 , and (optionally)  306  can be configured to operate substantially in parallel, where “substantially in parallel” has the meaning set forth above. Modules  302 ,  304 , and  306  can be configured to implement any encoding scheme in accordance with the invention. In the exemplary embodiment depicted in  FIG. 3A , modules  302 ,  304  are also configured to strip off the appended binary symbols. Modules  302 ,  304 ,  306  can “see” the appended binary symbols at the inputs but such symbols can be dropped before complementation. Note that the full vector complementing module does not have to complement vectors that are already in their primary (as opposed to alternate) form. 
   Where employed, validity check module  306  can be coupled to modules  302 ,  304  and can be configured to obtain putative encoded vectors and to determine if given ones of the putative encoded vectors are valid 10B encoded vectors Note that this can be performed by comparing received vectors to valid vectors to determine whether they are valid, or, conversely, by determining whether they are invalid, for example, by comparing them to invalid vectors. 
     FIG. 3A  is also indicative of exemplary method steps in a method of decoding 10B encoded vectors into decoded 9B source vectors, including the steps of obtaining a plurality of 10B encoded vectors that were encoded from a plurality of 9B source vectors according to an encoding scheme as described herein, as at the input of blocks  302 ,  304 , and  306 , and decoding the 10B encoded vectors into a plurality of 9B source vectors, as at the corresponding outputs, according to decoding rules of the encoding scheme. Optionally, the method can include an additional step of checking the plurality of 10B encoded vectors for selected ones of the encoded vectors that are not balanced and that end with a predetermined binary symbol. The predetermined binary symbol can be a “one” in a primary implementation of the encoding scheme and a “zero” in a complementary implementation of the encoding scheme. The decoding can include at least automatically complementing the selected ones of the encoded vectors Further details are provided below with regard to a specific exemplary implementation of an inventive coding and decoding scheme. In one or more embodiments, the code is specially designed to allow one to look for automatic complementation. There can be some other cases of auto complementation, such as for vectors that are dc balanced and end with four ones (or, four zeroes in complementary form). 
   The exemplary decoder circuit  300  includes a check for invalid vectors. In the presence of errors, the received blocks may have a disparity of ±6, ±8, or ±10, which are outside the normal range but are assigned a disparity value of ±4 for purposes of the running disparity. The disparity monitoring circuit shown in  FIG. 3B  has not been included in this exemplary design, because, in one or more applications, it may not contribute enough to the overall error checking schemes to justify the added complexity; however, it is to be understood that in other applications, one or more inventive embodiments could include such a circuit. In general, in the hardware-oriented view of  FIG. 3B , circuit  300  includes decoder block  308  and disparity check block  310 , further details to be provided below with respect to  FIGS. 56A-C . 
   Implementation issues to be addressed for Encoder and Decoder may include, for example, circuit area and delay reduction. Design principles illustrated for the simpler case of the 8B10B_P code with local parity of the aforementioned U.S. patent application Ser. No. 11/140,778, discussed in detail above, are applicable here as well:
     1. All vectors with individual bit changes are relegated to a class of vectors which are balanced and disparity independent.   2. Assignment of uncoded source vectors to coded vectors such that the number of vectors with individual bit changes is minimized.   3. Extensive sorting of vectors into groups with commonalties   4. Definition of the set of alternate vectors as a class of vectors which can be identified by a relatively simple logic equation.
 
Disparity Requirements for 7B8B and 9B10B Code
   

   At all 8B or 10B boundaries, the running disparity D can assume one of four values, D=±1, or D=±3. Encoded vectors in these codes are either balanced and disparity independent, balanced and disparity dependent (new), or have a disparity of ±2, or a disparity of ±4. If the current running disparity is positive (+1 or +3), only disparity independent vectors or vectors with a requited positive entry disparity may be entered and complementary rules apply for a negative running disparity. Almost half the source vectors axe translated into a single balanced disparity independent encoded vector. All other 7B and 9B vectors are translated into one of a pair of complementary 10B vector&#39;s, respectively, according to the disparity rules above. 
   DESCRIPTION OF EXEMPLARY 9B10B TRANSMISSION LINE CODE 
   A. 9B10B Code Definition 
   The 9B10B code comprises a total of 530 code points with 828 coded 10B vectors as illustrated by the trellis diagrams of  FIG. 4 . 
   1) 232 Balanced Disparity Independent 10B Vectors ( FIG. 4A.1 ) 
   There are 232 disparity independent balanced vectors. Disparity independence means that they can be entered in a sequence regardless of the current starting disparity (one of the 4 values defined above). Balance means that the running disparities at the start and end of the vector are identical. The subset (232) of all possible 10B vectors (1024) chosen is the set of balanced vectors with a run length of no more than three at the leading and trailing boundaries as shown in FIG.  4 A 1 . 
   2) 2×9 Balanced, Disparity Dependent 10B Vectors ( FIG. 4A.2 ) 
   These 9 data vectors have been added as a partial replacement of 10 vectors from  FIG. 4B  which have been reassigned for control characters. For a negative running disparity, 8 balanced vectors with either for leading ones or four trailing zeros and one vector with both four leading ones and four trailing zeros are included. For a positive running disparity, the complementary vectors on the right side of  FIG. 4A.2  are used. 
   3) 2×190 (180*) 10B Vectors with Disparity +/−2 ( FIG. 4B ) 
   A set of 190 10B vectors illustrated in  FIG. 4B  comprises all bit patterns with a disparity of 2, a run length of no more than three at the front end and no more than three zeros or four ones at the trailing end. An exact complementary set of another 190 vectors on the right side has a disparity of 2. With regard to the asterisk in the above heading, note that in  FIG. 4B , the set of 10 vectors with trailing ones is reserved for control characters in the 16B18B environment and is not used for applications where it could generate false commas, e.g. for contiguous 10B vectors. 
   4). 2×99 10B Vectors with Disparity +/−4 ( FIG. 4C.1  and  FIG. 4C.2 ) 
   The set of 95 10B vectors of  FIG. 4C.1  comprises all bit patterns with a disparity of 4, no more than four ones or two zeros at the front end and no more than one zero or four ones at the trailing end. An exact complementary set of another 95 vectors on the right side has a disparity of 4 The set of four 10B vectors of  FIG. 4C.2  comprises all bit patterns with a disparity of 4, no more than 3 ones or one zero at the front end and exactly two zeros at the trailing end. An exact complementary set of another 4 vectors on the right side has a disparity of 4. 
   5) Control and Comma Characters 
   Up to eighteen 10B vectors can be reserved for information other than normal data. If any of the 18 control characters is to be encoded, a control line K must be asserted together with an appropriate data field. One of the control vectors is reserved for the generation of a singular comma sequence for quick synchronization. The comma extends over a first 10B field and the first three bits of the next following vector which may belong also to the 9B10B code, to the 7B8B code, or other similar compatible codes. The comma bit pattern is 0011111110′111 for a negative starting disparity, or its complement for a positive starting disparity. For synchronization, only the 10 ones in bold type (or zeros) in an 11-bit field need to be monitored, assuming a synchronization enabling circuit is activated only after a majority of misaligned commas has been received. The construction of a complete 18B comma character is known, as discussed in U.S. Pat. Nos. 6,198,413 and 6,614,369 
   The 10B part of the comma sequence is listed as C 508  together with the other control characters Kx in Table  1 M of  FIG. 6M . 
   6) Comma Characters for Concatenated 9B10B Vectors ( FIG. 5 ) 
     FIG. 5  illustrates how the complete comma of either polarity fits into the trellis diagram. For purposes of the comma function, the possible location of the sequence at different disparity levels is irrelevant. To acquire the 2-byte word synchronization, the circuits may search for either one or both of the bit sequences ‘1111111 x111’ and ‘0000000x000.’ 
   The input to the encoder should be the specified bit patterns, but only the first source vector (9B) should be accompanied with a K value of one. Coded 10B blocks from the revised 9B10B code can be concatenated without any change in the code. The run length remains at 7, and the digital sum variation also remains constrained to 12. The comma pattern also remains unchanged as shown in  FIG. 5 . The second part is provided by selected 10B vectors as follows: 
   a) Basic Set of 2-Vector Comma Sequences 
   The C508 vector (0011111110/1100000001) can be paired with one of the disparity dependent vectors D 71 , D 135 , D 263 , or D 504  as listed in  FIG. 5  to end at node Y in  FIG. 5 . Four different 20-bit control blocks which include the comma sequence can be generated regardless of the running disparity and without the special disparity controls needed for the second vector of the comma in the 16B18B code. 
   b) Extended Set of 2-Vector Comma Sequences 
   If more than four 20-bit control blocks with a comma are useful, up to 14 additional ones can be provided using 14 balanced complementary vectors pairs with a leading run of three from the trellis of  FIG. 4A.1 . For the generation of the comma sequence, this subset of balanced 10B vectors must be made disparity dependent it they follow C 508  of Table  1 , similar to what is done for balanced 4B vectors in 8B10B control characters of the following references: Albert X Widmer, The ANSI Fibre Channel Transmission Code, IBM Research Report RC18855, Apr. 23, 1993, and U.S. Pat. Nos. 4,486,739, of Franaszek and Widmer, and 6,977,599, of Albert X. Widmer, and for the second part of the comma sequence of contiguous 7B8B vectors below. One or the other of the complements must be chosen depending on the polarity of the running disparity at the end of the C508 vector. This extended set is not included in the tables, equations and circuits of this repot. 
   The 10B bit patterns from Table  1  suitable for comma generation together with the required polarity in front of the 10B vector are listed below: 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               D488 − 0001011110 + 1110100001 
               D23 
             
             
                 
               D472 − 0001101110 + 1110010001 
               D39 
             
             
                 
               D440 − 0001110110 + 1110001001 
               D0 
             
             
                 
               D376 − 0001111010 + 1110000101 
               D503 
             
             
                 
               D248 − 0001111100 + 1110000011 
               D7 
             
             
                 
               D87  + 1110101000 − 0001010111 
               D40 
             
             
                 
               D103 + 1110011000 − 0001100111 
               D24 
             
             
                 
               D151 + 1110100100 − 0001011011 
               D495 
             
             
                 
               D167 + 1110010100 − 0001101011 
               D8 
             
             
                 
               D199 + 1110001100 − 0001110011 
               D264 
             
             
                 
               D279 + 1110100010 − 0001011101 
               D239 
             
             
                 
               D295 + 1110010010 − 0001101101 
               K216 
             
             
                 
               D327 + 1110001010 − 0001110101 
               D136 
             
             
                 
               D391 + 1110000110 − 0001111001 
               D72 
             
             
                 
                 
             
          
         
       
     
   
   The alternate vectors of the right column are decoded by full vector complementation if they contiguously follow the comma vector C 508   
   B. Properties of the 9B10B Code 
   Significant characteristics of the code can be directly extracted from the trellis diagram of  FIG. 5  which also shows four possible configurations for the comma sequence. Using  FIG. 5  together with the trellis diagrams defining the code ( FIG. 4   x.y ), one can verify that the comma sequence is singular, i.e. it cannot be reproduced in any other position relative to the vector boundaries neither within the 20B block nor across 20B block boundaries. U.S. Pat. No. 6,614,369 shows an identical comma sequence satisfying the singularity requirement for a 16B18B code comprising a 9B10B and a 7B8B part. 
   1) Clocking and Synchronization Parameters 
   The maximum run length is seven and no contiguous runs of seven are possible The minimum transition density is two per 10B block for an indefinite length. The code includes a singular comma sequence. 
   2) Compatibility with Decision Feedback Equalization (DFE) 
   In the exemplary embodiment, any run of alternating ones and zeros in a sequence of data vectors is less than two vectors long. However, such a pattern of arbitrary length can be generated by a steady sequence of either the K170 or the K341 control character. 
   3) Low Frequency Characteristics 
   The code is DC balanced. The maximum digital sum variation is 12. The normalized DC offset or area between zero disparity and the extreme contour of the trellis diagram as defined in Widmer, The ANSI Fibre Channel Transmission Code, mentioned above, is 4.9. The low frequency cut-off point for high pass filters should be located about 2.5 times lower than for Fibre Channel 8B10B code for equal eye closure. The low frequency wander can be reduced on a statistical basis by scrambling the data before encoding 8B10B coded, scrambled data can operate with a 50% higher low frequency cut-off point than a coded worst case pattern. For 9B10B code, the gain from scrambling before encoding is expected to be more. 
   4) 10B and 18B Control Characters 
   For operation with contiguous 10B vectors, there are 8 control vectors available In the 16B18B domain, the 10B and 8B fields include 18 and 7 control characters, respectively, so it possible to generate a total of [(18×135)+(7×530)]=6140 control characters in the 18-bit domain. The code includes four 18B comma sequences. Depending on the application, the user may relegate some of the unused control characters to the class of invalid vectors. 
   C. 9B10B Encoding Table 
   Table  1  of  FIGS. 6A through 6M  represents a specific coding assignment between uncoded and coded vectors in the 9B10B domain. 
   1) Designing Principles 
   The coding tables are created in steps as follows:
     1. Generate a list of all source vectors and all valid encoded vectors. Assume a default value for the appended bit. This design assumes a default value of zero. An alternate, equivalent code can be constructed by choosing complementary values for the appended bit and the vector sets   2. In the coded domain, reserve the vector required for the comma generation (0011111110). Assign it a source vector which matches the first n−1 coded bits.   3. Assign all source vectors which match the first 9 bits of encoded vectors ending with the default value of j=0 to the respective matching vectors and remove them from both lists.   4. The remaining source vectors are assigned to the class of disparity independent balanced vectors which end with j=1, the complement of the default value Assign the source vectors which match the first 9 bits of this set to the respective encoded vectors   5. Find sets of several source vectors, preferably complementary sets, which can be made to match an encoded vector in this class by complementing just one common bit position in the source vector and make the assignment.   6. The remaining uncoded vectors are sorted into complementary pairs to the extent possible, and the remaining available encoded vectors are also sorted into pairs which are complementary in all or most of the leading 9 bits.   7. Find close matches between the two sets and change one or more bit positions in the source pail to obtain a match with the closest unassigned encoded pair.   8. Look for single vectors which can be made to match a coded vector by changing just one bit, then look for matches based on 2-bit changes, and so on   9. Once all data vectors have been assigned, assign the remaining coded vectors to control characters and choose a corresponding source vector which matches the first n−1 bits.   

   2) Construction of the 9B10B Coding Table  1   
   This section describes auxiliary graphs and diagrams which were used for the assignment of coded 10B vectors to uncoded 9B vectors in Table  1   
   a) 414 9B Vectors congruent with the first 9 Bits of the 10B encoded Vectors ( FIGS. 7-12 ) 
   For 414 vectors (402 data, 12 control), represented by the trellis diagrams of  FIGS. 7 to 12 , the first nine bits of the primary encoded vectors are identical to the corresponding source vectors and the appended bit assumes the default value (0).  FIG. 7  represents the subset of 116 balanced, disparity independent vectors of  FIG. 4A.1  which end with a zero. 
     FIGS. 8A ,  8 B, and  8   c  Represent the 9 Balanced, Disparity Dependent Vectors of  FIG. 4A.2 .  FIG. 5A  is a copy of the lower left side of  FIG. 4A.2  and is assigned to the balanced primary data vectors D 55 , D 59 , D 61 , and D 62  which require a negative entry disparity.  FIG. 8B  represents those 4 vectors of the upper left side of  FIG. 4A.2  which end with zero and are assigned to the balanced primary data vectors D 47 , D 79 , D 143 , and D 271  which require a negative entry disparity.  FIG. 8C  is from the upper right side of  FIG. 4A.2  ending with a zero and is assigned to the balanced data primary vector D 496  which requires a positive entry disparity. 
     FIG. 9A  uses all 95 vectors of  FIG. 4C.1  with a disparity of four. The bold lines on the left side represent the control vector used for comma generation. 
   Enumeration of 25 primary Vectors FV 5 v′ 8 v′ of FIG.  9 A(L) which require a negative entry disparity: 
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D367 
               D375 
               D379 
               D381 
               D382 
               D431 
               D439 
               D443 
               D445 
               D446 
             
             
               D463 
               D471 
               D475 
               D477 
               D478 
               D487 
               D491 
               D493 
               D494 
               D499 
             
             
               D501 
               D502 
               D505 
               D506 
               C508* 
             
             
                 
             
             
               *The source vector C508 = 001111111 with K = 1 is coded into 0011111110. This represents the special character C508 and is part of the comma sequence. The same source vector D508 with K = 0 represents the data vector D508 and is coded into 0011010101. 
             
          
         
       
     
   
   Enumeration of 70 primary Vectors FI 5 u′ 5 q′ of FIG.  9 A(R) which require a positive entry disparity: 
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D35 
               D37 
               D38 
               D41 
               D42 
               D44 
               D49 
               D50 
               D52 
               D56 
             
             
               D67 
               D69 
               D70 
               D73 
               D74 
               D76 
               D81 
               D82 
               D84 
               D88 
             
             
               D97 
               D98 
               D100 
               D104 
               D112 
               D131 
               D133 
               D134 
               D137 
               D138 
             
             
               D140 
               D145 
               D146 
               D148 
               D152 
               D161 
               D162 
               D164 
               D168 
               D176 
             
             
               D193 
               D194 
               D196 
               D200 
               D208 
               D259 
               D261 
               D262 
               D265 
               D266 
             
             
               D268 
               D273 
               D274 
               D276 
               D280 
               D289 
               D290 
               D292 
               D296 
               D304 
             
             
               D321 
               D322 
               D324 
               D328 
               D336 
               D385 
               D386 
               D388 
               D392 
               D400 
             
             
                 
             
          
         
       
     
   
   The 4 vectors of  FIG. 9B  with disparity of plus four correspond to the 4 vectors of  FIG. 4C.2  and are assigned to the primary data vectors D 247 , D 251 , D 253 , and D 254  and require a negative entry disparity. The 74 vectors of  FIG. 10  with a disparity of +2 are the subset of the vectors of FIG.  4 B(L) which end with a zero and require a negative entry disparity. 
   Enumeration of 74 Vectors DC 4 c′ of  FIG. 10 : 
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D119 
               D123 
               D125 
               D126 
               D183 
               D187 
               D189 
               D190 
               D215 
               D219 
             
             
               D221 
               D222 
               D231 
               D235 
               D237 
               D238 
               D243 
               D245 
               D246 
               D249 
             
             
               D250 
               D252 
               D311 
               D315 
               D317 
               D318 
               D343 
               D347 
               D349 
               D350 
             
             
               D359 
               D363 
               D365 
               D366 
               D371 
               D373 
               D374 
               D377 
               D378 
               D380 
             
             
               D407 
               D411 
               D413 
               D414 
               D423 
               D427 
               D429 
               D430 
               D435 
               D437 
             
             
               D438 
               D441 
               D442 
               D444 
               D455 
               D459 
               D461 
               D462 
               D467 
               D469 
             
             
               D470 
               D473 
               D474 
               D476 
               D483 
               D485 
               D486 
               D489 
               D490 
               D492 
             
             
               D497 
               D498 
               D500 
               D504 
             
             
                 
             
          
         
       
     
   
   The 106 primary vectors of  FIG. 11  are the subset of vectors of FIG.  4 B(R) with one to three trailing zeros, a disparity of −2 and require a positive entry disparity 
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D71 
               D75 
               D77 
               D78 
               D83 
               D85 
               D86 
               D89 
               D90 
               D92 
             
             
               D99 
               D101 
               D102 
               D105 
               D106 
               D108 
               D113 
               D114 
               D116 
               D120 
             
             
               D135 
               D139 
               D141 
               D142 
               D147 
               D149 
               D150 
               D153 
               D154 
               D156 
             
             
               D163 
               D165 
               D166 
               D169 
               D170 
               D172 
               D177 
               D178 
               D180 
               D184 
             
             
               D195 
               D197 
               D198 
               D201 
               D202 
               D204 
               D209 
               D210 
               D212 
               D216 
             
             
               D22 
               D226 
               D228 
               D232 
               D263 
               D267 
               D269 
               D270 
               D275 
               D277 
             
             
               D278 
               D281 
               D282 
               D284 
               D291 
               D293 
               D294 
               D297 
               D298 
               D300 
             
             
               D305 
               D306 
               D308 
               D312 
               D323 
               D325 
               D326 
               D329 
               D330 
               D332 
             
             
               D337 
               D338 
               D340 
               D344 
               D353 
               D354 
               D356 
               D360 
               D387 
               D389 
             
             
               D390 
               D393 
               D394 
               D396 
               D401 
               D402 
               D404 
               D408 
               D417 
               D418 
             
             
               D420 
               D424 
               D449 
               D450 
               D452 
               D456 
             
             
                 
             
          
         
       
     
   
     FIG. 12  defines a set of 10 primary vectors with a disparity of −2 from FIG.  4 B(R) with four trailing zeros as optional control vectors. They require a positive entry disparity. These 10 control vectors can be used in the context of the 16B18B code. If 10B vectors are directly concatenated, they would generate false commas and are invalid vectors for that application. For all other applications, their use must be specifically evaluated. 
   Enumeration of 10 optional Control Vectors DMK 5 u 6 u of  FIG. 12 : 
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               K39 
               K43 
               K45 
               K46 
               K51 
               K53 
               K54 
               K57 
               K58 
               K60 
             
             
                 
             
          
         
       
     
   
   The table  1 M of  FIG. 6M  includes another set of 7 control characters. There are no restrictions on the use of those 7 control characters, and the previously defined comma character C 509 . The control source vectors are chosen so there is no need to ever change any source bits for encoding except the J-bit of the 6 vectors listed in Table  2 B of  FIG. 14B  at the bottom right side. 
   b) 116 Vectors with individual bit changes ( FIG. 13 ) 
     FIG. 13  represents the subset of 116 balanced, disparity independent vectors of  FIG. 2A.1  which end with one. The appended J-bit of  FIG. 13  is marked with a fat dotted line to indicate complementation from the default value for encoding. All source vectors which require individual bit changes for encoding are assigned to this class of balanced, disparity independent vectors. This important feature allows bit-encoding and whole vector inversions to proceed independently of each other in parallel for both encoding and decoding, greatly reducing circuit delay. The 116 vectors of  FIG. 13  are listed explicitly with their assigned source vectors in Table  2  of  FIG. 14 . The bit values in the encoded domain which are obtained by complementation of the respective source bit or the default value of bit J are shown in bold type. A value of 1 in the column S of Table  2  of  FIG. 14  indicates that the source bits on the right side are the exact complements of the left side and there are also symmetries in the coded domain which can be exploited for a simplified circuit implementation. 
   c) Value of Control Bit K 
   For a majority of data vectors, the value of the K-bit can be ignored as indicated by x in the K column. It must be included for all classifications and logic equations which include vectors with common values ABCDEFCGHI for a data and a control vector. 
   9B10B LOGIC EQUATIONS FOR IMPLEMENTATION 
   A. Logic Equations for 9B10B Encoder 
   1) Equations for Individual Bit Encoding 
   Generally, the encoded bits retain the value of the uncoded bit (a=A, b=B, etc), but the source bit is complemented (a=A′, b=B′, etc) if the respective equation below is true. 
   Encoded Bit a 
   The ‘a’ column has bold entries in Table  2  of FIG.  14 A/B for the 31 vectors listed in Table  3   a  of  FIG. 15 . The a-bit encoding equation of  FIG. 15  is derived from the coding labels of Table  3   a.    
   Encoded Bit b 
   The ‘b’ column has bold entries in Table  2  of FIG.  14 A/B for the 15 vectors listed in Table  3   b  of  FIG. 16 . The b-bit encoding equation of  FIG. 16  is derived from the coding labels of Table  3   b.    
   Encoded Bit c 
   The ‘c’ column has bold entries Table  2  of FIG.  14 A/B for the 31 vectors listed in Table  3   c  of  FIG. 17 . The c-bit encoding equation of  FIG. 17  is derived from the coding labels of Table  3   c.    
   Encoded Bit d 
   The ‘d’ column has bold entries in Table  2  of FIG.  14 A/B for the 45 vector&#39;s listed in Table  3   d  of  FIG. 19 . The d-bit encoding equation of  FIG. 18  is derived from the coding labels of Table  3   d.    
   Encoded Bit e 
   The ‘e’ column has bold entries in Table  2  of FIG.  14 A/B for the 45 vectors listed in Table  3   e  of  FIG. 19 . The e-bit encoding equation of  FIG. 20  is derived from the coding labels of Table  3   e.    
   Encoded Bit f 
   The ‘f’ column has bold entries in Table  2  of FIG.  14 A/B for the 19 vectors listed in Table  3   f  of  FIG. 21 . The f-bit encoding equation of  FIG. 21  is derived from the coding labels of Table  3   f.    
   Encoded Bit g 
   The ‘g’ column has bold entries in Table  2  of FIG.  14 A/B for the 22 vectors listed in Table  3   g  of  FIG. 22 . The g-bit encoding equation of  FIG. 22  is derived from the coding labels of Table  3   g.    
   Encoded Bit h 
   The ‘h’ column has bold entries in Table  2  of FIG.  14 A/B for the 20 vectors listed in Table  3   h  of  FIG. 23 . The h-bit encoding equation of  FIG. 23  is derived from the coding labels of Table  3   h.    
   Encoded Bit i 
   The ‘i’ column has bold entries in Table  2  of FIG.  14 A/B for the 32 vectors listed in Table  3   i  of  FIG. 24 . The i-bit encoding equation of  FIG. 24  is derived from the coding labels of Table  3   i.    
   Encoded Bit j 
   The ‘j’ column has bold entries for all 116 vectors of Table  2  of FIG.  14 A/B listed and rearranged in Table  3   j  of FIG.  25 A/B. The j-bit encoding equation of  FIG. 26  is derived from the coding labels of Table  3   j.    
   As illustrated at the end of Table  1 M of  FIG. 6M , all 12 control characters with a value of j=0 for the primary vector have a value of I=1 or GH=00 and all 6 control characters with j=1 have I=0 and (G+H)=1. With K=1 only the 18 valid control vectors must be presented at the input to the encoder. Therefore, the set of 6 control characters listed in Table  3   j  can be uniquely identified by the bit pattern (G+H)·I′·K. 
   2) Equations for the Required Disparity for Encoding DR 
   a) Positive Required Disparity for Encoding PDR 
   A total of 187 vectors listed in the Table  1  of  FIG. 6  require a positive entry disparity (PDR) They are listed and sorted in Table  4  of FIGS.  27 A/B/C. The validity of the expression G′·H′·K in  FIG. 27A  can be derived from the last 18 rows of Table  1 M of  FIG. 6M  where all control characters are listed. The Table  4 B of  FIG. 27B  includes a block of 80 vectors with:
 
 ABCDK=A⊕B·C′·D′·K′+C⊕D·A′·B′·K′ 
 
grouped into ten dual quartets (i.e., 10 double groups of four) with five complementary trailing bits EFGHI, which represent 20 of the 32 5-bit combinations. The 12 missing vectors are listed in Table  5  of  FIG. 28 . The trailing 5 bits of the vectors which are not members of the set can be described with the logic expression:
 
{(G⊕H′+H⊕I)·E⊕F′·F⊕G′}+(E⊕F·G⊕H′·H⊕I′)+(E⊕F′·F⊕H′·H⊕I′)
 
   Thus, the trailing 5 bits of the members of the set can be described by the complement of the above expression:
 
(G⊕H·H⊕I′+E⊕F+F⊕G)·(E⊕F′+G⊕H+H⊕I)·(E⊕F+F⊕H+H⊕I)
 
   The trailing five bits of a block of 78 vectors in Table  4 C of  FIG. 27C  with:
 
 ABCD=A⊕B·B⊕C·C⊕D′+A⊕B·C⊕D  
 
grouped into 13 sextets are listed in Table  6  of  FIG. 28 . The trailing 5 bits can be identified by the logic expression:
 
F⊕G·(H′+I′)·E′·K′+E⊕F·G·H′·I′·K′+H⊕I·E·F′·G′+(H+I)·E′·F′·G′
 
   The PDR equation of  FIG. 28  is derived from the coding labels of the Tables  4 A,  4 B, and  4 C of FIGS.  27 A/B/C. 
   b) Negative Required Disparity for Encoding NDR 
   A total of 111 vectors listed in the Table  1  of  FIG. 6  require a negative entry disparity (NDR.) They are listed and sorted in Tables  7 A/B of FIGS.  29 A/B. The expression (A′·B′·C·D·E·F·G·H·I·K′)′ in the leading coding label of Table  7 A prevents the disparity independent vector D 508  from activating NDR. It is a necessary appendix to E·F·H·I but is added as an inhibitor to the entire first group of 36 vectors of the Table  7 A to reduce the number of required levels for the logic circuit implementation. The Table  7 B of  FIG. 29B  represents a block of 64 vectors with the leading 4 bits as follows
 
 ABCD=A⊕B·C·D+C⊕D·A·B,  
 
grouped into 16 quartets with five matching trailing bits EFGHI as listed in the Table  8  of  FIG. 30  with one group (11011) listed redundantly twice. The trailing bits can be identified by the logic expression:
 
(EF+G·E′F′+G′)·H·I+E⊕F·H⊕I·G+(G′H′+I′)·E·F
 
   The NDR equation of  FIG. 30  is derived from the coding labels of the Tables  7 A, and  7 B of FIG.  29 A/B. 
   3) Equation for Complementation of the Primary Vector (CMPLP 10 ) 
   The running disparity at the vector boundaries is constrained to the four values plus or minus one or three. If the required entry disparity PDR or NDR does not match the polarity of running disparity RD, the alternate vector must be used. The alternate vector is generated by complementation of the primary vector. The positive or negative running disparity in front of a byte is referred to as PRDF or NRDF, respectively.
 
 CMPLP 10= PDR·NRDF+NDR·PRDF  
 
   The signals PRDF and NRDF are applied preferably separately upstream to each logic cone, instead of to the complete PDR and NDR functions, to eliminate one level of gating. Note that the equality NRDF=PRDF′ holds. 
   4) Equations for the Running Disparity RD ( FIG. 31 ) 
     FIG. 31  is a state transition diagram for the running disparity RD based on the block disparities DB of the encoded vectors. The vector complementation circuit ensures that the block polarities of vectors conform to the constraints of  FIG. 31 . The running disparity can be represented by two flip-flops which pass the value along from vector to vector The trailing values become the front values of the next encoding cycle. The output of a first flip-flop FFP indicates a positive (PRDF) or negative (NRDF) polarity and the output of a second flip-flop FFA indicates an arithmetic value of one (RD 1 ) or three (RD 3 ). 
   The two flip-flops can assume arbitrary initial values and disparity violations may be generated initially. At least three unbalanced vectors must be transmitted before payload data transmission is allowed to start Additional requirements may have to be met before the receiver disparity monitor is in the ready state. The conditions for complementing these two flip-flops can be derived from  FIG. 31 .
 
 CMPLFFP=DB 2 ·RD 1 +DB 4
 
 CMPLFFA=DB 2 ·RD 3 +DB 4
 
   The block disparity DB 2  in the above equation can have a value of ±2 and DB 4  can have a value of ±4. RD 1  may be RD+1 or RD−1 and RD 3  may be RD+3 or RD−3. The polarities of the above parameters can be ignored for purposes of the above two disparity equations because the complementation function CMPLP 10  enforces compliance. 
   a) Block Disparity of Four for Encoding DB 4   
   The Tables  4 A/B/C of FIG.  27 A/B/C and the Tables  7 A/B of FIG.  29 A/B include 70 and 29 vectors, respectively, with a block disparity of four. The Table  9 A of  FIG. 32  lists the trailing 5 bits of 10 quartets (groups of four) in the left column of Table  4 B of  FIG. 27B . The leading four bits of all these 10 quartets can be defined by:
 
A⊕B·C′·D′+C⊕D·A′·B′
 
   The Table  9 B of  FIG. 32  lists the trailing 5 bits of 4 sextets (groups of six) of Table  4 C of  FIG. 27C  and one sextet from Table  7 A of  FIG. 29A  which includes one vector (C 508 ) with K=1 The leading four bits of all these five sextets can be defined by:
 
A⊕B′·B⊕C·C⊕D′+A⊕B·C⊕D
 
   The value of y in the K column is one for C 508  and zero for D 508 . The data vector D 508  has zero disparity and is excluded by the expression:
 
(A′·B′·C·D·E·F·G·H·I·K′)′.
 
   The Table  9 C of  FIG. 32  lists the trailing 5 bits of 5 quartets of Table  7 B of  FIG. 29B  The leading four bits of all these 4 quartets can be defined by:
 
A⊕B·C·D+C⊕+D·A·B
 
   The 6 vectors of Table  4 A of  FIG. 27A  with DB=4 are defined by the equation:
 
(F⊕H·G⊕I+F+G·H⊕I)·A′·B′·C′·D·E.
 
   The vectors D 367 , D 431 , and D 463  of Table  7 A of  FIG. 29A  are defined by:
 
A·B·C·D·E′·I·(F·G·H′+F·G′·H+F′·G·H).
 
   The DB 4  equation of  FIG. 32  is derived from the coding labels of the Tables  4 A/B/C of FIG.  27 A/B/C, the Tables  7 A/B of FIG.  29 A/B, and the Tables  9 A,  9 B, and  9 C of  FIG. 32 . 
   b) Block Disparity of Two for Encoding DB 2   
   A total of 116 vectors listed in the Table  4  of FIG.  27 A/B/C and  74  vectors listed in Table  7  of FIG.  29 A/B have a block disparity of two. The expression G′·H′K is taken directly from the top of Table  4 A. It represents 10 optional control vectors fox 16B18B code, which are not valid for contiguous 9B10B vectors. The Table  10 A of  FIG. 33  lists the trailing 5 bits of 10 quartets of Table  4 B and one quartet from Table  7 A The leading four bits of these 11 quartets can be defined by:
 
A⊕B·C′·D′+C⊕D·A′·B′
 
   The Table  10 B of  FIG. 33  lists the trailing five bits of 9 sextets from Table  4 C and 5 sextets from Table  7 A The leading foul bits of these 14 sextets can be defined by:
 
A⊕B′·B⊕C·C⊕D′+A⊕B·C⊕D
 
   The Table  10 C of  FIG. 33  lists the trailing five bits of 3 quartets from Table  4 A and  10  quartets from Table  7 B. The leading four bits of all these 14 quartets can be defined by:
 
A⊕B·C·D+C⊕D·A·B
 
   The DB 2  equation of  FIG. 33  is derived from the coding labels of the Tables  4 ,  7 ,  10 A,  10 B, and  10 C 
   B. Logic Equations for 10B9B Decoding 
   It is a feature of this code that only balanced and disparity independent vectors are subject to individual bit changes and the complementation of entire vectors for disparity control is limited to primary vectors for which the source bits ABCDEFGHI are identical to the encoded bits abcdefghi. Consequently, bit decoding and complementation can be executed independently of each other in parallel. 
   1) Individual Bit Decoding 
   The bit decoding tables can be developed from the bit encoding Tables  3   a ,  3   b ,  3   c ,  3   d ,  3   f ,  3   g ,  3   h , and  3   i  of  FIGS. 15 through 24  by substitution of the bits ‘abcdefghi’ for ABCDEFGHI and a separate table for the control bit K. Some of the tables show both complementary bit sets and identical bit sets in the left and the right column; they are illustrated in italic and bold face type, respectively. 
   The j-bit has a value of one for all vectors which require individual bit modifications or full vector complementation for decoding and consequently, the j-position is eliminated from the Tables  11 A through  11 I of  FIGS. 34 through 43 . In the circuits, the j-bit value is added near the end of each logic cone which ostensibly adds one logic level, but this gating level is required for the complementation of entire vectors anyway and the two functions can be implemented with an AOI21 gate with a circuit delay and area which are comparable to typical primitive logic gates. 
   The logic equations for X1 are developed below. X1 is the command to complement an individual bit x where x stands for any one encoded bit. The respective decoded bits X are generated by a circuit implementation of the equation as shown on the right side of  FIG. 56C .
 
 X =( X 1 ·j )⊕ x  
 
   Two circuit simplification methods are available but if two bit positions of a set of vectors are ignored, all four possible combinations must be examined for correct operation:
     1. The decoding equations can be simplified if we allow arbitrary bit changes for the decoding of invalid vectors. Appropriate invalid vectors can be added to the vectors defining a logic expression. In the following, these redundant vectors are not shown, but the terms of logic expressions which can be eliminated by their inclusion are over-lined. Vectors with a leading or trailing run of five are easily recognized as invalid.   2. The value of a bit position before decoding of that bit can be ignored because for this code, the same bit position of a vector which is complementary in that position and equal in all other positions is an alternate or an invalid vector. Alternate vectors are complemented for decoding, as an example, D 16 =1001100011 has the first bit complemented to 0, but the entire vector 0001100011 (D 231 A) is complemented for decoding. However, for decoding classes which are applicable to several bits, the redundant bit is usually included to enable circuit sharing but underlined in the logic equations to indicate that it could be left out, for example, to reduce delay in a critical path.   

   The table labels include all terms, but the equations do not include the terms which are not included in the circuits. 
   Decoded Bit A 
   The ‘a’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 31 vectors listed in Table  11 A of  FIG. 34 . The A-bit decoding equation of  FIG. 34  is derived from the coding labels of Table  11 A. 
   Decoded Bit B 
   The ‘b’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 15 vectors listed in Table  11 B of  FIG. 35 . The B-bit decoding equation of  FIG. 35  is derived from the coding labels of Table  11 B. 
   Decoded Bit C 
   The ‘c’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 31 vectors listed in Table  11 C of  FIG. 36 . The C-bit decoding equation of  FIG. 36  is derived from the coding labels of Table  11 C. 
   Decoded Bit D 
   The ‘d’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 19 vectors listed in Table  11 D of  FIG. 37 . The D-bit decoding equation of  FIG. 37  is derived from the coding labels of Table  11 D. 
   Decoded Bit E 
   The ‘e’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 45 vectors listed in Table  11 E of  FIG. 38 . The E-bit decoding equation of  FIG. 39  is derived from the coding labels of Table  11 E. 
   Decoded Bit F 
   The f column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 19 vectors listed in Table  11 F of  FIG. 40 . The F-bit decoding equation of  FIG. 40  is derived from the coding labels of Table  11 F. 
   Decoded Bit G 
   The ‘g’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 22 vectors listed in Table  11 G of  FIG. 41 . The G-bit decoding equation of  FIG. 41  is derived from the coding labels of Table  11 G. 
   Decoded Bit H 
   The ‘h’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 20 vectors listed in Table  11 H of  FIG. 42 . The H-bit decoding equation of  FIG. 42  is derived from the coding labels of Table  11 H. 
   Decoded Bit I 
   The ‘i’ column has bold entries in the Tables  2 A/B of FIGS.  14 A/B for the 32 vectors listed in Table  11 I of  FIG. 43 . The I-bit decoding equation of  FIG. 43  is derived from the coding labels of Table  11 I. 
   Control Bit K 
   The primary and alternate versions of 18 control vectors at the trailing end of Table  1 M of  FIG. 6M  are listed in Table  11 K of  FIG. 44 . In the absence of errors, a 10-bit vector aligned with the vector boundaries can be identified as the control character C 508  by a run length of 7 in bits c through i because of code constraints. For some applications it may be advisable to check all 10 bits for improved error immunity. The optional control characters for 16B18B code are marked with an asterisk “*” in the ‘Name’ column of the tables and are not valid for contiguous 9B10B vectors. 
   The K-bit decoding equation of  FIG. 44  is derived from the coding labels of Table  11 K. 
   2) Full Vector Complementation 
   The appended bit ‘j’ is dropped before complementation and only the 9 leading bits need to be complemented. It is helpful to remember that for this code all alternate vectors have a j-bit value of one and the only vectors with j=1 which are not alternate vectors are the 116 balanced, disparity independent vectors BM 4 c′ 4 t′ 6 t′J of  FIG. 13  listed in Tables  2 A and  2 B of FIGS.  14 A/B. The equation for the complementation of alternate vectors can thus be expressed by:
 
 CMPL 10 =j ·( BM 4 c ′4 t ′6 t ′)′
 
   An expression in terms of bit values for BM 4 c′ 4 t′ 6 t′ can be derived from the trellis of  FIG. 13 . The left side of Table  12  of  FIG. 45  lists the bit patterns of  FIG. 13  from node  0   b  to the nodes  4   u ,  4   b , and  4   m , and the right side lists the bit patterns from nodes  4   u ,  4   b , and  4   m  to node M. The number of vectors represented is 4·5+6·10+4·9=116. 
   The CMPL 10  of  FIG. 45  is derived from the coding labels of Table  12   
   On the upper right side in the circuit diagram of  FIG. 56C , the part of the equation for COMPL 10  within the brackets{ } is referred to by the net name PBM 4 cn 4 tn 6 tn which references the trellis of  FIG. 13  up to node M. 
   3) Invalid Characters 
   Since there are 828 valid vectors in the code (with all optional control vectors included), there are 196 invalid vectors. They are listed in Table  13  of  FIG. 46 . The first two rows represent 124 vectors with a leading or trailing run of five. The letter x indicates arbitrary values for the bit positions involved. Each of the top two rows represents 64 vectors but only 124 vectors together because of overlap The third row is a complementary vector pair with a disparity of four not included in  FIG. 4C.1  or  4 C. 2 . This is followed by 10 complementary vector pairs with a disparity of two and a leading run of four not included in  FIG. 4B , and a complementary set of 25 vector pairs with disparity of six and not ending or starting with a run of five. The overlined bit positions are redundant because the opposite value would generate a leading or trailing run of five already captured by the top two rows. For concatenated 10B vectors, the optional control vectors identified by the expression INVK must also be included in the set of invalid vectors. The equations for INV and INVK of  FIG. 47  are derived from the coding labels of Table  13  of  FIG. 46  and Table  11 K of  FIG. 44 , respectively. 
   4) Disparity Checks on Decoding 
   Disparity checks serve a variety of purposes with different implementations depending on the application. As an example, long distance, multi-hop carrier type applications require a simple in line quality monitoring system as described for the case of a 7B8B code in the aforementioned Sharland paper Computer links use such checks to help in the isolation of failing link components and to supplement higher level error checking schemes in the goal of weeding out all flawed frames or packets. 
   Some important applications of this code may not be helped much by disparity monitoring and thus may not implement it As an example, a computer bus as described in U.S. Pat. No. 6,978,416 requires separate extensive error checking and collection facilities with low latency. Disparity errors often show up with some delay after one or more disparity independent coding blocks have passed. 
   Some applications may implement simplified monitoring circuits which miss a small fraction of disparity violations, or they may tolerate some double counts, or they may want to deactivate monitoring until a reliable running disparity value is reestablished after an error indication. Some expressions which can be used as building blocks for any such monitoring process are defined below. 
   For some applications, the disparity circuits awe less latency sensitive than the rest of the decoding circuits because system performance is not affected by modest delay in the error detection and perhaps more than one clock cycle is acceptable for the execution of these functions. Therefore, they can be generated by logic synthesis programs rather than a hand-crafted design and no circuit design for disparity monitoring is shown in this report. Any implementation can share many logic expressions with those already implemented for decoding. 
   At a receiver; the vector sequences can be monitored to see whether they still conform to the rules imposed by the encoder. A single or odd number of errors in transmission will always cause a violation of the disparity rules without necessarily generating an invalid vector as described above. In a mixture of balanced vectors, and vectors with a block disparity of ±2 or ±4, the running disparity in the absence of errors is constrained to values of ±1 and ±3 at the vector boundaries A transmission error is not always immediately detectable by just adding and subtracting the cumulative block disparities to see whether the actual running disparity of the received vector sequence meets the above constraints. The following rules assume that the error, if any, occurred before the vector under consideration. If an error is present in the block itself, a duplicate error indication may occur later because the value of the original running disparity following an error is uncertain. The rules apply to any mixture of vectors in the sequence such as 6B, 8B, 10B, or other vectors with compatible disparity characteristics. 
   An error is flagged if the required polarity of the entry disparity of a received coded block does not match the polarity of the running disparity at the start of that block. 
   5) Equations for Required Disparity on Decoding (DR) 
   a) Positive Required Disparity PDR 
   Any valid or invalid vector in  FIG. 1(L)  ending in nodes  10   m ,  10   t ,  10   q ,  10   s , or  10   n  and the 9 balanced vectors of  FIG. 4A.2(R)  require a positive entry disparity. These vectors can be grouped and defined as follows:
         3 or more zeros in the 5 leading bit positions combined with 3 or more zeros in the 5 trailing positions.   4 or more zeros in the 5 leading bit positions combined with 2 or more zeros in the 5 trailing positions.   2 or more zeros in the 5 leading bit positions combined with 4 or more zeros in the 5 trailing positions   5 or more zeros in the 6 leading bit positions or 4 leading zeros.       

   The equation for PDR is shown in  FIG. 48 . 
   b) Negative Required Disparity NDR 
   The equation for the negative required disparity NDR is the same as for PDR but with complementary bit values The equation for NDR is shown in  FIG. 48 . 
   6) Equations for Running Disparity on Decoding (RD) 
   The running disparity is determined by the characteristics of the most recent one or two disparity dependent blocks. Quicker recovery of the running disparity is possible by looking at the three most recent disparity dependent vectors, but the added complexity may not be worthwhile for some applications. Disparity independent blocks are ignored From the state diagram of  FIG. 31 , it is evident that after a block disparity of 4 (DB 4 ), the polarity (PRD/NRD) is known, but not the arithmetic value (RD 1 /RD 3 ). It also shows that the arithmetic value is RD 1  after any block with a disparity of 2 (DB 2 ). The running disparity is at +1 after DB 2  of either polarity followed by PDB 2  with a positive disparity or after PDB 2  followed by one of 9 disparity dependent balanced vectors PDB 0  with a positive required entry disparity RD (D 47 A, D 55 A, D 59 A, D 61 A, D 62 A, D 79 A, D 143 A, D 271 A, D 496 ). The running disparity is at −1 after DB 2  of either polarity followed by NDB 2  with a negative disparity or after NDB 2  followed by one of 9 disparity dependent balanced vectors NDB 0  with a negative required entry disparity (D 47 , D 55 , D 59 , D 61 , D 62 , D 79 , D 143 , D 271 , D 496 A). The primary version of these vectors is illustrated in the trellises of  FIGS. 8A ,  8 B, and  8 C. 
   The Table  14  of  FIG. 49  illustrates how the running disparity can be initially established or reestablished after an error and is used to extract the equations below for the polarity and the arithmetic value of the running disparity. The following acronyms are used: 
   PRD=Positive Running Disparity NRD=Negative Running Disparity 
   PDB 4 =Positive Block Disparity of 4 NDB 4 =Negative Block Disparity of 4 
   PDB 2 =Positive Block Disparity of 2 NDB 2  Negative Block Disparity of 2 
   RD 1 , RD 3 =Arithmetic value of the running disparity is equal 1 or 3, respectively 
   PDB 0 =D 47 A, D 55 A, D 59 A, D 61 A, D 62 A, D 79 A, D 143 A, D 271 A, D 496   
   NDB 0 =D 47 , D 55 , D 59 , D 61 , D 62 , D 79 , D 143 , D 271 , D 496 A 
   The appended letter L(ast) refers to the next preceding disparity dependent block
 
 PRD=PDB 4 +PDB 2·( PDB 2 L+NDB 2 L )+ PDB 0 ·PDB 2 L  
 
 NRD=NDB 4 +NADB 2·( PDB 2 L+NDB 2 T )+ NDB 0 ·NDB 2 L  
 
 RD 1 =PDB 2 +NDB 2+( PDB 4 +NDB 4)· RD 3 L  
 
 RD 3=( PDB 4 +NDB 4)· RD 1 L  
 
   7) Equations for Block Disparity (DB) 
   Invalid vectors which simplify the equations are included and such vectors with more than seven ones or zeros are lumped together with vectors of a disparity of four. 
   a) Positive Block Disparity of Four PDB 4   
   All vectors of this set contain at least seven ones and end with nodes  10   x ,  10   h ,  10   v , or  10   c  in the trellis of  FIG. 1(L) . Invalid vectors with fewer than 3 ones in the leading or trailing 5 bit positions are not included. The vectors belong to one of the following two groups:
         4 or 5 ones in the 5 leading bit positions combined with 3 or more ones in the 5 trailing 4 positions.   3 or more ones in the 5 leading bit positions combined with 4 or 5 ones in the 5 trailing positions.
 
The equation for PDB 4  is shown in  FIG. 50 .
       

   b) Negative Block Disparity of Four NDB 4   
   The equation for the negative block disparity NDB 4  is the same as for PDB 4  but with complementary bit values. The equation for NDB 4  is shown in  FIG. 50   
   c) Positive Block Disparity of Two PDB 2   
   This set includes all vectors with exactly 6 ones ending with node  10   u  in  FIG. 1(L) . Some invalid vectors with 5 leading or trailing ones are included with the assumption that they originated from valid vectors with only 4 ones in the respective 5 bit positions
         3 ones in the 5 leading bit positions combined with 3 ones in the 5 trailing bit positions   2 ones in the 5 leading bit positions combined with 4 or 5 ones in the trailing 5 positions.   4 or 5 ones in the 5 leading bit positions combined with 2 ones in the trailing 5 positions.       

   The equation for PDB 2  is shown in  FIG. 51   
   d) Negative Block Disparity of Two NDB 2   
   The equation for the negative block disparity NDB 2  is the same as for PDB 2  but with complemented bit values. The equation for NDB 2  is shown in  FIG. 51 . 
   e) Zero Block Disparity with a Positive Requited Front end Disparity PDB 0   
   This vector set can be derived from  FIG. 4A.2(R) . The equation for PDB 0  is shown in  FIG. 52 . 
   f) Zero Block Disparity with a Negative Required Front end Disparity NDB 0   
   This vector set can be derived from  FIG. 4A.2(L)  and is the same as for PDB 0  but with complemented bit values. The equation for NDB 0  is shown in  FIG. 52 . 
   9B10B CIRCUIT IMPLEMENTATION 
   For the circuit implementation, it is assumed that all inputs are available in complementary form, i.e. both the +L2 and −L2 outputs of the input register latches are made available. Nevertheless, the assumption is that the −L2 outputs are slightly delayed relative to the +L2 outputs. The circuit diagrams show only NAND, NOR, INV, XOR, XNOR, and AO121 gates and a single OR4 gate in a non-critical path in  FIG. 56A  (Pn 5 ). The use of AND and OR gates has been avoided because of their increased delays. For the NAND and NOR gates, the upper inputs of the logic symbols usually have less delay than the lower ones. The presumed critical paths are therefore routed through the top inputs. The wire routing also assumes that XNOR delays are shorter than XOR delays. The gate representations use bubble notation. A bubble indicates a lower logic level. The functions indicated by the symbols are true if the inputs and outputs are at the levels indicated. Functions suggested by net names are true when at the level indicated by the first letter, P for the upper level and N or n for the lower level. An explanation of the conventions used for net names in the circuits is given above under ‘Notation’. There is some leeway in the definition of the basic logic equations and in the partitioning of the longer expressions to match the fan-in limitations of the gates Variations in these choices leads to different ranges in circuit sharing and circuit counts In circuit areas which are suspected to be in the upper range of circuit delay, the circuit count has occasionally been increased to reduce delay primarily by reducing the fan-in of gates in the critical path. For delay considerations, both XOR and XNOR gates have been used at the input to generate both polarities and the skilled artisan will appreciate that some of those gates can be replaced by INV circuits upon generation of appropriate simulation results. Similarly, the circuit diagrams generally do not show complex gates to allow maximum circuit sharing; the logic processing programs will introduce complex gates automatically where appropriate. 
   Note that some of the logic variables of the equations are not present explicitly in the circuit diagrams. If so, they have been merged with other functions in a single gate to reduce overall circuit delay. An example is the variable PDR which is only present in the merged signal NRDFaPDR of  FIG. 54C . 
   A. Circuit for 9B10B Encoding 
   1) Block Diagram ( FIG. 53 ) 
     FIG. 53  is the block diagram for the encoding circuit with all inputs and outputs shown. 
   2) Gate Level Circuit Diagram ( FIGS. 54A ,  54 B,  54 C) 
   A gate-level circuit diagram of the encoder of  FIG. 53  is shown in  FIGS. 54A ,  54 B, and  54 C, which represent a single circuit with net sharing. 
   a) Individual Bit Complementation 
     FIG. 54A  shows most of the encoding of the leading 5 bits (abcde), the encoding of the trailing 5 bits (fghij) is shown in  FIG. 54B . The upper right side of  FIG. 54C  shows the last two gate levels for bit encoding. The center right side lists a number of EXCLUSIVE OR (XOR and XNOR) gates which are shared across the three encoding circuit diagrams. Some of these gates can be replaced by inverters driven from the gate of opposite polarity if they are not part of any critical timing path. 
   b) Full Vector Complementation Circuit 
   The signal CMPL 10  which complements all 10 bits of a coded byte is orthogonal to the signals (Ca 1 , Cb 1 , Cc 1 , Cd 1 , Ce 1 , Cf 1 , Cg 1 , Ch 1 , Ci 1 ) which cause complementation of individual bits In other words, both for encoding and decoding, no individual bits are changed when a full vector is complemented and vice-versa. This feature allows the merger of both types of signals in a single OR function as shown at the upper right side of  FIG. 54C , greatly simplifying the circuitry preceding the output EXCLUSIVE OR function. The upper left part of  FIG. 54C  shows the implementation of the equations for the complementation of entire vectors. The CMPL10 signal is not explicitly present in the circuit version shown. It is dependent on the required entry disparity and the starting running disparity RDF which is equal to the ending disparity RDI of the preceding byte. Note that the value of RDF is not required immediately at the start of the encoding interval, because in the critical signal paths, it is typically an input to a gate at the third of fourth level, which facilitates pipelining of this logic path into the next cycle if required as described in U.S. Pat. No. 6,977,599 for an 8B10B code. 
   c) Disparity Control 
   The bottom part of  FIG. 54C  shows the equation for the determination whether the polarity and/or absolute value of the running disparity at the end of the new vector has to be changed (CMPLFFP, CMPLFFA). Because these two signals typically feed a flip-flop with a multiplexer input which has a longer setup time than a regular flip-flop, extra gates have been added to reduce the number of logic levels to 6. 
   3) Gate Count, Circuit Delays and Pipelining for Encoding 
   The encoder circuit shown comprises 352 gates and two flip-flops (not shown) to keep track of the disparity No logic path exceeds 7 gates; all gates are of the inverting type with shorter delay except some XOR gates which for most power and loading levels have comparable or only slightly mole delay than XNOR gates. It is estimated that the circuit area can be reduced by about 5% to 10% if 8 gating levels are acceptable. 
   If the circuit does not meet desired performance goals, the first step is to reduce the fin-in of gates in the critical paths by off loading the shorter sections of the logic cone with some additional gates Pipelining can result in larger delay reductions. To this end, the fan-in for the trailing 3 logic levels has been kept low to reduce the number of parameters which must be carried forward. Minor rearrangements may be useful depending on whether one, two, or three trailing logic levels awe moved into a second clock cycle which can reduce the first cycle to four logic levels. 
   A further delay reduction can be accomplished by itself or in combination with any of the above versions by minor circuit modifications and moving some of the leading EXCLUSIVE OR functions into the preceding clock cycle in the data source path 
   B. 10B9B Decoding Circuit 
   1) Block Diagram ( FIG. 55 ) 
   The block diagram for the decoding circuit with all inputs and outputs is shown in  FIG. 55 . 
   2) Gate Level Circuit Diagram ( FIGS. 56A ,  56 B,  56 C) 
   a) Individual Bit Complementation and Validity Check 
   A gate-level circuit diagram of the decoder of  FIG. 55  is shown in  FIGS. 56A ,  56 B, and  56 C which represent a single circuit with net sharing  FIG. 56A  shows the implementation of the equations for the complementation of the first six individual bits (a, b, c, d, e, f) to restore the original values (A, B, C, D, E, F)  FIG. 56B  shows the decoding of the individual trailing three bits (g, h, i) to restore the original values (G, H, I) and the generation of the control bit K. The validity checks are shown at the bottom. 
   b) Full Vector (bit ‘a’ Through ‘i’) Complementation Circuit 
   The circuit which controls the complementation of entire 9-bit vectors at the top of the diagram of  FIG. 56C  generates the signal PBM 4 cn 4 tn 6 tn which complements at the lower level the entire vector to recover the primary version. The signal PBM 4 cn 4 tn 6 tn represents the 116 vectors of  FIG. 13 . The OAI21 gate, which is the negative polarity version of a circuit commonly referred in its positive version as AOI21, is counted as a single logic level because its typical delay and area is comparable to a NAND3 or a XNOR2 gate. 
   c) Error Monitoring Circuits 
   At the bottom of the diagram in  FIG. 56B  is the validity check A specific application may hold unused control vectors in reserve or declare them invalid at the circuit level. The control vectors represented by the signal Pn 60  are invalid for concatenated 9B10B vectors and are then not part of the NK output but are added to the NINV output as shown. A disparity monitoring circuit has not been implemented because bus applications may not use it, and for other applications, the detection of disparity errors may be allowed to take two cycles. The circuits are less time sensitive and can be generated automatically from the equations by design tools The shared EXCLUSIVE OR functions of all 3 diagrams are shown in  FIG. 56C . Again, inverters can be substituted for some of these gates depending on speed requirements. 
   3) Gate Count, Circuit Delays and Pipelining for Decoding 
   The decoder as shown without disparity monitoring comprises 298 gates, all of the inverting type except some XOR gates. No logic path exceeds seven levels. The paths for NK and for PINV are 5 and 6 logic levels, respectively. For fast operation, pipelining can be used analogous to the steps described above for the encoder. The fan-in to the third last gate of the NOR type in the bit decoding cones has been minimized at the cost of a few gates to reduce the number of latches required for pipelining at this point. Some of the 2-way and 3-way OR functions have been moved forward and merged with OR functions at the 4th level back from the end. This requires the duplication of some AND functions. It has been discovered that the circuit penalty is less than apparent, because a uniform design approach results in more matching signal polarities which enables more gate sharing. Similar modifications could be made to the encoding circuit if required. 
   DESCRIPTION OF EXEMPLARY 7B8B TRANSMISSION LINE CODE 
   A. 7B8B Code Definition 
   The 7B8B code comprises a total of 135 code points with 202 coded 8B vectors as illustrated by the trellis diagrams of  FIG. 57 . It should at this point be reiterated that  FIGS. 2A ,  2 B,  3 A and  3 B illustrate the example apparatuses and methods of the 9B10B code but are equally applicable to the 7B8B code if the numbers 10 and 9 are replace by 8 and 7, respectively. Thus, an exemplary method of encoding 7B source vectors into 8B encoded vectors can the steps of obtaining a plurality of 7B source vectors, and encoding the 7B source vectors into a plurality of 8B encoded vectors according to an encoding scheme. The 8B encoded vectors can include at least 8B encoded data vectors (“at least” is included to signify that, e.g., control vectors could be included in addition to the data vectors) The encoding scheme maps at least a first portion of the 7B source vectors into 8B encoded data vectors comprising disparity independent encoded vectors, and the encoding scheme maps at least a second portion of the 7B source vectors into 8B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations. The 8B encoded data vectors have one binary symbol appended thereto by the encoding scheme. 
   A fraction of the 8B encoded data vectors have binary symbol changes, other than whole-vector complementation, compared to corresponding ones of the 7B source vectors, the fraction not including any of the disparity dependent encoded representations. None of the encoded data vectors comprise exclusively alternating ones and zeroes (it is to be understood that in other embodiments, vectors comprising exclusively alternating ones and zeroes could be used as data vectors; for example, decision feedback equalization (DFE) typically requires a run of at least two for error recovery, but where DFE is not employed this may not be a concern so that vectors comprising exclusively alternating ones and zeroes could be used as data vectors). Optionally, the fraction of the 8B encoded vectors includes the disparity independent encoded vectors, and the disparity independent encoded vectors are dc-balanced and have no alternate representations. 
   The 7B source vectors can include 7B source data vectors and at least one 7B source control vector The encoding scheme can further map the at least one 7B source control vector into at least one 8B encoded control vector, and at least some of the second portion of the 7B source vectors, that are mapped into 8B encoded data vectors comprising disparity dependent encoded vectors having primary representations and alternate representations complementary to the primary representations, are mapped to dc-balanced 8B encoded data vectors. 
   The first portion of the 7B source vectors is mapped into 8B encoded vectors comprising a set of 34 disparity independent encoded vectors which does not require any bit changes during encoding, and the first portion of the 7B source vectors includes source vectors having:
         a disparity of +1,   a leading run-length no greater than 3,   no more than 2 trailing zeros in the case of those of the source vectors having trailing zeroes, and   no more than 4 trailing ones in the case of those of the source vectors having trailing ones.       

   The source vectors of the first portion are appended during encoding with a single binary symbol with a value of zero. 33 of the 34 disparity independent encoded vectors comprise the encoded data vectors, and a remaining one of the 34 disparity independent encoded vectors, comprising alternating ones and zeros, is defined as the encoded control vector. In other embodiments, such vector could instead be defined as an invalid vector; indeed, in general, any or all control vectors can instead be defined as invalid characters (invalid vectors) and synchronization can be acquired via techniques other than the comma character. 
   The first portion of the 7B source vectors can be mapped into 8B encoded vectors comprising a set of 34 disparity independent encoded vectors, a fraction of the 34 disparity independent encoded vectors requiring individual bit changes during encoding. The set of 34 encoded vectors comprises vectors having seven leading binary symbols with a disparity of −1, having:
         a leading run-length no greater than 3,   no more than 2 trailing ones in the case of those of the source vectors having trailing ones, and   no more than 4 trailing zeros in the case of those of the source vectors having trailing zeroes.       

   The first portion of the 7B source vectors becomes a 7B set, the 7B set being appended with a single binary symbol with a value of one when being encoded to obtain the 34 encoded vectors. As noted above for the 9B10B example, the terminology “7B set” is employed to accommodate the fact that some of the source bits are changed before they become the first 7 bits of the encoded 33 of the 34 encoded vectors comprise the encoded data vectors and a remaining one of the 34 disparity independent encoded vectors, comprising alternating ones and zeros, is defined as the encoded control vector. In other embodiments, such vector could instead be defined as an invalid vector; indeed, in general, any or all control vectors can instead be defined as invalid characters (invalid vectors) and synchronization can be acquired via techniques other than the comma character. 
   As with the 9B10B example, complementary implementations are possible and are intended to be encompassed within the inventive scope For example, the first portion of the 7B source vectors could be mapped into 8B encoded vectors comprising a set of 34 disparity independent encoded vectors which does not require any bit changes during encoding, and the first portion of the 7B source vectors could comprise source vectors having:
         a disparity of −1,   a leading run-length no greater than 3,   no more than 2 trailing ones in the case of those of the source vectors having trailing ones, and   no more than 4 trailing zeroes in the case of those of the source vectors having trailing zeroes.       

   Further, the source vectors of the first portion could be appended during encoding with a single binary symbol with a value of one, 33 of the 34 disparity independent encoded vectors could comprise the encoded data vectors, and a remaining one of the 34 disparity independent encoded vectors, comprising alternating zeroes and ones, could be defined as the encoded control vector. 
   By way of further comment on a possible complementary implementation, the first portion of the 7B source vectors could be mapped into 8B encoded vectors comprising a set of 34 disparity independent encoded vectors, with a fraction of the 34 disparity independent encoded vectors requiring individual bit changes during encoding, and the set of 34 encoded vectors could comprise vectors having seven leading binary symbols with a disparity of +1, and having:
         a leading run-length no greater than 3,   no more than 2 trailing zeroes in the case of those of the source vectors having trailing zeroes, and   no more than 4 trailing ones in the case of those of the source vectors having trailing ones.       

   The first portion of the 7B source vectors could become a 7B set, the 7B set (note discussion of “set” terminology above) being appended with a single binary symbol with a value of zero when being encoded to obtain the 34 encoded vectors, 33 of the 34 encoded vectors comprising the encoded data vectors and a remaining one of the 34 disparity independent encoded vectors, comprising alternating zeroes and ones, being defined as the encoded control vector. As noted above, in other embodiments, such vector could instead be defined as an invalid vector; indeed, in general, any or all control vectors can instead be defined as invalid characters (invalid vectors) and synchronization can be acquired via techniques other than the comma character. 
   As with the 9B10B example, variations from the source to encoded vector assignments are possible, for example:
         (i) The appended binary symbol has a default value of 1 and some or all of the specifications for the primary approach are changed to complementary bit values and disparity polarities   (ii) Some or all primary and alternate vector sets are swapped with the respective complementary sets, either in combination with (i) or independently.       

   An exemplary method of decoding 8B encoded vectors into decoded 7B source vectors can include the steps of obtaining a plurality of 8B encoded vectors that were encoded from a plurality of 7B source vectors according to an encoding scheme as described herein, and decoding the 8B encoded vectors into a plurality of 7B source vectors according to decoding rules of the encoding scheme. An additional optional step can include checking the plurality of 8B encoded vectors for selected ones of the encoded vectors that are not balanced and that end with a predetermined binary symbol, the predetermined binary symbol comprising a “one” in a primary implementation of the encoding scheme, and the predetermined binary symbol comprising a “zero” in a complementary implementation of the encoding scheme. In such case, the decoding comprises at least automatically complementing the selected ones of the encoded vectors As discussed with the 9B10B exemplary implementation, the 7B81B implementation is also specially designed to allow one to look for auto complementation, and there can be some other cases of auto complementation, such as, for example, dc balanced vectors ending with four ones (or, four zeroes in complementary form). 
   1) 68 Balanced 8B Vectors ( FIG. 57A.1 ) 
   A set of 68 disparity independent, balanced vectors is illustrated in  FIG. 57A.1 . The subset (68) of all possible 8B vectors (256) chosen is the set of balanced vectors with a run length of no more than three at the leading and trailing boundaries. 
   2) One Disparity Dependent, Balanced Complementary Vector Pair 
   The code includes one disparity dependent, balanced, complementary vector pair as illustrated in  FIG. 57A.2  with a leading and trailing run of four. It is assigned to the source vector D 15 =1111000. 
   3) 2×48 8B Vectors with Disparity +/−2 ( FIG. 57B ) 
     FIG. 57B  shows a set of 48 8B vectors comprising all valid bit patterns with a disparity of 2, no more than three ones or two zeros at the front end and no more than two zeros or three ones at the trailing end. An exact complementary set of another 48 vectors has a disparity of 2. 
   4) 2×18 8B Vectors with Disparity +/−4 ( FIG. 57C ) 
   The set of twelve 8B vectors of  FIG. 57C.1  comprises all bit patterns with a disparity of 4, no more than three ones or one zero at the front end and one to three ones at the trailing end. An exact complementary set of another 12 vectors has a disparity of 4.  FIG. 57C.2  illustrates a set of six vectors with a disparity of +4 and no more than two ones or one zero at the front and exactly one zero or 4 ones at the end. An exact complementary set of another 6 vectors has a disparity of 4. The leading part of the comma character for concatenated 8B vectors belongs to  FIG. 57C.2 . 
   5) Comma Characters for Concatenated 7B8B Coding Blocks and for 16B18B Code 
   To generate a comma, two 8B blocks are required. For this purpose, the control character C 126  with a run of six has been added. It is listed at the bottom of Table  15 D of  FIG. 68D . The control character C 126  can be used to generate a singular comma consisting of a run length of six followed contiguously by a run of one and ending with a run of three of the same polarity as the leading run of six (0000001′000 or 1111110&#39;111). Only the nine bold bits must be checked for synchronization The comma is embedded in two blocks of eight coded bits and is illustrated for one polarity in  FIG. 58 . The second byte is taken from the group of balanced vectors of  FIG. 57A.1 . These vectors must be made disparity dependent if they follow C 126  of Table  15 D to obtain a comma sequence regardless of the running disparity. 
   
     
       
         
             
             
             
           
             
                 
                 
             
           
          
             
                 
               D7  + 11100001 − 00011110 
               D120 
             
             
                 
               D23 + 11101000 − 00010111 
               D112 
             
             
                 
               D39 + 11100100 − 00011011 
               D95 
             
             
                 
               D71 + 11100010 − 00011101 
               D63 
             
             
                 
                 
             
          
         
       
     
   
   The trailing 8B patterns are identical to the trailing vector of the 16B18B comma of U.S. Pat. No. 6,198,413 where C 126  is replaced by C 508  (0011111110/1100000001) from the 10B alphabet. 
   B. Other Applications 17B20B, 12B14B Code ( FIG. 59 ) 
   Machine upgrades sometimes require serialization of parallel buses to deal with entry and exit congestion at the board level or other modular building blocks. These serial links are usually not based on neatly designed new serial architectures but must be based on existing bus structures which may not be modulo eight in width. To serve these requirements, it is useful to have a variety of code widths in the design arsenal and techniques to combine them into a wider structure. As an example, one application requires the efficient conversion of a 17-bit bus into serial form. This could be solved by two parallel 9B10B coders, which would provide one bit of spare capacity in a 20-bit coded block. Another, perhaps simpler and adequate solution combines one 7B8B coder with two 5B6B coders taken from U.S. Pat. No. 4,486,739 or 6,977,599 B2 to translate the 17 source bits into 20 coded bits suitable fox serial transmission. 
   The resulting 17B20B code has a maximum run length of 6 and a digital sum variation of 10. The synchronizing sequence or comma can be defined as a run of 6, contiguously followed by a run of one and ending with run of 2 of the same polarity as the leading run of six (111111011 or 000000100) as shown in  FIG. 59 . This sequence can be generated by C 126  from the 8B alphabet followed by the balanced vectors D 3 , D 11 , or D 19  from the 6B alphabet of the Widmer article on The ANSI Fibre Channel Transmission Code or U.S. Pat. No. 4,486,739 Again, the three balanced 6B vectors must be made disparity dependent if they follow C 126 . If the running disparity at the front of the 6B section is negative, they must be complemented as shown below 
   
     
       
         
             
             
             
             
           
             
                 
                 
             
           
          
             
                 
               D3 
               110001 − 001110 
               D28 
             
             
                 
               D11 
               110100 − 001011 
               D20 
             
             
                 
               D19 
               110010 − 001101 
               D12 
             
             
                 
                 
             
          
         
       
     
   
   Given the teachings herein, the skilled artisan will appreciate that the same rules apply to a 12B14B code which would be partitioned into a 7B8B code followed by a single 5B6B code. 
   C. Properties of the 7B8B (Code  FIG. 60 ) 
   Significant characteristics of the code can be directly extracted from the trellis diagram of  FIG. 60 , which also shows four possible configurations for the comma sequence. Using  FIG. 60  together with the trellis diagrams of  FIG. 57 , one can verify that the coma sequence is singular, i.e., it cannot be reproduced in any other position relative to the vector boundaries neither within two 8B blocks nor across the 8B block boundaries. 
   1) Low Frequency Characteristics 
   The code is DC balanced. The maximum digital sum variation is 12. The normalized DC offset, as defined in the Widmer article on the ANSI code, is 4.75. As a point of reference, the offset value of 8B10B code is 1.9. The low frequency cut-off point for high pass filters must be located about 2.5 times lower than for Fibre Channel 8B10B code for equal eye closure. The low frequency wander can be reduced on a statistical basis by scrambling the data before encoding. 8B10B coded data can operate with a 50% higher low frequency cut-off point than a coded worst case pattern For 7B8B code, the gain from scrambling before encoding is expected to be more because there are more and larger low frequency components to randomize. 
   2) Control Characters 
   The 7B5B code provides seven control characters which are recognizable as other than data. One of the control characters (C 126 ) is used to generate the singular comma sequence for instantaneous vector boundary synchronization and other signaling purposes The comma sequence extends over 10 baud intervals and 9 of the coded bits must be monitored The sequence requires two contiguous 8B vectors and as shown in  FIG. 60 . The comma sequence is followed by one of four different 4-bit trailing sequences. 
   3) Clocking and Synchronization Parameters 
   The maximum run length of the code is seven and no more than two contiguous runs of seven are possible (0111-11110000-0001 or complement). The minimum transition density is two pet 8B block for an indefinite length (-11110000-11110000- or complement) 
   D.7B8B Encoding Table 
   1) Design Principles 
   101 of the 135 encoded primary vectors are obtained by simply appending a bit with a default value of zero. An alternate, equivalent code can be constructed by choosing complementary values for the appended bit and the vector sets. All 34 vectors with individual bit changes other than full vector complementation are disparity independent with an appended bit value of one. Only 25 vectors require any changes in one to four individual source bits This arrangement has the advantage that full vector complementation and bit encoding and decoding can be executed independently of each other in parallel. 
   2) 7B8B Coding Table Construction 
   Table  15  of  FIGS. 68A through 68D  represents a specific coding assignment between uncoded and coded vectors in the 7B8B domain. In the column ‘Bit Encoding Class,’ K′ within parentheses for the vectors D 7 , D 23 , D 39 , and D 71  means that the K-bit value need not be considered for bit encoding since the encoded Dx vector and the primary KxP vector are identical; the K-bit value for these vectors is only significant for the required entry disparity DR. 
   a) 101 7B Primary Vectors Congruent with the First 7 Bits of the Coded 8B Vectors 
   For 101 source vectors, represented by the trellis diagrams of  FIGS. 61 ,  62 ,  63 ,  64 ,  65 , and  66 , the first 7 bits of the primary encoded vectors are identical to the corresponding source vectors and the appended bit assumes the default value (0). The set of vectors BU 4 c′ of  FIG. 61  uses up half the disparity independent balanced vectors of  FIG. 57A.1   
   Enumeration of 34 Vectors BU 4 c′ of  FIG. 61   
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D23 
               D27 
               D29 
               D30 
               D39 
               D43 
               D45 
               D46 
               D51 
               D53 
             
             
               D54 
               D57 
               D58 
               D60 
               D71 
               D75 
               D77 
               D78 
               D83 
               K85 
             
             
               D86 
               D89 
               D90 
               D92 
               D99 
               D101 
               D102 
               D105 
               D106 
               D108 
             
             
               D113 
               D114 
               D116 
               D120 
             
             
                 
             
          
         
       
     
   
   The primary vector BU 4 c of  FIG. 62  and  FIG. 57A.2(L)  is balanced and disparity dependent with a negative required entry disparity It is assigned to the data vector D 15 . 
   The primary vector set DC 4 c′ of  FIG. 63  has a disparity of +2 and uses 18 of the 48 vectors shown in FIG.  57 B(L). The complementary alternate set is part of FIG.  57 B(R). 
   Enumeration of 18 Vectors DC 4 c′ of  FIG. 63   
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D55 
               D59 
               D61 
               D62 
               D87 
               D91 
               D93 
               D94 
               D103 
               107 
             
             
               D109 
               D110 
               D115 
               D117 
               D118 
               D121 
               D122 
               D124 
             
             
                 
             
          
         
       
     
   
   The primary vector set FI 4 m of  FIG. 64  has a disparity of −4 and matches all 12 vectors shown in  FIG. 57C.1(R) . The complementary alternate set is shown in  FIG. 57C.1(L) . 
   Enumeration of 12 Vectors FT 4 m of  FIG. 64   
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D17 
               D18 
               D20 
               D24 
               D33 
               D34 
               D36 
               D40 
               D65 
               D64 
             
             
               D68 
               D72 
             
             
                 
             
          
         
       
     
   
   The set of 30 primary vectors DM 4 u′ 4 t′ of  FIG. 65  has a disparity −2 and uses the remaining 30 of the 48 vectors shown in FIG.  57 B(R). The complementary alternate set is part of FIG.  57 B(L). 
   Enumeration of 30 Vectors DM 4 u′ 4 t′ of  FIG. 65   
   
     
       
         
             
             
             
             
             
             
             
             
             
             
           
             
                 
             
           
          
             
               D19 
               D21 
               D22 
               D25 
               D26 
               D28 
               D35 
               D37 
               D38 
               D41 
             
             
               D42 
               D44 
               D49 
               D50 
               D52 
               D56 
               D67 
               D69 
               D70 
               D73 
             
             
               D74 
               D76 
               D81 
               D82 
               D84 
               D88 
               D97 
               D98 
               D100 
               D104 
             
             
                 
             
          
         
       
     
   
   The 6 primary vectors shown in  FIG. 66  are the vectors also illustrated in true and complement form in  FIG. 57C.2 . The vector C 126  in dash-dot lines on the right side is used to generate a comma character for concatenated 7B8B sequences and for 17B20B code. 
   b) 34 Primary Vectors with modified Source Bits for Encoding 
   All the encoded vectors with individual bit changes belong to the set of balanced disparity independent vectors BM 4 t′Z of  FIG. 67  and are identified in Table  16  of  FIG. 69 . The expression BM 4 t′ refers to the leading 7 encoded bits only. This set of vectors uses up the remaining half of  FIG. 57A.1 . For this subset of disparity independent vectors, one or more bits STUVWXYZ of the augmented source vector have to be complemented to fit the respective coded vector. 
   The 34 encoded vectors together with their assigned uncoded vectors are listed in Table  16  of  FIG. 69 . The bit in the S column of Table  16  is one if there is some symmetry in the bit patterns between the left and light side. The encoded bits which are obtained by complementation of the respective uncoded bit are shown in bold type. 
   c) Value of Control Bit K 
   The vectors K 7 , K 23 , K 39 , and K 71  of Table  15 D of  FIG. 68D  are not true control characters because by themselves, they can not be distinguished from data. They have control functions only in combination with the preceding control character C 126 , or C 508  in the context of the 16B18B code The K-bit value for these pseudo control characters can be either supplied externally or be supplanted by the leading comma part which is the preferred implementation because it simplifies the recovery of the K-bit for the true control characters at the cost of limiting the use of C 126  and C 508  to comma sequences and no other independent stand alone control functions. For the preferred implementation, the K-bit value of these 4 vectors can assume a zero value and the respective entries in the K-column of Table  15  could be changed to x. A value of 1 is shown as a reminder that these vectors are disparity dependent when following C 126  or C 508 . 
   For a majority of data vectors, the value of the K-bit can be ignored. It must be considered for all true control characters and for all data classes for which the bit encoding for some source vectors is different for data and control. For the class of DM 4 u′ 4   t ′ of  FIG. 65 , the vectors D 19 , D 22 , D 42 , D 50 , and D 74  are encoded differently from K 19 , K 22 , K 42 , K 50 , and K 74 , respectively. The same is true for the vector K 85  of  FIG. 61  and D 85  of Table  16  of  FIG. 69  and the vector D 126  of Table  16  and C 126  of  FIG. 66(R) . In contrast, the coded primary vectors and the disparity DB for D/K 7 , D/K 23 , D/K 39 , and D/K 71  are identical; the only difference is the required entry disparity DR. 
   LOGIC EQUATIONS FOR 7B8B IMPLEMENTATION 
   A. Logic Equations for 7B8B Encoder 
   1) Equations for Individual Bit Encoding 
   Generally, the encoded bits retain the value of the uncoded bit (s-S, t=T, etc), but the source bit is complemented (s=S′, t=T′, etc) if the respective equation below is true. 
   Encoded Bits 
   The ‘s’ column has bold entries in Table  16  of  FIG. 69  for the 15 vectors listed in Table  17   s  of  FIG. 70 . The s-bit encoding equation of  FIG. 70  is derived from the coding labels of Table  17   s.    
   Encoded Bit t 
   The ‘t’ column has bold entries in Table  16  of  FIG. 69  for the 9 vectors listed in Table  17   t  of  FIG. 71 . The t-bit encoding equation of  FIG. 71  is derived from the coding labels of Table  17   t.    
   Encoded Bit u 
   The ‘u’ column has bold entries in Table  16  of  FIG. 69  for the 4 vectors listed in Table  17   u  of  FIG. 72 . The u-bit encoding equation of  FIG. 72  is derived from the coding labels of Table  17   u.    
   Encoded Bit v 
   The ‘v’ column has bold entries in Table  16  of  FIG. 69  fox the 7 vectors listed in Table  17   v  of  FIG. 73 . The v-bit encoding equation of  FIG. 73  is derived from the coding labels of Table  17   v.    
   Encoded Bit w 
   The ‘w’ column has bold entries in Table  16  of  FIG. 69  for the 6 vectors listed in Table  17   w  of  FIG. 74 . The w-bit encoding equation of  FIG. 74  is derived from the coding labels of Table  17   w.    
   Encoded Bit x 
   The ‘x’ column has bold entries in Table  16  of  FIG. 69  for the 2 vectors listed in Table  17   x  of  FIG. 75 . The x-bit encoding equation of  FIG. 75  is derived from the coding labels of Table  17   x.    
   Encoded Bit y 
   The ‘y’ column has bold entries in Table  16  of  FIG. 69  for the 8 vectors listed in Table  17   y  of  FIG. 76 . The y-bit encoding equation of  FIG. 76  is derived from the coding labels of Table  17   y.    
   Encoded Bit z 
   The default value for the z-bit is zero. The z-bit is changed to one for the vectors with bold entries in the ‘z’ column of Table  16  of  FIG. 69 . The respective 34 vectors are listed in Table  17   z  of  FIG. 77 . The z-bit encoding equation of  FIG. 77  is derived from the coding labels of Table  17   z.    
   2) Equations for Required Disparity for Encoding DR 
   a) Positive Required Disparity PDR, Table  18   
   A total of 49 vectors listed in Table  18  of FIGS.  78 A/B require a positive entry disparity 30 belong to the class DM 4 u′ 4 t′ of  FIG. 65 , 12 to the class FT 4 m of  FIGS. 64 , and 3 to the class FI 3 m 4 b of  FIG. 66(L) . In addition, 4 primary pseudo-control vectors for the generation of commas also require a positive entry disparity (Table  15 D of  FIG. 68D : K 7 , K 23 , K 39 , K 71 ) The equation for positive required disparity PDR can thus be written as shown in  FIG. 78B . 
   The 4 pseudo-control characters may be governed by the higher level protocol which may set the respective K-value to 1, or it may be governed by an encoding circuit which automatically sets the K-value to 1 for vectors which follow the leading part of a comma. In the second case, ‘K’ in the last coding label of Table  18 B is replaced by ‘C 126 ’, which assumes a value of one if it is preceded by the C 126  vector for concatenated 8B vectors, or K is replaced by ‘C 508 ’ which likewise assumes a value of one if preceded by the C 508  vector of the 9B10B code in the 16B18B application. 
   b) Negative Required Disparity for Encoding NDR, Table  19   
   A total of 22 vectors listed in Table  19  of  FIG. 79  require a negative entry disparity 18 belong to the class DC 4 c′ of  FIG. 63 , 3 to the class FV 3 u of  FIG. 66(R) , and the vector BU 4 c is shown in  FIG. 62 . The coding label for C 126  can be verified by an examination of the bottom 11 rows of Table  15 D of  FIG. 68D . The equation for negative required disparity NDR can be written as shown in  FIG. 79 . 
   3) Equation for Complementation of the Primary Vector (CMPLP 8 ) 
   The explanations given above for COMPL 10  of the 9B10B code are applicable here as well.
 
 CMPLP 8 =PDR·NRDF+NDR·PRDF  
 
   4) Equations for Running Disparity RD ( FIG. 31 ) 
   The explanations given above for the Running Disparity of the 9B10B code are applicable here as well.
 
 CMPLFFP=DB 2 ·RD 1 +DB 4
 
 CMPLFFA=DB 2 ·RD 3 +DB 4
 
   a) DB4, Block Disparity of Four for Encoding 
   The set of three primary vectors FV 3 u with a positive block disparity of four is illustrated in  FIG. 66(R)  and the set of 15 primary vectors with a negative block disparity of four is illustrated in  FIG. 64  and  FIG. 66(L)  and belongs to the coding class FI 4 m and FT 3 m 4 b, respectively. The 18 vectors are listed in Table  20  of  FIG. 80  and grouped for easy implementation. The equation for DB 4  in  FIG. 80  is extracted from Table  20 . 
   b) DB2, Block Disparity of Two for Encoding 
   A set of 18 primary vectors DC 4 c′ illustrated in  FIG. 63  has a positive block Disparity of two. A set of 30 primary vectors DM 4 u′ 4 t′ illustrated in  FIG. 65  has a negative block disparity of two. The 48 vectors are listed and sorted for easy implementation in Table  21  of  FIG. 81 . The equation for DB 2  in  FIG. 82  is extracted from Table  21 . 
   B. Logic Equations for 8B7B Decoder 
   Significant circuit simplifications are enabled if the outcome of the decoding process for invalid vectors is allowed to be arbitrary. This primarily refers to vectors with disparities other than ±4, ±2, or 0, and to vectors with violations of the leading or trailing run length limitations. The decoding process is also simplified because of the following features:
         Full vector complementation to obtain the primary vector from an alternate vector can proceed in parallel with individual bit complementation because all 25 vectors which require individual bit changes are disparity independent and have no alternate version   The code has been constructed so all 71 alternate vectors with the exception of K7 have a z-value of one. The only other vectors with a z-value of one are the 34 balanced, disparity independent vectors listed in Table  16  of  FIG. 69  which have no alternate version.   All 25 vectors which require individual bit changes are balanced and have a z-value of one.   Decoding and validity checks are independent of each other and can proceed in parallel as illustrated in  FIG. 3A .       

   Because of the simplicity of the decoding process, no decoding table is given. The skilled artisan, given the teachings herein, can readily refer to Table  15  of  FIG. 68 , Table  16  of  FIG. 69 , or Table  22  of  FIG. 84  which list all 25 vectors which require individual bit changes Bits among the first seven encoded positions which must be complemented for decoding are marked in bold type. 
   1) Decoding Procedures
     1. All vectors ending with z=0 are decoded by simply stripping bit z (except K 7 A; see item 4 below)   2. For all unbalanced vectors ending with z=1 and the vector 00001111 (D 15 A), the z-bit is dropped and the leading 7 bits are complemented to obtain the decoded vector.   3 For the 34 balanced vectors of Table  16  of  FIG. 69  with z=1, the z-bit is dropped and 25 of these vectors, also listed in Table  22  of  FIG. 84  require one to four individual bit changes in the leading 7 positions. For 7, 11, and 6 vectors 1, 2, and 3 bits are complemented, respectively A single vector requires 4 bit changes   4. The control bit K is recovered by special considerations and 4 alternate vectors associated with comma generation (K 7 A, K 23 A, K 39 A, K 71 A) follow a special rule for vector complementation.   

   2) Full Vector Complementation 
   A single image, the primary vector of each complementary pair of vectors is created by complementing the leading 7 bits of all alternate vectors. There are two categories of alternate vectors:
         A first category of 67 alternate vectors is identified by a z-bit value of one and a bit pattern ‘stuvwxy’ other than associated with the 34 vectors illustrated in  FIG. 67  and listed in Table  16  of  FIG. 69 . A set of equations for these vectors can be derived directly from  FIG. 67 . The first line in the equation CMPLA (Complement Alternate Vector) below represents the 18 vectors through node  4   b , the second line represents the 12 vectors through node  4   m , and the third line represents the 4 vectors through node  4   u.      A second category of 4 alternate vectors listed above under “Comma Characters for concatenated 7B8B Coding Blocks and for 16B18B Code” is identified by its position contiguously following the vector C 126 , or C 508  in the context of the 16B18B code, i.e. having one of the C 126  or C 508  vectors as a prefix, and having three leading zeros followed by a one and a single zero in the last four bit positions. This condition is identified in the equation for complementation below by the expression:
 
C126PREF·(w⊕x·y·z+y⊕z·w·x)·s′·t′·u′·v.
       

   The equation CMPLA for the complementation of alternate vectors can now be expressed by the equation of  FIG. 83 . 
   3) Individual Bit Complementation 
   Bit mapping from the primary coded vectors back to the source vectors is accomplished by dropping the z-bit and complementation of selected bits for a minority of 25 disparity independent vectors extracted from Table  16  of  FIG. 69  and listed in Table  22  of  FIG. 84 . In Table  22  of  FIG. 84 , bit values in bold type must be complemented for decoding. Bit values in italic are either identical on several rows or complementary between the left and right side. Bit values in nonitalic type are equal on the left and right side if there is a 1 in the SY column. SY in this case stands for ‘Symmetry’, not the decoded bit values S and Y. 
   For the decoding of each bit, the vectors with a bold bit value for the bit column in question in Table  22  of  FIG. 84  are extracted and arranged in groups with commonalities in new Tables  23 S through  23 Y of  FIGS. 85 through 91 . Explicit decoding equations are then derived from the set of coding labels. In the Tables  23 S through  23 Y, and  23 K of  FIG. 92 , bit values in bold are complementary between the left and right side, and bit values in italic type are equal on the left and right side if there is a 1 in the SY column. The value of a bit position before decoding of that bit can be ignored because the same bit position of a vector which is complementary in that position and equal in all other positions is an alternate or invalid vector. Alternate vectors are complemented for decoding, as an example, D 8 =10010101 has the first bit complemented to 0, but the entire vector 00010101 (D 87 A) is complemented for decoding. However, for decoding classes which are applicable to several bits, the redundant bit is usually included to enable circuit sharing but underlined in the logic equations to indicate that it could be left out, e.g., to reduce delay in a critical path. 
   4) Logic Equations for 8B′7B Bit Mapping 
   Decoded Bit S 
   The 15 vectors which require complementation of the s-bit for decoding as indicated by a bold bit-value in the s-column of Table  22  of  FIG. 84  are listed in Table  23 S of  FIG. 85 . The S-bit decoding equation of  FIG. 85  is derived from the coding labels of Table  23 S. 
   Decoded Bit T 
   The 9 vectors which require complementation of the t-bit for decoding as indicated by a bold bit-value in the t-column of Table  22  of  FIG. 84  are listed in Table  23 T of  FIG. 86 . The T-bit decoding equation of  FIG. 86  is derived from the coding labels of Table  23 T. Because the value of bit t can be ignored, the expression s⊕t·t⊕u in the first row could be replaced by s⊕u′, but the full expression is retained to allow circuit sharing with V-bit and W-bit decoding. The expression s⊕t′·t⊕x′ in the second row could be replaced by s⊕x′ and is also retained to allow circuit sharing with S-bit decoding. 
   Decoded Bit U 
   The 4 vectors which require complementation of the u-bit for decoding as indicated by a bold bit-value in the u-column of Table  22  of  FIG. 84  are listed in Table  23 U of  FIG. 87 . The U-bit decoding equation of  FIG. 87  is derived from the coding labels of Table  23 U of  FIG. 87 . 
   Decoded Bit V 
   The 7 vectors which require complementation of the v-bit for decoding as indicated by a bold bit-value in the v-column of Table  22  of  FIG. 84  are listed in Table  23 V of  FIG. 88 . The V-bit decoding equation of  FIG. 88  is derived from the coding labels of Table  23 V Because the value of bit v can be ignored, the expression u⊕ v·v ⊕w′ in the first row can be replaced by u⊕w but is retained to enable circuit sharing with w-bit decoding. 
   Decoded Bit W 
   The 6 vectors which require complementation of the w-bit for decoding as indicated by a bold bit-value in the w-column of Table  22  of  FIG. 84  are listed in Table  23 W of  FIG. 89 . The W-bit decoding equation of  FIG. 89  is derived from the coding labels of Table  23 W Because the value of bit w can be ignored, the expression v⊕ w′·w ⊕x in the first row could be replaced by v⊕x and the expression v⊕ w·w ⊕x in the third row by v⊕x″. The expression v⊕ w′·w ⊕x is retained to allow circuit sharing with bit v and v⊕ w·w⊕ x is retained because v⊕x′ would require an additional NOR gate. 
   Decoded Bit X 
   The 2 vectors which require complementation of the x-bit for decoding as indicated by a bold bit-value in the x-column of Table  22  of  FIG. 84  are listed in Table  23 X of  FIG. 90 . The W-bit decoding equation of  FIG. 90  is derived from the coding labels of Table  23 X. 
   Decoded Bit Y 
   The 8 vectors which require complementation of the y-bit for decoding as indicated by a bold bit-value in the y-column of Table  22  of  FIG. 84  are listed in Table  23 Y of  FIG. 91 . The Y-bit decoding equation of  FIG. 91  is derived from the coding labels of Table  23 Y. 
   Decoded Bit K 
   The 8 true control vectors with a decoded K-bit value of one are listed in Table  23 K of  FIG. 92 . The first 7 bits of the vector C 126 A are complemented along with the unbalanced data vectors with a z-bit value of one The K-bit equation of  FIG. 92  is derived from the coding labels of Table  23 K. 
   C. Error Checking 
   1) Invalid 8B Vectors 
   The 8B alphabet of  FIGS. 57A.1 ,  57 A. 2 ,  57 B,  57 C. 1 , and  57 C. 2  comprises 202 valid vector&#39;s, so there are a total of 54 invalid 8B vectors One invalid vector I 255 P ends with node  8   h  in  FIG. 1(L) , eight invalid vectors end with node  8   v , ten with node  8   c , and eight with node  8   u . All complements of these 27 vectors are also invalid. All 54 invalid vectors axe listed in Table  24  of  FIG. 93  and the equation shown there for invalid 8B characters INVAL 8  is derived from the coding labels listed in the table. 
   2) Disparity Checks on Decoding 
   The general comments given above for 10B disparity checks apply equally to 8B disparity checks. 
   3) Equations for Required Disparity on Decoding (DR) 
   a) Positive Required Disparity PDR 
   Any received vector with five or more zeros or a leading run of four zeros requires a positive entry disparity, regardless whether the vector is valid or not. The primary pseudo control characters K 7 P, K 23 P, K 39 P, and K 71 P with a C126 prefix (C126PREF) require also a positive entry disparity but this rule can be ignored for the general case because this vector position might at the user&#39;s choice be assigned to a data vector with the same bit pattern and no disparity dependence. The remaining vectors belong to one of the following three groups:
         3 or 4 zeros in the leading 4 bit positions combined with 2 or more zeros in the last 4 positions.   2 or more zeros in the leading 4 bit positions combined with 3 or 4 zeros in the last 4 positions.   4 leading zeros       

   The equation for positive required disparity PDR can thus be written as shown in  FIG. 94 . 
   b) Negative Required Disparity NDR Any received vector with five or more ones or a leading run of four ones requires a negative entry disparity, regardless whether the vector is valid or not. The alternate pseudo control characters K 7 A, K 23 A, K 39 A, and K 71 A with a C126 prefix also require a negative entry disparity and can be ignored for the same reason given for PDR above The remaining vectors belong to one of the following three groups:
         3 or 4 ones in the leading 4 bit positions combined with 2 or more ones in the last 4 positions   2 or more ones in the leading 4 bit positions combined with 3 or 4 ones in the last 4 positions.   4 leading ones       

   The equation for negative required disparity NDR can thus be written as shown in  FIG. 94 . 
   4) Equations for Running Disparity on Decoding (RD) 
   The equations for PRD, NRD, RD 1 , and RD 3  expressed by the block disparities are the same as for the 9B10B code except that the 7B8B code has a single disparity dependent balanced vector pair D 15 . The primary version D 15 P has a required negative entry disparity and does not change the running disparity and the alternate version D 15 A requires a positive entry disparity. 
   5) Equations for Block Disparity (BD) 
   For the block disparity, invalid vectors are considered as well Vectors with more than six ones or zeros are lumped together with vectors of a disparity of four. Any vector other than D 15 P or D 15 A with four leading ones or zeros is invalid. If such a vector is received, it is assumed for classification purposes that originally there were only three ones or three zeros, respectively. Similarly, any vector with five trailing ones or zeros is invalid Therefore, for vectors with four trailing ones or zeros, it is assumed that the preceding bit ‘v’ has a complementary value. 
   a) Positive Block Disparity of Four PBD 4   
   All vectors with six ore more bits with a value of one are part of this set. These vectors end with nodes  8   h ,  8   v , or  8   c  in the trellis of  FIG. 1(L) . The vectors belong to one of the following two groups:
         3 or 4 ones in the leading 4 bit positions combined with 3 or 4 ones in the trailing 4 positions   2 or more ones in the leading 4 bit positions combined with 4 ones in the trailing 4 positions.       

   Note that a vector with 4 leading ones followed by anything other than 4 trailing zeros is invalid. 
   b) Positive Block Disparity of Two PBD 2   
   This set includes all vectors with exactly 5 ones ending with node  8   u  in  FIG. 1 . The vectors belong to one of the following three groups:
         3 or 4 ones in the leading 4 bit positions combined with 2 ones and 2 zeros in the trailing 4 positions Four leading ones combined with the specified tail are assumed to have been generated by an error from 3 ones in the leading 4 positions   2 ones and 2 zeros in the leading 4 bit positions combined with 3 ones and 1 zero in the trailing 4 positions.       

   c) Negative Block Disparity of Two NBD 2   
   This includes all vectors with exactly 5 zeros ending with node  8   m  in  FIG. 1 . The vectors belong to one of the following three groups:
         3 or 4 zeros in the leading 4 bit positions combined with 2 ones and 2 zeros in the trailing 4 positions. Four leading zeros combined with the specified tail are assumed to have been generated by an error from 3 zeros in the leading 4 positions   2 ones and 2 zeros in the leading 4 bit positions combined with 1 one and 3 zeros in the trailing 4 positions.       

   d) Negative Block Disparity of Four NBD 4   
   All vectors with six ore more bits with a value of zero are part of this set. These vectors end with nodes  8   s ,  8   q , or  8   t  in the trellis of  FIG. 1 . The vectors belong to one of the following two groups:
         3 or 4 zeros in the leading 4 bit positions combined with 3 or 4 zeros in the trailing 4 positions   2 or more zeros in the leading 4 bit positions combined with 4 zeros in the trailing 4 positions.       

   Note that a vector with 4 leading zeros followed by anything other than 4 trailing ones is invalid. The equations for the block disparities PBD 4 , PBD 2 , NPD 2 , and NBD 4  are shown in  FIG. 95 . For some of the above equations, the number of logic levels can be reduced at the cost of extra gates by merging the vector sets used for the definition of the expressions, e.g. for (PBD 2 +NBD 2 ), for (PBD 2 +D 15 A), and for (NBD 2 +D 15 P). 
   7B8B CIRCUIT IMPLEMENTATION 
   A. 7B8B Encoding 
   1) Block Diagram for Encoding 
   The block diagram for the 7B8B encoding circuit with all inputs and outputs is shown in  FIG. 96 . The output PCMPLFFA complements the arithmetic flip-flop described above under Disparity Control The outputs of flip-flop “A” are the PRD 1  and PRD 3  inputs for the next cycle. The output PCMPLFFP complements the polarity flip-flop, the outputs of which are the inputs PRDF and NRDF for the next clock cycle. 
   2) Gate Level Circuit Diagram for Encoding 
   A gate-level circuit diagram of the encoder is shown in  FIGS. 97A and 97B  which represent a single circuit with net sharing  FIG. 97A  shows the circuit required for bit encoding and  FIG. 97B  shows the disparity control circuit without the two flip-flops which keep track of the running disparity. The upper right side of  FIG. 97B  shows the last two gate levels for bit encoding performing selective bit (NCx 1 , where x=s, t, u v, w, x, y, or z) or full vector NPRDFaNDR, NRDFaNDR) complementation. Selective bit and full vector complementation are orthogonal functions, i.e. no individual bits are changed when a full vector is complemented and vice-versa. This feature of the code allows the merger of both types of signals in a single OR function. 
   As pointed out above, a shorter delay was generally preferred over minor additions to area. As an example, in the logic paths for the signals PCMPLFFP and PCMPLFFA neat the lower right corner of  FIG. 97B , three parallel NAND2 gates replace a single gate to eliminate one OR gating level in each path to reduce the logic depth to 6 levels. Shorter paths for these two signals are desirable because they each control a complementing flip-flop with a MUX input which adds to the setup time. As a result, the total delay conforms to the limit of 7 levels in all other parts of the codec. 
   3) Gate Count, Circuit Delays and Pipelining for Encoding 
   The encoder comprises 203 gates and two flip-flops (not shown) to keep track of the disparity. No logic path exceeds 7 gates. All gates are of the inverting type with shorter delay except some XOR gates which for most power and loading levels have comparable or only slightly more delay than XNOR gates. 
   The circuit presented has been structured for easy forward pipelining for fast operation at the cost of a few extra gates If a first encoding step is limited to six logic levels the 8 trailing EXCLUSIVE OR functions for the coded bits can be moved into a second cycle. The first encoding step can be reduced to five gating levels, if the OR functions immediately before the XOR and the last gate in the PCMPLFFP and PCMPLFFA path are also moved to a second step. A reduction to four gating levels in the first step requires additionally:
         Minor modifications in the leading segments of the t, u, v, w, and PDB4 paths.   Moving the NOR gates driving NCs 1  and NCT 1  at the top right side of  FIG. 97A  into the second cycle.   Moving the trailing gates driving NPRDFaNDR, NRDFaPDR into the second step.   Moving the trailing two gating levels for PCMPLFFA and PCMPLFFP into the second step.       

   A further delay reduction can be accomplished by itself or in combination with any of the above versions by minor circuit modifications and moving the leading EXCLUSIVE OR functions into the preceding clock cycle in the data source path. 
   B. 8B7B Decoding 
   1) Block Diagram for 8B7B Decoding 
   The block diagram for the 8B7B decoding circuit with all inputs and outputs is shown in  FIG. 98 . A gate-level circuit diagram of the decoder and the validity checks according to the equations derived above is shown in  FIGS. 99A and 99B  which represent a single circuit with net sharing. The comments given with respect to the encoding circuits generally are applicable for the decoding circuits as well. 
   2)_Gate Level Circuit Diagram for Decoding 
     FIG. 99A  shows the leading sections of the circuits for individual bit decoding (STUVWXYK)  FIG. 99B  shows the last two gating levels for bit decoding at the top right side These circuits perform individual bit complementation (NCMPL*1, *=s, t, U, v, w, x, or y) or alternate vector complementation (NCMPLA 1 , NCMPLA 2 ) which are all orthogonal as explained above under encoding. The bottom of  FIG. 99B  shows the vector validity check No circuits are shown for disparity monitoring. The shared EXCLUSIVE OR functions of both decoding diagrams are shown on the left side. Again, inverters can be substituted for some of these gates depending on speed requirements. The signal CMPLA 8  is not present explicitly in the circuit diagram but is represented by the 2 signals NCMPL 8   a  and NCMPL 8   b  in the decoder circuit of  FIG. 99B . 
   3) Gate Count, Circuit Delays and Pipelining for Decoding 
   The decoder comprises 145 gates. No logic path exceeds seven gates, all of the inverting type except some XOR gates. The INVAL 8  path is five gating levels, and the PK path is four gating levels. For fast operation, the circuit presented has been structured for easy forward pipelining at the cost of a few extra gates similar to the encoding circuit 
   ADDITIONAL COMMENTS 
   It will appreciated that one or more embodiments of the invention may afford a hardware implementation using combinational logic for the encoding and decoding circuits and the validity check of dc-balanced 9B10B and 7B8B transmission line codes (such codes build on those described in U.S. Pat. No. 6,614,369). The exemplary encoder and decoder circuits for the 9B10B and 7B8B codes require seven logic levels and can operate at a late comparable to the best implementations of the well known and widely used partitioned 8B10B code. The number of required gates is far lower than one would expect. Normalized to the number of source bits encoded, the 7B8B code requires about twice and the 9B10B code about 3 times the number of gates for 8B10B code. 
   Both codes can be used as a stand alone code or as a component of the 16B18B code of U.S. Pat. No. 6,198,413. They are also compatible with the 8B10B code, its 5B6B and 3B4B components, and the 1B2B Manchester codes. For a better fit for these other applications, the codes of U.S. Pat. No. 6,198,413 and U.S. Pat. No. 6,614,369 have been modified, in accordance with certain techniques of the invention, with minimal added complexity to enable a more flexible set of control and comma sequences. In the exemplary embodiment, no encoded data vector consists of a string of all alternating ones and zeros which limits the recovery time from an error for systems using differential encoding with decision feedback equalization (DFE). These changes are also applicable for the 16B18B code, so a single set of 78B and 9B10B macros can be built for all applications. 
   The modifications allow also a much more efficient circuit implementation with less latency The new encoder and decoder circuits for the 9B10B and the 7B8B code can be built with a total of 655 (9B10B) and 348 (7B8B) inverting type primitive logic gates, arranged in logic paths at most seven deep. The circuits have been structured so pipelining can be used with modest overhead to reduce the logic depth to 6, 5, 4, or even 3 per stage. For some applications, especially in the very high speed transceiver domain, clock rate ratios which are a power of two are sometimes preferred and the 7B8B code is naturally compatible with such clock systems. A particular attractive application of the full code or the components is for very high speed busses to save lines, in combination with techniques of U.S. Pat. No. 6,496,540, which shows how to avoid an increase in the line baud rate due to coding and how to eliminate clock gear boxes and extra clock domains or limit them to integer ratios by adding extra lines to compensate for the loss of throughput resulting from the code redundancy. 
   The tables and equations herein have been manually checked. Should any programmed computer checks subsequently reveal any errors, it should be noted that the basic coding principles are sound and detail errors can be corrected by the skilled artisan with the teachings of the present specification at hand. A user may also want to make minor modifications for a better match for a specific application. 
   For both the 7B8B and the 9B10B code, different assignments of the source vectors to the same set of encoded vectors can be chosen with no material effect on performance and implementation complexity. One such alternate code would simply chose a value of one as the default value for the binary appended symbol and the complements of the source vectors chosen for the description above In addition, a mix of identical assignments and alternate complementary assignments is possible It is fully intended to encompass such variations within the inventive scope. 
   The techniques set forth herein can be carried out, for example, via circuits realized on an integrated circuit chip. The chip design can be created, e.g., in a graphical computer programming language, and stored in a computer storage medium (such as a disk, tape, physical hard drive, or virtual hard drive such as in a storage area network) If the designer does not fabricate chips or the photolithographic masks used to fabricate chips, the designer may transmit the resulting design by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., through the Internet) to such entities, directly or indirectly. The stored design can then be converted into an appropriate format such as, for example, Graphic Design System II (GDSII), for the fabrication of photolithographic masks, which typically include multiple copies of the chip design in question that are to be formed on a wafer. The photolithographic masks can be utilized to define areas of the wafer (and/or the layers thereon) to be etched or otherwise processed. 
   Resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (that is, as a single wafer that has multiple unpackaged chips), as a bare die or in a packaged form. In the latter case, the chip can be mounted in a single chip package (such as a plastic carrier, with leads that are affixed to a mother board or other higher level carrier) or in a multi-chip package (such as a ceramic carrier that has either or both surface interconnections or buried interconnections). In any case, the chip may then be integrated with other chips, discrete circuit elements and/or other signal processing devices as part of either (a) an intermediate product, such as a mother board, or (b) an end product. The end product can be any product that employs coded communications. 
   A variety of techniques utilizing dedicated hardware, general purpose processors, firmware, software, or a combination of the foregoing may be employed to implement the present invention, in addition to the preferred implementation in hardware using logic gates. With reference to  FIG. 100 , such alternate implementations might employ, for example, a processor  10002 , a memory  10004 , and an input/output interface formed, for example, by a display  10006  and a keyboard  10008 . The term “processor” as used herein is intended to include any processing device, such as, for example, one that includes a CPU (central processing unit) and/or other forms of processing circuitry. Further, the term “processor” may refer to more than one individual processor. The term “memory” is intended to include memory associated with a processor or CPU, such as, for example, RAM (random access memory), ROM (read only memory), a fixed memory device (e.g., hard drive), a removable memory device (e.g., diskette), a flash memory and the like In addition, the phrase “input/output interface” as used herein, is intended to include, for example, one or more mechanisms for inputting data to the processing unit (e.g., mouse), and one or more mechanisms for providing results associated with the processing unit (e.g., printer). The processor  10002 , memory  10004 , and input/output interface such as display  10006  and keyboard  10008  can be interconnected, for example, via bus  10010  as part of a data processing unit  10012 . Suitable interconnections, for example via bus  10010 , can also be provided to a network interface  10014 , such as a network card, which can be provided to interface with a computer network, and to a media interface  10016 , such as a diskette or CD-ROM drive, which can be provided to interface with medium  10018 . 
   Accordingly, computer software including instructions or code for performing the methodologies of the invention, as described herein, may be stored in one or more of the associated memory devices (e.g., ROM, fixed or removable memory) and, when ready to be utilized, loaded in part or in whole (e.g., into RAM) and executed by a CPU Such software could include, but is not limited to, firmware, resident software, microcode, and the like Note that implementations of one or more embodiments of the present invention involving software may take advantage of the potential for parallelism described above to employ, for example, a vectorized or parallelized solution. 
   Furthermore, the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium (e.g., medium  10018 ) providing program code for use by or in connection with a computer or any instruction execution system For the purposes of this description, a computer usable or computer readable medium can be any apparatus for use by or in connection with the instruction execution system, apparatus, or device. 
   The medium can be an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system (or apparatus or device) or a propagation medium. Examples of a computer-readable medium include a semiconductor or solid-state memory (e g memory  10004 ), magnetic tape, a removable computer diskette (e.g. medium  10018 ), a random access memory (RAM), a read-only memory (ROM), a rigid magnetic disk and an optical disk. Current examples of optical disks include compact disk-read only memory (CD-ROM), compact disk-read/write (CD-R/W) and DVD. 
   A data processing system suitable for storing and/or executing program code will include at least one processor  10002  coupled directly or indirectly to memory elements  10004  through a system bus  10010 . The memory elements can include local memory employed during actual execution of the program code, bulk storage, and cache memories which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution. 
   Input/output or I/O devices (including but not limited to keyboards  10008 , displays 10006, pointing devices, and the like) can be coupled to the system either directly (such as via bus  10010 ) or through intervening I/O controllers (omitted for clarity). 
   Network adapters such as network interface  10014  may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modem and Ethernet cards are just a few of the currently available types of network adapters. 
   In any case, it should be understood that the components illustrated herein may be implemented in various forms of hardware, software, or combinations thereof, e.g., application specific integrated circuit(s) (ASICS), functional circuitry, one or more appropriately programmed general purpose digital computers with associated memory, one or more programmable logic arrays (PLAs), combinational logic as described herein, and the like. Given the teachings of the invention provided herein, one of ordinary skill in the related art will be able to contemplate other implementations of the components of the invention. It should of course be noted that an encoding scheme can be implemented via a look-up table. 
   Although illustrative embodiments of the present invention have been described herein with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various other changes and modifications may be made by one skilled in the art without departing from the scope or spirit of the invention.