Patent Publication Number: US-5831419-A

Title: Circuit and method for regulating a voltage

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 08/485,093, filed Jun. 7, 1995, issued as U.S. Pat. No. 5,644,215. 
    
    
     TECHNICAL FIELD 
     The present invention relates generally to electronic devices and more specifically to a circuit for regulating a voltage. In one aspect of the invention, an integrated device such as a memory circuit may incorporate the regulator circuit to regulate a voltage that the device generates internally. 
     BACKGROUND OF THE INVENTION 
     Many integrated devices incorporate circuitry to generate a regulated voltage from external power source for internal use in the device. For example, an electrically erasable and programmable read-only memory (EEPROM) may incorporate such a circuit or internally generating a programming voltage from an external supply voltage. Or, a memory device such as a dynamic random access memory (DRAM) and other types of integrated circuits may include such circuitry for internally generating from an external supply voltage a substrate or back bias voltage to adjust the thresholds of field-effect transistors (FETs) formed in the substrate. Such internal voltage generation often reduces the number of external supply voltages that the integrated device requires for operation. 
     Typically, such generation and regulation circuitry includes a voltage generator, such a charge pump, and a voltage regulator that maintains the internally generated voltage at a predetermined voltage level or within a predetermined voltage range. For example, the regulator may activate the generator when the voltage is not at the predetermine level or is outside the predetermined range, and may deactivate the generator once it drives the voltage to the predetermined level or within the predetermined range. 
     It is often desirable to design an integrated device such that it can operate over a relatively broad range of supply voltages. For example, it may be desirable to design a DRAM that can operate from a supply voltage ranging from approximately 3 to 6 volts. 
     Some existing voltage regulation circuits can maintain the regulated voltage at a substantially fixed level over the range of external supply voltages within which the integrated device is operational. Such regulation circuits, however, often require a stable reference voltage and associated comparison circuitry. The circuitry that generates the stable reference and the associated comparison circuitry often have a substantial number of components that occupy a relatively large area of the integrated device. 
     Other existing voltage regulation circuits have a minimum number of components, and thus occupy a minimum area of the integrated device. The level at which the regulator maintains the generated voltage, however, is often sensitive to changes in the supply voltage. That is, the level of the regulated voltage shifts as the supply voltage varies. Such shifts in the regulated voltage are often undesirable. 
     SUMMARY OF THE INVENTION 
     According to one aspect of the present invention, a circuit is provided for regulating a voltage by controlling a voltage generator. A voltage divider is coupled between the regulated voltage and a supply voltage, and generates a sense voltage. A clamp circuit is coupled to the divider, and reduces the sensitivity between the supply voltage and the regulated voltage by substantially prohibiting the voltage across itself from exceeding a predetermined value A detector circuit is coupled between the divider and the voltage generator, and provides a control signal that deactivates the generator when the sense voltage reaches a first predetermined threshold, and activates the generator when the sense voltage reaches a second predetermined threshold. 
     According to another aspect of the invention, the voltage divider includes a plurality of load elements that are serially coupled between the regulated and supply voltages, such that junctions or nodes are formed between consecutive pairs of the elements. The sense voltage is tapped from a selected one of the junctions. The clamp circuit includes a first clamp terminal that is coupled to one of the junctions and a second clamp terminal that is coupled to another of the junctions disposed between the selected junction from which the sense voltage is tapped and the regulated voltage, or that is coupled to the regulated voltage. 
     According to yet another aspect of the invention, the clamp circuit is coupled between a pair of nodes chosen from the selected junction, the regulated voltage, and those of the junctions that are disposed between the selected junction and the regulated voltage. 
     According to still another aspect of the invention, the clamp circuit is coupled across the load element that is coupled to the regulated voltage. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block diagram of a memory device in accordance with the present invention. 
     FIG. 2 is a block diagram of a preferred embodiment of the voltage regulator of FIG. 1 
     FIG. 3 is a schematic of the preferred embodiment of the regulator of FIG. 2. 
     FIG. 4 is a cross section of a portion of a substrate of the memory device of FIG. 1. 
     FIG. 5 is a graph showing the improved voltage regulation provided by the regulator of FIG. 3. 
     FIG. 6 is another graph showing the improved regulation provided by the circuit of FIG. 3. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     FIG. 1 is a block diagram of a memory device 10 that is designed and operates in accordance with the present invention, although the present invention could be used with other types of integrated devices. In one aspect of the invention, memory 10 is a DRAM. Memory 10 includes control circuitry 12 that is coupled to address, control, and data buses to receive address, control, and data signals from external circuitry (not shown), such as may be found in a computer system (not shown). Memory 10 also includes an array 14 of storage or memory cells for storing data, and a voltage generation and regulation circuit 16 that provides an internal voltage V INT  from an external power supply voltage V CC . V INT  may be used for a variety of purposes, including as a programming voltage in a memory 10 that contains electrically programmable memory cells, or as a back bias voltage for biasing a substrate in which field-effect transistor are formed to set or adjust the transistors&#39; threshold values. The internal generation of such a voltage often allows memory 10 to run from a single external supply voltage as opposed to multiple external supply voltages. 
     The regulation circuit 16 includes a charge pump 18 that generates V INT  in response to an activate/deactivate signal that it receives at its control terminal 19. A regulator circuit 20 monitors V INT  and generates the activate/deactivate signal in response to the level thereof. 
     In operation, control circuitry 12 receives the address, control, and data signals on the respective buses, and in accordance with these signals, reads and writes data from and to memory-cell array 14. Additionally, control circuitry 12 provides signals to activate and otherwise control the regulation circuit 16. 
     When control circuitry 12 activates the regulation circuit 16, the charge pump 18 begins either increasing or decreasing (depending on whether V INT  is positive or negative) V INT  until it reaches a first predetermined value. When the regulator circuit 20 detects that V INT  has reached this first predetermined value, it deactivates the charge pump 18. When V INT  becomes unequal to the first predetermined value, or becomes equal to a second predetermined value, which together with the first predetermined value defines a predetermined voltage window that is generated with a hysteresis circuit (described below in conjunction with FIG. 3), then the regulator circuit 20 activates the charge pump 18 to again begin the generation-regulation cycle. Known charge pumps or other types of voltage generating circuits are suitable for use in the regulation circuit 16. 
     FIG. 2 is a block diagram of a preferred embodiment of the regulator circuit 20 of FIG. 1. The regulator circuit 20 includes a voltage clamping circuit 22 that is coupled to a voltage divider 24. The voltage divider 24 is connected between the supply voltage V CC  and the voltage V INT  generated by the charge pump 18 (FIG. 1). A threshold detector 26 is coupled between voltage divider 24 and the voltage V INT  from the charge pump 18 (FIG. 1). The clamping circuit 22 acts to reduce the amount V INT  shifts as V CC  varies. 
     More specifically, the voltage divider 24 includes a plurality of load elements 28 that are serially coupled between the power supply voltage V CC  and the internally generated voltage V INT . As shown, the exact number of load elements 28 is not critical, as long as there are at least two. The serial coupling of the load elements 28 forms junctions or nodes 30 between consecutive pairs of adjacent load elements 28. As shown, there is one less junction than there are load elements. Terminals 32 and 34 of clamp 22 are coupled to a selected pair of junctions 30. Also, one of the terminals 32 and 34 may be coupled to a junction 30 and the other of terminals 32 and 34 may be coupled to V INT . One ofjunctions 30 is selected as a sense voltage terminal 36, which is coupled to an input terminal 38 of the detector 26. An output terminal 40 of the detector 26 is coupled to the control terminal 19 of the charge pump 18 (FIG. 1). Such a regulator circuit 20 is particularly suited for applications where V INT  is maintained at a value lower than that of V CC . 
     In operation, as V INT  rises, the sense voltage V S  at terminal 36 also rises in proportion to the ratio of the number and value of the load elements 28 that are located between terminal 36 and V INT  to the number and value of the load elements 28 between V CC  and V INT . As the sense voltage V S  rises above a predetermined value, the detector 26 detects that the sense voltage has surpassed this value, and outputs a signal at the terminal 40 to activate or &#34;turn on&#34; the charge pump 18. The charge pump 18 acts to lower the internal voltage V INT . Once voltage V INT  falls enough so that the sense voltage V S  falls below the predetermined value, the detector 26 generates a signal at terminal 40 to deactivate, ie., &#34;turn off&#34;, the charge pump 18. In this way, the regulator circuit 20 maintains V INT  at a regulated value. As further explained in conjunction with FIG. 3, the detector 26 may have a hysteresis added to it such that it detects the sense voltage V S  passing two predetermined values, one to turn on the charge pump 18 and the second lower predetermined value to turn off the charge pump 18. Such hysteresis may, among other things, prevent oscillation of the detector/charge-pump loop around a single predetermined threshold value. 
     As can be seen from FIG. 2, and ignoring clamp circuit 22 for the moment, as V CC  increases so does sense voltage V S  at terminal 36. Thus, V INT  must be driven to a lower voltage in order for the threshold detector 26 to turn off the charge pump 18. As a result, as V CC  rises, the regulated value of V INT  falls. In order to reduce the interdependence or sensitivity between V CC  and V INT , the clamp circuit 22 is provided as discussed above. In operation, the clamp circuit prevents the voltage between terminals 32 and 34 from exceeding a predetermined clamp value. That is, the clamp circuit 22 limits the voltage between terminals 32 and 34 to the predetermined clamp value. Once this predetermined clamp voltage has been reached, the clamp circuit 22 in effect removes from divider 24 the load elements 28 that are positioned between terminals 32 and 34. This allows V INT  to have a greater proportional effect on the sense voltage V S  at terminal 36. Thus, charge pump 18 need not drive V INT  as low to trip the detector 265 than it would need to if the clamp circuit 22 were omitted. 
     Although, as stated above, the terminals 32 and 34 may be coupled between any pair of junctions 30 or between a junction 30 and voltage V INT , a preferred embodiment of the invention is to have terminals 32 and 34 coupled to any pair ofjunctions 30 that are positioned between terminal 36 and voltage V INT  inclusive, i.e., including the junction coupled to terminal 36 and the terminal of the load element 28 n  that is coupled to V INT . 
     FIG. 3 is a circuit diagram of a preferred embodiment of the voltage regulator circuit 20 of FIG. 2. In this embodiment, the regulator circuit 20 is used to regulate a back bias voltage V BB  to back bias a substrate (FIG. 4) of the circuit incorporating the regulator circuit 20. As is known in the art, such back biasing provides benefits such as setting the thresholds of the transistors formed in the substrate. As shown, the clamp circuit 22 is formed from a pair of serially coupled diode-connected FET transistors 42 and 44. The voltage divider 24 includes three serially connected load elements 28 1 , 28 2 , and 28 3 . Although it is shown as a single resistor, load element 28 1  may be formed from multiple load elements of other types such as diode-connected, long-channel FETs. Load element 28 2  is formed from a diode-connected FET 46, and load element 28 3  is formed from a long-channel FET 48. As shown, clamp circuit 22 is coupled across, i.e., in parallel with, long-channel transistor 48. The gates, drains, and sources of transistors 42, 44, 46, and 48 are labeled G, D, and S, respectively. 
     Threshold detector 26 includes a power-supply terminal 50 and a reference terminal 52. A load device 54, which, although shown as a single resistor, may be made up of one or more other types of load elements such as one or more transistors, is coupled between a terminal 50 and the drain terminal of an FET 56. The gate and source of the transistor 56 are respectively coupled to the input terminal 38 and a reference terminal 52. Three inverters 58a-c are serially coupled between the drain of the transistor 56 and the output terminal 40. Although three inverters 58a-c are shown, any odd number of inverters may be used. The gate of an FET 60 is coupled to output terminal 40. The source and drain of the transistor 60 are respectively coupled to a reference terminal 52 and the source of an FET 62. The gate and drain of the FET 62 are respectively coupled to the input terminal 38 and the drain of the transistor 56. The combination of the inverters 58 and the transistors 60 and 62 form a hysteresis circuit 64. In one aspect of the invention, the gate of transistor 60 is the hysteresis-circuit input terminal, the gate of transistor 62 is the hysteresis-circuit control terminal, and the drain of transistor 62 is the hysteresis-circuit drive terminal. As discussed above for circuits 22 and 24, the gates, drains, and sources of the transistors 56, 60, and 62 are respectively labeled G, D, and S. In another aspect of the invention, the hysteresis circuit 64 is omitted, and the drain of transistor 56 may be coupled directly to the output terminal 40. 
     In a preferred embodiment of the invention, V CC  is approximately between 3 and 6 volts, VBB is regulated to approximately between -1 and -2 volts, and V REF  is approximately ground or zero volts. However, different voltages may be used as long as V REF  is between V CC  and V BB . Furthermore, load elements 28 1 , and 54 have approximate impedance values of 2 megohm and 200 kilaohms, respectively. The width-to-length ratios of transistors 42, 44, 46, 48, 56, 60, and 62 are approximately 6 microns/1 micron, 6/1, 2/2, 216.5, 611.5, 6/1, and 6/1, respectively. 
     In operation, as voltage V BB  rises, the sense voltage V S  at the terminal 36 of the voltage divider 24 also rises. When the sense voltage V S  is approximately the threshold voltage of the transistor 56 above V REF , the transistor 56 turns on, i.e., conducts. As the sense voltage V S  increases further, the transistor 56 becomes saturated and thus drives the voltage at its drain to approximately V REF . The voltage at the drain of the transistor 56 is considered a logic low, which propagates through inverters 58 such that inverter 58c generates a logic high at terminal 40. This logic high voltage activates the charge pump 18, which begins to drive voltage V BB  to a lower level. The logic high at terminal 40 also turns on the transistor 60, and the sense voltage V S  turns on the transistor 62. Thus, the transistors 60 and 62, which are driven at or near saturation, reinforce the voltage V REF  that appears at the drain of the transistor 56. That is, the transistors 60 and 62 provide hysteresis to the detector 26, such that sense voltage V S  must fall to a value lower than that at which it turned on transistor 56 in order for detector 26 to output a logic low to shut off the charge pump 18. Thus, the hysteresis loop in effect forms a threshold window with upper and lower predetermined values. When the sense voltage V S  increases above the upper, i.e., first predetermined value, the detector 26 turns on the charge pump 18, and when the sense voltage V S  falls below the lower, i.e., second predetermined value, the detector 26 turns off the charge pump 18. In this way, the regulator circuit 20 maintains voltage V BB  within a predetermined range that can be adjusted by varying the threshold window of the detector 26. 
     In order to reduce the sensitivity between V CC  and both the sense voltage V S  and V BB , the clamp circuit 22 is coupled across the long channel transistor 48. Because the clamp circuit 22 includes two serially coupled diode-connected transistors 42, 44, the clamping voltage will be approximately the sum of the thresholds of the transistors 42 and 44. In one aspect of the invention, the clamping voltage provided by the clamp circuit 22 is approximately between 1 and 2 volts. As the voltage across the transistor 48 increases above the clamping voltage, the clamp circuit 22 maintains the voltage across transistor 48 at a substantially constant value, and reduces or eliminates the affect of the resistance formed by the transistor 48. Thus, with only the resistance of the transistor 46 effectively between V BB  and the sense voltage, a change in V BB  will result in a larger proportionate change in the sense voltage V S . Therefore, as V CC  increases beyond a certain level, the clamp circuit 22 clamps the voltage across the transistor 48, and allows the regulator circuit 20 to maintain V BB  at a higher value than it could without the clamp circuit 22. That is, for changes in V CC , the clamp circuit 22 reduces or eliminates the corresponding variations in V BB . Therefore, the regulator circuit 20 can maintain V BB  at a more constant level. 
     FIG. 4 is a cross-sectional view of an n-channel FET transistor 65 formed in a p substrate 66. The transistor 65 includes a conductive gate 68, a gate insulator or dielectric 70, a drain 72, and a source 74. By biasing the substrate 66 to a negative voltage with respect to the source 74, the threshold of the transistor 65 can be adjusted. Additionally, other known benefits can also be obtained. For an n substrate containing a p-channel transistor (both not shown), the back bias voltage would be positive. 
     FIG. 5 is a graph of a computer simulation that plots the output of the detector 26 (shown in solid line) with the clamp circuit 22 present and the output of the detector 26 (shown in broken line) with the clamp circuit 22 omitted versus V BB  for V CC  =2.5 volts. As shown, with the clamp circuit 22 present, the regulator circuit 20 turns off the charge pump 18 when V BB  falls to approximately -1.1 volts, and turns on the charge pump when V BB  rises to approximately -0.7 volts. With the clamp circuit 22 not present, the regulator circuit 20 turns off the charge pump 18 when V BB  is approximately -1.2 volts and turns on the charge pump 18 when V BB  is approximately -0.8 volts. 
     Referring to FIG. 6, a similar graph to that shown in FIG. 5 is shown for V CC  =4 volts. As shown, with the clamp circuit 22 installed, the regulator circuit 20 turns off the charge pump 18 when V BB  is approximately -1.3 volts, and turns on the charge pump 18 when V BB  is approximately -1.1 volts. With the clamp circuit 22 removed, the regulator circuit 20 turns off the charge pump 18 when V BB  is approximately -1.7 volts and turns on the charge pump when V BB  is approximately -1.4 volts. 
     Referring to FIGS. 5 and 6, it is evident that the two trip points, i.e., charge pump off, charge pump on, for the regulator circuit 20 incorporating the clamp circuit 22 have changed -0.2 and -0.4 volts, respectively, from VCC=2.5 volts to V CC  =4 volts. For the regulator circuit 20 omitting the clamp circuit 22, the differences in the off and on trip points are -0.5 and -0.6 volts. Thus, the clamp circuit 22 significantly reduces the shifting of V BB  with changes in V CC . 
     It will also be evident that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, the n-channel transistors may be substituted with p-channel transistors or bipolar transistors.