Patent Publication Number: US-7714563-B2

Title: Low noise voltage reference circuit

Description:
TECHNICAL FIELD 
   The present invention relates to bandgap based voltage reference circuits, and in particular to voltage references having very low noise. 
   BACKGROUND 
   Reference voltages are widely used in electronic circuits especially in analog circuits where electrical signals have to be compared to a standard signal, stable with environmental conditions. The most adverse environmental factor for circuits on a chip is temperature. A reference voltage based on the bandgap principle consists of the summation of two voltages having opposite variations with temperature. The first voltage corresponds to a forward biased p-n junction having a Complimentary to Absolute Temperature (CTAT) variation with a drop of about 2.2 mV/° C. The PTAT voltage is generated by amplifying the base-emitter voltage difference of two bipolar transistors operating at different collector current density. A first order temperature insensitive voltage is generated by adding a CTAT voltage to a Proportional to Absolute Temperature (PTAT) voltage such that the two slopes compensate each other. If the PTAT and CTAT are well balanced, all that remains is a second order curvature effect, which may be compensated for as required by inclusion of additional circuitry. 
   While such circuits offer temperature insensitive reference voltages they suffer somewhat in that they are affected by voltage noise on the resultant reference voltage. As it is known to those skilled in the art, the voltage noise on a reference voltage has two components. A first component called low band noise, or 1/f noise or sometimes referred to as flicker noise typically has a contribution in the range from 0.1 Hz to 10 Hz. A second component referred to as high band noise, or white noise typically has a contribution over 10 Hz. 
   A major source of the low band noise in bandgap voltage references based on bipolar transistors, which is not easy to compensate, is generated by the bipolar base current and in order to reduce this noise the base current has to be reduced. One solution to reduce the base current and the associated 1/f noise is to use bipolar transistors with very high gain, which is the ratio of collector current to base current, usually called “beta” factor. From a cost or efficiency point of view it is always preferable to design a circuit using normal processes where “beta” factor is typical of the order of one hundred. Such beta factors are not typically sufficient to compensate for the low band noise. 
   The high band noise is generated by collector current such that the higher the collector current, the lower the high band noise. In order to reduce high band noise collector (and base) current have to be increased. As a result the operation conditions required to minimize low band noise and high band noise are opposite to one another. This makes it difficult to achieve circuitry which can minimize both these noise contributions simultaneously. 
   There are therefore a number of problems associated with generating voltage references with low noise contributions. 
   SUMMARY 
   These and other problems are addressed in accordance with the teaching of the invention by a circuit that provides a bandgap reference output with reduced noise contributions. Using the teaching of the present invention it is possible to minimize one or both of low band and high band noise effects on the reference voltage output. Such teaching is enabled by providing a voltage reference circuit that includes an amplifier coupled at its input to a high impedance input, the high impedance input being provided by a first set of bipolar transistors that collectively contribute to the formation of a bandgap reference and also for a pre-amplifier stage for the amplifier. 
   The present invention provides an improved voltage reference having very low 1/f noise and/or very low high band noise. In order to reduce 1/f voltage noise the two bipolar transistors acting as a preamplifier are shunted by two similar transistors with larger emitter area such that the collector and base currents of the two bipolar transistors from the preamplifier are accordingly reduced. In order to reduce high band noise from the voltage reference a capacitor is connected from the high impedance common collector node of the preamplifier to ground. 
   These and other features of the invention will now be described with reference to exemplary embodiments which are useful in an understanding of the teaching of the invention but are not intended to limit the invention in any way except as may be deemed necessary in the light of the appended claims. 

   
     DESCRIPTION OF DRAWINGS 
       FIG. 1  is an embodiment of the bandgap voltage reference in accordance with the teaching of the present invention. 
       FIG. 2  is a modification of the circuit of  FIG. 1  to include a curvature correction component, again according to the teaching of the invention. 
   

   DETAILED DESCRIPTION 
   As shown in  FIG. 1  a bandgap voltage reference circuit  100  in accordance with the teaching of the invention includes a first amplifier  105  having first and second inputs  110 ,  115  and providing at its output  120  a voltage reference. Coupled to the first and second inputs are a first pair of transistors  125  and a second pair of transistors  130  respectively. 
   The first pair of transistors  125  includes two pnp bipolar transistors; a first bipolar transistor QP 1  and second bipolar transistor QP 2  of the circuit. The bases of each of the first and second transistor are coupled together, the first transistor being additionally coupled to the amplifier input via its collector node and to the amplifier output  120  via a resistor R 5 . The second transistor is provided in a diode configuration with its base and emitter commonly coupled. 
   The second pair of transistors  130  which is coupled to the second input  115  includes two npn transistors; a third transistor QN 1  and a fourth transistor QN 2  of the circuit and a load resistor R 1 . The fourth transistor QN 2  is also provided in a diode configuration, and the load resistor R 1  couples the commonly coupled base-collector of QN 2  to the commonly coupled base-collector of QP 2 . The commonly coupled emitters of QN 1  and QN 2  are coupled via a resistor R 2  to ground. 
   The base of QN 1  is coupled to the commonly coupled bases of QP 1  and QP 2  and to the second input of the amplifier thereby coupling the first and second pairs of transistors and providing a base current for all three transistors, the amplifier, in use, keeping the base and collector of the first transistor at the same potential. 
   The emitter areas of QN 2  and QP 1  are scaled to be “n” times larger than that of QN 1  and QP 2 . As a result of this scaling, two base-emitter voltage differences are developed across R 1  and R 5 , respectively. These two voltages are of the form of proportional to absolute temperature (PTAT) voltages. The currents from two branches (R 5 , QP 1 , QN 1  and QP 2 , R 1 , QN 2 ) are PTAT currents and they are combined to generate a PTAT voltage across R 2 . A first order temperature insensitive voltage is generated when the temperature slope of this voltage is compensated by the temperature slope of base-emitter voltages of QN 1  plus QP 2 . 
   It will be understood that this circuit has an inherent base current compensation as the base current of QP 1  is used as base current of QN 1  when they are balanced, such that the error due to the base current is minimized. Secondly, QP 1  and QN 1  act as a preamplifier such that the operational requirements for the amplifier A are relaxed. Thirdly, as the amplifier is connected after the pre-amplifier stage, its offset voltage and noise have little impact on the reference voltage. It will be noted that the non-inverting input to the amplifier is a high impedance input. The main role of resistor R 5  in  FIG. 1  is to reduce the noise contribution of QN 1  and QP 1  on reference voltage. The circuit of  FIG. 1  can be used to generate a low noise voltage reference especially for high precision digital to analog and analog to digital converters. 
   It will be understood that the components described heretofore as forming the bandgap cell, while providing a low noise output still have low band and high band noise contributions at the voltage reference output. The effects of these can be minimized independently of one another by utilization of additional circuit components according to the teaching of the invention. 
   Addressing the high band noise initially, the teaching of the invention provides for a capacitor C 1  to be coupled to the commonly coupled collectors of QP 1  and QN 1 . As was mentioned above these two transistors effectively form a pre-amplifier to the amplifier A, and the capacitor C 1  is provided at the node between the pre-amplifier and the amplifier input. Such a capacitor provided at the input to the amplifier, may be provided as an external capacitor and serves to filter the high band noise. The cut-off frequency due to C 1  and the output impedance of QP 1  and QN 1  is: 
   
     
       
         
           
             
               
                 
                   f 
                   
                     
                       - 
                       3 
                     
                     ⁢ 
                     db 
                   
                 
                 = 
                 
                   
                     
                       r 
                       01 
                     
                     + 
                     
                       r 
                       02 
                     
                   
                   
                     2 
                     * 
                     π 
                     * 
                     
                       r 
                       01 
                     
                     * 
                     
                       r 
                       02 
                     
                     * 
                     
                       C 
                       1 
                     
                   
                 
               
             
             
               
                 ( 
                 1 
                 ) 
               
             
           
         
       
     
   
   Here r 01  and r 02  are the output resistors of QP 1  and QN 1 . It will be understood by those skilled in the art that that lower limits for wide band noise are typically of the order of 10 Hz. At such levels, and using typical values of resistors for r 01  and r 02  as providing a product of the order of 2 MΩ, it can be estimated that to provide the necessary cut-off frequency that a capacitor of the order of 8 nF would be required. To implement such a capacitor in silicon may require the provision of that capacitor as an off-chip element. However, if one is tolerable to cut-off frequencies above about 800 Hz, then use of capacitors of the order of the order of 10-100 pF may be satisfactory. Such capacitors can be provided on-chip using a silicon substrate. By having a high impedance input, the non-inverting input, to the amplifier it is possible to provide the capacitor at this input. This is advantageous in that a provision of a capacitor at the output could introduce stability issues with regard to the performance of the amplifier. These issues are not encountered with the capacitor at the input, as provided by the teaching of the invention. 
   While the provision of the capacitor serves to address the high band noise, the circuit may also be modified to address the 1/f or low band noise. In order to reduce 1/f voltage noise the two bipolar transistors QP 1 , QN 1  acting as a preamplifier in  FIG. 1  are shunted by two similar transistors with larger emitter area such that the collector and base currents of the two bipolar transistors from the preamplifier are accordingly reduced. 
   The shunt circuitry according to this illustrative embodiment includes two npn transistors QN 7 , QN 6  and one pnp transistor QP 6 . The emitter areas of the bipolar transistors desirably chosen such that QN 1 , unity emitter area; QN 2 , n 1  times unity emitter area; QP 2  unity emitter area; QP 1 , n 2  times unity emitter area; QP 6 , n 3  times unity emitter area; QN 6 , n 4  times unity emitter area; QN 7 , n 5  times unity emitter area. The role of QP 6 , QN 6  and QN 7  is to reduce the collector and base current of QP 1  and QN 1  and by consequence to reduce the low band noise. 
   The current through R 1  which is also the emitter current of QP 2  and QN 2  comes from the base-emitter voltage difference of QN 1  and QN 2 . The current through R 5  is the sum of emitter current of QP 1 , emitter current of QP 6  and collector current of QN 7 . We assume that for all bipolar transistors the base currents can be neglected compared to the corresponding emitter and collector current. 
   The base-emitter voltage, Vbe, of each bipolar transistor is given [2] as: 
   
     
       
         
           
             
               
                 
                   V 
                   be 
                 
                 = 
                 
                   
                     KT 
                     q 
                   
                   ⁢ 
                   
                     ln 
                     ⁡ 
                     
                       ( 
                       
                         Ic 
                         Is 
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 2 
                 ) 
               
             
           
         
       
     
   
   Here:
         K is boltzman constant;   T is actual absolute temperature [K];   q is electronic charge;   Ic is collector current;   Is saturation current, proportional to the emitter area.       

   The base-emitter voltage difference from QN 1  to QN 2 , due to the different collector currents and different emitter areas is reflected across R 1 : 
   
     
       
         
           
             
               
                 
                   
                     I 
                     1 
                   
                   * 
                   
                     R 
                     1 
                   
                 
                 = 
                 
                   
                     KT 
                     q 
                   
                   ⁢ 
                   
                     ln 
                     ⁡ 
                     
                       ( 
                       
                         
                           
                             I 
                             2 
                           
                           
                             I 
                             1 
                           
                         
                         ⁢ 
                         
                           n 
                           1 
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 3 
                 ) 
               
             
           
         
       
     
   
   Similarly the base-emitter voltage difference from QP 1  to QP 2  is reflected across R 5 : 
   
     
       
         
           
             
               
                 
                   
                     I 
                     4 
                   
                   * 
                   
                     R 
                     5 
                   
                 
                 = 
                 
                   
                     KT 
                     q 
                   
                   ⁢ 
                   
                     ln 
                     ⁡ 
                     
                       ( 
                       
                         
                           
                             I 
                             1 
                           
                           
                             I 
                             2 
                           
                         
                         ⁢ 
                         
                           n 
                           2 
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 4 
                 ) 
               
             
           
         
       
     
   
   From (3) and (4) we get: 
   
     
       
         
           
             
               
                 
                   
                     
                       I 
                       1 
                     
                     * 
                     
                       R 
                       1 
                     
                   
                   + 
                   
                     
                       I 
                       4 
                     
                     * 
                     
                       R 
                       5 
                     
                   
                 
                 = 
                 
                   
                     KT 
                     q 
                   
                   ⁢ 
                   
                     ln 
                     ⁡ 
                     
                       ( 
                       
                         
                           n 
                           1 
                         
                         * 
                         
                           n 
                           2 
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 5 
                 ) 
               
             
           
         
       
     
   
   From (5) we can see that the sum of voltage drop across R 1  and R 2  is constant for a specific temperature. If R 1  and R 2  are given then as one current increases the other is decreases. 
   For QP 6  and QN 6  with a combined larger area compared to QP 1  and QN 1  the current I 4 , is diverted away from the emitter and collector of QP 1  and QN 1 . As a result the collector and base current of QP 1 , QN 1  is reduced and the flicker noise due to these transistors is accordingly reduced. 
   The voltage difference from the emitter of QP 1  to the emitter of QN 1  is: 
   
     
       
         
           
             
               
                 
                   
                     
                       KT 
                       q 
                     
                     ⁢ 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             2 
                           
                           
                             
                               n 
                               2 
                             
                             * 
                             
                               I 
                               s 
                             
                           
                         
                         ) 
                       
                     
                   
                   + 
                   
                     
                       KT 
                       q 
                     
                     ⁢ 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             2 
                           
                           
                             I 
                             s 
                           
                         
                         ) 
                       
                     
                   
                 
                 = 
                 
                   
                     
                       KT 
                       q 
                     
                     ⁢ 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             5 
                           
                           
                             
                               n 
                               3 
                             
                             * 
                             
                               I 
                               s 
                             
                           
                         
                         ) 
                       
                     
                   
                   + 
                   
                     
                       KT 
                       q 
                     
                     ⁢ 
                     
                       ln 
                       ⁡ 
                       
                         ( 
                         
                           
                             I 
                             5 
                           
                           
                             
                               n 
                               4 
                             
                             * 
                             
                               I 
                               s 
                             
                           
                         
                         ) 
                       
                     
                   
                 
               
             
             
               
                 ( 
                 6 
                 ) 
               
             
           
         
       
     
   
   From (6) we get: 
   
     
       
         
           
             
               
                 
                   I 
                   5 
                 
                 = 
                 
                   
                     
                       
                         
                           n 
                           3 
                         
                         * 
                         
                           n 
                           4 
                         
                       
                       
                         n 
                         2 
                       
                     
                   
                   * 
                   
                     I 
                     2 
                   
                 
               
             
             
               
                 ( 
                 7 
                 ) 
               
             
           
         
       
     
   
   The collector current of QN 7 , Ic(QN 7 ), is: 
   
     
       
         
           
             
               
                 
                   
                     I 
                     c 
                   
                   ⁡ 
                   
                     ( 
                     
                       QN 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       7 
                     
                     ) 
                   
                 
                 = 
                 
                   
                     I 
                     5 
                   
                   * 
                   
                     
                       n 
                       5 
                     
                     
                       n 
                       4 
                     
                   
                 
               
             
             
               
                 ( 
                 8 
                 ) 
               
             
           
         
       
     
   
   The currents I 3  and I 4  are: 
   
     
       
         
           
             
               
                 
                   I 
                   3 
                 
                 = 
                 
                   
                     
                       I 
                       5 
                     
                     + 
                     
                       
                         I 
                         c 
                       
                       ⁡ 
                       
                         ( 
                         
                           QN 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           7 
                         
                         ) 
                       
                     
                   
                   = 
                   
                     
                       I 
                       2 
                     
                     * 
                     
                       
                         
                           
                             n 
                             3 
                           
                           * 
                           
                             n 
                             4 
                           
                         
                         
                           n 
                           2 
                         
                       
                     
                     ⁢ 
                     
                       ( 
                       
                         1 
                         + 
                         
                           
                             n 
                             5 
                           
                           
                             n 
                             4 
                           
                         
                       
                       ) 
                     
                   
                 
               
             
             
               
                 ( 
                 9 
                 ) 
               
             
           
           
             
               
                 
                   I 
                   4 
                 
                 = 
                 
                   
                     
                       I 
                       3 
                     
                     + 
                     
                       I 
                       2 
                     
                   
                   = 
                   
                     
                       I 
                       2 
                     
                     ⁡ 
                     
                       [ 
                       
                         1 
                         + 
                         
                           
                             
                               
                                 
                                   n 
                                   3 
                                 
                                 * 
                                 
                                   n 
                                   4 
                                 
                               
                               
                                 n 
                                 2 
                               
                             
                           
                           ⁢ 
                           
                             ( 
                             
                               1 
                               + 
                               
                                 
                                   n 
                                   5 
                                 
                                 
                                   n 
                                   4 
                                 
                               
                             
                             ) 
                           
                         
                       
                       ] 
                     
                   
                 
               
             
             
               
                 ( 
                 10 
                 ) 
               
             
           
         
       
     
   
   In the circuit of  FIG. 1  there are four dominant flicker noise sources, QP 1 , QN 1 , QP 2 , and QN 2 . For a given supply current as two currents, I 1  and I 2 , interact according to (5) a preferred tradeoff is to reduce the current I 2 , by properly adjusting the resistor ratio R 1 /R 5  and the area ratios, n 1  to n 5 , until these four noise sources are balanced to generate a minimum flicker noise. 
   By incorporating a filter and a current shunt into the bandgap voltage reference cell it is possible to reduce the low and high band noise. Illustrative, but it will be appreciated exemplary, values of improvement are that using a circuit in accordance with the teaching of the invention that it is possible it is possible generate three times less flicker noise and about five times less wide band noise than circuits without such filters or shunts. 
   While the capacitor C 1  may be used independently of the shunt circuitry and similarly the shunt circuitry may be used independently of a provided capacitor, the use of both provides for a simultaneous reduction in the high and low band noise. Similarly the capacitor C 1  may be provided in one or more components. Furthermore where the shunt circuitry is included, there is a large output impedance at the amplifier&#39;s non-inverting node as the currents through QP 1  and QN 1  are substantially reduced. As a result by combining the shunt circuitry with the capacitor a more efficient reduction in the high band noise is achieved than by using the capacitor in isolation. 
   While the circuit of  FIG. 1  is advantageous in that it provides a first order temperature insensitive bandgap reference circuit with reduced noise contributions it is possible to modify that circuit to include a reduction in the second order curvature effects. An example of a suitable modification is shown in  FIG. 2  where three pnp bipolar transistors, QP 3 , QP 4 , QP 5 ; three npn bipolar transistors, QN 3 , QN 4 , QN 5  and two resistors, R 3  and R 4  are included. The inclusion of these circuit components provides, in certain embodiments, for a compensation of the inherent TlogT voltage curvature that is present in the voltage reference generated from the bandgap cell. In order to do this it is necessary to provide a TlogT signal of opposite sign to the inherent TlogT signal generated. This arrangement provides for the generation of this TlogT signal by providing a complementary to absolute temperature current and using this current in combination with a third resistor, R 3 . The CTAT current, may be externally generated, or as shown in  FIG. 2 , may be provided by providing a transistor QP 4  in series between the output of the amplifier and resistor R 4  to generate and mirror the CTAT current via the bipolar transistor QP 5 . The CTAT current generated is then mirrored via a diode configured transistor QN 5  to another npn transistor QN 4  and the CTAT current reflected on the collector of QN 4  is pulled from the reference node, Vref, via two bipolar transistors: QP 3  having similar base/emitter voltages to QP 2 , and QN 3  with similar base/emitter voltages to QN 1 . The resistor R 3  is provided between the commonly coupled collector of QN 4 /emitter of QN 3  and the emitter of QN 1 . As a result across R 3  a voltage curvature of the form of TlogT is developed. By properly scaling the ratio of R 3  to R 2  the voltage curvature is reduced to zero. 
   This extra circuit has the role of compensating for the residual error known as “curvature” error and to shift the reference voltage to a desired value. The amplifier A is forcing the reference voltage at the node REF by keeping the base-collector voltage of QP 1  and QN 1  at substantially zero level. This combination of the two TlogT voltages of opposite signs provides a voltage reference at the output of the amplifier which is corrected for second order characteristics. The reference to the second order voltage reference is reflective of the fact that the curvature component is a second order effect. 
   Similarly, it will be understood that the present invention provides a bandgap voltage reference circuit that utilizes an amplifier with an inverting and non-inverting input and providing at its output a voltage reference. First and second pairs of transistors are provided, each pair being coupled to a defined input of the amplifier. By providing an NPN and PNP bipolar transistors coupling the bases of these two transistors together it is possible to connect the two pairs. This provides a plurality of advantages including the possibility of these transistors providing amplification functionality equivalent to a first stage of an amplifier. By providing a “second” amplifier it is possible to reduce the complexity of the architecture of the actual amplifier and also to reduce the errors introduced at the inputs of the amplifier. Furthermore the provision of a preamplifier or first stage of an amplifier provides a high impedance input to the amplifier which may be used in combination with a capacitor coupled between that input and ground so as to filter high band noise. By incorporating a shunt circuit which diverts some of the current from the feedback loop it is possible to reduce the collector emitter currents and hence the base currents of the transistors forming the bandgap cell, thereby reducing the 1/f noise that would otherwise inherently be present. The shunt circuitry serves to divert some of the emitter current of the first transistor; by lowering the emitter/collector currents it is possible to drive down the base current of the bipolar transistors, which as mentioned above is a primary source of the 1/f noise. 
   It will be understood that the present invention has been described with specific PNP and NPN configurations of bipolar transistors but that these descriptions are of exemplary embodiments of the invention and it is not intended that the application of the invention be limited to any such illustrated configuration. It will be understood that many modifications and variations in configurations may be considered or achieved in alternative implementations without departing from the spirit and scope of the present invention. Specific components, features and values have been used to describe the circuits in detail, but it is not intended that the invention be limited in any way except as may be deemed necessary in the light of the appended claims. It will be further understood that some of the components of the circuits hereinbefore described have been with reference to their conventional signals and the internal architecture and functional description of for example an amplifier has been omitted. Such functionality will be well known to the person skilled in the art and where additional detail is required may be found in any one of a number of standard text books. 
   Similarly the words comprises/comprising when used in the specification are used to specify the presence of stated features, integers, steps or components but do not preclude the presence or addition of one or more additional features, integers, steps, components or groups thereof.