Patent Publication Number: US-9893178-B2

Title: Semiconductor device having a channel separation trench

Description:
BACKGROUND 
     Power transistors commonly employed in automotive and industrial electronics require a low on-state resistance (R on ), while securing a high voltage blocking capability. For example, a MOS (“metal oxide semiconductor”) power transistor should be capable, depending upon application requirements to block drain to source voltages V ds  of some tens to some hundreds or thousands of volts. MOS power transistors typically conduct very large currents which may be up to some hundreds of Amperes at typical gate-source voltages of about 2 to 20 V. 
     Lateral power devices, in which current flow mainly takes place parallel to a main surface of a semiconductor substrate, are useful for semiconductor devices in which further components, such as switches, bridges and control circuits are integrated. 
     For example, power transistors may be used in DC/DC or AC/DC converters to switch a current through an inductor. In these converters frequencies in a range from several kHz up to several MHz are employed. In order to reduce switching losses, attempts are being made to minimize capacitances in the power transistors. Thereby, switching operations may be accelerated. 
     SUMMARY 
     According to an embodiment, a semiconductor device comprises a transistor in a semiconductor substrate including a main surface. The transistor comprises a source region, a drain region, a channel region, and a gate electrode. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. The channel region is disposed between the source region and the drain region. The channel region has a shape of a ridge extending along the first direction, the ridge including a top side and first and second sidewalls. The gate electrode is disposed at the first sidewall of the channel region, and the gate electrode is absent from the second sidewall of the channel region. 
     According to a further embodiment, a semiconductor device comprises a transistor formed in a semiconductor substrate comprising a main surface. The transistor comprises a source region, a drain region, a channel region, a gate trench adjacent to a first sidewall of the channel region, a gate conductive material being disposed in the gate trench, the gate conductive material being connected to a gate terminal, and a channel separation trench adjacent to a second sidewall of the channel region. The channel separation trench is filled with an insulating separation trench filling or has a conductive filling that is disconnected from the gate terminal. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. 
     According to a further embodiment, a semiconductor device comprises an array of transistors formed in a semiconductor substrate comprising a main surface. The array of transistors comprises a source region, a drain region, a plurality of channel regions, and a plurality of trenches adjacent to each of the channel regions, respectively, so that two trenches are adjacent to one of the channel regions. The plurality of trenches includes gate trenches and channel separation trenches. The semiconductor device further comprises a gate conductive material connected to a gate terminal, the gate conductive material being disposed in the gate trenches. The source region and the drain region are disposed along a first direction, the first direction being parallel to the main surface. At least one of the trenches is a channel separation trench, the channel separation trench being either filled with a dielectric material or having a conductive filling disconnected from the gate terminal. 
     Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and on viewing the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate the main embodiments and together with the description serve to explain the principles. Other embodiments and many of the intended advantages will be readily appreciated, as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numbers designate corresponding similar parts. 
         FIG. 1A  shows a cross-sectional view of a semiconductor device according to an embodiment in a plane parallel to a main surface of a semiconductor substrate; 
         FIG. 1B  shows a first cross-sectional view of the semiconductor device shown in  FIG. 1A ; 
         FIG. 1C  shows a cross-sectional view of the semiconductor device shown in  FIG. 1A  in a direction perpendicular to the direction of the cross-sectional view of  FIG. 1B ; 
         FIG. 2A  shows a cross-sectional view of a semiconductor device according to a further embodiment; 
         FIG. 2B  shows a cross-sectional view of the semiconductor device shown in  FIG. 2A ; 
         FIG. 2C  shows a cross-sectional view of a further semiconductor device; 
         FIG. 3A  shows a cross-sectional view of a semiconductor device according to an embodiment; 
         FIG. 3B  shows a cross-sectional view of a semiconductor device according to a further embodiment; and 
         FIG. 3C  shows a cross-sectional view of a semiconductor device according to still another embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description reference is made to the accompanying drawings, which form a part hereof and in which are illustrated by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology such as “top”, “bottom”, “front”, “back”, “leading”, “trailing” etc. is used with reference to the orientation of the Figures being described. Since components of embodiments of the invention can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope defined by the claims. 
     The description of the embodiments is not limiting. In particular, elements of the embodiments described hereinafter may be combined with elements of different embodiments. 
     The terms “wafer”, “substrate” or “semiconductor substrate” used in the following description may include any semiconductor-based structure that has a semiconductor surface. Wafer and structure are to be understood to include silicon-on-insulator (SOI), silicon-on sapphire (SOS), doped and undoped semiconductors, epitaxial layers of silicon supported by a base semiconductor foundation, and other semiconductor structures. The semiconductor need not be silicon-based. The semiconductor could as well be silicon-germanium, germanium, or gallium arsenide. According to other embodiments, silicon carbide (SiC) or gallium nitride (GaN) may form the semiconductor substrate material. 
     The terms “lateral” and “horizontal” as used in this specification intends to describe an orientation parallel to a first surface of a semiconductor substrate or semiconductor body. This can be for instance the surface of a wafer or a die. 
     The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the first surface of the semiconductor substrate or semiconductor body. 
     The Figures and the description illustrate relative doping concentrations by indicating “−” or “+” next to the doping type “n” or “p”. For example, “n − ” means a doping concentration which is lower than the doping concentration of an “n”-doping region while an “n + ”-doping region has a higher doping concentration than an “n”-doping region. Doping regions of the same relative doping concentration do not necessarily have the same absolute doping concentration. For example, two different “n”-doping regions may have the same or different absolute doping concentrations. In the Figures and the description, for the sake of a better comprehension, often the doped portions are designated as being “p” or “n”-doped. As is clearly to be understood, this designation is by no means intended to be limiting. The doping type can be arbitrary as long as the described functionality is achieved. Further, in all embodiments, the doping types can be reversed. 
     As used herein, the terms “having”, “containing”, “including”, “comprising” and the like are open ended terms that indicate the presence of stated elements or features, but do not preclude additional elements or features. The articles “a”, “an” and “the” are intended to include the plural as well as the singular, unless the context clearly indicates otherwise. 
     As employed in this specification, the terms “coupled” and/or “electrically coupled” are not meant to mean that the elements must be directly coupled together — intervening elements may be provided between the “coupled” or “electrically coupled” elements. The term “electrically connected” intends to describe a low-ohmic electric connection between the elements electrically connected together. 
     The present specification refers to a “first” and a “second” conductivity type of dopants, semiconductor portions are doped with. The first conductivity type may be p type and the second conductivity type slay be n type or vice versa. As is generally known, depending on the doping type or the polarity of the source and drain regions, MOSFETs may be n-channel or p-channel MOSFETs. For example, in an n-channel MOSFET, the source and the drain region are doped with n-type dopants, and the current direction is from the drain region to the source region. In a p-channel MOSFET, the source and the drain region are doped with p-type dopants, and the current direction is from the source region to the drain region. As is to be clearly understood, within the context of the present specification, the doping types may be reversed. If a specific current path is described using directional language, this description is to be merely understood to indicate the path and not the polarity of the current flow, i.e. whether the transistor is a p-channel or an n-channel transistor. The Figures may include polarity-sensitive components, e.g. diodes. As is to be clearly understood, the specific arrangement of these polarity-sensitive components is given as an example and may be inverted in order to achieve the described functionality, depending whether the first conductivity type means n-type or p-type. 
     Embodiments are described while specifically referring to so-called normally-off transistors, i.e. transistors which are in an off-state when no gate voltage or a gate voltage of 0V is applied. As is to be clearly understood, the present teaching can be equally applied to normally-on transistors, i.e. transistors which are in a conducting state when no gate voltage or a gate voltage of 0V is applied. 
       FIG. 1A  shows a cross-sectional view of a semiconductor device  1  or an integrated circuit which is taken in a plane parallel to a main surface of a semiconductor substrate. The semiconductor device  1  includes a transistor  200 . The transistor  200  shown in  FIG. 1A  comprises a source region  201 , a drain region  205 , a channel region  220 , and a drift zone  260 . The source region  201 , the drain region  205  and the drift zone  260  may be doped with dopants of a first conductivity type, for example n-type dopants. The doping concentration of the source and the drain regions  201 ,  205  may be higher than the doping concentration of the drift zone  260 . The channel region  220  is arranged between the source region  201  and the drift zone  260 . The channel region  220  is doped with dopants of a second conductivity type, for example with p-type dopants. The drift zone  260  may be arranged between the channel region  220  and the drain region  205 . The source region  201 , the channel region  220 , the drift, zone  260  and the drain region  205  are disposed along a first direction parallel to a main surface of the semiconductor substrate. The source region  201  is connected to the source electrode  202 . The drain region  205  is connected to the drain electrode  206 . The semiconductor device  1  further comprises a gate electrode  210 . The gate electrode  210  is insulated from the channel region  220  by means of an insulating gate dielectric material  211  such as silicon oxide. According to an embodiment, the transistor may further comprise a field plate  250  which is arranged adjacent to the drift zone  260 . The field plate  250  is insulated from the drift zone  260  by means of an insulating field dielectric layer  251  such as silicon oxide. The transistor  200  is a lateral transistor. Accordingly, a current flow from the source region  201  to the drain region  205  is mainly accomplished in the first direction parallel to the main surface of the semiconductor substrate. 
     When a suitable voltage is applied to the gate electrode  210 , an inversion layer is formed at the boundary between the channel region  220  and the insulating gate dielectric material  211 . Accordingly, the transistor is in a conducting state from the source region  201  to the drain region  205  via the drift zone  260 . The conductivity of the channel that is formed in the channel region  220  is controlled by the gate electrode. By controlling the conductivity of the channel formed in the channel region, the current flow from the source region  201  via the channel formed in the channel region  220  and the drift zone  260  to the drain region  205  may be controlled. 
     When the transistor is switched off, no conductive channel is formed at the boundary between the channel region  220  and the insulating gate dielectric material  211  so that a sub-threshold current flows. 
     According to an embodiment, the transistor may be implemented as a normally-off transistor. According to a further embodiment, the transistor may be implemented as a normally-on transistor. In this case, the channel region  220  may be doped with dopants of the first conductivity type, for example, with n-type dopants. 
     An appropriate voltage may be applied to the field plate in an off-state. For example, the field plate  250  may be electrically connected to a source terminal, which is also electrically connected to a source electrode  202 . In an off-state, the field plate  250  depletes charge carriers from the drift zone  260  so that the breakdown voltage characteristics of the transistor  200  are improved. In a transistor  200  comprising the field plate  250  the doping concentration of the drift zone  260  may be increased without deteriorating the breakdown voltage characteristics in comparison to a device without a field plate. Due to the higher doping concentration of the drift zone, the on-resistance RDS on  is further decreased resulting in improved device characteristics. 
     The semiconductor device  1  further comprises channel separation trenches  270 . Due to the presence of the channel separation trenches  270 , the width of the channel region  220  is decreased. Thereby, it is possible to implement a fully depleted transistor. In transistors having a relatively high breakdown voltage, a reduction of the width of the active channel does not degrade the on-state resistance (Ron×A), since the on-state resistance is mainly determined by the properties of the drift region. The separation trenches may be filled with insulating material or may include a conductive filling that is disconnected from a gate potential. Accordingly, the number of active trenches including a gate electrode is reduced in the semiconductor device  1 . 
       FIG. 1B  illustrates a cross-sectional view of the semiconductor device  1  between I and I′ along the first direction, as is also indicated in  FIG. 1A . The cross-sectional view of  FIG. 1B  is taken so as to intersect the channel region  220  and the drift zone  260 . As is indicated by dotted lines, gate trenches  212  are disposed adjacent to the channel region  220  in a plane before and behind the depicted plane of the drawing. Further, field plate trenches  252  may be disposed adjacent to the drift zone  260  in a plane before and behind the depicted plane of the drawing. The gate trench  212  and the field plate trench  252  extend from the main surface  110  in a depth direction of the substrate  100 . As a consequence, the gate electrode is adjacent to at least two sides of the channel region  220 . Further, the channel region  220  has the shape of a first ridge. Due to the presence of the field plate trenches  252 , according to an embodiment, the drift zone  260  may have the shape of a second ridge. 
     The source region  201  extends from the main surface  110  into a depth direction of the substrate  100 , i.e. perpendicularly with respect to the main surface  110 . The drain region  205  likewise extends from the main surface  110  in a depth direction of the substrate  100 .  FIG. 113  further shows a body connect implantation region  225  that disposed beneath the channel region  220  and beneath a part of the drift zone  260 . The body connect implantation portion  225  electrically connects the channel region to the source electrode  202  and further suppresses or deteriorates a parasitic bipolar transistor. Moreover, the body connect implantation portion  225  may extend beneath the drift zone  260  so that in an off-state of the transistor, the drift zone  260  may be depleted more easily. The body connect implantation portion  225  may be doped with dopants of the second conductivity type at a higher concentration than the channel region. 
       FIG. 1C  illustrates a cross-sectional view of the semiconductor device which is taken between II and II′ as is also illustrated in  FIG. 1A . The direction between II and II′ is perpendicular to the first direction. As is shown in  FIG. 1C , the channel region  220  has the shape of a ridge, the ridge having a width d 1 . For example, the ridge may have a top side, a first sidewall  220   b  and a second sidewall  220   a . The sidewalls  220   b ,  220   a  may extend perpendicularly or at an angle of more than 75° with respect to the main surface  110 . 
     According to the embodiment of  FIG. 1C , a semiconductor device comprises a transistor  200 . The transistor  200  comprises a source region  201 , a drain region  205 , a channel region  220  and a gate electrode  210 . The channel region  220  is disposed along a first direction between the source region  201  and the drain region  205 , the first direction being parallel to the main surface. The channel region  220  has a shape of a ridge extending along the first direction, the ridge including a top side  220   c , a first sidewall  220   b  and a second sidewall  220   a . The gate electrode  210  is adjacent to the first sidewall  220   b  of the channel region, and the gate electrode is absent from the second sidewall  220   a  of the channel region  220 . 
     When the semiconductor device  1  is operated in an on-state, a conductive inversion layer is formed along the first sidewall  220   b . Due to the absence of the gate electrode at the second sidewall  220   a  of the channel region  220 , no conductive inversion layer is formed at the second sidewall  220   a.    
     The semiconductor device  1  may comprise a channel separation element adjacent to the second sidewall  220   b  of the channel region  220 . 
     For example, the channel separation element may comprise a channel separation trench  270  filled with a separation trench filling. 
     According to a further embodiment, the channel separation trench  270  may include a conductive filling  274  and a separation dielectric  275  disposed between the conductive filling  274  and the channel region  220 . The thickness of the separation dielectric  275  may be larger than the thickness of the gate dielectric  211  between the gate electrode  210  and the channel region  220 . 
     According to an embodiment, the source region  201  and the conductive filling  274  of the channel separation trench  270  may be connected to a source terminal  280 . 
     The width of the several gate trenches  212  and of the several channel separation trenches  270  may be different from each other. 
     According to an embodiment, the width d 1  of the channel region  220  fulfills the following relationship: d 1 ≦l d  wherein l d  denotes a length of a depletion one which is formed at the interface between the gate dielectric layer  211  and the channel region  220 . For example, the width of the depletion zone may be determined as: 
               l   d     =         4   ⁢           ⁢     ɛ   s     ⁢   kT   ⁢           ⁢     ln   ⁡     (       N   A     /     n   i       )             q   2     ⁢     N   A                 
wherein ε s  denotes the permittivity of the semiconductor material (11.9×ε 0  for silicon, ε 0 =8.85×10 −14  F/cm) k denotes the Boltzmann constant (1.38066×10 −23  J/k), T denotes the temperature, ln the denotes the natural logarithm, N A  denotes the impurity concentration of the semiconductor body, n i  denotes the intrinsic carrier concentration (1.45×10 10  cm −3  for silicon at 27° C.), and q denotes the elementary charge (1.6×10 −19  C).
 
     Generally, the length of the depletion zone varies depending from the gate voltage. It is assumed that in a transistor the length of the depletion zone at a gate voltage corresponding to the threshold voltage corresponds to the maximum width of the depletion zone. For example, the width of the first ridges may be approximately 10 to 200 nm, for example, 20 to 60 nm along the main surface  110  of the semiconductor substrate  100 . 
     Moreover, the ratio of length to width may fulfill the following relationship: s 1 /d 1 &gt;2.0, wherein s 1  denotes the length of the first ridge overlapping with the gate electrode  210 , or, differently stated, the length of the channel region, measured along the first direction, as is also illustrated in  FIG. 1 . According to further embodiments, s 1 /d 1 &gt;2.5. 
     According to the embodiment in which the width d 1 ≦l d , the transistor  200  is a so-called “fully-depleted” transistor in which the channel region  220  is fully depleted when the gate electrode  210  is set to an on-voltage. In such a transistor, an optimal sub-threshold voltage may be achieved and short channel effects may be efficiently suppressed, resulting in improved device characteristics. 
     Due to the feature that the gate electrode is absent from the second sidewall of the channel region, the gate capacitance may be decreased resulting in reduced switching losses. According to an embodiment, the channel separation trench includes a conductive filling and a separation dielectric  275  disposed between the conductive filling  274  and the channel region  220 . The thickness of the separation dielectric  275  may be larger than the thickness of the gate dielectric  211  between the gate electrode  210  and the channel region  220 . As has been found out, due to this feature, a voltage applied to the gate electrode becomes almost completely effective at the gate electrode. To be more specific, due to the increased thickness of the separation dielectric  275  in comparison to the gate dielectric  211 , the conductive filling  274  in the channel separation trench  270  is prevented from acting as a voltage divider taking up part of the applied gate voltage. As a result, the steepness of the sub-threshold slope of the current-voltage characteristics of the transistor may be further increased. 
     According to a further embodiment, the channel separation trench  270  may be filled with an insulating material. Due to reasons of symmetry, such a separation trench acts like an SOI (silicon-on-insulator) substrate having an insulator of an infinite thickness. 
     According to an embodiment, the drift zone  260  may comprise a flat surface which is not patterned to form ridges. According to a further embodiment, the field plate  250  may be arranged in trenches  252  so that the drift zone  260  comprises ridges. In a transistor including a field plate  250 , it may be desirable to use a drift zone  260  having a width d 2  which is larger than the width d 1  of the channel region to limit e.g. the output capacitance C oss . Hence, the field plate trenches  252  may be disposed at a larger distance so that the portions of the drift zone  260  which are disposed between adjacent field plate trenches  252 , have a larger width. According to another embodiment, d 2  may be chosen to be smaller than d 1 . Typically, the thickness of the field dielectric layer between the field plate and the drift zone is thicker than the thickness of the gate dielectric layer to increase the drain-source breakdown voltage. This may result in a greater pitch of the field plate trenches in comparison with the gate trenches and the separation trenches. 
     In order to improve the characteristics of the semiconductor device in the channel region and to further improve the device characteristics in the drift zone, patterning the gate electrode and the field plate may be accomplished using an appropriate etching mask so as to provide a different width of the first and second ridges. 
     As will be further explained herein below, this may be accomplished by forming a set of gate trenches  212  having a smaller pitch and by forming a set of field plate trenches  752  having a larger pitch. According to an embodiment, the gate trenches  212  and the field plate trenches  252  may be separate from each other. According to a further embodiment, the gate trenches  212  and the field plate trenches  252  may be merged so as to form one single trench having different width. 
     The semiconductor devices illustrated in  FIGS. 1A to 1C  implement lateral power transistors. They may be employed in DC/DC or AC/DC converters since they may be integrated in an easy manner. Further, they may achieve high current densities so that they may be employed for small power and voltages between 10V and several hundred Volts. 
       FIG. 2A  shows a cross-sectional view of a semiconductor device or an integrated circuit according to an embodiment in a plane that is parallel to the main surface of the semiconductor substrate. The semiconductor device includes channel separation trenches  270 . In the embodiment of  FIG. 2A , the channel separation trenches  270  include a conductive filling  274 . A separation dielectric layer  275  is disposed between the conductive filling  274  and the adjacent channel region  220 . The conductive filling  274  is connected to a terminal  290  that is connected to a potential different from the gate potential. For example, the conductive filling may be connected to the source terminal or may be grounded. Thereby, the gate-drain capacitance may be further decreased. The separation dielectric layer  275  may have a greater thickness than the gate dielectric layer  211 . According to a further embodiment, the thickness of the separation dielectric layer  275  may be equal to the thickness of the gate dielectric layer  211 . According to an embodiment, a thickness of the gate dielectric layer  211  at a portion  211   d  adjacent to the drain region  205  may be larger than a thickness of the gate dielectric layer  211  at a portion adjacent to the channel region  220 . The further components of the embodiment shown in  FIG. 2A  are similar to those of  FIG. 1A . 
       FIG. 2B  shows a cross-sectional view of the semiconductor device shown in  FIG. 2A  between II and II′, as is also indicated in  FIG. 2A . As is shown, the gate electrode  210  is disposed adjacent to a first sidewall  220   b  of the channel region  220 . Further, channel separation trenches  270  are adjacent to a second sidewall  220   a  of each of the channel regions  220 . A conductive filling  274  is disposed in the channel separation trenches  270 . 
     The gate electrodes  210  are connected to a gate terminal  285 . Further, the conductive filling  274  of the channel separation trenches  270  is connected to a terminal  290  different from the gate terminal  285 . As a consequence, the gate drain capacitances may be decreased. Moreover, the thickness of the separation dielectric layer  275  may be larger than the thickness of the gate dielectric layer  211 . Thereby, the steepness of the sub-threshold slope of the current-voltage characteristics of the transistor may be further increased. 
     The concept explained above may be modified in various ways. For example, the drift zone  260  may be implemented in different manners. Further, the semiconductor device may be implemented without field plates including a conductive filling. For example, the semiconductor device may comprise, for example, a stack of alternating p- and n-doped compensation areas extending in the first direction, as is conventional. Thereby, a compensation device or superjunction device may be implemented. According to still a further embodiment, the drift region may be dispensed with. 
       FIG. 2C  shows a cross-sectional view of the embodiment, according to which the drain region  205  is directly adjacent to the channel region  220  without a drift zone  260  disposed between the channel region and the drain region  205 . According to the implementation shown in  FIG. 2C , the thickness of the gate dielectric layer  211  in the portion  211   d  adjacent to the drain region  205  may be increased so as to further reduce the gate-drain capacitance. 
       FIG. 3A  shows a cross-sectional view of a further embodiment of a semiconductor device or an integrated circuit. The cross-sectional view of  FIG. 3A  is taken parallel to the main surface of the substrate. According to the embodiment of  FIG. 3A , the channel separation trenches  270  including a conductive filling  274  are connected to the field plate trenches so as to form extended field plate trenches  273 . Hence, the semiconductor device according to the embodiment of  FIG. 3A  includes gate trenches  212  including the gate electrode  210  that is insulated from the adjacent channel region by means of the gate dielectric  211 . The semiconductor device further comprises extended field plate trenches  273  that extend to the channel region  220 . The extended field plate trenches are filled with a conductive filling  274  that may be connected to a source terminal  280 . The conductive filling  274  of the extended field plate trenches  273  is insulated from the channel region by means of the field dielectric layer  251 . The thickness of the field dielectric layer  251  may be larger than the thickness of the gate dielectric layer  211 . The channel region  220  includes a first sidewall  220   b  and a second sidewall  220   a , the gate electrode  210  being adjacent to the first sidewall. Further, the conductive filling  274  is adjacent to the second sidewall  220   a  of the ridges. Since the conductive filling  274  is not connected to the gate terminal, a depletion region is only formed at the interface of the first sidewall  220   b  with the gate dielectric  211 , when a suitable gate voltage is applied to the gate terminal  285 . In the semiconductor device shown in  FIG. 3A , the effective gate area may be decreased, resulting in a reduced gate capacitance. 
       FIG. 3B  shows a cross-sectional view of a semiconductor device or integrated circuit according to a further embodiment. In a similar manner as is shown in  FIG. 3A , the gate trenches  212  and the channel separation trenches  270  are disposed in an alternating manner so that one gate trench  212  is adjacent to a first sidewall  220   b  of each of the channel regions  220  and one channel separation trench  270   a ,  270   b  is adjacent to a second sidewall  220   a  of each of the channel regions. As is further shown in  FIG. 3B , the channel separation trenches  270  include first channel separation trenches  270   a  that are filled with an insulating material and second channel separation trenches  270   b  that are filled with a conductive filling  273  and a field dielectric layer  251  between the conductive filling  273  and the channel region  220 . As is further illustrated in  FIG. 3B , the second channel separation trenches  270   b  are implemented as extended field plate trenches  273  that extend to the drift zone  260  to form the field plate trenches. The thickness of the field dielectric layer  251  may be larger than the thickness of the gate dielectric layer  211 . 
       FIG. 3C  shows a cross-sectional view of a semiconductor device or integrated circuit according to a further embodiment. As is illustrated, the separation dielectric layer  275 , that is adjacent to the channel region  220 , may have a thickness that is approximately equal to the thickness of the gate dielectric layer  211 . Moreover, the second channel separation trenches are implemented as extended field plate trenches  273  in which the conductive filling  274  of the separation trenches extends to the drift zone  260  to form a field plate. The separation dielectric layer  275  has a larger thickness in a region adjacent to the drift zone  260  than in a region adjacent to the channel region  220 . As has been discussed hereinabove, a semiconductor device  1  comprises an array of transistors  200  formed in a semiconductor substrate  100  comprising a main surface  110 . The array of transistors  200  comprises a source region  201 , a drain region  205 , a plurality of channel regions  220 , and a plurality of trenches  212 ,  270  adjacent to each of the channel regions  220 , so that two trenches are adjacent to one of the channel regions. The plurality of trenches includes gate trenches  212  and channel separation trenches  270 . The semiconductor device comprises a gate conductive material  210  connected to a gate terminal  285 , and the gate conductive material  210  is disposed in the gate trenches  212 . The channel region  220  is disposed along a first direction between the source region  201  and the drain region  205 , the first direction being parallel to the main surface  110 . At least one of the trenches is a channel separation trench  270 , the channel separation trench  270  being either filled with a dielectric material  272  or being lined with a dielectric material and filled with a conductive filling  274  that is disconnected from the gate terminal  285 . 
     According to an embodiment, the gate trenches  212  and the channel separation trenches  270  are disposed in an alternating manner so that one gate trench  212  and one channel separation trench  270  are adjacent to different sidewalls  220   b,    220   a  of each of the channel regions  220 . 
     According to an embodiment, the channel separation trenches  270  include first channel separation trenches  270   a  filled with an insulating material and second channel separation trenches  270   b  filled with a conductive filling  274  and a separation dielectric layer  275  between the conductive filling  274  and the channel region  220 . 
     Hence, the number of active gate trenches is reduced in the semiconductor device  1 . The conductive inversion layer is formed at only one sidewall of the channel region. In devices having a higher breakdown voltage, a reduction of the density of active channels should have a small influence on Ron×A, which is mainly determined by the properties of the drift zone  260 . Accordingly, the gate capacitance may be decreased without deteriorating the on-state resistance (Ron×A). Further, according to an embodiment, the gate capacitance may be decreased without deteriorating the sub-threshold slope of the current-voltage characteristics, 
     In other embodiments, the transistor may be implemented as a normally-on device. In this case, the channel region may be of the same conductivity type as the source and drain regions. 
     The transistor described refers to a MOSFET (“metal oxide semiconductor field effect transistor”), in which a gate dielectric material such as silicon oxide is disposed between the gate electrode and the channel region. According to a further embodiment, the transistor may be a JFET (“junction field effect transistor”) in which the gate electrode is directly adjacent to the channel region, without a gate dielectric material being disposed between the gate electrode and the channel region. According to this embodiment, the channel region may be doped with n-type dopants. The gate electrode may be implemented by p-doped semiconductor material, for example, p-doped polysilicon. Further components of the semiconductor device may be implemented in a manner as has been described above. 
     According to a further embodiment, the semiconductor device may further comprise contacts to a second main surface which is opposite to the first main surface  110  of the semiconductor substrate  100 . According to an embodiment, the source electrode  202  that is electrically coupled to the source region  201 , may extend to the first main surface  110  and the drain electrode  206  that is electrically coupled to the drain region  205 , may extend to the second main surface being opposite to the first main surface  110 . 
     While embodiments of the invention have been described above, it is obvious that further embodiments may be implemented. For example, further embodiments may comprise any sub-combination of features recited in the claims or any sub-combination of elements described in the examples given above. Accordingly, this spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.