Patent Publication Number: US-6667659-B2

Title: High efficiency amplifier

Description:
FIELD OF THE INVENTION 
     This invention relates generally to the field of high efficiency amplifiers. Certain embodiments of this invention are more particularly related to radio frequency distributed power amplifiers with enhanced efficiency. 
     BACKGROUND OF THE INVENTION 
     In a conventional linear amplifier, DC to AC conversion efficiency is a function of output signal level relative to the DC supply voltage. Conversion efficiency decreases directly as a function of the output level, decreasing as the output signal level decreases. For battery powered devices such as radio frequency transmitters as used in cellular telephones and two-way radios, this limitation in efficiency imposes significant limitations on the battery life that can be expected for the device. 
     In some instances, the efficiency of a linear amplifier can be enhanced by modulating the supply voltage to the linear amplifier. In this technique, the amplifier&#39;s supply voltage is dynamically modified so that it approximately follows the envelope of the signal driving the linear amplifier. This keeps the supply voltage at or near the output voltage to enhance the amplifier&#39;s efficiency. Unfortunately, this technique cannot be universally applied to all linear amplifiers and generally requires that a DC-to-DC converter circuit be used to provide the supply voltage to the amplifier circuitry. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features of the invention believed to be novel are set forth with particularity in the appended claims. The invention itself however, both as to organization and method of operation, together with objects and advantages thereof, may be best understood by reference to the following detailed description of the invention, which describes certain exemplary embodiments of the invention, taken in conjunction with the accompanying drawings in which: 
     FIG. 1 is a diagram of an exemplary two-stage distributed amplifier structure consistent with certain embodiments of the present invention. 
     FIG. 2 is a graph depicting the conversion efficiency of the amplifier circuit  100  of FIG.  1 . 
     FIG. 3 is an exemplary four-stage high efficiency distributed amplifier structure consistent with certain embodiments of the present invention. 
     FIG. 4 is a diagram used to illustrate a virtual impedance analysis. 
     FIG. 5 is a graph depicting the conversion efficiency of the amplifier circuit  200  of FIG.  3 . 
     FIG. 6 is a graph depicting the control voltages used to drive the amplifier circuit  200  of FIG.  3 . 
     FIG. 7 is a schematic of a generalized distributed amplifier consistent with certain embodiments of the present invention. 
     FIG. 8 illustrates an embodiment of a drive circuit  315  consistent with certain embodiment of the present invention. 
     FIG. 9 illustrates another embodiment of a drive circuit  315  consistent with certain embodiment of the present invention. 
     FIG. 10 illustrates another embodiment of a drive circuit  315  consistent with certain embodiment of the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals are used to describe the same, similar or corresponding parts in the several views of the drawings. 
     An ideal conventional linear amplifier is designed to provide power, voltage, or current gain by reproducing the input envelope at the output with a constant multiplication factor as follows: 
     
       
           y ( t )= Ax ( t )  Equation 1 
       
     
     Where x(t) is the input signal and y(t) is the output signal, which is a replication of the input signal in amplitude and phase. In addition, the output signal power is a function of the output voltage and load impedance by the following relation:                P   O     =       V   O   2       2      R               Equation                 2                         
     Where P O  is the output power in watts, V O  is the output voltage, and R is the output load (assumed to be real only). By use of the present invention, the output voltage peak (V O ) can be maintained at or close to the limit of the battery voltage over a wide range of output power levels. This maintains high conversion efficiency over the power levels where the output voltage is kept close to the battery voltage. 
     Reviewing the relation shown in Equation 2, there is only one variable other than the output voltage V O  that can vary over the output power P O  range if V O  remains constant. That variable is R—the load impedance at the amplifier output terminal. Thus, if the output load can be varied as a function of the input signal amplitude, high conversion efficiency can be maintained. The present invention uses this concept and provides for modulation of the load to enhance the efficiency of the amplifier. This is very different from a conventional linear amplifier where the load remains constant over the entire range of output operating signal levels. To achieve the desired efficiency benefit without affecting the amplitude and phase information of the signal being processed, the load modulation can either be real only (no imaginary parts), or alternatively, any phase and/or amplitude load modulation can be compensated for to preserve the intended replication of the input signal at the output with increased power, voltage, and/or current. With this as a preface to some of the basic concepts of the present invention, consider an exemplary amplifier embodying concepts of the present invention. 
     Turning now to FIG. 1, a simple two-stage amplifier circuit arrangement  100  using a tapered distributed transmission line structure consistent with an embodiment of the present invention is illustrated. This circuit arrangement  100  uses a pair of transistors  104  and  108  separated by a quarter wavelength transmission line with characteristic impedance equal to R L . The transmission line may be either a coaxial, planar, stripline, or other form of actual transmission line, or may be a lumped element approximation of a transmission line, without limitation and is designed to resonate with any parasitic reactive elements and component reactive elements to operate as a wide band transmission line impedance transformer. 
     In this example, the amplifier circuit  100  is designed with a structure similar to that of a two-stage distributed amplifier. However, known conventional distributed amplifiers are designed to have input signals V in1  and V in2  as equal signals (in magnitude) driving the two transistors  104  and  108  using a passive input network. Maximum efficiency is achieved when the two input signals drive the transistors  104  and  108  to produce maximum output to load resistor  116 . When this occurs, I 1 (t) equals I 2 (t). However, as the input signal is reduced in both stages of a conventional distributed amplifier, the AC output signal decreases and the conversion efficiency drops. 
     In accordance with certain embodiments of the present invention, the input signals driving each stage of amplification are generated as a function of the input signal to be amplified in a manner such that they are not always equal. This permits enhanced efficiency by modulation of the load impedance seen by each stage of the amplifier. In the present example of FIG. 1, when the input signals are at their maximum values, the output signals are also at their maximum values, each device sees identical source and load impedances and the efficiency of amplifier  100  is maximized. In order to continue to achieve high efficiency, however, the amplifier  100  is provided distinctly different input signals whenever the instantaneous value of the output envelope is less than maximum in order to control the impedances seen by the transistors, as will be described. 
     In accordance with one embodiment using enhancement lateral double-diffused metal oxide semiconductor (LDMOS) power transistor device, as the value of V in2 (t) is reduced from its maximum value to V th  (linearly), the current I 2 (t) also reduces from its maximum value to zero by the relation: 
     
       
           I   2 ( t )= C   o   Wv   sat ( V   gs   −V   th )  Equation 3 
       
     
     Where V th =threshold voltage or turn-on voltage 
     
       
           V   th   &lt;V   gs   =V   in2 ( t )&lt; V   in2(max)   Equation 4 
       
     
     and where: 
     v sat =8×10 6  cm/s, the limiting velocity for electrons in silicon 
     W=device channel width 
     C o =gate oxide capacitance˜e ox e o /t ox    
     e ox =dielectric constant of silicon=3.9 
     e o =permitivity of free space 8.86×10 −14  F/m 
     t ox =gate oxide thickness. 
     The value of V in1 (t) is simultaneously reduced (linearly) from its maximum value to V IN1(max) −V th )/2, so that the first stage and second stage of amplification provided by transistor  104  operates at full efficiency as the contribution of the second stage to driving the output load is tapered off. As the current I 2 (t) decreases from its maximum to zero, I 1 (t) is also reduced to a lower value. These changes in current result in the load impedance seen by transistors  104  and transistor  108  changing to maximize the amplifier&#39;s efficiency until the current I 2 (t) reaches zero. This is possible because the impedance seen by the drain of  104  is a function of the transmission line  112  as well as the load seen by that transmission line. 
     When transistor  108  is driving the load resistor  116 , the impedance Z x  seen at right of the transmission line  112  is given by:                Z   X     =       V   X       I   X               Equation                 5                         
     and is thus a function of the current flowing through transistor  108  since: 
     
       
           I   3 ( t )= I   x ( t )+ I   2 ( t )  Equation 6 
       
     
     and thus:                Z   X     =         V   X       I   X       =         (       I   X     +     I   2       )          R   L         2        I   X                   Equation                 7                         
     This phenomenon of the impedance being affected by a current or voltage can be referred to as a “virtual impedance” effect. 
     As the current I 2  from transistor  108  decreases, the virtual impedance seen as a load by transistor  104  can be shown to go from R L  to 2R L , and thus, the load on transistor  104  is modulated. The power delivered to the load resistor  116  varies from the maximum to the maximum/4 over this range. Since the voltage delivered by the first transistor  104  is to an increased virtual load impedance, efficiency remains high over the range of output voltage of the transistor  108 . 
     Once the second stage transistor  108  is delivering zero current, it is effectively in cutoff and presents an impedance load approximating ∞. Thus, from this point downward to further reduced output signals, the amplifier  100  operates alone as a single stage transistor amplifier driving a fixed impedance load. However, over the first range described above, from maximum output power to ¼ maximum output power, the efficiency remains at or near peak efficiency. The efficiency curve of this amplifier is illustrated in the graph as curve  140  of FIG.  2 . For a conventional class A amplifier, the best efficiency of 50% is only achieved at peak output power as illustrated by curve  150 . 
     In the above two-stage amplifier  100 , efficiency is retained by separately controlling the input signal delivered to the first and second stages of amplification so that as the input signal (and thus the output signal) decreases, the efficiency remains high. Although the input to the first and second stages  104  and  108  are being reduced (which would reduce the efficiency in a conventional distributed amplifier design in which both inputs were equal in magnitude), they are reduced at different rates. This results in modulation of the virtual impedance seen by the transistors throughout the circuit so that the first stage transistor  104  and the second stage transistor  108  operate at peak efficiency throughout the range of operation of the second stage transistor  108 . Once the second stage of amplification is completely cut off (at ¼ output power), it ceases to drain current and contribute to decreased efficiency. Transistor  108 , when cut off, also ceases to contribute to the output. Thus, the load impedance seen at the right of transmission line  112  (Z x ) goes from R L  when transistor  108  is operating at maximum output to R L /2 when transistor  108  is cut off. Since transmission line  112  is a quarter wavelength long with characteristic impedance of R L , the load impedance seen by transistor  104  is transformed from R L  at full maximum output to 2R L  when transistor  108  is cut off. 
     In order to achieve this efficiency in practice, the input signals V in1 (t) and V in2 (t) are modulated as a function of some information signal m(t) being amplified in order to produce the efficiencies described herein. The exact relationships defining the input signals needed to achieve the operation described herein are somewhat difficult to generalize since they depend somewhat upon the exact amplifier configuration and types of devices used in the distributed amplifier. For the current two-stage amplifier, the output power can be defined as the sum of the contribution of the two amplifier stages as follows: 
     
       
           P   OUT ( t )= P   out1 ( t )+ P   out2 ( t )  Equation 8 
       
     
     Where P out1  and P out2  are the output power contributions of amplifiers  104  and  108  respectively. For this particular amplifier, using identical FETs with transconductance g m  as amplifying elements, the individual output powers are given by:                  P   out1          (   t   )       =       g   m   2            R   L     2            V   IN1   2          (   t   )                 Equation                 9                         
     and                  P   out2          (   t   )       =       g   m   2            R   L     2            V   IN2   2          (   t   )                 Equation                 10                         
     For maximum efficiency of operation, V y  is held constant and the following relationships hold:                  P   out          (   t   )       =       g   m   2              R   L     2          [       5        V   IN1   2       -     4        V   IN1          V   INMAX       +     V   INMAX   2       ]                 Equation                 11                         
     whenever the output power P out (t) is between the maximum output power P MAX  and P MAX /4; and                  P   out          (   t   )       =       g   m   2                R   L     2          [       V   IN1          (   t   )       ]       2               Equation                 12                         
     whenever the output power P out (t) is between P MAX /4 and zero (i.e., when V in2 (t)=0). For this particular amplifier structure, the efficiencies described can be achieved by driving the amplifier with a pair of input voltages that are derived by setting the power output equal to a modulating signal times a gain factor for the amplifier and solving for V in1 (t) and V in2 (t) as a function of the modulating signal in the above equations. 
     Turning now to FIG. 3, another exemplary amplifier circuit  200  using a tapered distributed transmission line structure is presented further illustrating the concepts of the present invention. In this embodiment, a four-stage amplifier is presented in which FET transistors (serving as amplifiers)  202 ,  204 ,  206  and  208  each contribute drive currents to drive a load  216 . Amplifiers  202  and  204  are separated by a quarter wavelength transmission line  220  at their output nodes (the drains) having characteristic impedance R L . Similarly, amplifiers  204  and  206  are separated by a quarter wavelength transmission line  224  having characteristic impedance R L /2. Finally, Amplifiers  206  and  208  are separated by a quarter wavelength transmission line  226  having characteristic impedance R L /3. This produces a tapered transmission line arrangement, according to preferred implementations. A drive source  230  is shown driving the four-stage amplifier  200  in accord with the principles of the present invention. 
     The term “stage” as used herein is a term of convenience in referencing the various amplifiers making up a distributed amplifier. Those having ordinary skill in the art will appreciate, however, that the term should not imply that the “stages” are cascaded to produce a multiplicative effect. Rather, the individual “stages” of the present distributed amplifier contribute to the overall output power delivered to the load in an additive manner. Thus, all things being equal, a four-stage distributed amplifier can deliver power output to a load that is the sum of the contributions of each of the four stages, and those contributions may or may not be equal at maximum power output. 
     The characteristic impedances of transmission lines  220 ,  224  and  226  are determined in this example using a virtual impedance model and solving for the virtual impedance needed to have each transistor operate under identical load conditions at maximum drain current output from each transistor, looking at the impedance at each node as will be shown more fully later. 
     Generally speaking, amplifier  200  operates in a manner similar to that of amplifier  100  of the present example with several ranges of operation. At full maximum output, all four transistors  202 ,  204 ,  206  and  208  are driving the load at maximum output to achieve maximum efficiency. 
     When a first range of output less than maximum output is needed (i.e., the input envelope drops below maximum), the drive to the fourth stage (rightmost stage  208 ) is reduced from maximum to zero. Simultaneously, the drive to the third stage  206  is reduced to a lesser degree down to some range limit value while the first two stages continue to produce maximum output. Stages  206  and  208  continue to produce output at peak efficiency, even though their output is less than maximum because the virtual impedance load seen by each stage is modulated to achieve maximum efficiency. 
     When a second range of output power is needed due to further reduction in input signal, the drive to the third stage  206  is further reduced while simultaneously reducing the drive to the second stage. In this range the fourth stage  208  is turned off and the first stage continues to deliver maximum power at maximum efficiency. Stages  204  and  206  continue to produce output at peak efficiency, even though their output is less than maximum because the virtual impedance load seen by each stage is modulated to achieve maximum efficiency. 
     When a third range of further reduced output power is needed, a similar action occurs with the third stage  206  turning completely off along with the fourth stage, while the drive to the second stage  204  and the first stage  202  are reduced. The first and second stages  202  and  204 , although producing less than maximum output, continue to produce output at or near peak efficiency in this range and the overall amplifier efficiency remains at or near peak efficiency. 
     When a final range of reduced power output is reached, the only transistor remaining to contribute to the output is transistor  202 . Transistors  204 ,  206  and  208  are all cut off and transistor  202  operates at gradually reduced output and efficiency until there is no output. 
     In order to understand the details of the operation of the amplifier  200 , significant values at the end points of the various ranges are derived below in detail. It is helpful to analyze the operation of this circuit from the load back in this process in order to appreciate the operation. But, before proceeding with the analysis of amplifier  200 , consider a generalized view at any given node as shown in FIG.  4 . The impedance looking into this node can be determined using basic circuit analysis and is given by:              Z   =       V     I   a       =         R   ·     (       I   a     +     I   b       )         I   a       =     R   ·     [     1   +       I   b       I   a         ]                   Equation                 13                         
     This Equation 13 takes the same form as that of Equation 5 above and illustrates that the impedance Z seen at any given point in the active circuit of FIG. 4 is a function not only of purely passive circuit elements, but also is a function of the active elements and the currents produced thereby. Thus, the “virtual impedance” Z can be controlled by application of appropriate currents I a  and I b  with the resulting virtual impedance being a function of the ratio of the two currents. Applying similar analysis to each of the nodes of FIG. 3, under the assumption that all currents are added in phase, and working from the load back, the following can be determined, with Equation 14 being trivial since there are no currents to sum and the load is shown to be purely resistive.                Z   10     =       R   L     4             Equation                 14                 Z   9     =         R   L     4     ·     [     1   +       I   8       I   d4         ]               Equation                 15                         
     Now consider the circumstance wherein all of the drain currents are maximized so that: 
     
       
           I   d1   =I   d1MAX   =I   d2   =I   d2MAX   =I   d3   =I   d3MAX   =I   d4   =I   d4MAX   =I   MAX   Equation 16 
       
     
     which means that: 
     
       
           I   TOTAL   =I   d1MAX   +I   d2MAX   +I   d3MAX   +I   d4MAX =4 I   MAX   Equation 17 
       
     
     and: 
     
       
           I   2   =I   MAX   Equation 18 
       
     
     and: 
     
       
           I   5   =I   2   +I   d2MAX =2 I   MAX   Equation 19 
       
     
     and: 
     
       
           I   8   =I   5   +I   d3MAX =2 I   MAX   Equation 20 
       
     
     In this case, Equation 5 becomes:                Z   9     =           R   L     4     ·     [     1   +       3        I   MAX         I   MAX         ]       =           R   L     4     ·     [   4   ]       =     R   L                 Equation                 21                         
     Now consider the case where the value of I D4  is reduced to zero by reducing the drive to the final stage transistor  208 . In this case the impedance given by Equation 15 is given by:                Z   9     =           R   L     4     ·     [     1   +       I   8       →   0         ]       →   ∞             Equation                 22                         
     So, as the current from the fourth transistor is cut off, the impedance Z 9  seen looking into the final stage transistor approaches ∞. A similar minimum and maximum analysis applied to Z 8  gives the following results:                Z   8     =           R   L     4     ·     [     1   +       I   MAX       3        I   MAX           ]       =           R   L     4     ·     [     4   3     ]       =       R   L     3                 Equation                 23                 Z   8     =           R   L     4     ·     [     1   +     0     3        I   MAX           ]       =       R   L     4               Equation                 24                         
     As Z 8  goes from its maximum value given by Equation 23 to its minimum value given by Equation 22, the impedance seen at Z 7  changes as shown in the equations below. When the impedance seen by the third transmission line  226  is equal to the transmission line&#39;s characteristic impedance, the value of Z 7  is given by:                Z   7     =         R   L     3     =     Z   03               Equation                 25                         
     When Z 8  deviates from the value of the characteristic impedance of the quarter wave transmission line  226 , (i.e., when it approaches its minimum value as given by Equation 24), the impedance seen at Z 7  can be determined from the relationship of Equation 26 below which defines the impedance of for a quarter wave transmission line terminated by any given termination impedance.                  (       R   L     4     )     ·     (     Z   7     )       =       (       R   L     3     )     2             Equation                 26                         
     Solving Equation 26 for Z 7  yields:                Z   7     =         (       R   L   2     9     )     ·     (     4     R   L       )       =       4                   R   L       9               Equation                 27                         
     In accordance with the principles of operation described above, it is desired that over the first range of operation where the currents of I d3 (t) and I d4 (t) are reduced, the first two stages  202  and  204  should continue to operate at maximum output and maximum efficiency. For this to hold true, the impedance Z 4  seen by the transistor  204 , and thus Z 5  seen by transmission line  224  should remain constant over this range. For now, assume this is the case, and thus at the range limits:                Z   5     =           R   L     3     ·     [     1   +       I   MAX       2        I   MAX           ]       =       R   L     2               Equation                 28                         
     and                  R   L     2     =         4        R   L       9     ·     [     1   +       [   X   ]     ·       I   MAX       2        I   MAX             ]               Equation                 29                         
     where X represents a fraction of the maximum current. Solving for X, it is determined that X=¼ at the other end of the range. Thus, by adjusting I d3 (t) from I d3MAX (t) to (¼)I d3MAX (t) while I d4 (t) is adjusted from I d4MAX (t) to a value of zero, the impedance Z 5  is kept constant at a value of R L /2 so that first and second stages  202  and  204  continue to operate at maximum output and efficiency during the first range of output values. Over this same range, Z 6  is given by:                Z   6     =           R   L     3     ·     [     1   +       2        I   MAX         I   MAX         ]       =     R   L               Equation                 30                         
     and                Z   6     =           4        R   L       9     ·     [     1   +       2        I   MAX           1   4     ·     I   MAX           ]       →     4        R   L                 Equation                 31                         
     Now consider the second range of operation wherein transistor  208  is cut off and transistor  206  is driven to generate drain currents in the range between (¼)I d3MAX (t) to zero. Through this range, the value of Z 5  is given by:                  Z   5              4        R   L       9     ·     [     1   +         1   4          I   MAX         2        I   MAX           ]         =       R   L     2             Equation                 32                         
     and                Z   5     =           4        R   L       9     ·     [     1   +     0     2        I   MAX           ]       =       4        R   L       9               Equation                 33                         
     Over this same second range of operation, Z 4  changes value in accord with the change of value of Z 5 . Over this range, the current through transistor  206  goes to zero, and thus, the impedance Z 6 →∞. When Z 5  is R L /2=the characteristic impedance of the transmission line  224 , the value Z 4  is:                Z   4     =         R   L     2     =     Z   02               Equation                 34                         
     When the value of Z 5  changes to its other extreme of this range of 4R L /9, the value of Z 4  is determined from the equation for the impedance of a terminated quarter wavelength transmission line as follows:                  (       4        R   L       9     )     ·     (     Z   4     )       =       (       R   L     2     )     2             Equation                 35                         
     Solving Equation 35 for Z 4  yields:                Z   4     =         (       R   L   2     4     )     ·     (     9     4        R   L         )       =       9        R   L       16               Equation                 36                         
     During this range of operation, it is desired to keep the first stage amplifier  202  operating at maximum output and maximum efficiency. For this to occur, the load Z 1  seen by transistor  202  should remain constant. This suggests that the load Z 2  seen by the transmission line  220  should also remain constant as I d2 (t) goes from its maximum value to some fraction Y of its maximum value. Thus:                Z   2     =           R   L     2     ·     [     1   +       I   MAX       I   MAX         ]       =     R   L               Equation                 37                         
     and                R   L     =         9        R   L       16     ·     [     1   +       [   Y   ]     ·       I   MAX       I   MAX           ]               Equation                 38                         
     Solving for Y it is determined that Y={fraction (7/9)} at the other end of the range. Thus, by adjusting I d2 (t) from I d2MAX (t) to ({fraction (7/9)})I d2MAX (t) while I d3 (t) is adjusted from (¼)I d3MAX (t) to a value of zero, the impedance Z 2  is kept constant at a value of R L  so that first stage  202  continues to operate at maximum output and efficiency during this range of output values. Over this same range, Z 3  is given by:                Z   3     =           9        R   L       16     ·     [     1   +       2        I   MAX           7   9          I   MAX           ]       =       9        R   L       7               Equation                 39                         
     and                Z   3     =           9        R   L       16     ·     [     1   +       I   MAX     0       ]       →   ∞             Equation                 40                         
     Now consider the operation of I d2 (t) ranging in value from ({fraction (7/9)})I d2MAX (t) down to zero. The value of Z 2  at each end of the range is given by:                Z   2     =           9        R   L       16     ·     [     1   +         7   9          I   MAX         I   MAX         ]       =     R   L               Equation                 41                         
     and                Z   2     =           9        R   L       16     ·     [     1   +     0     I   MAX         ]       =       9        R   L       16               Equation                 42                         
     When Z 2 =R L , the value of Z 1  is: 
     
       
           Z   1=R   L   Equation 43 
       
     
     When Z 2 =({fraction (9/16)})R L , the value of Z 1  can be determined from the equation for a terminated quarter wavelength transmission line as:                  (       9        R   L       16     )     ·     (     Z   1     )       =     R   L   2             Equation                 44                         
     Solving Equation 44 for Z 1  yields:                Z   1     =         R   L   2     ·     (     16     9        R   L         )       =       16        R   L       9               Equation                 45                         
     It is now desired to keep the voltage V 1  at the junction of the transistor  202  and the transmission line  220  constant as I d1 (t) changes in value from I d1MAX (t) to (K)I d1MAX (t) where K is a fractional part of the maximum current.                    I   d1MAX          (   t   )       ·     R   L       =       (   K   )              I   d1MAX          (   t   )       ·       16        R   L       9                 Equation                 46                         
     Solving for K results in: 
     
       
           K ={fraction (9/16)}  Equation 47 
       
     
     The total load current delivered to the load  216  is shown as I TOTAL . The square of this current I TOTAL  is proportional to the output power delivered to the load and is given by:                P   OUT     =       I   TOTAL   2            R   L     4               Equation                 48                         
     When designing the amplifier for the tapered distributed transmission line implementation shown above, the characteristic impedances of the transmission lines can be determined by applying the virtual impedance equation to each node with the objective of operating each amplifier stage into an identical load having value R L . The output from each transistor is additive to the total current delivered to the load, so that for a four stage distributed amplifier, ¼ of the total maximum current is delivered to the load by any individual transistor. At the load, there are two currents summed into the node, I 8  and I d4 . At maximum current, the single device virtual load impedance is given by:                    R   L     4     ·     (     1   +     3   1       )       =     R   L             Equation                 49                         
     while the virtual load impedance seen by transistor  206  is given by:                    R   L     4     ·     (     1   +     1   3       )       =       R   L     3             Equation                 50                         
     Therefore, the characteristic impedance of transmission line  226  is designed to have a characteristic impedance of R L /3 ohms. 
     Moving back one node to the node at transistor  206 &#39;s drain, the single device virtual impedance load is given by:                    R   L     3     ·     (     1   +     2   1       )       =     R   L             Equation                 51                         
     while the virtual load impedance seen by transistor  204  is given by:                    R   L     3     ·     (     1   +     1   2       )       =       R   L     2             Equation                 52                         
     Therefore, the characteristic impedance of transmission line  224  is designed to have a characteristic impedance of R L /2 ohms. 
     Moving back one node, the single device virtual impedance load is given by:                    R   L     2     ·     (     1   +     1   1       )       =     R   L             Equation                 53                         
     while the virtual load impedance seen by transistor  202  is given by:                    R   L     2     ·     (     1   +     1   1       )       =     R   L             Equation                 54                         
     Therefore, the characteristic impedance of transmission line  226  is designed to have a characteristic impedance of R L  ohms. As previously mentioned, the transmission lines may be implemented as lumped element devices or as actual transmission line sections of any suitable design. 
     The values derived above for the several ranges of operation of amplifier  200  are tabulated, below in TABLE 1. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 MAX 
                   
                   
                   
                   
                 ZERO 
               
               
                 Parameter 
                 OUTPUT 
                 Range 1 
                 Range 2 
                 Range 3 
                 Range 4 
                 OUTPUT 
               
               
                   
               
             
            
               
                 I d1   
                 I MAX   
                 I MAX   
                 I MAX    
                 I MAX →(9/16)I MAX   
                 (9/16)I MAX  → 0 
                 0 
               
               
                 I d2   
                 I MAX   
                 I MAX   
                 I MAX  → (7/9)I MAX   
                 (7/9)I MAX  → 0 
                 0 
                 0 
               
               
                 I d3   
                 I MAX   
                 I MAX  → (1/4)I MAX   
                 (1/4)I MAX  → 0 
                 0 
                 0 
                 0 
               
               
                 I d4   
                 I MAX   
                 I MAX  → 0 
                 0 
                 0 
                 0 
                 0 
               
               
                 I TOTAL   
                 4I MAX   
                 4I MAX  → (9/4)I MAX   
                 (9/4)I MAX  → (16/9)I MAX   
                 (16/9)I MAX  → (9/16)I MAX   
                 (9/16)I MAX  → 0 
                 0 
               
               
                 Z 1   
                 R L   
                 R L   
                 R L   
                 R L   
                 R L  → 16R L /9 
                 16R L /9 → ∞ 
               
               
                 Z 2   
                 R L   
                 R L   
                 R L   
                 R L  → 9R L /16 
                 9R L /16 
                 9R L /16 
               
               
                 Z 3   
                 R L   
                 R L   
                 R L  → 9R L 7 
                 9R L /7 → ∞ 
                 ∞ 
                 ∞ 
               
               
                 Z 4   
                 R L /2 
                 R L /2 
                 R L /2 → 9R L /16 
                 9R L /16 
                 9R L /16 
                 9R L /16 
               
               
                 Z 5   
                 R L /2 
                 R L /2 → R L /9 
                 R L /9 
                 R L /9 
                 R L /9 
                 R L /9 
               
               
                 Z 6   
                 R L   
                 R L  → 4R L   
                 4R L  → ∞ 
                 ∞ 
                 ∞ 
                 ∞ 
               
               
                 Z 7   
                 R L /3 
                 R L /3 → 4R L 9 
                 4R L /9 
                 4R L /9 
                 4R L /9 
                 4R L /9 
               
               
                 Z 8   
                 R L /3 
                 R L /3 → R L /4 
                 R L /4 
                 R L /4 
                 R L /4 
                 R L /4 
               
               
                 Z 9   
                 R L   
                 R L  → ∞ 
                 ∞ 
                 ∞ 
                 ∞ 
                 ∞ 
               
               
                 Z 10   
                 R L /4 
                 R L /4 
                 R L /4 
                 R L /4 
                 R L /4 
                 R L /4 
               
               
                   
               
            
           
         
       
     
     Thus, from the above development, it can be seen that as the drive to each successive stage is reduced to zero, the load seen by each stage is modulated to achieve maximum efficiency up until the time that only a single stage of amplification is contributing to the output power delivered to the load  216 . At this point, efficiency begins to fall off. But, prior to this point, extremely high efficiency is maintained throughout the range of input values. This is illustrated in FIG. 5 which shows curve  250  which graphs the conversion efficiency versus output current I TOTAL  for amplifier  200  illustrating that the conversion efficiency remains near 100% of maximum theoretical efficiency (for the particular amplifier class) until output current drops by about 18 dB from maximum. 
     This amplifier  200  provides a load modulation method of extending the peak output signal level conversion efficiency to levels down 9/64 below the peak output voltage and over almost an 18 dB power output range. This efficiency benefit provides a significant improvement in battery life when used in the RF amplifier section of portable communication devices. 
     In order to achieve this end result, control signals that drive the amplifier stages are applied to the gates (in this FET example) of transistors  202 ,  204 ,  206  and  208  to appropriately control the virtual impedances seen by the amplifier stages. Control voltage V g1  is applied to the gate of transistor  202 , V g2  is applied to the gate of transistor  204 , V g3  is applied to the gate of transistor  206 , and V g4  is applied to the gate of transistor  208 . In each case, it is assumed that the drain current at each respective transistor is proportional to its gate voltage and that the control voltage is proportional to the gate voltage. FIG. 6 illustrates graphically how the control voltages are varied in this example to achieve this result. The control voltages of this example, and the drive signals for any amplifier in general according to certain embodiments of the invention, may be generated in any number of ways within a suitable drive source  230  including, but not limited to, use of lookup tables and/or digital signal processing techniques. 
     Control voltage V g4  is varied linearly from zero to the maximum value of the gate voltage as I TOTAL  ranges from ({fraction (9/4)})I MAX  to 4I MAX . This change in control voltage V g4  is carried out as the control voltage V g3  applied to transistor  206  simultaneously decreases (at a different rate in this example). Thus, the values of control voltages V g3  and V g4  act in concert to increase the virtual impedances seen by transistors  206  and  208  so that the current is delivered to the load from the third and fourth stages at maximum efficiency. 
     Control voltage V g3  is varied linearly from zero to the maximum value of the gate voltage as I TOTAL  ranges from ({fraction (16/9)})I MAX  to 4I MAX . Control voltage V g3  is approximately (¼) of the maximum gate voltage at the point V g4  reaches zero. Simultaneously, during a portion of the range of operation, the control voltage V g2  is varying. The values of control voltages V g3  and V g2  act in concert to increase the virtual impedances seen by transistors  204  and  206  so that the current is delivered to the load from the second and third stages at maximum efficiency. 
     Control voltage V g2  is varied linearly from zero to the maximum value of the gate voltage as I TOTAL  ranges from ({fraction (9/16)})I MAX  to ({fraction (9/4)})I MAX . Control voltage V g2  is approximately ({fraction (7/9)}) of the maximum gate voltage at the point V g3  reaches zero. Simultaneously, during a portion of the range of operation, the control voltage V g1  is varying. The values of control voltages V g1  and V g2  act in concert to increase the virtual impedances seen by transistors  202  and  204  so that the current is delivered to the load from the first and second stages is kept at maximum efficiency until no input is delivered to drive transistor  204  and the sole contribution to output power is from transistor  202 . 
     Control voltage V g1  is varied linearly from zero to the maximum value of the gate voltage as I TOTAL  ranges from zero to ({fraction (16/9)})I MAX  and V g1  reaches its maximum at approximately the point where V g3  reaches zero. When the contribution of the second stage  204  reaches zero, transistor  202  is the only transistor driving the load and as the control signal V g3  decreases beyond this point, efficiency drops. 
     To summarize, the control voltage (or current or power) for a given stage is developed as a function of the input signal so that the voltage at each amplifier&#39;s output node is maintained constant until only one amplifier stage remains. This virtual impedance is a function of both the drain current of the stage and the current produced by the preceding stage, so that both stages act in concert to assure that a constant output voltage is seen at each node for as long as an output contribution is being made by two or more transistors in the distributed amplifier. 
     For a given pair of adjacent stages in the distributed amplifier structure (call them first and second stages), the first stage is connected to the second stage through a transmission line, the second stage provides a portion of a virtual impedance load to the first stage. An input signal m(t) to be amplified by the distributed amplifier is used to generate a pair of signals to drive the amplifier. A first drive signal is generated that varies as a function of m(t) to drive the first stage. A second drive signal is generated that varies as a function of m(t) to drive the second stage. The first drive signal varies as a function of m(t) from a maximum to zero as m(t) varies from a maximum value to some value m 1 , the second drive signal varies as a function of m(t) from a maximum value to zero as m(t) varies from a maximum value to a value m 2 , where m 1  is less than m 2 . The values can be derived from the graph of FIG. 6 along with the above equations. 
     Since the present embodiment is illustrated using field effect transistors, the drive signals (or control signals) are represented as voltages (control voltages or drive voltages). However, the control signals could equally well be expressed as currents or powers for other types of amplifiers such as bipolar amplifiers, with the assumption that the collector or emitter current is approximately proportional to a control current applied to the transistor&#39;s base. The transmission lines may be either a coaxial, planar, stripline, or other form of actual transmission line, or may be a lumped element approximation of a transmission line, without limitation. In addition, while a tapered distributed transmission line structure is preferred, embodiments using many of the teachings and benefits of the current invention can be realized without the preferred tapered distributed transmission line structure described. Such embodiments are contemplated by the present invention. Other equivalent variations will occur to those skilled in the art. 
     Amplifier  200  above operates to amplify a plurality of independently varying input signals as follows: 
     
       
           I   TOTAL =( V   g1   ·g   m1 )+( V   g2   ·g   m2 )+( V   g3   ·g   m3 )+( V   g4   ·g   m4 )  Equation 55 
       
     
     In order to achieve the efficiency described herein, the four gate voltages are developed within drive source  230  as a function of a modulating signal m(t) to be amplified. One issue presented to the designer is how to generate these four signals as a function of this modulating signal in the general case. In order to address this issue, consider an N stage generalized example as illustrated in FIG.  7 . While it is complex to generate a generalized expression for each drive signal due to many design variables, the principles described herein can be used to readily derive the drive signals for any given example. 
     The devices used for amplifiers can be bipolar devices, MOSFET devices, MESFET devices, or any other semiconductor or vacuum tube (or other technology) amplifying device. Accordingly, the exact input signal and drive signals can be viewed as either voltagess or currents. Moreover, depending on the exact device selected and its class of operation, the output currents and voltages are a function of the, voltage gain, current gain, transconductance, etc. properties of the amplifying device. Thus, for purposes of the present development, the drive signals used to drive the various amplifier sections of any given amplifier structure consistent with certain embodiments of the current invention are expressed in terms of the output signals they produce. 
     Referring now to FIG. 7, a generalized distributed amplifier circuit  300  according to the present invention is illustrated in which N transistors  302 ,  304 , . . .  308 ,  310  are driven at their bases (in this bipolar example) by a drive circuit  315 . The drive circuit  315  receives an input power signal P in (t), or in general an input signal S IN (t), and from that input signal produces a plurality of N drive signals S 1 (t) . . . S N (t) that are applied as inputs to the transistors  302 ,  304 , . . .  308 ,  310  such that the output signal delivered to load  320  is given by P out (t)=GP in (t), with G representing the amplifier circuit&#39;s power gain. The collectors represent the output current sources for each of the N transistors and produce output current into N nodes  1  through N. Each of the N nodes are separated by a transmission line, or equivalent circuit,  332 ,  334 , . . .  338 ,  340  that is preferably in the form of a tapered transmission line. The drive signal generating circuit produces the N drive signals such that over a first range of operation: 
     S N (t) produces an output current from transistor N ranging from a maximum output current to zero; 
     S N−1 (t) produces an output current from transistor N−1 that preserves the voltage at node N−1 constant over the range of output current from transistor N; and 
     S 1 (t) through S N−2 (t) produce maximum output current from transistors  1  through N−2. 
     Over a second range of operation: 
     S N (t) produces an output current from transistor N of zero; 
     S N−1 (t) produces an output current from transistor N−1 ranging from a current less than maximum to zero; 
     S N−2 (t) produces an output current from transistor N−2 that preserves the voltage at node N−2 constant over the range of output current from transistor N−1; and 
     S 1 (t) through S N−3 (t) produce maximum output current from transistors  1  through N−3. 
     Over a third range of operation: 
     S N (t) produces an output current from transistor N of zero; 
     S N−1 (t) produces an output current from transistor N of zero; 
     S N−2 (t) produces an output current from transistor N−2 ranging from a current less than maximum to zero; 
     S N−3 (t) produces an output current from transistor N−3 that preserves the voltage at node N−3 constant over the range of output current from transistor N−2; and 
     S 1 (t) through S N−4 (t) produce maximum output current from transistors  1  through N−4. 
     This operation continues through multiple ranges of operation depending upon the number of stage N until finally only the first stage is producing output current in which case over an N th  range of operation: 
     S N (t) through S 2 (t) produces an output current from transistors N through  2  of zero; and 
     S 1 (t) produces an output current from transistor  1  ranging from a current less than maximum to zero. 
     The above operation is possible, as previously described, by modulating the virtual impedance at each node to permit the voltage at the output to remain constant while maintaining high efficiency until the last range of the last stage of operation. 
     In the case of the four-stage amplifier  200 , the drive signals to the transistors  202 ,  204 ,  206  and  208  can be determined as follows. Beginning with the output node current I total  equal to the summation of the four device currents translated across device  206  and  208  output interconnect network, I 7  is determined as follows:                I   7     =         V   4       Z   03       =         I   Total          [         R   L     4         R   L     3       ]       =       3   4          [       I   01     +     I   02     +     I   03     +     I   04       ]                   Equation                 54                         
     Where the currents I 0x  represent the individual device currents I dx (t) translated to the output load R L /4. At the maximum output power operating point the device currents are expected to be equal at I dmax  and Equation 54 becomes:                I   7     =         (     3   4     )        4        I     d                 max         =     3        I     d                 max                   Equation                 55                         
     rewriting this relation in a general form with the constraint that I d3  and I d4  are decreased in a manner to preserve the operating conditions of I 51  and I 52  (currents attributed to device  202  and  204  at I 5  branch), leads to:                  I     51                 max       +     I     52                 max       +     I   d3       =       I   7     =       (     3   4     )          (       I     01                 max       +     I     02                 max       +     I     03                 max       +     I   d4       )                 Equation                 56                         
     replacing I 0x(max)  with I dmax  and deducing we obtain the following relation:                I   d3     =         I     d                 max       4     +       3        I   d4       4               Equation                 57                         
     a relation defining I d3  as a function of I d4  to preserve the operating load conditions on sections  202  and  204  constant independent of the current I d4 . 
     Keeping the first two sections operating in their peak output point maintains their maximum efficiency while the output power is lowered with a reduction in the third and fourth distributed amplifier section currents. The next step is development of a relation for I d3  and I d4  as a function of P out , the output power dissipated in the load R L /4.                P   out     =       GP   in     =         (       R   L     4     )            (       I     01                 max       +     I     02                 max       +     I   d3     +     I   d4       )     2       =         R   L     64            (       9        I     d                 max         +     7        I   d4         )     2                   Equation                 58                         
     where G is the gain of device  208 . Solving for the currents over the range 81I dmax R L /64&lt;=|P out &lt;=4I dmax R L  gives:                I   d4     =       1   7          [         (       64                   P   out         R   L       )       1   2       -     9        I     d                 max           ]               Equation                 59                         
     and                I   d3     =         3   28          [         (       64                   P   out         R   L       )       1   2       -     9        I     d                 max           ]       +       I     d                 max       4               Equation                 60                         
     By factoring in the gain (or transconductance) of the devices  206  and  208 , these relationships for I d3  and I d4  can be used to directly solve for the input signal levels |V g3 (t)| and |V g4 (t)| as a function of the desired output power range (and thus the input power range) in the range of 81R L /64&lt;=|P out |=|GP in |&lt;=4R L . 
     Continuing on with this procedure to obtain driving functions for V g1 (t) and V g2 (t) as a function of desired output power follows in a similar manner with the third output section load impedance                Z   7     =         Z   o3   2         R   L     4       =       4        R   L       9               Equation                 61                         
     and the node voltage                V   3     =         I   7          Z   7       =       (       I   51     +     I   52     +     I   d3       )            4                   R   L       9                 Equation                 62                         
     Transforming this through the quarter wavelength transmission line:                I   4     =         V   3       Z   o2       =         8   9          (       I   51     +     I   52     +     I   d3       )       =       I   21     +     I   d2                   Equation                 63                         
     solving for i d2  as a function of 0&lt;=I d3 &lt;=I dmax/ 4               I   d2     =           7        I     d                 max         9     +       8        I   d3       9       =         7        I     d                 max         +     8        I   d3         9               Equation                 64                         
     and output power is                P   out     =       GP   in     =         I   7   2          Z   7       =           4        R   L       9            (       I   51     +     I   52     +     I   d3       )     2       =         R   L     4            (       I     01                 max       +     I   d2     +     I   d3     +     I   d4       )     2                     Equation                 65                         
     Setting I 01(max)  equal to I dmax , I d4  equal to zero, and replacing I d2  in terms of I d3 , Equation 65 becomes:                P   out     =       GP   in     =           R   L     4          [         16        I     d                 max         +     17        I   d3         9     ]       2               Equation                 66                         
     over the P out  range 64I dmax R L /81&lt;=|P o |&lt;=81I dmax R L /64, i c4 =0, and                I   d3     =             4        P   out         R   L         -     16        I     d                 max           17             Equation                 67                         
     over the range 0&lt;=I d3 &lt;=I d3(max) /4 and 7I d2(max, /9&lt;=I d2 &lt;=I d2(max)  for Equation 64. Thus, for the second range of operation, the above equations for I d2  and I d3  can be solved for input signals V g2  and V g3  to produce the desired efficiency. 
     Continuing on to the next range of operation once I d3 =0,                Z   7     =       Z   5     =         Z   o3   2         R   L     4       =       4                   R   L       9                 Equation                 68                         
     and                Z   4     =         Z   o2   2         4        R   L       9       =           4        R   L       9            (       R   L     2     )     2       =       9        R   L       16                 Equation                 69                         
     and                V   2     =         (       I   12     +     I   d2       )          Z   4       =       (       I   12     +     I   d2       )          (       9        R   L       16     )                 Equation                 70                         
     which is transformed to the current:                I   d1     =         V   2       Z   01       =         (       I   12     +     I   d2       )          Z   4       =       (       I   12     +     I   d2       )          (     9   16     )                   Equation                 71                         
     Setting I 12  with I dmax  at the condition I d2 =7I dmax /9 results in:                I   d1     =       9   16          (       I     d                 max       +     I   d2       )               Equation                 72                         
     over the range 0&lt;=I c2 &lt;=7I c(max) /9, and solving for P out                 P   out     =       GP   in     =         I   4   2          Z   4       =           9        R   L       16            (       I   41     +     I   d2       )     2       =         R   L     4            (       I   d1     +     I   d2     +     I   d3     +     I   d4       )     2                     Equation                 73                         
     Setting I d4  and I d3  equal to zero, and expressing I d1  in terms of I d2 , Equation 73 becomes:                P   out     =         (         9        I     d                 max         +     25        I   d2         16     )     2            R   L     4               Equation                 74                         
     over the range 81i dmax R L /1024&lt;=|P o |&lt;=64i dmax R L /81 and 9i d1(max) /16&lt;=i d1 &lt;=i d1(max)   
     
       
         
           
             
               
                 
                   
                     I 
                     d2 
                   
                   = 
                   
                     
                       
                         
                           ( 
                           16 
                           ) 
                         
                          
                         
                           [ 
                           
                             
                               
                                 4 
                                  
                                 
                                   P 
                                   out 
                                 
                               
                               
                                 R 
                                 L 
                               
                             
                           
                           ] 
                         
                       
                       - 
                       
                         9 
                          
                         
                           I 
                           
                             d 
                              
                             
                                 
                             
                              
                             max 
                           
                         
                       
                     
                     25 
                   
                 
               
               
                 
                   Equation 
                    
                   
                       
                   
                    
                   75 
                 
               
             
           
         
         
         
             
         
       
     
     and                I   d1     =             (   16   )          [         4        P   out         R   L         ]       -     9        I     d                 max         +     I     d                 max         25          (     9   16     )               Equation                 76                                       P   out     =         (       9                   I   d1       16     )     2            R   L     4               Equation                 77                         
     over the final range 0&lt;=|P o |&lt;=64i dmax R L /81               I   d1     =         (   16   )          [         4        P   out         R   L         ]       9             Equation                 78                         
     Thus, for this four-stage example, there are seven drain current equations (59, 60, 64, 67, 72, 75, and 78) representing the drive signals needed to achieve extended linear efficiency performance over output power range 81i dmax R L /1024&lt;=|P out |&lt;=4i dmax R L . Working back from the required current, the appropriate drive voltages or currents can be generated for each active device. 
     In the exemplary generalized bipolar amplifier  300  of FIG. 7, a similar process can be used at each stage to compute the required collector current equations. These can then be used to derive base current or voltage required as the drive signals. As a linear amplifier, accurate reproduction of the input signal is desirable minimizing error and distortion terms. What this means (in a preferred ideal case) is the class of operation for each stage would be one with optimized linear performance thus defining the input drive signals based on class of operation as well as the extended linear function. However, the indepenent input signals of this extended linear technology offers a degree of freedom in uniquely defining each stage class of operation for optimized performance. 
     The above processes have been described in terms of one of the simpler mechanisms for generating appropriate virtual impedances at the various nodes to permit operation of the distributed amplifier structure with enhanced efficiency. However, many other drive mechanisms are possible without departing from the present invention. For example, more complex drive signals can be applied to the distributed amplifier&#39;s active elements to permit, for example, three of the active elements to produce reduced output currents simultaneously (rather than two at a time) while maintaining high efficiency of the overall structure. In other embodiments, the output of all of the amplifiers can be adjusted simultaneously using more complex drive signal generation while still maintaining high efficiency. Such variations are contemplated by this invention. However, for ease of understanding, the simplest case is described in detail. 
     Referring now to FIG. 8, an exemplary drive circuit  315  is illustrated in which an input signal S in (t) is applied to a processor such as a Digital Signal Processor (DSP)  350 . Processor  350  computes the value of signal needed for each input of the distributed amplifier, taking into consideration the voltage or current gain or transconductance of the amplifier. A plurality of N signal generators  354 ,  356 , . . .  560  are then instructed what instantaneous signal to produce by the processor  350 . 
     FIG. 9 illustrates a related embodiment of drive circuit  315  in which the values of the N drive signals is computed using a lookup table. In this case, N lookup tables  372 ,  374 , . . .  378  receive the input signal S in (t) and respectively look up the value required for each amplifier device input. The output is fed to a plurality of N signal generators in the form of quadrature modulators  382 ,  384 , . . .  388 . 
     Yet another example of a drive circuit  315  implementation is illustrated in FIG.  10 . In this embodiment, the value of S in (t) is evaluated at  402  to determine a range in which the input value falls. This can be accomplished readily, as illustrated, using a lookup table. Depending upon the range of the input signal, the input is applied to one of several (two illustrated) circuits having fixed transfer functions. For example, the input signal can be processed by a circuit  406  having transfer function T 1 -A for a first range of values of S in (t) and by circuit  408  having transfer function T 1 -B for a second range of values of S in (t) to produce an output signal S 1 (t). The ranges vary depending upon the stage of amplification and the transfer functions are adapted to each range of operation of each stage. Similar processing for the second stage is carried out in  412  or  414  depending upon the range of operation and so on until the final stage drive signal S n (t) is generated by either  420  or  422  depending upon the range selected by lookup table  402 . 
     Other embodiments of drive circuits are also possible including circuits using feedback sensed from the output voltage or current at each stage of the distributed amplifier and/or at the load to determine a proper range or input signal to create. Other embodiments of active/passive generation of the various drive signals will occur to those skilled in the art. 
     According to the above-described embodiments, a method of operating an N stage distributed amplifier to deliver power to a load can be generally described, without limitation, as over a first range of output power from a maximum output power to a first power P N  where P N  is greater than zero, driving the load with N stages of the distributed amplifier. Over a second range of output power from P N  to P N−1 , where P N−1  is less than P N , the load is driven with N−1 stages of the distributed amplifier. Over a third range of output power from P N−1  to P N−2 , where P N−2  is less than P N−1 , the load is driven with N−2 stages of the distributed amplifier. Over a fourth range of output power from P N−2  to P N−3 , where P N−3  is less than P N−2 , the load is driven with N−3 stages of the distributed amplifier, and so on. When the final stage is reached, over an N th  range of output power from P 1  to zero the load is driven with one stage of the distributed amplifier. The N stages of the distributed amplifier are driven with N drive signals that vary as a function of an input signal to be amplified. Preferably, the N drive signals are varied in a manner to maximize conversion efficiency of each operational stage over each range until the final stage. 
     In another embodiment, a method of operating an N stage distributed amplifier to deliver power to a load is carried out by: over a first range of output power from a maximum output power to a first power P N  where P N  is greater than zero, driving the load with N stages of the distributed amplifier; and over a last range of output power from P 1  to zero, driving the load with one stage of the distributed amplifier. 
     While the present invention can also be used to continuously vary the virtual impedances of the amplifiers for high efficiency, those skilled in the art will appreciate that the principles described herein can also be used for stepped output power control to retain high efficiency at selected lower output powers. 
     Each of the above exemplary embodiments utilize quarter wavelength transmission lines in a tapered distributed transmission line arrangement interconnecting the stages in the distributed amplifier. Using quarter wavelength inter-stage connection sections provide an advantage of elimination of the phase shifting of the signal through the composite system as the amplitude is varied. As the amplitude of the stages is varied independently the output networks are no longer terminated in their image or characteristic impedance. If the interconnection networks are not multiples of 90 degrees the resulting network undergoes an impedance transformation that is a function of the image parameters as does the termination impedance and the phase shift. For example, a transmission line terminated at both terminals with its characteristic impedance provides an impedance transformation independent of its length in degrees. However, when terminated in an impedance (including real only) other than the characteristic impedance results in impedance transformation that includes a real and reactive component that is a function of the phase length in degrees. There is at least one exception, when the length is a multiple of quarter wavelength and where the impedance transformation of a real load is also real. 
     A phase shift can be included in the virtual load conditioning provided by the second stage signal variation described above. This can be used to reduce the interconnection component requirements and/or extension of the operating frequency range. This means that interconnection networks with phase shifts other than quarter wavelength multiples can be used with phase and amplitude compensation signals. These compensation signals are determined using the virtual impedance relationships above. Also, although preferred, other embodiments can be devised that do not used the tapered distributed transmission line structure of the exemplary embodiments. 
     During the range of operation of this conditioned virtual impedance, the output signal voltages and power of the proceeding stages remains constant. This constant signal voltage condition can be used to generate a control loop for adjusting the following stage. However, the stage immediately preceding the final power delivering stage is also expected to maintain a constant output signal voltage while its load impedance is increasing and the output power is decreasing. This means that each stage can use its own output voltage to determine a control signal necessary to maintain a constant output voltage as the output load changes. 
     Those skilled in the art will understand that the distributed amplifiers depicted herein are depicted as using field effect transistors. However, distributed amplifiers are commonly implemented using other types of transistors including vacuum tubes, bipolar transistors, gallium arsenide devices, MOSFETS, MESFETS, etc. Moreover, the present illustrative examples are shown as single ended amplifiers, but the concepts described herein are equally and equivalently applicable to differential amplifier configurations. Such variations are equivalent and within the scope of the present invention. Additionally, the amplifiers shown herein operate by gradually reducing the output contribution of amplifier stages from the load back. This too should not be considered limiting since the amplifier stages can be controlled in any suitable manner using the principles of the present invention to modulate the load on one or more stages of amplification while reducing the contribution of any stage or stages to the output power without departing from the present invention. Additionally, as previously noted, the transmission lines can be lumped element approximations (for example, lumped element pi networks) or actual transmission lines or combinations thereof, and may or may not be tapered distributed transmission lines, and may or may not be quarter wavelength without departing from the present invention. 
     Those skilled in the art will recognize that the present invention has been described in terms of exemplary embodiments based upon use of a programmed processor. However, the invention should not be so limited, since the present invention could be implemented using hardware component equivalents such as special purpose hardware and/or dedicated processors which are equivalents to the invention as described and claimed. Similarly, general purpose computers, microprocessor based computers, micro-controllers, optical computers, analog computers, dedicated processors and/or dedicated hard wired logic may be used to construct alternative equivalent embodiments of the present invention. 
     The present invention, as described in embodiments herein, can be implemented using a programmed processor executing programming instructions that are broadly described above and which can be stored on any suitable electronic storage medium or transmitted over any suitable electronic communication medium. However, those skilled in the art will appreciate that the processes described above can be implemented in any number of variations and in many suitable programming languages without departing from the present invention. For example, the order of certain operations carried out can often be varied, additional operations can be added or operations can be deleted without departing from the invention. Error trapping can be added and/or enhanced and variations can be made in user interface and information presentation without departing from the present invention. Such variations are contemplated and considered equivalent. 
     While the invention has been described in conjunction with specific embodiments, it is evident that many alternatives, modifications, permutations and variations will become apparent to those of ordinary skill in the art in light of the foregoing description. Accordingly, it is intended that the present invention embrace all such alternatives, modifications and variations as fall within the scope of the appended claims.