Patent Publication Number: US-11037824-B2

Title: Semiconductor device and method for manufacturing the same

Description:
RELATED APPLICATIONS 
     The present application is a continuation application of U.S. application Ser. No. 16,222,640, filed on Dec. 17, 2018, now U.S. Pat. No. 10,755,977, issued on Aug. 25, 2020, which is a continuation application of U.S. application Ser. No. 15,907,148, filed on Feb. 27, 2018, now U.S. Pat. No. 10,157,790, issued on Dec. 18, 2018, which claims priority of U.S. Provisional Application Ser. No. 62,565,028, filed on Sep. 28, 2017, all of which are herein incorporated by reference in their entireties. 
     BACKGROUND 
     As the technology nodes shrink, in some integrated circuit (IC) designs, there has been a desire to replace the typically polysilicon gate electrode with a metal gate electrode to improve device performance with the decreased feature sizes. One process of forming a metal gate structure is termed a “gate last” process in which the final gate structure is fabricated “last” which allows for reduced number of subsequent processes, including high temperature processing, that must be performed after formation of the gate. Additionally, as the dimensions of transistors decrease, the thickness of the gate oxide must be reduced to maintain performance with the decreased gate length. In order to reduce gate leakage, high-dielectric-constant (high-k) gate dielectric layers are also used which allow greater physical thicknesses while maintaining the same effective thickness as would be provided by a thinner layer of the gate oxide used in larger technology nodes. 
     However, there are challenges to implementing such features and processes in complementary metal-oxide-semiconductor (CMOS) fabrication. As the gate length and spacing between devices decrease, these problems are exacerbated. For example, source/drain regions may short to metal gate structures due to misalignment of contacts. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1A and 1B  are a flow chart illustrating a method of fabricating a semiconductor device in accordance with some embodiments of the instant disclosure; and 
         FIGS. 2-23  are cross-sectional views of a portion of a semiconductor device at various stages in a helmet layer formation process in accordance with some embodiments of the instant disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. 
       FIGS. 1A and 1B  are flowcharts of a method for manufacturing a semiconductor device in accordance with some embodiments of the present disclosure.  FIGS. 2-23  illustrate a method of forming a semiconductor device in accordance with some embodiments of the present disclosure. 
     The method begins with block S 102  in which a gate dielectric layer, a dummy gate layer, and a mask layer are formed over a substrate (as shown in  FIG. 2 ). The method continues with block S 104  in which an etching process is performed to pattern the gate dielectric layer and the dummy gate layer (as shown in  FIG. 3 ). The method continues with block S 106  in which gate spacers are formed over the substrate (as shown in  FIG. 4 ). The method continues with block S 108  in which a first interlayer dielectric (ILD) layer is formed (as shown in  FIG. 5 ). The method continues with block S 110  in which the first and second dummy gate portions and mask portions thereon are removed to form a first recess and a second recess (as shown in  FIG. 6 ). The method continues with block S 112  in which a first gate stack and a second gate stack are formed in the first and second recesses respectively (as shown in  FIG. 7 ). The method continues with block S 114  in which a first self-aligned contact (SAC) hard mask layer is formed above the gate spacers and first ILD portions (as shown in  FIG. 8 ). The method continues with block S 116  in which a planarization process such is performed such that the first SAC hard mask layer is lowered to level with the gate spacers (as shown in  FIG. 9 ). The method continues with block S 118  in which first via openings are formed above source/drain regions (as shown in  FIG. 10 ). The method continues with block S 120  in which a first barrier layer is blanket formed over the substrate, the gate spacers, the first SAC hard mask portions (as shown in  FIG. 11 ). The method continues with block S 122  in which a first conductive layer is deposited above the first barrier layer (as shown in  FIG. 12 ). The method continues with block S 124  in which a planarization process is performed to remove the excess first conductive layer and the first barrier layer (as shown in  FIG. 13 ). The method continues with block S 126  in which an etch back process is performed to remove some portions of first barrier portions and conductive features (as shown in  FIG. 14 ). The method continues with block S 128  in which conductive caps are formed in openings (as shown in  FIG. 15 ). The method continues with block S 130  in which a second SAC hard mask layer is formed on the gate spacers (as shown in  FIG. 16 ). The method continues with block S 132  in which a planarization process is performed, so as to lower the second SAC hard mask layer to level with top surfaces of the gate spacers (as shown in  FIG. 17 ). The method continues with block S 134  in which a contact etch stop layer (CESL) and a second ILD layer are formed (as shown in  FIG. 18 ). The method continues with block S 136  in which second via openings are formed in the second ILD layer (as shown in  FIG. 19 ). The method continues with block S 138  in which an etching process is performed to remove some portions of the CESL and second SAC hard mask portions (as shown in  FIG. 20 ). The method continues with block S 140  in which a third via opening is formed above the first gate stack (as shown in  FIG. 21 ). The method continues with block S 142  in which a second barrier layer and a second conductive layer are formed over the CESL and the second ILD layer (as shown in  FIG. 22 ). The method continues with block S 144  in which a planarization process is performed to remove excess portions of the second ILD layer, the second barrier layer, and the second conductive layer (as shown in  FIG. 23 ). 
     Reference is made to  FIG. 2 . A gate dielectric layer  110 , a dummy gate layer  112 , and a mask layer  114  are formed over a substrate  102 . In some embodiments, the substrate  102  includes a semiconductor substrate. In some embodiments, the substrate  102  includes a bulk silicon substrate. In some embodiments, the substrate  102  may be silicon in a crystalline structure. In some embodiments, the substrate  102  may include other elementary semiconductors, such as germanium, or include a compound semiconductor, such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide. In some embodiments, the substrate  102  includes a silicon-on-insulator (SOI) substrate. The SOI substrate may be fabricated using separation by implantation of oxygen, wafer bonding, and/or other suitable methods. In some embodiments, the substrate  102  is patterned to form a fin structure extending in an elongate manner. 
     The dielectric layer  110  is formed over the substrate  102 . In some embodiments, the substrate  102  includes a fin structure, and the dielectric layer  110  is formed around the fin structure. The dielectric layer  110  may include a material having a dielectric constant, k, of at least or equal to about 4.0. Examples of high-k dielectric material include hafnium-based materials such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, and HfO 2 Al 2 O 3  alloy. Additional examples of high-k dielectrics include ZrO 2 , Ta 2 O 5 , Al 2 O 3 , Y 2 O 3 , La 2 O 3 , and SrTiO 3 . The dielectric layer  110  may be formed by using a deposition process, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputter deposition, or other techniques suitable for depositing materials. 
     The dummy gate layer  112  is formed over the gate dielectric layer  110 . In some embodiments, the dummy gate layer  112  may include polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, or metals. In some embodiments, the dummy gate layer  112  includes a metal-containing material such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multi-layers thereof. The dummy gate layer  112  may be formed by using a deposition process, for example, CVD, PVD, ALD, sputter deposition, or other techniques suitable for depositing materials. 
     The mask layer  114  is formed over the dummy gate layer  112  and then patterned to form mask portions  116 A and  116 B. The mask portions  116 A and  116 B can protect underlying portions of the dummy gate layer  112  and the gate dielectric layer  110  against subsequent etching processes. The patterned mask layer  114  may be formed by a series of operations including deposition, photolithography patterning, and etching processes. The photolithography patterning process may include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, developing the photoresist, rinsing, drying (e.g., hard baking), and/or other applicable processes. The etching processes may include dry etching, wet etching, and/or other etching methods (e.g., reactive ion etching). 
     Reference is made to  FIG. 3 . An etching process is performed to pattern the gate dielectric layer  110  and the dummy gate layer  112 , thereby forming a first dummy gate structure  118 A and a second dummy gate structure  118 B. In some embodiments, the etching process may include dry etching. During the etching process, the mask portions  116 A and  116 B serve as etching masks, such that the gate dielectric layer  110  and the dummy gate layer  112  (see  FIG. 2 ) are etched according to the patterns of mask portions  116 A and  116 B. After the etching process, the first and second dummy gate structures  118 A and  118 B formed over the substrate  102  are elongated bars crossing the fin structure of the substrate  102  in substantially perpendicular manner. The first and second dummy gate structures  118 A and  118 B can be referred to as gate electrodes having longitudinal directions parallel to each other. The first and second dummy gate structures  118 A and  118 B can define at least one channel region of the fin structure of the substrate  102 . After the etching process, some portions of the gate dielectric layer  110  and the dummy gate layer  112  (see  FIG. 2 ) remain, such as a first gate dielectric portion  110 A, a second gate dielectric portion  110 B, a first dummy gate portion  112 A, and a second dummy gate portion  112 B. Furthermore, the first gate dielectric portion  110 A and the first dummy gate portion  112 A may be collectively referred to as the first dummy gate structure  118 A, and the second gate dielectric portion  110 B and the second dummy gate portion  112 B may be collectively referred to as the second dummy gate structure  118 B. 
     Reference is made to  FIG. 4 . Gate spacers  120 A,  120 B,  120 C,  120 D, and  120 E are formed over the substrate  102 . The gate spacers  120 A and  120 B are around the first dummy gate structure  118 A, and the gate spacers  120 C and  120 D are around the second dummy gate structure  118 B. In some embodiments, a spacer material is deposited over the substrate  102  and then the spacer material is etched back, and selected portions as the gate spacers  120 A- 120 E remain after the etch back. For example, the first dummy gate structure  118 A is sandwiched between the gate spacers  120 A and  120 B, and the second dummy gate structure  118 B is sandwiched between the gate spacers  120 A and  120 B. Furthermore, in some embodiments, in prior to the formation of the gate spacers  120 A- 120 E, an ion implantation process may be performed to form lightly doped drain (LDD) regions in the substrate  102 . During the ion implantation process for forming the LDD regions, the first and second dummy gate structures  118 A and  118 B can serve as masks to help control the implant profile and distribution. 
     In some embodiments, the spacer material includes SiOC, SiCN, or a combination thereof. In some embodiments, the gate spacers  120 A- 120 E are made of SiOC by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an oxygen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the gate spacers  120 A- 120 E are made of SiCN by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an nitrogen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. 
     After the formation of the gate spacers  120 A- 120 E, source/drain (S/D) regions  122  are formed in the substrate  102 . The S/D regions  122  in the substrate  102  are laterally spaced from sides of at least one of the first and second dummy gate structures  118 A and  118 B (i.e. adjacent the regions of the substrate  102  underlying the first and second dummy gate structures  118 A and  118 B). In some embodiments, the S/D regions  122  are formed by using an ion implantation. For example, an n-type dopant, such as phosphorous, or a p-type dopant, such as boron is doped into at least one portion of the substrate  102  which is not covered by the first and second dummy gate structures  118 A and  118 B and the gate spacers  120 A- 120 E, so as to form the S/D regions  122 . 
     Reference is made to  FIG. 5 . A first ILD layer  124  is formed. The first ILD layer  124  may comprise a dielectric material. The dielectric material may comprise silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), spin-on glass (SOG), fluorinated silica glass (FSG), carbon doped silicon oxide (e.g., SiCOH), polyimide, and/or combinations thereof. It is understood that the first ILD layer  124  may comprise one or more dielectric materials and/or one or more dielectric layers. In some embodiments, the first ILD layer  124  may be deposited to a suitable thickness by CVD, high density plasma (HDP) CVD, sub-atmospheric CVD (SACVD), spin-on, sputtering, or other suitable methods. After the formation of the first ILD layer  124 , the first ILD layer  124  may adhere to the gate spacers  120 A- 120 E and be over the top of the mask portions  116 A and  116 B. Then, a planarization process such as chemical mechanical polish (CMP) is performed to remove the excess first ILD layer  124 . In some embodiments, the planarization process stops when the mask portions  116 A and  116 B are exposed. In such embodiments, the mask portions  116 A and  116 B may serve as the CMP stop layer in the planarization process. After the planarization process, some portions of the first ILD layer  124  remain. For example, first ILD portions  124 A and  124 B remain. The first ILD portion  124 A is between the gate spacers  120 B and  120 C, and the first ILD portion  124 B is between the gate spacers  120 D and  120 E. Furthermore, the gate spacers  120 A- 120 E and the first ILD portions  124 A and  124 B may have approximately the same height. 
     Reference is made to  FIG. 6 . The first and second dummy gate portions  112 A and  112 B and the mask portions  116 A and  116 B thereon (see  FIG. 5 ) are removed to form recesses  126 A and  126 B. The first and second dummy gate portions  112 A and  112 B (see  FIG. 5 ) are removed by using an etching process including wet etch and dry etch. In some embodiments, a hard mask is patterned over the fin structure of the substrate  102  to protect the first ILD portions  124 A and  124 B and the gate spacers  120 A- 120 E. Accordingly, after the etching process, the recesses  126 A and  126 B are formed, in which the recess  126 A is formed between the gate spacers  120 A and  120 B and the recess  126 B is formed between the gate spacers  120 C and  120 D. In some embodiments, the etch operations regarding the first and second dummy gate portions  112 A and  112 B (see  FIG. 5 ) may stop at the first and second gate dielectric portions  110 A and  110 B (see  FIG. 5 ). In some embodiments, the first and second gate dielectric portions  110 A and  110 B (see  FIG. 5 ) may be removed along with the first and second dummy gate portions  112 A and  112 B (see  FIG. 5 ). 
     Reference is made to  FIG. 7 . A first gate stack  128 A and a second gate stack  128 B are formed in the recesses  126 A and  126 B respectively. The first gate stack  128 A includes a first work function material portion  130 A and a first metal gate electrode  132 A, and the second gate stack  128 B includes a second work function material portion  130 B and a second metal gate electrode  132 B. In some embodiments, the first and second gate stacks  128 A and  128 B can be referred to as high-k metal gates. 
     In some embodiments, the first and second work function material portions  130 A and  130 B may be formed by conformally depositing a work function metal layer, and the first and second metal gate electrodes  132 A and  132 B may be formed by depositing a gate electrode material layer on the work function material layer. In such embodiments, the overfilled work function material layer and the gate electrode material layer are pulled back by, for example, an etch back process, to form the first and second gate stacks  128 A and  128 B. After the etch back process, some portions of the work function material layer and the gate electrode material layer thereon remain, such as the first and second work function material portions  130 A and  130 B and the first and second metal gate electrodes  132 A and  132 B. The first and second work function material portions  130 A and  130 B are respectively in the recesses  126 A and  126 B, and therefore the first and second gate dielectric portions  110 A and  110 B are respectively covered with the first and second work function material portions  130 A and  130 B. In addition, the first and second metal gate electrodes  132 A and  132 B are respectively in the recesses  126 A and  126 B as well. 
     In some embodiments, the first and second work function material portions  130 A and  130 B include suitable work function metals to provide suitable work functions for the first and second gate stacks  128 A and  128 B. In some embodiments, the first and second work function material portions  130 A and  130 B may include one or more n-type work function metals (N-metal) for forming an n-type transistor on the substrate  102 . The n-type work function metals may exemplarily include, but are not limited to, TiAl, TiAlN, TaCN, Hf, Zr, Ti, Ta, Al, metal carbides (e.g., HfC), ZrC, TiC, AlC, aluminides, and/or other suitable materials. In some embodiments, the first and second work function material portions  130 A and  130 B may include one or more p-type work function metals (P-metal) for forming a p-type transistor on the substrate  102 . The p-type work function metals may exemplarily include, but are not limited to, TiN, WN, W, Ru, Pd, Pt, Co, Ni, conductive metal oxides, and/or other suitable materials. In some embodiments, the first and second metal gate electrodes  132 A and  132 B may include W, Al, Cu, Ni, Co, Ti, Ta, TiN, TaN, nickel silicide, cobalt silicide, TaC, TaSiN, TaCN, TiAl, TiAlN, or other suitable materials. 
     Reference is made to  FIG. 8 . A first self-aligned contact (SAC) hard mask layer  134  is formed above the gate spacer  120 A- 120 E and the first ILD portions  124 A and  124 B. Some portions of the first SAC hard mask layer  134  are within the recesses  126 A and  126 B and serve to protect the underlying components or layers, such as the first and second gate stacks  128 A and  128 B in subsequent processes. In some embodiments, the first SAC hard mask layer  134  includes a suitable material, for example SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, ZrN, A-Si (amorphous silicon), or combinations thereof, which may be deposited by using e.g., PVD, CVD, PECVD, low pressure CVD, or the like. In some embodiments, the first SAC hard mask layer  134  is made of a material different from that of the first ILD portions  124 A and  124 B. 
     In some embodiments, the first hard layer  134  is made of SiO by using a deposition process at a temperature in a range from 50° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which SiH 4 , N 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiN by using a deposition process at a temperature in a range from 250° C. to 500° C. and at a pressure in a range from 1 Torr to 10 Torr, in which DCS, NH 3 , or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiC by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, tetramethylsilane (TMS), or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiON by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which SiH 4 , N 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiOC by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an oxygen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiCN by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, a nitrogen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of SiOCN by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of AlO or AlON by using a deposition process at a temperature in a range from 200° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which trimethylaluminum (TMA), H 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of ZrO/ZrN by using a deposition process at a temperature in a range from 200° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which ZrCl 4 , H 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the first hard layer  134  is made of A-Si by using a deposition process at a temperature in a range from 350° C. to 530° C. and at a pressure under 1 Torr, in which SiH 4 , Si 2 H 6 , or combinations thereof may be used in the deposition process as reacting precursors. 
     Reference is made to  FIG. 9 . A planarization process such as CMP is performed such that the first SAC hard mask layer  134  is lowered to level with the gate spacers  120 A- 120 E. After the planarization process, the portions of the first SAC hard mask layer  134  within the recesses  126 A and  126 B remain, such as the first SAC hard mask portions  134 A and  134 B. The first SAC hard mask portion  134 A is within the recesses  126 A and above the first gate stack  128 A, and the first SAC hard mask portion  134 B is within the recesses  126 B and above the second gate stack  128 B. The first SAC hard mask portions  134 A and  134 B can serve to protect the first and second gate stacks  128 A and  128 B in subsequent processes. In some embodiments, the first SAC hard mask portions  134 A and  134 B have the same thickness in a range from 5 nm to 50 nm. The first SAC hard mask portions  134 A and  134 B serve to protect the underlying components or layers like the first and second gate stacks  128 A and  128 B during subsequent via formation processes. 
     Reference is made to  FIG. 10 . First via openings  136 A and  136 B are formed above the S/D regions  122 . The first via openings  136 A and  136 B are formed by removing the first ILD portions  124 A and  124 B (see  FIG. 9 ). In some embodiments, The first ILD portions  124 A and  124 B (see  FIG. 9 ) may be removed by using an etch back process. In some embodiments, the etch back process may be a selectively etching process. During the selectively etching process, since the etch back process may be a selectively etching process, where the etchant(s) selectively remove the first ILD portions  124 A and  124 B (see  FIG. 9 ) while keep the first SAC hard mask portions  134 A and  134 B substantially intact. Accordingly, after the removal of the first ILD portions  124 A and  124 B (see  FIG. 9 ), the first via openings  136 A and  136 B are formed to expose the underlying S/D regions  122  in the fin structure of the substrate  102 . 
     Reference is made to  FIG. 11 . A first barrier layer  138  is blanket formed over the substrate  102 , the gate spacers  120 A- 120 E, and the first SAC hard mask portions  134 A and  134 B. Some portions of the first barrier layer  138  are within the first via openings  136 A and  136 B, in which these portions of the first barrier layer  138  may be in contact with a sidewall of at least one of the gate spacers  120 A- 120 E and the S/D regions  122  in the fin structure of the substrate  102 . In some embodiments, the first barrier layer  138  is a metal or metal alloy layer. The first barrier layer  138  may include Co, Ag, Al, Zn, Ca, Au, Mg, W, Mo, Ni, Cr, or the like, which may be deposited by using e.g., PVD, CVD, PECVD, LPCVD, or the like. 
     Reference is made to  FIG. 12 . A first conductive layer  140  is deposited above the first barrier layer  138 . The first via openings  136 A and  136 B formed after the removal of the first ILD portions  124 A and  124 B (see  FIG. 9 ) are filled by the first conductive layer  140 . The first conductive layer  140  is wrapped around in the pocket lined by the first barrier layer  138 . The first conductive layer  140  includes electrically conductive materials and provides electrical connection to the S/D regions  122 . For example, the first conductive layer  140  includes Co, Ru, or combinations thereof. In some embodiments, the first conductive layer  140  is made of Co by using a deposition process at a temperature in a range from 300° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr. 
     Reference is made to  FIG. 13 . A planarization process such as CMP is performed to remove the excess first conductive layer  140  and the first barrier layer  138 . By the planarization process, top surfaces of the first conductive layer  140  and the first barrier layer  138  are level with top surfaces of the gate spacers  120 A- 120 E and the first SAC hard mask portions  134 A and  134 B. After the planarization process, some portions of the first barrier layer  138  and the first conductive layer  140  remain, such as the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. The first barrier portion  138 A and the conductive feature  140 A are within the first via opening  136 A, and the first barrier portion  138 B and the conductive feature  140 B are within the first via opening  136 B. In some embodiments, the conductive features  140 A and  140 B can be configured to electrically communicate lateral components on the substrate  102 . 
     Reference is made to  FIG. 14 . An etch back process is performed to remove some portions of the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. Top surfaces of the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B are brought down. After the etch back process, the height of at least one of the first barrier portions  138 A and  138 B is lower than bottoms of first SAC hard mask portions  134 A and  134 B, and the height of at least one of the conductive features  140 A and  140 B is lower than the bottoms of first SAC hard mask portions  134 A and  134 B as well. The top surfaces of the first SAC hard mask portions  134 A and  134 B and the conductive features  140 A and  140 B are in a position lower than top surfaces of the first and second gate stacks  128 A and  128 B. In some embodiments, at least one of the conductive features  140 A and  140 B may have a thickness in a range from 10 nm to 30 nm. Accordingly, after the etch back process, the top surfaces of the gate spacers  120 A- 120 E are bare and free of the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. Furthermore, openings  152 A and  152 B are formed after the removal of the portions of the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. The openings  152 A and  152 B are defined by the sidewalls of the gate spacers  120 B- 120 E and the top surfaces of the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. 
     Reference is made to  FIG. 15 . Conductive caps  154 A and  154 B are respectively formed in the openings  152 A and  152 B. Conductive caps  154 A and  154 B are formed using a bottom-up deposition technique, rather than a conformal deposition technique. The resulting conductive caps  154 A and  154 B thus resemble a substantial flat layer, rather a U-shaped layer, overlying conductive features  140 A and  140 B. The first barrier portion  138 A and the conductive feature  140 A are covered with the conductive cap  154 A, and the first barrier portion  138 B and the conductive feature  140 B are covered with the conductive cap  154 B. The conductive cap  154 A has a bottom surface in contact with the first barrier portion  138 A and the conductive feature  140 A, and the conductive cap  154 B has a bottom surface in contact with the first barrier portion  138 B and the conductive feature  140 B. Top surfaces of the conductive caps  154 A and  154 B are in a portion higher than the top surfaces of the first and second gate stacks  128 A and  128 B and lower than the top surfaces of the gate spacers  120 A- 120 E. In some embodiments, the conductive caps  154 A and  154 B may include Co, Ru, W, or combinations thereof, which may be deposited by using e.g., PVD, CVD, PECVD, low pressure CVD, or the like. In some embodiments, the conductive caps  154 A and  154 B are made of W by a selective deposition process at a temperature in a range from 300° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which tungsten hexafluoride (WF 6 ), fluorine-free tungsten (FFW), or combinations thereof may be used in the selective deposition process as reacting precursors. During the selective deposition process, the conductive caps  154 A and  154 B tend to be formed on the conductive features  140 A and  140 B rather than gate spacers  120 A- 120 E which are made of the spacer material. In some embodiments, the conductive caps  154 A and  154 B include a material which is different from that of the conductive features  140 A and  140 B. For example, the conductive features  140 A and  140 B are made of Co, and the conductive caps  154 A and  154 B are made of W. In some embodiments, at least one of the conductive caps  154 A and  154 B has a thickness in a ranged from 3 nm to 10 nm. In some embodiments, the conductive caps  154 A and  154 B are thinner than the conductive features  140 A and  140 B. The conductive caps  154 A and  154 B serves to protect the underlying components or layers like the first barrier portions  138 A and  138 B and the conductive features  140 A and  140 B. 
     Reference is made to  FIG. 16 . A second SAC hard mask layer  156  is formed on the gate spacers  120 A- 120 E, in which some portions of the second mask layer  156  fill in the openings  152 A and  152 B and are above the first barrier portions  138 A and  138 B, the conductive features  140 A and  140 B, and the conductive caps  154 A and  154 B. The second SAC hard mask layer  156  may be spaced apart from the conductive features  140 A and  140 B by the conductive caps  154 A and  154 B. In some embodiments, the second SAC hard mask layer  156  includes a suitable material, for example SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, ZrN, A-Si (amorphous silicon), or combinations thereof, which may be deposited by using e.g., PVD, CVD, PECVD, low pressure CVD, or the like. In some embodiments, the second SAC hard mask layer  156  is made of a material different from those of the first SAC hard mask portions  134 A and  134 B. For example, when the first SAC hard mask portions  134 A and  134 B are made of SiOCN, the second SAC hard mask layer  156  may be made of SiN. In some embodiments, the material of the first SAC hard mask portions  134 A and  134 B may be the same as the second SAC hard mask layer  156 . 
     In some embodiments, the second SAC hard mask layer  156  is made of SiO by using a deposition process at a temperature in a range from 50° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which SiH 4 , N 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiN by using a deposition process at a temperature in a range from 250° C. to 500° C. and at a pressure in a range from 1 Torr to 10 Torr, in which DCS, NH 3 , or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiC by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, tetramethylsilane (TMS), or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiON by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which SiH 4 , N 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiOC by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an oxygen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiCN by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, a nitrogen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of SiOCN by using a deposition process at a temperature in a range from 200° C. to 450° C. and at a pressure in a range from 1 Torr to 10 Torr, in which a silicon-containing gas, a carbon-containing gas, an oxygen-containing gas, a nitrogen-containing gas, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of AlO or AlON by using a deposition process at a temperature in a range from 200° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which trimethylaluminum (TMA), H 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of ZrO/ZrN by using a deposition process at a temperature in a range from 200° C. to 400° C. and at a pressure in a range from 1 Torr to 10 Torr, in which ZrCl 4 , H 2 O, or combinations thereof may be used in the deposition process as reacting precursors. In some embodiments, the second SAC hard mask layer  156  is made of A-Si by using a deposition process at a temperature in a range from 350° C. to 530° C. and at a pressure under 1 Torr, in which SiH 4 , Si 2 H 6 , or combinations thereof may be used in the deposition process as reacting precursors. 
     Reference is made to  FIG. 17 . A planarization process such as CMP is performed, so as to lower the second SAC hard mask layer  156  (see  FIG. 16 ) to level with the top surfaces of the gate spacers  120 A- 120 E. After the planarization process, some portions of the second SAC hard mask layer  156  remain, such as the second SAC hard mask portions  156 A and  156 B. Top surfaces of the second SAC hard mask portions  156 A and  156 B are level with the top surfaces of the gate spacers  120 A- 120 E and the first SAC hard mask portions  134 A and  134 B. In some embodiments, the second SAC hard mask portions  156 A and  156 B have the same thickness in a range from 5 nm to 50 nm. In some embodiments, the second SAC hard mask portions  156 A and  156 B have the same thickness which is different from those of the first SAC hard mask portions  134 A and  134 B. For example, the second SAC hard mask portions  156 A and  156 B are thinner than the first SAC hard mask portions  134 A and  134 B. Furthermore, a distance from the top surface of the second SAC hard mask portion  156 A to a bottom surface of the first barrier portion  138 A which is in contact with the substrate  102  is substantially equal to the height of at least one of the gate spacers  120 A- 120 E. The second SAC hard mask portions  156 A and  156 B serve to protect the underlying components or layers like the conductive caps  154 A and  154 B during subsequent via formation processes. 
     Reference is made to  FIG. 18 . A contact etch stop layer (CESL)  158  and a second ILD layer  160  are formed. The CESL  158  is formed on the gate spacers  120 A- 120 E, the first SAC hard mask portions  134 A and  134 B, and the second SAC hard mask portions  156 A and  156 B. The second ILD layer  160  is formed above the CESL  158 . In some embodiments, the CESL  158  serve as a metal contact etch stop layer. 
     In some embodiments, the CESL  158  includes a suitable material, for example SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, ZrN, A-Si (amorphous silicon), or combinations thereof, which may be deposited by using e.g., PVD, CVD, PECVD, low pressure CVD, or the like. In some embodiments, the material of the second SAC hard mask portions  156 A and  156 B and the CESL  158  may be the same. For example, when the second SAC hard mask portions  156 A and  156 B are made of SiN, the CESL  158  is made of SiN as well. In such embodiments, the material of the second SAC hard mask portions  156 A and  156 B and the CESL  158  may be the same and is different from the material of the first SAC hard mask portions  134 A and  134 B. Furthermore, the CESL  158  may have a thickness in a range from 5 nm to 50 nm. 
     In some embodiments, the second ILD layer  160  includes a suitable material, for example tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), combinations thereof, or other suitable dielectric materials. In some embodiments, the second ILD layer  160  includes a suitable material, for example SiO, SiN, SiC, SiON, SiOC, SiCN, SiOCN, AlO, AlON, ZrO, ZrN, A-Si (amorphous silicon), or combinations thereof. In some embodiments, the material of the second ILD layer  160  is different from that of the CESL  158 . The second ILD layer  160  may formed by using PVD, CVD, PECVD, low pressure CVD, or other suitable deposition technique. 
     Reference is made to  FIG. 19 . Second via openings  162 A and  162 B are formed in the second ILD layer  160  by any suitable process. For example, the formation of the second via openings  162 A and  162 B may include patterning the second ILD layer  160  by photolithography and etching processes, in which the etching process may be performed by using a dry etching, wet etching, and/or plasma etching process, so as to remove some portions of the second ILD layer  160 . During the etching process, since the etching process of the second ILD layer  160  may be a selectively etching process, where the etchant(s) selectively remove the some portions of the second ILD layer  160  while keep the underlying CESL  158  substantially intact. Accordingly, after performing the etching process of the second ILD layer  160 , some portions of the CESL  158  are exposed from the second via openings  162 A and  162 B. Furthermore, the second via openings  162 A and  162 B may vertically overlap the conductive features  140 A and  140 B. 
     Reference is made to  FIG. 20 . An etching process is performed to remove some portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B. For example, the potions of the CESL  158  exposed from the second via openings  162 A and  162 B of  FIG. 19  and the underlying second SAC hard mask portions  156 A and  156 B are removed. In some embodiments, the CESL  158  and the second SAC hard mask portions  156 A and  156 B are made of the same material, and thus the portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B can be removed in the same etching process. Accordingly, during the etching process for removing the portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B, the second via openings  162 A and  162 B respectively extend toward the substrate  102  until the conductive caps  154 A and  154 B are exposed. In this regard, the conductive caps  154 A and  154 B can respectively protect the underlying conductive features  140 A and  140 B from be damaged by the etching process for removing the portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B. Furthermore, during the etching process, since the etching process for removing the portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B may be a selectively etching process, where the etchant(s) selectively remove the portions of the CESL  158  and the second SAC hard mask portions  156 A and  156 B while keep the gate spacer  120 A- 120 E and the first SAC hard mask portions  134 A and  134 B substantially intact. 
     Reference is made to  FIG. 21 . A third via opening  164  is formed above the first gate stack  128 A. The third via opening  164  can be formed by removing some portions of the second ILD layer  160 , the CESL  158 , and the first SAC hard mask portion  134 A. The removal of the some portions of the second ILD layer  160 , the CESL  158 , and the first SAC hard mask portion  134 A can be performed by any suitable process. For example, the removal may include an etching process performed by using a dry etching, wet etching, plasma etching process, or combinations thereof, so as to remove some portions of the second ILD layer  160 , the CESL  158 , and the first SAC hard mask portion  134 A. In some embodiments, the etching process may stop until the first metal gate electrode  132 A is exposed. During the etching process for removing the second ILD layer  160 , the CESL  158 , and the first SAC hard mask portion  134 A, since the conductive features  140 A and  140 B are covered with the conductive caps  154 A and  154 B, the conductive caps  154 A and  154 B can respectively protect the underlying conductive features  140 A and  140 B from be damaged by the etching process. Therefore, the protection mechanism provided by the conductive caps  154 A and  154 B can result in the conductive features  140 A and  140 B keep substantially intact during the etching process for removing the second ILD layer  160 , the CESL  158 , and the first SAC hard mask portion  134 A. Accordingly, the formation of the second via openings  162 A and  162 B may be prior to the formation of the third via opening  164 . 
     Reference is made to  FIG. 22 . A second barrier layer  166  and a second conductive layer  168  are formed over the CESL  158  and the second ILD layer  160 . The second barrier layer  166  is blanket formed over the CESL  158  and the second ILD layer  160 , and the second conductive layer  168  is formed over the second barrier layer  166 . After the formation of the second barrier layer  166  and the second conductive layer  168 , some portions of the second barrier layer  166  are within the second and third via openings  162 A,  162 B, and  164 , and the second conductive layer  168  fills into the second and third via openings  162 A,  162 B, and  164 . In some embodiments, the second barrier layer  166  is a metal or metal alloy layer. The second barrier layer  166  may include Co, Ag, Al, Zn, Ca, Au, Mg, W, Mo, Ni, Cr, or combinations thereof, which may be deposited by using e.g., PVD, CVD, PECVD, LPCVD, or the like. In some embodiments, the second conductive layer  168  includes TiN, TaN, Ta, Ti, Hf, Zr, Ni, W, Co, Cu, or Al. In some embodiments, the second conductive layer  168  may be formed by CVD, PVD, plating, ALD, or other suitable technique. The second conductive layer  168  adheres to the second barrier layer  166 . The second conductive layer  168  is deposited until the second and third via openings  162 A,  162 B, and  164  are over-filled. 
     Reference is made to  FIG. 23 . A planarization process such as CMP is performed to remove excess portions of the second ILD layer  160 , the second barrier layer  166 , and the second conductive layer  168 . After the planarization process, the remained portions of the second barrier layer  166  and the second conductive layer  168  can collectively serve as a first contact plug  170 A, a second contact plug  170 B, and a third contact plug  170 C. In some embodiments, the first contact plug  170 A is within the third via opening  164  collectively defined by the first SAC hard mask portion  134 A, the CESL  158 , and the second ILD layer  160  and in contact with the top surface of the metal gate electrodes  132 A, so as to electrically connect to the metal gate electrodes  132 A. In some embodiments, the second contact plug  170 B is within the second via opening  162 A collectively defined by the second SAC hard mask portions  156 A, the CESL  158 , and the second ILD layer  160 . The conductive cap  154 A is between the conductive feature  140 A and the second contact plug  170 B, and the second contact plug  170 B is in contact with the top surface of the conductive cap  154 A, so as to electrically connect to the conductive feature  140 A through the conductive cap  154 A. In some embodiments, the third contact plug  170 C is within the second via opening  162 B collectively defined by the CESL  158  and the second ILD layer  160 . The conductive cap  154 B is between the conductive feature  140 B and the second contact plug  170 C, and the second contact plug  170 C is in contact with the top surface of the conductive cap  154 B, so as to electrically connect to the conductive feature  140 B through the conductive cap  154 B. Furthermore, after the planarization process, the second ILD layer  160  may have a thickness in a range from 5 nm to 50 nm. 
     As described above, the conductive features above the S/D regions are covered with the conductive caps which may have a different material from that of the conductive features. The conductive caps serve to protect the conductive features during the subsequent via formation processes. As the via formation process is performed by an etching process, the conductive caps can protect the conductive features from be damaged. Therefore, the protection mechanism provided by the conductive caps can result in the conductive features keep substantially intact during the via formation process. 
     In some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate stack, a first gate spacer and a second gate spacer, a first source/drain region and a second source/drain region, a first conductive feature and a second conductive feature, and a first contact plug and a second contact plug. The gate stack is over the substrate. The first gate spacer and the second gate spacer are on opposite sidewalls of the gate stack, respectively. The first source/drain region and the second source/drain region are in the substrate and on opposite sides of the gate stack, in which the first source/drain region is adjacent to the first gate spacer, and the second source/drain region is adjacent to the second gate spacer. The first conductive feature and the second conductive feature are over the first source/drain region and the second source/drain region, respectively. The first conductive cap and the second conductive cap are over the first conductive feature and the second conductive feature, respectively. The first contact plug and the second contact plug are over the first conductive cap and the second conductive cap, respectively, in which the first contact plug is separated from the first gate spacer, and the second contact plug is in contact with a sidewall and a top surface of the second gate spacer. 
     In some embodiments of the present disclosure, a semiconductor device includes a substrate, a gate stack, a source/drain region, a conductive feature, a conductive cap, and a contact plug. The gate stack is over the substrate. The source/drain region is in the substrate and adjacent to the gate stack. The conductive feature is over the source/drain region. The conductive cap is over the conductive feature. The contact plug is over and in contact with a top surface of the conductive cap, in which the contact plug is separated from the conductive feature by the conductive cap. 
     In some embodiments of the present disclosure, a method includes forming first and second source/drain regions in a substrate and a gate stack on the substrate, in which the first and second source/drain regions are on opposite sides of the gate stack; forming first and second conductive features over the first and second source/drain regions, respectively; forming first and second conductive caps over the first and second conductive features, respectively; forming first and second dielectric masks over the first and second conductive caps, respectively; etching the first and second dielectric masks, such that an opening is formed in the first dielectric mask, and an entirety of the second dielectric mask is removed from the second conductive cap; and forming first and second contact plugs over the first and second conductive caps, respectively, in which the first contact plug is formed in the opening of the first dielectric mask. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.