Patent Publication Number: US-9904338-B2

Title: Control chip, control method and connection device utilizing the same

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims priority of Taiwan Patent Application No. 103103065, filed on Jan. 27, 2014, the entirety of which is incorporated by reference herein. 
     BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The invention relates to a connection device, and more particularly to a connection device which is capable of connecting a host device, an electronic device and a peripheral device simultaneously. 
     Description of the Related Art 
     In present USB transmittal technology, a connection line is utilized to transmit data between a host device and an electronic device. The conventional connection line includes two terminals. One terminal is a USB standard type-A plug port and another terminal is a USB micro-B plug port. If the electronic device desires to communicate with a peripheral device, another connection line is utilized. One terminal of the other connection line is a USB micro-B plug port and another terminal of the other connection line is a USB standard type-A jack port. Since the two connection lines cannot share among the host device, the electronic device and the peripheral device, a user must buy many connection lines and carry the lines to connect devices. 
     BRIEF SUMMARY OF THE INVENTION 
     In accordance with an embodiment, a control chip includes a plurality of first pins, a plurality of second pins, a plurality of third pins, a level detection unit, a determining unit and a control unit. The first pins are coupled to a host device via a first connection port. The second pins are coupled to an electronic device via a second connection port. The third pins are coupled to a peripheral device via a third connection port. The level detection unit detects the first and second pins to generate a first detection result. The determining unit determines whether a portion of the first and second pins transmit data to generate a determination result. The control unit adjusts a level of a specific pin among the first and second pins according to the first detection result and the determination result. 
     An exemplary embodiment of a control method for a connection device including a first connection port coupled to a host device, a second connection port coupled to an electronic device and a third connection port coupled to a peripheral device is described in the following. Power pins of the first and second connection ports are detected to generate a detection result. It is determined whether the second connection port transmits data to generate a determination result. An identification pin of the second connection port is adjusted according to the detection result and the determination result. 
     In accordance with another embodiment, a connection device includes a first connection port, a second connection port, a third connection port and a control chip. The first connection port is configured to couple to a host device. The second connection port is configured to couple to an electronic device. The third connection port is configured to couple to a peripheral device. The control chip includes a plurality of first pins, a plurality of second pins, a plurality of third pins, a level detection unit, a determining unit and a control unit. The first pins are coupled to the first connection port. The second pins are coupled to the second connection port. The third pins are coupled to the third connection port. The level detection unit detects the first and second pins to generate a first detection result. The determining unit determines whether the second connection port is coupled to the second pins to generate a determination result. The control unit adjusts a level of a specific pin among the second pins according to the first detection result and the determination result. 
     A detailed description is given in the following embodiments with reference to the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The invention can be more fully understood by referring to the following detailed description and examples with references made to the accompanying drawings, wherein: 
         FIGS. 1A and 1B  are schematic diagrams of exemplary embodiments of a transmittal system, in accordance with some embodiments; 
         FIGS. 2A-2C  are schematic diagrams of exemplary embodiments of a control chip, in accordance with some embodiments; 
         FIGS. 3A-3C and 4A-4C  are schematic diagrams of exemplary embodiments of a control method, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     The making and using of the embodiments of the disclosure are discussed in detail below. It should be appreciated, however, that the embodiments provide many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative, and do not limit the scope of the disclosure. 
       FIG. 1A  is a schematic diagram of an exemplary embodiment of a transmittal system, in accordance with some embodiments. The transmittal system  100  includes a host device  110 , an electronic device  120 , a connection device  130  and a peripheral device  140 . The host device  110  can be any device with data processing functions, such as a computer. Additionally, the invention does not limit the kinds of electronic device  120  and peripheral device  140 . In one embodiment, the electronic device  120  is a mobile electronic device, such as a mobile phone or a tablet PC. In some embodiments, the peripheral device  140  is a USB device, such as a flash drive or a mouse. 
     In this embodiment, the connection device  130  includes connection ports  131 ˜ 133  and a control chip  134 . The connection port  131  is configured to couple to the host device  110 . The connection port  132  is configured to couple to the electronic device  120 . The connection port  133  is configured to couple to the peripheral device  140 . The control chip  134  transmits data and power among the connection ports  131 ˜ 133 . The invention does not limit the kinds of connection ports  131 ˜ 133 . In one embodiment, the connection ports  131 ˜ 133  are USB ports. The connection ports  131  and  133  are USB type-A ports. The connection port  132  is a USB micro-A port or a USB micro-B port. 
     The invention does not limit the type of connection device  130 . As shown in  FIG. 1A , the connection device  130  is an adapter board. In  FIG. 1B , the connection device  130  is a cable having three ends to connect to the host device  110 , the electronic device  120  and the peripheral device  140 . A user utilizes the host device  110  to charge the electronic device  120  or the peripheral device  140  via a single cable or a single board. In another embodiment, when the electronic device  120  has an On The Go (OTG) function, the connection device  130  sets the operation mode of the electronic device  120  according to the connection state of the connection ports  131 ˜ 132 . 
     For example, when the host device  110  is coupled to the connection port  131  and the electronic device  120  is coupled to the connection port  132 , the connection device  130  sets the level of an identification pin of the connection port  132 . In one embodiment, the connection device  130  sets the level of the identification pin of the connection port  132  to a high level such that the electronic device  120  operates in a device mode. In the device mode, the electronic device  120  is controlled by the host device  110  and receives power provided by the host device  110 . 
     When the electronic device  120  is coupled to the connection port  132  and the peripheral device  140  is coupled to the connection port  133 , the connection device  130  sets the level of the identification pin of the connection port  132 . In one embodiment, the connection device  130  adjusts the level of the identification pin of the connection port  132  to a low level. Therefore, the electronic device  120  operates in a host mode. In the host mode, the electronic device  120  controls and provides power to the peripheral device  140 . 
     In other embodiments, when the host device  110  and the peripheral device  140  are coupled to the connection device  130 , since the electronic device  120  is not coupled to the connection device  130 , the connection device  130  sets or does not set the level of the identification pin of the connection port  132 . At this time, the peripheral device  140  is controlled by the host device  110  and receives the power provided by the host device  110 . 
     Furthermore, when the host device  110  is coupled to the connection port  131 , the electronic device  120  is coupled to the connection port  132  and the peripheral device  140  is coupled to the connection port  133 , the control chip  134  provides communication between the host device  110  and the electronic device  120 , between the electronic device  120  and the peripheral device  140  or between the host device  110  and the peripheral device  140  according to a pre-determined value. The invention does not limit the generation of the pre-determined value. In one embodiment, the pre-determined value is set by a user. For example, the connection device  130  includes a mechanical switch or a digital switch. The user adjusts the state of the mechanical switch or the digital switch to set the pre-determined value. In another embodiment, the pre-determined value is pre-determined by a designer and stored in the connection device  130 . 
       FIG. 2A  is a schematic diagram of an exemplary embodiment of a control chip, in accordance with some embodiments. Refer to  FIGS. 1A and 2A , the control chip  134 A includes various pins. The pins IN 1 , IN 2 , VOUT and GND are power pins to receive operation power. The pins IN 1 , IN 2  and VOUT receive high operation power and the pin GND receives low operation power. The pins TDP, TDM, DP 1 , DM 1 , DP 2  and DM 2  are data pins to transmit data. The GPIO is an input/output pin. In this embodiment, the pins IN 1 , GND, TDP and TDM are referred to as first pins to couple the connection port  131 . The pins IN 2 , GND, DP 1 , DM 1  and GPIO are referred to as second pins to couple to the connection port  132 . The pins VOUT, GND, DP 2  and DM 2  are referred to as third pins to couple to the connection port  133 . In one embodiment, the pin GND is a common pin for the connection ports  131 ˜ 133 . 
     As shown in  FIG. 2A , the control chip  134 A further includes a level detection unit  210 , a control unit  220  and a determining unit  230 . The level detection unit  210  detects the levels of the first and second pins to generate a detection result S D1 . In this embodiment, the level detection unit  210  determines whether the host device  110  is coupled to the connection port  131  and the electronic device  120  is coupled to the connection port  132  according to the levels of the pins IN 1  and IN 2 . The invention does not limit the circuit structure of the level detection unit  210 . Any structure can serve as the level detection unit  210 , as long as the structure is capable of detecting levels. 
     The determining unit  230  determines whether the second pins transmit data. In this embodiment, the determining unit  230  determines whether the pins DP 1  and DM 1  transmit data according to the levels of the pins DP 1  and DM to generate a determination result S D2 . The invention does not limit the circuit structure of the determining unit  230 . Any circuit structure can serve as the determining unit  230 , as long as the circuit structure is capable of determining the changes of the levels of the pins. In one embodiment, the determining unit  230  is a level detector. 
     The control unit  220  adjusts the level of a specific pin of the second pins according to the detection result S D1  and the determination result S D2  to control the operation mode of the electronic device  120 . In this embodiment, the control unit  220  adjusts the level of the pin GPIO. Since the pin GPIO is coupled to the identification pin of the connection port  132 , the control unit  220  adjusts the level of the pin GPIO to control the level of the identification pin of the connection port  132 . For example, when the level of the identification pin of the connection port  132  is at the high level, the electronic device  120  operates in a device mode and is controlled by the host device  110 . When the level of the identification pin of the connection port  132  is at the low level, the electronic device  120  operates in a host mode and controls the peripheral device  140 . 
     In another embodiment, the control unit  220  is coupled to at least one of the pins IN 1  and IN 2  and operates according to the power on the pins IN 1  and IN 2 . For example, when the host device  110  is coupled to the connection port  131 , the control unit  220  receives power provided from the host device  110  via the pin IN 1 . When the electronic device  120  is coupled to the connection port  132 , the control unit  220  receives the power provided from the electronic device  120  via the pin IN 2 . In some embodiments, the operation power of the control unit  220  is provided by other circuits. 
     The invention does not limit the internal structure of the control unit  220 . In one embodiment, the control unit  220  includes at least one of the micro-processors, micro-controllers, memories and logic circuits. In this embodiment, the control unit  220  includes controllers  221  and  222  to generate control signals with an analog format and a digital format. The controller  221  receives the power provided from the pins IN 1  and IN 2  and generates the control signal S C1  according to the detection result S D1 . The controller  222  receives the power provided by the pins IN 1  and IN 2  and generates the control signal S C2  according to the detection result S D1  and the determination result S D2 . In other embodiments, the control unit  220  only includes a single controller to generate control signals with an analog format or a digital format. 
     As shown in  FIG. 2A , the control chip  134 A further includes switch units  240  and  250  to transmit power and data. The switch unit  240  includes power transmittal paths  241 ˜ 243 . The switch unit  240  turns on one of the power transmittal paths  241 ˜ 243  according to the control signal S C1 . The power transmittal path  241  is coupled between the pins IN 1  and IN 2 . The power transmittal path  242  is coupled between the pins IN 1  and VOUT. The power transmittal path  243  is coupled between the pins IN 2  and VOUT. The switch unit  250  includes data transmittal paths  251 ˜ 253 . The switch unit  250  turns on one of the data transmittal paths  251 ˜ 253  according to the control signal S C2 . The data transmittal path  251  is coupled to the pins TDP, TDM, DP 1  and DM 1 . The data transmittal path  252  is coupled to the pins TDP, TDM, DP 2  and DM 2 . The data transmittal path  253  is coupled to the pins DP 1 , DM 1 , DP 2  and DM 2 . The control unit  220  generates the control signals S C1  and S C2  according to the detection result S D1  and the determination result S D2  to transmit data and power between the host device  110 , the electronic device  120  and the peripheral device  140 . 
     In one embodiment, when the level of the pin IN 1  is higher than a pre-determined value, it means that the host device  110  is coupled to the connection port  131 . At this time, if the level of the pin IN 2  is higher than the pre-determined value or the pins DP 1  and DM 1  transmit data, it means that the electronic device  120  is coupled to the connection port  132 . Therefore, the control unit  220  sets the level of the pin GPIO to a first level such that the electronic device  120  operates in a device mode and the control unit  220  enters a first operation mode. In the first operation mode, the control unit  220  turns on the paths  241  and  251 . Therefore, the host device  110  charges the electronic device  120  via the path  241  and transmits data to the electronic device  120  via the path  251 . 
     In a condition that the level of the pin IN 1  is higher than the pre-determined value, when the level of the pin IN 2  is not higher than the pre-determined value or when the pins DP 1  and DM 1  do not transmit data, it means that the host device  110  is coupled to the connection port  131  and the electronic device  120  is not coupled to the connection port  132 . Therefore, the control unit  220  does not set the level of the pin GPIO. The level of the pin GPIO may be any level, such as a high level or a low level. At this time, the control unit  220  enters a second operation mode. In the second operation mode, the paths  242  and  252  are turned on. Therefore, when the peripheral device  140  is coupled to the connection port  133 , the host device  110  can charge the peripheral device  140  via the path  242  and transmit data to the peripheral device  140  via the path  252 . 
     When the level of the pin IN 1  is not higher than the pre-determined value, if the level of the pin IN 2  is higher than the pre-determined value or the pins DP 1  and DM 1  transmit data, it means the host device  110  is not coupled to the connection port  131  and the electronic device  120  is coupled to the connection port  132 . Therefore, the control unit  220  sets the level of the pin GPIO to a second level such that the electronic device  120  enters a host mode. At this time, the control unit  220  enters a third operation mode. In one embodiment, the second level is lower than the first level. For example, the first level is a high level and the second level is a low level. In the third operation mode, the paths  243  and  253  are turned on. Therefore, when the peripheral device  140  is coupled to the connection port  133 , the electronic device  120  charges the peripheral device  140  via the path  243  and transmits data to the peripheral device  140  via the path  253 . 
     In other embodiments, during an initial period, the control unit  220  utilizes the control signals S C1  and S C2  to turn off the paths  241 ˜ 243  and  251 ˜ 253 . After a period of time, all elements and signals are stable. At this time, the control unit  220  generates the corresponding control signals S C1  and S C2 , according to the detection result S D1  and the determination result S D2 . Additionally, the control unit  220  sets the level of the pin GPIO to a low level in the initial period. 
       FIG. 2B  is a schematic diagram of an exemplary embodiment of a control chip, in accordance with some embodiments.  FIG. 2B  is similar to  FIG. 2A  with the exception that the control chip  134 B further includes a charge pump  260 , a temperature-detection unit  270 , and current-detection units  280 A and  290 A. In this embodiment, the switch unit  240  includes transistors SW 1  and SW 2 . To control the transistors SW 1  and SW 2 , the control unit  220  generates control signals S C1  and S C3  and provides the control signals S C1  and S C3  to the charge pump  260 . The charge pump  260  enhances the driving capacity of the control signals S C1  and S C3  and the enhanced signals are referred to as the driving signals S P1  and S P2 . The driving signals S P1  and S P2  turn on the transistors SW 1  and SW 2 , respectively. When the transistor SW 1  is turned on and the transistor SW 2  is turned off, the host device  110  charges the electronic device  120 . When the transistors SW 1  and SW 2  are turned on, the host device  110  charges the peripheral device  140 . When the transistor SW 2  is turned on and the transistor SW 1  is turned off, the electronic device  120  charges the peripheral device  140 . In some embodiments, when the transistors SW 1  and SW 2  are replaced with P-type transistors, the charge pump  260  can be omitted. In this case, the control signals S C1  and S C2  generated by the control unit  220  can directly drive the P-type transistors. 
     The temperature-detection unit  270  generates a detection result S D3  according to the internal temperature of the control chip  134 B. The current-detection unit  280 A detects the current of the path  241  to generate a detection result S D4 . The current-detection unit  290 A detects the current of the path  243  to generate a detection result S D5 . The control unit  220  generates the control signals S C1  and S C2  according to the detection results S D1 , S D3 ˜S D5  and the determination result S D2 . For example, when the internal temperature of the control chip  134 B is too high or the current of the path  241  or  243  is too large, the control unit  220  stops transmitting power and data between the host device  110 , the electronic device  120  and the peripheral device  140  to ensure the safety of the control chip  134 B. 
     In this embodiment, the switch unit  250  includes switches SW 3 ˜SW 5 . The switches SW 3 ˜SW 5  are configured to turn on the paths  251 ˜ 253  according to the control signals S C2 , S C4  and S C5 . When the switch SW 4  is turned on, the host device  110  communicates with the electronic device  120  via the path  251 . When the switch SW 3  is turned on, the host device  110  communicates with the peripheral device  140  via the path  252 . When the switch SW 5  is turned on, the electronic device  120  communicates with the peripheral device  140  via the path  253 . 
       FIG. 2C  is a schematic diagram of another exemplary embodiment of a control chip, in accordance with some embodiments.  FIG. 2C  is similar to  FIG. 2B  with the exception that the positions of the current-detection units  280 B and  290 B shown in  FIG. 2C  are different from the positions of the current-detection units  280 A and  290 A shown in  FIG. 2B . 
       FIGS. 3A-3C  are flowcharts of an exemplary embodiment of a control method, in accordance with some embodiments. The control method  300  can be applied in a connection device including a first connection port, a second connection port and a third connection port. The first connection port is coupled to a host device. The second connection port is coupled to an electronic device. The third connection port is coupled to the peripheral device. For clarity, the transmittal system  100  is taken as an example. 
     Refer to  FIGS. 1, 3A-3C , the level of the identification pin of the connection port  132  is set to a low level (step  310 ). If the electronic device  120  has an OTG function, when the level of the identification pin is at the low level, the electronic device  120  enters a host mode. In another embodiment, step  310  can be omitted. 
     Next, the power pins of the connection ports  131  and  132  are detected and it is determined whether the connection port  132  transmits data (step  320 ). In one embodiment, when the host device  110  is coupled to the connection port  131  and the electronic device  120  with the OTG function is coupled to the connection port  132 , the levels of the power pins of the connection ports  131  and  132  exceed a pre-determined value. Therefore, the connection status of the connection ports  131  and  132  are obtained according to the detection of the connection ports  131  and  132 . However, when the electronic device  120  does not have the OTG function, the detection of the levels of the power pins of the connection port  132  cannot to determine whether the electronic device  120  is coupled to the connection port  132 . Therefore, in another embodiment, the data transmittal of the connection port  132  is detected to determine whether the electronic device  120  is coupled to the connection port  132 . For example, when the electronic device  120  is coupled to the connection port  132 , the levels of the data pins of the connection port  132  are changed. When the electronic device  120  is not coupled to the connection port  132 , the levels of the data pins of the connection port  132  are not changed. 
     The level of the identification pin of the connection port  132  is adjusted and an operation mode is selected according to the detection result and the determination result (step  330 ). Then, power and data between the connection ports  131 ˜ 133  are stopped (step  340 ). In one embodiment, the stop time is approximately 500 ms. Step  340  can be omitted. 
     In a condition that the level of the power pin of the connection port  131  is higher than a pre-determined value, when the level of the power pin of the connection port  132  is higher than the pre-determined value or when data pins of the connection port  132  transmit data, it means that the host device  110  is coupled to the connection port  131  and the electronic device  120  is coupled to the connection port  132 . Therefore, a first operation mode is entered (step  350 ). In the first operation mode, the level of the identification pin of the connection port  132  is set to a first level such that the electronic device  120  enters a device mode and is controlled by the host device  110 . In this embodiment, the host device  110  provides power to the electronic device  120  and communicates with the electronic device  120 . 
     Next, the level of the power pin of the connection port  131  is detected (step  352 ) and it is determined whether the connection port  132  transmits data (step  351 ). If the level of the power pin of the connection port  131  is still higher than the pre-determined value, step  350  is executed and the first operation mode is activated. Similarly, if the connection port  132  still transmits data, step  350  is executed such that the electronic device  120  operates in the device mode. The invention does not limit the sequence of steps  351  and  352 . Step  351  may be before or after step  352 . In another embodiment, steps  351  and  352  are executed simultaneously. 
     When the level of the power pin of the connection port  131  is not higher than the pre-determined value, it means that the host device  110  is not coupled to the connection port  131 . Therefore, step  310  is executed to set the level of the identification pin of the connection port  132  to the low level and the levels of the power pins of the connection ports  131  and  132  are detected again. When the connection port  132  does not transmit data, it means that the electronic device  120  is not coupled to the connection port  132 . Therefore, step  330  is executed to again select the operation mode according to the connection statuses of the connection ports  131 ˜ 132 . 
     In another embodiment, the priority of step  352  is higher than the priority of step  351 . Therefore, while executing step  351 , if the level of the power pin of the connection port  131  is not higher than the pre-determined value, step  310  is executed and step  351  is not continuously executed. 
     In a condition that the level of the power pin of the connection port  131  is higher than the pre-determined value, when the level of the power pin of the connection port  132  is not higher than the pre-determined value or when the data pins of the connection port  132  do not transmit data, it means that the host device  110  is coupled to the connection port  131  and the electronic device  120  is not coupled to the connection port  132 . Therefore, a second operation mode is entered (step  360 ). In the second operation mode, since the electronic device  120  is not coupled to the connection port  132 , the level of the identification pin of the connection port  132  can not be controlled. The level of the identification pin of the connection port  132  may be any level, such as the first level or the second level. In the second operation mode, when the peripheral device  140  is coupled to the connection port  133 , the host device  110  provides power to the peripheral device  140  and communicates with the peripheral device  140 . 
     In the second operation mode, it is determined whether the connection port  132  transmits data (step  361 ) and the level of the power pin of the connection port  131  is detected to determine whether the level of the power pin of the connection port  131  is still higher than the pre-determined value (step  362 ). When the connection port  132  does not transmit data, it means the electronic device  120  is not coupled to the connection port  132 . Therefore, step  360  is executed to operate in the second operation mode. Furthermore, when the level of the power pin of the connection port  131  is higher than the pre-determined value, step  360  is executed. When the connection port  132  transmits data, it means that the electronic device  120  is coupled to the connection port  132 . Therefore, step  330  is executed to select the operation mode according to the connection statuses of the connection ports  131 ˜ 132 . When the level of the power pin of the connection port  131  is not higher than the pre-determined value, it means that the host device  110  is not coupled to the connection port  131 . Therefore, step  310  is executed to reset the level of the identification pin of the connection port  132  into the low level and again detect the levels of the power pins of the connection ports  131  and  132 . The invention does not limit the sequence of steps  361  and  362 . Step  361  may be before or after step  362 . In another embodiment, steps  361  and  362  are executed simultaneously. 
     When the level of the power pin of the connection port  131  is not higher than the pre-determined value, if the level of the power pin of the connection port  132  is higher than the pre-determined value or the connection port  132  transmits data, it means that the host device  110  is not coupled to the connection port  131  and the electronic device  120  is coupled to the connection port  132 . Therefore, a third operation mode is entered (step  370 ). During the third operation mode, the level of the identification pin of the connection port  132  is set to the low level, and the electronic device  120  enters a host mode. At this time, if the peripheral device  140  is coupled to the connection port  133 , the electronic device  120  provides power to the peripheral device  140  and communicates with the peripheral device  140 . 
     Next, the level of the power pin of the connection port  131  is detected to determine whether the level of the power pin of the connection port  131  is higher than the pre-determined value (step  371 ) and it is determined whether the connection port  132  transmits data (step  372 ). When the level of the power pin of the connection port  131  is not higher than the pre-determined value or the connection port  132  transmits data, step  370  is executed. When the level of the power pin of the connection port  131  is higher than the pre-determined value, it means that the host device  110  is coupled to the connection port  131 . Therefore, step  320  is executed to detect the levels of the connection ports  131  and  132  and determine whether the connection port  132  transmits data again. If the connection port  132  does not transmit data, it means that the electronic device  120  is not coupled to the connection port  132 . Therefore, step  330  is executed to select the operation mode according to the connection statuses of the connection ports  131  and  132 . The invention does not limit the sequence of steps  371  and  372 . Step  371  may be before or after step  372 . In another embodiment, steps  371  and  372  are executed simultaneously. 
       FIGS. 4A-4C  are schematic diagrams of an exemplary embodiment of a control method, in accordance with some embodiments.  FIGS. 4A-4C  are similar to  FIGS. 3A-3C  except for the first operation mode. Refer to  FIGS. 4A-4C , in the first operation mode, when the connection port  132  does not transmit data, the level of the power pin of the connection port  131  is detected to determine whether the level is higher than the pre-determined value (step  453 ). When the level of the power pin of the connection port  131  is higher than the pre-determined value, step  430  is executed. When the level of the power pin of the connection port  131  is not higher than the pre-determined value, step  410  is executed. Since other steps in  FIGS. 4A-4C  are the same as steps in  FIGS. 3A-3C , the descriptions of other steps in  FIGS. 4A-4C  are omitted. 
     The connection statuses of the connection ports  131 - 132  are obtained according to the levels of the pins of the connection ports  131 - 132 . The corresponding paths are turned on according to the obtained result to communicate with two devices, such as the host device  110  and the electronic device  120 , the host device  110  and the peripheral device  140  or the electronic device  120  and the peripheral device  140 . Therefore, the convenience of the transmittal system is increased. 
     In addition, when the host device  110  is coupled to the connection port  131 , the electronic device  120  is coupled to the connection port  132  and the peripheral device  140  is coupled to the connection port  133 , a pre-determined parameter is retrieved and power and data are transmitted between the host device  110  and the electronic device  120 , between the host device  110  and the peripheral device  140  or between the electronic device  120  and the peripheral device  140  according to the pre-determined parameter. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     While the invention has been described by way of example and in terms of the preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.