Patent Publication Number: US-10326424-B2

Title: Filter device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application claims the benefit of priority to Japanese Patent Application No. 2015-232048 filed on Nov. 27, 2015 and is a Continuation Application of PCT Application No. PCT/JP2016/070788 filed on Jul. 14, 2016. The entire contents of each application are hereby incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to filter devices in which a bandpass filter chip is mounted on a multilayer substrate. 
     2. Description of the Related Art 
     For bandpass filters, it is desirable to have greater attenuation outside their passbands. International Publication No. WO2008/146552 discloses a filter device in which a reception side elastic wave filter chip and a transmission side elastic wave filter chip are mounted on a substrate. In International Publication No. WO2008/146552, at least one of the reception side elastic wave filter chip and the transmission side elastic wave filter chip is a balanced filter. In this balanced filter, first wiring connecting one of balanced terminals of the balanced filter and a first balance terminal formed on the substrate crosses second wiring connecting the other of the balanced terminals and a second balance terminal formed on the substrate in a state where the first wiring and the second wiring are electrically insulated from each other. 
     International Publication No. WO2008/146552 describes that the filter device has a greater out-of-band attenuation in the balanced filter and is able to improve isolation since the first wiring crosses the second wiring in a state in which the first wiring and the second wiring are insulated from each other. 
     However, even in the configuration described in International Publication No. WO2008/146552, the expansion of the out-of-band attenuation in the balanced filter is not enough. 
     SUMMARY OF THE INVENTION 
     Preferred embodiments of the present invention provide filter devices with an expanded out-of-band attenuation. 
     A filter device according to a preferred embodiment of the present invention includes a multilayer substrate including a plurality of substrate layers, a first principal surface, and a second principal surface facing the first principal surface; a first bandpass filter chip mounted on the first principal surface of the multilayer substrate and including a first balanced output terminal and a second balanced output terminal, the first bandpass filter chip defining a first balanced bandpass filter; a first balanced input pad and a second balanced input pad provided on the first principal surface of the multilayer substrate and connected to the first balanced output terminal and the second balanced output terminal of the first bandpass filter chip, respectively; a first balanced output pad and a second balanced output pad provided on the second principal surface of the multilayer substrate for external electrical connection; a first balance wiring provided inside the multilayer substrate and electrically connecting the first balanced input pad and the first balanced output pad; and a second balance wiring provided inside the multilayer substrate and electrically connecting the second balanced input pad and the second balanced output pad, wherein the first balance wiring and the second balance wiring cross each other within the multilayer substrate in a state in which the first balance wiring and the second balance wiring are electrically insulated from each other, and when the multilayer substrate is viewed from a first principal surface side, in plan view, a first ground pattern is included at a region in which the first balance wiring overlaps the second balance wiring, and the first ground pattern is interposed between a portion of the first balance wiring and a portion of the second balance wiring disposed in a different substrate layer. 
     In a filter device according to a preferred embodiment of the present invention, a second ground pattern is disposed between a portion of the first balance wiring and a portion of the second balance wiring, and the portion of the first balance wiring and the portion of the second balance wiring are provided next to each other within a same plane of the multilayer substrate. In this case, the out-of-band attenuation is further expanded. 
     In a filter device according to a preferred embodiment of the present invention, of the plurality of substrate layers of the multilayer substrate, the second ground pattern is provided on a substrate layer closest to the second principal surface. In this case, the out-of-band attenuation is further expanded. 
     In a filter device according to a preferred embodiment of the present invention, a plurality of via conductors are further included, wherein a plurality of ground terminals is provided on the second principal surface of the multilayer substrate, and the plurality of via conductors connect the plurality of ground terminals and the second ground pattern. In this case, the ground is reinforced, and the out-of-band attenuation is further increased. 
     In a filter device according to a preferred embodiment of the present invention, when the multilayer substrate is viewed from the first principal surface, in plan view, a spatial relationship between the first balanced input pad and the second balanced input pad is opposite to a spatial relationship between the first balanced output pad and the second balanced output pad. In this case, the out-of-band attenuation is further expanded while ensuring flexibility in wiring length design within a constrained space. 
     In a filter device according to a preferred embodiment of the present invention, a second bandpass filter chip mounted on the first principal surface of the multilayer substrate and defining a second bandpass filter is further included, thus defining a duplexer. 
     In a filter device according to a preferred embodiment of the present invention, the second bandpass filter chip is unified with the first bandpass filter. In this case, the number of components is reduced, and the size of filter device is reduced. 
     In a filter device according to a preferred embodiment of the present invention, at least one ground pattern is used in common at the first bandpass filter and the second bandpass filter. In this case, the ground is reinforced, and the out-of-band attenuation is further expanded. 
     In a filter device according to a preferred embodiment of the present invention, the first bandpass filter is a reception filter, and the second bandpass filter is a transmission filter. In this case, the out-of-band attenuation of the reception filter is expanded, and isolation characteristics thereof is effectively improved. 
     With filter devices according to preferred embodiments of the present invention, the out-of-band attenuation is able to be further expanded. 
     The above and other elements, features, steps, characteristics and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram of a filter device according to a first preferred embodiment of the present invention. 
         FIGS. 2A and 2B  are a schematic plan view and a schematic front view of a filter device according to the first preferred embodiment of the present invention, respectively. 
         FIGS. 3A to 3C  are plan views illustrating an electrode structure on a first principal surface, an electrode structure on a top surface of a fourth substrate layer, and an electrode structure on a top surface of a third substrate layer in a filter device according to the first preferred embodiment of the present invention, respectively. 
         FIGS. 4A to 4C  are plan views illustrating an electrode structure on a top surface of a second substrate layer, an electrode structure on a top surface of a first substrate layer, and an electrode structure on a second principal surface, respectively. 
         FIG. 5  is a frontal cross-sectional diagram of a multilayer substrate provided in a filter device according to the first preferred embodiment of the present invention, and is a cross-sectional diagram of a portion corresponding to a portion along lines B-B in  FIGS. 3A to 3C . 
         FIG. 6  is a frontal cross-sectional diagram illustrating an example of a specific structure of a filter chip provided in the first preferred embodiment of the present invention. 
         FIG. 7  is a diagram illustrating attenuation-frequency characteristics and isolation characteristics of filter devices according to a preferred embodiment of the present invention and a comparison example. 
         FIG. 8  is a diagram extracting only the isolation characteristics illustrated in  FIG. 7 . 
         FIG. 9  is a diagram in which an isolation scale factor in a vertical axis of  FIG. 8  is expanded. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Hereinafter, the present invention is disclosed in detail by describing specific preferred embodiments of the present invention with reference to the drawings. 
     It is noted that each preferred embodiment described in this specification is for illustrative purposes only, and elements of different preferred embodiments may be combined or partially exchanged. 
       FIG. 1  is a circuit diagram of a filter device according to a first preferred embodiment of the present invention.  FIGS. 2A and 2B  are a schematic plan view and a schematic front view of the filter device according to the first preferred embodiment, respectively. 
     A filter device  1  according to the first preferred embodiment is preferably a duplexer, for example. The filter device  1  includes a multilayer substrate  2 . As illustrated in  FIGS. 2A and 2B , a filter chip  3  is mounted on the multilayer substrate  2 . In the present preferred embodiment, a reception filter chip portion  3 A and a transmission filter chip portion  3 B are unified in the filter chip  3 . Alternatively, the reception filter chip portion  3 A and the transmission filter chip portion  3 B may each be defined by an independent chip component. 
     Note that the reception filter chip portion  3 A is preferably a reception filter that defines and functions as a first bandpass filter in the present preferred embodiment. Furthermore, the transmission filter chip portion  3 B is preferably a transmission filter that defines and functions as a second bandpass filter. 
       FIG. 1  illustrates a circuit configuration inside the filter chip  3 , which is a section surrounded by the dashed-dotted line. Inside the filter chip  3  surrounded by the dashed-dotted line, the reception filter chip portion  3 A and the transmission filter chip portion  3 B are provided. 
     In the reception filter chip portion  3 A, first and second longitudinally coupled resonator surface acoustic wave filters  11  and  12  are connected to a common terminal  5  with one-port surface acoustic wave resonators  9  and  10  respectively interposed therebetween. Although schematically illustrated in  FIG. 1 , the first and second longitudinally coupled resonator surface acoustic wave filters  11  and  12  are preferably a three interdigital transducer (IDT) longitudinally coupled resonator surface acoustic wave filter, for example. In other words, the first longitudinally coupled resonator surface acoustic wave filter  11  includes a first IDT  11   a  provided at a center, and a second IDT  11   b  and a third IDT  11   c  provided at both sides of the first IDT  11   a  in a propagation direction of a surface acoustic wave. Similarly, the second longitudinally coupled resonator surface acoustic wave filter  12  includes a first IDT  12   a , a second IDT  12   b , and a third IDT  12   c.    
     One end portion of the first IDT  11   a  of the first longitudinally coupled resonator surface acoustic wave filter  11  and one end portion of the first IDT  12   a  of the second longitudinally coupled resonator surface acoustic wave filter  12  are connected in common to the common terminal  5  with the one-port surface acoustic wave resonators  9  and  10  interposed therebetween, respectively. The other end portions of the first IDT  11   a  and the first IDT  12   a  are connected to a ground potential. 
     End portions of the second IDT  11   b  and the third IDT  11   c  of the first longitudinally coupled resonator surface acoustic wave filter  11  are each connected to the ground potential, and the other end portions of the second IDT  11   b  and the third IDT  11   c  are respectively connected to end portions of a second IDT  13   b  and a third IDT  13   c  of a third three-IDT longitudinally coupled resonator surface acoustic wave filter  13 . The other end portions of the second IDT  13   b  and the third IDT  13   c  are connected to the ground potential. 
     Similarly, the second longitudinally coupled resonator elastic wave filter  12  is connected to and followed by a fourth three-IDT longitudinally coupled resonator surface acoustic wave filter  14 . In other words, end portions of the second IDT  12   b  and the third IDT  12   c  are each connected to the ground potential, and the other end portions of the second IDT  12   b  and the third IDT  12   c  are electrically connected to end portions of a second IDT  14   b  and a third IDT  14   c , respectively. The other end portions of the second IDT  14   b  and the third IDT  14   c  are connected to the ground potential. 
     One end portion of a first IDT  13   a  and one end portion of a first IDT  14   a  are connected in common to a first balanced terminal  17 . The other end portion of the first IDT  13   a  and the other end portion of the first IDT  14   a  are also connected in common to a second balanced terminal  18 . 
     Inside the multilayer substrate  2 , a first balance wiring  15  and a second balance wiring  16  are provided. 
     The first balanced terminal  17  is electrically connected to a first balanced input pad  7 A provided on the multilayer substrate  2 . The second balanced terminal  18  is connected to a second balanced input pad  8 A provided on the multilayer substrate  2 . 
     As illustrated in  FIG. 2B , the multilayer substrate  2  includes a first principal surface  2   a  and a second principal surface  2   b  facing the first principal surface  2   a . As illustrated in  FIGS. 2A and 2B , the filter chip  3  is mounted on the first principal surface  2   a . The first balanced input pad  7 A and the second balanced input pad  8 A described above are provided on the first principal surface  2   a . Inside the multilayer substrate  2 , the first balance wiring  15  and the second balance wiring  16  are provided. Furthermore, the first balanced output pad  7 B and the second balanced output pad  8 B illustrated in  FIG. 1  are provided on the second principal surface  2   b  of the multilayer substrate  2 . The first balance wiring  15  electrically connects the first balanced input pad  7 A and the first balanced output pad  7 B. The second balance wiring  16  electrically connects the second balanced input pad  8 A and the second balanced output pad  8 B. The first balance wiring  15  crosses the second balance wiring  16  within the multilayer substrate  2  in a state in which the first balance wiring  15  and the second balance wiring  16  are electrically insulated from each other. This configuration is now described with reference to  FIGS. 3A to 3C ,  FIGS. 4A to 4C , and  FIG. 5 . 
     The multilayer substrate  2  is preferably a multilayer body including five substrate layers, for example.  FIG. 3A  is a plan view illustrating an electrode structure on the first principal surface  2   a  of the multilayer substrate  2 .  FIG. 4C  is a plan view illustrating a transparent view of an electrode structure on the second principal surface  2   b  of the multilayer substrate  2 . Electrode structures illustrated in  FIGS. 3B, 3C  and  FIGS. 4A and 4B  are provided on interfaces of respective substrate layers arranged between the first principal surface  2   a  and the second principal surface  2   b .  FIG. 4B  illustrates an electrode structure on a first substrate layer  2   c , and  FIG. 4A  illustrates an electrode structure on a second substrate layer  2   d .  FIG. 3C  illustrates an electrode structure on a third substrate layer  2   e , and  FIG. 3B  illustrates an electrode structure on a fourth substrate layer  2   f .  FIG. 5  is a cross-sectional diagram of the multilayer substrate  2  at a portion corresponding to portions along lines B-B in  FIGS. 3A to 3C . As illustrated in  FIG. 5 , the first to the fourth substrate layers  2   c ,  2   d ,  2   e , and  2   f  are stacked in this order from the second principal surface  2   b  side toward the first principal surface  2   a  side. 
     On the first principal surface  2   a  of the multilayer substrate  2 , an antenna pad  5 A, the first balanced input pad  7 A, the second balanced input pad  8 A, and ground pads  21   a  to  21   c  to be connected to the ground potential are provided. Furthermore, at the portion at which the transmission filter chip portion  3 B is mounted, a transmission pad  6 A and ground pads  22   a  to  22   c  are provided. 
     In  FIGS. 3A to 3C  and  FIGS. 4A to 4C , the portions defining the first balance wiring  15  include a conductive film  15   a  of  FIG. 3B , a conductive film  15   b  of  FIG. 3C , a conductive film  15   c  of  FIG. 4A , a conductive film  15   d  of  FIG. 4B , the first balanced output pad  7 B, and via conductors connecting therebetween. Note that, in  FIGS. 3A to 4B , the dashed line illustrates locations of the via conductors connected to bottom surfaces of the conductive films. In  FIG. 4C , the dashed-dotted line illustrates locations of the via conductors connected to top surfaces of the conductive films, such as the balanced output pad  7 B, for example. 
     The second balance wiring  16  connects the second balanced input pad  8 A of  FIG. 3A  and the second balanced output pad  8 B of  FIG. 4C . Specifically, a conductive film  16   a  illustrated in  FIG. 3B , a conductive film  16   b  illustrated in  FIG. 3C , a conductive film  16   c  illustrated in  FIG. 4A , a conductive film  16   d  illustrated in  FIG. 4B , and via conductors connecting therebetween are included. Furthermore, the second balance wiring  16  includes a via conductor connecting the second balanced input pad  8 A and the conductive film  16   a  and a via conductor connecting the conductive film  16   d  and the second balanced output terminal  8 B. 
       FIGS. 3A to 4C  clearly illustrate that, when the first balance wiring  15  and the second balance wiring  16  are viewed from the first principal surface  2   a  side, in plan view, the first balance wiring  15  and the second balance wiring  16  cross over each other in a state in which the first balance wiring  15  and the second balance wiring  16  are electrically insulated from each other. 
     On the other hand, in the multilayer substrate  2 , the ground pads  21   a  to  21   c  and  22   a  to  22   c  are electrically connected to ground pads  23   a  to  23   d  provided on the second principal surface  2   b  with via conductors interposed therebetween, which are provided inside the multilayer substrate  2 . For example, as illustrated in  FIG. 5 , the ground pad  21   a  is electrically connected to a ground conductor  24   b  provided on the fourth substrate layer  2   f  with a via conductor  24   a  interposed therebetween. As illustrated in  FIG. 5 , the ground conductor  24   b  is electrically connected to a ground conductor  24   f  with a via conductor  24   c , a ground conductor  24   d , and a via conductor  24   e  interposed therebetween. The ground conductor  24   f  is connected to a ground conductor  24   g  provided on the first substrate layer  2   c  with a via conductor interposed therebetween, which is not illustrated in  FIG. 5 . The ground conductor  24   g  is connected to the ground pad  23   d  with a plurality of via conductors  24   h  interposed therebetween. Furthermore, the ground conductor  24   g  is also electrically connected to the ground pad  23   c  with a via conductor  24   i  interposed therebetween. 
     In the present preferred embodiment, the first balance wiring  15  and the second balance wiring  16  cross each other within the multilayer substrate  2  such that the first balance wiring  15  and the second balance wiring  16  are electrically insulated from each other and, when the multilayer substrate  2  is viewed from the first principal surface  2   a  side, at a region in which the first balance wiring  15  overlaps the second balance wiring  16  in plan view, the ground conductor  24   f  defining a first ground pattern is interposed between a portion of the first balance wiring  15  and a portion of the second balance wiring  16  disposed in a different layer. In other words, as clearly illustrated in  FIGS. 3A to 4C , when the portion in which the first balance wiring  15  and the second balance wiring  16  cross each other is viewed from the first principal surface  2   a  side, in plan view, the ground conductor  24   f  includes a flared portion  24   f   1 . The flared portion  24   f   1  is provided between the conductive film  15   d  that is a portion of the first balance wiring and the conductive film  16   b  that is a portion of the second balance wiring. In other word, the flared portion  24   f   1  is provided between the conductive film  15   d  on the first substrate layer  2   c  and the conductive film  16   b  provided on the third substrate layer  2   e , which is a different substrate layer. 
     Accordingly, in the filter device  1 , it is possible to expand the out-of-band attenuation at the reception filter, which will be described below. 
     In addition, as illustrated in  FIG. 4B , on the first substrate layer  2   c , the ground conductor  24   g  includes a protruded portion  24   g   1  that defines a second ground pattern. The protruded portion  24   g   1  is extended between the conductive film  15   d  and the conductive film  16   d . This reduces direct waves between the conductive film  15   d  and the conductive film  16   d , thus making it possible to further expand the out-of-band attenuation. 
     Furthermore, as illustrated in  FIGS. 4B, 4C , and  FIG. 5 , in the filter device  1 , the ground conductor  24   g  having a large area is provided on the interface between the substrate layers that are closest to the second principal surface  2   b , namely, on the top surface of the first substrate layer  2   c . The ground conductor  24   g  preferably extends below the reception filter chip portion  3 A and the transmission filter chip portion  3 B. In other words, the ground conductor  24   g  is used in common by the reception filter and the transmission filter. In addition, the ground conductor  24   g  having a large area is connected to the ground pad  23   d  with the plurality of via conductors  24   h  interposed therebetween. Thus, in the filter device  1 , it is possible to reinforce the ground potential, thus making it possible to expand the out-of-band attenuation. 
     Note that the height position inside the multilayer substrate  2  at which the first balance wiring  15  and the second balance wiring  16  cross each other is not limited to the position in the present preferred embodiment. Although the flared portion  24   f   1  is provided in the above, the first ground pattern extending between a portion of the first balance wiring and a portion of the second balance wiring may be similarly provided in a different substrate layer. 
     Furthermore, the second ground pattern is not limited to the protruded portion  24   g   1  of the ground conductor  24   g . The second ground pattern having any appropriate shape may be provided between a portion of the first balance wiring and a portion of the second balance wiring that are placed next to each other at the same height position. Furthermore, a plurality of the second ground patterns may alternatively be provided. 
     Furthermore, the ground conductor having a large area may alternatively be provided on the top surface of the second substrate layer  2   d  or on any other location closer to the first principal surface  2   a . Most preferably, as in the present preferred embodiment, the ground conductor  24   g  having a large area is provided on the top surface of the first substrate layer  2   c . More preferably, this ground conductor  24   g  is connected to the ground pad  23   d  by the plurality of via conductors  24   h  as described above. 
     Returning to  FIG. 1 , other elements of the filter device  1  are now described. 
     The transmission filter is connected to the common terminal  5 . The transmission filter chip portion  3 B is preferably a surface acoustic wave filter having a ladder circuit configuration including three series arm resonators S 1  to S 3  and three parallel arm resonators P 1  to P 3 , for example. 
     The series arm resonators S 1  to S 3  and the parallel arm resonators P 1  to P 3  are each preferably defined by a one-port surface acoustic wave resonator. 
     The transmission filter chip portion  3 B is electrically connected to a transmission terminal  6 . A transmitting signal is input from the transmission terminal  6 . The transmitting signal is output to the common terminal  5  with the transmission filter chip portion  3 B interposed therebetween. 
     Preferably, the filter device  1  of the present preferred embodiment may be used as a duplexer for BAND  1 , and its transmission frequency band is from about 1920 MHz to about 1980 MHz and its reception frequency band is from about 2110 MHz to about 2170 MHz, for example. 
     In the filter device  1 , the multilayer substrate  2  includes a plurality of substrate layers  2   c  to  2   g  made of insulating material. The insulating material is not limited to any particular material, and any appropriate insulating ceramic, such as alumina and other insulating ceramic or a synthetic resin and other suitable material may be used. 
     The first and second balanced input pads, the first and second balanced output pads, the conductive films, the ground conductors, and the via conductors, which are described above, may be made of any appropriate metal or alloy. 
       FIG. 6  is a frontal cross-sectional diagram illustrating an example of a specific structure of the filter chip  3 . The filter chip  3  includes a piezoelectric substrate  31 . The piezoelectric substrate  31  includes a first principal surface  31   a  and a second principal surface  31   b  facing the first principal surface  31   a . Functional electrodes  32  including the IDT electrodes are provided on the first principal surface  31   a . The functional electrodes  32  face a cavity space, and define the reception filter chip portion  3 A. In the transmission filter chip portion  3 B, functional electrodes  33  facing another cavity space are provided. 
     A support layer  34  with an opening is provided and defines the cavity spaces to which the functional electrodes  32  and  33  face. A cover  35  closes the opening of the support layer  34 . 
     An electrode land corresponding to the first balanced terminal  17  is provided on the first principal surface  31   a  of the piezoelectric substrate  31 . The second balanced terminal  18  illustrated in  FIG. 1  is not illustrated in  FIG. 6 . 
     The first balanced terminal  17  is joined to a bump  37  with an under-bump metal layer  36  interposed therebetween, which passes through the support layer  34  and the cover  35 . This bump  37  is joined to the first balanced input pad  7 A. Similarly, the second balanced terminal is connected to the second balanced input pad  8 A provided on the first principal surface of the multilayer substrate  2  with an under-bump metal layer and a bump interposed therebetween. 
     Preferably, the first balance wiring  15  and the second balance wiring  16  are structured such that the wiring length from the first balanced terminal  17  on the first principal surface  31   a  of the piezoelectric substrate  31  to the first balanced output pad  7 B provided on the second principal surface  2   b  of the multilayer substrate  2  is equal or substantially equal to the wiring length from the second balanced terminal to the second balanced output pad. In this case, isolation is further improved. 
     Note that the filter chip  3  is not limited to a WLP (wafer level packaging) structure illustrated in  FIG. 6 , and may alternatively be a CSP (chip scale packaging) structure. Furthermore, although the reception filter chip portion  3 A and the transmission filter chip portion  3 B are unified in the present preferred embodiment, they may alternatively be provided as individual filter chips. 
     Furthermore, the number of substrate layers stacked on the multilayer substrate  2  is not limited to five layers, and may be any number. 
     In the present preferred embodiments, in the multilayer substrate  2 , the ground conductors  24   f  and  24   g  defining the ground patterns preferably are used in common at the transmission side and the reception side. However, the ground conductors  24   f  and  24   g  may not necessarily be used in common. 
     Next, a specific experimental example is described. 
     A filter chip  3  of the present preferred embodiment having the following specifications was prepared. 
     (1) Configuration of Multilayer Substrate 
     Substrate material: Glass epoxy. Thickness of multilayer substrate  2 =about 0.3 mm. Number of substrate layers=5. 
     (2) Configuration of Reception Filter Chip Part  3 A 
     Substrate material: LiTaO 3 . Thickness of piezoelectric substrate=about 0.2 mm. 
     (3) Configuration of Transmission Filter Chip Part  3 B 
     Substrate material: LiTaO 3 . Thickness of piezoelectric substrate=about 0.2 mm. 
     For comparison, a multilayer substrate  2  was similarly configured except not including the flared portion  24   f   1  and the protruded portion  24   g   1 , and on the multilayer substrate  2 , a filter chip including a transmission filter chip portion and a reception filter chip portion that are similar to those in the present preferred embodiment was mounted. In this manner, a filter device of the comparative example was prepared. 
       FIG. 7  is a diagram illustrating attenuation-frequency characteristics of filter devices of the present preferred embodiment and the comparative example. In  FIG. 7 , a transmission band representing the transmission frequency band is from about 1920 MHz to about 1980 MHz, and a reception band representing the reception frequency band is from about 2110 MHz to about 2170 MHz. The solid line represents a result of the present preferred embodiment, and the dashed line represents a result of the comparative example.  FIG. 7  also illustrates isolation characteristics. The solid line represents a result of the present preferred embodiment, and the dashed line represents a result of the comparative example. Only the isolation characteristics illustrated in  FIG. 7  are extracted and illustrated in  FIG. 8 , and an enlarged view in which the isolation scale factor in the vertical axis of  FIG. 8  is expanded is illustrated in  FIG. 9 . 
     As clearly illustrated in  FIG. 7 , the out-of-band attenuation of the reception filter increased in the present preferred embodiment, particularly at the transmission band, as compared to the comparative example. Accordingly, as illustrated in  FIG. 7  to  FIG. 9 , it was possible to effectively improve the isolation at the transmission band. In other words, it was discovered and confirmed that the present preferred embodiment improved the isolation considerably at the worst isolation portion of the transmission band as compared to the comparative example. 
     While preferred embodiments of the present invention have been described above, it is to be understood that variations and modifications will be apparent to those skilled in the art without departing from the scope and spirit of the present invention. The scope of the present invention, therefore, is to be determined solely by the following claims.