Patent Publication Number: US-2022239302-A1

Title: Hybrid analog-to-digital converter with inverter-based residue amplifier

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application is a continuation of U.S. patent application Ser. No. 17/146,056, filed on Jan. 11, 2021, which claims priority to U.S. Provisional Patent Application No. 62/981,668, filed on Feb. 26, 2020, each of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     An analog-to-digital converter (ADC) is a circuit element that converts an analog signal to digital data. For example, digital data can include a number of different digital codes, and each of the digital codes can correspond to a unique voltage or current level of the analog signal. Analog-to-digital converter (ADC) has various architectures, for example, flash analog-to-digital converters (flash ADC), pipeline analog-to-digital converters (pipeline ADC), and successive approximation register analog-to-digital converters (SAR ADC), all of which have their respective application fields. For example, flash ADC is typically the fastest in terms of number of samples per second, but has the highest implementation cost. SAR ADC has a much lower implementation cost, however, it is considerably slower than flash ADC. Moreover, the small input signal linearity of the SAR ADC is limited. As to the pipelined ADC, it does not benefit from the technology scaling because the use of low voltage supplies gives rise to an augmented consumption of power. In addition, existing pipelined ADC architectures use high gain traditional Class-A amplifiers, which are very difficult to implement in a FinFET process 
     Furthermore, the existing ADC architectures have a low signal to noise ratio (SNR) and a limited conversion bandwidth in low voltage deep sub-micron processes. In view of the deficiency of above analog-to-digital converters, there is a need to provide an ADC with advantage of high dynamic range SNR (SNDR) and large conversion bandwidth with low power consumption, while scalable to deep sub-micron process technologies. 
     The information disclosed in this Background section is intended only to provide context for various embodiments of the invention described below and, therefore, this Background section may include information that is not necessarily prior art information (i.e., information that is already known to a person of ordinary skill in the art). Thus, work of the presently named inventors, to the extent the work is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Various exemplary embodiments of the present disclosure are described in detail below with reference to the following Figures. The drawings are provided for purposes of illustration only and merely depict exemplary embodiments of the present disclosure to facilitate the reader&#39;s understanding of the present disclosure. Therefore, the drawings should not be considered limiting of the breadth, scope, or applicability of the present disclosure. It should be noted that for clarity and ease of illustration these drawings are not necessarily drawn to scale. 
         FIG. 1  illustrates an exemplary circuit diagram of a hybrid analog-to-digital converter (ADC), in accordance with some embodiments of the present disclosure. 
         FIG. 2  illustrates an exemplary circuit diagram of the hybrid ADC, in accordance with some embodiments of the present disclosure 
         FIG. 3  illustrates an exemplary timing diagrams of operational phases described in Table 1, in accordance with some embodiments of the present disclosure. 
         FIG. 3  illustrates timing signals for operational phases Φ 1 , Φ 2 , Φ 3 , and Φ 4 , in accordance with some embodiments. 
         FIG. 4  illustrates a schematic diagram of a residual digital-to-analog converter (RDAC), a residual amplifier (RA) circuit, and a successive approximation register (SAR) circuit coupled to the RA circuit, in accordance with some embodiments 
         FIG. 5  illustrates an exemplary circuit diagram of an amplifier within the RA circuit, in accordance with some embodiments. 
         FIG. 6  shows variations of a deadzone voltage across a resistor with respect to the six front end of line (FEOL) process corners at reference supply voltages 0.90 V and 0.75 V. 
         FIG. 7  illustrates an exemplary flow chart of a method performing a residue amplification with the amplifier that has an output stage is biased in a stable sub-threshold region, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Various exemplary embodiments of the present disclosure are described below with reference to the accompanying figures to enable a person of ordinary skill in the art to make and use the present disclosure. As would be apparent to those of ordinary skill in the art, after reading the present disclosure, various changes or modifications to the examples described herein can be made without departing from the scope of the present disclosure. Thus, the present disclosure is not limited to the exemplary embodiments and applications described and illustrated herein. Additionally, the specific order and/or hierarchy of steps in the methods disclosed herein are merely exemplary approaches. Based upon design preferences, the specific order or hierarchy of steps of the disclosed methods or processes can be re-arranged while remaining within the scope of the present disclosure. Thus, those of ordinary skill in the art will understand that the methods and techniques disclosed herein present various steps or acts in a sample order, and the present disclosure is not limited to the specific order or hierarchy presented unless expressly stated otherwise. 
       FIG. 1  illustrates an exemplary block diagram of a hybrid ADC  100  according to some embodiments. As shown in  FIG. 1 , the hybrid ADC  100  includes a first successive approximation register (SAR) circuit  102 , a residue amplifier (RA) circuit  104 , a second SAR circuit  106 , a digital error correction circuit  115 , and a control logic circuit  117 . In some embodiments, the RA circuit  104  may have a gain of 16. In other embodiments, the RA circuit  104  may have a gain of 32. Each of the blocks  102 ,  104 ,  106 ,  115 , and  117  may include one or more circuits that each performs a respective function, which will be discussed in further detail below. 
     In some embodiments, the hybrid ADC  100  converts an analog input signal (e.g., an analog voltage signal)  101  to a digital output signal  103  representative of the analog input signal  101  in a digital format. As such, the digital output signal  103  obtained based on a first digital signal  105  output by the first SAR circuit  102  and a second digital signal  107  output by the second SAR circuit  106 , may be output by the error correction circuit  115 . In some embodiments, the digital signal  107  may be a 9-bit digital code. Moreover, by using the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106  to perform respective functions of three sequential phases in a pipelined fashion, the digital signals  105  and  107  can be respectively generated. More specifically, the first SAR circuit  102  may be configured to implement a binary search algorithm to determine digital values of the first digital signal  105 . The digital values of the first digital signal  105  correspond to the analog input signal  101  for the plurality of most significant bits (MSB). In some embodiments, the digital signal  105  may be a 6-bit digital code. The first SAR circuit  102  is also configured to generate a residue voltage  109 . The residue voltage  109  corresponds to a difference in voltage value between the analog input voltage  101  and the first digital signal  105 . 
     As shown in  FIG. 1 , the error correction circuit  115  may be configured to combine the digital signals  105  and  107  to generate the digital output signal  103 . In some embodiments, the control logic circuit  117 , coupled to the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106 , may be configured to control which function each of the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106  is configured to perform in each phase. In some embodiments, the control logic circuit  117  may include a clock generator configured to generate clock signals  118 . In other embodiments, the clock signals  118  may control operation of the hybrid ADC  100 . For example, the clock signals  118  may control the timing of phases Φ 1 , Φ 2 , and Φ 3 . General operations of the hybrid ADC  100  will be described below in conjunction with Table 1. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 1 
               
               
                   
               
               
                   
                 First SAR 
                 Residue Amplifier 
                 Second SAR 
               
               
                 Phase 
                 Circuit 102 
                 Circuit 104 
                 Circuit 106 
               
               
                   
               
             
            
               
                 Φ 1   
                 Sample current 
                 Residue amplifier 
                 Idle/Convert residue 
               
               
                   
                 analog input 
                 disabled; 
                 of previous analog 
               
               
                   
                 signal in 
                 Common-mode sense 
                 input signal using 
               
               
                   
                 both FSAR and 
                 capacitors 
                 both Φ 1  and Φ 2   
               
               
                   
                 RDAC 
                 re-charged; 
                 phases 
               
               
                   
                   
                 Deadzone Control 
               
               
                   
                   
                 Disabled 
               
               
                 Φ 2   
                 A/D conversion 
                 Auto-Zero; 
                 Idle/Convert residue 
               
               
                   
                 of the current 
                 Deadzone Control 
                 of previous analog 
               
               
                   
                 input signal 
                 Disabled 
                 input signal using 
               
               
                   
                   
                   
                 both Φ 1  and Φ 2   
               
               
                   
                   
                   
                 phases 
               
               
                 Φ 3   
                 Hold residual 
                 Amplify residual 
                 Sample amplified 
               
               
                   
                 signal of the 
                 signal of the current 
                 residual signal of the 
               
               
                   
                 current analog 
                 analog input signal; 
                 current analog input 
               
               
                   
                 input signal 
                 Deadzone control 
                 signal 
               
               
                   
                 using RDAC 
                 enabled 
               
               
                   
               
            
           
         
       
     
     In some embodiments, the control logic may initialize the hybrid ADC  100  to receive a first analog input signal  101 . In some embodiments, the control logic circuit  117  of the hybrid ADC  100  controls the timing of the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106 . In various embodiments, the control logic circuit  117  may be configured to control the respective operations of phase Φ 1  as specified in Table 1 above. For example, in phase Φ 1 , the first SAR circuit  102  may be configured to sample the first analog input signal  101 ; the RA circuit  104  is configured to be disabled; and the second SAR circuit  106  is configured to be in an idle mode. The term “sample,” as used herein, refers to an operation for extracting an analog value from a continuous and time-varying signal at a specific time. 
     After the first SAR circuit  102  finishes sampling the first analog input signal  101 , the control logic circuit  117  controls the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106  to perform the operations of phase Φ 2  as indicated in Table 1 above. For example, in phase Φ 2 , the first SAR circuit  102  is configured to convert the sampled first analog input signal  101  into the first digital signal  105  that, in some embodiments, corresponds to a most-significant-bits (MSB) portion of the digital output signal  103 , and further provides the residual voltage signal  109 . As the digital values for the first digital signal  105  are determined by the first SAR circuit  102 , the quantized voltage of the first digital signal  105  converges to the analog input signal  101 , and the residue voltage signal  109  decreases. Moreover, in phase Φ 2  the RA circuit  104  is configured to transition to an “auto-zero” mode that is configured to clear out an input offset, if any, present at input ends of the RA circuit  104 , which causes the RA circuit  104  to be ready to perform amplification, while the second SAR circuit  106  is still configured to be in the idle mode. 
     After phase Φ 2  the residual voltage signal  109  is provided to the RA circuit  122 , the control logic circuit  182  controls the first SAR circuit  102 , the RA circuit  104 , and the second SAR circuit  106  to perform the operations of phase Φ 3  as specified in Table 1 above. In phase Φ 3 , the first SAR circuit  102  is configured to hold the residual voltage signal  109  using a residual digital-to-analog converter (RDAC) implemented in the first SAR circuit  102 ; the RA circuit  104  is configured to amplify the residual voltage signal  109  so as to provide an amplified residual voltage signal  113  to the second SAR circuit  106 ; and the second SAR circuit  106  is configured to sample the amplified residual voltage signal  111 . The three main functional circuits ( 102 ,  104 , and  106 ) referenced in  FIG. 1  each performs a respective function in one of three sequential phases (in time). Alternatively stated, in accordance with some embodiments, the first SAR circuit, the RA circuit, and the second SAR circuit operate as a pipelined circuit and each performs a respective function in a certain phase during operations of such a pipelined hybrid ADC. 
     In some embodiments, the hybrid ADC  100  may be configured to operate through a second iteration. As such, during the second iteration the hybrid ADC  100  may receive a second input signal. Subsequently, the hybrid ADC  100  may transition to operate in phase Φ 1  so that the first SAR circuit  102  can sample the second input signal, while the RA circuit  104  is again disabled. During phases Φ 1  and Φ 2  of the second iteration, the second SAR circuit  106  may be configured to convert already sampled amplified residual voltage signal  109  that was part of the previously received analog input signal  101  in phase Φ 3  of the first iteration. In some embodiments, the second SAR circuit  106  is configured to convert the amplified residual voltage signal  113  into the digital signal  107  that corresponds to a least-significant-bits (LSB) portion of the digital output signal  103 . 
     During the second iteration, similar to the first iteration, after the first SAR circuit  102  samples the second analog input signal, the hybrid ADC  100  proceeds to perform operations in phase Φ 2  with respect to the second analog input signal. In some embodiments, in phase Φ 2  of the second iteration, the first SAR circuit  102  converts the sampled second analog input signal and further provides a residual voltage signal to the RA circuit  104 . Once the digital  105  and  107  signals are provided to the error correction circuit  115  (e.g., after phase 2 of the second iteration), the error correction circuit  115  is configured to perform error correction on the digital signals  105  and  107 , and then provide the digital output signal  103 . 
       FIG. 2  illustrates an exemplary circuit diagram of the hybrid ADC  100 . As shown in  FIG. 2 , the first SAR circuit  102  includes a fast SAR (FSAR)  203  and a residue digital-to-analog converter (RDAC)  201 , a comparator  205 , and an asynchronous SAR logic circuit  207 . Although in the illustrated embodiments of  FIG. 2 , the RDAC  201  and FSAR  203  are implemented as a fully-differential circuits, it is noted that the RDAC  201  and FSAR  203  may be implemented by any of a variety of configurations, while remaining within the scope of the present disclosure. For example, the FSAR  203  may include a single-ended SAR ADC, and the RDAC  201  may include a single-ended SAR DAC. 
     In some embodiments, during a current iteration, the FSAR  203  and RDAC  201  may be configured to concurrently receive and sample an analog input signal (e.g.,  101 ) in phase Φ 1  of the current iteration. As such, this enables the RDAC  201  and the FSAR  203  to decouple the high-speed path (ADC) from the noise-limited path (RDAC). This configuration allows for improved speed and power dissipation. In phase Φ 2  of the current iteration, the FSAR  203  may be configured to perform a successive approximation register (SAR) technique on the analog input signal (e.g.,  101 ). The MSBs of the converted analog input signal (e.g.,  101 ) may then be fed to the RDAC  201  to generate the residue voltage  109 . In some embodiments, the FSAR  203  may utilize minimum size capacitors to enable fast SAR iterations with low energy consumption. 
     In some embodiments, the FSAR  203  may be coupled to the comparator  205  that includes inverting and non-inverting input terminals and may be configured to compare voltage levels at its input terminals. Moreover, the asynchronous SAR logic circuit  207  may be coupled to the comparator  205  and further configured to sequentially provide a plurality of SAR feedback control signals  209  based on a plurality of sequentially provided comparison results  211  (outputs of the comparator  205 ). In some embodiments, the sequential provisions of the SAR control signals  209  may be provided based on a clock signal  213  received by the asynchronous SAR logic circuit  207  from the control logic circuit  117 . In some embodiments, the SAR control signals  209  provided by the SAR logic circuit  207  may be asynchronous. As such, the asynchronous SAR control signals  209  obviate the need to explicitly generate a high speed clock. In alternative embodiments, the control logic circuit  117  may include a clock generator as shown in the exemplary embodiments of  FIG. 2 . 
     In some embodiments, the first digital signal  105  output by the first SAR circuit  102  may comprise of 6 bits and a second digital signal  107  output by the second SAR circuit  106  may comprise of 9 bits. In further embodiments, the RA circuit  104  may exhibit a residual gain of 16. In some embodiments, the first SAR circuit  102  may be operated by a 1.2 V supply, which enables a 2.4 V pk-pk  (pick-to-pick) voltage swing for the input signal (e.g.,  101 ). 
     In some embodiments, the RA circuit  104  may be operated by a 0.75 V supply, while utilizing core transistors (e.g., transistors having minimum dimensions compared to input/output (I/O) transistors which have large channel width/length (W/L) rations), which provide low power consumption and improve the operating bandwidth of the hybrid ADC  100  due their a large transit frequency Ft and a large transconductance to drain current ratio (g m /I d ) compared to I/O transistors. In further embodiments, the RA circuit  104  may be operated by a supply voltage less than 1 V. 
       FIG. 3  illustrates a timing diagram of the pipelined hybrid ADC  100  operations, in accordance with some embodiments. In some embodiments, the first SAR circuit  102  is responsive to the rising edge of a signal Φ 1 . During a high period  301  of the signal Φ 1 , the first SAR circuit  102  may be sampling the first analog input signal  101 , while the RA circuit  104  is disabled. In some embodiments, the high period  301  may have a predetermined width. The rising edge of a signal Φ 2  may signal start of phase Φ 2 . During a high period  303  of the signal Φ 2 , the first SAR circuit  102  may be configured to convert the sampled first analog input signal  101  into the first digital signal  105 ; the RA circuit  104  may be configured to transition to an “auto-zero” mode and the second SAR circuit  106  may in the idle mode. In some embodiments, the high period  303  may have a predetermined width. The rising edge of a signal Φ 2  may signal start of phase Φ 3 . During a high period  305  of the signal Φ 3 , the first SAR circuit  102  may be configured to hold the residual voltage signal  109 , the RA circuit  104  may be configured to amplify the residual voltage signal  109 , and the second SAR circuit  106  may be configured to sample the amplified residual voltage signal  111 . In some embodiments, the high period  305  may have a predetermined width. In further embodiments, the signals Φ 1 , Φ 2 , and Φ 3  may be non-overlapping and can be generated by the control logic circuit  117 . In further embodiments, a signal Φ 4  may be provided that is low during the high period of the signal  13 . In some embodiments, during the high periods of the signal Φ 4 , the RA circuit  104  may be coupled to a common mode voltage. In further embodiments, a low period  307  of the signal Φ 4  may have a predetermined width. 
       FIG. 4  illustrates a schematic diagram of the RDAC  203 , the RA circuit  104 , and the second SAR circuit  106 , in accordance with some embodiments. As shown in  FIG. 4 , the RDAC  203  includes a first capacitor array  407  that the includes a plurality of capacitors, a second capacitor array  417  that the includes a plurality of capacitors, a plurality of bit switches S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , S 8 , and switches  411  and  411 ′. In some embodiments, each capacitor of the first and second capacitor arrays  407  and  417  has a top conductive plate (tp) and a bottom conductive plate (bp), as shown in  FIG. 4 . The tp&#39;s of the capacitors in the first capacitor array  407  are each coupled to a common voltage  409  through the switch  411  (when the switch  411  is turned on during the phase Φ 1 ); and the bp&#39;s of the capacitors in the first capacitor array  407  are each selectively coupled to either a node  403  or a node  405  based on a switching behavior of the respectively coupled bit switch (S 1 , S 2 , S 3 , or S 4 ). Further, in some embodiments, the node  403  is coupled to either the negative or positive reference voltage supplied from the FSAR  203 . And the node  405  is coupled to the one end (e.g., V IP ) of the differential analog input signal  101 . 
     Similarly, the tp&#39;s of the capacitors in the second capacitor array  417  are each coupled to the common voltage  409  through the switch  411 ′ (when the switch  411 ′ is turned on); and the bp&#39;s of the capacitors in the second capacitor array  417  are each selectively coupled to either a node  403 ′ or a node  405 ′ based on a switching behavior of the respectively coupled bit switch (S 5 , S 6 , S 7 , or S 8 ). Further, in some embodiments, the node  403 ′ is coupled to either the negative or positive reference voltage supplied from the FSAR  203 . And the node  405 ′ is coupled to the another end (e.g., VIM) of the differential analog input signal  101 . 
     In some embodiments, capacitances of the capacitors in the first capacitor array  407  are weighted with respect to one another. For example, if the minimum capacitance is C then the capacitors in the first capacitor array  407  may have capacitance of 2×C, 4×C, 8×C, 16×C. In further embodiments, a respective capacitance of each additional capacitor the first capacitor array  407  may be selected as: 2N×C, wherein N is an integer larger than 3. Capacitances of the capacitors in the second capacitor array  417  may be selected in similar fashion. In some embodiments, the total capacitance in the first capacitor array  407  (or the second capacitor array  407 ) is about 2.0 picofarad (pF), which provides low thermal noise. Moreover, the RDAC  203  capacitors in both first and second capacitor arrays  407  and  417  are sized for low-noise residue generation as determined by the “kT/C” thermal noise specification. Therefore, no additional energy is wasted on SAR bit iterations using large, noise limited capacitors in both first and second capacitor arrays  407  and  417 . 
     In some embodiments, the switching behavior of each of the bit switches (S 1 , S 2 , S 3 , S 4 , S 5 , S 6 , S 7 , and S 8 ) is controlled by the signal Φ 1  that is provided by the asynchronous SAR logic circuit  207  of the first SAR circuit  102  (also shown in  FIG. 2 ). And the switching behavior of each of the switches  411  and  411 ′ is concurrently determined according to the operation mode of the first SAR circuit  102  (e.g., phases Φ 1 , Φ 2 , or Φ 3 ), which may also be determined by the control logic circuit  117  ( FIG. 1 ). 
     The RDAC  203 , illustrated in  FIG. 4 , may also be configured to provide the residual voltage signal  109  to the RA circuit  102  of the hybrid ADC  100 . In further embodiments, similar to the analog input signal  101 , the residual voltage signal  109  may be provided, by the RDAC  203 , as differential signals  109  (in-phase) and  109 ′ (out-of-phase). In some embodiments, the RA circuit  102  may include a differential amplifier  425  having auto-zeroing capacitors C AZ  coupled to its differential inputs as shown in  FIG. 4 . In various embodiments, the auto-zeroing capacitors C AZ  may functions as an offset sampling and auto-zeroing capacitors and may be coupled to the output of the first SAR circuit  203 . In some embodiments, during the phase Φ 1  the auto-zeroing capacitors C AZ  may be connected to common nodes  419 / 419 ′ through switches S 18  and S 22 , which are closed when the signal Φ 1  is high. The common nodes  419 / 419 ′ may be coupled to a common voltage reference V CMI . During phase Φ 2 , the RA circuit  104  is configured to transition to the “auto-zero” mode. In the “auto-zero” mode, switches S 27  and S 26  may be closed to connect the auto-zeroing capacitors C AZ  to a common node voltage reference  413  (e.g., V CMI ). In some embodiments, the voltage reference nodes  413  and  419 / 419 ′ may have the same voltage. As a result, the voltage at the output of the amplifier  425  should still be relatively small. Moreover, in phase Φ 2 , switches S 21  and S 25  are closed, therefore, creating a feedback loop connecting the output of the amplifier  425  to the auto-zeroing capacitors C AZ  and cancelling input offset of the amplifier  425 . 
     Moreover, the RA circuit shown in  FIG. 4  may also include feedback capacitors  421  and  421 ′ that each have one of its terminal connected to the output of the amplifier  425  and the other terminal connected to one the auto-zeroing capacitors C AZ . During phase Φ 3 , the residual voltage signal  109 / 109 ′ may be received at the auto-zeroing capacitors C AZ  when the switches S 29  and S 28  are closed. Furthermore, during phase Φ 3 , switches S 20  and S 24  may be closed to connect the output of the amplifier  425  to the auto-zeroing capacitors C AZ  via the feedback capacitors  421  and  421 ′. In some embodiments, the feedback capacitors  421  and  421 ′ may be connected to a reference voltage node  423  and  423 ′, respectively during phases Φ 1  and Φ 2 . More specifically, switches S 19  and S 23  may be closed during phase Φ 4 . 
     Furthermore, as shown in  FIG. 4 , the second SAR circuit  106  coupled to the RA circuit  102  may include a comparator  431 , a first capacitor array  427  that includes a plurality of capacitors, a second capacitor array  429  that includes a plurality of capacitors, bit switches S 10 , S 11 , S 12 , S 13 , S 14 , S 15 , S 16 , S 17 , an SAR logic circuit  433 , and switches  439  and  439 ′. Each capacitor of the first and second capacitor arrays  427  and  429  is coupled to a respective bit switch at its respective conductive bottom plate (bp), which will be discussed below. As such, a number of the bit switches corresponds to a number of the capacitors in the first/second capacitor array ( 427 / 429 ). Although only four capacitors are shown in the first/second capacitor array ( 427 / 429 ), it is noted that any desired number of capacitors may be included in the first/second capacitor array ( 427 / 429 ), and a corresponding number of bit switches (S 10  to S 13  and S 14  to S 17 , etc.) may be included in the second SAR circuit  106  while remaining within the scope of the present disclosure. 
     In some embodiments, each capacitor of the first and second capacitor arrays  427  and  429  has a top conductive plate (tp) and a bottom conductive plate (bp), as shown in  FIG. 4 . More specifically, the tp&#39;s of each capacitors in the first capacitor array  427  are each coupled to a non-inverting input terminal of the comparator  431 , and also to a common voltage  437  (e.g., V CM ) through the switch  439  (when the switch  439  is turned on during phase Φ 3 ); and the bp&#39;s of the capacitors in the first capacitor array  427  are each selectively coupled to either a node  435  or nodes  441 / 443  based on a switching behavior of the respectively coupled bit switch (S 10 , S 11 , S 12 , and S 13 ). Further, in some embodiments, the node  435  is coupled to one of the terminals of the RA circuit&#39;s  102  differential output. Moreover, based on a switching behavior of the bit switches S 10 , S 11 , S 12 , and S 13 , bp&#39;s of the capacitors in the first capacitor array  427  may be connected to a high voltage node or a low voltage node provided by the reference voltage nodes  441 / 443 . Furthermore, the reference node  443  may also provide scaled versions (½, ¼, ⅛, etc.) of the reference voltages (e.g., low and high reference voltages) provided by the reference node  441 . 
     Similarly, the tp&#39;s of the capacitors in the second capacitor array  429  are each coupled to an inverting input terminal of the comparator  431 , and also to the common voltage  437 ′ (e.g., V CM ) through the switch  439 ′(when the switch  439 ′ is turned on during phase Φ 3 ); and the bp&#39;s of the capacitors in the second capacitor array  429  are each selectively coupled to either a node  435 ′ or a nodes  441 ′/ 443 ′ based on a switching behavior of the respectively coupled bit switch (S 14 , S 15 , S 16 , and S 17 ). Further, in some embodiments, the node  435 ′ is coupled to one of the terminals of the RA circuit&#39;s  102  differential output. Moreover, based on a switching behavior of the bit switches S 14 , S 15 , S 16 , and S 17 , bp&#39;s of the capacitors in the first capacitor array  429  may be connected to a high voltage node or a low voltage node provided by the reference voltage nodes  441 ′/ 443 ′. Furthermore, the reference node  443 ′ may also provide scaled versions (½, ¼, ⅛, etc.) of the reference voltages (e.g., low and high reference voltages) provided by the reference node  441 ′. 
     In some embodiments, capacitances of the capacitors in the first capacitor array  427  are weighted with respect to one another. For example, if the minimum capacitance is C then the capacitors in the first capacitor array  427  may have capacitance of 2×C, 4×C, 8×C, 16×C. In further embodiments, a respective capacitance of each additional capacitor the first capacitor array  427  may be selected as: 2N×C, wherein N is an integer larger than 3. Capacitances of the capacitors in the second capacitor array  429  may be selected in similar fashion. In some embodiments, the total capacitance in the first capacitor array  427  (or the second capacitor array  429 ) is about 55 femtofarad (fF), which provides low thermal noise. 
     In some embodiments, the switching behavior of each of the bit switches (S 10 , S 11 , S 12 , S 13 , S 14 , S 15 , S 16 , S 17 ) is controlled by the SAR logic  433 . In some embodiments, the SAR logic  433  is configured to sequentially provide a plurality of control signals controlling bit switches S 10 , S 11 , S 12 , S 13 , S 14 , S 15 , S 16 , S 17  based on a plurality of sequentially provided comparison results that are output by the comparator  431 . In some embodiments, the sequential control signals of the SAR logic  433  may be provided based on a clock signal received by the SAR logic  433 . 
     In some embodiments, the comparator  433  may be configured to compare voltage levels at its two input terminals after the control signals generated by the SAR logic  433  are used for toggling the respective bit switches (S 10 , S 11 , S 12 , S 13 , S 14 , S 15 , S 16 , S 17 ). In some embodiments, the comparator  433  is configured to convert the amplified residual voltage signal received from the RA circuit  104  into the digital signal  107  that corresponds to a least-significant-bits (LSB) portion of the digital output signal  103 . 
       FIG. 5  illustrates an exemplary circuit diagram of the amplifier  425  in the RA circuit  104 , in accordance with some embodiments of the present disclosure. In some embodiments, the amplifier  425  may be implemented as a differential circuit. Accordingly, the amplifier  425  is symmetric with respect to line  500 , as shown in  FIG. 5 . It is noted that the amplifier  425  may be alternatively implemented as a single-ended amplifier while remaining within the scope of the present disclosure. In some embodiments, the amplifier  425  includes three uncompensated inverter stages:  501 ,  503 , and  505  that are configured to receive, during phase Φ 3 , and amplify the differential residual signals  109  and  109 ′. More specifically, the first stage  501  is configured to receive the differential residual signals  109  and  109 ′ (e.g., V P  and V M ), the second stage  503  is configured to receive and process signals from the respective sides of the first stage  501 , and the third stage  505  is configured to receive and process signals from the respective sides of the second stage  503 . In some embodiments, the third stage  505  may employ a deadzone (e.g., voltage drop V DZ  on resistors  513 / 513 ′) to provide closed loop stability when the amplifier&#39;s  425  input  109 / 109 ′ approaches the desired common-mode voltage (e.g., V CMI  or V CMO ) by operating the third stage  505  in a deep sub-threshold region, thereby providing a high output resistance that forms a dominant pole for the stable feedback operation of the amplifier  425 . 
     In some embodiments, the first stage  501  comprises of transistors M 0 , M 1 , M 2 , M 3 , M 4  M 5  M 6  M 7  and M 8 . The second stage  503  comprises of transistors M 9 , M 10 , M 11 , M 12  and the two resistors  513 / 513 ′ coupled between the transistors (M 9  and M 10 ) and (M 11  and M 12 ), respectively and configured to dynamically apply offset voltages to the third stage  505  so as to operate the third stage  505  in deep-sub-threshold region during the steady state operation. The third stage  505  includes transistors M 13 , M 14 , M 15 , and M 16  and is further configured to operate in sub-threshold region, while exhibiting a high output resistance that forms a dominant pole needed for a stable feedback loop. In some embodiments, the transistors M 0 , M 1 , M 2 , M 3 , M 4 , M 9 , M 11 , M 13 , and M 15  each includes an NMOS transistor, and M 5 , M 6 , M 7 , M 8 , M 10 , M 12 , M 14 , and M 16  each includes a PMOS transistor. Although the illustrated embodiments of  FIG. 3  shows that M 0 -M 16  are either NMOS or PMOS transistors, any of a variety of transistors or devices that are suitable for use in a memory device may be implemented as at least one of M 0 -M 16  such as, for example, a bipolar junction transistor (BJT), a high-electron-mobility transistor (HEMT), etc. 
     In some embodiments, the transistor M 0  is gated by an enable signal EN that can used to enable or disable the amplifier  425 . In some embodiments, the enable signal EN may be derived from the signal Φ 1 . In further embodiments, the transistor M 0  may be coupled to a reference voltage  511  (e.g. ground) at its source; the transistors M 1  and M 2  are gated by bias signals  515  (V BIAS ) and  515 ′ (V CMFB ) and coupled to the transistor M 0  at the transistor M 0 &#39;s drain and M 1 &#39;s and M 2 &#39;s sources. 
     Since the amplifier  425  is symmetric with respect to the line  500 , for brevity, the following discussion of the amplifier  425  will be focused on the left side of the line  500 . In some embodiments, transistors M 3  and M 5  are formed as a first inverter, between V DD    509  and the drain of the transistor M 1 , that receives one of the differential residual signal  109  as an input signal; the transistor M 7  is coupled to a reference voltage  509  (e.g., V DD ) at its source, and the transistor M 7 &#39;s gate is coupled to a common node  517  coupled to the transistor M 3 &#39;s and M 5 &#39;s respective drains. In the second stage  503 , the transistors M 9  and M 10  are coupled to the common node  517  at their respective gates, and the transistors M 9  and M 10  are formed as a second inverter, between the reference voltage  509  and ground  511 ; and the resistor  313  is coupled between the transistors M 9  and M 10  at their respective drains. In the third stage  505 , the transistors M 15  and M 16  are formed as a third inverter between the reference voltage  509  and ground  511 , wherein the transistor M 15 &#39;s gate is coupled to a node Y and the transistor M 16 &#39;s gate is coupled to a node Z. In some embodiments, the third inverter of the third stage  505  may be configured to output signal  507  (e.g., V ON ) that is an amplified version of the signal  109 . In some embodiments, the amplified output signal  507  may correspond to an out-of-phase signal of the amplified residual voltage signal  113  ( FIG. 1 ). 
     On the right side of the line  500 , the transistors M 0 , M 2 , M 4 , M 6 , M 8 , M 11 , M 12 , M 13 , and M 14 , the resistor  513 ′ are laid out substantially similar to the components on the left side except that an inverter formed by the transistors M 4  and M 6  receives the other of the differential residual signal  109 ′ as its input signal, and another inverter formed by the transistors M 13  and M 14  is configured to output signal  507 ′ that is an amplified version of the signal  109 ′. 
     It is also noted a pair of current sources may be incorporated between the second and third stages  503  and  505 , wherein one of the pair of the current sources may be configured to carry a current I B  between the reference voltage V DD    509  and the node “Z,” and the other of the pair of the current sources may be configured to carry a current I B  between the node “Y” and ground  511 . In some embodiments the current sources may be incorporated in a deadzone control circuit  519  that includes one or more circuits each configured to provide the current I B  between the reference voltage V DD    509  and the node “Z” and the node “Y” and ground  511  as well as a deadzone control for a stable feedback operation of the amplifier  425  in various semiconductor process variation corners and supply voltages. The deadzone control circuit will be discussed in further detail below. 
     In semiconductor manufacturing, variations in fabrication parameters may vary the characteristics of the integrated circuits fabricated on semiconductor wafers. As such, the variations in fabrications parameters may cause feedback compensated amplifiers to oscillate or exhibit instability in operation in response to varying environmental conditions, such as high/low voltage supply, high/low clock frequency, and high/low temperature. In this regard,  FIG. 6  shows variations of a deadzone voltage V DZ    601  across the resistor  513  or  513 ′ with respect to the six front end of line (FEOL) process corners  603  (typical-typical (TT), fast-fast (FF), and slow-slow (SS)) at the reference voltage V DD    509  set to 0.90 V or to 0.75 V. Table 2 below lists six FEOL process corners at the reference supply voltage V DD    509  set to 0.90 V and to 0.75 V. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 2 
               
               
                   
               
               
                 Corner # 
                 1 
                 2 
                 3 
                 4 
                 5 
                 6 
               
               
                   
               
             
            
               
                 Process 
                 tt 
                 ss 
                 ff 
                 tt 
                 ss 
                 ff 
               
               
                 Supply, V 
                 0.90 
                 0.90 
                 0.90 
                 0.75 
                 0.75 
                 0.75 
               
               
                   
               
            
           
         
       
     
     As illustrated by a curve  605  of  FIG. 6 , the deadzone voltage V DZ    601  across the resistor  513  or  513 ′ in the absence of the deadzone control circuit  519  enters into unstable region  611  at the process corners 2, 4 and 5 and stays within the stable region  613  at the process corners 1 and 3. At the process corner 1, where the process is “tt” and the amplifier&#39;s  425  supply voltage V DD    509  is set to 0.9 V, the deadzone voltage V DZ , based on the simulated curve  605 , may be 270 mV. Yet, the deadzone voltage V DZ  of 270 mV does not provide enough voltage margin for safely operating the third inverter stage  505  in deep sub-threshold region, which, in turn, provides a high output resistance that forms a dominant pole for a stable feedback operation of the amplifier  425  as it approaches a steady state mode. Moreover, as further shown by the curve  605 , at the process corner 1, where the process is “tt” and the amplifier&#39;s  425  supply voltage V D D  509  is set to 0.75 V, the deadzone voltage V DZ , drops to 150 mV, which is outside the stable region  613 , causing oscillations due to insufficient deadzone induced instability. Furthermore, as shown by the curve  605 , at the process corner 6, the deadzone voltage V DZ  may be greater than 550 mV, and the amplifier  425  may operate in an undesired low gain region  615  as the transistors (M 9 , M 10 , M 11  and M 12 ) of the second stage  503  enter the linear operating region. Thus, as illustrated in  FIG. 6 , the allowable range for the deadzone voltage V DZ  variations become increasingly constrained at the lowered reference supply voltage V DD    509 , or else, the amplifier  425  may either becomes unstable (region  611 ), enter the undesired low gain region  615 , or even become non-functional. On the other hand, a curve  609  shows the deadzone voltage V DZ    601  across the resistor  513  or  513 ′ in the deadzone control circuit  519  enabled. As illustrated by the curve  609  of  FIG. 6 , the deadzone voltage V DZ  stays within the stable region  613  for all simulated process corners (e.g., process corners 1 to 6 of Table 2). 
     Refereeing again to  FIG. 5 , the deadzone control circuit  519  may include transistors M 17 , M 18 , M 19 , M 20 , M 21 , M 22 , M 23 , and M 24 , a differential amplifier with an active load  525 , a resistor  531 , and a feedback capacitor  527  and a resistor  529  connected in series. In some embodiments, the active load of the differential amplifier may be a current mirror. In some embodiments, the transistors M 21 , M 22 , and M 23  may be NMOS transistors and M 17 , M 20 , M 21 , and M 22  may be PMOS transistors. In further embodiments, the transistors M 17 , M 18 , M 19 , M 20 , M 21 , M 22 , and M 23  may also be implemented as bipolar junction transistors (BJT) or as high-electron-mobility transistors (HEMT). In some embodiments, the transistors M 18  and M 19  may form a compact (e.g., small area footprint) input pair configured to generate the current I B  between the reference voltage V DD    509  and the node “Z” and between the nodes “Y” and ground  511 . In some embodiments, drains of the transistors M 18  and M 19  may be coupled to nodes  505  and  505 ′, respectively and sources the transistors M 18  and M 19  may be coupled to the reference voltage V DD    509 . Moreover, the input pairs formed by the transistors M 18  and M 19  may also provide a gate voltage to the M 17  PMOS transistor, by coupling the gates of the transistors M 18  and M 19  to the gate of the transistor M 17 , so as to generate the same the current I B  from the reference voltage V DD  node  509  through the transistor M 17  to ground  511 . In some embodiments, the transistor M 20 &#39;s source may be coupled to the reference voltage V DD  node  509 , the transistor M 20 &#39;s gate may also be coupled to the gates of transistors M 17 , M 18 , and M 19 , and the transistor M 20 ′ drain may be commonly coupled to the drain and the gate of the transistor M 21  and gates of the transistors M 22 -M 23 . The transistors M 21 -M 23  may be coupled to ground  511  at their respective sources. Moreover, in some embodiments, drains of the transistors M 22  and M 23  may be coupled to nodes  504  and  504 ′, respectively. 
     In some embodiments, a resistance value of the resistor  531  coupled between the drain of the transistor M 17  and ground  511  may be substantially identical to a resistance value of the resistor R B    513 / 513 ′. Moreover, the differential amplifier with current mirror load  525 , in some embodiments, may be biased with the transistor M 24  having its gate set to a bias voltage reference V BIAS . In some embodiments, the deadzone control circuit  519  may be enabled or disabled through a switch EN coupled to the source of the bias transistor M 24  and controlled by the signal Φ 3 . Furthermore, during the test mode, one of the inputs of the differential amplifier with current mirror load  525  may be set to ground through a switch  521 . In some embodiments, the output of the differential amplifier  525  may be coupled to one of its input at node X through a passive feedback filter comprised of the capacitor  527  in series with the resistor  528 . In further embodiments, the differential amplifier with current mirror load  525  may be coupled to a reference voltage V RB  at one of its inputs through a switch  523 . In a steady-state, when the switch  523  is turned on, the gate voltage of the PMOS transistor M 17  that results in a voltage drop of V RB  across the resistor  531 , which yields a current, I B =V RB /R B . In some embodiments, the gate voltage of the PMOS transistor M 17  may be set by a reference voltage V ref  at one of inputs of the differential amplifier with current mirror load  525 . In further embodiments, the current I B  that flows through the resistor  531  may then be mirrored to the matched deadzone resistor R B    513 / 513 ′ in the second stage  503  of the amplifier  425 , resulting in a stable (i.e., process and temperature independent) voltage drop of V RB , which can be based on a bandgap reference. As such, the deadzone voltage V DZ  generated across the resistor R B    513 / 513 ′ in the second stage  503  is the sum of the voltage V RB  and the voltage drop generated by the inverter short circuit current. The deadzone voltage V DZ  may be expressed as follows: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       D 
                       ⁢ 
                       Z 
                     
                   
                   = 
                   
                     
                       V 
                       
                         R 
                         ⁢ 
                         B 
                       
                     
                     + 
                     
                       
                         1 
                         2 
                       
                       ⁢ 
                       μ 
                       ⁢ 
                       
                         C 
                         
                           o 
                           ⁢ 
                           x 
                         
                       
                       ⁢ 
                       
                         W 
                         L 
                       
                       ⁢ 
                       
                         
                           ( 
                           
                             
                               V 
                               
                                 G 
                                 ⁢ 
                                 S 
                               
                             
                             - 
                             
                               V 
                               
                                 T 
                                 ⁢ 
                                 H 
                               
                             
                           
                           ) 
                         
                         2 
                       
                       ⁢ 
                       
                         R 
                         B 
                       
                     
                   
                 
               
               
                 
                   ( 
                   1 
                   ) 
                 
               
             
           
         
       
     
     In equation (1), the deadzone voltage V DZ  is a sum of the voltage V RB  that is stable over process, voltage, and temperature (PVT) variations, etc. and the second term that is the voltage drop formed by the (long channel) saturation region transistor current through the resistor  513 / 513 ′ R B . In this regard, design choices for the voltage V RB , the resistors  531  and  513 / 513 ′ and the sizing (e.g., W/L) of the M 11  and M 12  (M 10  and M 9 ) transistors of the second stage  503  may result in the deadzone voltage V DZ  variations that are within the stable region  613  ( FIG. 6 ). 
     In some embodiments, transient response characteristics of the deadzone control voltage V DZ  during the amplification phase Φ 3  may be designed such that a coarse as well as fine amplification is accomplished. That is, during the initial moments of the amplification phase Φ 3 , the deadzone control voltage V DZ  may bias the transistors M 13  and M 14  (M 15  and M 16 ) of the third stage  505  of amplifier  425  in a high bandwidth and low gain state, which provides an initial fast and coarse slew charge at the output node  507 / 507 ′. Subsequently, the transistors M 13  and M 14  (M 15  and M 16 ) of the third stage  505  may then gradually converge towards a lower bandwidth and higher gain state for finer settling. In some embodiments, a deadzone current path  533  may be designed to be independent of the amplifier&#39;s  425  differential signal path. 
     In one exemplary advantage of the amplifier  425  shown in  FIG. 5  is that it produces a high gain by utilizing three cascaded gain stages  501 ,  503 , and  505 . Another exemplary advantage of the amplifier  425  is that it provides near rail-to rail swing for the output differential signals V ON  and V OP . Other advantages of the amplifier  425  are the ability to operate in a low voltage supply domain and to scale with advancing process technology, which provides an improved performance. 
       FIG. 7  illustrates an exemplary flow chart of a method for performing a residue amplification with an amplifier that has an output stage is biased in a stable sub-threshold region, in accordance with some embodiments. The method shown in  FIG. 7  is merely an example. Therefore, it should be understood that any of a variety of operations may be omitted, re-sequenced, and/or added while remaining within the scope of the present disclosure. In accordance with some embodiments, the operations of the method illustrated in  FIG. 7  can be performed by the amplifier  425  of  FIG. 5 , the RA circuit  104  of  FIG. 1, 2 or 4 . For ease of discussion, the following embodiment of the method illustrated in  FIG. 7  will be described using the amplifier  425  of  FIG. 5  as a representative example. 
     The method for performing a residue amplification starts with operation  701  in which the differential amplifier with a current mirror load  525  is turn on through the switch EN during the amplification phase Φ 3 , in accordance with some embodiments. 
     After the turning the differential amplifier  525  on, the method shown in  FIG. 7  proceeds to operation  703 , which includes receiving the reference voltage V ref  at one of the inputs of the differential amplifier  525 . In some embodiments, the reference voltage V ref  is used to establish a current I B  through the resistor  531 . In some embodiments, the voltage drop V RB  formed across the resistor  531  due to the current I B  may be substantially same as the received reference voltage V ref . 
     The method for performing a residue amplification continues to operation  705  in which a bias current is based on the reference voltage V ref  and configured to provide a stable bias voltage to an output stage  505  of the amplifier  425 , where the output stage  505  is biased in a sub-threshold region during the amplification phase Φ 3 . In some embodiments, the bias voltage for the output stage  505  of the amplifier is based on the deadzone voltage V DZ  formed across the deadzone resistor R B    513 / 513 ′ due to the current I B . In some embodiments, the deadzone voltage V DZ  formed across the deadzone resistor R B    513 / 513 ′, due to I B R B  voltage drop and the inverter short circuit current, is stable across process, voltage, and temperature variations. 
     At operation  707 , the current I B  that flows through the resistor  531  may be mirrored on the deadzone resistor R B    513 / 513 ′, in accordance with some embodiments. In further embodiments, the current I B  that flows through the resistor  531  may be mirrored through current mirrors connected in series and comprised of NMOS transistors M 21 , M 22 , and M 23  ( FIG. 5 ) and PMOS transistors M 17 , M 18 , M 19 , and M 20  ( FIG. 5 ). 
     At operation  709 , the residual voltage signal  109 / 109 ′ received from the RDAC  203  ( FIG. 4 ) may amplified by the amplifier  425  ( FIG. 5 ), in accordance with some embodiments. The operation  709  may correspond to phase Φ 3  of the first iteration with respect to Table 1. As such, in phase Φ 3  of the first iteration, the RDAC  203  ( FIG. 4 ) of the first SAR circuit  102  may be configured to hold the residual voltage signal  109 / 109 ′ and the RA circuit  104  may be configured to amplify the residual voltage signal  109 / 109 ′ by using the amplifier  425  comprising of three state inverters, so as to provide the amplified residual signal  113  for the second SAR circuit  106 . 
     While various embodiments of the present disclosure have been described above, it should be understood that they have been presented by way of example only, and not by way of limitation. Likewise, the various diagrams may depict an example architectural or configuration, which are provided to enable persons of ordinary skill in the art to understand exemplary features and functions of the present disclosure. Such persons would understand, however, that the present disclosure is not restricted to the illustrated example architectures or configurations, but can be implemented using a variety of alternative architectures and configurations. Additionally, as would be understood by persons of ordinary skill in the art, one or more features of one embodiment can be combined with one or more features of another embodiment described herein. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments. 
     It is also understood that any reference to an element herein using a designation such as “first,” “second,” and so forth does not generally limit the quantity or order of those elements. Rather, these designations are used herein as a convenient means of distinguishing between two or more elements or instances of an element. Thus, a reference to first and second elements does not mean that only two elements can be employed, or that the first element must precede the second element in some manner. 
     Additionally, a person having ordinary skill in the art would understand that information and signals can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits and symbols, for example, which may be referenced in the above description can be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. 
     A person of ordinary skill in the art would further appreciate that any of the various illustrative logical blocks, modules, processors, means, circuits, methods and functions described in connection with the aspects disclosed herein can be implemented by electronic hardware (e.g., a digital implementation, an analog implementation, or a combination of the two), firmware, various forms of program or design code incorporating instructions (which can be referred to herein, for convenience, as “software” or a “software module), or any combination of these techniques. 
     To clearly illustrate this interchangeability of hardware, firmware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware, firmware or software, or a combination of these techniques, depends upon the particular application and design constraints imposed on the overall system. Skilled artisans can implement the described functionality in various ways for each particular application, but such implementation decisions do not cause a departure from the scope of the present disclosure. In accordance with various embodiments, a processor, device, component, circuit, structure, machine, module, etc. can be configured to perform one or more of the functions described herein. The term “configured to” or “configured for” as used herein with respect to a specified operation or function refers to a processor, device, component, circuit, structure, machine, module, signal, etc. that is physically constructed, programmed, arranged and/or formatted to perform the specified operation or function. 
     Furthermore, a person of ordinary skill in the art would understand that various illustrative logical blocks, modules, devices, components and circuits described herein can be implemented within or performed by an integrated circuit (IC) that can include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, or any combination thereof. The logical blocks, modules, and circuits can further include antennas and/or transceivers to communicate with various components within the network or within the device. A processor programmed to perform the functions herein will become a specially programmed, or special-purpose processor, and can be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other suitable configuration to perform the functions described herein. 
     If implemented in software, the functions can be stored as one or more instructions or code on a computer-readable medium. Thus, the steps of a method or algorithm disclosed herein can be implemented as software stored on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that can be enabled to transfer a computer program or code from one place to another. A storage media can be any available media that can be accessed by a computer. By way of example, and not limitation, such computer-readable media can include RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to store desired program code in the form of instructions or data structures and that can be accessed by a computer. 
     In this document, the term “module” as used herein, refers to software, firmware, hardware, and any combination of these elements for performing the associated functions described herein. Additionally, for purpose of discussion, the various modules are described as discrete modules; however, as would be apparent to one of ordinary skill in the art, two or more modules may be combined to form a single module that performs the associated functions according embodiments of the present disclosure. 
     Various modifications to the implementations described in this disclosure will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other implementations without departing from the scope of this disclosure. Thus, the disclosure is not intended to be limited to the implementations shown herein, but is to be accorded the widest scope consistent with the novel features and principles disclosed herein, as recited in the claims below.