Patent Publication Number: US-11658269-B2

Title: Light-emitting device

Description:
REFERENCE TO RELATED APPLICATION 
     This application is a continuation application of U.S. patent application Ser. No. 16/891,670, filed on Jun. 3, 2020, now pending, which is a continuation application of U.S. patent application Ser. No. 16/384,890, filed on Apr. 15, 2019, U.S. Pat. No. 10,680,138, which is a continuation application of U.S. patent application Ser. No. 15/948,738, filed on Sep. 4, 2018, now U.S. Pat. No. 10,297,723, which is a continuation application of U.S. patent application Ser. No. 15/858,534, filed on Dec. 29, 2017, now U.S. Pat. No. 10,199,544, which is a continuation application of U.S. patent application Ser. No. 15/350,893, filed on Nov. 14, 2016, now U.S. Pat. No. 9,893,241, which claims the right of priority based on TW Application Serial No. 104137443, filed on Nov. 13, 2015, and the content of which is hereby incorporated by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     The application relates to a structure of a light-emitting device, and more particularly, to a light-emitting device comprising a semiconductor stack and a pad on the semiconductor stack. 
     DESCRIPTION OF BACKGROUND ART 
     Light-Emitting Diode (LED) is a solid-state semiconductor light-emitting device, which has the advantages of low power consumption, low heat generation, long working lifetime, shockproof, small volume, fast reaction speed and good optoelectronic property, such as stable emission wavelength. Therefore, light-emitting diodes are widely used in household appliances, equipment indicators, and optoelectronic products. 
     SUMMARY OF THE APPLICATION 
     A light-emitting device includes a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a first contact layer covering the one or multiple vias; a third insulating layer including a first group of one or multiple third insulating openings formed on the second semiconductor layer to expose the first contact layer; a first pad on the semiconductor stack and covering the first group of one or multiple third insulating openings; and a second pad on the semiconductor stack and separated from the first pad with a distance to define a region between the first pad and the second pad on the semiconductor stack, wherein the second pad is formed at a position other than positions of the one or multiple vias in a top view of the light-emitting device. 
     A light-emitting device includes a substrate including a center line; a semiconductor stack including a first semiconductor layer, a second semiconductor layer, and an active layer between the first semiconductor layer and the second semiconductor layer; one or multiple vias penetrating the active layer and the second semiconductor layer to expose the first semiconductor layer; a reflective structure covering the second semiconductor layer; a contact layer covering the one or multiple vias and extending to cover the second semiconductor layer; a third insulating layer formed on the second semiconductor layer and including a first group of third insulating opening and a second group of third insulating opening, wherein the first group of third insulating opening is close to one side of the center line, and the second group of third insulating opening is close to the other side of the center line; a first pad formed on the semiconductor stack, wherein the first pad is located at the one side of the center line and electrically connected to the first semiconductor layer through the first group of third insulating opening; and a second pad formed on the semiconductor stack, wherein the second pad is located at the other side of the center line and electrically connected to the second semiconductor layer through the second group of third insulating opening, and the first pad and the second pad are separated from each other with a distance. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS.  1 A- 7 C  illustrate a manufacturing method of a light-emitting device  1  or a light-emitting device  2  in accordance with embodiments of the present application; 
         FIG.  8    illustrates a top view of the light-emitting device  1  in accordance with an embodiment of the present application; 
         FIG.  9 A  illustrates a cross-sectional view of the light-emitting device  1  in accordance with an embodiment of the present application; 
         FIG.  9 B  illustrates a cross-sectional view of the light-emitting device  1  in accordance with an embodiment of the present application; 
         FIG.  10    illustrates a top view of the light-emitting device  2  in accordance with an embodiment of the present application; 
         FIG.  11 A  illustrates a cross-sectional view of the light-emitting device  2  in accordance with an embodiment of the present application; 
         FIG.  11 B  illustrates a cross-sectional view of the light-emitting device  2  in accordance with an embodiment of the present application; 
         FIGS.  12 A- 18 B  illustrate a manufacturing method of a light-emitting device  3  or a light-emitting device  4  in accordance with embodiments of the present application; 
         FIG.  19    illustrates a top view of the light-emitting device  3  in accordance with an embodiment of the present application; 
         FIG.  20    illustrates a cross-sectional view of the light-emitting device  3  in accordance with an embodiment of the present application; 
         FIG.  21    illustrates a top view of the light-emitting device  4  in accordance with an embodiment of the present application; 
         FIG.  22    illustrates a cross-sectional view of the light-emitting device  4  in accordance with an embodiment of the present application; 
         FIG.  23    illustrates a cross-sectional view of a light-emitting device  5  in accordance with an embodiment of the present application; 
         FIG.  24    illustrates a cross-sectional view of a light-emitting device  6  in accordance with an embodiment of the present application; 
         FIG.  25    illustrates a structure diagram of a light-emitting apparatus in accordance with an embodiment of the present application; and 
         FIG.  26    illustrates a structure diagram of a light-emitting apparatus in accordance with an embodiment of the present application. 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     The embodiment of the application is illustrated in detail, and is plotted in the drawings. The same or the similar part is illustrated in the drawings and the specification with the same number. 
       FIGS.  1 A- 11 B  illustrate a manufacturing method of a light-emitting device  1  or a light-emitting device  2  in accordance with embodiments of the present application. 
     As a top view in  FIG.  1 A  and a cross-sectional view in  FIG.  1 B  which is taken along line A-A′ of  FIG.  1 A  show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming a mesa, which includes providing a substrate  11   a  and forming a semiconductor stack  10   a  on the substrate  11   a , wherein the semiconductor stack  10   a  comprises a first semiconductor layer  101   a , a second semiconductor layer  102   a , and an active layer  103   a  between the first semiconductor layer  101   a  and the second semiconductor layer  102   a . The semiconductor stack  10   a  can be patterned by lithography and etching to remove a portion of the second semiconductor layer  102   a  and the active layer  103   a  to form one or multiple semiconductor structures  1000   a  and to form a surrounding part  111   a  surrounding the one or multiple semiconductor structures  1000   a . The surrounding part  111   a  exposes a first surface  1011   a  of the first semiconductor layer  101   a . The one or multiple semiconductor structures  1000   a  comprises a first outside wall  1003   a , a second outside wall  1001   a , and an inside wall  1002   a , wherein the first outside wall  1003   a  is a sidewall of the first semiconductor layer  101   a , the second outside wall  1001   a  is a sidewall of the active layer  103   a  and/or a sidewall of the second semiconductor layer  102   a . One end of the second outside wall  1001   a  is connected to a surface  102   s  of the second semiconductor layer  102   a  and another end of the second outside wall  1001   a  is connected to the first surface  1011   a  of the first semiconductor layer  101   a . One end of the inside wall  1002   a  is connected to the surface  102   s  of the second semiconductor layer  102   a  and another end of the inside wall  1002   a  is connected to a second surface  1012   a  of the first semiconductor layer  101   a . Multiple semiconductor structures  1000   a  are connected to each other through the first semiconductor layer  101   a . As shown in  FIG.  1 B , an obtuse angle is formed between the inside wall  1002   a  of the semiconductor structure  1000   a  and the second surface  1012   a  of the first semiconductor layer  101   a . An obtuse angle or a right angle is formed between the first outside wall  1003   a  of the semiconductor structure  1000   a  and a surface  11   s  of the substrate  11   a . An obtuse angle is formed between the second outside wall  1001   a  of the semiconductor structure  1000   a  and the first surface  1011   a  of the first semiconductor layer  101   a . The surrounding part  111   a  surrounds the semiconductor structure  1000   a , the top view of the surrounding part  111   a  is a rectangular or a polygonal shape. 
     In an embodiment of the present application, the light-emitting device  1  or the light-emitting device  2  comprises a side less than 30 mil. When an external current is injected into the light-emitting device  1  or the light-emitting device  2 , the semiconductor structure  1000   a  is surrounded by the surrounding part  111   a  to distribute the light field of the light-emitting device  1  or the light-emitting device  2  uniformly and reduce the forward voltage of the light-emitting device. 
     In an embodiment of the present application, the light-emitting device  1  or the light-emitting device  2  comprises a side larger than 30 mil. The semiconductor stack  10   a  can be patterned by lithography and etching to remove a portion of the second semiconductor layer  102   a  and the active layer  103   a  to form one or multiple vias  100   a  penetrating through the second semiconductor layer  102   a  and the active layer  103   a , wherein the one or multiple vias  100   a  expose one or more second surface  1012   a  of the first semiconductor layer  101   a . When an external current is injected into the light-emitting device  1  or the light-emitting device  2 , the surrounding part  111   a  and the multiple vias  100   a  are dispersedly disposed to distribute the light field distribution of the light-emitting device  1  or the light-emitting device  2  uniformly and reduce the forward voltage of the light-emitting device. 
     In an embodiment of the present application, the light-emitting device  1  or the light-emitting device  2  comprises a side less than 30 mil, the light-emitting device  1  or the light-emitting device  2  does not comprise one or multiple vias  100   a  to increase a light-emitting area of the active layer. 
     In an embodiment of the present application, the one or multiple vias  100   a  comprises an opening having a shape, such as circular, ellipsoidal, rectangular, polygonal, or any shape. The multiple vias  100   a  can be arranged in a plurality of rows, and the vias  100   a  in the adjacent two rows can be aligned with each other or staggered. 
     In an embodiment of the present application, the substrate  11   a  can be a growth substrate, comprising gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP), sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer or silicon carbide (SiC) wafer for growing indium gallium nitride (InGaN). The semiconductor stack  10   a  comprises optical characteristics, such as light-emitting angle or wavelength distribution, and electrical characteristics, such as forward voltage or reverse current. The semiconductor stack  10   a  can be formed on the substrate  11   a  by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), or ion plating. 
     In an embodiment of the present application, the first semiconductor layer  101   a  and the second semiconductor layer  102   a , such as a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer  101   a  is an n-type semiconductor, and the second semiconductor layer  102   a  is a p-type semiconductor. The active layer  103   a  is formed between the first semiconductor layer  101   a  and the second semiconductor layer  102   a . The electrons and holes combine in the active layer  103   a  under a current driving to convert electric energy into light energy to emit a light. The wavelength of the light emitted from the light-emitting device  1  or the light-emitting device  2  is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack  10   a . The material of the semiconductor stack  10   a  comprises a group III-V semiconductor material, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer  103   a , when the material of the semiconductor stack  10   a  is AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack  10   a  is InGaN series material, blue light having a wavelength between 450 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack  10   a  is AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted. The active layer  103   a  can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well structure, MQW). The material of the active layer  103   a  can be i-type, p-type, or n-type semiconductor. 
     Following the step of forming the mesa, as a top view in  FIG.  2 A  and a cross-sectional view in  FIG.  2 B  which is taken along line A-A′ of  FIG.  2 A  show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming the first insulating layer. A first insulating layer  20   a  can be formed on the semiconductor structure  1000   a  by sputter or vapor deposition, and patterned by lithography and etching to cover the first surface  1011   a  of the surrounding part  111   a  and the second surface  1012   a  on the via  100   a , and cover the second outside wall  1001   a  of the second semiconductor layer  102   a  and the active layer  103   a  of the semiconductor structure  1000   a  and the inside wall  1002   a  of the semiconductor structure  1000   a . The first insulating layer  20   a  comprises a first insulating surrounding region  200   a  covering the surrounding part  111   a , thereby the first surface  1011   a  of the first semiconductor layer  101   a  on the surrounding part  111   a  is covered by the first insulating surrounding region  200   a ; a first group of first insulating covering regions  201   a  covering the vias  100   a , thereby the second surfaces  1012   a  of the first semiconductor layer  101   a  on the vias  100   a  are covered by the first group of first insulating covering regions  201   a ; and a second group of first insulating openings  202   a  exposing the surface  102   s  of the second semiconductor layer  102   a . The first group of first insulating covering regions  201   a  is separated from each other, and is respectively corresponding to the multiple vias  100   a . The first insulating layer  20   a  includes one layer or multiple layers. When the first insulating layer  20   a  includes one layer, the first insulating layer  20   a  protects the sidewall of the semiconductor structure  1000   a  to prevent the active layer  103   a  from being destroyed by the following processes. When the first insulating layer  20   a  includes multiple layers, the first insulating layer  20   a  includes two or more layers having different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR), which can selectively reflect light of a specific wavelength. The first insulating layer  20   a  is formed of a non-conductive material and comprises organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     In an embodiment of the present application, following the step of forming the first insulating layer, as a top view in  FIG.  3 A  and a cross-sectional view in  FIG.  3 B  which is taken along line A-A′ of  FIG.  3 A  show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming the transparent conductive layer. A transparent conductive layer  30   a  can be formed in the second group of first insulating openings  202   a  by sputter, vapor deposition or the like, wherein an outer edge  301   a  of the transparent conductive layer  30   a  is spaced apart from the first insulating layer  20   a  with a distance to expose the surface  102   s  of the second semiconductor layer  102   a . Since the transparent conductive layer  30   a  is substantially formed on the entire surface of the second semiconductor layer  102   a  and contacts the second semiconductor layer  102   a , the current can be uniformly spread throughout the entire second semiconductor layer  102   a  by the transparent conductive layer  30   a . The material of the transparent conductive layer  30   a  comprises a material being transparent to the light emitted from the active layer  103   a , such as indium tin oxide (ITO) or indium zinc oxide (IZO). 
     In another embodiment of the present application, after the step of forming the mesa, the step of forming the transparent conductive layer can be performed first and is followed by the step of forming the first insulating layer. 
     In another embodiment of the present application, after the step of forming the mesa, the step of forming the first insulating layer can be omitted so the step of forming the transparent conductive layer can be directly performed. 
     In an embodiment of the present application, following the step of forming the transparent conductive layer, as a top view in  FIG.  4 A  and a cross-sectional view in  FIG.  4 B  which is taken along line A-A′ of  FIG.  4 A  show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming the reflective structure. The reflective structure comprises a reflective layer  40   a  and/or a barrier layer  41   a , which can be directly formed on the transparent conductive layer  30   a  by sputter, vapor deposition, or the like, wherein the reflective layer  40   a  is formed between the transparent conductive layer  30   a  and the barrier layer  41   a . As the top view of the light-emitting device  1  or the light-emitting device  2  shows, an outer edge  401   a  of the reflective layer  40   a  can be disposed on the inner side or the outer side of the outer edge  301   a  of the transparent conductive layer  30   a , or disposed to overlap with the outer edge  301   a  of the transparent conductive layer  30   a , the outer edge  411   a  of the barrier layer  41   a  can be disposed on the inner side or the outer side of the outer edge  401   a  of the reflective layer  40   a  or provided to overlap with the outer edge  401   a  of the reflective layer  40   a.    
     In another embodiment of the present application, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure is directly performed after the step of forming the mesa or the step of forming the first insulating layer. The reflective layer  40   a  and/or the barrier layer  41   a  is directly formed on the second semiconductor layer  102   a , and the reflective layer  40   a  is formed between the second semiconductor layer  102   a  and the barrier layer  41   a.    
     The reflective layer  40   a  includes one layer or multiple layers, such as a Distributed Bragg reflector (DBR). The material of the reflective layer  40   a  comprises a metal material having a high reflectance, for example, silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The high reflectance referred to herein means having 80% or more reflectance for a wavelength of a light emitted from the light-emitting device  1  or the light-emitting device  2 . In an embodiment of the present application, the barrier layer  41   a  covers the reflective layer  40   a  to prevent the surface of the reflective layer  40   a  from being oxidized that deteriorates the reflectivity of the reflective layer  40   a . The material of the barrier layer  41   a  comprises metal material, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer  41   a  includes one layer or multiple layers, such as titanium (Ti)/aluminum (Al) and/or titanium (Ti)/tungsten (W). In an embodiment of the present application, the barrier layer  41   a  comprises titanium (Ti)/aluminum (Al) on one side away from the reflective layer  40   a  and titanium (Ti)/tungsten (W) on another side adjacent to the reflective layer  40   a . In one embodiment of the present application, the material of the reflective layer  40   a  and the barrier layer  41   a  preferably includes a metal material other than gold (Au) or copper (Cu). 
     In an embodiment of the present application, following the step of forming the reflective structure, as a top view in  FIG.  5 A , a cross-sectional view in  FIG.  5 B  which is taken along line A-A′ of  FIG.  5 A , and a cross-sectional view in  FIG.  5 C  which is taken along line B-B′ of FIG.  5 A show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming the second insulating layer. A second insulating layer  50   a  can be formed on the semiconductor structure  1000   a  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form a first group of second insulating openings  501   a  to expose the first semiconductor layer  101   a  and a second group of second insulating openings  502   a  to expose the reflective layer  40   a  or the barrier layer  41   a . During the patterning of the second insulating layer  50   a , the first insulating surrounding region  200   a  which covers the surrounding part  111   a  and the first group of first insulating covering regions  201   a  formed in the vias  100   a  are partially etched to expose the first semiconductor layer  101   a . A first group of first insulating layer openings  203   a  is formed in the vias  100   a  to expose the first semiconductor layer  101   a . In the present embodiment, as the top view in  FIG.  5 A  shows, the first group of second insulating openings  501   a  and the second group of second insulating openings  502   a  comprise different widths or numbers. The opening shape of the first group of second insulating openings  501   a  and the second group of second insulating openings  502   a  comprises circular, elliptical, rectangular, polygonal, or arbitrary shapes. In the present embodiment, as shown in  FIG.  5 A , the first group of second insulating openings  501   a  is separated from each other and arranged in a plurality of rows, and the first group of second insulating openings  501   a  is corresponding to the multiple vias  100   a  and the first group of first insulating openings  203   a . The second group of second insulating openings  502   a  is disposed close to one side of the substrate  11   a , such as the left side or the right side of the substrate  11   a . The second group of second insulating openings  502   a  is separated from each other and located between two adjacent rows of the first group of second insulating openings  501   a . The second insulating layer  50   a  includes one layer or multiple layers. When the second insulating layer  50   a  includes one layer, the second insulating layer  50   a  protects the sidewalls of the semiconductor structure  1000   a  to prevent destruction of the active layer  103   a  by subsequent processes. When the second insulating layer  50   a  includes multiple layers, the second insulating layer  50   a  comprises two or more layers having different refractive index materials alternately stacked to form a Distributed Bragg reflector (DBR), which can selectively reflect light of a specific wavelength. The second insulating layer  50   a  is formed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     Following the step of forming the second insulating layer, as a top view in  FIG.  6 A , a cross-sectional view in  FIG.  6 B  which is taken along line A-A′ of  FIG.  6 A  and a cross-sectional view in  FIG.  6 C  which is taken along line B-B′ of  FIG.  6 A  show, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming the contact layer. A contact layer  60   a  can be formed on the first semiconductor layer  101   a  and the second semiconductor layer  102   a  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form one or more contact layer openings  602   a  on the second group of second insulating openings  502   a  to expose the reflective layer  40   a  or the barrier layer  41   a , and define a pin region  600   a  at a geometric center in the top view of the light-emitting device  1  or the light-emitting device  2 . In the cross-sectional view of the light-emitting device  1  or the light-emitting device  2 , the contact layer opening  602   a  comprises a width larger than a width of any one of the second group of second insulating openings  502   a . In the top view of the light-emitting device  1  or the light-emitting device  2 , the multiple contact layer openings  602   a  are close to one side of the substrate  11   a , for example, to the left side or the right side of the substrate  11   a . The contact layer  60   a  includes one layer or multiple layers. In order to reduce the resistance in contact with the first semiconductor layer  101   a , the material of the contact layer  60   a  comprises metal material such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. In an embodiment of the present application, the material of the contact layer  60   a  comprises a metal material other than gold (Au), copper (Cu). In an embodiment of the present application, the material of the contact layer  60   a  comprises a metal having high reflectivity, such as aluminum (Al) or platinum (Pt). In an embodiment of the present application, one side of the contact layer  60   a  contacting with the first semiconductor layer  101   a  comprises chromium (Cr) or titanium (Ti) to increase the bonding strength with the first semiconductor layer  101   a.    
     In an embodiment of the present application, the contact layer  60   a  covers all the vias  100   a  and extends over the second semiconductor layer  102   a , wherein the contact layer  60   a  is insulated from the second semiconductor layer  102   a  by the second insulating layer  50   a  and contacts the first semiconductor layer  101   a  through the via  100   a . When an external current is injected into the light-emitting device  1  or the light-emitting device  2 , the current is conducted to the first semiconductor layer  101   a  by the multiple vias  100   a . In the present embodiment, two adjacent vias  100   a  located on the same row comprise a first shortest distance there between, any via  100   a  adjacent to the edge of the light-emitting device and the first outside wall  1003   a  of the first semiconductor layer  101   a  comprises a second shortest distance there between, wherein the first shortest distance is greater than the second shortest distance. 
     In another embodiment of the present application, the contact layer  60   a  covers the surrounding part  111   a  and the via  100   a , and extends over the second semiconductor layer  102   a , wherein the contact layer  60   a  is insulated from the second semiconductor layer  102   a  by the second insulating layer  50   a , and the contact layer  60   a  contacts the first semiconductor layer  101   a  by the surrounding part  111   a  and the via  100   a . When an external current is injected into the light-emitting device  1  or the light-emitting device  2 , one part of the current is conducted to the first semiconductor layer  101   a  by the surrounding part  111   a  and other part is conducted to the first semiconductor layer  101   a  through the multiple vias  100   a . In the present embodiment, two adjacent vias  100   a  located on the same row comprise a first shortest distance there between. Any via  100   a  adjacent to the edge of the light-emitting device and the first outside wall  1003   a  of the first semiconductor layer  101   a  comprises a second shortest distance there between, wherein the first shortest distance is smaller than or equal to the second shortest distance. 
     In another embodiment of the present application, the multiple vias  100   a  can be arranged in a first row and a second row. A first shortest distance is between two adjacent vias  100   a  in the same row and a second shortest distance is between the via  100   a  located in the first row and the via  100   a  in the second row, wherein the first shortest distance is greater than or smaller than the second shortest distance. 
     In an embodiment of the present application, the multiple vias  100   a  can be arranged in a first row, a second row and a third row. A first shortest distance is between the via  100   a  in the first row and the via  100   a  in the second row and a second shortest distance is between the via  100   a  in the second row and the via  100   a  in the third row, where the first shortest distance is smaller than the second shortest distance. 
     In an embodiment of the present application, following the step of forming the contact layer, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming a third insulating layer. As a top view in  FIG.  7 A , a cross-sectional view in  FIG.  7 B  which is taken along line A-A′ of  FIG.  7 A , and a cross-sectional view in  FIG.  7 C  which is taken along line B-B′ of  FIG.  7 A  show, a third insulating layer  70   a  can be formed on the semiconductor structure  1000   a  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form a first group of third insulating openings  701   a  on the contact layer  60   a  to expose the contact layer  60   a  shown in  FIG.  6 A  and form a second group of third insulating openings  702   a  on the one or more contact layer openings  602   a  to expose the reflective layer  40   a  or the barrier layer  41   a  shown in  FIG.  6 A , wherein the contact layer  60   a  on the second semiconductor layer  102   a  is interposed between the second insulating layer  50   a  and the third insulating layer  70   a , the first group of third insulating openings  701   a , and the first group of second insulating openings  501   a  are offset from each other and do not overlap each other. The pin region  600   a  is surrounded and covered by the third insulating layer  70   a . In the present embodiment, as shown in  FIG.  7 A , the first group of third insulating openings  701   a  is separated from each other and is offset from the multiple vias  100   a . The second group of third insulating openings  702   a  is separated from each other and respectively corresponding to the multiple contact layer openings  602   a . As shown in the top view of  FIG.  7 A , the first group of third insulating openings  701   a  is close to one side of the substrate  11   a , for example, the right side, and the second group of third insulating openings  702   a  is close to another side of the substrate  11   a , for example, the left side of the substrate  11   a . In the cross-sectional view of the light-emitting device  1  or the light-emitting device  2 , any of the second group of third insulating openings  702   a  comprises a width smaller than the width of any of the contact layer openings  602   a , the third insulating layer  70   a  is filled to cover the sidewall of the contact layer opening  602   a  along the contact layer opening  602   a , and exposes the reflective layer  40   a  or the barrier layer  41   a  to form the second group of third insulating openings  702   a . The third insulating layer  70   a  includes one layer or multiple layers. When the third insulating layer  70   a  includes multiple layers, the third insulating layer  70   a  includes two or more layers having different refractive index alternately stacked to form a Distributed Bragg reflector (DBR), which can selectively reflects light of a specific wavelength. The third insulating layer  70   a  is formed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     Following the step of forming the third insulating layer, the manufacturing method of the light-emitting device  1  or the light-emitting device  2  comprises a step of forming a pad. As shown in the top view of  FIG.  8   , a first pad  80   a  and a second pad  90   a  can be formed on the one or more semiconductor structures  1000   a  by plating, sputter or vapor deposition, and then patterned by lithography and etching. As the top view in  FIG.  8    shows, the first pad  80   a  is adjacent to one side of the line  11   a , for example, the right side, and the second pad  90   a  is adjacent to another side of the substrate  11   a , for example, the left side. The first pad  80   a  covers all of the first group of third insulating openings  701   a  to contact the contact layer  60   a , and is electrically connected to the first semiconductor layer  101   a  through the contact layer  60   a  and the via  100   a . The second pad  90   a  covers all the second group of third insulating openings  702   a  to contact the reflective layer  40   a  or the barrier layer  41   a , and is electrically connected to the second semiconductor layer  102   a  through the reflective layer  40   a  or the barrier layer  41   a . The first pad  80   a  comprises one or more first pad openings  800   a , and a first side  802   a  and a plurality of first recesses  804   a  extending from the first side  802   a  in a direction away from the second pad  90   a . The second pad  90   a  comprises one or more second pad openings  900   a , and a second side  902   a  and a plurality of second recesses  904   a  extending from the second side  902   a  in a direction away from the first pad  80   a . The positions of the first pad opening  800   a  and the position of the second pad opening  900   a  are substantially corresponding to the positions of the vias  100   a , and the positions of the first recess  804   a  and the position of the second recess  904   a  are substantially corresponding to the positions of the vias  100   a . In other words, the first pad  80   a  and the second pad  90   a  do not cover any via  100   a . The first pad  80   a  and the second pad  90   a  are formed to surround the via  100   a  and are formed around the via  100   a . The first pad opening  800   a  or the second pad opening  900   a  comprises a diameter larger than that of any via  100   a  and the first recess  804   a  or the second recess  904   a  comprises a width larger than the diameter of any via  100   a . In an embodiment of the present application, a plurality of first recesses  804   a  is substantially aligned to a plurality of second recesses  904   a  in a top view of the light-emitting device. In another embodiment of the present application, the plurality of first recesses  804   a  is offset from the plurality of second recesses  904   a  in the top view. In an embodiment of the present application, a shape of the first pad  80   a  is same as or different from a shape of the second pad  90   a  in the top view of the light-emitting device  1  or the light-emitting device  2 . 
       FIG.  9 A  is a cross-sectional view taken along line A-A′ of  FIG.  8   , and  FIG.  9 B  is a cross-sectional view taken along line B-B′ of  FIG.  8   . The light-emitting device  1  disclosed in the present embodiment is a flip chip type of light-emitting diode. The light-emitting device  1  comprises a substrate  11   a ; one or more semiconductor structures  1000   a  on the substrate  11   a ; a surrounding part  111   a  surrounding one or more semiconductor structures  1000   a ; and a first pad  80   a  and a second pad  90   a  formed on one or more semiconductor structures  1000   a . Each of the one or more semiconductor structures  1000   a  comprises a semiconductor stack  10   a  comprising a first semiconductor layer  101   a , a second semiconductor layer  102   a , and an active layer  103   a  between the first semiconductor layer  101   a  and the second semiconductor layer  102   a . The multiple semiconductor structures  1000   a  are connected to each other by the first semiconductor layer  101   a . As shown in  FIG.  8   ,  FIG.  9 A , and  FIG.  9 B , the second semiconductor layer  102   a  and the active layer  103   a  around the one or more semiconductor structures  1000   a  are removed to expose the first surface  1011   a  of the first semiconductor layer  101   a . In other words, the surrounding part  111   a  comprises a first surface  1011   a  of the first semiconductor layer  101   a  to surround the semiconductor structure  1000   a.    
     The light-emitting device  1  further comprises one or more vias  100   a  passing through the second semiconductor layer  102   a  and the active layer  103   a  to expose one or more second surfaces  1012   a  of the first semiconductor layer  101   a , and a contact layer  60   a  formed on the first surface  1011   a  of the first semiconductor layer  101   a  to surround the semiconductor structure  1000   a  and contact the first semiconductor layer  101   a  to form an electrical connection. The contact layer  60   a  is formed on the one or more second surfaces  1012   a  of the first semiconductor layer  101   a  to cover the one or multiple vias  100   a  and contact the first semiconductor layer  101   a  to form an electrical connection. In the present embodiment, as the top view of the light-emitting device  1  shows, the contact layer  60   a  comprises a total surface area larger than a total surface area of the active layer  103   a , or the contact layer  60   a  comprises a peripheral length larger than a peripheral length of the active layer  103   a.    
     In an embodiment of the present application, the first pad  80   a  and/or the second pad  90   a  cover the multiple semiconductor structures  1000   a.    
     In an embodiment of the present application, the first pad  80   a  comprises one or more first pad openings  800   a  and the second pad  90   a  comprises one or more second pad openings  900   a . The first pad  80   a  and the second pad  90   a  are formed at positions other than a position of the via  100   a , and the positions of the first pad opening  800   a , the second pad opening  900   a , and the via  100   a  are overlapping each other. 
     In an embodiment of the present application, as the top view of the light-emitting device  1  shows, the first pad  80   a  comprises the same shape as that of the second pad  90   a , for example, the first pad  80   a  and the second pad  90   a  comprise comb shape As shown in  FIG.  8   , a curvature radius of the first pad opening  800   a  of the first pad  80   a  and a curvature radius of the first recess  804   a  are respectively larger than a curvature radius of the via  100   a , and the first pad  80   a  is formed at a region other than the positions of the multiple vias  100   a . A curvature radius of the second pad opening  900   a  of the second pad  90   a  and a curvature radius of the second recess  904   a  are respectively larger than the curvature radius of the via  100   a , and the second pad  90   a  is formed at a region other than the position of the multiple vias  100   a.    
     In one embodiment of the present application, as the top view of the light-emitting device  1  shows, the shape of the first pad  80   a  is different from the shape of the second pad  90   a . For example, when the shape of the first pad  80   a  is rectangular, the shape of the second pad  90   a  is comb-shaped. The first pad  80   a  comprises a first pad opening  800   a  and the first pad  80   a  is formed in a region other than the multiple vias  100   a . The second pad  90   a  comprises the second recess  904   a  and/or the second pad opening  900   a  and the second pad  90   a  is formed at a region other than the multiple vias  100   a.    
     In an embodiment of the present application, the size of the first pad  80   a  is different from the size of the second pad  90   a , for example, the area of the first pad  80   a  is larger than that of the second pad  90   a . The first pad  80   a  and the second pad  90   a  include one layer or multiple layers composed of metal material. The materials of the first pad  80   a  and the second pad  90   a  comprise metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickle (Ni), platinum (Pt), or an alloy of the above materials. When the first pad  80   a  and the second pad  90   a  include multiple layers, the first pad  80   a  comprises a first upper pad  805   a  and a first lower pad  807   a , and the second pad  90   a  comprises a second upper pad  905   a  and a second lower pad  907   a . The upper pad and the lower pad have different functions. The function of the upper pad is used for soldering and wiring. The light-emitting device  1  can be flipped and mounted onto the package substrate by using solder bonding or AuSn eutectic bonding through the upper pad. The metal material of the upper pad comprises highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), or an alloy of the above materials. The upper pad includes one layer or multiple layers. In an embodiment of the present application, the material of the upper pad comprises nickel (Ni) or gold (Au), and the upper pad includes one layer or multiple layers. The function of the lower pad is for forming a stable interface with the contact layer  60   a , the reflective layer  40   a , or the barrier layer  41   a . For example, the lower pad improves the interface bonding strength between the first lower pad  807   a  and the contact layer  60   a , or enhances the interface bonding strength between the second lower pad  907   a  and the reflective layer  40   a  or between the second lower pad  907   a  and the barrier layer  41   a . Another function of the lower pad is to prevent tin (Sn) in the solder or AuSn from diffusing into the reflective structure that damages the reflectivity of the reflective structure. Therefore, the lower pad comprises a metal material other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), or an alloy of the above materials, the lower pad includes one layer or multiple layers. In an embodiment of the present application, the lower pad comprises multiple layers composed of titanium (Ti) and aluminum (Al), or multiple layers composed of chromium (Cr) and aluminum (Al). 
     In an embodiment of the present application, viewing from a cross-sectional aspect of the light-emitting device  1 , a portion of the contact layer  60   a  connected to the first semiconductor layer  101   a  is formed under the second pad  90   a.    
     In an embodiment of the present application, viewing from a cross-sectional aspect of the light-emitting device  1 , a portion of the contact layer  60   a  connected to the first semiconductor layer  101   a  is formed above the reflective layer  40   a  and/or the barrier layer  41   a.    
     In an embodiment of the present application, as a top view of the light-emitting device  1  shows, the via  100   a  comprises a maximum width smaller than a maximum width of the first pad opening  800   a ; and/or the via  100   a  comprises a maximum width smaller than a maximum width of the second pad opening  900   a.    
     In an embodiment of the present application, as a top view of the light-emitting device  1  shows, the multiple vias  100   a  are respectively formed in the plurality of first recesses  804   a  of the first pad  80   a  and the plurality of second recesses  904   a  of the second pad  90   a.    
       FIG.  10    is a cross-sectional view of a light-emitting device  2  according to an embodiment of the present application. As compared with the light-emitting device  1  in the above-described embodiment, the light-emitting device  2  further comprises a first buffer pad  810   a  and a second buffer pad  910   a  respectively under the first pad  80   a  and the second pad  90   a . The light-emitting device  2  comprises the same structure as that of the light-emitting device  1 , and therefore, the structure named by same terms or labelled by same numbers of the light-emitting device  1  in  FIG.  9    and the light-emitting device  2  in  FIG.  10    have the same structure, materials, or have the same function, which will be omitted in this embodiment or not repeat them in the following description. In the embodiment, the light-emitting device  2  comprises a first buffer pad  810   a  formed between the first pad  80   a  and the semiconductor stack  10   a  and a second buffer pad  910   a  formed between the second pad  90   a  and the semiconductor stack  10   a , wherein the first buffer pad  810   a  and the second buffer pad  910   a  cover part or all of the vias  100   a . In the embodiment, when multiple insulating layers are formed between the pads  80   a ,  90   a  and the semiconductor stack  10   a , the stress is formed during the boning of the pads  80   a  and  90   a  of the light-emitting device  2  and the solder or AuSn eutectic, which causes cracks between the pads  80   a ,  90   a  and the insulating layer. The buffer pads  810   a ,  910   a  are respectively formed between the pads  80   a ,  90   a  and the third insulating layer  70   a , and the first buffer pad  810   a  and the second buffer pad  910   a  cover all the vias  100   a . The first pad  80   a  and the second pad  90   a  are formed in positions other than the positions of the vias  100   a . In other words, the first pad  80   a  and the second pad  90   a  do not cover the via  100   a . The material of the buffer pad is selected and the thickness of the pad is reduced to reduce the stress generated between the pad and the insulating layer. 
     In another embodiment of the present application, as shown in  FIG.  10   , from the top view of the light-emitting device  2 , the shapes of the buffer pads  810   a ,  910   a  are respectively the same as those of the pads  80   a ,  90   a . For example, the first buffer pad  810   a  and the first pad  80   a  are comb-shaped. 
     In an embodiment of the present application, from the top view of the light-emitting device  2  (nor shown), the shapes of the buffer pads  810   a ,  910   a  are different from those of the pads  80   a ,  90   a . For example, the shape of the first buffer pad  810   a  is rectangular and the shape of the first pad  80   a  is comb. 
     In another embodiment of the present application, the sizes of the buffer pads  810   a ,  910   a  are respectively different from those of the pads  80   a ,  90   a . For example, the area of the first buffer pad  810   a  is larger than the area of the first pad  80   a  and the area of the second buffer pad  910   a  is larger than that of the second pad  90   a.    
     In another embodiment of the present application, a distance between the first pad  80   a  and the second pad  90   a  is larger than a distance between the first buffer pad  810   a  and the second buffer pad  910   a.    
     In another embodiment of the present application, the buffer pads  810   a ,  910   a  comprise a larger area than that of the pads  80   a ,  90   a  to release the stress of the pads  80   a ,  90   a  during the bonding. In a cross-sectional view of the light-emitting device  2 , the first buffer pad  810   a  comprises a width 1.5 to 2.5 times, preferably 2 times the width of the first pad  80   a.    
     In another embodiment of the present application, the buffer pads  810   a ,  910   a  respectively comprises an area larger than that of the pads  80   a ,  90   a  to release the stress of the pads  80   a ,  90   a  during the bonding. In a cross-sectional view of the light-emitting device  2 , the first buffer pad  810   a  comprises a distance extending outside an edge of the first pad  80   a , which is more than one times the thickness of the first buffer pad  810   a , preferably more than two times the thickness of the first buffer pad  810   a.    
     In another embodiment of the present application, the pads  80   a ,  90   a  comprise a thickness between 1 μm and 100 μm, preferably between 2 μm and 6 μm. Each of the buffer pads  810   a ,  910   a  comprises a thickness larger than 0.5 μm to release the stress of the bond pads  80   a ,  90   a  during bonding. 
     In another embodiment of the present application, each of the first buffer pad  810   a  and the second buffer pad  910   a  includes one layer or multiple layers composed of a metal material. The first buffer  810   a  and the second buffer  910   a  function as a stable interface with the contact layer  60   a , the reflective layer  40   a , or the barrier layer  41   a . For example, the first buffer pad  810   a  contacts the contact layer  60   a , and the second buffer pad  910   a  contacts the reflective layer  40   a  or the barrier layer  41   a . The buffer pads  810   a ,  910   a  comprise metal materials other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru) or osmium (Os) to prevent tin (Sn) in the solder or AuSn eutectic from diffusing into the light-emitting device. 
     In another embodiment of the present application, the first buffer pad  810   a  and/or the second buffer pad  910   a  includes multiple layers composed of metal materials, wherein the multiple layers comprises a high ductility layer and a low ductility layer to prevent the stress formed in the bonding between the pads  80   a ,  90   a  and the solder or AuSn from causing cracks in the insulating layer between the pads  80   a ,  90   a  and the semiconductor stack  10   a . The high ductility layer and the low ductility layer comprise metals having different Young&#39;s modulus. 
     In another embodiment of the present application, the high ductility layers of the first buffer pad  810   a  and the second buffer pad  910   a  comprise a thickness larger than or equal to a thickness of the low ductility layers of the first buffer pad  810   a  and the second buffer pad  910   a.    
     In another embodiment of the present application, the first buffer pad  810   a  and the second buffer pad  910   a  comprise multiple layers composed of a metal material. When the first buffer pad  80   a  and the second buffer pad  90   a  comprise multiple layers composed of metal material, one side of the first buffer pad  810   a  and one side of the first pad  80   a  contacting each other comprise same metal material, one side of the second buffer pad  910   a  and one side of the second pad  90   a  contacting each other comprise same metal material, such as chromium (Cr), nickel (Ni), titanium (Ti), or platinum (Pt) to improve the interface bonding strength between the pad and the buffer pad. 
     As shown in  FIG.  11 A  and  FIG.  11 B , a fourth insulating layer  110   a  can be formed on the first buffer pad  810   a  and the second buffer pad  910   a  by sputter or vapor deposition and patterned by lithography and etching. The first pad  80   a  and the second pad  90   a  are respectively formed on the first buffer pad  810   a  and the second buffer pad  910   a  by the above described method, wherein the fourth insulating layer  110   a  surrounds sidewalls of the first buffer pad  810   a  and the second buffer pad  910   a . The fourth insulating layer  110   a  includes one layer or multiple layers. When the fourth insulating layer  110   a  includes multiple layers, the fourth insulating layer  110   a  comprises two or more layers having different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR) which can selectively reflect light of a specific wavelength. The material of the fourth insulating layer  110   a  comprises nonconductive material comprising organic materials, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     In an embodiment of the present application, the manufacturing process of the first pad  80   a  and the second pad  90   a  directly follows the manufacturing process of the first buffer pad  810   a  and the second buffer pad  910   a . In another embodiment of the present application, after the manufacturing process of the first buffer pad  810   a  and the second buffer pad  910   a , the step of forming the fourth insulating layer  110   a  is performed first and the manufacturing process of the first pad  80   a  and the second pad  90   a  follows the fourth insulating layer  110   a.    
       FIGS.  12 A- 22    illustrate a manufacturing method of a light-emitting device  3  or a light-emitting device  4  in accordance with embodiments of the present application. 
     As shown in a top view of  FIG.  12 A  and a cross-sectional view of  FIG.  12 B  which is taken along line A-A′ of  FIG.  12 A , a manufacturing method of a light-emitting device  3  or a light-emitting device  4  comprises a step of forming a mesa, which includes providing a substrate  11   b  and forming a semiconductor stack  10   b  on the substrate  11   b , wherein the semiconductor stack  10   b  comprises a first semiconductor layer  101   b , a second semiconductor layer  102   b , and an active layer  103   b  between the first semiconductor layer  101   a  and the second semiconductor layer  102   a . The semiconductor stack  10   b  can be patterned by lithography and etching to remove a portion of the second semiconductor layer  102   b  and the active layer  103   b  to form one or multiple semiconductor structures  1000   b , and form a surrounding part  111   b  surrounding the one or multiple semiconductor structures  1000   b . The surrounding part  111   b  exposes a first surface  1011   b  of the first semiconductor layer  101   b . The one or multiple semiconductor structures  1000   b  comprises a first outside wall  1003   b , a second outside wall  1001   b , and an inside wall  1002   b , wherein the first outside wall  1003   b  is a sidewall of the first semiconductor layer  101   b , the second outside wall  1001   b  is a sidewall of the active layer  103   b  and/or a sidewall of the second semiconductor layer  102   b . One end of the second outside wall  1001   b  is connected to a surface  102   s  of the second semiconductor layer  102   b  and another end of the second outside wall  1001   b  is connected to the first surface  1011   b  of the first semiconductor layer  101   b . One end of the inside wall  1002   b  is connected to the surface  102   s  of the second semiconductor layer  102   b  and another end of the inside wall  1002   b  is connected to a second surface  1012   b  of the first semiconductor layer  101   b . The multiple semiconductor structures  1000   b  are connected to each other through the first semiconductor layer  101   b . As shown in  FIG.  12 B , an obtuse angle is formed between the inside wall  1002   b  of the semiconductor structure  1000   b  and the second surface  1012   b  of the first semiconductor layer  101   b . An obtuse angle or a right angle is formed between the first outside wall  1003   b  of the semiconductor structure  1000   b  and a surface  11   s  of the substrate  11   b . An obtuse angle is formed between the second outside wall  1001   b  of the semiconductor structure  1000   a  and the first surface  1011   b  of the first semiconductor layer  101   b . The surrounding part  111   b  surrounds the semiconductor structure  1000   b  and the top view of the surrounding part  111   b  is a rectangular or a polygonal shape. 
     In an embodiment of the present application, the light-emitting device  3  or the light-emitting device  4  comprises a side less than 30 mil. When an external current is injected into the light-emitting device  3  or the light-emitting device  4 , the surrounding part  111   b  surrounds the semiconductor structure  1000   b  to distribute the light field of the light-emitting device  3  or the light-emitting device  4  uniformly and reduce the forward voltage of the light-emitting device. 
     In an embodiment of the present application, the light-emitting device  3  or the light-emitting device  4  comprises a side larger than 30 mil. The semiconductor stack  10   b  can be patterned by lithography and etching to remove a portion of the second semiconductor layer  102   b  and the active layer  103   b  to form one or multiple vias  100   a  penetrating through the second semiconductor layer  102   b  and the active layer  103   b , wherein the one or multiple vias  100   a  expose one or more second surface  1012   b  of the first semiconductor layer  101   b . When an external current is injected into the light-emitting device  3  or the light-emitting device  4 , the surrounding part  111   a  and the multiple vias  100   b  are dispersedly disposed to distribute the light field of the light-emitting device  3  or the light-emitting device  4  uniformly and reduce the forward voltage of the light-emitting device. 
     In an embodiment of the present application, the one or multiple vias  100   b  comprises an opening having a shape, such as circular, ellipsoidal, rectangular, polygonal, or any shape. The multiple vias  100   b  are arranged into a plurality of rows and the vias  100   b  of adjacent two rows can be aligned with each other or staggered. 
     In an embodiment of the present application, the substrate  11   b  can be a growth substrate, for example, a gallium arsenide (GaAs) wafer for growing aluminum gallium indium phosphide (AlGaInP) or a sapphire (Al 2 O 3 ) wafer, gallium nitride (GaN) wafer, or silicon carbide (SiC) wafer for growing indium gallium nitride (InGaN). The semiconductor stack  10   b  comprises optical characteristics, such as light-emitting angle or wavelength distribution, and electrical characteristics, such as forward voltage or reverse current. The semiconductor stack  10   a  can be formed on the substrate  11   b  by organic metal chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor deposition (HVPE), or ion plating. 
     In an embodiment of the present application, the first semiconductor layer  101   b  and the second semiconductor layer  102   b , such as a cladding layer or a confinement layer, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first semiconductor layer  101   b  is an n-type semiconductor and the second semiconductor layer  102   b  is a p-type semiconductor. The active layer  103   b  is formed between the first semiconductor layer  101   b  and the second semiconductor layer  102   b . The electrons and holes combine in the active layer  103   b  under a current driving to convert electric energy into light energy to emit a light. The wavelength of the light emitted from the light-emitting device  3  or the light-emitting device  4  is adjusted by changing the physical and chemical composition of one or more layers in the semiconductor stack  10   b . The material of the semiconductor stack  10   b  comprises a group III-V semiconductor material, such as Al x In y Ga (1-x-y) N or Al x In y Ga (1-x-y) P, wherein 0≤x, y≤1; (x+y)≤1. According to the material of the active layer  103   b , when the material of the semiconductor stack  10   b  is AlInGaP series material, red light having a wavelength between 610 nm and 650 nm or yellow light having a wavelength between 550 nm and 570 nm can be emitted. When the material of the semiconductor stack  10   b  is InGaN series material, blue light having a wavelength between 450 nm and 490 nm or green light having a wavelength between 490 nm and 550 nm can be emitted. When the material of the semiconductor stack  10   b  is AlGaN series material, UV light having a wavelength between 400 nm and 250 nm can be emitted. The active layer  103   a  can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), a multi-quantum well structure (MQW). The material of the active layer  103   b  can be i-type, p-type, or n-type semiconductor. 
     Following the step of forming the mesa, as a top view of  FIG.  13 A  and a cross-sectional view of  FIG.  13 B  which is taken along line A-A′ of  FIG.  13 A  show, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a first insulating layer. A first insulating layer  20   b  can be formed on the semiconductor structure  1000   b  by sputter or vapor deposition, and patterned by lithography and etching to cover the first surface  1011   b  of the surrounding part  111   b  and the second surface  1012   b  of the via  100   b , and cover the second outside wall  1001   b  of the second semiconductor layer  102   b  and the active layer  103   b  of the semiconductor structure  1000   b  and the inside wall  1002   b  of the semiconductor structure  1000   b . The first insulating layer  20   b  comprises a first insulating surrounding region  200   b  covering the surrounding part  111   b , thereby the first surface  1011   b  of the first semiconductor layer  101   b  on the surrounding part  111   b  is covered by the first insulating surrounding region  200   b ; a first group of first insulating covering regions  201   b  covering the vias  100   b , thereby the second surfaces  1012   b  of the first semiconductor layer  101   b  on the via  100   b  are covered by the first group of first insulating covering regions  201   b ; and a second group of first insulating openings  202   b  exposing the surface  102   s  of the second semiconductor layer  102   b . The first group of first insulating covering regions  201   b  is separated from each other and is respectively corresponding to the multiple vias  100   b . The first insulating layer  20   b  includes one layer or multiple layers. When the first insulating layer  20   b  includes one layer, the first insulating layer  20   b  protects the sidewall of the semiconductor structure  1000   b  to prevent the active layer  103   b  from being destroyed by the following processes. When the first insulating layer  20   b  includes multiple layers, the first insulating layer  20   b  comprises two or more layers having different refractive indexes alternately stacked to form a Distributed Bragg reflector (DBR) which can selectively reflect light of a specific wavelength. The first insulating layer  20   b  is composed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     In an embodiment of the present application, following the step of forming the first insulating layer, as a top view in  FIG.  14 A  and a cross-sectional view in  FIG.  14 B  which is taken along line A-A′ of  FIG.  14 A  show, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a transparent conductive layer. A transparent conductive layer  30   a  can be formed on the semiconductor structure  1000   b  by sputter, vapor deposition or the like, and contacts the second semiconductor layer  102   b , wherein the transparent conductive layer  30   a  does not cover the via  100   b . As the top view of the light-emitting device  3  or the light-emitting device  4  shows, the transparent conductive layer  30   b  is substantially formed on the entire surface of the second semiconductor layer  102   b . Specifically, the transparent conductive layer  30   b  can be formed in the second group of first insulating openings  202   b  by sputter, vapor deposition or the like, wherein an outer edge  301   b  of the transparent conductive layer  30   b  is spaced apart from the first insulating layer  20   b  with a distance to expose the surface  102   s  of the second semiconductor layer  102   b . The transparent conductive layer  30   b  comprises one or multiple transparent conductive layer openings  300   b  respectively corresponding to the one or multiple vias and/or the first group of first insulating covering regions  201   b , wherein the outer edge  301   b  of the transparent conductive layer openings  300   b  is separated from the inside wall  1002   b  of the semiconductor structure  1000   b  and/or an outer edge of the via  100   b  with a distance and the outer edge of the transparent conductive layer openings  300   b  surrounds the outer edge of the via  100   b  or the first group of first insulating covering regions  201   b . The material of the transparent conductive layer  30   b  comprises a material transparent to the light emitted from the active layer  103   b , such as indium tin oxide (ITO) or indium zinc oxide (IZO). 
     In another embodiment of the present application, after the step of forming the mesa, the step of forming the transparent conductive layer can be performed first and is followed by the step of forming the first insulating layer. 
     In another embodiment of the present application, after the step of forming the mesa, the step of forming the first insulating layer can be omitted so the step of forming the transparent conductive layer can be directly performed. 
     In an embodiment of the present application, following the step of forming the transparent conductive layer, as a top view in  FIG.  15 A  and a cross-sectional view in  FIG.  15 B  which is taken along line A-A′ of  FIG.  15 A  show, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a reflective structure. The reflective structure comprises a reflective layer  40   b  and/or a barrier layer  41   b , which can be directly formed on the transparent conductive layer  30   b  by sputter, vapor deposition, or the like, wherein the reflective layer  40   b  is formed between the transparent conductive layer  30   b  and the barrier layer  41   b . As the top view of the light-emitting device  3  or the light-emitting device  4  shows, the reflective layer  40   b  and/or the barrier layer  41   b  is substantially formed on the entire surface of the second semiconductor layer  102   b . An outer edge  401   b  of the reflective layer  40   b  may be disposed on the inner side or the outer side of the outer edge  301   b  of the transparent conductive layer  30   b , or may be disposed to overlap with the outer edge  301   b  of the transparent conductive layer  30   b . The outer edge  411   b  of the barrier layer  41   b  can be disposed on the inner side or the outer side of the outer edge  401   b  of the reflective layer  40   b  or provided to overlap with the outer edge  401   b  of the reflective layer  40   b . The reflective layer  40   b  comprises one or multiple reflective layer openings  400   b  respectively corresponding to the one or multiple vias  100   b . The barrier layer  41   b  comprises one or multiple barrier layer openings  410   b  respectively corresponding to the one or multiple vias  100   b . The transparent conductive layer openings  300   b , the reflective layer opening  400   b , and the barrier layer opening  410   b  overlap each other. An outer edge of the reflective layer opening  400   b  and/or an outer edge of the barrier layer opening  410   b  are separated from an outer edge of the via  100   b  with a distance, and the outer edge of the reflective layer opening  400   b  and/or the outer edge of the barrier layer opening  410   b  surround the outer edge of the via  100   b.    
     In another embodiment of the present application, the step of forming the transparent conductive layer can be omitted, and the step of forming the reflective structure is directly performed after the step of forming the mesa or the step of forming the first insulating layer. For example, the reflective layer  40   b  and/or the barrier layer  41   b  is directly formed on the second semiconductor layer  102   b  and the reflective layer  40   b  is formed between the second semiconductor layer  102   b  and the barrier layer  41   b . The reflective layer  40   b  includes one layer or multiple layers, such as a Distributed Bragg reflector (DBR). The material of the reflective layer  40   b  comprises a metal material having a high reflectance, for example, silver (Ag), aluminum (Al), or rhodium (Rh), or an alloy of the above materials. The high reflectance referred to herein means having 80% or more reflectance for a wavelength of a light emitted from the light-emitting device  3  or the light-emitting device  4 . In an embodiment of the present application, the barrier layer  41   b  covers the reflective layer  40   b  to prevent the surface of the reflective layer  40   b  from being oxidized that deteriorates the reflectivity of the reflective layer  40   b . The material of the barrier layer  41   b  comprises metal material, such as titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or an alloy of the above materials. The barrier layer  41   b  includes one layer or multiple layers, such as titanium (Ti)/aluminum (Al) and/or titanium (Ti)/tungsten (W). In an embodiment of the present application, the barrier layer  41   b  comprises titanium (Ti)/aluminum (Al) on one side away from the reflective layer  40   b  and titanium (Ti)/tungsten (W) on another side adjacent to the reflective layer  40   b . In an embodiment of the present application, the material of the reflective layer  40   b  and the barrier layer  41   b  comprises a metal material other than gold (Au) or copper (Cu). 
     In an embodiment of the present application, following the step of forming the reflective structure, as a top view in  FIG.  16 A , and a cross-sectional view in  FIG.  16 B  which is taken along line A-A′ of  FIG.  16 A  show, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a second insulating layer. A second insulating layer  50   b  can be formed on the semiconductor stack  10   b  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form a first group of second insulating openings  501   b  to expose the first semiconductor layer  101   b  and a second group of second insulating openings  502   b  to expose the reflective layer  40   b  or the barrier layer  41   b . During the patterning of the second insulating layer  50   b , the first insulating surrounding region  200   b  which covers the surrounding part  111   b  and the first group of first insulating covering regions  201   b  which covers the vias  100   b  are partially etched and a first group of first insulating openings  203   b  is formed in the vias  100   b  to expose the first semiconductor layer  101   b . In an embodiment of the present application, as shown in  FIG.  16 A , the first group of second insulating openings  501   b  are separated from each other and respectively corresponding to the multiple vias  100   b . The second group of second insulating openings  502   b  is close to one side of the substrate  11   b , for example, the left side or the right side of the substrate  11   b . In an embodiment, a number of the second group of second insulating openings  502   b  comprises one or more. In the embodiment, the second group of second insulating openings  502   b  is connected to each other to form an annular opening  5020   b . The shape of the annular opening  5020   b  comprises comb, rectangle, ellipse, circle, or polygon viewing from the top of the light-emitting device  3 . In an embodiment pf the present application, the second insulating layer  50   b  includes one layer or multiple layers. When the second insulating layer  50   b  includes multiple layers, the second insulating layer  50   b  comprises two or more layers having different refractive index alternately stacked to form a Distributed Bragg reflector (DBR) which can selectively reflect light of a specific wavelength. The second insulating layer  50   b  is composed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     Following the step of forming the second insulating layer, in an embodiment of the present application, as a top view of  FIG.  17 A  and a cross-sectional view in  FIG.  17 B  show, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a contact layer. A contact layer  60   b  can be formed on the semiconductor stack  10   b  by sputter or vapor deposition, etc., and then patterned by photolithography and etching to form a first contact layer  601   b  and a second contact layer  602   b . The first contact layer  601   b  covers all the first group of second insulating openings  501   b , fills into the one or multiple vias  100   b  to contact with the first semiconductor layer  101   b , and extends over the second insulating layer  50   b  and the second semiconductor layer  102   b , wherein the first contact layer  601   b  is insulated from the second semiconductor layer  102   b  by the second insulating layer  50   b . The second contact layer  602   b  is formed in the annular opening  5020   b  of the second insulating layer  50   b  to contact the reflective layer  40   b  and/or the barrier layer  41   b , wherein the sidewall  6021   b  of the second contact layer  602   b  and the sidewall  5021   b  of the annular opening  5020   b  are separated with a distance. The sidewall  6011   b  of the first contact layer  601   b  is separated from the sidewall  6021   b  of the second contact layer  602   b  with a distance. The first contact layer  601   b  does not contact the second contact layer  602   b  and the first contact layer  601   b  and the second contact layer  602   b  are electrically isolated by part of the second insulating layer  50   b . In the top view, the first contact layer  601   b  covers the surrounding part  111   b  of the semiconductor stack  10   b  such that the first contact layer  601   b  surrounds the second contact layer  602   b . In the top view of  FIG.  17 A , the second contact layer  602   b  is close to one side of the substrate  11   b , for example, the left or right side of the substrate  11   b . The contact layer  60   b  defines a pin region  600   b  at the geometric center in the top view of the semiconductor stack  10   b . The pin region  600   b  does not contact the first contact layer  601   b  and the second contact layer  602   b  and is electrically isolated from the first contact layer  601   b  and the second contact layer  602   b . The pin region  600   b  comprises the same material as that of the first contact layer  601   b  and/or the second contact layer  602   b . The pin region  600   b  serves as a structure for protecting the epitaxial stack to prevent the epitaxial stack from being damaged in the post process, such as die separation, die testing, or encapsulation. The contact layer  60   b  includes one layer or multiple layers. In order to reduce the resistance contacting the first semiconductor layer  101   b , the material of the contact layer  60   b  comprises a metal material, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickle (Ni), platinum (Pt), or an alloy of the above materials. In one embodiment of the application, the material of the contact layer  60   b  comprises a metal material other than gold (Au), copper (Cu). In an embodiment of the present application, the material of the contact layer  60   b  comprises a metal having high reflectivity, such as aluminum (Al) or platinum (Pt). In an embodiment of the present application, one side of the contact layer  60   b  contacting with the first semiconductor layer  101   b  comprises chromium (Cr) or titanium (Ti) to increase the bonding strength joining the first semiconductor layer  101   b.    
     In an embodiment of the present application, follow the contact layer forming step of  FIG.  17 A  and  FIG.  17 B , the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a third insulating layer. As a top view in  FIG.  18 A  and a cross-sectional view in  FIG.  18 B  which is taken along line A-A′ of  FIG.  18 A  show, a third insulating layer  70   b  can be formed on the semiconductor stack  10   b  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form a first third insulating opening  701   b  on the first contact layer  601   b  to expose the first contact layer  601   b  shown in  FIG.  17 A  and form a second third insulating opening  702   b  to expose the second contact layer  602   b  shown in  FIG.  17 A , wherein part of the first contact layer  601   b  formed on the second semiconductor layer  102   b  is interposed between the second insulating layer  50   b  and the third insulating layer  70   b . In the present embodiment, as shown in  FIG.  18 A , the first third insulating opening  701   b  and the second third insulating opening  702   b  are around the one or multiple vias  100   b . In the present embodiment, the first third insulating opening  701   b  and/or the second third insulating opening  702   b  is an annular opening and the shape of the annular opening comprises comb, rectangular, oval, circular, or polygon viewing from the top. In the top view of  FIG.  18 A , the first third insulating opening  701   b  is close to one side of the substrate  11   b , for example, the right side of the substrate  11   b . The second third insulating opening  702   b  is close to another side of the substrate  11   b , for example, the left side of the substrate  11   b . In the cross-sectional view, the first third insulating opening  701   b  comprises a width larger than a width of the second third insulating opening  702   b . The first third insulating layer  70   b  includes one layer or multiple layers. When the third insulating layer  70   b  includes multiple layers, the third insulating layer  70   b  comprises two or more layers having different refractive index alternately stacked to form a Distributed Bragg reflector (DBR) which can selectively reflect light of a specific wavelength. The third insulating layer  70   b  is composed of a non-conductive material comprising organic material, such as Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymers (COC), polymethylmethacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, fluorocarbon polymer, or inorganic material, such as silicone, glass, or dielectric material, such as aluminum oxide (Al 2 O 3 ), silicon nitride (SiN x ), silicon oxide (SiO x ), titanium oxide (TiO x ), or magnesium fluoride (MgF x ). 
     Following the step of forming the third insulating layer, the manufacturing method of the light-emitting device  3  or the light-emitting device  4  comprises a step of forming a pad. As shown in the top view of  FIG.  19   , a first pad  80   a  and a second pad  90   a  can be formed on the semiconductor stack  10   b  by plating, sputter or vapor deposition and then patterned by lithography and etching. As the top view in  FIG.  19    shows, the first pad  80   b  is adjacent to one side of the substrate  11   a , for example, the right side, and the second pad  90   b  is adjacent to another side of the substrate  11   b , for example, the left side. The first pad  80   b  contacts the first contact layer  601   b  through the first third insulating opening  701   b  and is electrically connected to the first semiconductor layer  101   b  through the first contact layer  601   b . The second pad  90   b  contacts the reflective layer  40   b  and/or the barrier layer  41   b  and is electrically connected to the second semiconductor layer  102   b  through the reflective layer  40   b  and/or the barrier layer  41   b . The first pad  80   b  comprises a plurality of first protrusions  801   b  and a plurality of first recesses  802   b  alternately connected to each other. The second pad  90   b  comprises a plurality of second protrusions  901   b  and a plurality of second recesses  902   b  alternately connected to each other. The position of the first recess  802   b  of the first pad  80   b  and the position of the second recess  902   b  of the second pad  90   b  substantially correspond to the positions of the vias  100   b . In other words, the first pad  801   b  and the second pad  802   b  do not cover any of the vias  100   b , the first recess  802   b  of the first pad  80   b , and the second recess  902   b  of the second pad  90   b  surround the via  100   b , and are formed around the via  100   b  such that the width of the first recess  802   b  of the first pad  80   b  or the width of the second recess  902   b  of the second pad  90   b  is larger than the diameter of any via  100   b . In an embodiment of the present application, the plurality of first recesses  802   b  is substantially aligned with the plurality of second recesses  902   b  in the top view. In another embodiment of the present application, the plurality of first recesses  802   b  is offset from the plurality of second recesses  902   b  in the top view. 
     In an embodiment of the present application, as shown in  FIG.  19   , the first pad  80   b  covers the first third insulating opening  701   b  and the second pad  90   b  covers the second third insulating opening  702   b . Since the first third insulating layer opening  701   b  comprises a maximum width greater than a maximum width of the second third insulating opening  702   b , the first pad  80   b  comprises a maximum width greater than a maximum width of the second pad  90   b . The first pad  80   b  and the second pad  90   b  comprise different sizes for the identification of the electrical connection of the pad and the solder pad during soldering to avoid the occurrence of bonding to the wrong electrical pad. 
     In an embodiment of the present application, the first third insulating opening  701   b  comprises an area larger or smaller than an area of the first pad  80   b  in the top view of the light-emitting device. 
     In another embodiment of the present application, a shortest distance between the first protrusion  801   b  and the second protrusion  901   b  is smaller than a maximum distance between the first recess  802   b  and the second recess  902   b.    
     In a another embodiment of the present application, the first pad  80   b  comprises a first flat edge  803   b  opposite to the first protrusion  801   b  and the first recess  802   b , and the second pad  90   b  comprises a second flat edge  903   b  opposite to the second protrusion  901   b  and the second recess  902   b . A maximum distance between the first flat edge  803   b  of the first pad  80   b  and the first protrusion  801   b  is larger than a shortest distance between the first protrusion  801   b  and the second protrusion  901   b . A maximum distance between the second flat edge  903   b  of the second pad  90   b  and the second protrusion  901   b  is larger than a shortest distance between the first protrusion  801   b  and the second protrusion  901   b.    
     In another embodiment of the present application, the curvature radius of the first plurality of first recesses  802   b  of the first pad  80   b  is different from the curvature radius of the plurality of first protrusions  801   b  of the first pad  80   b . For example, the curvature radius of the plurality of first recesses  802   b  of the first pad  80   b  is larger or smaller than the curvature radius of the plurality of first protrusions  801   b  of the first pad  80   b . In another embodiment of the application, the curvature radius of the plurality of second recesses  902   b  of the second pad  90   b  is larger or less than the curvature radius of the plurality of second protrusions  901   b  of the second pad  90   b.    
     In another embodiment of the present application, the curvature radius of the first protrusions  801   b  of the first pad  80   b  is larger or less than the curvature radius of the second protrusions  901   b  of the second pad  90   b.    
     In another embodiment of the present application, the plurality of first recesses  802   b  of the first pad  80   b  faces the plurality of second recesses  902   b  of the second pad  90   b  and the curvature radius of the plurality of first recesses  802   b  is larger or less than the curvature radius of the plurality of second recesses  902   b.    
     In another embodiment of the present application, the first pad  80   b  comprises a shape different from a shape of the second pad  90   b , for example, the first pad  80   b  comprises a rectangular shape, and the second pad  90   b  comprises a comb shape. 
     In another embodiment of the present application, the first pad  80   b  comprises a size different from a size of the second pad  90   b , for example, the first pad  80   b  comprises an area larger than an area of the second pad  90   b.    
       FIG.  20    is a cross-sectional view taken along line A-A′ of  FIG.  19   . In accordance with the embodiment, the light-emitting device  3  is a flip-chip type of light-emitting diode. The light-emitting deice  3  comprises a substrate  11   b  and one or multiple semiconductor structures  1000   b  on the substrate  11   b , wherein the semiconductor structure  1000   b  comprises a semiconductor stack  10   b  having a first semiconductor layer  101   b , a second semiconductor layer  102   b , and an active layer  103   b  between the first semiconductor layer  101   b  and the second semiconductor layer  102   b . The multiple semiconductor structures  1000   b  are connected to each other through the first semiconductor layer  101   b . The light-emitting deice  3  also comprises a surrounding part  111   b  surrounding the one or multiple semiconductor structures  1000   b  and a first pad  80   b  and a second pad  90   b  formed on the one or multiple semiconductor structures  1000   b , wherein the surrounding part  111   b  exposes a first surface  1011   b  of the first semiconductor layer  101   b . As shown in  FIG.  19    and  FIG.  20   , the one or multiple semiconductor structures  1000   b  respectively comprises a plurality of outside walls  1001   b  and a plurality of inside walls  1002   b . One end of the outside wall  1001   b  is connected to a surface  102   s  of the second semiconductor layer  102   b  and another end of the outside wall  1001   b  is connected to the first surface  1011   b  of the first semiconductor layer  101   b . One end of the inside wall  1002   b  is connected to the surface  102   s  of the second semiconductor layer  102   b  and another end of the inside wall  1002   b  is connected to a second surface  1012   b  of the first semiconductor layer  101   b.    
     In an embodiment of the present application, the light-emitting device  3  comprises a side larger than 30 mil and further comprises one or multiple vias penetrating through second semiconductor layer  102   b  and the active layer  103   b  to expose one or more second surfaces  1012   b . The light-emitting device  3  also comprises a contact layer  60   b  formed on the first surface  1011   b  of the first semiconductor layer  101   b  to surround the one or multiple semiconductor structures  1000   b  and contact the first semiconductor layer  101   b  for forming electrical connection, and the contact layer  60   b  is formed on the one or more second surfaces  1012   b  of the first semiconductor layer  101   b  to cover the one or multiple vias  100   b  and contact the first semiconductor layer  101   b  for forming electrical connection. The contact layer  60   b  comprises a first contact layer  601   b  and a second contact layer  602   b . The first contact layer  601   b  is formed on the second semiconductor layer, surrounds a sidewall of the second semiconductor layer, and is connected to the first semiconductor layer. The second contact layer  602   b  is formed on the second semiconductor layer and connected to the second semiconductor layer. The second contact layer  602   b  is surrounded by the first contact layer  601   b  while the first contact layer  601   b  and the second contact layer  602   b  do not overlap each other. 
     In an embodiment of the present application, the light-emitting device  3  does not comprise any via  100   b  in order to increase the light-emitting area. 
     In an embodiment of the present application, the contact layer  60   b  comprises a total surface area larger than a total surface area of the active layer  103   b  in the top view of the light-emitting device  3 . 
     In an embodiment of the present application, a total length of a periphery of the contact layer  60   b  is larger than a total length of a periphery of the active layer  103   b  in the top view of the light-emitting device  3 . 
     In an embodiment of the present application, the first contact layer  601   b  comprises an area larger than an area of the second contact layer  602   b  in the top view of the light-emitting device  3 . 
     In an embodiment of the present application, the first pad  80   b  and the second pad  90   b  are formed in positions outside the via  100   b . In other words, the via  100   b  is not covered by the first pad  80   b  or the second pad  90   b.    
     In an embodiment of the present application, the first contact layer  601   b  connected to the first semiconductor layer  101   b  is not disposed under the second pad  90   b  viewing from the cross-section of the light-emitting device  3 . 
     In an embodiment of the present application, a shortest distance between the first pad  80   b  and the second pad  90   b  is larger than 50 μm. 
     In an embodiment of the present application, a distance between the first pad  80   b  and the second pad  90   b  is smaller than 300 μm. 
     In an embodiment of the present application, the first pad  80   b  and the second pad  90   b  comprise a structure having one or more layers comprising a metal material. The materials of the first pad  80   b  and the second pad  90   b  comprise metal materials, such as chromium (Cr), titanium (Ti), tungsten (W), aluminum (Al), indium (In), tin (Sn), nickle (Ni), platinum (Pt), or an alloy of the above materials. When the first pad  80   b  and the second pad  90   b  include multiple layers, the first pad  80   b  comprises a first lower pad (not shown) and a first upper pad (not shown), and the second pad  90   b  comprises a second lower pad (not shown) and a second upper pad (not shown). The upper pad and the lower pad have different functions. The function of the upper pad is used for soldering and wiring. The light-emitting device  3  is flipped and mounted onto the package substrate by using solder bonding or AuSn eutectic bonding through the upper pad. The metal material of the upper pad comprises highly ductile materials such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), copper (Cu), gold (Au), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), osmium (Os), or an alloy of the above materials. The upper pad includes one layer or multiple layers. In an embodiment of the present application, the material of the upper pad comprises nickel (Ni) and/or gold (Au) and the upper pad includes one layer or multiple layers. The function of the lower pad is for forming a stable interface with the contact layer  60   b , the reflective layer  40   b , or the barrier layer  41   b , for example, to improve the interface bonding strength between the first lower pad and the contact layer  60   b , to enhance the interface bonding strength of the second lower pad and the reflective layer  40   b , or to enhance the interface bonding strength of the second lower pad and the barrier layer  41   b . Another function of the lower pad is to prevent tin (Sn) in the solder or AuSn from diffusing into the reflective structure and damaging the reflectivity of the reflective structure. Therefore, the lower pad comprises a metal material other than gold (Au) and copper (Cu), such as nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), tungsten (W), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), or osmium (Os), and the lower pad includes one layer or multiple layers. In an embodiment of the present application, the lower pad comprises multiple layers comprising titanium (Ti) and aluminum (Al), or chromium (Cr) and aluminum (Al). 
     In an embodiment of the present application, when the light-emitting device  3  is mounted on the package substrate in the form of flip-chip by means of a solder, a height difference H is between the first pad  80   b  and the second pad  90   b . As shown in  FIG.  20   , the second insulating layer  50   b  under the first pad  80   b  covers the reflective layer  40   b  and the second insulating layer  50   b  under the second pad  90   b  comprises the second insulating opening  502   b  to expose the reflective layer  40   b  or the barrier layer  41   b . When the first pad  80   b  and the second pad  90   b  are respectively formed in the first third insulating opening  701   b  and the second third insulating opening  702   b , the most top surface  80   s  of the first pad  80   b  is higher than the most top surface  90   s  of the second pad  90   b . In other words, the height difference H is between the most top surface  80   s  of the first pad  80   b  and the most top surface  90   s  of the second pad  90   b , and the height difference H between the first pad  80   b  and the second pad  90   b  is substantially the same as the thickness of the second insulating layer  50   b . In an embodiment, the height difference between the first pad  80   b  and the second pad  90   b  is between 0.5 μm and 2.5 μm. For example, the height difference between the first pad  80   b  and the second pad  90   b  is 1.5 μm. When the first pad  80   b  and the second pad  90   b  are respectively formed in the first third insulating layer opening  701   b  and the second third insulating layer opening  702   b , the first pad  80   b  contacts the first contact layer  601   b  through the first third insulating pad opening  701   b  and extends over partial surface of the second insulating layer  70   b  from the first third insulating pad opening  701   b . The second pad  90   b  contacts the second contact layer  601   b  through the second third insulating opening  702   b  and extends over partial surface of the third insulating layer  70   b  from the second third insulating opening  702   b.    
       FIG.  21    illustrates a top view of the light-emitting device  4  in accordance with an embodiment of the present application.  FIG.  22    illustrates a cross-sectional view of the light-emitting device  4  in accordance with an embodiment of the present application. As compared with the light-emitting device  3  in the above-described embodiment, in addition to the difference in the structure of the first pad and the second pad, the light-emitting device  4  comprises the same structure as that of the light-emitting device  3 , and therefore the structure named by same terms or labelled by same numbers of the light-emitting devices  3  and  4  will be omitted in this embodiment or not repeat them in the following description. When the light-emitting device  4  is mounted onto the package substrate in the form of flip chip by AuSn eutectic bonding, the height difference between the first pad  80   b  and the second pad  90   b  is preferably as small as possible to enhance the bonding stability between the pad and the package substrate. As shown in  FIG.  22   , the second insulating layer  50   b  under the first pad  80   b  covers the reflective layer  40   b  and the second insulating layer  50   b  under the second pad  90   b  comprises the second insulating opening  502   b  to expose the reflective layer  40   b  or the barrier layer  41   b . In the present embodiment, in order to reduce the height difference between the most top surface  80   s  of the first pad  80   b  and the most top surface  90   s  of the second pad  90   b , the first third insulating opening  701   b  comprises a width larger than that of the second third insulating opening  702   b . When the first pad  80   b  and the second pad  90   b  are respectively formed in the first third insulating layer opening  701   b  and the second third insulating layer opening  702   b , the whole first pad  80   b  is formed in the first third insulating layer opening  701   b  to contact the first contact layer  601   b . The second pad  90   b  is formed in the second third insulating opening  702   b  to contact the reflective layer  40   b  and/or the barrier layer  41   b . The second pad  90   b  extends from the second third insulating opening  702   b  to cover a partial surface of the third insulating layer  70   b . In other words, the third insulating layer is not formed under the first pad  80   b , but is partially formed under the second pad  90   b . In this embodiment, the height difference between the first pad  80   b  and the second pad  90   b  is smaller than 0.5 μm, preferably less than 0.1 μm, more preferably less than 0.05 μm. 
       FIG.  23    illustrates a cross-sectional view of the light-emitting device  5  in accordance with an embodiment of the present application. As compared with the light-emitting devices  3 ,  4  in the above-described embodiment, in addition to the difference in the structure of the second pad, the light-emitting device  5  comprises the same structure as those of the light-emitting devices  3 ,  4  and therefore, the structure named by same terms or labelled by same numbers of the light-emitting devices  3 ,  4  and  5  will be omitted in this embodiment or not repeat them in the following description. When the light-emitting device  5  is mounted onto the package substrate in the form of flip chip by AuSn eutectic bonding, the height difference between the first pad  80   b  and the second pad  90   b  is preferably as small as possible to enhance the bonding stability between the pad and the package substrate. As described above, in addition to forming a portion of the third insulating layer under the second pad  90   b , a second buffer pad  910   b  is formed under the second pad  90   b  to reduce the height difference between the top surface of the first pad  80   b  and the top surface of the second pad  90   b . As shown in  FIG.  23   , the second insulating layer  50   b  under the first pad  80   b  covers the reflective layer  40   b , and the second insulating layer  50   b  under the second pad  90   b  comprises the second insulating opening  502   b  to expose the reflective layer  40   b  or barrier layer  41   b . In the embodiment, the whole first pad  80   b  is formed in the first third insulating opening  701   b  to contact the first contact layer  601   b , and the whole second pad  90   b  is formed in the second third insulating opening  702   b  to contact the second contact layer  602   b . In other words, the third insulating layer does not formed under the first pad  80   b  and the second pad  90   b . In the embodiment, the second buffer pad  910   b  is formed between the second pad  90   b  and the second contact layer  602   b  to reduce the height difference between the top surface of the first pad  80   b  and the top surface of the second pad  90   b , wherein the second buffer pad  910   b  comprises a metal material other than gold (Au) and copper (Cu), such as chromium (Cr), nickel (Ni), cobalt (Co), iron (Fe), titanium (Ti), platinum (Pt), palladium (Pd), rhodium (Rh), iridium (Ir), ruthenium (Ru), zirconium (Zr), molybdenum (Mo), tantalum (Ta), aluminum (Al), or osmium (Os) to prevent tin (Sn) of the AuSn eutectic from diffusing into the light-emitting device  5 . In the embodiment, the height difference between the top surface of the first pad  80   b  and the top surface of the second pad  90   b  is less than 0.5 preferably less than 0.1 more preferably less than 0.05 In the present embodiment, the second buffer pad  910   b  comprises a thickness substantially same as the thickness of the second insulating layer  50   b.    
       FIG.  24    illustrates a cross-sectional view of the light-emitting device  6  in accordance with an embodiment of the present application. As compared with the light-emitting devices  3 ,  4  in the above-described embodiment, in addition to the difference in the structure of the third insulating layer  70   b  under the first pad  80   b , the light-emitting device  6  comprises the same structure as that of the light-emitting devices  3 ,  4  and therefore, the structure named by same terms or labelled by same numbers of the light-emitting devices  3 ,  4  and  6  will be omitted in this embodiment or not repeat them in the following description. As shown in  FIG.  24   , the third insulating layer  70   b  can be formed on the semiconductor stack  10   b  by sputter or vapor deposition, etc., and then patterned by lithography and etching to form the first third insulating openings  701   b  on the first contact layer  601   b  to expose the first contact layer  601   b  and the second third insulating opening  702   b  on the second contact layer  602   b  to expose the second contact layer  602   b . The first pad  80   b  and the second pad  90   b  can be formed on the semiconductor stack  10   b  by plating, sputter or vapor deposition, and then patterned by lithography and etching. The first pad  80   b  contacts the first contact layer  601   b  through the first third insulating openings  701   b  and is electrically connected to the first semiconductor layer  101   b  through the first contact layer  601   b . In the etching process for forming the first third insulating opening  701   b , the first contact layer  601   b  and the second insulation layer  50   b  under the first pad  80   b  may be over etched that exposes the reflective layer  40   b  and/or the barrier layer  41   b . In the embodiment, an area of the first third insulating opening  701   b  is reduced, and a first portion of the third insulating layer  70   b  is formed between the first pad  80   b  and the first contact layer  601   b  and the first portion of the third insulating layer  70   b  is entirely covered by the first pad  80   b . A second portion of the third insulating layer  70   b  is formed around the first pad  80   b . The first third insulating opening  701   b  is formed between the first portion and the second portion of the third insulating layer  70   b . Specifically, the first portion of the third insulating layer  70   b  completely covered by the first pad  80   b  comprises a width wider than that of the first third insulating opening  701   b  under the pad  80   b . In the present embodiment, the first third insulating opening  701   b  is an annular opening in the top view of the light-emitting device. 
       FIG.  25    is a schematic view of a light-emitting apparatus according to an embodiment of the present application. The light-emitting device  1 ,  2 ,  3 ,  4 ,  5 , or  6  in the foregoing embodiment is mounted on the first spacer  511  and the second spacer  512  of the package substrate  51  in the form of flip chip. The first spacer  511  and the second spacer  512  are electrically insulated from each other by an insulating portion  53  comprising an insulating material. The main light-extraction surface of the flip-chip type of light-emitting diode is one side of the growth substrates  11   a  and  11   b  opposite to the electrode-forming surface. A reflective structure  54  can be provided around the light-emitting devices  1 ,  2 ,  3 ,  4 ,  5 , or  6  to increase the light extraction efficiency of the light-emitting apparatus. 
       FIG.  26    illustrates a structure diagram of a light-emitting apparatus in accordance with an embodiment of the present application. A light bulb  600  comprises an envelope  602 , a lens  604 , a light-emitting module  610 , a base  612 , a heat sink  614 , a connector  616  and an electrical connecting device  618 . The light-emitting module  610  comprises a submount  606  and a plurality of light-emitting devices  608  on the submount  606 , wherein the plurality of light-emitting devices  608  can be the light-emitting device  1 ,  2 ,  3 ,  4 ,  5  or  6  described in above embodiments. 
     The principle and the efficiency of the present application illustrated by the embodiments above are not the limitation of the application. Any person having ordinary skill in the art can modify or change the aforementioned embodiments. Therefore, the protection range of the rights in the application will be listed as the following claims.