Patent Publication Number: US-2018047702-A1

Title: Bumpless build-up layer package with a pre-stacked microelectronic devices

Description:
CLAIM OF PRIORITY 
     This is a Continuation of application Ser. No. 15/170,833 filed Jun. 1, 2016, which is a Continuation of application Ser. No. 14/269,318 filed May 5, 2014 now U.S. Pat. No. 9,362,253 issued Sep. 28, 2014, which is a Continuation of application Ser. No. 12/868,816 filed Aug. 26, 2010 now U.S. Pat. No. 8,754,516 issued Jun. 17, 2014, which are hereby incorporated by reference. 
    
    
     BACKGROUND 
     Embodiments of the present description generally relate to the field of microelectronic device package designs and, more particularly, to a microelectronic device package having pre-stacked microelectronic devices in a bumpless build-up layer (BBUL) design. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which: 
         FIGS. 1-9  illustrate side cross-sectional views of a process of forming a microelectronic device package having pre-stacked microelectronic devices in a bumpless build-up layer design. 
         FIG. 10  illustrates a side cross-sectional view of another embodiment of a microelectronic device package having pre-stacked microelectronic devices in a bumpless build-up layer design. 
     
    
    
     DETAILED DESCRIPTION 
     In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description. 
     Embodiments of the present description relate to the field of fabricating microelectronic packages, wherein a first microelectronic device having through-silicon vias may be stacked with a second microelectronic device and used in a bumpless build-up layer package. 
       FIGS. 1-8  illustrate cross-sectional views of an embodiment of a process of forming a bumpless build-up layer coreless (BBUL-C) microelectronic package. As shown in  FIG. 1 , a first microelectronic device  102  may be provided, wherein the first microelectronic device  102  includes an active surface  104 , an opposing back surface  106  that is substantially parallel to the first microelectronic device active surface  104 , and at least one side  108  extending from the first microelectronic device active surface  104  to the first microelectronic device back surface  106 . The first microelectronic device  102  may have an active portion  105  proximate the first microelectronic device active surface  104  and a substrate portion  107  extending from the first microelectronic device active portion  105  to the first microelectronic device back surface  106 . As will be understood to those skilled in the art, the first microelectronic device active portion  105  comprises the integrated circuitry and interconnections (not shown) of the first microelectronic device  102 . The first microelectronic device  102  may be any appropriate integrated circuit device including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, or the like. In one embodiment, the first microelectronic device  102  is a microprocessor. 
     The first microelectronic device  102  may have at least one conductive via extending through the first microelectronic device substrate portion  107  from the first microelectronic device back surface  106  to the first microelectronic device active portion  105 . Such a conductive via configuration is known as a through-silicon via  112 . The first microelectronic device through-silicon via(s)  112  may be in electrical communication with the integrated circuitry (not shown) in the first microelectronic device active portion  105 . Each first microelectronic device through-silicon via  112  may have a contact land  116  on the first microelectronic device back surface  106 . Although the first microelectronic device back surface contact lands are shown directly adjacent the first microelectronic device through-silicon vias  112 , it is understood that they may be positioned at any appropriate location on the first microelectronic die back surface with conductive traces forming electrical contact therebetween. The first microelectronic device through-silicon vias  112  and the first microelectronic device back surface contact lands  116  may be fabricated by any technique known in the art, including, but not limited to drilling (laser and ion), lithography, plating, and deposition, and may be made of any appropriate conductive material, including but not limited to copper, aluminum, silver, gold, or alloys thereof. 
     As shown in  FIG. 2 , a second microelectronic device  122  may be aligned with the first microelectronic device  102 . The second microelectronic device  122  may have an active surface  124 , a back surface  126  that is substantially parallel to the second microelectronic device active surface  124 , and at least one side  128  extending from the second microelectronic device active surface  124  to the second microelectronic device back surface  126 . The second microelectronic device  122  may further include at least one contact land  132  adjacent the microelectronic device active surface  124 , wherein the second microelectronic device contact lands  132  may be connected to integrated circuits (not shown) within the second microelectronic device  122 . The second microelectronic device  122  may be any appropriate integrated circuit device including but not limited to a microprocessor (single or multi-core), a memory device, a chipset, a graphics device, an application specific integrated circuit, or the like. In one embodiment, the second microelectronic device  122  is a memory device. The second microelectronic device contact lands  132  may be any appropriate conductive material, including but not limited to copper, aluminum, silver, gold, or alloys thereof. 
     As further shown in  FIG. 2 , the second microelectronic device  122  may be attached to the first microelectronic device  102  through a plurality of interconnects  136  (shown as solder balls) connecting the second microelectronic device contact lands  132  to the first microelectronic device back surface contact lands  116 , thereby forming a stacked structure  140 . An underfill material  138 , such as an epoxy material, may be disposed between the first microelectronic device back surface  106  and the second microelectronic device active surface  124 , and around the plurality of interconnects  136 . The underfill material  138  may enhance the structural integrity of the stacked structure  140 . 
     As shown in  FIG. 3 , the second microelectronic device back surface  126  may be attached to a carrier  150 , such as with a DBF (die backside film) or an adhesive (not shown), as known to those skilled in the art. An encapsulation material  152  may be disposed adjacent the second microelectronic device side(s)  128 , the first microelectronic side(s)  108 , and over the first microelectronic device active surface  104  including the first microelectronic device active surface contact land(s)  114 , thereby forming a front surface  154  of the encapsulation material  152 , as shown in  FIG. 4 . The placement of the second microelectronic device back surface  126  on the carrier  150  may result in a back surface  156  of the encapsulation material  152  being formed substantially planar with the second microelectronic device back surface  126 , thereby forming substrate  160 . 
     The encapsulation material  152  may be disposed by any process known in the art, including a laminated process, as will be understood to those skilled in the art, and may be any appropriate dielectric material, including, but not limited to silica-filled epoxies, such as are available from Ajinomoto Fine-Techno Co., Inc., 1-2 Suzuki-cho, Kawasaki-ku, Kawasaki-shi, 210-0801, Japan (Ajinomoto GX13, Ajinomoto GX92, and the like). 
     Vias  162  may be formed through the encapsulation material front surface  154  to expose at least a portion of each first microelectronic device active surface contact land  114 , as shown in  FIG. 5 . The vias  162  of  FIG. 5  may be formed by any technique known in the art, including but not limited to laser drilling, ion drilling, and lithography, as will be understood to those skilled in the art. A patterning and plating process may be used to fill the vias  162  to form conductive vias  164  and to simultaneously form first layer conductive traces  172 , as will be understood by those skilled in the art, as shown in  FIG. 6 . 
     As shown in  FIG. 7 , a build-up layer  170  may be formed on the encapsulation material front surface  154 . The build-up layer  170  may comprise a plurality of dielectric layers with conductive traces formed on each dielectric layer with conductive vias extending through each dielectric layer to connect the conductive traces on different layers. Referring to  FIG. 7 , the build-up layer  170  may comprise the first layer conductive traces  172  with a dielectric layer  174  formed adjacent the first layer conductive traces  172  and the encapsulation material front surface  154 . At least one trace-to-trace conductive via  176  may extend through the dielectric layer  174  to connect at least one first layer conductive trace  172  to a second layer conductive trace  178 . A solder resist material  180  may be patterned on the dielectric layer  174  and second layer conductive traces  178  having at least one opening  182  exposing at least a portion of the second layer conductive traces  178 . 
     As shown in  FIG. 8 , at least one external interconnect  184  may be formed on the second layer conductive traces  178  through patterned openings  182  in the solder resist material  180 . The external interconnects  184  may be a solder material and may be used to connect the build-up layer  170  to external components (not shown). 
     It is understood that although only one dielectric layer and two conductive trace layers are shown, the build-up layer  170  may be any appropriate number of dielectric layers and conductive trace layers. The dielectric layer(s), such as the dielectric layer  174 , may be formed by any technique known in the art and may be any appropriate dielectric material. The conductive trace layers, such as first layer conductive traces  172  and the second layer conductive traces  178 , and the conductive vias  176 , may be fabricated by any technique known in the art, including but not limited to plating and lithography, and may be made of any appropriate conductive material, including but not limited to copper, aluminum, silver, gold, or alloys thereof. 
     The carrier  150  may be removed, resulting in a microelectronic package  190 , as shown in  FIG. 9 . The stacking and encapsulation of the first microelectronic device  102  and the second microelectronic device  122  results in the microelectronic package  190  being sufficiently thick enough to prevent warpage in the microelectronic package  190 , which may result in a reduction in yield losses from solder ball bridging and/or non-contact opens, as will be understood to those skilled in the art. 
     Another embodiment of a microelectronic package  192  is shown in  FIG. 10 . In this embodiment, the first microelectronic device active surface  104  may be in electrical communication with the second microelectronic device active surface  124  through the interconnects  136  extending between the first microelectronic device active surface contact land  114  and the second microelectronic device contact lands  132 . The build-up layer  170  may be formed proximate on the first microelectronic device back surface and may be in electrical communication with the first microelectronic device through-silicon vias  112 . 
     It is also understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in  FIGS. 1-10 . The subject matter may be applied to other stacked device applications. Furthermore, the subject matter may also be used in any appropriate application outside of the microelectronic device fabrication field. Furthermore, the subject matter of the present description may be a part of a larger bumpless build-up package, it may include multiple stacked microelectronic dice, it may be formed at a wafer level, or any number of appropriate variations, as will be understood to those skilled in the art. 
     The detailed description has described various embodiments of the devices and/or processes through the use of illustrations, block diagrams, flowcharts, and/or examples. Insofar as such illustrations, block diagrams, flowcharts, and/or examples contain one or more functions and/or operations, it will be understood by those skilled in the art that each function and/or operation within each illustration, block diagram, flowchart, and/or example can be implemented, individually and/or collectively, by a wide range of hardware, software, firmware, or virtually any combination thereof. 
     The described subject matter sometimes illustrates different components contained within, or connected with, different other components. It is understood that such illustrations are merely exemplary, and that many alternate structures can be implemented to achieve the same functionality. In a conceptual sense, any arrangement of components to achieve the same functionality is effectively “associated” such that the desired functionality is achieved. Thus, any two components herein combined to achieve a particular functionality can be seen as “associated with” each other such that the desired functionality is achieved, irrespective of structures or intermediate components. Likewise, any two components so associated can also be viewed as being “operably connected”, or “operably coupled”, to each other to achieve the desired functionality, and any two components capable of being so associated can also be viewed as being “operably couplable”, to each other to achieve the desired functionality. Specific examples of operably couplable include but are not limited to physically mateable and/or physically interacting components and/or wirelessly interactable and/or wirelessly interacting components and/or logically interacting and/or logically interactable components. 
     It will be understood by those skilled in the art that terms used herein, and especially in the appended claims are generally intended as “open” terms. In general, the terms “including” or “includes” should be interpreted as “including but not limited to” or “includes but is not limited to”, respectively. Additionally, the term “having” should be interpreted as “having at least”. 
     The use of plural and/or singular terms within the detailed description can be translated from the plural to the singular and/or from the singular to the plural as is appropriate to the context and/or the application. 
     It will be further understood by those skilled in the art that if an indication of the number of elements is used in a claim, the intent for the claim to be so limited will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. Additionally, if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should typically be interpreted to mean “at least” the recited number. 
     The use of the terms “an embodiment,” “one embodiment,” “some embodiments,” “another embodiment,” or “other embodiments” in the specification may mean that a particular feature, structure, or characteristic described in connection with one or more embodiments may be included in at least some embodiments, but not necessarily in all embodiments. The various uses of the terms “an embodiment,” “one embodiment,” “another embodiment,” or “other embodiments” in the detailed description are not necessarily all referring to the same embodiments. 
     While certain exemplary techniques have been described and shown herein using various methods and systems, it should be understood by those skilled in the art that various other modifications may be made, and equivalents may be substituted, without departing from claimed subject matter or spirit thereof. Additionally, many modifications may be made to adapt a particular situation to the teachings of claimed subject matter without departing from the central concept described herein. Therefore, it is intended that claimed subject matter not be limited to the particular examples disclosed, but that such claimed subject matter also may include all implementations falling within the scope of the appended claims, and equivalents thereof.