Patent Publication Number: US-9898959-B2

Title: Control sub-unit, shift register unit, shift register, gate driving circuit and display device

Description:
The application is a U.S. National Phase Entry of International Application No. PCT/CN2015/087761 filed on Aug. 21, 2015, designating the United States of America and claiming priority to Chinese Patent Application 201510148924.0, filed on Mar. 31, 2015. The present application claims priority to and the benefit of the above-identified applications and the above-identified applications are incorporated by reference herein in their entirety. 
     TECHNICAL FIELD 
     The present disclosure relates to a control sub-unit, a shift register unit, a shift register, a gate driving circuit and a display device. 
     BACKGROUND 
     Organic light emitting diodes OLEDs have been increasingly applied in a high performance display field as a current-type light-emitting device due to its characteristics of self-luminance, rapid response, wide view angle, possibility of being produced on a flexible substrate and so on. OLED display devices can be divided into passive matrix driving OLED PMOLED and active matrix driving OLED AMOLED according to their different driving manners. It can be expected that the AMOLEDs will replace liquid crystal displays as a next generation of new flat-panel display due to its advantages of low manufacturing cost, high response rapid, power saving, possibility of being applied into DC driving of portable devices, wide range of operational temperature and so on. Therefore, AMOLED display panels have attracted a lot of attentions. 
     Generally, an AMOLED panel is driven by gate driving signals having a plurality of pulses. In addition, in a LCD panel, in order to ensure fully charging, gate driving signals having a plurality of pulses are also required for driving. However, it is impossible to generate a gate driving signal having a plurality of pulses by a single shift register currently. 
     SUMMARY 
     In at least one embodiment of the present disclosure, there are provided a control sub-unit, a shift register unit comprising the control sub-unit, a shift register comprising the shift register unit, a gate driving circuit comprising the shift register and a display device comprising the gate driving circuit, the shift register unit is capable of outputting a plurality of pulse signals. 
     According to one aspect of the present disclosure, there is provided a control sub-unit comprising a low level input terminal, a selection module and N sets of nodes, each set of nodes comprises a first control node and a second control node, when the first control node in one set of nodes among the N sets of nodes is at a high level and the second control node in said one set of nodes is at a low level, the selection module connects the second control nodes of the other N−1 sets of nodes to the low level input terminal, such that the first control nodes and the second control nodes in the other N−1 sets of nodes are all at the low level, wherein N is a positive integer larger than 1. 
     Optionally, N is 2. 
     Optionally, the selection module comprises: a first thin film transistor having a gate connected to the first control node in said one set of nodes, a first electrode connected to the first control node in the other set of nodes, and a second electrode connected to the low level input terminal; a second thin film transistor having a gate connected to the first control node in the other set of nodes, a first electrode connected to the first control node in said one set of nodes, and a second electrode connected to the low level input terminal; a third thin film transistor having a gate connected to the first control node in said one set of nodes, a first electrode connected to the low level input terminal, and a second electrode connected to the second control node in the other set of nodes; and a fourth thin film transistor having a gate connected to the first control node in the other set of nodes, a first electrode connected to the low level input terminal, and a second electrode connected to the second control node in said one set of nodes. 
     Optionally, each set of nodes further comprises a first feedback node, and the selection module further comprises: a first feedback suppression thin film transistor having a gate connected to the first control node in said one set of nodes, a first electrode connected to the first control node in the other set of nodes, and a second electrode connected to the first feedback node in the other set of nodes; and a second feedback suppression thin film transistor having a gate connected to the first control node in the other set of nodes, a first electrode connected to the first control node in said one set of nodes, and a second electrode connected to the first feedback node in said one set of nodes, wherein the first electrode of the first thin film transistor is connected to the first feedback node in the other set of nodes rather than the first control node in the other set of nodes, and the first electrode of the second thin film transistor is connected to the first feedback node in said one set of nodes rather than the first control node in said one set of nodes. 
     According to another aspect of the present disclosure, there is provided a shift register unit having a main output terminal and comprising a control sub-unit and N shift register sub-units, said N shift register sub-units are capable of outputting signals with predefined waveforms during different time periods, the control sub-unit is the above control sub-unit provided in the present disclosure, said N set of nodes of the control sub-unit are corresponding to said N shift register sub-units one by one. For any one set of nodes, the first control node of said one set of nodes is connected to a pull-up node of the shift register sub-unit corresponding to said one set of nodes, the second control node of said one set of nodes is connected to a pull-down node of the shift register sub-unit corresponding to said one set of nodes, such that, during an output phase of any one of said N shift register sub-units, the control sub-unit connects the pull-down nodes of other shift register sub-units to the low level input terminal so as to make said other shift register sub-units output a high impedance state. 
     Optionally, each of said shift register sub-units comprises a transfer module, an output module and a transfer output terminal. The transfer module comprises a transfer pull-up transistor and a transfer pull-down transistor, the transfer pull-up transistor has a gate connected to the pull-up node, a first electrode connected to a clock signal input terminal and a second electrode connected to a first electrode of the transfer pull-down transistor, the transfer pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, and the transfer output terminal is connected between the second electrode of the transfer pull-up transistor and the first electrode of the transfer pull-down transistor. The output module comprises an output pull-up transistor and an output pull-down transistor, the output pull-up transistor has a gate connected to the pull-up node, a first electrode connected to the clock signal input terminal, and a second electrode connected to a first electrode of the output pull-down transistor, the output pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, and the main output terminal is connected between the second electrode of the output pull-up transistor and the first electrode of the output pull-down transistor. 
     Optionally, in the control sub-unit, each set of nodes comprises a first feedback node, and the selection module further comprises: a first feedback suppression thin film transistor having a gate connected to the first control node in said one set of nodes, a first electrode connected to the first control node in the other set of nodes, and a second electrode connected to the first feedback node in the other set of nodes; and a second feedback suppression thin film transistor having a gate connected to the first control node in the other set of nodes, a first electrode connected to the first control node in said one set of nodes, and a second electrode connected to the first feedback node in said one set of nodes, wherein the first electrode of the first thin film transistor is connected to the first feedback node in the other set of nodes rather than the first control node in the other set of nodes, and the first electrode of the second thin film transistor is connected to the first feedback node in said one set of nodes rather than the first control node in said one set of nodes. Each of said shift register sub-units comprises a second feedback node. The first feedback node is connected to the second feedback node of the shift register sub-unit corresponding thereto. Wherein, when the pull-up node of one stage of two stages of shift register sub-units is at a high level, the second feedback node of said one stage of shift register sub-unit is also at a high level; when the pull-up node of the other stage of two stages of shift register sub-units is at a high level, the second feedback node of the other stage of shift register sub-unit is also at a high level. 
     Optionally, each of said shift register sub-units comprises a feedback module, the feedback module comprises a feedback pull-up transistor, a feedback pull-down transistor and a feedback output transistor, the feedback pull-up transistor has a gate connected to the pull-up node, a first electrode connected to a clock signal input terminal, and a second electrode connected to a first electrode of the feedback pull-down transistor, the transfer pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, the feedback output transistor has a gate connected to the transfer output terminal, a first electrode connected to the second feedback node and a second electrode connected between the second electrode of the feedback pull-up transistor and the first electrode of the feedback pull-down transistor. 
     According to another aspect of the present disclosure, there is provided a shift register comprising a plurality of shift register units connected in cascade, wherein the shift register unit is the above shift register unit as provided in the present disclosure, in two adjacent stages of shift register units, the plurality of shift register sub-units in a first stage of the two adjacent stages of shift register units are connected in cascade with the plurality of shift register sub-units in a second stage of the two adjacent stages of shift register units in one-to-one correspondence. 
     According to another aspect of the present disclosure, there is further provided a gate driving circuit comprising the above shift register as provided in the present disclosure. 
     According to another aspect of the present disclosure, there is further provided a display apparatus comprising the above gate driving circuit as provided in the present disclosure. 
     In the shift register unit as provided in the present disclosure, the control sub-unit is added to merge a plurality of signals, such that it can be achieved that one shift register unit outputs a plurality of signals. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic modular diagram of a shift register unit comprising a control sub-unit provided in embodiments of the present disclosure; 
         FIG. 2  is a schematic diagram of a first implementation of the control sub-unit provided in the embodiments of the present disclosure; 
         FIG. 3  is a schematic diagram of a second implementation of the control sub-unit provided in the embodiments of the present disclosure; 
         FIG. 4  shows schematic diagram of timing sequence of signals at pull-up nodes and pull-down nodes of individual shift register sub-units  201 ,  202  and  20 N, schematic diagram of timing sequence of output signals of the individual shift register sub-units  201 ,  202  and  20 N, and schematic diagram of timing sequence of an output signal of the shift register unit provided in the embodiments of the present disclosure, respectively; 
         FIG. 5  is a schematic diagram of a part of the shift register unit provided in the embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, specific implementations of the present disclosure would be described in detail in connection with the accompanying drawings. It should be understood that the specific implementations described herein are only used for illustration and explanation of the present disclosure, but not intended to make any limitation to the present disclosure. 
       FIG. 1  is a schematic modular diagram of a shift register unit provided in embodiments of the present disclosure, the shift register unit comprises a control sub-unit  100  provided in the embodiments of the present disclosure. The control sub-unit  100  comprises a low level input terminal VGL, a selection module and N sets of nodes. Each set of nodes comprises a first control node and a second control node, the selection module is configured to, when the first control node in one set of nodes among the N sets of nodes is at a high level and the second control node in said one set of nodes is at a low level, connect the second control nodes of the other N−1 sets of nodes to the low level input terminal, such that the first control nodes and the second control nodes in the other N−1 sets of nodes are all at the low level, wherein N is a positive integer larger than 1. 
     In the implementation as shown in  FIG. 1 , a first set of nodes of the control sub-unit  100  comprises the first control node Q 1 ′ and the second control node QB 1 ′; a second set of nodes of the control sub-unit  100  comprises the first control node Q 2 ′ and the second control node QB 2 ′; and so on, a N th  set of node of the control sub-unit  100  comprises the first control node QN′ and the second control node QBN′. 
     As shown in  FIG. 1 , the control sub-unit  100  provided in the embodiments of the present disclosure can be applied in the shift register unit. The shift register unit comprises N shift register sub-units each of which comprises a pull-up node and a pull-down node. Each of the shift register sub-units is corresponding to a set of node in the control sub-unit  100 . 
     For any one set of nodes, the first control node of said one set of nodes is connected to a pull-up node of the shift register sub-unit corresponding to said one set of nodes, the second control node of said one set of nodes is connected to a pull-down node of the shift register sub-unit corresponding to said one set of nodes. 
     Since one shift register unit comprises N shift register sub-units, when any one of said N shift register sub-units is in an output phase, the selection module connects the second control nodes of N−1 sets of nodes other than the set of nodes corresponding to the shift register sub-unit in the output phase to the low level input terminal VGL, such that the first control nodes and the second control nodes of the other N−1 sets of nodes are at a low level. For any one set of nodes, a level at the first control node is same as a level at the pull-up node of its corresponding shift register sub-unit, and a level at the second control node is same as a level at the pull-down node of its corresponding shift register sub-unit. Therefore, except the shift register sub-unit in the output phase, the pull-up nodes and the pull-down nodes of the other N−1 shift register sub-units are all at a low level, such that it can be achieved that the output terminals of the other N−1 shift register sub-units can output a high impedance state. 
     Therefore, with the control sub-unit provided in the embodiments of the present disclosure, it can be achieved that the shift register sub-unit outputs the high impedance state, and then it can be achieved that a scan signal with different waveforms can be outputted on a single gate line. 
     Beside application into the shift register unit, the control sub-unit provided in the embodiments of the present disclosure can also be applied in other circuit configuration. 
     In the embodiments of the present disclosure, specific value of N is not defined, and N is an integer larger than 1. 
     Of course, value of N is determined according to where the control sub-unit  100  is particularly applied. For example, when the control sub-unit  100  is used in the shift register unit, the value of N can be determined according to the number of the shift register sub-unit. When the shift register unit having the control sub-unit  100  comprises two stages of shift register sub-units, N is 2. 
     As shown in  FIG. 1 , as another aspect of the embodiments of the present disclosure, there is provided a shift register unit, wherein the shift register unit has a main output terminal  300 , the shift register unit comprises a control sub-unit  100  and N shift register sub-units (the shift register sub-unit  201 , the shift register sub-unit  202  the shift register sub-unit  20 N as shown in  FIG. 1 ), said N shift register sub-units are capable of outputting signals with predefined waveforms during different time periods, the control sub-unit  100  is the above control sub-unit provided in the present disclosure, said N set of nodes of the control sub-unit are corresponding to said N shift register sub-units one by one. For any one set of nodes, the first control node of said one set of nodes is connected to a pull-up node of the shift register sub-unit corresponding to said one set of nodes, the second control node of said one set of nodes is connected to a pull-down node of the shift register sub-unit corresponding to said one set of nodes, such that, during an output phase of any one of said N shift register sub-units, the control sub-unit connects the pull-down nodes of other shift register sub-units to the low level input terminal so as to make said other shift register sub-units output a high impedance state. 
     In  FIG. 1 , the pull-up node Q 1  of the shift register sub-unit  201  is connected to the first control node Q 1 ′ of the first set of nodes in the control sub-unit  100 , the pull-down node QB 1  of the shift register sub-unit  201  is connected to the second control node QB 1 ′ of the first set of nodes; the pull-up node Q 2  of the shift register sub-unit  202  is connected to the first control node Q 2 ′ of the second set of nodes in the control sub-unit  100 , the pull-down node QB 2  of the shift register sub-unit  202  is connected to the second control node QB 2 ′ of the second set of nodes in the control sub-unit  100 ; the pull-up node QN of the shift register sub-unit  20 N is connected to the first control node QN′ of the N th  set of nodes in the control sub-unit  100 , the pull-down node QBN of the shift register sub-unit  20 N is connected to the second control node QBN′ of the N th  set of nodes in the control sub-unit  100 . 
     A shift register sub-unit in the embodiments of the present disclosure is equivalent to a typical shift register unit, the output state of the shift register sub-unit in the embodiments of the present disclosure is controlled by levels at the pull-up node and at the pull-down node thereof. When the pull-up node and the pull-down node of the shift register sub-unit are both at a low level, the output terminal of the shift register unit is in a floating state for a load, the transistor shows a huge off-state resistance between the high or low level signal inside the shift register and the output terminal of the shift register, therefore the shift register sub-unit cannot output any signal, which is equivalent to outputting a high impedance state. 
     Two specific implementations of the control sub-unit are shown in  FIG. 2  and  FIG. 3 . As shown in  FIG. 2 , the control sub-unit has two sets of nodes, one set of nodes comprises the first control node Q 1 ′ and the second control node QB 1 ′; the other set of nodes comprises the first control node Q 2 ′ and the second control node QB 2 ′. 
     The selection module comprises: a first thin film transistor M 1 _ 2  having a gate connected to the first control node Q 1 ′ in said one set of nodes, a first electrode connected to the first control node Q 2 ′ in the other set of nodes, and a second electrode connected to the low level input terminal VGL; a second thin film transistor M 2 _ 2  having a gate connected to the first control node Q 2 ′ in the other set of nodes, a first electrode connected to the first control node Q 1 ′ in said one set of nodes, and a second electrode connected to the low level input terminal VGL; a third thin film transistor M 3  having a gate connected to the first control node Q 1 ′ in said one set of nodes, a first electrode connected to the low level input terminal VGL, and a second electrode connected to the second control node QB 2 ′ in the other set of nodes; and a fourth thin film transistor M 4  having a gate connected to the first control node Q 2 ′ in the other set of nodes, a first electrode connected to the low level input terminal VGL, and a second electrode connected to the second control node QB 1 ′ in said one set of nodes. 
     Hereinafter, the operational principle of the control sub-unit as shown in  FIG. 2  will be explained with reference to specific application of the control sub-unit, and detailed explanations are not given here. 
     As shown in  FIG. 3 , each set of nodes comprises a first feedback node, and the selection module further comprises: a first feedback suppression thin film transistor M 1 _ 1  having a gate connected to the first control node Q 1 ′ in said one set of nodes, a first electrode connected to the first control node Q 2 ′ in the other set of nodes and a second electrode connected to the first feedback node OFF_ 2 ′ in the other set of nodes; and a second feedback suppression thin film transistor M 2 _ 1  having a gate connected to the first control node Q 2 ′ in the other set of nodes, a first electrode connected to the first control node Q 1 ′ in said one set of nodes, and a second electrode connected to the first feedback node OFF_ 1 ′ in said one set of nodes. 
     As shown in  FIG. 3 , in case that the selection module comprises the first feedback suppression thin film transistor M 1 _ 1  and the second feedback suppression thin film transistor M 2 _ 1 , wherein the first electrode of the first thin film transistor M 1 _ 2  is connected to the first feedback node OFF_ 2 ′ in the other set of nodes rather than the first control node Q 2 ′ in the other set of nodes, and the first electrode of the second thin film transistor M 2 _ 2  is connected to the first feedback node OFF_ 1 ′ in said one set of nodes rather than the first control node Q 1 ′ in said one set of nodes. 
     Hereinafter, advantages of the first feedback suppression thin film transistor and the second feedback suppression thin film transistor will be described with reference to specific implementations, detailed description is not given here. 
     Further explanations will be given to the shift register unit provided in the embodiments of the present disclosure with reference to  FIG. 4 . 
     In case that the output terminals of the shift register sub-units  201 ,  202  . . .  20 N are not connected to the main output terminal  300  and the control sub-unit  100  is not set, during t 1  time period, the shift register sub-unit  201  outputs a first set of pulse signals (as shown in the signal line (g) in  FIG. 4 ), and all of the other shift register sub-units output a low level signal; during t 2  time period, the shift register sub-unit  202  outputs a second set of pulse signals (as shown in the signal line (h) in  FIG. 4 ), and all of the other shift register sub-units output a low level signal; . . . ; during tN time period, the shift register sub-unit  20 N outputs a N th  set of pulse signals (as shown in the signal line (i) in  FIG. 4 ), and all of the other shift register sub-units output a low level signal. 
     In case that the shift register sub-unit  201  is used individually (that is, the output terminal of the shift register sub-unit  201  is not connected to the output terminals of the other shift register sub-units), in order to output the waveform as shown in the signal line (g) in  FIG. 4  during t 1  time period, a level at the pull-up node Q 1  thereof is as shown in the signal line (a) in  FIG. 4 , and a level at the pull-down node QB 1  thereof is as shown in the signal line (b) in  FIG. 4 . It can be seen that the shift register sub-unit  201  outputs a high level when the pull-up node Q 1  is at a high level, and outputs a low level when the pull-down node QB 1  is at a high level. 
     In case that the shift register sub-unit  202  is used individually (that is, the output terminal of the shift register sub-unit  202  is not connected to the output terminals of the other shift register sub-units), in order to output the waveform shown in the signal line (h) in  FIG. 4  during t 2  time period, a level at the pull-up node Q 2  thereof is as shown in the signal line (c) in  FIG. 4 , and a level at the pull-down node QB 2  thereof is as shown in the signal line (d) in  FIG. 4 . It can be seen that the shift register sub-unit  202  outputs a high level when the pull-up node Q 2  is at a high level, and outputs a low level when the pull-down node QB 2  is at a high level. 
     In case that the shift register sub-unit  20 N is used individually (that is, the output terminal of the shift register sub-unit  20 N is not connected to the output terminals of the other shift register sub-units), in order to output the waveform shown in the signal line (i) in  FIG. 4  during tN time period, a level at the pull-up node QN thereof is as shown in the signal line (e) in  FIG. 4 , and a level at the pull-down node QBN thereof is as shown in the signal line (f) in  FIG. 4 . It can be seen that the shift register sub-unit  20 N outputs a high level when the pull-up node QN is at a high level, and outputs a low level when the pull-down node QBN is at a high level. 
     After the output terminals of the N shift register sub-units  201 ,  202  . . .  20 N are not connected to the main output terminal  300 , since the output terminals of the shift register sub-units  201 ,  202  . . .  20 N are connected to the main output terminal  300  and the control sub-unit  100  is set, during t 1  time period, the control sub-unit  100  controls that the pull-up nodes and the pull-down nodes of the shift register sub-units  202  . . .  20 N at a low level, such that all of the shift register sub-units  202  . . .  20 N output a high impedance state. Therefore, during t 1  time period, only the first pulse signal outputted from the shift register sub-unit  201  is outputted to the main output terminal  300 , and then to a gate line connected to the main output terminal via the main output terminal  300 . 
     Accordingly, during t 2  time period, the control sub-unit  100  controls that the pull-up nodes and the pull-down nodes of all the shift register sub-units other than the shift register sub-unit  202  at a low level, such that all the shift register sub-units other than the shift register sub-unit  202  output a high impedance state. Therefore, during t 2  time period, only the second pulse signal outputted from the shift register sub-unit  202  is outputted to the main output terminal  300 , and then to a gate line connected to the main output terminal via the main output terminal  300 . 
     Accordingly, during tN time period, the control sub-unit  100  controls that the pull-up nodes and the pull-down nodes of all the shift register sub-units other than the shift register sub-unit  20 N at a low level, such that all the shift register sub-units other than the shift register sub-unit  20 N output a high impedance state. Therefore, during tN time period, only the N th  pulse signal outputted from the shift register sub-unit  20 N is outputted to the main output terminal  300 , and then to a gate line connected to the main output terminal via the main output terminal  300 . 
     At last, the waveform of the signal outputted from the main output terminal  300  is as shown in the signal line (j) in  FIG. 4 . 
     In the shift register unit provided in the embodiments of the present disclosure, the control sub-unit is added to merge a plurality of signals, and there is no need for setting additional leading wires for signal lines, therefore design of a narrow bezel of a display panel can be achieved by adopting the shift register unit as provided in the embodiments of the present disclosure. 
     In the embodiments of the present disclosure, no specific limitation is made on the number of the shift register sub-units. As a specific implementation of the embodiments of the present disclosure, the shift register unit comprises two stages of shift register sub-units. 
     That is, the shift register unit comprises a shift register sub-unit  201  (referred to as “one stage of shift register sub-unit” hereinafter) and a shift register sub-unit  202  (referred to as “the other stage of shift register sub-unit” hereinafter). The shift register sub-unit  201  has a pull-up node Q 1  and a pull-down node QB 1 , the shift register sub-unit  202  has a pull-up node Q 2  and a pull-down node QB 2 . Accordingly, the control sub-units comprises two sets of nodes, one set of nodes comprises a first control node Q 1 ′ and a second control node QB 1 ′; and the other set of nodes comprises a first control node Q 2 ′ and a second control node QB 2 ′. 
     In order to not affect the signal output of the respective shift register sub-units in the shift register unit, optionally, each of the shift register sub-units comprises a transfer module, an output module and a transfer output terminal. 
     The transfer module comprises a transfer pull-up transistor and a transfer pull-down transistor, the transfer pull-up transistor has a gate connected to the pull-up node, a first electrode connected to a clock signal input terminal, and a second electrode connected to a first electrode of the transfer pull-down transistor, the transfer pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, and the transfer output terminal is connected between the second electrode of the transfer pull-up transistor and the first electrode of the transfer pull-down transistor. 
     The output module comprises an output pull-up transistor and an output pull-down transistor, the output pull-up transistor has a gate connected to the pull-up node, a first electrode connected to the clock signal input terminal, and a second electrode connected to a first electrode of the output pull-down transistor, the output pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, and the main output terminal is connected between the second electrode of the output pull-up transistor and the first electrode of the output pull-down transistor. 
     The output module is only used to provide signal to the main output terminal, the transfer module is used to provide a start signal to a next stage of shift register sub-unit and a reset signal to a previous stage of shift register sub-unit and a reset signal to a previous stage of shift register sub-unit via the transfer output terminal. The control sub-unit can achieve control on the output module and the transfer module. 
     In the embodiments of the present disclosure, no specific requirement is made on specific configuration of the control sub-unit  100  only if it can be ensured that, when one shift register sub-unit outputs a set of pulse signals, the pull-down nodes of the other shift register sub-units are pulled down. As a specific implementation of the embodiments of the present disclosure, when the shift register unit comprises two stages of shift register sub-units, as shown in  FIG. 2 , the control sub-unit comprises a first thin film transistor M 1 _ 2 , a second thin film transistor M 2 _ 2 , a third thin film transistor M 3  and a fourth thin film transistor M 4 . It can be seen from  FIG. 1  and  FIG. 2 , the gate of the first thin film transistor M 1 _ 2  is connected to the pull-up node Q 1  of one stage of shift register sub-unit in the two stages of shift register sub-units, the first electrode of the first thin film transistor M 1 _ 2  is connected to the pull-up node Q 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units, and the second electrode of the first thin film transistor M 1 _ 2  is connected to the low level input terminal VGL; the gate of the second thin film transistor M 2 _ 2  is connected to the pull-up node Q 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units, the first electrode of the second thin film transistor M 2 _ 2  is connected to the pull-up node Q 1  of said one stage of shift register sub-unit in the two stages of shift register sub-units, and the second electrode of the second thin film transistor M 2 _ 2  is connected to the low level input terminal VGL; the gate of the third thin film transistor M 3  is connected to the gate of the first thin film transistor M 1 _ 2 , the first electrode of the third thin film transistor M 3  is connected to the first second electrode of the first thin film transistor M 1 _ 2 , the second electrode of the third thin film transistor M 3  is connected to the pull-down node QB 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units; the gate of the fourth thin film transistor M 4  is connected to the gate of the second thin film transistor M 2 _ 2 , the first electrode of the fourth thin film transistor M 4  is connected to the second electrode of the first thin film transistor M 2 _ 2 , the second electrode of the fourth thin film transistor M 4  is connected to the pull-down node QB 1  of said one stage of shift register sub-unit in the two stages of shift register sub-units. 
     The operational principle of such control sub-unit will be introduced hereinafter. When said one stage of shift register sub-unit is in an output phase, its pull-up node Q 1  is at a high level and its pull-down node QB 1  is at a low level, and the pull-up node Q 2  of the other stage of shift register sub-unit is at a low level and the pull-down node QB 2  of the other stage of shift register sub-unit is at a high level, therefore the first thin film transistor M 1 _ 2  and the third thin film transistor M 3  are turned on, and the second thin film transistor M 2 _ 2  and the fourth thin film transistor M 4  are turned off. Therefore, the pull-down node QB 2  of the other stage of shift register sub-unit is connected to the low level input terminal VGL, and is pulled down to the low level VGL by aid of the low level input terminal VGL. At this time, the pull-up node Q 2  and the pull-down node QB 2  of the other stage of shift register sub-unit are both at a low level, the other stage of shift register sub-unit outputs a high impedance state and said one stage of shift register sub-unit outputs a high level signal to the main output terminal. 
     Similarly, when the other stage of shift register sub-unit is in an output phase, its pull-up node Q 2  is at a high level and its pull-down node QB 2  is at a low level, and the pull-up node Q 1  of said one stage of shift register sub-unit is at a low level and the pull-down node QB 1  of said one stage of shift register sub-unit is at a high level, therefore the second thin film transistor M 2 _ 2  and the fourth thin film transistor M 4  are turned on, and the first thin film transistor M 1 _ 2  and the third thin film transistor M 3  are turned off. Therefore, the pull-down node QB 1  of said one stage of shift register sub-unit is connected to the low level input terminal VGL, and is pulled down to the low level VGL by aid of the low level input terminal VGL. At this time, the pull-up node Q 1  and the pull-down node QB 1  of said one stage of shift register sub-unit are both at a low level, said one stage of shift register sub-unit outputs a high impedance state and the other stage of shift register sub-unit outputs a high level signal to the main output terminal. 
     As a specific implementation of the control sub-unit  100 , in order to ensure the thin film transistor being turned off, optionally, as shown in  FIG. 3 , the control sub-unit further comprises the first feedback suppression thin film transistor M 1 _ 1  and the second feedback suppression thin film transistor M 2 _ 1 . Under this circumstance, each set of nodes in the control sub-unit comprises a first feedback node. For example, in the implementation as shown in  FIG. 3 , one set of nodes of the control sub-unit comprises a first feedback node OFF_ 1 ′ and the other set of nodes of the control sub-unit comprises a first feedback node OFF_ 2 ′, the specific configuration of the first feedback suppression thin film transistor M 1 _ 1  and the second feedback suppression thin film transistor M 2 _ 1  have been described above, and repeated descriptions are omitted herein. Accordingly, each of the shift register sub-units shall comprises a second feedback node, and the first feedback node is connected to the second feedback node of its corresponding shift register sub-unit. 
     It should be noted that when the pull-up node Q 1  of said one stage of shift register sub-unit in the two stages of shift register sub-units is at a high level, the second feedback node of said one stage of shift register sub-unit is also at a high level; when the pull-up node Q 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units is at a high level, the second feedback node of the other stage of shift register sub-unit is also at a high level. 
     With arrangement of the first feedback suppression thin film transistor M 1 _ 1  and the second feedback suppression thin film transistor M 2 _ 1 , it can be ensured that the second thin film transistor M 2 _ 2  is turned off when said one stage of shift register unit is in an output phase and the first thin film transistor M 2 _ 1  is turned off when the other stage of shift register unit is in an output phase. 
     For example, when said one stage of shift register sub-unit is in an output phase, the pull-up node Q 1  is at a high level and the pull-down node QB 1  is at a low level, the second feedback node of said one stage of shift register sub-unit is at a high level, such that the first feedback node OFF_ 1 ′ connected to the second feedback node is also at a high level, therefore the first thin film transistor M 1 _ 2  and the third thin film transistor M 3  are turned on, and the second thin film transistor M 2 _ 2  and the fourth thin film transistor M 4  are totally turned off (it can be ensured that the second thin film transistor M 2 _ 2  and the fourth thin film transistor M 4  are totally turned off since the first feedback node OFF_ 1 ′ in said one set of nodes of the control sub-unit is at a high level which is obviously higher than a low level at the first control node Q 2 ′ in the other set of nodes of the control sub-unit). Therefore, the pull-down node QB 2  of the other stage of shift register sub-unit is connected to the low level input terminal VGL, and is pulled down to the low level VGL by aid of the low level input terminal VGL. At this time, the pull-up node Q 2  and the pull-down node QB 2  of the other stage of shift register sub-unit are both at a low level, the other stage of shift register sub-unit outputs a high impedance state and said one stage of shift register sub-unit outputs a high level signal to the main output terminal. 
     Similarly, when the other stage of shift register sub-unit is in an output phase, its pull-up node Q 2  is at a high level and its pull-down node QB 2  is at a low level, and the pull-up node Q 1  of said one stage of shift register sub-unit is at a low level and the pull-down node QB 1  of said one stage of shift register sub-unit is at a high level, therefore the second thin film transistor M 2 _ 2  and the fourth thin film transistor M 4  are turned on, and the first thin film transistor M 1 _ 2  and the third thin film transistor M 3  are totally turned off (it can be ensured that the first thin film transistor M 1 _ 2  and the third thin film transistor M 3  are totally turned off since the first feedback node OFF_ 2 ′ in the other set of nodes of the control sub-unit is at a high level which is obviously higher than a low level at the first control node Q 1 ′ in said one set of nodes of the control sub-unit). Therefore, the pull-down node QB 1  of said one stage of shift register sub-unit is connected to the low level input terminal VGL, and is pulled down to the low level VGL by aid of the low level input terminal VGL. At this time, the pull-up node Q 1  and the pull-down node QB 1  of said one stage of shift register sub-unit are both at a low level, said one stage of shift register sub-unit outputs a high impedance state and the other stage of shift register sub-unit outputs a high level signal to the main output terminal. 
     In the embodiments of the present disclosure, no specific limitation is made on the specific location of the second feedback node of said one stage of shift register sub-unit and the second feedback node of the other stage of shift register sub-unit, only if following conditions can be met: when the pull-up node Q 1  of said one stage of shift register sub-unit in the two stages of shift register sub-units is at a high level, the second feedback node of said one stage of shift register sub-unit is also at a high level; when the pull-up node Q 1  of said one stage of shift register sub-unit in the two stages of shift register sub-units is at a low level, the second feedback node of said one stage of shift register sub-unit is also at a low level; when the pull-up node Q 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units is at a high level, the second feedback node of the other stage of shift register sub-unit is also at a high level; when the pull-up node Q 2  of the other stage of shift register sub-unit in the two stages of shift register sub-units is at a low level, the second feedback node of the other stage of shift register sub-unit is also at a low level. 
     As a preferable implementation of the embodiments of the present disclosure, each of the shift register sub-units further comprises a feedback module, the feedback module comprises a feedback pull-up transistor, a feedback pull-down transistor and a feedback output transistor, the feedback pull-up transistor has a gate connected to the pull-up node, a first electrode connected to a clock signal input terminal, and a second electrode connected to a first electrode of the feedback pull-down transistor, the feedback pull-down transistor has a gate connected to the pull-down node and a second electrode connected to the low level input terminal, the feedback output transistor has a gate connected to the transfer output terminal, a first electrode connected to the second feedback node and a second electrode connected between the second electrode of the feedback pull-up transistor and the first electrode of the feedback pull-down transistor. 
     Part of a specific implementation of the shift register unit as provided in the embodiments of the present disclosure is shown in  FIG. 5 . As shown in  FIG. 5 , the shift register unit comprises a shift register sub-unit  201 , a shift register sub-unit  202  and a control sub-unit  100  connected between the shift register sub-unit  201  and the shift register sub-unit  202 . It should be noted that only a part of the shift register sub-unit  201  and a part of the shift register sub-unit  202  are shown in  FIG. 5 . 
     The shift register sub-unit  201  has the transfer output terminal CR 1 . The transfer module of the shift register sub-unit  201  comprises a transfer pull-up transistor M 51  and a transfer pull-down transistor M 61 , the transfer pull-up transistor M 51  has a gate connected to the pull-up node Q 1 , a first electrode connected to a clock signal input terminal CLKB 1 , and a second electrode connected to a first electrode of the transfer pull-down transistor M 61 , the transfer pull-down transistor M 61  has a gate connected to the pull-down node QB 1  and a second electrode connected to the low level input terminal VGL. 
     The output module of the shift register sub-unit  201  comprises an output pull-up transistor M 71  and an output pull-down transistor M 81 , the output pull-up transistor M 71  has a gate connected to the pull-up node Q 1 , a first electrode connected to the clock signal input terminal CLKB 1  and a second electrode connected to a first electrode of the output pull-down transistor M 81 , the output pull-down transistor M 81  has a gate connected to the pull-down node QB 1  and a second electrode connected to the low level input terminal VGL, and the main output terminal  300  is connected between the second electrode of the output pull-up transistor M 71  and the first electrode of the output pull-down transistor M 81 . 
     The feedback module of the shift register sub-unit  201  comprises a feedback pull-up transistor M 91 , a feedback pull-down transistor M 101  and a feedback output transistor M 111 . The feedback pull-up transistor M 91  has a gate connected to the pull-up node Q 1 , a first electrode connected to the clock signal input terminal CLKB 1  and a second electrode connected to a first electrode of the feedback pull-down transistor M 101 , the feedback pull-down transistor M 101  has a gate connected to the pull-down node QB 1  and a second electrode connected to the low level input terminal VGL. The feedback output transistor M 111  has a gate connected to the transfer output terminal CR 1 , a first electrode connected to the second feedback node OFF_ 1  and a second electrode connected between the second electrode of the feedback pull-up transistor M 91  and the first electrode of the feedback pull-down transistor M 92 . 
     When the pull-up node Q 1  is at a high level and the pull-down node QB 1  is at a low level, the shift register sub-unit  201  outputs a high level to the main output terminal  300 , and the transfer output terminal CR 1  outputs a high level, such that the feedback output transistor M 111  is turned on and the drain of the feedback output transistor M 111  is at a high level (that is, the first electrode of the feedback output transistor M 111  is at the high level of the clock signal input terminal CLKB 1 ), and thus the second feedback node OFF_ 1  is at a high level. 
     The shift register sub-unit  202  has the transfer output terminal CR 2 . The transfer module of the shift register sub-unit  202  comprises a transfer pull-up transistor M 52  and a transfer pull-down transistor M 62 , the transfer pull-up transistor M 52  has a gate connected to the pull-up node Q 2 , a first electrode connected to a clock signal input terminal CLKB 2  and a second electrode connected to a first electrode of the transfer pull-down transistor M 62 , the transfer pull-down transistor M 62  has a gate connected to the pull-down node QB 2  and a second electrode connected to the low level input terminal VGL. 
     The output module of the shift register sub-unit  202  comprises an output pull-up transistor M 72  and an output pull-down transistor M 82 , the output pull-up transistor M 72  has a gate connected to the pull-up node Q 2 , a first electrode connected to the clock signal input terminal CLKB 2  and a second electrode connected to a first electrode of the output pull-down transistor M 82 , the output pull-down transistor M 82  has a gate connected to the pull-down node QB 2  and a second electrode connected to the low level input terminal VGL, and the main output terminal  300  is connected between the second electrode of the output pull-up transistor M 72  and the first electrode of the output pull-down transistor M 82 . 
     The feedback module of the shift register sub-unit  202  comprises a feedback pull-up transistor M 92 , a feedback pull-down transistor M 102  and a feedback output transistor M 112 . The feedback pull-up transistor M 92  has a gate connected to the pull-up node Q 2 , a first electrode connected to the clock signal input terminal CLKB 2  and a second electrode connected to a first electrode of the feedback pull-down transistor M 102 , the feedback pull-down transistor M 102  has a gate connected to the pull-down node QB 2  and a second electrode connected to the low level input terminal VGL. The feedback output transistor M 112  has a gate connected to the transfer output terminal CR 2 , a first electrode connected to the second feedback node OFF_ 2  and a second electrode connected between the second electrode of the feedback pull-up transistor M 92  and the first electrode of the feedback pull-down transistor M 102 . 
     When the pull-up node Q 2  is at a high level and the pull-down node QB 2  is at a low level, the shift register sub-unit  202  outputs a high level to the main output terminal  300 , and the transfer output terminal CR 2  outputs a high level, such that the feedback output transistor M 112  is turned on and the drain of the feedback output transistor M 112  is at a high level (that is, the first electrode of the feedback output transistor M 111  is at the high level of the clock signal input terminal CLKB 2 ), and thus the second feedback node OFF_ 2  is at a high level. 
     As another aspect of the embodiments of the present disclosure, there is provided a shift register comprising a plurality of shift register units connected in cascade, wherein the shift register unit is the above shift register unit as provided in the present disclosure. In two adjacent stages of shift register units, the plurality of shift register sub-units in a first stage of the two adjacent stages of shift register units are connected in cascade with the plurality of shift register sub-units in a second stage of the two adjacent stages of shift register units in one-to-one correspondence. 
     It can be seen from the above description that said one single output terminal of the shift register can output a plurality of different pulse signals without addition of number of leading wires, such that design of a narrow bezel of a display panel can be achieved. 
     When each of shift register sub-units in the shift register unit comprises a transfer module, the transfer output terminal of the first stage of shift register sub-unit is connected to the input terminal of the second stage of shift register sub-unit, and an effect on the output signal can be avoided by aid of transferring signal via the transfer module. 
     According to another aspect of the present disclosure, there is further provided a gate driving circuit comprising the above shift register as provided in the present disclosure. 
     According to another aspect of the present disclosure, there is further provided a display apparatus comprising the above gate driving circuit as provided in the present disclosure. 
     Since the gate driving circuit is the above gate driving circuit as provided in the embodiments of the present disclosure, the display apparatus can achieve a narrow bezel. In the embodiments of the present disclosure, the display apparatus can be a television, a computer display screen, a cell phone, a tablet, and a navigator etc. The display apparatus can be a liquid crystal display apparatus, and can also be an organic light emitting diode OLED display apparatus. 
     When the display apparatus is a liquid display apparatus, the gate driving circuit outputs a plurality of different pulse signals for each of gate lines, such that liquid crystal capacitors in the liquid display apparatus can be fully charged in divisional. When the display apparatus is an OLED display apparatus, the gate driving circuit outputs a plurality of different pulse signals for each of gate lines, such that each of pixel circuits in the OLED display apparatus can operate in different phases (for example, pre-charging phase, compensating phase and light emitting phase). 
     It should be understood that the above implementations are only exemplary implementations for illustration of principle of the embodiments of the present disclosure, and the embodiments of the present disclosure are not limited thereto. For those skilled in the art, various variations and improvements can be made without departing from the spirit and scope of the embodiments of the present disclosure, which should be considered as falling within the protection scope of the embodiments of the present disclosure. 
     This application claims priority to a Chinese Patent Application No. 201510148924.0, filed on Mar. 31, 2015 in the China&#39;s State Intellectual Property Office, the disclosure of which is incorporated by reference herein as a whole.