Patent Publication Number: US-8541995-B2

Title: Multiphase power regulator with active transient response circuitry

Description:
CROSS REFERENCES TO RELATED APPLICATIONS 
     This application includes subject matter that is related to and claims priority from the following patent applications, commonly assigned to the assignee of the present application, that are hereby incorporated herein by reference: 
     1. SYSTEM AND METHOD FOR HIGHLY PHASED POWER REGULATION, Ser. No. 10/112,738 filed Apr. 1, 2002, inventors: Duffy, et al, now U.S. Pat. No. 6,563,294. 
     2. SYSTEM, DEVICE AND METHOD FOR PROVIDING VOLTAGE REGULATION TO A MICROELECTRONIC DEVICE, Ser. No. 10/103,980, filed Mar. 22, 2002, inventors: Duffy et al. 
     3. SYSTEM AND METHOD FOR CURRENT HANDLING IN A DIGITALLY CONTROLLED POWER CONVERTER, Ser. No. 10/237,903, filed Sep. 9, 2002, inventors: Duffy et al. 
     4. SYSTEM AND METHOD FOR HIGHLY PHASED POWER REGULATION, Ser. No. 09/975,195, filed Oct. 10, 2001, inventors: Duffy et al. 
     5. SYSTEM AND METHOD FOR HIGHLY PHASED POWER REGULATION USING ADAPTIVE COMPENSATION CONTROL, Ser. No. 09/978,294, filed Oct. 15, 2001, inventors: Goodfellow et al. 
     6. SYSTEM AND METHOD FOR HIGHLY PHASED POWER REGULATION USING ADAPTIVE COMPENSATION CONTROL, Ser. No. 10/109,801, filed Oct. 15, 2001, inventors: Goodfellow et al. 
     7. DIGITAL CALIBRATION WITH LOSSLESS SENSING IN A MULTIPHASE SWITCHED POWER CONVERTER, Ser. No. 10/884,840, filed Jul. 2, 2004, inventors: Southwell et al 
     8. MULTI-THRESHOLD MULTI-GAIN ACTIVE TRANSIENT RESPONSE CIRCUIT AND METHOD FOR DIGITAL MULTIPHASE PULSE WIDTH MODULATED REGULATORS, Ser. No. 10/938,031 filed Sep. 10, 2004, inventors Tang et al. 
     9. This application claims priority to Provisional Patent Application 60/638,174 filed on Dec. 21, 2004 and entitled ACTIVE TRANSIENT RESPONSE CIRCUITS, SYSTEM AND METHOD FOR DIGITAL MULTIPHASE PULSE WIDTH MODULATED REGULATORS. 
     THIS IS A CONTINUATION-IN-PART OF: patent application Ser. No. 10/938,031 filed Sep. 10, 2004, inventors Tang et al. entitled: MULTI-THRESHOLD MULTI-GAIN ACTIVE TRANSIENT RESPONSE CIRCUIT AND METHOD FOR DIGITAL MULTIPHASE PULSE WIDTH MODULATED REGULATORS. 
     ALL OF THE FOREGOING ARE HEREBY INCORPORATED HEREIN BY REFERENCE 
    
    
     BACKGROUND OF THE INVENTION 
     1. Technical Field of Invention 
     The present invention relates, generally, to power regulation systems and, in particular, to providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished with an Active Transient Response (ATR) Circuit that detects multiple threshold levels and provides multiple levels of gain. Additional improvements in power regulation are accomplished with an External ATR Circuit, an Adaptive Voltage Positioning (AVP) Pre-positioning circuit, an Adaptive Filter, a Pulse Limiting Circuit and a Tri-state implementation. 
     2. Background of the Invention 
     Regulated power supplies or voltage regulators are typically required to provide the voltage and current supply to microelectronic devices. The regulator is designed to deliver power from a primary source to an electrical load at the specified current, voltage, and power efficiency. Switching power converters (SPC) also referred to as Buck regulators are commonly used voltage regulators due to their high efficiency, high current capability, and topology flexibility. In addition, they can be designed to provide very precise voltage and current characteristics required by devices such as microprocessors, microcontrollers, memory devices, and the like. 
     Power requirements for emerging leading edge technology microprocessors have become very difficult to satisfy. As the speed and integration of microprocessors increases, the demands on the power regulation system increase. In particular, as gate counts increase, the power regulation current demand increases, the operating voltage decreases and transient events (e.g. relatively large voltage spikes or droops at the load) typically increase in both magnitude and frequency. Some emerging microprocessors are expected to run on less than 1.3 volts and more than 100 amperes. 
     SPC&#39;s utilizing step-down multi-phase Buck converters have been the preferred topology to meet the low voltage and high current requirements of microprocessors. With the advent of increasingly complex power regulation topologies, digital techniques for power converter control, specifically in multiphase designs, can improve precision and reduce the system&#39;s total parts count while also supporting multiple applications in the same power system through digitally programmable feedback control. 
     Existing feedback controls have taken voltage measurements from the load, as well as from the individual output phases. The feedback information has been used to adjust the duty cycle, i.e. width of the pulses produced by each of the phases of a multi-phase buck regulator system to bring the supplied voltage and current within the load line tolerances specified by the microprocessor manufacturer. Such a multi-phase pulse width modulated (PWM) voltage regulator system has been disclosed in the patent applications cross-referenced hereinabove and the details of those disclosures are incorporated herein by reference. In particular, the co-pending patent application entitled: DIGITAL CALIBRATION WITH LOSSLESS SENSING IN A MULTIPHASE SWITCHED POWER CONVERTER, Ser. No. 10/884,840, filed Jul. 2, 2004, inventors: Southwell et al, of which an inventor of this application is a co-inventor, teaches a novel lossless technique for sensing current at the load that is provided in a feedback loop to bring the supplied voltage and current within the specified load line tolerances. 
     Active Transient Response (ATR) has been used for high frequency response to rapidly changing power requirements at the load by quickly activating multiple phases to supply or drain (as the case required) more current to or from the load, thereby temporarily over riding the generally slower overall voltage regulator system response. Such power regulation systems utilizing ATR have been disclosed in detail in the patent applications cross-referenced hereinabove and the details of those disclosures are incorporated herein by reference. In particular, the co-pending patent application entitled: SYSTEM, DEVICE AND METHOD FOR PROVIDING VOLTAGE REGULATION TO A MICROELECTRONIC DEVICE, Ser. No. 10/103,980, filed Mar. 22, 2002, inventors: Duffy et al, of which an inventor of this application is a co-inventor, discloses a power regulation system having an active transient response (ATR) circuit. 
     The use of ATR enables voltage regulator systems to be designed with lower overall output capacitance while maintaining equivalent dynamic performance. An ATR circuit includes a window comparator that compares the output supply voltage at the load to the reference voltage, as determined by the specified load line. As long as the output voltage remains within a specified tolerance range (i.e. window) above or below the specified load line, the ATR circuit provides no input signal to the PWM, which proceeds to provide power to the load in a conventional manner. On the other hand, as soon as the voltage is outside the “window”, the ATR circuit signals the PWM to modify its operation. For example, if the voltage drops below the specified voltage range, all low side power switches in the multi-phase system are turned off and then, after a short delay, all high side power switches are turned on, causing the normally staggered inductor charging to occur in parallel. 
     Thus, when the voltage at the load increases above a specified voltage, the window comparator signals an ATRL (Active Transient Response Low) event. Such an ATRL event requires a rapid lowering of the voltage at the load. This is accomplished by turning on additional low side FETs and blocking the high side from providing the normal synchronous phase pulses. This effectively is a compensation operation that reduces the output voltage. Conversely, when the voltage at the load decreases above a specified voltage, the window comparator signals an ATRH (Active Transient Response High) event. Such an ATRH event causes the high side FETs to increase their duty cycle. This effectively is a compensation operation that increases the output voltage back to within the specified window. This technique of compensating for transients causing over voltage and under voltage conditions is enhanced by adjusting the window comparator to a specified load line. By using AVP (Adaptive Voltage Positioning) as a reference “target voltage”, correction of under voltage and over voltage excursions is improved. 
     However, as the power regulation needs of load devices such as microprocessors and the like become even more demanding, even more precise ATR techniques than those disclosed in the aforementioned Duffy et al application, are desired. In particular, it is desired to more precisely detect and compensate the magnitude of the voltage excursion from the target voltage. In addition, it is desired to more accurately and quickly respond to transient power requirements of a load device. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present application describes ATR techniques for more accurately detecting voltage excursions from the specified load line (i.e. the target voltage). In particular, the present invention discloses a multi-level sensing technique that detects not only the fact that the voltage excursion requires an active transient response but also detects the amplitude of the excursion. In accordance with the invention, it has been found highly desirable to sense multiple thresholds, particularly multiple ATRH thresholds. 
     In particular, the invention provides multiple threshold based detection of under voltage that determines how many high-side phases need to be activated to maximize output current slew rate. For example, if the transient is slight, only one phase will respond. If the transient is severe, up to three additional phases (e.g. in the case of a system with four or more phases) can respond. Thus, a plurality of asynchronous pulses is provided on one or more of those phases asynchronously. As previously noted, by the presently disclosed method, the number of thresholds exceeded by the voltage excursion is detected. In short, the number of correction pulses provided is a function of the number of voltage thresholds that are exceeded. In this way, the multi-threshold sensing scheme allows variable gain to be applied by the ATR circuit by varying the number of ATR pulses that are generated so that the correction to the ATR event is in proportion to the magnitude of the sudden voltage excursion, i.e. transient. 
     In accordance with the invention, the multi-threshold sensing technique can be programmed to detect the amplitude of the excursion within desired parameters. The detected excursion is then used to provide an adjustment to the supply voltage that is more precise than would be possible with a less precisely detected excursion. The capability for such rapid enhanced response to transients allows a reduction in the bulk of output capacitors used in Buck regulators. 
     In accordance with another embodiment of the invention, ATR response is further improved by the use of an external ATR control circuit coupled to the load. ATR Comparators provide an ATRH or ATRL signal (upon the occurrence of one of these two events) to an external ATR Control Circuit. The external ATR Control Circuit is coupled to the load and thus provides corrective transient signals directly to the load. The output of the external ATR Control Circuit is coupled to the load in various ways such as: with a pair of external transistors connected directly to the load, with a single transistor and resistive current limiting, or with a single transistor and inductor limiting. As a further alternative, the external ATR Control Circuit is AC coupled to the calibration transistor (the FET used for calibration), which then provides a transient correction signal to the load. The external ATR control circuit provides transient current correction in addition to that already provided by the internal ATR circuits. This is particularly useful, for example, when the internal ATR circuits are already operating at 100% duty cycle. 
     In accordance with a further embodiment of the invention, there is provided a tri-state mode of operation in which both the high side and low side FETs are placed in a high impedance state, i.e. OFF. A Schottky diode is connected in parallel with the low side FET in each phase of the multi-phase pulse width modulated system. When both the high side and low side FETs are in their high impedance state, the Buck converter must draw current through the Schottky diode and the substrate body diode of the low side FET. This provides improved transient regulation, particularly for current going from the high state to the low state. 
     In accordance with a still further embodiment of the invention, ATR pulse limiting is provided. In normal operation, upon the occurrence of an over voltage or under voltage transient event (i.e. ATRL or ATRH) the ATR response is to either turn on all the low side FETs or to turn on one or more to the high side FETs to compensate to the transient event and also to minimize overshoot and undershoot. By pulse limiting this overriding ATR signal (i.e. limiting the amount of time this circuit is on, then forcing it off for a fixed amount of time), the strength of this compensating action can be modified. This effectively changes the gain of this control mechanism. Varying gain by adjusting the on and off times allows the transient response of the system to be optimized. 
     In accordance with the invention, an Adaptive Voltage Positioning (AVP) circuit determines the voltage/current requirements to track the specified load line, which in combination with the multi-threshold multi-gain ATR provides voltage regulator with enhanced performance. In this case, the target voltage is a variable voltage in accordance with the specified load line. Accordingly, the target voltage used as a reference for correcting for under voltage and over voltage conditions, combined with the multilevel sensing and mum-gain correction provide an improved response to transient excursions. A further performance enhancement is provided by pre-positioning the AVP specified load line. 
     By way of further example, in case of an over voltage condition, the ATR circuit can activate additional low-side phases, in addition to blocking high-side pulses to maximize output current slew rate. As will become more apparent in the following more detailed description, the ATR circuit of this invention is asynchronous relative to the synchronous PWM pulse generation. However, as a further feature, the invention provides a method of selecting phases when the correction pulses are applied in accordance with a predetermined scheduled timing relative to the synchronous pulse width modulated pulses. 
     In accordance with another aspect of the invention, the AVP circuit includes a variable low pass fitter that is adjusted in response to an ATR event. This resolves a conflict in the choice of AVP bandwidth. A low AVP bandwidth is desired to filter out current sense noise so that the AVP computation does not add a lot of noise to the output voltage. On the other hand, a high AVP bandwidth is desired for passing transients so that the transient response looks as close to an ideal voltage step as possible. By opening up the AVP bandwidth, the amount of overshoot associated with an ATRH event is reduced. By switching the bandwidth of an adaptive AVP filter between low bandwidth and high bandwidth modes, the regulator&#39;s voltage output ripple and transient performance are optimized. 
     In accordance with a still further aspect of the invention, the AVP circuit is configured to receive pre-determined current values representing different threshold levels of an ATR event. A pre-positioning circuit receives these pre-determined current values from memory and provides them as an output when receiving a signal indicative of an ATRH event. The particular current value provided at the output depends on the degree of the ATRH event, i.e. ATRH 1 , ATRH 2 , or ATRH 3 . These pre-determined current values are added to the compensation voltage applied to the load at a time prior to the detection of current transients. The detection of transient current values at the load is delayed because the current must pass through an inductor. 
     These and other features of the invention will become more apparent in the following more detailed description and claims when considered in connection with the drawings where like reference numerals refer to similar elements throughout the Figures. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a digital multiphase buck regulator that was disclosed in some of the related patent applications cross-referenced herein. 
         FIG. 2A  is a schematic diagram of an embodiment of the invention illustrating the connection of the ATR circuits; 
         FIG. 2B  illustrates an exemplary AVP circuit; 
         FIG. 2C  illustrates another embodiment of an AVP positioning circuit and adaptive AVP Bandwidth fitter. 
         FIGS. 2D and 2E  are waveform diagrams; 
         FIG. 2F  is a schematic diagram illustrating a still further embodiment of the AVP positioning and adaptive AVP Bandwidth fitter. 
         FIG. 3  is a schematic diagram of an ATR comparator circuit in accordance with the invention; 
         FIG. 4  is a circuit diagram illustrating the detection of multiple thresholds; 
         FIG. 5  is a waveform diagram illustrating a load line and exemplary thresholds for detecting an ATR event; 
         FIGS. 6A ,  6 B and  6 C are waveform diagrams illustrating a set of exemplary pulses generated in response to an ATR event; 
         FIG. 7  is a schematic diagram illustrating the multi-gain aspect of the invention; 
         FIG. 8  is a series of pulse train diagrams illustrating the system timing for a system having four phases; 
         FIG. 9  is a series of pulse train diagrams illustrating the system timing for a system having three phases; 
         FIG. 10  is a series of pulse train diagrams illustrating the system timing for a system having six phases; 
         FIG. 11  is a chart illustrating the high side ATR (ATRH) schedule for a system having multiple phases; 
         FIG. 12  is a schematic diagram illustrating an external ATR control with FETs; 
         FIG. 13  is a schematic diagram illustrating an external ATR control and FET with a resistive current limiter. 
         FIG. 14  is a schematic diagram illustrating an external ATR control and FET with an inductive current limiter 
         FIG. 15  is a schematic diagram illustrating an external ATR control that is AC coupled and utilizing the calibration FET to provide the external active transient response; 
         FIG. 16  is a schematic diagram illustrating a tri-state embodiment; 
         FIG. 17  is a schematic diagram illustrating dual input drivers to turn high side and low side devices on independently; 
         FIG. 18  is another schematic diagram illustrating dual Pulse Width Modulated Enable input drivers; 
         FIG. 19  is a waveform diagram illustrating the operation of the tri-state embodiment; 
         FIG. 20  is schematic diagram illustrating pulse limiting; 
         FIG. 21  is a circuit diagram illustrating a pulse limiting circuit; and 
         FIG. 22  is a waveform diagram illustrating the operation of the pulse limiting circuit. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention may be described herein in terms of various functional components and various processing steps. It should be appreciated that such functional components may be realized by any number of hardware or structural components configured to perform the specified functions. For example, the present invention may employ various integrated components comprised of various electrical devices, e.g. resistors, transistors, capacitors, inductors and the like, whose values may be suitably configured for various intended purposes. Any actual values provided for such components as well as applied voltage levels and currents are intended by way of example and not limitation. 
     In addition, the present invention may be practiced in any integrated circuit application. Such general applications and other details that will be apparent to those skilled in the art in light of the present disclosure are not described in detail herein. Further, it should be noted that while various components may be suitably coupled or connected to other components within exemplary circuits, such connections and couplings can be realized by direct connection between components, or by connection through other components and devices located therebetween. 
     Refer now to  FIG. 1 , which is a schematic diagram of a Digital Multiphase Buck Regulator that has previously been described in detail, for example, in the cross-referenced patent applications that have been incorporated herein by reference. It is also known as a Digital Multiphase Buck Converter because it converts a relatively high supply potential (+V) at e.g. 12 volts to a low voltage, e.g. 1 to 3 volts provided to a load at very high current levels. Digital controller  10  is shown including Digital Multi-phase Pulse Width Modulator (PWM)  20 , although frequently PWM  20  is depicted as a distinct power stage. The output of PWM  20  is a series of pulses on each of output lines, the phase  1  output being provided to driver  30  and the phase  2  output being provided to driver circuit  30 ′. In a multi-phase system having more than 2 phases, additional phases are connected in a similar manner. Low side FETs  50  and  52 , inductors  60  and  62 , and capacitor  70  are typically discrete devices. In each phase, (say phase  1  for example), a pulse output stage comprises a high side FET ( 40 ), a low side FET ( 50 ) and an inductor ( 60 ). Similarly, the pulse output stage for phase  2  comprises a high side FET  42 , a low side FET  52  and an inductor  62 . The pulse output stage charges up capacitor  70  and supplies power to the load. Load  80  is typically a microelectronic component, such as a microprocessor, requiring very accurate power that is regulated and maintained during rapidly changing power requirements. 
     Digital controller  10  receives a VID input at voltage control  12 . VID is a digital number provided by the microprocessor manufacturer describing specific power requirements, in particular the set point, i.e. initial load line voltage at minimum current. Digital controller  10  can also have a reference voltage  14  that is applied to analog-digital converter  16  that also receives, as a second input, the voltage at load  80 . The reference voltage from block  14  is used to calibrate the output of analog to digital converter ADC  16  to that reference voltage. The output of ADC  16  is a digital voltage value that is compared to the output of voltage control circuit  12  (the target voltage) in summer  17  and provided as a digital error voltage to digital compensator  18 . Digital compensators such as digital compensator  18  that provide inputs to multi-phase pulse width modulators, such as PWM  20  are well known and described for example in the above cross-referenced patent application, SYSTEM, DEVICE AND METHOD FOR PROVIDING VOLTAGE REGULATION TO A MICROELECTRONIC DEVICE, Ser. No. 10/103,980, filed Mar. 22, 2002, inventors: Duffy et al. of which an inventor in this application is a coinventor. Digital compensator  18  then provides an input to PWM  20  in order to modify the width of the pulses provided to the drivers  30  and  30 ′, etc. of each of the two phases in the illustrated example, and other phases, when utilized. Phase  1  is driven by driver circuits  32  and  34 . Circuit  32  drives the gate of FET  40  with a signal that is complementary to the output of circuit  34  that drives the gate of FET  50 . FET  40  and  50  have their drain-source paths connected in series, at a common point A, between a first potential source (+V) and a second potential source (ground). Since both FET  40  and  50  are shown as N-channel devices, only one of the two transistors is on at any one time. Of course, if transistor  40  were to be replaced with a P-type transistor, then the same phase signal could be used to drive the gate of both transistor  40  and  50 . In either case, there is never a direct current path between +V and ground. 
     The phase  2  output of PWM  20  is provided to circuits  36  and  38  during phase  2  time in the same way that circuits  32  and  34  receive the pulse width modulate signals during phase  1  time. Circuit  36  then drives the gate of FET  42  and circuit  38  drives the gate of FET  52 . Note that although two phases are shown, any number of phases can be used. Larger number of phases provides smoother and more accurate power to the load. 
     In operation, during phase  1 , while the pulse width modulated waveform turns high side FET  40  on, current flows through FET  40  into node A and through inductor  60  to charge capacitor  70  and provide power to load  80 . On the other hand, when low side FET  50  is turned on, current flows through FET  50 . High side FET  42  and low side FET  52 , connected in common at node B operate in a similar manner during phase  2 . The voltage from the load  80  is fed back to ADC  16  so that the voltage to the load can be adjusted to changing load conditions. It is desirable to also measure the voltage at node A and node B (and other corresponding nodes in systems with more phases) as an indication of the current being supplied to the load. The cross-referenced patent applications show how the measurements taken at nodes A and B are then used to better regulate the power provided to load  80 . Although such a system operates satisfactorily, it has been found that for more rapid response to high speed variations in the power requirements of load  80 , a second voltage adjustment technique is desired. In particular, when the voltage excursion from the load line exceeds a predetermined specified amount, then a secondary power adjustment is provided by active transient response (ATR) circuitry. 
     Refer now to  FIG. 2A , which is a schematic diagram of one embodiment of this invention. Components corresponding to  FIG. 1  have been identified with corresponding reference numerals. Multi-phase pulse width modulator  20  is coupled to the pulse output stage of each phase through drivers  30  and  30 ′. As in  FIG. 1 , each pulse output stage comprises a high side FET ( 40 ,  42 ), a low side FET ( 50 ,  52 ) and an inductor ( 60 ,  62 ), as a two phase system is shown. Additional phases would comprise similar structure. 
     In the  FIG. 2A  embodiment, voltage control is provided by Adaptive Voltage Positioning block AVP 12 . As in  FIG. 1 , AVP 12  gets a VID input. As shown in  FIG. 2A , AVP 12  also gets an RLOADLINE input, which is a number provided by microprocessor manufacturers indicating the desired slope of the load line. AVP  12  receives an additional input from current ADC 13 . Current from all the phases at the nodes (node A and node B in the illustrated two phase example) is sensed through resistor R 15  and resistor R 15 ′, clocked through multiplex circuit  11  at the active phase time and converted to a digital value in ADC  13 . This permits AVP 12  to provide an adjustment to the target voltage number provided to comparator  17  and active transient response circuit ATR circuit  100 . Thus, the target voltage is determined by AVP circuit  12  which adjusts the target voltage in accordance with the specified load line. In addition, AVP 12  receives inputs from ATR circuit  100  for providing early and predictive correction of the target voltage, as will be described in greater detail hereinbelow. 
     ATR circuit  100  is coupled between the output stage, at load  80  and multi-phase PWM 20  and is configured to detect the voltage level at the load. In case the transient voltage at the load deviates from the target voltage by one or more of the pre-set thresholds, ATR 100  provides a signal to PWM 20  that is a function of the amplitude of the deviation of the detected voltage from the target voltage. The ATR 100  output will be one of: ATRL, ATRH 1 , ATRH 2 , or ATRH 3 . 
     ATR 100  is also coupled between the output stage, at load  80 , and AVP 12  to provide one of the signals indicative of an ATR event, i.e. one of ATR signals (ATRL, ATRH 1 , ATRH 2 , or ATRH 3 ) to AVP 12 . This enables AVP 12  to provide an early, predictive change to summer  17 . This predictive change can occur prior to the time that the sensed current change is received from ADC 13  because the sensed load current change is delayed passing through inductors  60 ,  62 , and other similar inductors in additional phases. 
     As long as the voltage at the load is maintained within predetermined limits, ATR circuit  100  is not activated and no output signals are provided by ATR circuit  100 . However, when the changes in power demands by the load result in a voltage excursion at the load that exceeds the predetermined limits, ATR circuit  100  provides ATRL, ATRH 1 , ATRH 2 , or ATRH 3  signals to PWM generator  20  to correct the voltage deviation rapidly and with minimal noise generation. As shown in  FIG. 2A , these same signals are provided to AVP 12 . 
     Refer now to  FIG. 2B  illustrating one embodiment of ADP 12 . The sensed current from ADC  13  is received at demultiplexer circuit (demux)  202 . Demux  202  also receives a phase clock corresponding to the time of each phase output of PWM  20 . In this case, a six phase example is illustrated so that there are in fact 6 phase clock inputs. Demux  202  provides each of the channel currents ICH 1 , ICH 2 , ICH 3 , ICH 4 , ICH 5 , and ICH 6  to summer circuit  204 , which in turn provides the sum of the currents (ISUM) on all of the channels to multiplier circuit circuit  206 . ISUM is thus the rotating sum of the currents of all phases. The output of summing circuit  204  is provided to multiplier circuit  206 , where it is multiplied by RLOADLINE, which is a constant number representing the specified slope of the load line. The output of multiplier  206  is therefore a voltage value representing the change in voltage (VDELTA_AVP) resulting from the changing total current ISUM. This value is passed through a low pass digital fitter in order to pass as little ripple noise as possible. The filtered output voltage (FILT VDELTA AVP) is provided to summing circuit  210 , which also receives the VID input. Vout, the output of summing circuit  210  is then the VID set point value as modified by the sensed current. Although an AVP 12  in accordance with this embodiment operates satisfactorily, it has also been found that Vout is delayed undesirably. This is due to the fact that the sensed current input to DEMUX 202  is delayed in time because current at load  80  is sensed through N inductors  60 ,  62 , etc. (N being the number of phases in a system.) The elimination of this delay and other improvements are provided by the circuit of  FIG. 2C . 
     Refer now to  FIG. 2C  in which elements corresponding to  FIG. 2B  have been similarly numbered and function in the same manner. The aforementioned elimination of delay is provided at summing circuit  205 , which receives a pre-positioning signal (CUR_INJECT) which is added to ISUM to produce ISUM+CUR_INJECT. This larger current value is multiplied by the RLOADLINE (load line slope constant) to produce a larger DELTA AVP. This larger changed voltage value is provided to digital low pass filter  208 ′, which is also improved from the  FIG. 2B  embodiment. 
     In particular, for normal signals, it is desired that a digital filter, such as  208 ′, have a narrow bandwidth with fitter coefficients set at FC 1 , for example to filter out ripple noise so that the AVP computation doesn&#39;t add a lot of noise to the output voltage. However, for high frequency transient signals a wide bandwidth filter with filter coefficients set at FC 2 , for example, is desired so that transient response looks as close to an ideal voltage step as possible. These coefficients are set by 2:1 multiplex circuit  212 , as will now be described. 
     Circuit  212  receives a (FILTER_WIDE_BW) input when there is either an ATRL or an ATRH event. The second input (FILTER_NARROW_BW) is active when there is no ATR event. OR circuit  214  is also provided to provide an input to circuit  212  when either an ATRL 1  or an ATRH 1  event occurs. Circuit  212  will pass the FILTER_WIDE_BW signal when S=1, i.e. either ATRL 1  or ATRH 1  is up. Conversely circuit  212  will pass FILTER_NARROW_BW when S=0. Depending on which of these signals is inputted to digital filter  208 ′, it will operate with coefficient FC 1  or FC 2 . 
     Pre-positioning circuit  216  receives pre-stored inputs (from memory not shown) representing current values corresponding to ATRH thresholds exceeded. For example, CUR_INJECT_ATRH 1  could be preset at 25 Amps. Then, CUR_INJECT_ATRH 2  could be preset at 50 amps. CUR_INJECT_ATRH 3  could be preset at 75 amps and so on for the N thresholds. Logic circuit  218  receives the inputs ATRH 1 , ATRH 2  and ATRH 3  from ATR circuit  100 . Note that ATR circuit  100  receives a voltage sense input directly from the load  80 . This voltage transient signal is received much more quickly than the current sense signal transient which must pass through an inductor, e.g.  60 ,  62 , etc. In response to a voltage transient, ATR circuit  100  inputs to logic circuit  218 , the ATRH threshold (if any) that has been triggered. In response, circuit  216  provides the pre-programmed values of CUR_INJECT to summing circuit  205 . For example, the respective pre-programmed values of CUR_INJECT can be: O amps (no ATR), 25 amps (ATRH 1  event), 50 amps (ATRH 2  event) or 75 amps (ATRH 3  event). In turn, summer  205  provides the sum of the currents ISUM+CUR_INJECT to multiplier  206 . The output of circuit  206  is a voltage (DELTA_AVP) that is the product of RLOADLINE (the slope of the load line) and the current. It is the function of AVP Low pass fitter  208 ′ to filter this voltage. Filter  208 ′ receives a signal from circuit  212  and depending on that signal acts as a low pass fitter either with coefficient FC 1  or FC 2  to provide the filtered output to summer  210 . Summer  210  combined the VID_SET_POINT value with the filtered voltage value as the output of the AVP 12  circuit. 
       FIG. 2D  illustrates the improved waveform provided by using variable digital filter  208 ′. Waveform A is provided by using digital fitter  208 ′ while waveform B shows the waveform that is provided when digital filter  208 ′ is not tuned to the correct bandwidth. The significant difference in the two waveforms is illustrated by the arrow. The values of 0 Amps and 100 Amps are shown by way of example. With further reference to the waveform in  FIG. 2D , note that it has a delay “C”. This delay has been eliminated in waveform A′ in  FIG. 2E , which essentially is the same waveform A shown in  FIG. 2D , but without the delay. As previously described, the delay is eliminated with pre-positioning circuit  216 . 
     Refer now to  FIG. 2F , which is a schematic diagram illustrating a still further embodiment of the AVP positioning and adaptive AVP Bandwidth filter. Refer also to  FIG. 2C  and note that corresponding elements have been identified with the same reference numerals and function in the same manner. The previously described elimination of delay is provided at summing circuit  205 , which receives a pre-positioning signal (CUR_INJECT) from latch  216  and a signal from latch  220  which are added to ISUM in summer  205 . This larger current value is multiplied by the RSLOPE (PREVIOUSLY IDENTIFIED AS RLOADLINE, i.e. load line slope constant) to produce a larger DELTA AVP. This larger changed voltage value is provided to digital low pass filter  208 ′. 
     In particular, for normal signals, it is desired that a digital filter, such as  208 ′, have a narrow bandwidth with filter coefficients set at FC 1 , for example to fitter out ripple noise so that the AVP computation doesn&#39;t add a lot of noise to the output voltage. However, for high frequency transient signals a wide bandwidth filter with filter coefficients set at FC 2 , for example, is desired so that transient response looks as close to an ideal voltage step as possible. These coefficients are set by 2:1 multiplex circuit  212  (see  FIG. 2C ), which provides the ATRL and ATRH inputs to Filter  208 ′. Upon the occurrence of either ATR event (ATRL or ATRH), digital fitter  208 ′ will operate with filter coefficients set at FC 2 . It is the function of AVP filter  208 ′ to fitter the voltage received from multiplier  206  and to provide the filtered output to summer  210 . Summer  210  combines the VID_SET_POINT value with the filtered voltage value as the output of the AVP 12  circuit. 
     Refer now to  FIG. 3  for a more detailed description of the comparator circuit  300  used in the ATR circuit  100 . The comparator comprises 4 programmable threshold setting circuits  302 ,  304 ,  306 , and  308 . Threshold detector  302 : 1. Receives as an input, the analog value of the target voltage VADP from AVP 12 , 2. Adjusts that input by an amount that is the ATRL threshold e.g. 50 mv and 3. Provides that value to comparator circuit  310 . Comparator circuit  310  also receives, as a second input, the actual voltage sensed at the load. Since the VADP reference signal is in digital form, it is converted to an analog value in DAC 312 . Thus, whenever the voltage sensed at the load has an excursion that exceeds the ATRL threshold, comparator circuit  310  provides an output that indicates that there is an ATRL event. Comparator circuit  310  is configured to receive the aforementioned input signals in analog form and to provide the output in digital form. Those skilled in the art will know of various topologies for comparing two analog signals and providing a digital output (e.g. with an analog to digital converter integrated with the compare circuit. The ATRL pulse blocks the high side FETs and turns on the low side FETs as the output of the pulse width modulator  20  provides complementary outputs. 
     The ATRH comparator circuits  314 ,  316 , and  318  are configured in the same way and operate in a manner similar to comparator circuit  310 . Threshold setting circuit  304  sets the threshold voltage level ATRH 1  for comparator  314 . When the Vsense voltage deviates (in a negative direction in case of an ATRH event) to a greater value than the threshold voltage provided by block  304 , comparator  314  provides a high level logic signal indicating an ATRH 1  event. If the Vsense voltage deviates to a greater value than the threshold value provided by block  306 , comparator  316  provides a signal indicating an ATRH 2  event. If the Vsense voltage deviates to a greater value than the threshold value provided by block  308 , comparator  318  provides a signal indicating an ATRH 3  event. 
     Refer now to  FIG. 4 , for a description of the multi-threshold ATR comparator circuit  400 . The output voltage Vsense is received from the load at the gate of FET 402 . The analog value of VADP, i.e. Vtarget, is received at the gate of FET 404 , as converted into analog form by DAC 312 ′. DAC 406  receives the pre-determined ATRL threshold level in digital form and provides an analog current to a voltage divider comprising Resistors R 1 , R 2 , R 3 , and R 4 . The voltage at the common connection of R 3  and R 4  then sets the ATRL threshold at comparator  410 . DAC 408  provides a current to a voltage divider comprising Resistors R 5 , R 6 , R 7 , and R 8 . DAC 406  and DAC 408  are differential current DACs that set the threshold for the ATR comparator circuits by generating an offset voltage across resistors R 1 -R 4  and R 5 -R 8 , respectively. 
     The inputs Thresh_ATRL and Thresh_ATRH are programmable parameters stored in memory, which set the current DAC outputs. These programmable parameters are digital values permitting adjustment of ATRH 1 , ATRH 2 , and ATRH 3  by simply modifying the value of the Thresh_ATRH input to current DAC  408 . Similarly the ATRL threshold is programmable by simply adjusting the value of the Thresh_ATRL input to current DAC  406 . Differential current outputs are used so that the current through FETs  402  and  404  are fixed independent of setting (i.e. the sum of the true and complement currents are a fixed value.) 
     In operation, the voltage at the common connection of R 3  and R 4  Is applied as a first input to ATRL compare circuit  410 . This voltage value is determined by: 1. the amplitude of the target voltage applied to the gate of FET 404 , 2. the amplitude of the current supplied by DAC 406  and 3. the value of the resistors in the voltage divider formed by R 1 , R 2 , R 3 , and R 4 . The voltage at the common connection of R 8  and FET 402  is applied to the second input to ATRL compare circuit  410 . The voltage at this second input is determined by the amplitude of the sensed voltage applied at the gate of FET 402 . If the second input exceeds the first input, compare circuit  410  will signal an ATRL event (ATRL 1 ) resulting in the blocking of high side FETs and turning on low side FETs. 
     Comparator circuits  412 ,  414 , and  416  are configured and operate in a manner similar to just described circuit  410 . Each of them receives a first input that is a function of the target voltage applied to the gate of FET 404 . Each of them receives a second input that is a function of the sensed voltage provided to the gate of FET 402 , the threshold setting current provided by current DAC  408  and the resistor values of R 5 , R 6 , R 7 , and R 8 . In particular, comparator circuit  412  receives the sensed input from the common connection between R 7  and R 8 . In the event the voltage sensed at the common connection between R 7  and R 8  deviates from the target voltage by a value greater than the first threshold, then circuit  412  provides an output indicating an ATRH 1  event. If the voltage at the common connection of R 6  and R 7  deviates from the target voltage by a value greater than the second threshold, as set in comparator circuit  414 , then circuit  414  provides an output indicating an ATRH 2  event. Lastly, if the voltage at the common connection of R 5  and R 6  deviates from the target voltage by a value greater than the third threshold, as set in comparator circuit  416 , then circuit  416  provides an output indicating an ATRH 3  event. 
     Thus, setting a single threshold at a voltage level in a positive direction (at a pre-determined voltage higher than the target voltage) permits detection of a deviation greater than the pre-determined voltage. The detection of such a deviation signals an ATRL event activating circuitry to rapidly reduce voltage at the load. On the other hand, setting multiple thresholds at voltage levels in a negative direction (at multiple voltage levels lower than the target voltage) permits detection of the size of the deviation from the target voltage. The detection of such multiple levels of deviation, i.e. transients, signals not only the existence of an ATRH event, but also the amplitude of the deviation, i.e. ATRH 1 , ATRH 2 , or ATRH 3 . 
     The operation of the ATR comparators and ATR circuit  400  will also be understood with reference to the waveform shown in  FIG. 5 . FIG,  5  shows an AVP load line well known in the art. The amplitudes of Load voltage (V), Load current (A) and the slope of the AVP Load line are specified by the manufacturer of the load. Most typically, loads requiring precisely controlled low voltage levels at high currents under rapidly changing load conditions are microprocessors, microcontrollers, and the like. The specified error limits shown are also provided by the manufacturer of the load. Under normal operating conditions, the voltage and current provided to the load are expected to stay within the specified error limits, for example +/−19 millivolts. 
     Under rapidly changing conditions, for example if the load suddenly requires far less current, the load at the voltage could exceed the AVP load line voltage by more than the pre-set ATRL threshold. This is an ATRL event that will cause the ATR circuit  100  to be activated to rapidly bring the load voltage towards the AVP load line. Similarly, if the load suddenly requires far more current, then the load voltage could decrease to an amount that would exceed one or more of the ATRH thresholds. This will be an ATRH event that will cause the ATR circuit  100  to be activated to rapidly bring the load voltage towards the AVP load line. 
     In accordance with the invention, it has been found highly desirable to have multiple thresholds, particularly multiple ATRH thresholds. All of the embodiments in this application disclose three ATRH thresholds, to wit, ATRH 1 , ATRH 2  and ATRH 3 , which can be used to great advantage in PWM systems with 2-6 or more channels (phases). However, there is no practical reason why rather than 3 ATRH thresholds, 2, 4 or more ATRH thresholds could not be used. However, the use of multiple ATRH thresholds greatly improves circuit operation (as compared with a single ATRH threshold) and is more cost effective than 4 or more ATRH thresholds where the improved performance may reach the point of diminishing returns. The improvement in circuit operation is achieved by adjusting the magnitude of the ATR response to the magnitude of the excursion from the AVP load line. 
     The advantage of detecting multiple ATR thresholds is achieved by providing correction based on the magnitude of the excursion. This technique is shown in the waveform diagram of  FIG. 6A ; which shows exemplary timing pulses in a four phase system. The Vout waveform illustrates (in dotted lines) the likely output waveform when ATR is not used. A sudden high current demand causes the voltage to drop substantially and then gradually return to a lower steady state than the prior steady state level in accordance with the AVP load line. The method disclosed herein provides a pulse width modulator configured to provide multi-phase pulse outputs. In the  FIG. 6A  case, there are four channels (phases), to with PWM 1 , PWM 2 , PWM 3 , and PWM 4 , each providing an output pulse during its assigned time slot, as shown. In accordance with the method, each of the illustrated pulses has a width (duty cycle) that can be narrower or wider to maintain the desired regulated voltage during normal operation. 
     With continued reference to  FIG. 6A , and in particular to the area identified as an ATR Transient Event, note the Asynchronous PWM Activity. In this method step, a plurality of asynchronous pulses are provided on one or more of those phases that are not already providing a “normal” synchronous pulse width modulated pulse output. As previously noted, by the presently disclosed method, the number of thresholds exceeded by the voltage excursion is detected. The number of correction pulses provided is a function of the number of voltage thresholds that are exceeded. Refer to line PWM 1  which shows the occurrence of the first ATR pulse occurring shortly after the Vout voltage dropped. As illustrated, this first ATR pulse occurs at a point in time when the “normal” synchronous phase pulse PWM 2  is already off and PWM 3  is just turning on. This first pulse occurs in response to an ATRH 1  event so that at this point only the first threshold has been exceeded. In some cases, it is possible that at this point the voltage excursion is returned to normal and no more ATR pulses are required. However, in the  FIG. 8  illustration, additional ATR pulses are provided. As illustrated, a total of 4 ATR pulses occur on PWM 1 , 3 on PWM 2 , 1 on PWM 3  and 1 on PWM  4 . The last of the ATR pulses occur while “normal” synchronous PWM  4  is also on. As a result of the ATR pulses, the Vout voltage (solid line) dropped less than it would have without ATR. The multi-threshold sensing scheme allowed variable gain to be applied by the ATR circuit by varying the number of ATR pulses that are applied so that the correction to the ATR event is in proportion to the magnitude of the sudden voltage excursion, i.e. transient. 
     By way of further example, see  FIG. 6B  illustrating a two-phase system as in  FIG. 2A . As previously noted, additional phases, when used, operate in a similar manner. Vout is the voltage at the load. Upon the occurrence of an ATRH event (a down transient sufficient to trigger one or more ATRH threshold levels), the extra PWM pulses (in the circled area) are found at node A (V A ) and node B (V B ). Refer now to  FIG. 6C ; which illustrates how in the case of an ATRL event, the waveforms shown in FIG. C occur at Vout and nodes A and B. An up level transient that exceeds the ATRL threshold causes the ATRL event. Such an up level transient is caused when the current demand of the load decreases. In this case, PWM pulses are blocked at nodes A and B, by for example line ATRL 1  in  FIG. 7 . This permits Vout to be brought down quickly from its up level spike. In each case ( FIG. 6B  and  FIG. 6C ), the new voltage level at Vout is set in accordance with the new current demands of the load causing the new voltage to be positioned in accordance with the load line (see  FIG. 5 ) in accordance with known AVP techniques. 
     The multi-gain aspect is illustrated in greater detail in the schematic diagram of  FIG. 7 . For purposes of illustration, only one phase is shown. A multi-phase system will have one such  FIG. 7  circuit for every phase. However, it will be appreciated by those skilled in the art that a feature of this invention is accomplished with the capability of providing ATR compensation pulses on one or more phases, in addition to the normal synchronous pulse width modulated phase pulses. PWM  700  receives a docking signal and a phase signal (labeled phase x) for the particular phase with which it is associated. (In the four phase system illustrated in  FIG. 8 , these are the phase  1 , phase  4 , phase  2  and phase  3  signals.) It also receives a duty cycle signal from digital compensator  18  ( FIG. 2A ) to adjust the pulse width. The output is an internal pulse width modulated pulse train pwm_internal that is inputted to OR logic circuit  702 , which in turn provides this signal to AND logic circuit  704 . This pulse width modulated pulse train becomes the output of the multi-phase PWM generator, e.g. PWM  20  ( FIG. 1 ). However, this pulse train output is blocked by AND logic circuit  704  when an input is received as an ATRL event, for example from ATRL 1  ( FIG. 3  or  4 ). In case of an ATRL event, the output voltage has exceeded the ATRL threshold ( FIG. 5 ) and pulses are applied only through low side FETs to bring the output voltage down. In case the output voltage drops sufficiently below the AVP load line to exceed one or more of the ATRH thresholds (ATRH event), then a high level logic input is received at the corresponding AND logic circuit  706 ,  708 , and  710 . AND circuit  706  also receives a clocking signal ATRH 1 _PHASEX (from timing generator  701 ) in order to gate the ATRH 1  signal through AND logic gate  706  at the appropriate time, as will be explained in connection with a timing diagram ( FIG. 8 ). AND logic gate  706  passes this signal to OR logic gate  712 , which in turn passes the signal through OR logic gate  702  to AND logic gate  704 . Since an ATRH event will not occur simultaneously with an ATRL event, the ATRH 1  signal will become the output pwm_out. The ATRH 2  signal is clocked through AND logic gate  708  and the ATRH 3  signal is clocked through AND logic gate  710  and eventually to the output pwm_out in the same way as ATRH 1  at the occurrence of the corresponding PHASEX signal from timing generator  701 . 
     Refer now to  FIG. 8 , which illustrates the timing of pulse signals in a four phase system. As illustrated, phase  1 , phase  4 , phase  2  and phase  3  signals are generated to operate a four phase system. In the PWM 1  waveform, the pulses that are labeled as ATRL 1  are the “normal” synchronous pulses that occur during phase  1  time, unless of course blocked by an ATRL event, in which case the low side FETs are turned on. The operation of PWM 4 , PWM 2  and PWM 3  is similar. ATRL 1  labeled pulses are provided by PWM 4  during phase  4  time. Similarly, PWM 2  provides “normal” synchronous pulses during phase  2  time and PWM 3  provides “normal” synchronous pulses during phase  3  time. The labeled pulses for the PWM 1 , PWM 4 , PWM 2  and PWM 3  occur as an ATRH output at the indicated time as gated by the timing pulses shown in the remainder of the  FIG. 8  waveform diagram. 
     The pulse trains with the illustrated timing of the ATRHX_PHASEX signals are generated by timing generator  701  in response to the CLK input pulse. Thus, as shown in  FIG. 8 , the atrh 1 _phase  1  clock signal gates the atrh 1  signal to occur on PWM 1  at the designated times, in case the atrh 1  threshold was exceeded. Similarly the atrh 1 _phase  4  pulse gates the atrh 1  signal to PWM 4 . The atrh 1 -phase  2  pulse gates the atrh 1  signal to PWM 2  and the atrh 1 _phase  3  pulse gates the atrh 1  signal to PWM 3 . In case the ATRH 2  and ATRH 3  thresholds are exceeded, these signals are similarly gated at the indicated times to the indicated channel of the pulse width modulator. 
     As previously noted, the three ATRH threshold level detection is useful not only in four phase systems but in a system with any number of phases. For example, see  FIG. 9  which illustrates timing for a system having three phases. The various pulse trains: phase  1 , phase  2 , phase  4 , PWM 1 , PWM 2 , and PWM 3  are generated as in the prior example; however with only 3 phases, as shown. With a 3 phase system, ATRH 1  is activated when the first threshold is triggered and ATRH 2  is activated when the second threshold is triggered. However, if and when the third threshold is triggered, the ATR circuit has no effect in a three phase system. Similarly, in a two phase system, in case of an ATRH event, only ATRH 1  correction pulses are provided. 
     By way of example, see  FIG. 10 , where the system timing for a six phase system is shown. The various pulse trains: phase  1 , phase  2 , phase  4 , phase  5 , phase  6 , PWM 1 , PWM 2 , PWM 3 , PWM 4 , PWM 5  and PWM 6  are generated as in the prior example; however with the 6 phases, as shown. Thus, whenever more than 4 phases are provided with three threshold detectors, in case of an ATRH event that triggers all three thresholds, all ATRH pulses (atrh 1 , atrh 2  and atrh 3 ) are used. The ATRL events, being triggered by one threshold, remain the same regardless of the number of phases. In all cases, the ATRL and ATRH are mutually exclusive and cannot occur simultaneously. Also, as previously noted, in case of an ATRL event, the “normal” synchronous phase pulse is blocked, as well. By way of further detailed explanation see  FIG. 11  showing a schedule of phase selection for any number of phases from 2 to 6. Thus, although the correction pulses provided in response to an ATRH event are asynchronously generated in different phases, the phases are selected in accordance with a predetermined scheduled timing relative to the normal synchronous pulse width modulated pulses. 
     Refer now to  FIG. 12 , which is a schematic diagram of another embodiment of this invention. Components corresponding to  FIG. 2A  have been identified with corresponding reference numerals. Multi-phase pulse width modulator  20  is coupled to the pulse output stage of each phase through drivers  30  and  30 ′. As in  FIG. 2A , each pulse output stage comprises a high side FET ( 40 ,  42 ), a low side FET ( 50 ,  52 ) and an inductor ( 60 ,  62 ), as a two phase system is shown. Additional phases would comprise similar structure. 
     In the  FIG. 12  embodiment, voltage control is provided by Adaptive Voltage Positioning block AVP 12 . As in  FIG. 1 , AVP 12  gets a VID input. As shown in  FIG. 2A , AVP 12  also gets an RLOADLINE input, which is a number provided by microprocessor manufacturers indicating the desired slope of the load line. AVP  12  receives an additional input from current ADC 13 . Current from one phase only is sensed at node B in the illustrated two phase example) is sensed through resistor R 15  and converted to a digital value in ADC  13 . This permits AVP 12  to provide an adjustment to the target voltage number provided on line  12 ′ to summer  17  and active transient response comparators ATR comparators  100 . Thus, the target voltage is determined by AVP circuit  12  which adjusts the target voltage in accordance with the specified load line. In addition, AVP 12  receives ATRL and ATRH inputs from ATR comparators  100  for providing early and predictive correction of the target voltage, as will be described in greater detail hereinbelow. 
     ATR comparators  100  are coupled between the output stage, at load  80  and multi-phase PWM 20  and are configured to detect the voltage level at the load. In case the transient voltage at the load deviates from the target voltage by one or more of the pre-set thresholds, ATR 100  provides a signal to PWM 20  that is a function of the amplitude of the deviation of the detected voltage from the target voltage. The ATR 100  output will be ATRL or ATRH. ATRH can be any one of: ATRH 1 , ATRH 2 , or ATRH 3  but would usually be ATRH 1 . 
     ATR 100  is also coupled between the output stage, at load  80 , and AVP 12  to provide one of the signals indicative of an ATR event, i.e. one of ATR signals (ATRL or ATRH) to AVP 12 . This enables AVP 12  to provide an early, predictive change to summer  17 . This predictive change can occur prior to the time that the sensed current change is received from ADC 13  because the sensed load current change is delayed passing through inductors  60 ,  62 , and other similar inductors in additional phases. 
     As long as the voltage at the load is maintained within predetermined limits, ATR comparator  100  is not activated and no output signals are provided by ATR  100 . However, when the changes in power demands by the load result in a voltage excursion at the load that exceeds the predetermined limits, ATR  100  provides ATRL or ATRH, signals to PWM generator  20  to correct the voltage deviation rapidly and with minimal noise generation. As shown in  FIG. 2A , these same signals are provided to AVP 12 . 
     With continued reference to  FIG. 12 , note series connected high side FET  40 ′ and low side FET  52 ′ directly coupled to the output of the regulator and load  80 . The gates of FET  40 ′ and  52 ′ are coupled to the outputs of External ATR Control  101 . External ATR Control  101  has its inputs coupled to the outputs of ATR Comparators  100 . In operation, external ATR Control operates only if it receives an ATRL or ATRH input. In case of an ATRL input signal, FET  52 ′ is turned on. In case of an ATRH input signal, FET  40 ′ is turned on. This provides an additional current path through the conducting one of these two FETs ( 40 ′ or  52 ′) to rapidly compensate for the transient event. By way of example, if the maximum duty cycles of high side FET  40  provide 65% of additional current required to compensate for the transient event, then FET  40 ′ provides the additional 35% for a desired 100% transient compensation. 
     Refer now to  FIG. 13 , which is a schematic diagram of another embodiment of this invention. Components corresponding to  FIG. 12  have been identified with corresponding reference numerals. Multi-phase pulse width modulator  20  is coupled to the pulse output stage of each phase through drivers  30  and  30 ′. As in  FIG. 12 , each pulse output stage comprises a high side FET ( 40 ,  42 ), a low side FET ( 50 ,  52 ) and an inductor ( 60 ,  62 ), as a two phase system is shown. Additional phases would comprise similar structure. The difference to be noted in  FIG. 13  is the addition of current limiting resistor R 16  and the absence of high side FET  40 ′. In this embodiment, External ATR Control  101  provides an input to FET  52 ′ in the event of an ATRL event to conduct transient compensating current between the load and ground potential. This extra current conduction path is significant for compensating for an ATRL transient. 
     Refer now to  FIG. 14 , which is a schematic diagram of another embodiment of this invention. Components corresponding to  FIG. 13  have been identified with corresponding reference numerals. Multi-phase pulse width modulator  20  is coupled to the pulse output stage of each phase through drivers  30  and  30 ′. As in  FIG. 13 , each pulse output stage comprises a high side FET ( 40 ,  42 ), a low side FET ( 50 ,  52 ) and an inductor ( 60 ,  62 ), as a two phase system is shown. Additional phases would comprise similar structure. The difference to be noted in  FIG. 14  is that inductor  64  limits the current through FET  52 ′ instead of resistor R 16  that performed the current limiting function in  FIG. 13 . 
     Refer now to  FIG. 15  which is a schematic diagram of another embodiment of this invention. Components corresponding to  FIG. 13  have been identified with corresponding reference numerals. Multi-phase pulse width modulator  20  is coupled to the pulse output stage of each phase through drivers  30  and  30 ′. As in  FIG. 13 , each pulse output stage comprises a high side FET ( 40 ,  42 ), a low side FET ( 50 ,  52 ) and an inductor ( 60 ,  62 ), as a two phase system is shown. Additional phases would comprise similar structure. 
     In the  FIG. 15  embodiment, External ATR Control  101  is AC coupled to external low side FET  52 ′ through capacitor  71 . This AC coupling limits the time that an up level signal will keep FET  52 ′ on. This is not a problem as the short duration of transients (and the corresponding short duration of correction signals) is within the time frame that FET  52 ′ needs to be on. In the  FIG. 15  embodiment, Calibration Current Control  102  is coupled to FET  52 ′ through resistor R 17 . The previously described calibration function is performed during initialization when FET  52 ′ is referred to as a calibration FET with calibration resistor R 16 . During normal circuit operation, Calibration Current Control  102  remains off. As thus illustrated, in the  FIG. 15  embodiment FET  52 ′ (as well as resistor R 16 ) are “shared” and perform the function of calibration or the function of compensating for transients. This sharing of components is cost effective. 
     Refer now to  FIG. 16  illustrating driver circuits that provide a tri-state mode of operation in which both the high side FET and the low side FET are turned off. As in drawing figures in previous embodiments (see e.g.  FIG. 15 ), a two phase system is illustrated. A first phase has high side FET  40  and low side FET  50  series connected between +V and ground potential with the common node A therebetween connected to Inductor  60 . Inductor  60  is coupled to capacitor  70  and load  80 . Similarly, the second phase has high side FET  42  and low side FET  52  series connected between +V and ground potential with the common node B therebetween connected to Inductor  62 . Inductor  62  is also coupled to capacitor  70  and load  80 . An alternative way to implement this Buck converter circuit function is to replace the low side FETs (in this case  50  and  52 ) with diodes. Depending on the application, a diode may be preferred in place of a low side FET. 
     In a Buck converter having a high side FET and a low side FET, the duty cycle of the high side FET is increased when a higher current is demanded by the load and the duty cycle of the low side FET is increased when a lower current is demanded by the load. When switching between turning on the high side or low side FET, there is a brief interval when both FETs are off to avoid creating a DC current path from +V to ground potential. However, in Buck converters utilizing a diode in place of the low side FET, the diode begins to conduct immediately when the common node (e.g. A or B) drops one diode threshold below ground potential. By way of further explanation, FETs inherently have substrate diodes (also known as body diodes) that are usually not shown. Thus, FET  50  has body diode  51  and FET  52  has body diode  53 . These body diodes conduct current whenever the voltage drop from ground to the common node exceeds the threshold level of the diode. (Obviously, FETs  40  and  42  also have body diodes but these are not relevant to the present explanation.) 
     With continued reference to  FIG. 16 , note Schottky diode  54  connected in parallel to FET  50  between node A and ground potential and Schottky diode  56  connected in parallel to FET  52  between node B and ground potential. These also conduct as soon as their threshold levels are exceeded and avoid the creation of extremely high negative voltages that can occur at the common nodes A and B. In order to quickly compensate for transients at the load, it is desirable to maximize the output current slew rate. (Slew rate is defined by how quickly current can change through the inductor, e.g.  60  and  62 .) Slew rate (di/dt) is equal to V/L where V is the voltage across the inductor having inductance L. Assuming an output voltage (Vout) of approximately 2 volts, the voltage difference through the high side FET connected to +V (c. 12 volts) is far greater than the voltage difference through the low side FET connected to ground potential. It has been found that by placing both the high side FET and low side FET (e.g.  40  and  50 ) in a high impedance state when the current through the inductor is positive (i.e. being sourced from the power stage to the load), the current will flow through the Schottky diode or body diode, and the voltage across the inductor will be the output voltage plus the forward voltage of the diode, which maximizes the rate at which the current through the inductor is reduced compared to simply turning on the low side FET. 
     In order to achieve a tri-state output at nodes A and B (by putting both the high side and low side FET in a high impedance state), the input to each gate electrode must be held below threshold level. In the  FIG. 16  embodiment, tristate control in one phase is obtained with the use of series connected resistors R 16  and R 17  having their common connection connected to the inputs of driver circuit  32  and  34 . Driver circuit  32  provides an output when the input exceeds its threshold Vth. Driver circuit  34  provides an output when the input drops below Vtl. In the absence of an input from controller  1600  on the PWM line, the voltage at the node connecting R 16  and R 17  will reach a mid-point between +V and ground and the resultant output of drivers  32  and  34  will keep both FET  40  and  50  off. Of course, when the controller receives an internal enable signal then the internal pulse modulated signal PWM is outputted to the drivers and the respective high and low side FETs. 
     With continued reference to  FIG. 16 , note that in the second phase, tristate control is obtained with the use of series connected resistors R 18  and R 19  having their common connection connected to the inputs of driver circuit  36  and  38 . Driver circuit  36  provides an output when the input exceeds its threshold Vth. Driver circuit  38  provides an output when the input drops below Vtl. In the absence of an input from controller  1600  on the PWM 2  line, the voltage at the node connecting R 18  and R 19  will reach a mid-point between +V and ground and the resultant output of drivers  36  and  38  will keep both FET  42  and  52  off. As in the case of the first phase, when the controller receives an internal enable signal then the internal pulse modulated signal PWM is outputted to the drivers and the respective high and low side FETs. 
     Refer now to  FIG. 17 , which illustrates an alternative technique for placing the high side and low side FETs into a high impedance state providing the tri-state output. Elements corresponding to  FIG. 16  have been assigned similar reference numerals and operate in a similar manner. The difference from  FIG. 16  is that the  FIG. 17  embodiment provides a dual pulse width modulated N drive control. Controller  1700  includes logic elements  1702 ,  1704 ,  1706 ,  1708 ,  1710  and  1712  connected as shown. A separate pulse width modulated signal (PWM) is sent to the high side FET of each phase. Driver  1720  includes driver circuits  1722  and  1724  to drive phase  1  FETs  40  and  50 . Driver  1730  includes driver circuits  1732  and  1734  to drive phase  2  FETs  42  and  52 . 
     Refer now to  FIG. 18  which illustrates a dual PWM/enable technique for controlling the high side and low side FETs into a high impedance state providing the tri-state output. Controller  1800  includes logic elements  1802 ,  1804 ,  1806 , and  1808 , connected as shown. Driver  1820  includes driver circuit and logic elements  1822 ,  1824 ,  1826 ,  1828 , and  1830  connected, as shown. Driver  1830  includes driver circuit and logic elements  1922 ,  1924 ,  1926 ,  1928 , and  1930 , connected as shown. The remaining elements are identical to those in  FIG. 17  and are identified with corresponding reference numerals. The  FIG. 18  embodiment provides and enable signal when the high side FET and low side FET are intended to operate in their normal PWM mode. In the absence of an enable signal both the high side FET and low side FET are off, providing the desired tri-state high impedance output. 
     Refer now to  FIG. 19  which is a waveform diagram illustrating a 4 phase example of using a high impedance (tri-state) technique for transient compensation. The four PWM waveforms are as shown in normal multi-phase operation. However, at the occurrence of a transient event the normal PWM 1 , PWM 2 , PWM 3  and PWM 4  pulses are suppressed and replaced with half height pulses. As a result, the Vout pulse has the desired lower output waveform with ATR, as compared with the excessive overshoot of an output waveform without ATR. 
     Refer now to  FIG. 20 , which is a schematic diagram showing the pulse limiting feature of the invention. The normal internal output of PWM generator  2000  is provided to gating circuit  2020 . The ATRH 1 , ATRH 2 , and ATRH 3  signals are received in pulse limiting circuits  2010 ,  2012 , and  2014 , respectively and combined in logic gate  2018 . The ATRL signal is received on line  2008  into pulse limiting circuit  2016 . The output of logic gate  2018  and the output of PWM generator  2000  are combined in logic gate and supplied to logic gate  2022  with the output of pulse limiting circuit  2016 . The output of logic gate  2022  is the external output of the pulse limited pulse width modulator. 
     In case of an ATRH or ATRL event, the ATR circuit detects an overvoltage or undervoltage condition during a transient event and responds by either turning on all the low side FETs or turning on one or more of the high side FETs to compensate for the transient condition, minimizing overshoot and undershoot. By pulse limiting this overriding ATR compensating signal (i.e. limiting the amount of time this circuit is on, then forcing it off for a fixed amount of time), the strength of this compensating action can be modified. This effectively changes the gain of this control mechanism. Varying the gain by adjusting the on and off times allows the transient response of the system to be optimized. 
     Refer now to  FIG. 21 , which is a schematic diagram of a pulse limiting circuit such as one of pulse limiting circuits  2010 ,  2012 ,  2014 , or  2016  in  FIG. 20 . The pulse limiting circuit includes programmable counters  2100  and  2102 , and logic gates  2104 ,  2106 , and  2108  all connected as shown. Programmable counter receives a clock input signal. As illustrated in the waveform diagram in  FIG. 22 , when the input pulse received at AND gate  2108  goes to its up level, the pulsed output goes to its up level because at that time TC 1  (the output of programmable counter  2100 ) is at its down level). As soon as TC 1  goes to its up level, the pulsed output goes to its down level and remains complementary to the TC 1  pulse until the input signal goes to its down level. The pulse limiting circuitry of  FIG. 21  determines the duty cycle of the TC 1  pulse. 
     What has then been described is a multi-phase pulse width modulated voltage regulator in which voltage excursions or deviations that exceed the load line voltage by more than a pre-determined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Transient response is further improved with an external ATR control circuit, a tri-state mode of operation, AVP pre-positioning, as well as an adaptive filter and pulse limiting techniques. 
     The present invention has been described above with reference to various exemplary embodiments. However, those skilled in the art will recognize that changes and modifications may be made to the exemplary embodiments without departing from the spirit and scope of the present invention. For example, the various components may be implemented in alternate ways, such as, for example, by providing other configurations of SPC&#39;s. By way of another example, the number of phases utilized is a matter of design choice. By way of a still further, the specific Pulse Width Modulator used to generate the PWM pulses is also a matter of design choice. Such changes or modifications are intended to be included within the spirit and scope of the present invention.