Patent Publication Number: US-7710200-B2

Title: Output buffer and power amplifier comprising thereof

Description:
RELATED APPLICATIONS 
   This Nonprovisional application claims priorities under 35 U.S.C. §119(a) on Patent Applications No. 10-2007-0077771, 10-2007-0077782 filed in Republic of Korea on Aug. 2, 2007, the entire contents of which are hereby incorporated by reference. 
   BACKGROUND OF THE INVENTION 
   1. Field of the Invention 
   The present invention relates to an output buffer and a power amplifier having the same. More particularly, the present invention relates to an output buffer having low output impedance and a power amplifier having the same. 
   2. Description of the Background Art 
     FIG. 1  is a circuit diagram of a NMOS source follower. Referring to  FIG. 1 , comparative low output impedance can be obtained because an output voltage V o  is obtained from a source node of a transistor M NSF . However, the output voltage V o  cannot increase higher than a value obtained by subtracting voltage drop V gs  from a gate voltage due to the voltage drop V gs  between a gate and a source. Therefore, the shown structure has a problem of a narrow swing range of the output voltage V o . 
     FIG. 2  is a circuit diagram that lowers output impedance of a PMOS common source through a negative feedback using an operational transconductance amplifier (OTA). Referring to  FIG. 2 , it is possible to swing an output voltage until a transistor M PCS  falls into a triode region because an output voltage V o  is obtained from a drain node of a transistor M PCS . That is, the output voltage may increase up to V dd -V dsat . Here, V dd  denotes a high level power voltage and V dsat  is an overdrive voltage. However, a PMOS common source amplifier has a shortcoming that output impedance is dynamic resistance, which is very large. Accordingly, a structure lowering impedance of an output node through a negative feedback using an operational transconductance amplifier (OTA) is introduced as shown in  FIG. 2 . In such a structure, output impedance is small at a low frequency zone where a gain of an OTA is large. However, output impedance becomes increased because a gain of an OTA decreases as a frequency increases. Therefore, low impedance cannot be obtained. 
     FIG. 3  is a circuit diagram illustrating an output stage that lowers output impendence using a negative feedback loop composed of a NMOS source follower, a PMOS common source amplifier, and a PMOS common gate amplifier. Referring to  FIG. 3 , the shown structure obtains very low output impedance that could not be obtained by a typical CMOS circuit by further lowering low output impedance of an NMOS source follower M NSF  by connecting a NMOS source follower M NSF  and a PMOS common source amplifier M PCS . The shown structure has a wide bandwidth characteristic because only one low frequency pole exists in a negative feedback loop, and very low output impedance can be sustained in a high frequency band thereby. However, a swing range of an output voltage is limited at a predetermined area as shown in  FIG. 4  due to a NMOS source follower M NSF  like  FIG. 1  according to  FIG. 3 . 
     FIG. 4  is a graph showing an operating zone of an output electric current I o  for an output voltage V o  of  FIG. 3 . 
   Referring to  FIG. 4 , there are four quadrants presented when relation of an output electric current I o  for an output voltage V o  is illustrated. Throughout the specification, if an output stage is operable at four quadrants, it is defined as the output stage performs four-quadrant operation, and if the output stage is operable at two sections of a quadrant, it is defined as the output stage performs two-quadrant operation for convenience. Although dual supply voltage was described, single supply voltage can be applied to an output stage structure according to the present invention without changing any structure. However, an intermediate value of an output voltage is ½ of a power source voltage for a single supply voltage although an intermediate value of an output voltage is 0 for dual supply voltage. 
     FIG. 5  is a circuit diagram illustrating an output stage that lowers output impedance using a negative feedback loop composed of a PMOS source follower, a PMOS common source amplifier, and a NMOS common gate amplifier, and  FIG. 6  is a diagram illustrating an operation zone of an output electric current I o  for an output voltage V o  of  FIG. 5 . Referring to  FIGS. 5 and 6 , the output stage of  FIG. 5  is different from that of  FIG. 3  in which a PMOS source follower M PSF  is connected to a PMOS common source amplifier M PCS . Unlike the output stage of  FIG. 3  that uses a common gate amplifier formed of a PMOS transistor M P1  for forming a negative feedback loop, the output stage of FIG.  5  uses a common gate amplifier formed of a NMOS transistor M N1 . Since the PMOS source follower M PSF  is used, an output voltage cannot decrease a lot due to the PMOS source follower M PSF  in the output stage of  FIG. 5 . Except that, the output stage of  FIG. 5  has the same characteristics of the output stage shown in  FIG. 3 .  FIG. 6  is a region where an output voltage is limited by a PMOS source follower M PSF . 
   SUMMARY OF THE INVENTION 
   Accordingly, an aspect of the present invention is to solve at least the problems and disadvantages of the background art. In accordance with an aspect of the present invention, an output buffer includes a push-pull circuit unit including transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage, an output unit connected to the high level power voltage and the low level power voltage, and a driver for driving the output unit according to a signal from the push-pull circuit unit. 
   Output impedance may be lowered by forming negative feedback loops with the push-pull circuit unit, the output unit, and the driver. 
   The push-pull circuit unit may include a NMOS source follower and a PMOS source follower, which are connected in the push-pull formation. 
   The driver may include a PMOS common gate having a source connected to a drain of the NMOS source follower, and a NMOS common gate having a drain connected to a drain of the PMOS common gate and a source connected to a drain of the PMOS source follower. 
   The output unit may include a PMOS common source having a source connected to the high level power voltage and a drain connected to an output node. 
   The output impedance may be lowered by forming a first negative feedback loop with the NMOS source follower, the PMOS common gate, and the PMOS common source and by forming a second negative feedback loop with the PMOS source follower, the NMOS common gate, and the PMOS common source. 
   In accordance with another aspect of the present invention, an output buffer includes: a push-pull circuit unit including transistors connected in a push-pull formation between a high level power voltage and a low level power voltage; an output unit connected between the high level power voltage and the low level power voltage; a driver for driving the output unit according to a signal from the push-pull circuit unit; and a rail-to-rail controller for widening a swing range of the output voltage by controlling ON-OFF of the transistors included in the push-pull circuit unit according to an input voltage. 
   The output impedance may be lowered by forming negative feedback loops with the push-pull circuit unit, the output unit, and the driver. 
   The push-pull circuit may include a NMOS source follower and a PMOS source follower connected in the push-pull formation. 
   The driver may include a first amplifier having an input connected to a drain of the NMOS source follower, and a second amplifier having an output connected to an output of the first amplifier and an input connected to a drain of the PMOS source follower. 
   The driver may include a PMOS common gate having a source connected to a drain of the NMOS source follower, and a NMOS common gate having a drain connected to a drain of the PMOS common gate and a source connected to a drain of the PMOS source follower. 
   The output unit may include a PMOS common source having a source connected to the high level power voltage and a drain connected to an output node. 
   The rail-to-rail controller may include a first switch for controlling ON-OFF of the NMOS source follower, and a second switch for controlling ON-OFF of the PMOS source follower. 
   When the input voltage is a middle level, the first switch may be turned on so as to form a first negative feedback loop with the NMOS source follower, the PMOS common gate, and the PMOS common source and the second switch may be turned on so as to form a second negative feedback loop with the PMOS source follower, the NMOS common gate, and the PMOS common source. 
   When the input voltage is a high level, the first switch may be turned off so as to form a second negative feedback loop with the PMOS source follower, the NMOS common gate, and the PMOS common source. 
   When the input voltage is a low level, the second switch may be turned off so as to form a first negative feedback loop with the NMOS source follower, the PMOS common gate, and the PMOS common source. 
   In accordance with still another aspect of the present invention, an output buffer includes a push-pull circuit unit including transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage, an output unit including common sources connected between the high level power voltage and the low level power voltage, an output bias unit for biasing the output unit, a driver for driving the output unit according to a signal from the push-pull circuit unit, and a rail-to-rail controller for widening a swing range of the output voltage by controlling ON-OFF of the transistors included in the push-pull circuit unit according to an input voltage. 
   Output impedance may be lowered by forming negative feedback loops with the push-pull circuit unit, the output unit, and the driver. 
   The push-pull circuit unit may include a NMOS source follower and a PMOS source follower connected in the push-pull formation. 
   The output unit may include a PMOS common source having a source connected to the high level power voltage and a drain connected to an output node and a NMOS common source having a drain connected to the output node and a source connected to the low level power voltage. 
   The rail-to-rail controller may include a first switch for controlling ON-OFF of the NMOS source follower, and a second switch for controlling ON-OFF of the PMOS source follower. 
   The driver may include: a first amplifier having an input connected to a drain of the NMOS source follower, and an output commonly connected to the output bias unit and a gate of the PMOS common source, and a second amplifier having an output commonly connected to the output bias unit and a gate of the NMOS common source and an input connected to a drain of the PMOS source follower. 
   When the input voltage is a middle level, the first switch may be turned on so as to form a first negative feedback loop with the NMOS source follower, the first amplifier, and the PMOS common source and a third negative feedback loop with the NMOS source follower, the first amplifier, and the NMOS common source, and the second switch is turned on so as to form a second negative feedback loop with the PMOS source follower, the second amplifier, and the PMOS common source, and a fourth negative feedback loop with the PMOS source follower, the second amplifier, and the NMOS common source. 
   The input voltage is a high level, the first switch may be turned off so as to form a second negative feedback loop with the PMOS source follower, the second amplifier, and the PMOS common source, and a fourth negative feedback loop with the PMOS source follower, the second amplifier, and the NMOS common source. 
   When the input voltage is a low level, the second switch may be turned off so as to form a first negative feedback loop with the NMOS source follower, the first amplifier, and the PMOS common source and a third negative feedback loop with the NMOS source follower, the first amplifier, and the NMOS common source. 
   The driver may include a common gate type of a first PMOS field effect transistor having a source connected to a drain of the NMOS source follower and a drain connected to the output bias unit and a common gate type of a first NMOS field effect transistor having a drain connected to the output bias unit and a source connected to a drain of the PMOS source follower. 
   The output bias unit may include a first translinear loop for biasing the PMOS common source, and a second translinear loop for biasing the NMOS common source. 
   The driver may include a first PMOS field effect transistor, a second PMOS field effect transistor, a first NMOS field effect transistor, and a second NMOS field effect transistor. Sources of the first and second PMOS field effect transistors may be connected to a drain of the NMOS source follower. The first bias voltage may be supplied to gates of the first and second PMOS field effect transistors, a drain of the first PMOS field effect transistor is connected to a drain of the first NMOS field effect transistor, a drain of the second PMOS field effect transistor may be connected to a drain of the second NMOS field effect transistor, sources of the first and second NMOS field effect transistors may be connected to a drain of the PMOS source follower, a reference voltage may be supplied to a gate of the first NMOS field effect transistor, and a gate of the NMOS field effect transistor may be connected to the output bias unit. 
   The output bias unit may include a third PMOS field effect transistor for sensing a main current of the PMOS common source, a third NMOS field effect transistor for sensing a main current of the NMOS common source, and an electric current selector for supplying a voltage corresponding to a smaller electric current between the main current of the PMOS common source and the main current of the NMOS common source to a gate of the second NMOS field effect transistor. 
   A source of the third PMOS field effect transistor may be connected to a source of the PMOS common source, a gate of the third PMOS field effect transistor is connected to a gate of the PMOS common source and a drain of the first NMOS field effect transistor, and a drain of the third PMOS field effect transistor is connected to the electric current selector, and a source of the third NMOS field effect transistor may be connected to a source of the NMOS common source, a gate of the third NMOS field effect transistor is connected to a gate of the NMOS common source and a drain of the second NMOS field effect transistor, and a drain of the third NMOS field effect transistor is connected to the electric current selector. 
   The driver may includes first to fourth PMOS field effect transistors and first to fourth NMOS field effect transistors, sources of the first and second PMOS field effect transistors may be connected to a drain of the NMOS source follower, the third PMOS field effect transistor may be cascode-connected to the first PMOS field effect transistor, the fourth PMOS field effect transistor may be cascode-connected to the second PMOS field effect transistor, sources of the first and second NMOS field effect transistors may be connected to a drain of the PMOS source follower, the third NMOS field effect transistor may be cascode-connected to the first NMOS field effect transistor, the fourth NMOS field effect transistor may be cascode-connected to the second NMOS field effect transistor, a drain of the third NMOS field effect transistor may be connected to a drain of the third PMOS field effect transistor, and a drain of the fourth NMOS field effect transistor is connected to a drain of the fourth PMOS field effect transistor. 
   The output bias unit may control gates of the PMOS common source and the NMOS common source by comparing a reference current with a smaller electric current between main electric currents of the PMOS common source and the NMOS common source. 
   The output bias unit may include a PMOS sensing transistor for outputting a first sensed electric current according to a main electric current of the PMOS common source, a NMOS sensing transistor for outputting a second sensed electric current according to a main electric current of the NMOS common source, and a bias controller for controlling a gate of the PMOS common source and a gate of the NMOS common source by comparing a reference current with an electric current obtained by dividing one of the first sensed electric current and the second sensed electric current by half through current mirroring. 
   The channel width of the PMOS sensing transistor may be narrower than a channel width of the PMOS common source, and a channel width of the NMOS sensing transistor may be narrower than a channel width of the NMOS common source. 
   In accordance with further another aspect of the present invention, a power amplifier may include an output buffer including a push-pull circuit unit having transistors connected to each others in a push-pull formation between a high level power voltage and a low level power voltage, an output unit including common sources connected between the high level power voltage and the low level power voltage, an output bias unit for biasing the output unit, and a driver for driving the output unit according to a signal from the push-pull circuit unit, a rail-to-rail controller for widening a swing range of the output voltage by controlling ON-OFF of transistors included in the push-pull circuit unit according to an input voltage of the output buffer, a feedback unit for feedbacking the output voltage to an input unit, and an amplifier for amplifying difference between an input voltage and the feedbacked output voltage. 
   The push-pull circuit unit may include a NMOS source follower and a PMOS source follower connected in the push-pull formation. 
   The output unit may include a PMOS common source having a source connected to the high level power voltage and a drain connected to an output node, and a NMOS common source having a drain connected to the output node and a source connected to the low level power voltage. 
   The rail-to-rail controller may include a PMOS switch for controlling ON-OFF of the NMOS source follower, and a NMOS switch for controlling ON-OFF of the PMOS source follower. 
   The driver may include first to fourth PMOS field effect transistor, and first and fourth NMOS field effect transistors. Sources of the first and second PMOS field effect transistors may be connected to a drain of the NMOS source follower, the third PMOS field effect transistor may be cascode-connected to the first PMOS field effect transistor, the fourth PMOS field effect transistor may be cascode-connected to the second PMOS field effect transistor, sources of the first and second NMOS field effect transistors may be connected to a drain of the PMOS source follower, the third NMOS field effect transistor may be cascode-connected to the first NMOS field effect transistor, the fourth NMOS field effect transistor may be cascode connected to the second NMOS field effect transistor, a drain of the third NMOS field effect transistor may be connected to a drain of the third PMOS field effect transistor, and a drain of the fourth NMOS field effect transistor may be connected to a drain of the first PMOS field effect transistor. 
   The output bias unit may control gates of the PMOS common source and the NMOS common source by comparing a reference current with a smaller electric current between main electric currents of the PMOS common source and the NMOS common source. 
   The output bias unit may include a PMOS sensing transistor for outputting a first sensed electric current according to a main electric current of the PMOS common source, an NMOS sensing transistor for outputting a second sensed electric current according to a main electric current of the NMOS common source, and a bias controller for controlling a gate of the PMOS common source and a gate of the NMOS common source by comparing a reference current with an electric current obtained by dividing one of the first sensed electric current and the second sensed electric current by half through current mirroring. 
   A channel width of the PMOS sensing transistor may be narrower than a channel width of the PMOS common source, and a channel width of the NMOS sensing transistor may be narrower than a channel width of the NMOS common source. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention will be described in detail with reference to the following drawings in which like numerals refer to like elements. 
       FIG. 1  is a circuit diagram of a NMOS source follower. 
       FIG. 2  is a circuit diagram that lowers output impedance of a PMOS common source through a negative feedback using an operational transconductance amplifier (OTA). 
       FIG. 3  is a circuit diagram illustrating an output stage that lowers output impendence using a negative feedback loop composed of a NMOS source follower, a PMOS common source amplifier, and a PMOS common gate amplifier. 
       FIG. 4  is a graph showing an operating zone of an output electric current I o  for an output voltage V o  of  FIG. 3 . 
       FIG. 5  is a circuit diagram illustrating an output stage that lowers output impedance using a negative feedback loop composed of a PMOS source follower, a PMOS common source amplifier, and a NMOS common gate amplifier. 
       FIG. 6  is a diagram illustrating an operation zone of an output electric current I o  for an output voltage V o  of  FIG. 5 . 
       FIG. 7  is a diagram illustrating an output buffer according to a first embodiment of the present invention. 
       FIG. 8  is a graph showing an operation zone of an output electric current I o  for an output voltage V o  of an output buffer according to the first embodiment shown in  FIG. 7 . 
       FIG. 9  is a diagram illustrating an output buffer according to a second embodiment of the present invention. 
       FIG. 10  is a diagram illustrating an output buffer according to a third embodiment of the present invention. 
       FIG. 11  is a graph illustrating an operating zone of an output electric current I o  for an output voltage V o  in an output buffer according to the third embodiment shown in  FIG. 10 . 
       FIG. 12  is a diagram illustrating an output buffer according to a fourth embodiment of the present invention. 
       FIG. 13  is a graph illustrating an operating zone of an output electric current I o  for an output voltage V o  in an output buffer according to the fourth embodiment shown in  FIG. 12 . 
       FIG. 14  is a diagram illustrating an output buffer according to a fifth embodiment of the present invention. 
       FIG. 15  is a diagram illustrating an output buffer according to a sixth embodiment. 
       FIG. 16  is a diagram illustrating an output buffer according to a seventh embodiment of the present invention. 
       FIG. 17  is a diagram illustrating an output buffer according to an eighth embodiment of the present invention. 
       FIG. 18  is a diagram illustrating an output buffer according to a ninth embodiment of the present invention. 
       FIG. 19  is a diagram illustrating a power amplifier according to a first embodiment of the present invention. 
       FIG. 20  is a diagram illustrating a power amplifier according to the second embodiment of the present invention. 
       FIG. 21  is a graph showing results of simulations that obtains output impedance characteristics of a power amplifier of  FIG. 20  when an output voltage is a maximum level and an output voltage is a middle level. 
   

   DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
   Preferred embodiments of the present invention will be described in a more detailed manner with reference to the drawings. 
   It is an object of the present invention to provide an output buffer and a power amplifier for effectively supplying an output electric current. 
   It is another object of the present invention to provide an output buffer and a power amplifier for sustaining low output impedance while supplying and absorbing electric current at a predetermined output voltage and obtains a wide output voltage swing range. 
   Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings. 
     FIG. 7  is a diagram illustrating an output buffer according to a first embodiment of the present invention. Referring to  FIG. 7 , the output buffer according to the first embodiment includes a push-pull circuit unit  10 , an output unit  31 , and a driver  21 . 
   The push-pull circuit unit  10  includes transistors connected to each others in a push-pull formation between a high level power voltage +V dd  and a low level power voltage −V dd . In more detail, the push-pull circuit unit  10  may include a NMOS source follower M NSF  connected to an electric current source of the high level power voltage +V dd  side and a PMOS source follower M PSF  connected to an electric current source of the low level power voltage −V dd  side. The push-pull circuit unit  10  has low output impedance because of the MNOS source follower M NSF  and the PMOS source follower M PSF , which are connected in a push-pull formation. 
   The output unit  31  is connected between the high level power voltage +V dd  and the low level power voltage −V dd . In more detail, the output unit  31  may be a PMOS common source M PCS  having a source connected to the high level power voltage +V dd  and a drain connected to an output node. The output unit  31  widens a swing range of an output voltage V o  and supplies most of an output electric current I o . 
   The driver  21  drives the output unit  31  according to a signal from the push-pull circuit unit  10 . The driver  21  may include a PMOS common gate M P1  having a source connected to a drain of the NMOS source follower M NSF  and an NMOS common gate M N1  having a drain connected to a drain of the PMOS common gate M P1 , and a source connected to a drain of the PMOS source follower M PSF . 
   Output impedance is lowered by forming negative feedback loops with the push-pull circuit unit  10 , the output unit  31 , and the driver  21 , which are included in the output buffer according to the first embodiment. In more detail, the NMOS source follower M NSF  included in the push-pull circuit unit  10 , the PMOS common gate M P1  included the driver  21 , and the PMOS common source M PCS  included in the output unit  31  form a first negative feedback loop M NSF −M P1 −M PCS . Also, the PMOS source follower M PSF  included in the push-pull circuit unit  10 , the NMOS common gate M N1  included in the driver  21 , and the PMOS common source M PCS  included in the output unit  31  form a second negative feedback loop M PSF −M N1 −M PCS . The first and second negative feedback loops lower output impedance as much as times of a loop gain. 
   The output buffer according to the first embodiment has a better electric current supplying capability than an electric current absorbing capability. That is, the output buffer according to the first embodiment has a structure for two-quadrant operation that mainly considers a supplying side of an output electric current I o . In more detail, a first negative feedback loop M NSF −M P1 −M PCS  is formed by connecting the NMOS source follower M NSF  and the PMOS common gate M P1  to the PMOS common source M PCS  supplying most of an output electric current I o  and a second negative feedback loop M PSF −M N1 −M PCS  is formed by connecting the PMOS source follower M PSF  and the NMOS common gate M N1  to the PMOS common source M PCS . Accordingly, low output impedance can be sustained at a high frequency band because of two negative feedback loops such as the first and second negative feedback loops M NSF −M P1 −M PCS , M PSF −M N1 −M PCS . 
     FIG. 9  is a diagram illustrating an output buffer according to a second embodiment of the present invention. Referring to  FIG. 9 , the output buffer according to the second embodiment includes a push-pull circuit unit  10 , an output unit  31 , a driver  22 , and a rail-to-rail controller  40 . 
   The push-pull circuit unit  10  includes transistors connected to each others in a push-pull formation between a high level power voltage +V dd  and a low level power voltage −V dd . In more detail, the push-pull circuit unit  10  may include a NMOS source follower M NSF  connected to a current source of the high level power voltage +V dd  side and a PMOS source follower M PSF  connected to a current source of the low level power voltage −V dd  side. The push-pull circuit unit  10  has low output impedance because of the NMOS source follower M NSF  and the PMOS source follower M PSF , which are connected in a push-pull formation. 
   The output unit  31  is connected between high level power voltage +V dd  and low level power voltage −V dd . In more detail, the output unit  31  may be a PMOS common source M PCS  having a source connected to the high level power voltage +V dd  and a drain connected to an output node. The output unit  31  widens a swing range of an output voltage V o  and supplies most of an output electric current I o . 
   The driver  22  drives the output unit  31  according to a signal from the push-pull circuit unit  10 . The driver  22  may include a first amplifier A 1  having an input connected to a drain of the NMOS source follower M NSF  and a second amplifier A 2  having an output connected to an output unit of the first amplifier and an input connected to a drain of the PMOS source follower M PSF . 
   The rail-to-rail controller  40  widens a swing rage of an output voltage V o  by controlling ON-OFF of transistors included in the push-pull circuit unit  10  according to an input voltage V i  of the output buffer. The rail-to-rail controller  40  may include a first switch SW 1  for controlling ON-OFF of the NMOS source follower M NSF  and a second switch SW 2  for controlling ON-OFF of the PMOS source follower M PSF . 
   Hereinafter, the operations of the rail-to-rail controller  40  according to an input voltage V i  of a buffer will be described. 1) When the input voltage V i  is a middle level, the first switch SW 1  is turned on, thereby forming a first negative feedback loop with the NMOS source follower M NSF , the first amplifier A 1 , and the PMOS common source M PCS , and the second switch SW 2  is turned on, thereby forming a second negative feedback loop with the PMOS source follower M PSF , the second amplifier A 2 , and the PMOS common source M PCS . 2) When the input voltage V i  is high level, only the second negative feedback loop is formed with the PMOS source follower M PSF , the second amplifier A 2 , and the PMOS common source M PCS  because the NMOS source follower M NSF  is turned off by the first switch SW 1  that is turned off by the high level input voltage V i . 3) When an input voltage V i  is low level, only the first negative feedback loop is formed with the NMOS source follower M NSF , the first amplifier A 1 , and the PMOS common source M PCS  because the PMOS source follower M PSF  is turned off by the second switch SW 2  which is turned off by the low level input voltage. 
   The output buffer according to the second embodiment can supply a large output electric current with low output impedance sustained even at a high frequency because at least one of the negative feedback loops is formed for any output voltages. 
     FIG. 10  is a diagram illustrating an output buffer according to a third embodiment of the present invention. Referring to  FIG. 10 , the output buffer according to the third embodiment includes a push-pull circuit unit  10 , an output unit  31 , a driver  21 , and a rail-to-rail controller  40 . 
   The push-pull circuit unit  10  includes transistors connected to each others in a push-pull formation between a high level power voltage +V dd  and a low level power voltage −V dd . In more detail, the push-pull circuit unit  10  may include a NMOS source follower M NSF  connected to a current source of the high level power voltage +V dd  side and a NMOS source follower M PSF  connected to a current source of the low level power voltage −V dd  side. The push-pull circuit unit  10  has low output impedance due to the NMOS source follower M NSF  and the PMOS source follower M PSF  connected in a push-pull formation. 
   The output unit  31  is connected between the high level power voltage +V dd  and the low level power voltage −V dd . In more detail, the output unit  31  may be a PMOS common source M PCS  having a source connected to the high level power voltage +V dd  and a drain connected to an output node. The output unit  31  widens a swing range of an output voltage V o  and supplies most of an output electric current I o . 
   The driver  21  drives the output unit  31  according to a signal from the push-pull circuit unit  10 . The driver  22  includes a PMOS common gate MP 1  having a source connected to a drain of the NMOS source follower M NSF  and a NMOS common gate M N1  having a drain connected to a drain of the PMOS common gate M P1  and a source connected to a drain of the PMOS source follower M PSF . 
   The rail-t-rail controller  40  controls ON-OFF states of transistors included in the push-pull circuit unit  10  according to the input voltage V i  of the buffer, thereby widening the swing range of the output voltage V o . The rail-to-rail controller  40  includes a first switch SW 1  for controlling ON-OFF of the NMOS source follower M NSF  and a second switch SW 2  for controlling ON-OFF of the NMOS source follower M PSF . 
   Hereinafter, the operations of the rail-to-rail controller  40  according to the input voltage V i  of the buffer will be described. 1) When an input voltage V i  is a middle level, a first negative feedback loop is formed with the NMOS source follower M NSF , the PMOS common gate M P1 , and the PMOS common source M PCS  by turning on the first switch SW 1  and a second negative feedback loop is formed with the PMOS source follower M PSF , the NMOS common gate M N1 , and the PMOS common source M PCS , by turning on the second switch SW 2 . That is, when the input voltage V i  is an middle level, the first and second switches are turned on thereby supplying an electric current I 2  to the NMOS source follower M NSF  and the PMOS source follower M PSF . Accordingly, two negative feedback loops M NSF −M P1 −M PCS , M PSF −M N1 −M PCS  are formed and the output electric current is supplied thereby. 2) When an input voltage V i  is high level, the first switch SW 1  is turned off, thereby only forming the second negative feedback loop with the PMOS source follower M PSF , the NMOS common gate M N1 , and the PMOS common source M PCS . That is, when the input voltage V i  is a positive high level, the first switch SW 1  is turned off thereby interrupting the supplement of the electric current I 2 . Therefore, the NMOS source follower M NSF  is turned off and the first negative feedback loop is disconnected by the NMOS source follower M NSF . Only the second negative feedback loop is formed with the PMOS source follower M PSF , the NMOS common gate M N1 , and the PMOS common source M PCS . The second negative feedback loop M PSF −M N1 −M PCS  supplies an output current and sustains low output impedance. Since the NMOS source follower M NSF  disturbing a positive output voltage swing is turned off, it is possible to obtain a sufficient positive output voltage range. 3) when an input voltage V i  is a low level, the second switch SW 2  is turned off and the first negative feedback loop is formed with the NMOS source follower M NSF , the PMOS common gate M P1 , and the PMOS common source M PCS . That is, when the input voltage V i  is a negative low level, the second switch SW 2  is turned off and the supplement of an electric current I 2  is interrupted. Accordingly, the second negative loop is disconnected by the PMOS source follower M PSF  because the PMOS source follower M PSF  is turned off. The first negative feedback loop formed of the NMOS source follower M NSF , the PMOS common gate M P1 , and the PMOS common source M PCS  supplies an output current and sustains low output impedance. Since the PMOS source follower M PSF  disturbing a negative output voltage swing is turned off, it is possible to obtain sufficient negative output voltage range. 
   As described above, the output buffer according to the third embodiment can supply a large output electric current in a wide output voltage swing range with low output impedance sustained even in a high frequency band because the output buffer according to the third embodiment keeps at least one negative feedback loops formed even for any output voltages. 
     FIG. 11  is a graph illustrating an operating zone of an output electric current I o  for an output voltage V o  in an output buffer according to the third embodiment shown in  FIG. 10 . Referring to  FIG. 11 , the graph clearly shows that the output buffer according to the third embodiment can supply an output electric current for any output voltage in a first section and a second section of a quadrant. That is, the output buffer according to the third embodiment operates in two complete sections of a quadrant. 
     FIG. 12  is a diagram illustrating an output buffer according to a fourth embodiment of the present invention. Referring to  FIG. 12 , the output buffer according to the fourth embodiment includes a push-pull circuit unit  10 , an output unit  32 , an output bias unit  51 , a driver  22 , and a rail-to-rail controller  40 . 
   The push-pull circuit unit  10  includes transistors connected to each others in a push-pull formation between a high level power voltage +V dd  and a low level power voltage −V dd . In detail, the push-pull circuit unit  10  may include a NMOS source follower M NSF  connected to an electric current source of a high level power voltage +V dd  side and a PMOS source follower M PSF  connected to an electric current source of a low level power voltage −V dd  side. The push-pull circuit unit  10  has low output impedance because of the NMOS source follower M NSF  and the PMOS source follower M PSF  connected in the push-pull formation. 
   The output unit  32  is connected between the high level power voltage +V dd  and the low level power voltage −V dd . In detail, the output unit  32  may include a PMOS common source M PCS  having a source connected to the high level power voltage +V dd  and a drain connected to an output node and a NMOS common source M NCS  having a drain connected to an output node. The output unit  32  widens a swing range of an output voltage V o  and supplies most of an output electric current l o . The output unit  32  enables the output buffer according to the fourth embodiment to efficiently supply and absorb an output electric current I o . That is, the PMOS common source M PCS  and the NMOS common source M NCS  make the output buffer to operate in quadrant. In the concrete, the output buffer according to the fourth embodiment can efficiently supply and absorb an output electric current I o  by a first negative feedback loop composed of an NMOS source follower M NSF , a first amplifier A 1 , and a PMOS common source M PCS , a second negative feedback loop composed of a PMOS source follower M PSF , a second amplifier A 2 , and a PMOS common source M PCS , a third negative feedback loop composed of a NMOS source follower M NSF , a first amplifier A 1 , and a NMOS common source M NCS , and a fourth negative feedback loop composed of a PMOS source follower M PSF , a second amplifier A 2 , and an NMOS common source M NCS . 
   The driver  22  drives the output unit  32  according to a signal from the push-pull circuit unit  10 . The driver  22  may include a first amplifier A 1  having an input connected to a drain of a NMOS source follower M NSF  and an output unit commonly connected to an output bias unit  51  and a gate of a PMOS common source M PCS , and a second amplifier A 2  having an output commonly connected to an output bias unit  51  and a gate of a NMOS common source M NCS  and an input connected to a drain of a PMOS source follower M PSF . 
   The rail-to-rail controller  40  widens a swing range of an output voltage V o  by controlling ON-OFF of transistors included in the push-pull circuit unit  10  according to an input voltage V i  of a buffer. The rail-to-rail controller  40  may include a first switch SW 1  for controlling ON-OFF of a NMOS source follower M NSF  and a second switch SW 2  for controlling ON-OFF of a PMOS source follower M PSF . 
   Hereinafter, operations of the rail-to-rail controller  40  according to the input voltage V i  will be described. 1) When the input voltage V i  is a middle level, the first switch SW 1  is turned on, thereby forming a first negative feedback loop with the NMOS source follower M NSF , the first amplifier, and the PMOS common source M PCS , and forming a third negative feedback loop with the NMOS source follower M NSF , the first amplifier A 1 , and the NMOS common source M NCS . Also, the middle level input voltage V i  turns on the second switch SW 2 , thereby forming a second negative feedback loop with the PMOS source follower M PSF , the second amplifier A 2 , and the PMOS common source M PCS  and forming a fourth negative feedback loop with the PMOS source follower M PSF , the second amplifier A 2 , and the NMOS common source M NCS . That is, if the input voltage V i  is the middle level, an electric current I 2  is supplied to the NMOS source follower M NSF , the PMOS source follower M PSF , the first amplifier A 1 , and the second amplifier A 2  through the turned on first and second switches SW 1  and SW 2 . Accordingly, four negative feedback loops M NSF −A 1 −M PCS , M PSF −A 2 −M PCS , M NSF −A 1 −M NCS , M PSF −A 2 −M NCS  are formed, and the formed four negative feedback loops enables the output buffer according to the present embodiment to supply and absorb an output electric current with low output impedance sustained. 2) When an input voltage V i  is a high level, the first switch SW 1  is turned off, thereby forming the second negative feedback loop M PSF −A 2 −M PCS  and the fourth negative feedback loop M PSF −A 2 −M NCS . That is, if the input voltage V i  is a positive (+) high level, the first switch SW 1  is turned off, thereby interrupting the supplement of the electric current I 2 . Accordingly, the NMOS source follower M NSF  is turned off. Because of the turned off NMOS source follower M NSF , the first and third negative feedback loops M NSF −A 1 −M PCS  and M NSF −A 1 −M NCS  are disconnected. Also, the PMOS source follower M PSF  enables the second and fourth negative feedback loops M PSF −A 2 −M PCS  and M PSF −A 2 −M NCS  to supply and absorb an output electric current with low output impedance sustained. Since the NMOS source follower M NSF  that disturbs the swing of a positive output voltage is turned off, a positive (+) output voltage range can be sufficiently obtained. 3) When the input voltage V i  is a low level, the second switch SW 2  is turned off, thereby forming the first and third negative feedback loops M NSF −A 1 −M PCS  and M NSF −A 1 −M NCS . That is, if the input voltage V i  is a negative (−) low level, the second switch SW 2  is turned off, thereby interrupting the supplement of the electric current I 2 . Accordingly, the PMOS source follower M PSF  is turned off. Therefore, the turned off PMOS source follower M PSF  disconnects the second and fourth negative feedback loops M PSF −A 2 −M PCS  and M PSF −A 2 −M NCS , and the NMOS source follower M NSF  enables the first and third negative feedback loops M NSF −A 1 −M PCS  and M NSF −A 1 −M NCS  to supply and absorb an output electric current with low output impedance sustained. Since the PMOS source follower M PSF  that disturbs the swing of a negative output voltage is turned off, a negative (−) output voltage range can be obtained sufficiently. 
   In the output buffer according to the fourth embodiment, the output unit  32  is connected to the PMOS common source M PCS  and the NMOS common source M NCS  in the push-pull structure to enable both of supplying and absorbing an output electric current. Therefore, the output buffer according to the fourth embodiment further includes the output bias unit  51  for controlling a bias electric current of the PMOS common source M PCS  and the NMOS common source M NCS . 
   As described above, the output buffer according to the fourth embodiment can supply and absorb a high output electric current with low output impedance sustained even in a high frequency band because at least two negative feedback loops are kept formed for any output voltages. Therefore, it is possible to obtain an output electric current characteristic for an output voltage that can be operated in all four sections of a quadrant. Unlike typical output buffers, the output buffer according to the present embodiment has a structure close to an ideal buffer design because the output buffer according to the present embodiment can sustain low output impedance at a high frequency, be operable in four sections of a quadrant, have a wide output voltage range, and have a large output electric current driving capability. 
     FIG. 14  is a diagram illustrating an output buffer according to a fifth embodiment of the present invention. Referring to  FIG. 14 , the output buffer according to the fifth embodiment includes a push-pull circuit unit  10 , an output unit  32 , an output bias unit  52 , a driver  21 , and a rail-to-rail controller  40 . 
   Hereinafter, the output buffer according to the fifth embodiment will be described based on the driver  21  and the output bias unit  52 , which are the main features thereof, by comparing with the output buffer according to the fourth embodiment. 
   The driver  21  may includes a first PMOS field effect transistor M P1  having a source connected to a drain of a NMOS source follower M NSF  and a drain connected to the output bias unit  52  in a common gate form and a first NMOS field effect transistor M N1  having a drain connected to the output bias unit  52  and a source connected to a drain of a PMOS source follower M PSF  in a common gate form. 
   The output bias unit  52  biases the output unit  32  and is a FeedForward Class-AB Bias current control type. 
   The output bias unit  52  may include a first translinear loop M P3 −M P4 −M P2 −M PCS  for biasing a PMOS common source M PCS  and a second translinear loop M N3 −M N4 −M N2 −M NCS  for biasing a NMOS common source M NCS . 
   DC bias electric currents of a PMOS common source M PCS  and a NMOS common source M NCS  of the output unit  32  are decided by the first and second translinear loops M P3 −M P4 −M P2 −M PCS  and M N3 −M N4 −M N2 −M NCS . Accordingly, a minimum electric current is guaranteed not to turn off a NMOS common source M NCS  while supplying an output electric current and not to turn off a PMOS common source M PCS  while absorbing an output electric current. 
   As compared with a Feedback Class-AB Bias current control type that control a DC bias electric current and a minimum electric current by sensing an electric current of a PMOS common source M PCS  and a NMOS common source M NCS , the output bias unit  52  in the output buffer according to the fifth embodiment is a FeedForward Class-AB Bias current control type. 
   Meanwhile, a source follower biasing block  61  is embodied as a voltage source V GG  for deciding a bias electric current of a NMOS source follower M NSF  and a PMOS source follower M PSF  formed in a push-pull structure. 
     FIG. 15  is a diagram illustrating an output buffer according to a sixth embodiment. Referring to  FIG. 15 , the output buffer according to the sixth embodiment includes a push-pull circuit unit  10 , an output unit  32 , an output bias unit  53 , a driver  23 , and a rail-to-rail controller  40 . 
   Hereinafter, the output buffer according to the sixth embodiment will be described based on the driver  23  and the output bias unit  53 , which are the main features thereof, by comparing with the output buffer according to the fourth embodiment. 
   The driver  23  includes a first PMOS field effect transistor M P1 , a second PMOS field effect transistor M P2 , a first NMOS field effect transistor M N1 , and a second NMOS field effect transistor M N2 . 
   The sources of the first and second PMOS field effect transistors M P1  and M P2  are connected to a drain of a NMOS source follower M NSF , and a first bias voltage V bias1  is supplied to gates of the first and second PMOS field effect transistors M P1  and M P2 . A drain of the first PMOS field effect transistor M P1  is connected to a drain of the first NMOS field effect transistor M N1 , and a drain of the second PMOS field effect transistor M P2  is connected to a drain of the second NMOS field effect transistor M N2 . Sources of the first and second NMOS field effect transistors M N1  and M N2  are connected to a drain of the PMOS source follower M PSF , a reference voltage V REF  is supplied to a gate of the first NMOS field effect transistor M N1 , and a gate of the second NMOS field effect transistor M N2  is connected to the output bias unit  53 . 
   The output bias unit  53  may include a third PMOS field effect transistor M PS  for detecting a electric current of a PMOS common source M PCS , a third NMOS field effect transistor M NS  for detecting a electric current of a NMOS common source M NCS , and an electric current selector  531  for supplying a voltage to a gate of the second NMOS field effect transistor M N2  according to a smaller one of the electric current of the third NMOS field effect transistor M NS  and the electric current of the third PMOS field effect transistor M PS . 
   A source of a third PMOS field effect transistor M PS  is connected to a source of the PMOS common source M PCS , and a gate of the third PMOS field effect transistor M PS  is connected to a gate of the PMOS common source M PCS  and a drain of the first NMOS field effect transistor M N1 . A drain of the third PMOS field effect transistor M PS  is connected to the electric current selector  531 , and a source of the third NMOS field effect transistor M NS  is connected to a source of the NMOS common source M NS . A gate of the third NMOS field effect transistor M NS  is connected to a gate of the NMOS common source M NCS  and a drain of the second NMOS field effect transistor M N2 , and a drain of the third NMOS field effect transistor M NS  is connected to the electric current selector  531 . 
   Hereinafter, the operation of the output bias unit  53  included in the output buffer according to the sixth embodiment shown in  FIG. 15  will be described. 
   For class-AB bias current control, the output bias unit  53  1) detects electric currents of the PMOS common source M PCS  and the NMOS common source M NCS  included in the output unit  32 , 2) selects a smaller electric current from the detected two electric currents using the electric current selector  531 , and 3) controls a DC bias electric current and a minimum electric current of the PMOS common source M PCS  and the NMOS common source M NCS  included in the output unit  32  by transforming the selected minimum current to a voltage and comparing the voltage with a reference voltage V REF  supplied to a gate of the first NMOS transistor M N1 . 
   In order to obtain electric currents in proportion to the main electric currents, it is preferable to design the third PMOS transistor M PS  to have a narrower channel width than that of the PMOS common source M PCS  by reducing a channel width at a predetermined rate and to design the third NMOS transistor M NS  to have a narrower channel width than that of the NMOS common source M NCS  by reducing a channel width at a predetermined rate. 
   The electric current selector  531  selects a smaller electric current from electric currents detected by the third PMOS transistor M PS  and the third NMOS transistor M NS , and a differential signal is generated to control gates of the PMOS common source M PCS  and the NMOS common source M NCS  in order that a voltage obtained from the selected electric current may be equal to a reference voltage V REF  by a negative feedback loop. In order to individually control gates of the third PMOS transistor M PS  and the third NMOS transistors M NS  using the differential signal, the driver  23  forms a first path composed of the first NMOS field effect transistor M N1  and the first PMOS field effect transistor M P1  and a second path composed of the second NMOS field effect transistor M N2  and the second PMOS field effect transistor M P2 , connects a gate of the PMOS common source M PCS  to the first path, and connects a gate of the NMOS common source M PCS  to the second path. When one of the PMOS common source M PCS  and the NMOS common source M NCS  drives a load, the other supplies a preset minimum electric current using the output bias unit  53  without being turned off. Since the PMOS common source M PCS  and the NMOS common source M NCS  are not turned off, it is possible to reduce distortion that is formed by delay of turning back on after being turned off. 
     FIG. 16  is a diagram illustrating an output buffer according to a seventh embodiment of the present invention. 
   Hereinafter, the output buffer according to the seventh embodiment will be described based on a driver  24 , which is a major feature thereof, by comparing with the output buffer according to the sixth embodiment with reference to  FIG. 16 . 
   Unlike the output buffer according to the sixth embodiment that generates a control signal by transforming a selected minimum electric current to a voltage and comparing the voltage with a reference voltage, the output buffer according to the seventh embodiment generates control signals for controlling gates of a PMOS common source M PCS  and a NMOS common source M NCS  by directly comparing a selected minimum electric current with a reference current without transforming the selected minimum electric current to a voltage. 
   Referring to  FIG. 16 , the output buffer according to the seventh embodiment further includes cascode transistors formed of a third PMOS field effect transistor M P3 , a fourth PMOS field effect transistor M P4 , a third NMOS field effect transistor M N3 , and a fourth NMOS field effect transistor M N4  as compared with the output buffer of  FIG. 15 . 
   In more detail, the driver  24  includes first to fourth PMOS field effect transistors M P1 , M P2 , M P3 , and M P4 , and first to fourth NMOS transistors M N1 , M N2 , M N3 , and M N4 . 
   Sources of the first and second PMOS field effect transistors M P1  and M P2  are connected to a drain of an NMOS source follower M NSF , and the third PMOS field effect transistor M P3  is cascode-connected to the first PMOS field effect transistor M P1 . The fourth PMOS field effect transistor M P4  is cascode-connected to the second PMOS field effect transistor M P2 , and the sources of the first and second NMOS field effect transistors M N1  and M N2  are connected to a drain of a PMOS source follower M PSF . The third NMOS field effect transistor M N3  is cascode-connected to the first NMOS field effect transistor M N1 , and the fourth NMOS field effect transistor M N4  is cascode-connected to the second NMOS field effect transistor M N2 . A drain of the third NMOS field effect transistor M N3  is connected to a drain of the third PMOS field effect transistor M P3 , and a drain of the fourth NMOS field effect transistor M N4  is connected to a drain of the fourth PMOS field effect transistor M P4 . 
   Since the output buffer according to the sixth embodiment shown in  FIG. 15  transforms a selected minimum electric current to a voltage and compares the voltage with a reference voltage V REF , a pole is formed, which may influence a phase margin at a node for transforming the selected minimum electric current to a voltage, that is a gate node of the transistor M N2 . On the contrary, the output buffer according to the seventh embodiment of  FIG. 16  has an advantage of forming a pole at a high frequency area as much as not influencing a phase margin because gate control electric currents of the PMOS common source M PCS  and the NMOS common source M NCS  are supplied to source nodes of the cascode transistors. 
     FIG. 17  is a diagram illustrating an output buffer according to an eighth embodiment of the present invention. 
   Hereinafter, the output buffer according to the eighth embodiment will be described based on an output bias unit  55 , which is a main feature thereof, by comparing with the output buffer according to the seventh embodiment with reference to  FIG. 17 . 
   Referring to  FIG. 17 , the output bias unit  55  controls gates of a PMOS common source M PCS  and a NMOS common source M NCS  by comparing a reference current I REF  with a smaller electric current between main electric currents of a PMOS common source M PCS  and a NMOS common source M NCS . 
   The control operation of the output bias unit  55  will be described in more detail. 
   1) Two minimum electric current selection circuits M NS1 −M PS1 −M P5 −M P6 , and M NS2 −M PS2 −M N5 −M N6  select a smaller electric current between main electric currents of the PMOS common source M PCS  and the NMOS common source M NCS . 2) Signals are generated for controlling gates of the PMOS common source M PCS  and the NMOS common source M NCS  by comparing the selected electric current with a reference electric current I REF . 
   In order to generate a sensed current in proportion to the main electric currents of the PMOS common source M PCS  and the NMOS common source M NCS , the transistors M PS1  and M PS2  are designed to have a channel width narrower than that of the PMOS common source M PCS  at a predetermined rate, and the transistors M NS1  and M NS2  are designed to have a channel width narrower than that of the NMOS common source M NCS  at a predetermined rate. 
     FIG. 18  is a diagram illustrating an output buffer according to a ninth embodiment of the present invention. Referring to  FIG. 18 , the output buffer according to the ninth embodiment includes a push-pull circuit unit  10 , an output unit  32 , an output bias unit  56 , a driver  24 , a rail-to-rail controller  40 , and a source follower biasing block  61 . 
   Hereinafter, the output buffer according to the ninth embodiment will be described based on the output bias unit  56 , which is a major feature thereof, by comparing with the output buffer according to the eighth embodiment. 
   The output bias unit  56  may include a PMOS sensing transistor M PS  for outputting a first sensed current according to a main electric current of a PMOS common source M PCS , a NMOS sensing transistor M NS  for outputting a second sensed current according to a main electric current of a NMOS common source M NCS , and a bias controller  561  for controlling a gate of the PMOS common source M PCS  and a gate of the NMOS common source M NCS  by comparing a reference current I REF  with an electric current obtained by dividing one of the first sensed current and the second sensed current by half through current mirroring. 
   The operations of the output bias unit  56  will be described hereinafter. 
   The PMOS sensing transistor M PS  senses a main electric current of the PMOS common source M PCS  and the NMOS sensing transistor M NS  senses a main electric current of the NMOS common source M NCS . One of the sensing transistors M PS  and M NS , which is connected to a common source where a higher electric current of the two main electric currents follows, cannot sense an electric current because it enters a Triode Region. On the contrary, a sensed current from the sensing transistor connected to a common source where a lower electric current of the two main electric currents flows is divided by half through current mirror M N5 −M N6 , and M P5 −M P6 . Then, the divided current is compared with a reference current I REF , thereby generating the control signals. 
   Such operation will be described in more detail as follows. 
   1. When a high electric current is supplied by a PMOS common source M PCS . 
   The PMOS sensing transistor M PS  enters the Triode Region. Therefore, a high level power voltage +V dd  is formed at a drain node of the PMOS sensing transistor M PS . A drain electric current of the NMOS sensing transistor M NS , which senses the main electric current of the NMOS common source M NCS , is divided by half at transistors M N5  and M N6 . A gate of the NMOS common source M NCS  is controlled by comparing electric current following to the transistor M N6  with a reference current I REF  not to turn off the NMOS common source M NCS . 
   2. When the NMOS common source M NCS  supplies a large electric current to an output. 
   The NMOS sensing transistor M NS  falls a Triode Region. An electric current sensed by the PMOS sensing transistor M PS  is divided by half and the gates of the PMOS common source M PCS  and the NMOS common source M NCS  are controlled by comparing the divided sensed current with a reference current I REF . 
   The output buffer according to the ninth embodiment of the present invention has an advantage that the output bias unit has a structure simpler than that of the output buffer according to the eighth embodiment of  FIG. 17 . 
   According to the ninth embodiment, a sensing transistor connected to a common source driving a high current cannot sense an electric current because the sensing transistor enters a triode region. Therefore, the output buffer according to the ninth embodiment can advantageously reduce unnecessary power consumption to sense an electric current. In more detail, 1) When the PMOS common source M PCS  supplies a high electric current to an output node in the output buffer according to the eighth embodiment of  FIG. 17 , the transistor M N6  cannot be operated as a current mirror because the transistor M N6  falls into a triode region. Therefore, the electric current sensed by the transistor M PS2  is wasted through the transistor M N5  without being used for controlling a gate of a common source. Since the wasted electric current increases in proportion to an electric current flowing through the PMOS common source M PCS . 2) When the NMOS common source M NCS  supplies a large electric current to an output node in the output buffer according to the eight embodiment of  FIG. 17 , the transistor M P6  cannot be operated as a current mirror because the transistor M P6  falls into a triode region. Therefore, an electric current sensed by the transistor M NS1  is wasted through the transistor M P5  without being used for controlling a gate of a common source. 3) Unlikely, in the output buffer according to the ninth embodiment of  FIG. 18 , a wasted electric current without being used for controlling is not detected at a common source where a large electric current flows in a step of selecting a minimum electric current among electric currents of common sources. Therefore, unnecessary power consumption can be reduced. If a channel width ratio of a common source and a sensing transistor sensing an electric current of the common source is N:1, a Quiescent bias current that flows to the common source without an input signal becomes 2N*I REF . When an input signal is applied, a minimum electric current guaranteed at the common source is decided as 2N*I REF . 
     FIG. 19  is a diagram illustrating a power amplifier according to a first embodiment of the present invention. Referring to  FIG. 19 , the power amplifier according to the first embodiment a push-pull circuit unit  10  having transistors connected to each others in a push-pull formation between a high level power voltage +V dd  and a low level power voltage −V dd , an output unit  32  having common sources connected between the high level power voltage +V dd  and the low level power voltage −V dd , an output bias unit  51  for biasing the output unit  32 , a driver  21  for driving the output unit  32  according to a signal from the push-pull circuit unit  10 , a rail-to-rail controller  40  for widening a swing range of an output voltage Vo by controlling ON-OFF of the transistors included in the push-pull circuit unit  10  according to an input voltage V i  of the output buffer, a feedback unit  70  for feedbacking the output voltage V o  to an input side, and an amplifier  80  for amplifying a difference between an input voltage V in  and the feedbacked output voltage V o . 
   The power amplifier according to the first embodiment of the present invention includes constituent elements identical to those of the output buffer according to the embodiments of the present invention, which were already described. Therefore, the descriptions of the identical constituent elements are omitted. 
   The power amplifier according to the first embodiment shown in  FIG. 19  is an example of embodying an amplifier having low output impedance using the feedback unit  70  and the amplifier  80  with the output unit  32 , the driver  21 , and the rail-to-rail controller  40 , which are included the output buffer according to the fifth embodiment of  FIG. 14 . In order to embody the source follower biasing block  62  for defining a bias electric current of source followers M NSF  and M PSF  having in a push-pull formation, source followers composed of M PG −I 3  and M NG −I 3  are used. An amplifier having low output impedance can be embodied in various ways using the output buffers according to the embodiments of the present invention. The power amplifier according to the first embodiment shown in  FIG. 19  is one of examples thereof. Referring to  FIG. 19 , when the amplifier  80  is used for supplying a large electric power to an output node, a power amplifier can be embodied by forming an open-loop amplifier through connecting an output buffer including the push-pull circuit unit  10 , the output unit  32 , the output bias unit  51 , the driver  21 , and the rail-to-rail controller  40  to the amplifier  80  in series and forming a closed-loop through forming a negative feedback loop around the open-loop amplifier. For example, a negative feedback can be formed by applying voltage-series negative feedback using the feedback unit  70 . 
     FIG. 20  is a diagram illustrating a power amplifier according to the second embodiment of the present invention. 
   Differences between the power amplifiers according to the first and second embodiments shown in  FIGS. 19 and 20  are structures of a driver and an output bias unit. 
   Referring to  FIG. 20 , the power amplifier according to the second embodiment is embodied by employing the driver  24  and the output bias unit  56  included in the output buffer according to the ninth embodiment of the present invention. Since the driver  24  and the output bias unit  56  were already described above, detail descriptions thereof are omitted. 
   In order to embody a source follower biasing block  62  used for defining a bias electric current of source followers M NSF  and M PSF  having a push-pull formation as shown in  FIG. 19 , source followers formed of M PG −I 3  and M NG −I 3  are used. 
     FIG. 21  is a graph illustrating output impedance characteristics of a power amplifier of  FIG. 20  according to frequencies through simulations. 
   According to the power amplifier of the second embodiment shown in  FIG. 20 , operating zones of source followers M NSF  and M PSF  are decided and one of loops to be disconnected is decided according to an output voltage range. Therefore, output impedance is also influenced by an output voltage. A bandwidth of a loop must be wide for sustaining low output impedance at high frequency. Therefore, the output impedance at high frequency region is appeared as highest in a range of high output voltages because a bandwidth of a loop M PSF −M N1 −M N3 −M PCS  that includes a PMOS source follower M PSF  and a PMOS common source M PCS  is the narrowest among four loops. The output impedance for a middle level output voltage is the lowest because four loops are all formed. Referring to  FIG. 21 , the graph clearly shows that the output impedance less than 1Ω is sustained up to 10 MHz. 
   As described above, the output buffer and the power amplifier according to the present invention can effectively supply an output electric current. 
   Also, the output buffer and the power amplifier according to the present invention can sustain low output impedance up to a high frequency area while supplying and absorbing an electric current at any output voltages and can obtain a wide output voltage swing range. 
   Furthermore, the output buffer and the power amplifier can obtain further low output impedance which could not be obtained using a typical CMOS circuit by lowering low output impedance of a source follower as much as times of a negative loop gain. Moreover, the output buffer and the power amplifier can obtain a wide rail-to-rail output voltage swing range by overcoming an output voltage swing limitation caused by a source follower using a common source amplifier. 
   In addition, low output impedance can be sustained while sourcing or sinking an output electric current regardless of an output voltage because at least one of source followers forms a negative feedback loop with a common source amplifier without being turned off for any output voltage level according to the present invention. 
   Moreover, the output buffer and the power amplifier has wideband characteristics because only one low frequency pole is formed in a negative feedback loop according to the present invention. Therefore, very low output impedance can be sustained in a high frequency region. 
   The output buffer and the power amplifier according to the present invention may be particularly proper for a power amplifier output stage and a voltage regulator requesting low output impedance and large current-driving capability. It is expected that the demand of the output buffer and the power amplifier according to the present invention will increase due to the expansion of a mark for voltage regulators and power amplifiers. 
   The foregoing exemplary embodiments and aspects of the invention are merely exemplary and are not to be construed as limiting the present invention. The present teaching can be readily applied to other types of apparatuses. Also, the description of the exemplary embodiments of the present invention is intended to be illustrative, and not to limit the scope of the claims, and many alternatives, modifications, and variations will be apparent to those skilled in the art.