Patent Publication Number: US-9853650-B1

Title: Method and apparatus of frequency synthesis

Description:
BACKGROUND OF THE INVENTION 
     Field of the Invention 
     The present invention generally relates to phase lock loops. 
     Description of Related Art 
     Persons of ordinary skills in the art understand terms and basic concepts related to microelectronics that are used in this disclosure, such as “voltage,” “current,” “signal,” “logical signal,” “clock,” “rising edge,” “phase,” “capacitor,” “charge,” “charge pump,” “transistor,” “MOS (metal-oxide semiconductor),” “PMOS (p-channel metal oxide semiconductor),” “NMOS (n-channel metal oxide semiconductor),” “source,” “gate,” “drain,” “circuit node,” “ground node,” “switch,” “inverter,” “time-to-digital converter,” “digital-to-analog converter,” and “digital-to-time converter.” Terms and basic concepts like these are apparent to those of ordinary skills in the art and thus will not be explained in detail here. 
     Through this disclosure, a logical signal is a signal of two states: “high” and “low,” which can also be re-phrased as “1” and “0.” For brevity, a logical signal in the “high” (“low”) state is simply stated as the logical signal is “high” (“low”), or alternatively, the logical signal is “1” (“0”). Also, for brevity, quotation marks may be omitted and the immediately above is simply stated as the logical signal is high (low), or alternatively, the logical signal is 1 (0), with the understanding that the statement is made in the context of describing a state of the logical signal. 
     A logical signal is said to be asserted when it is high. A logical signal is said to be de-asserted when it is low. 
     A clock signal is a cyclic logical signal. For brevity, hereafter, “clock signal” may be simply referred to as “clock.” 
     A timing of a clock signal refers to a time instant where the clock signal undergoes a transition of state, either a low-to-high transition or a high-to-low transition. When a clock signal undergoes a low-to-high (high-to-low) transition, a rising (falling) edge is observed in a timing diagram. 
     As is known, a phase lock loop (PLL) receives a first clock and outputs a second clock such that a phase of the second clock tracks a phase of the first clock. As a result, a frequency of the second clock is determined by a frequency of the first clock. A prior art phase lock loop comprises a phase/frequency detector (hereafter PFD), a charge pump (hereafter CP) circuit, a loop filter (hereafter LF), a voltage-controlled oscillator (hereafter VCO), and a clock divider circuit, wherein: the VCO outputs the second clock in accordance with a control voltage such that the frequency of the second clock is determined by the control voltage, the clock divider circuit receives the second clock and outputs a third clock in accordance with a division ratio, the PFD receives the first clock and the third clock and outputs a timing signal representing a difference in timing between the first clock and the third clock, the CP circuit converts the timing signal into a current signal, the LF filters the current signal to establish the control voltage to control the frequency of the second clock. The frequency of the second clock is thus adjusted in a closed loop manner to track a frequency of the first clock. “Phase/frequency detector,” “charge pump circuit,” “loop filter,” “voltage-controlled oscillator,” and “clock divider circuit” are all well known in the prior art and thus not described in detail here. In a steady state, the frequency of the second clock is equal to the frequency of the first clock multiplied by a multiplication factor N that can be expressed as
 
 N=N   int +α
 
     where N int  is a positive integer and α is a rational number smaller than 1 (one) but not smaller than 0 (zero). If α is zero, the clock divider circuit has a fixed division factor N int , i.e. it performs a “divide by N int ” function wherein one cycle of the third clock is output for every N int  cycles of the second clock. If α is nonzero, it must be a fractional number; in this case, the phase lock loop is referred to as “fractional-N PLL,” and the clock divider circuit cannot have a fixed division factor. In an embodiment, the division factor of the clock divider circuit is modulated by a delta-sigma modulator and dynamically toggle between N int  and N int +1 such that a mean value of the division factor is equal to N int +α. Since the value of the division factor is modulated, an instantaneous value differs from a mean value of the division factor (e.g., N int  and N int +1 are different from N int +α), resulting in an instantaneous noise additive to the PLL. In U.S. Pat. No. 7,999,622, Galton et al disclosed a method to cancel the additive noise resulting from the modulation of the division factor. The method is based on using a digital-to-analog converter to output a current that offsets an additive noise in the output of the charge pump circuit (resulting from the modulation of the division factor). The digital-to-analog converter (DAC), however, contributes thermal noise. To reduce the thermal noise contribution, a large current can be used at the cost of high power consumption. Besides, in practice the DAC is not perfectly linear, and its nonlinearity can contribute additional noise to PLL. To reduce the adverse effect of the nonlinearity of the DAC, a dynamic element matching can be used at the cost of high circuit complexity. 
     BRIEF SUMMARY OF THIS INVENTION 
     What is desired and disclosed herein is a method for cancelling a noise in a fractional-N PLL resulting from a modulation of a division factor without consuming high power or demanding high circuit complexity. 
     An aspect of the present invention is to use a digitally controlled timing adjustment circuit to correct a pre-known timing error in a fractional-N phase lock loop due to a modulation of a division factor of a clock divider, wherein a gain of the digitally controlled timing adjustment circuit is calibrated in a closed-loop manner based upon a correlation between the pre-known timing error and a residual timing error of an output of the digitally controlled timing adjustment circuit. 
     In an embodiment, an apparatus comprises: a digitally controlled timing adjustment circuit configured to receive a first clock and a second clock and output a third clock and a fourth clock in accordance with a noise cancellation signal and a gain control signal; an analog phase detector configured to receive the third clock and the fourth clock and output an analog timing error signal; a filtering circuit configure to receive the analog timing error signal and output an oscillator control signal; a controllable oscillator configured to receive the oscillator control signal and output a fifth clock; a clock divider configured to receive the fifth clock and output the second clock in accordance with a division factor; a modulator configured to receive a clock multiplication factor and output the division factor and the noise cancellation signal; a digital phase detector configured to receive the third clock and the fourth clock and output a digital timing error signal, wherein the digital phase detector is self-calibrated so that a mean value of the digital timing error signal is zero; and a correlation circuit configured to receive the digital timing error signal and the noise cancellation signal and output the gain control signal. In an embodiment, a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset. In an embodiment, the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal. In an embodiment, a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal. In an embodiment, the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal. 
     In an embodiment, the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal. In an embodiment, the correlation circuit comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no changes to the gain control signal if the noise cancellation signal is zero. In an embodiment, the modulator comprises a delta-sigma modulator. In an embodiment, the modulator comprises a first order delta-sigma modulator. In an embodiment, the analog phase detector comprises a phase/frequency detector. In an embodiment, the filtering circuit comprises a charge pump and a load circuit comprising a serial connection of a capacitor and a resistor. In an embodiment, the controllable oscillator is a voltage-controlled oscillator. In an embodiment, the clock divider is a counter. 
     In an embodiment, a method comprises: receiving a first clock and a clock multiplication factor; modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor; establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor; deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with a noise cancellation signal and a gain control signal; establishing an analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector; filtering the analog timing error signal into an oscillator control signal using a filtering circuit; outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator; outputting the second clock by dividing down the fifth clock in accordance with the division factor; establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero; and adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal. In an embodiment, a timing difference between the fourth clock and the third clock is equal to a sum of: a timing difference between the second clock and the first clock, the noise cancellation signal scaled by the gain control signal, and a timing offset. In an embodiment, the digitally controlled timing adjustment circuit comprises: a fixed-delay circuit configured to receive the second clock and output the fourth clock, and a digitally controlled variable-delay circuit configured to receive the first clock and output the third clock in accordance with the noise cancellation signal and the gain control signal. In an embodiment, a delay of the digitally controlled variable delay circuit is linearly dependent on the noise cancellation signal and also linearly dependent on the gain control signal. In an embodiment, the digitally controlled variable delay circuit comprises: a tunable inverter comprising an inverter supplied by a rail voltage controlled by the gain control signal, and a variable capacitor controlled by the noise cancellation signal. In an embodiment, the digital phase detector comprises: a skew adjustment circuit configured to receive the third clock and the fourth clock and output a first delayed clock and a second delayed clock in accordance with a delay control signal, a time-to-digital converter configured to receive the first delayed clock and the second delay clock and output the digital timing error signal, and an integrator configured to receive the digital timing error signal and output the delay control signal. In an embodiment, the correlation circuit comprises a digital signal processing unit configured to decrement the gain control signal by a value determined by the digital timing error signal if the noise cancellation signal is positive, increment the gain control signal by the value determined by the digital timing error signal if the noise cancellation signal is negative, or make no change to the gain control signal if the noise cancellation signal is zero. In an embodiment, modulating the clock multiplication factor comprises using a delta-sigma modulator. In an embodiment, modulating the clock multiplication factor comprises using a first order delta-sigma modulator. In an embodiment, the analog phase detector comprises a phase/frequency detector. In an embodiment, the filtering circuit comprises a charge pump and a load circuit comprising a serial connection of a capacitor and a resistor. In an embodiment, the controllable oscillator is a voltage-controlled oscillator. In an embodiment, the dividing down the fifth clock comprises using a counter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  shows a functional block diagram of a fractional-N phase lock loop in accordance with an embodiment of the present invention. 
         FIG. 1B  shows a schematic diagram of a phase/frequency detector. 
         FIG. 1C  shows a schematic diagram of a charge pump. 
         FIG. 1D  shows a schematic diagram of a loop filter. 
         FIG. 1E  shows a schematic diagram of a voltage-controlled oscillator. 
         FIG. 1F  shows a functional block diagram of a digitally controlled timing adjustment circuit. 
         FIG. 1G  shows a schematic diagram of a digitally controlled variable-delay circuit. 
         FIG. 2  shows a schematic diagram of a self-calibrating time-to-digital converter. 
         FIG. 3  shows a schematic diagram of a modulator. 
         FIG. 4  shows a flow diagram of a method in accordance with the present invention. 
     
    
    
     DETAILED DESCRIPTION OF THIS INVENTION 
     The present invention relates to phase lock loops. While the specification describes several example embodiments of the invention considered favorable modes of practicing the invention, it should be understood that the invention can be implemented in many ways and is not limited to the particular examples described below or to the particular manner in which any features of such examples are implemented. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention. 
       FIG. 1A  shows a functional block diagram of a PLL  100  in accordance with an embodiment of the present invention. PLL  100  comprises: a digitally controlled timing adjustment circuit  160  configured to receive a first clock CK 1  and a second clock CK 2  and output a third clock CK 3  and a fourth clock CK 4  in accordance with a noise cancellation signal N C  and a gain control signal G C ; a phase/frequency detector (PFD)  110  configured to receive the third clock CK 3  and the fourth clock CK 4  and output an analog timing error signal S TE  representing a timing difference between the third clock CK 3  and the fourth clock CK 4 ; a charge pump (CP)  120  configured to convert the analog timing error signal S TE  into a correction current I C ; a loop filter (LF)  130  configured to receive the correction current I C  and output a control voltage V CTL ; a voltage-controlled oscillator (VCO)  140  configured to output a fifth clock CK 5  in accordance with the control voltage V CTL ; a clock divider  150  configured to receive the fifth clock CK 5  and output the second clock CK 2  in accordance with a division factor N DIV ; a modulator (MOD)  170  configured to output the division factor N DIV  and the noise cancellation signal N C  in accordance with a clock multiplication factor N MUL ; a self-calibrating TDC (time-to-digital converter)  190  configured to receive the third clock CK 3  and the fourth clock CK 4  and output a digital timing error signal D TE , and a correlation circuit  180  configured to output the gain control signal G C  in accordance with a correlation between the digital timing error signal D TE  and the noise cancellation signal N C . For brevity, hereafter the first (second, third, fourth, fifth) clock CK 1  (CK 2 , CK 3 , CK 4 , CK 5 ) is simply referred to as CK 1  (CK 2 , CK 3 , CK 4 , CK 5 ), the analog timing error signal S TE  is simply referred to as S TE , the digital timing error signal D TE  is simply referred to as D TE , the correction current I C  is simply referred to as I C , the control voltage V CTL  is simply referred to as V CTL , the noise cancellation signal N C  is simply referred to as N C , the gain control signal G C  is simply referred to as G C , the clock multiplication factor N MUL  is simply referred to as N MUL , and the division factor N DIV  is simply referred to as N DIV . 
     PLL  100  will be the same as the aforementioned prior art PLL if: the digitally controlled timing adjustment circuit  160 , the self-calibration TDC  190 , and the correlation circuit  180  are removed, and PFD  110  receives CK 1  and CK 2 , instead of CK 3  and CK 4 . Similar to the prior art PLL, PLL  100  receives CK 1  and outputs CK 5  using VCO  140 , which is adjusted in a closed loop manner via a feedback path comprising the clock divider  150 , PFD  110 , CP  120 , and LF  130 , such that a frequency of CK 5  is equal to a frequency of CK 1  times N MUL , which is not a pure integer. Since N MUL  is not a pure integer but N DIV  (which is the clock division factor of the clock divider  150 ) needs to be an integer, N DIV  must be modulated in a way such that a mean value of N DIV  equals N MUL . Modulator  170  receives N MUL  and outputs N DIV , effectively modulating N DIV  such that the mean value of N DIV  equals N MUL . In doing so, the average frequency of CK 5  is equal to the frequency of CK 1  times N MUL , but an instantaneous timing of CK 2  might deviate from an ideal timing of a fictitious clock divider that allows a non-integer division factor of N MUL . The deviation of the instantaneous timing of CK 2  from the ideal timing due to the modulation of N DIV  leads to an instantaneous noise in the timing difference between CK 2  and CK 1 . However, the instantaneous noise of the timing difference between CK 2  and CK 1  due to the modulation of N DIV  is pre-known. The instantaneous noise is calculated by the modulator  170  and represented by N C . The digitally controlled timing adjustment circuit  160  is configured to correct the instantaneous noise in the timing difference between CK 2  and CK 1  due to the modulation of N DIV , such the timing difference between CK 4  and CK 3  is free of the instantaneous noise. However, N C  is numeric and digital in nature, while the timing difference between CK 2  and CK 1  is temporal and analog in nature. A function of digital-to-analog conversion is performed by the digitally controlled timing adjustment circuit  160  to convert N C  into the amount of timing difference that needs to be cancelled. G C  determines a gain factor of the digital-to-analog conversion. 
     The self-calibrating TDC  190  detects a timing difference between CK 3  and CK 4  and output D TE  to represent the timing difference. The self-calibrating TDC  190  calibrates itself so that a mean value of D TE  is zero. 
     Note that PFD (such as PFD  110  of  FIG. 1A ) is an example of analog phase detector, while TDC (such as the self-calibrating TDC  190  of  FIG. 1A ) is an example of digital phase detector. 
     In an embodiment, a function of the digitally controlled timing adjustment circuit  160  can be described by the following mathematical expression:
 
 t   4   −t   3   =t   2   −t   1   +N   C   ·G   C   +t   OS   (1)
 
     Here, t 1  is a timing of a rising edge of CK 1 , t 2  is a timing of a rising edge of CK 2 , t 3  is a timing of a rising edge of CK 3 , t 4  is a timing of a rising edge of CK 4 , and t OS  is a timing offset. Here, t 2 −t 1  is a timing difference between CK 2  and CK 1 , while t 4 −t 3  is a timing difference between CK 4  and CK 3 . Both S TE  and D TE  represent a relative timing between CK 4  and CK 3  and is mathematically equal to t 4 −t 3 . A major difference between S TE  and D TE  is that S TE  is analog but D TE  is digital. N C  presents the instantaneous noise in t 2 −t 1  due to the modulation of N DIV . If G C , which is the conversion gain for converting N C  into the timing difference to be cancelled, is set properly, the noise in t 2 −t 1  due to the modulation of N DIV  will be corrected and absent in t 4 −t 3 . On the other hand, if G C  is not set properly, the noise will be either over-corrected or under-corrected, resulting in a residual noise in t 4 −t 3  that will become a part of D TE . When G C  is set too large (small), the noise will be over-corrected (under-corrected); as a result, t 4 −t 3  will contain a residual noise that is positively (negatively) correlated with N C , and therefore D TE  will tend to be positive (negative) when N C  is positive and negative (positive) when N C  is negative. Correlation circuit  180  thus adjusts G C  in accordance with a correlation between N C  and D TE : when D TE  is positively (negatively) correlated with N C , it indicates G C  is too large (small) and needs to be decreased (increased). 
     In an embodiment depicted in  FIG. 1B , PFD  110  comprises two data flip-flops (DFF)  111  and  112  and an AND gate  113 . Each DFF comprises an input terminal labeled “D,” an output terminal labeled “Q,” a reset terminal labeled “R,” and a clock terminal denoted by a wedge symbol; such notations are widely used in the prior art. DFF  111  outputs a first logical signal UP while DFF  112  outputs a second logical signal DN. The NAND gate  113  receives the two logical signals UP and DN and outputs a reset signal RST. The first (second) logical signal UP (DN) is asserted upon a rising edge of CK 3  (CK 4 ) and is de-asserted when the reset signal RST is asserted. The two logical signals UP and DN jointly embody the timing error signal S TE  representing a timing difference between CK 3  and CK 4 ; such embodiment is widely used and well known in the prior art and thus not explained in detail here. 
     In an embodiment depicted in  FIG. 1C , CP  120  comprises a current source  121  configured to source a charge-up current I UP , a current sink  122  configured to sink a charge-down current I DN , a first switch  123  configured to couple the charge-up current I UP  to an output node  125  when the logical signal UP is asserted, and a second switch  124  configured to couple the charge-down current I DN  to the output node  125  when the logical signal DN is asserted. The output node  125  interfaces with and provides the correction current I C  to LF  130  of  FIG. 1A . Throughout this disclosure, “VDD” denotes a power supply node.  FIG. 1C  is well known in the prior art and self-explanatory to those of ordinary skills in the art and thus not described in detail here. 
     In an embodiment depicted in  FIG. 1D , LF  130  comprises a resistor  131 , a first capacitor  132 , and a second capacitor  133 , configured to receive the correction current I C  from CP  120  of  FIG. 1A  and output the control voltage V CTL  to VCO  140  of  FIG. 1A .  FIG. 1D  is well known in the prior art and self-explanatory to those of ordinary skills in the art and thus not described in detail here. 
     In an embodiment depicted in  FIG. 1E , VCO  140  comprises a voltage-to-current converter  141  configured to convert the control voltage V CTL  into a control current I CTL , a current mirror  143  configured to mirror the control current I CTL  into a mirrored current I M , and a ring oscillator  146  configured to output CK 5  in accordance with the mirrored current I M . The voltage-to-current converter  142  comprises a NMOS transistor  142 . The current mirror  143  comprises two PMOS transistors  144  and  145 . The ring oscillator comprises three inverters  147 ,  148 , and  149  configured in a ring topology, jointly receiving the mirror current I M . When the control voltage V CTL  rises, the control current I CTL  rises, and so does the mirrored current I M . As a result, the three inverters  147 ,  148 , and  149  receive more power and become faster, resulting in a higher oscillation frequency for CK 5 . 
     Clock divider  150  can be embodied by a counter that increments a count upon a rising edge of CK 5 . The count starts with 0, increments to 1 upon a rising edge of CK 5 , then increments to 2 upon a next rising edge of CK 5 , and so on. When the count reaches N DIV −1, it wraps around to 0 upon a next rising edge of CK 5 . In this manner, the counter cyclically counts from 0 to N DIV −1. CK 2  is asserted whenever the count equals 0, and de-asserted otherwise. 
     Digitally controlled timing adjustment circuit  160  receives CK 1  and CK 2  and outputs CK 3  and CK 4 , so that a timing difference between CK 4  and CK 3  is related to a timing difference between CK 2  and CK 1  in accordance with a relation described by equation (1). In an embodiment depicted in  FIG. 1F , digitally controlled timing adjustment circuit  160  comprises: a fixed-delay circuit  160 _ 1  configured to receive CK 2  and output CK 4 , and a digitally controlled variable-delay circuit  160 _ 2  configured to receive CK 1  and output CK 3  in accordance with G C  and N C . The fixed-delay circuit  160 _ 1  provides a fixed timing difference between CK 4  and CK 2 ; that is, t 4 −t 2  is fixed. On the other hand, the digitally controlled variable-delay circuit  160 _ 2  provides a variable timing difference between CK 3  and CK 1  and the variable timing difference is controlled by G C  and N C ; that is, t 3 −t 1  is variable and controlled by G C  and N C . As a result, t 4 −t 3  is different from t 2 −t 1  by a variable amount controlled by G C  and N C . In particular, the variable timing difference is linearly dependent on N C , and also linearly dependent on G C . In an embodiment, the fixed-delay circuit  160 _ 1  is simply a short circuit; in this case, the fixed delay is zero and CK 3  is the same as CK 1 . In an alternative embodiment, the fixed-delay circuit is an inverter chain that includes an even number of inverters configured in a cascade topology. 
     By way of example but not limitation, N C  is a four-bit word comprising four bits N C [ 0 ], N C [ 1 ], N C [ 2 ], and N C [ 3 ]. In an embodiment depicted in  FIG. 1G , the digitally controlled variable-delay circuit  160 _ 2  comprises: a tunable inverter  161  configured to receive CK 1  and output an intermediate clock CKI at a circuit node  165  in accordance with G C ; an output inverter  162  configured to receive the intermediate clock CKI and output CK 3 ; and a variable capacitor  166  configured to provide a capacitive load at the circuit node  165 . The tunable inverter  161  comprises: a DAC (digital-to-analog converter)  169  configured to receive G C  and output a rail voltage VR; an inverter  168  comprising a PMOS transistor MP and a NMOS transistor MN configured to receive CK 1  and output CKI in accordance with the rail voltage VR. The variable capacitor  166  comprises four capacitors  163 _ 0 ,  163 _ 1 ,  163 _ 2 , and  163 _ 3  configured to conditionally shunt the circuit node  165  to ground via four switches  164 _ 0 ,  164 _ 1 ,  164 _ 2 , and  164 _ 3  in accordance with N C [ 0 ], N C [ 1 ], N C [ 2 ], and N C [ 3 ], respectively. The output inverter  162  serves as an inverting buffer, and together with the tunable inverter  161  causes CK 3  to be the same as CK 1  except for a delay. In an embodiment, a capacitance of the variable capacitor  166  increases linearly with a value of N C . When CK 1  is low, CKI is high and equal to the rail voltage VR, and CK 3  is low. Note that the rail voltage VR is linearly dependent on G C , thanks to the digital-to-analog conversion function of the DAC  169 . A low-to-high transition of CK 1  will cause the tunable inverter  167  to discharge the variable capacitor  166  via the NMOS transistor MN, resulting in a high-to-low transition of CKI, and consequently a low-to-high transition of CK 3 . The time that CKI takes to finish the high-to-low transition in response to the low-to-high transition of CK 1  is linearly dependent on a total capacitance at the circuit node  175 , and also linearly dependent on the rail voltage VR. The capacitance of the variable capacitor is linearly dependent on the value of N C  and the rail voltage VR is also linearly dependent on G C , the time that the intermediate clock CKI takes to finish the transition is approximately linearly dependent on N C  and also linearly dependent on G C . Therefore, digitally controlled timing adjustment circuit  160  can effectively embody equation (1). 
     The correlation circuit  180  outputs G C  based on a correlation between D TE  and N C . In an embodiment, G C  is established in accordance with an algorithm of adaptation described by the following equation 
     
       
         
           
             
               
                 
                   
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     Here, μ is an adaptation constant, G C   (old)  is a value before adaptation, and G C   (new)  is a value after adaptation. Since D TE  and N C  are purely digital, and equation (2) can be implemented by using a digital signal processing engine. In an embodiment, G C  is a digital signal, and the correlation circuit  180  comprises a digital signal processing unit that adapts G C  in accordance with D TE  and N C  using equation (2). 
     A functional block diagram of a self-calibrating TDC  200  suitable for embodying the self-calibrating TDC  190  of  FIG. 1A  is depicted in  FIG. 2 . Self-calibrating TDC  200  comprises: a skew adjustment circuit  210  configured to receive CK 3  and CK 4  and output a first delayed clock CK 3 D and a second delayed clock CK 4 D in accordance with a delay control signal D CTL ; a TDC (time-to-digital converter)  220  configured to receive the first delay clock CK 3 D and the second delayed clock CK 4 D and output D TE ; and an integrator  230  configured to receive D TE  and output the delay control signal D CTL . For brevity, hereafter the first delayed clock CK 3 D is simply referred to as CK 3 D, the second delayed clock CK 4 D is simply referred to as CK 4 D, and the digital control signal D CTL  is simply referred to as D CTL . The skew adjustment circuit  210  comprises: a variable delay circuit  211  configured to receive CK 3  and output CK 3 D in accordance with D CTL , and a fixed delay circuit  212  configured to receive CK 4  and output CK 4 D. TDC  220  comprises a data flip-flop (DFF)  221  configured to output D TE  by sampling CK 3 D in accordance with CK 4 D. In this particular embodiment, TDC  220  is a single-bit TDC, wherein D TE  is a logical signal that is high (low) when a rising edge of CK 3 D arrives earlier (later) than a rising edge of CK 4 D. In the context of digital signal processing, however, D TE  is interpreted as a binary signal that is either “1” or “−1,” indicating a relative timing (early or late) of CK 3 D with respect to CK 4 D. D CTL  is an integral of D TE . In an embodiment, the fixed delay circuit  212  comprises a cascade of an even number of inverters. In an embodiment, the variable delay circuit  211  is a digital-to-time converter, wherein CK 3 D is derived from CK 3  by delaying CK 3  with a delay that is linearly dependent on a value of D CTL . Digital-to-time converters are well known in the prior art and thus not described in detailed here. Of the two possible values of D TE , if “1” (“−1”) occurs more often than “−1” (“1”), the value of D CTL  will increase (decrease), and consequently the delay of CK 3 D will increase (decrease); as a result, the likelihood of CK 3 D being earlier than CK 4 D in timing is decreased (increased), so is the likelihood of D TE  being “1” (“−1”). D CTL  is thus adjusted in a closed loop manner. In a steady state, a mean value of D TE  is zero and therefore there is no substantial change to D CTL . 
     In an embodiment, MOD  170  of  FIG. 1A  is embodied by a modulator  300  depicted in  FIG. 3 . Modulator  300  comprises a rounding operator (denoted by round(•))  302 , two unit delays (denoted by z −1 )  304  and  306 , and three summing operators  301 ,  303 , and  305 . Unit delay  304  receives a rounding error e 1  and outputs a delayed rounding error e 1d . Summing operator  301  sums N MUL  and e 1d  into a modified multiplication factor N′ MUL . Rounding operator  302  rounds N′ MUL  into N DIV . Summing operator  303  subtracts N DIV  from N′ MUL  to generate e 1 . Summing operator  305  sums N C  with N DIV  and deducts N MUL  to output an intermediate signal G CNEXT . Unit delay  306  receives N CNEXT  and outputs N C . Rounding operator  302 , summing operator  301  and  303 , and unit delay  304  form a 1st order delta-sigma modulator, so that a mean value of N DIV  equals N MUL . Summing operator  305  and unit delay  306  form an error accumulator, so that N C  is equal to an accumulative sum of a difference between N DIV  and N MUL . The difference between N DIV  and N MUL  is an instantaneous error of the 1st order delta-sigma modulator, and thus an error of the clock dividing operation of the clock divider  150 . N C  is the accumulative sum of a difference between N DIV  and N MUL , represents an accumulative error of the clock dividing operation of the clock divider  150  and thus a timing error of CK 2 . Digitally controlled timing adjustment circuit  160  corrects the timing error by adjusting the timing difference between CK 2  and CK 1  with an amount determined by N C . 
     Now refer to  FIG. 1F . In an alternative embodiment not shown in the figure, the fixed-delay circuit  160 _ 1  and the digitally controlled variable-delay circuit  160 _ 2  are swapped, and the digitally controlled variable-delay circuit  160 _ 2  is controlled by G C  and −N C  instead, where −N C  is an inversion of N C . In this alternative embodiment, the timing difference between CK 3  and CK 1  is fixed and the timing difference between CK 4  and CK 2  is variable and controlled by G C  and −N C , but the function remains the same and equation (1) is fulfilled. 
     Still refer to  FIG. 1F . The digitally controlled variable-delay circuit  160 _ 2  belongs to a category of circuits known as digital-to-time converters, wherein a timing of an output clock is controlled by a digital signal. The digitally controlled variable-delay circuit  160 _ 2  can be embodied by other digital-to-time converters, as long as the time difference between CK 3  and CK 1  is linearly dependent on both N C  and G C . 
     Now refer to  FIG. 1A . PFD  110  is merely an exemplary analog phase detector but not a limitation. An alternative phase detector can be used instead, as long as the timing difference between CK 4  and CK 3  can be detected and properly represented by an associated timing error signal (such as S TE ). Also, VCO  140  is merely an exemplary controllable oscillator circuit but not a limitation. An alternative controllable oscillator circuit can be used instead, as long as an output clock (such as CK 5 ) can be generated and a frequency of the output clock can be controlled by a control signal (such as V CTL ). Likewise, CP  120  and the subsequent LF  130  are an exemplary embodiment, but not a limitation, configured to filter an analog timing error signal (such as S TE ) generated by a preceding analog phase detector (such as PFD  110 ) into a control signal (such as V CTL ). An alternative embodiment can be used instead, as long as the analog timing error signal can be filtered into a controllable signal for controlling a subsequent controllable oscillator circuit (such as VCO  140 ). 
     In accordance with an embodiment of the present invention, a flow chart  400  of a method comprises: receiving a first clock and a clock multiplication factor (step  401 ); modulating the clock multiplication factor into a division factor, wherein a mean value of the division factor is equal to the clock multiplication factor (step  402 ); establishing a noise cancellation signal in accordance with a difference between the clock multiplication factor and the division factor (step  403 ); deriving a third clock and a fourth clock from the first clock and a second clock using a digitally controlled timing adjustment circuit in accordance with the noise cancellation signal and a gain control signal (step  404 ); establishing an analog timing error signal by detecting a timing difference between the fourth clock and the third clock using an analog phase detector (step  405 ); filtering the analog timing error signal into an oscillator control signal using a filtering circuit (step  406 ); outputting a fifth clock in accordance with the oscillator control signal using a controllable oscillator (step  407 ); outputting the second clock by dividing down the fifth clock in accordance with the division factor (step  408 ); establishing a digital timing error signal by detecting the timing difference between the fourth clock and the third clock using a digital phase detector that is self-calibrating so that a mean value of the digital timing error signal is zero (step  409 ); and adjusting the gain control signal in accordance with a correlation between the digital timing error signal and the noise cancellation signal (step  410 ). 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.