Patent Publication Number: US-2013234332-A1

Title: Semiconductor device and method for manufacturing the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-051026, filed on Mar. 7, 2012; the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same. 
     BACKGROUND 
     There is a semiconductor device including a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. 
     In such a semiconductor device, the stacked conductive layers are processed in a stepwise manner in order to connect each of the plurality of stacked conductive layers to an upper layer wiring. That is, the conductive layers are processed in such a way as to become longer toward a lower layer at a region where each of the plurality of stacked conductive layers is connected to the upper layer wiring. 
     However, it is difficult to accurately process the stacked conductive layers in the stepwise manner, and there is a concern of decreasing productivity. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic perspective view for illustrating a configuration of the element region  1   a  provided in the semiconductor device  1  according to the first embodiment; 
         FIG. 2  is a schematic view for illustrating a cross-section of a portion where the silicon body  20  penetrates the conductive layers WL 1  to WL 4  and the insulating layers  25  between the conductive layers; 
         FIG. 3  is a schematic cross-sectional view for illustrating a configuration of the contact region  1   b  provided in the semiconductor device  1  according to the first embodiment; 
         FIG. 4  is schematic process cross-sectional view for illustrating the formation of the elements provided in the contact region  1   b;    
         FIGS. 5A to 5C  are schematic process cross-sectional views for illustrating the formation of the elements provided in the contact region  1   b;    
         FIGS. 6A and 6B  are schematic process cross-sectional views for illustrating the formation of the elements provided in the contact region  1   b;    
         FIGS. 7A and 7B  are schematic process cross-sectional views for illustrating the formation of the elements provided in the contact region  1   b;    
         FIGS. 8A and 8B  are schematic process cross-sectional views for illustrating formation of the frame portion  61   f  and the contact electrode  60   f  in the peripheral circuit region  1   c ; and 
         FIG. 9  is a schematic perspective view for illustrating a configuration of an element region  1   a   1  provided in the semiconductor device  1  according to the first embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     In general, according to one embodiment, a semiconductor device includes a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked. The semiconductor device includes a plurality of contact electrodes, a plurality of first insulating portions, and a plurality of second insulating portions. The plurality of contact electrodes extends in a stacking direction of the stacked body. Each of the contact electrodes reaches corresponding one of the conductive layers. The plurality of first insulating portions respectively is provided between the plurality of contact electrodes and the stacked body. The plurality of second insulating portions respectively is provided between the plurality of first insulating portions and the stacked body. 
     Hereinafter, embodiments will be illustrated with reference to the drawings. Note that, in each of the drawings, similar configuration elements will be denoted with the same reference numerals and detailed description is properly omitted. 
     Also, an XYZ rectangular coordinate system is herein introduced for convenience of description. In this coordinate system, two directions parallel to a main surface of a substrate  10  and orthogonal to each other are defined as an X direction and a Y direction, and a direction orthogonal to both the X and Y directions is defined as a Z direction. 
     Although a silicon semiconductor is illustrated in the following embodiments, semiconductors other than the silicon semiconductor may be used. 
     First Embodiment 
     First, a semiconductor device  1  according to a first embodiment will be illustrated. 
     The semiconductor device  1  according to the first embodiment includes an element region  1   a  and a contact region  1   b . The element region  1   a  is a region where a semiconductor element is provided, and the contact region  1   b  is a region where a contact electrode for connecting a conductive layer to an upper layer wiring is provided. 
     Note that, a known technology can be applied to a peripheral circuit region where a peripheral circuit for driving the semiconductor element (memory cell) provided in the element region  1   a  is provided, the upper layer wiring, and the like, and therefore description is omitted. 
     First, a configuration of the element region  1   a  will be illustrated. 
       FIG. 1  is a schematic perspective view for illustrating a configuration of the element region  1   a  provided in the semiconductor device  1  according to the first embodiment. 
       FIG. 1  illustrates a configuration of a memory cell array provided in the element region  1   a , as an example. 
     Note that, in  FIG. 1 , for purpose of easily viewing the drawing, illustration of insulating portions other than an insulating film formed inside a memory hole is omitted. 
     As shown in  FIG. 1 , a back gate BG is provided above the substrate  10  via an insulating layer (not shown). The back gate BG is, for example, a silicon layer doped with an impurity and having conductivity. A plurality of conductive layers WL 1  to WL 4  and a plurality of insulating layers (not shown) are alternately stacked on the back gate BG. The number of the conductive layers WL 1  to WL 4  can be arbitrarily determined and, for example, a case of four layers will be illustrated in the embodiment. The conductive layers WL 1  to WL 4  are, for example, silicon layers doped with an impurity and having conductivity. 
     The conductive layers WL 1  to WL 4  are divided into a plurality of blocks by grooves extending in the X direction. A drain-side selection gate DSG is provided above the uppermost conductive layer WL 1  of a certain block via an insulating layer (not shown). The drain-side selection gate DSG is, for example, a silicon layer doped with an impurity and having conductivity. A source-side selection gate SSG is provided, via an insulating layer (not shown), above the uppermost conductive layer WL 1  of another block adjacent to the block of the drain-side selection gate DSG. The source-side selection gate SSG is, for example, a silicon layer doped with an impurity and having conductivity. 
     A source line SL is provided above the source-side selection gate SSG via an insulating layer (not shown). The source line SL is, for example, a silicon layer doped with an impurity and having conductivity. Alternatively, the source line SL may be made of a metal material. A plurality of bit lines BL is provided above the source line SL and the drain-side selection gate DSG via an insulating layer (not shown). Each of the bit lines BL extends in the Y direction. 
     A plurality of U-shaped memory holes is formed in the above-described stacked body on the substrate  10 . The memory hole is formed in the block which includes the drain-side selection gate DSG, the memory hole penetrating the drain-side selection gate DSG and the conductive layers WL 1  to WL 4  under the drain-side selection gate DSG and extending in the Z direction. Further, the memory hole is formed in the block which includes the source-side selection gate SSG, the memory hole penetrating the source-side selection gate SSG and the conductive layers WL 1  to WL 4  under the source-side selection gate SSG and extending in the Z direction. The both memory holes are mutually connected via the memory hole formed inside the back gate BG and extending in the Y direction. 
     A silicon body  20  serving as a U-shaped semiconductor layer is provided inside the memory hole. A gate insulating film  35  is formed on an inner surface of the memory hole between the drain-side selection gate DSG and the silicon body  20 . A gate insulating film  36  is formed on an inner surface of the memory hole between the source-side selection gate SSG and the silicon body  20 . An insulating film  30  is formed on an inner surface of the memory hole between each of the conductive layers WL 1  to WL 4  and the silicon body  20 . The insulating film  30  is also formed on an inner surface of the memory hole between the back gate BG and the silicon body  20 . The insulating film  30  has an oxide-nitride-oxide (ONO) structure in which a silicon nitride film is placed between a pair of silicon oxide films, for example. 
       FIG. 2  is a schematic view for illustrating a cross-section of a portion where the silicon body  20  penetrates the conductive layers WL 1  to WL 4  and the insulating layers  25  between the conductive layers. 
     A first insulating film  31 , a charge storage layer  32 , and a second insulating film  33  are provided between the conductive layers WL 1  to WL 4  and the silicon body  20  in this order from the side of the conductive layers WL 1  to WL 4 . The first insulating film  31  is in contact with the conductive layers WL 1  to WL 4 , the second insulating film  33  is in contact with the silicon body  20 , and the charge storage layer  32  is provided between the first insulating film  31  and the second insulating film  33 . 
     The silicon body  20  functions as a channel, the conductive layers WL 1  to WL 4  function as control gates, and the charge storage layer  32  functions as a data memory layer for storing charges injected from the silicon body  20 . That is, a memory cell having a structure in which the control gate surrounds a periphery of the channel is formed at an intersection of the silicon body  20  and each of the conductive layers WL 1  to WL 4 . 
     The semiconductor device  1  is a nonvolatile semiconductor memory device which is capable of electrically freely writing/erasing data, and retaining stored contents even when the power is turned off. The memory cell is, for example, a memory cell of a charge trap structure. The charge storage layer  32  has a large number of traps that confine charges (electrons), and is made of a silicon nitride film, for example. The second insulating film  33  is, for example, made of a silicon oxide film, and serves as a potential barrier when the charges are injected from the silicon body  20  to the charge storage layer  32 , or when the charges stored in the charge storage layer  32  diffuse into the silicon body  20 . The first insulating film  31  is, for example, made of a silicon oxide film, and prevents the charges stored in the charge storage layer  32  from diffusing into the conductive layers WL 1  to WL 4 . 
     Referring back to  FIG. 1 , the gate insulating film  35  is provided between the drain-side selection gate DSG and the silicon body  20  which penetrates the drain-side selection gate DSG. The gate insulating film  35 , the drain-side selection gate DSG, and the silicon body  20  constitute a drain-side selection transistor DST. An upper end portion of the silicon body  20  protruding upward from the drain-side selection gate DSG is connected to a corresponding bit line BL. 
     The gate insulating film  36  is provided between the source-side selection gate SSG and the silicon body  20  which penetrates the source-side selection gate SSG. The gate insulating film  36 , the source-side selection gate SSG, and the silicon body  20  constitute a source-side selection transistor SST. An upper end portion of the silicon body  20  protruding upward from the source-side selection gate SSG is connected to the source line SL. 
     The back gate BG, the silicon body  20  provided in the back gate BG, and the insulating film  30  between the back gate BG and the silicon body  20  constitute a back gate transistor BGT. 
     A memory cell MC 1  having the conductive layer WL 1  as the control gate, a memory cell MC 2  having the conductive layer WL 2  as the control gate, a memory cell MC 3  having the conductive layer WL 3  as the control gate, and a memory cell MC 4  having the conductive layer WL 4  as the control gate are provided between the drain-side selection transistor DST and the back gate transistor BGT. 
     A memory cell MC 5  having the conductive layer WL 4  as the control gate, a memory cell MC 6  having the conductive layer WL 3  as the control gate, a memory cell MC 7  having the conductive layer WL 2  as the control gate, and a memory cell MC 8  having the conductive layer WL 1  as the control gate are provided between the back gate transistor BGT and the source-side selection transistor SST. 
     The drain-side selection transistor DST, the memory cells MC 1  to MC 4 , the back gate transistor BGT, the memory cells MC 5  to MC 8 , and the source-side selection transistor SST are connected in series to constitute one memory string. A plurality of such memory strings is arranged in the X and Y directions, whereby the plurality of memory cells MC 1  to MC 8  is three-dimensionally provided in the X, Y and Z directions. 
     Next, the contact region  1   b  will be illustrated. 
       FIG. 3  is a schematic cross-sectional view for illustrating a configuration of the contact region  1   b  provided in the semiconductor device  1  according to the first embodiment. 
     The contact region  1   b  is contiguously provided to the element region  1   a  shown in  FIG. 1  in the X direction. Further, the back gate BG is provided above the substrate  10  via an insulating layer  24 , and the plurality of conductive layers WL 1  to WL 4  and the plurality of insulating layers  25  are alternately stacked on the back gate BG in the contact region  1   b  in a similar manner to the element region  1   a . Note that, in  FIG. 3 , an insulating layer between the substrate  10  and the back gate BG is shown as the insulating layer  24 , an insulating layer between the conductive layers is shown as the insulating layer  25 , and an insulating layer provided on the drain-side selection gate DSG and the source-side selection gate SSG is shown as an insulating layer  43 , illustration of the above insulating layers having been omitted in  FIG. 1 . The insulating layers  24 ,  25 , and  43  can be, for example, formed of silicon oxide. 
     An upper surface of the insulating layer  43  is flattened, and an upper layer wiring (not shown) and the like which are connected to contact electrodes  60   a  to  60   e  are provided on the upper surface. 
     The contact electrodes  60   a  to  60   e  are provided in the contact region  1   b . The contact electrodes  60   a  to  60   e  extend in a stacking direction of the stacked body (Z direction), and each of the contact electrodes  60   a  to  60   e  reaches corresponding one of the conductive layers WL 1  to WL 4  and the back gate BG. 
     As the material for the contact electrodes  60   a  to  60   e , for example, a barrier metal having excellent adhesion properties such as titanium or titanium nitride, and a metal having excellent embedding properties such as tungsten, copper, or ruthenium can be used in combination. For example, portions  60   a   1  to  60   e   1  using the barrier metal are formed on inner surfaces of first insulating portions  63   a  to  63   e , and portions  60   a   2  to  60   e   2  using the metal such as tungsten are embedded in interiors formed by the portions  60   a   1  to  60   e   1 , thereby serving as the contact electrodes  60   a  to  60   e.    
     The conductive layers WL 1  to WL 4  are respectively connected, via the contact electrodes  60   a  to  60   d , to an upper layer wiring (not shown), and the back gate BG is connected to an upper layer wiring (not shown) via the contact electrode  60   e . Note that, the drain-side selection gate DSG and the source-side selection gate SSG are also connected to an upper layer wiring (not shown) via contact electrodes (not shown). 
     Frame portions  61   a  to  61   e  are provided in such a way as to cover the contact electrodes  60   a  to  60   e . The frame portions  61   a  to  61   e  are provided with the first insulating portions  63   a  to  63   e  and second insulating portions  62   a  to  62   e.    
     The first insulating portions  63   a  to  63   e  are provided between the contact electrodes  60   a  to  60   e  and the stacked body. The first insulating portions  63   a  to  63   e  are provided in such a way as to fill a space between the second insulating portions  62   a  to  62   e  and the contact electrodes  60   a  to  60   e.    
     The second insulating portions  62   a  to  62   e  are provided between the first insulating portions  63   a  to  63   e  and the stacked body. The second insulating portions  62   a  to  62   e  have cylindrical shapes with bottoms, and bottom surfaces  62   a   1  to  62   d   1  are in contact with the respective conductive layers WL 1  to WL 4 . A bottom surface  62   e   1  is in contact with the back gate BG. 
     The contact electrodes  60   a  to  60   d  penetrate the respective bottom surfaces  62   a   1  to  62   d   1  of the second insulating portions  62   a  to  62   d , and reach the respective conductive layers WL 1  to WL 4 . The contact electrode  60   e  penetrates the bottom surface  62   e   1  of the second insulating portion  62   e , and reaches the back gate BG. 
     The first insulating portions  63   a  to  63   e  and the second insulating portions  62   a  to  62   e  are formed of the material having insulation properties. 
     In this case, an etching rate of the material for the second insulating portions  62   a  to  62   e  is lower than that of the material for the first insulating portions  63   a  to  63   e . For example, the second insulating portions  62   a  to  62   e  are formed of silicon nitride, and the first insulating portions  63   a  to  63   e  are formed of silicon oxide. 
     Note that  FIG. 3  illustrates a case where the frame portions  61   a  to  61   e  have an approximately constant section size from upper end portions to bottom portions. However, the section size is not limited to this case. For example, the frame portions  61   a  to  61   e  may have an inverted circular truncated cone shape in which the section size decreases gradually from the upper end portion to the bottom portion, or may have a step by changing the section size between the upper end portion and the bottom portion. 
     According to the semiconductor device  1  of the embodiment, it is not necessary to process the conductive layers WL 1  to WL 4  provided in the contact region  1   b  in a stepwise manner, whereby improvement of productivity can be achieved. 
     Further, it is not necessary to process the conductive layers WL 1  to WL 4  provided in the contact region  1   b  in the stepwise manner, whereby downsizing of the semiconductor device  1  can be achieved. 
     Furthermore, if the conductive layers WL 1  to WL 4  are processed in the stepwise manner, the contact electrodes  60   a  to  60   d  can be only provided at a portion (stepped portion) protruding from an upper conductive layer. However, according to the semiconductor device  1  of the embodiment, positions where the contact electrodes  60   a  to  60   d  are provided can be freely arranged. For example, the contact electrode  60   a  having a short length can be provided closer to the element region  1   a  than the other electrodes or, in contrast, the contact electrode  60   d  or the contact electrode  60   e  having long lengths can be provided closer to the element region  1   a  than the other electrodes. 
     Furthermore, since the frame portions  61   a  to  61   e  are provided, processing accuracy of lower end positions of the contact electrodes  60   a  to  60   e  can be improved. 
     Second Embodiment 
     Next, a method of manufacturing a semiconductor device  1  according to a second embodiment will be illustrated. 
     As described above, the semiconductor device  1  is provided with an element region  1   a , a contact region  1   b , a peripheral circuit region (not shown), an upper layer wiring (not shown), and the like. A known technology can be applied to formation of elements provided in a region other than the contact region  1   b . Therefore, the formation of the elements provided in the contact region  1   b  will be herein mainly illustrated. 
       FIGS. 4 to 7  are schematic process cross-sectional views for illustrating the formation of the elements provided in the contact region  1   b.    
     First, as shown in  FIG. 4 , a stacked body  64  is formed in the following manner. An insulating layer  24  is formed on a substrate  10 , a back gate BG is formed on the insulating layer  24 , a plurality of insulating layers  25  and a plurality of conductive layers WL 1  to WL 4  are alternately stacked on the back gate BG, a drain-side selection gate DSG and a source-side selection gate SSG are formed on the stacked layers, and an insulating layer  43  is formed on top of the stacked layers. 
     In this case, the formation of the stacked body  64  can be performed at both the element region  1   a  and the contact region  1   b  simultaneously. 
     For example, by a chemical vapor deposition (CVD) method, the insulating layer  24  is formed on the substrate  10  shown in  FIG. 1 , the back gate BG is formed on the insulating layer  24 , the plurality of insulating layers  25  and the plurality of conductive layers WL 1  to WL 4  are stacked on the back gate BG alternately, the drain-side selection gate DSG and the source-side selection gate SSG are formed on the stacked layers, and the insulating layer  43  is formed on top of the stacked layers. 
     Furthermore, for example, a sacrificial layer may be formed instead of forming the insulating layers  24 ,  25 , and  43 . The sacrificial layer is then removed via a memory hole after the memory hole is formed in the element region  1   a . The insulating layers  24 ,  25 , and  43  may be formed on the portion where the sacrificial layer has been removed via the memory hole. In this case, the sacrificial layer can be, for example, formed of polysilicon without a doped impurity. A wet etching method using aqueous solution of choline (TMY) or the like can be, for example, used for the removal of the sacrificial layer. An atomic layer deposition (ALD) method or the like can be, for example, used for the formation of the insulating layers  24 ,  25 , and  43 . 
     Next, holes  65   a  to  65   e  (which correspond to an example of first holes) are formed as shown in  FIGS. 5A to 5C  in which the frame portions  61   a  to  61   e  are formed. 
     That is, the holes  65   a  to  65   e  are formed wherein the holes  65   a  to  65   e  extend in the stacking direction of the stacked body  64 , and each of the holes  65   a  to  65   e  reaches corresponding one of the conductive layers WL 1  to WL 4  and the back gate BG. 
     In this case, the holes  65   a  to  65   e  having different depths can be formed one by one. However, as shown in  FIGS. 5A to 5C , the number of man-hours of processing can be reduced by combining the forming depths. 
     That is, first, a hole having a first depth is formed. Next, when a hole having a second depth is formed, the formed hole having the first depth is further processed simultaneously. 
     In this case, a resist mask described later is formed by properly selecting a photomask from among a plurality of photomasks which are prepared in accordance with the forming depths, and performing a photolithography process using the selected photomask. Then, a process at the contact region  1   b  is performed using the formed resist mask. 
     For example, first, the hole  65   b  is formed as shown in  FIG. 5A . 
     In this case, a resist mask  66   b  having a predetermined opening is formed on the insulating layer  43 , and the hole  65   b  is formed by a reactive ion etching (RIE) method or the like. The hole  65   b  is also formed in a position where the hole  65   e  is to be formed. After the formation of the hole  65   b , the resist mask  66   b  is removed by a wet ashing method or the like. 
     Next, as shown in  FIG. 5B , a resist mask  66   c  having a predetermined opening is formed on the insulating layer  43 , and the hole  65   c  is formed by the RIE method or the like. In this case, the hole  65   c  is also formed in positions where the holes  65   d  and  65   e  are to be formed. Since the hole  65   b  has already been formed in the position where the hole  65   e  is to be formed, the hole  65   e  having a longer depth than the hole  65   b  can be formed. 
     That is, the hole  65   e  can be formed, when the hole  65   c  is formed, in such a way as to extend the hole  65   b  which has already been formed. In this case, a step due to misalignment or the like in the photolithography process may occur at a joint portion between the hole  65   b  which has already been formed and a hole to be newly formed. However, even if such a step occurs, the frame portion  61   e  can be formed. 
     After the formation of the hole  65   c , the resist mask  66   c  is removed by the wet ashing method or the like. 
     Next, as shown in  FIG. 5C , a resist mask  66   a  having a predetermined opening is formed on the insulating layer  43 , and the hole  65   a  is formed by the RIE method or the like. In this case, the hole  65   a  is also formed in a position where the hole  65   d  is to be formed. Since the hole  65   c  has already been formed in the position where the hole  65   d  is to be formed, the hole  65   d  having a longer depth than the hole  65   c  can be formed. 
     That is, the hole  65   d  can be formed, when the hole  65   a  is formed, in such a way as to extend the hole  65   c  which has already been formed. In this case, a step due to misalignment or the like in the photolithography process may occur at a joint portion between the hole  65   c  which has already been formed and a hole to be newly formed. However, even if such a step occurs, the frame portion  61   d  can be formed. 
     After the formation of the hole  65   a , the resist mask  66   a  is removed by the wet ashing method or the like. 
     Next, as shown in  FIG. 6A , the second insulating portions  62   a  to  62   e  are formed on inner surfaces of the holes  65   a  to  65   e . Then, the first insulating portions  63   a  to  63   e  are formed in interiors formed by the second insulating portions  62   a  to  62   e . The formation of the second insulating portions  62   a  to  62   e  and the first insulating portions  63   a  to  63   e  can be, for example, performed by the CVD method or the like. 
     In this case, the second insulating portions  62   a  to  62   e  are formed using the material having a lower etching rate than the material for the first insulating portion  63   a  to  63   e . For example, the second insulating portions  62   a  to  62   e  can be formed of silicon nitride, and the first insulating portions  63   a  to  63   e  can be formed of silicon oxide. 
     Next, as shown in  FIG. 6B , holes  67   a  to  67   e  (which correspond to an example of second holes) are formed in which the contact electrodes  60   a  to  60   e  are formed. 
     That is, the holes  67   a  to  67   e  are formed, wherein the holes  67   a  to  67   e  extend inside the first insulating portions  63   a  to  63   e  in the stacking direction of the stacked body  64 , and each of the holes  67   a  to  67   e  reaches the corresponding one of conductive layers WL 1  to WL 4  and the back gate BG. 
     For example, a resist mask  68  having a predetermined opening is formed on the insulating layer  43 , and the holes  67   a  to  67   e  are formed by the RIE method or the like. 
     In this case, the hole  67   a  having a short depth is formed first, and the bottom surface  62   a   1  of the second insulating portion  62   a  will be exposed. However, since the second insulating portions  62   a  to  62   e  are formed of the material having the lower etching rate than that of the material for the first insulating portions  63   a  to  63   e , the other holes  67   b  to  67   e  are formed before the hole  67   a  penetrates the bottom surface  62   a   1  of the second insulating portion  62   a . That is, the holes  67   a  to  67   e  penetrating the first insulating portions  63   a  to  63   e  are formed before the holes  67   a  to  67   e  penetrate the bottom surfaces  62   a   1  to  62   e   1  of the second insulating portions  62   a  to  62   e.    
     Next, as shown in  FIG. 7A , the conductive layers WL 1  to WL 4  and the back gate BG are respectively exposed by allowing the respective bottom surfaces  62   a   1  to  62   e   1  of the second insulating portions  62   a  to  62   e  to be penetrated. 
     The resist mask  68  is then removed by the wet ashing method or the like. 
     Next, as shown in  FIG. 7B , the contact electrodes  60   a  to  60   e  are respectively formed in the holes  67   a  to  67   e.    
     For example, a film serving as the contact electrodes  60   a  to  60   e  can be formed in such a way as to cover a surface of the insulating layer  43 . 
     The film formed outside the holes  67   a  to  67   e  is then removed, and the contact electrodes  60   a  to  60   e  are embedded and formed inside the holes  67   a  to  67   e.    
     As described above, the elements provided in the contact region  1   b  can be formed. 
     Then, an upper layer wiring (not shown) is formed above the insulating layer  43 , and the contact electrodes  60   a  to  60   e  and the upper layer wiring (not shown) are connected. 
     In this way, the semiconductor device  1  can be manufactured. 
     According to the method of manufacturing a semiconductor device of the embodiment, it is not necessary to process the conductive layers WL 1  to WL 4  provided in the contact region  1   b  in a stepwise manner, whereby improvement of productivity can be achieved. 
     Further, it is not necessary to form the conductive layers WL 1  to WL 4  provided in the contact region  1   b  in the stepwise manner, whereby downsizing of the semiconductor device  1  can be achieved. 
     Furthermore, if the conductive layers WL 1  to WL 4  are processed in the stepwise manner, the contact electrodes  60   a  to  60   d  can be only provided at a portion (stepped portion) protruding from a conductive layer of an upper layer. However, according to the method of manufacturing a semiconductor device of the embodiment, positions where the contact electrodes  60   a  to  60   d  are provided can be freely arranged. For example, the contact electrode  60   a  having a short length can be provided closer to the element region  1   a  than the other electrodes or, in contrast, the contact electrode  60   d  and the contact electrode  60   e  having long lengths can be provided closer to the element region  1   a  than the other electrodes. 
     Furthermore, since the frame portions  61   a  to  61   e  are provided, processing accuracy of lower end positions of the contact electrodes  60   a  to  60   e  can be improved. 
     Here, a peripheral circuit region  1   c  is also contiguously provided to the element region  1   a . Also, a semiconductor element  22  (for example, a transistor) for driving a memory cell provided in the peripheral circuit region  1   c  is connected to an upper layer wiring (not shown) via a contact electrode  60   f.    
     Therefore, the number of man-hours of processing the peripheral circuit region  1   c  can be reduced by forming a frame portion  61   f  and the contact electrode  60   f  in the peripheral circuit region  1   c  when the frame portions  61   a  to  61   e  and the contact electrodes  60   a  to  60   e  are formed in the contact region  1   b.    
       FIGS. 8A and 8B  are schematic process cross-sectional views for illustrating formation of the frame portion  61   f  and the contact electrode  60   f  in the peripheral circuit region  1   c.    
     First, as shown in  FIG. 8A , the hole  65   f  is formed in the peripheral circuit region  1   c  when the hole  65   e  is formed in the contact region  1   b . That is, the hole  65   f  can be formed in a similar manner to the formation of the hole  65   e  illustrated in  FIGS. 5A to 5C . 
     Next, as shown in  FIG. 8B , a second insulating portion  62   f  is formed when a second insulating portion  62   e  is formed, a first insulating portion  63   f  is formed when a first insulating portion  63   e  is formed, a hole  67   f  is formed when a hole  67   e  is formed, a bottom surface  62   f   1  of the second insulating portion  62   f  is penetrated when a bottom surface  62   e   1  of the second insulating portion  62   e  is penetrated, and the contact electrode  60   f  is formed when the contact electrode  60   e  is formed. 
     That is, the frame portion  61   f  and the contact electrode  60   f  can be formed in the peripheral circuit region  1   c  when the frame portion  61   e  and the contact electrode  60   e  are formed in the contact region  1   b.    
     In this case, a portion  60   f   1  using a barrier metal is formed on an inner surface of the first insulating portion  63   f  and a portion  60   f   2  using a metal such as tungsten is embedded in an interior formed by the portion  60   f   1  in a similar manner to the contact electrode  60   e , thereby serving as the contact electrode  60   f.    
     In this way, the number of man-hours of processing the peripheral circuit region  1   c  can be reduced. 
       FIG. 9  is a schematic perspective view for illustrating a configuration of an element region  1   a   1  provided in the semiconductor device  1  according to the first embodiment. 
     Note that, in  FIG. 9 , for purpose of easily viewing the drawing, illustration of insulating portions are omitted and only conductive portions are shown. 
     Although a U-shaped memory string has been illustrated in  FIG. 1 , an I-shaped memory string can be employed as shown in  FIG. 9 . 
     In this structure, a source line SL is provided on a substrate  10 , a source-side selection gate SSG (or lower portion selection gate) is provided above the source line SL, conductive layers WL 1  to WL 4  are provided above the source-side selection gate SSG, and a drain-side selection gate DSG (or upper portion selection gate) is provided between the uppermost conductive layer WL 1  and a bit line BL. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions. Moreover, above-mentioned embodiments can be combined mutually and can be carried out.