Patent Publication Number: US-2023145240-A1

Title: Methods for selective deposition utilizing n-type dopants and/or alternative dopants to achieve high dopant incorporation

Description:
FIELD OF INVENTION 
     This application is a divisional of, and claims priority to and the benefit of, U.S. patent application Ser. No. 16/932,275, filed Jul. 17, 2020 and entitled “METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION,” which is a non-provisional of, and claims priority to and the benefit of, U.S. Provisional Patent Application No. 62/879,980, filed Jul. 29, 2019 and entitled “METHODS FOR SELECTIVE DEPOSITION UTILIZING N-TYPE DOPANTS AND/OR ALTERNATIVE DOPANTS TO ACHIEVE HIGH DOPANT INCORPORATION,” both of which are hereby incorporated by reference herein. 
    
    
     FIELD OF INVENTION 
     The present disclosure generally relates to selective deposition of semiconductor films on substrates. More particularly, the disclosure relates to selective deposition utilizing dopants. The dopant precursors may include hydrides and halogenated Group V. 
     BACKGROUND OF THE DISCLOSURE 
     For logic applications, FinFET transistors have been made by epitaxial deposition processes. Dopants have been used to match a particular channel type, such as an n-type doped layer for NMOS applications. Particular n-type layers formed may include silicon carbide (SiC), silicon carbophosphine (SiCP), and silicon phosphine (SiP), for example. 
     Formation of the layers may be difficult when growing on a substitutional lattice site. There may be issues that may result in sacrificing at least one of selectivity, growth rate, dopant concentration, and resistivity of the grown layers. For example, to achieve particular selectivity for the layer, this may require the flow of a particular chemistry or the reduction in a process temperature that could adversely affect the growth rate of the layer and/or dopant incorporation. 
     As a result, it is desired to develop a process that allows for an optimal growth rate of a doped layer, while achieving a desired selectivity and geometry for the doped layer. 
     SUMMARY OF THE DISCLOSURE 
     This summary is provided to introduce a selection of concepts in a simplified form. These concepts are described in further detail in the detailed description of example embodiments of the disclosure below. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. 
     A method for forming a contact layer is disclosed. The method may comprise: cleaning a device on a semiconductor substrate of any oxides, the semiconductor substrate being disposed on a susceptor in a reaction chamber; stabilizing a temperature of the reaction chamber; flowing a halide precursor onto the device, the halide precursor comprises at least one of: hydrogen fluoride (HF); hydrogen chloride (HCl); hydrogen bromide (HBr); hydrogen iodide (HI); chlorine (Cl 2 ); fluorine (F 2 ); bromine (Br 2 ); or iodine (I 2 ); flowing a silicon precursor onto the device, the silicon precursor comprises at least one of: silane (SiH 4 ); dichlorosilane (DCS); disilane; or trisilane; and flowing a dopant precursor onto the device, the dopant precursor comprises at least one of: PCl 3 ; PCl 5 ; PBr 3 ; PBr 5 ; PI 3 ; PI 5 ; AsCl 3 ; AsCl 5 ; AsBr 3 ; AsBr 5 ; AsI 3 ; AsI 5 ; SbCl 3 ; SbCl 5 ; SbBr 3 ; SbBr 5 ; SbI 3 ; SbI 5 ; arsine (AsH 3 ); or phosphine (PH 3 ); wherein the halide precursor prevents deposition onto a dielectric layer disposed on the semiconductor substrate; wherein the silicon precursor and the dopant precursor react to form a contact layer; wherein any of the flowing steps are repeated to form a desired thickness of the contact layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWING FIGURES 
       These and other features, aspects, and advantages of the invention disclosed herein are described below with reference to the drawings of certain embodiments, which are intended to illustrate and not to limit the invention. 
         FIG.  1    is a cross-sectional illustration of a NMOS device formed in accordance with at least one embodiment of the invention. 
         FIG.  2    is a process flow diagram in accordance with at least one embodiment of the invention. 
         FIG.  3    illustrates an apparatus in accordance with at least one embodiment of the invention. 
     
    
    
     It will be appreciated that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help improve understanding of illustrated embodiments of the present disclosure. 
     DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS 
     Although certain embodiments and examples are disclosed below, it will be understood by those in the art that the invention extends beyond the specifically disclosed embodiments and/or uses of the invention and obvious modifications and equivalents thereof. Thus, it is intended that the scope of the invention disclosed should not be limited by the particular disclosed embodiments described below. 
     The illustrations presented herein are not meant to be actual views of any particular material, structure, or device, but are merely idealized representations that are used to describe embodiments of the disclosure. 
     For FinFET applications, a contact layer may be needed on top of a Fin. Contact layers may also be grown for silicon germanium (SiGe) applications as well. For contact layers in particular NMOS applications, it may be desirable to incorporate high levels of n-type dopant. Such may increase the electrically active behavior of the contact layer. 
       FIG.  1    illustrates a device  100  in accordance with at least one embodiment of the invention. The device  100  may comprise: a Fin  110 ; a shallow trench isolation (STI) layer  120 ; a contact layer  130 ; and a gate  140 . The Fin  110  may be a stack of lateral nanowires comprising at least one of: silicon, germanium, silicon germanium, or combinations thereof. The STI layer  120  may comprise a dielectric material, such as silicon oxide, silicon oxynitride, silicon oxycarbon, and combinations thereof, for example. The gate  140  may also comprise an oxide material, such as hafnium oxide or aluminum oxide, for example. 
     The contact layer  130  may comprise at least one of: silicon phosphine (SiP); silicon arsenide (SiAs); silicon antimonide (SiSb); or combinations thereof, for example. The contact layer  130  may be grown with a particular crystallographic orientation, such as a ( 111 ) direction in accordance with the Miller indices notation. 
     In growing the contact layer  130 , an additional issue may arise with the selectivity, as it may be difficult to grow the contact layer  130  without depositing a layer on the exposed dielectric material of the STI layer  120 . In other applications, the way to achieve such selectivity may be to increase a flow of hydrogen chloride (HCl) or to decrease a temperature of the process. However, such may not be possible in this application as increasing a flow of HCl or decreasing a process temperature may inhibit the growth rate of the contact layer  130  and/or adversely affect a doping level incorporated in the contact layer  130 . 
     In order to achieve a proper growth rate and doping level,  FIG.  2    illustrates a process  200  for growing a contact layer  130 . The process  200  may comprise: a preclean step  210 ; a temperature stabilization step  220 ; a halide precursor flow step  230 ; a silicon precursor flow step  240 ; a dopant precursor flow step  250 ; and a repeat cycle  260 . The process  200  may occur in a deposition apparatus comprising: a reaction chamber, a heating element, a susceptor, and multiple gas sources. 
     The preclean step  210  may comprise a process to remove any oxides on a device prior to growing the contact layer  130 . The preclean step  210  may incorporate flow of chemical and sublimation as described in U.S. Pat. No. 10,053,774, entitled “Reactor System for Sublimation of Pre-Clean Byproducts and Method Thereof,” which is hereby incorporated by reference. Alternatively, the preclean step  210  may flow NF 3  and ammonia (NH 3 ) chemistry with remote plasma. The preclean step  210  may take place at a temperature range between 500° C. and 800° C., between 550° C. and 700° C., or between 600° C. and 650° C. 
     The temperature stabilization step  220  may be required if the preclean step  210  requires a different temperature than that required to form the contact layer  130 . The temperature stabilization step  220  may result in a temperature of a reaction chamber ranging between 300° C. and 800° C., between 400° C. and 650° C., or between 450° C. and 550° C. 
     The halide precursor flow step  230  may comprise a flow of at least one of: hydrogen fluoride (HF); hydrogen chloride (HCl); hydrogen bromide (HBr); hydrogen iodide (HI); chlorine (Cl 2 ); fluorine (F 2 ); bromine (Br 2 ); iodine (I 2 ); or combinations thereof. The purpose of the halide precursor flow step  230  is to allow for selective deposition of the contact layer  130  onto the Fin  110 , and not the STI layer  120 . However, the halide precursor flow step  230  should not be so great as to inhibit the growth rate of the contact layer  130 . 
     The silicon precursor flow step  240  may comprise a flow of at least one of: silane (SiH 4 ); dichlorosilane (DCS); disilane; trisilane; trichlorosilane; or combinations thereof. The silicon precursor will deposit onto the Fin  110 , where it will react to form the contact layer  130 . 
     The dopant precursor flow step  250  may comprise a flow of at least one of: a phosphoric halide, such as PCl 3 , PCl 5 , PBr 3 , PBr 5 , PI 3 , or PI 5 ; an arsenic halide, such as AsCl 3 , AsCl 5 , AsBr 3 , AsBr 5 , AsI 3 , or AsI 5 ; an antimony halide, such as SbCl 3 , SbCl 5 , SbBr 3 , SbBr 5 , SbI 3 , or SbI 5 ; or a hydride, such as arsine (AsH 3 ) or phosphine (PH 3 ), for example. The dopant precursor flow step  250  may comprise co-flowing or alternately flowing multiple dopant sources chosen among the ones listed above. 
     Prior approaches may have used phosphine or arsine as a dopant source, but such may result in safety issues in terms of handling and delivery to the reaction chamber due to the high vapor pressures involved. By including at least one of the dopant precursors listed above, the surface chemistry may be modified to incorporate more of the n-type dopant in an electrically active lattice position, while operating in a safe regime. 
     The method  200  may also include the repeat cycle step  260  in order to form a film of a desired thickness. 
     As a result of the steps in the method  200 , a lower temperature and pressure for the reaction chamber may be possible. The temperature may range between 400° C. and 800° C., between 550° C. and 700° C., or between 600° C. and 650° C. The pressure may range between 0.1 and 760 Torr, between 10 and 200 Torr, or between 30 and 100 Torr. 
     Furthermore, the process  200  may result in a contact layer formed with silicon phosphine (SiP), for example, that has a high phosphorous content and electrically active characteristic without going into a defect state. In addition, a high level of dopant incorporation may be possible due to the process  200 . 
       FIG.  3    illustrates an apparatus  300  for forming a device in accordance with at least one embodiment of the disclosure. Apparatus  300  includes a reaction chamber  302 , a first gas source  304  configured to provide a first gas to reaction chamber  302 , a second gas source  306  configured to provide a second gas to reaction chamber  302 ; and a susceptor  308  configured to hold a semiconductor substrate on which a device is formed. Apparatus  300  can further include a gas distribution device  310  to provide one or more gases to reaction chamber  302 . Additionally, apparatus  300  can include a controller  312  to, for example, control gas flowrates, reaction chamber pressure, reaction chamber temperature, and/or the like. Apparatus  300  can be configured to perform a method as described herein. 
     The particular implementations shown and described are illustrative of the invention and its best mode and are not intended to otherwise limit the scope of the aspects and implementations in any way. Indeed, for the sake of brevity, conventional manufacturing, connection, preparation, and other functional aspects of the system may not be described in detail. Furthermore, the connecting lines shown in the various figures are intended to represent exemplary functional relationships and/or physical couplings between the various elements. Many alternative or additional functional relationship or physical connections may be present in the practical system, and/or may be absent in some embodiments. 
     It is to be understood that the configurations and/or approaches described herein are exemplary in nature, and that these specific embodiments or examples are not to be considered in a limiting sense, because numerous variations are possible. The specific routines or methods described herein may represent one or more of any number of processing strategies. Thus, the various acts illustrated may be performed in the sequence illustrated, in other sequences, or omitted in some cases. 
     The subject matter of the present disclosure includes all novel and nonobvious combinations and subcombinations of the various processes, systems, and configurations, and other features, functions, acts, and/or properties disclosed herein, as well as any and all equivalents thereof.