Patent Publication Number: US-9847708-B2

Title: PFC circuit

Description:
RELATED APPLICATIONS 
     This application is a continuation of the following application, U.S. patent application Ser. No. 14/327,769, filed on Jul. 10, 2014, and which is hereby incorporated by reference as if it is set forth in full in this specification, and which also claims the benefit of Chinese Patent Application No. 201310308722.9, filed on Jul. 18, 2013, which is incorporated herein by reference in its entirety. 
    
    
     FIELD OF THE INVENTION 
     The present invention generally relates to power converter circuitry, and more particularly to power factor correction (PFC) circuits. 
     BACKGROUND 
     Power factor correction (PFC) circuitry is typically added at an input side of a converter to decrease harmonic pollution to the power grid generated by power electric apparatuses. Active PFC may be utilized to increase the power factor of power electric apparatuses to decrease harmonic pollution because the input current can be regulated to be in phase with input voltage. For example, boost PFC topology may be used as an active PFC circuit, such as in high power applications operating in a continuous conduction mode (CCM). 
     SUMMARY 
     In one embodiment, a power factor correction (PFC) circuit can include: (i) a rectifier bridge and a PFC converter coupled to an input capacitor; (ii) a harmonic wave compensation circuit configured to shift a phase of a DC input voltage provided from the rectifier bridge, where the harmonic wave compensation circuit comprises a phase of about −45° when a corner frequency is about 50 Hz; and (iii) a PFC control circuit configured to control the PFC converter, where the PFC control circuit comprises a first sampling voltage, and the harmonic wave compensation circuit is configured to control a phase of the first sampling voltage to lag a phase of the DC input voltage by about 45°. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block diagram of an example PFC circuit. 
         FIG. 2  is a schematic block diagram of a first example PFC circuit, in accordance with embodiments of the present invention. 
         FIG. 3  is a schematic block diagram of a second example PFC circuit, in accordance with embodiments of the present invention. 
         FIG. 4  is an example bode diagram, in accordance with embodiments of the present invention. 
         FIG. 5  is a schematic block diagram of a third example PFC circuit, in accordance with embodiments of the present invention. 
         FIG. 6  is a schematic block diagram of a fourth example PFC circuit, in accordance with embodiments of the present invention. 
         FIG. 7  is a schematic block diagram of a fifth example PFC circuit, in accordance with embodiments of the present invention. 
         FIG. 8  is a schematic block diagram of a sixth PFC example circuit, in accordance with embodiments of the present invention. 
         FIG. 9  is a schematic block diagram of a seventh example PFC circuit, in accordance with embodiments of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference may now be made in detail to particular embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention may be described in conjunction with the preferred embodiments, it may be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it may be readily apparent to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known methods, procedures, processes, components, structures, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention. 
     Referring now to  FIG. 1 , shown is a schematic block diagram of an example power factor correction (PFC) circuit. This example PFC circuit can include power stage circuit  101  and PFC control circuit  102 . Power stage circuit  101  may include rectifier bridge  1011  to rectify AC input voltage V in  to DC input voltage V g . Power stage circuit  101  may also include input capacitor C in  coupled between the two output terminals of rectifier bridge  1011 , and configured to filter an output signal of rectifier bridge  1011 . Also, PFC converter  1012  can be coupled in parallel with input capacitor C in  to generate DC output voltage V o  to supply to loads (e.g., light-emitting diode [LED] loads). 
     PFC control circuit  102  may include voltage sampling circuit  1021 , the input terminal of which can connect to the high voltage output terminal of rectifier bridge  1011  to sample DC input voltage V g . PFC control circuit  102  may also include current sampling circuit  1022 , the input terminal of which can connect to the output terminal of PFC converter  1012  to sample output current i o  of power stage circuit  101 . PFC control circuit  102  may also include feedback signal regulation circuit  1023  configured to regulate DC input voltage V g  and output current i o  to generate a driving signal to drive PFC converter  1012 . The driving signal generated by PFC control circuit  102  may be used to control operation of power stage circuit  101  such that a waveform of AC input current i in  varies with a waveform of AC input voltage V in  in order to achieve power factor correction (PFC) and improve the overall power factor value. 
     Because of the capacitive effects of input capacitor C in , the phase of DC input current i g  output by rectifier bridge  1011  may be advanced relative to the phase of DC input voltage V g  by about 90°, which may decrease the performance as to AC input current i in  varying with AC input voltage V in . Furthermore, because output current signal i o  may be regulated by PFC control circuit  102 , a component, the phase of which may be advanced relative to AC input voltage V in  by about 45°, may be added to the input power. This may also decrease the performance as to AC input current i in  varying with AC input voltage V in . Thus, due to the influence of input capacitor C in  and PFC control circuit  102 , the power factor value of the PFC circuit may be reduced due to the performance of AC input current i in  varying with AC input voltage V in . 
     In one embodiment, a PFC circuit can include: (i) a rectifier bridge and a PFC converter coupled to an input capacitor; (ii) a harmonic wave compensation circuit configured to shift a phase of a DC input voltage provided from the rectifier bridge, where the harmonic wave compensation circuit comprises a phase of about −45° when a corner frequency is about 50 Hz; and (iii) a PFC control circuit configured to control the PFC converter, where the PFC control circuit comprises a first sampling voltage, and the harmonic wave compensation circuit is configured to control a phase of the first sampling voltage to lag a phase of the DC input voltage by about 45°. 
     Referring now to  FIG. 2 , shown is a schematic block diagram of a first example PFC circuit, in accordance with embodiments of the present invention. This particular example PFC circuit can include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . The input of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and the output of harmonic wave compensation circuit  204  can connect to a voltage sampling input of PFC control circuit  203 . Also, a ground terminal harmonic wave compensation circuit  204  can connect to ground (e.g., VSS). For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     When corner frequency f c  of harmonic wave compensation circuit  204  is about 50 Hz, the phase of voltage at the output of harmonic wave compensation circuit  204  may lag a phase of DC input voltage V g  at the input of harmonic wave compensation circuit  204  by about 45°, which may lag a phase of AC input voltage V in  of the PFC circuit by about 45°. Because an output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 , the phase of the voltage signal received by PFC control circuit  203  may lag a phase of AC input voltage V in  by about 45°. 
     Thus, the phase shift generated by the component, with a phase advanced relative to a phase of input voltage by about 45°, as added to the input power may be counterbalanced. Because PFC control circuit  203  may be configured as a closed loop control mode, the phase shift of about 45° generated by harmonic wave compensation circuit  204  can also decrease the phase shift of AC input current i in  advanced relative to AC input voltage V in  to some extent. In this way, a PFC circuit of particular embodiments can substantially eliminate the influence of power factor value by PFC control circuit  203  and weaken the influence of power factor value by input capacitor C in . 
     Referring now to  FIG. 3 , shown is a schematic block diagram of a second example PFC circuit, in accordance with embodiments of the present invention. This particular example PFC circuit can include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . An input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and an output terminal of harmonic wave compensation circuit  204  can connect to a voltage sampling input terminal of PFC control circuit  203 . For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is 50 Hz. 
     Harmonic wave compensation circuit  204  may include harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c  coupled in series. The common node of harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c  may be configured as the output terminal of harmonic wave compensation circuit  204 . The other terminal of harmonic wave compensation resistor R c  may be configured as the input terminal of harmonic wave compensation circuit  204 . The other terminal of harmonic wave compensation capacitor C c  may be configured as a ground terminal of harmonic wave compensation circuit  204 . DC input voltage V g  generated by rectifying AC input voltage V in  may be configured as an input signal of harmonic wave compensation circuit  204 . Also, a value of corner frequency f c  of the RC first-order filter that includes harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c  can be determined in accordance with RC filter characteristics. 
     Referring now to  FIG. 4 , shown is an example bode diagram, in accordance with embodiments of the present invention. In this example bode diagram of harmonic wave compensation circuit  204 , when corner frequency f c  is about 50 Hz, the corresponding phase is about −45° in the phase diagram. This indicates that the phase of the output voltage of harmonic wave compensation circuit  204  may lag a phase of DC input voltage V g  received at the input terminal by about 45°. Further, this indicates that the phase of the output voltage of harmonic wave compensation circuit  204  may lag a phase of AC input voltage V in  of the PFC circuit by about 45°. 
     Because the output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 , the phase of DC input voltage V g  received by PFC control circuit  203  may lag a phase of AC input voltage V in  of the PFC circuit by about 45°. Thus, the phase shift generated by the component with a phase advanced relative to input voltage V g  by 45°, and added to the input power can be counterbalanced based on PFC circuit characteristics. 
     Referring now to  FIG. 5 , shown is a schematic block diagram of a third example PFC circuit, in accordance with embodiments of the present invention. This example PFC circuit can include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . The input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and the output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 . For example, the phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     PFC control circuit  203  can include voltage sampling circuit  2031 , an input terminal of which may be configured as the voltage sampling input terminal of PFC control circuit  203 . PFC control circuit  203  may also include current sampling circuit  2032  coupled to an output terminal of PFC converter  202 . PFC control circuit  203  may also include error signal amplifier circuit  2033 , an input terminal of which can connect to an output terminal of current sampling circuit  2032  and coupled to the output terminal of voltage sampling circuit  2031 . PFC control circuit  203  may also include driving signal generation circuit  2034 , an input terminal of which can connect to an output terminal of error signal amplifier circuit  2033 . An output terminal of driving signal generation circuit  2034  can connect to a power switch (e.g., a transistor gate) of PFC converter  202 . 
     Voltage sampling circuit  2031  may be configured to sample DC input voltage V g  to generate sampling voltage V gi . Current sampling circuit  2032  may be configured to sample output current i o  of PFC converter  202  to generate sampling voltage V s . Error signal amplifier circuit  2033  can receive sampling voltage V gi , sampling voltage V s , and reference voltage V ref  that represents an average value of output current i o . Error signal amplifier circuit  2033  may regulate sampling voltage V s  to generate an error voltage signal. Also, driving signal generation circuit  2034  may compare the error voltage signal against ramp signal V ramp  to generate a driving signal to control operation of the power switch of PFC converter  202 . 
     Referring now to  FIG. 6 , shown is a schematic block diagram of a fourth example PFC circuit, in accordance with embodiments of the present invention. This particular example PFC circuit can as well include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . The input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and the output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 . For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     PFC control circuit  203  include voltage sampling circuit  2031 , the input terminal of which may be configured as the voltage sampling input terminal of PFC control circuit  203 . PFC control circuit  203  may also include current sampling circuit  2032  coupled to the output terminal of PFC converter  202 . PFC control circuit  203  may also include error signal amplifier circuit  2033 , the input terminal of which can connect to an output terminal of current sampling circuit  2032 , and may be coupled to an output terminal of voltage sampling circuit  2031 . PFC control circuit  203  may also include driving signal generation circuit  2034 , an input terminal of which can connect to the output terminal of error signal amplifier circuit  2033 , and an output terminal of which can connect to the power switch of PFC converter  202 . 
     Voltage sampling circuit  2031  include resistor R 1  and resistor R 2  coupled in series. The common node between resistor R 1  and resistor R 2  may be configured as the output terminal of voltage sampling circuit  2031 . The other terminal of resistor R 1  may be configured as an input terminal of voltage sampling circuit  2031 , and the other terminal of resistor R 2  can connect to ground. Of course, those skilled in the art will recognize that other voltage sampling circuit implementations can be supported in particular embodiments, and the voltage sampling circuit including resistors R 1  and R 2  coupled in series represents only one example. Also for example, current sampling circuit  2032  can be implemented by resistor R s , shown as dotted box  2032  in  FIG. 6 , but other current sampling circuit implementations can also be supported in particular embodiments. 
     Referring now to  FIG. 7 , shown is a schematic block diagram of a fifth example PFC circuit, in accordance with embodiments of the present invention. This particular example PFC circuit can include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . An input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and an output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 . For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     PFC control circuit  203  can include voltage sampling circuit  2031 , the input terminal of which may be configured as a voltage sampling input terminal of PFC control circuit  203 . PFC control circuit  203  can also include current sampling circuit  2032 , coupled to the output terminal of PFC converter  202 . PFC control circuit  203  can also include error signal amplifier circuit  2033 , the input terminal of which can connect to the output terminal of current sampling circuit  2032 , and may be coupled to the output terminal of voltage sampling circuit  2031 . PFC control circuit  203  can also include driving signal generation circuit  2034 , the input terminal of which can connect to the output terminal of error signal amplifier circuit  2033 , and the output terminal of which can connect to the power switch of PFC converter  202 . 
     Error signal amplifier circuit  2033  may include operational amplifier G m  and capacitor C 1 . The inverting input terminal of operational amplifier G m  can connect to the output terminal of current sampling circuit  2032  to receive sampling voltage V s , and the non-inverting input terminal of operational amplifier G m  may receive reference voltage V ref . The output terminal of operational amplifier G m  can connect to one terminal of capacitor C 1 , and the other terminal of capacitor C 1  can connect to the output terminal of voltage sampling circuit  2031 . 
     Also, the common node of the output terminal of operational amplifier G m  and capacitor C 1  may be configured as the output terminal (e.g., error voltage signal) of error signal amplifier circuit  2033 . One terminal of capacitor C 1  may receive sampling voltage V gi , and the other terminal of capacitor C 1  can connect to the output terminal of operational amplifier G m . The error between sampling voltage V s  and reference voltage V ref  may be calculated and amplified by operational amplifier G m  to generate the error voltage signal, which may be provided to driving signal generator  2034 . 
     Referring now to  FIG. 8 , shown is a schematic block diagram of a sixth PFC example circuit, in accordance with embodiments of the present invention. This example PFC circuit can also include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . The input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and an output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 . For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     PFC control circuit  203  can include voltage sampling circuit  2031 , the input terminal of which may be configured as the voltage sampling input terminal of PFC control circuit  203 . PFC control circuit  203  can also include current sampling circuit  2032 , coupled to the output terminal of PFC converter  202 . PFC control circuit  203  can also include error signal amplifier circuit  2033 , the input terminal of which can connect to an output terminal of current sampling circuit  2032 , and can connect to an output terminal of voltage sampling circuit  2031 . PFC control circuit  203  can also include driving signal generation circuit  2034 , the input terminal of which can connect to an output terminal of error signal amplifier circuit  2033 , and the output terminal of which can connect to the power switch of PFC converter  202 . 
     Driving signal generation circuit  2034  may include a comparator. The inverting input terminal of the comparator may receive the error voltage signal from error signal amplifier circuit  2033 , and the non-inverting input terminal of the comparator may receive ramp voltage V ramp . The output terminal of the comparator may output the driving signal to control and/or drive the power switch of PFC converter  202 . For example, PFC converter  202  can be any suitable converter or regulator, such as switched-mode power supply (SMPS) topology (e.g., buck, boost, buck-boost, SEPIC, Zeta, flyback, forward, etc.). 
     Referring now to  FIG. 9 , shown is a schematic block diagram of a seventh example PFC circuit, in accordance with embodiments of the present invention. This example PFC circuit can also include rectifier bridge  201 , input capacitor C in , PFC converter  202 , PFC control circuit  203 , and harmonic wave compensation circuit  204 . The input terminal of harmonic wave compensation circuit  204  can connect to the high voltage output terminal of rectifier bridge  201 , and the output terminal of harmonic wave compensation circuit  204  can connect to the voltage sampling input terminal of PFC control circuit  203 . For example, a phase of harmonic wave compensation circuit  204  may be about −45° when corner frequency f c  is about 50 Hz. 
     Harmonic wave compensation circuit  204  can include harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c  coupled in series. The common node of harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c  may be configured as the output terminal of harmonic wave compensation circuit  204 . The other terminal of harmonic wave compensation resistor R c  may be configured as an input terminal of harmonic wave compensation circuit  204 , and the other terminal of harmonic wave compensation capacitor C c  may be grounded. 
     PFC control circuit  203  can include voltage sampling circuit  2031 , current sampling circuit  2032 , error signal amplifier circuit  2033 , and driving signal generation circuit  2034 . Voltage sampling circuit  2031  include resistors R 1  and R 2  coupled in series, and a common node between resistors R 1  and R 2  may be configured as an output of voltage sampling circuit  2031 . The other terminal of resistor R 1  may be configured as an input terminal of voltage sampling circuit  2031 , and the other terminal of resistor R 2  can connect to ground. 
     Current sampling circuit  2032  can be implemented by sampling resistor R s . Also, error signal amplifier circuit  2033  may include operational amplifier G m  and capacitor C 1 . The inverting input terminal of operational amplifier G m  can connect to the output terminal of current sampling circuit  2032  to receive sampling voltage V s , and the non-inverting input terminal of operational amplifier G m  may receive reference voltage V ref . The output terminal of operational amplifier G m  can connect to one terminal of capacitor C 1 , and the other terminal of capacitor C 1  can connect to an output terminal of voltage sampling circuit  2031 . The common node of the output terminal of operational amplifier G m  and capacitor C 1  may be configured as the output terminal (e.g., the error voltage signal) of error signal amplifier circuit  2033 . Signal generation circuit  2034  include a comparator. The inverting input terminal of the comparator may receive the error voltage signal, and the non-inverting input terminal of the comparator may receive ramp voltage V ramp . The output of the comparator may be configured as the driving signal to drive the power switch of PFC converter  202 . 
     DC input voltage V g  generated by rectifying AC input voltage V in  may be received at harmonic wave compensation circuit  204 . The value of corner frequency f c  of the RC first-order filter, including harmonic wave compensation resistor R c  and harmonic wave compensation capacitor C c , can be determined to be about 50 Hz based on RC filter characteristics. Thus, the phase of the output voltage of harmonic wave compensation circuit  204  may lag a phase of DC input voltage V g  at the input terminal by about 45°. This can also indicate that the phase of the output voltage of harmonic wave compensation circuit  204  may lag a phase of AC input voltage V in  of the PFC circuit by about 45°. Because the output of harmonic wave compensation circuit  204  can connect to the voltage sampling input of PFC control circuit  203 , the phase of sampling voltage V g , received at one terminal of capacitor C 1  of PFC control circuit  203  may lag a phase of AC input voltage V in  by about 45°. 
     An error between sampling voltage V s  and reference voltage V ref  may be determined and amplified by operational amplifier G m . The output of operational amplifier G m  can be coupled to the other terminal of capacitor C 1  to generate the error voltage signal. The error voltage signal may be compared against ramp voltage V ramp  by driving signal generation circuit  2034  to generate the driving signal to control/drive the power switch (e.g., power transistor) of PFC converter  202 . Also, the phase shift generated by the component with a phase advanced relative to the input voltage by about 45° can be counterbalanced by harmonic wave compensation circuit  204 . 
     The embodiments were chosen and described in order to best explain the principles of the invention and its practical applications, to thereby enable others skilled in the art to best utilize the invention and various embodiments with modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims appended hereto and their equivalents.