Patent Publication Number: US-2023132901-A1

Title: Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     The present application is divisional application of U.S. patent application Ser. No. 17/355,178 filed on Jun. 23, 2021, which claims priority to U.S. Provisional Patent Application No. 63/043,068, filed on Jun. 23, 2020, each of which is incorporated by reference herein in its entirety. 
    
    
     BACKGROUND 
     The present disclosure relates to clock and data recovery (CDR) and, more particularly, to a clock and data recovery circuit having a triple-path structure for bandwidth tracking, and a related oscillator circuit and method for clock and data recovery. 
     With the use of clock and data recovery (CDR) techniques, a receiver can retrieve data from a data stream transmitted without additional timing information. Firstly, the receiver may perform clock recovery to extract a clock signal embedded in level transitions in the data stream. Next, the receiver can phase-align the clock signal to the level transitions in the data stream, and recover the data from the data stream by sampling the data stream according to the phase-aligned clock signal. For example, CDR circuits have been widely used in high-speed serial interfaces to regenerate a data stream according to a high speed clock signal, which is phase-aligned to level transitions in the data stream. CDR circuits may face several challenges. For example, an oscillator circuit of a CDR circuit may suffer from large jitter resulting from process variations, temperature variations, and/or timing uncertainties in high-speed data transmission. 
     SUMMARY 
     The described embodiments provide a clock and data recovery circuit having a triple-path structure for bandwidth tracking, and a related oscillator circuit and method for clock and data recovery. 
     Some embodiments described herein may include a clock and data recovery (CDR) circuit. The CDR circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock and accordingly generate a sampling result. The phase detector, coupled to the sampling circuit, is configured to generate a detection result according to the sampling result. The first processing circuit, coupled to the sampling circuit, is configured to process the sampling result to generate a first digital code. The second processing circuit, coupled to the first processing circuit, is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit, coupled to the sampling circuit, the phase detector, the first processing circuit and the second processing circuit, is configured to generate the output clock according to the detection result, the first digital code and the second digital code. A phase of the output clock is adjusted at least according to the detection result, and a frequency of the output clock is adjusted according to the first digital code and the second digital code. 
     Some embodiments described herein may include an oscillator circuit. The oscillator circuit includes a current-controlled oscillator, a first conversion circuit, a second conversion circuit and a third conversion circuit. The current-controlled oscillator is configured to generate an output clock according to a first control current, a second control current and a third control current. A frequency of the output clock is controlled by the first control current and the second control current, and a phase of the output clock is controlled by the third control current. The first conversion circuit, coupled to the current-controlled oscillator, is configured to convert a first digital code to the first control current according to a first reference current. The second conversion circuit, coupled to the current-controlled oscillator and the first conversion circuit, is configured to convert a second digital code to the second control current, the first reference current and a second reference current. The second digital code is an accumulation result of at least one most significant bit of the first digital code. The third conversion circuit, coupled to the current-controlled oscillator and the first conversion circuit, is configured to convert a third digital code and the second reference current to the third control current. 
     Some embodiments described herein may include a method for clock and data recovery (CDR). The method includes: generating a data signal and an edge signal by sampling input data according to an output clock outputted from an oscillator, the data signal and the edge signal carrying phase error information on a phase error between the input data and the output clock; generating a detection result according to the data signal and the edge signal, the detection result indicating a phase relationship between the input data and the output clock; accumulating the phase error information carried by the data signal and the edge signal to generate a first digital code; accumulating at least one most significant bit of the first digital code to generate a second digital code; adjusting a phase of the output clock according to the detection result and the second digital code; and adjusting a frequency of the output clock according to the first digital code and the second digital code. 
     With the use of the proposed CDR scheme, an oscillator circuit in a CDR circuit can not only have a wide tuning range but also high resolution despite temperature variations. In addition, the proposed CDR scheme can achieve bandwidth tracking at various frequency corners, thereby ensuring good loop stability. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    is a block diagram illustrating an exemplary clock and data recovery circuit in accordance with some embodiments of the present disclosure. 
         FIG.  2    illustrates an implementation of the clock and data recovery circuit shown in  FIG.  1    in accordance with some embodiments of the present disclosure. 
         FIG.  3    illustrates an implementation of the control circuit shown in  FIG.  2    in accordance with some embodiments of the present disclosure. 
         FIG.  4    illustrates an implementation of the digital-to-analog converter shown in  FIG.  3    in accordance with some embodiments of the present disclosure. 
         FIG.  5    is a flow chart of an exemplary method for clock and data recovery in accordance with some embodiments of the present disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, parameter values in the description that follows may vary depending on a given technology node. As another example, parameter values for a given technology node may vary depending on a given application or operating scenario. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, it will be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present. 
     To ensure loop stability despite temperature variations, a clock and data recovery (CDR) circuit may utilize an oscillator circuit with a wide tuning range. For example, the oscillator circuit may be designed to have a large frequency step to thereby widen a tuning range thereof. However, the large frequency step results in large jitter outputted from the oscillator circuit. 
     The present disclosure describes exemplary CDR circuits, each of which can employ a triple-path structure for controlling operation of an oscillator circuit. The oscillator circuit is included in the exemplary CDR circuit, and configured to generate an output clock for recovering data from a data stream. Two circuit paths of the triple-path structure can perform coarse tuning and fine tuning on a frequency of the output clock, respectively. In some embodiments, one of the two circuit paths is configured to receive a digital code to perform the fine tuning, and the other of the two circuit paths is configured to receive an accumulation result of a portion of the digital code to perform the coarse tuning. Additionally, or alternatively, the triple-path structure can achieve bandwidth tracking with the use of the circuit path used for the coarse tuning. The present disclosure further describes exemplary oscillator circuits, each of which can not only have a wide tuning range but also high resolution. Related methods for CDR are also described in the present disclosure. Further description is provided below. 
       FIG.  1    is a block diagram illustrating an exemplary CDR circuit in accordance with some embodiments of the present disclosure. The CDR circuit  100  can be configured to recover timing information carried by input data D IN , such as a data stream, and regenerate the input data D IN  according to the recovered timing information. The CDR circuit  100  includes, but is not limited to, a sampling circuit  110 , a phase detector (PD)  120 , a plurality of processing circuits  130  and  140 , and an oscillator circuit  150 . In the present embodiment, the CDR circuit  100  may employ a triple-loop structure. For example, the sampling circuit  110  may be used together with the PD  120  and the oscillator circuit  150  to implement a phase tracking loop. The sampling circuit  110  may be used together with the processing circuit  130  and the oscillator circuit  150  to implement a frequency tracking loop. Also, the sampling circuit  110  may be used together with the processing circuit  130 , the processing circuit  140  and the oscillator circuit  150  to implement another frequency tracking loop. 
     The sampling circuit  110  is configured to sample the input data D IN  according to an output clock CK OUT , and accordingly generate a sampling result SR. In the present embodiment, the sampling circuit  110  may sample data bits of the input data D IN  and a data edge in between two consecutive data bits according to the output clock CK OUT , and accordingly generate a data signal DS and an edge signal ES. As a result, the data signal DS and the edge signal ES can carry phase error information on a phase error between the input data D IN  and the output clock CK OUT . By way of example but not limitation, the sampling circuit  110  may perform two-times (2×) oversampling on the input data D IN  to generate the sampling result SR. 
     The PD  120 , coupled to the sampling circuit  110 , is configured to generate a detection result DR according to the sampling result SR. The detection result DR may indicate whether the output clock CK OUT  lags or leads the input data D IN . In the present embodiment, the PD  120  may receive the data signal DS and the edge signal ES to detect a difference in phase between the input data D IN  and the output clock CK OUT . The detection result DR may include an up signal UP and a down signal DN to indicate whether the output clock CK OUT  lags or leads the input data D IN . For example, the PD  120  may generate the up signal UP with a predetermined logic level when the output clock CK OUT  lags the input data D IN , and generate the down signal DN with a predetermined logic level when the output clock CK OUT  leads the input data D IN . In some embodiments, the detection result DR may be implemented using a digital code DC P  which includes the up signal UP and the down signal DN. 
     The processing circuit  130 , coupled to the sampling circuit  110 , is configured to process the sampling result SR to generate a digital code DC I , which can indicate information on a frequency error between the input data D IN  and the output clock CK OUT . In the present embodiment, the digital code DC I  is implemented as an M-bit digital signal, where M is an integer greater than one. 
     The processing circuit  140 , coupled to the processing circuit  130 , is configured to accumulate a portion of the digital code DC I  to generate a digital code DC F . A rate of change of a code value of the digital code DC F  can be slower than a rate of change of a code value of the digital code DC I . For example, the portion of the digital code DC I  may be K bits of the digital code DC I , where K is a positive integer less than M. As another example, the portion of the digital code DC I  may be the most significant bit (MSB) of the digital code DC I . As another example, the portion of the digital code DC′ may be the first two MSBs of the digital code DC I . As still another example, the portion of the digital code DC I  may be at least one MSB of the digital code DC I . In the present embodiment, the digital code DC F  can indicate information on the frequency error between the input data D IN  and the output clock CK OUT  since the digital code DC F  is an accumulation result of the portion of the digital code DC I . The digital code DC F  can be implemented as an N-bit digital signal, where N is a positive integer. 
     The oscillator circuit  150 , coupled to the sampling circuit  110 , the PD  120 , the processing circuit  130  and the processing circuit  140 , is configured to generate the output clock CK OUT  according to the detection result DR, the digital code DC I  and the digital code DC F . A phase of the output clock CK OUT  is adjusted at least according to the detection result DR, and a frequency of the output clock CK OUT  is adjusted according to the digital code DC′ and the digital code DC F . In some embodiments where the detection result DR is implemented using the digital code DC P , the oscillator circuit  150  can be implemented as a digitally-controlled oscillator (DCO) circuit. Additionally, or alternatively, as the rate of change of the code value of the digital code DC F  can be slower than that of the code value of the digital code DC I , the digital code DC F  can be regarded as a control input for coarse tuning of the frequency of the output clock CK OUT , and the digital code DC I  can be regarded as a control input for fine tuning of the frequency of the output clock CK OUT . 
     In the present embodiment, the oscillator circuit  150  includes, but is not limited to, a control circuit  160  and an oscillator  170 . The control circuit  160 , coupled to the PD  120 , the processing circuit  130  and the processing circuit  140 , may utilize a triple-path structure to control operation of the oscillator  170 . For example, the control circuit  160  is configured to generate a control signal CS P  at least according to the detection result DR, generate a control signal CS I  at least according to the digital code DC′, and generate a control signal CS F  according to the digital code DC F . The control signal CS P , generated from one path in the control circuit  160 , is sent to the oscillator  170  to adjust the phase of the output clock CK OUT . The control signals CS I  and CS F , generated from other two paths in the control circuit  160 , are sent to the oscillator  170  to adjust the frequency of the output clock CK OUT . An increase in a signal level of the control signal CS F , generated when the code value of the digital code DC F  is incremented by a predetermined amount such as a binary 1, is greater than an increase in a signal level in the control signal CS I , generated when the code value of the digital code DC I  is incremented by the predetermined amount. As a result, the control signal CS F  can be used for coarse tuning of the frequency of the output clock CK OUT , and the control signal CS I  can be used for fine tuning of the frequency of the output clock CK OUT . 
     The oscillator  170 , coupled to the sampling circuit  110  and the control circuit  160 , is configured to generate the output clock CK OUT  according to the control signal CS P , the control signal CS I  and the control signal CS F . The oscillator  170  may be implemented using a current-controlled oscillator (CCO), a voltage-controlled oscillator (VCO) or a hybrid current/voltage-controlled oscillator. 
     In operation, the sampling circuit  110  may oversample the input data D IN  according to the output clock CK OUT , and accordingly generate the data signal DS and the edge signal ES. The PD  120  may output the up signal UP and the down signal DN according to whether the output clock CK OUT  lags or leads the input data D IN . The control circuit  160  may utilize the up signal UP and the down signal DN to generate the control signal CS P  to thereby adjust the phase of the output clock CK OUT . A circuit path associated with generation of the control signal CS P  can be referred to as a proportional path (denoted as P-path). The processing circuit  130  may process the sampling result SR to accumulate the phase error information carried by the data signal DS and the edge signal ES, thereby producing the digital code DC I  which indicates the information on the frequency error between the input data D IN  and the output clock CK OUT . The control circuit  160  may utilize the digital code DC I  to generate the control signal CS I  to thereby adjust the frequency of the output clock CK OUT . A circuit path associated with generation of the control signal CS I  can be referred to as an integral path (denoted as I-path). In addition, the processing circuit  140  may accumulate at least one MSB of the digital code DC I  to produce the digital code DC F . The control circuit  160  may utilize the digital code DC F  to generate the control signal CS F  to thereby adjust the frequency of the output clock CK OUT . A circuit path associated with generation of the control signal CS F  is denoted as F-path. 
     As the code value of the digital code DC F  changes more slowly than the code value of the digital code DC I , the control circuit  160  may utilize the digital code DC F  to coarse tune the frequency of the output clock CK OUT , and utilize the digital code DC I  to fine tune the frequency of the output clock CK OUT . For example, when the code value of the digital code DC F  is unchanged and the code value of the digital code DC I  increases, the signal level of the control signal CS I  increases. The frequency of the output clock CK OUT  can be adjusted using a fine step size. When the code value of the digital code DC F  increases, the signal level of the control signal CS F  increases. The frequency of the output clock CK OUT  can be adjusted using a coarse step size. 
     It is worth noting that, with the use of the proposed CDR scheme, the gain associated with the integral path of the control circuit  160  can be kept small to provide high frequency resolution. In addition, the coarse tuning implemented using the processing circuit  140  can provide a large frequency step size and therefore allow the oscillator circuit  150  to have a wide tuning range. Moreover, the control circuit  160  may generate the control signal CS P  according to the detection result DR and the digital code DC F . By adjusting respective signal levels of the control signals CS P , CS I  and CS F  according to the digital code DC F , the control circuit  160  can allow each of the control signal CS P  generated from the P-path and the control signal CS I  generated from the I-path to track the control signal CS F  generated from the F-path, thereby achieving bandwidth tracking at various frequency corners. 
     In some embodiments, before the CDR circuit  100  starts to track the input data D IN , the processing circuit  140  can be configured to compare a frequency of a reference clock CK R  with the frequency of the output clock CK OUT , and accordingly set the code value of the digital code DC F  to a predetermined value. When the CDR circuit  100  starts to track the input data D IN , the processing circuit  140  can accumulate the portion of the digital code DC I  to update the code value of the digital code DC F . With the use of the predetermined value, the CDR circuit  100  can shorten a period of time it takes to lock the output clock CK OUT . 
     To facilitate understanding of the present disclosure, some embodiments are given as follows for further description of the proposed CDR scheme. Those skilled in the art should appreciate that other embodiments employing the architecture shown in  FIG.  1    are also within the contemplated scope of the present disclosure. 
       FIG.  2    illustrates an implementation of the CDR circuit  100  shown in  FIG.  1    in accordance with some embodiments of the present disclosure. The CDR circuit  200  includes, but is not limited to, the sampling circuit  110  and the PD  120  shown in  FIG.  1   , a plurality of processing circuits  230  and  240 , and an oscillator circuit  250 . The processing circuits  230  and  240  can represent embodiments of the processing circuits  130  and  140  shown in  FIG.  1   , respectively. The oscillator circuit  250  can represent an embodiment of the oscillator circuit  150  shown in  FIG.  1   . 
     The processing circuit  230  includes, but is not limited to, a deserializer  232  and an accumulator  236 . The deserializer  232 , coupled to the sampling circuit  110 , is configured to process the data signal DS and the edge signal ES to generate a deserialization result DES. The deserialization result DES can indicate the phase error information on the phase error between the input data D IN  and the output clock CK OUT . The accumulator  236 , coupled to the deserializer  232 , is configured to accumulate the phase error information indicated by the deserialization result DES to generate the digital code DC I . 
     The processing circuit  240  includes, but is not limited to, a calibration circuit  242  and an accumulator  246 . The calibration circuit  242 , coupled to the oscillator circuit  250 , is configured to compare the frequency of the reference clock CK R  with the frequency of the output clock CK OUT  to generate a calibration result CR. The accumulator  246 , coupled to the calibration circuit  242 , is configured to set the code value of the digital code DC F  according to the calibration result CR, and accumulate a portion of the digital code DC I  to update the code value of the digital code DC F  after the code value of the digital code DC F  is set according to the calibration result CR. 
     The oscillator circuit  250  includes, but is not limited to, a control circuit  260  and a current-controlled oscillator (CCO)  270 . The control circuit  260  is configured to generate a control current I I  at least according to the digital code DC I , generate a control current I F  according to the digital code DC F , and generate a control current I P  at least according to the digital code DC P  (i.e. the detection result DR outputted from the PD  120 ). The control currents I P , I I  and I F  can represent embodiments of the control signals CS P , CS I  and CS F  shown in  FIG.  1   , respectively. An increment in the control current I F , generated when the code value of the digital code DC F  is incremented by a predetermined amount such as binary 1, is greater than an increment in the control current I I , generated when the code value of the digital code DC I  is incremented by the predetermined amount. As a result, the control current I F  can be used for coarse tuning of the frequency of the output clock CK OUT , and the control current I I  can be used for fine tuning of the frequency of the output clock CK OUT . 
     In the present embodiment, the control circuit  260  can be configured to generate the control current I I  according to the digital code DC I  and the digital code DC F , and generate the control current I P  according to the digital code DC P  and the digital code DC F . As a result, the control circuit  260  can allow each of the control current I P  and the control current I I  to track the control current I F , thus achieving bandwidth tracking and ensure good loop stability. For example, the control circuit  260  may include a plurality of conversion circuits  262 ,  264  and  266 , which can be used to implement the P-path, the I-path and the F-path shown in  FIG.  1   , respectively. The control circuit  260  may allow at least one of the control current I I  generated from the conversion circuit  262  and the control current I P  generated from the conversion circuit  266  to track the control current I F  generated from the conversion circuit  264 . 
     The conversion circuit  262 , coupled to the processing circuit  230 , is configured to generate the control current I I  according to the digital code DC I  and a reference current I REFI . For example, the conversion circuit  262  is configured to convert the digital code DC I  to the control current I I  according to the reference current I REFI . A current level of the control current I I  changes in response to a current level of the reference current I REFI  when the code value of the digital code DC I  is kept unchanged. 
     The conversion circuit  264 , coupled to the processing circuit  240  and the conversion circuit  262 , is configured to generate the control current I F  and the reference current I REFI  according to the digital code DC F . For example, the conversion circuit  264  is configured to convert the digital code DC F , i.e. an accumulation result of a portion of the digital code DC I , to the control current I F  and the reference current I REFI . When the code value of the digital code DC F  increases, each of the control current I F  and the reference current I REFI  may increase. In the present embodiment, the conversion circuit  264  is further configured to convert the digital code DC F  to a reference current I REFP . Respective current levels of the reference currents I REFI  and I REFP  can change in response to a current level of the control current I F  when the code value of the digital code DC F  is kept unchanged. In other words, each of the reference currents I REFI  and I REFP , coming from the conversion circuit  264 , can track the control current I F . For example, when the code value of the digital code DC F  increases, each of the reference current I REFI  and the reference current I REFP  may increase. 
     The conversion circuit  266 , coupled to the PD  120  and the conversion circuit  264 , is configured to convert the digital code DC P  and the reference current I REFP  to the control current I P . For example, the conversion circuit  266  can be configured to generate the control current I P  by selectively steering the reference current I REFP  from the conversion circuit  264  to the CCO  270  according to the digital code DC P . A current level of the control current I P  changes in response to a current level of the reference current I REFP  when the code value of the digital code DC P  is kept unchanged. 
     The CCO  270 , coupled to the conversions circuit  262 ,  264  and  266 , is configured to generate the output clock CK OUT  according to the control currents I P , I I  and I F . In the present embodiment, the frequency of the output clock CK OUT  is controlled by the control current I I  and the control current I F , and the phase of the output clock CK OUT  is controlled by the control current I P . 
     In operation, before the CDR circuit  200  starts to track the input data D IN , the calibration circuit  242  may be activated to generate the calibration result CR by comparing the frequency of the reference clock CK R  with the frequency of the output clock CK OUT . The accumulator  246  may set the code value of the digital code DC F  to a predetermined value according to the calibration result CR. After the CDR circuit  200  starts to track the input data D IN , the calibration circuit  242  may be deactivated. The sampling circuit  110  may oversample the input data D IN  according to the output clock CK OUT , and accordingly generate the data signal DS and the edge signal ES. 
     With regard to frequency tracking loops, the deserializer  232  may convert the data signal DS and the edge signal ES in serial form into the deserialization result DES which is in parallel form. The accumulator  236  may accumulate the phase error information indicated by the deserialization result DES to produce the digital code DC I , which indicates the information on the frequency error between the input data D IN  and the output clock CK OUT . The accumulator  246  may accumulate the portion of the digital code DC I  from the predetermined value to update the code value of the digital code DC F . 
     In addition, the conversion circuit  264  may generate the control current I F  and the reference current I REFI  according to the digital code DC F . The conversion circuit  262  may convert the digital code DC I  to the control current I I  according to the reference current I REFI  provided by the conversion circuit  264 . When the code value of the digital code DC F  increases, the control current I F  increases. When a code value of another portion of the digital code DC I  increases, the control current I I  increases. For example, the accumulator  246  updates the digital code DC F  by accumulating at least one MSB of the digital code DC I  from the predetermined value. The another portion of the digital code DC I  may be at least one least significant bit (LSB) of the digital code DC I  which is not accumulated by the accumulation  246 . When the code value of the digital code DC F  is unchanged, and the code value of the another portion of the digital code DC I  increases, it means that the control circuit  260  fine tunes the frequency of the output clock CK OUT . The control current I I  increases in response to the code value of the digital code DC I . The frequency of the output clock CK OUT  can be adjusted using a fine step size. When the code value of the digital code DC F  changes or increases, it means that the control circuit  260  coarse tunes the frequency of the output clock CK OUT . The control current I F  may increase accordingly. The frequency of the output clock CK OUT  can be adjusted using a coarse step size. 
     With regard to a phase tracking loop, the PD  120  may output the up signal UP and the down signal DN according to the data signal DS and the edge signal ES. The conversion circuit  266  may convert the digital code DC P  and the reference current I REFP , provided by the conversion circuit  264 , to the control current I P . For example, when the digital code DC P  has a predetermined code value, the conversion circuit  266  is configured to increase the control current I P  by steering the reference current I REFP  from the conversion circuit  264  to the CCO  270 . When the digital code DC P  has another predetermined code value, the conversion circuit  266  is configured to decrease the control current I P  by stopping steering the reference current I REFP  to the CCO  270 . The phase of the output clock CK OUT  can be adjusted according to the control current I P . 
     The above circuit structures are provided for illustrative purposes, and are not intended to limit the scope of the present disclosure. In some embodiments, the calibration circuit  242  may be optional. In some embodiments, the oscillator circuit  250  may be implemented using a VCO circuit or a hybrid current/voltage-controlled oscillator circuit. Such modifications and alternatives also fall within the contemplated scope of the present disclosure. 
       FIG.  3    illustrates an implementation of the control circuit  260  shown in  FIG.  2    in accordance with some embodiments of the present disclosure. The control circuit  360  includes a plurality of conversion circuits  362 ,  364  and  366 , which represent embodiments of the conversion circuits  262 ,  264  and  266  shown in  FIG.  2   , respectively. In the present embodiment, the conversion circuit  362  includes, but is not limited to, a current mirror circuit  372 , a digital-to-analog converter (DAC)  382  and a voltage-to-current converter  392 . The current mirror circuit  372  can be configured to mirror the reference current I REFI  to generate an auxiliary current I AUXI . By way of example but not limitation, the current mirror circuit  372  may include a plurality of transistors M 31  and M 32 . The DAC  382 , coupled to the current mirror circuit  372 , can be configured to convert the digital code DC I  to an auxiliary voltage V AUXI  according to the auxiliary current I AUXI . The voltage-to-current converter  392 , coupled to the DAC  382 , can be configured to convert the auxiliary voltage V AUXI  to the control current I I . By way of example but not limitation, the voltage-to-current converter  392  may include an amplifier A 1 , a resistor R 1  and a plurality of transistors M 33  and M 34 . 
     The conversion circuit  364  includes, but is not limited to, a DAC  374  and a voltage-to-current converter  384 . The DAC  374  can be configured to convert the digital code DC F  to an auxiliary voltage V AUXF . The voltage-to-current converter  384 , coupled to the DAC  374 , can be configured to convert the auxiliary voltage V AUXF  to the reference current I REFI , the reference current I REFP  and the control current I F . By way of example but not limitation, the voltage-to-current converter  384  may include an amplifier A 2 , a resistor R 2  and a plurality of transistors M 35 -M 39 . 
     The conversion circuit  366  includes, but is not limited to, a plurality of switches SW U  and SW D . The switches SW U  and SW D  can be controlled by the up signal UP and the down signal DN provided by the PD  120  shown in  FIG.  2   , respectively. As those skilled in the art can appreciate the generation of the control currents I P , I I  and I F  after reading the above paragraphs directed to  FIG.  1    and  FIG.  2   , further description is omitted here for brevity. 
       FIG.  4    illustrates an implementation of the DAC  382  shown in  FIG.  3    in accordance with some embodiments of the present disclosure. The DAC  382  is configured to convert the digital code DC I , implemented as an M-bit digital signal, to the auxiliary voltage V AUXI  according to the auxiliary current I AUXI . In the present embodiment, the DAC  382  includes a plurality of transistors M 4   0 -M 4   M+1 , a plurality of switches SW 0 -SW M , and a resistor R 4 . The switches SW 0 -SW M  are controlled by M bits B 0 -B M  of the digital code DC I . As a result, a voltage level of the auxiliary voltage V AUXI  can be determined according to the number of switches which are turned on. In some embodiments, the DAC  374  shown in  FIG.  3    may employ a circuit structure similar to that of the DAC  382  shown in  FIG.  4   . 
     It is worth noting that the above circuit implementations shown in  FIG.  3    and  FIG.  4    are provided for illustrative purposes, and are not intended to limit the scope of the present disclosure. As long as a control circuit employs a triple-path structure, which accumulates a digital code for fine frequency tuning and accumulates a portion of the digital code for coarse frequency tuning, to control operation of an oscillator, associated modifications and alternatives fall within the contemplated scope of the present disclosure. Additionally, or alternatively, as long as a control circuit employs a triple-path structure, which allows respective control signals provided by a proportional path and an integral path to track a control signal provided by another path used for coarse frequency tuning, to control operation of an oscillator, associated modifications and alternatives fall within the contemplated scope of the present disclosure. 
       FIG.  5    is a flow chart of an exemplary method for clock and data recovery (CDR) in accordance with some embodiments of the present disclosure. The method  500  is described with reference to the CDR circuit  200  shown in  FIG.  2    for illustrative purposes. Those skilled in the art should appreciate that the method  500  can be employed in the CDR circuit  100  shown in  FIG.  1    or other CDR circuits having triple-path structure without departing from the scope of the present disclosure. Additionally, in some embodiments, other operations in the method  500  can be performed. In some embodiments, operations of the method  500  can be performed in a different order and/or vary. In some other embodiments, one or more operations of the method  500  may be optional. 
     At operation  502 , a data signal and an edge signal are generated by sampling input data according to an output clock outputted from an oscillator. The data signal and the edge signal carry phase error information on a phase error between the input data and the output clock. For example, the sampling circuit  110  can generate the data signal DS and edge signal ES by sampling the input data D IN  according to the output clock CK OUT  outputted from the CCO  270 . The data signal DS and the edge signal ES can carry phase error information on a phase error between the input data D IN  and the output clock CK OUT . 
     At operation  504 , a detection result is generated according to the data signal and the edge signal. The detection result indicates a phase relationship between the input data and the output clock. For example, the PD  120  can generate the detection result DR according to the data signal DS and edge signal ES, wherein the detection result DR, including the up signal UP and the down signal DN, can indicate a phase relationship between the input data D IN  and the output clock CK OUT . 
     At operation  506 , the phase error information, carried by the data signal and the edge signal, is accumulated to generate a first digital code. For example, the deserializer  232  can process the data signal DS and the edge signal ES in serial form to generate the deserialization result DES in parallel form, wherein the deserialization result DES can indicate the phase error information on the phase error between the input data D IN  and the output clock CK OUT . The accumulator  236  can accumulate the phase error information indicated by the deserialization result DES to generate the digital code DC I . 
     At operation  508 , at least one MSB of the first digital code is accumulated to generate a second digital code. For example, the accumulator  246  can accumulate one or more MSBs of the digital code DC I  to generate the digital code DC F . 
     At operation  510 , a phase of the output clock is adjusted according to the detection result and the second digital code. For example, the control circuit  260  can adjust the phase of the output clock CK OUT  according to the detection result DR and the digital code DC F . 
     At operation  512 , a frequency of the output clock is adjusted according to the first digital code and the second digital code. For example, the control circuit  260  can adjust the frequency of the output clock CK OUT  according to the digital code DC I  and the digital code DC F . It is worth noting that as the phase and the frequency of the output clock CK OUT  can be adjusted according to the digital code DC F , the CDR circuit  200  can achieve bandwidth tracking and provide good loop stability. 
     In some embodiment, at operation  508 , an initial value of the second digital code can be determined according to a reference clock and the output clock, which can shorten a period of time it takes to lock the output clock. For example, before the CDR circuit  200  starts to track the input data D IN , the calibration circuit  242  may compare the frequency of the reference clock CK R  with the frequency of the output clock CK OUT  to generate the calibration result CR. Next, the accumulator  246  may set the code value of the digital code DC F  according to the calibration result CR. After the code value of the digital code DC F  is set according to the calibration result CR, the accumulator  246  may update the code value of the digital code DC F  by accumulating the one or more MSB s of the digital code DC I . 
     As those skilled in the art can appreciate operation of the method  500  after reading the above paragraphs directed to  FIG.  1    through  FIG.  4   , further description is omitted here for brevity. 
     With the use of the proposed CDR scheme, an oscillator circuit in a CDR circuit can not only have a wide tuning range but also high resolution despite temperature variations. In addition, the proposed CDR scheme can achieve bandwidth tracking at various frequency corners, thereby ensuring good loop stability. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.