Patent Publication Number: US-2022223593-A1

Title: Semiconductor device structure and methods of forming the same

Description:
BACKGROUND 
     The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of processing and manufacturing ICs. 
     Therefore, there is a need to improve processing and manufacturing ICs. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS. 1-18  are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. 
         FIGS. 19 and 20  are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of  FIG. 18 , in accordance with some embodiments. 
         FIG. 21  is a top view of the semiconductor device structure shown in  FIG. 20 , in accordance with some embodiments. 
         FIGS. 22A-22C  are cross-sectional side views of one of various stages of manufacturing the semiconductor device structure taken along lines A-A, B-B, C-C of  FIG. 21 , respectively, in accordance with some embodiments. 
         FIGS. 23A-30A  are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line A-A of  FIG. 21 , in accordance with some embodiments. 
         FIGS. 23B-30B  are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line B-B of  FIG. 21 , in accordance with some embodiments. 
         FIGS. 23C-30C  are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line C-C of  FIG. 21 , in accordance with some embodiments. 
         FIGS. 23D-30D  are cross-sectional side views of various stages of manufacturing the semiconductor device structure taken along line D-D of  FIG. 21 , in accordance with some embodiments. 
         FIG. 31  is a cross-sectional side view of one of various stages of manufacturing the semiconductor device structure taken along line A-A of  FIG. 21 , in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “over,” “on,” “top,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
       FIGS. 1-31  show exemplary sequential processes for manufacturing a semiconductor device structure  100 , in accordance with some embodiments. It is understood that additional operations can be provided before, during, and after processes shown by  FIGS. 1-31  and some of the operations described below can be replaced or eliminated, for additional embodiments of the method. The order of the operations/processes may be interchangeable. 
       FIGS. 1-18  are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments. As shown in  FIG. 1 , a stack of semiconductor layers  104  is formed over a substrate  101 . The substrate  101  may be a semiconductor substrate. In some embodiments, the substrate  101  includes a single crystalline semiconductor layer on at least the surface of the substrate  101 . The substrate  101  may include a single crystalline semiconductor material such as, but not limited to silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium arsenic antimonide (GaAsSb) and indium phosphide (InP). In this embodiment, the substrate  101  is made of Si. In some embodiments, the substrate  101  is a silicon-on-insulator (SOI) substrate, which includes an insulating layer (not shown) disposed between two silicon layers. In one aspect, the insulating layer is an oxide. 
     The substrate  101  may include one or more buffer layers (not shown) on the surface of the substrate  101 . The buffer layers can serve to gradually change the lattice constant from that of the substrate to that of the source/drain (S/D) regions to be grown on the substrate  101 . The buffer layers may be formed from epitaxially grown single crystalline semiconductor materials such as, but not limited to Si, Ge, germanium tin (GeSn), SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, GaN, and InP. In one embodiment, the substrate  101  includes SiGe buffer layers epitaxially grown on the silicon substrate  101 . The germanium concentration of the SiGe buffer layers may increase from 30 atomic percent germanium for the bottom-most buffer layer to 70 atomic percent germanium for the top-most buffer layer. 
     The substrate  101  may include various regions that have been suitably doped with impurities (e.g., p-type or n-type impurities). The dopants are, for example boron for an n-type fin field effect transistor (FinFET) and phosphorus for a p-type FinFET. 
     The stack of semiconductor layers  104  includes first semiconductor layers  106  and second semiconductor layers  108 . The first semiconductor layers  106  and the second semiconductor layers  108  are made of semiconductor materials having different etch selectivity and/or oxidation rates. For example, the first semiconductor layers  106  are made of Si and the second semiconductor layers  108  are made of SiGe. In some embodiments, the stack of semiconductor layers  104  includes alternating first and second semiconductor layers  106 ,  108 . The first semiconductor layers  106  or portions thereof may form nanosheet channel(s) of the semiconductor device structure  100  at a later stage. The semiconductor device structure  100  may include a nanosheet transistor. The term nanosheet is used herein to designate any material portion with nanoscale, or even microscale dimensions, and having an elongate shape, regardless of the cross-sectional shape of this portion. Thus, this term designates both circular and substantially circular cross-section elongate material portions, and beam or bar-shaped material portions including for example a cylindrical in shape or substantially rectangular cross-section. The nanosheet channel(s) of the semiconductor device structure  100  may be surrounded by the gate electrode layer. The nanosheet transistors may be referred to as nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistors having the gate electrode layer surrounding the channels. The use of the first semiconductor layers  106  to define a channel or channels of the semiconductor device structure  100  is further discussed below. In some embodiments, the first and second semiconductor layers  106 ,  108  are replaced with a single semiconductor material connected to the substrate  101 , and the device is a FinFET. 
     It is noted that 3 layers of the first semiconductor layers  106  and 3 layers of the second semiconductor layers  108  are alternately arranged as illustrated in  FIG. 1 , which is for illustrative purposes and not intended to be limiting beyond what is specifically recited in the claims. It can be appreciated that any number of first and second semiconductor layers  106 ,  108  can be formed in the stack of semiconductor layers  104 ; the number of layers depending on the predetermined number of channels for the semiconductor device structure  100 . In some embodiments, the number of first semiconductor layers  106 , which is the number of channels, is between 3 and 8. 
     As described in more detail below, the first semiconductor layers  106  may serve as channels for the semiconductor device structure  100  and the thickness is chosen based on device performance considerations. In some embodiments, each first semiconductor layer  106  has a thickness ranging from about 6 nanometers (nm) to about 12 nm. The second semiconductor layers  108  may eventually be removed and serve to define a vertical distance between adjacent channels for the semiconductor device structure  100  and the thickness is chosen based on device performance considerations. In some embodiments, each second semiconductor layer  108  has a thickness ranging from about 2 nm to about 6 nm. 
     The first and second semiconductor layers  106 ,  108  are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the stack of semiconductor layers  104  may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and/or other suitable epitaxial growth processes. 
     A mask structure  110  is formed over the stack of semiconductor layers  104 . The mask structure  110  may include an oxygen-containing layer  112  and a nitrogen-containing layer  114 . The oxygen-containing layer  112  may be a pad oxide layer, such as a SiO 2  layer. The nitrogen-containing layer  114  may be a pad nitride layer, such as Si 3 N 4 . The mask structure  110  may be formed by any suitable deposition process, such as chemical vapor deposition (CVD) process. 
       FIG. 2  is a perspective view of one of the various stages of manufacturing the semiconductor device structure  100 , in accordance with some embodiments. As shown in  FIG. 2 , fins  202   a  and  202   b  are formed. In some embodiments, each fin  202   a ,  202   b  includes a substrate portion  102   a ,  102   b  formed from the substrate  101 , a portion of the stack of semiconductor layers  104 , and a portion of the mask structure  110 . The fins  202   a ,  202   b  may be fabricated using suitable processes including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, may then be used to pattern the fins  202   a ,  202   b  by etching the stack of semiconductor layers  104  and the substrate  101 . The etch process can include dry etch, wet etch, reactive ion etch (RIE), and/or other suitable processes. As shown in  FIG. 2 , two fins are formed, but the number of the fins is not limited to two. Three or more fins are arranged along the X direction in some embodiments, as shown in  FIG. 20 . 
     In some embodiments, the fins  202   a ,  202   b  may be fabricated using suitable processes including photolithography and etch processes. The photolithography process may include forming a photoresist layer (not shown) over the mask structure  110 , exposing the resist to a pattern, performing post-exposure bake processes, and developing the resist to form a patterned resist. In some embodiments, patterning the resist to form the patterned resist may be performed using an electron beam (e-beam) lithography process. The patterned resist may then be used to protect regions of the substrate  101 , and layers formed thereupon, while an etch process forms trenches  204  in unprotected regions through the mask structure  110 , the stack of semiconductor layers  104 , and into the substrate  101 , thereby leaving the extending fins  202   a ,  202   b . The trenches  204  may be etched using a dry etch (e.g., RIE), a wet etch, and/or combination thereof. 
       FIG. 3  is a perspective view of one of the various stages of manufacturing the semiconductor device structure  100 , in accordance with some embodiments. As shown in  FIG. 3 , a liner  304  is formed over the substrate  101  and the fins  202   a ,  202   b . In some embodiments, an optional liner  302  may be formed on the substrate  101  and fins  202   a ,  202   b , and the liner  304  is formed on the optional liner  302 . The liner  304  may be made of a semiconductor material, such as Si. In some embodiments, the liner  304  is made of the same material as the substrate  101 . The optional liner  302  may be made of an oxygen-containing material, such as an oxide. The liner  304  may be a conformal layer and may be formed by a conformal process, such as an atomic layer deposition (ALD) process. The term “conformal” may be used herein for ease of description upon a layer having substantial same thickness over various regions. The optional liner  302  may be a conformal layer and may be formed by a conformal process, such as an ALD process. 
       FIG. 4  is a perspective view of one of the various stages of manufacturing the semiconductor device structure  100 , in accordance with some embodiments. As shown in  FIG. 4 , an insulating material  402  is formed on the substrate  101 . The insulating material  402  fills the trench  204  ( FIG. 2 ). The insulating material  402  may be first formed over the substrate  101  so that the fins  202   a ,  202   b  are embedded in the insulating material  402 . Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and/or an etch-back process, is performed such that the tops of the fins  202   a ,  202   b  (e.g., the liner  304 ) are exposed from the insulating material  402 , as shown in  FIG. 4 . The insulating material  402  may be made of an oxygen-containing material, such as silicon oxide or fluorine-doped silicate glass (FSG); a nitrogen-containing material, such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-K dielectric material; or any suitable dielectric material. The insulating material  402  may be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma enhanced CVD (PECVD) or flowable CVD (FCVD). 
     Next, as shown in  FIG. 5 , the insulating material  402  may be recessed by removing a portion of the insulating material  402  located between adjacent fins  202   a ,  202   b  to form trenches  502 . The trenches  502  may be formed by any suitable removal process, such as dry etch or wet etch that selectively removes the insulating material  402  but not the semiconductor material of the liner  304 . The recessed insulating material  402  may be the shallow trench isolation (STI). The insulating material  402  includes a top surface  504  that may be level with or below a surface of the second semiconductor layers  108  in contact with the substrate portions  102   a ,  102   b  of the substrate  101 . 
     Next, as shown in  FIG. 6 , a cladding layer  602  is formed on the exposed surface of the liner  304  ( FIG. 5 ), and the optional liner  302  is omitted for clarity. The liner  304  may be diffused into the cladding layer  602  during the formation of the cladding layer  602 . Thus, in some embodiments where the optional liner  302  does not exist, the cladding layer  602  is in contact with the stack of semiconductor layers  104 , as shown in  FIG. 6 . In some embodiments, the cladding layer  602  includes a semiconductor material. The cladding layer  602  grows on semiconductor materials but not on dielectric materials. For example, the cladding layer  602  includes SiGe and is grown on the Si of the liner  304  but not on the dielectric material of the insulating material  402 . In some embodiments, the cladding layer  602  may be formed by first forming a semiconductor layer on the liner  304  and the insulating material  402 , and followed by an etch process to remove portions of the semiconductor layer formed on the insulating material  402 . The etch process may remove some of the semiconductor layer formed on the top of the fins  202   a ,  202   b , and the cladding layer  602  formed on the top of the fins  202   a ,  202   b  may have a curved profile instead of a flat profile. In some embodiments, the cladding layer  602  and the second semiconductor layers  108  include the same material having the same etch selectivity. For example, the cladding layer  602  and the second semiconductor layers  108  include SiGe. The cladding layer  602  and the second semiconductor layer  108  may be removed subsequently to create space for the gate electrode layer. 
     Next, as shown in  FIG. 7 , a liner  702  is formed on the cladding layer  602  and the top surface  504  of the insulating material  402 . The liner  702  may include a low-K dielectric material (e.g., a material having a K value lower than 7), such as SiO 2 , SiN, SiCN, SiOC, or SiOCN. The liner  702  may be formed by a conformal process, such as an ALD process. The liner  702  may have a thickness ranging from about 1 nm to about 6 nm. The liner  702  may function as a shell to protect a flowable oxide material to be formed in the trenches  502  ( FIG. 5 ) during subsequent removal of the cladding layer  602 . Thus, if the thickness of the liner  702  is less than about 1 nm, the flowable oxide material may not be sufficiently protected. On the other hand, if the thickness of the liner  702  is greater than about 6 nm, the trenches  502  ( FIG. 5 ) may be filled. 
     A dielectric material  704  is formed in the trenches  502  ( FIG. 5 ) and on the liner  702 , as shown in  FIG. 7 . The dielectric material  704  may be an oxygen-containing material, such as an oxide, formed by FCVD. The oxygen-containing material may have a K value less than about 7, for example less than about 3. The width of the dielectric material  704  along the X direction may be defined by the width of the trench  502  and the thickness of the liner  702 . In some embodiments, the width of the dielectric material  704  ranges from about 8 nm to about 30 nm. A planarization process, such as a CMP process, may be performed to remove portions of the liner  702  and the dielectric material  704  formed over the fins  202   a ,  202   b . The portion of the cladding layer  602  disposed on the nitrogen-containing layer  114  may be exposed after the planarization process. 
     Next, as shown in  FIG. 8 , the liner  702  and the dielectric material  704  are recessed to the level of the topmost first semiconductor layer  106 . For example, in some embodiments, after the recess process, the dielectric material  704  may include a top surface  802  that is substantially level with a top surface  804  of the topmost first semiconductor layer  106 . The top surface  804  of the topmost first semiconductor layer  106  may be in contact with the mask structure  110 , such as in contact with the oxygen-containing layer  112 . The liner  702  may be recessed to the same level as the dielectric material  704 . The recess of the liners  702  and the dielectric material  704  may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a first etch process may be performed to recess the dielectric material  704  followed by a second etch process to recess the liner  702 . The etch processes may be selective etch processes that do not remove the semiconductor material of the cladding layer  602 . As a result of the recess process, trenches  806  are formed between the fins  202   a ,  202   b.    
     A dielectric material  904  is formed in the trenches  806  ( FIG. 8 ) and on the dielectric material  704 , the liner  702 , as shown in  FIG. 9 . The dielectric material  904  may include SiO, SiN, SiC, SiCN, SiON, SiOCN, AlO, AlN, AlON, ZrO, ZrN, ZrAlO, HfO, or other suitable dielectric material. The dielectric material  904  may be formed by any suitable process, such as a CVD, PECVD, FCVD, or ALD process. The dielectric material  904  may have a thickness ranging from about 5 nm to about 20 nm. The dielectric material  904  may fill the trenches  806  ( FIG. 8 ). Thus, if the thickness of the dielectric material  904  is less than about 5 nm, the trenches  806  may not be filled. On the other hand, if the thickness of the dielectric material  904  is greater than about 20 nm, the manufacturing cost is increased without significant advantage. 
     A planarization process is performed to expose the nitrogen-containing layer  114  of the mask structure  110 , as shown in  FIG. 9 . The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the dielectric material  904  and the cladding layer  602  disposed over the mask structure  110 . The liner  702 , the dielectric material  704 , and the dielectric material  904  together may be referred to as a dielectric feature  906 . The dielectric feature  906  includes a bottom portion  908  having a shell, which is the liner  702 , and a core, which is the dielectric material  704 . The dielectric feature further includes a top portion, which is the dielectric material  904 . The dielectric feature  906  may be a dielectric fin that separates adjacent source/drain (S/D) epitaxial features  1502  ( FIG. 15 ) and adjacent gate electrode layers  1906  ( FIG. 19 ). 
     Next, as shown in  FIG. 10 , the cladding layers  602  are recessed, and the mask structures  110  are removed. The recess of the cladding layers  602  may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. The recess process may be controlled so that the remaining cladding layers  602  are substantially at the same level as the top surface  804  of the topmost first semiconductor layer  106  in the stack of semiconductor layers  104 . The etch process may be a selective etch process that does not remove the dielectric material  904 . The removal of the mask structures  110  may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. The removal of the mask structure  110  exposes the top surfaces  804  of the topmost first semiconductor layers  106  in the stacks of semiconductor layers  104 . 
     The top portion of the dielectric feature  906  (e.g., the dielectric material  904 ) may have a height H 1  along the Z direction. The height H 1  may range from about 6 nm to about 15 nm. The dielectric material  904  may be disposed on the top surface  802  of the dielectric material  704 , and the top surface  802  may be coplanar with the top surface  804  of the topmost first semiconductor layer  106  of the stack of semiconductor layers  104 . Thus, the dielectric material  904  may extend over a plane defined by the top surface  804  by the height H 1 , in order to separate, or cut-off, adjacent gate electrode layers  1906  ( FIG. 19 ). If the height H 1  is less than about 6 nm, the gate electrode layers  1906  ( FIG. 19 ) may not be sufficiently separated, or cut-off. On the other hand, if the height H 1  is greater than about 15 nm, the manufacturing cost is increased without significant advantage. 
     Next, as shown in  FIG. 11 , one or more sacrificial gate stacks  1102  are formed on the semiconductor device structure  100 . The sacrificial gate stack  1102  may include a sacrificial gate dielectric layer  1104 , a sacrificial gate electrode layer  1106 , and a mask structure  1108 . The sacrificial gate dielectric layer  1104  may include one or more layers of dielectric material, such as SiO 2 , SiN, a high-K dielectric material, and/or other suitable dielectric material. In some embodiments, the sacrificial gate dielectric layer  1104  includes a material different than that of the dielectric material  904 . In some embodiments, the sacrificial gate dielectric layer  1104  may be deposited by a CVD process, a sub-atmospheric CVD (SACVD) process, a FCVD process, an ALD process, a PVD process, or other suitable process. The sacrificial gate electrode layer  1106  may include polycrystalline silicon (polysilicon). The mask structure  1108  may include an oxygen-containing layer  1110  and a nitrogen-containing layer  1112 . In some embodiments, the sacrificial gate electrode layer  1106  and the mask structure  1108  are formed by various processes such as layer deposition, for example, CVD (including both LPCVD and PECVD), PVD, ALD, thermal oxidation, e-beam evaporation, or other suitable deposition techniques, or combinations thereof. 
     The sacrificial gate stacks  1102  may be formed by first depositing blanket layers of the sacrificial gate dielectric layer  1104 , the sacrificial gate electrode layer  1106 , and the mask structure  1108 , followed by pattern and etch processes. For example, the pattern process includes a lithography process (e.g., photolithography or e-beam lithography) which may further include photoresist coating (e.g., spin-on coating), soft baking, mask aligning, exposure, post-exposure baking, photoresist developing, rinsing, drying (e.g., spin-drying and/or hard baking), other suitable lithography techniques, and/or combinations thereof. In some embodiments, the etch process may include dry etch (e.g., RIE), wet etch, other etch methods, and/or combinations thereof. By patterning the sacrificial gate stack  1102 , the stacks of semiconductor layers  104  of the fins  202   a ,  202   b  are partially exposed on opposite sides of the sacrificial gate stack  1102 . As shown in  FIG. 11 , two sacrificial gate stacks  1102  are formed, but the number of the sacrificial gate stacks  1102  is not limited to two. More than two sacrificial gate stacks  1102  are arranged along the Y direction in some embodiments. 
     As shown in  FIG. 12 , a spacer  1202  is formed on the sidewalls of the sacrificial gate stacks  1102 . The spacer  1202  may be formed by first depositing a conformal layer that is subsequently etched back to form sidewall spacers  1202 . For example, a spacer material layer can be disposed conformally on the exposed surfaces of the semiconductor device structure  100 . The conformal spacer material layer may be formed by an ALD process. Subsequently, anisotropic etch is performed on the spacer material layer using, for example, RIE. During the anisotropic etch process, most of the spacer material layer is removed from horizontal surfaces, such as the tops of the fins  202   a ,  202   b , the cladding layer  602 , the dielectric material  904 , leaving the spacers  1202  on the vertical surfaces, such as the sidewalls of sacrificial gate stack  1102 . The spacer  1202  may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and/or combinations thereof. In some embodiments, the spacer  1202  includes multiple layers, such as main spacer walls, liner layers, and the like. 
     Next, exposed portions of the fins  202   a ,  202   b , exposed portions of the cladding layers  602 , exposed portions of the dielectric material  904  not covered by the sacrificial gate stacks  1102  and the spacers  1202  are selectively recessed by using one or more suitable etch processes, such as dry etch, wet etch, or a combination thereof. In some embodiments, exposed portions of the stacks of semiconductor layers  104  of the fins  202   a ,  202   b  are removed, exposing portions of the substrate portions  102   a ,  102   b , respectively. As shown in  FIG. 12 , the exposed portions of the fins  202   a ,  202   b  are recessed to a level at or below the top surface  504  of the insulating material  402 . The recess processes may include an etch process that recesses the exposed portions of the fins  202   a ,  202   b  and the exposed portions of the cladding layers  602 . 
     In some embodiments, the etch process may reduce the height of the exposed top portion (e.g., the dielectric material  904 ) of the dielectric feature  906  from H 1  to H 2 , as shown in  FIG. 12 . Thus, a first portion  1204  of the dielectric material  904  under the sacrificial gate stack  1102  and the spacers  1202  has the height H 1 , while a second portion  1206  of the dielectric material  904  located between S/D epitaxial features  1502  ( FIG. 15 ) has the height H 2  less than the height H 1 . 
     At this stage, end portions of the stacks of semiconductor layers  104  under the sacrificial gate stacks  1102  and the spacers  1202  have substantially flat surfaces which may be flush with corresponding spacers  1202 . In some embodiments, the end portions of the stacks of semiconductor layers  104  under the sacrificial gate stacks  1102  and spacers  1202  are slightly horizontally etched. 
     Next, as shown in  FIG. 13 , the edge portions of each second semiconductor layer  108  and edge portions of the cladding layers  602  are removed, forming gaps  1302 . In some embodiments, the portions of the second semiconductor layers  108  and cladding layers  602  are removed by a selective wet etch process that does not remove the first semiconductor layers  106 . For example, in cases where the second semiconductor layers  108  are made of SiGe, and the first semiconductor layers  106  are made of silicon, a selective wet etch including an ammonia and hydrogen peroxide mixtures (APM) may be used. 
     Next, as show in  FIG. 14 , dielectric spacers  1402  are formed in the gaps  1302 . In some embodiments, the dielectric spacers  1402  may be made of a low-K dielectric material, such as SiON, SiCN, SiOC, SiOCN, or SiN. In some embodiments, the dielectric spacers  1402  may be formed by first forming a conformal dielectric layer using a conformal deposition process, such as ALD, followed by an anisotropic etch to remove portions of the conformal dielectric layer other than the dielectric spacers  1402 . The dielectric spacers  1402  may be protected by the first semiconductor layers  106  and the spacers  1202  during the anisotropic etch process. In some embodiments, the dielectric spacers  1402  may be flush with the spacers  1202 . 
     Next, as shown in  FIG. 15 , S/D epitaxial features  1502  are formed on the substrate portions  102   a ,  102   b  of the fins  202   a ,  202   b . The S/D epitaxial feature  1502  may include one or more layers of Si, SiP, SiC and SiCP for an n-channel FET or Si, SiGe, Ge for a p-channel FET. The S/D epitaxial features  1502  may grow both vertically and horizontally to form facets, which may correspond to crystalline planes of the material used for the substrate portions  102   a ,  102   b . The S/D epitaxial features  1502  are formed by an epitaxial growth method using CVD, ALD or MBE. The S/D epitaxial features  1502  are in contact with the first semiconductor layers  106  and dielectric spacers  1402  ( FIG. 14 ). The S/D epitaxial features  1502  may be the S/D regions. In this disclosure, a source and a drain are interchangeably used, and the structures thereof are substantially the same. 
     Next, as shown in  FIG. 16 , a contact etch stop layer (CESL)  1602  may be formed on the S/D epitaxial features  1502 , the dielectric features  906 , and adjacent the spacers  1202 . The CESL  1602  may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, the like, or a combination thereof. The CESL  1602  may be formed by CVD, PECVD, ALD, or any suitable deposition technique. In some embodiments, the CESL  1602  is a conformal layer formed by the ALD process. An interlayer dielectric (ILD) layer  1604  may be formed on the CESL  1602 . The materials for the ILD layer  1604  may include tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron doped silicon glass (BSG), and/or other suitable dielectric materials. The ILD layer  1604  may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after formation of the ILD layer  1604 , the semiconductor device structure  100  may be subject to a thermal process to anneal the ILD layer  1604 . 
     A planarization process is performed to expose the sacrificial gate electrode layer  1106 , as shown in  FIG. 16 . The planarization process may be any suitable process, such as a CMP process. The planarization process removes portions of the ILD layer  1604  and the CESL  1602  disposed on the sacrificial gate stacks  1102 . The planarization process may also remove the mask structure  1108  ( FIG. 11 ). The ILD layer  1604  may be recessed to a level below the top of the sacrificial gate electrode layer  1106 , and a nitrogen-containing layer  1606 , such as a SiCN layer, may be formed on the recessed ILD layer  1604 , as shown in  FIG. 16 . The nitrogen-containing layer  1606  may protect the ILD layer  1604  during subsequent etch processes. 
       FIG. 17  is a perspective view of one of the manufacturing stages of the semiconductor device structure  100  taken along line A-A of  FIG. 16 , in accordance with some embodiments. As shown in  FIG. 17 , the sacrificial gate electrode layer  1106  (FIG.  16 ) and the sacrificial gate dielectric layer  1104  are removed, exposing the cladding layers  602  and the stacks of semiconductor layers  104 . The sacrificial gate electrode layer  1106  may be first removed by any suitable process, such as dry etch, wet etch, or a combination thereof, followed by the removal of the sacrificial gate dielectric layer  1104 , which may be performed by any suitable process, such as dry etch, wet etch, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution can be used to selectively remove the sacrificial gate electrode layer  1106  but not the spacers  1202 , the nitrogen-containing layer  1606 , the dielectric material  904  of the dielectric features  906 , and the CESL  1602 . In some embodiments, the spacers  1202  may be recessed by the etchant used to remove the sacrificial gate electrode layer  1106  and/or the sacrificial gate dielectric layer  1104 . 
     Next, as shown in  FIG. 18 , the cladding layers  602  and the second semiconductor layers  108  are removed. The removal processes expose the dielectric spacers  1402  and the first semiconductor layers  106 . The removal process may be any suitable processes, such as dry etch, wet etch, or a combination thereof. The etch process may be a selective etch process that removes the cladding layers  602  and the second semiconductor layers  108  but not the spacers  1202 , the CESL  1602 , the nitrogen-containing layer  1606 , the dielectric material  904 , and the first semiconductor layers  106 . As a result, openings  1802  are formed, as shown in  FIG. 18 . In some embodiments, the dimension of the portion of the liner  702  in contact with sidewalls of the dielectric material  704  may be reduced, leading to the bottom portion  908  of the dielectric feature  906  having a width less than the width of the dielectric material  904  of the dielectric feature  906 . The portion of the first semiconductor layers  106  not covered by the dielectric spacers  1402  may be exposed in the openings  1802 . Each first semiconductor layer  106  may be a nanosheet channel of the nanosheet transistor. 
       FIGS. 19 and 20  are cross-sectional side views of various manufacturing stages of the semiconductor device structure  100  along line A-A of  FIG. 18 , in accordance with some embodiments. As shown in  FIG. 19 , oxygen-containing layers  1902  may be formed around the exposed surfaces of the first semiconductor layers  106  and the substrate portions  102   a ,  102   b  of the fins  202   a ,  202   b  in the openings  1802 . Gate dielectric layers  1904  are formed on the oxygen-containing layers  1902  and the dielectric features  906  in the openings  1802 , as shown in  FIG. 19 . The oxygen-containing layer  1902  may be an oxide layer, and the gate dielectric layer  1904  may include the same material as the sacrificial gate dielectric layer  1104  ( FIG. 11 ). In some embodiments, the gate dielectric layer  1904  includes a high-K dielectric material. The oxygen-containing layers  1902  and the gate dielectric layers  1904  may be formed by any suitable processes, such as ALD processes. In some embodiments, the oxygen-containing layers  1902  and the gate dielectric layers  1904  are formed by conformal processes. 
     Next, the gate electrode layers  1906  are formed in the openings  1802  and on the gate dielectric layers  1904 . The gate electrode layer  1906  is formed on the gate dielectric layer  1904  to surround a portion of each first semiconductor layer  106 . The gate electrode layer  1906  includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and/or combinations thereof. The gate electrode layers  1906  may be formed by PVD, CVD, ALD, electro-plating, or other suitable method. 
     Next, the gate electrode layers  1906  are recessed to the same level as the top surfaces  2004  of the dielectric material  904  of the dielectric feature  906 , as shown in  FIG. 20 . Additional fins  202   c ,  202   d ,  202   e  may be formed from the substrate  101 . The fins  202   a ,  202   b ,  202   c ,  202   d ,  202   e  may have different widths. For example, fins  202   a ,  202   b  each has a width greater than a width of each of the fins  202   c ,  202   d ,  202   e . A wider fin width leads to a wider channel, and different devices may have different channel widths. For example, devices with wider channels may be more suitable for high-speed applications, such as NAND devices. Devices with narrower channels may be more suitable for low-power and low-leakage applications, such as inverter devices. The distances between adjacent gate electrode layers  1906  may be different. In other words, the widths of the dielectric features  906  may be different. For example, the dielectric feature  906  disposed between the gate electrode layer  1906  over the substrate portion  102   c  and the gate electrode layer  1906  over the substrate portion  102   d  is wider than the dielectric feature  906  disposed between the gate electrode layer  1906  over the substrate portion  102   d  and the gate electrode layer  1906  over the substrate portion  102   e , as shown in  FIG. 20 . 
     The recess of the gate electrode layers  1906  may be any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, the recess process may be a selective dry etch process that does not substantially affect the nitrogen-containing layer  1606  ( FIG. 18 ), the spacer  1202  ( FIG. 18 ), and the CESL  1602  ( FIG. 18 ). As a result of the recess process, adjacent gate electrode layers  1906  are separated, or cut-off, by the dielectric feature  906 . 
       FIG. 21  is a top view of the semiconductor device structure  100  shown in  FIG. 20 , in accordance with some embodiments. As shown in  FIG. 21 , the semiconductor device structure  100  includes the plurality of fins  202   a ,  202   b ,  202   c ,  202   d ,  202   e  shown in dotted lines. The ILD layers  1604  are formed over portions of the fins  202   a ,  202   b ,  202   c ,  202   d ,  202   e . The CESL  1602  and the nitrogen-containing layer  1606  are omitted for clarity. A trench  2102  is formed over a portion of the fins  202   a ,  202   b ,  202   c ,  202   d ,  202   e  between the ILD layers  1604 . The bottom of the trench  2102  includes the gate electrode layers  1906  separated by the dielectric materials  904  of the dielectric features  906 . The spacers  1202  are omitted for clarity. 
       FIGS. 22A-22C  are cross-sectional side views of one of various stages of manufacturing the semiconductor device structure  100  taken along lines B-B, C-C, D-D of  FIG. 21 , respectively, in accordance with some embodiments.  FIGS. 22A and 22C  are cross-sectional side views of sections of the trench  2102  above the dielectric features  906 , and  FIG. 22B  is a cross-sectional side view of a section of the trench  2102  above the gate electrode layer  1906 . As shown in  FIGS. 22A, 22B, 22C , the trench  2102  may be formed between ILD layers  1604 . The ILD layer  1604  may be disposed on the CESL  1602 , and the nitrogen-containing layer  1606  may be disposed on the ILD layer  1604 . The spacers  1202  may be in contact with the CESL  1602 . As shown in  FIGS. 22A and 22C , the dielectric material  904  of the dielectric feature  906  includes the first portion  1204  and the second portion  1206 . The first portion  1204  of the dielectric material  904  of the dielectric feature  906  may be the bottom of the sections of the trench  2102  shown in  FIGS. 22A and 22C . 
     The trench  2102  includes various sections having different bottoms, such as the first portions  1204  of the dielectric features  906  as shown in  FIGS. 22A, 22C , and the gate electrode layer  1906  as shown in  FIG. 22B . In some embodiments, the surfaces  2003  of the gate electrode layer  1906  and the surfaces  2004  of the dielectric materials  904  are coplanar. 
       FIGS. 23A-23D  are cross-sectional side views of one of various stages of manufacturing the semiconductor device structure taken along lines A-A, B-B, C-C, D-D of  FIG. 21 , respectively, in accordance with some embodiments. As shown in  FIG. 23A , a seed layer  2302  is formed on the surfaces  2003  of the gate electrode layers  1906  and surfaces  2004  of the dielectric materials  904 . The seed layer  2302  is formed on the nitrogen-containing layers  1606 , adjacent the spacers  1202  and the bottom of the trench  2102 , such as the dielectric material  904  and the gate electrode layer  1906 , as shown in  FIGS. 23B, 23C, 23D . The seed layer  2302  may include a conductive material, such as TiN, TaN, W, Ru, or other suitable conductive material. The seed layer  2302  may be formed by any suitable process, such as ALD, CVD, PECVD, or PVD. Portions of the seed layer  2302  formed on horizontal surfaces, such as the nitrogen-containing layer  1606 , the dielectric material  904 , and the gate electrode layer  1906 , may be thicker than portions of the seed layer  2302  formed on vertical surfaces, such as the spacers  1202 , due to a less conformal deposition process. The seed layer  2302  is formed on both the dielectric material  904  and the gate electrode layer  1906 , and a conductive layer  2802  ( FIGS. 28A-28D ) is formed on the seed layer  2302  at a later stage. The conductive layer  2802  includes a conductive material that forms on a conductive material but not a dielectric material. Thus, without the seed layer  2302 , the conductive layer  2802  would not form over multiple gate electrode layers  1906  across the dielectric material  904 . The seed layer  2302  and the conductive layer  2802  electrically connect two or more gate electrode layers  1906 . 
     In some embodiments, the seed layer  2302  and the conductive layer  2802  may be separated into segments (e.g.,  FIG. 29A ). The separation may include first forming an opening  2902  ( FIG. 29A ) in the seed layer  2302  and the conductive layer  2802 , followed by forming a dielectric material  3002  ( FIG. 30A ) in the opening  2902 . In some embodiments, the portion of the seed layer  2302  formed on horizontal surfaces has a thickness ranging from about 1 nm to about 2 nm. If the thickness of the seed layer  2302  is less than about 1 nm, there may not be sufficient amount of the seed layer for the conductive layer  2802  to form thereon. On the other hand, if the thickness of the seed layer  2302  is greater than about 2 nm, the etch process to form the opening  2902  may damage the gate electrode layers  1906  under the seed layer  2302 . 
     Next, as shown in  FIGS. 24B, 24C, 24D , portions of the seed layer  2302  disposed adjacent the spacers  1202  are removed. The removal may be performed by any suitable process, such as a wet etch. The wet etch removes the portions of the seed layer  2302  disposed on vertical surfaces to expose the spacers  1202 . The portions of the seed layer  2302  disposed on horizontal surfaces are not completely removed, because the portions of the seed layer  2302  disposed on vertical surfaces are thinner than the portions of the seed layer  2302  disposed on horizontal surfaces. 
     Next, a mask  2502  is formed in the trench  2102  and over the nitrogen-containing layers  1606 , as shown in  FIGS. 25A-25D . The mask  2502  may include an oxygen-containing material and/or a nitrogen-containing material. In some embodiments, the mask  2502  is a photoresist. Portions of the mask  2502  disposed on the seed layer  2302  over the nitrogen-containing layers  1606  may be removed, as shown in  FIGS. 26A-26D . The portions of the mask  2502  may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. The portion of the mask  2502  in the trench  2102  is not affected by the removal process. The removal process exposes portions of the seed layer  2302  disposed on the nitrogen-containing layers  1606 . 
     Next, as shown in  FIGS. 27A-27D , the portions of the seed layer  2302  disposed on the nitrogen-containing layers  1606  are removed, followed by the removal of the portion of the mask  2502  in the trench  2102  to expose the portion of the seed layer  2302  formed on the bottom of the trench  2102 . The portions of the seed layer  2302  disposed on the nitrogen-containing layer  1606  may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. In some embodiments, as shown in  FIGS. 26B-26D and 27B-27D , the portions of the mask  2502  and the portions of the seed layer  2302  disposed on the nitrogen-containing layers  1606  are removed by two etch processes. Alternatively, the portions of the mask  2502  and the portions of the seed layer  2302  disposed on the nitrogen-containing layer  1606  are removed by a planarization process, such as a CMP process. 
     The portion of the mask  2502  disposed in the trench  2102  may be removed by any suitable process, such as a dry etch, a wet etch, or a combination thereof. The removal of the portion of the mask  2502  may be selective, so the nitrogen-containing layers  1606 , the spacers  1202 , and the seed layer  2302  disposed on the bottom of the trench  2102  are not removed due to different etch selectivity. 
     Next, as shown in  FIGS. 28A-28D , the conductive layer  2802  is formed on the seed layer  2302 . The conductive layer  2802  may include a metal, such as W, Ru, Co, or other suitable conductive material. The conductive layer  2802  may be formed by any suitable process, such as PVD or ALD. The conductive layer  2802  is formed on conductive material of the seed layer  2302  but not the dielectric material of the nitrogen-containing layer  1606 . The conductive layer  2802  may have a thickness ranging from about 2 nm to about 5 nm. The conductive layer  2802  may be utilized to function as an electrical path for the gate electrode layers  1906 . Thus, if the thickness of the conductive layer  2802  is less than about 2 nm, the electrical resistance may be high. On the other hand, if the thickness of the conductive layer  2802  is greater than about 5 nm, the manufacturing cost is increased without significant advantage. 
     An opening  2902  is formed in the conductive layer  2802  and the seed layer  2302 , as shown in  FIGS. 29A-29D . In some embodiments, the opening  2902  is formed by two etch processes. A first etch process is performed to remove a portion of the conductive layer  2802  to expose a portion of the seed layer  2302 . The first etch process may be a dry etch, a wet etch, or a combination thereof. The first etch process may be a selective etch process that removes the portion of the conductive layer  2802  but not the nitrogen-containing layers  1606  and the spacers  1202 . The gate electrode layers  1906  located below the removed portion of the conductive layer  2802  are protected by the seed layer  2302  from the etchant that removes the portion of the conductive layer  2802 . A second etch process is performed to remove the exposed portion of the seed layer  2302  to form the opening  2902 . The second etch process may be a dry etch, a wet etch, or a combination thereof. The second etch process may be a selective etch process that removes the portion of the seed layer  2302  but not the nitrogen-containing layers  1606 , the spacers  1202 , the conductive layer  2802 , the dielectric material  904 , and the gate electrode layers  1906 . The opening  2902  exposes the dielectric material  904  of one of the dielectric features  906 . Portions of the gate electrode layers  1906  adjacent the dielectric feature  906  may be also exposed. 
     Next, as shown in  FIGS. 30A-30D , the dielectric material  3002  is formed in the opening  2902  and on the conductive layer  2802 . The dielectric material  3002  may include the same material as the dielectric material  904  and may be formed by the same process as that of the dielectric material  904 . The dielectric material  3002  may be formed in the opening  2902  and in contact with the dielectric material  904  and portions of the gate electrode layers  1906 . As shown in  FIG. 30A , the seed layer  2302  and the conductive layer  2802  are separated by the dielectric material  3002  into multiple segments, such as two segments. One segment of the seed layer  2302  and the conductive layer  2802  electrically connects the gate electrode layers  1906  located above the substrate portions  102   c ,  102   d ,  102   e , while the other segment of the seed layer  2302  and the conductive layer  2802  electrically connects the gate electrode layers  1906  located above the substrate portions  102   a ,  102   b . For example, a first seed layer  2302  is in contact with two or more gate electrode layers  1906  separated by one or more dielectric features  906 , and a first conductive layer  2802  is disposed on the first seed layer  2302 . A second seed layer  2302  is in contact with two or more gate electrode layers  1906  separated by one or more dielectric features  906 , and a second conductive layer  2802  is disposed on the second seed layer  2302 . The first seed layer  2302  and the first conductive layer  2802  are separated from the second seed layer  2302  and the second conductive layer  2802  by the dielectric material  3002 . 
     A conductive feature  3102  may be formed through the dielectric material  3002 , the conductive layer  2802 , and the seed layer  2302  and in contact with the gate electrode layer  1906 , as shown in  FIG. 31 . The conductive feature  3102  may include a material having one or more of Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN and TaN, and may be formed by any suitable process, such as PVD, ECP, or CVD. The conductive feature  3102  may provide a signal, such as an electrical current, to the gate electrode layer  1906  located therebelow. Furthermore, the signal may be provided to adjacent gate electrode layer  1906  via the conductive layer  2802  and the seed layer  2302 . Thus, adjacent gate electrode layers  1906  may receive the signal from one conductive feature  3102  via the conductive layer  2802  and seed layer  2302 . The dielectric material  3002  cuts off the conductive layers  2802  and seed layers  2302 , so the signal is not provided to the conductive layer  2802  and seed layer  2302  on the other side of the dielectric material  3002 . 
     The present disclosure provides a semiconductor device structure  100  including first, second, and third gate electrode layers  1906  separated by dielectric features  906 . A first conductive layer  2802  and a first seed layer  2302  are disposed on the first and second gate electrode layers  1906 , and a second conductive layer  2802  and a second seed layer  2302  are dispose on the third gate electrode layers  1906 . The first conductive layer  2802  and the first seed layer  2302  are separated from the second conductive layer  2802  and the second seed layer  2302  by a dielectric material  3002 , and the dielectric material  3002  is disposed on the first and second conductive layers  2802 . Some embodiments may achieve advantages. For example, the seed layer  2302  allows the conductive layer  2802  to be formed over and electrically connecting two or more gate electrode layers  1906 . The removal of the conductive layer  2802  to form the opening  2902  does not damage the gate electrode layers  1906  due to the presence of the seed layer  2302 . 
     An embodiment is a semiconductor device structure. The semiconductor device structure includes a first gate electrode layer, a second gate electrode layer adjacent the first gate electrode layer, a third electrode layer adjacent the second gate electrode layer, a first dielectric feature disposed between the first gate electrode layer and the second gate electrode layer, a second dielectric feature disposed between the second gate electrode layer and the third gate electrode layer, a first seed layer in contact with the first gate electrode layer, the first dielectric feature, and the second gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer in contact with the third gate electrode layer, a second conductive layer disposed on the second seed layer, and a dielectric material disposed on the second dielectric feature, the first conductive layer, and the second conductive layer. The dielectric material is between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer. 
     Another embodiment is a semiconductor device structure. The structure includes a first gate electrode layer, a second gate electrode layer adjacent the first gate electrode layer, and a dielectric feature disposed between the first gate electrode layer and the second gate electrode layer. The dielectric feature includes a liner, a first dielectric material disposed on the liner, and a second dielectric material disposed on the liner and the first dielectric material. The semiconductor device structure further includes a first seed layer disposed on the first gate electrode layer, a first conductive layer disposed on the first seed layer, a second seed layer disposed on the second gate electrode layer, a second conductive layer disposed on the second seed layer, and a third dielectric material disposed between the first seed layer and the second seed layer and between the first conductive layer and the second conductive layer. 
     A further embodiment is a method. The method includes forming first and second fins from a substrate, and the first fin includes a first plurality of semiconductor layers and the second fin includes a second plurality of semiconductor layers. The method further includes forming a dielectric feature between the first and second fins, forming a gate electrode layer surrounding the first and second pluralities of semiconductor layers; forming a seed layer on the gate electrode layer and the dielectric feature, forming a conductive layer on the seed layer, forming a first opening in the seed layer and the conductive layer to expose the dielectric feature, and forming a first dielectric material in the first opening on the dielectric feature. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.