Patent Publication Number: US-7225304-B2

Title: Controller and method for writing data

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
   This application is based upon and claims the benefit of priority from prior Japanese Patent Application No. 2003-285159, filed on Aug. 1, 2003, and Japanese Patent Application No. 2004-014679, filed on Jan. 22, 2004, the entire contents of each which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to a controller and a method for writing data. 
   Usually, peripheral equipment for a computer such as an optical disk drive includes a ROM (read-only memory) as a memory for storing a microcomputer operation program (hereinafter referred to as microcomputer control software) that is used for controlling each circuit. In recent years, usually, an electrically rewritable flash ROM that can rewrite data is used as this ROM. This is because the microcomputer control software must be updated in order to debug the microcomputer control software while the peripheral equipment is being developed or to perform updates (version upgrade) for improving functioning of the microcomputer control software. 
   Two types of software are written to a flash ROM, one is the aforementioned microcomputer control software for allowing a microcomputer to control each circuit and the other is an update program to be executed by the microcomputer to update the microcomputer control software. During normal operation of peripheral equipment, the microcomputer controls each circuit in accordance with the microcomputer control software written to the flash ROM. In contrast, during update of the microcomputer control software, the microcomputer rewrites the microcomputer control software recorded in the flash ROM in accordance with the update program written to the flash ROM. 
   The aforementioned description relates to an operation state in which microcomputer control software and an update program have been already written to the flash ROM. In a complete initial state, however, naturally, no data has been written to the flash ROM. That is, to allow a microcomputer to write the microcomputer control software to the flash ROM, at least the update program must have been already written to the flash ROM, but even this program has not been written in a complete initial state. 
   Consequently, conventionally, predetermined initial data (data containing at least an update program) is written to a flash ROM in a standalone state by commissioning flash ROM manufacturers or by using a ROM writer. A flash ROM chip, to which initial microcomputer control software is written, is subsequently mounted on a printed wiring board of the relevant peripheral equipment by soldering. 
   In the aforementioned method, because writing of the initial microcomputer control software is needed separately before the flash ROM chip is mounted on the peripheral equipment, the process becomes complicated and manufacturing cost inevitably increases. 
   Accordingly, Japanese Laid Open Patent publication No. 5-81012 discloses a method that is adopted for mounting a flash ROM chip without writing initial microcomputer control software and writing the microcomputer control software after it is mounted. Specifically, a mask ROM in which at least an update program is recorded in advance is incorporated in the relevant peripheral equipment and this mask ROM is connected to the microcomputer. Subsequently, the microcomputer is operated in accordance with a mask ROM program. The microcomputer writes the microcomputer control software received from a personal computer (PC) via an interface such as an RS232C and an ATAPI or a SCSI to the flash ROM. 
   This method, however, needs a mask ROM, which stores at least an update program but is not used for normal operations. Accordingly, the employment of the mask ROM, which is not necessary at all during normal operations, increases the chip area of a control chip (control integrated circuit). 
   SUMMARY OF THE INVENTION 
   One aspect of the present invention is a controller for use with a memory to perform predetermined control in response to an instruction from a host computer. The controller includes a first register for connection to the host computer and storing a command and data sent from the host computer. The command is in a first state or a second state. A second register for function expansion is connected to the first register and fetches data stored in the first register when the command stored in the first register is in the first state. A decoder is connected to the second register and receives the data stored in the first register via the second register, performs a predetermined decoding process on the data, and provides the data to the memory when the command stored in the first register is in the second state. The data received in the decoder includes an operation program for the controller. 
   Another aspect of the present invention is a method for writing data, used by a controller to perform predetermined control, to a memory in response to an instruction from a host computer. The controller includes a first register that is connected to the host computer and stores a command and data sent from the host computer. The command is in a first state or a second state. A second register for function expansion is connected to the first register and fetches data stored in the first register when the command stored in the first register is in the first state. A decoder is connected to the second register. The method includes providing the decoder with the data stored in the first register via the second register when the command stored in the first register is in the second state, performing a predetermined decoding process on the data with the decoder, and writing the decoded data to the memory. The data provided to the memory includes an operation program for the controller. 
   Other aspects and advantages of the present invention will become apparent from the following description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention, together with objects and advantages thereof, may best be understood by reference to the following description of the presently preferred embodiments together with the accompanying drawings in which: 
       FIG. 1  is a schematic block diagram showing peripheral equipment including a control chip according to a preferred embodiment of the present invention; 
       FIG. 2  is a schematic block diagram of the control chip of  FIG. 1 ; 
       FIG. 3  is a table showing flash memory commands; 
       FIG. 4  is a timing chart of an erase operation performed by the flash memory; and 
       FIG. 5  is a timing chart of a program operation performed by the flash memory. 
   

   DESCRIPTION OF PREFERRED EMBODIMENTS 
   In the drawings, like numerals are used for like elements throughout. 
   An embodiment in accordance with the present invention is described below with reference to  FIG. 1 . 
     FIG. 1  is a schematic block diagram showing computer peripheral equipment  100 , for example, a CD-ROM drive. The peripheral equipment  100  has a control chip (control integrated circuit)  11  and a flash ROM  12 . The control chip  11  incorporates a CPU  21 , an interface  22 , a decoder  23 , and an additional interface  24 . The interface  22  includes an Advanced Technology Attachment (ATA) register  22   a  and an AT Attachment Packet Interface (ATAPI) register  22   b . The ATA register  22   a  of the first interface  22  in the control chip (peripheral equipment)  11  is communicatively connected to a host computer  30 . 
   The ATA register  22   a  is an 8-byte register for mediating between signals (commands or read and write data) in accordance with an ATA standard that specifies the signal exchange between the host computer  30  and the peripheral equipment  100 . The ATA register  22   a , which includes a command register and a data register, writes data to, and reads data from, the host computer  30  and the CPU  21  in compliance with the ATA standard. 
   On the other hand, the ATAPI register  22   b  is a 12-byte register added for operating expanded functions from the standpoint of the standard, in order to enable access to peripheral equipment other than a hard disk drive. The host computer  30  can write 12-byte data to the ATAPI register  22   b  via the ATA register  22   a  by writing a command having code value A0h (hexadecimal) to the command register of the ATA register  22   a . Hereinafter, when describing a code value, the “command code value” will be used together with the hexadecimal value. For example, the command having code value A0h will be shown as command code A0h. That is, the command code A0h is written to the command register of the ATA register  22   a  to set the destination of a signal of a data register to the ATAPI register  22   b , and the 12-byte data immediately following the command code A0h is sent to the ATAPI register  22   b.    
   The 12-byte data includes a command, which is decoded and executed by the CPU  21 . Accordingly, the peripheral equipment  100  operates in accordance with the 12-byte data written to the ATAPI register  22   b.    
   Because initial data (microcomputer control software and an update program) is not written to the flash ROM  12  immediately after the flash ROM is manufactured in a factory, the CPU  21  cannot perform any operations. 
   The writing of initial data to the flash ROM  12  in this embodiment is described below. 
   The interface  22  of the control chip  11  is connected to the host computer  30 , which stores the initial data. 
   A write mode for the initial data is started in accordance with data provided from the host computer  30  and written to the ATA register  22   a . By transmitting command code A0h (hexadecimal) according to ATA (ATAPI) to the ATA register  22   a , data subsequent to the command code A0h is stored in the ATA register  22   a , and then the data is stored in the ATAPI register  22   b  via the ATA register  22   a . The command code A0h is an ATA standard command that sets a window for the ATAPI register  22   b  in the ATA register  22   a  and enables access of the ATAPI register  22   b  by the host computer  30 . In the present embodiment, the command code A0h designates the ATAPI register  22   b  as the destination for 12-bytes of data sent subsequent to the command code A0h. That is, the host computer  30  writes data to the ATAPI register  22   b  via the ATA register  22   a  connected thereto by writing the command code A0h to a command register of the ATA register  22   a.    
   The data written to the ATAPI register  22   b  via the ATA register  22   a  can include command codes that are not regulated by the standard. That is, vendor unique special commands that are not regulated by the ATAPI standard are set as the command codes. These special commands indicate writing to the flash ROM  12 . When the special commands are sent to the ATAPI register  22   b  from the host computer  30  via the ATA register  22   a , the control chip  11  of the peripheral equipment  100  executes the special commands and writes data to the flash ROM  12 . Since the special commands are vendor unique commands that are not defined by the ATA/ATAPI standard, the function of the peripheral equipment  100  in normal operation is not affected by the special commands. 
   Specifically, the host computer  30  writes the command code A0h to the command register of the ATA register  22   a  and sends the special command to the ATAPI register  22   n  via the ATA register  22   a  connected thereto. The data sent from the host computer  30  to the ATAPI register  22   b  via the ATA register  22   a  is decoded by the decoder  23 . Consequently, the decoder  23  enables access to the flash ROM  12  via the interface  24  as a sequence, generates a control signal that writes predetermined write data to the predetermined write address, and then generates a control signal that causes the CPU  21  to sleep at the write operation. Thus, the decoder  23  can sequentially write predetermined data to the predetermined address of the flash ROM  12  without being hindered by the CPU  21 . 
   When writing data, the host computer  30  utilizes a signal IORDY (not shown) according to the ATA standard. The IORDY is a signal externally output by the interface  24  if data can be input to the peripheral equipment  100 . That is, the host computer  30  detects that it is possible to write next data to the ATA register  22   a  (ATAPI register  22   b ) based on the signal IODRY. This detection decreases unnecessary wait time when writing a command to the ATA register  22   a  and the ATAPI register  22   b  in comparison to a method in which the host computer  30  waits until a time sufficient to write data has elapsed by using, for example, a timer, thereby shortening time need for writing to the flash ROM  12  and performing data writing in an effective and fast manner. 
   When all of the write data (microcomputer control software) is written, the host computer  30  verifies the data written to the flash ROM  12  via the interface  24 , the decoder  23 , the ATAPI register  22   b , and the ATA register  22   a . After the data is verified, the host computer  30  sends a command that terminates the writing of initial data to the ATA register  22   a . Consequently, a path into the interface  24  of the decoder  23  and a path into the ATAPI register  22   b  of the ATA register  22   a  closes and the write mode terminates. At the same time, the CPU sleeping state is released by the control of the decoder  23 . 
     FIG. 2  is a schematic block diagram of the control chip  11 . 
   The ATA register  22   a  includes a plurality of sections (registers). Each register is accessed to write data, set a value, or to read a status. The register  41  is a register for writing and reading data and is referred to as a data register. The register  42 , which is a register for writing a command and reading a status, is referred to as a command register when writing a command and is referred to as a status register when reading a status. Although the command register and the status register are actually formed in different sections, the same address is accessed. Thus, when the host computer  30  writes data to this address, the data is written to the command register  42 . When data is read from this address, the contents of the status register  42  are read. 
   The host computer  30  writes data for the peripheral equipment  100  to the data register  41  and reads data for the peripheral equipment  100  from the data register  41 . The host computer  30  writes a command to the command register  42 . The peripheral equipment  100  analyzes and executes the command written to the peripheral equipment  100 . The host computer  30  reads the content of the status register  42  and determines the state of the peripheral equipment  100  based on the contents read. 
   The ATAPI register  22   b  includes a plurality of pages (registers)  50   a ,  50   b  and  50   c . The storage capacity of each of the pages  50   a ,  50   b  and  50   c  is set to an amount of data (12-bytes) transferred by one write command at maximum. Each of the pages  50   a ,  50   b  and  50   c  is changed to be accessible by page designation. 
   The first page  50   a  has a plurality of sections (registers)  51   a ,  51   b ,  51   c  and  51   d , each accessed to set the operation mode or to write and read address data. These accesses are performed via the data register  41  of the ATA register  22   a  during the write mode. That is, data provided from the host computer  30  is written to each of the registers  51   a ,  51   b ,  51   c , and  51   d  via the data register  41  of the ATA register  22   a . Further, the data read from each of the registers  51   a ,  51   b ,  51   c , and  51   d  is provided to the host computer  30  via the data register  41 . 
   Each of the registers  51   a ,  51   b ,  51   c , and  51   d  is used to set an operation mode. An operation mode for consecutively writing data is set for the register  51   a . An operation mode for writing a single piece of data is set for the register  51   b . An operation mode for reading a single piece of data is set for the register  51   c . An operation mode for automatically incrementing the accessed address is set for the register  51   d.    
   The second page  50   b  has a plurality of sections (registers)  52   a ,  52   b ,  52   c , and  52   d . The register  52   a  functions as a register for storing the access address of the flash ROM  12  (access address register). Further, the register  52   b  functions as a register for writing data to that address or reading data from that address (access data register) 
   The register  52   c  function as a register for writing the cycle number (count value) required for accessing the flash ROM  12 . The cycle number is set in the register  52   c  as a count value corresponding to the electrical characteristics of the flash ROM  12  and the frequency of the clock signal. 
   Due to a setup or hold time, the flash ROM  12  is accessed at predetermined time intervals. For example, when consecutively writing data to the flash ROM  12 , a predetermined time must elapse from when a piece of data is written to the flash ROM  12  before writing the next piece of data. The predetermined time is determined by the electrical characteristics of the flash ROM  12 . 
   The decoder  23  counts the number of pulses of a clock signal to measure the access time (wait time) for the flash ROM  12 . The frequency of the clock signal may differ depending on the peripheral equipment to which the control chip  11  is mounted. Accordingly, the host computer  30  writes a count value, which corresponds to the electrical characteristics of the flash ROM  12  and the frequency of the clock signal, to the register  52   c . The decoder  23  measures the wait time based on the count value and accesses the flash ROM  12  in accordance with the measured wait time. 
   The third page  50   c  has a plurality of sections (registers)  53 . The register  53  is a register set for storing a command set that operates the flash ROM  12 . A command for operating (mode switching) the flash ROM  12  is configured by plural bytes and is referred to as the command set. The command set is used to prevent noise or the data written to the flash ROM  12  in a normal mode, from being erroneously recognized as a command. The command set is configured by plural pairs of command addresses and command data. The number of pairs differs between commands. 
     FIG. 3  shows a typical command set for a flash memory, and  FIGS. 4 and 5  show the timing for providing the command set. Referring to  FIG. 3 , the flash ROM  12  is provided with a command configured by a predetermined address and data when data is erased from, written to, or read from the flash ROM  12 . A certain number of cycles are required to provide the command, and the number of such cycles differs between commands. 
   Referring to  FIG. 4 , for example, during an erasing operation, a command address and command data for erasing data is sequentially provided during six cycles. The erasing is started based on the erase address (sector address) and data  30   h  provided in the sixth address. 
   Referring to  FIG. 5 , for example, during a write operation, a command address and command data for writing data is sequentially provided during four cycles. The write operation is started based on the write address and write data provided in the fourth address. 
   For example, the host computer  30  stores the command set shown in  FIG. 3 , as a command set configured by four pairs of command addresses and command data, in eight registers. The decoder  23  sequentially reads the address and data of each pair from the registers and provides the flash ROM  12  with the read addresses and data. 
   Referring to  FIG. 2 , the decoder  23  includes a control circuit  61 , a counter  62 , and a plurality of flip-flops  63 . The control circuit  61  is connected to the counter  62 . Further, the control circuit  61  is connected to the interface  24  via the flip-flops  63 . Each of the flip-flops  63  holds a plurality of signals transferred between the control circuit  61  and the flash ROM  12 . 
   The control circuit  61  operates based on the contents written to the ATAPI register  22   b , reads the program data written to the ATAPI register  22   b  from the host computer  30 , and writes the program data to the flash ROM  12 . Further, the control circuit  61  sets the count value (set value) written to the register  52   c  in the counter  62 . 
   The counter  62  is, for example, an increment counter, and counts the number of pulses of a reference clock signal (not shown). The counter  62  provides the control circuit with a count-up signal having a predetermined value when the count value matches the set value of the control circuit  61  to reset the count value. In response to the count-up signal, the control circuit  61  performs the next access of the flash ROM  12 . 
   The interface  24  includes a plurality of switch circuits  71 , respectively corresponding to the flip-flops  63 , and a plurality of interface (I/F) circuits  72 , respectively corresponding to the switch circuits  71 . The I/F circuits  72  and the switch circuits  71  correspond to signals transferred between the control circuit  61  and the flash ROM  12 . 
   In accordance with the operation state of the control chip  11 , the switch circuits  71  switch the connection between the flash ROM  12  and the CPU  21  and the connection between the flash ROM  12  and the decoder  23 . The writing of a command to the ATA register  22   a  changes the operation state of the control chip  11 . More specifically, the switch circuits  71  are operated to connect the flash ROM  12  to the CPU  21  during normal operation. In response to a control signal S 1  generated in accordance with the write mode (i.e., the writing of the command code A0h to the command register  42  by the host computer  30 ), the switch circuits  71  connect the flash ROM  12  to the decoder  23 . Further, in response to the control signal S 1  generated when aborting the write mode (i.e., the writing of a predetermined command (in this case,  87   h ) to the command register  42  by the host computer  30 ), the switch circuits  71  connect the flash ROM  12  to the CPU  21 . 
   The procedures for writing a program to the flash ROM  12  will now be discussed. 
   (1) The host computer  30  writes a command code, which has a predetermined value (A 0 h) to the command register  42  of the ATA register  22   a . This opens a window for the ATAPI register  22   b  (enables the host computer  30  to access the ATAPI register  22   b  via the data register  41 ), and switches the connection of the flash ROM  12  and the CPU  21  to the connection of the flash ROM  12  and the decoder  23  with the switch circuits  71 . 
   (2) The host computer  30  writes the data described below to the corresponding registers of the ATAPI register  22   b  via the data register  41  of the ATA register  22   a.    
   (a) Data for selecting a program write mode is written to the register  51   a , and data for selecting an address increment mode is written to the register  51   a.    
   (b) The count value is written to the register  52   a.    
   (c) An initial word command set for performing a writing operation on the flash ROM  12  is written to the register  53 . 
   (d) An access address is written to the register  52   a.    
   (3) The host computer  30  performs the following on a register of the ATAPI register  22   b  via the data register  41  of the ATA register  22   a.    
   (e) Write access data. 
   (4) In response to the writing of the access data, the control circuit  61  of the decoder  23  reads the mode setting value of the ATAPI register  22   b . Since the program write mode is selected, the control circuit  61  sequentially reads the initial work command set for performing a writing operation on the flash ROM  12  and accesses the flash ROM  12  via the flip-flops  63  and the interface  72 . In this state, for each access, the control circuit  61  waits for a time (predetermined period) that is obtained by the counter from the product of the clock signal cycle and the count value. 
   (5) The control circuit  61  reads access address and access data from the registers  52   a  and  52   b  to perform writing on the flash ROM  12 . Then, the control circuit  61  accesses the flash ROM  12  via the flip-flop  63  and the interface  72 . 
   (6) After the period during which data is written to the flash ROM  12  (the period required for providing the flash ROM  12  with a command set and for writing access data) elapses, the host computer  30  writes the access data of the next address to the register  52   b  of the ATAPI register  22   b  via the data register  41  of the ATA register  22   a.    
   (7) In response to the writing of the access data, the control circuit  61  reads the mode setting value of the ATAPI register  22   b . Since the program write mode is selected, the control circuit  61  sequentially reads the initial work command set for performing a writing operation on the flash ROM  12  and accesses the flash ROM  12  via the flip-flops  63  and the interface  72 . Since the address increment mode is selected, the control circuit  61  increments (+1) the access address of the register  52   a.    
   (8) The control circuit  61  reads access data for performing a write operation on the flash ROM  12  and accesses the flash ROM  12  at the incremented access address via the flip-flops  63  and the interface  72 . 
   (9) The control circuit  61  repeats steps 6, 7, and 8 until completion of the writing of the entire program data. 
   (10) The host computer  30  writes a command code having a predetermined value ( 87   h ), which ends writing, to the command register  42  of the ATA register  22   a . This closes the window of the ATAPI register  22   b  and switches the connection of the flash ROM  12  and the decoder  23  to the connection of the flash ROM  12  and the CPU  21 . 
   In this manner, microcomputer control software (a control circuit operation program) for allowing the CPU  21  to control each circuit of the peripheral equipment and an update program for allowing the CPU  21  to update the microcomputer control software are written to the flash ROM  12 . Accordingly, the CPU  21  reads the microcomputer control software written to the flash ROM  12  via the interface  24  and controls each circuit in accordance with the software. For example, when the peripheral equipment  100  is a CD-ROM drive, the CD-ROM drive moves a pick-up for irradiating a laser on the predetermined position of an optical disk or reads out the data recorded on the optical disk by reading the reflected light of the laser. On the other hand, during the update of the microcomputer control software, the CPU  21  rewrites the data of the microcomputer control software in accordance with the update program. 
   As described above, according to this embodiment, the following advantages are obtained. 
   (1) In this embodiment, when the command code A0h is sent from the host computer  30  to the ATA register  22   a , the data sent from the host computer  30  is sent to the ATAPI register  22   b  via the ATA register  22   a . Subsequently, the data including a special command is sent to the ATAPI register  22   b , and the data is decoded by the decoder  23  to generate a write address for writing data to the flash ROM  12  and write data. When the special command is sent to the ATAPI register  22   b  in this manner, the write address and write data are generated in the circuit configuration in which only provided is the decoder  23  that decodes the data transmitted to the ATAPI register  22   b , thereby enabling the writing of initial data to the flash ROM  12 . That is, only a slight change in a circuit that is composed mainly of existing interfaces is necessary, but an increase in the circuit area of the control chip  11  can be suppressed as there is no need to provide a mask ROM for writing microcomputer control software. Moreover, because tasks such as writing in advance initial data in the flash ROM  12  in a standalone state and mounting the flash ROM  12  is unnecessary, an increase in manufacturing cost can also be suppressed. 
   (2) In this embodiment, data (microcomputer control software) can be written to the flash ROM  12  using data processing (a command) that is regulated by the ATA (ATAPI) standard. Accordingly, circuit design load for writing the microcomputer control software can also be reduced. In particular, the host computer  30  and the control chip  11  can be connected in accordance with the existing standard and can reduce the load under which a dedicated interface is developed even when the initial data is written. 
   (3) In this embodiment, if a special command is sent to the ATA register  22   a  via the ATA register, the CPU  21  is made to sleep by the decoder  23 . Consequently, the write processing of the microcomputer control software for the flash ROM  12  can be prevented from being hindered by the operation of the CPU  21 . 
   (4) In this embodiment, because data is not recorded in advance in the flash ROM  12 , for example, a ROM can be integrated in the control chip. In this case, the circuit area of the entire peripheral equipment can be reduced. 
   It should be apparent to those skilled in the art that the present invention may be embodied in many other specific forms without departing from the spirit or scope of the invention. Particularly, it should be understood that the present invention may be embodied in the following forms. 
   As described previously, the flash ROM  12  can also be integrated in the control chip  11 . In this case, the circuit area of the entire peripheral equipment can be reduced. 
   In addition, a flash ROM may be employed as a memory. If data can be written, another PROM (Programmable ROM) can also be employed. 
   Further, the ATA register  22   a  and the ATAPI register  22   b  are employed as a first register and a function expanding register, respectively, but a register that conforms to another standard can also be employed. Even in this case, a command that enables the same data processing can be set corresponding to the standard. 
   Also, peripheral equipment  100  can be any type of equipment, as well as a CD-ROM drive, if the peripheral equipment can exchange data by connection with a computer. For example, the peripheral equipment can be an optical disk drive such as an MD and a DVD-RAM, a magneto optical disk drive such as an MO or a magnetic disk drive, such as a hard disk. Further, the peripheral equipment is not limited to such as that for information recording. For example, the peripheral equipment can be also an output device such as a printer, a reader such as a scanner, or a communication device such as a MODEM or a LAN. 
   The present examples and embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalence of the appended claims.