Patent Publication Number: US-7903056-B2

Title: Voltage-current converting method, voltage-current converting circuit and active matrix type display apparatus

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a voltage-current converting method and a voltage-current converting circuit. In particular, the present invention relates to an active matrix type display apparatus using a current drive type display device and a current programming type pixel circuit, and a voltage-current converting method of the display apparatus. 
     2. Description of the Related Art 
     In recent years, self-luminous type displays using light emitting devices have been watched as next generation displays. Among them, the application and the development of an organic electroluminescence (EL) device, which is a current control type light emitting device, the light emission luminance of which is controlled by the current flowing through the element, have been actively performed. An organic EL display including the peripheral circuitry thereof uses thin film transistors (TFTs) not only in the display area thereof but also in the peripheral circuitry. A conventional image display panel (hereinafter referred to as an EL panel) that applies EL elements, which are such self-luminous elements, as image display elements and uses the TFTs in the display area thereof and the peripheral circuitry thereof will be described with reference to the attached drawings. 
       FIG. 12  illustrates an example of the configuration of an EL panel including conventional current setting system pixel circuits. 
     In an EL panel  100  illustrated in  FIG. 12 , a pixel display unit  9  and the peripheral circuitry thereof are arranged. In the pixel display unit  9 , EL elements, the number of which is equal to the number of R, G, B primary colors, and pixel circuits  2  composed of TFTs for controlling the currents input into the EL elements are two-dimensionally arranged in a matrix of N columns by M rows. A horizontal scanning control signal  11   a  is input from the outside into an input circuit  6  in the peripheral circuitry. Moreover, a vertical scanning control signal  12   a  is input from the outside into an input circuit  7 . Furthermore, an auxiliary column control signal  13   a  is input from the outside into an input circuit  8 . 
     A horizontal scanning control signal  11  (including a horizontal clock signal and a horizontal scanning start signal) converted by the input circuit  6  is input into a column shift register  3 . Moreover, a vertical scanning control signal  12  converted by the input circuit  7  is input into a row shift register  5 . A row scanning signal  20  output from each output terminal of the row shift register  5  is input into the pixel circuits  2  on each row through a scanning line. 
     Moreover, an auxiliary column control signal  13  converted by the input circuit  8  is input into each of gate circuits  4  and  16 . A first horizontal sampling signal  17  output from each terminal of the column shift register  3  is input into a horizontal sampling signal gate circuit  15  together with a control signal  21  converted by the gate circuit  16 . A second horizontal sampling signal  18  converted by the horizontal sampling signal gate circuit  15  is input into column current generation circuits (also referred to as “column current control circuits” or “column control circuits”)  1  together with a video signal (voltage signal)  10  input from the outside and a control signal  19  converted by the gate circuit  4 . A column control signal  14 , which is a current signal converted from a video signal by the column current generation circuit  1 , is input into the pixel circuit  2  of each column through a data line. 
     The plurality of column current generation circuits  1  are arranged according to the number of primary colors of each column of the pixel circuits  2 , and are configured to cope with each number of primary colors of the input video signal  10 . Each of the column current generation circuits  1  is configured by using a voltage-current converting circuit converting a dot sequential voltage video signal into a line sequential current video signal by the line. 
       FIG. 13  illustrates an example of the configuration of a voltage-current converting circuit constituting the column current generation circuit  1  described in U.S. Pat. No. 7,126,565. Incidentally, a gate, a source, and a drain of a transistor will be denoted by brevity codes of /G, /S, and /D, respectively, and a signal and a signal line for supplying the signal will be similarly represented without distinguishing them as the occasion demands in the following description. Transistors M 5  and M 12  among transistors M 1 -M 12 , which are TFTs, are p-channel TFTs (PMOSs) and the other transistors are n-channel TFTs (NMOSs). The transistors M 3  and M 9  are column current generating drive transistors (NMOS current drive transistors). 
     A video signal video, sampling signals SPa and SPb, and control signals P 1 -P 6 , each of which constitutes the control signal  19 , are input into the column current generation circuit  1  illustrated in  FIG. 13 . The video signal video is connected to the M 1 /S and the M 7 /S, and the sampling signals SPa and sampling signal SPb are connected to the M 1 /G and M 7 /G, respectively. The M 1 /D is connected to a capacitor C 1 , and the other end of the capacitor C 1  is connected to a capacitor C 2 , one end of which is grounded, and the transistor M 3 /G, the source of which is grounded. The M 3 /D and the M 3 /G are connected to the M 2 /D and the M 2 /S, respectively, and the control signal P 1  is connected to the M 2 /G. The M 3 /D is connected the M 4 /S; the M 4 /D is connected to the short-circuited gate and drain of the transistor M 5 , the source of which is connected to a power source voltage VCC; and the M 4 /G is connected to the control signal P 2 . Furthermore, the M 3 /D is connected to the M 6 /S; the M 6 /D is connected to a terminal from which a current signal i (data) is output; and the M 6 /G is connected to the control signal P 3 . On the other hand, the M 7 /D is connected to a capacitor C 3 , and the other end of the capacitor C 3  is connected to a capacitor C 4 , one end of which is grounded, and the gate of the transistor M 9 , the source of which is grounded. The M 9 /D and the M 9 /G are connected to the M 8 /D and the M 8 /S, respectively, and the control signal P 4  is connected to the M 8 /G. The M 9 /D is connected to the M 11 /S; the M 11 /D is connected to the short-circuited gate and drain of the transistor M 12 , the source of which is connected to the power source voltage VCC; and the M 11 /G is connected to the control signal P 5 . Furthermore, the M 9 /D is connected to the M 10 /S; the M 10 /D is connected to the terminal outputting the current signal i (data); and the M 10 /G is connected to the control signal P 6 . 
       FIG. 14  is a time chart for describing the operation of the column current generation circuit  1  illustrated in  FIG. 13 .  FIG. 14  illustrates the operation for three horizontal scanning periods of a video signal, or for three lines of the EL panel. 
     First, just before a time t 1 , each of the sampling signals SPa and SPb is the L level, and the control signals P 1 -P 6  are L, L, H, L, H, and L levels, respectively. Each of the transistors M 1 , M 2 , M 4 , M 6 , M 7 , M 8 , M 11 , and M 10 , which perform switching operations, are in the following state: M 1 =OFF, M 2 =OFF, M 4 =OFF, M 6 =ON, M 7 =OFF, M 8 =OFF, M 11 =ON, and M 10 =OFF, respectively. At this time, the transistors M 3  and M 9  are current-driven by holding voltages Va 1  and Vb 1  charged in the capacitor attended to each of their gate electrodes, respectively. That is, the current Ia 1  of the M 3 /D is output as the current signal i (data), and becomes the column control signal  14 . The current of the M 9 /D is supplied to the transistor M 12 , and the voltage of the M 9 /D is determined. 
     Next, at the time t 1 , the input video signal video is at the blanking level Vb 1 . At this time point, the sampling signal SPa, and the control signals P 2 , P 3 , P 5 , and P 6  change to the H, H, L, L, and H levels, respectively. Consequently, each of the transistors M 1 , M 2 , M 4 , M 6 , M 7 , M 8 , M 11 , and M 10 , which perform switching operations, are in the following state: M 1 =ON, M 2 =OFF, M 4 =ON, M 6 =OFF, M 7 =OFF, M 8 =OFF, M 11 =OFF, and M 10 =ON, respectively. At this time, as the current signal i (data), the current Ib 1  of the M 9 /D driven by the voltage Vb 1  of the M 9 /G is output in the place of the current Ia 1  of the M 3 /D. Before a time t 2 , the control signal P 1  changes to the H level, and the transistor M 2  turns to ON. The M 3 /G is charged by the transistor M 5  in a short period of time from this time point to a time t 2 . 
     Next, at the time t 2 , the charging operation of the M 3 /G by the transistor M 5  stops, and the M 3 /G performs a self-discharge operation it gradually approaches its own threshold voltage Vth. Next, at a time t 3 , the sampling signal SPa changes to the L level, and the transistor M 1  turns to OFF. Before a time t 4 , the control signal P 1  changes to the L level, and the transistor M 2  turns OFF. Then, the self-discharge operation of the transistor M 3  ends at this time point. During the period from this time point to the time t 4 , both the transistors M 2  and M 4  turn OFF, and the M 3 /D quickly changes to be at the L level. Consequently, the voltage of the M 3 /G somewhat drops owing to the drain-to-gate capacitor of the transistor M 3  and the like as illustrated in  FIG. 14 . 
     Next, at the time t 4  when the control signal P 2  changes to the H level, the transistor M 4  turns ON, and the M 3 /D again rises. Consequently, the voltage of the M 3 /G again rises to return to the almost original state as illustrated in  FIG. 14 . At this time point, because the voltage of the M 3 /G is a voltage Vrsa in the neighborhood of its own threshold voltage Vth, the current of the M 3 /D is almost zero. In an effective period of the video signal video from the time t 1  to a time t 7 , the sampling signal SPa, which is a horizontal sampling signal group, is generated, but the sampling signal SPb is not generated. 
     Next, in a period of from a time t 5  to a time t 6 , by the horizontal sampling signal SPa of a column corresponding to the period, the voltage of the M 3 /G changes from the voltage Vrsa in the neighborhood of its own threshold value Vth by a voltage AV 1  according to a video signal level d 1  based on the blanking level Vb 1 . The voltage AV 1  can be roughly expressed by AV 1 =d 1 ×C 1 /(C 1 +C 2 +C(M 3 )). The C(M 3 ) denotes gate input capacitor of the transistor M 3 . At this time, the drive current Id of the transistor M 3  is expressed by: Id=β×ΔV 2  (where β denotes a drive coefficient, and ΔV=Vgs−Vth). After that, when the corresponding sampling signal SPa changes to the L level, the transistor M 1  turns OFF, and the voltage of the M 3 /G changes to the voltage Va 2 , which somewhat drops owing to the parasitic capacitor operation of the transistor M 1 , and the voltage again becomes the held state. 
     After shifting to the next horizontal scanning period, at the time t 7 , the input video signal video has become the blanking level Vb 1 , and the sampling signal SPb and the control signals P 2 , P 3 , P 5 , and P 6  change to the H, L, H, H, and L levels, respectively. A drive current Ia 2  of the transistor M 3  driven by the voltage Va 2  of the M 3 /G is output as the current signal i (data) in place of the current Ib 1  of the M 9 /D. 
     In a period of from that time to a time t 13 , a voltage Vb 2  of the M 9 /G, which voltage Vb 2  is increased from a voltage (Vrsb) in the neighborhood of the own threshold voltage Vth by a voltage ΔV 2  corresponding to a video signal level d 2  based on the blanking level Vb 1 , is sampled and held by the operation similar to the one mentioned above. And then at the time t 13 , the current signal i (data) is changed from the drive current Ia 2  of the transistor M 3  mentioned above to a drive current Ib 2  of the transistor M 9 , which drive current Ib 2  is driven by the voltage Vb 2  of the M 9 /G. 
     When the operation has shifted to the further next horizontal scanning period, after the time t 13  on, a voltage Va 3  of the M 9 /G, which voltage Va 3  is increased from a voltage (Vrsa) in the neighborhood of the own threshold voltage Vth by a voltage ΔV 3  corresponding to a video signal level d 3  based on the blanking level, is sampled and held by the operation similar to the one mentioned above. 
     However, because the aforesaid column current generation circuit used in the conventional display apparatus uses NMOS transistors as current drive transistors for the generation of column currents, characteristic variations of their voltage-current converting characteristics among elements are larger in comparison with those of PMOS transistors. In particular, the variations of the drive currents Id caused by the drive coefficient β among the voltage-current converting characteristics expressed by the formula Id=β×(Vgs−Vth) 2  are not settled by the conventional circuits, such as the column current generation circuit  1  disclosed in the U.S. Pat. No. 7,126,564 mentioned above. Consequently, current values supplied to EL elements vary every column of pixel circuits, and then the light emission luminance of the EL elements varies every column. In the worst case, the variations appear as vertical line noises on a display area, and the vertical line noises are one of the primary factors of image quality deteriorations. Consequently, the settlement of the variations of the current values has been desired. 
     SUMMARY OF THE INVENTION 
     It is an object of the present invention to suppress the changes of drive currents owing to the variations of the characteristics of current drive transistors for the generation of column currents, and to decrease vertical line noises in a display area for improving an image quality. 
     In order to achieve the object mentioned above, the present invention is first a voltage-current converting method converting an input voltage signal into a current signal and outputting the current signal, the method comprising the steps of: connecting a source of a PMOS transistor to a first power source and to a signal input terminal via a coupling capacitor and connecting a gate thereof and a drain thereof to a second power source to flow a current between the source and the drain of the PMOS transistor while a constant voltage being applied to the signal input terminal, thereby charging a holding capacitor connected between the gate and the source of the PMOS transistor; disconnecting the source of the PMOS transistor from the first power source, thereby discharging the holding capacitor through the PMOS transistor; disconnecting the drain of the PMOS transistor from the second power source and supplying the input voltage signal from the signal input terminal to the holding capacitor via the coupling capacitor; and disconnecting the coupling capacitor from the signal input terminal and the gate of the PMOS transistor from the second power source, connecting the drain of the PMOS transistor to the second power source the source thereof to an output terminal, thereby outputting the current signal. 
     Moreover, the present invention is second voltage-current converting circuit converting an input voltage signal into a current signal and outputting the current signal, the circuit comprising: a PMOS transistor, a coupling capacitor connected between a signal input terminal and a source of the PMOS transistor a holding capacitor connected between a gate and the source of the PMOS transistor; a first switching element connecting an input terminal of the voltage signal to the coupling capacitor; a second switching element connecting the source of the PMOS transistor to a first power source; a third switching element connecting a drain of the PMOS transistor to a second power source; a fourth switching element connecting the source of the PMOS transistor to an output terminal of the current signal; and a fifth switching element connecting the gate of the PMOS transistor to the second power source. 
     The present invention is third an active matrix type display apparatus comprising: a plurality of two-dimensionally arranged display elements to be driven according to input currents; a plurality of pixel circuits supplying the currents to the plurality of display elements to drive the display elements; signal lines for supplying the currents to the plurality of pixel circuits every column; and column current generation circuits outputting the currents to the signal lines according to input voltage signals, wherein each of the column current generation circuits includes: a PMOS transistor, a coupling capacitor connected between a voltage signal input terminal and a source of the PMOS transistor, a holding capacitor connected between a gate and the source of the PMOS transistor; a first switching element connecting the voltage signal input terminal to the coupling capacitor; a second switching element connecting the source of the PMOS transistor to a first power source; a third switching element connecting a drain of the PMOS transistor to a second power source; a fourth switching element connecting the source of the PMOS transistor to one of the signal lines; and a fifth switching element connecting the gate of the PMOS transistor to the second power source. 
     The display elements may be electroluminescence elements. 
     According to the present invention, the changes of drive currents caused by the characteristic variations of the current drive transistors for the generation of a column current can be suppressed, and the vertical line noises in a display area can be decreased to improve image quality. 
     The present invention is especially applied to an active matrix type display apparatus using a current drive type display device. By using the display apparatus, for example, an information display apparatus can be configured. The information display apparatus is formed in any of, for example, a portable telephone (or mobile phone), a portable computer, a still camera, and a video camera. Alternatively, the information display apparatus is an apparatus for realizing a plurality of functions of the apparatus mentioned above. The information display apparatus includes an information input unit. For example, the information input unit of the portable telephone is configured to include an antenna. In the case of a personal digital assistant (PDA) or a portable type personal computer, the information input unit is configured to include an interface unit to a network. In the case of the still camera or a movie camera, the information input unit is configured to include a sensor unit made of a CCD, a CMOS, or the like. 
     Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a circuit diagram illustrating the internal configuration of a column current generation circuit of a display apparatus according to a first exemplary embodiment of the present invention. 
         FIG. 2  is a timing chart for describing the operation of the column current generation circuit in the first exemplary embodiment. 
         FIG. 3  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 1  (pre-charging period) of  FIG. 2 . 
         FIG. 4  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 2  (Vth reset period) in  FIG. 2 . 
         FIG. 5  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 3  (sampling standby period) in  FIG. 2 . 
         FIG. 6  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 4  (sampling period) in  FIG. 2 . 
         FIG. 7  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 5  (current hold period) in  FIG. 2 . 
         FIG. 8  is a circuit diagram for describing the ON/OFF states of the SW transistors at a step S 6  (current output period) in  FIG. 2 . 
         FIG. 9A  is a graph for describing voltage-current conversion variations of an NMOS. 
         FIG. 9B  is a graph for describing voltage-current conversion variations of a PMOS. 
         FIG. 10  is a graph for describing voltage-current conversion characteristics of transistors. 
         FIG. 11  is a block diagram illustrating the whole configuration of a digital still camera system using a display apparatus according to a second exemplary embodiment of the present invention. 
         FIG. 12  is a diagram illustrating the whole configuration of a conventional display apparatus. 
         FIG. 13  is a diagram illustrating the internal configuration of a conventional column current generation circuit. 
         FIG. 14  is a timing chart for describing the operation of the conventional column current generation circuit. 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     In the following, the exemplary embodiments for implementing an active matrix type display apparatus according to the present invention will be concretely described with reference to the attached drawings. 
     First, a conceptional point of the present invention will be described. 
       FIGS. 9A ,  9 B, and  10  are for describing voltage-current conversion characteristics of current drive transistors and their variations. 
       FIGS. 9A and 9B  illustrate the cases of using an NMOS transistor and a PMOS transistor, respectively. The ordinate axes in the figures illustrate the drive currents (drain currents) Id (ΔV) between sources and drains when voltages ΔV are applied between gates and the sources, and the abscissa axes illustrate arrangement positions (column numbers) in column directions of column current generation circuits.  FIG. 10  illustrates the characteristics of the drain currents Id to the gate-to-source voltages Vgs of an NMOS transistor and a PMOS transistor. 
     From these figures, it is found that the change variations of the drive current Id of a PMOS transistor are smaller than those of an NMOS transistor, and that the voltage-current conversion characteristic of the PMOS transistor is superior to that of the NMOS transistor. The reason can be considered as follows. That is, it is supposed that the variation of the mobility of electrons, which determines the mobility of a NMOS transistor, is denoted by Δ 1 . The movements of holes, which are the carriers of a PMOS transistor, are achieved by the participation of the mobility of a plurality (N) of electrons. If the variation of the movement of each electron is supposed to be the same in the movement of a hole of the PMOS transistor, a square-root law can be applied to the movement, and the variations of the mobility of the PMOS transistor become the 1/√N of those of the NMOS transistor. 
     Accordingly, the present invention aims at the following points. First, 1) the current drive transistors of the column current generation circuits are composed of PMOS transistors, which have smaller characteristic variations. Next, 2) in order to operate the input video signals of the column current generation circuits in the positive polarity similarly to the configuration of the conventional NMOS drive current transistors, currents are programmed to the source sides of the PMOS drive current transistors. And then, 3) the transistors for switching (SW) of the column current generation circuits are adapted to be able to be composed of the NMOS transistors, which have fewer leaks, similarly to the configurations of the conventional NMOS drive transistors. 
     That is, the active matrix type display apparatus according to the present invention is basically configured to arrange predetermined signal lines and pixel circuits, both being for supplying a current to each of display elements arranged in two dimensions. In this configuration, a voltage is generated between the control electrode (gate) of a PMOS transistor and the main electrode (source) having higher electric potential according to an input video signal, and the generated voltage is held by a capacitor. Thereby, a current group (current signals) is generated from the main electrodes of the PMOS transistors having higher electric potential, and the current group is supplied to the signal line of each column. 
     In such a way, by adapting the column current generating drive transistors using the PMOS transistors having smaller characteristic variations to adapt a circuit configuration so that the circuit configuration may be positive polarity input and positive polarity output, the changes of the drive current Id can be suppressed, and the vertical line noises can be decreased to improve the image quality. 
     In the following, exemplary embodiments embodying the present invention will be described. 
     First Exemplary Embodiment 
     The present exemplary embodiment is the one in which the present invention is applied to a column current generation circuit of an active matrix type display apparatus using EL elements. Because the whole configuration of the active matrix type display apparatus used for the present exemplary embodiment is the same as that of the prior art illustrated in  FIG. 12 , the description of the whole configuration is omitted. 
       FIG. 1  illustrates the whole configuration of a column current generation circuit  1  of the present exemplary embodiment. 
     The column current generation circuit  1  illustrated in  FIG. 1  is a current-voltage converting circuit receiving the input of a video signal video as an input voltage signal and converting the received video signal video into a current signal to alternately output from the sources of drive transistors M 5   a  and M 5   b  as a current signal. 
     The column current generation circuit  1  is composed of 2 systems of current converting circuits including connection points a and b, respectively, and each of the current converting circuits includes five NMOS transistors, that is, M 1   a , M 3   a , M 4   a , M 6   a , and M 7   a , and M 1   b , M 3   b , M 4   b , M 6   b , and M 7   b , and two PMOS transistors, that is, M 2   a  and M 5   a , and M 2   b  and M 5   b , respectively. 
     Each of the NMOS transistors M 1   a , M 3   a , M 4   a , M 6   a , M 7   a , M 1   b , M 3   b , M 4   b , M 6   b , and M 7   b  is adapted to a switching (SW) transistor, which turns ON or OFF the current path between the source thereof and the drain thereof according to a control signal (of the L level or the H level) applied to the gate thereof. Each of the transistors M 2   a  and M 2   b  among the PMOS transistors M 2   a , M 5   a , M 2   b , and M 5   b  is adapted to a transistor of a current source, the source and the drain of which are short-circuited to form a diode connection. Moreover, each of the transistors M 5   a  and M 5   b  is adapted to a current drive transistor, which generates a drain current (drive current) Id between the source thereof and the drain thereof according to a gate-to-source voltage Vgs applied to the gate thereof. As described above, the present exemplary embodiment uses the PMOS transistors M 5   a  and M 5   b  as the current drive transistors of the column current generation circuit  1 . 
     Moreover, capacities C 1   a  and C 1   b  are coupling capacitor transmitting the signal line voltages of the video signal video to the sources of the current drive transistors M 5   a  and M 5   b . Moreover, capacities C 2   a  and C 2   b  are holding capacities for regulating the gate-to-source voltages Vgs of the transistors M 5   a  and M 5   b . The gate-to-source voltage Vgs of the transistor M 5   a  corresponds to the electric potential at the connection point a between the capacities C 1   a  and C 2   a , which electric potential is determined by the ratio of the capacitors C 1   a  and C 2   a . Similarly, the gate-to-source voltage Vgs of the transistor M 5   b  corresponds to the electric potential at the connection point b between the capacitors C 1   b  and C 2   b , which electric potential is determined by the ratio of the capacitors C 1   b  and C 2   b.    
     Moreover, the wiring of a pair of power sources, that is, the wiring of a first power source, a voltage VCC, and the wiring of a second power source, ground potential GND, is connected to the column current generation circuit  1 . Moreover, the column current generation circuit  1  is connected to the signal line of the video signal video, the signal lines of the sampling signals SPa and SPb, the signal lines of the control signals P 1 -P 8 , and the signal line (data line) of a current signal data. 
     The signal line of the video signal video is connected to the sources of the transistors M 1   a  and M 1   b , which are signal input terminals. The signal lines of the sampling signals SPa and SPb are connected to the gates of the transistors M 1   a  and M 1   b , respectively, in parallel to each other. The signal lines of the control signals P 1 -P 8  are connected to the gates of the transistors M 3   a , M 4   a , M 6   a , M 7   a , M 3   b , M 4   b , M 6   b , and M 7   b , respectively. 
     The drain of the transistor M 1   a  is connected to one terminal of the capacitor C 1   a . The other terminal of the capacitor C 1   a  is connected to the connection point a between the one terminal of the capacitor C 2   a  and the source of the transistor M 3   a  and a connection point between the sources of the transistors M 6   a  and M 5   a . The drain of the transistor M 3   a  is connected to the drain and the gate of the diode-connected transistor M 2   a . The source of the transistor M 2   a  is connected to the wiring of the power source voltage VCC. The other terminal of the capacitor C 2   a  is connected to the gate of the transistor M 5   a  and the drain of the transistor M 4   a . The drain of the transistor M 5   a  is connected to the drain of the transistor M 7   a . The sources of the transistors M 4   a  and M 7   a  are connected to the wiring of the ground potential GND. The drain of the transistor M 6   a  is connected to the signal line of the current signal data. 
     Similarly, the drain of the transistor M 1   b  is connected to one terminal of the capacitor C 1   b . The other terminal of the capacitor C 1   b  is connected to the connection point b between one terminal of the capacitor C 2   b  and the source of the transistor M 3   b  and a connection point between the sources of the transistors M 6   b  and M 5   b . The drain of the transistor M 3   b  is connected to the drain and the gate of the diode-connected transistor M 2   b . The source of the transistor M 2   b  is connected to the wiring of the power source voltage VCC. The other terminal of the capacitor C 2   b  is connected to the gate of the transistor M 5   b  and the drain of the transistor M 4   b . The drain of the transistor M 5   b  is connected to the drain of the transistor M 7   b . The sources of the transistors M 4   b  and M 7   b  are connected to the wiring of the ground potential GND. The drain of the transistor M 6   b  is connected to the signal line of the current signal data. 
       FIG. 2  is a time chart for describing the operation of the column current generation circuit  1  of  FIG. 1 .  FIG. 2  illustrates the operation for two horizontal scanning periods of a video signal, or for two lines of an EL panel. In the following description, the operation for one line of the EL panel of the operations for the two lines of the EL panel will be described. 
     First, at a step S 1 , which is equivalent to the period between the times t 1  and t 2  of  FIG. 14 , the charging of the holding capacitor C 2   a  is performed. 
     In the period at the step S 1 , a constant voltage as the video signal video is supplied. The constant voltage is a video voltage level in a blanking period. 
     The sampling signal SPa, the control signals P 1 , P 2 , P 3 , and P 4  are the H, H, H, L, and H levels, respectively. Consequently, the SW transistors M 1   a , M 3   a , M 4   a , M 6   a , and M 7   a  are ON, ON, ON, OFF, and ON, respectively. 
     At this time, because the transistor M 1   a  is ON, the video voltage of the blanking period of the video signal video is supplied to the gate of the transistor M 5   a  through the capacities C 1   a  and C 2   a . Moreover, because the transistors M 4   a  and M 7   a  are ON, the gate and the drain of the transistor M 5   a  are short-circuited with each other through the ground potential GND, and the diode connection of the transistor M 5   a  is formed. Then, because the transistor M 3   a  is ON, a current is supplied from the power source voltage VCC to the transistor M 5   a , which is in the state of the diode connection, through the diode-connected transistor M 2   a.    
     The capacities C 1   a  and C 2   a  are charged by the current, and the gate-to-source voltage Vgs of the transistor M 5   a  rises. This state is illustrated in  FIG. 3 . The period is hereinafter referred to as a “pre-charging period.” In the pre-charging period, because the transistor M 6   a  is OFF, the drive current Id of the transistor M 5   a  is not output to the signal line of the current signal data. 
     Next, at a step S 2 , which is equivalent to the period from the time t 2  to the time t 3  of  FIG. 14 , the charges of the holding capacitor C 2   a  are discharged. 
     At the period of the step S 2 , the control signal P 1  changes to the L level, and the transistor M 3   a  turns OFF. The source of the transistor M 5   a  is thereby separated from the power source voltage VCC, and the charging operations of the capacities C 1   a  and C 2   a  stop. Then, the operation of the self-discharge of the charges accumulated in the capacitor C 2   a  through the transistor M 5   a  is started. The discharge is performed until the gate-to-source voltage Vgs of the transistor M 5   a , that is, the electric potential at the connection point a between the capacities C 1   a  and C 2   a , reaches a level in the neighborhood of the threshold voltage Vth of the transistor M 5   a . Consequently, the gate-to-source voltage Vgs of the transistor M 5   a  is reset so that the gate-to-source voltage Vgs may take the level in the neighborhood of the threshold value Vth when the video signal video is the video voltage in the blanking period. This state is illustrated in  FIG. 4 . Hereinafter the period is referred to as a “Vth reset period.” Also in the Vth reset period, because the transistor M 6   a  is OFF, the drive current Id of the transistor M 5   a  is not supplied to the signal line of the current signal data. 
     Next, in the period of a step S 3 , which is equivalent to the period from the time t 4  to the time t 5  in  FIG. 14 , the video signal is sampled by the other columns. 
     In the period at the step S 3 , the sampling signals SPa and the control signal P 4  change to the L levels, and the transistors M 1   a  and M 7   a  turn OFF. Consequently, because the transistor M 1   a  is OFF, the signal input terminal is opened, and the supply of the video signal video is intercepted. On the other hand, because the transistor M 7   a  is OFF, the drain of the transistor M 5   a  is opened, and the transistor M 5   a  becomes a state in which the drain current thereof does not flow. This state is illustrated in  FIG. 5 . 
     The electric potential at the connection point a maintains the level in the neighborhood of the threshold value Vth, which level is the one at the time of being reset as above. 
     Hereinafter the period is referred to as a “sampling standby period.” Also in the sampling standby period, because the transistor M 6   a  is OFF, the drive current Id of the transistor M 5   a  is not output to the signal line of the current signal data. 
     Next, at a step S 4 , which is equivalent to the period from the time t 5  to the time t 6  of  FIG. 14 , the video signal is sampled, and is held by the holding capacitor C 2   a.    
     In the period at the step S 4 , the horizontal sampling signal SPa of a corresponding column in one horizontal scanning period changes to the H level, and the transistor M 1   a  turns ON. Consequently, the video signal video is supplied to the source of the transistor M 5   a  through the transistor M 1   a  and the capacitor C 1   a . This state is illustrated in  FIG. 6 . 
     Because the voltage of the signal input terminal has changed from the voltage during the blanking period to a video signal voltage, the electric potential at the connection point a between the capacities C 1   a  and C 2   a  rises from the value in the neighborhood of the threshold value Vth by a value obtained by performing the capacitor division of a voltage change at the input terminal by the capacities C 1   a  and C 2   a . The gate-to-source voltage Vgs of the transistor M 5   a  becomes the voltage equal to the threshold voltage Vth added by (the capacitor division voltage of) the input signal voltage according to the voltage rise at the connection point a from the value in the neighborhood of the threshold value Vth. 
     In such a way, the video voltage of the video signal video at the corresponding column is sampled through the capacities C 1   a  and C 2   a . Hereinafter this period is referred to as a “sampling period.” Also in the sampling period, because the transistor M 6   a  is OFF, the drive current Id of the transistor M 5   a  is not output to the signal line of the current signal data. 
     Next, at a step S 5 , which is equivalent to the period from the time t 6  to the time t 7  in  FIG. 14 , the column current generation circuit  1  stands by until the sampling of all the columns has been completed. 
     In the period at the step S 5 , the sampling signal SPa changes to the L level, and the transistor M 1   a  turns OFF to make the signal input terminal an opened state. Thereby, the gate-to-source voltage Vgs of the transistor M 5   a  corresponding to the video voltage of the video signal video sampled as above is maintained, and the drive current Id caused by the gate-to-source voltage Vgs of the transistor M 5   a  is held in the circuit. This state is illustrated in  FIG. 7 . Hereinafter this period is referred to as a “current hold period.” Also in the current hold period, because the transistor M 6   a  is OFF, the drive current Id of the transistor M 5   a  is not output to the signal line of the current signal data. 
     Next, at a step S 6 , which is equivalent to the period from the time t 7  to the time t 13  in  FIG. 14 , the current signal is output. 
     In the period at the step S 6 , the control signal P 2  changes to the L level, and the transistors M 6   a  and M 7   a  change to the H levels. Then, the transistors M 4   a , M 6   a , and M 7   a  turn OFF, ON, and ON, respectively. Thereby, the gate of the transistor M 5   a  is separated from the ground potential GND, and the drain thereof is in turn connected to the ground electric potential GND. This state is illustrated in  FIG. 8 . 
     Because the gate is separated from the ground electric potential GND, the voltage of the capacitor C 2   a  is maintained to the gate-to-source voltage Vgs determined at the step S 4 , and the drive current Id is generated between the source and the drain of the transistor M 5   a  according to the gate-to-source voltage Vgs. The drive current Id is expressed as follows: Id=β×(Vgs−Vth) 2  (β: drive coefficient). Because the gate-to-source voltage Vgs is the one equal to the threshold value Vth added by the signal voltage subjected to the capacitor division, the variations of the threshold values Vth is cancelled in the drive current Id, and consequently a current according to the signal voltage is generated. The drive current Id of the transistor M 5   a  is output from the source side to the signal line of the current signal data through the transistor M 6   a.    
     Hereinafter this period is referred to as a “current output period.” The current output period is maintained until the next horizontal scanning period ends. In the next horizontal scanning period, the sampling signal SPb changes to the H level, and the transistor M 1   b  turns ON. Then, each of the operations in the pre-charging period, the Vth reset period, the sampling standby period, the sampling period, the current hold period, and the current output period is performed on the transistor M 5   b  side similarly to on the transistor M 5   a  side. 
     As described above, the present exemplary embodiment uses PMOS transistors, which have small characteristic variations as the current drive transistors in the column current generation circuit  1 . Moreover, because the present exemplary embodiment operates the input video signal into the column current generation circuit  1  in positive polarity similarly in the configuration of the conventional NMOS drive current transistors, the present exemplary embodiment programs the currents on the source sides of the PMOS drive current transistors. Furthermore, the present exemplary embodiment is adapted to be able to configure the SW transistors in the column current generation circuit  1  using NMOS transistors, which have fewer leaks, similarly in the configuration of the conventional NMOS drive transistors. 
     By this configuration, the present exemplary embodiment turns on the transistor M 1   a  to supply the video signal video to the gate of the transistor M 5   a  through the holding capacities C 1   a  and C 2   a , and turns on the transistor M 3   a  in the state in which the transistor M 5   a  is diode-connected to supply the current from the power source voltage VCC. Next, the present exemplary embodiment turns off the transistor M 3   a  to intercept the supply of the current, and thereby resets the capacities C 1   a  and C 2   a  so that the gate voltage of the transistor M 5   a  may become the threshold voltage Vth. Next, the present exemplary embodiment turns off the transistor M 7   a  to intercept the current path between the drain of the transistor M 5   a  and the ground potential GND, and in this state, the present exemplary embodiment turns on the transistor M 5   a  to supply the video signal to the gate of the transistor M 5   a  through the capacities C 1   a  and C 2   a . Next, the present exemplary embodiment turns on the transistor M 6   a  to form a current path between the transistor M 5   a  and the signal line data, and outputs the current generated between the source and the drain of the transistor M 5   a  from the source side to the signal line data. 
     Consequently, according to the present exemplary embodiment, the current drive transistor are composed of the PMOS transistors, which have smaller characteristic variations, and the circuit configuration is constructed so as to be positive polarity input and positive polarity output. Consequently, the present exemplary embodiment can suppress the changes of the drive current Id, and can decrease the vertical line noises to improve the image quality. 
     Second Exemplary Embodiment 
     The present exemplary embodiment is an example of using the display apparatus described above into electric equipment. 
       FIG. 11  is a block diagram of an example of a digital still camera system of the present exemplary embodiment. The figure illustrates a digital still camera system  50 , an image capture unit  51 , an image signal processing circuit  52 , a display panel  53 , a memory  54 , a CPU  55 , and an operation unit  56 . 
     In  FIG. 11 , an image photographed by the image capture unit  51  or an image recorded in the memory  54  is subjected to the signal processing by the image signal processing circuit  52  to be able to be seen on the display panel  53 . The CPU  55  controls the image capture unit  51 , the memory  54 , the image signal processing circuit  52 , and the like based on an input from the operation unit  56  to perform photographing, recording, reproducing, and display that are suitable to a situation. Moreover, the display panel  53  can be used as a display unit of various kinds of electric equipment besides. 
     Although the display apparatus using the EL elements have been described as examples in the exemplary embodiments mentioned above, the present invention is not limited to the display apparatus. For example, the present invention can be applied to a current drive type display apparatus, such as a plasma display panel (PDP) and a field emission display (FED). 
     While the present invention has been described with reference to the exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions. 
     This application claims the benefit of Japanese Patent Application No. 2006-181668, filed Jun. 30, 2006 which is hereby incorporated by reference herein in its entirety.