Patent Publication Number: US-9852946-B1

Title: Self aligned conductive lines

Description:
BACKGROUND 
     The present invention generally relates to complimentary metal-oxide semiconductors (CMOS) and metal-oxide-semiconductor field-effect transistors (MOSFET), and more specifically relates to conductive lines used in semiconductor devices. 
     The MOSFET is a transistor used for switching electronic signals. The MOSFET has a source, a drain, and a gate electrode. The gate is electrically insulated from the main semiconductor n-channel or p-channel by a thin layer of insulating material, for example, silicon dioxide or high dielectric constant (high-k) dielectrics, which makes the input resistance of the MOSFET relatively high. The gate voltage controls whether the path from drain to source is an open circuit (“off”) or a resistive path (“on”). 
     N-type field effect transistors (nFET) and p-type field effect transistors (pFET) are two types of complementary MOSFETs. The nFET uses electrons as the current carriers and includes n-doped source and drain junctions. The pFET uses holes as the current carriers and includes p-doped source and drain junctions. 
     The FinFET is a type of MOSFET. The FinFET is a multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The word “fin” refers to a generally fin-shaped semiconductor structure patterned on a substrate that often has three exposed surfaces that form the narrow channel between source and drain regions. A thin dielectric layer arranged over the fin separates the fin channel from the gate. Because the fin provides a three dimensional surface for the channel region, a larger channel length may be achieved in a given region of the substrate as opposed to a planar FET device. 
     Gate spacers form an insulating film along gate sidewalls. Gate spacers may also initially be formed along sacrificial gate sidewalls in replacement gate technology. The gate spacers are used to define source/drain regions in active areas of a semiconductor substrate located adjacent to the gate. 
     Device scaling in the semiconductor industry reduces costs, decreases power consumption, and provides faster devices with increased functions per unit area. Improvements in optical lithography have played a major role in device scaling. However, optical lithography has limitations for minimum dimensions and pitch, which are largely determined by the wavelength of the irradiation. 
     SUMMARY 
     According to an embodiment of the present invention, a method for forming conductive lines on a semiconductor wafer comprises forming a first hardmask on an insulator layer, a planarizing layer on the first hardmask, a second hardmask on the planarizing layer and a layer of sacrificial mandrel material on the second hardmask. Portions of the layer of sacrificial mandrel material are removed to expose portions of the second hardmask and form a first sacrificial mandrel and a second sacrificial mandrel on the second hardmask. Spacers are formed adjacent to sidewalls of the first sacrificial mandrel and sidewalls of the second sacrificial mandrel. A filler material is deposited on the second hardmask between the first sacrificial mandrel and the second sacrificial mandrel and a first mask is formed on a portion of the second sacrificial mandrel. Exposed portions of the first sacrificial mandrel and the second sacrificial mandrel are removed to form a first cavity and a second cavity that expose portions of the second hardmask and the first mask is removed. A second mask is deposited that fills the first cavity and the second cavity, and a resist mask is formed over a portion of the filler material. Exposed portions of the second mask and exposed portions of the filler material are removed to expose portions of the first hardmask. The resist mask and exposed portions of the first hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The planarizing layer, the second hardmask, the filler material, the sacrificial mandrel, and the spacers are removed to expose the first hardmask. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material. 
     According to another embodiment of the present invention, a method for forming conductive lines on a semiconductor wafer comprises forming a first hardmask on an insulator layer, a first planarizing layer on the first hardmask, a second hardmask on the first planarizing layer, and a first mask on the second hardmask. Exposed portions of the second hardmask are removed to expose portions of the first planarizing layer. A third hardmask is formed on the first hardmask and the exposed portions of the first planarizing layer. A layer of sacrificial mandrel material is formed on the third hardmask and a fourth hardmask is formed on the layer of sacrificial mandrel material. A second mask is formed on the fourth hardmask. Exposed portions of the fourth hardmask and the layer of sacrificial mandrel material are removed to expose portions of the third hardmask and form a first sacrificial mandrel and a second sacrificial mandrel. Spacers are formed adjacent to sidewalls of the first sacrificial mandrel and sidewalls of the second sacrificial mandrel and a second planarizing layer is formed adjacent to the spacers. Exposed portions of the first sacrificial mandrel and the second sacrificial mandrel are removed to form a first cavity and a second cavity. A depth of the first cavity and a depth of the second cavity are increased by removing exposed portions of the third hardmask, the second hardmask, and the first planarizing layer to expose portions of the first hardmask. Exposed portions of the first hardmask are removed to expose portions of the insulator layer. Exposed portions of the insulator layer are removed to form a first trench and a second trench. The first hardmask is removed, and the first trench and the second trench are filled with a conductive material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1-18  illustrate an exemplary embodiment of a method for forming conductive lines for a semiconductor device. 
         FIG. 1  illustrates a side view of a structure formed on a substrate. 
         FIG. 2  illustrates a side view following an etching process that selectively removes exposed portions of the sacrificial mandrel layer. 
         FIG. 3  illustrates a top view of the patterned resist arranged on the second hardmask. 
         FIG. 4  illustrates a side view following the deposition of a layer of spacer material over exposed portions of the second hardmask and the sacrificial mandrels. 
         FIG. 5  illustrates a side view following the formation of spacers along sidewalls of the sacrificial mandrels. 
         FIG. 6A  illustrates a side view following the formation of a non-mandrel lines over exposed portions of the second hardmask. 
         FIG. 6B  illustrates a top view of the sacrificial mandrels, the spacers, and the non-mandrel lines. 
         FIG. 7A  illustrates a cut-away view along the line A-A (of  FIG. 7B ) following the formation of a photolithographic mask. 
         FIG. 7B  illustrates a top view of the mask. 
         FIG. 8  illustrates a cut-away view following a selective etching process that removes exposed portions of the sacrificial mandrel. 
         FIG. 9  illustrates a top view of the resultant structure following the removal of the mask. 
         FIG. 10A  illustrates a cut-away view following the deposition of a mask that fills the cavities. 
         FIG. 10B  illustrates a top view of the pillar resist, where a portion of the mask has not been shown for clarity. 
         FIG. 11A  illustrates a cut-away view along the line A-A (of  FIG. 11B ) following a selective etching process. 
         FIG. 11B  illustrates a top view following the selective etching process described above. 
         FIG. 12  illustrates a cut-away view following a selective etching process that removes exposed portions of the underlying second hardmask. 
         FIG. 13  illustrates a cut-away view following a selective anisotropic etching process that removes exposed portions of the organic planarization layer. 
         FIG. 14  illustrates a cut-away view following another selective anisotropic etching process that removes exposed portions of the first hardmask. 
         FIG. 15  illustrates a cut-away view of the resultant structure following the removal of the organic planarization layer, the second hardmask, the spacers, the non-mandrel line, and the sacrificial mandrel. 
         FIG. 16  illustrates a cut-away view following a selective etching process. 
         FIG. 17  illustrates a cut-away view following the deposition of a conductive material. 
         FIG. 18A  illustrates a cut-away view along the line A-A (of  FIG. 18B ) following a planarization process. 
         FIG. 18B  illustrates a top view of the resultant structure following the formation of the conductive lines. 
         FIGS. 19-38B  illustrate another exemplary embodiment of a method for forming conductive lines for a semiconductor device. 
         FIG. 19  illustrates a side view of a structure formed on a substrate. 
         FIG. 20A  illustrates a cut-away view along the line A-A (of  FIG. 20B ) view following the patterning and deposition of a mask. 
         FIG. 20B  illustrates a top view of the mask. 
         FIG. 21A  illustrates a cut-away view along the line A-A (of  FIG. 21B ) following an anisotropic etching process. 
         FIG. 21B  illustrates a top view of the second hardmask arranged on the organic planarization layer. 
         FIG. 22  illustrates a cut-away view following the deposition of a third hardmask over exposed portions of the organic planarizing layer. 
         FIG. 23A  illustrates a cut-away view along the line A-A (of  FIG. 23B ) following the patterning and deposition of a photolithographic resist. 
         FIG. 23B  illustrates a top view of the resist arranged on the fourth hardmask. 
         FIG. 24  illustrates a cut-away view of the resultant structure following a selective etching process. 
         FIG. 25  illustrates a cut-away view following the deposition of a layer of spacer material over the exposed portions of the third hardmask 
         FIG. 26  illustrates a cut-away view following an anisotropic etching process such as, for example, reactive ion etching. 
         FIG. 27  illustrates a cut-away view following the deposition of a second organic planarization layer. 
         FIG. 28  illustrates a cut-away view following an etching or planarization process that removes portions of the second organic planarization layer. 
         FIG. 29A  illustrates a cut-away view along the line A-A (of  FIG. 29C ) following a selective etching process that removes exposed portions of the sacrificial mandrels. 
         FIG. 29B  illustrates a cut-away view along the line B-B (of  FIG. 29C ) of the cavities. 
         FIG. 29C  illustrates a top view of the cavities. 
         FIG. 30  illustrates a cut-away view following a selective anisotropic etching process such as, for example, reactive ion etching. 
         FIG. 31  illustrates a cut-away view following a selective anisotropic etching process. 
         FIG. 32  illustrates a cut-away view following another selective anisotropic etching process. 
         FIG. 33  illustrates a cut-away view following another anisotropic etching process that removes non-obscured regions of the organic planarizing layer. 
         FIG. 34A  illustrates a cut-away view along the line A-A (of  FIG. 34B ) of the resultant structure following an anisotropic etching process that removes exposed portions of the first hardmask. 
         FIG. 34B  illustrates a top view of the first hardmask arranged on the inter-level dielectric layer. 
         FIG. 35  illustrates a cut-away view following a selective anisotropic etching process. 
         FIG. 36  illustrates a cut-away view following a selective etching process that removes the first hardmask (of  FIG. 35 ). 
         FIG. 37  illustrates a cut-away view following the deposition of a conductive material. 
         FIG. 38A  illustrates a cut-away view along the line A-A (of  FIG. 38B ) following a planarization process. 
         FIG. 38B  illustrates a top view of the conductive lines arranged in the inter-level dielectric layer. 
     
    
    
     DETAILED DESCRIPTION 
     Conductive connections in semiconductor devices and integrated circuits often include conductive lines that are arranged in trenches formed in an insulating material. The conductive lines connect to devices in the circuit. Integrated circuits often have multiple layers of devices and conductive lines arranged on one or more wafers. Conductive vias are used to form electrical connections between different layers of an integrated circuit. 
     As the scale of semiconductor devices continues to decrease, aligning and patterning conductive lines in desired locations on the chip continues to become more challenging. Typically, in an integrated circuit having trenches filled with conductive material to form conductive lines, it is desirable to pattern the trenches using a self-alignment method to avoid misalignments. As the pitch of the trenches or lines scales down, the use of previous patterning methods has not resulted in a desired trench alignment. 
     The embodiments described herein provide for a method for patterning that distinguishes mandrel lines and non-mandrel lines on device during the formation of the conductive lines. The method allows vias to be selectively formed on either mandrel or non-mandrel lines. 
       FIGS. 1-18B  illustrate an exemplary embodiment of a method for forming conductive lines for a semiconductor device. 
       FIG. 1  illustrates a side view of a structure formed on a substrate  103 . The substrate may include, for example, any suitable semiconductor material. 
     Non-limiting examples of suitable materials for the semiconductor layer  103  include Si (silicon), strained Si, SiC (silicon carbide), Ge (germanium), SiGe (silicon germanium), SiGeC (silicon-germanium-carbon), Si alloys, Ge alloys, III-V materials (e.g., GaAs (gallium arsenide), InAs (indium arsenide), InP (indium phosphide), or aluminum arsenide (AlAs)), II-VI materials (e.g., CdSe (cadmium selenide), CdS (cadmium sulfide), CdTe (cadmium telluride), ZnO (zinc oxide), ZnSe (zinc selenide), ZnS (zinc sulfide), or ZnTe (zinc telluride)), or any combination thereof. Other non-limiting examples of semiconductor materials include III-V materials, for example, indium phosphide (InP), gallium arsenide (GaAs), aluminum arsenide (AlAs), or any combination thereof. The III-V materials may include at least one “III element,” such as aluminum (Al), boron (B), gallium (Ga), indium (In), and at least one “V element,” such as nitrogen (N), phosphorous (P), arsenic (As), antimony (Sb). 
     Semiconductor devices  105  are arranged on the substrate  103 . The semiconductor devices  105  may include, for example, MOSFET or other types of electronic devices. A layer of insulating material  101  such as, for example, an oxide material is arranged over the substrate  103  and the semiconductor devices  105 . A conductive line  102  is arranged on the layer of insulating material  101 . The conductive line  102  may include a conductive metallic material such as, for example, copper, aluminum, silver, gold, or another suitable conductive material. 
     One or more of the semiconductor devices  105  may be electrically connected to the conductive line  102 . In the illustrated exemplary embodiments described herein a method for forming conductive lines that may connect with vias to the underlying conductive line  102  will be described. 
       FIG. 1  further includes an inter-level dielectric layer (insulator layer)  104  arranged on the conductive line  102 . In the illustrated exemplary embodiment, the insulator layer  104  is an inter-level dielectric layer. 
     The inter-level dielectric layer  104  is formed from, for example, a low-k dielectric material (with k&lt;4.0), including but not limited to, silicon oxide, spin-on-glass, a flowable oxide, a high density plasma oxide, borophosphosilicate glass (BPSG), or any combination thereof. The inter-level dielectric layer  104  is deposited by a deposition process, including, but not limited to CVD, PVD, plasma enhanced CVD, atomic layer deposition (ALD), evaporation, chemical solution deposition, or like processes. Following the deposition of the inter-level dielectric layer  104 , a planarization process such as, for example, chemical mechanical polishing is performed. 
     A first hardmask  106  is arranged on the inter-level dielectric layer  104 . The first hardmask  106  may include, for example, titanium nitride, silicon oxide, silicon nitride (SiN), SiOCN, SiBCN or any suitable combination of those. The first hardmask  106  may be deposited using a deposition process, including, but not limited to, PVD, CVD, PECVD, or any combination thereof. 
     An organic planarization layer (OPL)  108  is arranged on the first hardmask  106 . The OPL  108  may be deposited by, for example, a spin-on process followed by a bake. A second hardmask  110  is arranged on the organic planarization layer  108 . The second hardmask  110  in the illustrated embodiment is similar to the first hardmask  106  however, in alternate exemplary embodiments, the first hardmask  106  and the second hardmask  110  may include dissimilar materials respectively. 
     A sacrificial mandrel layer  112  is arranged on the second hardmask  110 . The sacrificial mandrel layer  112  in the illustrated exemplary embodiment includes an amorphous silicon material, alternate exemplary embodiments may include other materials such as, for example, an amorphous carbon material or a nitride material such as silicon nitride or titanium nitride. 
     A resist  114  is patterned on the sacrificial mandrel layer  112 . Suitable resist masks include photoresists, electron-beam resists, ion-beam resists, X-ray resists and etch resists. The resist may a polymeric spin on material or a polymeric material. 
       FIG. 2  illustrates a side view following an etching process such as, for example, reactive ion etching that selectively removes exposed portions of the sacrificial mandrel layer  112  to expose portions of the second hardmask  110  and form sacrificial mandrels (mandrel lines)  202 . For simplicity and illustrative purposes, the substrate  103 , the semiconductor devices  105 , and the insulator layer  101  have been omitted from  FIG. 2  and subsequent figures. 
       FIG. 3  illustrates a top view of the patterned resist  114  arranged on the second hardmask  110 . 
       FIG. 4  illustrates a side view following the deposition of a layer of spacer material  402  over exposed portions of the second hardmask  110  and the sacrificial mandrels  202 . 
     Non-limiting examples of suitable materials for the layer of spacer material include dielectric oxides (e.g., silicon oxide), dielectric nitrides (e.g., silicon nitride), dielectric oxynitrides, or any combination thereof. The layer of spacer material is deposited by a suitable deposition process, for example, chemical vapor deposition (CVD) or physical vapor deposition (PVD). 
       FIG. 5  illustrates a side view following the formation of spacers  502  along sidewalls of the sacrificial mandrels  202 . Following the deposition of the layer of spacer material, a suitable anisotropic etching process such as, for example, a reactive ion etching process is performed to remove portions of the layer of spacer material and form the spacers  502 . 
       FIG. 6A  illustrates a side view following the formation of a non-mandrel lines  602  over exposed portions of the second hardmask  110 . The non-mandrel lines  602  are formed by, for example, depositing a flowable material such as a carbide material over the second hardmask  110  adjacent to the spacers  502 . Following the deposition of the non-mandrel line material, an etching or planarization process may be performed to define the non-mandrel lines  602 .  FIG. 6B  illustrates a top view of the sacrificial mandrels  202 , the spacers  502 , and the non-mandrel lines  602 . 
     Various materials have been discussed above regarding the sacrificial mandrels  202 , the spacers  502 , and the non-mandrel lines  602  features. In the illustrated exemplary embodiment, the materials used for the sacrificial mandrels  202 , the spacers  502  and the non-mandrel lines  602  are dissimilar materials that provide for selective etching such that each of the features may be selectively removed without substantially removing exposed portions of the remaining two features. 
       FIG. 7A  illustrates a cut-away view along the line A-A (of  FIG. 7B ) following the formation of a photolithographic mask  702  over portions of the sacrificial mandrels  202 , the spacers  502 , and the non-mandrel lines  602 . Suitable masks include photoresists, electron-beam resists, ion-beam resists, X-ray resists, and etch resists. The resist may a polymeric spin on material or a polymeric material.  FIG. 7B  illustrates a top view of the mask  702 . 
     The mask  702  is arranged to expose a portion of a desired sacrificial mandrel  202 . Because the sacrificial mandrel  202  is formed from a material that is dissimilar from the materials used to form the spacers  502  and the non-mandrel lines  602 , the alignment of the mask  702  need only mask sacrificial mandrel  202  material that is not intended to be removed in the subsequent etching process (described below). Thus, the mask  702  may be aligned within a margin of error that is substantially equal to the width of the non-mandrel lines  602  and spacers  502  adjacent to the mandrel line  202  that will be subsequently etched. 
       FIG. 8  illustrates a cut-away view following a selective etching process that removes exposed portions of the sacrificial mandrel  202  (of  FIG. 7A ) and forms a cavity  802 . Following the removal of the exposed sacrificial mandrel  202 , exposed portions of the underlying second hardmask  110 , the organic planarization layer  106  and the first hardmask  106  are removed to expose a portion of the inter-level dielectric layer  104  using an anisotropic etching process. 
       FIG. 9  illustrates a top view of the resultant structure following the removal of the mask  702  (of  FIG. 8 ) using a suitable process such as, for example, ashing. The ashing process may be used to remove a photoresist material, amorphous carbon, or organic planarization (OPL) layer. Ashing is performed using a suitable reaction gas, for example, O2, N2, H2/N2, O3, CF4, or any combination thereof. 
       FIG. 10A  illustrates a cut-away view following the deposition of a mask  1002  that fills the cavities  802  (of  FIG. 8 ). The mask  1002  includes a pillar resist portion  1004  that is arranged over a portion of the non-mandrel line  602   a.    
     The pillar resist portion  1004  is arranged to mask a portion of a desired non-mandrel line  602   a . Because the non-mandrel line  602   a  is formed from a material that is dissimilar from the materials used to form the spacers  502  and the sacrificial mandrel lines  202 , the alignment of the pillar resist  1004  need only mask a portion of the non-mandrel line  602   a  material that is not intended to be removed in the subsequent etching process (described below). Thus, the pillar resist  1004  may be aligned within a region having a margin of error that is substantially equal to the width (d) of the sacrificial mandrels  202  and spacers  502  adjacent to the non-mandrel line  602   a  that will be subsequently etched.  FIG. 10B  illustrates a top view of the pillar resist  1004 , where a portion of the mask  1002  has not been shown for clarity. 
       FIG. 11A  illustrates a cut-away view along the line A-A (of  FIG. 11B ) following a selective etching process that removes exposed portions of the mask  1002  material and the non-mandrel lines  602  (of  FIG. 10A ).  FIG. 11B  illustrates a top view following the selective etching process described above. 
       FIG. 12  illustrates a cut-away view following a selective etching process that removes exposed portions of the underlying second hardmask  110  to expose a portion of the organic planarization layer  108  using an anisotropic etching process. 
       FIG. 13  illustrates a cut-away view following a selective anisotropic etching process that removes exposed portions of the organic planarization layer  108  to expose portions of the first hardmask  106 . 
       FIG. 14  illustrates a cut-away view following another selective anisotropic etching process that removes exposed portions of the first hardmask  106  to expose portions of the inter-level dielectric layer  104 . 
       FIG. 15  illustrates a cut-away view of the resultant structure following the removal of the organic planarization layer  108 , the second hardmask  110 , the spacers  502 , the non-mandrel line  602 , and the sacrificial mandrel  202  (of  FIG. 14 .) 
       FIG. 16  illustrates a cut-away view following a selective etching process such as, for example, reactive ion etching. The etching process forms cavities (trenches)  1602  by removing exposed portions of the inter-level dielectric layer  104 . 
       FIG. 17  illustrates a cut-away view following the deposition of a conductive material  1702  such as, for example, copper, silver, gold, aluminum, or another conductive material into the trenches  1602 . 
       FIG. 18A  illustrates a cut-away view along the line A-A (of  FIG. 18B ) following a planarization process. The planarization process such as, for example, chemical mechanical polishing may be performed to remove overburden material and form conductive lines  1802 . Prior to depositing the conductive material, a liner layer (not shown) may be formed.  FIG. 18B  illustrates a top view of the resultant structure following the formation of the conductive lines  1802 . 
       FIGS. 19-38B  illustrate another exemplary embodiment of a method for forming conductive lines for a semiconductor device. 
       FIG. 19  illustrates a side view of a structure formed on a substrate  103  that is similar to the structure described above in  FIG. 1 . Semiconductor devices  105  are arranged on the substrate  103 , a layer of insulating material  101  is arranged on the semiconductor devices  105  and the substrate  103 . A conductive line  102  is arranged on the layer of insulating material  101 . An inter-level dielectric layer (insulator layer)  104  is arranged on the conductive line  102 . A first hardmask  106  is arranged on the inter-level dielectric layer  104 . An organic planarization layer  108  is arranged on the first hardmask  106  and a second hardmask  110  is arranged on the organic planarization layer  108 . 
       FIG. 20A  illustrates a cut-away view along the line A-A (of  FIG. 20B ) view following the patterning and deposition of a mask  2002  over portions of the second hardmask  110 . For simplicity and illustrative purposes, the substrate  103 , the semiconductor devices  105 , and the insulator layer  101  have been omitted from  FIG. 2  and subsequent figures.  FIG. 20B  illustrates a top view of the mask  2002 . 
       FIG. 21A  illustrates a cut-away view along the line A-A (of  FIG. 21B ) following an anisotropic etching process. The anisotropic etching process, such as, for example, reactive ion etching, removes exposed portions of the second hardmask  110  to expose portions of the organic planarization layer  108 .  FIG. 21B  illustrates a top view of the second hardmask  110  arranged on the organic planarization layer  108 . 
       FIG. 22  illustrates a cut-away view following the deposition of a third hardmask  2202  over exposed portions of the organic planarizing layer  108  and the second hardmask  110 . The third hardmask  2202  in the illustrated embodiment includes an oxide material. Other exemplary embodiments may include other suitable materials such as, for example, a nitride material. A sacrificial mandrel material  2204  is deposited over the third hardmask  2202  followed by a fourth hardmask  2206  that is deposited over the sacrificial mandrel material  2204 . The sacrificial mandrel material  2204  may include, for example, an amorphous carbon or amorphous silicon material. 
       FIG. 23A  illustrates a cut-away view along the line A-A (of  FIG. 23B ) following the patterning and deposition of a photolithographic resist  2302  over portions of the fourth hardmask  2206 .  FIG. 23B  illustrates a top view of the resist  2302  arranged on the fourth hardmask  2206 . 
       FIG. 24  illustrates a cut-away view of the resultant structure following a selective etching process. The etching process is an anisotropic etching process, such as for example, reactive ion etching that removes exposed portions of the sacrificial mandrel layer  2204  (of  FIG. 23A ) to expose portions of the third hardmask  2202  and form sacrificial mandrels  2402  on the third hardmask  2202 . 
       FIG. 25  illustrates a cut-away view following the deposition of a layer of spacer material  2502  over the exposed portions of the third hardmask  2202  and the sacrificial mandrels  2402 . The layer of spacer material  2502  may include, for example, a nitride or an oxide material. 
       FIG. 26  illustrates a cut-away view following an anisotropic etching process such as, for example, reactive ion etching. The etching process removes portions of the layer of spacer material  2502  to form spacers  2602  along sidewalls of the sacrificial mandrels  2402 . 
       FIG. 27  illustrates a cut-away view following the deposition of a second organic planarization layer  2702  over exposed portions of the sacrificial mandrels  2402  and the spacers  2602 . 
       FIG. 28  illustrates a cut-away view following an etching or planarization process that removes portions of the second organic planarization layer  2702  to form non-mandrel lines  2802 . 
       FIG. 29A  illustrates a cut-away view along the line A-A (of  FIG. 29C ) following a selective etching process that removes exposed portions of the sacrificial mandrels  2404  (of  FIG. 28 ) to form cavities  2902 .  FIG. 29B  illustrates a cut-away view along the line B-B (of  FIG. 29C ) of the cavities  2902 .  FIG. 29C  illustrates a top view of the cavities  2902 . 
       FIG. 30  illustrates a cut-away view following a selective anisotropic etching process such as, for example, reactive ion etching. The etching process removes exposed portions of the third hardmask  2202  in the cavities  2902  to increase the depth of the cavities  2902  and expose portions of the second hardmask  110 . 
       FIG. 31  illustrates a cut-away view following a selective anisotropic etching process such as, for example, reactive ion etching. The etching process removes exposed portions of the second hardmask  110  in the cavities  2902  to increase the depth of the cavities  2902  and expose portions of the organic planarization layer  108 . 
       FIG. 32  illustrates a cut-away view following another selective anisotropic etching process such as, for example, reactive ion etching. The etching process removes exposed portions of the organic planarization layer  108  to increase the depth of the cavities  2902  and expose portions of the first hardmask  106 . During the etching process the exposed portions of the non-mandrel lines  2802  (of  FIG. 31 ) are removed. 
       FIG. 33  illustrates a cut-away view following another anisotropic etching process that removes non-obscured regions of the organic planarizing layer  108  to further expose portions of the first hardmask  106 . 
       FIG. 34A  illustrates a cut-away view along the line A-A (of  FIG. 34B ) of the resultant structure following an anisotropic etching process that removes exposed portions of the first hardmask  106 . Following the removal of portions of the first hardmask  106 , the remnants of the organic planarizing layer  108 , the second hardmask  110 , the third hardmask  2202  and the spacers  2602  (of  FIG. 33 ) are removed to expose the first hardmask  106 .  FIG. 34B  illustrates a top view of the first hardmask  106  arranged on the inter-level dielectric layer  104 . 
       FIG. 35  illustrates a cut-away view following a selective anisotropic etching process such as, for example, reactive ion etching that removes exposed portions of the inter-level dielectric layer  104  to form cavities (trenches)  3502 . 
       FIG. 36  illustrates a cut-away view following a selective etching process that removes the first hardmask  104  (of  FIG. 35 ). 
       FIG. 37  illustrates a cut-away view following the deposition of a conductive material  3702  such as, for example, copper, silver, gold, aluminum, or another conductive material into the cavities  3502 . Prior to depositing the conductive material, a liner layer (not shown) may be formed. 
       FIG. 38A  illustrates a cut-away view along the line A-A (of  FIG. 38B ) following a planarization process. The planarization process such as, for example, chemical mechanical polishing may be performed to remove overburden material and form conductive lines  3802  in the cavities  3503  (of  FIG. 35 ).  FIG. 38B  illustrates a top view of the conductive lines  3802  arranged in the inter-level dielectric layer  104 . 
     The embodiments described herein provide for the formation of mandrel lines and non-mandrel lines that are formed from dissimilar materials, and thus, may be selectively etched. The selectively of the mandrel and non-mandrel lines provides for selectively forming conductive lines in the regions defined by the mandrel and non-mandrel lines. 
     The embodiments described herein provide for patterning mandrels and non-mandrel lines on the substrate. Such embodiments allow for substantially self-aligning conductive lines with a greater margin of alignment error when patterning using a mask. The greater margin of error in mask alignment allows conductive lines to be formed as the pitch scale of the devices decreases. 
     As used herein, the terms “invention” or “present invention” are non-limiting terms and not intended to refer to any single aspect of the particular invention but encompass all possible aspects as described in the specification and the claims. The term “on” may refer to an element that is on, above or in contact with another element or feature described in the specification and/or illustrated in the figures. 
     As used herein, the term “about” modifying the quantity of an ingredient, component, or reactant of the invention employed refers to variation in the numerical quantity that can occur, for example, through typical measuring and liquid handling procedures used for making concentrates or solutions. Furthermore, variation can occur from inadvertent error in measuring procedures, differences in the manufacture, source, or purity of the ingredients employed to make the compositions or carry out the methods, and the like. In one aspect, the term “about” means within 10% of the reported numerical value. In another aspect, the term “about” means within 5% of the reported numerical value. Yet, in another aspect, the term “about” means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported numerical value. 
     It will also be understood that when an element, such as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly over” “on and in direct contact with” another element, there are no intervening elements present, and the element is in contact with another element. 
     It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. 
     The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.