Patent Publication Number: US-2002009001-A1

Title: Integrated circuit with a matrix of programmable logic cells

Description:
[0001] The invention relates to an integrated circuit with programmable logic with an interconnected matrix of programmable logic cells.  
       [0002] From U.S. Pat. No. 6,014,509 it is known to arrange programmable logic cells in a matrix. Each cell has a programmable computation function. The result of the computation can be passed to other cells where it may be used as input for further computations. This allows the implementation of complex computational functions. The efficiency of such computations, in terms of integrated circuit substrate area that is required to implement the function, depends, amongst others, on the flexibility with which results can be routed between cells. The circuit of U.S. Pat. No. 6,014,509 provides for routing of a result of one cell to all of its neighbors and to busses that are shared by cells in rows and columns of the matrix respectively. Cells are programmed to select their inputs from their neighbors and/or the busses.  
       [0003] Amongst others, it is an object of the invention to improve the efficiency with which functions can be implemented in an integrated circuit with a matrix of computing cells.  
       [0004] The integrated circuit according to the invention is described in claim  1 . According to the invention, programmable switches are located between adjacent cells and the cells contain local conductors that connect the switches on opposite sides of the cells. The switches connect conductors of neighboring cells. In a matrix of rows and columns for example, local conductors connect the switches on opposite sides in the row direction and other local conductors connect the switches on opposite sides in the column direction. A cell also contains a computation logic circuit, which preferably is programmable, with an input and outputs. The input is connected to the conductor of the cell and the outputs are programmably connected to the conductors of neighboring cells. Whether an output is actively connected to the conductor of a neighboring cell can be programmed individually for different neighboring cells.  
       [0005] Thus, the cell provides both for computation and for routing data from and between neighboring cells. To keep the conductors of the cell free for receiving input signals, the output of the computation logic circuit of a cell is connected to the conductors of the neighboring cells, from where the output can be isolated from the conductor of the cell by means of the switches between the cells. It can be selected which of the neighboring cells receive the output and which do not receive the output. The conductors of the latter can be connected to the cell by the switches for supplying an input routed through the neighboring cell, but of course the input may also be received directly from the output of the neighboring cell, because this output is in turn connected to the conductor of the cell. In an alternative embodiment, the connections of inputs and outputs are interchanged, the output being coupled to the conductor of the cell and the inputs being individually programmably connected to the conductors of the neighboring cells.  
       [0006] In an embodiment the cell contains a plurality of local conductors that connect switches on opposite sides of the cell. Each conductor is connected by the switch to a different corresponding connector in the neighboring cell. The computation logic circuit has inputs connected to the conductors of the cell. In a further embodiment, the cell contains a programmable interconnection switch for making a programmable connection between conductors in the cell. Thus, it is possible to provide more complicated routing, from one conductor to another, in the cell.  
       [0007] In another embodiment the matrix has rows and columns. Local row conductors connect the switches on opposite sides in the row direction and local column conductors connect the switches on opposite sides in the column direction. In a further embodiment, the cell contains cross connection switches between the local row conductors and the local column conductors. The combination of the switches between cells and cross-connection switches allows more complicated routing, where the cell serves to rout data from for example a neighboring cell in the column direction to a neighboring cell in the row direction.  
       [0008] In another embodiment of the integrated circuit according to the invention, the circuit also contains global conductors, which run through a number of cells in the same row or column for example. The computation logic circuit has inputs and outputs connected to the global conductors as well. This allows routing between cells at greater distances without encumbering the local conductors of the intervening cells. 
     
    
    
     [0009] These and other advantageous aspects of the integrated circuit according to the invention will be described using the following figures.  
     [0010]FIG. 1 shows a matrix of programmable cells  
     [0011]FIG. 2 shows a routing plane of a cell  
     [0012]FIG. 3 shows a computation logic circuit. 
    
    
     [0013]FIG. 1 shows a matrix of programmable cells  100   a - c,    102   a - c,    104   a - c,  arranged in rows and columns. Between neighboring cells connection circuits  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c  are shown. Two pairs of local conductors (e.g.  106   a,b  and  108   a,b ) are shown in each cell  100   a - c,    102   a - c,    104   a - c,  running in a row direction and in a column direction respectively. Each pair of local conductors  108   a,b  that runs in the row direction is coupled to the pairs of local conductors of the neighboring cells in the row direction via a connection circuit  120   a - c,    122   a - c  in the row direction. Each pair of local conductors  106   a,b  that runs in the column direction is coupled to the pairs of local conductors of the neighboring cells in the column direction via a connection circuit  140   a - c,    142   a - c  in the column direction. Each connection circuit contain switches  124   a,b  connecting the local conductors of the neighboring cells. The switches  124   a,b  of only one connection circuit  120   a  are shown explicitly for reasons of clarity.  
     [0014] Each cell  100   a - c,    102   a - c,    104   a - c  contains a programmable computation logic circuit  110   a,b  (the computation logic circuit  110   a,b  of only one of the cells  120   a  being shown explicitly for reasons of clarity. Moreover the computation logic circuit  110   a,b  is shown in two parts  110   a,b  in order to avoid encumbering the figure with connections. In reality, the computation logic circuit  110   a,b  may be a single part performing its function as a whole), with inputs connected to the local conductors of the cell. The computation logic circuit has an output coupled to conductors  106   a,b,    108   a,b  of the neighboring cells  100   a - c,    102   a - c,    104   a - c  “behind” the connection circuit, i.e. with the connection circuit between the output and the local conductors  106   a,b,    108   a,b  of the cell to which the inputs of the computation logic circuit are connected.  
     [0015] The open/closed state of the switches in the connection circuits  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c  and the function of the computation logic circuit are controlled by configuration data in configuration memory locations (not shown).  
     [0016] In operation each computation logic circuits  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c  receive data from the local conductors of the cells to which the computation logic circuit  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c  belongs. From this data the computation logic circuit  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c  computes result data. The result data is applied to the local conductors of selected ones of the neighboring cells, the selection being controlled by the configuration data.  
     [0017] The result data is used as input by the computation logic circuit of one or more other cells  120   a - c,    122   a - c,    140   a - c,    142   a - c,    144   a - c.  This can be the cells that neighbor the particular cell of the computation logic circuit that has produced the result data, but it can also be cells further away from the particular cell, those cells receiving the result data via the local conductors of intervening cells by closing the appropriate switches in the connection circuits between the cells.  
     [0018] The conductors of the cell and switches between the conductors will commonly be referred to as the “routing plane of the cell.  
     [0019]FIG. 2 shows a routing plane of a more complicated cell  20  than the ones shown in FIG. 1, in combination with the connection circuits  220 ,  222 ,  224 ,  226  to the neighboring cells (not shown). The cell  20  contains four local column conductors  24   a - d,  four local row conductors  26   a - d,  two global column conductors  25   a,b  two global row conductors  27   a,b  and a computation logic circuit  200 ,  202   a,b.  Each connection circuit  220 ,  222 ,  224 ,  226  contains four switches  220   a - d,    222   a - d,    224   a - d,    226   a - d.  Two of the connection circuits  220 ,  222 ,  224 ,  226  are column connection circuits  220 ,  224 , the other two are row connection circuits  222 ,  226 . The switches  220   a - d,    224   a - d  of each column connection circuit are connected on one side to respective ones of the local column conductors  24   a - d.  On the other side these switches  220   a - d,    224   a - d  are connected to similar column conductors of neighboring cells (not shown) in the column direction. The global column conductors  25   a,b  run on to the global column conductors of neighboring cells in the column direction without interruption by a switch. The switches  222   a - d,    226   a - d  of each row connection circuit are connected on one side to respective ones of the local row conductors  26   a - d.  On the other side these switches  222   a - d,    226   a - d  are connected to similar column conductors of neighboring cells (not shown) in the column direction. The global row conductors  27   a,b  run on to the global row conductors of neighboring cells in the row direction without interruption by a switch.  
     [0020] Within cell  20  column interconnection switches  240   a,b  are shown connecting pairs of local column conductors  24   a - d.  Within cell  20  row interconnection switches  260   a,b  are shown connecting pairs of local row conductors  24   a - d.  Within cell  20  four cross connection switches  280   a - d,  each connecting a respective one of the local column conductors  24   a - d  to a respective one of the local row conductors  26   a - d.  Within cell  20  two global cross-connection switches  270   a,b  are shown, each connecting a respective one of the global column conductors  25   a,b  to a respective one of the global row conductors  27   a,b.    
     [0021] The computation logic circuit  200 ,  202   a,b  contains a computation core  200  and output connection circuits  202   a,b.  The computation core  200  has inputs connected to the local column conductors  24   a - d,  the local row conductors  26   a - d,  the global column conductors  26   a,b  and the global row conductors  27   a,b.  The computation core  200  has outputs connected to the connection circuits  202   a,b.  The output connection circuits  202   a,b  have outputs connected to the local row and column conductors of the neighboring cells and to the global row and column conductors  26   a,b,    27   a,b.    
     [0022] Signals from a configuration memory (not shown) control the function of the computation core  200 , the output connection circuits  202   a,b  and the state of the switches  220   a - b,    222   a - d,    224   a - d,    226   a - d  in the connection circuits  220 ,  222 ,  224 ,  226 , the interconnection switches  240   a,b,    260   a,b  and the cross-connection switches  280   a - d,    270   a,b.    
     [0023]FIG. 3 shows an embodiment of a computation core  200 . The core  200  contains an access network  30 , a computation logic block  32  and a distribution circuit  34 , coupled in series with one another. One possible embodiment of an access network  30  will be described, but it will be obvious that many alternative embodiments are possible. The access network  30  that is shown contains first and second multiplexers  300   a - f,    304   a - f  interconnected by a connection network  302 . The function of first and second multiplexers  300   a - f  and  304   a - f  is programmable, using configuration bits stored in a memory (not shown). Each first multiplexer has a pair of inputs coupled to a “horizontal” conductor and a “vertical” conductor respectively. The second multiplexers  304   a - f  each have four inputs, coupled to the outputs of four of the first multiplexers  300   a - f,  for example three second multiplexers  300   a - c  that receive a fist set of outputs of four of first multiplexers  304   a - f  and three other second multiplexers  300   d - f  that receive a second set of outputs of four of first multiplexers  300   a - f.  Here the first and second set both contain the outputs of the first multiplexers  300   a - f  that are connected to the global conductors  29   a,b.  Otherwise, they contain the outputs of different ones of the first multiplexers  200   a - f  that are connected to the local conductors. The outputs of the second multiplexers  304   a - f  form the outputs of the access network  30 . Of course many other kinds of connections between inputs and outputs of access network are possible, for example six 12 to 1 multiplexers.  
     [0024] The outputs of access network  20  are coupled to the inputs of computation logic block  32 . One possible embodiment of computation logic block  32  will be described, but it will be obvious that many alternative embodiments are possible. The computation logic block  32  that is shown contains a first and second SRAM  320 ,  322 , an output control multiplexer  324  and a first and second output multiplexer  326 ,  328 . The SRAMs  320 ,  322  serve as programmable look-up tables that define the relation between input and output. Three inputs of the computation logic block  32  are coupled to an address input of the first SRAM  320 , the other three inputs are coupled to an address input of the second SRAM  302 . An output of the first SRAM  320  is coupled to a first and second output of the computation logic block  32  via first and second output multiplexer  326 ,  328  respectively. An output of second SRAM  322  is coupled to the first second output of computation logic block via the first and second output multiplexer  326 ,  328 . The inputs of the computation logic block  32  are coupled to the control inputs of the output control multiplexer  324 , which has an output coupled to a control input of the first and second output multiplexer  326 ,  328 , so that either the output of the first SRAM  320  is coupled to the first output of the computation logic block and the output of the second SRAM  322  is coupled to the second output of the computational logic block or vice versa, dependent on the inputs of the computational logic block (the nature of this dependence is controlled by configuration bits (not shown)).  
     [0025] The outputs of computation logic block  32  are coupled to the inputs of distribution circuit  34 . Distribution circuit contains a distribution network  340 , first and second distribution multiplexer  342   a,b,  and flip-flops  344   a,b.  The outputs of the computation logic block  32  are coupled to the inputs of the first distribution multiplexer  342   a,  directly from the computational logic block  32  and via the first flip-flop  344   a.  Similarly the outputs of the computation logic block  32  are coupled to the inputs of the second distribution multiplexer  342   b,  directly from the output of the computational logic block  32  and via the second flip-flop  344   b.  The outputs of the first and second distribution multiplexer  342   a,b  form the outputs of the distribution circuit. In operation, the multiplexers are programmed with configuration bits not shown, allowing any output signal of the computation logic block  32  to be passed to any output of the distribution circuit  34 , if necessary via a flip-flop to delay the output by one clock cycle, so as to allow pipelined processing.