Patent Publication Number: US-11658212-B2

Title: Quantum dot devices with conductive liners

Description:
BACKGROUND 
     Quantum computing refers to the field of research related to computation systems that use quantum mechanical phenomena to manipulate data. These quantum mechanical phenomena, such as superposition (in which a quantum variable can simultaneously exist in multiple different states) and entanglement (in which multiple quantum variables have related states irrespective of the distance between them in space or time), do not have analogs in the world of classical computing, and thus cannot be implemented with classical computing devices. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. To facilitate this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example, not by way of limitation, in the figures of the accompanying drawings. 
         FIGS.  1 - 4    are cross-sectional views of a quantum dot device, in accordance with various embodiments. 
         FIGS.  5 - 36    illustrate various example stages in the manufacture of a quantum dot device, in accordance with various embodiments. 
         FIGS.  37 - 39    are cross-sectional views of another quantum dot device, in accordance with various embodiments. 
         FIGS.  40 - 42    are cross-sectional views of example quantum well stacks and substrates that may be used in a quantum dot device, in accordance with various embodiments. 
         FIGS.  43 - 49    illustrate example base/fin arrangements that may be used in a quantum dot device, in accordance with various embodiments. 
         FIGS.  50 - 53    are cross-sectional views of other quantum dot devices, in accordance with various embodiments. 
         FIG.  54    is a cross-sectional view of another quantum dot device, in accordance with various embodiments. 
         FIG.  55    is a cross-sectional view of an example of a portion of the quantum dot device of  FIG.  54   , in accordance with various embodiments. 
         FIG.  56    illustrates an embodiment of a quantum dot device having multiple fins arranged in a two-dimensional array, in accordance with various embodiments. 
         FIG.  57    illustrates an embodiment of a quantum dot device having multiple groups of gates on a single fin, in accordance with various embodiments. 
         FIGS.  58 - 61    illustrate various alternative stages in the manufacture of a quantum dot device, in accordance with various embodiments. 
         FIG.  62    is a cross-sectional view of a quantum dot device with multiple interconnect layers, in accordance with various embodiments. 
         FIG.  63    is a cross-sectional view of a quantum dot device package, in accordance with various embodiments. 
         FIGS.  64 A and  64 B  are top views of a wafer and dies that may include any of the quantum dot devices disclosed herein. 
         FIG.  65    is a cross-sectional view of a device assembly that may include any of the quantum dot devices disclosed herein. 
         FIG.  66    is a flow diagram of an illustrative method of operating a quantum dot device, in accordance with various embodiments. 
         FIG.  67    is a block diagram of an example quantum computing device that may include any of the quantum dot devices disclosed herein, in accordance with various embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     Disclosed herein are quantum dot devices with conductive liners, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base, a first fin extending from the base, a second fin extending from the base, a conductive material between the first fin and the second fin, and a dielectric material between the conductive material and the first fin. 
     The quantum dot devices disclosed herein may enable the formation of quantum dots to serve as quantum bits (“qubits”) in a quantum computing device, as well as the control of these quantum dots to perform quantum logic operations. Unlike previous approaches to quantum dot formation and manipulation, various embodiments of the quantum dot devices disclosed herein provide strong spatial localization of the quantum dots (and therefore good control over quantum dot interactions and manipulation), good scalability in the number of quantum dots included in the device, and/or design flexibility in making electrical connections to the quantum dot devices to integrate the quantum dot devices in larger computing devices. 
     In the following detailed description, reference is made to the accompanying drawings that form a part hereof, and in which is shown, by way of illustration, embodiments that may be practiced. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made, without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. 
     Various operations may be described as multiple discrete actions or operations in turn in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed as to imply that these operations are necessarily order dependent. In particular, these operations may not be performed in the order of presentation. Operations described may be performed in a different order from the described embodiment. Various additional operations may be performed, and/or described operations may be omitted in additional embodiments. 
     For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term “between,” when used with reference to measurement ranges, is inclusive of the ends of the measurement ranges. As used herein, the notation “A/B/C” means (A), (B), and/or (C). For convenience, the collection of drawings of  FIGS.  11 A and  11 B  may be referred to herein as “ FIG.  11   ,” and the collection of drawings of  FIGS.  15 A and  15 B  may be referred to herein as “ FIG.  15   .” 
     The description uses the phrases “in an embodiment” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as “above,” “below,” “top,” “bottom,” and “side”; such descriptions are used to facilitate the discussion and are not intended to restrict the application of disclosed embodiments. The accompanying drawings are not necessarily drawn to scale. As used herein, a “high-k dielectric” refers to a material having a higher dielectric constant than silicon oxide, and a “low-k dielectric” refers to a material having a lower dielectric constant than silicon oxide. As used herein, a “magnet line” refers to a magnetic field-generating structure to influence (e.g., change, reset, scramble, or set) the spin states of quantum dots. One example of a magnet line, as discussed herein, is a conductive pathway that is proximate to an area of quantum dot formation and selectively conductive of a current pulse that generates a magnetic field to influence a spin state of a quantum dot in the area. 
       FIGS.  1 - 4    are cross-sectional views of a quantum dot device  100 , in accordance with various embodiments. In particular,  FIG.  3    illustrates the quantum dot device  100  taken along the section A-A of  FIGS.  1  and  2    (while  FIG.  1    illustrates the quantum dot device  100  taken along the section C-C of  FIG.  3   , and  FIG.  2    illustrates the quantum dot device  100  taken along the section E-E of  FIG.  3   ), and  FIG.  4    illustrates the quantum dot device  100  taken along the section B-B of  FIGS.  1  and  2    with a number of components not shown to more readily illustrate how the gates  106 / 108  and the magnet line  121  may be patterned (while  FIG.  1    illustrates a quantum dot device  100  taken along the section D-D of  FIG.  4   ). Although  FIGS.  1  and  2    indicate that the cross-section illustrated in  FIG.  3    is taken through the fin  104 - 1 , an analogous cross-section taken through the fin  104 - 2  may be identical, and thus the discussion of  FIG.  3    refers generally to the “fin  104 .” 
     The quantum dot device  100  may include a base  102  and multiple fins  104  extending away from the base  102 . The base  102  and the fins  104  may include a substrate and a quantum well stack (not shown in  FIGS.  1 - 4   , but discussed below with reference to the substrate  144  and the quantum well stack  146 ), distributed in any of a number of ways between the base  102  and the fins  104 . The base  102  may include at least some of the substrate, and the fins  104  may each include a quantum well layer of the quantum well stack (discussed below with reference to the quantum well layer  152 ). Examples of base/fin arrangements are discussed below with reference to the base fin arrangements  158  of  FIGS.  43 - 49   . 
     Although only two fins,  104 - 1  and  104 - 2 , are shown in  FIGS.  1 - 4   , this is simply for ease of illustration, and more than two fins  104  may be included in the quantum dot device  100 . In some embodiments, the total number of fins  104  included in the quantum dot device  100  is an even number, with the fins  104  organized into pairs including one active fin  104  and one read fin  104 , as discussed in detail below. When the quantum dot device  100  includes more than two fins  104 , the fins  104  may be arranged in pairs in a line (e.g., 2N fins total may be arranged in a 1×2N line, or a 2×N line) or in pairs in a larger array (e.g., 2N fins total may be arranged as a 4×N/2 array, a 6×N/3 array, etc.). The discussion herein will largely focus on a single pair of fins  104  for ease of illustration, but all the teachings of the present disclosure apply to quantum dot devices  100  with more fins  104 . In some embodiments, a quantum dot device  100  may include “dummy” fins  104  in addition to the active/read fins  104  (e.g., as discussed below with reference to  FIG.  55   ). These dummy fins  104  may be included in the quantum dot device  100  for ease and improved reliability in manufacturing, and they may not be actively utilized for quantum dot generation/detection during operation of the quantum dot device  100 . Any number of dummy fins  104  may be included in a quantum dot device  100 . 
     As noted above, each of the fins  104  may include a quantum well layer (not shown in  FIGS.  1 - 4   , but discussed below with reference to the quantum well layer  152 ). The quantum well layer included in the fins  104  may be arranged normal to the z-direction, and may provide a layer in which a two-dimensional electron gas (2DEG) may form to enable the generation of a quantum dot during operation of the quantum dot device  100 , as discussed in further detail below. The quantum well layer itself may provide a geometric constraint on the z-location of quantum dots in the fins  104 , and the limited extent of the fins  104  (and therefore the quantum well layer) in the y-direction may provide a geometric constraint on the y-location of quantum dots in the fins  104 . To control the x-location of quantum dots in the fins  104 , voltages may be applied to gates disposed on the fins  104  to adjust the energy profile along the fins  104  in the x-direction and thereby constrain the x-location of quantum dots within quantum wells (discussed in detail below with reference to the gates  106 / 108 ). The dimensions of the fins  104  may take any suitable values. For example, in some embodiments, the fins  104  may each have a width  162  between 5 nanometers and 30 nanometers. In some embodiments, the fins  104  may each have a vertical dimension  164  between 70 nanometers and 400 nanometers (e.g., between 100 nanometers and 350 nanometers, or equal to 300 nanometers). 
     The fins  104  may be arranged in parallel, as illustrated in  FIGS.  1  and  4   . In some embodiments, the fins  104  may be spaced apart by a distance  160  between 60 nanometers and 250 nanometers. As discussed in further detail below, although the fins  104  are illustrated in some of the accompanying drawings as substantially rectangular, the fins  104  may have a tapered shape, narrowing away from the base  102 . Further, the side faces of the fins  104  may not be straight, but may have some curvature (e.g., as illustrated in  FIG.  55   ). 
     A dielectric material  131  may be disposed at side faces of the fins  104 . The portions of the dielectric material  131  at side faces of the fins  104  may be part of materially contiguous dielectric material structures that extend onto the base  102 . For example, the layer of dielectric material  131  between the fins  104 - 1  and  104 - 2  has a U-shaped cross-section, with portions on the “inner” side faces of the fins  104 - 1  and  104 - 2  and a portion on the base  102 . In some embodiments, the dielectric material  131  may not be present on the base  102  (e.g., as discussed below with reference to  FIG.  8   ). The thickness  137  of the dielectric material  131  may be between 1 nanometer and 20 nanometers (e.g., between 1 nanometer and 10 nanometers). The dielectric material  131  may be conformal on the side faces of the fins  104  and the top surface of the base  102  (when present there). In some embodiments, the dielectric material  131  may be a semiconductor oxide (e.g., a thermal oxide grown by oxidizing material of the fin  104 , as discussed further below with reference to  FIG.  8   ). In some embodiments, the dielectric material  131  may be a high-k dielectric material. In some embodiments, the dielectric material  131  may take the form of any of the embodiments of the gate dielectric  114  discussed herein. In some embodiments, the dielectric material  131  may be a low-k dielectric material. In some embodiments, the dielectric material  131  may be a low loss dielectric material, as discussed below with reference to the low loss dielectric materials  151  discussed below. In some embodiments, the dielectric material  131  and the low loss dielectric materials  151  (when present) may have different material compositions. In some embodiments, the dielectric material  131  and the insulating material  128  (discussed below) may have different compositions. 
     A conductive material  117  may be disposed proximate to side faces of the fins  104 , spaced away from the side faces of the fins  104  by the intervening dielectric material  131 . The portions of the conductive material  117  proximate to side faces of the fins  104  may be part of materially contiguous conductive material structures that extend onto the base  102 . For example, the layer of conductive material  117  between the fins  104 - 1  and  104 - 2  has a U-shaped cross-section, with portions proximate to the “inner” side faces of the fins  104 - 1  and  104 - 2  and a portion proximate to the base  102 . In some embodiments, the conductive material  117  may not be present on the base  102  (e.g., as discussed below with reference to  FIG.  9   ). The thickness  119  of the conductive material  117  may be between 1 nanometer and 20 nanometers (e.g., between 2 nanometers and 10 nanometers). The conductive material  117  may be conformal on the dielectric material  131  on the side faces of the fins  104  and the top surface of the base  102  (when present there). In some embodiments, the conductive material  117  may be a metal (e.g., any of the materials discussed herein with reference to the gate metals  110 / 112 , such as titanium nitride). In some embodiments, the conductive material  117  may be a superconducting material. 
     An electrically insulating material  128  may also be disposed between the fins  104 . In some embodiments, the insulating material  128  may be a nitride (e.g., silicon nitride or another nitride). In some embodiments, the insulating material  128  may include germanium, carbon, or phosphorous. In some embodiments, the insulating material  128  may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, or silicon oxycarbide. In some embodiments, the insulating material  128  may include a carbosilane dielectric. A carbosilane dielectric may be a dielectric film that includes crosslinked cyclic carbosilanes. A cyclic carbosilane may have a ring structure including carbon and silicon. In some embodiments, a carbosilane dielectric may have a carbon content between 45 atomic-percent and 60 atomic-percent, a silicon content between 25 atomic-percent and 35 atomic-percent, and an oxygen content between 10 atomic-percent and 20 atomic-percent. Some carbosilane dielectrics that may be included in the insulating material  128  may have a k-value between 1.6 and 2.5. Some carbosilane dielectrics may have a porosity between 5 percent and 60 percent (e.g., between 35 percent and 50 percent). 
     The bottom portions of the fins  104  may be surrounded by the dielectric material  131 /conductive material  117 /insulating material  128 , while the top portions of the fins  104  may be surrounded by one or more low loss dielectric materials  151 . As used herein, a “low loss dielectric material” is one whose loss tangent is less than the loss tangent of the insulating material  128 . For example, as illustrated in  FIGS.  1  and  2    (and discussed in further detail below with reference to  FIGS.  12 - 15   ), a low loss dielectric material  151 - 1  may be disposed on either side face of the fin  104  proximate to the gates  106 , while a low loss dielectric material  151 - 2  may be disposed on either side face of the fin  104  proximate to the gates  108 . The low loss dielectric materials  151  around a top portion of a fin  104  may contact side faces of a quantum well layer  152  (not shown) included in that fin  104 . Utilizing low loss dielectric materials  151  near the quantum well layer  152  or other sensitive layers of a quantum well stack  146  in a fin  104  may reduce the charge noise present in these layers during operation, and thus may improve device operation. The depth  153  of the low loss dielectric materials  151  relative to the top of the fins  104  may have any suitable value; for example, the depth  153  may be between 10 nanometers and 100 nanometers (e.g., between 20 nanometers and 50 nanometers). In some embodiments, the depth  153  of the low loss dielectric material  151 - 1  may be different from the depth  153  of the low loss dielectric material  151 - 2 . 
     In the embodiment of  FIGS.  1  and  2   , the low loss dielectric materials  151  may extend between the fins  104 - 1  and  104 - 2 . Such embodiments may provide a low loss “channel” between the fins  104 , which may desirably improve the capacitive coupling of quantum dots  142  in different fins  104  (e.g., when one quantum dot  142  is being “read” by another quantum dot  142 , as discussed further below). The dielectric constant of the low loss dielectric material  151  between a portion of the fin  104 - 1  and a portion of the fin  104 - 2  may be selected to further control the coupling between the fins  104 . A low loss dielectric material  151  with a high dielectric constant may be utilized when strong coupling is desired, and a low loss dielectric material  151  with a low dielectric constant may be utilized when coupling is not desired. For example, a high-k low loss dielectric material  151 - 1  ( 151 - 2 ) may be utilized when the gates  106  ( 108 ) are “plunger” gates (as discussed below) to improve coupling between quantum dots  142  that form under the gates  106  in different fins  104 , and a low-k low loss dielectric material  151 - 1  ( 151 - 2 ) may be utilized when the gates  106  ( 108 ) are “barrier” gates (as discussed below) to reduce coupling between the portions of the quantum well stack  146  under the gates  106  ( 108 ) in different ones of the fins  104 . In other embodiments, the low loss dielectric materials  151  around each fin  104  may not span the volume between the fins  104 , and instead, the dielectric material  131 , conductive material  117 , and/or the insulating material  128  may be present between the low loss dielectric material  151  around the fin  104 - 1  and the low loss dielectric material  151  around the fin  104 - 2  (e.g., as discussed below with reference to  FIG.  51   ). Examples of high-k low loss dielectric materials  151  may include any of the materials discussed herein with reference to the gate dielectric  114 , with sufficiently high quality, low loss, low defectivity, and low leakage (e.g., highly coordinated oxides). 
       FIGS.  1  and  2    illustrate an embodiment in which different low loss dielectric materials  151  are disposed “under” the gates  106  and the gates  108 . In other embodiments, a same low loss dielectric material  151  may be disposed under the gates  106  and the gates  108 ; an example of such an embodiment is discussed below with reference to  FIG.  53   . 
     In some embodiments, no low loss dielectric materials  151  may be included in a quantum dot device  100 . In such embodiments, the conductive material  117  (and the dielectric material  131 , if desired) may be recessed below the plane of the top surface of the fins  104  in an area between two fins  104  when coupling between those fins  104  is desired; when coupling between a pair of fins  104  is not desired, the conductive material  117  may not be recessed, and may instead extend up to the plane of the top surfaces of the fins  104 . Examples of such embodiments are illustrated in  FIGS.  54  and  55    and discussed further below. 
     Multiple gates may be disposed on each of the fins  104 . In the embodiment illustrated in  FIG.  3   , three gates  106  and two gates  108  are shown as distributed on the top of the fin  104 . This particular number of gates is simply illustrative, and any suitable number of gates may be used. Additionally, as discussed below with reference to  FIG.  56   , multiple groups of gates (like the gates illustrated in  FIG.  3   ) may be disposed on the fin  104 . 
     As shown in  FIG.  3   , the gate  108 - 1  may be disposed between the gates  106 - 1  and  106 - 2 , and the gate  108 - 2  may be disposed between the gates  106 - 2  and  106 - 3 . Each of the gates  106 / 108  may include a gate dielectric  114 ; in the embodiment illustrated in  FIG.  3   , the gate dielectric  114  for all of the gates  106 / 108  is provided by a common layer of gate dielectric material. In other embodiments, the gate dielectric  114  for each of the gates  106 / 108  may be provided by separate portions of gate dielectric  114  (e.g., as discussed below with reference to  FIGS.  58 - 61   ). In some embodiments, the gate dielectric  114  may be a multilayer gate dielectric (e.g., with multiple materials used to improve the interface between the fin  104  and the corresponding gate metal). The gate dielectric  114  may be, for example, silicon oxide, aluminum oxide, or a high-k dielectric, such as hafnium oxide. More generally, the gate dielectric  114  may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of materials that may be used in the gate dielectric  114  may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric  114  to improve the quality of the gate dielectric  114 . 
     Each of the gates  106  may include a gate metal  110  and a hardmask  116 . The hardmask  116  may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal  110  may be disposed between the hardmask  116  and the gate dielectric  114 , and the gate dielectric  114  may be disposed between the gate metal  110  and the fin  104 . Only one portion of the hardmask  116  is labeled in  FIG.  3    for ease of illustration. In some embodiments, the gate metal  110  may be a superconductor, such as aluminum, titanium nitride (e.g., deposited via atomic layer deposition (ALD)), or niobium titanium nitride. In some embodiments, the hardmask  116  may not be present in the quantum dot device  100  (e.g., a hardmask like the hardmask  116  may be removed during processing, as discussed below). The sides of the gate metal  110  may be substantially parallel, as shown in  FIG.  3   , and insulating spacers  134  may be disposed on the sides of the gate metal  110  and the hardmask  116 . As illustrated in  FIG.  3   , the spacers  134  may be thicker closer to the fin  104  and thinner farther away from the fin  104 . In some embodiments, the spacers  134  may have a convex shape. The spacers  134  may be formed of any suitable material, such as a carbon-doped oxide, silicon nitride, silicon oxide, or other carbides or nitrides (e.g., silicon carbide, silicon nitride doped with carbon, and silicon oxynitride). The gate metal  110  may be any suitable metal, such as titanium nitride. 
     Each of the gates  108  may include a gate metal  112  and a hardmask  118 . The hardmask  118  may be formed of silicon nitride, silicon carbide, or another suitable material. The gate metal  112  may be disposed between the hardmask  118  and the gate dielectric  114 , and the gate dielectric  114  may be disposed between the gate metal  112  and the fin  104 . In the embodiment illustrated in  FIG.  3   , the hardmask  118  may extend over the hardmask  116  (and over the gate metal  110  of the gates  106 ), while in other embodiments, the hardmask  118  may not extend over the gate metal  110 . In some embodiments, the hardmask  118  may not be present in the quantum dot device  100  (e.g., a hardmask like the hardmask  118  may be removed during processing, as discussed below). 
     In some embodiments, the gate metal  112  and the gate metal  110  may have the same material structure; in other embodiments, the gate metal  112  may have a different material structure from the gate metal  110 . As used herein, two materials may have a same “material structure” when their chemical composition and internal strain are approximately the same; two materials may have a different “material structure” when their chemical composition and/or their internal strain differ. As used herein, a “relaxed” material may be a material that is substantially free from compressive or tensile strain, while a “strained” material may be a material exhibiting compressive or tensile strain. In particular, in some embodiments, the material structures of the gate metal  110  and  112  may be different and may be selected so as to induce strain in the underlying material layers (including the quantum well layer  152 , discussed below). 
     The strain induced in the underlying material layers by the gate metal  110 / 112  may not be uniform through these underlying material layers, but may vary along the material layers depending upon the relative location below the gate metal  110 / 112 . For example, the region of a quantum well layer  152  below the gate metal  110  may be tensilely strained, while the region below the gate metal  112  may be compressively strained (or vice versa). In some embodiments, the region of a quantum well layer  152  below the gate metal  110  may be tensilely (compressively) strained, and the region below the gate metal  112  may be tensilely (compressively) strained as well, but by a different amount. The gate metals  110  and  112  may be selected to achieve a particular differential strain landscape in the underlying material layers (e.g., in the quantum well layer  152 ) that may improve the electric field control of the potential energies in these material layers (e.g., the “barrier” and “plunger” potentials, as discussed below). 
     In some embodiments, the gate metal  110  and or the gate metal  112  itself may be strained (e.g., with strain induced during deposition, as known in the art). In other embodiments, the differential strain induced in the quantum well layer  152  may be a function of the interaction between the gate metals  110 / 112  and the adjacent materials (e.g., the gate dielectric  114 , a barrier layer  156  (discussed below), etc.). 
     Differential strain may be induced in the quantum well layer  152  by the gate metal  110 / 112  in a number of ways. For example, differential strain may be induced in the quantum well layer  152  when the gate metal  110  is formed of different metal than the gate metal  112 . For example, in some embodiments, the gate metal  110  may be a superconductor while the gate metal  112  is a non-superconductor (or vice versa). In some embodiments, the gate metal  110  may be titanium nitride while the gate metal  112  is a metal different than titanium nitride (e.g., aluminum or niobium titanium nitride) (or vice versa). In some embodiments, the gate metal  110  and the gate metal  112  may be different non-magnetic metals. 
     Even when the gate metal  110  and the gate metal  112  include the same metal, differential strain may be induced in the quantum well layer  152  (and other intervening material layers) when the gate metal  110  and the gate metal  112  are deposited under different conditions (e.g., precursors, time, temperature, pressure, deposition technique, etc.). For example, the gate metal  110  and the gate metal  112  may be deposited using the same technique (e.g., ALD, electroless deposition, electroplating, or sputtering), but the parameters and/or materials of these deposition processes may be different, resulting in different structures of the gate metals  110 / 112  and therefore differential strain in the underlying material layers. In some embodiments, the thin film deposition of the gate metals  110 / 112  may induce strain in the underlying quantum well layer  152 . 
     The gate  108 - 1  may extend between the proximate spacers  134  on the sides of the gate  106 - 1  and the gate  106 - 2 , as shown in  FIG.  3   . In some embodiments, the gate metal  112  of the gate  108 - 1  may extend between the spacers  134  on the sides of the gate  106 - 1  and the gate  106 - 2 . Thus, the gate metal  112  of the gate  108 - 1  may have a shape that is substantially complementary to the shape of the spacers  134 , as shown. Similarly, the gate  108 - 2  may extend between the proximate spacers  134  on the sides of the gate  106 - 2  and the gate  106 - 3 . In some embodiments in which the gate dielectric  114  is not a layer shared commonly between the gates  108  and  106 , but instead is separately deposited on the fin  104  between the spacers  134  (e.g., as discussed below with reference to  FIGS.  58 - 61   ), the gate dielectric  114  may extend at least partially up the sides of the spacers  134 , and the gate metal  112  may extend between the portions of gate dielectric  114  on the spacers  134 . The gate metal  112 , like the gate metal  110 , may be any suitable metal, such as titanium nitride. 
     The dimensions of the gates  106 / 108  may take any suitable values. For example, in some embodiments, the z-height  166  of the gate metal  110  may be between 40 nanometers and 75 nanometers (e.g., approximately 50 nanometers); the z-height of the gate metal  112  may be in the same range. In embodiments like the ones illustrated in  FIG.  3   , the z-height of the gate metal  112  may be greater than the z-height of the gate metal  110 . In some embodiments, the length  168  of the gate metal  110  (i.e., in the x-direction) may be between 20 nanometers and 40 nanometers (e.g., 30 nanometers). In some embodiments, the distance  170  between adjacent ones of the gates  106  (e.g., as measured from the gate metal  110  of one gate  106  to the gate metal  110  of an adjacent gate  106  in the x-direction, as illustrated in  FIG.  3   ) may be between 40 nanometers and 60 nanometers (e.g., 50 nanometers). In some embodiments, the thickness  172  of the spacers  134  may be between 1 nanometer and 10 nanometers (e.g., between 3 nanometers and 5 nanometers, between 4 nanometers and 6 nanometers, or between 4 nanometers and 7 nanometers). The length of the gate metal  112  (i.e., in the x-direction) may depend on the dimensions of the gates  106  and the spacers  134 , as illustrated in  FIG.  3   . As indicated in  FIG.  1   , the gates  106 / 108  on one fin  104  may extend over the insulating material  128  beyond their respective fins  104  and toward the other fin  104 , but may be isolated from their counterpart gates by the intervening insulating material  130  and spacers  134 . 
     Although all of the gates  106  are illustrated in the accompanying drawings as having the same length  168  of the gate metal  110 , in some embodiments, the “outermost” gates  106  (e.g., the gates  106 - 1  and  106 - 3  of the embodiment illustrated in  FIG.  3   ) may have a greater length  168  than the “inner” gates  106  (e.g., the gate  106 - 2  in the embodiment illustrated in  FIG.  3   ). Such longer “outside” gates  106  may provide spatial separation between the doped regions  140  and the areas under the gates  108  and the inner gates  106  in which quantum dots  142  may form, and thus may reduce the perturbations to the potential energy landscape under the gates  108  and the inner gates  106  caused by the doped regions  140 . 
     Although various ones of the accompanying figures illustrate “alternating” gate metals  110  and  112  (and “alternating” low loss dielectric materials  151 ), a quantum dot device may include more than two different gate metals (or low loss dielectric materials  151 ) that have different material structures, and these different gate metals (or low loss dielectric materials  151 ) may be arranged in any desired manner to achieve a desired strain landscape in the underlying material layers. For example, in some embodiments, three or more gate metals with different material structures may be used in place of the gate metals  110 / 112  to achieve a desired strain landscape in a quantum well layer  152 . In still other embodiments, the gate metals  110  and  112  may not induce strain in an underlying quantum well layer  152 . 
     As shown in  FIG.  3   , the gates  106  and  108  may be alternatingly arranged along the fin  104  in the x-direction. During operation of the quantum dot device  100 , voltages may be applied to the gates  106 / 108  to adjust the potential energy in the quantum well layer (not shown) in the fin  104  to create quantum wells of varying depths in which quantum dots  142  may form. Only one quantum dot  142  is labeled with a reference numeral in  FIGS.  3  and  4    for ease of illustration, but five are indicated as dotted circles in each fin  104 . The location of the quantum dots  142  in  FIG.  3    is not intended to indicate a particular geometric positioning of the quantum dots  142 . The spacers  134  may themselves provide “passive” barriers between quantum wells under the gates  106 / 108  in the quantum well layer, and the voltages applied to different ones of the gates  106 / 108  may adjust the potential energy under the gates  106 / 108  in the quantum well layer; decreasing the potential energy may form quantum wells, while increasing the potential energy may form quantum barriers. A voltage may also be applied to the conductive material  117  to help isolate the potential energy landscape in the fins  104  from extraneous influences; the conductive material  117  may thus act as electromagnetic screens or shields for the fins  104 . 
     The fins  104  may include doped regions  140  that may serve as a reservoir of charge carriers for the quantum dot device  100 . For example, an n-type doped region  140  may supply electrons for electron-type quantum dots  142 , and a p-type doped region  140  may supply holes for hole-type quantum dots  142 . In some embodiments, an interface material  141  may be disposed at a surface of a doped region  140 , as shown. The interface material  141  may facilitate electrical coupling between a conductive contact (e.g., a conductive via  136 , as discussed below) and the doped region  140 . The interface material  141  may be any suitable metal-semiconductor ohmic contact material; for example, in embodiments in which the doped region  140  includes silicon, the interface material  141  may include nickel silicide, aluminum silicide, titanium silicide, molybdenum silicide, cobalt silicide, tungsten silicide, or platinum silicide (e.g., as discussed below with reference to  FIGS.  25 - 26   ). In some embodiments, the interface material  141  may be a non-silicide compound, such as titanium nitride. In some embodiments, the interface material  141  may be a metal (e.g., aluminum, tungsten, or indium). 
     The quantum dot devices  100  disclosed herein may be used to form electron-type or hole-type quantum dots  142 . Note that the polarity of the voltages applied to the gates  106 / 108  to form quantum wells/barriers depends on the charge carriers used in the quantum dot device  100 . In embodiments in which the charge carriers are electrons (and thus the quantum dots  142  are electron-type quantum dots), amply negative voltages applied to a gate  106 / 108  may increase the potential barrier under the gate  106 / 108 , and amply positive voltages applied to a gate  106 / 108  may decrease the potential barrier under the gate  106 / 108  (thereby forming a potential well in which an electron-type quantum dot  142  may form). In embodiments in which the charge carriers are holes (and thus the quantum dots  142  are hole-type quantum dots), amply positive voltages applied to a gate  106 / 108  may increase the potential barrier under the gate  106 / 108 , and amply negative voltages applied to a gate  106  and  108  may decrease the potential barrier under the gate  106 / 108  (thereby forming a potential well in which a hole-type quantum dot  142  may form). The quantum dot devices  100  disclosed herein may be used to form electron-type or hole-type quantum dots. 
     Voltages may be applied to each of the gates  106  and  108  separately to adjust the potential energy in the quantum well layer under the gates  106  and  108 , and thereby control the formation of quantum dots  142  under each of the gates  106  and  108 . Additionally, the relative potential energy profiles under different ones of the gates  106  and  108  allow the quantum dot device  100  to tune the potential interaction between quantum dots  142  under adjacent gates. For example, if two adjacent quantum dots  142  (e.g., one quantum dot  142  under a gate  106  and another quantum dot  142  under a gate  108 ) are separated by only a short potential barrier, the two quantum dots  142  may interact more strongly than if they were separated by a taller potential barrier. Since the depth of the potential wells/height of the potential barriers under each gate  106 / 108  may be adjusted by adjusting the voltages on the respective gates  106 / 108 , the differences in potential between adjacent gates  106 / 108  may be adjusted, and thus the interaction tuned. 
     In some applications, the gates  108  may be used as plunger gates to enable the formation of quantum dots  142  under the gates  108 , while the gates  106  may be used as barrier gates to adjust the potential barrier between quantum dots  142  formed under adjacent gates  108 . In other applications, the gates  108  may be used as barrier gates, while the gates  106  are used as plunger gates. In other applications, quantum dots  142  may be formed under all of the gates  106  and  108 , or under any desired subset of the gates  106  and  108 . 
     Conductive vias and lines may make contact with the gates  106 / 108 , and to the doped regions  140 , to enable electrical connection to the gates  106 / 108  and the doped regions  140  to be made in desired locations. Conductive vias and lines (not shown) may also make contact with the conductive material  117  to enable electrical signals to be provided to the conductive material  117 . As shown in  FIGS.  1 - 4   , the gates  106  may extend away from the fins  104 , and conductive vias  120  may contact the gates  106  (and are drawn in dashed lines in  FIG.  3    to indicate their location behind the plane of the drawing). The conductive vias  120  may extend through the hardmask  116  and the hardmask  118  to contact the gate metal  110  of the gates  106 . The gates  108  may extend away from the fins  104 , and conductive vias  122  may contact the gates  108  (also drawn in dashed lines in  FIG.  3    to indicate their location behind the plane of the drawing). The conductive vias  122  may extend through the hardmask  118  to contact the gate metal  112  of the gates  108 . Conductive vias  136  may contact the interface material  141  and may thereby make electrical contact with the doped regions  140 . The quantum dot device  100  may include further conductive vias and/or lines (not shown) to make electrical contact to the gates  106 / 108  and/or the doped regions  140 , as desired. The conductive vias and lines included in a quantum dot device  100  may include any suitable materials, such as copper, tungsten (deposited, e.g., by chemical vapor deposition (CVD)), or a superconductor (e.g., aluminum, tin, titanium nitride, niobium titanium nitride, tantalum, niobium, or other niobium compounds such as niobium tin and niobium germanium). 
     During operation, a bias voltage may be applied to the doped regions  140  (e.g., via the conductive vias  136  and the interface material  141 ) to cause current to flow through the doped regions  140 . When the doped regions  140  are doped with an n-type material, this voltage may be positive; when the doped regions  140  are doped with a p-type material, this voltage may be negative. The magnitude of this bias voltage may take any suitable value (e.g., between 0.25 volts and 2 volts). 
     The quantum dot device  100  may include one or more magnet lines  121 . For example, a single magnet line  121  is illustrated in  FIGS.  1 - 4    proximate to the fin  104 - 1 . The magnet line  121  may be formed of a conductive material, and may be used to conduct current pulses that generate magnetic fields to influence the spin states of one or more of the quantum dots  142  that may form in the fins  104 . In some embodiments, the magnet line  121  may conduct a pulse to reset (or “scramble”) nuclear and/or quantum dot spins. In some embodiments, the magnet line  121  may conduct a pulse to initialize an electron in a quantum dot in a particular spin state. In some embodiments, the magnet line  121  may conduct current to provide a continuous, oscillating magnetic field to which the spin of a qubit may couple. The magnet line  121  may provide any suitable combination of these embodiments, or any other appropriate functionality. 
     In some embodiments, the magnet line  121  may be formed of copper. In some embodiments, the magnet line  121  may be formed of a superconductor, such as aluminum. The magnet line  121  illustrated in  FIGS.  1 - 4    is non-coplanar with the fins  104 , and is also non-coplanar with the gates  106 / 108 . In some embodiments, the magnet line  121  may be spaced apart from the gates  106 / 108  by a distance  167 . The distance  167  may take any suitable value (e.g., based on the desired strength of magnetic field interaction with the quantum dots  142 ); in some embodiments, the distance  167  may be between 25 nanometers and 1 micron (e.g., between 50 nanometers and 200 nanometers). 
     In some embodiments, the magnet line  121  may be formed of a magnetic material. For example, a magnetic material (such as cobalt) may be deposited in a trench in the insulating material  130  to provide a permanent magnetic field in the quantum dot device  100 . 
     The magnet line  121  may have any suitable dimensions. For example, the magnet line  121  may have a thickness  169  between 25 nanometers and 100 nanometers. The magnet line  121  may have a width  171  between 25 nanometers and 100 nanometers. In some embodiments, the width  171  and thickness  169  of a magnet line  121  may be equal to the width and thickness, respectively, of other conductive lines in the quantum dot device  100  (not shown) used to provide electrical interconnects, as known in the art. The magnet line  121  may have a length  175  that may depend on the number and dimensions of the gates  106 / 108  that are to form quantum dots  142  with which the magnet line  121  is to interact. The magnet line  121  illustrated in  FIGS.  1 - 4    (and the magnet lines  121  illustrated in  FIGS.  37 - 39    below) are substantially linear, but this need not be the case; the magnet lines  121  disclosed herein may take any suitable shape. Conductive vias  123  may contact the magnet line  121 . 
     The conductive vias  120 ,  122 ,  136 , and  123  may be electrically isolated from each other by an insulating material  130 . The insulating material  130  may be any suitable material, such as an interlayer dielectric (ILD). Examples of the insulating material  130  may include silicon oxide, silicon nitride, aluminum oxide, carbon-doped oxide, and/or silicon oxynitride. As known in the art of integrated circuit manufacturing, conductive vias and lines may be formed in an iterative process in which layers of structures are formed on top of each other. In some embodiments, the conductive vias  120 / 122 / 136 / 123  may have a width that is 20 nanometers or greater at their widest point (e.g., 30 nanometers), and a pitch of 80 nanometers or greater (e.g., 100 nanometers). In some embodiments, conductive lines (not shown) included in the quantum dot device  100  may have a width that is 100 nanometers or greater, and a pitch of 100 nanometers or greater. The particular arrangement of conductive vias shown in  FIGS.  1 - 4    is simply illustrative, and any electrical routing arrangement may be implemented. 
     As discussed above, the structure of the fin  104 - 1  may be the same as the structure of the fin  104 - 2 ; similarly, the construction of gates  106 / 108  on the fin  104 - 1  may be the same as the construction of gates  106 / 108  on the fin  104 - 2 . The gates  106 / 108  on the fin  104 - 1  may be mirrored by corresponding gates  106 / 108  on the parallel fin  104 - 2 , and the insulating material  128  may separate the gates  106 / 108  on the different fins  104 - 1  and  104 - 2 . In particular, quantum dots  142  formed in the fin  104 - 1  (under the gates  106 / 108 ) may have counterpart quantum dots  142  in the fin  104 - 2  (under the corresponding gates  106 / 108 ). In some embodiments, the quantum dots  142  in the fin  104 - 1  may be used as “active” quantum dots in the sense that these quantum dots  142  act as qubits and are controlled (e.g., by voltages applied to the gates  106 / 108  of the fin  104 - 1 ) to perform quantum computations. The quantum dots  142  in the fin  104 - 2  may be used as “read” quantum dots in the sense that these quantum dots  142  may sense the quantum state of the quantum dots  142  in the fin  104 - 1  by detecting the electric field generated by the charge in the quantum dots  142  in the fin  104 - 1 , and may convert the quantum state of the quantum dots  142  in the fin  104 - 1  into electrical signals that may be detected by the gates  106 / 108  on the fin  104 - 2 . Each quantum dot  142  in the fin  104 - 1  may be read by its corresponding quantum dot  142  in the fin  104 - 2 . Thus, the quantum dot device  100  enables both quantum computation and the ability to read the results of a quantum computation. 
     The quantum dot devices  100  disclosed herein may be manufactured using any suitable techniques.  FIGS.  5 - 36    illustrate various example stages in the manufacture of the quantum dot device  100  of  FIGS.  1 - 4   , in accordance with various embodiments. Although the particular manufacturing operations discussed below with reference to  FIGS.  5 - 36    are illustrated as manufacturing a particular embodiment of the quantum dot device  100 , these operations may be applied to manufacture many different embodiments of the quantum dot device  100 , as discussed herein. Any of the elements discussed below with reference to  FIGS.  5 - 36    may take the form of any of the embodiments of those elements discussed above (or otherwise disclosed herein). 
       FIG.  5    is a cross-sectional view of an assembly  200  including a substrate  144 . The substrate  144  may include any suitable semiconductor material or materials. In some embodiments, the substrate  144  may include a semiconductor material. For example, the substrate  144  may include silicon (e.g., may be formed from a silicon wafer). Various embodiments of the substrate  144  are discussed below with reference to  FIGS.  40 - 42   . 
       FIG.  6    is a cross-sectional view of an assembly  201  subsequent to providing a quantum well stack  146  on the substrate  144  of the assembly  200  ( FIG.  5   ). The quantum well stack  146  may include a quantum well layer (not shown) in which a 2DEG may form during operation of the quantum dot device  100 . Various embodiments of the quantum well stack  146  are discussed below with reference to  FIGS.  40 - 42   . 
       FIG.  7    is a cross-sectional view of an assembly  202  subsequent to forming fins  104  in the assembly  201  ( FIG.  6   ). The fins  104  may extend from a base  102 , and may be formed in the assembly  201  by patterning and then etching the assembly  201 , as known in the art. For example, a combination of dry and wet etch chemistry may be used to form the fins  104 , and the appropriate chemistry may depend on the materials included in the assembly  201 , as known in the art. At least some of the substrate  144  may be included in the base  102 , and at least some of the quantum well stack  146  may be included in the fins  104 . In particular, the quantum well layer (not shown) of the quantum well stack  146  may be included in the fins  104 . Example arrangements in which the quantum well stack  146  and the substrate  144  are differently included in the base  102  and the fins  104  are discussed below with reference to  FIGS.  43 - 49   . 
       FIG.  8    is a cross-sectional view of an assembly  203  subsequent to forming a conformal layer of dielectric material  131  on the fins  104  and the exposed surfaces of the base  102  of the assembly  202  ( FIG.  7   ). In some embodiments, the dielectric material  131  may be formed by oxidizing the material of the fins  104  and the exposed surfaces of the base  102  to a desired depth equal to the thickness  137 . For example, when the fins  104  include silicon, the dielectric material  131  may be thermally grown silicon oxide. In some embodiments, the dielectric material  131  may be formed using a conformal deposition process, such as atomic layer deposition (ALD) to a thickness  137 .  FIG.  8    (and others of the accompanying figures) illustrate the dielectric material  131  on the surface of the base  102 ; in some embodiments, the dielectric material  131  may be removed from the surface of the base  102  (e.g., by performing a directional etch) while leaving the dielectric material  131  on side faces of the fins  104 ; in such embodiments, the dielectric material  131  may not be present on the surface of the base  102  in the quantum dot device  100 . 
       FIG.  9    is a cross-sectional view of an assembly  204  subsequent to forming a conformal layer of conductive material  117  on the dielectric material  131  (over the fins  104  and the exposed surfaces of the base  102 ) of the assembly  203  ( FIG.  8   ). The conductive material  117  may be formed using a conformal deposition process, such as ALD, to a desired thickness  119 .  FIG.  9    (and others of the accompanying figures) illustrate the conductive material  117  on the “horizontal surfaces” of the assembly  204  (e.g., on the dielectric material  131  on the surface of the base  102 ); in some embodiments, the conductive material  117  may be removed from the horizontal surfaces of the assembly  204  (e.g., by performing a directional etch) while leaving the conductive material  117  on side faces of the fins  104 ; in such embodiments, the conductive material  117  may not be present on the horizontal surface proximate to the surface of the base  102  in the quantum dot device  100 . 
       FIG.  10    is a cross-sectional view of an assembly  205  subsequent to providing an insulating material  128  on the assembly  204  ( FIG.  9   ). The insulating material  128  may take the form of any of the embodiments disclosed herein (e.g., an oxide, a nitride, a carbosilane, etc.). As initially deposited, the insulating material  128  may extend over the fins  104 . 
       FIG.  11 A  is a cross-sectional view of an assembly  206  subsequent to planarizing the assembly  205  ( FIG.  10   ) to remove the dielectric material  131 , the conductive material  117 , and the insulating material  128  above the fins  104 . In some embodiments, the assembly  205  may be planarized using a chemical mechanical polishing (CMP) technique. In some embodiments, the planarization operation may stop once the dielectric material  131  is reached (i.e., the planarization operation may remove the conductive material  117  and the insulating material  128  above the fins  104 , but the dielectric material  131  may remain above the fins  104 ). In such an embodiment, the dielectric material  131  may be present on top of the fins  104  in the quantum dot device  100 , between the fins  104  and the gate metal  110 / 112  of the gates  106 / 108 . Any of the embodiments of the quantum dot devices  100  disclosed herein may include the dielectric material  131  on the top surfaces of the fins  104 .  FIG.  11 B  is a perspective view of at least a portion of the assembly  206 , showing the fins  104  extending from the base  102  and separated by the dielectric material  131 , the conductive material  117 , and the insulating material  128 . The cross-sectional views of  FIGS.  5 - 11 A  are taken parallel to the plane of the page of the perspective view of  FIG.  11 B . 
       FIG.  12    is a perspective view of an assembly  207  subsequent to recessing select portions of the dielectric material  131 , the conductive material  117 , and the insulating material  128  of the assembly  206  ( FIG.  11   ). In the embodiment of  FIG.  12   , the recessed portions of the dielectric material  131 , the conductive material  117 , and the insulating material  128  may be the portions that will correspond to the low loss dielectric material  151 - 1 , as discussed further below. The dielectric material  131 , the conductive material  117 , and the insulating material  128  may be selectively recessed by providing and patterning a mask material that covers the portions of the dielectric material  131 , the conductive material  117 , and the insulating material  128  that are not to be recessed, etching the exposed dielectric material  131 , the conductive material  117 , and the insulating material  128 , and then removing the mask material. The depth of the recess may equal the depth  153  of the low loss dielectric materials  151 , discussed above. In embodiments in which the low loss dielectric material  151  does not span the distance between adjacent fins  104  (e.g., as discussed above and as discussed below with reference to  FIG.  51   ), or when the low loss dielectric material  151  is only to be present between the fins  104  (and not in the volume “outside” the fins  104 , as discussed below), the pattern of the recessing in the assembly  207  may be adjusted accordingly. 
       FIG.  13    is a perspective view of an assembly  208  subsequent to providing a low loss dielectric material  151 - 1  on the assembly  207  ( FIG.  12   ) and then planarizing the result to remove any low loss dielectric material  151 - 1  above the fins  104 . Any suitable technique may be used to deposit the low loss dielectric material  151 - 1  (e.g., any technique that will allow the low loss dielectric material  151 - 1  to fill the recesses in the dielectric material  131 , the conductive material  117 , and the insulating material  128  of the assembly  207 ). 
       FIG.  14    is a perspective view of an assembly  209  subsequent to recessing select portions of the dielectric material  131 , the conductive material  117 , and the insulating material  128  of the assembly  208  ( FIG.  13   ). In the embodiment of  FIG.  14   , the recessed portions of the dielectric material  131 , the conductive material  117 , and the insulating material  128  may be the portions that will correspond to the low loss dielectric material  151 - 2 , as discussed further below. The dielectric material  131 , the conductive material  117 , and the insulating material  128  may be selectively recessed as discussed above with reference to  FIG.  12   . 
       FIG.  15 A  is a perspective view of an assembly  210  subsequent to providing a low loss dielectric material  151 - 2  on the assembly  209  ( FIG.  14   ) and then planarizing the result to remove any low loss dielectric material  151 - 2  above the fins  104 . Any suitable technique may be used to deposit the low loss dielectric material  151 - 2 , as discussed above with reference to  FIG.  14   . Note that, in embodiments in which only a single low loss dielectric material  151  is used in the quantum dot device  100 , only one recessing/deposition process need be performed (e.g., as discussed below with reference to  FIG.  53   ). Further, although a particular pattern of low loss dielectric materials  151  is illustrated in  FIG.  15 A , the techniques discussed herein may be used to create any desired pattern of one or more low loss dielectric materials  151  around a top portion of one or more fins  104  in a quantum dot device  100 .  FIG.  15 B  is a cross-sectional view of the assembly  210 , taken along the dashed line along the fin  104 - 1  in  FIG.  15 A . The cross-sectional views illustrated in  FIGS.  14 - 27 ,  29 ,  31 ,  33 , and  35    are taken along the same cross-section as  FIG.  15 B . The cross-sectional views illustrated in  FIGS.  28 ,  30 ,  32 ,  34   , and  36  are taken along the same cross-section as  FIG.  11 A . 
       FIG.  16    is a cross-sectional view of an assembly  214  subsequent to forming and patterning a gate stack on the fins  104  of the assembly  210  ( FIG.  15   ) to form the gates  106 . The gate stack may include the gate dielectric  114 , the gate metal  110 , and a hardmask  116 . The hardmask  116  may be formed of an electrically insulating material, such as silicon nitride or carbon-doped nitride. In some embodiments, the hardmask  116  may be patterned, and then that pattern may be transferred to the gate metal  110 . The pattern applied to the hardmask  116  may correspond to the locations for the gates  106 , as discussed below. The hardmask  116  may be patterned by applying a resist, patterning the resist using lithography, and then etching the hardmask (using dry etching or any appropriate technique). Subsequently, the gate metal  110  that is not protected by the patterned hardmask  116  may be removed, resulting in the gates  106 . In some embodiments, as illustrated in  FIG.  16   , the gate dielectric  114  may remain after the gate metal  110  is etched away; in other embodiments, the gate dielectric  114  may also be etched during the etching of the gate metal  110 . Examples of such embodiments are discussed below with reference to  FIGS.  58 - 61   . 
       FIG.  17    is a cross-sectional view of an assembly  216  subsequent to providing spacer material  132  on the assembly  214  ( FIG.  16   ). The spacer material  132  may include any of the materials discussed above with reference to the spacers  134 , for example, and may be deposited using any suitable technique. For example, the spacer material  132  may be a nitride material (e.g., silicon nitride) deposited by sputtering. 
       FIG.  18    is a cross-sectional view of an assembly  218  subsequent to etching the spacer material  132  of the assembly  216  ( FIG.  17   ), leaving spacers  134  formed of the spacer material  132  on the sides of the gates  106  (e.g., on the sides of the hardmask  116  and the gate metal  110 ). The etching of the spacer material  132  may be an anisotropic etch, etching the spacer material  132  “downward” to remove the spacer material  132  on top of the gates  106  and in some of the area between the gates  106 , while leaving the spacers  134  on the sides of the gates  106 . In some embodiments, the anisotropic etch may be a dry etch. 
       FIG.  19    is a cross-sectional view of an assembly  220  subsequent to providing the gate metal  112  on the assembly  218  ( FIG.  18   ). The gate metal  112  may fill the areas between adjacent ones of the gates  106 , and may extend over the tops of the gates  106 . 
       FIG.  20    is a cross-sectional view of an assembly  222  subsequent to planarizing the assembly  220  ( FIG.  19   ) to remove the gate metal  112  above the gates  106 . In some embodiments, the assembly  220  may be planarized using a CMP technique. Some of the remaining gate metal  112  may fill the areas between adjacent ones of the gates  106 , while other portions  150  of the remaining gate metal  112  may be located “outside” of the gates  106 . 
       FIG.  21    is a cross-sectional view of an assembly  224  subsequent to providing a hardmask  118  on the planarized surface of the assembly  222  ( FIG.  20   ). The hardmask  118  may be formed of any of the materials discussed above with reference to the hardmask  116 , for example. 
       FIG.  22    is a cross-sectional view of an assembly  226  subsequent to patterning the hardmask  118  of the assembly  224  ( FIG.  21   ). The pattern applied to the hardmask  118  may extend over the hardmask  116 , over the gate metal  110  of the gates  106 , and over the locations for the gates  108  (as illustrated in  FIG.  3   ). The hardmask  118  may be non-coplanar with the hardmask  116 , as illustrated in  FIG.  22   . The hardmask  118  illustrated in  FIG.  22    may thus be a common, continuous portion of hardmask  118  that extends over all of the hardmask  116 . The hardmask  118  may be patterned using any of the techniques discussed above with reference to the patterning of the hardmask  116 , for example. 
       FIG.  23    is a cross-sectional view of an assembly  228  subsequent to etching the assembly  226  ( FIG.  22   ) to remove the portions  150  that are not protected by the patterned hardmask  118  to form the gates  108 . Portions of the hardmask  118  may remain on top of the hardmask  116 , as shown. The operations performed on the assembly  226  may include removing any gate dielectric  114  that is “exposed” on the fin  104 , as shown. The excess gate dielectric  114  may be removed using any suitable technique, such as chemical etching or silicon bombardment. 
       FIG.  24    is a cross-sectional view of an assembly  230  subsequent to doping the fins  104  of the assembly  228  ( FIG.  23   ) to form doped regions  140  in the portions of the fins  104  “outside” of the gates  106 / 108 . The type of dopant used to form the doped regions  140  may depend on the type of quantum dot desired, as discussed above. In some embodiments, the doping may be performed by ion implantation. For example, when the quantum dot  142  is to be an electron-type quantum dot  142 , the doped regions  140  may be formed by ion implantation of phosphorous, arsenic, or another n-type material. When the quantum dot  142  is to be a hole-type quantum dot  142 , the doped regions  140  may be formed by ion implantation of boron or another p-type material. An annealing process that activates the dopants and causes them to diffuse farther into the fins  104  may follow the ion implantation process. The depth of the doped regions  140  may take any suitable value; for example, in some embodiments, the doped regions  140  may extend into the fin  104  to a depth  115  between 500 Angstroms and 1000 Angstroms. 
     The outer spacers  134  on the outer gates  106  may provide a doping boundary, limiting diffusion of the dopant from the doped regions  140  into the area under the gates  106 / 108 . As shown, the doped regions  140  may extend under the adjacent outer spacers  134 . In some embodiments, the doped regions  140  may extend past the outer spacers  134  and under the gate metal  110  of the outer gates  106 , may extend only to the boundary between the outer spacers  134  and the adjacent gate metal  110 , or may terminate under the outer spacers  134  and not reach the boundary between the outer spacers  134  and the adjacent gate metal  110 . The doping concentration of the doped regions  140  may, in some embodiments, be between 10 17 /cm 3  and 10 20 /cm 3 . 
       FIG.  25    is a cross-sectional view of an assembly  232  subsequent to providing a layer of nickel or other material  143  over the assembly  230  ( FIG.  24   ). The nickel or other material  143  may be deposited on the assembly  230  using any suitable technique (e.g., a plating technique, CVD, or ALD). 
       FIG.  26    is a cross-sectional view of an assembly  234  subsequent to annealing the assembly  232  ( FIG.  25   ) to cause the material  143  to interact with the doped regions  140  to form the interface material  141 , then removing the unreacted material  143 . When the doped regions  140  include silicon and the material  143  includes nickel, for example, the interface material  141  may be nickel silicide. Materials other than nickel may be deposited in the operations discussed above with reference to  FIG.  25    in order to form other interface materials  141 , including titanium, aluminum, molybdenum, cobalt, tungsten, or platinum, for example. More generally, the interface material  141  of the assembly  234  may include any of the materials discussed herein with reference to the interface material  141 . 
       FIG.  27    is a cross-sectional view of an assembly  236  subsequent to providing an insulating material  130  on the assembly  234  ( FIG.  26   ). The insulating material  130  may take any of the forms discussed above. For example, the insulating material  130  may be a dielectric material, such as silicon oxide. The insulating material  130  may be provided on the assembly  234  using any suitable technique, such as spin coating, CVD, or plasma-enhanced CVD (PECVD). In some embodiments, the insulating material  130  may be polished back after deposition, and before further processing. In some embodiments, the thickness  173  of the insulating material  130  provided on the assembly  236  (as measured from the hardmask  118 , as indicated in  FIG.  27   ) may be between 50 nanometers and 1.2 microns (e.g., between 50 nanometers and 300 nanometers).  FIG.  28    is another cross-sectional view of the assembly  236 , taken along the section C-C of  FIG.  27   . 
       FIG.  29    is a cross-sectional view of an assembly  238  subsequent to forming a trench  125  in the insulating material  130  of the assembly  236  ( FIGS.  27  and  28   ). The trench  125  may be formed using any desired techniques (e.g., resist patterning followed by etching), and may have a depth  127  and a width  129  that may take the form of any of the embodiments of the thickness  169  and the width  171 , respectively, discussed above with reference to the magnet line  121 .  FIG.  30    is another cross-sectional view of the assembly  238 , taken along the section C-C of  FIG.  29   . In some embodiments, the assembly  236  may be planarized to remove the hardmasks  116  and  118 , then additional insulating material  130  may be provided on the planarized surface before forming the trench  125 ; in such an embodiment, the hardmasks  116  and  118  would not be present in the quantum dot device  100 . 
       FIG.  31    is a cross-sectional view of an assembly  240  subsequent to filling the trench  125  of the assembly  238  ( FIGS.  29  and  30   ) with a conductive material to form the magnet line  121 . The magnet line  121  may be formed using any desired techniques (e.g., plating followed by planarization, or a semi-additive process), and may take the form of any of the embodiments disclosed herein.  FIG.  32    is another cross-sectional view of the assembly  240 , taken along the section C-C of  FIG.  31   . 
       FIG.  33    is a cross-sectional view of an assembly  242  subsequent to providing additional insulating material  130  on the assembly  240  ( FIGS.  31  and  32   ). The insulating material  130  provided on the assembly  240  may take any of the forms of the insulating material  130  discussed above.  FIG.  34    is another cross-sectional view of the assembly  242 , taken along the section C-C of  FIG.  33   . 
       FIG.  35    is a cross-sectional view of an assembly  244  subsequent to forming, in the assembly  242  ( FIGS.  33  and  34   ), conductive vias  120  through the insulating material  130  (and the hardmasks  116  and  118 ) to contact the gate metal  110  of the gates  106 , conductive vias  122  through the insulating material  130  (and the hardmask  118 ) to contact the gate metal  112  of the gates  108 , conductive vias  136  through the insulating material  130  to contact the interface material  141  of the doped regions  140 , and conductive vias  123  through the insulating material  130  to contact the magnet line  121 .  FIG.  36    is another cross-sectional view of the assembly  244 , taken along the section C-C of  FIG.  35   . Further conductive vias and/or lines (e.g., to the conductive material  117 ) may be formed in the assembly  244  using conventional interconnect techniques, if desired. The resulting assembly  244  may take the form of the quantum dot device  100  discussed above with reference to  FIGS.  1 - 4   . 
     In the embodiment of the quantum dot device  100  illustrated in  FIGS.  1 - 4   , the magnet line  121  is oriented parallel to the longitudinal axes of the fins  104 . In other embodiments, the magnet line  121  may not be oriented parallel to the longitudinal axes of the fins  104 . For example,  FIGS.  37 - 39    are various cross-sectional views of an embodiment of a quantum dot device  100  having multiple magnet lines  121 , each proximate to the fins  104  and oriented perpendicular to the longitudinal axes of the fins  104 . Other than orientation, the magnet lines  121  of the embodiment of  FIGS.  37 - 39    may take the form of any of the embodiments of the magnet line  121  discussed above. The other elements of the quantum dot devices  100  of  FIGS.  37 - 39    may take the form of any of those elements discussed herein. The manufacturing operations discussed above with reference to  FIGS.  5 - 36    may be used to manufacture the quantum dot device  100  of  FIGS.  37 - 39   . 
     Although a single magnet line  121  is illustrated in  FIGS.  1 - 4   , multiple magnet lines  121  may be included in that embodiment of the quantum dot device  100  (e.g., multiple magnet lines  121  parallel to the longitudinal axes of the fins  104 ). For example, the quantum dot device  100  of  FIGS.  1 - 4    may include a second magnet line  121  proximate to the fin  104 - 2  in a symmetric manner to the magnet line  121  illustrated proximate to the fin  104 - 1 . In some embodiments, multiple magnet lines  121  may be included in a quantum dot device  100 , and these magnet lines  121  may or may not be parallel to one another. For example, in some embodiments, a quantum dot device  100  may include two (or more) magnet lines  121  that are oriented perpendicular to each other (e.g., one or more magnet lines  121  oriented like those illustrated in  FIGS.  1 - 4   , and one or more magnet lines  121  oriented like those illustrated in  FIGS.  37 - 39   ). 
     As discussed above, the base  102  and the fin  104  of a quantum dot device  100  may be formed from a substrate  144  and a quantum well stack  146  disposed on the substrate  144 . The quantum well stack  146  may include a quantum well layer in which a 2DEG may form during operation of the quantum dot device  100 . The quantum well stack  146  may take any of a number of forms, several of which are discussed below with reference to  FIGS.  40 - 42   . The various layers in the quantum well stacks  146  discussed below may be grown on the substrate  144  (e.g., using epitaxial processes). Although the singular term “layer” may be used to refer to various components of the quantum well stack  146  of  FIGS.  40 - 42   , any of the layers discussed below may include multiple materials arranged in any suitable manner. In embodiments in which a quantum well stack  146  includes layers other than a quantum well layer  152 , layers other than the quantum well layer  152  in a quantum well stack  146  may have higher threshold voltages for conduction than the quantum well layer  152  so that when the quantum well layer  152  is biased at its threshold voltages, the quantum well layer  152  conducts and the other layers of the quantum well stack  146  do not. This may avoid parallel conduction in both the quantum well layer  152  and the other layers, and thus avoid compromising the strong mobility of the quantum well layer  152  with conduction in layers having inferior mobility. In some embodiments, silicon used in a quantum well stack  146  (e.g., in a quantum well layer  152 ) may be grown from precursors enriched with the 28Si isotope. In some embodiments, germanium used in a quantum well stack  146  (e.g., in a quantum well layer  152 ) may be grown from precursors enriched with the 70Ge, 72Ge, or 74Ge isotope. As noted above, different regions of a quantum well layer  152  of a quantum dot device  100  may be relaxed or strained (e.g., depending upon the differential material structure of the gate metals  110  and  112  proximate to those regions of the quantum well layer  152 ). Further, when additional material layers in a quantum well stack are disposed between the quantum well layer  152  and the gate metal  110 / 112  (e.g., a barrier layer  156 , as discussed below), different regions of those material layers may be relaxed or strained depending upon the differential material structure of the gate metals  110  and  112  proximate to those regions of the material layers. 
       FIG.  40    is a cross-sectional view of a quantum well stack  146  on a substrate  144 . The quantum well stack  146  may include a buffer layer  154  on the substrate  144 , and a quantum well layer  152  on the buffer layer  154 . In some embodiments of the quantum dot device  100  including the arrangement of  FIG.  40   , the gate dielectric  114  (not shown) may be directly on the quantum well layer  152 . The quantum well layer  152  may be formed of a material such that, during operation of the quantum dot device  100 , a 2DEG may form in the quantum well layer  152  proximate to the upper surface of the quantum well layer  152 . 
     In some embodiments, the quantum well layer  152  of  FIG.  40    may be formed of intrinsic silicon, and the gate dielectric  114  may be formed of silicon oxide; in such an arrangement, during use of the quantum dot device  100 , a 2DEG may form in the intrinsic silicon at the interface between the intrinsic silicon and the silicon oxide. Embodiments in which the quantum well layer  152  of  FIG.  40    is formed of intrinsic silicon may be particularly advantageous for electron-type quantum dot devices  100 . In some embodiments, the quantum well layer  152  of  FIG.  40    may be formed of intrinsic germanium, and the gate dielectric  114  may be formed of germanium oxide; in such an arrangement, during use of the quantum dot device  100 , a 2DEG may form in the intrinsic germanium at the interface between the intrinsic germanium and the germanium oxide. Such embodiments may be particularly advantageous for hole-type quantum dot devices  100 . In some embodiments, the quantum well layers  152  disclosed herein may be differentially strained, with its strain induced by the gate metal  110 / 112 , as discussed above; in other embodiments, the quantum well layers  152  may not be strained by the gate metal  110 / 112 . 
     The buffer layer  154  may be formed of the same material as the quantum well layer  152  (e.g., silicon or germanium), and may be present to trap defects that form in this material as it is grown on the substrate  144 . In some embodiments, the buffer layer  154  may be grown under different conditions (e.g., deposition temperature or growth rate) from the quantum well layer  152 . In particular, the quantum well layer  152  may be grown under conditions that achieve fewer defects than in the buffer layer  154 . In some embodiments of the quantum well stack  146 , no buffer layer  154  may be present; thus, a quantum well stack  146  may include a single material layer. 
       FIG.  41    is a cross-sectional view of an arrangement including a quantum well stack  146  that includes a buffer layer  154 , a barrier layer  156 - 1 , a quantum well layer  152 , and an additional barrier layer  156 - 2 . The barrier layer  156 - 1  ( 156 - 2 ) may provide a potential barrier between the quantum well layer  152  and the buffer layer  154  (gate dielectric  114 , not shown). In some embodiments in which the quantum well layer  152  includes silicon or germanium, the barrier layers  156  may include silicon germanium. The germanium content of this silicon germanium may be between 20 atomic-percent and 80 atomic-percent (e.g., between 30 atomic-percent and 70 atomic-percent). 
     In some embodiments of the arrangement of  FIG.  41   , the buffer layer  154  and the barrier layer  156 - 1  may be formed of silicon germanium. In some such embodiments, the silicon germanium of the buffer layer  154  may have a germanium content that varies (e.g., continuously or in a stepwise manner) from the substrate  144  to the barrier layer  156 - 1 ; for example, the silicon germanium of the buffer layer  154  may have a germanium content that varies from zero percent at the substrate to a nonzero percent (e.g., between 30 atomic-percent and 70 atomic-percent) at the barrier layer  156 - 1 . The barrier layer  156 - 1  may in turn have a germanium content equal to the nonzero percent. In other embodiments, the buffer layer  154  may have a germanium content equal to the germanium content of the barrier layer  156 - 1  but may be thicker than the barrier layer  156 - 1  to absorb the defects that arise during growth. In some embodiments of the quantum well stack  146  of  FIG.  41   , the barrier layer  156 - 2  may be omitted. 
       FIG.  42    is a cross-sectional view of another example quantum well stack  146  on an example substrate  144 . The quantum well stack  146  of  FIG.  42    may include an insulating layer  155  on the substrate  144 , a quantum well layer  152  on the insulating layer  155 , and a barrier layer  156  on the quantum well layer  152 . The presence of the insulating layer  155  may help confine carriers to the quantum well layer  152 , providing high valley splitting during operation. 
     In some embodiments, the substrate  144  of  FIG.  42    may include silicon. The insulating layer  155  may include any suitable electrically insulating material. For example, in some embodiments, the insulating layer  155  may be an oxide (e.g., silicon oxide or hafnium oxide). The substrate  144 , the quantum well layer  152 , and/or the barrier layer  156  of  FIG.  42    may take the form of any of the embodiments disclosed herein. In some embodiments, the quantum well layer  152  may be formed on the insulating layer  155  by a layer transfer technique. In some embodiments, the barrier layer  156  may be omitted from the quantum well stack  146  of  FIG.  42   . 
     The thicknesses (i.e., z-heights) of the layers in the quantum well stacks  146  of  FIGS.  40 - 42    may take any suitable values. For example, in some embodiments, the thickness of the quantum well layer  152  may be between 5 nanometers and 15 nanometers (e.g., approximately equal to 10 nanometers). In some embodiments, the thickness of a buffer layer  154  may be between 0.3 microns and 4 microns (e.g., between 0.3 microns and 2 microns, or approximately 0.5 microns). In some embodiments, the thickness of the barrier layers  156  may be between 0 nanometers and 300 nanometers. In some embodiments, the thickness of the insulating layer  155  in the quantum well stack  146  of  FIG.  42    may be between 5 nanometers and 200 nanometers. 
     The substrate  144  and the quantum well stack  146  may be distributed between the base  102  and the fins  104  of the quantum dot device  100 , as discussed above. This distribution may occur in any of a number of ways. For example,  FIGS.  43 - 49    illustrate example base/fin arrangements  158  that may be used in a quantum dot device  100 , in accordance with various embodiments. 
     In the base/fin arrangement  158  of  FIG.  43   , the quantum well stack  146  may be included in the fins  104 , but not in the base  102 . The substrate  144  may be included in the base  102 , but not in the fins  104 . When the base/fin arrangement  158  of  FIG.  43    is used in the manufacturing operations discussed with reference to  FIGS.  6 - 7   , the fin etching may etch through the quantum well stack  146 , and stop when the substrate  144  is reached. 
     In the base/fin arrangement  158  of  FIG.  44   , the quantum well stack  146  may be included in the fins  104 , as well as in a portion of the base  102 . A substrate  144  may be included in the base  102  as well, but not in the fins  104 . When the base/fin arrangement  158  of  FIG.  44    is used in the manufacturing operations discussed with reference to  FIGS.  6 - 7   , the fin etching may etch partially through the quantum well stack  146 , and stop before the substrate  144  is reached.  FIG.  45    illustrates a particular embodiment of the base/fin arrangement  158  of  FIG.  44   . In the embodiment of  FIG.  45   , the quantum well stack  146  of  FIG.  40    is used; the base  102  includes the substrate  144  and a portion of the buffer layer  154  of the quantum well stack  146 , while the fins  104  include the remainder of the quantum well stack  146 . 
     In the base/fin arrangement  158  of  FIG.  46   , the quantum well stack  146  may be included in the fins  104 , but not the base  102 . The substrate  144  may be partially included in the fins  104 , as well as in the base  102 . When the base/fin arrangement  158  of  FIG.  46    is used in the manufacturing operations discussed with reference to  FIGS.  6 - 7   , the fin etching may etch through the quantum well stack  146  and into the substrate  144  before stopping.  FIG.  47    illustrates a particular embodiment of the base/fin arrangement  158  of  FIG.  46   . In the embodiment of  FIG.  47   , the quantum well stack  146  of  FIG.  42    is used; the fins  104  include the quantum well stack  146  and a portion of the substrate  144 , while the base  102  includes the remainder of the substrate  144 . 
     Although the fins  104  have been illustrated in many of the preceding figures as substantially rectangular with parallel sidewalls, this is simply for ease of illustration, and the fins  104  may have any suitable shape (e.g., shape appropriate to the manufacturing processes used to form the fins  104 ). For example, as illustrated in the base/fin arrangement  158  of  FIG.  48   , in some embodiments, the fins  104  may be tapered. In some embodiments, the fins  104  may taper by 3-10 nanometers in x-width for every 100 nanometers in z-height (e.g., 5 nanometers in x-width for every 100 nanometers in z-height). When the fins  104  are tapered, the wider end of the fins  104  may be the end closer to the base  102 , as illustrated in  FIG.  48   .  FIG.  49    illustrates a particular embodiment of the base/fin arrangement  158  of  FIG.  48   . In  FIG.  49   , the quantum well stack  146  is included in the tapered fins  104  while a portion of the substrate  144  is included in the tapered fins and a portion of the substrate  144  provides the base  102 .  FIG.  50    illustrates a cross-sectional view (analogous to the view of  FIG.  1   ) of a quantum dot device  100  in which the fins  104  are tapered. 
     As noted above, in some embodiments, a low loss dielectric material  151  may not “span” the distance between two adjacent fins  104 .  FIG.  51    illustrates an example of an embodiment in which the low loss dielectric material  151 - 1  around the top portion of the fin  104 - 1  under a gate  106  is spaced apart from the low loss dielectric material  151 - 1  around the top portion of the fin  104 - 2  under a gate  106  by some of the insulating material  128 ; the view of  FIG.  51    is analogous to the view of  FIG.  1   . In the quantum dot device  100  of  FIG.  51   , the low loss dielectric material  151 - 2  around the top portion of the fin  104 - 1  under a gate  108  may or may not be spaced apart from the low loss dielectric material  151 - 2  around the top portion of the fin  104 - 2  under a gate  108  (e.g., the low loss dielectric material  151 - 2  may span the distance between two fins  104 , while the low loss dielectric material  151 - 1  may not, or vice versa). 
     Although the low loss dielectric materials  151  illustrated in various ones of the accompanying drawings have been illustrated as having substantially rectangular profiles, this is simply for ease of illustration, and the low loss dielectric materials  151  may have any suitable profile (e.g., any profile corresponding to a recess formation and/or deposition technique). For example,  FIG.  52    illustrates an embodiment in which the profile of the low loss dielectric material  151 - 1  is tapered, narrowing from the top of the fin  104  toward the bottom of the fin  104 ; the view of  FIG.  52    is analogous to the view of  FIG.  1   . The profile of the low loss dielectric material  151 - 2  may be the same, or different. In other embodiments, the profile of the low loss dielectric material  151  included in a quantum dot device  100  may be curved at the bottom (e.g., shaped like a “U”). 
     As also noted above, in some embodiments, a quantum dot device  100  may include only a single low loss dielectric material  151  around the top portion of a fin  104 . For example,  FIG.  53    is a perspective view (analogous to that of  FIG.  15 A ) showing an assembly  250  (analogous to the assembly  210 ) including a single low loss dielectric material  151  around multiple fins  104 . In other embodiments, the single low loss dielectric material  151  may not span the distance between parallel fins  104 , as discussed above with reference to  FIG.  51   . 
     As noted above, in some embodiments, no distinct low loss dielectric material  151  may be included in a quantum dot device  100 . For example,  FIG.  54    is a cross-sectional view (analogous to the view of  FIG.  1   ) of a quantum dot device  100  that does not include a low loss dielectric material  151 - 1  (and may or may not include a low loss dielectric material  151 - 2 , analogously). In the volume between the fins  104 - 1  and  104 - 2 , the top surface of the conductive material  117  may be set back from the top surface of the proximate fins  104  such that the top portions of the side faces of the fins  104 - 1 / 104 - 2  that face each other are not shielded by the conductive material  117  (and thus quantum dots formed in these portions of the fins  104 - 1 / 104 - 2  may couple through the intervening insulating material  128 ). The distance  157  from the top surface of the conductive material  117  between the fins  104 - 1 / 104 - 2  to the plane of the top surface of the fins  104 - 1 / 104 - 2  may be between 5 nanometers and 50 nanometers (e.g., between 10 nanometers and 30 nanometers). If no coupling between a section of the top portion of a fin  104 - 1  and a corresponding section of the top portion of the fin  104 - 2  is desired, the conductive material  117  proximate to that section may extend all the way to the plane of the top surfaces of the fins  104 - 1 / 104 - 2  (e.g., as discussed above with reference to the low loss dielectric material  151  instead acting as a “barrier”). In the volume between the fins  104 - 1  and  104 - 2 , the top surface of the dielectric material  131  may or may not be set back from the top surface of the proximate fins  104 ;  FIG.  54    illustrates the top surface of the dielectric material  131  between the fins  104 - 1 / 104 - 2  as being coplanar with the top surfaces of the fins  104 - 1 / 104 - 2 , but in other embodiments, the dielectric material  131  may also be “recessed” like the conductive material  117 . 
       FIG.  54    also illustrates an embodiment in which, in the volumes not between the fins  104 - 1  and  104 - 2 , the top surface of the conductive material  117  may extend all the way to the plane of the top surfaces of the fins  104 - 1 / 104 - 2  (as may the top surface of the dielectric material  131 ). As noted above, when a quantum dot device  100  includes dummy fins  104 , it may be desirable to have the conductive material  117  proximate to side faces of the dummy fins  104  extend to the plane of the top surfaces of the dummy fins  104 , thereby mitigating undesired coupling between the dummy fins  104  and active/read fins  104 .  FIG.  55    is a cross-sectional view of a portion of a quantum dot device  100  that includes fins  104 - 1  and  104 - 2 , as well as dummy fins  104 - x  and  104 - y  “exterior” to the fins  104 - 1 / 104 - 2 . The fins  104 - x  and  104 - 1  are both under a single gate  106  (including a gate metal  110  and a gate dielectric  114 ), as are the fins  104 - 2  and  104 - y . The fins  104  of  FIG.  55    are illustrated as having a tapered shape that may reflect the realities of practical manufacturing processes. Further,  FIG.  55    illustrates the gate dielectric  114  as extending up the “interior” sides of the gate metal  110 ; this may occur when a replacement metal gate (RMG) process is used to form the gates  106 , as discussed further below. 
     In  FIG.  55   , the conductive material  117  may extend up to the plane of the top surfaces of the fins  104  in all regions except proximate to the top portions of the “interior” side faces of the fins  104 - 1  and  104 - 2 , as shown, to permit coupling between the top portions of the fins  104 - 1  and  104 - 2 . Although the dielectric material  131  is illustrated as extending up to the plane of the top surfaces of the fins  104 , the dielectric material  131  may also be selectively set back from this plane, as desired. As noted above, if no coupling is desired between a section of the fin  104 - 1  and a corresponding section of the fin  104 - 2 , the conductive material  117  may extend into the region between these sections of the fins  104 - 1 / 104 - 2 . No spacers  134  are depicted in  FIG.  55   , for ease of illustration. 
     Although various ones of the accompanying drawings illustrate portions of low loss dielectric material  151  adjacent to both side faces of an individual fin  104 , in some embodiments, a low loss dielectric material  151  (e.g., the low loss dielectric material  151 - 1  and/or the low loss dielectric material  151 - 2 ) may only be present adjacent to a single side of an individual fin  104 . For example, in any of the embodiments of the quantum dot devices  100  disclosed herein, a portion of low loss dielectric material  151  may be adjacent to the side face of the fin  104 - 1  that faces the fin  104 - 2 , but no portion of low loss dielectric material  151  may be adjacent to the other side face of the fin  104 - 1 ; similarly, a portion of low loss dielectric material  151  may be adjacent to the side face of the fin  104 - 2  that faces the fin  104 - 1 , but no portion of low loss dielectric material  151  may be adjacent to the other side face of the fin  104 - 2 . More generally, portions of low loss dielectric material  151  may be present in the volume between an “active” fin  104  and an adjacent “read” fin  104  (e.g., to enhance or reduce coupling between different regions of the active fin  104  and the read fin  104 ), but in some embodiments, no low loss dielectric material  151  may be present in volumes “outside” the inter-fin volume. 
     As noted above, a quantum dot device  100  may include multiple fins  104  arranged in an array of any desired size. For example,  FIG.  56    is a top cross-sectional view, like the view of  FIG.  4   , of a quantum dot device  100  having multiple fins  104  arranged in a two-dimensional array. Magnet lines  121  are not depicted in  FIG.  56   , although they may be included in any desired arrangements. In the particular example illustrated in  FIG.  56   , the fins  104  may be arranged in pairs, each pair including an “active” fin  104  and a “read” fin  104 , as discussed above. The particular number and arrangement of fins  104  in  FIG.  56    is simply illustrative, and any desired arrangement may be used. Similarly, a quantum dot device  100  may include multiple sets of fins  104  (and accompanying gates, as discussed above with reference to  FIGS.  1 - 4   ) arranged in a two-dimensional array. 
     As noted above, a single fin  104  may include multiple groups of gates  106 / 108 , spaced apart along the fin  104  by a doped region  140 .  FIG.  57    is a cross-sectional view of an example of such a quantum dot device  100  having multiple groups of gates  180  at least partially disposed in a single fin  104 , in accordance with various embodiments. Each of the groups  180  may include gates  106 / 108  (not labeled in  FIG.  57    for ease of illustration) that may take the form of any of the embodiments of the gates  106 / 108  discussed herein. A doped region  140  (and its interface material  141 ) may be disposed between two adjacent groups  180  (labeled in  FIG.  57    as groups  180 - 1  and  180 - 2 ), and may provide a common reservoir for both groups  180 . In some embodiments, this “common” doped region  140  may be electrically contacted by a single conductive via  136 . The particular number of gates  106 / 108  illustrated in  FIG.  57   , and the particular number of groups  180 , is simply illustrative, and a fin  104  may include any suitable number of gates  106 / 108  arranged in any suitable number of groups  180 . The quantum dot device  100  of  FIG.  57    may also include one or more magnet lines  121 , arranged as desired. Similarly, in embodiments of the quantum dot device  100  that include fins, a single fin  104  may include multiple groups of gates  106 / 108 , spaced apart along the fin. 
     As discussed above, in some embodiments in which the gate dielectric  114  is not a layer shared commonly between the gates  108  and  106 , but instead is separately deposited on the fins  104  between the spacers  134 , the gate dielectric  114  may extend at least partially up the sides of the spacers  134 , and the gate metal  112  may extend between the portions of gate dielectric  114  on the spacers  134 .  FIGS.  58 - 61    illustrate various alternative stages in the manufacture of such an embodiment of a quantum dot device  100 , in accordance with various embodiments. In particular, the operations illustrated in  FIGS.  58 - 61    (as discussed below) may take the place of the operations illustrated in  FIGS.  16 - 19   . 
       FIG.  58    is a cross-sectional view of an assembly  1258  subsequent to etching the assembly  214  ( FIG.  16   ) to remove the exposed gate dielectric  114 . 
       FIG.  59    is a cross-sectional view of an assembly  1260  subsequent to providing spacers  134  on the sides of the gates  106  (e.g., on the sides of the hardmask  116 , the gate metal  110 , and the gate dielectric  114 ) of the assembly  1258  ( FIG.  58   ). The provision of the spacers  134  may take any of the forms discussed above with reference to  FIGS.  17 - 18   , for example. 
       FIG.  60    is a cross-sectional view of an assembly  1262  subsequent to providing a gate dielectric  114  on the fins  104  between the gates  106  of the assembly  1260  ( FIG.  59   ). In some embodiments, the gate dielectric  114  provided between the gates  106  of the assembly  1260  may be formed by ALD and, as illustrated in  FIG.  60   , may cover the exposed fins  104  between the gates  106 , and may extend onto the adjacent spacers  134 . 
       FIG.  61    is a cross-sectional view of an assembly  1264  subsequent to providing the gate metal  112  on the assembly  1262  ( FIG.  60   ). The gate metal  112  may fill the areas on the fins  104  between adjacent ones of the gates  106 , and may extend over the tops of the gates  106 , as shown. The provision of the gate metal  112  may take any of the forms discussed above with reference to  FIG.  19   , for example. The assembly  1264  may be further processed as discussed above with reference to  FIG.  20   , for example. 
     As noted above, in some embodiments, an RMG process may be used to form the gates  106 / 108 . In an RMG process, a dummy gate dielectric may be initially deposited in place of the gate dielectric  114 , and a dummy gate metal may be initially deposited in place of the gate metal  110 / 112  (e.g., to form the assembly  222  of  FIG.  20   ). Subsequently, the dummy gate dielectric and the dummy gate metal may be removed from the gates  106  (the gates  108 ), a conformal gate dielectric  114  may be deposited, and then a gate metal  110  (gate metal  112 ) may be deposited. These “real” gates may be masked, and the process repeated for the gates  108  (gates  106 ). An RMG process may be used in conjunction with any of the embodiments disclosed herein. 
     In some embodiments, the quantum dot device  100  may be included in a die and coupled to a package substrate to form a quantum dot device package. For example,  FIG.  62    is a cross-sectional view of a die  302  including the quantum dot device  100  of  FIG.  3    and conductive pathway layers  303  disposed thereon, while  FIG.  63    is a cross-sectional view of a quantum dot device package  300  in which the die  302  and another die  350  are coupled to a package substrate  304  (e.g., in a system-on-a-chip (SoC) arrangement). Details of the quantum dot device  100  are omitted from  FIG.  63    for economy of illustration. As noted above, the particular quantum dot device  100  illustrated in  FIGS.  62  and  63    may take a form similar to the embodiment illustrated in  FIG.  3   , but any of the quantum dot devices  100  disclosed herein may be included in a die (e.g., the die  302 ) and coupled to a package substrate (e.g., the package substrate  304 ). In particular, any number of fins  104 , gates  106 / 108 , doped regions  140 , magnet lines  121 , and other components discussed herein with reference to various embodiments of the quantum dot device  100  may be included in the die  302 . 
     The die  302  may include a first face  320  and an opposing second face  322 . The base  102  may be proximate to the second face  322 , and conductive pathways  315  from various components of the quantum dot device  100  may extend to conductive contacts  365  disposed at the first face  320 . The conductive pathways  315  may include conductive vias, conductive lines, and/or any combination of conductive vias and lines. For example,  FIG.  62    illustrates an embodiment in which one conductive pathway  315  (extending between a magnet line  121  and associated conductive contact  365 ) includes a conductive via  123 , a conductive line  393 , a conductive via  398 , and a conductive line  396 . More or fewer structures may be included in the conductive pathways  315 , and analogous conductive pathways  315  may be provided between ones of the conductive contacts  365  and the gates  106 / 108 , doped regions  140 , or other components of the quantum dot device  100 . In some embodiments, conductive lines of the die  302  (and the package substrate  304 , discussed below) may extend into and out of the plane of the drawing, providing conductive pathways to route electrical signals to and/or from various elements in the die  302 . 
     The conductive vias and/or lines that provide the conductive pathways  315  in the die  302  may be formed using any suitable techniques. Examples of such techniques may include subtractive fabrication techniques, additive or semi-additive fabrication techniques, single Damascene fabrication techniques, dual Damascene fabrication techniques, or any other suitable technique. In some embodiments, layers of oxide material  390  and layers of nitride material  391  may insulate various structures in the conductive pathways  315  from proximate structures, and/or may serve as etch stops during fabrication. In some embodiments, an adhesion layer (not shown) may be disposed between conductive material and proximate insulating material of the die  302  to improve mechanical adhesion between the conductive material and the insulating material. 
     The gates  106 / 108 , the doped regions  140 , and the quantum well stack  146  (as well as the proximate conductive vias/lines) may be referred to as part of the “device layer” of the quantum dot device  100 . The conductive lines  393  may be referred to as a Metal  1  or “M 1 ” interconnect layer, and may couple the structures in the device layer to other interconnect structures. The conductive vias  398  and the conductive lines  396  may be referred to as a Metal  2  or “M 2 ” interconnect layer, and may be formed directly on the M 1  interconnect layer. 
     A solder resist material  367  may be disposed around the conductive contacts  365 , and, in some embodiments, may extend onto the conductive contacts  365 . The solder resist material  367  may be a polyimide or similar material, or may be any appropriate type of packaging solder resist material. In some embodiments, the solder resist material  367  may be a liquid or dry film material including photoimageable polymers. In some embodiments, the solder resist material  367  may be non-photoimageable (and openings therein may be formed using laser drilling or masked etch techniques). The conductive contacts  365  may provide the contacts to couple other components (e.g., a package substrate  304 , as discussed below, or another component) to the conductive pathways  315  in the quantum dot device  100 , and may be formed of any suitable conductive material (e.g., a superconducting material). For example, solder bonds may be formed on the one or more conductive contacts  365  to mechanically and/or electrically couple the die  302  with another component (e.g., a circuit board), as discussed below. The conductive contacts  365  illustrated in  FIG.  62    take the form of bond pads, but other first-level interconnect structures may be used (e.g., posts) to route electrical signals to/from the die  302 , as discussed below. 
     The combination of the conductive pathways and the proximate insulating material (e.g., the insulating material  130 , the oxide material  390 , and the nitride material  391 ) in the die  302  may provide an interlayer dielectric (ILD) stack of the die  302 . As noted above, interconnect structures may be arranged within the quantum dot device  100  to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures depicted in  FIG.  62    or any of the other accompanying figures, and may include more or fewer interconnect structures). During operation of the quantum dot device  100 , electrical signals (such as power and/or input/output (I/O) signals) may be routed to and/or from the gates  106 / 108 , the magnet line(s)  121 , and/or the doped regions  140  (and/or other components) of the quantum dot device  100  through the interconnects provided by conductive vias and/or lines, and through the conductive pathways of the package substrate  304  (discussed below). 
     Example superconducting materials that may be used for the structures in the conductive pathways  313 ,  317 ,  319  (discussed below), and  315 , and/or conductive contacts of the die  302  and/or the package substrate  304 , may include aluminum, niobium, tin, titanium, osmium, zinc, molybdenum, tantalum, vanadium, or composites of such materials (e.g., niobium titanium, niobium aluminum, or niobium tin). In some embodiments, the conductive contacts  365 ,  379 , and/or  399  may include aluminum, and the first-level interconnects  306  and/or the second-level interconnects  308  may include an indium-based solder. 
     As noted above, the quantum dot device package  300  of  FIG.  63    may include a die  302  (including one or more quantum dot devices  100 ) and a die  350 . As discussed in detail below, the quantum dot device package  300  may include electrical pathways between the die  302  and the die  350  so that the dies  302  and  350  may communicate during operation. In some embodiments, the die  350  may be a non-quantum logic device that may provide support or control functionality for the quantum dot device(s)  100  of the die  302 . For example, as discussed further below, in some embodiments, the die  350  may include a switching matrix to control the writing and reading of data from the die  302  (e.g., using any known word line/bit line or other addressing architecture). In some embodiments, the die  350  may control the voltages (e.g., microwave pulses or constant voltages) applied to the gates  106 / 108 , the doped regions  140 , and/or the conductive material  117  of the quantum dot device(s)  100  included in the die  302 . In some embodiments, the die  350  may include magnet line control logic to provide microwave pulses to the magnet line(s)  121  of the quantum dot device(s)  100  in the die  302 . The die  350  may include any desired control circuitry to support operation of the die  302 . By including this control circuitry in a separate die, the manufacture of the die  302  may be simplified and focused on the needs of the quantum computations performed by the quantum dot device(s)  100 , and conventional manufacturing and design processes for control logic (e.g., switching array logic) may be used to form the die  350 . 
     Although a singular “die  350 ” is illustrated in  FIG.  63    and discussed herein, the functionality provided by the die  350  may, in some embodiments, be distributed across multiple dies  350  (e.g., multiple dies coupled to the package substrate  304 , or otherwise sharing a common support with the die  302 ). Similarly, one or more dies providing the functionality of the die  350  may support one or more dies providing the functionality of the die  302 ; for example, the quantum dot device package  300  may include multiple dies having one or more quantum dot devices  100 , and a die  350  may communicate with one or more such “quantum dot device dies.” 
     The die  350  may take any of the forms discussed below with reference to the non-quantum processing device  2028  of  FIG.  67   . Mechanisms by which the control logic of the die  350  may control operation of the die  302  may be take the form of an entirely hardware embodiment or an embodiment combining software and hardware aspects. For example, the die  350  may implement an algorithm executed by one or more processing units, e.g. one or more microprocessors. In various embodiments, aspects of the present disclosure may take the form of a computer program product embodied in one or more computer readable medium(s), preferably non-transitory, having computer readable program code embodied (e.g., stored) in or coupled to the die  350 . In various embodiments, such a computer program may, for example, be downloaded (updated) to the die  350  (or attendant memory) or be stored upon manufacturing of the die  350 . In some embodiments, the die  350  may include at least one processor and at least one memory element, along with any other suitable hardware and/or software to enable its intended functionality of controlling operation of the die  302  as described herein. A processor of the die  350  may execute software or an algorithm to perform the activities discussed herein. A processor of the die  350  may be communicatively coupled to other system elements via one or more interconnects or buses (e.g., through one or more conductive pathways  319 ). Such a processor may include any combination of hardware, software, or firmware providing programmable logic, including by way of non-limiting example, a microprocessor, a digital signal processor (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA), an application-specific integrated circuit (ASIC), or a virtual machine processor. The processor of the die  350  may be communicatively coupled to the memory element of the die  350 , for example, in a direct-memory access (DMA) configuration. A memory element of the die  350  may include any suitable volatile or nonvolatile memory technology, including double data rate (DDR) random access memory (RAM), synchronous RAM (SRAM), dynamic RAM (DRAM), flash, read-only memory (ROM), optical media, virtual memory regions, magnetic or tape memory, or any other suitable technology. In some embodiments, the memory element and the processor of the “die  350 ” may themselves be provided by separate physical dies that are in electrical communication. The information being tracked or sent to the die  350  could be provided in any database, register, control list, cache, or storage structure, all of which can be referenced at any suitable timeframe. The die  350  can further include suitable interfaces for receiving, transmitting, and/or otherwise communicating data or information in a network environment (e.g., via the conductive pathways  319 ). 
     In some embodiments, the die  350  may be configured to apply appropriate voltages to any one of the gates  106 / 108  (acting as, e.g., plunger gates, barrier gates, and/or accumulation gates) in order to initialize and manipulate the quantum dots  142 , as discussed above. For example, by controlling the voltage applied to a gate  106 / 108  acting as a plunger gate, the die  350  may modulate the electric field underneath that gate to create an energy valley between the tunnel barriers created by adjacent barrier gates. In another example, by controlling the voltage applied to a gate  106 / 108  acting as a barrier gate, the die  350  may change the height of the tunnel barrier. When a barrier gate is used to set a tunnel barrier between two plunger gates, the barrier gate may be used to transfer charge carriers between quantum dots  142  that may be formed under these plunger gates. When a barrier gate is used to set a tunnel barrier between a plunger gate and an accumulation gate, the barrier gate may be used to transfer charge carriers in and out of the quantum dot array via the accumulation gate. The term “accumulation gate” may refer to a gate used to form a 2DEG in an area that is between the area where the quantum dots  142  may be formed and a charge carrier reservoir (e.g., the doped regions  140 ). Changing the voltage applied to the accumulation gate may allow the die  350  to control the number of charge carriers in the area under the accumulation gate. For example, changing the voltage applied to the accumulation gate may reduce the number of charge carriers in the area under the gate so that single charge carriers can be transferred from the reservoir into the quantum well layer  152 , and vice versa. In some embodiments, the “outermost” gates  106  in a quantum dot device  100  may serve as accumulation gates. In some embodiments, these outermost gates  106  may have a greater length  168  than “inner” gates  106 . Controlling a voltage applied to the conductive material  117  may enable selective isolation of the fins  104 , as discussed above. 
     As noted above, the die  350  may provide electrical signals to control spins of charge carriers in quantum dots  142  of the quantum dot device(s)  100  of the die  302  by controlling a magnetic field generated by one or more magnet line(s)  121 . In this manner, the die  350  may initialize and manipulate spins of the charge carriers in the quantum dots  142  to implement qubit operations. If the magnetic field for a die  302  is generated by a microwave transmission line, then the die  350  may set/manipulate the spins of the charge carriers by applying appropriate pulse sequences to manipulate spin precession. Alternatively, the magnetic field for a quantum dot device  100  of the die  302  may be generated by a magnet with one or more pulsed gates; the die  350  may apply the pulses to these gates. 
     In some embodiments, the die  350  may be configured to determine the values of the control signals applied to the elements of the die  302  (e.g. determine the voltages to be applied to the various gates  106 / 108 ) to achieve desired quantum operations (communicated to the die  350  through the package substrate  304  via the conductive pathways  319 ). In other embodiments, the die  350  may be preprogrammed with at least some of the control parameters (e.g. with the values for the voltages to be applied to the various gates  106 / 108 ) during the initialization of the die  350 . 
     In the quantum dot device package  300  ( FIG.  63   ), first-level interconnects  306  may be disposed between the first face  320  of the die  302  and the second face  326  of a package substrate  304 . Having first-level interconnects  306  disposed between the first face  320  of the die  302  and the second face  326  of the package substrate  304  (e.g., using solder bumps as part of flip chip packaging techniques) may enable the quantum dot device package  300  to achieve a smaller footprint and higher die-to-package-substrate connection density than could be achieved using conventional wirebond techniques (in which conductive contacts between the die  302  and the package substrate  304  are constrained to be located on the periphery of the die  302 ). For example, a die  302  having a square first face  320  with side length N may be able to form only 4N wirebond interconnects to the package substrate  304 , versus N 2  flip chip interconnects (utilizing the entire “full field” surface area of the first face  320 ). Additionally, in some applications, wirebond interconnects may generate unacceptable amounts of heat that may damage or otherwise interfere with the performance of the quantum dot device  100 . Using solder bumps as the first-level interconnects  306  may enable the quantum dot device package  300  to have much lower parasitic inductance relative to using wirebonds to couple the die  302  and the package substrate  304 , which may result in an improvement in signal integrity for high speed signals communicated between the die  302  and the package substrate  304 . Similarly, first-level interconnects  309  may be disposed between conductive contacts  371  of the die  350  and conductive contacts  379  at the second face  326  of the package substrate  304 , as shown, to couple electronic components (not shown) in the die  350  to conductive pathways in the package substrate  304 . 
     The package substrate  304  may include a first face  324  and an opposing second face  326 . Conductive contacts  399  may be disposed at the first face  324 , and conductive contacts  379  may be disposed at the second face  326 . Solder resist material  314  may be disposed around the conductive contacts  379 , and solder resist material  312  may be disposed around the conductive contacts  399 ; the solder resist materials  314  and  312  may take any of the forms discussed above with reference to the solder resist material  367 . In some embodiments, the solder resist material  312  and/or the solder resist material  314  may be omitted. Conductive pathways may extend through the insulating material  310  between the first face  324  and the second face  326  of the package substrate  304 , electrically coupling various ones of the conductive contacts  399  to various ones of the conductive contacts  379 , in any desired manner. The insulating material  310  may be a dielectric material (e.g., an ILD), and may take the form of any of the embodiments of the insulating material  130  disclosed herein, for example. The conductive pathways may include one or more conductive vias  395  and/or one or more conductive lines  397 , for example. 
     For example, the package substrate  304  may include one or more conductive pathways  313  to electrically couple the die  302  to conductive contacts  399  on the first face  324  of the package substrate  304 ; these conductive pathways  313  may be used to allow the die  302  to electrically communicate with a circuit component to which the quantum dot device package  300  is coupled (e.g., a circuit board or interposer, as discussed below). The package substrate  304  may include one or more conductive pathways  319  to electrically couple the die  350  to conductive contacts  399  on the first face  324  of the package substrate  304 ; these conductive pathways  319  may be used to allow the die  350  to electrically communicate with a circuit component to which the quantum dot device package  300  is coupled (e.g., a circuit board or interposer, as discussed below). 
     The package substrate  304  may include one or more conductive pathways  317  to electrically couple the die  302  to the die  350  through the package substrate  304 . In particular, the package substrate  304  may include conductive pathways  317  that couple different ones of the conductive contacts  379  on the second face  326  of the package substrate  304  so that, when the die  302  and the die  350  are coupled to these different conductive contacts  379 , the die  302  and the die  350  may communicate through the package substrate  304 . Although the die  302  and the die  350  are illustrated in  FIG.  63    as being disposed on the same second face  326  of the package substrate  304 , in some embodiments, the die  302  and the die  350  may be disposed on different faces of the package substrate  304  (e.g., one on the first face  324  and one on the second face  326 ), and may communicate via one or more conductive pathways  317 . 
     In some embodiments, the conductive pathways  317  may be microwave transmission lines. Microwave transmission lines may be structured for the effective transmission of microwave signals, and may take the form of any microwave transmission lines known in the art. For example, a conductive pathway  317  may be a coplanar waveguide, a stripline, a microstrip line, or an inverted microstrip line. The die  350  may provide microwave pulses along the conductive pathways  317  to the die  302  to provide electron spin resonance (ESR) pulses to the quantum dot device(s)  100  to manipulate the spin states of the quantum dots  142  that form therein. In some embodiments, the die  350  may generate a microwave pulse that is transmitted over a conductive pathway  317  and induces a magnetic field in the magnet line(s)  121  of a quantum dot device  100  and causes a transition between the spin-up and spin-down states of a quantum dot  142 . In some embodiments, the die  350  may generate a microwave pulse that is transmitted over a conductive pathway  317  and induces a magnetic field in a gate  106 / 108  to cause a transition between the spin-up and spin-down states of a quantum dot  142 . The die  350  may enable any such embodiments, or any combination of such embodiments. 
     The die  350  may provide any suitable control signals to the die  302  to enable operation of the quantum dot device(s)  100  included in the die  302 . For example, the die  350  may provide voltages (through the conductive pathways  317 ) to the gates  106 / 108 , and thereby tune the energy profile in the quantum well stack  146 . 
     In some embodiments, the quantum dot device package  300  may be a cored package, one in which the package substrate  304  is built on a carrier material (not shown) that remains in the package substrate  304 . In such embodiments, the carrier material may be a dielectric material that is part of the insulating material  310 ; laser vias or other through-holes may be made through the carrier material to allow conductive pathways  313  and/or  319  to extend between the first face  324  and the second face  326 . 
     In some embodiments, the package substrate  304  may be or may otherwise include a silicon interposer, and the conductive pathways  313  and/or  319  may be through-silicon vias. Silicon may have a desirably low coefficient of thermal expansion compared with other dielectric materials that may be used for the insulating material  310 , and thus may limit the degree to which the package substrate  304  expands and contracts during temperature changes relative to such other materials (e.g., polymers having higher coefficients of thermal expansion). A silicon interposer may also help the package substrate  304  achieve a desirably small line width and maintain high connection density to the die  302  and/or the die  350 . 
     Limiting differential expansion and contraction may help preserve the mechanical and electrical integrity of the quantum dot device package  300  as the quantum dot device package  300  is fabricated (and exposed to higher temperatures) and used in a cooled environment (and exposed to lower temperatures). In some embodiments, thermal expansion and contraction in the package substrate  304  may be managed by maintaining an approximately uniform density of the conductive material in the package substrate  304  (so that different portions of the package substrate  304  expand and contract uniformly), using reinforced dielectric materials as the insulating material  310  (e.g., dielectric materials with silicon dioxide fillers), or utilizing stiffer materials as the insulating material  310  (e.g., a prepreg material including glass cloth fibers). In some embodiments, the die  350  may be formed of semiconductor materials or compound semiconductor materials (e.g., group III-group V compounds) to enable higher efficiency amplification and signal generation to minimize the heat generated during operation and reduce the impact on the quantum operations of the die  302 . In some embodiments, the metallization in the die  350  may use superconducting materials (e.g., titanium nitride, niobium, niobium nitride, and niobium titanium nitride) to minimize heating. 
     The conductive contacts  365  of the die  302  may be electrically coupled to the conductive contacts  379  of the package substrate  304  via the first-level interconnects  306 , and the conductive contacts  371  of the die  350  may be electrically coupled to the conductive contacts  379  of the package substrate  304  via the first-level interconnects  309 . In some embodiments, the first-level interconnects  306 / 309  may include solder bumps or balls (as illustrated in  FIG.  63   ); for example, the first-level interconnects  306 / 309  may be flip chip (or controlled collapse chip connection, “C 4 ”) bumps disposed initially on the die  302 /die  350  or on the package substrate  304 . Second-level interconnects  308  (e.g., solder balls or other types of interconnects) may couple the conductive contacts  399  on the first face  324  of the package substrate  304  to another component, such as a circuit board (not shown). Examples of arrangements of electronics packages that may include an embodiment of the quantum dot device package  300  are discussed below with reference to  FIG.  65   . The die  302  and/or the die  350  may be brought in contact with the package substrate  304  using a pick-and-place apparatus, for example, and a reflow or thermal compression bonding operation may be used to couple the die  302  and/or the die  350  to the package substrate  304  via the first-level interconnects  306  and/or the first-level interconnects  309 , respectively. 
     The conductive contacts  365 ,  371 ,  379 , and/or  399  may include multiple layers of material that may be selected to serve different purposes. In some embodiments, the conductive contacts  365 ,  371 ,  379 , and/or  399  may be formed of aluminum, and may include a layer of gold (e.g., with a thickness of less than 1 micron) between the aluminum and the adjacent interconnect to limit the oxidation of the surface of the contacts and improve the adhesion with adjacent solder. In some embodiments, the conductive contacts  365 ,  371 ,  379 , and/or  399  may be formed of aluminum, and may include a layer of a barrier metal such as nickel, as well as a layer of gold, wherein the layer of barrier metal is disposed between the aluminum and the layer of gold, and the layer of gold is disposed between the barrier metal and the adjacent interconnect. In such embodiments, the gold may protect the barrier metal surface from oxidation before assembly, and the barrier metal may limit the diffusion of solder from the adjacent interconnects into the aluminum. 
     In some embodiments, the structures and materials in the quantum dot device  100  may be damaged if the quantum dot device  100  is exposed to the high temperatures that are common in conventional integrated circuit processing (e.g., greater than 100 degrees Celsius, or greater than 200 degrees Celsius). In particular, in embodiments in which the first-level interconnects  306 / 309  include solder, the solder may be a low temperature solder (e.g., a solder having a melting point below 100 degrees Celsius) so that it can be melted to couple the conductive contacts  365 / 371  and the conductive contacts  379  without having to expose the die  302  to higher temperatures and risk damaging the quantum dot device  100 . Examples of solders that may be suitable include indium-based solders (e.g., solders including indium alloys). When low temperature solders are used, however, these solders may not be fully solid during handling of the quantum dot device package  300  (e.g., at room temperature or temperatures between room temperature and 100 degrees Celsius), and thus the solder of the first-level interconnects  306 / 309  alone may not reliably mechanically couple the die  302 /die  350  and the package substrate  304  (and thus may not reliably electrically couple the die  302 /die  350  and the package substrate  304 ). In some such embodiments, the quantum dot device package  300  may further include a mechanical stabilizer to maintain mechanical coupling between the die  302 /die  350  and the package substrate  304 , even when solder of the first-level interconnects  306 / 309  is not solid. Examples of mechanical stabilizers may include an underfill material disposed between the die  302 /die  350  and the package substrate  304 , a corner glue disposed between the die  302 /die  350  and the package substrate  304 , an overmold material disposed around the die  302 /die  350  on the package substrate  304 , and/or a mechanical frame to secure the die  302 /die  350  and the package substrate  304 . 
     In some embodiments of the quantum dot device package  300 , the die  350  may not be included in the package  300 ; instead, the die  350  may be electrically coupled to the die  302  through another type of common physical support. For example, the die  350  may be separately packaged from the die  302  (e.g., the die  350  may be mounted to its own package substrate), and the two packages may be coupled together through an interposer, a printed circuit board, a bridge, a package-on-package arrangement, or in any other manner. Examples of device assemblies that may include the die  302  and the die  350  in various arrangements are discussed below with reference to  FIG.  65   . 
       FIGS.  64 A-B  are top views of a wafer  450  and dies  452  that may be formed from the wafer  450 ; the dies  452  may be included in any of the quantum dot device packages (e.g., the quantum dot device package  300 ) disclosed herein. The wafer  450  may include semiconductor material and may include one or more dies  452  having conventional and quantum dot device elements formed on a surface of the wafer  450 . Each of the dies  452  may be a repeating unit of a semiconductor product that includes any suitable conventional and/or quantum dot device. After the fabrication of the semiconductor product is complete, the wafer  450  may undergo a singulation process in which each of the dies  452  is separated from the others to provide discrete “chips” of the semiconductor product. A die  452  may include one or more quantum dot devices  100  and/or supporting circuitry to route electrical signals to the quantum dot devices  100  (e.g., interconnects including conductive vias and lines), as well as any other integrated circuit (IC) components. In some embodiments, the wafer  450  or the die  452  may include a memory device (e.g., a static random access memory (SRAM) device), a logic device (e.g., AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die  452 . For example, a memory array formed by multiple memory devices may be formed on a same die  452  as a processing device (e.g., the processing device  2002  of  FIG.  67   ) or other logic that is configured to store information in the memory devices or execute instructions stored in the memory array. 
       FIG.  65    is a cross-sectional view of a device assembly  400  that may include any of the embodiments of the quantum dot device packages  300  disclosed herein. The device assembly  400  includes a number of components disposed on a circuit board  402 . The device assembly  400  may include components disposed on a first face  440  of the circuit board  402  and an opposing second face  442  of the circuit board  402 ; generally, components may be disposed on one or both faces  440  and  442 . 
     In some embodiments, the circuit board  402  may be a printed circuit board (PCB) including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board  402 . In other embodiments, the circuit board  402  may be a package substrate or flexible board. In some embodiments, the die  302  and the die  350  ( FIG.  63   ) may be separately packaged and coupled together via the circuit board  402  (e.g., the conductive pathways  317  may run through the circuit board  402 ). 
     The device assembly  400  illustrated in  FIG.  65    includes a package-on-interposer structure  436  coupled to the first face  440  of the circuit board  402  by coupling components  416 . The coupling components  416  may electrically and mechanically couple the package-on-interposer structure  436  to the circuit board  402 , and may include solder balls (as shown in  FIG.  63   ), male and female portions of a socket, an adhesive, an underfill material, and/or any other suitable electrical and/or mechanical coupling structure. 
     The package-on-interposer structure  436  may include a package  420  coupled to an interposer  404  by coupling components  418 . The coupling components  418  may take any suitable form for the application, such as the forms discussed above with reference to the coupling components  416 . For example, the coupling components  418  may be the second-level interconnects  308 . Although a single package  420  is shown in  FIG.  65   , multiple packages may be coupled to the interposer  404 ; indeed, additional interposers may be coupled to the interposer  404 . The interposer  404  may provide an intervening substrate used to bridge the circuit board  402  and the package  420 . The package  420  may be a quantum dot device package  300  or may be a conventional IC package, for example. In some embodiments, the package  420  may take the form of any of the embodiments of the quantum dot device package  300  disclosed herein, and may include a quantum dot device die  302  coupled to a package substrate  304  (e.g., by flip chip connections). Generally, the interposer  404  may spread a connection to a wider pitch or reroute a connection to a different connection. For example, the interposer  404  may couple the package  420  (e.g., a die) to a ball grid array (BGA) of the coupling components  416  for coupling to the circuit board  402 . In the embodiment illustrated in  FIG.  65   , the package  420  and the circuit board  402  are attached to opposing sides of the interposer  404 ; in other embodiments, the package  420  and the circuit board  402  may be attached to a same side of the interposer  404 . In some embodiments, three or more components may be interconnected by way of the interposer  404 . In some embodiments, a quantum dot device package  300  including the die  302  and the die  350  ( FIG.  63   ) may be one of the packages disposed on an interposer like the interposer  404 . In some embodiments, the die  302  and the die  350  ( FIG.  63   ) may be separately packaged and coupled together via the interposer  404  (e.g., the conductive pathways  317  may run through the interposer  404 ). 
     The interposer  404  may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer  404  may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-group V compounds and group IV materials. The interposer  404  may include metal interconnects  408  and vias  410 , including but not limited to through-silicon vias (TSVs)  406 . The interposer  404  may further include embedded devices  414 , including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency (RF) devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer  404 . The package-on-interposer structure  436  may take the form of any of the package-on-interposer structures known in the art. 
     The device assembly  400  may include a package  424  coupled to the first face  440  of the circuit board  402  by coupling components  422 . The coupling components  422  may take the form of any of the embodiments discussed above with reference to the coupling components  416 , and the package  424  may take the form of any of the embodiments discussed above with reference to the package  420 . The package  424  may be a quantum dot device package  300  (e.g., including the die  302  and the die  350 , or just the die  302 ) or may be a conventional IC package, for example. In some embodiments, the package  424  may take the form of any of the embodiments of the quantum dot device package  300  disclosed herein, and may include a quantum dot device die  302  coupled to a package substrate  304  (e.g., by flip chip connections). 
     The device assembly  400  illustrated in  FIG.  65    includes a package-on-package structure  434  coupled to the second face  442  of the circuit board  402  by coupling components  428 . The package-on-package structure  434  may include a package  426  and a package  432  coupled together by coupling components  430  such that the package  426  is disposed between the circuit board  402  and the package  432 . The coupling components  428  and  430  may take the form of any of the embodiments of the coupling components  416  discussed above, and the packages  426  and  432  may take the form of any of the embodiments of the package  420  discussed above. Each of the packages  426  and  432  may be a quantum dot device package  300  or may be a conventional IC package, for example. In some embodiments, one or both of the packages  426  and  432  may take the form of any of the embodiments of the quantum dot device package  300  disclosed herein, and may include a die  302  coupled to a package substrate  304  (e.g., by flip chip connections). In some embodiments, a quantum dot device package  300  including the die  302  and the die  350  ( FIG.  63   ) may be one of the packages in a package-on-package structure like the package-on-package structure  434 . In some embodiments, the die  302  and the die  350  ( FIG.  63   ) may be separately packaged and coupled together using a package-on-package structure like the package-on-package structure  434  (e.g., the conductive pathways  317  may run through a package substrate of one or both of the packages of the dies  302  and  350 ). 
     A number of techniques are disclosed herein for operating a quantum dot device  100 .  FIG.  66    is a flow diagram of a particular illustrative method  1020  of operating a quantum dot device, in accordance with various embodiments. Although the operations discussed below with reference to the method  1020  are illustrated in a particular order and depicted once each, these operations may be repeated or performed in a different order (e.g., in parallel), as suitable. Additionally, various operations may be omitted, as suitable. Various operations of the method  1020  may be illustrated with reference to one or more of the embodiments discussed above, but the method  1020  may be used to operate any suitable quantum dot device (including any suitable ones of the embodiments disclosed herein). 
     At  1022 , electrical signals may be provided to one or more first gates disposed above a quantum well stack as part of causing a first quantum well to form in a quantum well layer in the quantum well stack. The quantum well stack may take the form of any of the embodiments disclosed herein (e.g., the quantum well stacks  146  discussed above with reference to  FIGS.  40 - 42   ), and may be included in any of the quantum dot devices  100  disclosed herein. For example, a voltage may be applied to a gate  108 - 11  as part of causing a first quantum well (for a first quantum dot  142 ) to form in the quantum well stack  146  below the gate  108 - 11 . 
     At  1024 , electrical signals may be provided to one or more second gates disposed above the quantum well stack as part of causing a second quantum well to form in the quantum well layer. For example, a voltage may be applied to the gate  108 - 12  as part of causing a second quantum well (for a second quantum dot  142 ) to form in the quantum well stack  146  below the gate  108 - 12 . 
     At  1026 , electrical signals may be provided to one or more third gates disposed above the quantum well stack as part of (1) causing a third quantum well to form in the quantum well layer or (2) providing a potential barrier between the first quantum well and the second quantum well. For example, a voltage may be applied to the gate  106 - 12  as part of (1) causing a third quantum well (for a third quantum dot  142 ) to form in the quantum well stack  146  below the gate  106 - 12  (e.g., when the gate  106 - 12  acts as a “plunger” gate) or (2) providing a potential barrier between the first quantum well (under the gate  108 - 11 ) and the second quantum well (under the gate  108 - 12 ) (e.g., when the gate  106 - 12  acts as a “barrier” gate). 
       FIG.  67    is a block diagram of an example quantum computing device  2000  that may include any of the quantum dot devices disclosed herein. A number of components are illustrated in  FIG.  67    as included in the quantum computing device  2000 , but any one or more of these components may be omitted or duplicated, as suitable for the application. In some embodiments, some or all of the components included in the quantum computing device  2000  may be attached to one or more PCBs (e.g., a motherboard). In some embodiments, various ones of these components may be fabricated onto a single SoC die. Additionally, in various embodiments, the quantum computing device  2000  may not include one or more of the components illustrated in  FIG.  67   , but the quantum computing device  2000  may include interface circuitry for coupling to the one or more components. For example, the quantum computing device  2000  may not include a display device  2006 , but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device  2006  may be coupled. In another set of examples, the quantum computing device  2000  may not include an audio input device  2024  or an audio output device  2008 , but may include audio input or output device interface circuitry (e.g., connectors and supporting circuitry) to which an audio input device  2024  or audio output device  2008  may be coupled. 
     The quantum computing device  2000  may include a processing device  2002  (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processing device  2002  may include a quantum processing device  2026  (e.g., one or more quantum processing devices), and a non-quantum processing device  2028  (e.g., one or more non-quantum processing devices). The quantum processing device  2026  may include one or more of the quantum dot devices  100  disclosed herein, and may perform data processing by performing operations on the quantum dots that may be generated in the quantum dot devices  100 , and monitoring the result of those operations. For example, as discussed above, different quantum dots may be allowed to interact, the quantum states of different quantum dots may be set or transformed, and the quantum states of quantum dots may be read (e.g., by another quantum dot). The quantum processing device  2026  may be a universal quantum processor, or specialized quantum processor configured to run one or more particular quantum algorithms. In some embodiments, the quantum processing device  2026  may execute algorithms that are particularly suitable for quantum computers, such as cryptographic algorithms that utilize prime factorization, encryption/decryption, algorithms to optimize chemical reactions, algorithms to model protein folding, etc. The quantum processing device  2026  may also include support circuitry to support the processing capability of the quantum processing device  2026 , such as input/output channels, multiplexers, signal mixers, quantum amplifiers, and analog-to-digital converters. For example, the quantum processing device  2026  may include circuitry (e.g., a current source) to provide current pulses to one or more magnet lines  121  included in the quantum dot device  100 . 
     As noted above, the processing device  2002  may include a non-quantum processing device  2028 . In some embodiments, the non-quantum processing device  2028  may provide peripheral logic to support the operation of the quantum processing device  2026 . For example, the non-quantum processing device  2028  may control the performance of a read operation, control the performance of a write operation, control the clearing of quantum bits, etc. The non-quantum processing device  2028  may also perform conventional computing functions to supplement the computing functions provided by the quantum processing device  2026 . For example, the non-quantum processing device  2028  may interface with one or more of the other components of the quantum computing device  2000  (e.g., the communication chip  2012  discussed below, the display device  2006  discussed below, etc.) in a conventional manner, and may serve as an interface between the quantum processing device  2026  and conventional components. The non-quantum processing device  2028  may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices. 
     The quantum computing device  2000  may include a memory  2004 , which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), nonvolatile memory (e.g., ROM), flash memory, solid state memory, and/or a hard drive. In some embodiments, the states of qubits in the quantum processing device  2026  may be read and stored in the memory  2004 . In some embodiments, the memory  2004  may include memory that shares a die with the non-quantum processing device  2028 . This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM). 
     The quantum computing device  2000  may include a cooling apparatus  2030 . The cooling apparatus  2030  may maintain the quantum processing device  2026  at a predetermined low temperature during operation to reduce the effects of scattering in the quantum processing device  2026 . This predetermined low temperature may vary depending on the setting; in some embodiments, the temperature may be 5 Kelvin or less. In some embodiments, the non-quantum processing device  2028  (and various other components of the quantum computing device  2000 ) may not be cooled by the cooling apparatus  2030 , and may instead operate at room temperature. The cooling apparatus  2030  may be, for example, a dilution refrigerator, a helium-3 refrigerator, or a liquid helium refrigerator. 
     In some embodiments, the quantum computing device  2000  may include a communication chip  2012  (e.g., one or more communication chips). For example, the communication chip  2012  may be configured for managing wireless communications for the transfer of data to and from the quantum computing device  2000 . The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. 
     The communication chip  2012  may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication chip  2012  may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip  2012  may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip  2012  may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication chip  2012  may operate in accordance with other wireless protocols in other embodiments. The quantum computing device  2000  may include an antenna  2022  to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions). 
     In some embodiments, the communication chip  2012  may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, the communication chip  2012  may include multiple communication chips. For instance, a first communication chip  2012  may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip  2012  may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip  2012  may be dedicated to wireless communications, and a second communication chip  2012  may be dedicated to wired communications. 
     The quantum computing device  2000  may include battery/power circuitry  2014 . The battery/power circuitry  2014  may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the quantum computing device  2000  to an energy source separate from the quantum computing device  2000  (e.g., AC line power). 
     The quantum computing device  2000  may include a display device  2006  (or corresponding interface circuitry, as discussed above). The display device  2006  may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example. 
     The quantum computing device  2000  may include an audio output device  2008  (or corresponding interface circuitry, as discussed above). The audio output device  2008  may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example. 
     The quantum computing device  2000  may include an audio input device  2024  (or corresponding interface circuitry, as discussed above). The audio input device  2024  may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). 
     The quantum computing device  2000  may include a GPS device  2018  (or corresponding interface circuitry, as discussed above). The GPS device  2018  may be in communication with a satellite-based system and may receive a location of the quantum computing device  2000 , as known in the art. 
     The quantum computing device  2000  may include an other output device  2010  (or corresponding interface circuitry, as discussed above). Examples of the other output device  2010  may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. 
     The quantum computing device  2000  may include an other input device  2020  (or corresponding interface circuitry, as discussed above). Examples of the other input device  2020  may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader. 
     The quantum computing device  2000 , or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. The following paragraphs provide various examples of the embodiments disclosed herein. 
     Example 1 is a quantum dot device, including: a base; a first fin extending from the base; a second fin extending from the base; a conductive material between the first fin and the second fin; and a dielectric material between the conductive material and the first fin. 
     Example 2 includes the subject matter of Example 1, and further specifies that the dielectric material has a thickness that is less than 20 nanometers. 
     Example 3 includes the subject matter of Example 2, and further specifies that the dielectric material has a thickness between 1 nanometer and 10 nanometers. 
     Example 4 includes the subject matter of any of Examples 1-3, and further specifies that the conductive material has a thickness between 1 nanometer and 15 nanometers. 
     Example 5 includes the subject matter of any of Examples 1-4, and further specifies that the conductive material is a first conductive material, the dielectric material is a first dielectric material, and the quantum dot device further includes: a second conductive material between the first conductive material and the second fin; and a second dielectric material between the second conductive material and the second fin. 
     Example 6 includes the subject matter of Example 5, and further includes: a third dielectric material between the first conductive material and the second conductive material. 
     Example 7 includes the subject matter of Example 6, and further specifies that the third dielectric material has a different material composition than the first dielectric material. 
     Example 8 includes the subject matter of any of Examples 5-7, and further specifies that the first conductive material and the second conductive material have a same material composition. 
     Example 9 includes the subject matter of Example 8, and further specifies that the first conductive material and the second conductive material are portions of a materially continuous conductive material structure. 
     Example 10 includes the subject matter of Example 9, and further specifies that the conductive material structure has a U-shaped cross-section. 
     Example 11 includes the subject matter of any of Examples 5-10, and further specifies that the first dielectric material and the second dielectric material have a same material composition. 
     Example 12 includes the subject matter of Example 11, and further specifies that the first dielectric material and the second dielectric material are portions of a materially continuous dielectric material structure. 
     Example 13 includes the subject matter of Example 12, and further specifies that the dielectric material structure has a U-shaped cross-section. 
     Example 14 includes the subject matter of any of Examples 5-13, and further specifies that top surfaces of the first and second conductive materials are spaced apart from a plane of top surfaces of the first and second fins. 
     Example 15 includes the subject matter of any of Examples 5-14, and further specifies that top surfaces of the first and second conductive materials are aligned with top surfaces of the first and second fins. 
     Example 16 includes the subject matter of any of Examples 1-15, and further specifies that the dielectric material is a high-k dielectric material or a low-k dielectric material. 
     Example 17 includes the subject matter of any of Examples 1-16, and further includes: a first gate above the first fin; and a second gate, different from the first gate, above the second fin. 
     Example 18 includes the subject matter of any of Examples 1-16, and further includes: a first gate above the first fin and above the second fin. 
     Example 19 includes the subject matter of any of Examples 1-18, and further specifies that a top surface of the conductive material is spaced apart from a plane of a top surface of the first fin by a distance between 5 nanometers and 50 nanometers. 
     Example 20 includes the subject matter of any of Examples 1-19, and further specifies that the dielectric material is a first dielectric material, and the quantum dot device further comprises: a second dielectric material between a top surface of the conductive material and a plane of the top surface of the first fin, wherein the second dielectric material has a different material composition than the first dielectric material. 
     Example 21 includes the subject matter of Example 20, and further specifies that the second dielectric material has a loss tangent that is less than a loss tangent of the first dielectric material. 
     Example 22 includes the subject matter of any of Examples 1-21, and further specifies that the first fin has a tapered shape that is widest proximate to the base. 
     Example 23 includes the subject matter of any of Examples 1-21, and further specifies that the first fin includes isotopically purified silicon. 
     Example 24 is a quantum dot device, including: a base; a fin extending from the base; a dielectric material on a side face of the fin, wherein the dielectric material has a thickness from the side face of the fin that is less than 20 nanometers; and a conductive material on the dielectric material, wherein the conductive material is spaced apart from the side face of the fin by the thickness of the dielectric material. 
     Example 25 includes the subject matter of Example 24, and further specifies that the dielectric material has a thickness between 1 nanometer and 10 nanometers. 
     Example 26 includes the subject matter of any of Examples 24-25, and further specifies that the conductive material has a thickness between 1 nanometer and 15 nanometers. 
     Example 27 includes the subject matter of Example 26, and further specifies that the conductive material has a thickness between 2 nanometers and 10 nanometers. 
     Example 28 includes the subject matter of any of Examples 24-27, and further specifies that the conductive material is a portion of a conductive material structure having a U-shaped cross-section. 
     Example 29 includes the subject matter of any of Examples 24-28, and further specifies that the dielectric material is a portion of a dielectric material structure having a U-shaped cross-section. 
     Example 30 includes the subject matter of any of Examples 24-29, and further specifies that a top surface of the conductive material is spaced apart from a plane of a top surface of the fin. 
     Example 31 includes the subject matter of Example 30, and further specifies that the top surface of the conductive material is spaced apart from the plane of the top surface of the fin by a distance between 5 nanometers and 50 nanometers. 
     Example 32 includes the subject matter of Example 30, and further specifies that the top surface of the conductive material is spaced apart from the plane of the top surface of the fin by a distance between 10 nanometers and 30 nanometers. 
     Example 33 includes the subject matter of any of Examples 24-32, and further specifies that the dielectric material is a first dielectric material, and the quantum dot device further comprises: a second dielectric material between a top surface of the conductive material and a plane of the top surface of the fin, wherein the second dielectric material has a different material composition than the first dielectric material. 
     Example 34 includes the subject matter of Example 33, and further specifies that the second dielectric material has a loss tangent that is less than a loss tangent of the first dielectric material. 
     Example 35 includes the subject matter of any of Examples 24-34, and further specifies that the fin has a tapered shape that is widest proximate to the base. 
     Example 36 includes the subject matter of any of Examples 24-35, and further specifies that the fin includes isotopically purified silicon. 
     Example 37 includes the subject matter of any of Examples 24-36, and further specifies that the dielectric material is a first dielectric material, the conductive material is a first conductive material, and the quantum dot device further includes: a second dielectric material; and a second conductive material; wherein the fin is between the second dielectric material and the first dielectric material, and the second dielectric material is between the second conductive material and the fin. 
     Example 38 includes the subject matter of Example 37, and further specifies that a top surface of the first conductive material is spaced apart from a plane of a top surface of the fin, and a top surface of the second conductive material is aligned with the plane of the top surface of the fin. 
     Example 39 includes the subject matter of Example 37, and further specifies that top surfaces of the first and second conductive materials are aligned with a top surface of the fin. 
     Example 40 includes the subject matter of any of Examples 24-39, and further includes: a plurality of gates at a top surface of the fin. 
     Example 41 is a quantum dot device, including: a base; a fin extending from the base; a first conductive material above the base; and a second conductive material above the base; wherein the fin is between the first conductive material and the second conductive material. 
     Example 42 includes the subject matter of Example 41, and further specifies that the first conductive material has a thickness between 1 nanometer and 15 nanometers. 
     Example 43 includes the subject matter of any of Examples 41-42, and further specifies that the first conductive material has a thickness between 1 nanometer and 15 nanometers. 
     Example 44 includes the subject matter of any of Examples 41-43, and further specifies that a top surface of the first conductive material is spaced apart from a plane of a top surface of the fin, and a top surface of the second conductive material is aligned with the plane of the top surface of the fin. 
     Example 45 includes the subject matter of any of Examples 41-43, and further specifies that top surfaces of the first and second conductive materials are aligned with a top surface of the fin. 
     Example 46 includes the subject matter of any of Examples 41-45, and further includes: a first dielectric material between the first conductive material and the fin; and a second dielectric material between the second conductive material and the fin. 
     Example 47 includes the subject matter of Example 46, and further specifies that the first dielectric material has a thickness that is less than 20 nanometers. 
     Example 48 includes the subject matter of Example 47, and further specifies that the first dielectric material has a thickness between 1 nanometer and 10 nanometers. 
     Example 49 includes the subject matter of any of Examples 46-48, and further specifies that the second dielectric material has a thickness that is less than 20 nanometers. 
     Example 50 includes the subject matter of Example 49, and further specifies that the second dielectric material has a thickness between 1 nanometer and 10 nanometers. 
     Example 51 includes the subject matter of any of Examples 46-50, and further specifies that the first dielectric material is a portion of a dielectric material structure having a U-shaped cross-section. 
     Example 52 includes the subject matter of Example 51, and further specifies that the second dielectric material is a portion of a dielectric material structure having a U-shaped cross-section. 
     Example 53 includes the subject matter of any of Examples 41-52, and further specifies that the first conductive material is a portion of a conductive material structure having a U-shaped cross-section. 
     Example 54 includes the subject matter of Example 53, and further specifies that the second conductive material is a portion of a conductive material structure having a U-shaped cross-section. 
     Example 55 includes the subject matter of any of Examples 41-54, and further includes: a dielectric material between a top surface of the first conductive material and a plane of the top surface of the fin. 
     Example 56 includes the subject matter of any of Examples 41-55, and further specifies that the fin has a tapered shape that is widest proximate to the base. 
     Example 57 includes the subject matter of any of Examples 41-56, and further specifies that the fin includes isotopically purified silicon or isotopically purified germanium. 
     Example 58 is a method of operating a quantum dot device, including: providing electrical signals to a first gate above a fin of a quantum dot device as part of causing a first quantum well to form in the fin, wherein the quantum dot device takes the form of any of the quantum dot devices of claims  1 - 57 ; providing electrical signals to a second gate above the fin as part of causing a second quantum well to form in the fin; and providing electrical signals to a third gate above the fin to (1) cause a third quantum well to form in the fin or (2) provide a potential barrier between the first quantum well and the second quantum well. 
     Example 59 includes the subject matter of Example 58, and further specifies that the fin is a first fin, and the method further includes: providing electrical signals to a fourth gate above a second fin of the quantum dot device as part of causing a fourth quantum well to form in the second fin; providing electrical signals to a fifth gate above the second fin as part of causing a fifth quantum well to form in the second fin; and providing electrical signals to a sixth gate above the second fin to (1) cause a sixth quantum well to form in the second fin or (2) provide a potential barrier between the fourth quantum well and the fifth quantum well. 
     Example 60 includes the subject matter of Example 59, and further includes: detecting a state of a quantum dot in the first fin by a quantum dot in the second fin. 
     Example 61 includes the subject matter of any of Examples 59-60, and further specifies that the quantum dot device includes a conductive liner spaced apart from the fins, and the method further includes: providing electrical signals to the conductive liner. 
     Example 62 is a quantum computing device, including: a quantum processing device, wherein the quantum processing device includes the quantum dot device of any of claims  1 - 57 ; and a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to a plurality of gates of the quantum processing device, wherein the plurality of gates are disposed above a fin in the quantum processing device to control quantum dot formation in the fin. 
     Example 63 includes the subject matter of Example 62, and further includes: a memory device to store data generated by quantum dots formed in the quantum well layer during operation of the quantum processing device.