Patent Publication Number: US-11652171-B2

Title: Contact for semiconductor device and method of forming thereof

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application claims the benefit of U.S. Provisional Application No. 63/151,920, filed on Feb. 22, 2021, which application is hereby incorporated herein by reference. 
    
    
     BACKGROUND 
     Semiconductor devices are used in a variety of electronic applications, such as, for example, personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. 
     The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continual reductions in minimum feature size, which allow more components to be integrated into a given area. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIG.  1    illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. 
         FIGS.  2 ,  3 ,  4 ,  5 ,  6 ,  7 A,  7 B,  8 A,  8 B,  9 A,  9 B,  10 A,  10 B,  10 C,  10 D,  11 A,  11 B,  12 A,  12 B,  13 A,  13 B ,  14 A,  14 B,  14 C,  15 A,  15 B,  16 A,  16 B,  16 C,  16 D,  17 A,  17 B,  17 C,  17 D,  18 A,  18 B,  19 A,  19 B,  20 A, and  20 B are cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments. 
         FIGS.  20 C,  20 D,  20 E, and  20 F  are top views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated  90  degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. 
     An interconnect structure of a semiconductor device and a method of forming the same are provided, in accordance with some embodiments. In some embodiments, a gate contact is formed on a gate structure. A contact plug is subsequently formed on the gate contact. The contact plug has a smaller width than the gate contact, and a bottom portion of the contact plug comprising a rivet shape extends below a top surface of the gate contact. The rivet shape of the bottom portion of the contact plug may be useful for reducing undesirable etching of the gate contact by slurry from a CMP performed on the contact plug. The gate contact having a larger width than the contact plug may be useful for allowing the rivet shape of the bottom portion of the contact plug to be wider and shallower, which can reduce undesirable contact resistance and improve yield gain for high bandwidth memory. 
       FIG.  1    illustrates an example of a FinFET in a three-dimensional view, in accordance with some embodiments. The FinFET comprises a fin  52  on a substrate  50  (e.g., a semiconductor substrate). Isolation regions  56  are disposed in the substrate  50 , and the fin  52  protrudes above and from between neighboring isolation regions  56 . Although the isolation regions  56  are described/illustrated as being separate from the substrate  50 , as used herein the term “substrate” may be used to refer to just the semiconductor substrate or a semiconductor substrate inclusive of isolation regions. Additionally, although the fin  52  is illustrated as a single, continuous material as the substrate  50 , the fin  52  and/or the substrate  50  may comprise a single material or a plurality of materials. In this context, the fin  52  refers to the portion extending between the neighboring isolation regions  56 . 
     A gate dielectric layer  92  is along sidewalls and over a top surface of the fin  52 , and a gate electrode  94  is over the gate dielectric layer  92 . Source/drain regions  82  are disposed in opposite sides of the fin  52  with respect to the gate dielectric layer  92  and gate electrode  94 .  FIG.  1    further illustrates reference cross-sections that are used in later figures. Cross-section A-A is along a longitudinal axis of the gate electrode  94  and in a direction, for example, perpendicular to the direction of current flow between the source/drain regions  82  of the FinFET. Cross-section B-B is perpendicular to cross-section A-A and is along a longitudinal axis of the fin  52  and in a direction of, for example, a current flow between the source/drain regions  82  of the FinFET. Cross-section C-C is parallel to cross-section A-A and extends through a source/drain region of the FinFET. Subsequent figures refer to these reference cross-sections for clarity. 
     Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments contemplate aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs), or the like. 
       FIGS.  2  through  20 B  are cross-sectional views of intermediate stages in the manufacturing of FinFETs, in accordance with some embodiments.  FIGS.  2  through  7 B  illustrate reference cross-section A-A illustrated in  FIG.  1   , except for multiple fins/FinFETs.  FIGS.  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A,  15 A,  16 A, and  17 A  are illustrated along reference cross-section A-A illustrated in  FIG.  1   , and  FIGS.  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B,  14 C,  15 B,  16 B,  16 C,  16 D,  17 B,  17 C,  17 D,  18 A,  18 B,  19 A,  19 B,  20 A, and  20 B  are illustrated along a similar cross-section B-B illustrated in  FIG.  1   , except for multiple fins/FinFETs.  FIGS.  10 C and  10 D  are illustrated along reference cross-section C-C illustrated in  FIG.  1   , except for multiple fins/FinFETs. 
     In  FIG.  2   , a substrate  50  is provided. The substrate  50  may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate  50  may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multi-layered or gradient substrate may also be used. In some embodiments, the semiconductor material of the substrate  50  may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenide phosphide; or combinations thereof. 
     The substrate  50  has an n-type region  50 N and a p-type region  50 P. The n-type region  50 N can be for forming n-type devices, such as NMOS transistors, e.g., n-type FinFETs. The p-type region  50 P can be for forming p-type devices, such as PMOS transistors, e.g., p-type FinFETs. The n-type region  50 N may be physically separated from the p-type region  50 P (as illustrated by divider  20 ), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region  50 N and the p-type region  50 P. 
     In  FIG.  3   , fins  52  are formed in the substrate  50 . The fins  52  are semiconductor strips. In some embodiments, the fins  52  may be formed in the substrate  50  by etching trenches in the substrate  50 . The etching may be any acceptable etch process, such as a reactive ion etch (RIE), neutral beam etch (NBE), the like, or a combination thereof. The etch may be anisotropic. 
     The fins may be patterned by any suitable method. For example, the fins  52  may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, pitches smaller than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins  52 . 
     In  FIG.  4   , an insulation material  54  is formed over the substrate  50  and between neighboring fins  52 . The insulation material  54  may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by a high density plasma chemical vapor deposition (HDP-CVD), a flowable CVD (FCVD) (e.g., a CVD-based material deposition in a remote plasma system and post curing to make it convert to another material, such as an oxide), the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the insulation material  54  is silicon oxide formed by a FCVD process. An anneal process may be performed once the insulation material is formed. In an embodiment, the insulation material  54  is formed such that excess insulation material  54  covers the fins  52 . Although the insulation material  54  is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments a liner (not shown) may first be formed along a surface of the substrate  50  and the fins  52 . Thereafter, a fill material, such as those discussed above may be formed over the liner. 
     In  FIG.  5   , a removal process is applied to the insulation material  54  to remove excess insulation material  54  over the fins  52 . In some embodiments, a planarization process such as a chemical mechanical polish (CMP), an etch-back process, combinations thereof, or the like may be utilized. The planarization process exposes the fins  52  such that top surfaces of the fins  52  and the insulation material  54  are level after the planarization process is complete. In embodiments in which a mask remains on the fins  52 , the planarization process may expose the mask or remove the mask such that top surfaces of the mask or the fins  52 , respectively, and the insulation material  54  are level after the planarization process is complete. 
     In  FIG.  6   , the insulation material  54  is recessed to form Shallow Trench Isolation (STI) regions  56 . The insulation material  54  is recessed such that upper portions of fins  52  in the n-type region  50 N and in the p-type region  50 P protrude from between neighboring STI regions  56 . Further, the top surfaces of the STI regions  56  may have a flat surface as illustrated, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions  56  may be formed flat, convex, and/or concave by an appropriate etch. The STI regions  56  may be recessed using an acceptable etching process, such as one that is selective to the material of the insulation material  54  (e.g., etches the material of the insulation material  54  at a faster rate than the material of the fins  52 ). For example, an oxide removal using, for example, dilute hydrofluoric (dHF) acid may be used. 
     The process described with respect to  FIGS.  2  through  6    is just one example of how the fins  52  may be formed. In some embodiments, the fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer to expose the underlying substrate  50 . Homoepitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins  52 . For example, the fins  52  in  FIG.  5    can be recessed, and a material different from the fins  52  may be epitaxially grown over the recessed fins  52 . In such embodiments, the fins  52  comprise the recessed material as well as the epitaxially grown material disposed over the recessed material. In an even further embodiment, a dielectric layer can be formed over a top surface of the substrate  50 , and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from the substrate  50 , and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer to form the fins  52 . In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be in situ doped during growth, which may obviate prior and subsequent implantations although in situ and implantation doping may be used together. 
     Still further, it may be advantageous to epitaxially grow a material in n-type region  50 N (e.g., an NMOS region) different from the material in p-type region  50 P (e.g., a PMOS region). In various embodiments, upper portions of the fins  52  may be formed from silicon-germanium (Si x Ge 1−x , where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like. 
     Further in  FIG.  6   , appropriate wells (not shown) may be formed in the fins  52  and/or the substrate  50 . In some embodiments, a P well may be formed in the n-type region  50 N, and an N well may be formed in the p-type region  50 P. In some embodiments, a P well or an N well are formed in both the n-type region  50 N and the p-type region  50 P. 
     In the embodiments with different well types, the different implant steps for the n-type region  50 N and the p-type region  50 P may be achieved using a photoresist and/or other masks (not shown). For example, a photoresist may be formed over the fins  52  and the STI regions  56  in the n-type region  50 N. The photoresist is patterned to expose the p-type region  50 P of the substrate  50 . The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implant is performed in the p-type region  50 P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into the n-type region  50 N. The n-type impurities may be phosphorus, arsenic, antimony, or the like implanted in the region to a concentration of equal to or less than 10 18  cm −3 , such as between about 10 16  cm −3  and about 10 18  cm −3 . After the implant, the photoresist is removed, such as by an acceptable ashing process. 
     Following the implanting of the p-type region  50 P, a photoresist is formed over the fins  52  and the STI regions  56  in the p-type region  50 P. The photoresist is patterned to expose the n-type region  50 N of the substrate  50 . The photoresist can be formed by using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implant may be performed in the n-type region  50 N, and the photoresist may act as a mask to substantially prevent p-type impurities from being implanted into the p-type region  50 P. The p-type impurities may be boron, boron fluoride, indium, or the like implanted in the region to a concentration of equal to or less than 10 18  cm −3 , such as between about 10 16  cm −3  and about 10 18  cm −3 . After the implant, the photoresist may be removed, such as by an acceptable ashing process. 
     After the implants of the n-type region  50 N and the p-type region  50 P, an anneal may be performed to repair implant damage and to activate the p-type and/or n-type impurities that were implanted. In some embodiments, the grown materials of epitaxial fins may be in situ doped during growth, which may obviate the implantations, although in situ and implantation doping may be used together. 
     In  FIGS.  7 A and  7 B , layers for forming dummy gates are formed on the fins  52 .  FIG.  7 A  illustrates a first gate area  100 A in which relatively smaller gate structures may subsequently be formed (see below,  FIG.  14 B ) and  FIG.  7 B  illustrates a second gate area  100 B in which relatively larger gate structures may subsequently be formed (see below,  FIG.  14 B ). Differences in the sizes of the subsequently formed gate structures may be due to, e.g., loading effects or dishing effects of CMPs in areas with different pattern densities. The first gate area  100 A and the second gate area  100 B may be physically separated. The first gate area  100 A and the second gate area  100 B may each contain respective n-type regions  50 N and p-type regions  50 P. 
     Referring to  FIGS.  7 A and  7 B , a dummy dielectric layer  60  is formed on the fins  52 . The dummy dielectric layer  60  may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. It is noted that the dummy dielectric layer  60  is shown covering only the fins  52  for illustrative purposes only. In some embodiments, the dummy dielectric layer  60  may be deposited such that the dummy dielectric layer  60  covers the STI regions  56 , extending over the STI regions and between subsequently formed dummy gate layers (see below) and the STI regions  56 . 
     Still referring to  FIGS.  7 A and  7 B , a dummy gate layer  62 A is formed over the dummy dielectric layer  60  in the first gate area  100 A and a dummy gate layer  62 B is formed over the dummy dielectric layer  60  in the second gate area  100 B. The dummy gate layers  62 A and  62 B may be deposited over the dummy dielectric layer  60  and then planarized, such as by respective CMP processes. In some embodiments, the dummy gate layer  62 A is formed and planarized to a height H 1  in a range of 110 nm to 130 nm and the dummy gate layer  62 B is formed and planarized to a height H 2  in a range of 110 nm to 130 nm. In other embodiments, the dummy gate layer  62 A and  62 B are formed to about the same height. The dummy gate layers  62 A and  62 B may be a conductive or non-conductive material and may be selected from a group including amorphous silicon, polycrystalline-silicon (polysilicon), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layers  62 A and  62 B may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layers  62 A and  62 B may be made of other materials that have a high etching selectivity from the etching of isolation regions, e.g., the STI regions  56  and/or the dummy dielectric layer  60 . 
     Further referring to  FIGS.  7 A and  7 B , a mask layer  64  is formed over the dummy gate layers  62 A and  62 B. The mask layer  64  may include one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single mask layer  64  are formed across the n-type region  50 N and the p-type region  50 P. In some embodiments, the mask layer  64  may be formed to different thicknesses in the first gate area  100 A and the second gate area  100 B. 
       FIGS.  8 A through  20 F  illustrate various additional steps in the manufacturing of embodiment devices.  FIGS.  8 A through  20 F  illustrate features in either of the n-type region  50 N and the p-type region  50 P. For example, the structures illustrated in  FIGS.  8 A through  20 F  may be applicable to both the n-type region  50 N and the p-type region  50 P. Differences (if any) in the structures of the n-type region  50 N and the p-type region  50 P are described in the text accompanying each figure.  FIGS.  8 A,  9 A,  10 A,  10 C,  10 D,  11 A,  12 A,  13 A,  14 A,  15 A,  16 A, and  17 A  illustrate features in the first gate area  100 A and the second gate area  100 B, as the structures illustrated in  FIGS.  8 A,  9 A,  10 A,  11 A,  12 A,  13 A,  14 A,  15 A,  16 A, and  17 A  may be applicable to both the first gate area  100 A and the second gate area  100 B. Differences (if any) in the structures of the first gate area  100 A and the second gate area  100 B are described in the text accompanying each figure.  FIGS.  8 B,  9 B,  10 B,  11 B,  12 B,  13 B,  14 B,  15 B,  16 B, and  17 B  illustrate the first gate area  100 A and the second gate area  100 B separated by a divider  22 . 
     In  FIGS.  8 A and  8 B , the mask layer  64  (see  FIG.  7   ) may be patterned using acceptable photolithography and etching techniques to form masks  74 . The pattern of the masks  74  then may be transferred to the dummy gate layer  62 . In some embodiments (not illustrated), the pattern of the masks  74  may also be transferred to the dummy dielectric layer  60  by an acceptable etching technique to form dummy gates  72 A and  72 B in the first gate area  100 A and the second gate area  100 B, respectively. The dummy gates  72 A and  72 B may be collectively be referred to as dummy gates  72 , as illustrated in  FIG.  8 A  and subsequent figures following from  FIG.  8 A . The dummy gates  72 A and  72 B cover respective channel regions  58  of the fins  52 . The pattern of the masks  74  may be used to physically separate each of the dummy gates  72 A and  72 B from adjacent dummy gates. The dummy gates  72 A and  72 B may also have a lengthwise direction substantially perpendicular to the lengthwise direction of respective epitaxial fins  52 . In some embodiments, the dummy gates  72 A are patterned to have widths W 1  in a range of 8 nm to 36 nm and the dummy gates  72 B are patterned to have widths W 2  in a range of 72 nm to 240 nm. 
     Further in  FIGS.  8 A and  8 B , gate seal spacers  80  can be formed on exposed surfaces of the dummy gates  72 A and  72 B, the masks  74 , and/or the fins  52 . A thermal oxidation or a deposition followed by an anisotropic etch may form the gate seal spacers  80 . The gate seal spacers  80  may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. 
     After the formation of the gate seal spacers  80 , implants for lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In the embodiments with different device types, similar to the implants discussed above in  FIG.  6   , a mask, such as a photoresist, may be formed over the n-type region  50 N, while exposing the p-type region  50 P, and appropriate type (e.g., p-type) impurities may be implanted into the exposed fins  52  in the p-type region  50 P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region  50 P while exposing the n-type region  50 N, and appropriate type impurities (e.g., n-type) may be implanted into the exposed fins  52  in the n-type region  50 N. The mask may then be removed. The n-type impurities may be the any of the n-type impurities previously discussed, and the p-type impurities may be the any of the p-type impurities previously discussed. The lightly doped source/drain regions may have a concentration of impurities of from about 10 15  cm −3  to about 10 19  cm −3 . An anneal may be used to repair implant damage and to activate the implanted impurities. 
     In  FIGS.  9 A and  9 B , gate spacers  86  are formed on the gate seal spacers  80  along sidewalls of the dummy gates  72 A and  72 B and the masks  74 . The gate spacers  86  may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers  86  may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. 
     It is noted that the above disclosure generally describes a process of forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be utilized, different sequence of steps may be utilized (e.g., the gate seal spacers  80  may not be etched prior to forming the gate spacers  86 , yielding “L-shaped” gate seal spacers), spacers may be formed and removed, and/or the like. Furthermore, the n-type and p-type devices may be formed using a different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate seal spacers  80  while the LDD regions for p-type devices may be formed after forming the gate seal spacers  80 . 
     In  FIGS.  10 A and  10 B  epitaxial source/drain regions  82  are formed in the fins  52 . The epitaxial source/drain regions  82  are formed in the fins  52  such that each dummy gate  72 A and  72 B is disposed between respective neighboring pairs of the epitaxial source/drain regions  82 . In some embodiments the epitaxial source/drain regions  82  may extend into, and may also penetrate through, the fins  52 . In some embodiments, the gate spacers  86  are used to separate the epitaxial source/drain regions  82  from the dummy gates  72 A and  72 B by an appropriate lateral distance so that the epitaxial source/drain regions  82  do not short out subsequently formed gates of the resulting FinFETs. A material of the epitaxial source/drain regions  82  may be selected to exert stress in the respective channel regions  58 , thereby improving performance. 
     The epitaxial source/drain regions  82  in the n-type region  50 N may be formed by masking the p-type region  50 P and etching source/drain regions of the fins  52  in the n-type region  50 N to form recesses in the fins  52 . Then, the epitaxial source/drain regions  82  in the n-type region  50 N are epitaxially grown in the recesses. The epitaxial source/drain regions  82  may include any acceptable material, such as appropriate for n-type FinFETs. For example, if the fin  52  is silicon, the epitaxial source/drain regions  82  in the n-type region  50 N may include materials exerting a tensile strain in the channel region  58 , such as silicon, silicon carbide, phosphorous doped silicon carbide, silicon phosphide, or the like. The epitaxial source/drain regions  82  in the n-type region  50 N may have surfaces raised from respective surfaces of the fins  52  and may have facets. 
     The epitaxial source/drain regions  82  in the p-type region  50 P may be formed by masking the n-type region  50 N and etching source/drain regions of the fins  52  in the p-type region  50 P to form recesses in the fins  52 . Then, the epitaxial source/drain regions  82  in the p-type region  50 P are epitaxially grown in the recesses. The epitaxial source/drain regions  82  may include any acceptable material, such as appropriate for p-type FinFETs. For example, if the fin  52  is silicon, the epitaxial source/drain regions  82  in the p-type region  50 P may comprise materials exerting a compressive strain in the channel region  58 , such as silicon-germanium, boron doped silicon-germanium, germanium, germanium tin, or the like. The epitaxial source/drain regions  82  in the p-type region  50 P may have surfaces raised from respective surfaces of the fins  52  and may have facets. 
     The epitaxial source/drain regions  82  and/or the fins  52  may be implanted with dopants to form source/drain regions, similar to the process previously discussed for forming lightly-doped source/drain regions, followed by an anneal. The source/drain regions may have an impurity concentration of between about 10 19  cm −3  and about 10 21  cm −3 . The n-type and/or p-type impurities for source/drain regions may be any of the impurities previously discussed. In some embodiments, the epitaxial source/drain regions  82  may be in situ doped during growth. 
     As a result of the epitaxy processes used to form the epitaxial source/drain regions  82  in the n-type region  50 N and the p-type region  50 P, upper surfaces of the epitaxial source/drain regions have facets which expand laterally outward beyond sidewalls of the fins  52 . In some embodiments, these facets cause adjacent source/drain regions  82  of a same FinFET to merge as illustrated by  FIG.  10 C . In other embodiments, adjacent source/drain regions  82  remain separated after the epitaxy process is completed as illustrated by  FIG.  10 D . In the embodiments illustrated in  FIGS.  10 C and  10 D , gate spacers  86  are formed covering a portion of the sidewalls of the fins  52  that extend above the STI regions  56  thereby blocking the epitaxial growth. In some other embodiments, the spacer etch used to form the gate spacers  86  may be adjusted to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region  56 . 
     In  FIGS.  11 A and  11 B , a first interlayer dielectric (ILD)  88  is deposited over the structure illustrated in  FIGS.  10 A and  10 B . The first ILD  88  may be formed of a dielectric material, and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulation materials formed by any acceptable process may be used. In some embodiments, a first contact etch stop layer (CESL)  87  is disposed between the first ILD  88  and the epitaxial source/drain regions  82 , the masks  74 , and the gate spacers  86 . The first CESL  87  may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a lower etch rate than the material of the overlying first ILD  88 . 
     In  FIGS.  12 A and  12 B , a planarization process, such as a CMP, may be performed to level the top surface of the first ILD  88  with the top surfaces of the dummy gates  72  or the masks  74 . The planarization process may also remove the masks  74  on the dummy gates  72 , and portions of the gate seal spacers  80  and the gate spacers  86  along sidewalls of the masks  74 . After the planarization process, top surfaces of the dummy gates  72 , the gate seal spacers  80 , the gate spacers  86 , and the first ILD  88  are level. Accordingly, the top surfaces of the dummy gates  72  are exposed through the first ILD  88 . In some embodiments, the masks  74  may remain, in which case the planarization process levels the top surface of the first ILD  88  with the top surfaces of the masks  74 . 
     After the planarization, the dummy gate  72 A may have a height H 3  in a range of 15 nm to 19 nm and the dummy gate  72 B may have a height H 4  in a range of 18 nm to 28 nm. In some embodiments, the dummy gates  72 A and  72 B have a similar height before the planarization and the height H 4  of the dummy gates  72 B is greater than the height H 3  of the dummy gates  72 A after the planarization, which may be due to e.g. larger dishing effects on the dummy gates  72 A such as from greater pattern density. 
     In  FIGS.  13 A and  13 B , the dummy gates  72 A and  72 B, and the masks  74  if present, are removed in an etching step(s), so that recesses  90 A and  90 B are formed. Portions of the dummy dielectric layer  60  in the recesses  90 A and  90 B may also be removed. In some embodiments, only the dummy gates  72 A and  72 B are removed and the dummy dielectric layer  60  remains and is exposed by the recesses  90 A and  90 B. In some embodiments, the dummy dielectric layer  60  is removed from recesses  90 A and  90 B in a first region of a die (e.g., a core logic region) and remains in recesses  90 A and  90 B in a second region of the die (e.g., an input/output region). In some embodiments, the dummy gates  72 A and  72 B are removed by an anisotropic dry etch process. For example, the etching process may include a dry etch process using reaction gas(es) that selectively etch the dummy gates  72 A and  72 B with little or no etching of the first ILD  88  or the gate spacers  86 . Each recess  90 A and  90 B exposes and/or overlies a channel region  58  of a respective fin  52 . Each channel region  58  is disposed between neighboring pairs of the epitaxial source/drain regions  82 . During the removal, the dummy dielectric layer  60  may be used as an etch stop layer when the dummy gates  72 A and  72 B are etched. The dummy dielectric layer  60  may then be optionally removed after the removal of the dummy gates  72 A and  72 B. 
     In  FIGS.  14 A and  14 B , gate dielectric layers  92 A and  92 B, collectively referred to as gate dielectric layers  92 , and gate electrodes  94 A and  94 B, collectively referred to as gate electrodes  94 , are formed for replacement gates.  FIG.  14 C  illustrates a detailed view of region  89  of  FIG.  14 B . To form the gate dielectric layers  92  one or more layers are deposited in the recesses  90 A and  90 B, such as on the top surfaces and the sidewalls of the fins  52  and on sidewalls of the gate seal spacers  80 /gate spacers  86 . The gate dielectric layers  92  may also be formed on the top surface of the first ILD  88 . In some embodiments, the gate dielectric layers  92  comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers  92  include an interfacial layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers  92  may include a dielectric layer having a k value greater than about 7.0. The formation methods of the gate dielectric layers  92  may include Molecular-Beam Deposition (MBD), ALD, PECVD, and the like. In embodiments where portions of the dummy dielectric layer  60  remains in the recesses  90 A and  90 B, the gate dielectric layers  92  include a material of the dummy dielectric layer  60  (e.g., SiO 2 ). 
     The gate electrodes  94  are deposited over the gate dielectric layers  92 , respectively, and fill the remaining portions of the recesses  90 . The gate electrodes  94  may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multi-layers thereof. For example, although a single layer gate electrode  94 B is illustrated in  FIG.  14 B , the gate electrode  94 B may comprise any number of liner layers  91 , any number of work function tuning layers  93 , and a fill material  95  as illustrated by  FIG.  14 C . After the filling of the recesses  90 A and  90 B, a planarization process, such as a CMP, may be performed to remove the excess portions of the gate dielectric layers  92  and the material of the gate electrodes  94 , which excess portions are over the top surface of the first ILD  88 . The remaining portions of material of the gate electrodes  94  and the gate dielectric layers  92  thus form replacement gates of the resulting FinFETs. The gate electrodes  94  and the gate dielectric layers  92  may be collectively referred to as a “gate stack.” The gate and the gate stacks may extend along sidewalls of a channel region  58  of the fins  52 . 
     The formation of the gate dielectric layers  92  in the n-type region  50 N and the p-type region  50 P may occur simultaneously such that the gate dielectric layers  92  in each region are formed from the same materials, and the formation of the gate electrodes  94  may occur simultaneously such that the gate electrodes  94  in each region are formed from the same materials. In some embodiments, the gate dielectric layers  92  in each region may be formed by distinct processes, such that the gate dielectric layers  92  may be different materials, and/or the gate electrodes  94  in each region may be formed by distinct processes, such that the gate electrodes  94  may be different materials. Various masking steps may be used to mask and expose appropriate regions when using distinct processes. 
     In  FIGS.  15 A and  15 B , gate masks  96 A and  96 B, collectively referred to as gate masks  96 , are formed over the gate stacks (including a gate dielectric layer  92  and a corresponding gate electrode  94 ), and the gate masks  96  may be disposed between opposing portions of the gate spacers  86 . In some embodiments, forming the gate masks  96  includes recessing the gate stack so that a recess is formed directly over the gate stack and between opposing portions of gate spacers  86 . A gate mask  96  comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled in the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD  88 . 
     In the first gate area  100 A, after forming the gate mask  96 A, the gate electrode  94 A may have a height H 5  in a range of 8 nm to 11 nm and a width W 3  in a range of 8 nm to 36 nm. The gate mask  96 A may have a height H 6  in a range of 0.5 nm to 2 nm. In the second gate area  100 B, after forming the gate mask  96 B, the gate electrode  94 B may have a height H 7  in a range of 72 nm to 103 nm and a width W 4  in a range of 72 nm to 240 nm. The gate mask  96 B may have a height H 8  in a range of 0.5 nm to 2 nm. 
     As also illustrated in  FIGS.  15 A and  15 B , a second ILD  108  is deposited over the first ILD  88 . In some embodiments, the second ILD  108  is a flowable film formed by a flowable CVD method. In some embodiments, the second ILD  108  is formed of a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD and PECVD. The subsequently formed gate contacts  110  ( FIGS.  16 A and  16 B ) penetrate through the second ILD  108  and the gate mask  96  to contact the top surface of the recessed gate electrode  94 . 
     In  FIGS.  16 A,  16 B, and  16 C , gate contacts  110 A and  110 B, collectively referred to as gate contacts  110 , and source/drain contacts  112  are formed through the second ILD  108  and the first ILD  88  in accordance with some embodiments, with  FIG.  16 C  illustrating a detailed view of region  118  as shown in  FIG.  16 B  and  FIG.  16 D  illustrating a detailed view of region  119  as shown in  FIG.  16 B . Openings for the source/drain contacts  112  are formed through the first ILD  88  and second ILD  108 . The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material may be formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  108 . The remaining liner and conductive material form the source/drain contacts  112 . An anneal process may be performed to form a silicide at the interface between the epitaxial source/drain regions  82  and the source/drain contacts  112 . The source/drain contacts  112  are physically and electrically coupled to the epitaxial source/drain regions  82 . 
     Openings for the gate contacts  110 A and  110 B are formed through the second ILD  108  and the gate masks  96 A and  96 B, respectively. The openings may be formed using acceptable photolithography and etching techniques. After forming the openings for the gate contacts  110 A and  110 B, the openings are first lined with respective liners  109 A and  109 B. The liners  109 A and  109 B are formed over bottom surfaces and sidewalls of the openings and may extend over exposed surfaces of the gate electrodes  94 A and  94 B, the gate masks  96 A and  96 B, the source/drain contacts  112 , and the second ILD  108 . The liners  109 A and  109 B comprise one or more layers of TaN, Ta, TiN, Ti, Co, or the like, or combinations thereof, and may be deposited by any suitable method, for example, CVD, PECVD, PVD, ALD, PEALD, ECP, electroless plating and the like. In some embodiments, the liners  109 A and  109 B comprise a bottom layer of Ti and a top layer of TiN. In some embodiments, a glue layer (not illustrated) is formed in the openings before forming the liners  109 A and  109 B. The glue layer may be TiSi and may have a thickness of 9 nm to 10 nm. 
     After forming the liners  109 A and  109 B, conductive fill material  111 A and  111 B for the gate contacts  110 A and  110 B, respectively, is formed in the openings. The conductive fill material  111 A and  111 B may be cobalt, copper, a copper alloy, silver, gold, tungsten, aluminum, nickel, or the like. A planarization process, such as a CMP, may be performed to remove excess material from a surface of the second ILD  108 . The remaining liners  109 A and  109 B and conductive fill material  111 A and  111 B form the gate contacts  110 A and  110 B and are physically and electrically coupled to the gate electrodes  94 A and  94 B, respectively. 
     The gate contact  110 A may be formed to a height H 9  in a range of 22 nm to 26 nm and to a width W 5  in a range of 16 nm to 37 nm. The gate contact  110 B may be formed to a height H 10  in a range of 16 nm to 20 nm. The gate contact  110 B may have a smaller height H 10  than the height H 9  of the gate contact  110 A, which may be due to the gate contact  110 A being formed on a taller gate electrode  94 B. 
     The gate contact  110 B may be formed to a width W 6  in a range of 42 nm to 38 nm, which may be useful in the subsequent formation of a recess with a rivet shape profile in a top surface of the gate contact  110 B (see below,  FIG.  19 B ). The smaller height H 10  could lead to over-etching of the gate contact  110 B in the subsequent formation of the recess with a rivet shape profile. The wider width W 6  may lead to the recess having a broader width and a more shallow depth, which may be useful for reducing over-etching of the gate contact  110 B. In some embodiments, a ratio of the width W 6  to the width W 5  is in a range of 1.2 to 2.6, and a ratio of the height H 10  to the height H 9  is in a range of 1.2 to 1.6. 
     The gate contact  110 B having a width W 6  smaller than 42 nm may be disadvantageous because it may lead to over-etching of the gate contact  110 B in the subsequent formation of the recess with a rivet shape profile. The gate contact  110 B having a width W 6  larger than 38 nm may be disadvantageous because it may lead to a shorter height of the gate contact  110 B. 
     The source/drain contacts  112  and gate contacts  110  may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross-sections, it should be appreciated that each of the source/drain contacts  112  and gate contacts  110  may be formed in different cross-sections, which may avoid shorting of the contacts. 
     In  FIGS.  17 A through  17 D , a second contact etch stop layer (CESL)  114  and an inter metal dielectric (IMD)  116  are formed.  FIG.  17 C  illustrates a detailed view of region  118  of  FIG.  17 B , and  FIG.  17 D  illustrates a detailed view of region  119  of  FIG.  17 B . The second CESL  114  is formed on top surfaces of the second ILD  108 , the gate contacts  110 , and source/drain contacts  112 . The second CESL  114  may comprise or be silicon nitride, silicon carbon nitride, silicon carbon oxide, carbon nitride, aluminum oxide, the like, or a combination thereof, and may be deposited by CVD, plasma enhanced CVD (PECVD), ALD, or another deposition technique. 
     The IMD  116  is formed on the second CESL  114  and may comprise or be silicon dioxide, a low-k dielectric material, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiO x C y , Spin-On-Glass, Spin-On-Polymers, silicon carbon material, TEOS, a compound thereof, a composite thereof, the like, or a combination thereof. The IMD  116  may be deposited by spin-on, CVD, flowable CVD (FCVD), PECVD, PVD, or another deposition technique. 
       FIGS.  18 A and  18 B , following from  FIGS.  17 C and  17 D , respectively, illustrate the formation of openings  124 A and  124 B through the IMD  116  and second CESL  114  to the gate contacts  110 A and  110 B. The IMD  116  and second CESL  114  may be patterned to form the openings  124 A and  124 B, for example, using photolithography and one or more etch processes. The etch process may be a dry etch and may include a reactive ion etch (RIE), neutral beam etch (NBE), inductively coupled plasma (ICP) etch, capacitively coupled plasma (CCP) etch, ion beam etch (IBE), the like, or a combination thereof. The etch process may be anisotropic. In some embodiments, the etching process can include a plasma using a first gas comprising carbon tetrafluoride (CF 4 ), methane (CH 4 ), hexafluoroethane (C 2 F 6 ), octafluoropropane (C 3 F 8 ), fluoroform (CHF 3 ), difluoromethane (CH 2 F 2 ), fluoromethane (CH 3 F), a carbon fluoride (e.g., C x F y  where x can be in a range from 1 to 5 and y can be in a range from 4 to 8), the like, or a combination thereof. The plasma can further use a second gas comprising nitrogen (N 2 ), hydrogen (H 2 ), oxygen (O 2 ), argon (Ar), xenon (Xe), helium (He), carbon monoxide (CO), carbon dioxide (CO 2 ), carbonyl sulfide (COS), the like, or a combination thereof. An inert gas may be optionally supplied during the etching process. In some embodiments, the openings  124 A are formed to a width W 7  in a range of 17 nm to 23 nm, and the openings  124 B are formed to a width W 8  in a range of 37 nm to 43 nm. 
       FIGS.  18 A and  18 B  further illustrate the formation of residual regions  126 A and  126 B on top surfaces of the gate contacts  110 A and  110 B, respectively. The residual regions  126 A and  126 B are formed by the reaction of the top surfaces of the gate contacts  110 A and  110 B with etchants from the formation the openings  124 A and  124 B. In some embodiments, the etchants may comprise fluorine and the material of the residual regions  126 A and  126 B may comprise a water-soluble metal fluoride such as, e.g. cobalt fluoride. 
       FIGS.  19 A and  19 B  illustrate the formation of recesses  128 A and  128 B in top surfaces of the gate contacts  110 A and  110 B, respectively. After the openings  124 A and  124 B are formed, a wet etch such as a wet cleaning process may be performed to remove the residual regions  126 A and  126 B from the gate contacts  110 A and  110 B. The wet cleaning process is performed to efficiently remove the residual regions  126 A and  126 B from the surfaces of the gate contacts  110 A and  110 B and to remove etching byproducts on the sidewalls of the IMD  116 . The recesses  128 A and  128 B may extend into respective top surfaces of the gate contacts  110 A and  110 B after the wet cleaning process removes the residual regions  126 A and  126 B. 
     In an embodiment, the wet cleaning process can include immersing the semiconductor substrate  50  (see above,  FIGS.  17 A and  17 B ) in deionized (DI) water or another suitable chemical (which may be diluted in DI water). In another embodiment, the wet cleaning process uses ammonium hydroxide. In an embodiment wherein the gate contacts  110  are fabricated from Co containing materials, DI water may efficiently dissolve the residual material which may be a water-soluble metal fluoride such as e.g. cobalt fluoride, thus removing the material of the residual regions  126 A and  126 B and forming the recesses  128 A and  128 B on the gate contacts  110 A and  110 B. In other embodiments, a chemical etchant which reacts with the material of the gate contacts  110  may be utilized. The recesses  128 A and  128 B may be formed as a concave surface (e.g., an upper concave surface on the gate contacts  110 ) having tip ends  129 A and  129 B formed under a bottom surface of the second CESL  114 . As the wet cleaning process is an isotropic etching process, the chemical reaction between the solution and the gate contacts  110  isotropically and continuously occurs when the solution contacts the gate contacts  110  until a predetermined process time period is reached. The tip ends  129 A and  129 B of the recesses  128 A and  128 B, respectively, extend laterally from the gate contacts  110 A and  110 B and further extend underneath the bottom surface of the second CESL  114 . The tip ends  129 A and  129 B may assist the materials subsequently formed therein to anchor and engage in the vias  120  with better adhesion and clinch, as well as catching slurry used in subsequent CMP processes (may also be referred to as CMP slurry) and reducing the amount of CMP slurry reaching the gate contacts  110 A and  110 B, thereby reducing further etching of the gate contacts  110 A and  110 B. 
     Because the width W 6  of the gate contact  110 B is larger than the width W 5  of the gate contact  110 A, the isotropic etching process may form the recess  128 A to a larger depth D 1  than the depth D 2  of the recess  128 B, and it may form the recess  128 A to a smaller width W 9  than the width W 10  of the recess  128 B. The depth D 2  being smaller than the depth D 1  may be useful because the height H 8  of the gate contact  110 B is smaller than the height H 7  of the gate contact  110 A and achieving a smaller depth D 2  of the recess  128 B may reduce over-etching of the recess  128 B through the gate contact  110 B into the gate electrode  94 B. This may be useful for reducing contact resistance and increasing yield gain for high bandwidth memory. 
     In some embodiments, the depth D 1  of the recess  128 A is in a range of 6 nm to 14 nm, which may be useful for achieving a wide enough rivet-shaped bottom portion of a subsequently formed conductive contact (see below,  FIG.  20 A ) to catch slurry used in subsequent CMP processes. The depth D 1  being less than 6 nm may be disadvantageous because the subsequently formed conductive contact may not be wide enough to catch slurry used in subsequent CMP processes, leading to undesirable etching of the gate contact  110 A. The depth D 1  being greater than 14 nm may be disadvantageous because the subsequently formed conductive contact may have an undesirably large width, which may lead to shorts with source/drain regions  82  or source/drain contacts  112  (see above,  FIG.  17 B ). 
     In some embodiments, the depth D 2  of the recess  128 B is in a range of 6 nm to 10 nm, which may be useful for achieving a wide enough rivet-shaped bottom portion of a subsequently formed conductive contact (see below,  FIG.  20 A ) to catch slurry used in subsequent CMP processes without undesirable over-etching of the gate contact  110 B. The depth D 2  being less than 6 nm may be disadvantageous because the subsequently formed conductive contact may not be wide enough to catch slurry used in subsequent CMP processes, leading to undesirable etching of the gate contact  110 B. The depth D 2  being greater than 10 nm may be disadvantageous because the gate contact  110 B may be over-etched, leading to greater contact resistance and worse device performance. In some embodiments, a width W 9  of the recess  128 A is in a range of 0.4 nm to 3.2 nm. 
     In  FIGS.  20 A and  20 B , which follow from  FIGS.  19 A and  19 B , respectively, conductive features  130 A and  130 B are formed in the recess  128 A and the opening  124 A and the recess  128 B and the opening  124 B, respectively, in connection with the gate contacts  110 A and  110 B, respectively. In some embodiments, the conductive features  130 A and  130 B are formed with a conductive fill material comprising tungsten that is deposited with an ALD process. A precursor comprising tungsten and fluorine may be used for the selective ALD, such as e.g. WF 6 . In other embodiments, the conductive features  130 A and  130 B can be formed by CVD, electroless deposition (ELD), PVD, electroplating, or another deposition technique. The conductive features  130 A and  130 B may be or comprise tungsten, cobalt, copper, ruthenium, aluminum, gold, silver, alloys thereof, the like, or a combination thereof. When the conductive features  130 A and  130 B substantially fill the recesses  128 A and  128 B and the openings  124 A and  124 B, respectively, the deposition process is then terminated. The excess of conductive features  130 A and  130 B outgrown from the openings  124 A and  124 B may be removed by using a planarization process such as a CMP, for example. The planarization process may remove excess conductive feature  130 A and  130 B from above a top surface of the IMD  116 . Hence, top surfaces of the conductive features  130 A and  130 B and the IMD  116  may be coplanar. The conductive features  130 A and  130 B may be or may be referred to as contacts, plugs, metal plugs, conductive lines, conductive pads, vias, via-to-interconnect layer (V 0 ), etc. A larger contact area on the bottom surface of the conductive features  130 A and  130 B may result in lower contact resistance, improving device functioning. 
     In order to make it easier to fill the openings  124 A and  124 B, the conductive features  130 A and  130 B may be formed without a barrier layer or an adhesion layer. Therefore, adhesion between the conductive features  130 A and  130 B and the IMD  116  may degrade, and tiny cracks may exist between the conductive features  130 A and  130 B and the IMD  116 . During the CMP process, the slurry used in the CMP process (may also be referred to as CMP slurry) may seep down through the cracks and reach the gate contacts  110 A and  110 B. The slurry may have a high etch selectivity (e.g., having a high etch rate) for the material (e.g., cobalt) of the gate contacts  110 A and  110 B, and therefore, may cause the upper surfaces of the conductive features  130 A and  130 B to recess, thereby causing unreliable electrical connection between the conductive features  130 A and  130 B and the underlying gate contacts  110 A and  110 B. By filling the recesses  128 A and  128 B with respective tip ends  129 A and  129 B (see above,  FIGS.  19 A and  19 B ), the conductive features  130 A and  130 B may comprise rivet-shaped bottom portions extending into top surfaces of the respective gate contacts  110 A and  110 B. The enlarged rivet-shaped bottom portions of the conductive features  130 A and  130 B may catch the CMP slurry seeping down the cracks and may reduce the amount of CMP slurry reaching the gate contacts  110 A and  110 B, thereby reducing or preventing recessing of the gate contacts  110 A and  110 B. 
     In some embodiments, a ratio of a width W 10  measured across opposing outer sidewalls of the rivet-shaped bottom portion of the conductive feature  130 B to the width W 8  measured across opposing inner sidewalls of the conductive feature  130 B is in a range of 1.2 to 1.5, which may be advantageous for catching the CMP slurry seeping down the cracks and thereby reducing or preventing recessing of the gate contacts  110 B. The ratio of the width W 10  to the width W 8  being smaller than 1.2 may be disadvantageous for not catching the CMP slurry seeping down the cracks and thereby increasing recessing of the gate contacts  110 B. The ratio of the width W 10  to the width W 8  being greater than 1.5 may be disadvantageous because it may lead to shorts between adjacent gate contacts  110 B and source/drain contacts  112 . 
       FIGS.  20 C through  20 F  illustrate top views of the structure through cross section D-D′ as shown in  FIG.  20 B , in accordance with some embodiments.  FIG.  20 C  illustrates an embodiment in which the gate contact  110 B and the conductive feature  130 B comprise rectangular profiles, wherein the conductive feature  130 B surrounds the gate contact  110 B.  FIG.  20 D  illustrates an embodiment in which the gate contact  110 B and the conductive feature  130 B comprise ovular profiles, wherein the conductive feature  130 B surrounds the gate contact  110 B.  FIG.  20 E  illustrates an embodiment in which the gate contact  110 B and the conductive feature  130 B comprise square profiles, wherein the conductive feature  130 B surrounds the gate contact  110 B.  FIG.  20 F  illustrates an embodiment in which the gate contact  110 B and the conductive feature  130 B comprise circular profiles, wherein the conductive feature  130 B surrounds the gate contact  110 B. However, as one having ordinary skill in the art will recognize, the top view profiles of the gate contact  110 B and the conductive feature  130 B described above are merely examples and are not meant to limit the current embodiments. Any suitable profiles may be used, and all such profiles are fully intended to be included within the scope of the embodiments discussed herein. 
     The disclosed FinFET embodiments could also be applied to nanostructure devices such as nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field effect transistors (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source/drain regions are formed in a manner similar to the above-described embodiments. After the dummy gate stacks are removed, the sacrificial layers can be partially or fully removed in channel regions. The replacement gate structures are formed in a manner similar to the above-described embodiments, the replacement gate structures may partially or completely fill openings left by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source/drain regions may be formed in a manner similar to the above-described embodiments. A nanostructure device can be formed as disclosed in U.S. Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety. 
     Embodiments may provide advantages. A gate contact is formed on a gate structure and a contact plug is subsequently formed on the gate contact. The gate contact has a larger width than the contact plug, and a rivet-shaped bottom portion of the contact plug extends into the gate contact. The rivet-shaped bottom portion of the contact plug may reduce undesirable etching of the gate contact by slurry from a subsequently performed CMP. The gate contact having a larger width than the contact plug may allow the rivet-shaped bottom portion of the contact plug to be wider and shallower, which may reduce undesirable contact resistance and improve yield gain for high bandwidth memory. 
     In accordance with an embodiment, a semiconductor device includes: a first gate electrode on a substrate; a second gate electrode on the substrate; a first conductive contact on the first gate electrode, the first conductive contact having a first height and a first width; a second conductive contact on the second gate electrode, the second conductive contact having a second height and a second width, the second height being smaller than the first height, the second width being greater than the first width; an etch stop layer (ESL) on the first conductive contact and the second conductive contact; a third conductive contact extending through the ESL, the ESL overhanging a portion of the third conductive contact, a convex bottom surface of the third conductive contact physically contacting a concave top surface of the first conductive contact, the third conductive contact having a third width measured at a bottom surface of the ESL; and a fourth conductive contact extending through the ESL, the ESL overhanging a portion of the fourth conductive contact, a convex bottom surface of the fourth conductive contact physically contacting a concave top surface of the second conductive contact, the fourth conductive contact having a fourth width measured at the bottom surface of the ESL, the fourth width being greater than the third width. In an embodiment, the first conductive contact and the second conductive contact include cobalt. In an embodiment, the third conductive contact and the fourth conductive contact include tungsten. In an embodiment, the semiconductor device further includes a dielectric layer between the second gate electrode and the ESL. In an embodiment, a portion of the second conductive contact is interposed between the dielectric layer and the fourth conductive contact. 
     In accordance with another embodiment, a semiconductor device includes: a first channel region on a semiconductor substrate; a second channel region on the semiconductor substrate; a first gate structure on the first channel region, the first gate structure including a first gate electrode, the first gate electrode having a first height; a second gate structure on the second channel region, the second gate structure including a second gate electrode, the second gate electrode having a second height, the second height being greater than the first height; a first dielectric layer on the first gate structure and the second gate structure; a first conductive contact on the first gate electrode, the first conductive contact extending to a top surface of the first dielectric layer; a second conductive contact on the second gate electrode, the second conductive contact extending to the top surface of the first dielectric layer; an etch stop layer (ESL) on the first dielectric layer, the ESL covering a portion of the first conductive contact and a portion of the second conductive contact; a third conductive contact, including: a first bottom portion below a lower surface of the ESL, the first bottom portion being surrounded by the first conductive contact in a top view, the first bottom portion extending under the lower surface of the ESL, the first bottom portion having a third width; and a first top portion above the lower surface of the ESL; and a fourth conductive contact, including: a second bottom portion below the lower surface of the ESL, the second bottom portion being surrounded by the second conductive contact in the top view, the second bottom portion extending under the lower surface of the ESL, the second bottom portion having a fourth width, the fourth width being greater than the third width; and a second top portion above the lower surface of the ESL. In an embodiment, the second conductive contact includes a liner and a conductive fill material. In an embodiment, the liner includes titanium. In an embodiment, the conductive fill material includes cobalt. In an embodiment, a portion of the conductive fill material is interposed between the liner and the fourth conductive contact. 
     In accordance with yet another embodiment, a method of forming a semiconductor device includes: depositing a first dielectric layer on a first gate electrode and a second gate electrode, the first gate electrode and the second gate electrode extending from a substrate; forming a first conductive material through the first dielectric layer, a first portion of the first conductive material having a first height and a first width, a second portion of the first conductive material having a second height and a second width, the first height being greater than the second height, the second width being greater than the first width; forming an etch stop layer (ESL) over the first conductive material and the first dielectric layer; depositing a second dielectric layer on the ESL; etching a first opening through the second dielectric layer and the ESL, the first opening extending into the first portion of the first conductive material, the first opening being surrounded by the second portion of the first conductive material in a top view, the ESL overhanging a portion of the first opening; etching a second opening through the second dielectric layer and the ESL, the second opening extending into the second portion of the first conductive material, the second opening being surrounded by the first conductive material in the top view, the ESL overhanging a portion of the first opening; and filling the first opening and the second opening with a second conductive material. In an embodiment, the first conductive material includes cobalt. In an embodiment, the second conductive material includes tungsten. In an embodiment, etching the first opening and the second opening includes a dry etch and a wet etch. In an embodiment, the dry etch includes fluorine. In an embodiment, the fluorine reacts with a top surface of the first conductive material to form a residual region including a water-soluble fluoride. In an embodiment, the wet etch is a wet cleaning process including deionized (DI) water. In an embodiment, the DI water removes the residual region. In an embodiment, the first opening extends into the first portion of the first conductive material below a bottom surface of the ESL to a first depth in a range of 6 nm to 14 nm. In an embodiment, the second opening extends into the second portion of the first conductive material below a bottom surface of the ESL to a second depth in a range of 6 nm to 10 nm. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.