Patent Publication Number: US-7907116-B2

Title: Dual output voltage system with charge recycling

Description:
TECHNICAL FIELD 
     The present invention generally relates to a drive system for a flat panel display. More particularly, the present invention relates to a dual output voltage system with charge recycling in Electrophoretic Panel Display (EPD) applications. 
     BACKGROUND 
     Panel displays are commonly used in electronic products. It is known to provide panel displays based on electrophoretic effects. Electrophoretic effects comprise charged particles dispersed in a fluid or liquid medium moving under the influence of an electric field. As an example of the application of the electrophoretic effects, displays may use charged pigment particles dispersed and contained in a dye solution and arranged between a pair of electrodes. The dye solution in which charged pigment particles are dispersed is known as “electrophoretic ink” or “electronic ink.” A display using electrophoretic ink is known as an electrophoretic display (“EPD”). Under the influence of an electric field, the charged pigment particles are attracted to one of two display electrodes. In response, the desired images are displayed. 
     In recent years, EPD technology was introduced for use in flat panel display.  FIGS. 1A  and B illustrate a technology using tiny microcapsules filled with electrically charged white particles suspended in a pigmented oil. For example,  FIG. 1A  illustrates one implementation in which the underlying circuitry controls whether white particles are at the top or bottom of the capsule. In this example, if the white particles are at the top of the capsule, the display appears white to the viewer. On the other hand, if the white particles are at the bottom of the capsule, the viewer sees the color of the oil, as illustrated in  FIG. 1B . Therefore, the use of microcapsules allows the display to be used on flexible plastic sheets, as well as on glass. 
     One feature of EPD technology is that the pixels are bi-stable. That is, the pixels can be maintained in either of two states without a constant supply of power. Another feature of EPD technology is that particles in an EPD panel move in different directions according to control voltages, in order to display different colors. As a result, EPD panels have a response time which is slower than those of other types of flat panel display. 
     One application of EPD technology, the electronic paper display device, is being developed as a next generation display device to replace liquid crystal display devices, plasma display panels, and organic electro-luminescent display panels. In particular, electronic paper display panels using “electronic ink” are expected to be a replacement, in certain applications, for existing print media such as books, newspapers, magazines, or the like. 
     An electronic ink display is well suited for use in a flexible display device because the device can be created on a flexible substrate. For example, by creating an electronic ink display device in a panel using a substrate of a flexible material, the electronic ink display device may have the advantages of flexibility, simplicity, and reliability. The electronic ink display device may also provide the means to construct paper-thin reflective displays without use of a backlight, resulting in very low power consumption. 
     However, the drive system of EPD panels requires high voltage levels. These high voltages can be provided by traditional DC-DC methods. However, low power consumption is an important objective in applications including EPD technologies. As a result, it is desirable to reduce power consumption in these applications. 
       FIG. 2  illustrates typical drive voltage levels and a waveform for an electrophoretic panel display. Initially, a top transparent “segment” electrode is connected to a first voltage level (V 1 ). The segment electrode is then driven to a second, higher, voltage level (V 0 ) before being returned to V 1 . For the entire period, a common electrode is always connected to V 1 . 
     A second DC-DC method is disclosed by Kurt Muhlemann, in an article entitled “A 30-V Row/Column Driver for Flat-Panel Liquid Crystal Displays.” Muhlemann presents the system architecture used in a STN (twisted-nematic) display driver, which can be slightly modified for use in an electrophoretic panel display (EPD). For example,  FIG. 3  shows a high voltage generation circuit  300  with output voltages V 0  and V 1 . The analog buffer  301  is supplied with voltages V 0 , of a positive value, and V ss , of zero value. In general, voltage V 0  may be generated from a regulated charge pump  302  or provided by an external power supply. A resistor ladder  303  is employed to set V 1  as a reference voltage level. 
     The function of analog buffer  301  is to provide a large driving capability for the V 1  voltage. Also shown in  FIG. 3  is a simplified segment and common (Seg/Com) controller  304 . Seg/Com controller  304  consists of a plurality of switches, coupled to a plurality of pixels (only one of which is shown) in the EPD panel. Each pixel may be represented by a capacitor C PIXEL    305 . The plurality of switches in Seg/Com controller  304  may be used to connect the pixels of the panel to the different voltage levels, such as V 0 , V 1 , or V ss . 
     However, the voltage generation method disclosed above presents several disadvantages. For example, analog buffer  301  consumes static current. Thus, analog buffer  301  and resistor ladder  303  exhibit current consumption which cannot be reduced even when the driving waveform (as shown in  FIG. 2 ) is not active. 
     Yet another disadvantage of the above-described voltage generation method is that the electrical charges in the panel&#39;s pixel may not be recycled or reused. As mention above, each of the pixels can be represented by a capacitor (C PIXEL )  305 . 
     The structure of  FIG. 2 , can exhibit charge transfer as shown in  FIGS. 4 and 5 .  FIG. 4  depicts Seg/Com controller  304  as separate elements (segment  406  and common  407 ). As shown in  FIG. 4 , during phase  1  of  FIG. 2 , a segment  406  is connected to a V 0  source and charged from V 1  to V 0 . During phase one, common  407  is also connected to V 1 . During this operation, segment  406  stores charge (Q) as determined by Equation 1.
 
 Q =( V 0− V 1)* C   Pixel   (Eq. 1)
 
     As shown in  FIG. 5 , during phase  2  of  FIG. 2 , the segment  406  is connected to a bias source of V 1 . At this time, a charge in the segment  406  equal to (V 0 -V 1 )*C PIXEL  will be discharged. If bias voltage V 1  is provided by an analog buffer  301 , the charge in the panel&#39;s pixel will go to ground (V ss ) through analog buffer  301  and be dissipated. Thus, no charge from the pixel can be reused or recycled, thereby resulting in undesirably high current consumption. 
     This shortcoming has been addressed in U.S. Pat. No. 6,556,177 to Katayama et al. by a charge recycling system  600  for electroluminescent display panel (EL) applications ( FIG. 6 ). The system disclosed by Katayama includes a power supply at V 1  and a capacitor  602 , which may represent a pixel (C PIXEL ). System  600  may also include a capacitor  601 , to perform charge recycling. As a result, system  600  of Katayama provides a voltage level that is twice the value of V 1 . 
       FIGS. 7A-C  show the charge recycling operation of Katayama. As shown in  FIG. 7A , during phase  1 , a pixel capacitor  602  and recycle capacitor  601  are charged from V ss  to V 1 . During phase  2 , switches operate as shown in  FIG. 7B , such that the capacitor  601  is connected in series with the power supply (V 1 ). The voltage across capacitor  601  then rises to a level equal to twice the value of V 1  (2*V 1 ) and charges the pixel  602  to the same level. During this operation, a charge equal to V 1 *C PIXEL  is transferred to pixel capacitor  602 . As shown in  FIG. 7C , during phase  3 , switches operate as shown, such that pixel capacitor  602  is connected to V 1  again. The charge equal to V 1 *C PIXEL  is transferred back and stored in the capacitor  601 . 
       FIGS. 8A-B  illustrate the voltage output of capacitor  601  and the waveform EL of pixel  602  as part of the charge recycling system  600  disclosed by Katayama. Initially, as shown in  FIG. 8A , during phase  1 , switches operate such that capacitor  601  is charged from V ss  to V 1 . During phase  2 , as shown in  FIG. 8A , switches operate such that capacitor  601  is connected in series with the power supply (V 1 ). Capacitor  601  then rises to a voltage level equal to twice the value of V 1  (2*V 1 ). During this operation, a charge equal to V 1 *C PIXEL  is transferred to pixel capacitor  602 . During phase  3 , the charge equal to V 1 *C PIXEL  is transferred back and stored in the capacitor  601 . 
     As shown in  FIG. 8B , during phase  1 , pixel capacitor  602  (EL) is charged by a voltage V 1 . During phase  2 , as shown in  FIG. 8B , capacitor  601  has a voltage level equal to twice the value of V 1  (2*V 1 ) and charges pixel capacitor  602  to the same voltage level (2*V 1 ). During this operation, a charge equal to V 1 *C PIXEL  is transferred to pixel capacitor  602  (EL). As shown in  FIG. 8B , during phase  3 , the voltage across pixel  602  is once again V 1 . Accordingly, a charge equal to V 1 *C PIXEL  is transferred from pixel  602  and stored in the capacitor  601 . 
     However, since capacitor  601  disclosed by Katayama is charged to V 1  during phase one and employed to generate a voltage level equal to twice the value of V 1  (2*V 1 ) at phase two, sources of voltages V 1  and 2*V 1  do not exist at the same time.  FIG. 8  illustrates the waveform EL of pixel capacitor  602  during a charge recycling operation.  FIG. 8A  shows that the voltage waveform of pixel capacitor  602  is dependent on the operation of the capacitor  601 . 
       FIGS. 8A-B  also show the available voltages of this system at each phase. At phases one and three, voltage levels V 1  and V ss  are available for driving the pixels. At phase two, 2*V 1  and V ss  levels are available. Due to this voltage availability limitation, only one drive voltage level (either V 1  or 2*V 1 ) is available for driving the pixels at any one time. 
     The output voltages of the DC-DC converter in Katayama are not continuous in time. Using the typical drive waveform for EPD pixels given in  FIG. 2  as an example, if V 0  and V 1  are not available simultaneously from the DC-DC converter in the form of continuous time voltages, a method for driving different pixels in sequence instead of in common will not be possible. Driving different pixels in sequence comprises starting and stopping a drive scheme of, for example V 1 -V 0 -V 1 , for different pixels at different times. Driving different pixels in common comprises starting and stopping the drive scheme for different pixels at the same time. 
     As such, there is a need for a power efficient charge recycling DC-DC converter system that provides continuous time output voltages. 
     SUMMARY 
     In one exemplary embodiment, there is provided a drive system for a flat panel display having segment and common lines. The system may include a first charge pump, including an input terminal for receiving electric charge at an input voltage level and a circuit for generating a first pumped voltage level. The system may also include a first storage capacitor coupled to the first charge pump for storing electric charge at the first pumped voltage level. The system may include a second charge pump, including an input terminal coupled to the first storage capacitor for receiving electric charge at the first pumped voltage level; a pump output terminal; and a circuit for generating a second pumped voltage level at the pump output terminal. The system may further include a second storage capacitor coupled to the pump output terminal for storing electric charge at the second pumped voltage level. The system may also include a controller coupled to the first and second storage capacitors, including segment and common output terminals respectively coupled to segment and common lines of an associated flat panel display; a plurality of switching devices coupled to the first and second storage capacitors; and a control circuit operating the switching devices to selectively connect the segment output terminal to the first and second storage capacitors so as to supply charge to the segment output terminal during a first phase and to return charge from the segment output terminal to the second storage capacitor during a second phase. 
     It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as described. Further features and/or variations may be provided in addition to those set forth herein. For example, the present invention may be directed to various combinations and subcombinations of the disclosed features and/or combinations and subcombinations of several further features disclosed below in the detailed description. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings, which are incorporated in and constitute a part of this specification, show certain aspects of the present invention and, together with the description, help explain some of the principles associated with the invention. In the drawings, 
         FIG. 1A  and B illustrate a cross-section of a thin electrophoretic film in accordance with the prior art; 
         FIG. 2  illustrates a typical drive voltage waveform and voltage level according to the prior art; 
         FIG. 3  illustrates a typical voltage generation circuit according to the prior art; 
         FIG. 4  illustrates an exemplary process of charging a pixel (C PIXEL ) from V ss  to V 0  according to the prior art; 
         FIG. 5  illustrates an exemplary process of discharging a pixel (C PIXEL ) from V 0  to V 1  according to the prior art; 
         FIG. 6  illustrates an exemplary charge recycling circuit according to the prior art; 
         FIG. 7A-C  illustrate an exemplary process of charging a pixel (C PIXEL ) in three different stages according to the prior art; 
         FIG. 8A-B  illustrate an exemplary waveform showing the process of charging a pixel (C PIXEL ) in three different stages according to the prior art. 
         FIG. 9  illustrates a dual output voltage system consistent with the present invention; 
         FIG. 10  illustrates a typical 2× charge pump with regulated output function consistent with the present invention; and 
         FIGS. 11 and 12  illustrate the operation of the proposed dual voltage output system with a pixel consistent with the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the invention, examples of which are illustrated in the accompanying drawings. The implementations set forth in the following description do not represent all implementations consistent with the claimed invention. Instead, they are merely some examples consistent with certain aspects related to the invention. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. 
       FIG. 9  shows a drive system  900  for an electrophoretic panel display (EPD) consistent with the present invention. System  900  constitutes a dual output voltage system and includes a 4× booster circuit  901  that consists of two 2× booster circuits  902  and  903 . A first stage charge pump  903  provides voltage level V 1 . Voltage level V 1  may be employed to drive an electrophoretic panel display (EPD) without the use of a traditional analog buffer. In addition, the output of first stage charge pump  903  is supplied to the input of a second stage charge pump  902 , which generates a V 0  voltage level. All voltage levels in  FIG. 9  are referenced to a common voltage V ss . 
     In general, the drive capacity of charge pump  903  is greater than that of an analog buffer. Eliminating the use of a traditional analog buffer may also result in lower power consumption and a smaller silicon area. The design of system  900  may also eliminate driving capability limitations posed by analog buffers. 
     In contrast to the analog buffers employed by prior art systems, in system  900 , the response time for driving an electrophoretic panel display (EPD) with the output of charge pump  903  only depends on the storage capacitance and the segment resistance. It should be noted that the proposed design of system  900  may provide either dual regulated voltages or one regulated output voltage, depending on the required accuracy of the output voltages. 
     In  FIG. 9 , each 2× charge pump  902  and  903  consists of switches employed to transfer energy and boost the input voltage to output voltage (not shown); a flying capacitor C F1  or C F2  employed to transfer charge; a comparator and feedback network, employed to control and define a regulated output level (not shown); and a storage capacitor C S1  or C S2 , employed to store energy charge and to stabilize the output voltage level. 
       FIG. 10  illustrates a 2× charge pump  1000  with regulated output function that may be implemented as charge pump  902  or  903 . The operation principle of 2× charge pump  1000 , including two phases, is now described. 
     In phase one, clock driver PH 1  switches are operated by Phase Control Logic such that a flying capacitor, C flying , is pre-charged to Vin level with a VN terminal connected to V ss  and a VP terminal connected to Vin. 
     In phase two, PH 1  switches are opened while PH 2  switches are closed. Terminal VN is connected to Vin level and terminal VP is pumped to a 2× V IN  voltage level by a capacitor coupling effect. The charge stored in C flying  will perform the charge redistribution, with C storage  providing charge at a 2× V IN  voltage level to V out . 
     The regulated mode of the 2× charge pumps is now described. In 2× charge pump  1000 , resistors R 1  and R 2  function as a voltage divider. This voltage divider defines the regulated output value. A feedback voltage V FB  is compared with a pre-defined reference voltage V REF  by the voltage comparator. If V FB  is larger than V REF , the voltage comparator will output a control signal to the phase control logic, directed to stop the pump action by stopping the clock driving the switches, e.g., switches PH 1 , PH 2 . 
       FIGS. 11 and 12  illustrate the operation of system  900  with a pixel, represented by capacitor  1101 , with the waveform at  FIG. 2 . The operation is separated into phase one and phase two. During phase one ( FIG. 12 ), pixel capacitor  1101  is charged to V 0  from V 1 . As a result, an amount of charge equal to (V 0 -V 1 )*C PIXEL  is transferred to the pixel capacitor  1101 . During phase two ( FIG. 11 ), pixel capacitor  1101  is connected to V 1 . The charge equal to (V 0 -V 1 )*C PIXEL  is then released and transferred back to C S1 . These charges not only increase the voltage level of V 1 , but may also function as an energy source for the second stage charge pump  902 . Therefore, by returning the charges, they may be reused rather than discharged to V ss . 
     As a result, in system  900 , voltages V 0 , V 1 , and V ss  exist at the same time. Also, output voltages are continuously maintained by means of the capacitors (C S1 , C S2 ). The pixel&#39;s waveform does not depend on the switching frequency and timing of the charge pump or power system. Moreover, a new pixel&#39;s waveform does not need to wait for the previous pixel&#39;s waveform to be completed first. 
     Although system  900  shows architecture with two similar charge pump stages, each charge pump stage outputting a voltage level 2× of input voltage level, the architecture of system  900  may be extended to allow cascading of stages which may not be similar in circuit configurations and which may have different times of multiplication of input voltages (e.g., 3×, 4×, etc.). The architecture of system  900  can also extend, for example, to a charge pump system consisting of multiple branches of cascaded stages, with downstream stages taking electronic charges from the outputs of upstream stages of multiple branches, in order to produce outputs at voltage levels required in the application, wherein optimization of power efficiency considerations on the system level will indicate the optimal output to be used for the input of each stage. 
     Various configurations are possible. For example, all components of system  900  may be packaged as an integrated circuit. 
     System level consideration for power efficiency should take the driving scheme and the panel loading into account. Generally, the overall charge pump system would consist of a minimum number of stages that can still meet the number of drive levels required. The system should balance charging and discharging of panel loading in order to minimize instantaneous power demand from power supplies. 
     The foregoing description is intended to illustrate but not to limit the scope of the invention, which is defined by the scope of the appended claims. Other embodiments are within the scope of the following claims.