Patent Publication Number: US-2007101207-A1

Title: PCI Express interface testing apparatus

Description:
BACKGROUND OF THE INVENTION  
      1. Field of the Invention  
      The present invention relates to a Peripheral Component Interconnect Express (PCI Express) interface testing apparatus for a motherboard.  
      2. General Background  
      PCI Express is a revolution in graphics add-in card-interconnect standards. This specification, significantly increases bandwidth between the central processing unit and graphics processing unit by enabling balanced distribution of bandwidth to those applications that require it the most.  
      A connection between any two PCI Express devices is known as a “link”. The PCI Express link is built around a bidirectional, serial (1-bit), point-to-point connection known as a “lane”. Transmitting and receiving pairs are separate differential-pairs for a total of 4 data wires per lane. The PCI Express link may be comprised of multiple lanes. In such configurations, the connection is labeled as x 1 , x 2 , x 4 , x 8 , x 16 , or x 32 , where the number is effectively the number of lanes. Therefore, where PCI Express x 1  would require 4 wires to connect, an x 16  implementation would require 16 times that amount or 64 wires. This also results in differently sized slots.  
      With increasing performance requirement of computers, accurate testing of characteristics of signal transmission, such as signal sensitivities, jitter tolerances, and so on, of both sending and receiving signals are needed. Testing signal transmissions through different PCI Express slots of a motherboard is needed to insure proper performance.  
      Therefore, appropriate devices are needed to validate the characteristics of signal transmissions of a PCI Express interface slots. A typical PCI Express interface testing apparatus can test the characteristics of signal transmissions of the sending signals of the elements adopting the PCI Express interface specification. However, the characteristics of the signal transmissions of the receiving signals cannot be tested.  
      What is needed, therefore, is a PCI Express interface testing apparatus which can test characteristics of signal transmission of both the sending and receiving signal elements of the interface.  
     SUMMARY  
      In one preferred embodiment, a PCI Express interface testing apparatus for testing characteristics of signal transmissions of a PCI Express interface includes a printed circuit board, a plurality of sending signal connectors, and a plurality of receiving signal connectors. Both the sending signal connectors and the receiving signal connectors are electrically connected to the printed circuit board. A method for testing the characteristics of signal transmissions of a PCI Express interface is also provided.  
      Other advantages and features will become more apparent from the following detailed description when taken in conjunction with accompanying drawings, in which: 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
       FIG. 1  is an isometric view of a PCI Express interface testing apparatus in accordance with a preferred embodiment of the present invention;  
       FIG. 2  is a side view of the PCI Express interface testing apparatus of  FIG. 1  mounted on a printed circuit board in a first position and including an oscilloscope; and  
       FIG. 3  is similar to  FIG. 2 , but the PCI Express interface testing apparatus is in a second position and connected to a signal source. 
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENT  
      A PCI Express interface testing apparatus in accordance with a preferred embodiment of the present invention is described herein. Referring to FIGS.  1  to  3 , the apparatus  10  includes a circuit substrate such as a printed circuit board (PCB)  11  and a plurality of connectors  13 , the connectors  13  include a plurality of sending signal connectors  15  and receiving signal connectors  17 . A test device such as an oscilloscope  30 , and a signal injection device such as a signal source  40 , is provided to cooperate with the apparatus  10  to test PCI Express interface slots. The connectors  15 ,  17  are electrically connected with the PCB  11 . Typically, different elements adopting PCI Express interface specifications are connected with an electronic component such as a motherboard  22  via different sizes of PCI Express interface slots. For example, a north bridge chip  20  is on the motherboard  22 . The north bridge chip  20  transmits signals via a PCI Express x 16  slot  24  of the motherboard  22 . The slot  24  consists of 16 lanes according to known specifications (not shown). Each lane has a sending portion and a receiving portion. In the preferred embodiment of the present invention, two similar testing printed circuit boards are needed to allow testing a group of first 8 lanes and then a group of second 8 lanes of the slot  24  respectively, any problem detected in testing is thus isolated to either the first group of lanes or the second group of lanes of the slot  24 . In the following description, only the printed circuit board  11  configured with traces for connecting the connectors  15 ,  17  to the first group of lanes of the slot  24  via a sending interface  12  and a receiving interface  14  is explained. The other of the two PCBs is similar to the PCB  11 , except the only difference is that traces therein are configured for electrically connecting connectors to the second group of lanes of the slot  24 . PCI Express x 1 , x 2 , x 4 , x 8 , x 32  slots can be tested in a similar manner as well, using PCBs with traces and connectors configured accordingly.  
      In the preferred embodiment, the sending interface  12  is formed along one side of the PCB  11 , and the receiving interface  14  is formed on an opposite side thereof. The connectors  15 ,  17  are further arranged and connected to the PCB  11  in pairs. There are eight pairs for each of connectors  15 ,  17 . That is one pair of connectors  15  for each sending portion and one pair of connectors  17  for each receiving portion of each lane of the first group of eight lanes.  
      The detail testing process is as follows: first, the sending interface  12  is inserted into the PCI Express x 16  slot  24  of the motherboard  22 . Then the north bridge chip  20  is activated to transmit signals via the slot  24 . Probes  21 ,  31  of the oscilloscope  30  are then contacted with each pair (line  21  to one of the pair, line  23  to the other of the pair) of connectors  15  in turn. Readings of the oscilloscope  30  then reveal if the sending portions of the first group of lanes are operating properly.  
      Then, to test the receiving portions of the first group of lanes, the receiving interface  14  is inserted into the slot  24 . Then the signal source  40  is activated to inject a test signal via output lines  31 ,  33 . The probes  21 ,  23  of the oscilloscope  30  are connected to the north bridge chip  20  for monitoring the injected test signal. Then the output lines  31 ,  33  are connected to each pair (line  31  to one of the pair, line  33  to the other of the pair) of receiving connectors  17  in turn. Thus, readings of the oscilloscope  30  then reveal if the receiving portions of the first group of lanes are operating properly.  
      It is believed that the present embodiment and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the example hereinbefore described merely being a preferred or exemplary embodiment.