Patent Publication Number: US-2021172999-A1

Title: Circuit for testing monitoring circuit and operating method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the benefit of Korean Patent Application No. 10-2019-0162913, filed on Dec. 9, 2019 in the Korean Intellectual Property Office, the subject matter of which is hereby incorporated by reference. 
     BACKGROUND 
     The inventive concept relates to test circuits, and more particularly, test circuits that verify the operation of a monitoring circuit. The inventive concept also relates to methods of testing a monitoring circuit. 
     Monitoring circuits may be used to detect abnormal operation of components in an electrical system. For example, because serious problems may arise if electrical components operate abnormally in a vehicle. Hence, a monitoring circuit is often used to detect any abnormal operation of the electrical components. As the number of electrical components increases and the number of functions performed by the electrical components is increases, however, the number of monitoring circuits required to detect abnormal operation increases dramatically. 
     Given the importance of the monitoring circuit, a test circuit for testing the monitoring circuit may be used. For example, the test circuit may test the monitoring circuit while the monitoring circuit stops monitoring the operations of the electrical components. Due to high accuracy of the monitoring circuit, the test circuit may also be required to have high accuracy. Due to the increased number of monitoring circuits, the test circuit may be required to have high efficiency, for example, a small area and low power consumption. 
     SUMMARY 
     The inventive concept provides a circuit for testing a monitoring circuit with high accuracy and high efficiency and an operating method thereof. 
     According to an aspect of the inventive concept, there is provided a test circuit for testing a monitoring circuit, including: a ramp generator configured to generate a ramp signal in response to an activated first control signal, a counter configured to count pulses of a clock signal in response to the activated first control signal, at least one register configured to store an output value of the counter based on change in an output signal generated by the monitoring circuit in response to the ramp signal, and a controller configured to generate the first control signal, wherein the monitoring circuit is set to a test mode in response to an activated first control signal, and the controller is further configured to verify the operation of the monitoring circuit based on a ratio of at least one value stored in the at least one register, wherein the at least one value is obtained during the test mode. 
     According to an aspect of the inventive concept, there is provided a system including; a main circuit configured to perform at least one function and generate an object signal, a monitoring circuit configured to monitor the object signal during a normal mode and monitor a ramp signal during a test mode, and a test circuit configured as a built-in, self-test for the monitoring circuit, and further configured to generate the ramp signal and test the monitoring circuit based on a ratio between a first period during which the ramp signal is generated, and a second period determined by a change in an output signal of the monitoring circuit in response to the ramp signal. 
     According to an aspect of the inventive concept, there is provided a method of testing a monitoring circuit. The method includes; generating a ramp signal, counting pulses of a clock signal while the ramp signal is generated, storing a first count value based on a first period determined by a change in an output signal of the monitoring circuit, and verifying the monitoring circuit based on a ratio of the first count value and a second count value based on a second period determined by the generating of the ramp signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: 
         FIG. 1  is a block diagram illustrating an electrical system according to an embodiment of the inventive concept; 
         FIG. 2  is a block diagram further illustrating an example of the monitoring circuit  14  of  FIG. 1  according to an embodiment of the inventive concept; 
         FIG. 3  is a block diagram illustrating an example of the test circuit  30  according to an embodiment of the inventive concept; 
         FIGS. 4A and 4B  are respective circuit diagrams illustrating examples of the a ramp generator according to an embodiment of the inventive concept; 
         FIG. 5  is a timing diagram illustrating an example of an operation of a test circuit according to an embodiment of the inventive concept; 
         FIG. 6  is a block diagram further illustrating an example of a test circuit according to an embodiment of the inventive concept; 
         FIG. 7  is a block diagram further illustrating an example of a test circuit according to an embodiment of the inventive concept; 
         FIGS. 8 and 9  are respective timing diagrams illustrating examples of an operation of a test circuit according to an embodiment of the inventive concept; 
         FIG. 10  is a block diagram illustrating an example of a test circuit according to an embodiment of the inventive concept; 
         FIG. 11  is a timing diagram illustrating an example of an operation of a test circuit according to an embodiment of the inventive concept; 
         FIG. 12  is a block diagram further illustrating an example of a monitoring circuit according to an embodiment of the inventive concept; 
         FIG. 13  is a block diagram further illustrating an example of a test circuit according to an embodiment of the inventive concept; 
         FIG. 14  is a block diagram illustrating an electrical system according to an embodiment of the inventive concept; 
         FIG. 15  is a timing diagram illustrating an example of an operation of an electrical system according to an embodiment of the inventive concept; 
         FIGS. 16, 17A, 17B, 18A, 18B and 19  are respective flowcharts variously summarizing examples of methods of testing a monitoring circuit according to an embodiment of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 1  is a block diagram illustrating an electrical system  10  according to an embodiment of the inventive concept. The electrical system  10  may be any apparatus configured to perform one or more function(s) using electrical energy. For example, the electrical system  10  may be a semiconductor chip, a module including at least one semiconductor chip, or a system including two or more modules that communicate with each other. The electrical system  10  may be a unit capable of independent use (e.g., a mobile phone), a unit (or functional component) configured for operation within a system (e.g., a vehicle), or a constituent (or entire) system (e.g., a System-on-Chip). As illustrated in  FIG. 1 , the electrical system  10  may generally include, possibly among many other elements, a main circuit  12 , a monitoring circuit  14 , and a test circuit  16 . 
     The main circuit  12  may be designed to perform one or more function(s) associated with the electrical system  10 . That is, the main circuit  12  may actually perform the one or more function(s) or perform a function that is, in an of itself, a basis for one or more function(s) performed by the electrical system  10 . For example, the main circuit  12  may include one or more analog circuit(s) (e.g., a voltage generator, an analog filter, an amplifier, etc.), one or more digital circuit(s), and/or one or more mixed signal circuit(s) (e.g., an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), etc.). Hereinafter, a voltage generator will principally be referred to as one example of the main circuit  12 , but it will be understood that embodiments of the inventive concept are not limited thereto. 
     It is possible for a myriad of reasons (e.g., manufacturing defects, aging wear and tear, mechanical shock, harsh operating conditions, etc.) that the main circuit  12  may fail to properly perform an intended function (hereafter, generally, “operates abnormally”). When the main circuit  12  operate abnormally, the electrical system  10  and/or a system incorporating the electrical system  10  may operationally fail. 
     For example, the electrical system  10  may be included in a vehicle and may be intended to perform one or more critical function(s) necessary to the safe driving (e.g., autonomous driving) of the vehicle. Hence, any abnormal operation of the electrical system  10  may cause serious problems. In order to safeguard against an abnormal operation of the main circuit  12  and/or the electrical system  10  in certain applications, various international standards have been defined and are widely available (e.g., on the Internet). For example, one standard referred to as ISO26262 has been defined by the International Standard Organization (ISO) and relates to the operation and functional safety of vehicles. In this regard, ISO26262 defines various requirements for functional safety associated with electrical and/or electronic (E/E) systems in vehicles. In one particular aspect, ISO26262 requires the essential inclusion of a component capable of continuously monitoring the functional operation of the main circuit  12 . 
     As generally expressed in  FIG. 1 , the monitoring circuit  14  may be used to monitor the main circuit  12 . For example, the monitoring circuit  14  may monitor the operation of the main circuit  12  in response to (or based on) an object signal OBJ provided by the main circuit  12 . When the main circuit  12  operates abnormally, the monitoring circuit  14  may generate an output signal OUT indicating the abnormal operation of the main circuit  12 . The output signal OUT may be provided to component(s) internal to the electrical system  10  (e.g., a system controller  148  of  FIG. 14 ), and/or component(s) external to the electrical system  10 . Therefore, whether the main circuit  12  operates abnormally/normally may be determined based on the output signal OUT. When the main circuit  12  operates abnormally, necessary follow-up measures must be appropriately undertaken. In some embodiments, like those described with reference to  FIG. 2  hereafter, the monitoring circuit  14  may include one or more comparator(s) configured to determine the state of the object signal OBJ. That is, in certain embodiments of the inventive concept, the monitoring circuit  14  may generate the output signal OUT based on the output of comparator(s). Examples of the monitoring circuit  14  will be described in some additional detail with reference to  FIGS. 2 and 12 . 
     International standards, such as ISO26262, may define the essential inclusion of the monitoring circuit  14  for the monitoring of the main circuit  12 , as well as certain additional component(s) configured to detecting whether or not the monitoring circuit  14  itself is operating normally. That is, the test circuit  16  (e.g., a built-in, self-test or BIST) may be provided as a further safeguard related to the functional performance of the main circuit  12 . For example, should the monitoring circuit  14  operate abnormally, a concurrent abnormal operation by the main circuit  12  could go undetected (a false positive indication). Alternately, a malfunctioning monitoring circuit  14  may erroneously generate the output signal OUT indicating abnormal operation of the main circuit  12  when, in fact, the main circuit  12  is operating normally (a false negative indication). To prevent either of these outcomes, the test circuit  16  may be used to verify the normal operation of the monitoring circuit  14 —as the monitoring circuit  14  monitors the performance of the main circuit  12 . 
     In the illustrated example of  FIG. 1 , the test circuit  16  provides a mode signal MD and a ramp signal RMP to the monitoring circuit  14 , and further provides a verify signal VFY indicating the results of verification testing on the monitoring circuit  14  in response to the output signal OUT provided by the monitoring circuit  14 . Here, the verify signal VFY may be provided to one or more internal components and/or one or more external components. 
     In this regard, the monitoring circuit  14  may be configured (or set) to operate in either a “normal mode” during which the monitoring circuit  14  monitors the main circuit  12 , or a “test mode” during which the monitoring circuit  14  performs verification testing in conjunction with the test circuit  16 . Thus, the monitoring circuit  14  may be configured in response to the mode signal MD to set either the normal mode or test mode of operation. For example, during the normal mode, the monitoring circuit  14  may generate the output signal OUT based on the object signal OBJ received from the main circuit  12 . In contrast, during the test mode, the monitoring circuit  14  may generate the output signal OUT based on the ramp signal RMP received from the test circuit  16 . 
     In regular operation, therefore, the test circuit  16  may set the monitoring circuit  14  to the test mode using the mode signal MD in order to run verification testing on the monitoring circuit  14 , and once the verification testing is complete, the test circuit  16  may reset the monitoring circuit  14  to the normal mode using the mode signal MD. In some embodiments, as described below with reference to  FIG. 3 , the mode signal MD may be same as a first control signal CTR 1 . 
     The test circuit  16  may generate the ramp signal RMP that gradually increases or decreases in order to test the monitoring circuit  14 . As described above, the monitoring circuit  14  may include at least one comparator that determines the state (or adequacy) of the object signal OBJ. In the test mode, the ramp signal RMP may be provided to the at least one comparator included in the monitoring circuit  14 . When the monitoring circuit  14  operates normally, the state of the output signal OUT may change at a first time according to a particular magnitude of the ramp signal RMP. Otherwise, the output signal OUT may change at a second time, different from the first time, or it may not change at all over a period of the ramp signal RMP. In some embodiments, the test circuit  16  may determine this “change time”, as measured by the change in the output signal OUT in response to the ramp signal RMP. In certain embodiments of the inventive concept, verification testing of the monitoring circuit  14  may include determining a ratio between the change time and an overall test time. Therefore, the monitoring circuit  14  may be accurately tested in spite of possible variations in a clock signal and/or the ramp signal RMP used to determine the change time and/or a total test time, thereby improving the reliability of the electrical system  10 . 
     In some embodiments, the electrical system  10  may include a plurality of monitoring circuits that respectively monitor the main circuit  12  or additional main circuits  12  (not shown in  FIG. 1 ). For example, a DC-DC converter used to generate a supply voltage may require about 10 or more monitoring circuits. Thus, when multiple DC-DC converters are included in the electrical system  10  in order to generate different supply voltages, the total number of monitoring circuits included in the electrical system  10  may become significant. For example, a dramatic increase in the number of monitoring circuits may cause a corresponding increase in the number of required test circuits, and the resulting tangle of many monitoring circuits and test circuits may greatly complicate the design and layout of the electrical system  10  and adversely impact the spatial efficiency of the electrical system  10 . 
     Alternatively, instead of increasing the number of test circuits, two or more monitoring circuits may share a test circuit. However, in this case, additional components may be required to facilitate the connection and operational sharing of the test circuit, and test errors may occur due to extended distancing between the test circuit and the monitoring circuit. In great contrast, embodiments of the inventive concept, like those described in relation to  FIGS. 4A and 4B , the test circuit  16  of  FIG. 1  may include an analog circuit having a simple structure and configured to generate the ramp signal RMP. Such embodiments allow BIST to be faithfully achieved with reduced overall overhead and complexity. 
       FIG. 2  is a block diagram further illustrating an example of the monitoring circuit  14  of  FIG. 1  according to an embodiment of the inventive concept. As described above with reference to  FIG. 1 , the monitoring circuit  20  of  FIG. 2  may be configured to monitor the functional performance of the main circuit  12  by determining the state (e.g., a level) of the object signal OBJ. As illustrated in  FIG. 2 , the monitoring circuit  20  may include a first comparator  21 , a second comparator  22 , and a switch circuit  25 . 
     Referring to  FIGS. 1 and 2 , the monitoring circuit  20  may monitor whether the level of the object signal OBJ falls within a specified “normal range.” For example, the monitoring circuit  20  may receive the object signal OBJ (e.g., as an object voltage V OBJ ) and the ramp signal RMP (e.g., as a ramp voltage V RMP ). The normal range of the object voltage V OBJ  may be defined by a second reference voltage V REF2  that is different from (e.g., greater than) a first reference voltages V REF1  (e.g., V REF2 &gt;V REF1 ), such that the monitoring circuit  20  may detect whether the object voltage V OBJ  falls between the first reference voltage V REF1  and the second reference voltage V REF2 . To this end, the monitoring circuit  20  may include a first comparator  21  that receives the first reference voltage V REF1  and a second comparator  22  that receives the second reference voltage V REF2 . The monitoring circuit  20  may generate an output signal OUT as a first output signal OUT 1  provided by the first comparator  21  and a second output signal OUT 2  provided by the second comparator  22 . Here, the first reference voltage V REF1  may be referred to as a “lower limit” of the object voltage V OBJ , and the second reference voltage V REF2  may be referred to as an “upper limit” of the object voltage V OBJ . 
     The switch circuit  25  may be used to provide either the object voltage V OBJ  or the ramp voltage V RMP  to the first and second comparators  21  and  22  in response to the mode signal MD provided by the test circuit  16 . For example, the switch circuit  25  may provide the object voltage V OBJ  to the first and second comparators  21  and  22  when the mode signal MD indicates the normal mode, and the ramp voltage V RMP  to the first and second comparators  21  and  22  when the mode signal MD indicates the test mode. Therefore, as described below with reference to  FIG. 5 , in the test mode, the first and second comparators  21  and  22  may generate the first and second output signals OUT 1  and OUT 2 , which respective change at first and second times at which the ramp voltage V RMP  respectively crosses the first and second reference voltages V REF1  and V REF2 . In the following description, and as illustrated in  FIG. 2 , it is assumed that the object signal OBJ and the ramp signal RMP of  FIG. 1  are the object voltage V OBJ  and the ramp voltage V RMP , respectively, and, therefore, that the monitoring circuit  14  includes the voltage comparator. However, it should be noted that the monitoring circuit  14  may perform monitoring using other types of signals (e.g., current signals). In some embodiments, the switch circuit  25  may include at least one transistor controlled by the mode signal MD. 
       FIG. 3  is a block diagram further illustrating an example of the test circuit  16  of  FIG. 1  according to an embodiment of the inventive concept. Referring to  FIGS. 1, 2 and 3 , the test circuit  30  may receive the output signal OUT and generate the ramp signal RMP and the verify signal VFY. In addition, the test circuit  30  may be used to generate a first control signal CTR 1 . The first control signal CTRL 1  may be used as the mode signal MD previously described in relation to  FIGS. 1 and 2 , or as a separate control signal in addition to the mode signal MD. In the illustrated example of  FIG. 3 , the test circuit  30  includes a ramp generator  31 , a controller  33 , a counter  35 , and a register set  37 . 
     In the description that follows, control signals like the mode signal MD and the first control signal CTR 1  are assumed to be active high signals. Therefore, an activated control signals has a high level and a inactivated control signal has a low level. 
     The ramp generator  31  may generate a ramp voltage V RMP  in response to an activated first control signal CTR 1 . For example, the ramp generator  31  may generate the ramp voltage V RMP  that gradually increases over a period beginning from when the first control signal CTR 1  is activated (e.g., the period between time t 11  and time t 18  shown in  FIG. 5 ). The ramp generator  31  may generate the ramp voltage V RMP  capable of crossing both the lower limit (e.g., the first reference voltage V REF1 ) and the upper limit (e.g., the second reference voltage V REF2 ). In some embodiments, the period during which the first control signal CTR 1  is activated may be the same as a period during which the monitoring circuit  20  is set to the test mode. This period may be referred to as a test period (PER 0 ). As described hereafter with reference to  FIGS. 4A and 4B , the ramp generator  31  may generate the ramp voltage V RMP  using a simple circuit structure instead of a more complicated structure like a DAC. 
     The counter  35  may generate a count signal CNT by counting pulses of a clock signal in response to the activated first control signal CTR 1 . Thus, the count signal CNT may be referred to as an output of the counter  35 , and a value indicated by the count signal CNT may be referred to as an output value or a “count value” of the counter  35 . Here, the counter  35  may be reset in response to the inactivated first control signal CTR 1  (e.g., CNT=0) and may start counting at a time at which the first control signal CTR 1  is activated. As illustrated in  FIG. 3 , the count signal CNT may be provided to the register set  37 . In some embodiments, the counter  35  may include a number of logic gates. 
     In the illustrated example of  FIG. 3 , the register set  37  includes at least one register, receives the output signal OUT and the count signal CNT, and provides at least one value VAL stored in the register set  37  to the controller  33 . For example, the register set  37  may include first and second registers REG 1  and REG 2 . Values stored in the first and second registers REG 1  and REG 2  may be provided to the controller  33 . The register set  37  may store a count value for the count signal CNT in response to the output signal OUT. For example, as described above with reference to  FIG. 2 , the output signal OUT may change when the ramp voltage V RMP  crosses the lower limit (i.e., V REF1 ) and/or the upper limit (i.e., V REF2 ). That is, the first register REG 1  may store the a first count value when the output signal OUT changes in relation to the crossing of the lower limit, and the second register REG 2  may store a second value when the output signal OUT changes in relation to the crossing of the upper limit. Therefore, as described below with reference to  FIG. 5 , the controller  33  may recognize, according to one value VAL, a time period extending from a time at which the generation of the ramp voltage V RMP  begins (e.g., the time at which the first control signal CTR 1  is activated), to a time at which the ramp voltage V RMP  crosses the lower limit. The controller  33  may further recognize, according to another value VAL, a time period extending from a time at which the generation of the ramp voltage V RMP  begins (e.g., the time at which the first control signal CTR 1  is activated), to a time at which the ramp voltage V RMP  crosses the upper limit. 
     In other embodiments, instead of the register set  37  directly receiving the output signal OUT, the controller  33  may receive the output signal OUT and the register set  37  may store the value of the count signal CNT under the control of the controller  33 . 
     The controller  33  may obtain at least one value VAL from the register set  37  and may generate the first control signal CTR 1  and the verify signal VFY. The controller  33  may set the monitoring circuit  20  to the test mode by generating the activated first control signal CTR 1  and may set the monitoring circuit  20  to the normal mode by generating the inactivated first control signal CTR 1 . The controller  33  may determine whether the monitoring circuit  20  operates normally based on at least one value VAL obtained during the test mode, and may generate the verify signal VFY according to determination. For example, in some embodiments, the controller  33  may determine whether the monitoring circuit  20  operates normally, based on a ratio between a value VAL associated with a duration during which the first control signal CTR 1  is activated. 
     In some embodiments, the controller  33  may include a state machine including a plurality of logic gates and may also include a processor and a memory that stores instructions to be executed by the processor. 
       FIGS. 4A and 4B  are circuit diagrams respectively illustrating examples of ramp generators  40   a  and  40   b  according to embodiments of the inventive concept. That is,  FIG. 4A  is a circuit diagram illustrating the ramp generator  40   a  that generates a gradually increasing ramp voltage V RMP , and  FIG. 4B  is the circuit diagram illustrating the ramp generator  40   b  that generates a gradually decreasing ramp voltage V RMP . 
     Referring to  FIG. 4A , the ramp generator  40   a  may include a current source CS 4   a , a switch SW 4   a , and a capacitor C 4   a . The current source CS 4   a  may provide a constant current from a positive supply voltage VDD to a first node N 1   a . The switch SW 4   a  and the capacitor C 4   a  may be connected in parallel between the first node N 1   a  and a ground node. The switch SW 4   a  may be turned on or off according to the first control signal CTR 1 . In some embodiments, the switch SW 4   a  may include a transistor that is controlled by the first control signal CTR 1 . For example, the switch SW 4   a  may be turned off in response to the activated first control signal CTR 1  and may be turned on in response to the inactivated first control signal CTR 1 . Therefore, the current provided by the current source CS 4   a  in the normal mode may flow through the switch SW 4   a  to the ground node, and the voltage of the first node N 1   a , that is, the ramp voltage V RMP , may be approximately same with the ground potential. The current provided by the current source CS 4   a  in the test mode may be provided to the capacitor C 4   a . As the capacitor C 4   a  is charged, the ramp voltage V RMP  may gradually increase from the ground potential. In the test mode, the slope of the ramp voltage V RMP  may depend on the current provided by the current source CS 4   a  and the capacitance of the capacitor C 4   a.    
     Referring to  FIG. 4B , the ramp generator  40   b  may include a current source CS 4   b , a switch SW 4   b , and a capacitor C 4   b . The current source CS 4   b  and the capacitor C 4   b  may be connected in parallel between a first node N 1   b  and a ground node. The current source CS 4   b  may drain a constant current from the first node N 1   b  to the ground node. The switch SW 4   b  may selectively apply a positive supply voltage VDD to the first node N 1   b  according to the first control signal CTR 1 . For example, the switch SW 4   b  may be turned off in response to the activated first control signal CTR 1  and may be turned on in response to the inactivated first control signal CTR 1 . Therefore, in the normal mode, the current source CS 4   b  may drain a current from the positive supply voltage VDD, and the voltage of the first node N 1   b , that is, the ramp voltage V RMP , may be approximately same with the positive supply voltage VDD. In the test mode, the current source CS 4   b  may drain a current from the capacitor C 4   b . As the capacitor C 4   b  is discharged, the ramp voltage V RMP  p may gradually decrease from the positive supply voltage VDD. In the test mode, the slope of the ramp voltage V RMP  may depend on the current drained by the current source CS 4   b  and the capacitance of the capacitor C 4   b.    
     As described above with reference to  FIGS. 4A and 4B , the ramp generators  40   a  and  40   b  have relatively simple structures and may, therefore, occupy a relatively small area. Also, the first control signal CTR 1  provided so as to generate the ramp voltage V RMP  may be a single-bit signal. Therefore, signal routing between the ramp generators  40   a  and  40   b  and the controller  33  of  FIG. 3  may be minimal. Accordingly, the ramp generator  40   a  or  40   b  and the test circuit  30  including the same may be implemented in a small area, and the overhead associated with BIST may be significantly reduced. 
     In the description that follows, it is assumed that the ramp generator generates the gradually increasing ramp voltage V RMP  like the ramp generator  40   a  of  FIG. 4A . 
       FIG. 5  is a timing diagram illustrating example signal relationships during operation of the test circuit  30  of  FIG. 3  used to test the monitoring circuit  20  of  FIG. 2  according to an embodiment of the inventive concept. 
     Referring to  FIGS. 2, 3 and 5 , the object voltage V OBJ  may be required to fall within a range ‘R 0 ’ between the first reference voltage V REF1  and the second reference voltage V REF2 . In order to monitor the object voltage V OBJ , the monitoring circuit  20  may use the first reference voltage V REF1  (which may be defined according to a lower limit range R 1 ) to set a lower limit, and may use the second reference voltage V REF2  (which may be defined by an upper limit range R 2 ) to set an upper limit. Accordingly, the test circuit  30  may test the monitoring circuit  20  by determining whether the object voltage V OBJ  crosses (or exceeds) the first reference voltage V REF1  (i.e., the lower limit range R 1  and/or the second reference voltages V REF2  (i.e., the upper limit range R 2 ). 
     For example, at time t 11 , the controller  33  may activate the first control signal CTR 1 . Therefore, the ramp generator  31  begins generating the gradually increasing ramp voltage V RMP  and the counter  35  starts counting. So long as the ramp voltage V RMP  falls to cross (or exceed) the first reference voltage V REF1  (i.e., the lower limit range R 1 ), both the first and second output signals OUT 1  and OUT 2  of the first and second comparators  21  and  22  remain activated. 
     However, when the ramp voltage V RMP  exceeds the first reference voltage V REF1 , the first output signal OUT 1  is inactivated and the first register REG 1  stores a first value VAL 1  as the value of the count signal CNT. In certain embodiments of the inventive concept like the one illustrated in  FIG. 5 , the ramp signal V RMP  “exceeds” (or “crosses) the first reference voltage V REF1  in a gradual manner in relation to a defined limit range, rather than a discrete manner. Thus, at time t 12  the ramp signal V RMP  enters the lower limit range R. At time t 13 , the ramp signal V RMP  equals the first reference voltage V REF1 , and at time t 14  the ramp signal V RMP  exits the lower limit range R 1 . 
     When the ramp voltage V RMP  crosses the first reference voltage V REF1  at time t 13 , the first output signal OUT 1  may be inactivated and the first register REG 1  may store a first value VAL 1  as the value of the count signal CNT. 
     In a similar manner, the ramp voltage V RMP  may enter the upper limit range R 2  at time t 15 , cross the second reference voltage V REF2  at time t 16 , and exit the upper limit range R 2  at time t 17 . When the ramp voltage V RMP  crosses the second reference voltage VREG 2  at time t 16 , the second output signal OUT 2  may be inactivated and the second register REG 2  may store a second value VAL 2  as the value of the count signal CNT. 
     Assuming that the counter  35  is an up-counter, the second value VAL 2  will be greater than the first value VAL 1  (i.e., VAL 2 &gt;VAL 1 ). 
     At time t 18 , the controller  33  may inactivate the first control signal CTR 1 . In some embodiments, the controller  33  may receive the count signal CNT from the counter  35  and inactivate the first control signal CTR 1  based on a value of the count signal CNT. In some embodiments, the controller  33  may inactivate the first control signal CTR 1  based on a change in the first output signal OUT 1  and/or the second output signal OUT 2  after the first control signal CTR 1  is activated. Due to the inactivated first control signal CTR 1 , the ramp generator  31  may stop generating the gradually increasing ramp voltage V RMP  and the counter  35  may stop counting and be reset. In some embodiments, the counter  35  may maintain the value of the count signal CNT at time t 18 . 
     The controller  33  may estimate the duration of a first period PER 1  based on the first value VAL 1  stored in the first register REG 1 , and may estimate the duration of the second period PER 2  based on the second value VAL 2  stored in the second register REG 2 . Thus, if the first reference voltage V REF1  is defined according to the lower limit range R 1 , the duration of the first period PER 1  will also be defined according to the lower limit range R. Similarly, when the second reference voltage V REF2  is defined according to the upper limit range R 2 , the duration of the second period PER 2  will also be defined according to the upper limit range R 2 . The controller  33  may determine whether the first reference voltage V REF1  belongs to the lower limit range R 1  based on a ratio of the first period PER 1  to the test period PER 0 . For example, the controller  33  may verify the operation of the monitoring circuit  20  based on the lower limit range R 1  using the following Equation 1: 
     
       
         
           
             
               
                 
                   
                     
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                   ] 
                 
               
             
           
         
       
     
     Here, PER 1  and PER 0  indicate the duration of the first period PER 1  and the duration of the test period PER 0 , respectively. The first reference value REF and a positive margin ‘a’ may be predefined based on the lower limit range R. Similarly, the controller  33  may determine whether the second reference voltage V REF2  belongs to the upper limit range R 2  based on a ratio of the second period PER 2  to the test period PER 0 . For example, the controller  33  may verify the operation of the monitoring circuit  20  based on the upper limit range using the following Equation 2: 
     
       
         
           
             
               
                 
                   
                     
                       REF 
                        
                       
                           
                       
                        
                       2 
                     
                     - 
                     β 
                   
                   &lt; 
                   
                     
                       PER 
                        
                       
                           
                       
                        
                       2 
                     
                     
                       PER 
                        
                       
                           
                       
                        
                       0 
                     
                   
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                       REF 
                        
                       
                           
                       
                        
                       2 
                     
                     + 
                     β 
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
                      
                     2 
                   
                   ] 
                 
               
             
           
         
       
     
     Here, PER 2  indicates the duration of the second period PER 2 , and a second reference value REF 2  and a positive margin ‘β’ may be predefined based on the upper limit range R 2 . When both Equation 1 and Equation 2 are satisfied, the controller  33  may determine that the monitoring circuit  20  is operating normally, and may generate a verify signal VFY accordingly. In some embodiments, a in Equation 1 and β in [Equation 2] may be same with each other. Also, in some embodiments, the controller  33  may include a memory (e.g., non-volatile memory such as flash memory) that stores the first reference values REF and α from Equation 1 as well as second reference values REF 2  and β from Equation 2, or may access the memory, and may update at least one of the first reference value REF 1 , the second reference value REF 2 , α, and β stored in the memory in response to an external signal. 
       FIG. 6  is a block diagram further illustrating another example of the test circuit  16  of  FIG. 1  according to an embodiment of the inventive concept. That is, the block diagram of  FIG. 6  illustrates a test circuit  60  including a controller  63  that receives an end signal END from a ramp generator  61 . Similar to the test circuit  30  of  FIG. 3 , the test circuit  60  may include the ramp generator  61 , the controller  63 , a counter  65 , and a register set  67 . 
     Referring to  FIGS. 1, 3, 5 and 6  the ramp generator  61  may generate the end signal END in response to the ramp voltage V RMP . In some embodiments, the ramp generator  61  may generate the activated end signal END when the ramp voltage V RMP  generated to increase gradually in response to an activated first control signal CTR 1  reaches a predefined upper level. In this case, the upper level may be higher than the upper limit range R 2  and the second reference voltage V REF2 . Therefore, when the end signal END is activated, the ramp voltage V RMP  may have been crossed with both the first reference voltage V REF1  and the second reference voltage V REF2 . 
     Similar to the test circuit  30  of  FIG. 3 , the register set  67  may include first and second registers REG 1  and REG 2  and may further include a reference register REG 0 . The reference register REG 0  may store a value of a count signal CNT when a test period is ended. For example, as illustrated in  FIG. 6 , the register set  67  may receive the end signal END from the ramp generator  61 , and the reference register REG 0  may store the value of the count signal when the end signal END is activated. 
     The controller  63  may generate the verify signal VFY based on the values stored in the reference register REG 0 , as well as the values stored in the first and second registers REG 1  and REG 2  included in the register set  67 . For example, the controller  63  may recognize the duration of the test period PER 0  based on the value stored in the reference register REG 0  and may verify the operation of the monitoring circuit  20  based (e.g.,) the relationships described by [Equation 1] and [Equation 2]. In some embodiments, the controller  63  may receive the end signal END from the ramp generator  61  and inactivate the first control signal CTR 1  in response to the activated end signal END. Also, in some embodiments, instead of the register set  67  directly receiving the end signal END, unlike in  FIG. 6 , the controller  63  may receive the end signal END and the register set  67  may store the value of the count signal CNT under the control of the controller  63 . 
       FIG. 7  is a block diagram illustrating a test circuit  70  according to an embodiment of the inventive concept, and  FIG. 8  is a timing diagram further illustrating the operation of the test circuit  70  according to an embodiment of the inventive concept. 
     Here, the test circuit  70  may include a controller  73  that further generates a second control signal CTR 2  provided to a ramp generator  71 . The timing diagram of  FIG. 8  illustrates the operation of the test circuit  70  that tests the monitoring circuit  20  of  FIG. 2 . 
     Referring to  FIGS. 2, 7 and 8  (and similar to the test circuit  30  of  FIG. 3 ), the test circuit  70  may include the ramp generator  71 , the controller  73 , a counter  75 , and a register set  77 . The ramp generator  71  may generate a ramp voltage V RMP  in response to an activated first control signal CTR 1  and may adjust a slope of the ramp voltage V RMP  based on the second control signal CTR 2 . In some embodiments, when the ramp generator  71  includes the same elements as those of the ramp generator  40   a  of  FIG. 4A , the current source CS 4   a  may receive the second control signal CTR 2  and may adjust the magnitude of a current provided from the positive supply voltage VDD to the first node N 1   a  based on the second control signal CTR 2 . Therefore, in the test mode, the slope of the ramp voltage V RMP  may decrease when the current provided by the current source CS 4   a  decreases and may increase when the current provided by the current source CS 4   a  increases. Also, in some embodiments, the capacitor C 4   a  may have a variable capacitance according to the second control signal CTR 2 . In the example of  FIG. 8  to be described below, it is assumed that the ramp generator  71  decreases the slope of the ramp voltage V RMP  in response to the activated second control signal CTR 2 . 
     The controller  73  may adjust testing resolution for the monitoring circuit  20  using the second control signal CTR 2 . That is, when the slope of the ramp voltage V RMP  is relatively small, more clock signal pulses may be generated in a given voltage range. Therefore, relatively high resolution testing may be achieved. However, in order to reduce the time required for the BIST performed by the test circuit  70 , the controller  73  may adjust (i.e., decrease) the slope of the ramp voltage V RMP  in at least part of the entire test period PER 0  (e.g., CAN 1  and CAN 2  in  FIG. 8 ). As illustrated in  FIG. 7 , the controller  73  may determine a period in which the slope of the ramp voltage V RMP  is adjusted, based on the count signal CNT received from the counter  75 . 
     In some embodiments, the controller  73  may generate the second control signal CTR 2  such that the slope of the ramp voltage V RMP  decreases in a candidate period (e.g., CAN 1  and CAN 2  of  FIG. 8 ) including a time at which a change in the first output signal OUT 1  and/or the second output signal OUT 2  is expected. That is, in order to achieve higher resolution around time(s) at which the ramp voltage V RMP  crosses the lower limit or the upper limit, the controller  73  may decrease the slope of the ramp voltage V RMP  during candidate period(s). Therefore, the test circuit  70  may perform the verification of the ramp voltage V RMP , that is, the test of the monitoring circuit  20 , with higher resolution while minimizing an increase in the overall test period. 
     Referring to  FIG. 8 , at time t 21 , the controller  73  may activate the first control signal CTR 1 . Therefore, the ramp generator  31  may generate the gradually increasing ramp voltage V RMP  and the counter  75  may start counting. The controller  73  may generate the inactivated second control signal CTR 2 , and accordingly, the ramp generator  71  may generate the ramp voltage V RMP  increasing at a second slope. 
     At time t 22 , the controller  73  may activate the second control signal CTR 2 . At time t 23 , the ramp voltage V RMP  may cross the lower limit (i.e., the first reference voltage V REF1 . At time t 24 , the controller  73  may inactivate the second control signal CTR 2 . Therefore, the ramp voltage V RMP  may increase at a low slope (i.e., the first slope) before crossing the first reference voltage V REF1  or before entering the lower limit range R 1  and may increase again at an high slope (i.e., the second slope) after crossing the first reference voltage V REF1 , or after exiting from the lower limit range R. As illustrated in  FIG. 8 , a period in which the slope of the ramp voltage V RMP  decreases corresponding to the first reference voltage V REF1  or the lower limit range R 1  may be referred to as a first candidate period CAN 1 . The first period PER 1  may end within the first candidate period CAN 1 . 
     At time t 25 , the controller  73  may again activate the second control signal CTR 2 . At time t 26 , the ramp voltage V RMP  may cross the upper limit (i.e., the second reference voltage V REF2 ). At time t 27 , the controller  73  may inactivate the second control signal CTR 2 . Therefore, the ramp voltage V RMP  may increase at a low slope before crossing the second reference voltage V REF2  or before entering the upper limit range R 2  and may increase again at an high slope after crossing the upper limit (i.e., the second reference voltage V REF2 ), or after exiting from the upper limit range R 2 . As illustrated in  FIG. 8 , a period in which the slope of the ramp voltage V RMP  decreases corresponding to the second reference voltage V REF2  or the upper limit range R 2  may be referred to as a second candidate period CAN 2 . The second period PER 2  may end within the second candidate period CAN 2 . 
     At time t 28 , the controller  73  may inactivate the first control signal CTR 1 . Therefore, the ramp generator  71  may stop generating the increasing ramp voltage V RMP , and the counter  75  may stop counting. As described above with reference to  FIG. 5 , the controller  73  may test the monitoring circuit  20  based on a ratio of the first period PER 1  to the test period PER 0  and a ratio of the second period PER 2  to the test period PER 0 . 
       FIG. 9  is a timing diagram illustrating another example of the operation of the test circuit  70  according to an embodiment of the inventive concept. Here, the timing diagram of  FIG. 9  illustrates an example of the operation of the test circuit  70  of  FIG. 7  that tests the monitoring circuit  20  of  FIG. 2 . 
     Referring to  FIGS. 2, 7 and 9 , the controller  73  may adjust the slope of the ramp voltage V RMP  so as to adjust the test period PER 0 . For example, the controller  73  may obtain information about the time allowed for testing of the monitoring circuit  20  and may determine the test period PER 0  based on the information. In some embodiments, the test period PER 0  for the monitoring circuit  20  immediately after power is supplied to the test circuit  70  may be relatively long, and the test period PER 0  used during the operation of the test circuit  70  (e.g., in an idle period or periodically) may be relatively short. The controller  73  may adjust the slope of the ramp voltage V RMP  through the second control signal CTR 2  so that the test of the monitoring circuit  20  is completed within the determined test period PER 0 . 
     Referring to  FIG. 9 , as illustrated by a ramp voltage V RMP1 , when a longest test period PER 01  is allowed, the controller  73  may generate the first control signal CTR 1  activated between time t 31  and time t 34  and may generate the second control signal CTR 2  corresponding to a lowest slope. Also, as illustrated by the ramp voltage V RMP2 , when a test period PER 02  having an intermediate duration is allowed, the controller  73  may generate the first control signal CTR 1  activated between time t 31  and time t 33 , the ramp voltage V RMP2  may generate the first control signal CTR 1  activated between time t 31  and time t 33 , and the controller  73  may generate the second control signal CTR 2  corresponding to an intermediate slope. Also, as illustrated by a ramp voltage V RMP3 , when a shortest test period PER 03  is allowed, the controller  73  may generate the first control signal CTR 1  activated between time t 31  and time t 32  and may generate the second control signal CTR 2  corresponding to a highest slope. In some embodiments, unlike in  FIG. 9 , the ramp generator  71  may support four or more or two or less different slopes of the ramp voltage V RMP , and the controller  73  may select the supported slopes of the ramp voltage V RMP  through the second control signal CTR 2 . 
       FIG. 10  is a block diagram illustrating a test circuit  100  according to an embodiment of the inventive concept, and  FIG. 11  is a timing diagram illustrating the operation of the test circuit  100  according to an embodiment of the inventive concept. Here, the test circuit  100  may include a controller  103  that controls a clock generator  109 . 
     Referring to  FIGS. 2, 10 and 11  (and similar to the test circuit  30  of  FIG. 3 ), the test circuit  100  may include a ramp generator  101 , the controller  103 , a counter  105 , and a register set  107  and may further include the clock generator  109 . The clock generator  109  may provide a clock signal CLK to the counter  105 , and the counter  105  may count pulses of the clock signal CLK. Although not illustrated in  FIG. 3 , the test circuit  30  of  FIG. 3  may further include a clock generator providing the clock signal CLK to the counter  35 . The clock generator  109  may receive a third control signal CTR 3  from the controller  103  and may adjust a frequency of the clock signal CLK based on the third control signal CTR 3 . In some embodiments, the clock generator  109  may receive a first control signal CTR 1  and generate the clock signal CLK in response to the activated first control signal CTR 1 . Hereinafter, in the example of  FIG. 11 , it is assumed that the clock generator  109  increases the frequency of the clock signal CLK in response to the activated third control signal CTR 3 . 
     The controller  103  may adjust the testing resolution for the monitoring circuit  20  through the third control signal CTR 3 . That is, as a counting speed of the counter  105  increases at a given time, higher resolution may be achieved. However, in order to reduce power consumption caused by clock signal CLK transitions, the controller  73  may adjust (e.g., increase) the frequency of the clock signal CLK during at least part of the entire test period PER 0  (e.g., CAN 1  and CAN 2  in  FIG. 11 ). As illustrated in  FIG. 10 , the controller  103  may receive a count signal CNT from the counter  105  and may determine a period for adjusting the frequency of the clock signal CLK based on the count signal CNT. 
     Referring to  FIG. 11  (similar to the example of  FIG. 8 ), the controller  103  may generate the third control signal CTR 3 , so as to increase the frequency of the clock signal CLK, during candidate periods CAN 1  and CAN 2  that overlap a time at which a change in a first output signal OUT 1  and/or a second output signal OUT 2  is expected. At time t 41 , the controller  103  may activate the first control signal CTR 1 . Therefore, the ramp generator  101  may generate a gradually increasing ramp voltage V RMP  and the counter  105  may start counting. The controller  103  may generate the inactivated third control signal CTR 3 . Therefore, the clock generator  109  may generate the clock signal CLK oscillating at a second frequency. 
     At time t 42 , the controller  103  may activate the third control signal CTR 3 . At time t 43 , the ramp voltage V RMP  may cross a first reference voltage V REF1 . At time t 44 , the controller  103  may inactivate the third control signal CTR 3  again. Therefore, the clock signal CLK may have an increased frequency (which may be referred to as a first frequency herein) before the ramp voltage V RMP  crosses the first reference voltage V REF1  or before the ramp voltage V RMP  enters the first range R 1  and may have a decreased frequency (which may be referred to as a second frequency herein) after the ramp voltage V RMP  crosses the first reference voltage V REF1  or after the ramp voltage V RMP  deviates from the first range R 1 . That is, the frequency of the clock signal CLK may be increased in the first candidate period CAN 1 , and the value of the count signal CNT may be increased at a faster rate. 
     At time t 45 , the controller  103  may activate the third control signal CTR 3 . At time t 46 , the ramp voltage V RMP  may cross a second reference voltage V REF2 . At time t 47 , the controller  103  may inactivate the third control signal CTR 3  again. Therefore, the clock signal CLK may have an increased frequency before the ramp voltage V RMP  crosses the second reference voltage V REF2  or before the ramp voltage V RMP  enters the second range R 2  and may have a decreased frequency after the ramp voltage V RMP  crosses the second reference voltage V REF2  or after the ramp voltage V RMP  deviates from the second range R 2 . That is, the frequency of the clock signal CLK may be increased in the second candidate period CAN 2 , and the value of the count signal CNT may be increased at a faster rate. 
     At time t 48 , the controller  103  may inactivate the first control signal CTR 1 . Therefore, the ramp generator  101  may stop generating the increasing ramp voltage V RMP  and the counter  105  may stop counting. As described above with reference to  FIG. 5 , the controller  103  may test the monitoring circuit  20  based on a ratio of the first period PER 1  to the test period PER 0  and a ratio of the second period PER 2  to the test period PER 0 . 
       FIG. 12  is a block diagram illustrating an example of a monitoring circuit  120  according to an embodiment of the inventive concept.  FIG. 13  is a block diagram illustrating an example of a test circuit  130  according to an embodiment of the inventive concept. 
     Here,  FIG. 12  illustrates the monitoring circuit  120  including multiple comparators (e.g., first, second, and third comparators  121 ,  122 , and  123 ) and  FIG. 13  illustrates the test circuit  130  that tests the monitoring circuit  120 . 
     Referring to  FIG. 12  (similar to the monitoring circuit  20  of  FIG. 2 ), the monitoring circuit  120  may include a switch circuit  125  and the first and second comparators  121  and  122  and may further include the third comparator  123 . The first and second comparators  121  and  122  may receive first and second reference voltages V REF1  and V REF2  corresponding to lower and upper limits, respectively. The third comparator  123  may receive a third reference voltage V REF3  that is lower than the first reference voltage V REF1  corresponding to the lower limit. For example, the main circuit  12  of  FIG. 1  may be a DC-DC converter, and the object voltage V OBJ  may provide power to electrical components as a supply voltage. Serious problems may be caused when a current path is formed between the object voltage V OW  and the ground potential due to a failure of at least one of the electrical components supplied with power from the object voltage V OBJ . The monitoring circuit  120  may include the third comparator  123  that receives a third reference voltage V REF3  so as to detect a short circuit event and whether the main circuit  12  operates normally. Therefore, when a short circuit event occurs, a third output signal OUT 3  included in an output signal OUT may transition to a low level. 
     Referring to  FIG. 13  (similar to the test circuit  30  of  FIG. 3 ), the test circuit  130  may include a ramp generator  131 , a controller  133 , a counter  135 , and a register set  137 . Compared with the register set  37  of  FIG. 3 , the register set  137  of  FIG. 13  may further include a third register REG 3 . The third register REG 3  may store the value of the count signal CNT when the output signal OUT corresponding to a short circuit is changed. For example, similar to [Equation 1] and [Equation 2], the controller  133  may verify the operation of the monitoring circuit  20  in relation to a potential short circuit with reference to the following [Equation 3]: 
     
       
         
           
             
               
                 
                   
                     
                       REF 
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                       3 
                     
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                       PER 
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                       3 
                     
                     
                       PER 
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                       0 
                     
                   
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                       REF 
                        
                       
                           
                       
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                       3 
                     
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                     γ 
                   
                 
               
               
                 
                   [ 
                   
                     Equation 
                      
                     
                         
                     
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                     3 
                   
                   ] 
                 
               
             
           
         
       
     
     In [Equation 3], PER 3  indicates the duration of the third period, that is, the period from the start of the test period REG 0  to the time at which the ramp voltage V RMP  crosses the third reference voltage V REF3 , and a third reference value REF 3  and a positive margin ‘y’ may be predefined based on an allowable range including the third reference voltage V REF3 . 
       FIG. 14  is a block diagram illustrating an example of an electrical system  140  according to an embodiment of the inventive concept.  FIG. 15  is a timing diagram illustrating an example of the operation of the electrical system  140  according to an embodiment of the inventive concept. Here, the block diagram of  FIG. 14  illustrates the electrical system  140  including a voltage generator  142  as a main circuit, and  FIG. 15  illustrates an operation of a monitoring circuit  144  for the voltage generator  142  and an operation of a test circuit  146  for the monitoring circuit  144 . It is assumed that the monitoring circuit  144  of  FIG. 14  has the same structure as that of the monitoring circuit  20  of  FIG. 2 . 
     Referring to  FIG. 14 , the voltage generator  142  may generate an output voltage V OUT  from an input voltage V IN , where the output voltage V OUT  is required to have a particular level. The monitoring circuit  144  may receive the output voltage V OUT  from the voltage generator  142  and may receive the ramp voltage V RMP  and the mode signal MD from the test circuit  146 . In some embodiments (similar to the description above with reference to  FIG. 3 ), the mode signal MD may be same with a first control signal CTR 1 . Also, the monitoring circuit  144  may generate the output signal OUT and provide the output signal OUT to a system controller  148 . The test circuit  146  may receive the output signal OUT from the monitoring circuit  144 , generate a verify signal VFY, and provide the verify signal VFY to the system controller  148 . 
     The system controller  148  may recognize the state of the voltage generator  142  and the state of the monitoring circuit  144  based on the output signal OUT and the verify signal VFY. The system controller  148  may output a signal indicating the state of the electrical system  140  to the outside of the electrical system  140 , based on the output signal OUT and the verify signal VFY, and may control at least one of the voltage generator  142 , the monitoring circuit  144 , and the test circuit  146 . For example, when the voltage generator  142  and/or the monitoring circuit  144  does not operate normally, the system controller  148  may stop the operation of the voltage generator  142 . Also, the system controller  148  may instruct the test circuit  146  to test the monitoring circuit  144 . 
     Referring to  FIG. 15 , as power is supplied to the electrical system  140  or a system including the electrical system  140 , the input voltage V IN  may reach a satisfactory level at time t 51 . The system controller  148  may instruct the test circuit  146  to test the monitoring circuit  144 , and the voltage generator  142  may not start generating the output voltage V OUT . The test circuit  146  may set the monitoring circuit  144  to a test mode by enabling the mode signal MD and generate an increasing ramp voltage V RMP . Between time t 51  and time t 52 , the ramp voltage V RMP  may pass through a desirable range R 0  of the output voltage V OUT . Therefore, first and second output signals OUT 1  and OUT 2  may transition. At time t 52 , the test circuit  146  may determine whether the monitoring circuit  144  operates normally, based on changes in the first and second output signals OUT 1  and OUT 2 , and may inactivate the mode signal MD. As the test circuit  146  determines that the monitoring circuit  144  operates normally, the test circuit  146  may generate the inactivated verify signal VFY. 
     At time t 53 , even though the input voltage V IN  maintains a constant level, the voltage generator  152  may stop generating the output voltage V OUT . For example, the system controller  158  may enter a low power mode. In this case, the system controller  158  may turn off the voltage generator  142 . Therefore, the output voltage V OUT  may decrease from time t 53 . At time t 54 , the system controller  158  may instruct the test circuit  146  to test the monitoring circuit  144 , for example, before turning on the voltage generator  142  so as to release the low power mode. The test circuit  146  may set the monitoring circuit  144  to the test mode through the mode signal MD and may generate the increasing ramp voltage V RMP  p. 
     Between time t 54  and time t 55 , the ramp voltage V M p may pass through the desirable range R 0  of the output voltage V OUT . Therefore, the first and second output signals OUT 1  and OUT 2  may transition. As illustrated in  FIG. 15 , unlike between time t 51  and time t 52 , a second period PER 2 ′ measured between time t 54  and time t 55  may be short. Therefore, the test circuit  146  may determine that there is an error in the operation of the monitoring circuit  14  based on the upper limit. Therefore, at time t 55 , the test circuit  146  may generate the inactivated verify signal VFY and inactivate the mode signal MD. 
     Between time t 56  and time t 57 , the test circuit  146  may test the monitoring circuit  144 . At time t 57 , when the test circuit  146  determines that the monitoring circuit  144  operates normally, the test circuit  146  may generate the activated verify signal VFY. At time t 58 , the output voltage V OUT  may deviate from the range R 0  due to an unspecified cause. Therefore, the monitoring circuit  144  may notify the system controller  148  of the abnormal operation of the voltage generator  142  by disabling the second output signal OUT 2 . 
       FIG. 16  is a flowchart summarizing a method of testing a monitoring circuit according to an embodiment of the inventive concept. In some embodiments, the method of  FIG. 16  may be performed using the test circuit  30  of  FIG. 3 . 
     Referring to  FIGS. 2, 3 and 16 , the clock signal may be generated (S 10 ). For example, the test circuit  30  may include the clock generator (e.g.,  109  of  FIG. 10 ). The clock generator may generate the clock signal and provide the clock signal to the counter  35 . The ramp signal RMP may be generated (S 30 ). For example, the ramp generator  31  may generate the ramp voltage V RMP  as the ramp signal RMP in response to the activated first control signal CTR 1 . Pulses of the clock signal may be counted (S 50 ). For example, the counter  35  may count the pulses of the clock signal in response to the activated first control signal CTR 1  and output the count signal CNT. The count value may be recorded based on the output signal OUT of the monitoring circuit  20  (S 70 ). For example, the register set  37  may receive the output signal OUT, and the first and second registers REG 1  and REG 2  may store the value of the count signal CNT according to changes in the output signal OUT corresponding to the lower limit and upper limit. The operation of the monitoring circuit  20  may be verified (S 90 ). For example, the controller  33  may end the test period by disabling the first control signal CTR 1  and may determine whether the monitoring circuit (e.g.,  20  of  FIG. 2 ) operates normally, based on the duration of the test period and the ratios between the values stored in the register set  37 . The controller  33  may generate the verify signal VFY corresponding to a result of the determining. 
       FIGS. 17A and 17B  are flowcharts further summarizing examples of operation S 10  of the method of  FIG. 16  according to embodiments of the inventive concept. As described above with reference to  FIG. 16 , in operations S 10   a  and S 10   b  of  FIGS. 17A and 17B , the clock signal CLK may be generated. In some embodiments, operations S 10   a  and S 10   b  of  FIGS. 17A and 17B  may be performed by the test circuit  100  of  FIG. 10 .  FIGS. 17A and 17B  will be described below with reference to  FIG. 10 . 
     Referring to  FIG. 17A , operation S 10   a  may include a plurality of operations S 11  to S 14 . A clock signal CLK having a second frequency may be generated (S 11 ). For example, the controller  103  may set the frequency of the clock signal CLK to the relatively low second frequency through the third control signal CTR 3 . A determination is made as to whether the candidate period has begun (S 12 ). For example, the controller  103  may determine whether the candidate period begins, based on the count signal CNT. As illustrated in  FIG. 17A , when the candidate period does not begins, operation S 11  may be repeated. When the candidate period begins, the clock signal CLK of a first frequency may be generated (S 13 ). For example, the controller  103  may set the frequency of the clock signal CLK to the first frequency higher than the second frequency through the third control signal CTR 3  in the candidate period. A determination is made as to whether the candidate period is finished (S 14 ). For example, the controller  103  may determine whether the candidate period finishes, based on the count signal CNT. As illustrated in  FIG. 17A , when the candidate period does not finish, operation S 13  may be repeated. When the candidate period finishes, the frequency of the clock signal CLK may be set again to the second frequency in operation S 11 . 
     Referring to  FIG. 17B , operation S 10   b  may include operations S 15  and S 16 . Initially, resolution information may be obtained (S 15 ). For example, the controller  103  may receive a signal including resolution information required for testing the monitoring circuit (e.g.,  20  of  FIG. 2 ) from an external and/or internal component (e.g.,  148  of  FIG. 14 ). The frequency of the clock signal CLK may then be adjusted (S 16 ). For example, when the resolution information obtained in operation S 15  corresponds to high resolution, the controller  103  may increase the frequency of the clock signal CLK, and when the resolution information obtained in operation S 15  corresponds to low resolution, the controller  103  may decrease the frequency of the clock signal CLK. 
       FIGS. 18A and 18B  are flowcharts further summarizing examples of operation S 30  of  FIG. 16  according to embodiments of the inventive concept. As described above with reference to  FIG. 16 , in operations S 30   a  and S 30   b  of  FIGS. 18A and 18B , the ramp signal may be generated. In some embodiments, operations S 30   a  and S 30   b  of  FIGS. 18A and 18B  may be performed by the test circuit  70  of  FIG. 7 .  FIGS. 18A and 18B  will be described below with reference to  FIG. 7 . 
     Referring to  FIG. 18A , operation S 30   a  may include generating the ramp signal of (or having) a second slope (S 31 ). For example, the controller  73  may set the slope of the ramp voltage V RMP  to the relatively high second slope using the second control signal CTR 2 . Next, a determination is made as to whether a candidate period has begun (S 32 ). For example, the controller  73  may determine whether the candidate period begins based on the count signal CNT. As illustrated in  FIG. 18A , if the candidate period does not begin (S 32 =NO), then operation S 31  may be repeated. However, when the candidate period begins (S 32 =YES), the ramp signal of a first slope is generated (S 33 ). For example, the controller  73  may set the slope of the ramp voltage V RMP  to the first slope lower than the second slope using the second control signal CTR 2  during the candidate period. Next, a determination is made as to whether the candidate period is finished (S 34 ). For example, the controller  73  may determine whether the candidate period is finished based on the count signal CNT. As illustrated in  FIG. 18A , if the candidate period is not finished (S 34 =NO), operation S 33  may be repeated. However, when the candidate period is finished (S 34 =YES, the slope of the ramp signal may again be set to the second slope (S 31 ). 
     Referring to  FIG. 18B , operation S 30   b  may include; obtaining allowable time information (S 35 ); and adjusting the slope of the ramp signal (S 36 ). For example, the controller  73  may receive a signal indicating allowable time information for testing by the monitoring circuit (e.g.,  20  of  FIG. 2 ) from an external or internal component (e.g.,  148  of  FIG. 14 ). Thereafter, the controller  73  may decrease the slope of the ramp signal when the allowable time information indicates a long time, or increase the slope of the ramp signal when the allowable time information indicates a short time. 
       FIG. 19  is a flowchart further illustrating an example of operation S 90  of  FIG. 16  according to an embodiment of the inventive concept. As described above with reference to  FIG. 16 , the operation of the monitoring circuit may be verified in operation S 90 ′ of  FIG. 19 . In some embodiments, operation S 90 ′ may be performed by the test circuit  30  of  FIG. 3 . 
     Referring to  FIGS. 1, 3, 5 and 19 , a reference range may be updated (S 92 ). The reference range may include the lower limit range R 1  and/or the upper limit range R 2  for the object signal OBJ. The controller  33  may modify one of the these ranges based on a signal received from an external source. A determination is made as to whether a calculated ratio satisfies the reference range (S 94 ). For example, the controller  33  may calculate the ratio between the values stored in the register set  37  with respect to the entire test period and may determine whether the calculated ratio satisfies the reference range or a range obtained by modifying the reference range (e.g., ranges defined by [Equation 1], [Equation 2], and [Equation 3]). In some embodiments, the controller  33  may calculate a plurality of ratios and may determine whether the plurality of ratios respectively satisfy a plurality of reference ranges. When the calculated ratio satisfies the reference range (S 94 =YES), the verification of the monitoring circuit (e.g.,  20  of  FIG. 2 ) is deemed successful (S 96 ) and a corresponding (e.g., activated) verify signal VFY is generated. However, if the calculated ratio does not satisfy the reference range (S 94 =NO), the verification of the monitoring circuit (e.g.,  20  of  FIG. 2 ) is deemed a failure and a corresponding (e.g., inactivated) verify signal VFY is generated (S 98 ). 
     While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims.