Patent Publication Number: US-10778406-B2

Title: Synthesized clock synchronization between networks devices

Description:
FIELD OF THE INVENTION 
     The present invention relates to clock synchronization, and in particular relates to clock synchronization in network devices. 
     BACKGROUND 
     Clock synchronization among network devices is used in many network applications. One application of using a synchronized clock value is for measuring latency between two devices. If the clocks are not synchronized the resulting latency measurement will be inaccurate. 
     Synchronous Ethernet (SyncE) is an International Telecommunication Union Telecommunication (ITU-T) Standardization Sector standard for computer networking that facilitates the transference of clock signals over the Ethernet physical layer. In particular, SyncE enables clock synchronization inside a network with respect to a master device clock source or master clock. Each network element (e.g., a switch, a network interface card (NIC), or router) needs to recover the master clock from high-speed data received from the master device clock source and use the recovered master clock for its own data transmission in a manner such that the master clock spreads throughout the network. 
     SUMMARY 
     There is provided in accordance with an embodiment of the present disclosure a network device including frequency generation circuitry configured to generate a clock signal, a phase-locked loop (PLL) configured to generate a local clock based on the clock signal, a plurality of receivers configured to receive respective data streams from respective remote clock sources, each receiver of the plurality of receivers being configured to recover a remote clock from a respective data stream, and a controller configured to identify the remote clock recovered by one of the plurality of receivers as a master clock, find a clock differential between the identified remote clock and the local clock, provide a control signal to the frequency generation circuitry responsively to the clock differential, which causes the frequency generation circuit to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential. 
     Further in accordance with an embodiment of the present disclosure each one receiver of the plurality of receivers is configured to compute a difference between the recovered remote clock of the one receiver and the local clock. 
     Still further in accordance with an embodiment of the present disclosure the frequency generation circuitry includes an oscillator. 
     Additionally, in accordance with an embodiment of the present disclosure the frequency generation circuitry includes a frequency mixer configured to combine the control signal from the controller with an output from the oscillator yielding the clock signal as a combined signal for output towards the PLL. 
     Moreover, in accordance with an embodiment of the present disclosure, the device includes switching circuitry configured to switch between connecting the output of the oscillator to the PLL, and connecting an output of the frequency mixer to the PLL. 
     Further in accordance with an embodiment of the present disclosure the controller is configured to provide a control signal to the switching circuitry to switch to connecting the output of the frequency mixer to the PLL when the absolute value of the clock differential is greater than a given value. 
     Still further in accordance with an embodiment of the present disclosure the switching circuitry includes a multiplexer. 
     Additionally, in accordance with an embodiment of the present disclosure, the device includes a clock clean-up PLL disposed between an output of the frequency mixer and an input of the PLL to remove jitter from the combined signal. 
     Moreover, in accordance with an embodiment of the present disclosure, the device includes a shaper disposed between the controller and the frequency mixer to delay receipt, by the frequency mixer, of the control signal provided by the controller. 
     Further in accordance with an embodiment of the present disclosure the frequency generation circuitry includes a voltage-controlled oscillator. 
     Still further in accordance with an embodiment of the present disclosure the network device includes a network switch or a network router. 
     Additionally, in accordance with an embodiment of the present disclosure, the device includes a first core die and a second core die, the first core die and the second core die being different dies, the first core die including switching circuitry, the second core die including the plurality of receivers. 
     There is also provided in accordance with another embodiment of the present disclosure a clock synchronization method including generating a clock signal, generating a local clock based on the clock signal, receiving a plurality of data streams from respective remote clock sources, recovering a remote clock from each of the plurality of data streams, identifying the remote clock recovered from one of the plurality of data streams as a master clock, finding a clock differential between the identified remote clock and the local clock, and providing a control signal which causes adjustment of the clock signal so as to iteratively reduce an absolute value of the clock differential. 
     Moreover, in accordance with an embodiment of the present disclosure, the method includes, for each of the plurality of data streams, computing a difference between the recovered remote clock and the local clock. 
     Further in accordance with an embodiment of the present disclosure, the method includes combining the control signal with an output from an oscillator yielding the clock signal as a combined signal. 
     Still further in accordance with an embodiment of the present disclosure, the method includes switching between using the output of the oscillator as the clock signal, and using the combined signal as the clock signal. 
     Additionally, in accordance with an embodiment of the present disclosure, the method includes switching to using the combined signal as the clock signal when the absolute value of the clock differential is greater than a given value. 
     Moreover, in accordance with an embodiment of the present disclosure, the method includes removing jitter from the combined signal. 
     Further in accordance with an embodiment of the present disclosure, the method includes delaying receipt of the control signal. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be understood from the following detailed description, taken in conjunction with the drawings in which: 
         FIG. 1  is a schematic block diagram view of a network device constructed and operative in accordance with an embodiment of the present invention; 
         FIG. 2  is a schematic block diagram view of the network device of  FIG. 1  in an initial stage of clock synchronization; 
         FIG. 3  is a schematic block diagram view of the network device of  FIG. 1  in a later stage of clock synchronization; 
         FIG. 4  is a schematic block diagram view of the network device of  FIG. 1  in a final stage of clock synchronization; 
         FIG. 5  is a flow chart including exemplary steps in a method of clock synchronization in the network device of  FIG. 1 ; and 
         FIG. 6  is a schematic block diagram view of a network device constructed and operative in accordance with an alternative embodiment of the present invention. 
     
    
    
     DESCRIPTION OF EXAMPLE EMBODIMENTS 
     Overview 
     A source of a master clock is generally designated by a network management function. As such there may be situations in which the identity of the source of the master clock is currently not known, for example, when a network device is booted or a connection to the source of the master clock is lost. 
     In devices with many ports or lanes, such as high bandwidth switches or routers, the clock used by each port or lane needs to be synchronized with the master clock. As the identity of the source of the master clock may not currently be known, the common practice is to use the recovered clock extracted from a clock recovery circuit within each Serializer/Deserializer (SerDes) receiver of the network device to recover the clocks from the various streams received by ports of the network device. The recovered clocks from the various streams received by the ports are multiplexed throughout the network device to all the ports and lanes of the network device so that once the source of the master clock is designated, the relevant recovered clock value may be used by the ports and lanes of the network device. The recovered clocks may be divided and multiplexed in groups depending on the configuration of the network device. 
     The above synchronization method becomes increasingly complex as the integrated circuits of the network devices become bigger. Buffering the recovered clocks throughout the integrated circuit adds noise to the sensitive circuits and data could be lost. Moreover, in network devices with more than one die, die-to-die clock routing may add unnecessary jitter which could harm the clock quality and require a significant routing effort in the device. 
     In embodiments of the present invention, clock synchronization is achieved without the need to multiplex the recovered clocks of each receiver over the integrated circuit(s) of the network device, thereby simplifying clock synchronization without adding unnecessary noise and jitter in the network device. Additionally, embodiments of the present invention scale for network devices with multiple dies and/or multi-chip modules and any suitable number of ports and lanes. 
     In embodiments described below, the network device includes frequency generation circuitry which generates a clock signal. The frequency generation circuitry may include an oscillator such as a crystal oscillator to generate the clock signal. An on-chip phase-locked loop (PLL) generates a local high-speed clock based on the clock signal. The local clock may be used by all ports and lanes in the network device as a reference clock until a master clock is designated by a network management function. 
     The receivers in the network device receive respective data streams from respective remote clock sources. A clock and data recovery (CDR) process running in each receiver recovers a remote clock from the respective data stream of the respective remote clock source. The CDR may also compute a clock differential between the recovered remote clock and the local clock of the network device. 
     Once the master clock has been designated, a controller identifies the remote clock recovered by one of the receivers (“selected receiver”) as the master clock. The controller typically comprises a programmable processor, which performs the functions described herein under the control of firmware or other software. Additionally, or alternatively, at least some of these functions can be carried out by hardware logic, which may be hard-wired or programmable. The controller also finds the clock differential between the identified remote clock and the local clock, for example, by reading the clock differential from a register written to by the selected receiver that computed the clock differential. In some embodiments, instead of the receivers computing the clock differentials, the controller may compute the clock differential of the selected receiver based on the local high-speed clock of the PLL and the recovered remote clock recovered by the selected receiver. 
     The clock differential of the selected receiver provides an indication of whether the local clock is faster or slower than the master clock and by how much. The difference between the local clock and the master clock may be expressed in any suitable measurement unit, for example, Hz or parts-per-million (PPM). 
     The controller provides a control signal to the frequency generation circuitry to slow down or speed up the clock signal depending on whether the local clock is faster or slower than the master clock. The control signal may also be a function of the magnitude of the clock differential. The resulting change in the clock signal generated by the frequency generation circuitry causes a change in the local clock generated by the PLL. The change in the local clock generated by the PLL in turn causes a change in the clock differential between the local clock generated by the PLL and the recovered remote clock recovered by the selected receiver. 
     The controller adjusts the control signal so as to slow down or speed up the clock signal according to the new clock differential, which provides an indication of whether the local clock is still faster or slower than the master clock and by how much. 
     The above process is repeated so as to iteratively reduce an absolute value of the clock differential, for example until the absolute value of the clock differential is less than a given value. In the above way, the local clock generated by the PLL is synchronized with the master clock. 
     In some embodiments, the frequency generation circuitry includes a frequency mixer which combines an output of the oscillator with the control signal so as to adjust the clock signal. In other embodiments, the frequency generation circuitry may include a digital voltage-controlled oscillator which may be controlled by the control signal to adjust the clock signal until the local clock is synchronized with the master clock. 
     System Description 
     Documents incorporated by reference herein are to be considered an integral part of the application except that, to the extent that any terms are defined in these incorporated documents in a manner that conflicts with definitions made explicitly or implicitly in the present specification, only the definitions in the present specification should be considered. 
     Reference is now made to  FIG. 1 , which is a schematic block diagram view of a network device  10  constructed and operative in accordance with an embodiment of the present invention. The network device  10  includes a switch core die  12  and a satellite die  14 . 
     The switch core die  12  includes multi-chip module (MCM) core logic  16  and switching circuitry to perform switching functions. The switch core die  12  also includes a frequency mixer  18 , a shaper  20  and a clock cleanup PLL  22 . In some embodiments the frequency mixer  18 , the shaper  20  and/or the clock cleanup PLL  22  may be implemented off of the main dies of the network device  10 . The frequency mixer  18 , the shaper  20  and the clock cleanup PLL  22  are described in more detail with reference to  FIGS. 2-4 . 
     The satellite die  14  includes MCM satellite logic  24  to perform receiving and transmission functions of the switch. The satellite die  14  may also include a PLL  26  and a plurality of receivers  28  and connections to a plurality of ports (not shown). The receivers  28  have been labelled individually as  28 - 1 ,  28 - 2  and  28 - 3  for the sake of simplified reference. The switch core die  12  and the satellite die  14  are generally connected using an MCM interconnect  30 . 
     The network device  10  may also include an oscillator  32 , a controller  34 , and a multiplexer  36 . The controller  34  is described in more detail with reference to  FIGS. 2-5 . The oscillator  32  and the frequency mixer  18  form part of frequency generation circuitry of the network device  10 . 
     Although the network device  10  has been described with reference to a multi-die network switch, embodiments of the present invention may be implemented on any suitable network switch including one or more dies or any suitable network device, for example, but not limited to a network router with one or more dies. 
     The oscillator  32  is configured to generate a clock signal. The oscillator  32  may be a crystal oscillator or any other suitable oscillator. The frequency of the clock signal may be any suitable frequency. In the example, of  FIG. 1  the frequency of the clock signal generated by the oscillator is 156 MHz. The multiplexer  36  is disposed between the oscillator  32  and the PLL  26 . The multiplexer  36  is configured as a switch under control of the controller  34 . Any suitable switching circuitry may be used instead of the multiplexer  36 . The multiplexer  36  enables switching between using the output of the oscillator  32  as the clock signal and an output of the frequency mixer  18  as the clock signal as will become clearer with reference to  FIG. 2 . On booting of the network device  10  or until a master clock is designated by a network management function, the PLL  26  receives the clock signal from the oscillator  32  via the multiplexer  36 . The PLL  26  is configured to generate a local clock based on the received clock signal. The local clock generated by the PLL  26  may be in the GHz range. In the example of  FIG. 1 , the PLL  26  has generated a local clock with a frequency of 3 GHz. The local clock is generally used by all the ports and lanes of the network device  10 . 
     The receivers  28  are configured to receive and buffer (in a buffer  44 ) respective data streams  38  (labeled  38 - 1  to  38 - 3 ) from respective remote clock sources (not shown). For the sake of simplicity only one of the buffers  44  has been labeled with the reference numeral  44 . Each receiver  28  may be implemented using any suitable hardware such as a Serializer/Deserializer (SerDes), for example, but not limited to, an LR SerDes RX. The data in the data streams  38  generally arrives from the remote clock sources without a clock value. Each receiver  28  may include a clock and data recovery (CDR) process  42  running therein to recover a remote clock from its received data stream  38 , for example based on transitions in the data of the received data stream  38 . For the sake of simplicity only one of clock and data recovery (CDR) process  42  has been labeled with the reference numeral  42 . The CDR of each receiver  28  may also compute a clock differential  40  (labeled  40 - 1  to  40 - 3 ), which is a difference between its recovered remote clock and the local clock (generated by the PLL  26 ) (i.e., the recovered remote clock less the local clock) of the network device  10  so that for each received data stream  38 , a difference between the recovered remote clock of the data stream  38  and the local clock is computed. The clock differential  40  is stored in a register of the network device  10 . In some embodiments, each clock differential  40  is stored in a register of the receiver  28  that computed that clock differential  40 . The clock recovery may be implemented based on any suitable process, including a non-CDR based process, for example, but not limited to, using a delay-locked loop and oversampling of the data stream. The data streams  38 , apart from their use in recovery of the remote clocks, generally include data for forwarding to other devices in the network. Therefore, the data streams  38  are generally forwarded via the MCM interconnect  30  to the multi-chip module core logic  16  to perform various switching functions (or routing functions when the network device  10  is implemented as a router). The recovered clocks and the clock differentials  40  are generally not forwarded to the multi-chip module core logic  16  via the MCM interconnect  30 . 
       FIG. 1  shows that data stream  38 - 1  received by the receiver  28 - 1  has a recovered clock of 3.001 GHz. Therefore, the clock differential  40 - 1  between the recovered clock of the received data stream  38 - 1  of 3.001 GHz and the local clock of 3 GHz is +333 PPM (i.e., the master clock is faster than the local clock by 333 PPM). The data stream  38 - 2  received by the receiver  28 - 2  has a recovered clock of 3.002 GHz. Therefore, the clock differential  40 - 2  between the recovered clock of the received data stream  38 - 2  of 3.002 GHz and the local clock of 3 GHz is +666 PPM (i.e., the master clock is faster than the local clock by 666 PPM). The data stream  38 - 3  received by the receiver  28 - 3  has a recovered clock of 2.999 GHz. Therefore, the clock differential  40 - 3  between the recovered clock of the received data stream  38 - 3  of 2.999 GHz and the local clock of 3 GHz is −333 PPM (i.e., the master clock is slower than the local clock by 333 PPM). 
     The example of  FIG. 1  shows three receivers  28 . The number of receivers  28  may be any suitable number of receivers and is not limited to three. The example of  FIG. 1  shows three boxes for the PLL  26 , one with a solid-line box and two with a dotted-line box. The three boxes represent the same PLL  26 , which has been duplicated twice for the sake of clarity. 
     Reference is now made to  FIG. 2 , which is a schematic block diagram view of the network device  10  of  FIG. 1  in an initial stage of clock synchronization. Some of the elements of the network device  10  shown in  FIG. 1  have not been included in  FIGS. 2-4  for the sake of simplicity. At this stage, the master clock has been designated by the network management function. The designation of the master clock may be received by the controller  34 . In some embodiments, the network management function may run on the controller  34  so that the controller  34  effectively designates the master clock. In the example of  FIG. 2 , the remote clock source generating the master clock is also sending the data stream  38 - 3  which is received by the receiver  28 - 3 . The frequency of the master clock is therefore equal to 2.999 GHz which is 333 PPM slower than the local clock of 3 GHz generated by the PLL  26 . The adjustment of the local clock to the master clock associated with the data stream  38 - 3  is now described in more detail. 
     The controller  34  is configured to identify the remote clock recovered by one of the receivers  28  (i.e., recovered from one of the data streams  38 ) as a master clock. As mentioned above, in the example of  FIG. 2  the identified remote clock was recovered by the receiver  28 - 3  from the data stream  38 - 3 . 
     The controller  34  is configured to find the clock differential  40 - 3  (e.g., −333 PPM) between the identified remote clock and the local clock generated by the PLL  26 . The controller  34  may “find” the clock differential  40 - 3  by reading the clock differential  40 - 3  from a register, e.g., a register of the receiver  28 - 3  or by computing the clock differential  40 - 3  from the local clock generated by the PPL  26  and the remote clock recovered by the receiver  28 - 3 . 
     The controller  34  is configured to generate a control signal  46 , responsively to the clock differential  40 - 3 , for providing to the frequency mixer  18  to slow down or speed up the clock signal provided to the PLL  26 . In the example of  FIG. 2  the local clock is faster than the master clock, therefore the control signal  46  needs to slow down the clock signal provided to the PLL  26 . The controller  34  is generally configured to change the clock signal provided to the PLL  26  slowly, for example, but not limited to, by the smallest resolution possible. For example, a slow-down command may be given until the feedback indicates that the clock needs to run quicker. Then a “metastable” state is entered where the clock speed is adjusted up and down in succession, thereby indicating that the target frequency has been reached. 
     In some embodiments, the frequency mixer  18  may aggregate the control signal  46  adjustments. In other embodiments, the frequency mixer  18  may use the current control signal  46  without aggregating previous control signals  46 . In such a case, the control signal  46  is provided by the controller  34  continuously or frequently enough to maintain the required adjusted output of the frequency mixer  18 . 
     The controller  34  is configured to provide the control signal  46  to the frequency mixer  18  via the shaper  20 . The shaper  20  delays receipt of the control signal  46  by the frequency mixer  18 . The shaper  20  is described in more detail with reference to  FIG. 3 . In some embodiments the shaper  20  is not included in the network device  10  and delay may optionally be provided by another element. 
     The frequency mixer  18  is configured to combine the control signal  46  from the controller  34  with an output from the oscillator  32  (the 156 MHz clock signal in the example of  FIG. 2 ) yielding a clock signal (which in the example of  FIG. 2  should be less than 156 MHz), as a combined signal, for output towards the PLL  26  via the clock cleanup PLL  22 . The clock cleanup PLL  22  is disposed between an output of the frequency mixer  18  and an input of the PLL  26  to remove jitter from the combined signal. In some embodiments, the clock cleanup PLL  22  is not included in the network device  10 . 
     In some embodiments, the frequency mixer  18  may be implemented with a higher speed mixer and a frequency divider to improve resolution of the mixer ticks. A mixer tick is a single mixer step in any direction. The above is now illustrated by way of an example of a frequency mixer operating at 1.56 GHz so that corrections to the output of the frequency mixer are made in a 1.56 GHz resolution so that the corrections may be more accurate. The output of the higher speed mixer is then scaled down using a frequency divider which in this example would divide the output of the mixer by 10. 
     Although at this point the output of the oscillator  32  is connected to an input of the frequency mixer  18 , the direct output from the oscillator  32  via the multiplexer  36  is blocked under control of the controller  34 . The multiplexer  36  is now configured to route the output of the frequency mixer  18  and the clock cleanup PLL  22  to the PLL  26 . Therefore, at around the same time that the control signal  46  is sent to the frequency mixer  18  via the shaper  20 , the controller  34  is also configured to provide another control signal to the multiplexer  36  to switch to connecting the output of the frequency mixer  18  via the clock cleanup PLL  22  to the PLL  26 . The switching is generally performed when the absolute value of the clock differential  40 - 3  is greater than a given value. If the absolute value of the clock differential  40 - 3  is less than the given value then there is generally no need to synchronize the local clock with the master clock as the value of the local clock and the master clock are the same or are close enough. Therefore, the multiplexer  36  is configured under control of the controller  34  to switch between: connecting the output of the oscillator  32  to the PLL  26 ; and connecting the output of the frequency mixer  18  to the PLL  26  (i.e. switching between using the output of the oscillator  32  as the clock signal and using the combined signal as the clock signal). 
     In some embodiments, the multiplexer  36  may include suitable logic to switch back to routing the output of the oscillator  32  to the PLL  26  if the frequency mixer  18  no longer provides a signal or provides a signal that includes too much jitter or too much frequency drift. This could occur if the link to the master clock is down. The amount of jitter and frequency drift that could cause the switch-back is generally implementation dependent. 
     Reference is now made to  FIG. 3 , which is a schematic block diagram view of the network device  10  of  FIG. 1  in a later stage of clock synchronization. 
     The adjusted clock signal outputted by the frequency mixer  18  via the clock cleanup PLL  22  and the multiplexer  36  is received by the PLL  26 . The PLL  26  therefore now generates the local clock based on the adjusted clock signal generated by the frequency mixer  18  and cleaned by the clock cleanup PLL  22 .  FIG. 3  shows that the control signal  46  has caused a reduction in the local clock generated by the PLL  26  from 3 GHz to 2.9995 GHz. In response to the adjustment of the local clock to 2.9995 GHz, the clock differential  40 - 3  computed by the clock and data recovery (CDR) process  42  of the receiver  28 - 3  or by the controller  34  is updated. The updated clock differential  40 - 3  in the example of  FIG. 3  is equal to the difference between the master clock value of 2.999 GHz and the local clock value of 3 GHz, giving −167 PPM. In other words, the master clock is slower than the local clock by 167 PPM. 
     Therefore, the controller  34  is configured to update the control signal  46 , responsively to the updated clock differential  40 - 3 , for providing to the frequency mixer  18  to further slow-down (in the example of  FIG. 3 ) the clock signal provided to the PLL  26 . The controller  34  is configured to provide the updated control signal  46  to the frequency mixer  18  via the shaper  20 . The frequency mixer  18  is configured to combine the updated control signal  46  from the controller  34  with the output (156 MHz in the example of  FIG. 3 ) from the oscillator  32  yielding an adjusted clock signal, as a combined signal, for output towards the PLL  26  via the clock cleanup PLL  22 . 
     If the control signal  46  performed an over adjustment of the local clock, for example, the local clock is less than the master clock, the controller  34  adjusts the control signal  46  so as to speed up the local clock. 
     The above process of adjusting the control signal  46  responsively to the clock differential  40 - 3  causing the frequency mixer  18  to adjust the clock signal is performed iteratively to reduce an absolute value of the clock differential  40 - 3  to below a given value. 
     The shaper  20 , disposed between the controller  34  and the frequency mixer  18  is configured to delay receipt, by the frequency mixer  18 , of the control signal  46  provided by the controller  34 . The delaying performed by the frequency mixer  18  attempts to prevent over correction of the clock signal and the local clock by the controller  34  as adjustments to the control signal  46  may take some time to appear in the adjusted clock signal and the adjusted local clock. The delay is generally dependent upon timing of the feedback loop such as time constants of the multiplexer  36 , and stabilization time of the frequency mixer  18  to move to a new frequency. 
     Reference is now made to  FIG. 4 , which is a schematic block diagram view of the network device  10  of  FIG. 1  in a final stage of clock synchronization. The iterative adjustments of the control signal  46  ( FIG. 3 ) have led to the iterative adjustments to the clock signal generated by the frequency mixer  18  and the iterative adjustments to the local clock generated by the PLL  26  so that the local clock is now equal 2.999 GHz which also equals the value of the master clock so that the clock differential  40 - 3  is now equal to zero. As mentioned above the PPM may need to be reduced to below a given value in order for the local clock to be considered synchronized with the master clock even if the PPM is non-zero. 
     Reference is now made to  FIG. 5 , which is a flow chart  48  including exemplary steps in a method of clock synchronization in the network device  10  of  FIG. 1 . Reference is also made to  FIG. 2 . The controller  34  is configured to identify (block  50 ) the remote clock recovered by one of the receivers  28  as the master clock. The controller  34  is configured to find (block  52 ) the clock differential  40  between the identified remote clock and the local clock. 
     The controller  34  is configured to check (at a decision block  54 ) if the absolute value of the clock differential is greater than a given value. If the absolute value of the clock differential is not greater than the given value (branch  56 ), then there is at present no need to synchronize the local clock with the master clock as the local clock is close enough to the master clock without performing any adjustments. If the absolute value of the clock differential is greater than, or equal to, the given value (branch  58 ), then the controller  34  is configured to generate (block  60 ) the control signal  46  described in more detail above with reference to  FIGS. 2 and 3 . 
     The controller  34  is configured to provide (block  62 ) the control signal  46  to the frequency mixer  18  (or any suitable frequency generation circuitry) responsively to the clock differential  40 , which causes the frequency mixer  18  (or the frequency generation circuit) to adjust the clock signal so as to iteratively reduce an absolute value of the clock differential. 
     The controller  34  is configured to provide a control signal to the multiplexer  36  (or any suitable switching circuitry) to switch to connecting the output of the frequency mixer  18  to the PLL  26  (via the clock cleanup PLL  22 ) when the absolute value of the clock differential is greater than the given value. This step may be performed at any suitable time after the step of block  54  is performed. The multiplexer  36  is generally configured to continue to connect the output of the frequency mixer  18  to the PLL  26  (via the clock cleanup PLL  22 ) for as long as the connection to the master clock is maintained. 
     If a new master clock is designated, the controller  34  repeats the steps described above with respect to the receiver  28  of the newly assigned master clock. 
     The steps of blocks  52 - 62  are repeated periodically (arrow  68 ), subject to a delay added by the shaper  20 , to perform the iterative adjustment of the clock signal and local clock described above with reference to  FIGS. 2-4 . 
     Reference is now made to  FIG. 6 , which is a schematic block diagram view of a network device  100  constructed and operative in accordance with an alternative embodiment of the present invention. The network device  100  is substantially the same as the network device  10  of  FIGS. 1-5  except for the following differences. The frequency mixer  18 , shaper  20 , clock cleanup PLL  22 , oscillator  32  and the multiplexer  36  are replaced with frequency generation circuitry including a voltage-controlled oscillator  104  which under control of a controller  134  using a control signal  146  generates the clock signal. Prior to the master clock being designated by the network management function, the controller  134  is configured to control the voltage-controlled oscillator  104  to generate a clock signal with any suitable frequency, e.g., 156 MHz. Once the master clock has been designated by the network management function, the controller  134  is configured to adjust the clock signal generated by the voltage-controlled oscillator  104  using the control signal  146  based on a clock differential  140  between a recovered remote clock (designated as the master clock) and the local clock generated by a PLL  126 . 
     In practice, some or all of the functions of the controller  34  or the controller  134  may be combined in a single physical component or, alternatively, implemented using multiple physical components. These physical components may comprise hard-wired or programmable devices, or a combination of the two. In some embodiments, at least some of the functions of the processing circuitry may be carried out by a programmable processor under the control of suitable firmware. This firmware may be downloaded to a device in electronic form, over a network, for example. Alternatively, or additionally, the software may be stored in tangible, non-transitory computer-readable storage media, such as optical, magnetic, or electronic memory. 
     The software components of the present invention may, if desired, be implemented in ROM (read only memory) form. The software components may, generally, be implemented in hardware, if desired, using conventional techniques. The software components may be instantiated, for example: as a computer program product or on a tangible medium. In some cases, it may be possible to instantiate the software components as a signal interpretable by an appropriate computer, although such an instantiation may be excluded in certain embodiments of the present invention. 
     Various features of the invention which are, for clarity, described in the contexts of separate embodiments may also be provided in combination in a single embodiment. Conversely, various features of the invention which are, for brevity, described in the context of a single embodiment may also be provided separately or in any suitable sub-combination. 
     The embodiments described above are cited by way of example, and the present invention is not limited by what has been particularly shown and described hereinabove. Rather the scope of the invention includes both combinations and subcombinations of the various features described hereinabove, as well as variations and modifications thereof which would occur to persons skilled in the art upon reading the foregoing description and which are not disclosed in the prior art.