Patent Publication Number: US-11031347-B2

Title: Semiconductor packages

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a continuation of U.S. application Ser. No. 15/869,517, filed on Jan. 12, 2018, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2017-0100440, filed on Aug. 8, 2017, in the Korean Intellectual Property Office, the disclosure of each of which is hereby incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     Example embodiments of the present disclosure relate to semiconductor packages and, more specifically, to wafer level packages. 
     2. Discussion of Related Art 
     A semiconductor chip in a semiconductor package may malfunction due to electromagnetic interference (EMI). As electronic devices are downsized, a semiconductor package is highly integrated and downscaled. There are increasing demands for enhanced EMI shield and high heat dissipation performance in the highly integrated and downscaled semiconductor package. 
     SUMMARY 
     According to an example embodiment of the inventive concepts, a semiconductor package may include a heat spreading layer including a hole, a first semiconductor chip below the heat spreading layer, a redistribution structure below the first semiconductor chip, a first mold layer between the heat spreading layer and the redistribution structure, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole. 
     According to an example embodiment of the inventive concepts, a semiconductor package may include a heat spreading layer including at least one chip portion, a shielding portion surrounding the at least one chip portion, and a hole portion outside the shielding portion and including a hole, at least one first semiconductor chip below the at least one chip portion of the heat spreading layer, at least one shielding wall in contact with and below the shielding portion of the heat spreading layer, a first conductive pillar passing through the hole included in the hole portion of the heat spreading layer, a second conductive pillar below the at least one first semiconductor chip, a first mold layer covering at least one sidewall of the shielding wall, a sidewall of the first conductive pillar, a sidewall of the at least one second conductive pillar, and a sidewall of the first semiconductor chip, and a redistribution structure below the first semiconductor chip and in contact with the at least one shielding wall, the first conductive pillar, and the second conductive pillar. 
     According to an example embodiment of the inventive concepts, a semiconductor package may include a first semiconductor package, a second semiconductor package on the first semiconductor package, and an inter-package connection between the first semiconductor package and the second semiconductor package. The first semiconductor package may include a redistribution structure, a first semiconductor chip on the redistribution structure, a heat spreading layer on the first semiconductor chip and including a hole, a first mold layer between the heat spreading layer and the redistribution structure and covering a sidewall of the first semiconductor chip, a shielding wall extending from the redistribution structure and the heat spreading layer and surrounding the first semiconductor chip, and a first conductive pillar extending from the redistribution structure into the hole. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A and 1B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. 
         FIG. 2A  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. 
         FIG. 2B  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. 
         FIGS. 3A and 3B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. 
         FIGS. 4A and 4B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. 
         FIG. 5  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. 
         FIGS. 6A, 6C, 6E, 6G, 6I, 6K, and 6L  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. 
         FIGS. 6B, 6D, 6F, 6H, and 6J  are plan views illustrating a method of manufacturing a semiconductor package according to an example embodiment. 
         FIGS. 7A, 7B, and 7C  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. 
         FIGS. 8A and 8B  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Various example embodiments will now be described more fully hereinafter with reference to the accompanying drawings. Like reference numerals may refer to like elements throughout this application. 
       FIGS. 1A and 1B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. 
     Referring to  FIGS. 1A and 1B , a semiconductor package  100  may include a heat spreading layer  110 , a first semiconductor chip  140 A, a shielding wall  130 , a first conductive pillar  120 , a second conductive pillar  160 , a first mold layer  170 , a redistribution structure  180 , and an outer terminal  190 . 
     The heat spreading layer  110  may include a thermal and electrically conductive material. The heat spreading layer  110  may include, for example, Cu, Ni, Au, Ag, Al, or a combination thereof. In some embodiments, the heat spreading layer  110  may be formed of stacked layers. In some embodiments, the heat spreading layer  110  may include a laminate, such as a copper clad laminate (CCL). 
     The heat spreading layer  110  may include a chip portion  112 , a shielding portion  114 , and a hole portion  116 . The chip portion  112  may be located in a central region of the heat spreading layer  110 . The shielding portion  114  may surround the chip portion  112 . The hole portion  116  may be located outside the shielding portion  114 . The heat spreading layer  110  may include a hole H penetrating the heat spreading layer  110  in the hole portion  116 . In some embodiments, the hole portion  116  may include a plurality of spaced holes H arranged along sides (e.g., peripheral areas) of the heat spreading layer  110 . 
     The first semiconductor chip  140 A may be disposed below the chip portion  112  of the heat spreading layer  110 . The first semiconductor chip  140 A may be, for example, a logic or memory chip. The logic chip may be, for example, a central processing unit (CPU), a controller, an application processor (AP), or an application specific integrated circuit (ASIC). The memory chip may be, for example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a flash memory, an electrically erasable programmable read-only memory (EEPROM), a phase change memory (PRAM), a resistive random access memory (RRAM), or a magnetic random access memory (MRAM). 
     The first semiconductor chip  140 A may be attached to an underside (e.g., a bottom surface) of the chip portion  112  of the heat spreading layer  110  by a chip adhesion layer  150  disposed between the first semiconductor chip  140 A and the chip portion  112 . The chip adhesion layer  150  may include, for example, a non-conductive adhesive, an anisotropic conductive adhesive, or an isotropic conductive adhesive. The non-conductive adhesive, the anisotropic conductive adhesive, and an isotropic conductive adhesive may be of a film or paste type. The non-conductive adhesive may include polymer resin. The anisotropic conductive adhesive and an isotropic conductive adhesive may include polymer resin and conductive particles. The conductive particles may include, for example, Ni, Au, Ag, and/or Cu. The polymer resin may include, for example, thermal curable resin, thermoplastic resin, and/or ultraviolet (UV) curable resin. The chip adhesion layer  150  may include, for example, epoxy resin, urethane resin, or acrylic resin. 
     The second conductive pillar  160  may be disposed below the first semiconductor chip  140 A. The second conductive pillar  160  may be electrically connected to the first semiconductor chip  140 A. The first semiconductor chip  140 A may be electrically connected to the redistribution structure  180  via the second conductive pillar  160 . The second conductive pillar  160  may include an electrically conductive material. For example, the second conductive pillar  160  may include metal (e.g., Cu, Ni, Al, Au, or Ag). 
     The shielding wall  130  may be disposed below the shielding portion  114  of the heat spreading layer  110 . The shielding wall  130  may vertically extend from the shielding portion  114  of the heat spreading layer  110  to the redistribution structure  180 . The shielding wall  130  may be spaced from first semiconductor chip  140 A and (continuously) extend along an outer perimeter of the chip portion  112  to surround the first semiconductor chip  140 A. A width of the shielding wall  130  may be about 5 μm to 100 μm. A height of the shielding wall  130  may be about 10 μm to 500 μm. The shielding wall  130  may be connected to the ground via the redistribution structure  180 . The shielding wall  130  may function as a electromagnetic interference (EMI) shield and a heat transfer medium for transmitting heat generated at the redistribution structure  180  to the heat spreading layer  110 . The shielding wall  130  may include metal (e.g., Cu, Al, Ni, Au, and/or Ag). The shielding wall  130  may include the same material as or a different material from the heat spreading layer  110 . 
     The first conductive pillar  120  may contact the redistribution structure  180  and extend into the hole H of the heat spreading layer  110 . A diameter of the first conductive pillar  120  may be smaller than a diameter of the hole H. A sidewall of the first conductive pillar  120  may be spaced from an inner sidewall of the hole H. An upper surface of the first conductive pillar  120  may be coplanar with an upper surface of the heat spreading layer  110 . A height of the first conductive pillar  120  may be greater than the height of the shielding wall  130 . A difference in the heights of the first conductive pillar  120  and the shielding wall  130  may be equal to a thickness of the heat spreading layer  110 . The semiconductor package  100  may be connected to the same or different type of another semiconductor package via the first conductive pillar  120 . The first conductive pillar  120  may include an electrically conductive material. The first conductive pillar  120  may include, for example, Cu, Ni, Al, Au, Ag, or a combination thereof. The first conductive pillar  120  and the shielding wall  130  may be made of the same material. In some embodiments, the first conductive pillar  120  and the shielding wall  130  may be made of different materials. An upper portion of the first conductive pillar  120  may include, for example, organic solderability preservative (OSP), Ni/Au, electroless nickel immersion gold (ENIG), or electroless nickel electroless palladium immersion gold (ENEPIG), to prevent or mitigate oxidation thereof. 
     A lower surface of the shielding wall  130 , a lower surface of the first conductive pillar  120 , and a lower surface of the second conductive pillar  160  may each be connected to the redistribution structure  180 . The lower surface of the shielding wall  130 , the lower surface of the first conductive pillar  120 , and the lower surface of the second conductive pillar  160  may be coplanar. The redistribution structure  180  may include an upper pad  182 , a redistribution pattern  186 , a lower pad  188 , and an insulating layer  184 . The upper pad  182  may be disposed on an upper side (e.g., a top surface) of the redistribution structure  180  and be electrically connected to the shielding wall  130 , the first conductive pillar  120 , and/or the second conductive pillar  160 . The lower pad  188  may be disposed on an underside of the redistribution structure  180  and be electrically connected to the outer terminal  190 . The redistribution pattern  186  may connect the upper pad  182  to the lower pad  188 . A shape or configuration of the redistribution pattern  186  is not limited to that shown in  FIG. 1B , but may be variously modified. In some embodiments, the redistribution pattern  186  may be formed of a plurality of layers. The upper pad  182 , the lower pad  188 , and the redistribution pattern  186  may include an electrically conductive material, for example, Cu, Ni, Au, Ag, Al, W, Ti, Ta, TiN, or a combination thereof. The insulating layer  184  may include, for example, an organic insulating material (e.g., polyimide, polybenzoxazole (PBO), or benzocyclobutene (BCB)), or an inorganic insulating material (e.g., silicon nitride, silicon oxynitride, or silicon oxide). 
     The first mold layer  170  may fill a space between the redistribution structure  180  and the heat spreading layer  110 . The first mold layer  170  may cover at least a sidewall of the first semiconductor chip  140 A, a sidewall of the shielding wall  130 , and a sidewall of the second conductive pillar  160 . The first mold layer  170  may fill the hole H. The first mold layer  170  may fill a gap between the inner sidewall of the hole H and a sidewall of the first conductive pillar  120 . Thus, the first conductive pillar  120  and the heat spreading layer  110  may be separated from each other with the first mold layer  170  disposed therebetween. An upper surface of a portion of the first mold layer  170  filling the hole H, the upper surface of the first conductive pillar  120 , and the upper surface of the heat spreading layer  110  may be coplanar. The first mold layer  170  may include, for example, thermally curable resin, thermoplastic resin, or UV curable resin. The first mold layer  170  may include, for example, epoxy resin (e.g., epoxy mold compound (EMC)) or silicone resin. 
     The outer terminal  190  may be disposed below the redistribution structure  180 . The outer terminal  190  may be connected to the lower pad  188  of the redistribution structure  180 . The outer terminal  190  may include a bump, such as a metal bump or a solder bump. The metal bump may include an electrical conductive material (e.g., Cu, Al, and/or Au). The solder bump may include, for example, Sn/Pb or Sn/Ag/Cu. Although not shown, the outer terminal  190  may further include an under bump metal pattern disposed between the bump and the lower pad  188  of the redistribution structure  180 . The under bump metal pattern may include metal (e.g., Cr, W, Ti, Cu, Ni, Al, Pd, and/or Au). 
     According to an example embodiment of the inventive concepts, because the shielding wall  130  and the heat spreading layer  110  cover the first semiconductor chip  140 A, the first semiconductor chip  140 A may be shielded from electromagnetic interference (EMI). Additionally, heat generated from the first semiconductor chip  140 A and/or the redistribution structure  180  may be transmitted to the heat spreading layer  110  having a lager plane area, such that the semiconductor package  100  may have an enhanced heat dissipation performance. 
     The heat spreading layer  110  may be formed to have the plane area occupying or covering most of or an entirety of a plane area of the semiconductor package  100 . For example, an upper surface of the first mold layer  170  except for the portion filling the hole H may be covered by the heat spreading layer  110 . A plane area of the redistribution structure  180  may be substantially equal to a sum of the plane area of the heat spreading layer  110  and a plane area of the hole H. The semiconductor package  100  may have the enhanced heat dissipation property by the heat spreading layer  110  having the larger plane area. 
     Furthermore, because the heat spreading layer  110  and the redistribution structure  180  are disposed at the upper portion and lower portion, respectively, of the semiconductor package  100 , the warpage of the semiconductor package  100 , caused by a difference in coefficients of thermal expansion between elements of the semiconductor package  100 , may be reduced or prevented. By adjusting a thickness and material of the heat spreading layer  110 , the warpage of the semiconductor package  100  may be controlled. 
       FIG. 2A  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package  200 A according to the present example embodiment and the semiconductor package  100  according to the example embodiment described with reference to  FIGS. 1A and 1B  will be described. 
     Referring to  FIG. 2A , the semiconductor package  200 A may further include a third conductive pillar  210  disposed between the chip portion  112  of the heat spreading layer  110  and the first semiconductor chip  140 A. The third conductive pillar  210  may extend from the chip portion  112  of the heat spreading layer  110  toward the first semiconductor chip  140 A. A height of the third conductive pillar  210  may be smaller than the height of the first conductive pillar  120  and the height of the shielding wall  130 . An upper surface of the third conductive pillar  210  may contact the chip portion  112  of the heat spreading layer  110 . A lower surface of the third conductive pillar  210  may not contact the first semiconductor chip  140 A. The chip adhesion layer  150  may be disposed between the first semiconductor chip  140 A and the heat spreading layer  110  and between the first semiconductor chip  140 A and the lower surface of the third conductive pillar  210 . The third conductive pillar  210  may include an electrically and thermally conductive material. The third conductive pillar  210  may include, for example, Cu, Ni, Au, Ag, Al, or a combination thereof. Because the semiconductor package  200 A includes the third conductive pillar  210 , the heat generated from the first semiconductor chip  140 A may be more rapidly transmitted to the heat spreading layer  110 . For example, the heat generated from the first semiconductor chip  140 A may be transmitted to the heat spreading layer  110  via a short thermal path of the chip adhesion layer  150  and the third conductive pillar  210  having the relatively high thermal conductivity. Thus, the semiconductor package  200 A may have an enhanced heat dissipation performance. 
       FIG. 2B  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package  200 B according to the present example embodiment and the semiconductor package  200 A according to the example embodiment described with reference to  FIG. 2A  will be described. 
     Referring to  FIG. 2B , the lower surface of the third conductive pillar  210  may contact the first semiconductor chip  140 A in the semiconductor package  200 B. The heat generated from the first semiconductor chip  140 A may be transmitted to the heat spreading layer  110  via the third conductive pillar  210  having relatively high thermal conductivity. Thus, the semiconductor package  200 B may have an enhanced heat dissipation performance. 
       FIGS. 3A and 3B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package  300  according to the present example embodiment and the semiconductor package  100  according to the example embodiment described with reference to  FIGS. 1A and 1B  will be described. 
     Referring to  FIGS. 3A and 3B , in the semiconductor package  300 , the heat spreading layer  110  may include a plurality of laterally spaced chip portions  112 A and  112 B. The shielding portion  114  may surround the plurality of chip portions  112 A and  112 B. A plurality of semiconductor chips  140 A and  140 B may be disposed below the plurality of chip portions  112 A and  112 B, respectively. For example, referring to  FIG. 3B , the heat spreading layer  110  may include a first chip portion  112 A and a second chip portion  112 B. The plurality of semiconductor chips  140 A and  140 B may include the first semiconductor chip  140 A and a second semiconductor chip  140 B. The first semiconductor chip  140 A may be disposed below the first chip portion  112 A of the heat spreading layer  110 . The second semiconductor chip  140 B may be disposed below the second chip portion  112 B of the heat spreading layer  110 . The first semiconductor chip  140 A and the second semiconductor chip  140 B may each be a memory or logic device. The first semiconductor chip  140 A and the second semiconductor chip  140 B may be of the same type or different types. A plurality of shielding walls  130 A and  130 B may be disposed below the shielding portion  114  of the heat spreading layer  110  and respectively surround the plurality of semiconductor chips  140 A and  140 B. The plurality of shielding walls  130 A and  130 B may include a first shielding wall  130 A and a second shielding wall  130 B. The first shielding wall  130 A may surround the first semiconductor chip  140 A. The second shielding wall  130 B may surround the second semiconductor chip  140 B. As the plurality of shielding walls  130 A and  130 B surround the plurality of semiconductor chips  140 A and  140 B, respectively, EMI that may be generated between the plurality of semiconductor chips  140 A and  140 B may be prevented or reduced. In some embodiments, the semiconductor package  300  may be of a system in package (SIP) type. 
       FIGS. 4A and 4B  are a plan view and a cross-sectional view, respectively, illustrating a semiconductor package according to an example embodiment. Hereinafter, differences between a semiconductor package  400  according to the present example embodiment and the semiconductor package  300  according to the example embodiment described with reference to  FIGS. 3A and 3B  will be described. 
     Referring to  FIGS. 4A and 4B , in the semiconductor package  400 , the plurality of semiconductor chips  140 A and  140 B may be disposed below one chip portion  112  of the heat spreading layer  110 . For example, the first semiconductor chip  140 A and the second semiconductor chip  140 B may be disposed below the one chip portion  112  of the heat spreading layer  110 . One shielding wall  130  disposed below the shielding portion  114  of the heat spreading layer  110  may surround the plurality of semiconductor chips  140 A and  140 B. 
       FIG. 5  is a cross-sectional view illustrating a semiconductor package according to an example embodiment. 
     Referring to  FIG. 5 , a semiconductor package  500  may be of a package on package (POP) type. The semiconductor package  500  may include a first semiconductor package  510 , a second semiconductor package  520  on the first semiconductor package  510 , and an inter-package connection  530  between the first semiconductor package  510  and the second semiconductor package  520 . 
     The first semiconductor package  510  may be one of the semiconductor packages  100 ,  200 A,  200 B,  300 , or  400  described above. For example, the first semiconductor package  510  may include the redistribution structure  180 , the outer terminal  190  below the redistribution structure  180 , the first semiconductor chip  140 A on the redistribution structure  180 , the heat spreading layer  110  disposed on the first semiconductor chip  140 A and having the hole H, the first mold layer  170  filling the space between the redistribution structure  180  and the heat spreading layer  110  and surrounding or covering the first semiconductor chip  140 A, the shielding wall  130  extending from the redistribution structure  180  to the heat spreading layer  110  and covering or surrounding at least a sidewall of the first semiconductor chip  140 A, and the first conductive pillar  120  extending from the redistribution structure  180  into the hole H of the heat spreading layer  110 . Further, the first semiconductor package  510  may further include the chip adhesion layer  150  disposed between the heat spreading layer  110  and the first semiconductor chip  140 A. In some embodiments, the first semiconductor package  510  may further include the third conductive pillar  210  between the heat spreading layer  110  and the first semiconductor chip  140 A, shown in  FIG. 2A or 2B . 
     The second semiconductor package  520  may be the same as or different from the first semiconductor package  510 . The second semiconductor package  520  may include, for example, a second substrate  522 , a plurality of second semiconductor chips  140 B on the second substrate  522 , and a second mold layer  526  covering the second semiconductor chips  140 B. 
     The second mold layer  526  may protect the second semiconductor chips  140 B from physical or chemical damage. The second mold layer  526  may include thermally curable resin, thermoplastic resin, and/or UV curable resin. The second mold layer  526  may include silicon resin or epoxy resin (e.g., EMC). The second substrate  522  may include, for example, silicon, glass, ceramic, or plastics. 
     The second semiconductor chips  140 B may each be a memory or logic device. The second semiconductor chips  140 B may be of the same type as or different types from the first semiconductor chip  140 A. The number of the second semiconductor chips  140 B may not be limited to the number of those shown in  FIG. 5 . 
     The adhesion layer  523  may be disposed between the second semiconductor chips  140 B and between a lowermost one of the second semiconductor chips  140 B and the second substrate  522  such that the second semiconductor chips  140 B may be attached to each other and to the second substrate  522 . The adhesion layer  523  may include, for example, thermally curable resin, thermoplastic resin, and/or UV curable resin. The adhesion layer  523  may include, for example, epoxy resin, urethane resin, or acrylic resin. The second semiconductor chips  140 B may each include a through silicon via (TSV)  524  and an inner connection  528 . The second semiconductor chips  140 B and the second substrate  522  may be electrically connected via the TSV  524  and the inner connection  528 . The TSV  524  and the inner connection  528  may include an electrically conductive material. 
     The structure of the second semiconductor package  520  may not be limited to that shown in  FIG. 5 . For example, the second semiconductor chips  140 B may be connected to the second substrate  522  by a boding wire. In some embodiments, the second semiconductor package  520  may include one semiconductor chip. The one semiconductor chip and the second substrate  522  may be connected by a wire bonding method or a flip chip bonding method. 
     The inter-package connection  530  may electrically connect the first semiconductor package  510  to the second semiconductor package  520 . The inter-package connection  530  may contact the first conductive pillar  120  and not contact the heat spreading layer  110 . The inter-package connection  530  may include an electrically conductive material, for example, Al, Au, or solder. 
     As the semiconductor package  500  includes the shielding wall  130  and the heat spreading layer  110 , EMI that may be generated between the first semiconductor chip  140 A and the second semiconductor chips  140 B may be prevented or reduced. 
       FIGS. 6A, 6C, 6E, 6G, 6I, 6K, and 6L  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment.  FIGS. 6B, 6D, 6F, 6H, and 6J  are plan views illustrating the same method of manufacturing a semiconductor package according to the same example embodiment.  FIGS. 6B, 6D, 6F, 6H, and 6J  correspond to  FIGS. 6A, 6C, 6E, 6G, 6I , respectively. 
     Referring to  FIG. 6A , a carrier adhesion layer  620  and the heat spreading layer  110  may be formed on a carrier  610 . The carrier  610  may include, for example, glass, plastics, ceramic, or a semiconductor material (e.g., silicon or germanium). The carrier adhesion layer  620  may include, for example, thermally curable resin, thermoplastic resin, or UV curable resin. The carrier adhesion layer  620  may be an adhesive tape including acrylic resin or epoxy resin. In some embodiments, the heat spreading layer  110  may be formed by attaching copper clad laminate (CCL) to the carrier  610  using the carrier adhesion layer  620 . When using the method of attaching the CCL, the heat spreading layer  110  that is relatively thick may be quickly formed on the carrier  610 . Thus, the semiconductor package having improved EMI shielding effect may be manufactured, and its manufacturing time may be reduced. 
     Referring to  FIG. 6B , the heat spreading layer  110  may include the chip portion  112 , the shielding portion  114 , and the hole portion  116 . 
     Referring to  FIGS. 6C and 6D , the hole H may be formed in the hole portion  116  of the heat spreading layer  110 . The hole H may be formed by a photolithography process. For example, the hole H may be formed by forming a photoresist pattern (not shown) on the heat spreading layer  110 , etching the hole portion  116  of the heat spreading layer  110  exposed by the photoresist pattern, and removing the photoresist pattern. The heat spreading layer  110  may be etched by dry or wet etch. In some embodiments, the hole H may be formed by mechanical drilling. 
     In some embodiments, unlike those shown in  FIGS. 6A to 6D , the hole H in the heat spreading layer  110  may be formed first, and then the heat spreading layer  110  including the hole H may be attached to the carrier adhesion layer  620 . 
     In some embodiments, unlike those shown in  FIGS. 6A to 6D , the heat spreading layer  110  including the hole H may be formed by a photolithography process and an electric plating process. For example, the heat spreading layer  110  including the hole H may be formed by forming a mask pattern on the carrier adhesion layer  620  by the photolithography process, and then forming a material layer on the resulting structure having the mask pattern by the electric plating process and removing the mask pattern. 
     Referring to  FIGS. 6E and 6F , the first conductive pillar  120  extending from the inside of the hole H and the shielding wall  130  extending from the shielding portion  114  of the heat spreading layer  110  may be formed. The first conductive pillar  120  and the shielding wall  130  may be formed at the same time. For example, the first conductive pillar  120  and the shielding wall  130  may be concurrently formed by forming a photoresist pattern on the heat spreading layer  110 , forming a metal layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern. Because the first conductive pillar  120  and the shielding wall  130  may be concurrently formed, its manufacturing time and cost may be reduced. 
     Referring to  FIGS. 6G and 6H , the first semiconductor chip  140 A having the second conductive pillar  160  connected thereto may be attached to the chip portion  112  of the heat spreading layer  110 . To attach the first semiconductor chip  140 A to the heat spreading layer  110 , the chip adhesion layer  150  may be used. 
     Referring to  FIGS. 6I and 6J , the first mold layer  170  may be formed on the heat spreading layer  110  to encapsulate the first semiconductor chip  140 A, the first conductive pillar  120 , the shielding wall  130 , and the second conductive pillar  160 . The first mold layer  170  may fill the hole H to insulate the first conductive pillar  120  from an inner surface of the hole H. Thereafter, the first mold layer  170  may be ground to expose the first conductive pillar  120 , the shielding wall  130 , and the second conductive pillar  160 . 
     Referring to  FIG. 6K , the redistribution structure  180  may be formed on the first mold layer  170 . The outer terminal  190  may be formed on the redistribution structure  180 . The redistribution structure  180  may include the insulating layer  184 , the redistribution pattern  186 , the upper pad  182 , and the lower pad  188 . The insulating layer  184  may be formed by, for example, a spin coating process, a physical vapor deposition process, or a chemical vapor deposition process, or an atomic layer deposition process. The redistribution pattern  186  may be formed by, for example, photolithography process and an electric plating process. The upper pad  182  and the lower pad  188  may be formed by, for example, a sputtering process or an electric plating process. The outer terminal  190  may be formed by, for example, attaching a solder ball on the lower pad  188  and performing a reflowing process. 
     Referring to  FIG. 6L , the carrier  610  and the carrier adhesion layer  620  may be removed. The carrier adhesion layer  620  may be removed along with the carrier  610  or separately removed. Thereafter, a cutting process may be performed such that the semiconductor package  100  shown in  FIGS. 1A and 1B  may be completed. The cutting process may include a sawing process or a laser cutting process. 
       FIGS. 7A, 7B, and 7C  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. Hereinafter, differences between the present example embodiment and the example embodiment described with reference to  FIG. 6A to 6I  will be described. 
     Referring to  FIG. 7A , after performing the same processes as described with reference to  FIGS. 6A to 6D , the third conductive pillar  210  may be formed on the heat spreading layer  110 . For example, the third conductive pillar  210  may be formed by forming a photoresist pattern on the heat spreading layer  110  to have an opening exposing a portion of the heat spreading layer  110 , forming a conductive material layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern. 
     Referring to  FIG. 7B , the first conductive pillar  120  extending from the inside of the hole H and the shielding wall  130  extending from the heat spreading layer  110  may be formed. For example, the first conductive pillar  120  and the shielding wall  130  may be concurrently formed by forming a photoresist pattern on the heat spreading layer  110  to have an opening exposing the hole H and another portion of the heat spreading layer  110 , forming a conductive material layer on the resulting structure having the photoresist pattern by an electric plating process, and removing the photoresist pattern. 
     In some embodiments, the order of the process described with reference to  FIG. 7A  and the process described with reference to  FIG. 7B  may be inverted. For example, after forming the first conductive pillar  120  and the shielding wall  130  using a first photolithography process and a first electric plating process, the third conductive pillar  210  may be formed using a second photolithography process and a second electric plating process. 
     Referring to  FIG. 7C , the first semiconductor chip  140 A may be attached to the third conductive pillar  210  using the chip adhesion layer  150  coated on the first semiconductor chip  140 A. The chip adhesion layer  150  may contact the heat spreading layer  110  by pressing the first semiconductor chip  140 A. The chip adhesion layer  150  may or may not remain between the first semiconductor chip  140 A and the third conductive pillar  210  depending on a pressing pressure against the first semiconductor chip  140 A. In some embodiments, after coating the chip adhesion layer  150  on the third conductive pillar  210  and the heat spreading layer  110 , the first semiconductor chip  140 A may be attached to the third conductive pillar  210 . 
     Thereafter, the same processes as described with reference to  FIGS. 61 to 6L  may be performed to complete the semiconductor package  200 A or  200 B shown in  FIG. 2A or 2B . 
       FIGS. 8A and 8B  are cross-sectional views illustrating a method of manufacturing semiconductor package according to an example embodiment. Hereinafter, differences between the present example embodiment and the example embodiment described with reference to  FIG. 7A to 7C  will be described. 
     Referring to  FIG. 8A , after performing the same processes as described with reference to  FIGS. 6A to 6D , a first portion  120 A of the first conductive pillar  120 , a first portion  130 - 1  of the shielding wall  130 , and the third conductive pillar  210  may be formed. The first portion  120 A of the first conductive pillar  120 , the first portion  130 - 1  of the shielding wall  130 , and the third conductive pillar  210  may be concurrently formed by a first photolithography process and a first electric plating process. 
     Referring to  FIG. 8B , a second portion  120 B of the first conductive pillar  120  and a second portion  130 - 2  of the shielding wall  130  may be concurrently formed on the first portion  120 A of the first conductive pillar  120  and the first portion  130 - 1  of the shielding wall  130 , respectively, by a second photolithography process and a second electric plating process. 
     Thereafter, the same processes as described with reference to  FIGS. 7C and 6I to 6L  may be performed to complete the semiconductor packages  200 A and  200 B shown in  FIG. 2A or 2B . 
     While the present inventive concepts have been shown and described with reference to some example embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made thereto without departing from the spirit and scope of the present inventive concepts as set forth by the following claims.