Patent Publication Number: US-6984563-B1

Title: Floating gate semiconductor component and method of manufacture

Description:
FIELD OF THE INVENTION 
     The present invention relates, in general, to a semiconductor component and, more particularly, to surface planarity within a semiconductor component. 
     BACKGROUND OF THE INVENTION 
     Semiconductor component manufacturers typically make a plurality of semiconductor components from a single semiconductor wafer. The number of integrated circuits that can be manufactured from the single semiconductor wafer ranges from one up to tens of thousands. Because integrated circuits are comprised of transistors or semiconductor devices, one technique for lowering their cost of manufacture is to shrink the transistor sizes, which in turn shrinks the integrated circuit sizes. Manufacturing costs are lowered because more integrated circuits can be manufactured from each semiconductor wafer. Another advantage of shrinking transistor sizes is that their operating speeds increase. 
     A drawback with shrinking transistors is that the surface of the semiconductor wafer becomes non-planar which may limit the resolution of the photolithography processes used in integrated circuit manufacture. Non-planar surfaces that arise during manufacture can create imperfections such as voids in layers subsequently formed over the non-planar surfaces. Voids degrade integrated circuit performance.  FIG. 1  illustrates a portion of a prior art Electrically Erasable and Programmable Read Only Memory (“EEPROM”)  10  during an intermediate stage of manufacture. EEPROM  10  comprises a semiconductor substrate  12  having a major surface  14  and Shallow Trench Isolation (“STI”) structures  16 A,  16 B, and  16 C. STI structure  16 A separates active regions  17 A and  17 B from each other, STI structure  16 B separates active regions  17 B and  17 C from each other, and isolation structure  16 C separates active regions  17 C and  17 D from each other. A layer of dielectric material  18  is formed on major surface  14 . Floating gates  20 ,  22 ,  24 , and  26  are disposed on portions of dielectric layer  18  and are spaced apart from each other. Preferably, floating gates  20 – 26  are formed over respective active regions  17 A– 17 D. Because of the small device sizes and the short distance between isolation structures, surface non-planarity may cause floating gates  20 – 26  to be misaligned. This misalignment decreases the reliability of EEPROM  10 . 
     Floating gates  22  and  26  are shown as being misaligned in  FIG. 1  such that floating gate  22  has an edge or side near an edge of isolation structure  16 B and floating gate  26  has an edge or side near an edge of isolation structure  16 C. An Oxide-Nitride-Oxide (“ONO”) dielectric structure  30  is formed on floating gates  20 – 26 . A layer of polysilicon  32  having a surface  34  is disposed on dielectric structure  30 . Although not shown for the sake of clarity, it should be understood that polysilicon layer  32  is patterned to serve as a word line of EEPROM  10 . The misalignment of floating gate  22  causes a portion of polysilicon layer  32  to be sufficiently close to one edge of floating gate  22  and isolation structure  16 B to stress it during operation. Likewise, the misalignment of floating gate  26  causes another portion of polysilicon layer  32  to be sufficiently close to one edge of floating gate  26  and isolation structure  16 C to stress it during operation. The increased stress decreases the reliability of the semiconductor component and may result in failure of EEPROM  10 . 
     Accordingly, what is needed is a semiconductor component and method for its manufacture that improves surface planarity and mitigates misalignment of structures such as floating gates. 
     SUMMARY OF THE INVENTION 
     The present invention satisfies the foregoing need by providing a floating gate semiconductor component having a planar surface on which a film can be formed and a method for manufacturing the floating gate semiconductor component. In accordance with one aspect, the present invention comprises providing a semiconductor substrate having an active region and an isolation structure. A first layer of dielectric material is formed on the semiconductor substrate. A first layer of semiconductor material is formed over the active region. A portion of the first layer of dielectric material is between the semiconductor substrate and the first layer of semiconductor material. A second layer of dielectric material is formed over the first layer of dielectric material and the isolation structure. The second layer of dielectric material is planarized. 
     In accordance with another aspect, the present invention comprises a method for manufacturing a memory element comprising providing a semiconductor substrate. A plurality of isolation structures are formed in the semiconductor substrate such that a first active region of the semiconductor substrate is between the first and second isolation structures of the plurality of isolation structures. A first finger of semiconductor material is formed over the first active region and dielectric material is disposed over the first finger and the first and second isolation structures. The dielectric material is planarized to have a substantially planar surface. An electrical isolation material is formed on the substantially planar surface. A layer of semiconductor material is formed over the electrical isolation material. 
     In accordance with yet another aspect, the present invention comprises a semiconductor component that includes a semiconductor substrate having a first active region between first and second isolation structures of the plurality of isolation structures. A first finger of semiconductor material is disposed over the first active region and a first dielectric material is disposed over the first finger and the first and second isolation structures. A second dielectric material is disposed on the first finger of semiconductor material. A layer of semiconductor material is disposed over the electrical isolation material. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present invention will be better understood from a reading of the following detailed description, taken in conjunction with the accompanying drawing figures, in which like reference numbers designate like elements and in which: 
         FIG. 1  is a cross-sectional side view of a portion of a prior art semiconductor component at an intermediate stage of manufacture; 
         FIG. 2  is a cross-sectional side view of the a semiconductor component at an early stage of manufacture in accordance with an embodiment of the present invention; 
         FIG. 3  is an isometric view of the semiconductor component of  FIG. 2  at a later stage of manufacture; 
         FIG. 4  is a cross-sectional side view of the semiconductor component of  FIG. 3  at a later stage of manufacture; 
         FIG. 5  is a cross-sectional side view of the semiconductor component of  FIG. 4  at a later stage of manufacture; and 
         FIG. 6  is an isometric view of the semiconductor component of  FIG. 5  at a later stage of manufacture. 
     
    
    
     DETAILED DESCRIPTION 
       FIG. 2  is a cross-sectional side view of a portion of a semiconductor component  100  during manufacture in accordance with an embodiment of the present invention. What is shown in  FIG. 2  is a substrate  102  having a major surface  104  and a plurality of Shallow Trench Isolation (STI) structures  106  formed therein. Techniques for forming STI structures  106  are known to those skilled in the art. Suitable materials for substrate  102  include silicon, silicon germanium, germanium, Silicon-On-Insulator (SOI), and the like. The semiconductor material may also be a semiconductor substrate having an epitaxial layer formed thereon. The conductivity type of substrate  102  is not a limitation of the present invention. In accordance with this embodiment, the conductivity type is chosen to form an N-channel insulated gate semiconductor device or transistor. However, the conductivity type can be selected to form a P-channel insulated gate semiconductor device or a complementary insulated gate semiconductor device, e.g., a Complementary Metal Oxide Semiconductor (CMOS) device. A layer of dielectric material  108  is formed on major surface  104 . Dielectric layer  108  serves as a gate dielectric material. By way of example, dielectric layer  108  is formed using thermal oxidation and has a thickness ranging from about 15 Å to about 500 Å. 
     A layer of polysilicon  110  is formed on dielectric layer  108  using, for example, a chemical vapor deposition technique. A suitable range of thicknesses for polysilicon layer  110  is from about 300 Å to about 2,000 Å. Layer  110  is not limited to being polysilicon. Other suitable materials for layer  110  include amorphous silicon, silicon carbide, gallium arsenide, indium phosphide, and the like. These materials may be monocrystalline or polycrystalline. A layer of photoresist is deposited on polysilicon layer  110  and patterned to form an etch mask layer  112 . 
     Referring now to  FIG. 3 , an isometric view of semiconductor component  100  is shown further along in processing. Polysilicon layer  110  is etched using an etch chemistry that preferentially etches polysilicon to form polysilicon fingers  114 ,  116 ,  118 , and  120  on dielectric layer  108 . By way of example, polysilicon layer  110  is etched using anisotropic Reactive Ion Etching (RIE). Methods for etching polysilicon are well known to those skilled in the art. After etching, etch mask layer  112  is removed. 
     Referring now to  FIG. 4 , a layer of dielectric material  130  having a thickness ranging from about 2500 Å to about 7500 Å is deposited on polysilicon fingers  114 – 120 , and the exposed portions of dielectric layer  108 . By way of example, dielectric material  130  is silicon dioxide formed by decomposition of tetraethylorthosilicate. 
     Referring now to  FIG. 5 , a cross-sectional side view of semiconductor component  100  is shown further along in manufacture. Dielectric material  130  is planarized using, for example, chemical mechanical planarization, leaving dielectric fingers or portions  132 ,  134 , and  136 . Portion  132  is between polysilicon fingers  114  and  116 , portion  134  is between polysilicon fingers  116  and  118 , and portion  136  is between polysilicon fingers  118  and  120 . The method of planarizing dielectric material  130  is not a limitation of the present invention. Other suitable planarization techniques include electropolishing, electrochemical polishing, chemical polishing, and chemical enhanced planarization. After planarization, the remaining portions of polysilicon fingers  114 – 120  and the remaining portions of dielectric material  130 , i.e., portions  132 ,  134 , and  136 , have a substantially contiguous planar surface  138 . 
     Still referring to  FIG. 5 , a dielectric material  140  is deposited on surface  138 , i.e., the surface formed from the remaining portions of polysilicon fingers  114 – 120  and portions  132 – 136  of dielectric material  130 . By way of example, dielectric material  140  is an Oxide-Nitride-Oxide (ONO) structure or stack having a thickness ranging from about 100 Å to about 200 Å. A layer of polysilicon material  142  having a thickness ranging from a monolayer of polysilicon to about 300 Å is formed on ONO structure  140 . By way of example, polysilicon layer  142  is formed using chemical vapor deposition. 
     Referring now to  FIG. 6 , an isometric view of semiconductor component  100  is shown further along in processing. A layer of photoresist (not shown) is patterned on polysilicon layer  142  to form an etch mask layer. Polysilicon layer  142 , ONO dielectric structure  140 , dielectric fingers  132 – 136 , and polysilicon fingers  114 – 120  are etched, respectively, to form floating gate devices  150 ,  152 ,  154 ,  156 ,  160 ,  162 ,  164 , and  166 , and word lines  142 A and  142 B. By way of example, polysilicon layer  142  is etched using anisotropic Reactive Ion Etching (RIE) to form word lines  142 A and  142 B. After etching polysilicon layer  142 , the etch chemistry is modified to etch ONO structure  140 . After etching ONO structure  140 , the etch chemistry is again modified to etch polysilicon fingers  114 ,  116 ,  118 , and  120  to form floating gate devices  150 ,  152 ,  154 ,  156 ,  160 ,  162 ,  164 , and  166 . The etch mask layer is removed and semiconductor component  100  is annealed. 
     Although not shown, it should be understood that semiconductor component  100  may undergo further processing such as, for example, formation of metal contacts and formation of a metallization system. 
     By now it should be appreciated that a semiconductor component having floating gates and a method for manufacturing the semiconductor component have been provided. An advantage of the present invention is that the regions between the floating gates is filled with a dielectric material, which can be planarized to form a contiguous planar surface with the surface of the control gates. Thus, films deposited on the contiguous surface are sufficiently separated from the underlying structures to reduce the probability of the semiconductor components failing for reliability reasons. In addition, the dielectric material cooperates with the floating gates to form a planar surface on which subsequent films or material layers can be deposited. The planar surface reduces depth of focus and overlay problems during the photolithographic steps. 
     Although certain preferred embodiments and methods have been disclosed herein, it will be apparent from the foregoing disclosure to those skilled in the art that variations and modifications of such embodiments and methods may be made without departing from the spirit and scope of the invention. It is intended that the invention shall be limited only to the extent required by the appended claims and the rules and principles of applicable law.