Patent Publication Number: US-2013239074-A1

Title: Apparatus, method and medium storing program for designing semiconductor integrated circuit

Description:
CROSS REFERENCE TO RELATED APPLICATION(S) 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2012-50202, filed on Mar. 7, 2012, the entire contents of which are incorporated herein by reference. 
     FIELD 
     Embodiments described herein relate generally to an apparatus for designing a semiconductor integrated circuit, a computer-implemented method for designing the semiconductor integrated circuit and a medium storing a computer program for designing the semiconductor integrated circuit. 
     BACKGROUND 
     Generally, in designing a semiconductor integrated circuit, layout data is generated and a test is performed based on the layout data. 
     A scan test is well known as a method for testing the semiconductor integrated circuit. Nowadays a compression scan test that is of an application of the scan test is used. The compression scan test is performed using a scan test module incorporated in the semiconductor integrated circuit. The scan test module is a combination of a scan chain and a compression scan circuit. The compression scan circuit includes a decompressor and a compressor. One end of each of the decompressor and the compressor is connected to an external circuit (for example, semiconductor inspection apparatus) of the semiconductor integrated circuit. The other end of each of the decompressor and the compressor is connected to the scan chain. The scan chain is classified into groups (hereinafter referred to as “functional groups”) in each functional block. The compression scan circuit is disposed outside or inside the functional group. 
     However, in generating the layout data, when a cell position in the semiconductor integrated circuit is determined in a unit of functional group, positional relationship between cells, which relates to an operation signal of the semiconductor integrated circuit, is considered but positional relationship between cells, which relates to a scan signal for the scan test to be added, is not considered. In other words, when the cell position in the semiconductor integrated circuit is determined, an operation of the semiconductor integrated circuit is considered but the scan test is not considered in determination of the cell position. 
     Accordingly, a distance between the scan chain and the compression scan circuit is lengthened in the semiconductor integrated circuit, which is obtained based on the layout data. As a result, a wire length of a wire (hereinafter referred to as a “scan wire”) connecting the scan chain and the compression scan circuit increases, which obstructs integration of the semiconductor integrated circuit. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a block diagram illustrating a configuration of a design apparatus  1  of the embodiment. 
         FIG. 2  is a flowchart of the designing process of the embodiment. 
         FIG. 3A  is a configuration diagram of the semiconductor integrated circuit corresponding to the first net list obtained in S 104  of the embodiment. 
         FIG. 3B  is an enlarged view of a region surrounded by a broken line A in  FIG. 3A . 
         FIG. 4  is a flowchart of changing the compression logic (S 110 ) of the embodiment. 
         FIG. 5  is a schematic diagram of the compression pattern table obtained by calculating the total wire length (S 110 - 4 ) of the embodiment. 
         FIG. 6  is a configuration diagram of the semiconductor integrated circuit corresponding to the second net list obtained in changing of the net list (S 110 - 8 ) of the embodiment. 
         FIG. 7  is a schematic diagram of a semiconductor integrated circuit LSI corresponding to layout data obtained in the comparative example of the embodiment. 
         FIG. 8  is a schematic diagram of the semiconductor integrated circuit LSI corresponding to the layout data obtained through the designing process of the embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments will now be explained with reference to the accompanying drawings. 
     In general, according to one embodiment, a designing apparatus includes a register position determining module, a net list generator, and a layout data generator. The register position determining module determines a register position on a layout of a semiconductor integrated circuit from a hardware description. The net list generator generates a net list according to the register position. The layout data generator generates layout data based on the net list. The layout data indicates the layout of the semiconductor integrated circuit. 
     A configuration of a design apparatus according to an embodiment will be described.  FIG. 1  is a block diagram illustrating a configuration of a design apparatus  1  of the embodiment. 
     As illustrated in  FIG. 1 , the design apparatus  1  includes a computer  10 , a memory  30 , and a display  50 . A design program is stored in the memory  30 . The design program means a program that causes the computer  10  to perform a designing process of the embodiment. 
     The computer  10  activates the design program to implement a logic synthesizer  11 , a compression logic generator  12 , a scan synthesizer  13 , a scan rule checker  14 , a register position determining module  15 , a compression logic changer  16 , and a layout data generator  17 . Each module of the computer  10  is described later. For example, the computer  10  is a CPU (Central Processing Unit). 
     Not only the design program but also various pieces of data necessary for the designing process are stored in the memory  30 . For example, the data necessary for the designing process is a Register Transfer Level (hereinafter referred to as an “RTL”) description. The RTL description means data indicating a register-level operation of the semiconductor integrated circuit to be designed. 
     The display  50  displays an image indicating a processing result of the computer  10 . For example, the display  50  is an LCD (Liquid Crystal Display). 
     An operation of the design apparatus of the embodiment will be described below.  FIG. 2  is a flowchart of the designing process of the embodiment. 
     &lt;S 100 &gt; The logic synthesizer  11  performs logic synthesis with respect to the RTL description to generate a hardware description. The hardware description means data indicating a configuration (for example, a register array) of the semiconductor integrated circuit, which implements the operation indicated by the RTL description. For example, the hardware description is an HDL (Hardware Description Language) description.
 
&lt;S 102 &gt; The compression logic generator  12  adds a compression scan description indicating a compression scan circuit and a decompression scan description indicating a decompression scan circuit to the hardware description obtained in S 100 . The compression scan circuit aggregates scan wires connected to plural registers in order to compress a test pattern size of the semiconductor integrated circuit. The decompression scan description can be omitted.
 
&lt;S 104 &gt; The scan synthesizer  13  performs scan synthesis with respect to the hardware description (that is, the hardware description includes at least the compression scan description) obtained in S 102  to generate a first net list. The first net list means data indicating inter-terminal connection (for example, connection between two registers) of the configuration of the semiconductor integrated circuit corresponding to the hardware description obtained in S 102 . For example, the scan synthesizer  13  rewrites the hardware description such that a scan chain is constituted in each functional group in the semiconductor integrated circuit corresponding to the hardware description obtained in S 102 . Therefore, the first net list is obtained.  FIG. 3  is a configuration diagram of the semiconductor integrated circuit corresponding to the first net list obtained in S 104  of the embodiment.
 
     As illustrated in  FIG. 3A , a semiconductor integrated circuit LSI corresponding to the first net list includes plural registers REG, a compression scan circuit COM, and a decompression scan circuit DCOM. 
       FIG. 3B  is an enlarged view of a region surrounded by a broken line A in  FIG. 3A . As illustrated in  FIG. 3B , the registers REG constitute scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3 . 
     The scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  are aggregated in each functional block (functional blocks BLKa and BLkb). Therefore, the scan chains SCa 1  to SCa 3  constitute the functional block BLKa and the scan chains SCb 1  to SCb 3  constitute the functional block BLKb. 
     The compression scan circuit COM includes plural compressors CM 1 , CM 2 , and SP. For example, the compressors CM 1 , CM 2 , and SP are XOR elements. 
     The compressor CM 1  is a module that aggregates the functional block BLKa (that is, the compressor CM 1  integrates the scan wires connected to the scan chains SCa 1  to SCa 3 ). The compressor CM 2  is a module that aggregates the functional block BLKb (that is, the compressor CM 2  integrates the scan wire connected to the scan chains SCb 1  to SCb 3 ). The compressor SP is a module that further compresses outputs of the compressors CM 1  and CM 2  and outputs the compressed outputs. 
     &lt;S 106 &gt; Based on an operation constraint of the semiconductor integrated circuit, the scan rule checker  14  checks whether the semiconductor integrated circuit corresponding to the first net list satisfies the operation constraint. When the semiconductor integrated circuit does not satisfy the operation constraint, S 100  to S 104  are performed again after at least one of the RTL description and the hardware description is corrected.
 
&lt;S 108 &gt; Based on the first net list, the register position determining module  15  determines a register position on a layout of the semiconductor integrated circuit from the hardware description.
 
&lt;S 110 &gt; The compression logic changer  16  changes a compression logic. In changing the compression logic, based on the register position, the compression logic changer  16  changes the configuration (for example, a connection relationship between the compressor and the scan chain) of the compression scan circuit COM such that a total wire length of the scan wires in the semiconductor integrated circuit LSI is shortened, and then the compression logic changer  16  generates a second net list. The second net list means data indicating a relationship of inter-terminal connection (for example, connection between two registers) of the configuration of the semiconductor integrated circuit corresponding to the configuration of the post-change compression scan circuit COM.  FIG. 4  is a flowchart of changing the compression logic (S 110 ) of the embodiment.
 
&lt;S 110 - 2 &gt; The compression logic changer  16  generates a compression pattern in each combination of the compressors CM 1  and CM 2  and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3 
 
&lt;S 110 - 4 &gt; The compression logic changer  16  calculates the total wire length in each compression pattern generated in S 110 - 2 , and generates a compression pattern table. For example, the compression logic changer  16  calculates the total wire length in each compression pattern based on positional information indicating positions of the compressors CM 1  and CM 2  and positional information indicating positions of the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  in the resister position determined in S 108 . Therefore, the compression pattern table is obtained.  FIG. 5  is a schematic diagram of the compression pattern table obtained by calculating the total wire length (S 110 - 4 ) of the embodiment.
 
     As illustrated in  FIG. 5 , the compression pattern table includes items of “compressing pattern ID”, “compressor CM 1 ,” “compressor CM 2 ,” and “total wire length.” The “compressing pattern ID” indicates unique information in each compression pattern. The “compressor CM 1 ” and the “compressor CM 2 ” indicate the scan chains that are connected to the compressors CM 1  and CM 2 , respectively. The “total wire length” indicates the total of wire lengths in each compression pattern. For example, the “total wire length” of L 2  corresponding to the “compressing pattern ID” of 2 indicates the total of the wire lengths connecting the compressor CM 1  with the scan chains SCa 1 , SCa 3 , SCb 2 , and SCb 3  and the wire lengths connecting the compressor CM 2  with the scan chains SCa 2  and SCb 1 . The “compressing pattern ID” of 0 corresponds to the compression pattern before changing the compression logic (S 110 ), namely, the compression pattern (see  FIG. 3B ) obtained in the scan synthesis (S 104 ). 
     &lt;S 110 - 6 &gt; The compression logic changer  16  selects the compression pattern (hereinafter referred to as an “optimal compression pattern”) whose total wire length is the shortest of the total wire lengths in each compression pattern which are calculated in S 110 - 4 . For example, in the case that the total wire length L 2  in  FIG. 5  is shorter than the total wire lengths L 0  and L 1 , the compression logic changer  16  selects the compression pattern corresponding to the “compressing pattern ID” of 2 as the optimal compression pattern.
 
&lt;S 110 - 8 &gt; The compression logic changer  16  generates the second net list based on the optimal compression pattern selected in S 110 - 6 .  FIG. 6  is a configuration diagram of the semiconductor integrated circuit corresponding to the second net list obtained in changing of the net list (S 110 - 8 ) of the embodiment.
 
     As illustrated in  FIG. 6 , in the semiconductor integrated circuit LSI corresponding to the second net list, the compressor CM 1  is connected to the scan chains SCa 1 , SCa 3 , SCb 2 , and SCb 3 , the compressor CM 2  is connected to the scan chains SCa 2  and SCb 1 , and the compressor SP is connected to the compressors CM 1  and CM 2 . The “total wire length” of L 2  between the compressors CM 1  and CM 2  and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  in  FIG. 6  is shorter than the total wire length L 0  between the compressors CM 1  and CM 2  and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  in  FIG. 3 . 
     &lt;S 112 &gt; The layout data generator  17  generates layout data based on the second net list, and outputs the layout data to the display  50 . The layout data means data indicating a layout (for example, layouts of the compressor CM 1  and CM 2  and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3 ) of the semiconductor integrated circuit LSI corresponding to the second net list. 
     A comparative example of the embodiment will be described.  FIG. 7  is a schematic diagram of a semiconductor integrated circuit LSI corresponding to layout data obtained in the comparative example of the embodiment.  FIG. 8  is a schematic diagram of the semiconductor integrated circuit LSI corresponding to the layout data obtained through the designing process of the embodiment. 
     As illustrated in  FIG. 7 , in the layout data obtained through a general designing process, the wire lengths of the scan wires between the compression scan circuit COM and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  increase, and the congestion of the scan wires is deteriorated (see a broken line B 1  in  FIG. 7 ). This is because, in the general designing process, the layout data is generated from the net list (corresponding to the first net list of the embodiment), which is obtained by rewriting the hardware description, such that the scan chain is constituted, in each functional group. 
     On the other hand, as illustrated in  FIG. 8 , in the layout data obtained through the designing process of the embodiment, the wire lengths of the scan wires between the compression scan circuit COM and the scan chains SCa 1  to SCa 3  and SCb 1  to SCb 3  decrease, and the congestion of the scan wires is improved, compared with the semiconductor integrated circuit LSI in  FIG. 7  (see a broken line B 2  in  FIG. 8 ). This is because, in the designing process of the embodiment, the layout data is generated from the net list (that is, the second net list of the embodiment) based on the positional information of the modules of the semiconductor integrated circuit LSI. 
     At least a portion of the design apparatus  1  according to the above-described embodiments may be composed of hardware or software. When at least a portion of the design apparatus  1  is composed of software, a program for executing at least some functions of the design apparatus  1  may be stored in a recording medium, such as a flexible disk or a CD-ROM, and a computer may read and execute the program. The recording medium is not limited to a removable recording medium, such as a magnetic disk or an optical disk, but it may be a fixed recording medium, such as a hard disk or a memory. 
     In addition, the program for executing at least some functions of the design apparatus  1  according to the above-described embodiment may be distributed through a communication line (which includes wireless communication) such as the Internet. In addition, the program may be encoded, modulated, or compressed and then distributed by wired communication or wireless communication such as the Internet. Alternatively, the program may be stored in a recording medium, and the recording medium having the program stored therein may be distributed. 
     While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.