Patent Publication Number: US-6707335-B2

Title: Control method of charge-pump circuit

Description:
BACKGROUND OF THE INVENTION 
     The present invention relates to a charge-pump circuit outputting converted voltage in increments of less than a power supply voltage Vdd, and a control method thereof, particularly a control method of a charge-pump circuit capable of normal charge-pumping operation removing influence of a parasitic diode associated with a charge transfer device. 
     The charge-pump circuit devised by J. F. Dickson generates higher voltage than power supply voltage Vdd of an LSI chip by connecting plural stages of the pumping packet in series to boost the voltage. For example, it is used for generating voltage for program/erase of flash memories. 
     However, the conventional charge-pump circuit carries out voltage conversion in increments of the power source voltage Vdd, and a circuit capable of carrying out voltage conversion in increments of less than the power supply voltage Vdd had not yet been proposed. Efficiency of the power supply circuit can be significantly improved, if a voltage boosting in increments of e.g. 0.5 Vdd is realized. 
     So, the inventor has already proposed a charge-pump circuit capable of carrying out voltage conversion in increments of less than the power supply voltage Vdd and improving efficiency η of the circuit (U.S. patent application Ser. No. 09/732,944 filed on Dec. 8, 2000). 
     The outline thereof will be described below. FIG.  9  and FIG. 10 are circuit diagrams showing a circuitry and operation of +0.5 Vdd voltage boosting charge-pump circuit. The charge-pump circuit generates a boosted voltage of 1.5 Vdd from an input voltage Vdd. 
     Diodes D 1  and D 2  (charge transfer devices) are connected in series. The power supply voltage Vdd is provided as an input voltage Vin to an anode of the diode D 1 . Each of the diodes D 1  and D 2  can be realized with a MOS transistor with its gate and drain connected together. Switches S 1 , S 2  and S 3  connect two capacitors  1  and  2  to a connecting point between the diodes D 1  and D 2 , alternating between in parallel and in series. 
     The switches S 1 , S 2  and S 3  can be implemented with MOS transistors. A clock driver  3  provides the capacitors  1  and  2  with clock CLK. An output of the clock driver  3  is connected to one of the terminals of the capacitor  2 . A power supply voltage to the clock driver  3  is Vdd, and amplitude of the clock is Vdd. The clock driver can be implemented with two stages of CMOS inverters for example. 
     The boosted voltage outputted from the diode D 2  is supplied to a load  4 . The output node of the diode D 2  has a capacitance CL. 
     Next, the operation of the charge-pump circuit will be explained referring to the FIGS. 9,  10  and  11 . FIG. 11 is an operating waveform chart of the charge-pump circuit. For the sake of simplicity, a voltage drop VF of the diode D 1  and D 2  is assumed 0 V, and the capacitances of the condensers C 1  and C 2  are assumed equal. 
     When input clock CLK of the clock driver  3  is at low level (CLK=Low), and assuming that S 1  is OFF, S 2  is ON and S 3  is OFF, two capacitors  1  and  2  are connected in series to a connecting node (pumping node) between the diodes D 1  and D 2 , as shown in FIG.  9 . Thus the voltage at the connecting node V1 is Vdd and each of the capacitors  1  and  2  are charged to 0.5 Vdd respectively. 
     At this time, a current lout from the power supply Vdd flows through the diode D 1 , and into the capacitors  1  and  2 . The same current lout flows into the clock driver  3 . 
     Next, as shown in FIG. 10, the input clock of the clock driver  3  changes to high (CLK=High), and the switches turn to S 1 =ON, S 2 =OFF and S 3 =ON. Thus the two capacitors  1  and  2  are connected to the connecting node of the diodes D 1  and D 2  in parallel. Since the voltage of each of the capacitors  1  and  2  is Vdd/2 and the output voltage of the clock driver  3  is Vdd, the voltage V1 at the connecting node (pumping node) between the diode D 1  and D 2  is boosted to 1.5 Vdd. 
     At this time, a current which flows from the two capacitors  1  and  2  to the diode D 2  is 2 Iout, and the same amount of current 2 Iout flows out from the clock driver  3 . 
     Followings stand in a steady state, assuming that the output current from the diode D 2  is steady at 2 Iout, and taking average current over time for each current. 
     1) Vout=1.5 Vdd where the power supply voltage of the driver is Vdd. 
     2) Input current=0.5 Iout 
     3) Current from the power supply Vdd of the clock driver=Iout. 
     An important point of this embodiment of the charge pump circuit is that the boosting in increments of 0.5 Vdd is done by repeating charging the capacitors  1  and  2  connected in series and discharging them connected in parallel. It is also important that the input current Iin=Iout from the power supply Vdd is a ½ of the output current 2 Iout. Because of this, the theoretical efficiency η of the circuit can be 100% and there is no loss in boosting to 1.5 Vdd, when no regulation is made on the output voltage. 
     The input current is a sum of 2 Iout while CLK=H and Iout while CLK=L. Thus, 
     the efficiency η of the charge-pump circuit 
     =output power/input power 
     =(1+0.5)·Vdd·Iout/Vdd·(1+0.5)·Iout 
     =1=100% 
     Therefore, the charge-pump circuit described above can be regarded in effect as a 0.5 stage charge-pump circuit. And the efficiency η of the circuit can be made 100%. The voltage of 0.5 Vdd can be generated by other methods, for example by a resistance voltage divider. However, it can not realize the efficiency η of 100%, being a certain power loss inherent in it. 
     On the other hand, the power loss can be made 0% theoretically with the charge-pump circuit proposed by the inventor, since the connection of the capacitors are alternated between series and parallel in accordance with the level of the clock CLK. 
     If the two capacitors  1  and  2  are kept in series (S 1 =OFF, S 2 =ON, S 3 =OFF) during the operation regardless of the level of the clock CLK, then the circuit operates in the same way as the conventional charge-pump resulting in Vout=2 Vdd. In this case, a switch control circuit (not shown) provides the switches S 1 , S 2  and S 3  with the switch control signal whether to keep the capacitors  1  and  2  always in series or to alternate between series and parallel in accordance with the level of the clock CLK. 
     That is to say, the charge-pump circuit of the embodiment can generate either 1.5 Vdd or 2 Vdd. In other words, it can be switched between 0.5 stage and 1 stage charge-pump. 
     However, a detailed examination by the inventor had proved that a malfunction occurs in the transition from the status of the FIG. 9 to the status of the FIG. 10 as well as in the reverse transition, if the timing to switch the S 1 , S 3  and S 3  is not aligned properly. 
     For example, in the transition from the status of the FIG. 9 to the status of the FIG. 10, the voltage V1 at the connection between the diodes D 1  and D 2  becomes 2 Vdd, if the clock CLK is changed from L level to H level while the switch S 2  is ON. 
     Also, in the transition from the status of the FIG. 10 to the status of the FIG. 9, the voltage V1 at the connection between the diodes D 1  and D 2  becomes 0.5 Vdd, if the clock CLK is changed from H level to L level while the switches S 1  and S 3  are ON. 
     SUMMARY OF THE INVENTION 
     An object of the invention is to prevent the malfunctioning of the charge-pump circuit which boosts a voltage in increments of less than the power supply voltage Vdd. 
     A control method of the charge-pump circuit of this invention is to align the timing of the change in the clock CLK and the switching of the S 1 , S 2  and S 3 . The control is done in steps {circle around (1)}-{circle around (7)} described below. 
     {circle around (1)} The switch S 2  (the first switching means) is turned ON to connect the capacitors  1  and  2  in series while the clock CLK is at L level. 
     {circle around (2)} The switch S 2  is turned OFF. 
     {circle around (3)} The clock CLK is changed to H level. 
     {circle around (4)} The switches S 1  and S 3  (the second switching means) are turned ON to connect the capacitors  1  and  2  in parallel. 
     {circle around (5)} The switches S 1  and S 3  are turned OFF. 
     {circle around (6)} The clock CLK is changed to L level. 
     {circle around (7)} Repeat the steps {circle around (1)} through {circle around (6)}. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram showing a control method of the charge-pump circuit according to an embodiment of the invention. 
     FIG. 2 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 3 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 4 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 5 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 6 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 7 is a timing chart showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 8 is a circuit diagram showing the control method of the charge-pump circuit according to the embodiment of the invention. 
     FIG. 9 is a circuit diagram showing a circuitry and an operation of the conventional charge-pump circuit. 
     FIG. 10 is a circuit diagram showing the circuitry and the operation of the conventional charge-pump circuit. 
     FIG. 11 is a waveform chart showing the operation of the conventional charge-pump circuit. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An embodiment of the invention will be described below with reference to the drawings. FIG.  1  through FIG. 6 are circuit diagrams showing circuitry and operation of the charge-pump circuit outputting +0.5 Vdd boosted voltage. The charge-pump circuit generates 1.5 Vdd for the input voltage Vdd. 
     Explanation of the circuitry of the charge-pump is omitted since it is the same as one shown in FIG.  9  and FIG.  10 . Although the charge transfer devices are shown as diodes, it is possible to replace them with MOS transistors. 
     A control method of the charge-pump circuit having the above-mentioned circuitry will be described below, referring to FIG.  1  through FIG.  7 . FIG. 7 is a first timing chart to describe the control method of the charge-pump circuit. 
     It is assumed that a supply voltage to the clock driver  3  is Vdd, the same voltage as the input voltage (5 V for example), and that capacitances of the capacitor  1  and  2  are equal. It is further assumed that voltage drops caused by the diode D 1  and D 2  (charge transfer device) and by the switch S 1 , S 2  and S 3  are zero. Switching control of S 1 , S 2  and S 3  is done by a control circuit, which is not shown. 
     (1) First Control Step 
     At time t1, the switch S 2  is turned ON (the switches S 1  and S 3  are OFF), while the input clock CLK to the clock driver  3  is at L level. With this, the two capacitors  1  and  2  are connected to the pumping node in series. Thus the capacitors  1  and  2  are charged to 0.5 Vss respectively, and the voltage V1 at the pumping node becomes Vdd. As shown in the FIG. 1, VA=VB=0.5 Vdd and VC=0 V. Input current Iout flows through the diode D 1 , and Iout flows into the clock driver  3  (Refer to FIGS.  1  and  7 ). As shown in the figure, VA is a voltage at the connecting node between the capacitor C 1  and the switch S 2 , VB is a voltage at a connecting node between the switch S 2  and the capacitor  2  and VC is a voltage at a connecting node between output of the clock driver  3  and the capacitor  2 . 
     (2) Second Control Step 
     Next, at time t2, the switch S 2  is turned OFF, while the clock CLK is at L level. With this, all of the switches S 1 , S 2  and S 3  are OFF, and the voltage at each of the nodes are kept unchanged (Refer to FIG.  2  and FIG.  7 ). 
     (3) Third Control Step 
     Next, at time t3, the clock CLK is changed to H level (CLK=H) from L level, while all of the switches S 1 , S 2  and S 3  are kept OFF. (Refer to FIG.  3  and FIG.  7 ). 
     (4) Fourth Control Step 
     Next, at time t4, the switches S 1  and S 3  are turned ON to connect the capacitors  1  and  2  to the pumping node in parallel. Thus the voltage V1 at the pumping node changes to 1.5 Vdd. At this time, VA=Vdd and VB=1.5 Vdd, and current 2 Iout flows from the clock driver  3  into the capacitors  1  and  2 , and the same amount of current 2 Iout flows through the diode D 2  (Refer to FIG.  4  and FIG. 7) 
     (5) Fifth Control Step 
     Next, at time t5, the switches S 1  and S 3  are turned OFF, while the clock CLK is kept at H level. With this, all of the switches S 1 , S 2  and S 3  are turned OFF and the voltage at each of the nodes is kept unchanged (Refer to FIG.  5  and FIG.  7 ). 
     (6) Sixth Control Step 
     Next, at time t6, the clock CLK is changed from H level to L level, while all of the switches S 1 , S 2  and S 3  are OFF (Refer to FIG.  6  and FIG.  7 ). 
     After that, returning to the above-mentioned first control step, the first through sixth steps are repeated. 
     According to the above-mentioned control method, the malfunction of the charge-pump circuit is prevented, since the voltage V1 at the pumping node varies only between Vdd and 1.5 Vdd, as a result of the alignment made to the timing of the change in the clock CLK and to the timing of the switching of S 1 , S 2  and S 3 . 
     Although the embodiment shows an example applied to a single stage charge-pump which outputs +0.5 Vdd boosted voltage, the invention can be applied to a double stage charge-pump circuit which outputs +1.5 Vdd boosted voltage by increasing the number of the stages of the charge-pump. 
     In general, the invention can be applied to a multi-stage charge-pump circuit, which incorporates the charge-pump circuit of the embodiment as a core. 
     The multi-stage charge-pump circuit takes a structure with the first stage charge-pump circuit outputting e.g. 0.5 Vdd, and the second and higher stages of Dickson type conventional charge-pump circuits, as shown in FIG.  8 . In the case of the charge-pump circuit shown in FIG. 8, the output voltage Vout is 3.5 Vdd. 
     Although the charge-pump circuit of the embodiment generates the boosted voltage in increments of 0.5 Vdd by changing the connection of the two capacitors  1  and  2  alternating between series and parallel, it is also possible to generate the boosted voltage in increments of less than 0.5 Vdd by changing connection of more than two capacitors alternating between series and parallel. The present invention is also applicable to such a charge-pump circuit. 
     In the charge-pump circuit which boost a voltage in increments of less than the power supply voltage by alternately connecting capacitors to the pumping node in series and in parallel, the control method of the charge-pump circuit of this invention prevents the pumping node voltage from transient abnormal voltage. The effect of the invention is keeping the operation of the charge-pump normal as well as improving the power efficiency.