Patent Publication Number: US-2004046879-A1

Title: Solid state image pickup apparatus

Description:
[0001] This application is a continuation-in-part of (1) application Ser. No. 314,275, filed Feb. 23, 1989, which is a continuation of application Ser. No. 929,892, filed Nov. 13, 1986, now abandoned; and (2) application Ser. No. 460,012, filed Jan. 2, 1990 which is a continuation of application Ser. No. 096,534, filed Sep. 14, 1987, now U.S. Pat. No. 4,914,519, issued Apr. 3, 1990. 
    
    
     
       BACKGROUND OF THE INVENTION  
       [0002] 1. Field of the Invention  
       [0003] The present invention relates to a solid state image pickup apparatus and, more particularly, to a solid state image pickup apparatus having a plurality of photoelectric transducer elements each having a capacitor electrode on a control electrode region of a corresponding semiconductor transistor.  
       [0004] The present invention also relates to a solid state image pickup apparatus for selectively reading out a plurality of sensor signals and, more particularly, to a solid state image pickup apparatus capable of eliminating unnecessary components such as variations in dark signals and drive noise.  
       [0005] 2. Related Background Art  
       [0006] A TV or SV camera with an image sensor such as a CCD or MOS sensor has an aperture mechanism. Photoelectric transducer apparatuses each having a TV or SV camera with an automatic aperture mechanism are described in Japanese Patent Disclosure (Kokai) Nos. 12759/1985 to 12765/1985.  
       [0007] This photoelectric transducer apparatus includes a photosensor having a plurality of sensor cells each having a capacitor formed on a control electrode of a corresponding semiconductor transistor.  
       [0008] In the conventional photoelectric transducer apparatus described above, noise is often mixed in an output signal read out from the photosensor cells due to variations in dark voltage generated in the cells with arbitrary store time.  
       [0009] An output signal corresponding to the dark current component generated within the photosensor cell is prestored as reference optical information in an external memory in a conventional apparatus. A reference output signal derived from the reference optical information and an output signal from the actual optical information read out from the photosensor cell are compared with each other, and the output signal of the actual optical information is corrected, thereby eliminating the noise component caused by the dark voltage.  
       [0010] In the conventional photoelectric transducer apparatus described above, in order to constitute a photoelectric transducer system, the resultant system is undesirably complicated since a separate external circuit including a noise removal memory is required.  
       [0011] When a conventional photoelectric transducer apparatus is applied to a video camera or the like, the following problem occurs. When photoelectric transducer cells are arranged in a two-dimensional matrix and scanned in the vertical and horizontal directions, holes are stored in the base of each photoelectric transducer cell in a store mode upon reception of strong light. The base potential is forward-biased with respect to the emitter potential. The potential of a vertical line connected to the emitter electrode of each photoelectric transducer cell receiving strong light is increased to cause a blooming phenomenon. In order to prevent this, it is proposed that the vertical lines are grounded for a period excluding the readout operation, thereby refreshing the charge overflowed onto the vertical line. However, the vertical line can be grounded for only the horizontal blanking period, i.e., about 10 μs. Therefore, the charge overflowed onto the vertical line during the horizontal scanning period still causes the blooming phenomenon.  
       [0012] In the readout mode, when made signals are sequentially output by horizontal scanning after they are stored in a vertical line, a dummy signal is generated during the store of the signal in the vertical line. In other words, a smear phenomenon occurs.  
       [0013] In addition, the period for performing the refresh operation in the conventional apparatus is about 10 μs in the horizontal blanking period. The refresh time is short to result in incomplete refreshing and hence an after image phenomenon.  
       [0014] Furthermore, assume that when the conventional photoelectric transducer apparatus is used as a single-plate type solid-state imaging device in a color television video camera, color filters are deposited or adhered onto the pixels. If an alignment scheme such as a Bayer alignment is used to form vertical lines in units of colors, i.e., R, G, and B, at least to vertical lines are required for the pixels of each column. In this case, since the vertical line portion does not serve as the photosensitive portion, the light-receiving area is reduced by the two vertical lines for each column. In other words, the opening of the aperture is undesirably reduced.  
       [0015] In a conventional photosensitive transducer apparatus, negative and positive voltages are required to bias an output amplifier, and the constitution is thus complicated. It is difficult to read out the signal component without degrading the frequency characteristics.  
       [0016]FIG. 15A is a schematic circuit diagram of a conventional solid-state image pickup apparatus.  
       [0017] Referring to FIG. 15A, signals from sensors S 1  to Sn are respectively amplified by amplifiers A 1  and An, and transistors T 1  to Tn are sequentially turned on. A dot sequential output appears on an output line  101 A. The dot sequential signal is amplified by a buffer amplifier  102 A, and the resultant signal appears as an output signal Vout.  
       [0018] In the conventional image pickup apparatus described above, variations in input/output characteristics of the amplifiers A 1  to An are included in the sensor signals as the dot sequential output appearing on the output line  101 A. As a result, steady pattern noise undesirably occurs.  
       [0019]FIG. 15B shows a schematic arrangement of another conventional photoelectric transducer apparatus.  
       [0020] Referring to FIG. 15B, signals read out from photosensors S 1  to Sn are temporarily stored in storage capacitors C 1  to Cn. Transistors T 1  to Tn are sequentially turned on at timings of a scanning circuit SH, and the readout signals sequentially appear on an output line  101 A and are output to an external device through an amplifier  102 A.  
       [0021] In the above photoelectric transducer apparatus, however, unnecessary components such as dark signals and drive noise of the photosensors are undesirably included.  
       [0022] Drive noise is defined as noise generated when a photosensor is driven to read out a signal. The drive noise components are noise caused by manufacture variations such as element shapes and smear caused by element-isolation and depending on radiation amounts.  
       [0023] The dark signal is defined as a dark current of a photosensor and greatly depends on accumulation time and temperature of the photosensor.  
       [0024] This drive noise will be described in detail. Variations in drive capacity of a drive element for driving a photoelectric transducer element and variations in capacity of a photoelectric transducer element cause variations in leakage component of drive pulses. These variation components as an information signal are superposed on a necessary photoelectric transducer signal and are read out. The cause of generation of drive noise will be described below.  
       [0025]FIG. 15C is a schematic view of a photoelectric transducer element described in Japanese Patent Laid-Open Gazette No. 12764/1985, FIG. 15D is a timing chart of drive pulses for driving the photoelectric transducer element shown in FIG. 15C, and FIG. 15E is a chart showing the base potential of the photoelectric transducer element.  
       [0026] Referring to FIG. 15C, the photoelectric transducer element includes a base accumulation type bipolar transistor B, a drive capacitor Cox for reverse- or forward-biasing the transistor B in response to a drive pulse ør, and a refresh transistor Qr. The transistor B has junction capacitances Cbc and Cbe. It should be noted that Cox, Cbc, and Cbe are referred to as capacitances or capacitors hereinafter, as needed. The capacitances Cox, Cbc, and Cbe are added to obtain a charge storage capacitance Ctot.  
       [0027] The operation of the photoelectric transducer element will be described below.  
       [0028] Assume that the initial value of a base potential VB is given as V0. When the drive pulse ør is set at a potential Vør at time t1, a voltage Va is applied to the base of the transistor B through the drive capacitor Cox. In this case, the voltage Va can be represented as follows:  
                   Va   =              Cox   /     (     Cox   +   Cbc   +   Cbe     )       ×   V                 φ                 r                 =              (     Cox   /   Ctot     )     ×   V                 φ                 r                   (   1   )                       
 
       [0029] When the drive pulse ørh is set at a high potential at time t2, a transistor Qr is turned on.  
       [0030] When the transistor B is forward-biased, the base potential VB is abruptly decreased. A time interval TC between time t2 and time t3 is a so-called refresh time interval.  
       [0031] The drive pulse ør is set at zero at time t3, and a voltage −Va is added to the base voltage VB, so that the base voltage VB is set at V2. This reverse-biased state is the accumulation state.  
       [0032] The above description was confined to one photoelectric transducer element. However, a line or area sensor has a large number of photoelectric transducer elements. The capacitances of the capacitors Cox, Cbc, and Cbe between a large number of photoelectric transducer elements vary by a few fractions of 1%. For example, if the following conditions are given:  
       [0033] Cox=Cbc=Cbe=0.014 pF, and Vør=5 V  
       [0034] and the capacitance variation is 0.2%, then a variation ΔVa in capacitance division voltage Va is about 3 mV.  
       [0035] The variation ΔVa can be reduced by refreshing. However, when the refresh mode is changed to an accumulation operation mode (time t3), the variation occurs again to produce ΔVb. The variation ΔVb does not satisfy relation ΔVb=−ΔVa, and the correlation cannot be established therebetween according to test results.  
       [0036] The above fact is assumed to be derived from different bias voltage dependencies of Cbc an Cbe.  
       [0037] In the next read cycle, when the transistor B is forward-biased, the variation in base potential thereof is approximated as follows:  
         ΔV   2   =ΔVa   2   +ΔVb   2 +2 KΔVaΔb   (2)  
       [0038] for K is −1 or more. As a result, the variation ΔV becomes steady drive noise of about 4 to 5 mV.  
       [0039] The variation in leakage component of such a drive pulse (to be referred to as drive noise hereinafter) is eliminated according to the following conventional technique. That is, the above drive noise is stored in a memory means and is read out and subtracted from the signal read out from the sensor to obtain a true information signal.  
       [0040] The conventional drive noise correction technique described above causes a bulky, expensive photoelectric transducer element which does not have any industrial advantage.  
       [0041] In particular, in case of that the numbers of elements arranged in the horizontal direction and vertical direction are five hundred respectively, an area sensor requires 250,000 photoelectric elements arranged in a matrix form. In addition, when the resolution of the sensor is also taken into consideration, a memory of several megabits is required.  
       [0042] The unnecessary signals such as drive noise and a dark signal pose serious problems when an image of a dark object is to be picked up, i.e., image pickup at a low intensity. In the low-intensity image pickup mode, an information signal level is low and accordingly the S/N ratio is degraded. As a result, image quality is degraded. In order to improve image quality, the unnecessary signals must be reduced.  
       [0043] As described above, however, the dark signal primarily depends on temperature and charge accumulation time, although the drive noise rarely depends thereon. If these unnecessary signals are to be eliminated, the dark signal must separated from the drive noise and a correction coefficient must be determined, thus requiring a large-capacity memory. As a result, signal processing is complicated and expensive, and an image pickup apparatus is undesirably bulky.  
       SUMMARY OF THE INVENTION  
       [0044] It is an object of the present intention to provide a photoelectric transducer apparatus capable of solving the conventional drawbacks described above.  
       [0045] It is another object of the present invention to provide a simple photoelectric transducer apparatus capable of eliminating variations in dark voltage.  
       [0046] It is still another object of the present invention to provide a photoelectric transducer apparatus comprising optical information storing means for storing optical information read out from a photoelectric transducer element and dark voltage storing means for storing a voltage corresponding to a dark voltage component read out from the photoelectric transducer element, wherein actual optical information stored in the optical information storing means is simultaneously read out together with the dark voltage component stored in the dark voltage storing means onto separate output lines, thereby correcting the information corresponding to the dark voltage in units of optical sensor cells and hence removing noise caused by variations in dark voltage from the output signal from the photosensor cells.  
       [0047] In order to achieve the above object, according, to an aspect of the present invention, there is provided a photoelectric transducer apparatus having a plurality of photoelectric transducer elements each having a capacitor electrode formed on a control electrode of a corresponding semiconductor transistor, the apparatus being adapted to sequentially select each element in units of lines, to control a potential of the control electrode of the selected photoelectric transducer element through the capacitor electrode, to store carriers in the control electrode region, and to read out a signal component corresponding to the amount of charge stored in the control electrode region, comprising: optical information storing means for storing optical information read out from the photoelectric transducer element; and dark voltage storing means for storing a voltage corresponding to a drak voltage read out from the photoelectric transducer element, wherein actual optical information stored in the optical information storing means and information corresponding to the dark voltage component stored in the dark voltage sotring means are simultaneously read out onto different information output lines.  
       [0048] The information corresponding to the dark voltage component stored in the dark voltage storing means is read out onto the information output line therefor, and at the same time the information corresponding to the dark voltage is corrected in units of photosensor cells, thereby eliminating noise caused by variations in dark voltage.  
       [0049] The noise corresponding to the dark voltage component can, therefore, be processed within the sensor. An external circuit or the like need not be used to easily constitute a system configuration, thereby obtaining a low-cost photoelectric transducer apparatus.  
       [0050] It is still another object of the present invention to provide an imaging element and an apparatus using the same, wherein the after image, blooming, and smearing can be prevented with a simple construction.  
       [0051] It is still another object of the present invention to provide a color imaging element having a large aperture.  
       [0052] In order to achieve these objects, according to another aspect of the present invention, there is provided a photoelectric transducer apparatus comprising:  
       [0053] a plurality of photoelectric transducer cells;  
       [0054] a signal read line for reading out signals from the plurality of photoelectric transducer elements; and  
       [0055] a plurality of capacitors for selectively storing the signals read out through the signal read line.  
       [0056] According to this aspect of the present invention, since the plurality of capacitors for selectively storing the signals read out through the signal read line are provided, the image signal appearing on the vertical line can be shortened, thereby reducing the frequency of occurrence of the blooming and smearing phenomena. Since the capacitor can be disconnected from the pixel after the image signal is stored in the capacitor, the refresh time can be prolonged to reduce the occurrence of the after image phenomenon. In addition, if the photoelectric transducer apparatus is used in a color video camera, the number of capacitors can be that of the color signals of the row pixels, and only one vertical line is used, thereby increasing the aperture.  
       [0057] It is still another object of the present invention to provide a photoelectric transducer apparatus wherein a single power source con be used without degrading the signal component of the read  
       [0058] In order to achieve the above object, according to still another aspect of the present invention, there is provided a photoelectric transducer apparatus for reading output a read signal from a photoelectric transducer element through an amplifier after the read signal is temporarily stored in a storing means, comprising switching means for properly applying a bias voltage to the storing means.  
       [0059] With the above arrangement, the reference potential of the store capacitor can be properly changed to use a single power source without degrading the signal component of the read signal.  
       [0060] It is still another object of the present invention to provide a photoelectric transducer apparatus little subjected to smearing or blooming.  
       [0061] In order to achieve the above object, according to still another aspect of the present invention, a capacitor is arranged in a vertical signal line through a switch to store the signal from the photoelectric transducer cell in the capacitor, thereby resetting the vertical signal line, so that the signal component in the capacitor is free from smearing or blooming.  
       [0062] It is another object of the present invention to eliminate variations in drive noise in units of sensor cells.  
       [0063] It is still another object of the present invention to compensate for variations in electrical characteristics of a plurality of amplifiers arranged for sensor cells.  
       [0064] In order to achieve the above objects according to an aspect of the present invention, there is provided a solid state image pickup apparatus having a selector for selecting a plurality of sensor signals through corresponding amplifiers, comprising a processing circuit for calculating a difference between a selected sensor signal and a reference signal selected through the same circuit for selecting the sensor signal.  
       [0065] The sensor signal selected by the selector, therefore, includes a noise component caused by variations in amplifier characteristics since the sensor signal is amplified by the corresponding amplifier. For this reason, the reference signal is selected through the same amplifier which has amplified the sensor signal, so that the amplifier noise is superposed on the reference signal. A difference between the selected sensor signal and the selected reference signal is calculated to eliminate the noise component.  
       [0066] According to another aspect of the present invention, there is provided a photoelectric transducer apparatus having storage means for storing a signal from a photoelectric transducer element, wherein the storage means comprises first storage means for storing the signal read out from the photoelectric transducer element and second storage means for storing a residual signal after the photoelectric transducer element is refreshed, and further comprising difference processing means for calculating a difference between the readout and residual signals respectively stored in the first and second storage means.  
       [0067] Since the residual signal obtained upon completion of refreshing is subtracted from the readout signal, the unnecessary components such as a dark signal and drive noise of the photoelectric transducer element can be eliminated.  
       [0068] A MOS, electrostatic induction, or base accumulation type photosensor may be used as a photoelectric transducer element.  
       [0069] “Refreshing” of the photoelectric transducer element means erasure of optical information of the photoelectric transducer element. In some photosensors, optical information is erased, simultaneously, when the information is read out. However, in some photosensors, optical information is kept unerased even after the information is read out.  
       [0070] According to still another aspect of the present invention, in order to eliminate the conventional drawbacks described above, there is provided a solid state image pickup apparatus comprising a plurality of photoelectric transducer elements, first storage means, arranged in units of photoelectric transducer elements, for storing a video signal, second storage means, arranged in units of photoelectric transducer elements, for storing noise components, a; first readout means for simultaneously and independently reading out signals for photoelectric transducer elements of a plurality of horizontal lines from the first storage means, and second readout means for adding signals for the photoelectric transducer elements of the plurality of horizontal lines from the second storage means and for reading out a sum signal.  
       [0071] With the above arrangement, it is assumed that the drive noise is generated as a sum of noise components generated in the refresh, charge accumulation, and readout modes of the photoelectric transducer element and the drive noise level is substantially identical in each mode. A difference between the photoelectric transducer signal read out upon completion of exposure and drive noise read out in the photoelectric transducer signal readout mode is calculated to eliminate the drive noise. It should be noted that the noise components are read out after they are added, thereby reducing the number of read lines.  
       [0072] According to still another aspect of the present invention, in order to eliminate the conventional drawbacks described above, there is provided a solid state image pickup apparatus comprising photoelectric transducer elements, a plurality of storage capacitors for storing readout signals when the photoelectric transducer elements are read-accessed a plurality of times, dot sequential processing means for converting signals from the storage capacitors into a dot sequential signal, and clamping means for clamping some components of the dot sequential signal from the dot sequential processing means.  
       [0073] With the above arrangement, it is assumed that the drive noise is generated as a sum of noise components generated in the refresh, charge accumulation, and readout modes of the photoelectric transducer element and the drive noise level is substantially identical in each mode. The photoelectric transducer signal read out upon completion of exposure and drive noise read out in the photoelectric transducer signal readout mode ore converted into a dot sequential signal, and the drive noise component is clamped, thereby eliminating the drive noise included in the photoelectric transducer signal components.  
       [0074] The above and other objects, features, and advantages of the present invention will be apparent from the following detailed description in conjunction with the accompanying drawings.  
       BRIEF DESCRIPTION OF THE DRAWINGS  
       [0075]FIG. 1 is a circuit diagram of a photoelectric transducer apparatus according to a first embodiment of the present invention;  
       [0076]FIG. 2 is a timing chart for explaining the operation of the apparatus in FIG. 1;  
       [0077]FIG. 3A is a circuit diagram of a photoelectric transducer apparatus according to a second embodiment of the present invention;  
       [0078]FIG. 3B is a circuit diagram showing the main part of a third embodiment;  
       [0079]FIG. 4 is a timing chart for explaining the operation of the second and third embodiments of the present invention;  
       [0080]FIG. 5 is a circuit diagram of a photoelectric transducer apparatus according to a fourth embodiment of the present invention;  
       [0081]FIG. 6 is a timing chart for explaining the operation of the apparatus in FIG. 5;  
       [0082]FIG. 7 is a circuit diagram of a photoelectric transducer apparatus according to a fifth embodiment of the present invention;  
       [0083]FIG. 8 is a timing chart for explaining the operation of the apparatus in FIG. 7;  
       [0084]FIG. 9 is a circuit diagram of a photoelectric transducer apparatus according to a sixth embodiment of the present invention;  
       [0085]FIG. 10 is a circuit diagram of a photoelectric transducer apparatus according to a seventh embodiment of the present invention;  
       [0086]FIG. 11 is a timing chart for explaining the apparatus in FIG. 10;  
       [0087]FIG. 12A is a circuit diagram for explaining a basic operation of the seventh embodiment of the present invention;  
       [0088]FIG. 12B is a timing chart showing the voltage waveforms in the seventh embodiment;  
       [0089]FIG. 13 is a block diagram of an imaging device on the basis of the above embodiments of the present invention; and  
       [0090]FIG. 14 is a circuit diagram showing part of an eighth embodiment of the present invention.  
       [0091]FIG. 15A is a schematic circuit diagram of a conventional solid state image pickup apparatus;  
       [0092]FIG. 15B is a schematic view of another conventional solid state image pickup apparatus;  
       [0093]FIGS. 15C to  15 E are views for explaining the principle of generation of drive noise of a photoelectric transducer element;  
       [0094]FIGS. 16A and 16B are schematic circuit diagrams showing a solid state image pickup apparatus according to an embodiment of the present invention;  
       [0095]FIG. 17 is a circuit diagram showing an arrangement of switches SW 1  to SWn in the apparatus of FIG. 16A;  
       [0096]FIG. 18 is a circuit diagram showing another arrangement of switches SW 1  to SWn in the apparatus of FIG. 16A;  
       [0097]FIG. 19A is a circuit diagram showing another arrangement of a difference processing circuit in the apparatus of FIG. 16A;  
       [0098]FIG. 19B is a timing chart for explaining the operation of the difference processing circuit shown in FIG. 11A;  
       [0099]FIG. 20A is a schematic circuit diagram showing a solid state image pickup apparatus according to another embodiment of the present invention;  
       [0100]FIG. 20B is a timing chart for explaining the operation of the apparatus shown in FIG. 10A;  
       [0101]FIG. 21 is a block diagram showing an image pickup system using the apparatus (of any embodiment described above) as an image pickup device;  
       [0102]FIG. 22A is a schematic sectional view of a photoelectric transducer cell described in Japanese Patent Laid-Open Gazettes Nos. 12759/1985 to 12765/1985.  
       [0103]FIG. 22B is an equivalent circuit diagram thereof;  
       [0104]FIG. 23 is a graph showing the relationship between a width t of a refresh pulse applied to the photoelectric transducer cell and a photoelectric transducer cell output after refreshing;  
       [0105]FIG. 24 is a circuit diagram for explaining a basic arrangement of a solid state image pickup apparatus according to still another embodiment of the present invention;  
       [0106]FIG. 25 is a timing chart for explaining the operation of the apparatus shown in FIG. 24;  
       [0107]FIG. 26 is a circuit diagram showing the overall arrangement of the apparatus shown in FIG. 24;  
       [0108]FIGS. 27A and 27B are timing charts for explaining two operation modes of the apparatus shown in FIG. 24;  
       [0109]FIG. 28 is a circuit diagram of a solid state image pickup apparatus according to still another embodiment of the present invention;  
       [0110]FIG. 29 is a detailed circuit diagram of a readout circuit Ri in the apparatus shown in FIG. 28;  
       [0111]FIG. 30 is a timing chart for explaining the operation of the apparatus shown in FIG. 28;  
       [0112]FIG. 31 is a block diagram showing an image pickup system using the apparatus (FIG. 24) as an image pickup device;  
       [0113]FIG. 32 is a circuit diagram showing an image pickup apparatus according to still another embodiment of the present invention;  
       [0114]FIG. 33 is a block diagram showing an image pickup system using the image pickup apparatus (FIG. 32) as an area sensor;  
       [0115]FIG. 34 is a circuit diagram of a solid state image pickup apparatus according to still another embodiment of the present invention;  
       [0116]FIG. 35 is a timing chart for explaining the operation of the apparatus shown in FIG. 34;  
       [0117]FIG. 36 is a schematic view showing an arrangement when the apparatus in FIG. 34 is applied to an area sensor; and  
       [0118]FIG. 37 is a timing chart for explaining the operation of the area sensor shown in FIG. 36. 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS  
     [0119]FIG. 1 is a circuit diagram of a photoelectric transducer apparatus as a line sensor according to a first embodiment of the present invention, and FIG. 2 is a timing chart for explaining the operation thereof.  
     [0120] Referring to FIGS. 1 and 2, capacitor electrodes  101  of photosensor cells  100  are commonly connected to a driving line, and collector electrodes  102  thereof are commonly connected to a positive voltage terminal.  
     [0121] A driving terminal is connected to the driving line.  
     [0122] A pulse signal is applied to the driving terminal to drive the photosensor cells  100 . Emitter terminals  103  of the photosensor cells  100  are connected to vertical signal lines and commonly connected to each other through reset FETs  104 . The emitter terminals  103  are connected to a ground terminal GND.  
     [0123] The gate electrodes of the FETs  104  are commonly connected to a first reset terminal.  
     [0124] The FETs  104  are switching field effect transistors.  
     [0125] The vertical signal lines are connected to store capacitors  106  through FETs  105  and to the source electrodes of FETs  107 . The drain electrodes of the FETs  107  are commonly connected to a horizontal signal line. The gate electrodes of the FETs  105  are commonly connected to a control terminal.  
     [0126] The gate electrodes of the FETs  107  are respectively connected to output terminals of a scanning circuit  108 .  
     [0127] Horizontal signal lines are connected to an external output terminal through an output amplifier  109  and to the ground terminal GND through an FET  100 .  
     [0128] The gate terminal of the FET  110  is connected to a second reset terminal.  
     [0129] The FET  110  is a field effect transistor for resetting the horizontal line.  
     [0130] The operator of the circuit in FIG. 1 will be described with reference to a timing chart in FIG. 2.  
     [0131] The control and first reset terminals are simultaneously set at H level during the reset time. During the reset time, the optical information stored in the store capacitors  106  is discharged through the FETs  104 .  
     [0132] When the control terminal is set at H level and the first reset terminal is set at L level, the optical information stored in the photosensor cells  100  is read out onto the vertical signal lines by applying the readout pulse signal to the driving terminal. Therefore, the optical information is stored in the store capacitors  106 .  
     [0133] In this manner, when the readout pulse signal is set at H level, readout operation of the photosensor cells  100  is started. After the lapse of a predetermined period of time, the readout pulse signal is set at L level, thereby terminating the readout operation.  
     [0134] When the control terminal is set at L level, and the first reset and driving terminals are set at H level, the refresh operation state is obtained. The optical information stored in the photosensor, cells  100  is erased through the FETs  104 .  
     [0135] When the refresh pulse signal is set at L level, the refresh operation is ended.  
     [0136] Thereafter, during the period until the readout operation state is obtained again, the store time for storing the carriers in the photosensor cells  100  is defined.  
     [0137] The signal pulses from the output terminals of the scanning circuit  108  are used to sequentially turn on the FETs  107  according to the shift timings.  
     [0138] The optical information signals stored in the store capacitors  106  are sequentially read out onto the horizontal lines by horizontal scanning of the scanning circuit  108 . The readout signals are amplified by the output amplifier  109  and appear at the external output terminal.  
     [0139] When all optical information signals stored in the store capacitors  106  are read out completely, the reset time is initialized again.  
     [0140] The above operations are thus repeated.  
     [0141] With the above arrangement, the signal charge is not kept on the vertical signal line for a long period of time, thus reducing blooming and smearing.  
     [0142] A second embodiment of the present invention will be described with reference to the accompanying drawings.  
     [0143]FIG. 3 is a circuit diagram of a photoelectric transducer apparatus according to the second embodiment.  
     [0144] Referring to FIG. 3, photosensor cells  1  as the photoelectric transducer elements are one-dimensionally arranged.  
     [0145] Capacitor electrodes  2  of the photosensor cells  1  are commonly connected to a driving line and to a driving terminal. Collector electrodes  3  of the photosensor cells  1  are commonly connected to a positive voltage terminal.  
     [0146] Emitter electrodes  4  of the photosensor cells  1  are respectively connected to vertical lines  5 . The vertical lines  5  are commonly connected through FETs  6 . The FETs  6  are connected to a ground terminal  7 .  
     [0147] The gate electrodes of the FETs  6  are commonly connected to a first reset terminal.  
     [0148] The capacitors  9  and the source electrodes of the FETs  100  are respectively connected to the vertical lines  5  through FETs  8 . The capacitors  9  are connected to a ground terminal  12  through a ground line  11 .  
     [0149] The capacitors  9  are signal charge store capacitors, respectively.  
     [0150] The gate electrodes of the FETs  10  are respectively connected to output terminals  14  of the scanning circuit  13 . The drain electrodes of the FETs  10  are connected to an output amplifier  16  through a horizontal line  15 . The output terminal of the output amplifier  16  is connected to an external output terminal  17 , so that an output voltage is extracted from the external output terminal  17 .  
     [0151] The gate electrodes of the FETs  10  are respectively connected to the gate electrodes of FETs  18 . The drain electrodes of the FETs  18  are connected to an output amplifier  20  through an output line  19 .  
     [0152] The output terminal of the output amplifier  20  is connected to an external output terminal  21 , so that an output voltage is extracted from the external output terminal  21 .  
     [0153] The source electrodes of the FETs  18  are connected to the vertical lines  5  through FETs  22 .  
     [0154] In the above embodiment, one electrode of each of capacitors  24  is connected between a corresponding one of the source electrodes of the FETs  18  and a corresponding one of the FETs  22  through a corresponding one of vertical lines  23 . The other electrode of each of the capacitors  24  is connected to the ground line  11 .  
     [0155] The capacitors  24  serve as dark voltage store capacitors, respectively. Reset FETs  26  are connected between the lines  15  and  19  and ground, respectively. The gate electrodes of the FETs  26  are connected to the second reset terminal. A control circuit  27  supplies timing pulses (FIG. 4) to the respective terminals.  
     [0156] The operation of the above embodiment will be described below.  
     [0157] As shown in the timing chart of FIG. 4, the photosensor cells store optical information corresponding to the amounts of light upon light store operation during the light irradiation store time.  
     [0158] During a predetermined period of time until the light information readout, the photosensor cells  1  perform store operations of carriers upon light irradiation. During the reset time, both the control and first reset terminals are set at H level, so that the charges stored in the capacitors  9  are reset through the corresponding FETs  6 .  
     [0159] The control terminal is set at H level, and the first reset terminal is set at L level. When a readout pulse voltage is applied to the driving terminal, the optical or light information stored in the photosensor cells  1  is read out onto the vertical lines, and the light information is stored in the capacitors  9 .  
     [0160] When the light information readout time has elapsed, the first reset terminal is set at H level and the control terminal is set at L level. In this state, when the refresh pulse voltage is applied to the driving terminal, the photosensor cells  1  are maintained in the refresh state. The light information stored in the photosensor cells  1  is erased through the FETs  6 .  
     [0161] When the refresh time has elapsed, the photosensor cells  1  are temporarily shielded from light so that a shading time is started.  
     [0162] In this case, the photosensor cells  1  store the dark voltage generated in the dark state. It should be noted that the dark voltage store time is controlled to be equal to the light irradiation store time.  
     [0163] Subsequently, both the dark voltage readout terminal and the first reset terminal are set at H level to reset through the FETs  6  the charges stored in the capacitors  24  during the reset time.  
     [0164] The light information corresponding to the dark voltage components, stored in the photosensor cells  1  is read out onto the vertical lines under the following conditions. The dark voltage readout terminal is set at H level, the first reset terminal is set at L level, and the readout pulse voltage Er is applied to the driving terminal. Therefore, the dark voltage signals are stored in the corresponding capacitors  24 .  
     [0165] When the dark voltage readout time has elapsed, the dark voltage readout terminal is set at L level, and the first reset terminal is set at H level. The refresh pulse voltage E0 is applied to, the driving terminal to set the photosensor cells  1  in the refresh state.  
     [0166] When a predetermined period of time has elapsed, the refresh pulse voltage applied to the driving terminal is set at L level. Therefore, the refresh time as terminated. Along with this, the shading time is ended, and the first reset terminal is set at L level.  
     [0167] Subsequently, clocks are supplied to the scanning circuit  13  to sequentially shift the output pulses from the output terminals  14  thereof. The FETs  10  and  18  are sequentially turned on in response to these timing pulses.  
     [0168] By this horizontal scanning, light information signals are sequentially read out from the capacitors  9  onto the horizontal line  15 . In synchronism with the readout operation, the information signals corresponding to the dark voltage components stored in the capacitors  24  are read out onto the output line  19 .  
     [0169] In this manner, the light information signals read out onto the horizontal line  15  are output to the external output terminal  17  through the output amplifier  16 . The information signals corresponding to the dark voltage components read out onto the output line  19  are output to the external output terminal  21  through the output amplifier  20 , so that the output voltage is thus extracted from this external output terminal.  
     [0170] For example, the readout operation for one horizontal scanning time is completed, and the reset time is started. Thereafter, the above operations will be repeated.  
     [0171] Since the photoelectric transducer apparatus of this embodiment is operated as described above, an additional external circuit which was required in the conventional photoelectric transducer apparatus to remove the noise component caused by the dark voltage need not be used, thereby amplifying the system configuration. Therefore, demand for a low-cost photoelectric transducer apparatus can be satisfied.  
     [0172] In the above embodiment, the actual light information signals simultaneously read out onto the corresponding lines and the information signals corresponding to the dark voltage components are amplified by the output amplifiers  16  and  20  in an output circuit  25 , and the amplified signals are extracted through the external output terminals, respectively. However, the present invention is not limited to the above arrangement. As shown in FIG. 3, (a third embodiment), the output circuit  25  may be replaced with a differential amplifier  28  to subtract the information corresponding to the dark voltage components from the actual light information. Light information representing a difference may be output from a terminal  29 .  
     [0173] In the second and third embodiments, the dark voltage store time is set to be equal to the light irradiation. However, such setting need not be  
     [0174] For example, by effectively utilizing the relationship between the dark voltage store time and the amount of dark voltage components generated by the photosensor cells  1 , i.e., a substantially proportional relationship, the dark voltage store time may be set to be shorter than the light irradiation time, and gains of the output amplifiers  16  and  20  in the output circuit  25  may be independently controlled. Alternatively, the capacitances of the store capacitors  9  and  24  are adjusted to obtain the same effect as in the above embodiments.  
     [0175] In the second and third embodiments, the photosensor cells are one-dimensionally aligned. However, the arrangement of the cells is not limited to this.  
     [0176] As described above, the photoelectric transducer apparatus comprises light information storing means for storing light information read out from the photoelectric transducer element, and dark voltage storing means for storing a voltage corresponding to the dark voltage component read out from the photoelectric transducer element. The actual light information stored in the light information storing means and the information corresponding to the dark voltage component stored in the dark voltage storing means are simultaneously reed out from the separate output lines. Therefore, the information corresponding to the dark voltage included in the output can be corrected in units of photosensor cells when the actual optical information read out from the photosensor cell is output, and noise caused by variations in dark voltage can be removed from the output signal. Unlike in the conventional photoelectric transducer apparatus, an additional external circuit is not required to simplify the system configuration. In addition, demand for an economical photoelectric transducer apparatus can be satisfied.  
     [0177] A fourth embodiment of the present invention will be described in detail with reference to the accompanying drawings.  
     [0178]FIG. 5 is a circuit diagram of photoelectric transducer elements arranged in a 4×4 matrix to constitute a photoelectric transducer apparatus.  
     [0179] The photoelectric transducer apparatus includes: basic photosensor cells  100  (the collector of each bipolar transistor is connected to the substrate and the substrate electrode), horizontal lines  31 ,  31 ′,  31 ″, and  31 ′″ serving as the readout-refresh pulse lines; a vertical shift register  32  for generating a readout pulse buffer MOS transistors  33 ,  33 ′,  33 ″, and  33 ′″ arranged between the vertical shift register  32  and the horizontal lines  31 ,  31 ′,  31 ″,  31  ′″; a terminal for applying a pulse φR to the drains of the buffer MOS transistors  33 ,  33 ′,  33 ″, and  33 ′″; a vertical shaft register  32 ′ for generating a refresh pulse; buffer MOS transistors,  47 ,  47 ′,  47 ″, and  47 ′″ formed between the vertical shift register  32 ′ and the horizontal lines  31 ,  31 ′,  31 ″, and  31 ′″; a terminal  48  for applying a pulse to the drains of the buffer MOS transistors  47 ,  47 ′,  47 ″, and  47 ′″ vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ serving as vertical readout lines for reading out signal charges from the basic photosensor cells  100 ; capacitors  37 - 1 ,  37 - 2 ,  37 - 1 ′,  37 - 2 ′,  37 - 1 ″,  37 - 2 ″,  37 - 1 ′″, and  37 - 2 ′″ for storing these signal charges; transfer MOS transistors  36 - 1 ,  36 - 2 ,  36 - 1 ′,  36 - 2 ′,  36 - 1 ″,  36 - 2 ″,  36 - 1 ′″, and  36 - 2 ′″ arranged between the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ and the capacitors  37 - 1 ,  37 - 2 ,  37 - 1 ′,  37 - 2 ′,  37 - 1 ″,  37 - 2 ″,  37 - 1 ′″, and  37 - 2 ′″; a horizontal shift register  46  for generating a pulse for selecting each store capacitor; gate MOS transistors  38 - 1 ,  38 - 2 ,  38 - 1 ′,  38 - 2 ′,  38 - 1 ″,  38 - 2 ″,  38 - 1 ′″, and  38 - 2 ′″ for charging/discharging the store capacitors  37 - 1 ,  37 - 2 ,  37 - 1 ′,  37 - 2 ′,  37 - 1 ″,  37 - 2 ″,  37 - 1 ′″, and  37 - 2 ′″; output lines  39 - 1  and  39 - 2  for reading out the store voltages and supplying them to an amplifier; MOS transistors  40 - 1  and  40 - 2  for refreshing the charges on the readout lines; a terminal  41  applying the refresh pulse to the MOS transistors  40 - 1  and  40 - 2 ; transistors  42 - 1  and  42 - 2  such as bipolar transistors, MOSFETs or JFETs for amplifying the output signals; output terminals  43 - 1  and  43 - 2  of the transistors  42 - 1  and  42 - 2 ; MOS transistors  44 ,  44 ′,  44 ″, and  44 ′″, for refreshing the charges stored on the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″; a terminal  45  for supplying a pulse to the gates of the MOS transistors  44 ,  44 ′,  44 ″, and  44 ′″; a horizontal shift register  46  for turning on the MOS transistors  38 - 1 ,  38 - 2 ,  38 - 1 ′,  38 - 2 ′,  38 - 1 ″,  38 - 2 ″,  38 - 1 ′″, and  38 - 2 ′″; and a control circuit  200  for supplying signals to the respective terminals.  
     [0180] The operation of the photoelectric transducer apparatus will be described with reference to FIG. 5 and a timing chart of FIG. 6.  
     [0181] Assume that the collector potential of the photosensor cells is kept at a positive potential in the following description.  
     [0182] The store operation is performed until the t1, and holes corresponding to the amounts of light incident on the photoelectric transducer cells  100  are respectively stored in their p-type base regions.  
     [0183] At time t1, a pulse signal φvc rises to turn on the transistors  44 ,  44 ′,  44 ″, and  44 ′″. A pulse signal φT 1  rises to turn on the transistors  36 - 1 ,  36 - 1 ′,  36 - 1 ″ and  36 - 1 ′″ to refresh the store capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ″″. A pulse signal φHc rises to turn on the transistors  40 - 1  and  40 - 2  to refresh the residual charges on the output lines  39 - 1  and  39 - 2 . Subsequently, the pulse signal vc falls to turn off the transistors  44 ,  44 ′,  44 ″, and  44 ′″, and the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ and the capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ′″ are set in the floating state. A pulse signal φv 1  is output from the vertical shift register  32  to turn on the transistor  33 . When a readout pulse signal φR is then applied to the terminal  34  and to the horizontal line  31  through the transistor  33 , the readout operation of the photoelectric transducer cells  100  of the first row is started. By this readout operation, the readout signals from the cells of the first row appear on the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ and in the store capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ′″. When the readout operation is completed, the pulse signal φT 1  falls to turn off the transistors  36 - 1 ,  36 - 1 ′,  36 - 1 ″, and  36 - 1 ′″. The capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ′″ and the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ are disconnected, and then the residual charges on the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ are refreshed.  
     [0184] At time t2, a pulse signal φT 2  rises to turn on the transistors  36 - 2 ,  36 - 2 ′,  36 - 2 ″, and  36 - 2 ′″ so that the charges in the store capacitors  37 - 2 ,  37 - 2 ′,  37 - 2 ″, and  37 - 2 ′″ are refreshed. Subsequently, the pulse signal φvc falls to turn off the transistors  44 ,  44 ′,  44 ″, and  44 ′″. A pulse signal φv 2  is output from the vertical shift register  33 ′, and the readout pulse signal φR is supplied to the horizontal line  31 ′ through the terminal  34 . In this state, the readout operation of the photoelectric transducer cells  100  of the second row is started. By this readout operation, the readout signals from the cells  100  of the second row appear on the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″ and in the store capacitors  37 - 2 ,  37 - 2 ′.  37 - 2 ″, and  37 - 2 ′″. Upon completion of the readout operation for the second row, the pulse signal T 2  falls to turn off the transistors  36 - 2 ,  36 - 2 ′,  36 - 2 ″, and  36 - 2 ′″, and the capacitors  37 - 2 ,  37 - 2 ′,  37 - 2 ″, and  37 - 2 ′″ and the lines  35 ,  35 ′,  35 ″, and  35 ′″ are disconnected. The pulse signal φvc rises to refresh the residual charges from the vertical lines  35 ,  35 ′,  35 ″, and  35 ′″.  
     [0185] At time t3, the pulse signal φHc falls to turn off the transistors  40 - 1  and  40 - 2 . The pulse signal φH 1  is output from the horizontal shift register  46  to turn on the transistors  38 - 1  and  38 - 2 . The charges in the capacitors  37 - 1  and  37 - 2  are amplified by the transistors  42 - 1  and  42 - 2  through the transistors  38 - 1  and  38 - 2  and the output lines  39 - 1  and  39 - 2 . The amplified signals appear at the terminals  43 - 1  and  43 - 2 . When this output operation is completed, the pulse signal φHc rises to refresh the output lines  39 - 1  and  39 - 2 . Sub-sequently, the pulse signals φH 2  and φH 3  are sequentially output from the horizontal shift register  46 . In the same manner as described above, the readout signals from the cell of the first row and the secoond column and the cell of the second row and the second column and the readout signals from the cell of the first row and the third column and the cell of the second row and the third column are sequentially output from the terminals  43 - 1  and  43 - 2 . Every time the readout signals appear, the output lines  39 - 1  and  39 - 2  are refreshed.  
     [0186] At time t4, a pulse signal φc 1  is output from the vertical shift register  32 ′ to turn on the transsistors  47  and  47 ′. A pulse signal φF is applied to the terminal  48  so that the refresh pulse is applied to the horizontal lines  31  and  31 ′ through the transistors  31  and  31 ′. As a result, the refresh operation of the photoelectric transducer cells  100  of the first and second rows is performed.  
     [0187] The readout and refresh operations for the cells  100  of the third and fourth rows are performed at time t5 in the same manner as in the cells of the first and second rows. The readout and refresh operations are repeated for the cells  100  of the first and second rows at time t6. The above operations are repeated.  
     [0188] In the above operation, the time required for sending the readout signal onto the vertical line is the period between rising of the pulse signal φR and falling of the pulse signal φT 1 , i.e., between the times t1 and t2 when the output from the photoelectric transducer cell  100  of the first row and the first column as assumed. This time interval apparently has a large margin. In the conventional photoelectric transducer apparatus applied in the video camera, the vertical line selected last by horizontal scanning stores the signal charge for about 52.5 μs. For example, if the time interval between rising of the pulse signal φR and falling of the pulse signal φT 1  is set to be 0.5 μs, the apparatus of this embodiment can be improved by about 105 times (40 dB) for blooming and smearing, as compared with the conventional apparatus.  
     [0189] Since the store capacitors are arranged, the photosensitive transducer cells are disconnected from the store capacitors by turning off the transistors  36 - 1 ,  36 - 2 ,  36 - 1 ′,  36 - 2 ′,  36 - 1 ″,  36 - 2 ″,  36 - 1 ′″, and  36 - 2 ′″ after the signal charges are stored in the store capacitors, the photoelectric transducer cells  100  can be sufficiently refreshed. For example, the refresh time may be a time interval between times t3 and t5, i.e., one horizontal scanning cycle. Therefore, the after image phenomenon can be reduced as compared with the conventional case.  
     [0190] If the photoelectric transducer apparatus is applied to a color video camera and color filters are formed on the sensor cells, the number of capacitors is that of the colors of column cells, and the operation as described above is performed. In this case, only one vertical line is used for each column, and the aperture of the sensor cells is not reduced. For example, as shown in FIG. 5, the color filters R, G, and B are arranged according to the Bayer&#39;s scheme, and the cells are operated at the timings shown in FIG. 6. B signals are stored in the capacitors  37 - 1  and  37 - 1 ″, G signals are stored in the capacitors  37 - 2 ,  37 - 1 ′,  37 - 2 ″, and  37 - 1 ′″, and R signals are stored in the capacitors  37 - 2 ′ and  37 - 2 ′″, respectively.  
     [0191] In the above embodiment, the two vertical lines are simultaneously accessed. However, the number of lines is not limited to two, but can be extended to three or more. In this case, the number of store capacitors is that of vertical pixels which are simultaneously accessed.  
     [0192]FIG. 7 is a circuit diagram showing a fifth embodiment of the present invention. A decoder  49  is arranged between a vertical shift register  32  and horizontal lines  31 ,  31 ′,  31 ″, and  31 ′″, and a control circuit  200  is operated at timings shown in FIG. 8.  
     [0193] In this embodiment, the decoder  49  also serves the function of the photoelectric transducer cell refresh vertical register  46  of the fourth embodiment (FIG. 5), thereby further simplifying the system configuration.  
     [0194] The operation of the fifth embodiment will be described with reference to the timing chart of FIG. 8. Assume that the store operation is performed until time t1, and that the holes corresponding to the amounts of light incident on the photoelectric transducer cells  100  are respectively stored in their p-type base regions.  
     [0195] At time t1, a pulse signal φvc has already risen, the vertical lines have already been grounded, and a pulse signal φT 1  rises to refresh the charges of the capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ′″. Thereafter, when the pulse signal φvc falls to set the vertical lines and the capacitors in the floating state, the decoder  49  outputs a pulse φD 1 .  
     [0196] The signals from the photoelectric transducer cells  100  of the first row appear on the vertical lines and in the capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 ′″. After the readout operation is completed, the pulse signal φT 1  falls to disconnect the capacitors  37 - 1 ,  37 - 1 ′,  37 - 1 ″, and  37 - 1 ′″ from the vertical lines, and the pulse signal φvc rises again to refresh the vertical lines. The pulse signal φT 2  rises to refresh the capacitors  37 - 2 ,  37 - 2 ′,  37 - 2 ″, and  37 - 2 ′″, and the pulse signal φvc then falls. When the pulse signal φD 2  rises again, the signals from the photoelectric transducer cells of the second row appear on the vertical lines and the capacitors  37 - 2 ,  37 - 2 ′,  37 - 2 ″, and  37 - 2 ′″. Thereafter, the pulse signal φT 2  falls and the pulse signal φvc rises to refresh the vertical lines. In this state, the signals from the first row are stored in the capacitors  37 - 1 ,  37 - 1 ′.  37 - 1 ″ and  37 - 1 ′″, and the signals from the second row are stored in the capacitors  37 - 2 ,  37 - 2 ′,  37 - 2 ″, and  37 - 2 ′″.  
     [0197] In the same manner as in the first embodiment, these stored signals are sequentially read out from time t3 to time t5. In this case, during the time interval from time t4 to time immediately before time t5, the pulse signals φD 1  and φD 2  are set at high level, so that the photoelectric transducer cells  100  of the first and second rows are refreshed.  
     [0198] The readout and refresh operations of the photoelectric transducer calls of the third and fourth rows are performed in the same manner as described above.  
     [0199] According to this embodiment, the refresh end readout operations of the photoelectric transducer cells of each cell are performed by using a single vertical shift register, thereby simplifying the system configuration.  
     [0200] In the above embodiment, the two output lines are used. However, the number of output lines may be three or more. For example, as shown in a sixth embodiment of FIG. 9, four output lines are used in units of colors of filters. In this case, the load of the output lines can be reduced into ½ of the two output lines. In addition, an image processing circuit can also be simplified.  
     [0201] The arrangement of FIG. 9 is different from that of FIG. 5 in the following points. Output lines  39 - 3  and  39 - 4  are added. Transistors  38 - 1  and  38 - 1 ′″ are connected to a transistor  39 - 3  instead of the transistor  39 - 1 . Transistors  38 - 2 ′ and  38 - 2 ′″ are connected to a transistor  39 - 4  instead of the transistor  39 - 2 . Transistors  40 - 3  and  40 - 4 , the gates of which are commonly connected to the gates of transistors  40 - 1  and  40 - 2 , are added to refresh the output lines  39 - 3  and  39 - 4 . A transistor  42 - 3  for outputting a signal from the output signal  39 - 3 , an output terminal  43 - 4 , a transistor  42 - 4  for outputting a signal from the output line  39 - 4 , and an output terminal  43 - 4  are added.  
     [0202] Other arrangements of FIG. 9 are the same as those of FIG. 5, and the same reference numerals as in FIG. 5 denote the same parts in FIG. 9.  
     [0203] In the photoelectric transducer apparatuses in the foruth to sixth embodiments as described above in detail, a plurality of capacitors are arranged for each readout line of the photoelectric transducer cells. The signal charges can be stored in the capacitors in a short period of time, and then the readout lines can be disconnected therefrom. Therefore, blooming and smearing caused by the present of the signal charges on the readout lines can be completely prevented.  
     [0204] Furthermore, since the refresh time can be sufficiently prolonged, the after image phenomenon can be effectively prevented.  
     [0205] Many lines are often simultaneously accessed when the photoelectric transducer apparatus is applied to a color video camera or the like. The capacitors corresponding to the pixels to be accessed are arranged for each readout line. The number of readout lines need not be increased, and thus the aperture can be increased.  
     [0206] A seventh embodiment of the present invention will be described below.  
     [0207]FIG. 10 is a circuit diagram of a photoelectric transducer apparatus as according to the seventh embodiment of the present invention.  
     [0208] Referring to FIG. 10, a driving pulse φR is applied from a control circuit  200  to capacitor electrodes of photoelectric transducer cells S 1  to Sn. A predetermined positive voltage is applied to the collector electrodes of the cells S 1  to Sn. The emitter electrodes of the cells S 1  to Sn are respectively connected to vertical lines VL 1  to VLn. Each of these vertical lines is connected to one terminal of a corresponding one of store capacitors C 1  to Cn (each having a capacitance Ct) through a corresponding one of transistors Qt 1  to Qtn. The other terminal of each of the capacitors C 1  to Cn properly receives a bias voltage Vct in a manner to be described later.  
     [0209] One terminal of each of the capacitors C 1  to Cn is connected to an output line  201  through a corresponding one of transistors QS 1  and QSn. The output line  201  has a stray capacitance Ch equal to the capacitance Ct of each of the store capacitors C 1  to Cn.  
     [0210] The input terminal of an output amplifier  202  is connected to the output line  201  and to a transistor Qrh for properly applying a reset voltage Vrh. The value of the reset voltage Vrh is selected within the range wherein the linearity of the output amplifier  202  is not degraded. In this embodiment, the range is 1.5 to 3.5 V. The output amplifier  202  is connected to a single power source and is driven thereby.  
     [0211] Pulses φh 1  to φhn are sequentially applied from a scanning circuit  103  to the gate electrodes of the transistors QS 1  and QSn. A pulse φt is applied to the gate electrodes of the transistors Qt 1  to Qtn.  
     [0212] A voltage Vvc is applied to the respective vertical lines through transistors Qr 1  to Qrn. The gate electrodes of these transistors receive a pulse φvc. A control circuit  200  supplies a driving pulse of each terminal. FIG. 11 is a timing chart for explaining the operation of the control circuit.  
     [0213] The transistors Qr 1  to Qrn and the transistors Qt 1  to Qtn are turned on in response to the pulses φvc and φt, respectively, to clear (duration T 1 ) the capacitors C 1  to Cn. Subsequently, the pulse φvc is set at L level, and the capacitors C 1  to Cn are charged (duration T 2 ) with the readout signals from the photoelectric transducer cells in response to the driving pulse φr. In this case, the bias voltage Vct is the ground potential.  
     [0214] After the bias voltage Vct is set to be +2V, the signals from the capacitors C 1  to Cn are output at timings of the shift pulses φh 1  to φhn.  
     [0215] More specifically, the transistor QS 1  is turned on in response to the pulse φh 1 . As described above, the signal read out from the photoelectric transducer cell S 1  and stored in the capacitor C 1  is read out onto the output line  201 . Subsequently, the transistor Qrh is turned on in response to the pulse φrh, and the output line  201  is reset to the reset voltage Vrh (e.g., +2V). In the same manner as described above, the readout signals stored in the capacitors C 2  to Cn are sequentially read out onto the output line  101  and are output through the output amplifier  102  (a duration T 3 ).  
     [0216] When the output operation is completed, the refresh operation is performed in response to the pulse vc and the driving pulse φr (a duration T 4 ).  
     [0217] The basic operation of the circuit in FIG. 10 will be described below.  
     [0218]FIG. 12A is a circuit diagram for explaining the basic operation of the circuit in FIG. 10, and FIG. 12B is a timing chart showing the voltage waveforms.  
     [0219] Referring to FIG. 12A, a switch for selecting the ground voltage (contact A) or the bias voltage of +2V (contact B) is equivalently connected to the store capacitor Ct. A switch Qrh for applying the reset voltage Vrh (+2V) is equivalently connected to the output line  201 . Also assume that the voltage of the capacitor Ct is v1, and that the voltage of the output line  201  is v2.  
     [0220] The capacitor Ct is connected to the contact A and grounded, and the readout signal from the sensor is stored in the capacitor Ct. The capacitor Ct is then connected to the contact a and receives the bias voltage of +2V. The voltage of the capacitor Ct at the time of zero level of the readout signal is set to be equal to the reset voltage of the output line.  
     [0221] Subsequently, when the switch Qs is closed, the ½ component of the signal of the voltage v1 appears on the output line  201  since Ct=Ch. This voltage is input as a voltage V2 to the output amplifier  202 . Closing of the switch Qrh causes resetting of the output line  201  at the voltage of +2V (FIG. 12B).  
     [0222] According to this embodiment, only the signal component is input to the output amplifier  102 , and the input voltage does not greatly vary upon resetting. The dynamic range of the output amplifier  202  can therefore be increased. The amplitude of the voltage Vrh or Vct can have a large margin.  
     [0223] By setting the potential of the output line  201  connected to the input terminal of the output amplifier  202  at a low potential excluding the ground potential, the Vss terminal of the output amplifier  202  can be grounded and a positive voltage (+5V in this case) can be applied to the Vdd terminal thereof by a single power source. (For example, if the reset potential is zero, the negative and positive potentials are respectively applied to the Vss and Vdd terminals, end thus two power sources are required).  
     [0224] If the bias voltage of the capacitor Ct is not changed, the potential of the output line  201  greatly varies between the reset potential Vrh and the signal component potential of the readout signal. The sensor signal is normally amplified to a proper signal level by a signal processor (to be described later). If the above unnecessary component is generated, the circuit system is saturated since the unnecessary component has a magnitude larger than that of the signal component, thereby degrading the signal component. However, according to the above embodiment, the above problem does not occur. If an output amplifier having a wide dynamic range is arranged, it prevents use of a low-level driving source and design of a compact imaging device. However, according this embodiment, the wide dynamic range of the amplifier  202  is not required, so that a compact imaging device can be provided.  
     [0225] Now assume the charge/discharge time. A reset potential portion of the output signal Vout can sufficiently drive a load capacitance (a bonding capacitance, a wiring capacitance, an input transistor capacitance, and the like) by a source current of a source follower circuit. However, the signal component portion of the output signal becomes a sink current of the source follower circuit. If an output resistance is not sufficiently small, a discharge time constant is increased to degrade linearity of a small signal. A decrease in output resistance causes current consumption loss. According to this embodiment, since the dynamic range of the output amplifier can be narrowed, this problem does not occur.  
     [0226] In order to eliminate the unnecessary voltage variation component, a sample/hold (S/H) circuit is required. The relationship between a timing pulse for the S/H circuit and the signal component is very important. It is desirable not to arrange the S/H circuit to obtain good temperature characteristics and the power source voltage characteristics. However, if the S/H circuit is not arranged, the blocking characteristic curve of a low-pass filter becomes steep when the output signal is band-limited thereby, and hence image quality is degraded. However, according to this embodiment, since the S/H circuit need not be used, the apparatus of this embodiment can be stably operated against temperature and voltage variations.  
     [0227]FIG. 13 shows a schematic arrangement of an imaging device using the above embodiment.  
     [0228] Referring to FIG. 13, an imaging element  501  has the same arrangement as in the embodiment of FIG. 10. An output signal Vout from the imaging element  501  is gain-controlled by a signal processing circuit  502  and is output as a standard NTSC signal or the like.  
     [0229] Various pulses φ and the bias voltage Vct for driving the imaging element  501  are generated by a control circuit  200 . The control circuit  200  is operated under the control of the control unit  504 . In this case, the control circuit  200  also serves as the switching means for properly applying the bias voltage Vct. The control unit  504  controls the gain or the like of the signal processing circuit  502  on the basis of the output from the imaging element  501  to control the amount of light incident on the imaging element  501 .  
     [0230] The bias voltage Vct applied to the store capacitors C 1  to Cn is supplied from the control circuit  200 . However, an internal power source  601  shown in FIG. 14, may be arranged. In this case, the internal power source  601  is operated in response to a control pulse φct from the control unit  504  to generate the bias voltage Vct.  
     [0231] In the photoelectric transducer apparatus as described in detail, a simple method of temporarily changing the reference potential of the capacitors in the readout mode is employed, so that only a single power source for the imaging driving voltage can be used. As a result, the imaging device can be made more compact at lower power consumption.  
     [0232]FIG. 16A is a schematic circuit diagram of a solid state image pickup apparatus according to an embodiment of the present invention.  
     [0233] Referring to FIG. 16A, switches SW 1  to SWn are arranged to select corresponding inputs in response to pulses øc 1  to øcn. The switches SW 1  to SWn respectively receive sensor signals S 1  to Sn from photosensors S 1  to Sn arranged in a line or a matrix form. The switches SW 1  to SWn also receive signals E from reference signal sources E, respectively.  
     [0234] The output terminals of the switches SW 1  to SWn are respectively connected to the input terminals of amplifiers A 1  to An. The output terminals of the amplifiers A 1  to An are connected to an output line  101 A through corresponding transistors T 1  to Tn. Pulses ø 1  to øn from a scanning circuit SH such as a shift register are respectively supplied to the gate electrodes of the transistors T 1  to Tn. The transistors T 1  to Tn are turned on in response to the pulses ø 1  to øn.  
     [0235] The output line  101 A is grounded through a transistor  103 A. A pulse øhrs is applied to the gate electrode of the transistor  103 A. The output line  101 A is also connected to a difference processing circuit  1 A. An output signal Vout free from noise components is output from the difference processing circuit  1 A.  
     [0236] In the difference processing circuit  1 A in this embodiment, the output line  101 A is connected to an amplifier  11 A. The input terminals of sample/hold (S/H) circuits  12 A and  13 A are connected to the output terminal of the amplifier  11 A. Pulses φh 1  and φh 2  as control signals are respectively supplied to the S/H circuits  12 A and  13 A so that the S/H circuits  12 A and  13 A hold the inputs at the input timings of these pulses, respectively. The output terminals of the S/H circuits  12 A and  13 A are respectively connected to the noninverting and inverting input terminals of a differential amplifier  14 A. The output signal Vout is output from the differential amplifier  14 A.  
     [0237] The operation of this embodiment will be described below.  
     [0238] When the reference E is input to the amplifier A 1  upon operation of the switch SW 1 , the reference signal E is amplified by the amplifier A 1 , and an amplified signal E 1 ′ is output to the transistor T 1 . In this case, only the transistor T 1  is kept on in response to the pulse ø 1 , and other transistors T 2  to Tn are kept off. The reference signal E 1 ′ is selected by the transistor T 1  and appears on the output line  101 A. The reference signal E 1 ′ is held in the S/H circuit  12 A through the amplifier  11 A. More specifically, the pulse φh 1  is supplied to the S/H circuit  12 A when it holds the reference signal E 1 ′.  
     [0239] The reference signal E 1 ′ held by the S/H circuit  12 A is a signal reflecting variation characteristics of the amplifier A 1 , i.e., a signal including a noise component N 1  which becomes a steady pattern noise. In other words, E 1 ′=E+N 1 .  
     [0240] Subsequently, the transistor  103 A is turned on in response to the pulse øhrs to remove the charge left on the output line  101 A. An output signal from the sensor S 1  is input to the amplifier A 1  through the switch SW 1 . In the same manner as described above, a sensor signal S 1 ′ amplified by the amplifier A 1  appears on the output line  101 A through the ON transistor T 1  and is held by the S/H circuit  13  through the amplifier  11 A.  
     [0241] The sensor signal S 1 ′ held by the S/H circuit  13 A also reflects variation characteristics, i.e., a signal including the noise component N 1  (S 1 ′=S 1 +N 1 ).  
     [0242] When the reference signal E 1 ′ and the sensor signal S 1 ′ are respectively held by the S/H circuits  12 A and  13 A, the signals S 1 ′ and E 1 ′ are input to the differential amplifier  14 A. The output Vout from the differential amplifier  14 A is a difference (S 1 ′−E 1 ′) between the sensor and reference signals S 1 ′ and E 1 ′, thereby obtaining a signal (S 1 −E) free from the noise component N 1 . In this case, the reference signal E represents the reference level of the sensor signal S 1 , so that E=0 is established. Therefore, the output signal Vout is the sensor signal S 1  before being subjected to the influence of the amplifier A 1 .  
     [0243] When the sensor signal S 1  is output in this manner, the residual charge on the output line  101 A is eliminated by the transistor  103 A. At the timings in the same manner as described above, the sensor signals S 2  to Sn free from the noise components N 2  to Nn are sequentially output from the differential amplifier  14 A.  
     [0244] In the above description, the reference signal E is read out prior to the corresponding sensor signal. However, each sensor signal may be read out prior to the reference signal E.  
     [0245] In the above description, the reference and sensor signals E 1 ′ and S 1 ′ are held in the separate S/H circuits, respectively. However, one of the S/H circuits may be omitted, and the output terminal of the amplifier  11 A may be directly connected to the amplifier  14 A (FIG. 16B). In this case, one readout signal is held by the S/H circuit  12 A in response to the pulse øh 1 , and the output signal Vout is output from the differential amplifier  14 A at the read timing of the other readout signal.  
     [0246]FIG. 17 is a circuit diagram showing an arrangement of switches SW 1  to SWn in the apparatus shown in FIG. 1A.  
     [0247] Referring to FIG. 17, a transistor  201 A is turned on in response to a pulse øt to store the sensor signal S 1  in a capacitor C 1 . Subsequently, a transistor  203 A is turned on in response to a pulse øcb to output the reference signal E to the amplifier A 1 .  
     [0248] When the reference signal E 1 ′ is held as described above, the transistor  202 A is turned on in response to a pulse øca to output the sensor signal S 1  from the capacitor C 1  to the amplifier A 1 .  
     [0249] The switches SW 2  to SWn have the same arrangement as that of the switch SW 1 , and operations of the switches SW 2  to SWn are also the same as that of the switch SW 1 .  
     [0250]FIG. 18 is a circuit diagram showing another arrangement of the switches SW 1  to SWn in the apparatus of FIG. 16A.  
     [0251] In this arrangement, the reference signal E is generated by drive noise caused by variations in leakage component of the sensor.  
     [0252] Referring to FIG. 18, a transistor  301 A is turned on in response to a pulse øt 1  to store the sensor signal S 1  in a capacitor C 11 . Subsequently, a transistor  303 A is turned on in response to a pulse øt 2 . A sensor signal representing absence of optical information or the dark state thereof serves as the reference signal E. This reference signal E is stored in a capacitor C 12 . In this state, a drive noise component of the corresponding sensor is stored in the capacitor C 12 . In the same manner as described above, a transistor  304 A is turned on to output the reference signal E from the capacitor C 12  to an amplifier A 1  and then a transistor  302 A is turned on to output the sensor signal S 1  from the capacitor C 11  to the amplifier A 1 .  
     [0253] By using the sensor drive noise component as the reference signal E, the output Vout (=S 1 ′−E 1 ′) from the differential amplifier  14 A is free from the sensor drive noise component as well as the noise component N 1  of the amplifier A 1 .  
     [0254]FIG. 19A is a circuit diagram showing another arrangement of the difference processing circuit in the apparatus shown in FIG. 16A, and FIG. 19B is a timing chart for explaining the operation thereof.  
     [0255] Difference processing is performed by a clamping circuit in this arrangement.  
     [0256] Referring to FIGS. 19A and 19B, the reference signal E 1 ′ amplified by the amplifier A 1  appears on the output line  101 A and is input to a clamp circuit through an amplifier comprising transistors  15 A and  16 A. In this case, the clamp circuit comprises a capacitor  17 A and a transistor  18 A. Since the transistor  18 A in the clamp circuit is kept on in response to a clamp pulse øs, the level of the reference signal E 1 ′ is clamped as the reference level. As a result, the sensor signal S 1 ′ subsequently appearing on the output line  101 A is amplified by an amplifier of transistors  19 A and  20 A using the reference signal E 1 ′ as a reference level. In the same manner as in FIG. 15, the output signal Vout obtained by removing the reference signal E 1 ′ from the sensor signal S 1 ′ is obtained. Similarly, the clamp pulse øs is generated at a read timing of the reference signal E 1 ′, and the sensor signals S 1  to Sn free from the noise components are sequentially output.  
     [0257]FIG. 20A is a schematic circuit diagram of a solid state image pickup apparatus according to another embodiment of the present invention, and FIG. 20B is a timing chart for explaining the operation thereof.  
     [0258] Referring to FIG. 20A, sensors B 1  to Bn (to be referred to as B hereinafter) are base accumulation type phototransistors. A base potential of each transistor is controlled through a capacitor, and the carriers excited upon incidence of light are accumulated in the base region of the transistor. The accumulated voltage is read out as a sensor signal, or the accumulated carriers are removed.  
     [0259] A read or refresh pulse ør is applied to the capacitor electrodes of the sensors B. The emitter electrodes of the sensors B which are adapted to read out sensor signals S 1  to Sn (to be referred to as S hereinafter) are grounded through transistors Qr 1  to Qrn (to be referred to as Qr hereinafter), respectively. The emitter electrodes are connected to temporary storage capacitors C 11  to Cn 1  through transistors Qa 1  to Qan (to be referred to as Qa hereinafter) and to temporary storage capacitors C 12  to Cn 2  through transistors Qc 1  to Qcn (to be referred to as Qc hereinafter), respectively.  
     [0260] The capacitors C 11  to Cn 1  are connected to the gate electrodes of amplifiers A 1  to An through transistors Qb 1  to Qbn, respectively. The capacitors C 12  to Cn 2  are connected to the gate electrodes of the amplifier A 1  to An through transistors Qd 1  to Qdn, respectively.  
     [0261] A voltage Vcc is applied to the first terminals of the amplifiers A 1  to An, and an output line  501 A is commonly connected to the second input terminals thereof.  
     [0262] A pulse øa 1  is applied to the gate electrodes of the transistors Qb 1  to Qbn through transistors Qe 1  to Qen. A pulse øb 1  is applied to the gate electrodes of the transistors Qd 1  to Qdn through transistors Qf 1  to Qfn.  
     [0263] Pulses ø 1  to øn from a scanning circuit SH are sequentially supplied to the gate electrodes of the transistors Qe 1  to Qen, Qf 1  to Qfn, and T 1  to Tn, respectively.  
     [0264] A transistor  502 A is connected to the output line  501 A, and a voltage Vss is applied to the output line  501 A through the transistor  502 A. A signal S′ amplified by each amplifier and appearing on the output line  501 A is input to the difference processing circuit  1 A, and difference processing as described above is performed. It should be noted that the difference processing circuit lain this embodiment is of a differential type using the S/H circuit shown in FIG. 16A.  
     [0265] The operation of the apparatus of this embodiment will be described with reference to FIG. 20B.  
     [0266] Assume that carriers corresponding to the intensity levels of the incident light are stored in the base regions of the sensors B, respectively.  
     [0267] For a time interval Tm 1 , the transistors or are kept on in response to the pulse ørh, and the emitter electrodes of the sensors B and the vertical lines are grounded. At the same time, the transistors Qa and Qc are turned on in response to the pulses øt 1  and øt 2  to clear the carriers from the capacitors C 11  to Cn 1  and C 12  to Cn 2 , respectively.  
     [0268] For a time interval Tm 2 , the transistors Qa are kept on in response to the pulse øt 1  to supply the read pulse ør to the sensors B. Therefore, the sensor signals S from the sensors B are stored in is the capacitors C 11  to Cn 1 , respectively. These sensor signals include the drive noise components of the corresponding sensors.  
     [0269] For a time interval Tm 3 , the transistors Qr are kept on in response to the pulse ørh to ground the emitters of the sensors B. The sensors B are refreshed in response to the refresh pulse ør. Upon completion of refreshing, the transistors Qrh are turned off, and the transistors Qc are turned on in response to the pulse øt 2 . During this period, the read pulse ør is applied to read out the signals from the sensors B. Their drive noise components, i.e., the above-mentioned reference signals E 1  to En are respectively stored in the capacitors C 12  to Cn 2 . Thereafter, the pulse or falls to cause the sensors B to start charge accumulation.  
     [0270] The above operations are performed during a blanking period BLK, and the signals temporarily stored in the corresponding capacitors are sequentially read out onto the output line  501 A.  
     [0271] The transistors T 1 , Qe 1 , and Qf 1  are turned, on in response to the pulse ø 1 . The voltage Vcc is applied to the amplifier A 1 , and the amplifier A 1  is rendered operative (other amplifiers A 2  to An are rendered inoperative). The pulse øa 1  rises in synchronism with the pulse ø 1  and the transistor Qb 1  is turned on through the ON transistor Qe 1 . The sensor signal S 1  stored in the capacitor C 11  is amplified by the amplifier A 1 , and the amplified signal appears on the output line  501 A and is then held in an S/H circuit  12 A in a difference processing circuit  1 A.  
     [0272] Subsequently, the pulse øb 1  rises and then the transistor Qd 1  is turned on through the transistor Qf 1 . The reference signal E 1  stored in the capacitor C 12  is amplified by the amplifier A 1 , and the amplified signal appears on the output line  501 A and then held by an S/H circuit  13 A.  
     [0273] It can be assumed that a potential of an input to the amplifier A 1  can be reset to a reference potential for a period from the time when the sensor signal S 1  is output from the capacitor C 11  to the amplifier A 1  and to the time when the reference signal E 1  is output from the capacitor C 12 .  
     [0274] However, most of the input capacitance of the amplifier A 1  is an overlap capacitance of the transistors. The input capacitance is sufficiently smaller than the capacitances of the capacitors C 11 , and C 12 , and the residual charge can be neglected. Steady pattern noise caused by variations in amplifier characteristics is typical when the image signal is small. In this case, the residual charge is further decreased.  
     [0275] From the above reasons, a means for resetting the input terminals of the amplifiers A 1  to An is omitted. However, in an application wherein the residual charge cannot be neglected, a reset means must be connected to the inputs of the amplifiers A.  
     [0276] When the sensor and reference signals S 1 ′ and E 1 ′ are respectively held by the S/H circuits  12 A and  13 A, the above-mentioned difference processing is performed to cause the differential amplifier  14 A to produce the sensor signal S 1  as the output signal Vout free from the drive noise component and the noise component N 1 . Similarly, the sensor outputs S 1  to Sn are sequentially output.  
     [0277] When all sensor signals are output, the next sensor signals corresponding to the incident light are stored in the sensors B. In the same manner as described above, sensor read access and refreshing are performed for the blanking period BLK. Charge accumulation of the sensors B and dot sequential operation of the sensor signals temporarily stored in the capacitors are simultaneously performed.  
     [0278] When the clamp circuit shown in FIG. 19 is used in the difference processing circuit  1 A, the capacitor C 12  for charging the reference signal E 1  and then the capacitor C 11  for charging the sensor signal S 1  must be discharged. This applies to the signal readout operations of the sensor signals  52  to Sn.  
     [0279]FIG. 21 shows a schematic arrangement of an image pickup system using any one of the image pickup apparatuses of the embodiments as an image pickup device.  
     [0280] Referring to FIG. 21, an image pickup device  601 A comprises an image pickup apparatus of any one of the above embodiments. The gain or the like of the output signal Vout is controlled by a signal processing circuit  602 A, and the resultant signal is output as a video signal.  
     [0281] Various pulses ø for driving the image pickup device  601 A are supplied from a driver  603 A. The driver  603 A is operated under the control of a control unit  604 A. The control unit  604 A controls the gain or the like of the signal processing circuit  602 A on the basis of the output from the image pickup device  601 A and also controls an exposure control unit  605 A to adjust an amount of light incident on the image pickup device  301 A.  
     [0282] As described above, in the solid state image pickup apparatus according to the above embodiments, a difference between the selected sensor signal and the selected reference signal is calculated to obtain an output signal free from the noise components. Therefore, the variations in readout signal depending on the potential variations of the input/output characteristics of the selector can be corrected. The steady pattern noise caused by the variations in amplifier characteristics can be eliminated.  
     [0283] A photoelectric transducer element used in FIGS. 16A to  21  will be described as a supplementary explanation of FIGS. 15C to  15 E.  
     [0284]FIG. 22A is a schematic sectional view of a photoelectric transducer cell described in Japanese Patent Laid-Open Gazettes No. 12759/1985 to 12765/1985, and FIG. 22B is an equivalent circuit diagram of the cell.  
     [0285] Referring to FIGS. 22A and 22B, photoelectric transducer cells are formed on an n + -type silicon substrate  701 A and each photoelectric transducer cell is electrically insulated from adjacent photoelectric transducer cells by an element isolation region  700 A made of SiO 2 , SiH 3 N 4 , or polysilicon.  
     [0286] Each photoelectric transducer cell has the following structure.  
     [0287] A p-type region  704 A doped with a p-type impurity is formed on an n − -type region  703 A formed by an epitaxial technique and having a low impurity concentration. An n + -type region  705 A is formed in the p-type region  704 A by impurity diffusion or ion implantation. The p-type region  704 A and the n + -type region  705 A respectively serve as the base and emitter of a bipolar transistor.  
     [0288] An oxide film  706 A is formed on the n − -type region  703 A, and a capacitor electrode  707 A having a predetermined area is formed on the oxide film  706 A. The capacitor electrode  707 A opposes the p-type region  704 A through the oxide film  706 A and controls a potential of the p-type region  704 A floating upon application of a pulse voltage to the capacitor electrode  707 A.  
     [0289] In addition, an emitter electrode  708 A is connected to the n + -type region  705 A, an n + -type region  711 A having a high impurity concentration is formed on the lower surface of the substrate  701 A, and a collector electrode  712 A is formed to apply a potential to the collector of the bipolar transistor.  
     [0290] The basic operation of the above arrangement will be described. Assume that the p-type region  704 A serving as the base of the bipolar transistor is set at a negative potential. Light  713 A is incident from the side of the p-type region  704 A. Holes in the electron-hole pairs generated upon radiation are accumulated in the p-type region  714 A and the potential at the p-type region  714 A is increased by the accumulated holes in the positive direction (charge accumulation).  
     [0291] Subsequently, a positive read voltage is applied to the capacitor electrode  707 A, and a read signal corresponding to a change in base potential during charge accumulation is output from the floating emitter electrode  708 A (read operation). It should be noted that the amount of accumulated charge is rarely reduced in the p-type region  704 A serving as the base of the bipolar transistor, so that read access can be repeated.  
     [0292] In order to remove the holes from the p-type region  704 A, the emitter electrode  708 A is grounded, and a refresh pulse of a positive voltage is applied to the capacitor electrode  708 A. Upon application of the refresh pulse, the p-type region  704 A is forward-biased with respect to the n + -type region  705 A, thereby removing the holes. When the refresh pulse falls, the p-type region  704 A restores the initial state of the negative potential (refresh operation). Charge accumulation, read access, and refreshing are repeated as described above.  
     [0293] In order to restore the initial potential state of the p-type region  704 A by refreshing, a refresh pulse having a sufficient pulse width is required. To the contrary, the refresh pulse width must be shortened to achieve high-speed operation. In this case, when the refresh pulse width is short, satisfactory refreshing cannot be performed. Unnecessary components such as a dark signal and drive noise are added to the after image.  
     [0294]FIG. 23 is a graph showing the relationship  1  between a refresh pulse width t applied to the photoelectric transducer cell and the photoelectric transducer cell output.  
     [0295] Referring to FIG. 23, an output at t=0 is a read signal after charge accumulation and represents a read signal having a level corresponding to the intensity of the incident light.  
     [0296] The output level of such a photoelectric transducer is reduced by refreshing. However, the rate of change in output level and the level of the residual image upon refreshing vary depending on the intensity of the incident light.  
     [0297] When identical refreshing is performed, the levels of the residual signals are not constant. When the intensity of the incident light is high, the level of the residual signal is high. In other words, the after image is typically formed.  
     [0298] The residual signal level of high-intensity incident light is higher than that of low-intensity incident light but is greatly lowered as compared with the initial read signal level. The ratio of the unnecessary components contained in the read signal is substantially low. On the contrary, the residual signal level of the low-intensity incident light is low. A decrease in the residual signal level is small as compared with the initial read signal level. Therefore, the ratio of the unnecessary components included in the read signal is high.  
     [0299] Even in the photoelectric transducer cell having the above characteristics, by subtracting the residual signal obtain upon refreshing from the initial read signal, the above-mentioned specific after image components as well as the unnecessary components such as a dark signal and drive noise can be simultaneously removed.  
     [0300] A second embodiment of the present invention will be described below.  
     [0301]FIG. 24 is a circuit diagram for explaining the basic arrangement of an image pickup element according, to the second embodiment of the present invention.  
     [0302] Referring to FIG. 24, an emitter electrode  708 A of a photoelectric transducer cell S is connected to a vertical line VL and is grounded through a transistor Qr. The vertical line VL is connected to storage capacitors Ct 1  and Ct 2  through corresponding transistors Qt 1  and Qt 2 . The capacitors Ct 1  and Ct 2  are connected to output lines  721 A and  722 A through transistors Qs 1  and Qs 2 , respectively. The output lines  721 A and  722 A are connected to the input terminals of a differential amplifier  721 A, respectively.  
     [0303] A pulse ø from a scanning circuit SH is applied to the gate electrodes of the transistors Qs 1  and Qs 2 . Pulses øt 1  and øt 2  are applied to the gate electrodes of the transistors Qt 1  and Qt 2 , respectively. A pulse ørh is applied to the gate electrode of the transistor Qr. A read or refresh pulse ør is applied to a capacitor electrode  707 A of the photoelectric transducer cell S.  
     [0304] The operation of the above arrangement will be described below.  
     [0305]FIG. 25 is a timing chart for explaining the operation of the circuit shown in FIG. 24.  
     [0306] The transistors Qt 1 , Qt 2 , and Qr are turned on in response to the pulses øt 1 , øt 2 , and ørh, respectively, to clear the capacitors Ct 1  and Ct 2  (time interval T 1 ).  
     [0307] Subsequently, the pulse ør is supplied to the capacitor electrode  707 A while the transistor Qt 1  is kept on. The read signal from the photoelectric transducer cell S is stored in the capacitor Ct 1  (time interval T 2 ).  
     [0308] The transistor Qt 1  is turned off while the pulse ør is kept applied to the capacitor electrode  707 A. The transistor Qr is turned in on response to the pulse ørh. The photoelectric transducer cell S is refreshed in response to the pulse ørh (time interval T 3 ).  
     [0309] Upon completion of refreshing, the transistor Qt 2  is turned on in response to the pulse øt 2  while the pulse ør is kept applied to the capacitor electrode  707 A. The residual signal of the photoelectric transducer cell S is store in the capacitor Ct 2  (time interval T 4 ).  
     [0310] When the read and residual signals are stored in the capacitors Ct 1  and Ct 2 , respectively, the transistors Qs 1  and Qs 2  are turned on in response to the pulse ø. The read and residual signals are input to the differential amplifier  723 A through the corresponding output lines  721 A and  722 A. A signal Vout proportional to the difference between the read and the residual signals is output from the differential amplifier  723 A (time interval T 5 ).  
     [0311] As described above, the signal Vout is a signal free from the after image component and the unnecessary components such as a dark signal and drive noise and accurately corresponds to the intensity of the incident light. In particular, unnecessary component removal on the low-intensity side is effective, and an S/N ratio can be greatly increased.  
     [0312]FIG. 26 is a circuit diagram of an image pickup system of this embodiment. The circuit in FIG. 26 has n circuits of FIG. 24.  
     [0313] Referring to FIG. 26, the emitter electrodes  708 A of photoelectric transducer cells S 1  to Sn are respectively connected to vertical lines VL 1  to VLn. The same circuits as in FIG. 24 are connected to the vertical lines. The gate electrodes of the transistors Qr are commonly connected, and the pulse ørh is applied thereto. The gate electrodes of the transistors Qt 1  and the gate electrodes of the transistor Qt 2  are also commonly connected, and the pulses øt 1  and øt 2  are supplied to the common gate electrodes, respectively.  
     [0314] The gate electrodes of the transistors Qs 1  and Qs 2  corresponding to the photoelectric transducer cells S 1  to Sn are connected to the parallel output terminals of the scanning circuit SH and receive the pulses ø 1  to øn, respectively. The transistors Qs 1  are commonly connected to the output line  721 A and the transistors Qs 2  are commonly connected to the output line  722 A. These output lines are grounded through corresponding transistors  103 A. A reset pulse øhrs is supplied to the gate electrodes of the transistors  103 A.  
     [0315] A mode of operation of the arrangement described above will be briefly described with reference to FIG. 27A.  
     [0316]FIG. 27 is a timing chart for explaining the operation of the above arrangement.  
     [0317] As already described above, the capacitors Ct 1  and Ct 2  corresponding to each photoelectric transducer cell are cleared during the time interval T 1 . During the time interval T 2 , the read signal from each photoelectric transducer cell is stored in the corresponding capacitor Ct 1 . During the time interval T 3 , each photoelectric transducer cell is refreshed. During the time interval T 4 , the residual signal of each refreshed photoelectric transducer cell is stored in the corresponding capacitor Ct 2 .  
     [0318] After the read and residual signals of each photoelectric transducer cell are accumulated in the manner described above, the pulse ø 1  from the scanning circuit SH is supplied to the gate electrodes of the transistors Qs 1  and Qs 2 . The read and residual signals stored in the capacitors Ct 1  and Ct 2  of the photoelectric transducer cell S 1  are read out and appear on the output lines  721 A and  722 A. A difference between these signals is calculated by the differential amplifier  723 A, thereby removing the unnecessary components and hence obtaining the output signal Vout.  
     [0319] When a signal is output from the photoelectric transducer cell S 1 , the transistor  103 A is turned on in response to the pulse øhrs, and the charges left on the output lines  721 A and  722 A are removed.  
     [0320] In the same manner as described above, the read and residual signals of the photoelectric transducer cells S 2  to Sn are output from the capacitors Ct 1  and Ct 2  and appear on the output lines  721 A and  722 A and are subjected to subtractions by the differential amplifier  723 A, thereby sequentially outputting signals Vout.  
     [0321]FIG. 27B shows another mode of operation of the above arrangement.  
     [0322] During a time interval Ts, the base electrodes of the cells S are reverse-biased to perform charge accumulation. Upon completion of charge accumulation, unnecessary charges on the vertical transfer line VL and the storage capacitor Ct 1  are removed before the photoelectric transducer signals are transferred to the storage capacitor Ct 1  within a time interval Tvc.  
     [0323] Refreshing is performed again during a time interval Tc 1 , and drive noise is transferred to the storage capacitor Ct 2  during a time interval Tt 2 . Thereafter, the cell S is refreshed during a time interval Tc 2 , and the next charge accumulation cycle is initiated. The photoelectric transducer signal and drive noise which are stored in the storage capacitors Ct 1  and Ct 2  are output onto horizontal signal lines  721 A and  722 A, respectively.  
     [0324] In the above embodiment, the sensor shown in FIGS. 22A and 22B is exemplified. However, the present invention is not limited to any specific scheme of the photosensor.  
     [0325] The present invention can be applied to a color image pickup apparatus of a scheme for processing a plurality of horizontal line signals.  
     [0326]FIG. 28 is a circuit diagram of a third embodiment of the present invention, and FIG. 29 is a detailed circuit diagram of a readout circuit Ri in this embodiment. This embodiment exemplifies a scheme for processing a signal of two horizontal lines. This can apply to any scheme for processing a signal of three or more horizontal lines.  
     [0327] Referring to FIG. 28, photosensors S are arranged in an m×n area. Mosaic R, G, and B filters are arranged on the sensor surface.  
     [0328] Column photosensor outputs are respectively output to the readout circuits R 1  to Rn through vertical lines VL 1  to VLn.  
     [0329] Referring to FIG. 29, in any readout circuit Ri (i=1, 2, . . . n), the vertical lines VLi are connected to storage capacitors Ct 1  to Ct 4  through transistors Qt 1  to Qt 4 , and the capacitors Ct 1  to Ct 4  are connected to output lines  801 A to  804 A through transistors Qs 1  to Qs 4 , respectively. Since the scheme for processing a signal of two horizontal lines is used, two capacitors for storing the read signals and other two capacitors for storing residual signals are formed.  
     [0330] The gate electrodes of the transistors Qt 1  to Qt 4  are commonly connected through corresponding readout circuits R 1  to R 4 . Pulses ø 1  to ø 4  are supplied to the gate circuits of the transistors Qt 1  to Qt 4 .  
     [0331] A pulse øi from a horizontal scanning circuit SH is supplied to the transistors Qs 1  to Qs 4  of the readout circuit Ri. The transistors Qs 1  to Qs 4  are simultaneously turned on/off.  
     [0332] The output lines  801 A and  802 A are connected to the input terminals of a differential amplifier  805 A, and the output lines  803 A and  804 A are connected to the input terminals of a differential amplifier  806 . Signals OUT 1  and OUT 2  are output from the differential amplifiers  805 A and  806 A, respectively.  
     [0333] Two lines per field are selected by a vertical scanning circuit  807 A and an interlace circuit  808 A. Pairs of two horizontal scanning lines in units of fields are selected in response to pulses Vr 1  and Vr 2 .  
     [0334] The operation of the above circuit will be described with reference to FIG. 30.  
     [0335]FIG. 30 is a timing chart for explaining the operation of the above circuit.  
     [0336] Each photosensor read signal and its residual signal for two horizontal lines are read out during a horizontal blanking (HBLK) period and are stored in the storage capacitors in the readout circuits R 1  to Rn. Transfer of one of the two horizontal lines is performed during a time interval Ta in response to the pulse Vr 1 . Transfer of the remaining horizontal line is performed during a time interval Tb in response to the pulse Vr 2 .  
     [0337] The transfer operations are substantially the same as those in FIG. 26. However, since transfer is performed during the HBLK period, the transfer time can be shortened as compared with a scheme for processing a signal of one horizontal line. Clearing of the residual signal storage capacitor and its charge accumulation are performed during substantially equal time intervals T 3 ′ and T 3 ″. Smear generated during signal transfer is proportional to the transfer time. In this sense, T 2  (T 2 ′) and T 3 ′ (T 3 ″) are shortened to suppress the smearing phenomenon.  
     [0338] The capacitors Ct 1  and Ct 2  are cleared within a time interval T 1  in the time interval Ta. During a time interval T 2 , a pulse ør 1  is supplied to the first horizontal line in response to the pulse Vr 1 , and read signals of the photosensors on the first horizontal line are stored in the capacitors Ct 1  in the readout circuits R 1  to Rn. Subsequently, during a time interval T 3 ′, the photosensors of the first horizontal line are refreshed, and the residual signals upon completion of refreshing are stored in the capacitors Ct 2 .  
     [0339] During the next time interval Tb, the same transfer as in the first horizontal line is performed for the second horizontal line in response to the pulse ør 2  generated in response to the pulse Vr 2 . The read and residual signal of each photosensor for the second horizontal line are respectively stored in the capacitors Ct 3  and Ct 4 .  
     [0340] When the read and residual signals of the first and second horizontal lines are stored in the capacitors Ct 1  to Ct 4  of the readout circuits R 1  to Rn, the pulses ø 1  to øn from the horizontal scanning circuit SH are sequentially output to the readout circuits R 1  to Rn, so that an R- and G-dot sequential signal OUT 1  and a G- and B-dot sequential signal OUT 2  which are free from the unnecessary components are output from the differential amplifiers  805 A and  806 A, respectively. It should be noted that the signal OUT 1  is a G- and B-dot sequential signal and the signal OUT 2  is an R- and G-dot sequential signal in the next field.  
     [0341]FIG. 31 is a schematic block diagram of an image pickup system using the solid state image pickup apparatus as an image pickup device.  
     [0342] An image pickup device  901 A comprises an image pickup apparatus shown in FIGS. 28 and 29. The output signals OUT 1  and OUT 2  from the image pickup device  90 A are processed by an image processing circuit  903 A through a sample/hold (S/H) circuit  902 A to produce a standard television signal such as an NTSC signal.  
     [0343] Pulses for driving the image pickup device  901 A are supplied from a driver  904 A. The driver  904  is controlled by a control unit  905 A. The control unit  905 A also controls an exposure control unit  906 A to determine an intensity of light incident on the image pickup device  501 A.  
     [0344] According to the image pickup apparatus according to the third embodiment of the present, as described above, the residual signal is subtracted from the read signal of the photoelectric transducer cell upon its refreshing to remove the unnecessary components (e.g., a dark signal and drive noise) of the photoelectric transducer element, thereby obtaining a video signal having a high S/N ratio. As a result, a low-cost, compact image pickup apparatus can be manufactured.  
     [0345]FIG. 32 is a schematic view of an area sensor for simultaneously reading out signals of two horizontal lines. This circuit includes switching transistors Tr 11  to Tr 22 , bipolar transistors B-Tr 10  and B-Tr 20 , and capacitors Cox 10  and Cox 20 . In this sensor, a photoelectric transducer signal and drive noise of the bipolar transistor B-Tr 10  are respectively stored in the capacitors Ct 1  and Ct 2 . A photoelectric transducer signal and drive noise of the bipolar transistor B-Tr 20  are respectively stored in the capacitors Ct 3  and Ct 4 . When these signals are to be read out, the photoelectric transducer signals are simultaneously and independently read out onto horizontal signal lines S 2  and S 3 , and drive noise components are simultaneously output onto the horizontal signal line S 1 . Therefore, the drive noise components are output as a sum signal. R and G filters in an order of R, G, R, G, . . . are formed on photoelectric transducer elements of the even-numbered rows, and G and B filters in an order of G, B, G, B, . . . are arranged on photoelectric transducer elements of the odd-numbered rows.  
     [0346]FIG. 33 shows an image pickup system using the area sensor shown in FIG. 32.  
     [0347] The image pickup system includes an inversion amplifier  60 A, an adder  70 A, a color separation circuit  80 A, a color image signal processing system  90 A, an area sensor  10 ′A, a driver  20 ′A, and a clock generator  30 ′A.  
     [0348] Photoelectric transducer signals S 2  and S 3  read out from the area sensor  10 ′A are input to the adder  70 A and are averaged, thereby obtaining a signal in the form of R+2G+B. The drive noise is inverted by the inversion amplifier  60 A, and the inverted signal is input to the adder  70 A. The adder  70 A subtracts the drive noise from the photoelectric transducer signal, thereby producing a luminance signal Y consisting of only an information signal.  
     [0349] The color separation circuit  80 A receives the photoelectric transducer signals S 1  and S 2  and separates them into chrominance signals R, G, and B. The resultant signals Y, R, G, and B are processed by the color image signal processing system  90 A. The processing system  90 A generates a standard television signal such as an NTSC signal.  
     [0350] In the above embodiment, the scheme for simultaneously reading out signals of two horizontal lines is used. However, the present invention is applicable to a scheme for simultaneously reading out signals of three horizontal signals.  
     [0351] The storage capacitors can be omitted if the image pickup apparatus includes a shutter.  
     [0352] A subtracter for removing the drive noise may be connected to the output terminal within the apparatus.  
     [0353] In the above embodiment, the drive noise can be output independently of the photoelectric transducer signal, so that an external large-capacity memory need not be arranged.  
     [0354] In the horizontal line readout scheme, since the noise components can be added and its sum can be output, the number of horizontal signal lines can be reduced. Therefore, a multi horizontal line readout scheme can be easily achieved.  
     [0355]FIG. 34 shows still another embodiment of the present invention. In this embodiment, the differential amplifier  723 A in FIG. 24 is replaced with a clamp circuit. The same reference numerals as in FIGS.  15  to  33  denote the same parts in FIG. 34.  
     [0356]FIG. 35 is a timing chart for explaining the operation of the circuit shown in FIG. 34.  
     [0357] Cells S are reverse-biased to perform charge accumulation during a time interval Ts. Upon completion of charge accumulation, the unnecessary charges on the vertical transfer lines VL and in the storage capacitors Ct 1  are removed prior to transfer of photoelectric transducer signals within a time interval Tvc. The photoelectric transducer signal is transferred to a corresponding storage capacitor Ct 1  during the time interval Tt 1 .  
     [0358] Refreshing is performed during a time interval Tc 1 , and drive noise is transferred to the storage capacitor Ct 2  during a time interval Tt 2 . Thereafter, the cells S are refreshed during a time interval of Tc 2 , and the next charge accumulation cycle is initiated. The photoelectric transducer signals and the drive noise are independently obtained. The signals stored in the storage capacitors Ct 1  and Ct 2  are dot-sequentially transferred on a single signal line S in response to drive pulses øs 1  and øs 2 . This operation occurs during time intervals TR 1  and TR 2 . A drive pulse øhrs is used to reset the signal line to the reference potential. The signal obtained by the above-mentioned read operation represents a waveform of an output Vout. The drive noise and the photoelectric transducer signal are represented by W and S′, respectively.  
     [0359] The dot sequential signal S is input to a clamp circuit  1 A, and only the drive noise N is clamped in accordance with a drive pulse øs 2 . As a result, the drive noise N is eliminated, and a true information signal indicated by a hatched portion in FIG. 35 can be obtained.  
     [0360]FIG. 36 is a schematic circuit diagram of an area sensor constituted by the photoelectric transducer elements shown in FIG. 34. Referring to FIG. 36, the area sensor includes a vertical shift register V•SR, a horizontal shift register H•SR, and Smn, base accumulation type transistors arranged in an m×n matrix. The operation of the area sensor is basically the same as that of the photoelectric transducer element shown in FIG. 34, except that the area sensor performs horizontal scanning and vertical scanning, and a detailed description thereof will be omitted. Clamping of the read signal, which is the characteristic feature of this embodiment shown in FIG. 36, will be described in detail.  
     [0361] A schematic waveform of the read signal is shown in FIG. 37. A signal S′ appears on a read signal line S, and a pulse øs 2  is a drive pulse. Referring to FIG. 37, drive noise and the photoelectric signal of a cell S 11  correspond to N 1  and S 1 , respectively. A cell S 12  outputs signals N 2  and S 2 , a cell S 13  outputs signals N 3  and S 3 , a cell S 14  outputs signals N 4  and S 4 , . . . . The drive noise component of the dot sequential signal is clamped in response to the drive pulse øs 2 . As a result, the drive noise is removed, and only the true information signal can be obtained.  
     [0362] The above embodiment exemplifies a scheme for reading out a signal of one horizontal line. However, this embodiment may be applied to a scheme for reading out a signal of one horizontal line in a time-divisional manner or a scheme for simultaneously reading signals of a plurality of horizontal lines, as shown in FIG. 28.  
     [0363] The base accumulation type transistor is exemplified as the photoelectric transducer element. However, a MOS or SIT image pickup device may be used as the photoelectric transducer element.  
     [0364] In the above embodiment, the drive noise and the photoelectric tansducer signal are converted into a dot sequential signal, and clamping can be easily performed, thereby easily removing the drive noise.