Patent Publication Number: US-8530323-B2

Title: Capacitor and method for fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a Division of pending U.S. application Ser. No. 12/603,124, filed on Oct. 21, 2009, which claims the benefit under 35 U.S.C. §119(a) of Korean Patent Application No. 10-2008-0133890 filed on Dec. 24, 2008, in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field 
     The following description relates to semiconductor fabrication technology; and, for example, to a metal-insulator-metal (MIM) capacitor and a method for fabricating the same. 
     2. Description of Related Art 
     An MIM capacitor is used in an analog circuit and a radio frequency (RF) circuit. The MIM capacitor is used when a capacitor of a high quality factor Q having a low serial resistance is needed. Furthermore, the MIM capacitor is used on behalf of analog capacitors due to its low thermal budget and low power voltage and low parasitic capacitance. 
       FIGS. 1A to 1E  are cross-sectional views illustrating a conventional method for fabricating an MIM capacitor. 
     As shown in  FIG. 1A , a lower metal line  102  is formed on a substrate  101 . A lower electrode  103 , a dielectric layer  104 , and an upper electrode  105  are sequentially formed on the lower metal line  102 . 
     Referring to  FIG. 1B , the upper electrode  105  is etched to form an upper electrode pattern  105 A, and the dielectric layer  104  is also partially etched to form a first dielectric layer pattern  104 A. Here, the first dielectric layer pattern  104 A remains on the lower electrode  103  in a predetermined thickness. 
     Referring to  FIG. 1C , the remaining first dielectric layer pattern  104 A is etched to form a second dielectric layer pattern  104 B. 
     Referring to  FIG. 1D , the lower electrode  103  and the lower metal line  102  are sequentially etched to form a lower electrode pattern  103 A and a lower metal line pattern  102 A. 
     Referring to  FIG. 1E , by performing a line process after forming an inter-layer insulation layer  106 , first and second vias  107  and  108  are formed inside the inter-layer insulation layer  106 , and an upper metal line  111  is formed thereon. The upper metal line  111  is a stack layer of first and second layers  109  and  110 . 
     In the conventional method of fabricating the MIM capacitor, due to polymer or various kinds of conductive residues, the upper electrode pattern  105 A is not electrically isolated from the lower electrode pattern  103 A or the lower metal line pattern  102 A, which functions as a part of the lower electrode pattern  103 A. As a result, they may be shorted and, consequently, a leakage current may be generated. 
     SUMMARY 
     In one general aspect, there is provided a method for fabricating a capacitor, the method including forming a dielectric layer over a lower electrode on a substrate, forming an upper electrode over the dielectric layer, forming a hard mask over the upper electrode, etching the hard mask to form a hard mask pattern, etching the upper electrode to make the dielectric layer remain on the lower electrode in a predetermined thickness, forming an isolation layer along an upper surface of the remaining dielectric layer and the hard mask pattern, leaving the isolation layer having a shape of a spacer on one sidewall of the hard mask pattern, the upper electrode, and the dielectric layer, and etching the lower electrode to be isolated. 
     A general aspect of the method may further provide that the leaving of the isolation layer includes forming a predetermined portion of the dielectric layer to extend to a lower side of the isolation layer. 
     A general aspect of the method may further provide that the forming of the predetermined portion includes aligning the extended portion of the dielectric layer with one side of the isolation layer. 
     A general aspect of the method may further provide that the extended portion of the dielectric layer has a uniform thickness within variation ranging from approximately 10 Å to approximately 20 Å in a wafer. 
     A general aspect of the method may further provide that a thickness of the extended portion of the dielectric layer is less than a thickness of a portion of the dielectric layer between the upper electrode and the lower electrode. 
     A general aspect of the method may further provide that the extended portion of the dielectric layer has a thickness ranging from approximately 30 Å to approximately 100 Å. 
     A general aspect of the method may further provide that the etching of the hard mask is performed by using a photoresist pattern as an etch mask. 
     A general aspect of the method may further provide removing the photoresist pattern after the forming of the hard mask. 
     A general aspect of the method may further provide performing a clean process after the removing of the photoresist pattern. 
     A general aspect of the method may further provide that the etching of the upper electrode is performed by a main etch process and an over-etch process, the main etch process having a duration that is greater by a predetermined amount than a duration of the over-etch process. 
     A general aspect of the method may further provide that the main etch process is performed for approximately 100 seconds to approximately 130 seconds. A general aspect of the method may further provide that the over-etch process is performed for approximately 20 seconds to approximately 30 seconds. 
     A general aspect of the method may further provide that the main etch process is performed by using chlorine (Cl) gas and nitrogen (N 2 ) gas. 
     A general aspect of the method may further provide that the over-etch process is performed by using boron trichloride (BCl 3 ) gas and argon (Ar) gas. 
     A general aspect of the method may further provide that the main etch process is performed until the dielectric layer remains on the lower electrode in a predetermined thickness. 
     A general aspect of the method may further provide that the hard mask pattern is formed of an oxide layer or a nitride layer. 
     A general aspect of the method may further provide that the isolation layer is formed of an oxide layer or a nitride layer. 
     A general aspect of the method may further provide that during the leaving of the isolation layer, an etch-back process or a blanket process is performed. 
     A general aspect of the method may further provide forming an inter-layer insulation layer to cover the upper electrode and the substrate after the etching the lower electrode to be isolated, etching the inter-layer insulation layer and the hard mask pattern to form first and second holes to partially expose the lower electrode and the upper electrode, forming first and second vias to fill the first and second holes, and forming a plurality of upper metal lines, each coupled to the first and second vias. 
     A general aspect of the method may further provide that each of the upper and lower electrodes is selected from the group consisting of ruthenium (Ru), strontium ruthenate (SrRuO 3 ), platinum (Pt), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), cobalt (Co), copper (Cu), hafnium (Hf), and a combination thereof. 
     A general aspect of the method may further provide that the dielectric layer is selected from the group consisting of silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), strontium titanate (SrTiO 3 ), Perofskite (CaTiO 3 ), lanthanum aluminate (LaAlO 3 ), barium zirconia (BaZrO 3 ), barium zircon titanate (BaZrTiO 3 ), strontium zircon titanate (SrZrTiO 3 ), and a combination thereof. 
     A general aspect of the method may further provide that the leaving of the isolation layer includes separating the isolation layer from the lower electrode using the dielectric layer. 
     A general aspect of the method may further provide that, in the etching of the hard mask, a fluorocarbon gas is used as a main gas, and a gas selected from the group consisting of oxygen (O 2 ) gas, nitrogen (N 2 ) gas, and argon (Ar) gas is used as a supplementary gas. 
     A general aspect of the method may further provide that the fluorocarbon gas is selected from the group consisting of Perfluoromethane (CF 4 ), Trifluoromethane (CHF 3 ), Hexafluoroethane (C 2 F 6 ), Octafluoroethane (C 2 F 8 ), Octafluorocyclobutane (C 4 F 8 ), and a combination thereof. 
     A general aspect of the method may further provide that, in the etching of the upper electrode, a chlorine-based gas is used as a main gas, and a gas selected from the group consisting of nitrogen gas and argon gas is used as a supplementary gas. 
     A general aspect of the method may further provide that the chlorine-based gas is selected from the group consisting of chlorine (Cl 2 ), Boron Trichloride (BCl 3 ), carbon chloride (CCl), hydrochloride (HCl), chlorotrifluoromethane (CF 3 Cl), tetraclorosilane (SiCl 4 ), and a combination thereof. 
     Other features and aspects may be apparent from the following detailed description, the drawings, and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A to 1E  are cross-sectional views illustrating a conventional method for fabricating an MIM capacitor. 
         FIGS. 2A to 2D  are cross-sectional views illustrating an example of a method for fabricating an MIM capacitor in accordance with a first example embodiment. 
         FIG. 3  is a graph illustrating an example of comparison results of a leakage current in accordance with the first example embodiment and the conventional method. 
         FIG. 4  is a plan view illustrating an example of a metal line fabricated in accordance with the first example embodiment. 
         FIG. 5  is a plan view illustrating an example of a via fabricated in accordance with the first example embodiment. 
         FIG. 6  is a graph illustrating an example of comparison results of a resistance of via contacts in accordance with the first example embodiment and the conventional method. 
         FIGS. 7A to 7F  are cross-sectional views illustrating an example of a method for fabricating an MIM capacitor in accordance with a second example embodiment. 
         FIG. 8  is a graph illustrating an example of comparison results of a leakage current in accordance with the first and second example embodiments and the conventional method. 
         FIG. 9  is a graph illustrating an example of comparison results of a resistance of via contacts in accordance with the first and second example embodiments and the conventional method. 
     
    
    
     Throughout the drawings and the detailed description, unless otherwise described, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The relative size and depiction of these elements may be exaggerated for clarity, illustration, and convenience. 
     DETAILED DESCRIPTION 
     The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein. Accordingly, various changes, modifications, and equivalents of the systems, apparatuses and/or methods described herein will be suggested to those of ordinary skill in the art. Also, descriptions of well-known functions and constructions may be omitted for increased clarity and conciseness. 
     It is understood that the features of the present disclosure may be embodied in different forms and should not be constructed as limited to the example embodiment(s) set forth herein. Rather, embodiment(s) are provided so that this disclosure will be thorough and complete, and will convey the full scope of the present disclosure to those skilled in the art. The drawings may not be necessarily to scale, and, in some instances, proportions may have been exaggerated in order to clearly illustrate features of the embodiment(s). 
     It will also be understood that when a layer (or film) is referred to as being ‘on’ another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. Further, it will be understood that when a layer is referred to as being ‘under’ another layer, it can be directly under, and one or more intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being ‘between’ two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. Furthermore, it will also be understood that when each reference numeral includes an English character, it can mean that the same layer is partially changed through an etch process, a polish process and the like. 
     First Example Embodiment 
       FIGS. 2A to 2D  are cross-sectional views illustrating an example of a method for fabricating an MIM capacitor in accordance with a first example embodiment. 
     Referring to  FIG. 2A , a lower metal line  202  is formed on a substrate  201 . Here, the lower metal line  202  is selected from the group consisting of a transition metal. The lower metal line  202  may be formed of any metal among aluminum (Al), copper (Cu), and platinum (Pt). The thickness of the lower metal line  202  may vary according to a specific resistance Rs required for a line process of a corresponding layer. 
     Subsequently, a lower electrode  203  is formed over the lower metal line  202 . The lower electrode  203  includes antireflection materials and may be selected from the group consisting of ruthenium (Ru), strontium ruthenate (SrRuO 3 ), platinum (Pt), tantalum nitride (TaN), tungsten nitride (WN), titanium nitride (TiN), titanium aluminum nitride (TiAlN), cobalt (Co), copper (Cu), hafnium (Hf), and a combination thereof. 
     Subsequently, a dielectric layer  204  is formed over the lower electrode  203 . The dielectric layer  204  includes insulation materials and may be selected from the group consisting of silicon nitride (SiN), silicon oxide (SiO 2 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), strontium titanate (SrTiO 3 ), Perofskite (CaTiO 3 ), lanthanum aluminate (LaAlO 3 ), barium zirconia (BaZrO 3 ), barium zircon titanate (BaZrTiO 3 ), strontium zircon titanate (SrZrTiO 3 ), and a combination thereof. 
     Subsequently, an upper electrode  205  is formed over the dielectric layer  204 . The upper electrode  205  may be formed of substantially the same materials as the lower electrode  203 . For example, the upper electrode  205  may be selected from the group consisting of Ru, SrRuO 3 , Pt, TaN, WN, TiN, TiAIN, Co, Cu, Hf, and a combination thereof. 
     Referring to  FIG. 2B , the upper electrode  205  is etched to form an upper electrode pattern  205 A. Herein, an over-etch process is performed. That is, through the etch process, the upper electrode  205  is etched to form the upper electrode pattern  205 A, and, at the same time, the dielectric layer  204  is also partially etched to form a first dielectric layer pattern  204 A remaining on the lower electrode  203 . The etch process may use chlorine-based gas as a main gas, and a gas selected from the group consisting of nitrogen (N 2 ) gas and argon (Ar) gas as a supplementary gas. The chlorine-based gas may be selected from the group consisting of chlorine (Cl 2 ), Boron Trichloride (BCl 3 ), carbon chloride (CCl), hydrochloride (HCl), chlorotrifluoromethane (CF 3 Cl), tetraclorosilane (SiCl 4 ), and a combination thereof. 
     Referring to  FIG. 2C , the remaining first dielectric layer pattern  204 A, the lower electrode  203  and the lower metal line  202  are sequentially etched to form a second dielectric layer pattern  204 B, a lower electrode pattern  203 A, and a lower metal line pattern  202 A partially exposing a surface of the substrate  201 . Accordingly, a desired profile of the MIM capacitor may be formed as shown in  FIG. 2C . 
     Referring to  FIG. 2D , a line process is performed as follows. After forming an inter-layer insulation layer  206  over the substrate  201  and the MIM capacitor, the lower electrode pattern  203 A and the upper electrode pattern  205 A are partially exposed to thereby form first and second holes (not shown). Thereafter, first and second vias  207  and  208  are formed to fill the first and second holes. Then, a plurality of upper metal lines  211  are formed thereon to be electrically coupled with the first and second vias  207  and  208 . 
     Each of the upper metal lines  211  includes a first conductive layer  209 , which may substantially function as a metal line, and a second conductive layer  210  formed over the first conductive layer  209 . The first conductive layer  209  is selected from the group consisting of a transition metal. The first conductive layer  209  may be formed of any metal among aluminum (Al), copper (Cu), and platinum (Pt). The second conductive layer  210  may be selected from the group consisting of Ru, SrRuO 3 , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, and a combination thereof. 
     According to the teachings above, there is provided a method for fabricating the MIM capacitor in accordance with the first embodiment, in which the lower electrode pattern  203 A is electrically isolated from the upper electrode pattern  205 A by leaving a predetermined thickness of the second dielectric layer pattern  204 B over the lower electrode pattern  203 A, as shown in  FIG. 2C , which may server to prevent a short between the lower electrode pattern  203 A and the upper electrode pattern  205 A due to various residues generated during plural fabricating processes. 
       FIG. 3  is a graph illustrating an example of comparison results of a leakage current in accordance with the first example embodiment and the conventional method. 
     As shown in  FIG. 3 , a characteristic of the leakage current of the MIM capacitor in accordance with the first example embodiment is better than that of the conventional method. 
     In the first example embodiment, the predetermined thickness of the second dielectric layer pattern  204 B remains over the lower electrode pattern  203 A as shown in  FIG. 2C . In case that the dielectric layer is formed of metal oxide materials having a high dielectric constant such as aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO), tantalum oxide (Ta 2 O 5 ), the remaining dielectric layer may affect a subsequent process. 
       FIG. 4  is a plan view illustrating an example of a metal line fabricated in accordance with the first example embodiment. 
     As shown in  FIG. 4 , when the dielectric layer remains over the lower electrode, it requires an additional etch process to the dielectric layer. Accordingly, a margin of a photoresist is insufficient, and a profile of the metal line has a poor characteristic due to a conductive polymer. 
       FIG. 5  is a plan view illustrating an example of a via fabricated in accordance with the first example embodiment. 
     As shown in  FIG. 5 , when the dielectric layer remains over the lower electrode, the conductive polymer remains inside the via during an etch process for forming the via where the metal line is formed. If the conductive polymer remains inside the via, a resistance of via contacts is increased so that a device characteristic is deteriorated. 
       FIG. 6  is a graph illustrating an example of comparison results of a resistance of via contacts in accordance with the first example embodiment and the conventional method. 
     As shown in  FIG. 6 , the resistance of via contacts in accordance with the first example embodiment is increased in comparison with the conventional method. That is, when the dielectric layer remains over the lower electrode, the resistance of the via contact becomes increased. 
     Second Example Embodiment 
       FIGS. 7A to 7F  are cross-sectional views illustrating an example a method for fabricating an MIM capacitor in accordance with a second example embodiment. 
     Referring to  FIG. 7A , a lower metal line  302  is formed on a substrate  301 . A lower electrode  303 , a dielectric layer  304  and an upper electrode  305  are sequentially formed over the lower metal line  302 . 
     Subsequently, a hard mask  306  is formed over the upper electrode  305 . The hard mask  306  may be formed of an oxide layer such as undoped silicate glass (USG), tetraethyl orthosilicate (TEOS) and high density plasma (HDP), or a nitride layer such as silicon nitride (SiN) or silicon oxynitride (SiON) through a low pressure chemical vapor deposition (LPCVD) process. The hard mask  306  is formed with a thickness ranging from approximately 100 Å to approximately 4000 Å. 
     Referring to  FIG. 7B , a photoresist pattern (not shown) is formed over the hard mask  306 . An etch process is performed to etch the hard mask  306  by using the photoresist pattern as an etch mask to thereby form a hard mask pattern  306 A. Here, the etch process uses a fluorocarbon gas as a main gas, and a gas selected from the group consisting of oxygen (O 2 ) gas, nitrogen (N 2 ) gas and argon (Ar) gas as a supplementary gas. The fluorocarbon gas may be selected from the group consisting of Perfluoromethane (CF 4 ), Trifluoromethane (CHF 3 ), Hexafluoroethane (C 2 F 6 ), Octafluoroethane (C 2 F 8 ), Octafluorocyclobutane (C 4 F 8 ), and a combination thereof. After the hard mask pattern  306 A is formed, the photoresist pattern is removed and a clean process may be performed thereon. 
     Subsequently, the upper electrode  305  is etched to form an upper electrode pattern  305 A. Herein, the upper electrode  305  is etched by using the photoresist pattern as an etch mask, or using only the hard mask pattern  306 A as an etch mask. The upper electrode  305  may be etched by using chlorine-based gas as a main gas, and a gas selected from the group consisting of nitrogen gas and argon gas as a supplementary gas. The chlorine-based gas may be selected from the group consisting of chlorine (Cl 2 ), Boron Trichloride (BCl 3 ), carbon chloride (CCl), hydrochloride (HCl), chlorotrifluoromethane (CF 3 Cl), tetraclorosilane (SiCl 4 ), and a combination thereof. 
     When using only the hard mask pattern  306 A as an etch mask, a strip process is performed to remove the photoresist pattern before etching the upper electrode  305 . The strip process is performed by using O 2  plasma. The photoresist pattern is removed before etching the upper electrode  305  because the materials of the photoresist pattern function as sources generating the polymer. 
     Meanwhile, it is possible to remove the photoresist pattern after etching the upper electrode  305 , not before etching the upper electrode  305 . Herein, plural polymers may be generated around the upper electrode  305  during etching the upper electrode  305 . Since the generated polymers are not removed during subsequent processes, a leakage current of the MIM capacitor may be caused. Accordingly, it is desirable that the photoresist pattern is removed before etching the upper electrode  305 . 
     In another example embodiment , a two-step process may be performed to etch the upper electrode  305 . The two-step process includes a main etch process and an over-etch process. The main etch process is performed for a predetermined time longer than that of the over-etch process. The main etch process may be performed for approximately 100 seconds to approximately 130 seconds, and the over-etch process is performed for approximately 20 seconds to approximately 30 seconds. The main etch process is performed by using chlorine (Cl) gas and nitrogen (N 2 ) gas, and the over-etch process is performed by using boron trichloride (BCl 3 ) gas and argon (Ar) gas. The main etch process may be performed until a predetermined thickness of the dielectric layer  304  remains to form a dielectric layer pattern  304 A. 
     The two-step process is used to etch the upper electrode  305  in order to secure uniformity to the remaining thickness of the dielectric layer pattern  304 A after etching the upper electrode  305 . The dielectric layer pattern  304 A may be formed of metal oxide materials having a high dielectric constant, i.e., a high permittivity layer. The high permittivity layer has a lower etch rate compared to a silicon oxide layer, thereby deteriorating etch uniformity. 
     During the main etch process for etching the upper electrode  305  using chlorine (Cl) gas and nitrogen (N 2 ) gas, an etch rate around a wafer is faster than that at the center of the wafer. On the contrary, during the main etch process for etching the dielectric layer pattern  304 A exposed after etching the upper electrode  305 , which is performed under the same conditions, an etch rate at the center of a wafer is faster than that around the wafer. During the over-etch process using boron trichloride (BCl 3 ) gas and argon (Ar) gas, an etch rate around the wafer is faster than that at the center of the wafer. As a result, the uniformity to the remaining thickness of the dielectric layer pattern  304 A of the high permittivity layer is determined by combining the etch rates of those processes. 
     In the conventional method, an over-etch process is performed after finishing etching the upper electrode. On the contrary, in the present example embodiment, the main etch process is performed on the dielectric layer in advance. Then, the over-etch process is continuously performed thereon, thereby possibly improving the uniformity in the remaining thickness of the dielectric layer. 
     For reference, during the etching of the upper electrode  305 , the dielectric layer pattern  304 A remaining after the performing of the main etch process and the over-etch process includes a first thickness extended to a lower side of an isolation layer pattern having a shape of a spacer, which is shown as reference symbol  307 A in  FIG. 7D , and a second thickness between the upper electrode pattern  305 A and the lower electrode  303 . The first thickness is thinner than the second thickness. The first thickness may have an uniform thickness ranging from approximately 30Å to approximately 100 Å within variation ranging from approximately 10 Å to approximately 20 Å in the wafer. 
     Referring to  FIG. 7C , an isolation layer  307  is formed along an upper surface of the remaining dielectric layer pattern  304 A and the hard mask pattern  306 A. The isolation layer  307  has an etch selectivity to the hard mask pattern  306 A. For example, the isolation layer  307  is formed of a nitride layer when the hard mask pattern  306 A is formed of an oxide layer, and the isolation layer  307  is formed of an oxide layer when the hard mask pattern  306 A is formed of a nitride layer. Both the hard mask pattern  306 A and the isolation layer  307  may be formed of a nitride layer, or both the hard mask pattern  306 A and the isolation layer  307  may be formed of an oxide layer. Herein, the oxide layer includes USG, TEOS or HDP, and the nitride layer includes SiN or SiON. The isolation layer  307  is formed in a predetermined thickness ranging from approximately 100 Å to approximately 4000 Å. 
     Referring to  FIG. 7D , the isolation layer  307  is etched to form an isolation layer pattern  307 A remaining on one sidewall of the hard mask pattern  306 A, the upper electrode pattern  305 A, and the dielectric layer pattern  304 A. Herein, the etch process is a dry etch process. The etch process may include an etch-back process or a blanket process. The etch process may be performed to etch the dielectric layer pattern  304 A remaining over the lower electrode  303  shown in  FIG. 7C . Accordingly, one side of the dielectric layer pattern  304 A extended to a lower side of the isolation layer pattern  307 A is aligned with one side of the isolation layer pattern  307 A, which is an opposite side to the upper electrode pattern  305 A. 
     Referring to  FIG. 7E , the lower electrode  303  and the lower metal line  302  are sequentially etched to form a lower electrode pattern  303 A and a lower metal line pattern  302 A partially exposing a surface of the substrate  301 . 
     Referring to  FIG. 7F , a line process is performed to sequentially form first and second interconnection metal lines  309  and  310 , and a plurality of upper metal lines  313 . The line process is performed as follows. First, after forming an inter-layer insulation layer  308 , the lower electrode pattern  303 A and the upper electrode pattern  305 A are partially exposed to thereby form first and second vias (not shown). Thereafter, the first and second interconnection metal lines  309  and  310  are formed to fill the first and second vias, and then the upper metal lines  313  are formed thereon to be electrically coupled with the first and interconnection metal lines  309  and  310 . 
     Like the first example embodiment, the upper metal lines  313  include a first conductive layer  311 , which may substantially function as a metal line, and a second conductive layer  312  formed over the first conductive layer  311 . The first conductive layer  311  may be selected from the group consisting of a transition metal, and the second conductive layer  313  may be selected from the group consisting of Ru, SrRuO 3 , Pt, TaN, WN, TiN, TiAlN, Co, Cu, Hf, and a combination thereof. 
       FIG. 8  is a graph illustrating an example of comparison results of a leakage current in accordance with the first and second example embodiments and the conventional method. 
     As shown in  FIG. 8 , like the first example embodiment, a characteristic of the leakage current of the MIM capacitor in accordance with the second example embodiment is improved. 
       FIG. 9  is a graph illustrating comparison results of a resistance of via contacts in accordance with the first and second example embodiments of the present invention and the conventional method. 
     As shown in  FIG. 9 , the resistance of via contacts in accordance with the second example embodiment is improved in comparison with the first example embodiment and the conventional method. 
     The example embodiments may have the following effects. 
     First, an isolation layer may be formed with a shape of a spacer on one sidewall of an upper electrode and a dielectric to thereby electrically isolate the upper electrode and a lower electrode. Accordingly, a characteristic of a leakage current of an MIM capacitor may be improved by fundamentally preventing the upper electrode and the lower electrode from being short. 
     Second, a process for forming vias to connect an upper metal line and a lower electrode may be performed in a state that a predetermined portion of a dielectric layer remaining on the lower electrode, which does not overlap the upper metal line, is removed. Consequently, a resistance of via contacts caused by the remaining dielectric layer may be improved. 
     Third, a hard mask pattern may be formed on an upper electrode and an isolation layer having a shape of a spacer may be formed on one sidewall of the upper electrode to thereby entirely separate the upper electrode from the external environment. As a result, a leakage current characteristic of an MIM capacitor may be improved, and thus a reliability may be improved. 
     Fourth, an etch process to an upper electrode may be performed in a state that a photoresist pattern does not exist by removing the photoresist pattern prior to the etch process to the upper electrode after forming a hard mask pattern. As a result, it may be possible to prevent polymers from being generated by the photoresist pattern during the etching of the upper electrode. 
     Fifth, when performing an etch process to an upper electrode, a main etch process may be performed for a predetermined time longer than that of an over-etch process. Accordingly, after finishing the etch process to the upper electrode, a thickness of a dielectric layer remaining on a lower electrode may be uniformly maintained within variation range of approximately 20 Å in a wafer. 
     A number of examples have been described above. Nevertheless, it will be understood that various modifications may be made. For example, suitable results may be achieved if the described techniques are performed in a different order and/or if components in a described system, architecture, device, or circuit are combined in a different manner and/or replaced or supplemented by other components or their equivalents. Accordingly, other implementations are within the scope of the following claims.