Patent Publication Number: US-2020279968-A1

Title: Interdigitated back-contacted solar cell with p-type conductivity

Description:
FIELD OF THE INVENTION 
     The present invention relates to a back-contacted p-type solar cell. In addition, the invention relates to a solar panel or photovoltaic module comprising at least one such solar cell. 
     BACKGROUND 
     A conventional p-type IBC (Interdigitated Back-Contacted) solar cell has on its rear side regions of either a p-type base or diffused n-type emitter. It is a challenge to select a dielectric layer that can passivate both regions equally well. Most dielectric layers have a surface charge. Well-known passivating dielectric layer are aluminum oxide (alumina, Al 2 O 3 ) with a negative surface charge and hydrogenated amorphous silicon nitride (a-SiN x :H) with a positive surface charge. 
     If Al 2 O 3  is applied over the entire rear surface of a p-type IBC solar cell this has a beneficial effect on the surface recombination at the p-type base region. In that case electrons (minority carriers) are repelled while holes (majority carriers) are attracted, which is denoted as “accumulation”. Since the minority carrier concentration is the limiting factor it determines the surface recombination rate. In this way, the surface recombination rate at the p-type base surface can be reduced, which contributes to a high open-circuit voltage. However, at the n-type region (the emitter) the mechanism works in the opposite direction. Here, holes (minority carriers) are attracted and electrons (majority carriers) are repelled. This increases surface recombination, since also here the minority carrier concentration, which are in this area the holes, sets the rate of recombination. 
     If the doping concentration of the n-type emitter decreases, which is usually beneficial for the reduction of surface recombination, the effect becomes stronger. The worst case occurs when the product of the concentration of electrons N e  and the capture cross section σ e  for electrons equals those parameters N h , σ h  of holes (i.e. N e  σ e =N h  σ h ). 
     This situation is denoted as “depletion”, since the sum of concentration of electrons and holes is in that case minimal. 
     Hoex et al., in “Surface passivation of phosphorus-diffused n+-type emitters by plasma-assisted atomic-layer deposited Al 2 O 3 ”, Phys. Status Solidi RRL 6, No. 1, 4-6 (2012)/DOI 10.1002/pssr.201105445, show a minimum in implied V oc  of an non-metallized solar cell that illustrates this situation ( FIG. 3 , ibid.). 
     Further reduction of the doping concentration leads to “inversion” in the emitter, which means that the electron concentration becomes lower than the hole concentration. This can be beneficial for surface recombination reduction, but leads to a non-functional solar cell. 
     If, on the contrary, a dielectric with a positive surface charge, like a-SiN x :H, is deposited on the p/n+ rear surface of the conventional p-type IBC cell, the physics work in the opposite way. The positive surface charge has beneficial effect on the emitter surface recombination and, in general, the surface recombination current jo decreases with decreasing doping surface concentration (which in practice means an increasing emitter sheet resistance). 
     However, on the lowly doped p-type substrate, typically having a resistivity of 1-3 Ω·cm, the strong positive surface charge leads to inversion. The implies that base surface region has become a surface-charge induced (i.e., non-diffused) emitter which extends towards the base contact. It is well known that this leads to shunts, causing extreme poor cell results. 
     A possible solution to the above problem is to create a dielectric layer with a (near-) zero surface charge. However, it has shown to be quite difficult to process these dielectric layers. Moreover, the quality of the passivation does not depend anymore on the field effect but only on the so-called “chemical passivation”, which is in general much harder to realize. An example of such a layer is intrinsic amorphous silicon of which the chemical surface recombination is very good provided that the wet chemical pretreatment is of a very high standard. However, such a layer is known not to be stable at high temperatures and therefore not suitable in combination with mainstream firing process of screen-printed metal contacts. 
     It is an object of the present invention to overcome or mitigate one or more of the problems of the prior art. 
     SUMMARY OF THE INVENTION 
     The object is achieved by a back-contacted solar cell based on a silicon substrate of p-type conductivity having a front surface for receiving radiation and a rear surface; in which the rear surface is provided with a tunnel oxide layer and a doped polysilicon layer of n-type conductivity; the tunnel oxide layer and the doped polysilicon layer of n-type conductivity forming a patterned layer stack, is provided with gaps in the patterned layer stack; an Al—Si contact is arranged within each of the gaps, in electrical contact with a base layer of the substrate, and one or more Ag contacts is arranged on the patterned doped polysilicon layer and in electrical contact with the patterned doped polysilicon layer. 
     According to the invention, there is provided a p-type IBC solar cell with a patterned stack layer of tunnel oxide and n-type polysilicon emitter region. The tunnel-oxide is typically 0.5-2 nm thick and can be made by wet chemical oxidation (e.g. with a HNO 3  solution) or by gas-based oxidation at elevated temperatures. 
     In such a solar cell, the passivating properties are determined by the silicon oxide surface of the tunnel oxide layer. Also, the passivation of dangling bonds of the silicon substrate surface by hydrogen atoms plays a key role. 
     In one embodiment where the rear surface of the p-type IBC solar cell has alternating structure of n-type polysilicon emitter regions and base region, a dielectric with a negative surface charge, like Al 2 O 3  (or a stack comprising Al 2 O 3  layer and a-SiN x :H layer), can be deposited. Then the presence of the dielectric layer causes the desired accumulation at the base region surface, whereas the tendency towards depletion is not detrimental since, first of all, the doping concentration in n-type polysilicon is rather high and, secondly, the tendency towards depletion takes place at a distance of typically 10-20 nm and therefore does not affect the surface recombination at the tunnel oxide since the polysilicon layer is typically one order of magnitude thicker. In the case of n-type polysilicon, the important function of the dielectric layer is to provide hydrogen that will migrate during an elevated temperature step (usually taking place during firing of the contacts of the solar cell) towards the tunnel oxide and thereby strongly reduces the surface recombination. 
     In another embodiment the solar cell&#39;s rear surface has an interdigitating electrode pattern comprising alternating areas of n-type polysilicon and intrinsic polysilicon. This can typically be made by subsequently depositing the tunnel oxide and the intrinsic polysilicon layer. Thereafter a diffusion barrier pattern is applied and a diffusion of phosphorous atoms into the wafer surface takes place, e.g. by POCl 3  diffusion or by ion implant. This is then followed by removal of the diffusion barrier. In this embodiment the surface passivation is at the tunnel oxide over the full area. The hydrogenation of the tunnel oxide where the hydrogen atoms will be located at the dangling bonds of the silicon wafer surface is resulting in a very high degree of surface passivation. Since a polysilicon layer, of about 200 nm, is covering the tunnel oxide and the surface charge of the dielectric only affects carrier concentration levels to 10-20 nm at the outer polysilicon surface, the sign of the surface charge is not relevant anymore. The only role of the dielectric is for both the intrinsic and the n-type polysilicon to provide hydrogen. In this embodiment therefore the choice of the dielectric layer type is free. This means the dielectric layer can for example be Al 2 O 3 , a-SiN x :H or a stack of these dielectric layers. 
     The present invention also relates to a solar panel or photovoltaic module comprising one or more of solar cells as described above. 
     According to an aspect, the invention relates to a method for manufacturing a back-contacted solar cell based on a silicon substrate of p-type conductivity having a front surface for receiving radiation and a rear surface; the method comprising: providing on the rear surface a layer stack of a tunnel oxide layer and a doped polysilicon layer of n-type conductivity, the tunnel oxide layer being arranged between the rear surface and the doped polysilicon layer; patterning the layer stack to have gaps in the layer stack; arranging an Al—Si alloyed contact within each of the gaps, in electrical contact with a base layer of the substrate, and arranging one or more Ag contacts or transition metal contacts on the doped polysilicon layer of the patterned layer stack and in electrical contact with said doped polysilicon layer. 
     According to an embodiment, the method includes that the patterning of the layer stack with gaps in the layer stack comprises the deposition or creation of a cover layer comprising a SiO 2  layer and/or a SiN x  layer and patterning the cover layer by creating openings in the cover layer by means of a local removal of said SiO 2  layer and/or SiN x  layer(s) by a laser beam. 
     According to a further embodiment, the method as described above comprises: removing the patterned cover layer to expose the doped polysilicon layer; depositing on the rear surface, over the gaps and the exposed patterned doped polysilicon layer, a dielectric layer, and creating openings in the dielectric layer at location of the gaps by means of a laser beam. 
     Also, the invention relates to a method for manufacturing a back-contacted solar cell based on a silicon substrate of p-type conductivity having a front surface for receiving radiation and a rear surface; the method comprising: 
     providing on the rear surface a layer stack of a tunnel oxide layer and an intrinsic polysilicon layer, the tunnel oxide layer being arranged between the rear surface and the intrinsic polysilicon layer; covering the layer stack with a cover layer comprising a SiO 2  layer and/or SiN x  layer and creating a pattern of sintered SiO 2  layer and/or SiN x  layer areas in the cover layer; removing the SiO 2  layer and/or SiN x  layer areas that were not sintered; exposing the intrinsic polysilicon layer not covered by the pattern of sintered SiO 2  and/or SiN x  layer(s) areas to an n-type dopant species, so as to create a pattern of n-type doped polysilicon layer areas where not covered by the sintered SiO 2  and/or SiN x  layer(s); removing the patterned sintered SiO 2  and/or SiN x  layer(s) areas so as to expose one or more areas of intrinsic polysilicon; arranging Al—Si alloyed contacts on said one or more areas of intrinsic polysilicon, each in electrical contact with the respective area of intrinsic polysilicon, and creating Ag contacts or transition metal contacts on one or more of the patterned n-type doped polysilicon layer areas and in electrical contact with said patterned n-type doped polysilicon layer areas. 
     According to an embodiment, the method comprises that the pattern of sintered SiO 2  layer and/or SiN x  layer areas is created by using a laser beam as local heat source for sintering. 
     According to an embodiment, the method as described above further comprises: after said removal of the patterned sintered SiO 2  and/or SiN x  layer(s) areas, depositing a dielectric layer over the areas of intrinsic polysilicon and the areas of n-type doped polysilicon, and for one or more areas of intrinsic polysilicon, creating a gap or opening at a location in the dielectric layer overlaying the area of intrinsic polysilicon; in which the gap or opening in the dielectric layer overlaying the area of intrinsic polysilicon is created by using a laser beam. 
     Advantageous embodiments are further defined by the dependent claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the present invention will be described in more detail hereinafter, by way of example only, with reference to the accompanying drawings which are schematic in nature and therefore not necessarily drawn to scale. Furthermore, corresponding reference signs in the drawings relate to corresponding or substantially similar elements. 
       In the drawings,  FIG. 1  schematically shows a cross-section of a solar cell in accordance with an embodiment of the present invention; 
         FIG. 2  schematically shows a cross-section of a solar cell according to an present invention; 
         FIG. 3  schematically shows a cross-section of a solar cell according to an embodiment of the present invention; 
         FIG. 4  schematically shows a plane view of a rear surface of a solar cell according to an embodiment of the present invention; 
         FIG. 5  schematically shows a cross-section of the solar cell of  FIG. 4 ; 
         FIG. 6  schematically shows a plane view of a rear surface of a solar cell in accordance with an embodiment of the present invention; 
         FIG. 7  schematically shows a plane view of a rear surface of a solar cell according to an embodiment of the present invention; 
         FIG. 8  shows a cross-section of a solar panel comprising at least one solar cell according to an embodiment of the invention; 
         FIG. 9  shows a cross-section of a solar cell during various stages of a method according to an embodiment, and 
         FIG. 10  shows a cross-section of a solar cell during various stages of a method according to an embodiment. 
     
    
    
     DESCRIPTION OF EMBODIMENTS 
     The solar cell of the present invention is based on a p-type semiconductor substrate with positive and negative polarity contacts arranged on the rear surface of the substrate. The positive contacts directly connect to the p-type base layer of the substrate, while the negative contacts are connected to n-type doped areas on the rear surface. Typically, the positive contacts are embodied as metal-alloy contacts, the negative contacts are embodied as metal or metallic contacts. 
       FIG. 1  schematically shows a cross-section of a solar cell in accordance with an embodiment of the present invention. 
     According to an embodiment of the invention, a solar cell  1  comprises a silicon substrate  10  of p-type conductivity. For example, the silicon substrate is doped with Boron as dopant species. 
     The silicon substrate  10  has a front surface F and a rear surface R. 
     On the rear surface R, a stack of a tunnel oxide layer  12  and a doped poly-silicon layer  14  is arranged. The layer stack  12 ,  14  is patterned with gaps A to the surface of the silicon substrate. The tunnel oxide layer  12  consists typically of silicon dioxide and typically has a thickness of about 2 nanometer or less. 
     The patterned doped poly-silicon layer  14  has an n-type conductivity, opposite to the p-type conductivity of the silicon substrate. The thickness of the n-type patterned poly-silicon layer is between about 10 and about 300 nm. 
     Within the pattern of the patterned n-type doped poly-silicon layer gaps A are present. In the gaps A, a contact  16  of a first conductivity type is positioned that connects to the silicon substrate  10 , i.e., the base of the solar cell. In this embodiment, the contact of first conductivity type is a metal-alloy contact, typically an Al—Si contact. Optionally this contact comprises Boron. Such an Al—Si contact consists in general of a layered structure comprising an Al head  160 , an Al—Si alloy layer  161  and an Al doped BSF region  162 . Optionally, layers  160 ,  161  and  162  comprise Boron. The BSF region  162  typically is in contact with the silicon matrix of the substrate and envelopes the Al—Si alloy layer  161 . The Al head  160  is positioned on top of the Al—Si alloy layer at the rear surface R and extending therefrom. The lateral size of an Al—Si contact at the substrate level is smaller than the lateral size of a gap A to avoid contact with the bordering region of n-type doped polysilicon. 
     Contacts  18  of the second conductivity type, opposite to the first conductivity type, are arranged on and in electrical contact with the patterned n-type doped poly-silicon layer  14 . According to the invention, the contacts  18  of the second conductivity type are embodied as metal contacts, in an embodiment Ag contacts or alternatively transition metal (e.g., Ni—Cu plated, potentially by Light Induced Plating) contacts. The lateral size of an Ag contact  18  is smaller than the lateral size of the patch of the patterned n-type doped poly-silicon on which the Ag contact is positioned. 
     The patterned n-type doped poly-silicon layer  14  and the openings A are covered by a hydrogenated dielectric layer  20 . Such hydrogenated dielectric layer  20  improves the passivation of the rear surface, i.e., the interface between the tunnel oxide and the surface of the silicon substrate  10 , by providing hydrogen to mask electrically active faults at the rear surface R, (e.g., dangling bonds at the silicon surface). The hydrogenated dielectric layer  20  can comprise a layer of hydrogenated silicon nitride SiN x :H  24 , a layer of alumina (Al 2 O 3 )  22 , or a dielectric layer stack of these layers  22 ,  24 . In such a dielectric layer stack, the alumina layer  22  is positioned in-between the rear surface of the substrate and the SiN x :H layer  24 , since the SiN x :H layer may have a positive surface charge. 
     Both the Al—Si contacts  16  and the Ag contacts  18  extend through the hydrogenated dielectric layer(s) to be in electrical contact with the base of the silicon substrate  10  and the patterned n-type doped poly-silicon layer  14 , respectively. 
     In an embodiment, the hydrogenated dielectric layer is configured to have a negative surface charge. Such negative surface charge influences the distribution of minority and majority charge carriers in the silicon substrate which as explained in the introductory part beneficially provides a reduction of the recombination effect. 
     In an embodiment, the front surface F which is to receive radiation is covered by an Al 2 O 3  layer  30 , bordering the silicon substrate  10  of p-type conductivity, and a SiN x :H layer  32  on top of the Al 2 O 3  layer. 
     In another embodiment, the front surface F which is to receive radiation is covered by an intrinsic poly-silicon layer  30 A and an anti-reflecting coating layer  32 A, for example silicon nitride. Since intrinsic poly-silicon is known to parasitically absorb blue light, a solar cell with such an intrinsic poly-silicon layer  30 A could be used as a bottom solar cell in a tandem device where the bottom cell mainly harvests Near Infra-Red light and the parasitic absorption of i-poly is then relatively low. 
     In case the front surface F is configured with only an anti-reflecting coating, the solar cell  1  will suffer less from parasitic blue light absorption 
       FIG. 2  schematically shows a cross-section of a solar cell  2  according to an embodiment of the present invention. 
     The solar cell  2  according to this embodiment comprises a silicon substrate  10  of p-type conductivity. 
     On the rear surface R, a tunnel oxide layer  12  is arranged. On the tunnel oxide layer  12 , a patterned n-type doped poly-silicon layer  14  is arranged. 
     Within the pattern of the patterned n-type doped poly-silicon layer, regions of intrinsic poly-silicon  26  are present that border on the n-type doped poly-silicon  14 . In this embodiment, the tunnel oxide layer  12  is also present between the intrinsic polysilicon  26  and the rear surface R of the silicon substrate. 
     In the intrinsic poly-silicon region  26 , a metal-alloy contact  16 ;  160 , 161 , 162  of a first conductivity type, typically an Al—Si contact, is positioned that connects to the silicon substrate  10 , i.e., the base of the solar cell. The lateral size of an Al—Si contact is smaller than the lateral size of the intrinsic poly-silicon region  26 . 
     Metal contacts  18  of the second conductivity type such as Ag contacts are arranged on and in electrical contact with the patterned n-type doped poly-silicon layer  14 , as described above with reference to  FIG. 1 . 
     In this embodiment of the solar cell  2 , the patterned n-type doped poly-silicon layer  14  and the intrinsic poly-silicon regions  26  are covered by a layer of hydrogenated silicon nitride SiN x :H  24  which beneficially provides hydrogen for passivation of the rear surface. 
     Both the Al—Si contacts  16 ;  160 , 161 , 162  and the Ag contacts  18  extend through the hydrogenated dielectric layer(s) to be in electrical contact with the base of the silicon substrate  10  and the patterned n-type doped poly-silicon layer  14 , respectively. 
       FIG. 3  schematically shows a cross-section of a solar cell  3  according to an embodiment of the present invention. 
     The solar cell shown in  FIG. 3  may be regarded as a variant of the solar cell  2  as described above with reference to  FIG. 2 . 
     On the rear surface R, a tunnel oxide layer  12  is arranged. On the tunnel oxide layer  12 , a patterned n-type doped poly-silicon layer  14  is arranged. 
     Within the pattern of the patterned n-type doped poly-silicon layer, regions of intrinsic poly-silicon  26  are present that border on the n-type doped poly-silicon  14 . The tunnel oxide layer  12  is also present between the intrinsic polysilicon  26  and the rear surface R of the silicon substrate. 
     The Ag contact  18  is positioned as shown in  FIG. 2  on the patterned n-type doped poly-silicon  14 . 
     In the region of intrinsic poly-silicon  26 , the Al—Si contact  16 ;  160 , 161 , 162  is arranged in electrical contact with the base layer of the silicon substrate  10 . 
     In this embodiment of the solar cell, the intrinsic poly-silicon and the n-type doped poly-silicon are covered with an alumina layer  22  that functions as hydrogenated dielectric layer that provides hydrogen for surface passivation at the tunnel oxide. 
     The Al—Si contact  16 ;  160 , 161 , 162  is located between flanking bounding elements  28  that consist of a material characterized as an inert material with respect to the alumina dielectric, aluminum and Al—Si alloy. The bounding elements  28  are arranged on the stack of alumina  22  and intrinsic polysilicon  26  which shows to be a stable configuration during the heat treatment to form the Al—Si contacts  16 . 
     In an embodiment, the bounding elements material comprises aluminium-oxide particles. Also, the bounding elements material may comprise a material based on aluminum oxide or aluminium nitride. 
     The bounding elements are configured to prevent poor Al—BSF formation at the edges of the Al. This reduces contact recombination. This is in particular important if the Al-paste is a firing-through paste with etchant particles, e.g. a glass frit. 
     Since the material of the bounding elements does not react with the dielectric layer or the silicon substrate at the annealing temperature, the bounding elements act as an inert template during the anneal step. Typically, the anneal step is done between about 660° C. and about 800° C. 
     In addition, as the aperture (i.e., the width between the bounding elements) determines the surface area where Al reacts with Si, the bounding elements do not require a high aspect ratio and may have a rounded cross-section or sloped side walls like a mound or embankment. The bounding elements can be printed in a similar manner as aluminum based paste, e.g. by screen printing. 
       FIG. 4  schematically shows a plane view of a rear surface of a solar cell in accordance with the embodiment of the solar cell  2  shown in  FIG. 2 . On the rear surface R, the Al—Si contacts  16 ; 160 , 161 , 162  and Ag contacts  18  are laid out as interdigitating electrodes. The intrinsic poly-silicon layer  26  and the n-type doped poly-silicon layer  14  are laid-out in corresponding interdigitating patterns. 
     In the intrinsic poly-silicon layer  26  an elongated opening  34  to the silicon substrate has been created by a laser scribe or by printing an etching paste. The Al—Si contact  16 ;  160 , 161 , 162  fills the elongated opening  34  and is in electrical contact with the underlying silicon substrate as shown in  FIG. 2 . 
     On the intrinsic poly-silicon layer  26  the Al head portion  160  of the Al—Si contact extends beyond the boundaries of the laser scribed elongated opening  34  in both transverse and longitudinal directions Y; X. 
     Both the Ag contact interdigitating electrode  18  and the Al—Si contact interdigitating electrode  16  are each connected to respective busbar  118 ;  116  of n-type and p-type polarity, that run in the transverse direction Y perpendicular with the longitudinal direction of the interdigitating electrodes  18 ; 16 . 
     According to the invention, both busbars  116 ,  118  consist of Ag (or Ag alloy). However, the busbars connecting the Al—Si interdigitating electrode can also be made in a similar way as the Al fingers. During manufacturing, the Ag busbars are formed simultaneous with the Ag contacts i.e., the Ag interdigitating electrodes. The Ag busbar for connecting the Al—Si contact (the Al—Si interdigitating electrode) overlaps  216  with a proximal end of the Al—Si interdigitating electrode  16  to obtain an electrical contact. Usually, busbars  116 ,  118  are provided with Ag interconnection pads. 
     It is noted that the layout of the interdigitating electrodes  16 ,  18  and busbars  116 ,  118  are similar for the solar cells described with reference to  FIG. 1  and  FIG. 3 , respectively. 
       FIG. 5  schematically shows a cross-section of a solar cell according to an embodiment of the invention. In this embodiment, the Al—Si contact  16 , in particular the Al head  160 , is flanked by Ag sub-contacts  181 ,  182  that creates an electrical contact between the Al head  160  and the top of the intrinsic poly-silicon layer  26 , which function as interconnecting pad for solder and electrically conductive adhesive (ECA). As shown in  FIG. 4 , Ag busbars are created on both n-type doped poly-silicon  14  and intrinsic poly-silicon  26 . This layout allows to use a two-step print of Ag in one step and Al in the other step to create interdigitating electrodes, interconnecting pads and busbars. In the one-step Ag paste print case the Ag paste is firing-through paste that penetrates into the polysilicon. Since the intrinsic poly is not conductive, this will not lead to shunts. 
       FIG. 6  schematically shows a plane view of a rear surface of a solar cell in accordance with an embodiment of the present invention. The layout of the interdigitating electrodes on the rear surface is similar as described above with reference to  FIG. 4 . In the embodiment of the solar cell shown in  FIG. 6 , the width W of the Al head  160  of the Al—Si contact  16  is larger than the width of the elongated intrinsic poly-silicon  26  surrounding the elongated opening  34  to the silicon substrate. The Al head  160  is configured to overlap a portion of the neighboring n-type doped poly-silicon layer  14 . 
     As it will be appreciated that Al is the limiting factor for the conduction of the metallization (in comparison with Ag). By using a wider Al—Si contact a lower resistance is obtained. Also, by overlapping the n-type doped poly-silicon (the other polarity) the lateral conductance can be improved. Moreover, by varying the Al paste width the alloying process can be tuned. In this way the Al layer size, the alloy layer size and the BSF thickness (i.e., the formation of the layered stack of Al head  160 , Al—Si layer  161  and Al-based BSF region  162  and their respective thickness within the Al—Si contact  16 ) can be tuned for optimal performance. 
       FIG. 7  schematically shows a plane view of a rear surface of a solar cell according to an embodiment of the present invention. In this embodiment, the Al—Si interdigitating electrode  16  is provided with a series of intermittent elongated openings  36  in the intrinsic poly-silicon  26  within the length of the electrode. In comparison to the single elongated opening  34  as shown in  FIG. 4  and  FIG. 6  the series of intermittent openings has a shorter contact length with the underlying silicon substrate  10 . As a result, recombination in the contact can beneficially be reduced. 
     As shown here, the layout of intermittent openings  36  can be combined with an Al head layer  160  partially overlapping the neighboring n-type doped poly-silicon  14  to tune performance. 
       FIG. 8  shows a cross-section of a solar panel comprising at least one solar cell according to an embodiment of the invention. 
     The invention also relates to a solar panel  800  or photovoltaic module that comprises one or more back-contacted solar cells  1 ; 2 ; 3  as described above with reference to the  FIGS. 1-7 . 
     The solar panel  800  further comprises a transparent top-plate  802 , a top encapsulant  804 , a bottom encapsulant  806  and a back sheet  808 . 
     The one or more solar cells  1 ; 2 ; 3  are arranged on the backsheet  808 , that is provided with a conductor pattern (not shown) to which the busbars  116 ,  118  that connect to the Al—Si interdigitating electrodes  16  and the Ag interdigitating electrodes, respectively are electrically contacted by solder or conductive adhesive  810 . The bottom encapsulant layer  806  is arranged in-between the rear surface R of the one or more solar cells and the back-sheet with contact openings at the locations where the busbars  116 ;  118  connect to the back-sheet  808 . 
     On top of the solar cells, above the front surfaces F thereof, the top encapsulant  804  is arranged, in-between the solar cells and the top transparent plate  802 . 
     It is noted that the front surface and/or the rear surface R may have a texture of pyramidal shapes. 
     Also it is noted that the silicon nitride layer  24  at the rear surface R has a thickness that may be tuned for reflection of radiation that has reached the rear surface R. In particular the tuning of the thickness can be done with respect to a minimal wavelength of the radiation. In an embodiment, the minimal wavelength may be about 900 nm. The thickness may be at least about 80 nm, or about 150 nm or preferably about 200 nm. 
     The solar cell according to the invention can be created by various methods of manufacturing. Below these methods are described. 
     Nomenclature 
     
         
         
           
             FT=firing-through 
             NFT=non firing-through 
             LCO=Local Contact Opening 
             PGR=POCl3 Glass Removal 
             SSE=Single Side Etch 
           
         
       
    
     The p-type interdigitate back contact (IBC) solar cell is manufactured on boron doped p-type silicon wafer. It has the emitter at rear surface R that does not face to the sunlight and may have or may not have a Front Surface Field (FSF) on the front surface of the silicon substrate. Preferably, the FSF is absent since this saves costly processing steps (e.g. BBr3 diffusion) and moreover, in general, an FSF-free top surface has a lower surface recombination current density. In addition, the high-temperature Boron diffusion step can have detrimental effect on the quality of the base material. Since p-type wafers from an ingot with a resistivity range of 1-3 Ω·cm are standard, an FSF is not really needed to have sufficient conduction in the base. The front Si surface is passivated by a dielectric layer or a stack layer. At the rear surface R, alternating emitter/base-regions are formed by different patterning techniques. A p-type IBC cell with three different types of rear architectures will be described below. These are:
         I. A rear surface where diffused emitter regions alternate with base regions, where the entire surface is covered with a dielectric layer or a stack of layers with a negative surface charge.   II. A rear surface where n-type polysilicon emitter regions alternate with base regions, where the entire surface is covered with a, hydrogen-providing, dielectric layer or stack of layers with a negative surface charge.   III. A rear surface where n-type polysilicon emitter regions alternate with intrinsic polysilicon regions, where the entire surface is covered with a, hydrogen-providing, dielectric layer or stack of layers with an arbitrary surface charge.       

     The solar cell manufacturing process consists of the following steps:
         1. Preparing the p-type wafer;   2. Creating a patterned emitter;   3. Applying the front-surface passivation;   4. Applying the rear-surface passivation;   5. Opening of the dielectric;   6. Applying metallization.       

     These process steps are elaborated below. 
     1. Preparing the p-Type Wafer (Table 1) 
     
       
         
           
               
             
               
                 TABLE 1 
               
               
                   
               
               
                 Process steps for preparing monocrystalline and multi-crystalline wafers 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                 Mono-crystalline wafer (e.g. 
                 Multi-crystalline wafer 
               
               
                 Czochralski (Cz)) 
                   
               
               
                 Optional pre-clean in (acidic) wet 
                 Optional pre-clean in (acidic) wet 
               
               
                 chemical solution 
                 chemical solution 
               
               
                 Optional saw-damage removal 
                 Optional saw-damage removal 
               
               
                 Random pyramid etch, e.g. by wet 
                 Texturing step suitable for mc-Si 
               
               
                 chemical alkaline (KOH) etch at 
                 wafers, like acidic texturing, ISO 
               
               
                 elevated temperature. 
                 texture, Reactive Ion Etching, dry 
               
               
                   
                 etching, Metal-assisted wet chemical 
               
               
                   
                 etching, alkaline etch and 
               
               
                   
                 combinations. 
               
               
                 Optional acidic wet chemical etch 
                 Optional alkaline or acidic etch to 
               
               
                 step to round the pyramid tips and 
                 remove damage of the previous step 
               
               
                 valleys 
                   
               
               
                 Optional single sided etch (SSE) 
                 Optional SSE step to polish the rear 
               
               
                 step to polish the rear surface 
                 surface 
               
               
                 Optional step to remove micro- 
                 Optional step to remove micro- 
               
               
                 roughness at the surface, e.g. by 
                 roughness at the surface, e.g. by 
               
               
                 subsequent oxidation (by e.g. 
                 subsequent oxidation (by e.g. HNO3) 
               
               
                 HNO3) followed by a (buffered) HF 
                 followed by a (buffered) HF wet 
               
               
                 wet chemical step. 
                 chemical step. 
               
               
                   
               
            
           
         
       
     
     2. Creating a Patterned Emitter (Table 2). 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Rear-surface area type-I (alternating bare base region, with  
               
               
                 classically diffused emitter region) 
               
            
           
           
               
               
               
               
               
            
               
                 Textured  
                 Textured  
                 Textured  
                 Textured  
                 Textured  
               
               
                 wafer 
                 wafer 
                 wafer 
                 wafer 
                 wafer 
               
               
                   
               
               
                 Optional  
                 Optional  
                 Optional  
                 Optional  
                 Optional  
               
               
                 HF-dip 
                 HF-dip 
                 HF-dip 
                 HF-dip 
                 HF-dip 
               
               
                   
                   
                 Print  
                 Print  
                 Print  
               
               
                   
                   
                 diffusion 
                 diffusion 
                 dopant 
               
               
                   
                   
                 barrier rear 
                 barrier 
                 paste 
               
               
                 POCI3  
                 POCI3  
                 POCI3  
                 Ion implant  
                 Thermal  
               
               
                 diffusion 
                 diffusion 
                 diffusion 
                 rear surface 
                 step 
               
               
                 PGR 
                 PGR 
                 PGR 
                 Anneal 
                   
               
               
                 SSE front 
                   
                 SSE front 
                 Remove  
                   
               
               
                   
                   
                   
                 barrier 
                   
               
               
                 Print etch  
                 Print etch 
                   
                   
                 PGR  
               
               
                 paste 
                 barrier on 
                   
                   
                 and (wet 
               
               
                 Cure 
                 emitter region 
                   
                   
                 chemical  
               
               
                 Remove  
                 (Acidic) etch 
                   
                   
                 clean) 
               
               
                 etch 
                 Etch-barrier 
                   
                   
                   
               
               
                 paste 
                 removal 
                   
                   
                   
               
               
                   
                 (e.g. diluted 
                   
                   
                   
               
               
                   
                 KOH and 
                   
                   
                   
               
               
                   
                 ultrasonic bath) 
               
               
                   
               
            
           
         
       
     
     For rear surface type II and III, a polysilicon layer of typically 10-300 nm is applied. Prior to the polysilicon deposition a very thin (e.g. 0.5-2 nm) silicon dioxide layer is created on the silicon surface. This can be realized by in-situ deposition in a Low Pressure Chemical Vapor Deposition (LPCVD) system or in a Plasma Enhanced Vapor Deposition (PECVD) system, or by ex-situ chemical oxidation (such as NAOS, RCA, H 2 O 2 , etc.). 
     On top of the oxide layer an intrinsic polysilicon layer or an n-type, in situ doped, polysilicon with a thickness of typically 10-300 nm is deposited by LPCVD or by PECVD. In fact, the PECVD deposition mostly leads to deposition of amorphous silicon (a-Si), which can be converted into polysilicon by an elevated temperature step (anneal). 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 Rear-side type II (alternating bare base region, with n-type polysilicon emitter) 
               
            
           
           
               
               
               
               
            
               
                 Textured wafer 
                 Textured wafer 
                 Textured wafer 
                 Textured wafer 
               
               
                 with tunnel- 
                 with tunnel- 
                 with tunnel-oxide 
                 with tunnel-oxide 
               
               
                 oxide 
                 oxide 
                 &amp; in-situ doped 
                 &amp; in-situ doped 
               
               
                 &amp; intrinsic- 
                 &amp; intrinsic- 
                 n-type 
                 n-type 
               
               
                 polysilicon 
                 polysilicon 
                 polysilicon 
                 polysilicon 
               
               
                   
               
               
                 Optional HF-dip 
                 Optional HF-dip 
                 Optional HF-dip 
                 Optional HF-dip 
               
               
                 POCI3 diffusion 
                 POCI3 diffusion 
                 SSE front 
                   
               
               
                 PGR 
                 PGR 
                 (optional) 
                   
               
               
                 SSE front 
                   
                   
                   
               
               
                 (optional) 
                   
                   
                   
               
               
                 Print etching paste 
                 Print etch barrier 
                 Print etch paste 
                 Print etch barrier 
               
               
                 Cure 
                 on emitter region 
                 Cure 
                 on emitter region 
               
               
                 Remove etching 
                 Wet chemical 
                 Remove etch 
                 Wet chemical 
               
               
                 paste 
                 (acidic) etch 
                 paste 
                 (acidic) etch 
               
               
                   
                 Etch-barrier 
                   
                 Etch-barrier 
               
               
                   
                 removal 
                   
                 removal 
               
               
                 SSE front 
                   
                 SSE front 
                   
               
               
                 (optional) 
                   
                 (optional) 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 4 
               
             
            
               
                   
               
               
                 Rear-side type III (alternating intrinsic-polysilicon with n-type polysilicon regions) 
               
            
           
           
               
               
               
               
            
               
                 Textured wafer 
                 Textured wafer 
                 Textured wafer 
                 Textured wafer 
               
               
                 with tunnel- 
                 with tunnel- 
                 with tunnel- 
                 with tunnel- 
               
               
                 oxide &amp; intrinsic-  
                 oxide &amp; intrinsic- 
                 oxide &amp; intrinsic- 
                 oxide &amp; intrinsic- 
               
               
                 poly 
                 poly 
                 poly 
                 poly 
               
               
                   
               
               
                 HF-dip 
                 HF-dip 
                 HF-dip 
                 HF-dip 
               
               
                   
                 Print diffusion 
                 Print diffusion 
                 Print dopant paste 
               
               
                   
                 barrier rear 
                 barrier 
                   
               
               
                 POCI3 diffusion 
                 POCI3 diffusion 
                 Ion implant rear 
                 Thermal step 
               
               
                 PGR 
                 PGR 
                 Anneal 
                   
               
               
                   
                 SSE front 
                 Remove barrier 
                   
               
               
                 Print etch barrier 
                   
                   
                   
               
               
                 on targeted 
                   
                   
                   
               
               
                 emitter region 
                   
                   
                   
               
               
                 Acidic etch 
                   
                   
                   
               
               
                 Etch-barrier 
                   
                   
                   
               
               
                 removal 
               
               
                   
               
            
           
         
       
     
     For a special embodiment of type II and III solar cells, the intrinsic polysilicon layer on the front side can deliberately be kept. An intrinsic poly silicon layer on the front side can be obtained if the ion implant takes place on the rear surface R or if a temporary diffusion barrier (e.g. SiO 2  or SiN x ) is applied on the front surface F and after POCl 3  processing is removed. This embodiment can have a very low front-surface recombination due to the good passivating properties of the oxide-intrinsic poly stack. However the intrinsic polysilicon layer will parasitically absorb blue light. Because of this, this solar cell type is targeted as bottom solar cell in a tandem device. 
     3. Applying the Front-Surface Passivation 
     For all types I, II, III a (wet) chemical clean step can be applied prior to front coating deposition, which could be RCA-1, RCA-2, HNO 3 , (buffered) HF, HCl and different combinations and different sequences. 
     Front coatings can be Al 2 O 3 , or a stack of Al 2 O 3 —SiN x  or SiN x . The preferred coating is the stack of Al 2 O 3 —SiN x  since this is proven as passivating layer on the rear surface of PERC solar cells and the layers of the stack can be optimized for anti-reflection purposes as well. Typically a stack of 6 nm Al 2 O 3  and 80 nm SiN x  could work for this purpose. 
     4. Applying the Rear Surface Passivation 
     
       
         
           
               
               
               
             
               
                 TABLE 5 
               
               
                   
               
               
                 Type-I 
                 Type-II 
                 Type-III 
               
               
                   
               
             
            
               
                 Deposition of a hydrogen- 
                 Deposition of a hydrogen- 
                 Deposition of a hydrogen- 
               
               
                 providing dielectric layer or a 
                 providing dielectric layer or a 
                 providing dielectric layer 
               
               
                 stack of dielectric layers with  
                 stack of dielectric layers with 
                 or a stack of dielectric 
               
               
                 a negative surface charge, 
                 a negative surface charge, 
                 layers with an arbitrary 
               
               
                 like 
                 like 
                 surface charge, like 
               
               
                 Al 2 O 3  or Al 2 O 3 —SiN x   
                 Al 2 O 3  or Al 2 O 3 —SiN x   
                 Al 2 O 3  or Al 2 O 3 —SiN x  or SiN x   
               
               
                   
               
            
           
         
       
     
     It should be noted that the front dielectric layers could be co-deposited with the rear dielectric layers. For instance, for all types (I, II and III) first double-sided Al 2 O 3  followed by double-sided SiN x  could be applied. Deposition systems in which half-fabricates are levitated and float through the deposition chamber might be a useful for this purpose. It should be noted that, unlike single-side deposition where wrap-around of the deposition can be undesired, the double-sided deposition has more forgiving process conditions. 
     The rear surface will be opened at the base regions by laser ablation or by printing a chemical etch paste. This is followed by a (wet) chemical clean to remove laser damage and dielectric coating flakes. 
     Optionally the dielectric is opened in a similar way at the emitter regions, which can later on be used for the contacting of NFT Ag-paste. 
     5. Opening of the Dielectric 
     Openings in the dielectric layer at the base regions are realized. Per targeted aluminium print area this can be a line shape or a series of smaller lines or dots. Opening can be realized by laser ablation or by selective chemical etching, e.g. by printing an etch paste. These steps can be followed with a chemical clean step. Optionally, local contact openings (LCOs) on the emitter regions can be realized in the same process step. The LCOs can then be used to make a metallic contact to the emitter by (screen)printing of NFT Ag-paste or by (Light Induced) plating. It should be noted that for these types of metallization the metal does not penetrate into the n-type polysilicon emitter or into the classically diffused emitter. 
     6. Applying Metallization 
     The process for the metallization is listed in Table 6. Three metal types are envisaged for (screen) printing: Al-paste, FT Ag-paste and NFT Ag-paste. The latter will not fire through the dielectric layer. For the NFT pastes, two categories can be identified: The first is co-fired with the Al-paste and the FT Ag-paste and the second is separately printed and fired, mostly at lower firing temperatures. The second paste type is often referred to as “floating busbar” paste. 
     The NFT paste is used to make contact to the Al-paste. Both the NFT Ag paste and the FT paste can be electrically connected to the metal leads that series connect solar cells in the photovoltaic module by solder or by electrically conductive adhesive. 
     In all cases the Al paste is printed on the rear dielectric layer such that the LCO in the dielectric layer of the base region is fully covered. The Al paste area might also partially overlap with the emitter region. 
     The BSF is formed by an Aluminum-Silicon alloy process in which the Aluminum of the screen-printed Al-paste dissolves the silicon of the base wafer material and, optionally, the intrinsic polysilicon during heating up above 660° C. (i.e. the melting point of aluminum) and where during the cooling down phase Al-doped silicon is rejected from the melt and recrystallizes, also known as epitaxial growth. 
     Table 6 shows metallization options for the types I, II and III. 
     
       
         
           
               
             
               
                 TABLE 6 
               
             
            
               
                   
               
               
                 Metallization options 
               
            
           
           
               
               
               
               
               
            
               
                 Type I, II, III 
                 Type I, II, III 
                 Type III 
                 Type I, II, III 
                 Type I, II, III 
               
               
                   
               
               
                 LCO at base 
                 LCO at base 
                 LCO at base 
                 LCO at base 
                 LCO at base 
               
               
                 region only 
                 region only 
                 region only 
                 region and 
                 region and 
               
               
                   
                   
                   
                 emitter region 
                 emitter 
               
               
                   
                   
                   
                   
                 region 
               
               
                 (screen) print 
                 (screen) print 
                 (screen) print 
                   
                 Apply Ni 
               
               
                 FT Ag-paste 
                 FT Ag-paste 
                 FT Ag-paste 
                   
                 and/or Cu 
               
               
                 on emitter 
                 on emitter 
                 on emitter 
                   
                 plating on 
               
               
                 regions 
                 regions 
                 regions 
                   
                 the emitter 
               
               
                 (fingers &amp; 
                 (fingers only) 
                 (fingers &amp; 
                   
                 regions. 
               
               
                 busbars) 
                   
                 busbars) and 
                   
                 Light- 
               
               
                   
                   
                 on base 
                   
                 induced 
               
               
                   
                   
                 regions 
                   
                 plating is an 
               
               
                   
                   
                 (busbars only) 
                   
                 option. 
               
               
                 (screen) print 
                 (screen) print 
                   
                 (screen) print 
                 (screen) 
               
               
                 NFT Ag-paste 
                 NFT Ag-paste 
                   
                 NFT Ag-paste 
                 print NFT 
               
               
                 on base 
                 on base region 
                   
                 on base region 
                 Ag-paste on 
               
               
                 regions 
                 to contact Al 
                   
                 to contact Al 
                 base region 
               
               
                   
                 and as emitter 
                   
                 and in the 
                 to contact Al 
               
               
                   
                 busbars to 
                   
                 LCOs of the 
                   
               
               
                   
                 contact the FT- 
                   
                 emitter 
                   
               
               
                   
                 Ag paste. 
                   
                 regions. 
                   
               
               
                 (screen) print 
                 (screen) print 
                 (screen) print 
                 (screen) print 
                 (screen) 
               
               
                 Al-paste at 
                 Al-paste at 
                 Al-paste at 
                 Al-paste at 
                 print Al- 
               
               
                 base regions 
                 base regions 
                 base regions 
                 base regions 
                 paste at 
               
               
                 on top of 
                 on top of 
                 on top of 
                 on top of 
                 base 
               
               
                 LCOs, partially  
                 LCOs, partially 
                 LCOs, partially 
                 LCOs, partially 
                 regions on 
               
               
                 on top of NFT 
                 on top of NFT 
                 on top of the 
                 on top of NFT 
                 top of LCOs, 
               
               
                 Ag paste. 
                 Ag paste. 
                 FT Ag-paste. 
                 Ag paste. 
                 partially on 
               
               
                   
                   
                   
                   
                 top of NFT 
               
               
                   
                   
                   
                   
                 Ag paste. 
               
               
                   
               
            
           
         
       
     
     After the (screen) print steps, the solar cell  1 ,  2 ,  3 ; I, II, III can undergo a thermal step where the FT Ag-paste penetrates the dielectric layer and contacts the classically diffused emitter, the n-type poly silicon emitter or the intrinsic poly-silicon. 
     The FT Ag-paste can be selected amongst the pastes used for PERC front-side emitter contacting. Examples of the NFT Ag-paste that are used for PERC solar cells rear surfaces are SOL326, SOL 326S by Heraeus, PV56x by Dupont, BS828B by ENC and GB21 by Gonda. 
     The BSF is formed by an Aluminum-Silicon alloy process in which aluminum of the screen-printed Al-paste dissolves silicon of the base wafer material and, in case of surface-area type III, the intrinsic polysilicon, during heating up above 660° C. and where during the cooling down phase Al-doped silicon is rejected from the melt and recrystallizes, which also denoted by epitaxial growth. 
     All metal conductive pastes can be sintered by co-firing at a temperature of (typically 700-840° C.). Due to application of three different pastes, three print steps are required to complete the metallization of this type of p-IBC solar cell. For type III the option exists to apply two print step, namely FT Ag-paste and Al-paste. In that case the FT Ag-paste also penetrates the intrinsic polysilicon but since this layer does not conduct it will not lead to shunt. 
       FIG. 9  shows a cross-section of a solar cell during various stages of a method according to an embodiment. Here the method is described in relation to the consecutive stages. 
     In stage  901 , a silicon substrate (silicon wafer)  10  is provided as a basis for the solar cell. Typically, the silicon substrate is etched during this stage. The etching step may comprise a polishing etch. Alternatively or additionally the etching step may comprise a first texturing etch followed by a second smoothening etch. 
     In stage  902 , a stack of a thin oxide layer  12  and an n-type polysilicon layer  14  is created on both front and rear surfaces of the silicon substrate. The thin oxide layer is intended as tunnel oxide layer and is arranged in between each of the surfaces of the silicon substrate  10  and the n-type polysilicon layer  14 . 
     In a next stage  903 , a SiO 2  layer or SiN x  layer or a combination thereof, indicated by reference  40 , is created as cover layer on the rear side of the silicon substrate (i.e., the side of the substrate where the back contacts are to be formed) on top of the n-type polysilicon layer. Preferably, the SiO 2  layer or SiN x  layer  40  is created by plasma enhanced chemical vapor deposition PECVD, on the rear side of the substrate  10 . 
     Then in a subsequent stage  904 , a laser beam  50  is used for creating a gap  42  or opening  42  in the cover layer  40  on the rear surface. The laser beam  50  is configured to selectively remove the SiO 2  layer and/or SiN x  layer  40  at predetermined locations on the rear surface. Thus a patterned SiO 2  layer and/or SiN x  layer  40 - 1  is obtained in which the gaps or openings  42  expose the underlying n-type polysilicon layer. 
     Next, in stage  905 , the substrate is exposed to an all-sided alkaline etch. The alkaline etch selectively removes the exposed polysilicon layer  14  and thin oxide  12  at the rear surface while using the patterned SiO 2  layer or SiN x  layer  40 - 1  as a mask layer. Thus in the gaps or openings  42  in the patterned SiO 2  layer or SiN x  layer  40 - 1  the surface of the substrate  10  is now exposed. At the same time, the n-type polysilicon layer  14  and thin oxide layer  12  are removed from the front surface by the alkaline etch. The alkaline etch may comprise a surfactant and depending on its composition and temperature the etch can be isotropic or anisotropic resulting in a (random pyramid) texture. 
     In stage  906 , the alkaline etch is followed by a HF (fluoric acid) etch which now selectively removes the patterned SiO 2  layer or SiN x  layer  40 - 1  from the rear surface. A patterned layer stack of thin oxide  12 - 1  and n-type polysilicon  14 - 1  remains at the rear surface. 
     Subsequently, in stage  907 , the substrate comprising the patterned layer stack  12 - 1 ,  14 - 1  on the rear surface is exposed to an all-sided deposition of a dielectric layer of either an Al 2 O 3  layer  44 , or a SiN x  layer  44  or a stack  44  of Al 2 O 3  and SiN x  layers. 
     Finally in stage  908 , a laser beam  52  is used to remove the Al 2 O 3  and/or SiN x  layers  44  at a location(s)  46  inside the gaps or openings  42  created earlier in stage  904 . Thus, at the location(s) an area portion of the silicon substrate is exposed. 
     At the exposed area portion at the location(s)  46 , an Al—Si contact can be formed at a later stage, as described above with reference to  FIG. 1  for example. 
     The method relates to providing on the rear surface a layer stack of a tunnel oxide layer and a doped polysilicon layer of n-type conductivity, the tunnel oxide layer being arranged between the rear surface and the doped polysilicon layer; patterning the layer stack to have gaps in the layer stack; arranging an Al—Si alloyed contact within each of the gaps, in electrical contact with a base layer of the substrate, and arranging one or more Ag contacts or transition metal contacts on the doped polysilicon layer of the patterned layer stack and in electrical contact with said doped polysilicon layer. 
     According to an aspect of the method, the patterning of the layer stack with gaps in the layer stack comprises the deposition or creation of a cover layer comprising a SiO 2  layer and/or a SiN x  layer and patterning the cover layer by creating openings in the cover layer by means of a local removal of said SiO 2  layer and/or SiN x  layer(s) by a laser beam. 
     The SiO 2  and/or SiN x  layer(s) are sacrificial layers in this exemplary embodiment. The skilled in the art will appreciate the method may be modified in a manner that the patterned SiO 2  and/or SiN x  layer(s), forming a barrier against alkaline etch, are permanent layers. 
     In addition, it will be appreciated that the stages as described may be combined with other intermediate processing steps not described here. Such intermediate processing steps may be required for preparation, transportation, intermediate cleaning, native oxide removal, etc. 
       FIG. 10  shows a cross-section of a solar cell during various stages  1001 - 1008  of a method according to an embodiment. In this embodiment, a stack of a thin oxide layer  12  and an intrinsic polysilicon layer  54  is applied instead of the stack of a thin oxide layer and an n-type doped polysilicon layer. The term “intrinsic polysilicon” is to be construed here as undoped polysilicon or intentionally undoped polysilicon, i.e., having a base dopant level at least an order of magnitude lower than the n-type dopant level. 
     Here the embodiment of the method is described in relation to the consecutive stages. 
     In stage  1001 , a silicon substrate (silicon wafer)  10  is provided as a basis for the solar cell. Typically, the silicon substrate is etched during this stage. The etching step may comprise a polishing etch. Alternatively or additionally the etching step may comprise a first texturing etch followed by a second smoothening etch. 
     In stage  1002 , a stack of a thin oxide layer  12  and an intrinsic polysilicon layer  54  is created on both front and rear surfaces of the silicon substrate. The thin oxide layer is intended as tunnel oxide layer and is arranged in between each of the surfaces of the silicon substrate and the intrinsic polysilicon layer. 
     In a next stage  1003 , a SiO 2  layer or SiN x  layer or a combination thereof indicated by reference  40  is created as cover layer on top of the intrinsic polysilicon layer  54  on the rear side of the silicon substrate  10  (i.e., the side of the substrate where the back contacts are to be formed). Preferably, the SiO 2  layer or SiN x  layer or combination layer  40  is created by plasma enhanced chemical vapor deposition PECVD, on the rear side of the substrate. 
     Then in a subsequent stage  1004 , a laser beam  56  is used for creating a sintered area  41  in the SiO 2  layer or SiN x  layer or combination layer  40  on the rear surface. The laser beam is configured to selectively heat the SiO 2  layer or SiN x  layer or combination layer  40  at predetermined locations  58  on the rear surface, which has the effect that the SiO 2  layer or SiN x  layer or combination layer  40  is structurally modified in comparison with the portion  40 - 2  of the SiO 2  layer or SiN x  layer or combination layer  40  that is not irradiated by the laser beam  56 . The structural modification at the predetermined location(s)  58  may involve a densification of the irradiated SiO 2  layer or SiN x  layer and/or structural phase transition of the layer. 
     Next, in stage  1005 , the substrate is exposed to an all-sided HF etch. The HF etch selectively removes the non-sintered portion  40 - 2  of the SiO 2  layer and/or SiN x  layer  40  from the front and rear surfaces. 
     The sintered polysilicon layer at the rear surface remains and is used as a patterned mask layer. In this manner, the intrinsic polysilicon is exposed on the rear surface in a pattern corresponding with the locations where the non-sintered SiO 2  layer or SiN x  layer was removed. 
     After the HF etch process, the substrate is subjected to a n-type doping process which provides diffusion of an n-type dopant into the exposed intrinsic polysilicon to create n-type doped poly silicon  14  at the exposed locations. In an embodiment, the n-type dopant is phosphorous. The doping process can be the well-known POCl 3  process which uses phosphoryl chloride as precursor. 
     Under the sintered SiO 2  layer or SiN x  layer area(s)  41  the polysilicon layer remains an intrinsic polysilicon layer  54 - 1  after stage  1005 . 
     In a next stage  1006 , an HF etch is applied to remove the sintered oxide layer and—if present—the Phosphor glass resulting from the POCl 3  process and subsequently a single sided etch on the front surface of the substrate  10  is carried out. In this process, as shown in stage  1006 , the n-type polysilicon  14  and thin oxide  12  layers remain at the rear surface but are removed from the front surface. 
     On the rear surface a patterned polysilicon layer remains that comprises areas of intrinsic polysilicon  54 - 1  and areas of n-type doped polysilicon  14 . Between the patterned polysilicon layer  14 ,  54 - 1  and the substrate  10  the thin-oxide layer  12  is arranged. 
     Subsequently, in stage  1007 , the substrate  10  comprising the patterned polysilicon layer  14 ,  54 - 1  stacked on the thin oxide layer  12  on the rear surface is exposed to an all-sided deposition of a hydrogen providing dielectric coating which can be either an Al 2 O 3  layer, or a SiN x  layer or a stack of Al 2 O 3  and SiN x  layers, indicated by reference  44 . 
     Finally in stage  1008 , a laser beam  60  is used to remove/open the Al 2 O 3  and/or SiN x  layers  44  at a location(s)  62  above the intrinsic polysilicon layer  54 - 1  created earlier in stage  1005 . Thus, at the location(s)  62  an area portion of the intrinsic polysilicon  54 - 1  is exposed. At the exposed area portion, an Al—Si contact (not shown) can be formed at a later stage by depositing aluminium on the intrinsic polysilicon and a subsequent annealing. 
     In this embodiment, the method relates to providing on the rear surface a layer stack of a tunnel oxide layer and an intrinsic polysilicon layer, the tunnel oxide layer being arranged between the rear surface and the intrinsic polysilicon layer; covering the layer stack with a cover layer comprising a SiO 2  layer and/or SiN x  layer and creating a pattern of sintered SiO 2  layer and/or SiN x  layer areas within the cover layer; removing the SiO 2  layer and/or SiN x  layer areas that were not sintered; exposing the intrinsic polysilicon layer not covered by the pattern of sintered SiO 2  and/or SiN x  layer(s) areas to an n-type dopant species, so as to create a pattern of n-type doped polysilicon layer areas where not covered by the sintered SiO 2  and/or SiN x  layer(s); removing the patterned sintered SiO 2  and/or SiN x  layer(s) areas so as to expose one or more areas of underlying intrinsic polysilicon; arranging Al—Si alloyed contacts on said one or more areas of intrinsic polysilicon, each in electrical contact with the respective area of intrinsic polysilicon, and creating Ag contacts or transition metal contacts on one or more of the patterned n-type doped polysilicon layer areas and in electrical contact with said patterned n-type doped polysilicon layer areas. 
     According to an embodiment, the method further comprises that the pattern of sintered SiO 2  layer and/or SiN x  layer areas is created by using a laser beam as local heat source for sintering. 
     According to an embodiment, the method further comprises, after said removal of the patterned sintered SiO 2  and/or SiN x  layer(s) areas, a step of depositing a dielectric layer over the areas of intrinsic polysilicon and the areas of n-type doped polysilicon, and for one or more areas of intrinsic polysilicon, creating a gap or opening at a location in the dielectric layer overlaying the area of intrinsic polysilicon, in which the gap or opening in the dielectric layer overlaying the area of intrinsic polysilicon is created by using a laser beam. 
     In the foregoing description, the invention has been described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the scope of the invention as summarized in the attached claims. 
     In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the essential scope thereof. The skilled in the art will appreciate that the exemplary embodiments as described above may be modified and combined in accordance with the scope and spirit of the invention. 
     Therefore, it is intended that the invention not be limited to the particular embodiments disclosed, but that the invention will include all embodiments falling within the scope of the appended claims.