Patent Publication Number: US-11049796-B2

Title: Manufacturing method of packaging device

Description:
RELATED APPLICATIONS 
     This application is a Divisional Application of the U.S. application Ser. No. 14/549,996, filed Nov. 21, 2014, of which is herein incorporated by reference. 
    
    
     BACKGROUND 
     Field of Invention 
     The present invention relates to a packaging device. 
     Description of Related Art 
     Integrated circuit (IC) assemblies for such complex electronic systems typically have a large number of interconnected IC chips, or dies. Integrated circuit chips are being fabricated with gradually smaller sizes and higher circuit densities. When the IC chips becomes denser in term of electrical power consumption per unit volume, heat generated is also increases correspondingly. As the state of the art progresses, the ability to adequately dissipate heat is often a constraint on the rising complexity of package design, higher device operating speed and power consumption. 
     SUMMARY 
     An aspect of the present invention is to provide a packaging device including a first semiconductor device, a thermal dissipating component, an encapsulation layer, a via, and a pad. The first semiconductor device includes a substrate, an active region, and an electrode. The active region is disposed between the substrate and the electrode. The substrate has a first surface opposite to the active region, and the electrode has a second surface opposite to the active region. The thermal dissipating component is disposed on the first surface of the substrate. The encapsulation layer encloses the second surface of the electrode and a part of the thermal dissipating component, such that another part of the thermal dissipating component is exposed by the encapsulation layer. The pad is disposed on the encapsulation layer. The via is disposed in the encapsulation layer and connects the pad to the electrode. 
     In one or more embodiments, a thickness of the thermal dissipating component is greater than a thickness of the pad. 
     In one or more embodiments, a quantity of heat dissipation through the first surface of the substrate is greater than a quantity of heat dissipation through the second surface of the electrode. 
     In one or more embodiments, the active region and the electrode form a GaN transistor. 
     In one or more embodiments, the packaging device further includes a solder disposed between the first semiconductor device and the thermal dissipating component. 
     In one or more embodiments, the solder is made from metal. 
     In one or more embodiments, the electrode of the first semiconductor device is spatially separated from the thermal dissipating component. 
     In one or more embodiments, the thermal dissipating component includes a first portion and a second portion separated from each other. The first portion is disposed on the first semiconductor device. The packaging device further includes a second semiconductor device, and the second portion is disposed thereon. 
     In one or more embodiments, the first portion of the thermal dissipating component has a cavity for accommodating the first semiconductor device. 
     In one or more embodiments, a thickness of the first semiconductor device is different from a thickness of the second semiconductor device. 
     In one or more embodiments, the second surface of the first semiconductor device and a surface of the second semiconductor device opposite to the thermal dissipating component are coplanar. 
     In one or more embodiments, the packaging device further includes a third semiconductor device electrically connected to the first portion and the second portion of the thermal dissipating component. 
     Another aspect of the present invention is to provide a method for manufacturing a packaging device including providing a thermal dissipating component. A first surface of the first semiconductor device is fixed on or above the thermal dissipating component. The thermal dissipating component and the first semiconductor device are covered by an encapsulation layer. The encapsulation layer encloses a part of the thermal dissipating component and another part of the thermal dissipating component is exposed by the encapsulation layer. A through hole is formed in the encapsulation layer to expose a portion of a second surface of the first semiconductor device. The second surface is opposite to the first surface. A via is formed in the through hole and a pad is formed on the via 
     In one or more embodiments, the through hole is performed using photolithography process, laser drilling process, or mechanical machining process. 
     In one or more embodiments, the via and the pad are performed using copper electroplating process. 
     In one or more embodiments, the method further includes forming a solder between the first semiconductor device and the encapsulation layer. 
     In one or more embodiments, the solder is made from metal. 
     In one or more embodiments, the thermal dissipating component includes a first portion and a second portion separated from each other. The first semiconductor device is formed on the first portion, and the method further includes forming a second semiconductor device on the second portion, and the encapsulation layer encloses the second semiconductor device and the second portion of the thermal dissipating component. 
     In one or more embodiments, fixing the first semiconductor device on or above the thermal dissipation component includes fixing the first semiconductor device in a cavity in the thermal dissipating component. 
     In one or more embodiments, the method further includes forming a third semiconductor device to be electrically connected to the first portion and the second portion of the thermal dissipating component. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram of a packaging device according to one embodiment of the present invention; 
         FIG. 2  is a cross-sectional view taken along line A-A of  FIG. 1  according to one embodiment; 
         FIG. 3  is a cross-sectional view taken along line A-A of  FIG. 1  according to another embodiment; 
         FIGS. 4A-4D  are schematic diagrams of a method for manufacturing the packaging device of  FIG. 2 ; and 
         FIGS. 5A-5F  are schematic diagrams of a method for manufacturing the packaging device of  FIG. 3 . 
     
    
    
     DETAILED DESCRIPTION 
     Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIG. 1  is a schematic diagram of a packaging device according to one embodiment of the present invention, and  FIG. 2  is a cross-sectional view taken along line A-A of  FIG. 1  according to one embodiment. The packaging device includes a first semiconductor device  110 , a thermal dissipating component  120 , an encapsulation layer  130 , a via  140 , and a pad  150 . The first semiconductor device  110 , such as a flip-chip, includes a substrate  112 , an active region  114 , and an electrode  116 . The active region  114 , is disposed between the substrate  112  and the electrode  116 . The substrate  112  has a first surface  112   a  opposite to the active region  114 , and the electrode  116  has a second surface  116   b  opposite to the active region  114 . More specifically, the substrate  112  has the first surface  112   a  and a second surface  112   b  opposite to each other, and the electrode  116  has a first surface  116   a  and the second surface  116   b  opposite to each other. The second surface  112   b  of the substrate  112  faces the active region  114 , and the first surface  114   a  of the electrode  116  faces the active region  114 . The thermal dissipating component  120  is disposed on the first surface  112   a  of the substrate  112 . The encapsulation layer  130  encloses the second surface  116   b  of the electrode  116  and a part of the thermal dissipating component  120 , such that another part of the thermal dissipating component  120  is exposed by the encapsulation layer  130 . The pad  150  is disposed on the encapsulation layer  130 . The via  140  is disposed in the encapsulation layer  130  and connects the pad  150  to the electrode  116 . In some embodiments, the active region  114  and the electrode  116  can form a GaN transistor. 
     In this embodiment, since there is no electrically connection element to interconnect the thermal dissipating component  120  and the active region  114 , i.e., the thermal dissipating component  120  and the pad  150  are spatially separated, the packaging device can have individual current path and individual thermal path to improve heat dissipation. In greater detail, the first semiconductor device  110  can be electrically connected to external devices or circuits (such as plate circuit boards) sequentially through the via  140  and the pad  150 . This means the current of the first semiconductor device  110  flows to the external devices or circuits through the via  140  to the pad  150 . On the other hand, the first semiconductor device  110  (more specifically, the active region  114 ) generates heat when it is in operation, and the heat can be mainly dissipated through the thermal dissipating component  120 . Moreover, the heat dissipation efficiency is improved since a part of the thermal dissipating component  120  is exposed by the encapsulation layer  130 . As a result, the current and the heat of the first semiconductor device  110  can mainly flow from opposite sides (i.e., the first surface  112   a  and the second surface  116   b ) of the first semiconductor device  110 , respectively, such that the heat dissipation can be improved while the heat does not interfere with the electrical signal of the first semiconductor device  110 . Moreover, since the encapsulation layer  130  encloses a part of the thermal dissipating component  120 , i.e., the encapsulation layer  130  surrounds the thermal dissipating component  120  except the surface of the thermal dissipating component  120  opposite to the first semiconductor device  110 , the thermal dissipating component  120  has high structure strength and is hard to be striped from the first semiconductor device  110  because of the encapsulation layer  130 . 
     In this embodiment, the thickness T 1  of the thermal dissipating component  120  is greater than the thickness T 2  of the pad  150 . In other words, the thermal dissipating component  120  has higher thermal conductance than that of the pad  150  if they are made from the same material such as copper. Hence, the quantity of heat dissipation H 1  passing through the first surface  112   a  of the substrate  112  is greater than the quantity of heat dissipation H 2  passing through the second surface  116   b  of the electrode  116 . For example, over 50% of the heat generated from the active region  114  can be dissipated from the thermal dissipating component  120 . Moreover, the contact area between the thermal dissipating component  120  and the first semiconductor device  110  is larger than the contact area between the via  140  and the first semiconductor device  110 , facilitating the heat flow through the thermal dissipating component  120  rather than through the via  140  and the pad  150 . 
     In this embodiment, the packaging device further includes a solder  160  disposed between the first semiconductor device  110  and the thermal dissipating component  120 . The solder  160  is configured for fixing the first semiconductor device  110  to the thermal dissipating component  120 . The solder  160  may be made from metal, such as tin, silver, or alloys. 
     In one or more embodiments, the electrodes  116 , the vias  140  and the pads  150  can be plural. The pads  150  can be electrically connected to the different electrodes  116 , such as a source electrode, a drain electrode, and a gate electrode, of the first semiconductor device  110  through different vias  140 . Furthermore, since heat of the first semiconductor device  110  does not mainly flow through the vias  140 , distance among the vias  140  can be extended to achieve high voltage device package. 
       FIG. 3  is a cross-sectional view taken along line A-A of  FIG. 1  according to another embodiment. In this embodiment, the packaging device includes a plurality of semiconductor devices. In greater detail, the thermal dissipating component  120  includes a first portion  122  and a second portion  124  separated from each other. The first portion  122  is disposed on the first semiconductor device  110 . The packaging device further includes a second semiconductor device  170 , and the second portion  124  is disposed thereon. In this embodiment, the current of the second semiconductor device  170  can flow to the external device or circuits through some of the vias  140  and some of the pads  150 . 
     In this embodiment, both of the first semiconductor device  110  and the second semiconductor device  170  have individual current paths and heat paths. The currents flow from the second surfaces  116   b  and  176   b  of the first semiconductor device  110  and the second semiconductor device  170  while the heats mainly flow from the first surfaces  112   a  and  172   a  of the first semiconductor device  110  and the second semiconductor device  170 . Therefore, the heat dissipation of both of the first semiconductor device  110  and the second semiconductor device  170  can be improved. 
     In this embodiment, the packaging device allows semiconductor devices with different heights to be packaged together. That is, the thickness T 3  of the first semiconductor device  110  can be different from the thickness T 4  of the second semiconductor device  170 . For example, the thickness T 3  of the first semiconductor device  110  is greater than the thickness T 4  of the second semiconductor device  170 , as shown in  FIG. 3 . Thus, the first portion  122  of the thermal dissipating component  120  can have a cavity  123  for accommodating the first semiconductor device  110 . For example, the depth of the cavity  123  can be the height difference (i.e., T 1 -T 2 ) between the first semiconductor device  110  and the second semiconductor device  170 . In this way, the second surface  116   b  of the first semiconductor device  110  and a surface of the second semiconductor device  170  opposite to the thermal dissipating component  120  (i.e., the second surface  176   b ) are coplanar. This configuration facilitates convenience for manufacturing the vias  140 . 
     In this embodiment, the solder  160  is disposed between the first semiconductor device  110  and the first portion  122  of the thermal dissipating component  120 . The solder  160  is configured for fixing the first semiconductor device  110  to the first portion  122 . Furthermore, the packaging device can further include a solder  165  disposed between the second semiconductor device  170  and the second portion  124  of the thermal dissipating component  120 . The solder  165  is configured for fixing the second semiconductor device  170  to the second portion  124 . Both of the solders  160  and  165  may be made from metal, such as tin, silver, or alloys. 
     In this embodiment, the packaging device can further include an insulating layer  180 , a plurality of inter-pillars  190 , and a patterned metal layer  195 . The insulating layer  180  is disposed between the pads  150  and the patterned metal layer  195 . The inter-pillars  190  are disposed within the insulating layer  180  and interconnect the pads  150  and the patterned metal layer  195 . The pads  150 , the inter-pillars  190 , and the patterned metal layer  195  can form different circuits that depends on the electrically connection between the first semiconductor device  110  and the second semiconductor device  170 . In some embodiments, the inter-pillars  190  and the patterned metal layer  195  can be formed from copper, and the claimed scope is not limited in this respect. Other relevant structural details of the packaging device of  FIG. 3  are all the same as the packaging device of  FIG. 2 , and, therefore, a description in this regard will not be repeated hereinafter. 
       FIGS. 4A-4D  are schematic diagrams of a method for manufacturing the packaging device of  FIG. 2 . Reference is made to  FIG. 4A . A thermal dissipating component  120  is provided. In this embodiment, the thermal dissipating component  120  is a pre-formed metal plate, such as copper plate. This means the thermal dissipating component  120  is no longer to be cut or shaped during the following manufacturing processes. Subsequently, a first surface  112   a  (see  FIG. 2 ) of a first semiconductor device  110  is fixed above the thermal dissipating component  120 . The first surface  112   a  is a surface without any circuit layout. That is, the current of the first semiconductor device  110  does not flow through the first surface  112   a . The first semiconductor device  110  can be attached to the thermal dissipating component  120  using a solder  160  or a die attached material. That is, the solder  160  is formed between the first semiconductor device  110  and the thermal dissipating component  120 . In some embodiments, the solder  160  can be made from metal, such as tin, silver, or alloys. 
     In this embodiment, the first semiconductor device  110  includes a substrate  112 , an active region  114 , and an electrode  116 . The active region  114  is disposed between the substrate  112  and the electrode  116 . The first semiconductor device  110  can be a flip-chip, and the active region  114  and the electrode  116  can form a GaN transistor. The electrodes  116  can be a source electrode, a drain electrode, or a gate electrode. However, the type of the active region  114  is not limited in this respect. 
     Reference is made to  FIGS. 4B and 2 . Then, the thermal dissipating component  120  and the first semiconductor device  110  are covered by an encapsulation layer  130 . The encapsulation layer  130  encloses a part of the thermal dissipating component  120  and another part of the thermal dissipating component  120  is exposed by the encapsulation layer  130 , as shown in  FIG. 2 . In other words, the thermal dissipating component  120  and the first semiconductor device  110  are covered by the encapsulation layer  130  except the exposed part of the thermal dissipating component  120 . In some embodiments, the encapsulation layer  130  can be performed using epoxy, resin, or insulating materials, and the encapsulation layer  130  can be made from polymer materials. 
     Reference is made to  FIG. 4C . For clarity, the embedded portion of through holes in  FIGS. 4C to 4D  are depicted with thin lines. A plurality of through holes  132  are formed in the encapsulation layer  130  to expose a portion of a second surface  116   b  (see  FIG. 2 ) of the first semiconductor device  110 . That is, the through holes  132  can respectively expose portions of the electrodes  116  of the first semiconductor device  110 . In some embodiments, the through holes  132  can be performed using photolithography process, laser drilling process, or mechanical machining process. 
     Reference is made to  FIG. 4D . A plurality of vias  140  are formed in the through holes  132 . In some embodiments, the vias  140  are performed using copper electroplating process. In other words, the vias  140  are made from copper. A copper electrolyte can be filled in the through holes  132  to form the vias  140 . Subsequently, a plurality of pads  150  are formed on the vias  140  and the encapsulation layer  130 . For example, a copper layer can be formed on the vias  140  and the encapsulateon layer  130  using copper electroplating process or laminating process. Then, the copper layer is patterned to be the pads  150 , whose patterns are not limited in the structure shown in  FIG. 4D . Each pad  150  can be electrically connected to different electrode  116  (see  FIG. 4C ) of the first semiconductor device  110 . As a result, the manufacturing process of the packaging device is complete. 
       FIGS. 5A-5F  are schematic diagrams of a method for manufacturing the packaging device of  FIG. 3 . In the following paragraphs, the manufacturing details described before are not repeated hereinafter, and only further information is supplied to perform the packaging device of  FIG. 3 . Reference is made to  FIG. 5A . A thermal dissipating component  120  is provided. The thermal dissipating component  120  includes a first portion  122  and a second portion  124 , and both of the first portion  122  and a second portion  124  are pre-performed metal plates. Subsequently, a first surface  112   a  (see  FIG. 3 ) of a first semiconductor device  110  is fixed above the first portion  122  of the thermal dissipating component  120 , and a first surface  172   a  (see  FIG. 3 ) of a second semiconductor device  170  is fixed above the second portion  124  of the thermal dissipating component  120 . The first surfaces  112   a  and  172   a  are surfaces without any circuit layout. The first semiconductor device  110  can be attached to the first portion  122  using a solder  160  or a die attached material, and the second semiconductor device  170  can be attached to the second portion  124  using a solder  165  or a die attached material. That is, the solder  160  is formed between the first semiconductor device  110  and the first portion  122 , and the solder  165  is formed between the second semiconductor device  170  and the second portion  124 . In some embodiments, the solders  160  and  165  can be made from metal, such as tin, silver, or alloys. 
     In this embodiment, the second semiconductor device  170  includes a substrate  172 , an active region  174 , and an electrode  176 . The active region  174  is disposed between the substrate  172  and the electrode  176 . Furthermore, reference is made to  FIGS. 5A and 3 . The thickness T 2  of the second semiconductor device  170  can be different from the thickness T 1  of the first semiconductor device  110 . For example, the thickness T 1  is greater than the thickness T 2 . Hence, a cavity  123  can be formed in the first portion  122  of the thermal dissipating component  120 . The depth of the cavity  123  can be substantially the difference between the thickness T 1  and T 2 . Therefore, the second surfaces  116   b  and  176   b  are coplanar as shown in  FIG. 3 . 
     Reference is made again to  FIG. 5A . In this embodiment, a third semiconductor device  210  can be fixed above the first portion  122  and the second portion  124  of the thermal dissipating component  120 . That is, the third semiconductor device  210  is electrically connected to the first portion  122  and the second portion  124  of the thermal dissipating component  120 . The third semiconductor device  210  can be attached to the first portion  122  using a solder  220  and to the second portion  124  using a solder  225 . In some embodiments, the solders  220  and  225  can be made from metal, such as tin, silver, or alloys. Moreover, if the third semiconductor device  210  is thicker than the second semiconductor device  170 , a cavity  125  can be formed in the first portion  122  and a cavity  126  can be formed in the second portion  124  to together accommodate the third semiconductor device  210 . 
     Reference is made to  FIGS. 5B and 3 . Then, the thermal dissipating component  120 , the first semiconductor device  110 , the second semiconductor device  170 , and the third semiconductor device  210  are all covered by an encapsulation layer  130 . The encapsulation layer  130  encloses the second portion  124  and a part of the first portion  122  of the thermal dissipating component  120 , and another part of the first portion  122  is exposed by the encapsulation layer  130 , as shown in  FIG. 3 . In other words, the thermal dissipating component  120  and the first semiconductor device  110  are covered by the encapsulation layer  130  except the exposed part of the first portion  122 . 
     Reference is made to  FIG. 5C . For clarity, the embedded portion of through holes in  FIGS. 5C to 5F  are depicted with thin lines. A plurality of through holes  132  are formed in the encapsulation layer  130  to expose a portion of a second surface  116   b  (see  FIG. 3 ) of the first semiconductor device  110  and a second surface  176   b  (see  FIG. 3 ) of the second semiconductor device  170 . That is, the through holes  132  can respectively expose portions of the electrodes  116  and  176  of the first semiconductor device  110  and the second semiconductor device  170 . Moreover, in some embodiments, a plurality of through holes  134  can be formed in the encapsulation layer  130  to expose a portion of the second portion  124  of the thermal dissipating component  120 . 
     Reference is made to  FIG. 5D . A plurality of vias  140  are formed in the through holes  132  and a plurality of vias  145  are formed in the through holes  134 . In some embodiments, the vias  140  and  145  are performed using copper electroplating process. In other words, the vias  140  and  145  are made from copper. A copper electrolyte can be filled in the through holes  132  and  134  to form the vias  140  and  145 . Subsequently, a plurality of pads  150  are formed on the vias  140  and  145  and the encapsulation layer  130 . For example, a copper layer can be formed on the vias  140 ,  145  and the encapsulateon layer  130  using copper electroplating process or laminating process. Then, the copper layer is patterned to be the pads  150 , whose patterns are not limited in the structure shown in  FIG. 5D . Each pad  150  can be electrically connected to the electrode  116  (see  FIG. 5C ) of the first semiconductor device  110 , the electrode  176  (see  FIG. 5C ) of the second semiconductor device  170 , or the second portion  124  of the thermal dissipating component  120 . Moreover, since the vias  145  interconnect some of the pads  150  and the second portion  124  of the thermal dissipating component  120 , and the third semiconductor device  210  (see  FIG. 5B ) is electrically connected to the first portion  122  and the second portion  124 , the first portion  122  and the second portion  124  can be as portions of circuit of the packaging device. However, the vias  145  can be omitted if there is no need to interconnect the second portion  124  and the pad  150 . As a result, the manufacturing process of the packaging device is complete. 
     Reference is made to  FIG. 5E . In some embodiments, after the step of  FIG. 5D , an insulating layer  180  can be formed on and cover the pads  150 . Then, a plurality of through holes  182  are formed in the insulating layer  180  to expose portions of the pads  150 . In this embodiment, the insulating layer  180  can be made from epoxy, resin, or insulating materials, the insulating layer  180  is formed using molding process, and the through holes  182  are formed using photolithography process, laser drilling process, or mechanical machining process. 
     Reference is made to  FIG. 5F . A plurality of inter-pillars  190  are formed in the through holes  182 , and a patterned metal layer  195  is formed on the inter-pillars  190  and the insulating layer  180 . Since the manufacturing process of the inter-pillars  190  and the patterned metal layer  195  are the same as that of the vias  140  and the pads  150 , a description in this regard will not be repeated hereinafter. The pads  150  (see  FIG. 5E ), the inter-pillars  190 , and the patterned metal layer  195  can form different circuits that depends on the electrically connection between the first semiconductor device  110  and the second semiconductor device  170  (see  FIG. 5A ). As a result, the manufacturing process of the packaging device is complete. 
     Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.