Patent Publication Number: US-11652038-B2

Title: Semiconductor package with front side and back side redistribution structures and fabricating method thereof

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS/INCORPORATION BY REFERENCE 
     The present application is a continuation of U.S. patent application Ser. No. 16/260,674, filed Jan. 29, 2019, and titled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” expected to issue as U.S. Pat. No. 10,943,858; which is a continuation of U.S. patent application Ser. No. 15/854,095, filed Dec. 26, 2017, and titled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” now U.S. Pat. No. 10,192,816; which is a CONTINUATION of U.S. patent application Ser. No. 15/400,041, filed Jan. 6, 2017, and titled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” now U.S. Pat. No. 9,852,976; which is a CONTINUATION of U.S. patent application Ser. No. 14/823,689, filed Aug. 11, 2015, and titled “SEMICONDUCTOR PACKAGE AND FABRICATING METHOD THEREOF,” now U.S. Pat. No. 9,543,242; the contents of each of which are hereby incorporated herein by reference in their entirety. 
     This application is related to U.S. patent application Ser. No. 13/753,120, filed Jan. 29, 2013, and titled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE”; U.S. patent application Ser. No. 13/863,457, filed on Apr. 16, 2013, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/083,779, filed on Nov. 19, 2013, and titled “SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIA-LESS DEEP WELLS”; U.S. patent application Ser. No. 14/218,265, filed Mar. 18, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/313,724, filed Jun. 24, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/444,450, Jul. 28, 2014, and titled “SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS”; U.S. patent application Ser. No. 14/524,443, filed Oct. 27, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS”; U.S. patent application Ser. No. 14/532,532, filed Nov. 4, 2014, and titled “INTERPOSER, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE”; U.S. patent application Ser. No. 14/546,484, filed Nov. 18, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE”; and U.S. patent application Ser. No. 14/671,095, filed Mar. 27, 2015, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF;” the contents of each of which are hereby incorporated herein by reference in their entirety. 
    
    
     FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     [Not Applicable] 
     SEQUENCE LISTING 
     [Not Applicable] 
     MICROFICHE/COPYRIGHT REFERENCE 
     [Not Applicable] 
     BACKGROUND 
     Present semiconductor packages and methods for forming semiconductor packages are inadequate, for example resulting in excess cost, decreased reliability, or package sizes that are too large. Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such approaches with the present disclosure as set forth in the remainder of the present application with reference to the drawings. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the present disclosure, and are incorporated in and constitute a part of this specification. The drawings illustrate examples of the present disclosure and, together with the description, serve to explain various principles of the present disclosure. In the drawings: 
         FIGS.  1 A- 1 J  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  2    is a flow diagram of an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  3 A- 3 B  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  4 A- 4 D  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  5 A- 5 F  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  6 A- 6 D  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  7 A- 7 L  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  8    is a flow diagram of an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  9    shows a cross-sectional view illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  10 A- 10 B  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  11 A- 11 D  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIGS.  12 A- 12 B  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  13    shows a cross-sectional view illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  14    shows a cross-sectional view illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  15    shows a cross-sectional view illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
         FIG.  16    shows a cross-sectional view illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. 
     
    
    
     SUMMARY 
     Various aspects of this disclosure provide a semiconductor device structure and a method for making a semiconductor device. As non-limiting examples, various aspects of this disclosure provide various semiconductor package structures, and methods for making thereof, that comprise a thin fine-pitch redistribution structure. 
     DETAILED DESCRIPTION OF VARIOUS ASPECTS OF THE DISCLOSURE 
     The following discussion presents various aspects of the present disclosure by providing examples thereof. Such examples are non-limiting, and thus the scope of various aspects of the present disclosure should not necessarily be limited by any particular characteristics of the provided examples. In the following discussion, the phrases “for example,” “e.g.,” and “exemplary” are non-limiting and are generally synonymous with “by way of example and not limitation,” “for example and not limitation,” and the like. 
     As utilized herein, “and/or” means any one or more of the items in the list joined by “and/or”. As an example, “x and/or y” means any element of the three-element set {(x), (y), (x, y)}. In other words, “x and/or y” means “one or both of x and y.” As another example, “x, y, and/or z” means any element of the seven-element set {(x), (y), (z), (x, y), (x, z), (y, z), (x, y, z)}. In other words, “x, y and/or z” means “one or more of x, y, and z.” 
     The terminology used herein is for the purpose of describing particular examples only and is not intended to be limiting of the disclosure. As used herein, the singular forms are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “includes,” “comprising,” “including,” “has,” “have,” “having,” and the like when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Thus, for example, a first element, a first component or a first section discussed below could be termed a second element, a second component or a second section without departing from the teachings of the present disclosure. Similarly, various spatial terms, such as “upper,” “lower,” “side,” and the like, may be used in distinguishing one element from another element in a relative manner. It should be understood, however, that components may be oriented in different manners, for example a semiconductor device may be turned sideways so that its “top” surface is facing horizontally and its “side” surface is facing vertically, without departing from the teachings of the present disclosure. 
     Various aspects of the present disclosure provide a semiconductor device or package and a fabricating (or manufacturing) method thereof, which can decrease the cost, increase the reliability, and/or increase the manufacturability of the semiconductor device. 
     The above and other aspects of the present disclosure will be described in or be apparent from the following description of various example implementations. Various aspects of the present disclosure will now be presented with reference to accompanying drawings, such that those skilled in the art may readily practice the various aspects. 
       FIGS.  1 A- 1 J  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. The structures shown in  1 A- 1 J may share any or all characteristics with analogous structures shown in  FIGS.  3 A- 3 B,  4 A- 4 D,  5 A- 5 F,  6 A- 6 D,  7 A- 7 L,  9 ,  10 A- 10 B,  11 A- 11 D,  12 A- 12 B,  13 ,  14 ,  15 , and  16   .  FIG.  2    is a flow diagram of an example method  200  of making a semiconductor package, in accordance with various aspects of the present disclosure.  FIGS.  1 A- 1 K  may, for example, illustrate an example semiconductor package at various steps (or blocks) of the method  200  of  FIG.  2   .  FIGS.  1 A- 1 K  and  FIG.  2    will now be discussed together. It should be noted that the order of the example blocks of the method  200  may vary without departing from the scope of this disclosure. 
     The example method  200  may, at block  205 , comprise preparing a logic wafer for processing (e.g., for packaging). Block  205  may comprise preparing a logic wafer for processing in any of a variety of manners, non-limiting manner of which are presented herein. 
     For example, block  205  may comprise receiving a logic wafer, for example from supplier shipping, from an upstream process at a manufacturing site, etc. The logic wafer may, for example, comprise a semiconductor wafer that comprises a plurality of active semiconductor die. The semiconductor die may, for example, comprise a processor die, memory die, programmable logic die, application specific integrated circuit die, general logic die, etc. 
     Block  205  may, for example, comprise forming conductive interconnection structures on the logic wafer. Such conductive interconnection structures may, for example, comprise conductive pads, lands, bumps or balls, conductive pillars, etc. The forming may, for example, comprise attaching preformed interconnection structures to the logic wafer, plating the interconnection structures on the logic wafer, etc. 
     In an example implementation, the conductive structures may comprise conductive pillars comprising copper and/or nickel, and may comprise a solder cap (e.g., comprising tin and/or silver). For example, conductive structures comprising conductive pillars may comprise: (a) an under bump metallization (“UBM”) structure that includes (i) a layer of titanium-tungsten (TiW) formed by sputtering (which may be referred to as a “seed layer”), and (ii) a layer of copper (Cu) on the titanium-tungsten layer formed by sputtering, (b) a copper pillar formed on the UBM by electroplating, and (c) a layer of solder formed on the copper pillar or a layer of nickel formed on the copper pillar with a layer of solder formed on the nickel layer. 
     Also, in an example implementation, the conductive structures may comprise a lead and/or lead-free wafer bump. For example, lead-free wafer bumps (or interconnect structures) may be formed, at least in part, by: (a) forming an under bump metallization (UBM) structure by (i) forming a layer of titanium (Ti) or titanium-tungsten (TiW) by sputtering, (ii) forming a layer of copper (Cu) on the titanium or titanium-tungsten layer by sputtering, (iii) and forming a layer of nickel (Ni) on the copper layer by electroplating; and (b) forming a lead free solder material on the nickel layer of the UBM structure by electroplating, wherein the lead free solder material has a composition by weight of 1% to 4% silver (Ag) and the remainder of the composition by weight is tin (Sn). 
     Block  205  may, for example, comprise performing partial or full thinning of the logic wafer (e.g., grinding, etching, etc.). Block  205  may also, for example, comprise dicing the logic wafer into separate die or die sets for later attachment. Block  205  may also comprise receiving the logic wafer from an adjacent or upstream manufacturing station at a manufacturing facility, from another geographical location, etc. The logic wafer may, for example, be received already prepared or additional preparation steps may be performed. 
     In general, block  205  may comprise preparing a logic wafer for processing (e.g., for packaging). Accordingly, the scope of this disclosure should not be limited by characteristics of particular types of logic wafer and/or die processing. 
     The example method  200  may, at block  210 , comprise preparing a carrier, substrate, or wafer. The prepared (or received) wafer may be referred to as a redistribution structure wafer or RD wafer. Block  210  may comprise preparing an RD wafer for processing in any of a variety of manners, non-limiting example of which are presented herein. 
     The RD wafer may, for example, comprise an interposer wafer, wafer of package substrates, etc. The RD wafer may, for example, comprise a redistribution structure formed (e.g., on a die-by-die basis) on a semiconductor (e.g., silicon) wafer. The RD wafer might, for example, comprise only electrical pathways and not electronic devices (e.g., semiconductor devices). The RD wafer might also, for example, comprise passive electronic devices but not active semiconductor devices. For example, the RD wafer may comprise one or more conductive layers or traces formed on (e.g., directly or indirectly on) or coupled to a substrate or carrier. Examples of the carrier or substrate may include a semiconductor (e.g., silicon) wafer or a glass substrate. Examples of processes used to form conductive layers (e.g., copper, aluminum, tungsten, etc.) on a semiconductor wafer include utilizing semiconductor wafer fabrication processes, which may also be referred to herein as back end of line (BEOL) processes. In an example implementation, the conductive layers may be deposited on or over a substrate using a puttering and/or electroplating process. The conductive layers may be referred to as redistribution layers. The redistribution layers may be used to route an electrical signal between two or more electrical connections and/or to route an electrical connection to a wider or narrower pitch. 
     In an example implementation, various portions of the redistribution structure (e.g., interconnection structures (e.g., lands, traces, etc.) that may be attached to electronic devices) may be formed having a sub-micron pitch (or center-to-center spacing) and/or less than a 2 micron pitch. In various other implementations, a 2-5 micron pitch may be utilized. 
     In an example implementation, a silicon wafer on which the redistribution structure is formed may comprise silicon that is a lower grade than can be adequately utilized to form the semiconductor die ultimately attached to the redistribution structure. In another example implementation, the silicon wafer may be a reclaimed silicon wafer from a failed semiconductor device wafer fabrication. In a further example implementation, the silicon wafer may comprise a silicon layer that is thinner than can be adequately utilized to form the semiconductor die ultimately attached to the redistribution structure. Block  210  may also comprise receiving the RD wafer from an adjacent or upstream manufacturing station at a manufacturing facility, from another geographical location, etc. The RD wafer may, for example, be received already prepared or additional preparation steps may be performed. 
       FIG.  1 A  provides an example illustration of various aspects of block  210 . Referring to  FIG.  1 A , the RD wafer  100 A may, for example, comprise a support layer  105  (e.g., a silicon or other semiconductor layer, a glass layer, etc.). A redistribution (RD) structure  110  may be formed on the support layer  105 . The RD structure  110  may, for example, comprise a base dielectric layer  111 , a first dielectric layer  113 , first conductive traces  112 , a second dielectric layer  116 , second conductive traces  115 , and interconnection structures  117 . 
     The base dielectric layer  111  may, for example, be on the support layer  105 . The base dielectric layer  111  may, for example, comprise an oxide layer, a nitride layer, etc. The base dielectric layer  111  may, for example, be formed to specification and/or may be native. Dielectric layer  111  may be referred to as a passivation layer. Dielectric layer  111  may be or comprise, for example, a silicon dioxide layer formed using a low pressure chemical vapor deposition (LPCVD) process. 
     The RD wafer  100 A may also, for example, comprise first conductive traces  112  and a first dielectric layer  113 . The first conductive traces  112  may, for example, comprise deposited conductive metal (e.g., copper, aluminum, tungsten, etc.). Conductive traces  112  may be formed by sputtering and/or electro-plating. The conductive traces  112  may, for example, be formed at a sub-micron or sub-two-micron pitch (or center-to-center spacing). The first dielectric layer  113  may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). Note that in various implementations, the dielectric layer  113  may be formed prior to the first conductive traces  112 , for example formed with apertures which are then filled with the first conductive traces  112  or a portion thereof. In an example implementation, for example comprising copper conductive traces, a dual damascene process may be utilized to deposit the traces. 
     In an alternative assembly, the first dielectric layer  113  may comprise an organic dielectric material. For example, the first dielectric layer  113  may comprise bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzo cyclo butene (BCB), poly benz oxazole (PBO), epoxy and equivalents thereof and compounds thereof, but aspects of the present disclosure are not limited thereto. The organic dielectric material may be formed in any of a variety of manners, for example chemical vapor deposition (CVD). In such an alternative assembly, the first conductive traces  112  may, for example, be at a 2-5 micron pitch (or center-to-center spacing). 
     The RD wafer  100 A may also, for example, comprise second conductive traces  115  and a second dielectric layer  116 . The second conductive traces  115  may, for example, comprise deposited conductive metal (e.g., copper, etc.). The second conductive traces  115  may, for example, be connected to respective first conductive traces  112  through respective conductive vias  114  (e.g., in the first dielectric layer  113 ). The second dielectric layer  116  may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer  116  may comprise an organic dielectric material. For example, the second dielectric layer  116  may comprise bismaleimidetriazine (BT), phenolic resin, polyimide (PI), benzo cyclo butene (BCB), poly benz oxazole (PBO), epoxy and equivalents thereof and compounds thereof, but aspects of the present disclosure are not limited thereto. The second dielectric layer  116  may, for example, be formed using a CVD process, but the scope of this disclosure is not limited thereto. 
     Though two sets of dielectric layers and conductive traces are illustrated in  FIG.  1 A , it should be understood that the RD structure  110  of the RD wafer  100 A may comprise any number of such layers and traces. For example, the RD structure  110  might comprise only one dielectric layer and/or set of conductive traces, three sets of dielectric layers and/or conductive traces, etc. 
     As with the logic wafer prep at block  205 , block  210  may comprise forming interconnection structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive lands or pads, etc.) on a surface of the RD structure  110 . Examples of such interconnection structures  117  are shown in  FIG.  1 A , in which the RD structure  110  comprises interconnection structures  117 , which are shown formed on the front (or top) side of the RD structure  110  and electrically connected to respective second conductive traces  115  through conductive vias in the second dielectric layer  116 . Such interconnection structures  117  may, for example, be utilized to couple the RD structure  110  to various electronic components (e.g., active semiconductor components or die, passive components, etc.). 
     The interconnection structures  117  may, for example, comprise any of a variety of conductive materials (e.g., any one of or a combination of copper, nickel, gold, etc.). The interconnection structures  117  may also, for example, comprise solder. 
     In general, block  210  may comprise preparing a redistribution structure wafer (RD wafer). Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of performing such preparing. 
     The example method  200  may, at block  215 , comprise forming interconnection structures (e.g., through mold via (TMV) interconnection structures) on the RD wafer. Block  215  may comprise forming such interconnection structures in any of a variety of manners. 
     The interconnection structures may comprise any of a variety of characteristics. For example, the interconnection structures may comprise solder balls or bumps, multi-ball solder columns, elongated solder balls, metal (e.g., copper) core balls with a layer of solder over a metal core, plated pillar structures (e.g., copper pillars, etc.), wire structures (e.g., wire bonding wires), etc. 
     The interconnection structures may comprise any of a variety of dimensions. For example, the interconnection structures may extend from the RD wafer to a height less than the heights of the electronic components coupled to the RD wafer (e.g., at block  220 ). Also for example, the interconnection structures may extend from the RD wafer to a height greater than or equal to the heights of the electronic components coupled to the RD wafer. The significance of such relative heights will become apparent in the discussion herein (e.g., in the discussions of mold thinning, package stacking, top substrate attaching, top redistribution structure formation, etc.). The interconnection structures may also, for example, be formed at various pitches (or center-to-center spacing). For example, the interconnection structures (e.g., conductive posts or pillars) may be plated and/or bonded at a 150-250 micron pitch or less. Also for example, the interconnection structures (e.g., elongated and/or metal-filled solder structures) may be attached at a 250-350 micron pitch or less. Additionally for example, the interconnection structures (e.g., solder balls) may be attached at a 350-450 micron pitch or less. 
     Block  215  may comprise attaching the interconnection structures in any of a variety of manners. For example, block  215  may comprise reflow-attaching the interconnection structures on the RD wafer, plating the interconnection structures on the RD wafer, wire-bonding the interconnection structures on the RD wafer, attaching preformed interconnection structures to the RD wafer with conductive epoxy, etc. 
       FIG.  1 B  provides an example illustration of various aspects of block  215 , for example interconnection structure formation aspects. In the example assembly  100 , the interconnection structures  121  (e.g., solder balls) are attached (e.g., reflow attached, attached using a solder ball drop process, etc.) to the RD structure  110  of the RD wafer  100 A. 
     Though two rows of interconnection structures  121  are shown, various implementations may comprise a single row, three rows, or any number of rows. As will be discussed herein, various example implementations might have none of such interconnection structures  121  and thus block  215  might be included in example method  200 . 
     Note that although in the example method  200 , the block  215  is performed before the wafer molding operation at block  230 , the interconnection structures may be formed after the wafer molding operation instead (e.g., forming via apertures in the mold material and then filling such apertures with conductive material). Also note that block  215  may be performed after the block  220  die attachment operation as shown in  FIG.  2   , for example instead of before die attachment. 
     In general, block  215  may comprise forming interconnection structures on the RD wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of particular types of interconnection structures or by characteristics of any particular manner of forming such interconnection structures. 
     The example method  200  may, at block  220 , comprise attaching one or more semiconductor die to the RD structure (e.g., of the RD wafer). Block  220  may comprise attaching the die to the RD structure in any of a variety of manners, non-limiting examples of which are provided herein. 
     The semiconductor die may comprise characteristics of any of a variety of types of semiconductor die. For example, the semiconductor die may comprise a processor die, a memory die, an application specific integrated circuit die, general logic die, active semiconductor components, etc.). Note that passive components may also be attached at block  220 . 
     Block  220  may comprise attaching the semiconductor die (e.g., as prepared at block  205 ) in any of a variety of manners. For example, block  220  may comprise attaching the semiconductor die utilizing mass reflow, thermocompression bonding (TCB), conductive epoxy, etc. 
       FIG.  1 B  provides an example illustration of various aspects of block  220 , for example die attachment aspects. For example, the first die  125  (e.g., which may have been diced from a logic wafer prepared at block  205 ) is electrically and mechanically attached the redistribution structure  110 . Similarly, the second die  126  (e.g., which may have been diced from a logic wafer prepared at block  205 ) is electrically and mechanically attached to the redistribution structure  110 . For example, as explained at block  205 , the logic wafer (or die thereof) may have been prepared with various interconnection structures (e.g., conductive pads, lands, bumps, balls, wafer bumps, conductive pillars, etc.) formed thereon. Such structures are shown generally in  FIG.  1 B  as items  119 . Block  220  may, for example, comprise electrically and mechanically attaching such interconnection structures to the redistribution structure  110  utilizing any of a variety of attachment processes (e.g., mass reflow, thermocompression bonding (TCB), conductive epoxy, etc.). 
     The first die  125  and the second die  126  may comprise any of a variety of die characteristics. In an example scenario, the first die  125  may comprise a processor die and the second die  126  may comprise a memory die. In another example scenario, the first die  125  may comprise a processor die, and the second die  126  may comprise a co-processor die. In another example scenario, the first die  125  may comprise a sensor die, and the second die  126  may comprise a sensor processing die. Though the assembly  100  at  FIG.  1 B  is shown with two die  125 ,  126 , there may be any number of die. For example, there might be only one die, three die, four die, or more than four die. 
     Additionally, though the first die  125  and the second die  126  are shown attached to the redistribution structure  110  laterally relative to each other, they may also be arranged in a vertical assembly. Various non-limiting examples of such structures are shown and discussed herein (e.g., die-on-die stacking, die attachment to opposite substrate sides, etc.). Also, though the first die  125  and the second die  126  are shown with generally similar dimensions, such die  125 ,  126  may comprise different respective characteristics (e.g., die height, footprint, connection pitch, etc.). 
     The first die  125  and the second die  126  are illustrated with generally consistent pitch, but this need not be the case. For example, most or all of the contacts  119  of the first die  125  in a region of the first die footprint immediately adjacent to the second die  126  and/or most of the contacts  119  of the second die  126  in a region of the second die footprint immediately adjacent to the first die  125  may have substantially finer pitch than most or all of the other contacts  119 . For example, a first 5, 10, or n rows of contacts  119  of the first die  125  closest to the second die  126  (and/or of the second die  126  closest to the first die  125 ) may have a 30 micron pitch, while other contacts  119  may generally have an 80 micron and/or 200 micron pitch. The RD structure  110  may thus have corresponding contact structures and/or traces at the corresponding pitch. 
     In general, block  220  comprises attaching one or more semiconductor die to the redistribution structure (e.g., of a redistribution wafer). Accordingly, the scope of this disclosure should not be limited by characteristics of any particular die, or by characteristics of any particular multi-die layout, or by characteristics of any particular manner of attaching such die, etc. 
     The example method  200  may, at block  225 , comprise underfilling the semiconductor die and/or other components attached to the RD structure at block  220 . Block  225  may comprise performing such underfilling in any of a variety of manners, non-limiting examples of which are presented herein. 
     For example, after die attachment at block  220 , block  225  may comprise underfilling the semiconductor die utilizing a capillary underfill. For example, the underfill may comprise a reinforced polymer material viscous enough to flow between the attached die and the RD wafer in a capillary action. 
     Also for example, block  225  may comprise underfilling the semiconductor die utilizing a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the die are being attached at block  220  (e.g., utilizing a thermocompression bonding process). For example, such underfill materials may be deposited (e.g., printed, sprayed, etc.) prior to attaching the semiconductor die. 
     As with all of the blocks illustrated in the example method  200 , block  225  may be performed at any location in the method  200  flow so long as the space between the die and the redistribution structure is accessible. 
     The underfilling may also occur at a different block of the example method  200 . For example, the underfilling may be performed as part of the wafer molding block  230  (e.g., utilizing a molded underfill). 
       FIG.  1 B  provides an example illustration of various aspects of block  225 , for example the underfilling aspects. The underfill  128  is positioned between the first semiconductor die  125  and the redistribution structure  110  and between the second semiconductor die  126  and the redistribution structure  110 , for example surrounding the contacts  119 . 
     Though the underfill  128  is generally illustrated to be flat, the underfill may rise up and form fillets on the sides of the semiconductor die and/or other components. In an example scenario, at least a fourth or at least a half of the die side surfaces may be covered by the underfill material. In another example scenario, one or more or all of the entire side surfaces may be covered by the underfill material. Also for example, a substantial portion of the space directly between the semiconductor die, between the semiconductor die and other components, and/or between other components may be filled with the underfill material. For example, at least half of the space or all of the space between laterally adjacent semiconductor die, between the die and other components, and/or between other components may be filled with the underfill material. In an example implementation, the underfill  128  may cover the entire redistribution structure  110  of the RD wafer. In such example implementation, when the RD wafer is later diced, such dicing may also cut through the underfill  128 . 
     In general, block  225  may comprise underfilling the semiconductor die and/or other components attached to the RD structure at block  220 . Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of underfill or of any particular manner of performing such underfilling. 
     The example method  200  may, at block  230 , comprise molding the RD wafer (e.g., or an RD structure). Block  230  may comprise molding the RD wafer in any of a variety of manners, non-limiting examples of which are presented herein. 
     For example, block  230  may comprise molding over the top surface of the RD wafer, over the die and/or other components attached at block  220 , over interconnection structures formed at block  215  (e.g., conductive balls, ellipsoids, columns or pillars (e.g., plated pillars, wires or wirebond wires, etc.), etc.), over the underfill formed at block  225 , etc. 
     Block  230  may, for example, comprise utilizing compression molding (e.g., utilizing liquid, powder and/or film) or vacuum molding. Also for example, block  230  may comprise utilizing a transfer molding process (e.g., a wafer-level transfer molding process). 
     The molding material may, for example, comprise any of a variety of characteristics. For example, the molding material (e.g., epoxy mold compound (EMC), epoxy resin molding compound, etc.) may comprise a relatively high modulus, for example to provide wafer support in a subsequent process. Also for example, the molding material may comprise a relatively low modulus, to provide wafer flexibility in a subsequent process. 
     As explained herein, for example with regard to block  225 , the molding process of block  230  may provide underfill between the die and the RD wafer. In such an example, there may be uniformity of material between the molded underfill material and the mold material encapsulating the semiconductor die. 
       FIG.  1 C  provides an example illustration of various aspects of block  230 , for example molding aspects. For example, the molded assembly  100 C is shown with the mold material  130  covering the interconnection structures  121 , first semiconductor die  125 , second semiconductor die  126 , underfill  128 , and the top surface of the redistribution structure  110 . Though the mold material  130 , which may also be referred to herein as encapsulant, is shown completely covering the sides and tops of the first semiconductor die  125  and second semiconductor die  126 , this need not be the case. For example, block  230  may comprise utilizing a film assist or die seal molding technique to keep the die tops free of mold material. 
     The mold material  130  may generally, for example, directly contact and cover portions of the die  125 ,  126  that are not covered by the underfill  128 . For example in a scenario in which at least a first portion of the sides of the die  125 ,  126  is covered by underfill  128 , the mold material  130  may directly contact and cover a second portion of the sides of the die  125 ,  126 . The mold material  130  may also, for example, fill the space between the die  125 ,  126  (e.g., at least a portion of the space that is not already filled with underfill  128 ). 
     In general, block  230  may comprise molding the RD wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular molding material, structure and/or technique. 
     The example method  200  may, at block  235 , comprise grinding (or otherwise thinning) the mold material applied at block  230 . Block  235  may comprise grinding (or thinning) the mold material in any of a variety of manners, non-limiting examples of which are presented herein. 
     Block  235  may, for example, comprise mechanically grinding the mold material to thin the mold material. Such thinning may, for example, leave the die and/or interconnection structures over molded, or such thinning may expose one or more die and/or one or more interconnection structures. 
     Block  235  may, for example, comprise grinding other components in addition to the mold compound. For example, block  235  may comprise grinding the top sides (e.g., backsides or inactive sides) of the die attached at block  220 . Block  235  may also, for example, comprise grinding the interconnect structures formed at block  215 . Additionally, in a scenario in which the underfill applied at block  225  or block  230  extends upward enough, block  235  may also comprise grinding such underfill material. Such grinding may, for example, result in a flat planar surface at the top of the ground material. 
     Block  235  may, for example, be skipped in a scenario in which the height of the mold material is originally formed at a desired thickness. 
       FIG.  1 D  provides an example illustration of various aspects of block  235 , for example the mold grinding aspects. The assembly  100 D is illustrated with the mold material  130  (e.g., relative to the mold material  130  illustrated at  FIG.  1 C ) thinned to reveal top surfaces of the die  125 ,  126 . In such an example, the die  125 ,  126  may also have been ground (or otherwise thinned). 
     Though as illustrated in  FIG.  1 D , the top surface of the mold material is above the interconnection structures  121 , and thus the interconnection structures  121  were not ground, the interconnection structures  121  may be ground as well. Such an example implementation may, for example, result in a top surface at this stage that includes a top surface of the die  125 ,  126 , a top surface of the mold material  130 , and a top surface of the interconnection structures  121 , all in a common plane. 
     As explained herein, the mold material  130  may be left covering the die  125 ,  126  in an overmold configuration. For example, the mold material  130  might not be ground, or the mold material  130  might be ground but not to a height that exposes the die  125 ,  126 . 
     In general, block  235  may comprise grinding (or otherwise thinning) the mold material applied at block  230 . Accordingly, the scope of this disclosure should not be limited by characteristics of any particular amount or type of grinding (or thinning). 
     The example method  200  may, at block  240 , comprise ablating the mold material applied at block  230 . Block  240  may comprise ablating the mold material in any of a variety of manners, non-limiting examples of which are provided herein. 
     As discussed herein, the mold material may cover the interconnection structures formed at block  215 . If the mold material covers the interconnection structures and the interconnection structures need to be revealed (e.g., for subsequent package attachment, top-side redistribution layer formation, top side laminate substrate attachment, electrical connection, heat sink connection, electromagnetic shield connection, etc.), block  240  may comprise ablating the mold material to reveal the connecting structures. 
     Block  240  may, for example, comprise exposing the interconnection structures through the mold material utilizing laser ablation. Also for example, block  240  may comprise utilizing soft beam drilling, mechanical drilling, chemical drilling, etc. 
       FIG.  1 D  provides an example illustration of various aspects of block  240 , for example the ablation aspects. For example, the assembly  100 D is shown comprising ablated vias  140  extending through the mold material  130  to the interconnection structures  121 . Though the ablated vias  140  are shown with vertical side walls, it should be understood that the vias  140  may comprise any of a variety of shapes. For example the side walls may be sloped (e.g., with larger openings at the top surface of the mold material  130  than at the interconnection structure  121 ). 
     Though block  240  is illustrated in  FIG.  2    as being immediately after wafer molding at block  230  and mold grinding at block  235 , block  240  may be performed at any point later in the method  200 . For example, block  240  may be performed after the wafer support structure (e.g., attached at block  245 ) is removed. 
     In general, block  240  may comprise ablating the mold material applied at block  230  (e.g., to expose the interconnection structures formed at block  215 ). Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of performing such ablation or by characteristics of any particular ablated via structure. 
     The example method  200  may, at block  245 , comprise attaching the molded RD wafer (e.g., the top or mold side thereof) to a wafer support structure. Block  245  may comprise attaching the molded RD wafer to the wafer support structure in any of a variety of manners, non-limiting examples of which are provided herein. 
     The wafer support structure may, for example, comprise a wafer or fixture formed of silicon, glass, or various other materials (e.g., dielectric materials). Block  245  may, for example, comprise attaching the molded RD wafer to the wafer support structure utilizing an adhesive, a vacuum fixture, etc. Note that as illustrated and explained herein, a redistribution structure may be formed on the top side (or backside) of the die and mold material prior to the wafer support attachment. 
       FIG.  1 E  provides an example illustration of various aspects of block  245 , for example wafer support attaching aspects. The wafer support structure  150  is attached to the top side of the mold material  130  and die  125 ,  126 . The wafer support structure  150  may, for example, be attached with an adhesive, and such adhesive may also be formed in the vias  140  and contacting the interconnection structures  121 . In another example assembly, the adhesive does not enter the vias  140  and/or does not contact the interconnection structures  121 . Note that in an assembly in which the tops of the die  125 ,  126  are covered with the mold material  130 , the wafer support structure  150  might only be directly coupled to the top of the mold material  130 . 
     In general, block  245  may comprise attaching the molded RD wafer (e.g., the top or mold side thereof) to a wafer support structure. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer support structure or by characteristics of any particular manner of attaching a wafer support structure. 
     The example method  200  may, at block  250 , comprise removing a support layer from the RD wafer. Block  250  may comprise removing the support layer in any of a variety of manners, non-limiting examples of which are presented herein. 
     As discussed herein, the RD wafer may comprise a support layer on which an RD structure is formed and/or carried. The support layer may, for example, comprise a semiconductor material (e.g., silicon). In an example scenario in which the support layer comprises a silicon wafer layer, block  250  may comprise removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all of the silicon, for example at least 90% or 95%, from the RD wafer, etc.). For example, block  250  may comprise mechanically grinding almost all of the silicon, followed by a dry or wet chemical etch to remove the remainder (or almost all of the remainder). In an example scenario in which the support layer is loosely attached to the RD structure formed (or carried) thereon, block  250  may comprise pulling or peeling to separate the support layer from the RD structure. 
       FIG.  1 F  provides an example illustration of various aspects of block  250 , for example support layer removing aspects. For example, the support layer  105  (shown in  FIG.  1 E ) is removed from the RD structure  110 . In the illustrated example, the RD structure  110  may still comprise abase dielectric layer  111  (e.g., an oxide, nitride, etc.) as discussed herein. 
     In general, block  250  may comprise removing a support layer from the RD wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer material or by characteristics of any particular manner of wafer material removal. 
     The example method  200  may, at block  255 , comprise forming and patterning a first redistribution layer (RDL) dielectric layer for etching an oxide layer of the RD structure. Block  255  may comprise forming and patterning the first RDL dielectric layer in any of a variety of manners, non-limiting examples of which are presented herein. 
     In the examples generally discussed herein, the RD structure of the RD wafer is generally formed on an oxide layer (or nitride or other dielectric). To enable metal-to-metal attachment to the RD structure portions of the oxide layer covering traces (or pads or lands) of the RD structure may be removed, for example by etching. Note that the oxide layer need not necessarily be removed or completely removed so long as it has acceptable conductivity. 
     The first RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The first RDL dielectric layer may, for example, comprise a laminated film or other materials. The first RDL dielectric layer may, for example, generally comprise an organic material. In various example implementations, however, the first RDL dielectric layer may comprise an inorganic material. 
     In an example implementation, the first RDL dielectric layer may comprise an organic material (e.g., polyimide, PBO, etc.) formed on a first side of the base dielectric layer of the RD structure, which may comprise an oxide or nitride or other dielectric material. 
     The first RDL dielectric layer may, for example, be utilized as a mask for etching the base dielectric layer, for example an oxide or nitride layer (e.g., at block  260 ). Also for example, after etching, the first RDL dielectric layer may remain, for example to utilize in forming conductive RDL traces thereon. 
     In an alternative example scenario (not shown), a temporary mask layer (e.g., a temporary photoresist layer) may be utilized. For example, after etching, the temporary mask layer may be removed and replaced by a permanent RDL dielectric layer. 
       FIG.  1 G  provides an example illustration of various aspects of block  255 . For example, the first RDL dielectric layer  171  is formed and patterned on the base dielectric layer  111 . The patterned first RDL dielectric layer  171  may, for example, comprise vias  172  through the first RDL dielectric layer  171 , for example through which the base dielectric layer  111  may be etched (e.g., at block  260 ) and in which first traces (or portions thereof) may be formed (e.g., at block  265 ). 
     In general, block  255  may comprise forming and patterning a first dielectric layer (e.g., a first RDL dielectric layer), for example on the base dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of a particular dielectric layer or by characteristics of a particular manner of forming a dielectric layer. 
     The example method  200  may, at block  260 , comprise etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.), for example unmasked portions thereof, from the RD structure. Block  260  may comprise performing the etching in any of a variety of manners, non-limiting examples of which are presented herein. 
     For example, block  260  may comprise performing a dry etch process (or alternatively a wet etch process) to etch through portions of the base dielectric layer (e.g., oxide, nitride, etc.) exposed by vias through the first dielectric layer, which functions as a mask for the etching. 
       FIG.  1 G  provides an example illustration of various aspects of block  260 , for example dielectric etching aspects. For example, portions of the base dielectric layer  111  that were shown below the first conductive traces  112  in  FIG.  1 F  are removed from  FIG.  1 G . This, for example, enables a metal-to-metal contact between the first conductive traces  112  and first RDL traces formed at block  265 . 
     In general, block  260  may, for example, comprise etching the base dielectric layer. Accordingly, the scope of this disclosure should not be limited by any particular manner of performing such etching. 
     The example method  200  may, at block  265 , comprise forming first redistribution layer (RDL) traces. Block  265  may comprise forming the first RDL traces in any of a variety of manners, non-limiting examples of which are presented herein. 
     As discussed herein, the first RDL dielectric layer (e.g., formed at block  255 ) may be utilized for etching (e.g., at block  260 ) and then remain for formation of the first RDL traces. Alternatively, the first RDL dielectric layer may be formed and patterned after the etching process. In yet another alternative implementation discussed herein, the etching process for the base dielectric layer may be skipped (e.g., in an implementation in which the base dielectric layer (e.g., a thin oxide or nitride layer) is conductive enough to adequately serve as a conductive path between metal traces. 
     Block  265  may comprise forming the first RDL traces attached to the first conductive traces of the RD structure that are exposed through the patterned first RDL dielectric layer. The first RDL traces may also be formed on the first RDL dielectric layer. Block  265  may comprise forming the first RDL traces in any of a variety of manners, for example by plating, but the scope of this disclosure is not limited by the characteristics of any particular manner of forming such traces. 
     The first RDL traces may comprise any of a variety of materials (e.g., copper, gold, nickel, etc.). The first RDL traces may, for example, comprise any of a variety of dimensional characteristics. For example, a typical pitch for the first RDL traces may, for example, be 5 microns. In an example implementation, the first RDL traces may, for example, be formed at a center-to-center pitch that is approximately or at least an order of magnitude greater than a pitch at which various traces of the RD structure of the RD wafer were formed (e.g., at a sub-micron pitch, approximately 0.5 micron pitch, etc.). 
       FIGS.  1 G and  1 H  provide an example illustration of various aspects of block  265 , for example RDL trace forming aspects. For example, a first portion  181  of the first RDL traces may be formed in the vias  172  of the first RDL dielectric layer  171  and contacting the first conductive traces  112  of the RD structure  110  exposed by such vias  172 . Also for example, a second portion  182  of the first RDL traces may be formed on the first RDL dielectric layer  171 . 
     In general, block  265  may comprise forming first redistribution layer (RDL) traces. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular RDL traces or by characteristics of any particular manner of forming such RDL traces. 
     The example method  200  may, at block  270 , comprise forming and patterning a second RDL dielectric layer over the first RDL traces (e.g., formed at block  265 ) and the first RDL dielectric layer (e.g., formed at block  255 ). Block  270  may comprise forming and patterning the second dielectric layer in any of a variety of manners, non-limiting examples of which are presented herein. 
     For example, block  270  may share any or all characteristics with block  255 . The second RDL dielectric layer may, for example, be formed utilizing a same material as the first RDL dielectric layer formed at block  255 . 
     The second RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The second RDL dielectric layer may, for example, generally comprise an organic material. In various example implementations, however, the first RDL dielectric layer may comprise an inorganic material. 
       FIG.  1 H  provides an example illustration of various aspects of block  270 . For example, the second RDL dielectric layer  183  is formed on the first RDL traces  181 ,  182  and on the first RDL dielectric layer  171 . As shown in  FIG.  1 H , vias  184  are formed in the second RDL layer  183  through which conductive contact can be made with the first RDL traces  182  exposed by such vias  184 . 
     In general, block  270  may comprise forming and/or patterning a second RDL dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular dielectric layer or by characteristics of any particular manner of forming a dielectric layer. 
     The example method  200  may, at block  275 , comprise forming second redistribution layer (RDL) traces. Block  275  may comprise forming the second RDL traces in any of a variety of manners, non-limiting examples of which are presented herein. Block  275  may, for example, share any or all characteristics with block  265 . 
     Block  275  may comprise forming the second RDL traces attached to the first RDL traces (e.g., formed at block  265 ) that are exposed through vias in the patterned second RDL dielectric layer (e.g., formed at block  270 ). The second RDL traces may also be formed on the second RDL dielectric layer. Block  275  may comprise forming the second RDL traces in any of a variety of manners, for example by plating, but the scope of this disclosure is not limited by the characteristics of any particular manner. 
     As with the first RDL traces, the second RDL traces may comprise any of a variety of materials (e.g., copper, etc.). Additionally, the second RDL traces may, for example, comprise any of a variety of dimensional characteristics. 
       FIGS.  1 H and  1 I  provide an example illustration of various aspects of block  275 . For example, the second RDL traces  191  may be formed in vias  184  in the second RDL dielectric layer  183  to contact the first RDL traces  181  exposed through such vias  184 . Additionally, the second RDL traces  191  may be formed on the second RDL dielectric layer  183 . 
     In general, block  275  may comprise forming second redistribution layer (RDL) traces. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular RDL traces or by characteristics of any particular manner of forming such RDL traces 
     The example method  200  may, at block  280 , comprise forming and patterning a third RDL dielectric layer over the second RDL traces (e.g., formed at block  275 ) and the second RDL dielectric layer (e.g., formed at block  270 ). Block  280  may comprise forming and patterning the third dielectric layer in any of a variety of manners, non-limiting examples of which are presented herein. 
     For example, block  280  may share any or all characteristics with blocks  270  and  255 . The third RDL dielectric layer may, for example, be formed utilizing a same material as the first RDL dielectric layer formed at block  255  (and/or after etching at block  260  and stripping a temporary mask layer), and/or utilizing a same material as the second RDL dielectric layer formed at block  270 . 
     The third RDL dielectric layer may, for example, comprise a polyimide or a polybenzoxazole (PBO) material. The third RDL dielectric layer may, for example, generally comprise an organic material. In various example implementations, however, the third RDL dielectric layer may comprise an inorganic material. 
       FIG.  1 I  provides an example illustration of various aspects of block  280 . For example, the third RDL layer  185  may be formed on the second RDL traces  191  and on the second RDL layer  183 . As shown in  FIG.  1 I , vias are formed in the third RDL layer  185  through which conductive contact can be made with the second RDL traces  191  exposed by such vias. 
     In general, block  280  may comprise forming and/or patterning a third RDL dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular dielectric layer or by characteristics of any particular manner of forming a dielectric layer. 
     The example method  200  may, at block  285 , comprise forming interconnection structures on the second RDL traces and/or on the third RDL dielectric layer. Block  285  may comprise forming the interconnection structures in any of a variety of manners, non-limiting examples of which are presented herein. 
     Block  285  may, for example, comprise forming an underbump metal on portions of the second RDL traces exposed through vias in the third dielectric layer. Block  285  may then, for example, comprise attaching conductive bumps or balls to the underbump metal. Other interconnection structures may be utilized as well, examples of which are presented herein (e.g., conductive posts or pillars, solder balls, solder bumps, etc.). 
       FIG.  1 I  provides an example illustration of various aspects of block  285 , for example interconnection structure forming aspects. For example, interconnection structures  192  are attached to the second RDL traces  191  through vias formed in the third RDL dielectric layer  185 . Note that although the interconnection structures  192  are illustrated as being smaller than the interconnection structures  121 , this disclosure is not so limited. For example, the interconnection structures  192  may be the same size as the interconnection structures  121  or larger than the interconnection structures  121 . Additionally, the interconnection structures  192  may be the same type of interconnection structure as the interconnections structures  121  or may be a different type. 
     Though the redistribution layer(s) formed at blocks  255 - 285 , which may also be referred to as the frontside redistribution layer (RDL), are generally illustrated in  FIG.  1    in a fan-out assembly (e.g., extending outside of the footprint of the die  125 ,  126 ), they may also be formed in a fan-in assembly, for example in which the interconnection structures  192  do not generally extend outside the footprint of the die  125 ,  126 . Non-limiting examples of such an assembly are presented herein. 
     In general, block  285  may comprise forming interconnection structures, for example on the second RDL traces and/or on the third RDL dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular interconnection structures or by any particular manner of forming interconnection structures. 
     The example method  200  may, at block  290 , comprise debonding (or de-attaching) the wafer support that was attached at block  245 . Block  290  may comprise performing such debonding in any of a variety of manners, non-limiting aspects of which are presented herein. 
     For example, in an example scenario in which the wafer support is adhesively attached, the adhesive may be released (e.g., using heat and/or force). Also for example, chemical release agents may be utilized. In another example scenario in which the wafer support is attached utilizing a vacuum force, the vacuum force may be released. Note that in a scenario involving adhesives or other substances to aid in the wafer support attachment, block  285  may comprise cleaning residue from the electrical assembly and/or from the wafer support after the debonding. 
       FIGS.  1 I and  1 J  provide an example illustration of various aspects of block  290 . For example, the wafer support  150  illustrated in  FIG.  1 I  is removed in  FIG.  1 J . 
     In general, block  290  may comprise debonding the wafer support. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer support or by any particular manner of debonding a wafer support. 
     The example method  200  may, at block  295 , comprise dicing the wafer. Block  295  may comprise dicing the wafer in any of a variety of manners, non-limiting examples of which are presented herein. 
     The discussion herein has generally focused on processing of a single die of the RD wafer. Such focus on a single die of the RD wafer is for illustrative clarity only. It should be understood that all of the process steps discussed herein may be performed on an entire wafer. For example, each of the illustrations provided at  FIGS.  1 A- 1 J  and other figures herein may be replicated tens or hundreds of times on a single wafer. For example, until dicing, there might be no separation between one of the illustrated assemblies and a neighboring assembly of the wafer. 
     Block  295  may, for example, comprise dicing (e.g., mechanical punch-cutting, mechanical saw-cutting, later cutting, soft beam cutting, plasma cutting, etc.) the individual packages from the wafer. The end result of such dicing may, for example, be the package shown in  FIG.  1 J . For example, the dicing may form side surfaces of the package comprising coplanar side surfaces of a plurality of components of the package. For example, side surfaces of any or all of the mold material  130 , the RD structure  110  dielectric layers, the various RDL dielectric layers, underfill  128 , etc., may be coplanar. 
     In general, block  295  may comprise dicing the wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of dicing a wafer. 
       FIGS.  1  and  2    presented various example method aspects and variations thereof. Other example method aspects will now be presented with reference to additional figures. 
     As discussed herein in the discussion of  FIGS.  1  and  2   , block  235  may comprise grinding (or otherwise thinning) the mold material  130  to expose one or more of the die  125 ,  126 . An example is provided at  FIG.  1 D . 
     As also discussed, the mold grinding (or thinning) at block  235  need not be performed or may be performed to an extent that still leaves the tops of the die  125 ,  126  covered with mold material  130 . An example is provided at  FIG.  3   . As shown in  FIG.  3 A , the mold material  130  covers the tops of the semiconductor die  125 ,  126 . Note that the interconnection structures  121  may be shorter or taller than the die  125 ,  126 . Continuing the comparison, rather than the resulting package  100 J appearing as shown in  FIG.  1 J , the resulting package  300 B may appear as shown in  FIG.  3 B . 
     Also, as discussed herein in the discussion of  FIGS.  1  and  2   , block  215 , forming TMV interconnection structures, and block  240 , TMV mold ablation, may be skipped. An example is provided at  FIG.  4   . As shown in  FIG.  4 A , as opposed to block  215  and  FIG.  1 B , there are no TMV interconnection structures  121  formed. As shown in  FIG.  4 B , as opposed to block  230  and  FIG.  1 C , the mold material  130  does not cover interconnection structures. 
     Continuing the comparison, as explained herein, the mold grinding (or thinning) at block  235  may be performed to an extent that exposes one or more of the tops of the die  125 ,  126  from the mold material  130 .  FIG.  4 C  provides an example illustration of such processing. Generally, the  FIG.  4 C  assembly  400 C is similar to the  FIG.  1 J  assembly  100 J, less the interconnection structures  121  and the ablated vias exposing the interconnection structures through the mold material  130 . 
     Also for example, as explained herein, the mold grinding (or thinning) at block  235  may be skipped or performed to an extent that leaves the tops of the die  125 ,  126  covered with mold material  130 .  FIG.  4 D  provides an example illustration of such processing. Generally, the  FIG.  4 D  assembly  400 D is similar to the  FIG.  1 J  assembly  100 J, less the interconnection structures  121  and the ablated vias exposing the interconnection structures through the mold material  130 , and with mold material  130  covering the die  125 ,  126 . 
     In another example, as explained herein in the discussion of block  215 , the TMV interconnections may comprise any of a variety of structures, for example a conductive pillar (e.g., plated post or pillar, vertical wire, etc.).  FIG.  5 A  provides an example illustration of conductive pillars  521  attached to the RD structure  110 . The conductive pillars  521  may, for example, be plated on the RD structure  110 . The conductive pillars  521  may also, for example, comprise wires (e.g., wire-bond wires) attached (e.g., wire-bond attached, soldered, etc.) to the RD structure  110  and extending vertically. The conductive pillars  521  may, for example, extend from the RD structure  110  to a height greater than a height of the die  125 ,  126 , equal to the height of one or more of the die  125 ,  126 , less than a height of the die  125 ,  126 , etc. In an example implementation, the pillars may have a height greater than or equal to 200 microns at a center-to-center pitch of 100-150 microns. Note that any number of rows of the pillars  521  may be formed. Generally, the  FIG.  5 A  assembly  500 A is similar to the  FIG.  1 B  assembly  100 B with conductive pillars  521  as interconnection structures instead of conductive balls  121 . 
     Continuing the example,  FIG.  5 B  illustrates the RD structure  110 , conductive pillars  521 , semiconductor die  125 ,  126 , and underfill  128  covered with mold material  130 . The molding may, for example, be performed in accordance with block  230  of the example method  200 . Generally, the  FIG.  5 B  assembly  500 B is similar to the  FIG.  1 C  assembly  100 C with conductive pillars  521  as interconnection structures instead of conductive balls  121 . 
     Still continuing the example,  FIG.  5 C  illustrates the mold material  130  having been thinned (e.g., ground) to a desired thickness. The thinning may, for example, be performed in accordance with block  235  of the example method  200 . Note, for example, that the conductive pillars  521  and/or the semiconductor die  125 ,  126  may also be thinned. Generally, the  FIG.  5 D  assembly  500 D is similar to the  FIG.  1 D  assembly  100 D with conductive pillars  521  as interconnection structures instead of conductive balls  121 , and also without the ablated vias  140  of  FIG.  1 D . For example, the thinning of the mold material  130  may expose the top ends of the conductive pillars  521 . If instead, however, the thinning of the mold material  130  does not expose the top ends of the conductive pillars  521 , a mold ablating operation (e.g., in accordance with block  240 ) may be performed. Note that although the assembly is shown with the tops of the semiconductor die  125 ,  126  being exposed, the tops need not be exposed. For example, the pillars  521  may stand taller than the semiconductor die  125 ,  126 . Such an example configuration may, for example allow the pillars  521  to be exposed from and/or protrude from the mold material  130  while the mold material  130  continues to cover the backside surfaces of the semiconductor die  125 ,  126 , which may, for example, provide protection for the semiconductor die  125 ,  126 , prevent or reduce warpage, etc. 
     In an example implementation in which the pillars  521  are formed with a height less than the die  125 ,  126 , the thinning may comprise first grinding the mold material  130 , then grinding both the mold material  130  and the back (or inactive) sides of the die  125 ,  126  until the pillars  521  are exposed. At this point, the thinning may be stopped or may be continued, for example grinding the mold material  130 , the die  125 ,  126  and the pillars  521 . 
     Continuing the example, the assembly  500 C shown in  FIG.  5 C  may be further processed by forming a redistribution layer (RDL)  532  over the mold material  130  and die  125 ,  126 .  FIG.  5 D  shows an example of such processing. The redistribution layer  532  may also be referred to herein as the backside redistribution (RDL) layer  532 . Though such backside RDL formation is not explicitly shown in one of the blocks of the example method  200 , such operation may be performed in any of the blocks, for example after the block  235  mold grinding operation and before the block  245  wafer support attaching (e.g., at block  235 , at block  240 , at block  245 , or between any of such blocks). 
     As shown in  FIG.  5 D , a first backside dielectric layer  533  may be formed and patterned on the mold material  130  and the die  125 ,  126 . The first backside dielectric layer  533  may, for example, be formed and patterned in a same or similar manner to the first RDL dielectric layer  171  formed at block  260 , albeit on a different surface. For example, the first backside dielectric layer  533  may be formed on the mold material  130  and on the semiconductor die  125 ,  126  (e.g., directly on exposed backside surfaces of the die  125 ,  126 , on mold material  130  covering the backside surfaces of the die  125 ,  126 , etc.), and vias  534  may be formed (e.g., by etching, ablating, etc.) in the first backside dielectric layer  533  to expose at least the tops of the conductive pillars  521 . Note that in an example configuration in which the mold material  130  covers the backside surfaces of the semiconductor die  125 ,  126 , the first backside dielectric layer  533  may still be formed, but need not be (e.g., the backside traces  535  discussed below may be formed directly on the mold material  130  rather than on the first backside dielectric layer  533 ). 
     Backside traces  535  may be formed on the first backside dielectric layer  533  and in the vias  534  of the first backside dielectric layer  533 . The backside traces  535  may thus be electrically connected to the conductive pillars  521 . The backside traces  535  may, for example, be formed in a same or similar manner to the first RDL traces formed at block  265 . At least some, if not all, of the backside traces  535  may, for example, extend horizontally from the conductive pillars  521  to locations directly above the semiconductor die  125 ,  126 . At least some of the backside traces  535  may also, for example, extend from the conductive pillars  521  to locations that are not directly above the semiconductor die  125 ,  126 . 
     A second backside dielectric layer  536  may be formed and patterned on the first backside dielectric layer  533  and backside traces  535 . The second backside dielectric layer  536  may, for example, be formed and patterned in a same or similar manner to the second RDL dielectric layer  183  formed at block  270 , albeit on a different surface. For example, the second backside dielectric layer  536  may be formed over the first backside dielectric layer  533  and over the backside traces  535  and vias  537  may be formed (e.g., by etching, ablating, etc.) in the second backside dielectric layer  536  to expose contact areas of the backside traces  535 . 
     Backside interconnection pads  538  (e.g., ball contact pads) may be formed on the second backside dielectric layer  536  and/or in the vias  537  of the second backside dielectric layer  536 . The backside interconnection pads  538  may thus be electrically connected to the backside traces  535 . The backside interconnection pads  538  may, for example, be formed in a same or similar manner to the second RDL traces formed at block  275 . The backside interconnection pads  538  may, for example, be formed by forming metal contact pads and/or forming under bump metallization (e.g., to enhance subsequent attachment to the backside traces  535  by interconnection structures). 
     Though the backside RDL layer  532  is shown with two backside dielectric layers  533 ,  536  and one layer of backside traces  535 , it should be understood that any number of dielectric and/or trace layers may be formed. 
     As shown by example in  FIG.  5 E , after the backside RDL layer  532  is formed, a wafer support structure  150  may be attached to the backside RDL layer  532  (e.g., directly, with an intervening adhesive layer, utilizing vacuum force, etc.). The wafer support  150  may, for example, be attached in a same or similar manner to the wafer support  150  attached at block  245 . For example,  FIG.  5 E  shows the wafer support  150  attachment in a manner similar to that of  FIG.  1 E , albeit with attachment to the RDL layer  532  rather than attachment to the mold layer  130  and semiconductor die  125 ,  126 . 
     As illustrated by example in  FIG.  5 F , the support layer  105  (shown in  FIG.  5 E ) may be removed from the RD wafer, a frontside redistribution layer may be formed on a side of the RD structure  110  opposite the die  125 ,  126 , interconnection structures  192  may be formed, and the wafer support  150  may be removed. 
     For example, the support layer  105  may be removed in a same or similar manner to that discussed herein with regard to block  250  and  FIGS.  1 E- 1 F . Also for example, a frontside redistribution layer may be formed in a same or similar manner to that discussed herein with regard to blocks  255 - 280  and  FIGS.  1 G- 1 H . Additionally for example, interconnection structures  192  may be formed in a same or similar manner to that discussed herein with regard to block  285  and  FIG.  1 I . Further for example, the wafer support  150  may be removed in a same or similar manner to that discussed herein with regard to block  290  and  FIG.  1 J . 
     In another example implementation, a substrate (e.g., a laminate substrate, package substrate, etc.) may be attached above the semiconductor die  125 ,  126 , for example instead of or in addition to the backside RDL discussed herein with regard to  FIG.  5   . For example, as illustrated in  FIG.  6 A , the interconnection structures  621  may be formed at a height that will extend to the height of the die  125 ,  126 . Note that this height is not necessarily present, for example in a scenario in which the backside substrate has its own interconnection structures or in which additional interconnection structures are utilized between the interconnection structures  621  and the backside substrate. The interconnection structures  621  may, for example, be attached in a same or similar manner as that discussed herein with regard to block  215  and  FIG.  1 B . 
     Continuing the example, as illustrated in  FIG.  6 B , the assembly  600 B may be molded and the mold may be thinned if necessary. Such molding and/or thinning may, for example, be performed in a same or similar manner to that discussed herein with regard to blocks  230  and  235 , and  FIGS.  1 C and  1 D . 
     As shown in  FIG.  6 C , a wafer support  150  may be attached, support layer  105  may be removed, and a front side RDL may be formed. For example, a wafer support  150  may be attached in a same or similar manner as that discussed herein with regard to block  245  and  FIG.  1 E . Also for example, support layer  105  may be removed in a same or similar manner as that discussed herein with regard to block  250  and  FIG.  1 F . Additionally for example, a frontside RDL may be formed in a same or similar manner as that discussed herein with regard to blocks  255 - 280  and  FIGS.  1 G- 1 H . 
     As illustrated in  FIG.  6 D , interconnection structures  192  may be attached, the wafer support  150  may be removed, and the backside substrate  632  may be attached. For example, the interconnection structures  192  may be attached in a same or similar manner as that discussed herein with regard to block  285  and  FIG.  1 I . Also for example, the wafer support  150  may be removed in a same or similar manner as that discussed herein with regard to block  290  and  FIG.  1 J . Further for example, the backside substrate  632  may be electrically attached to the interconnection structures  621  and/or mechanically attached to the mold material  130  and/or the die  125 ,  126 . The backside substrate  632  may, for example, be attached in wafer (or panel) form and/or single package form, and may for example be attached before or after dicing (e.g., as discussed at block  295 ). 
     The example methods and assemblies shown in  FIGS.  1 - 7    and discussed herein are merely non-limiting examples presented to illustrate various aspects of this disclosure. Such methods and assemblies may also share any or all characteristics with the methods and assemblies shown and discussed in the following co-pending United States patent applications: U.S. patent application Ser. No. 13/753,120, filed Jan. 29, 2013, and titled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE”; U.S. patent application Ser. No. 13/863,457, filed on Apr. 16, 2013, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/083,779, filed on Nov. 19, 2013, and titled “SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIA-LESS DEEP WELLS”; U.S. patent application Ser. No. 14/218,265, filed Mar. 18, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/313,724, filed Jun. 24, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/444,450, Jul. 28, 2014, and titled “SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS”; U.S. patent application Ser. No. 14/524,443, filed Oct. 27, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS”; U.S. patent application Ser. No. 14/532,532, filed Nov. 4, 2014, and titled “INTERPOSER, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE”; U.S. patent application Ser. No. 14/546,484, filed Nov. 18, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE”; and U.S. patent application Ser. No. 14/671,095, filed Mar. 27, 2015, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF;” the contents of each of which are hereby incorporated herein by reference in their entirety. 
     It should be noted that any or all of the semiconductor packages discussed herein may be, but need not be, attached to a package substrate. Various non-limiting examples of such semiconductor device packages and methods of manufacturing thereof will now be discussed. 
       FIGS.  7 A- 7 L  show cross-sectional views illustrating an example semiconductor package and an example method of making a semiconductor package, in accordance with various aspects of the present disclosure. The structures shown in  7 A- 7 L may, for example, share any or all characteristics with analogous structures shown in  FIGS.  1 A- 1 J,  3 A- 3 B,  4 A- 4 D,  5 A- 5 F,  6 A- 6 D,  9 ,  10 A- 10 B,  11 A- 11 D,  12 A- 12 B,  13 , and  14   .  FIG.  8    is a flow diagram of an example method  800  of making a semiconductor package, in accordance with various aspects of the present disclosure. The example method  800  may, for example, share any or all characteristics with the example method  200  illustrated in  FIG.  2    and discussed herein and with any methods discussed herein.  FIGS.  7 A- 7 L  may, for example, illustrate an example semiconductor package at various steps (or blocks) of the production method  800  of  FIG.  8   .  FIGS.  7 A- 7 L  and  FIG.  8    will now be discussed together. 
     The example method  800  may, at block  805 , comprise preparing a logic wafer for processing (e.g., for packaging). Block  805  may comprise preparing a logic wafer for processing in any of a variety of manners, non-limiting examples of which are presented herein. Block  805  may, for example, share any or all characteristics with block  205  of the example method  200  shown in  FIG.  2    and discussed herein. 
     The example method  800  may, at block  810 , comprise preparing a redistribution structure wafer (RD wafer). Block  810  may comprise preparing an RD wafer for processing in any of a variety of manners, non-limiting examples of which are provided herein. Block  810  may, for example, share any or all characteristics with block  210  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 A  provides an example illustration of various aspects of block  810 . Referring to  FIG.  7 A , the RD wafer  700 A may, for example, comprise a support layer  705  (e.g., a silicon layer). A redistribution (RD) structure  710  may be formed on the support layer  105 . The RD structure  710  may, for example, comprise a base dielectric layer  711 , a first dielectric layer  713 , first conductive traces  712 , a second dielectric layer  716 , second conductive traces  715 , and interconnection structures  717 . 
     The base dielectric layer  711  may, for example, be on the support layer  705 . The base dielectric layer  711  may, for example, comprise an oxide layer, a nitride layer, etc. The base dielectric layer  711  may, for example, be formed to specification and/or may be native. 
     The RD wafer  700 A may also, for example, comprise first conductive traces  712  and a first dielectric layer  713 . The first conductive traces  712  may, for example, comprise deposited conductive metal (e.g., copper, etc.). The first dielectric layer  713  may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the first dielectric layer  713  may comprise an organic dielectric material. 
     The RD wafer  700 A may also, for example, comprise second conductive traces  715  and a second dielectric layer  716 . The second conductive traces  715  may, for example, comprise deposited conductive metal (e.g., copper, etc.). The second conductive traces  715  may, for example, be connected to respective first conductive traces  712  through respective conductive vias  714  (e.g., in the first dielectric layer  713 ). The second dielectric layer  716  may, for example, comprise an inorganic dielectric material (e.g., silicon oxide, silicon nitride, etc.). In an alternative assembly, the second dielectric layer  716  may comprise an organic dielectric material. 
     Though two sets of dielectric layers and conductive traces are illustrated in  FIG.  7 A , it should be understood that the RD structure  710  of the RD wafer  700 A may comprise any number of such layers and traces. For example, the RD structure  710  might comprise only one dielectric layer and/or set of conductive traces, three sets of dielectric layers and/or conductive traces, etc. 
     As with the logic wafer prep at block  205 , block  210  may comprise forming interconnection structures (e.g., conductive bumps, conductive balls, conductive pillars, conductive lands or pads, etc.) on a surface of the RD structure  710 . Examples of such interconnection structures  717  are shown in  FIG.  7 A , in which the RD structure  710  comprises interconnection structures  717 , which are shown formed on the front (or top) side of the RD structure  710  and electrically connected to respective second conductive traces  715  through conductive vias in the second dielectric layer  716 . Such interconnection structures  717  may, for example, be utilized to couple the RD structure  710  to various electronic components (e.g., active semiconductor components or die, passive components, etc.). 
     The interconnection structures  717  may, for example, comprise any of a variety of conductive materials (e.g., any one of or a combination of copper, nickel, gold, etc.). The interconnection structures  717  may also, for example, comprise solder. 
     In general, block  810  may comprise preparing a redistribution structure wafer (RD wafer). Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of performing such preparing. 
     The example method  800  may, at block  820 , comprise attaching one or more semiconductor die to the RD structure (e.g., of the RD wafer). Block  820  may comprise attaching the die to the RD structure in any of a variety of manners, non-limiting examples of which are provided herein. Block  820  may, for example, share any or all characteristics with block  220  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 B  provides an example illustration of various aspects of block  820 , for example the die attachment. For example, the first die  725  (e.g., which may have been diced from a logic wafer prepared at block  805 ) is electrically and mechanically attached to the redistribution structure  710 . Similarly, the second die  726  (e.g., which may have been diced from a logic wafer prepared at block  805 ) is electrically and mechanically attached to the redistribution structure  710 . 
     The first die  725  and the second die  726  may comprise any of a variety of die characteristics. In an example scenario, the first die  725  may comprise a processor die and the second die  726  may comprise a memory die. In another example scenario, the first die  725  may comprise a processor die, and the second die  726  may comprise a co-processor die. In another example scenario, the first die  725  may comprise a sensor die, and the second die  726  may comprise a sensor processing die. Though the assembly  700 B at  FIG.  7 B  is shown with two die  725 ,  726 , there may be any number of die. For example, there might be only one die, three die, four die, or more than four die. 
     Additionally, though the first die  725  and the second die  726  are shown attached to the redistribution structure  710  laterally relative to each other, they may also be arranged in a vertical assembly. Various non-limiting example assemblies of such structures are shown and discussed herein (e.g., die-on-die stacking, die attach to opposite substrate side, etc.). Also, though the first die  725  and the second die  726  are shown with generally similar dimensions, such die  725 ,  726  may comprise different respective characteristics (e.g., die height, footprint, connection pitch, etc.). 
     The first die  725  and the second die  726  are illustrated with generally consistent pitch, but this need not be the case. For example, most or all of the contacts of the first die  725  in a region of the first die footprint immediately adjacent to the second die  726  and/or most of the contacts of the second die  726  in a region of the second die footprint immediately adjacent to the first die  725  may have substantially finer pitch than most or all of the other contacts. For example, a first 5, 10, or n rows of contacts of the first die  725  closest to the second die  726  (and/or of the second die  726  closest to the first die  725 ) may have a 30 micron pitch, while other contacts may generally have an 80 micron and/or 200 micron pitch. The RD structure  710  may thus have corresponding contact structures and/or traces at the corresponding pitch. 
     In general, block  820  comprises attaching one or more semiconductor die to the redistribution structure (e.g., of a redistribution wafer). Accordingly, the scope of this disclosure should not be limited by characteristics of any particular die or by characteristics of any particular multi-die layout, or by characteristics of any particular manner of attaching such die, etc. 
     The example method  800  may, at block  825 , comprise underfilling the semiconductor die and/or other components attached to the RD structure at block  820 . Block  825  may comprise performing such underfilling in any of a variety of manners, non-limiting examples of which are presented herein. Block  825  may, for example, share any or all characteristics with block  225  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 B  provides an example illustration of various aspects of block  825 , for example the underfilling. The underfill  728  is positioned between the first semiconductor die  725  and the redistribution structure  710  and between the second semiconductor die  726  and the redistribution structure  710 . 
     Though the underfill  728  is generally illustrated to be flat, the underfill may rise up and form fillets on the sides of the semiconductor die and/or other components. In an example scenario, at least a fourth or at least a half of the die side surfaces may be covered by the underfill material. In another example scenario, one or more or all of the entire side surfaces may be covered by the underfill material. Also for example, a substantial portion of the space directly between the semiconductor die, between the semiconductor die and other components, and/or between other components may be filled with the underfill material. For example, at least half of the space or all of the space between laterally adjacent semiconductor die, between the semiconductor die and other components, and/or between other components may be filled with the underfill material. In an example implementation, the underfill  728  may cover the entire redistribution structure  710  of the RD wafer. In such example implementation, when the RD wafer is later diced, such dicing may also cut through the underfill  728 . 
     In general, block  825  may comprise underfilling the semiconductor die and/or other components attached to the RD structure at block  820 . Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of underfill or of any particular manner of performing such underfilling. 
     The example method  800  may, at block  830 , comprise molding the RD wafer (or RD structure). Block  830  may comprise molding the RD wafer in any of a variety of manners, non-limiting examples of which are presented herein. Block  830  may, for example, share any or all characteristics with block  230  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 C  provides an example illustration of various aspects of block  830 , for example molding aspects. For example, the molded assembly  700 C is shown with the mold material  730  covering the first semiconductor die  725 , second semiconductor die  726 , underfill  728 , and the top surface of the redistribution structure  710 . Though the mold material  730 , which may also be referred to herein as encapsulant, is shown completely covering the sides and tops of the first semiconductor die  725  and second semiconductor die  726 , this need not be the case. For example, block  830  may comprise utilizing a film assist or die seal molding technique to keep the die tops free of mold material. 
     The mold material  730  may generally, for example, directly contact and cover portions of the die  725 ,  726  that are not covered by the underfill  728 . For example in a scenario in which at least a first portion of the sides of the die  725 ,  726  is covered by underfill  728 , the mold material  730  may directly contact and cover a second portion of the sides of the die  725 ,  726 . The mold material  730  may also, for example, fill the space between the die  725 ,  726  (e.g., at least a portion of the space that is not already filled with underfill  728 ). 
     In general, block  830  may comprise molding the RD wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular molding material, structure and/or technique. 
     The example method  800  may, at block  835 , comprise grinding (or otherwise thinning) the mold material applied at block  830 . Block  835  may comprise grinding (or thinning) the mold material in any of a variety of manners, non-limiting examples of which are presented herein. Block  835  may, for example, share any or all characteristics with block  235  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 D  provides an example illustration of various aspects of block  835 , for example the mold grinding aspects. The assembly  700 D is illustrated with the mold material  730  (e.g., relative to the mold material  730  illustrated at  FIG.  7 C ) thinned to reveal top surfaces of the die  725 ,  726 . In such an example, the die  725 ,  726  may also have been ground (or otherwise thinned). 
     As explained herein, the mold material  730  may be left covering the die  725 ,  726  in an overmold assembly. For example, the mold material  730  might not be ground, or the mold material  730  might be ground but not to a height that exposes the die  725 ,  726 . 
     In general, block  835  may comprise grinding (or otherwise thinning) the mold material applied at block  830 . Accordingly, the scope of this disclosure should not be limited by characteristics of any particular amount or type of grinding (or thinning). 
     The example method  800  may, at block  845 , comprise attaching the molded RD wafer (e.g., the top or mold side thereof) to a wafer support structure. Block  845  may comprise attaching the molded RD wafer to the wafer support structure in any of a variety of manners, non-limiting examples of which are provided herein. Block  845  may, for example, share any or all characteristics with block  245  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 E  provides an example illustration of various aspects of block  845 , for example wafer support attaching aspects. The wafer support structure  750  is attached to the top side of the mold material  730  and die  725 ,  726 . The wafer support structure  750  may, for example, be attached with an adhesive. Note that in an assembly in which the tops of the die  725 ,  726  are covered with the mold material  730 , the wafer support structure  750  might only be directly coupled to the top of the mold material  730 . 
     In general, block  845  may comprise attaching the molded RD wafer (e.g., the top or mold side thereof) to a wafer support structure. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer support structure or by characteristics of any particular manner of attaching a wafer support structure. 
     The example method  200  may, at block  850 , comprise removing a support layer from the RD wafer. Block  850  may comprise removing the support layer in any of a variety of manners, non-limiting examples of which are presented herein. Block  850  may, for example, share any or all characteristics with block  250  of the example method  200  shown in  FIG.  2    and discussed herein. 
     As discussed herein, the RD wafer may comprise a support layer on which an RD structure is formed and/or carried. The support layer may, for example, comprise a semiconductor material (e.g., silicon). In an example scenario in which the support layer comprises a silicon wafer layer, block  850  may comprise removing the silicon (e.g., removing all of the silicon from the RD wafer, removing almost all of the silicon, for example at least 90% or 95%, from the RD wafer, etc.). For example, block  850  may comprise mechanically grinding almost all of the silicon, followed by a dry or wet chemical etch to remove the remainder (or almost all of the remainder). In an example scenario in which the support layer is loosely attached to the RD structure formed (or carried) thereon, block  850  may comprise pulling or peeling to separate the support layer from the RD structure. 
       FIG.  7 F  provides an example illustration of various aspects of block  850 , for example support layer removing aspects. For example, the support layer  705  (shown in  FIG.  7 E ) is removed from the RD structure  710 . In the illustrated example, the RD structure  710  may still comprise abase dielectric layer  711  (e.g., an oxide, nitride, etc.) as discussed herein. 
     In general, block  850  may comprise removing a support layer from the RD wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer material or by characteristics of any particular manner of wafer material removal. 
     The example method  800  may, at block  855 , comprise forming and patterning a redistribution layer (RDL) dielectric layer for etching an oxide layer of the RD structure. Block  855  may comprise forming and patterning the RDL dielectric layer in any of a variety of manners, non-limiting examples of which are presented herein. Block  855  may, for example, share any or all characteristics with block  255  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 G  provides an example illustration of various aspects of block  855 . For example, the RDL dielectric layer  771  is formed and patterned on the base dielectric layer  711 . The patterned RDL dielectric layer  771  may, for example, comprise vias  772  through the RDL dielectric layer  771 , for example through which the base dielectric layer  711  may be etched (e.g., at block  860 ) and in which conductive traces (or portions thereof) may be formed (e.g., at block  865 ). 
     In general, block  855  may comprise forming and patterning a dielectric layer (e.g., an RDL dielectric layer), for example on the base dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of a particular dielectric layer or by characteristics of a particular manner of forming a dielectric layer. 
     The example method  800  may, at block  860 , comprise etching the base dielectric layer (e.g., oxide layer, nitride layer, etc.), for example unmasked portions thereof, from the RD structure. Block  860  may comprise performing the etching in any of a variety of manners, non-limiting examples of which are presented herein. Block  860  may, for example, share any or all characteristics with block  260  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIG.  7 G  provides an example illustration of various aspects of block  860 . For example, portions of the base dielectric layer  711  that were shown below the first conductive traces  712  in  FIG.  7 F  are removed from  FIG.  7 G . This, for example, enables a metal-to-metal contact between the first conductive traces  712  and the RDL traces formed at block  865 . 
     In general, block  860  may, for example, comprise etching the base dielectric layer. Accordingly, the scope of this disclosure should not be limited by any particular manner of performing such etching. 
     The example method  800  may, at block  865 , comprise forming redistribution layer (RDL) traces. Block  865  may comprise forming the RDL traces in any of a variety of manners, non-limiting examples of which are presented herein. Block  865  may, for example, share any or all characteristics with block  265  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIGS.  7 G and  7 H  provide an example illustration of various aspects of block  865 , for example RDL trace forming aspects. For example, a first portion  781  of the RDL traces may be formed in the vias  772  of the RDL dielectric layer  771  and contacting the first conductive traces  712  of the RD structure  710  exposed by such vias  772 . Also for example, a second portion  782  of the first RDL traces may be formed on the first RDL dielectric layer  771 . 
     In general, block  865  may comprise forming redistribution layer (RDL) traces. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular RDL traces or by characteristics of any particular manner of forming such RDL traces. 
     Note that although the example method  800 , shows the formation of only one RDL dielectric layer at  855  and one RDL trace layer at block  865 , such blocks may be repeated as many times as desired. 
     The example method  800  may, at block  885 , comprise forming interconnection structures on the RDL traces. Block  885  may comprise forming the interconnection structures in any of a variety of manners, non-limiting examples of which are presented herein. For example, block  885  may share any or all characteristics with block  285  of the example method  200  shown in  FIG.  2    and discussed herein. 
     Block  885  may, for example, comprise forming conductive pillars (e.g., metal pillars, copper pillars, solder-capped pillars, etc.) and/or conductive bumps (e.g., solder bumps, etc.) on the RDL traces. For example, block  885  may comprise plating conductive pillars, placing or pasting conductive bumps, etc. 
       FIG.  7 I  provides an example illustration of various aspects of block  885 , for example bump forming aspects. For example, interconnection structures  792  (e.g., shown as solder-capped metal pillars, for example copper pillars) are attached to the RDL traces  782 . 
     Though the redistribution layer(s) formed at blocks  855 - 885 , which may also be referred to as the frontside redistribution layer (RDL), are generally illustrated in  FIG.  7    in a fan-in assembly (e.g., generally contained within the footprint of the die  725 ,  726 ), they may also be formed in a fan-out assembly, for example in which at least a portion the interconnection structures  792  generally extend outside the footprint of the die  125 ,  126 . Non-limiting examples of such an assembly are presented herein. 
     In general, block  885  may comprise forming interconnection structures, for example on the RDL traces and/or on the RDL dielectric layer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular interconnection structures or by any particular manner of forming interconnection structures. 
     The example method  800  may, at block  890 , comprise debonding (or de-attaching) the wafer support that was attached at block  845 . Block  890  may comprise performing such debonding in any of a variety of manners, non-limiting examples of which are presented herein. For example, block  890  may share any or all characteristics with block  290  of the example method  200  shown in  FIG.  2    and discussed herein. 
       FIGS.  7 H and  7 I  provide an example illustration of various aspects of block  890 . For example, the wafer support  750  illustrated in  FIG.  7 H  is removed in  FIG.  7 I . 
     In general, block  890  may comprise debonding the wafer support. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of wafer support or by any particular manner of debonding a wafer support. 
     The example method  800  may, at block  895 , comprise dicing the wafer. Block  895  may comprise dicing the wafer in any of a variety of manners, non-limiting examples of which are presented herein. Block  895  may, for example, share any or all characteristics with block  295  of the example method  200  shown at  FIG.  2    and discussed herein. 
     The discussion herein has generally focused on discussing processing of a single die of the RD wafer. Such focus on a single die of the RD wafer is for illustrative clarity only. It should be understood that all of the process steps (or blocks) discussed herein may be performed on an entire wafer. For example, each of the illustrations provided at  FIGS.  7 A- 7 L  and other figures herein may be replicated tens or hundreds of times on a single wafer. For example, until dicing, there might be no separation between one of the illustrated device assemblies and a neighboring device assembly of the wafer. 
     Block  895  may, for example, comprise dicing (e.g., mechanical punch-cutting, mechanical saw-cutting, later cutting, soft beam cutting, plasma cutting, etc.) the individual packages from the wafer. The end result of such dicing may, for example, be the package shown in  FIG.  7   . For example, the dicing may form side surfaces of the package comprising coplanar side surfaces of a plurality of components of the package. For example, any or all of side surfaces of the mold material  730 , the RD structure  710  dielectric layers, the RDL dielectric layer  771 , underfill  728 , etc., may be coplanar. 
     In general, block  895  may comprise dicing the wafer. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular manner of dicing a wafer. 
     The example method  800  may, at block  896 , comprise preparing a substrate, or wafer or panel thereof, for attachment of the assembly  700 I thereto. Block  896  may comprise preparing a substrate in any of a variety of manners, non-limiting examples of which are presented herein. Block  896  may, for example, share any or all aspects with blocks  205  and  210  of the example method  200  shown in  FIG.  2    and discussed herein. 
     The substrate may, for example, comprise characteristics of any of a variety of substrates. For example, the substrate may comprise a package substrate, motherboard substrate, laminate substrate, molded substrate, semiconductor substrate, glass substrate, etc.). Block  896  may, for example, comprise preparing front side and/or backside surfaces of the substrate for electrical and/or mechanical attachment. Block  896  may, for example, leave a panel of substrates in a panel form at this stage and excise individual packages later, or may excise individual substrates from a panel at this stage. 
     Block  896  may also comprise receiving the substrate from an adjacent or upstream manufacturing station at a manufacturing facility, from another geographical location, etc. The substrate may, for example, be received already prepared or additional preparation steps may be performed. 
       FIG.  7 J  provides an example illustration of various aspects of block  896 . For example, the assembly  700 J includes an example substrate  793  that was prepared for attachment. 
     In general, block  896  may comprise preparing a substrate, or wafer or panel thereof, for attachment of the assembly  700 I thereto. Accordingly, the scope of various aspects of this disclosure should not be limited by characteristics of particular substrates or by characteristics of any particular manner of preparing a substrate. 
     The example method  800  may, at block  897 , comprise attaching an assembly to the substrate. Block  897  may comprise attaching an assembly (e.g., an assembly  700 I as exemplified at  FIG.  7 I  or other assembly) in any of a variety of manners, non-limiting examples of which are presented herein. Block  897  may, for example, share any or all characteristics with block  220  of the example method  200  shown in  FIG.  2    and discussed herein. 
     The assembly may comprise characteristics of any of a variety of assemblies, non-limiting examples of which are presented herein, for example in all of the figures and/or related discussions herein. Block  897  may comprise attaching the assembly in any of a variety of manners. For example, block  897  may comprise attaching the assembly to the substrate utilizing mass reflow, thermocompression bonding (TCB), conductive epoxy, etc. 
       FIG.  7 J  provides an example illustration of various aspects of block  897 , for example assembly attachment aspects. For example, the assembly  700 I shown at  FIG.  7 I  is attached to the substrate  793 . 
     Though not shown in  FIG.  7 J , in various example implementations (e.g., as shown in  FIGS.  7 K and  7 L ), interconnection structures, for example through mold interconnection structures, may be formed on the substrate  793 . In such example implementations, block  897  may share any or all characteristics with block  215  of the example method  200  shown in  FIG.  2    and discussed herein, albeit with regard to forming the interconnection structures on the substrate  793 . Note that such interconnection structures may be performed before or after the assembly attachment, or may also be performed before or after the underfilling at block  898 . 
     In general, block  897  comprises attaching an assembly to the substrate. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular assembly, substrate, or manner of attaching an assembly to a substrate. 
     The example method  800  may, at block  898 , comprise underfilling the assembly on the substrate. Block  898  may comprise any of a variety of manners of underfilling, non-limiting examples of which are presented herein. Block  898  may, for example, share any or all characteristics with block  825  and/or with block  225  of the example method  200  shown in  FIG.  2    and discussed herein. 
     For example, after assembly attachment at block  897 , block  898  may comprise underfilling the attached assembly utilizing a capillary underfill. For example, the underfill may comprise a reinforced polymer material viscous enough to flow between the assembly and the substrate in a capillary action. 
     Also for example, block  897  may comprise underfilling the semiconductor die utilizing a non-conductive paste (NCP) and/or a non-conductive film (NCF) or tape while the assembly is being attached at block  897  (e.g., utilizing a thermocompression bonding process). For example, such underfill materials may be deposited (e.g., printed, sprayed, etc.) prior to attaching the assembly. 
     As with all of the blocks illustrated in the example method  800 , block  898  may be performed at any location in the method  8900  flow so long as the space between the assembly and the substrate is accessible. 
     The underfilling may also occur at a different block of the example method  800 . For example, the underfilling may be performed as part of the substrate molding block  899  (e.g., utilizing a molded underfill). 
       FIG.  7 K  provides an example illustration of various aspects of block  898 , for example the underfilling aspects. The underfill  794  is positioned between the assembly  700 I and the substrate  793 . 
     Though the underfill  794  is generally illustrated to be flat, the underfill may rise up and form fillets on the sides of the assembly  700  and/or other components. In an example scenario, at least a fourth or at least a half of the assembly  700  side surfaces may be covered by the underfill material. In another example scenario, one or more or all of the entire side surfaces of the assembly  700 I may be covered by the underfill material. Also for example, a substantial portion of the space directly between the assembly  700 I and other components and/or between other components (shown in various figures) may be filled with the underfill material  794 . For example, at least half of the space or all of the space between the assembly  700 I and a laterally adjacent component may be filled with the underfill material. 
     As shown in  FIG.  7 J , the assembly  700 J may comprise a first underfill  728  between the die  725 ,  726  and the RD structure  710 , and a second underfill  794  between the RD structure  710  and the substrate  793 . Such underfills  728 ,  794  may, for example, be different. For example, in an example scenario in which the distance between the die  725 ,  726  and the RD structure  710  is less than the distance between the RD structure  710  and the substrate  793 , the first underfill  728  may generally comprise a smaller filler size (or have higher viscosity) than the second underfill  794 . In other words, the second underfill  794  may be less expensive than the first underfill  728 . 
     Also, the respective underfilling processes performed at block  898  and  825  may be different. For example, block  825  may comprise utilize a capillary underfill procedure, while block  898  may comprise utilizing a non-conductive paste (NCP) underfill procedure. 
     In another example, blocks  825  and  898  may comprise being performed simultaneously in a same underfilling process, for example after block  897 . Additionally, as discussed herein, a molded underfill may also be utilized. In such an example scenario, block  899  may comprise performing the underfilling of either or both of blocks  825  and/or  898  during the substrate molding process. For example, block  825  may comprise performing a capillary underfill, while block  898  is performed at block  899  as a mold underfill process. 
     In general, block  898  may comprise underfilling the assembly and/or other components attached to the substrate at block  897 . Accordingly, the scope of this disclosure should not be limited by characteristics of any particular type of underfill nor of any particular manner of performing underfilling. 
     The example method  800  may, at block  899 , comprise molding the substrate. Block  899  may comprise performing such molding in any of a variety of manners, non-limiting examples of which are presented herein. Block  899  may, for example, share any or all characteristics with block  830  and/or block  230  of the example method  200  shown in  FIG.  2    and discussed herein. 
     For example, block  899  may comprise molding over the top surface of the substrate, over the assembly attached at block  897 , over TMV interconnection structures if formed on the substrate (e.g., conductive balls, ellipsoids, columns or pillars (e.g., plated pillars, wires or wirebond wires, etc.), etc.). 
     Block  899  may, for example, comprise utilizing transfer molding, compression molding, etc. Block  899  may, for example, comprise utilizing a panel-molding process in which a plurality of the substrates are connected in a panel and molded together, or block  899  may comprise molding the substrate individually. In a panel-molding scenario, after the panel molding, block  899  may comprise performing an excising process in which individual substrates are separated from the substrate panel. 
     The molding material may, for example, comprise any of a variety of characteristics. For example, the molding material (e.g., epoxy mold compound (EMC), epoxy resin molding compound, etc.) may comprise a relatively high modulus, for example to provide package support in a subsequent process. Also for example, the molding material may comprise a relatively low modulus, to provide package flexibility in a subsequent process. 
     Block  899  may, for example, comprise utilizing a mold material that is different from the mold material utilized at block  830 . For example, block  899  may utilize a mold material with a lower modulus than the mold material utilized at block  830 . In such a scenario, the central areas of the assembly may be relatively stiffer than the perimeter areas of the assembly, providing for the absorption of various forces in more robust areas of the assembly. 
     In an example scenario in which the mold material  735  of the assembly  700 K and the mold material  730  of the assembly  700 I are different and/or formed at different stages and/or formed utilizing different types of processes, block  899  (or another block) may comprise preparing the mold material  730  for adhesion to the mold material  735 . For example, the mold material  730  may be physically or chemically etched. The mold material  730  may, for example, be plasma etched. Also for example, grooves, indentations, protrusions, or other physical features may be formed on the mold material  730 . Further for example, an adhesive agent may be placed on the mold material  730 . 
     Block  899  may, for example, utilize a different type of molding process than utilized at block  830 . In an example scenario, block  830  may utilize a compression molding process, while block  899  utilizes a transfer molding process. In such an example scenario, block  830  may utilize a mold material that is specifically adapted to compression molding, and block  899  may utilize a mold material that is specifically adapted to transfer molding. Such molding materials may, for example, have distinctly different material characteristics (e.g., flow characteristics, cure characteristics, hardness characteristics, particle size characteristics, chemical compound characteristics, etc.). 
     As explained herein, for example with regard to block  898 , the molding process of block  899  may provide underfill between the assembly  700 I and the substrate  793  and/or may provide underfill between the die  725 ,  726  and the RD structure  710 . In such an example, there may be uniformity of material between the molded underfill material and the mold material encapsulating the substrate  793  and assembly  700 I and/or the mold material encapsulating the RD structure  710  and semiconductor die  725 ,  726 . 
       FIG.  7 K  provides an example illustration of various aspects of block  899 , for example the molding aspects. For example, the molded assembly  700 K is shown with the mold material  735  covering the interconnection structures  795  and the assembly  700 . Though the mold material  735 , which may also be referred to herein as encapsulant, is shown leaving the top of the assembly  700 I exposed, this need not be the case. For example, block  899  may completely cover the assembly  700 I and need not be followed by a thinning (or grinding) operation to expose the top of the assembly  700 I. 
     The mold material  735  may generally, for example, directly contact and cover portions of the assembly  700 I that are not covered by the underfill  794 . For example in a scenario in which at least a first portion of the sides of the assembly  700 I is covered by underfill  794 , the mold material  735  may directly contact and cover a second portion of the sides of the assembly  700 I. Also, the mold material  735  may extend laterally to the edge of the substrate  793  and thus comprise a side surface that is coplanar with the substrate  793 . Such an assembly may, for example, be formed with panel-molding, followed by singulation of separate packages from the panel. 
     In general, block  899  may comprise molding the substrate. Accordingly, the scope of this disclosure should not be limited by characteristics of any particular molding material, structure and/or technique. 
     The example method  800  may, at block  886 , comprise forming interconnection structures on the substrate, for example on the side of the substrate opposite the side to which the assembly is attached at block  897 . The interconnection structures may comprise characteristics of any of variety of types of interconnection structures, for example structures that may be utilized to connect a semiconductor package to another package or to a motherboard. For example, the interconnection structures may comprise conductive balls (e.g., solder balls) or bumps, conductive posts, etc. 
       FIG.  7 K  provides an example illustration of various aspects of block  886 , for example the interconnection-forming aspects. For example, the interconnection structures  792  are illustrated attached to lands  791  of the substrate  793 . 
     In general, block  886  may comprise forming interconnection structures on the substrate. Accordingly, the scope of this disclosure should not be limited by characteristics of particular interconnection structures or by any particular manner of forming such structures. 
     As discussed herein, the underfill  728  may cover at least a portion of the sides of the die  725 ,  726 , and/or the underfill  794  may cover at least a portion of the sides of the assembly  700 .  FIG.  7 L  provides an illustrative example of such coverage. For example, the assembly  700 I is shown with the underfill  728  contacting a portion of the sides of the die  725 ,  726 . As discussed herein, during a dicing process, the underfill  728  may also be diced, resulting in an assembly  700 I that comprises a planar side surface that includes a side surface of the RD structure  710 , a side surface of the mold material  730  and a side surface of the underfill  728 . 
     The assembly  700 L, which may also be referred to as a package, is shown with the underfill  794  contacting a portion of the sides of the assembly  700 I (e.g., sides of the RD structure  710 , sides of the underfill  728 , and sides of the mold material  730 . Note that as discussed herein, the underfill  794  may, in various example implementations, comprise molded underfill that is the same material as the mold material  735 . The mold material  735  is shown encapsulating the substrate  793 , the interconnection structures  795 , the underfill  794 , and the assembly  700 . Although in the example illustration, the tops of the assembly  700 I and the interconnection structures  795  are exposed from the mold material  735 , this need not be the case. 
       FIGS.  7  and  8    presented various example method aspects and variations thereof. Other example method aspects will now be presented with reference to additional figures. 
     As discussed herein in the discussion of  FIGS.  7  and  8   , block  835  may comprise grinding (or otherwise thinning) the mold material  730  to expose one or more of the die  725 ,  726 . An example is provided at  FIG.  7 D . 
     As also discussed, the mold grinding (or thinning) at block  835  need not be performed or may be performed to an extent that still leaves the tops of the die  725 ,  726  covered with mold material  730 . An example is provided at  FIG.  9   , in which the mold material  735  covers the tops of the die  725 ,  726  of the assembly  700 I. 
     As also discussed herein, for example with regard to block  897  and  FIGS.  7 K and  7 L , in various example implementations, interconnection structures may be formed on the substrate. An example is provided at  FIG.  9   . For example, though the tops of the die interconnection structures  795  are initially covered by the mold material  735 , vias  940  are ablated in the mold material  735  to reveal the interconnection structures  795 . 
     Also, as discussed herein in the discussion of  FIGS.  7  and  8   , in various example implementations, TMV interconnection structures need not be formed on the substrate. An example is provided at  FIG.  10 A . As shown in  FIG.  10 A , as opposed to  FIG.  7 K , there are no TMV interconnection structures  795  formed. Also as shown in  FIG.  10 A , as opposed to block  FIG.  1 K , the mold material  735  does not cover interconnection structures. 
     Also for example, as explained herein, the mold grinding (or thinning) at block  899  may be skipped or performed to an extent that leaves the tops of the assembly  700 I and/or at least one of the die  725 ,  726  covered with mold material  735 .  FIG.  10 A  provides an example illustration of such processing. Generally, the  FIG.  10 A  assembly  1000 A is similar to the  FIG.  7 K  assembly  700 K, less the interconnection structures  795  and with mold material  735  covering the assembly  700 I. 
     Additionally, as explained herein, the mold grinding (or thinning) at block  899  may be performed to an extent that exposes the assembly  700 I and/or one or more of the tops of the die  725 ,  726  thereof from the mold material  735  (and/or mold material  730 ).  FIG.  10 B  provides an example illustration of such processing. Generally, the  FIG.  10 B  assembly  1000 B is similar to the  FIG.  7 K  assembly  700 K, less the interconnection structures  795 . 
     In another example, as explained herein in the discussion of block  897 , the TMV interconnections may comprise any of a variety of structures, for example a conductive pillar (e.g., plated post or pillar, vertical wire, etc.).  FIG.  11 A  provides an example illustration of conductive pillars  1121  attached to the substrate  793 . The conductive pillars  1121  may, for example, be plated on the substrate  793 . The conductive pillars  1121  may also, for example, comprise wires (e.g., wire-bond wires) attached (e.g., wire-bond attached, soldered, etc.) to the substrate  793  and extending vertically. The conductive pillars  1121  may, for example, extend from the substrate  793  to a height greater than a height of the die  725 ,  726 , equal to the height of one or more of the die  725 ,  726 , less than a height of the die  725 ,  726 , etc. Note that any number of rows of the pillars  1121  may be formed. Generally, the  FIG.  11 A  assembly  1100 A is similar to the  FIG.  7 K  assembly  700 K (less the mold compound  735 ) with conductive pillars  1121  as interconnection structures instead of elongated conductive balls  795 . 
     Continuing the example,  FIG.  11 B  illustrates the substrate  793 , conductive pillars  1121 , assembly  700 I (e.g., semiconductor die  725 ,  726 ), and underfill  794  covered with mold material  735 . The molding may, for example, be performed in accordance with block  899  of the example method  800 . Generally, the  FIG.  11 B  assembly  1100 B is similar to the  FIG.  7 K  assembly  700 K with conductive pillars  1121  as interconnection structures instead of elongated conductive balls  795 , and with mold material  735  that has not been thinned or has not been thinned enough to expose the assembly  700 I. 
     Still continuing the example,  FIG.  11 C  illustrates the mold material  735  having been thinned (e.g., ground) to a desired thickness. The thinning may, for example, be performed in accordance with block  899  of the example method  800 . Note, for example, that the conductive pillars  1121  and/or the assembly  700 I (e.g., including mold material  730  and/or semiconductor die  725 ,  726  may also be thinned. For example, the thinning of the mold material  735  may expose the top ends of the conductive pillars  1121 . If instead, however, the thinning of the mold material  735  does not expose the top ends of the conductive pillars  1121 , a mold ablating operation may be performed. Note that although the assembly  1100 C is shown with the tops of the semiconductor die  725 ,  726  of the assembly  700 I exposed, the tops need not be exposed. 
     Generally, the  FIG.  11 C  assembly  1100 C is similar to the  FIG.  7 K  assembly  700 K with conductive pillars  1121  as interconnection structures instead of elongated conductive balls  795 . 
     Continuing the example, the assembly  1100 C shown in  FIG.  11 C  may be further processed by forming a redistribution layer (RDL)  1132  over the mold material  735  and the assembly  700  (e.g., including the mold material  730  and/or semiconductor die  725 ,  726  thereof).  FIG.  11 D  shows an example of such processing. The redistribution layer  1132  may also be referred to herein as the backside redistribution (RDL) layer  1132 . Though such backside RDL forming is not explicitly shown in one of the blocks of the example method  800 , such operation may be performed in any of the blocks, for example after the block  899  mold grinding operation (if performed). 
     As shown in  FIG.  11 D , a first backside dielectric layer  1133  may be formed and patterned on the mold material  735  and the assembly  700 I (e.g., including the mold material  730  and/or semiconductor die  725 ,  726  thereof). The first backside dielectric layer  1133  may, for example, be formed and patterned in a same or similar manner to the RDL dielectric layer  771  formed at block  855 , albeit on a different surface. For example, the first backside dielectric layer  1133  may be formed on the mold material  735  and/or on the assembly  700 I (e.g., including the mold material  730  and/or semiconductor die  725 ,  726  thereof), for example directly on exposed backside surfaces of the die  725 ,  726 , on mold material  730  and/or  735  covering the backside surfaces of the die  725 ,  726 , etc., and vias  1134  may be formed (e.g., by etching, ablating, etc.) in the first backside dielectric layer  1133  to expose at least the tops of the conductive pillars  1121 . 
     Backside traces  1135  may be formed on the first backside dielectric layer  1133  and in the vias  1134  of the first backside dielectric layer  1133 . The backside traces  1135  may thus be electrically connected to the conductive pillars  1121 . The backside traces  1135  may, for example, be formed in a same or similar manner to the RDL traces  782  formed at block  865 . At least some, if not all, of the backside traces  1135  may, for example, extend from the conductive pillars  1121  to locations directly above the assembly  700 I (e.g., including the mold material  730  and/or semiconductor die  725 ,  726  thereof). At least some of the backside traces  1135  may also, for example, extend from the conductive pillars  1121  to locations that are not directly above the assembly  700 I (e.g., including the mold material  730  and/or semiconductor die  725 ,  726  thereof). 
     A second backside dielectric layer  1136  may be formed and patterned on the first backside dielectric layer  1133  and backside traces  1135 . The second backside dielectric layer  1136  may, for example, be formed and patterned in a same or similar manner to the RDL dielectric layer  771  formed at block  855 , albeit on a different surface. For example, the second backside dielectric layer  1136  may be formed over the first backside dielectric layer  1133  and over the backside traces  1135 , and vias  1137  may be formed (e.g., by etching, ablating, etc.) in the second backside dielectric layer  1136  to expose contact areas of the backside traces  1135 . 
     Backside interconnection pads  1138  (e.g., ball contact pads, lands, terminals, etc.) may be formed on the second backside dielectric layer  1136  and/or in the vias  1137  of the second backside dielectric layer  1136 . The backside interconnection pads  1138  may thus be electrically connected to the backside traces  1135 . The backside interconnection pads  1138  may, for example, be formed in a same or similar manner to the RDL traces formed at block  865 . The backside interconnection pads  1138  may, for example, be formed by forming metal contact pads and/or forming under bump metallization (e.g., to enhance subsequent attachment to the backside traces  1135  by other interconnection structures). 
     Though the backside RDL layer  1132  is shown with two backside dielectric layers  1133 ,  1136  and one layer of backside traces  1135 , it should be understood that any number of dielectric and/or trace layers may be formed. 
     Though not shown in  FIG.  11 D , interconnection structures may be formed on the substrate  793 , for example on a side of the substrate  793  opposite the assembly  700 I and mold material  735 , as discussed herein for example with regard to block  886  and  FIG.  7 K . 
     In another example implementation, a substrate (e.g., a laminate substrate, package substrate, etc.) may be attached above the assembly  700 I (e.g., including the semiconductor die  725 ,  726 , and mold material  730 ) and the mold material  735 , for example instead of or in addition to the backside RDL discussed herein with regard to  FIGS.  11 A- 11 D . 
     For example, as illustrated in  FIG.  12 A , the interconnection structures  795  may be formed at a height that will extend to at least the height of the assembly  700 . Note that this height is not necessarily present, for example in a scenario in which the backside substrate has its own interconnection structures or in which additional interconnection structures are utilized between the interconnection structures  795  and the backside substrate. The interconnection structures  795  may, for example, be attached in a same or similar manner as that discussed herein with regard to block  897  and  FIG.  7 K . 
     Continuing the example, as illustrated in  FIG.  12 A , the assembly  1200 A may be molded with a mold material  735  and the mold material  735  may be thinned if necessary. Such molding and/or thinning may, for example, be performed in a same or similar manner to that discussed herein with regard to block  899 , and  FIG.  7 K . 
     As shown in  FIG.  12 B , a backside substrate  1232  may be attached. For example, the backside substrate  1232  may be electrically connected to the interconnection structures  795  and/or mechanically attached to the mold material  735  and/or the assembly  700 I (e.g., the mold material  730  and/or semiconductor die  725 ,  726 ). The backside substrate  1232  may, for example, be attached in panel form and/or single package form, and may for example be attached before or after singulation. 
     As discussed herein, after the assembly  700 I is attached to the substrate  793 , the substrate  793  and/or assembly  700 I may be covered with a mold material. Alternatively, or in addition, the substrate  793  and/or assembly  700 I may be covered with a lid or stiffener.  FIG.  13    provides an illustrative example.  FIG.  13    generally shows the assembly  700 J of  FIG.  7 J , with the addition of a lid  1310  (or stiffener). 
     The lid  1310  may, for example, comprise metal and provide electromagnetic shielding and/or heat dissipation. For example, the lid  1310  may be electrically coupled to a ground trace on the substrate  793  to provide shielding. The lid  1310  may, for example, be coupled to the substrate  793  with solder and/or conductive epoxy. Though not shown, thermal interface material may be formed in a gap  1315  between the assembly  700 I and the lid  1310 . 
     Though most of the examples shown and discussed herein have generally only shown the assembly  700 I attached to the substrate  793 , other components (e.g., active and/or passive components) may also be attached to the substrate  793 . For example, as shown in  FIG.  14   , a semiconductor die  1427  may be attached to the substrate  793  (e.g., flip-chip bonded, wire bonded, etc.). The semiconductor die  1427  is attached to the substrate  793  in a manner that is laterally adjacent to the assembly  700 I. After such attachment, any of the packaging structures discussed herein (e.g., interconnection structures, moldings, lids, etc.) may then be formed. 
     In another example implementation, other components may be coupled to the top side of the assembly  700 I, in a vertical stacking assembly.  FIG.  15    shows an example of one such assembly  1500 C. A third die  1527  and a fourth die  1528  (e.g., the inactive sides thereof) may be attached to the top of the assembly  700 I. Such attachment may, for example, be performed using adhesive. Bond pads on the active sides of the third die  1527  and the fourth die  1528  may then be wire-bonded to the substrate  793 . Note that in a scenario in which an RDL and/or substrate is attached over the assembly  700 , the third die  1527  and/or fourth die  1528  may be flip-chip bonded to such RDL and/or substrate. After such attachment, any of the packaging structures discussed herein (e.g., interconnection structures, moldings, lids, etc.) may then be formed. 
     In yet another example implementation, another component may be coupled to the bottom side of the substrate.  FIG.  16    shows an example of one such assembly. A third die  1699  is attached to the bottom side of the substrate  793 , for example in a gap between interconnection structures on the bottom side of the substrate  793 . After such attachment, any of the packaging structures discussed herein (e.g., interconnection structures, moldings, lids, etc.) may then be formed. 
     The example methods and assemblies shown in  FIGS.  8 - 16    and discussed herein are merely non-limiting examples presented to illustrate various aspects of this disclosure. Such methods and assemblies may also share any or all characteristics with the methods and assemblies shown and discussed in the following co-pending United States patent applications: U.S. patent application Ser. No. 13/753,120, filed Jan. 29, 2013, and titled “SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE”; U.S. patent application Ser. No. 13/863,457, filed on Apr. 16, 2013, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/083,779, filed on Nov. 19, 2013, and titled “SEMICONDUCTOR DEVICE WITH THROUGH-SILICON VIA-LESS DEEP WELLS”; U.S. patent application Ser. No. 14/218,265, filed Mar. 18, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/313,724, filed Jun. 24, 2014, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF”; U.S. patent application Ser. No. 14/444,450, Jul. 28, 2014, and titled “SEMICONDUCTOR DEVICE WITH THIN REDISTRIBUTION LAYERS”; U.S. patent application Ser. No. 14/524,443, filed Oct. 27, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED THICKNESS”; U.S. patent application Ser. No. 14/532,532, filed Nov. 4, 2014, and titled “INTERPOSER, MANUFACTURING METHOD THEREOF, SEMICONDUCTOR PACKAGE USING THE SAME, AND METHOD FOR FABRICATING THE SEMICONDUCTOR PACKAGE”; U.S. patent application Ser. No. 14/546,484, filed Nov. 18, 2014, and titled “SEMICONDUCTOR DEVICE WITH REDUCED WARPAGE”; and U.S. patent application Ser. No. 14/671,095, filed Mar. 27, 2015, and titled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF;” the contents of each of which are hereby incorporated herein by reference in their entirety 
     The discussion herein included numerous illustrative figures that showed various portions of a semiconductor package assembly. For illustrative clarity, such figures did not show all aspects of each example assembly. Any of the example assemblies presented herein may share any or all characteristics with any or all other assemblies presented herein. For example and without limitation, any of the example assemblies shown and discussed with regard to  FIGS.  1 - 7   , or portions thereof, may be incorporated into any of the example assemblies discussed with regard to  FIGS.  8 - 16   . Conversely, any of the assemblies shown and discussed with regard to  FIGS.  8 - 16    may incorporated into the assemblies shown and discussed with regard to  FIGS.  1 - 7   . 
     In summary, various aspects of this disclosure provide a semiconductor device or package structure and a method for making thereof. While the foregoing has been described with reference to certain aspects and examples, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from its scope. Therefore, it is intended that the disclosure not be limited to the particular example(s) disclosed, but that the disclosure will include all examples falling within the scope of the appended claims.