Patent Publication Number: US-11652110-B2

Title: Metal oxide film and method for forming metal oxide film

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of U.S. application Ser. No. 16/024,997, filed Jul. 2, 2018, now allowed, which is a continuation of U.S. application Ser. No. 15/879,506, filed Jan. 25, 2018, now U.S. Pat. No. 10,461,099, which is a continuation of U.S. application Ser. No. 14/071,932, filed Nov. 5, 2013, now U.S. Pat. No. 9,881,939, which claims the benefit of foreign priority applications filed in Japan as Serial No. 2012-245992 on Nov. 8, 2012, Serial No. 2013-016242 on Jan. 30, 2013, and Serial No. 2013-056768 on Mar. 19, 2013, all of which are incorporated by reference. 
    
    
     TECHNICAL FIELD 
     One embodiment of the present invention relates to, for example, a semiconductor device, a display device, a light-emitting device, a driving method thereof, or a manufacturing method thereof. One embodiment of the present invention particularly relates to a metal oxide film and a method for forming the metal oxide film. Further, one embodiment of the present invention relates to a semiconductor device including the metal oxide film. 
     Note that a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics, and for example, electro-optical devices, semiconductor circuits, and electronic devices are all semiconductor devices. 
     BACKGROUND ART 
     A technique by which a transistor is formed using a semiconductor thin film formed over a substrate having an insulating surface has been attracting attention. Such a transistor is applied to a wide range of electronic devices such as an integrated circuit (IC) and an image display device (also simply referred to as a display device). As a semiconductor film applicable to the transistor, a silicon-based semiconductor material is widely known; moreover, a metal oxide exhibiting semiconductor characteristics (an oxide semiconductor) has been attracting attention as another material. 
     For example, Patent Document 1 discloses a technique in which a transistor is manufactured using an amorphous oxide containing In, Zn, Ga, Sn, and the like as an oxide semiconductor. 
     REFERENCE 
     Patent Document 
     [Patent Document 1] Japanese Published Patent Application No. 2006-165529 
     DISCLOSURE OF INVENTION 
     One object of one embodiment of the present invention is to provide a metal oxide film including a crystal part. 
     Another object of one embodiment of the present invention is to provide a metal oxide film having highly stable physical properties. 
     Another object of one embodiment of the present invention is to provide a highly reliable semiconductor device including the above metal oxide film. 
     Another object of one embodiment of the present invention is to provide a novel semiconductor device. Note that the descriptions of these objects do not disturb the existence of other objects. Note that in one embodiment of the present invention, there is no need to achieve all the objects. Note that other objects will be apparent from the description of the specification, the drawings, the claims, and the like and other objects can be derived from the description of the specification, the drawings, the claims, and the like. 
     One embodiment of the disclosed invention is a metal oxide film including a minute crystal part in which periodic atomic arrangement is not observed macroscopically or long-range order in atomic arrangement is not observed macroscopically. The metal oxide film of one embodiment of the present invention includes a region where a halo pattern indicating an amorphous state is observed in a selected-area electron diffraction pattern of the plane. On the other hand, in a nanobeam electron diffraction pattern of the cross-section, the halo pattern is not observed, and spots without directionality, which are different from spots having regularity that represents crystal parts aligned with a specific plane, are observed. Specifically, one embodiment of the disclosed invention is, for example, a metal oxide film having any of the following structures. 
     One embodiment of the present invention is a metal oxide film including a region where a plurality of circumferentially distributed spots are observed in a nanobeam electron diffraction pattern of a cross-section. 
     Another embodiment of the present invention is a metal oxide film including a region where a plurality of circumferentially distributed spots are observed in a nanobeam electron diffraction pattern of a cross-section, and a halo pattern is observed in a selected-area electron diffraction pattern of a plane. 
     In the above, a measurement area of the selected-area electron diffraction is preferably greater than or equal to 300 nmφ. 
     In the above, a measurement area of nanobeam electron diffraction is preferably greater than or equal to 5 nmφ and less than or equal to 10 nmφ. Note that irradiation with an electron beam whose beam diameter is converged to 1 nmφ can give a nanobeam electron diffraction pattern with a measurement area greater than or equal to 5 nmφ and less than or equal to 10 nmφ. 
     In the above, it is preferable that the nanobeam electron diffraction pattern be that of a cross-section of a sample which is thinned to greater than 10 nm and less than or equal to 50 nm. 
     In the above, the metal oxide film preferably includes the crystal part and the size of the crystal part is preferably less than or equal to 10 nm. Alternatively, the size of the crystal part is preferably greater than or equal to 1 nm and less than or equal to 10 nm. 
     One embodiment of the present invention is a metal oxide film including a crystal part which includes a region having the following features: nanobeam electron diffraction with a measurement area greater than or equal to 5 nmφ and less than or equal to 10 nmφ allows the observation of a plurality of circumferentially distributed spots from a cross-section of the metal oxide film thinned to greater than 10 nm and less than or equal to 50 nm, while spots having regularity that represents crystal parts aligned with a specific plane are observed from a cross-section of the metal oxide film thinned to less than or equal to 10 nm. 
     Any one of the above metal oxide films preferably contains at least indium, gallium, or zinc. 
     Another embodiment of the present invention is a method for forming a metal oxide film including a region where a plurality of circumferentially distributed spots are observed in a nanobeam electron diffraction pattern of a cross-section. The metal oxide film is formed by a sputtering method at room temperature in an atmosphere containing oxygen using an oxide target. 
     In the above method for forming a metal oxide film, partial pressure of oxygen in the atmosphere is preferably greater than or equal to 33%. 
     One embodiment of the present invention can provide a metal oxide film including a crystal part. 
     Further, one embodiment of the present invention can provide a metal oxide film having highly stable physical properties. Furthermore, with the use of the metal oxide film in a semiconductor device, the semiconductor device can have high reliability. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1 A  is a cross-sectional TEM image of a metal oxide film of one embodiment of the present invention and  FIGS.  1 B to  1 D  are nanobeam electron diffraction patterns thereof. 
         FIG.  2 A  is a plane TEM image of a metal oxide film of one embodiment of the present invention and  FIG.  2 B  is a selected-area electron diffraction pattern thereof. 
         FIGS.  3 A to  3 C  are conceptual diagrams of electron diffraction intensity distribution. 
         FIG.  4    is a nanobeam electron diffraction pattern of a quartz glass substrate. 
         FIGS.  5 A and  5 B  are cross-sectional TEM images of a metal oxide film of one embodiment of the present invention. 
         FIG.  6    shows a result of X-ray diffraction analysis of a metal oxide film of one embodiment of the present invention. 
         FIG.  7    is a nanobeam electron diffraction pattern of a metal oxide film of one embodiment of the present invention. 
         FIG.  8    is a nanobeam electron diffraction pattern of a metal oxide film of one embodiment of the present invention. 
         FIGS.  9 A to  9 C  each illustrate a structural example of a transistor in one embodiment. 
         FIGS.  10 A to  10 D  illustrate an example of a method for forming a transistor in one embodiment. 
         FIGS.  11 A to  11 C  each illustrate a structural example of a transistor in one embodiment. 
         FIGS.  12 A to  12 C  each illustrate a structure of a display panel in one embodiment. 
         FIG.  13    is a block diagram of an electronic device in one embodiment. 
         FIGS.  14 A to  14 D  are each an external view of an electronic device in one embodiment. 
         FIG.  15 A  is a cross-sectional TEM image of a metal oxide film of one embodiment of the present invention and  FIGS.  15 B to  15 E  are nanobeam electron diffraction patterns thereof. 
         FIG.  16    is a conceptual diagram illustrating a method for thinning a sample by an ion milling method. 
         FIGS.  17 A to  17 D  are each a nanobeam electron diffraction pattern of a metal oxide film of one embodiment of the present invention. 
         FIGS.  18 A and  18 B  show SIMS analysis results of metal oxide films in a comparative example and one embodiment. 
         FIGS.  19 A to  19 D  each show results of X-ray diffraction analysis of samples prepared by a liquid phase method. 
         FIGS.  20 A to  20 C  are cross-sectional TEM images of a sample in a comparative example. 
         FIGS.  21 A to  21 C  are nanobeam electron diffraction patterns of a sample in a comparative example and  FIG.  21 D  is a nanobeam electron diffraction pattern of a metal oxide film of one embodiment of the present invention. 
         FIG.  22    illustrates a crystal structure of an oxide semiconductor layer used for calculation. 
         FIGS.  23 A to  23 D  show calculation results for an influence of hydrogen addition on a crystal state. 
         FIGS.  24 A to  24 D  show measurement results of bond energy in a metal oxide film of one embodiment of the present invention and a sample in a comparative example by XPS. 
     
    
    
     BEST MODE FOR CARRYING OUT THE INVENTION 
     Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the description below and it is easily understood by those skilled in the art that the modes and the aspects can be changed in various ways. Therefore, the invention should not be construed as being limited to the description in the following embodiments. 
     Embodiment 1 
     In this embodiment, a metal oxide film of one embodiment of the present invention will be described with reference to  FIGS.  1 A to  1 D ,  FIGS.  2 A and  2 B ,  FIGS.  3 A to  3 C ,  FIG.  4   ,  FIGS.  5 A and  5 B ,  FIG.  6   ,  FIG.  7   ,  FIGS.  15 A to  15 E ,  FIG.  16   ,  FIGS.  17 A to  17 D ,  FIGS.  18 A and  18 B ,  FIGS.  19 A to  19 D ,  FIGS.  20 A to  20 C , and  FIGS.  21 A to  21 D . 
     &lt;Crystal Part in Metal Oxide Film&gt; 
     The metal oxide film of this embodiment includes a minute crystal part in which periodic atomic arrangement is not observed macroscopically or long-range order in atomic arrangement is not observed macroscopically. Therefore, spots having regularity that represents a crystal state are not observed in some cases by electron diffraction when the measurement area is larger (wider) than a crystal part included therein. 
     &lt;&lt;Cross-sectional TEM Image and Nanobeam Electron Diffraction Patterns&gt;&gt; 
       FIG.  1 A  is a cross-sectional transmission electron microscopy (TEM) image of the metal oxide film of this embodiment.  FIGS.  1 B,  1 C, and  1 D  are electron diffraction patterns observed by nanobeam electron diffraction at points  1 ,  2 , and  3  in  FIG.  1 A , respectively. 
     As an example of the metal oxide film, a 50-nm-thick In—Ga—Zn-based oxide film was formed over a quartz glass substrate. The metal oxide film was formed under the following conditions: an oxide target containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used; an oxygen atmosphere (flow rate of 45 sccm) was used; the pressure was 0.4 Pa; the direct current (DC) power supply was 0.5 kW; and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to about 50 nm (e.g., 40 nm±10 nm) and a cross-sectional TEM image and nanobeam electron diffraction patterns were observed. 
     The cross-sectional TEM image of the metal oxide film was observed with a transmission electron microscope (“H-9000NAR” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV and at a magnification of 2000000 times. The nanobeam electron diffraction was carried out with a transmission electron microscope (“HF-2000” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ. Note that a measurement area of the nanobeam electron diffraction was greater than or equal to 5 nmφ and less than or equal to 10 nmφ. 
     As shown in  FIG.  1 B , in the nanobeam electron diffraction of the metal oxide film of this embodiment, circumferentially arranged spots (light spots) were observed. This means that, in the case of the metal oxide film of this embodiment, a plurality of circumferentially distributed spots are observed. It can also be said that a plurality of concentric circles are formed by a plurality of circumferentially distributed spots. 
     Further, also in  FIG.  1 C  which shows the central portion of the metal oxide film in the thickness direction and in  FIG.  1 D  which shows the vicinity of an interface with the quartz glass substrate, a plurality of circumferentially distributed spots are observed similarly to  FIG.  1 B . In  FIG.  1 C , the radius of a first circle (distance from a main spot to the circumference) is in a range from 3.88/nm to 4.93/nm, or from 0.203 nm to 0.257 nm when converted into interplanar spacing. 
     Apart from a halo pattern indicating an amorphous state, a plurality of spots are observed in the nanobeam electron diffraction patterns shown in  FIGS.  1 B to  1 D . This confirms that the metal oxide film of this embodiment includes a crystal part. However, spots without directionality, which do not have regularity that represents crystal parts aligned with a specific plane, are observed in the nanobeam electron diffraction patterns shown in  FIGS.  1 B to  1 D . Accordingly, it is assumed that the metal oxide film of this embodiment includes a plurality of crystal parts whose surface orientations are random and whose sizes are different from each other. 
       FIGS.  5 A and  5 B  are partial enlarged views of the cross-sectional TEM image of  FIG.  1 A .  FIG.  5 A  is a cross-sectional TEM image of the vicinity of the point  1  (a surface of the metal oxide film) in  FIG.  1 A , which is observed at an observation magnification of 8000000 times.  FIG.  5 B  is a cross-sectional TEM image of the vicinity of the point  2  (the central portion of the metal oxide film in the thickness direction) in  FIG.  1 A , which is observed at an observation magnification of 8000000 times. 
     In the cross-sectional TEM images of the metal oxide film of this embodiment shown in  FIGS.  5 A and  5 B , a crystal structure cannot be clearly observed. 
     &lt;&lt;Plane TEM Image and Selected-area Electron Diffraction Pattern&gt;&gt; 
       FIG.  2 A  is a plane TEM image of the metal oxide film of this embodiment.  FIG.  2 B  shows an electron diffraction pattern of a region surrounded by a circle in  FIG.  2 A , which is observed by selected-area electron diffraction. 
     As an example of the metal oxide film, a 50-nm-thick In—Ga—Zn-based oxide film was formed over a quartz glass substrate. The metal oxide film was formed under the following conditions: an oxide target containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used; an oxygen atmosphere (flow rate of 45 sccm) was used; the pressure was 0.4 Pa; the direct current (DC) power supply was 0.5 kW; and the substrate temperature was room temperature. Then, the formed metal oxide film was thinned to about 50 nm (e.g., 40 nm±10 nm) and a plane TEM image and a selected-area electron diffraction pattern were observed. 
     The images in  FIGS.  2 A and  2 B  were obtained with a transmission electron microscope (“H-9000NAR” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV. To obtain the image in  FIG.  2 A , a plane of the metal oxide film was observed at an observation magnification of 500000 times.  FIG.  2 B  shows a diffraction result of the region in the circle in  FIG.  2 A  obtained by selected-area electron diffraction. The pattern in  FIG.  2 B  was obtained by electron diffraction with a selected area of 300 nmφ. In consideration of electron beam expansion (about several nanometers), a measurement area is greater than or equal to 300 nmφ. 
     As shown in  FIG.  2 B , in the case of the metal oxide film of this embodiment, the plurality of spots observed by nanobeam electron diffraction were not observed and a halo pattern was observed in an electron diffraction pattern observed by selected-area electron diffraction the measurement area of which is wider than that of the nanobeam electron diffraction. Thus, the metal oxide film of this embodiment can be regarded as a metal oxide film including a minute crystal part in which periodic atomic arrangement is not observed macroscopically (in the case where a measurement area is greater than or equal to 300 rump, for example) or long-range order in atomic arrangement is not observed macroscopically. 
     &lt;&lt;Conceptual Diagram of Electron Diffraction Intensity Distribution&gt;&gt; 
       FIGS.  3 A to  3 C  conceptually illustrate diffraction intensity distribution in the electron diffraction patterns in  FIGS.  1 B to  1 D  and  FIGS.  2 A and  2 B .  FIG.  3 A  is a conceptual diagram of diffraction intensity distribution in the nanobeam electron diffraction patterns in  FIGS.  1 B to  1 D .  FIG.  3 B  is a conceptual diagram of diffraction intensity distribution in the selected-area electron diffraction pattern in  FIG.  2 B .  FIG.  3 C  is a conceptual diagram of diffraction intensity distribution in an electron diffraction pattern of an ideal polycrystalline structure. 
     In each of  FIGS.  3 A to  3 C , the vertical axis represents electron diffraction intensity (arbitrary unit) and the horizontal axis represents a distance from a main spot. 
     In  FIG.  3 C  for the ideal polycrystalline structure, a peak is observed at a specific distance from the main spot based on interplanar spacing (d value) of a plane with which crystal parts are aligned. In that case, in the electron diffraction pattern, a ring with a small line-width is clearly observed at the specific distance from the main spot. 
     On the other hand, as shown in  FIGS.  1 B to  1 D , the circumferential region, which is formed with the plurality of spots observed in the nanobeam electron diffraction pattern of the metal oxide film of this embodiment, has a relatively large line-width. Thus, its electron beam diffraction intensity is discretely distributed and includes a plurality of zones (peak zones) in which peaks are distributed, as shown in  FIG.  3 A . Note that a small number of spots are observed between the plurality of the circumferentially arranged regions in the nanobeam electron diffraction pattern. This means that, as shown in  FIG.  3 A , diffraction peaks exist between two peak zones. 
     On the other hand, the electron beam diffraction intensity distribution in the selected-area electron diffraction pattern of the metal oxide film of this embodiment is continuous as shown in  FIG.  3 B . Since  FIG.  3 B  can approximate to a result obtained by observing the electron beam diffraction intensity distribution shown in  FIG.  3 A  in a wide area, it can be considered that the peak zone in  FIG.  3 A  is integrated and the continuous intensity distribution is obtained. 
       FIGS.  3 A to  3 C  indicate that the metal oxide film of this embodiment includes a plurality of crystal parts whose surface orientations are random and whose sizes are different from each other, and the crystal parts are so minute that spots are not observed in the selected-area electron diffraction patterns. 
     The metal oxide film which gives a plurality of spots in the nanobeam electron diffraction pattern as shown in  FIGS.  1 B to  1 D  is thinned to about 50 nm. Further, since the beam diameter of the electron beam is converged to 1 nmφ, the measurement area is greater than or equal to 5 nm and less than or equal to 10 nm. Accordingly, it is assumed that the size of the crystal part included in the metal oxide film of this embodiment is at least less than or equal to 50 nm, for example, less than or equal to 10 nm or less than or equal to 5 nm. 
     &lt;&lt;Nanobeam Electron Diffraction Pattern of Extremely Thin Sample&gt;&gt; 
     In the case where the size of the crystal part included in the metal oxide film of this embodiment is less than or equal to 10 nm or less than or equal to 5 nm, a measurement area in the depth direction is larger than the size of the crystal part in the sample in which the metal oxide film is thinned to about 50 nm; as a result, a plurality of crystal parts are observed in the measurement area, in some cases. Thus, a metal oxide film thinned to less than or equal to 10 nm was formed, and its cross section was observed by nanobeam electron diffraction. 
     A method for forming the sample is as follows. A 50-nm-thick In—Ga—Zn-based oxide film was formed over a quartz glass substrate. The film was formed under the following conditions: an oxide target containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used; an oxygen atmosphere (flow rate of 45 sccm) was used; the pressure was 0.4 Pa; the direct current (DC) power supply was 0.5 kW; and the substrate temperature was room temperature. After the metal oxide film was formed, first heat treatment was performed at 450° C. in a nitrogen atmosphere for one hour and second heat treatment was performed at 450° C. in an atmosphere containing nitrogen and oxygen for one hour. 
     The metal oxide film on which the second heat treatment was performed was further thinned by an ion milling method using Ar ions. First, the quartz glass substrate over which the metal oxide film was formed was attached to a dummy substrate for reinforcement. Then, the film was thinned to about 50 μm by cutting and polishing. After that, as illustrated in  FIG.  16   , a metal oxide film  204  provided to a quartz glass substrate  200  and a dummy substrate  202  were irradiated with argon ions at a steep angle (about 3°) so that ion milling was performed to form a region  210   a  which was thinned to about 50 nm (40 nm±10 nm) and a region  210   b  which was thinned to less than or equal to 10 nm, for example, 5 nm to 10 nm. Then, the cross section of each region was observed. 
       FIG.  15 A  is a cross-sectional TEM image of a sample thinned to about 50 nm, which corresponds to the region  210   a .  FIGS.  15 B to  15 E  show electron diffraction patterns observed by nanobeam electron diffraction of the cross section shown in  FIG.  15 A .  FIG.  15 B  shows an electron diffraction pattern observed with the use of an electron beam whose beam diameter is converged to 1 nmφ.  FIG.  15 C  shows an electron diffraction pattern observed with the use of an electron beam whose beam diameter is converged to 10 nmφ.  FIG.  15 D  shows an electron diffraction pattern observed with the use of an electron beam whose beam diameter is converged to 20 nmφ.  FIG.  15 E  shows an electron diffraction pattern observed with the use of an electron beam whose beam diameter is converged to 30 nmφ. 
     As shown in  FIG.  15 B , a plurality of circumferentially distributed spots (light spots), which are similar to those in  FIGS.  1 B to  1 D , are observed also in the metal oxide film on which heat treatment is performed. Further, as shown in  FIGS.  15 C to  15 E , when the beam diameter of an electron beam is increased to observe a wider measurement area, the spots are gradually blurred. 
       FIGS.  17 A to  17 D  show nanobeam electron diffraction patterns at four given points in a sample thinned to less than or equal to 10 nm, which corresponds to the region  210   b . The nanobeam electron diffraction patterns are observed with the use of an electron beam whose beam diameter is converged to 1 nmφ. 
     In  FIGS.  17 A and  17 B , spots having regularity that represents crystal parts aligned with a specific plane are observed. This indicates that the metal oxide film of this embodiment undoubtedly includes a crystal part. In  FIGS.  17 C and  17 D , on the other hand, a plurality of circumferentially distributed spots (light spots) are observed. 
     As described above, the size of the crystal part included in the metal oxide film of this embodiment is minute and is at least less than or equal to 50 nm, for example, less than or equal to 10 nm or less than or equal to 5 nm. Thus, in the case where a sample is thinned to less than or equal to 10 nm and the diameter of an electron beam is converged to 1 rump to make a measurement area smaller than the size of one crystal part, for example, spots having regularity that represents crystal parts aligned with a specific plane can be observed, depending the measured regions. In the case where a plurality of crystal parts are included in the observed region, an electron beam transmitted through a crystal part further irradiates another crystal part located in the depth direction, which would result in the observation of a plurality of nanobeam electron diffraction patterns. 
     &lt;&lt;Nanobeam Electron Diffraction Pattern of Quartz Substrate&gt;&gt; 
       FIG.  4    shows a nanobeam electron diffraction pattern of a quartz glass substrate. The measurement conditions are the same as those for the oxide semiconductor film shown in  FIGS.  1 B to  1 D . 
     As shown in  FIG.  4   , a halo pattern in which a specific spot is not given by diffraction and whose luminance is gradually changed form a main spot is observed in the case of a quartz glass substrate having an amorphous structure. Thus, circumferentially arranged spots like those observed in the metal oxide film of this embodiment are not observed in a film having an amorphous structure even when electron diffraction is performed on a minute region. This confirms that the circumferentially arranged spots observed in  FIGS.  1 B to  1 D  are peculiar to the metal oxide film of this embodiment. 
     &lt;&lt;Electron Diffraction Pattern after Continuous Irradiation with Nanobeam&gt;&gt; 
       FIG.  8    shows an electron diffraction pattern observed after the point  2  in  FIG.  1 A  is irradiated with an electron beam whose beam diameter is converged to about 1 nmφ for one minute. 
     Similarly to the electron diffraction pattern shown in  FIG.  1 C , a plurality of circumferentially distributed spots are observed in the electron diffraction pattern shown in  FIG.  8   , and there is no significant difference between the electron diffraction patterns in  FIG.  1 C  and  FIG.  8   . This means that the crystal part identified by  FIG.  1 C  is formed when the metal oxide film of this embodiment is formed and is not resulted from the irradiation of the converged electron beam. 
     &lt;&lt;Analysis by X-Ray Diffraction&gt;&gt; 
     The sample of the metal oxide film of this embodiment formed over a quartz glass substrate, which is used for  FIGS.  1 A to  1 D  and  FIGS.  2 A and  2 B , was analyzed by X-ray diffraction (XRD).  FIG.  6    shows an XRD spectrum measured by an out-of-plane method. 
     In  FIG.  6   , the vertical axis represents the X-ray diffraction intensity (arbitrary unit) and the horizontal axis represents the diffraction angle 2θ (degree). Note that the XRD spectra were measured with an X-ray diffractometer, D8 ADVANCE manufactured by Bruker AXS. 
     As shown in  FIG.  6   , a peak corresponding to quartz appears at around 2θ=20° to 23°; however, a peak corresponding to the crystal part included in the metal oxide film cannot be found. 
     The result in  FIG.  6    indicates that the crystal part included in the metal oxide film of this embodiment is minute. 
     According to the above results, it can be assumed that the metal oxide film of this embodiment is a film in which crystal parts whose surface orientations are random are cohered. 
     In addition, it is assumed that the size of a crystal part included in the metal oxide film of this embodiment is less than or equal to 10 nm or less than or equal to 5 nm, for example. The metal oxide film of this embodiment includes a crystal part (nanocrystal (nc)) whose size is greater than or equal to 1 nm and less than or equal to 10 nm, for example 
     &lt;Method for Forming Metal Oxide Film&gt; 
     A method for forming the metal oxide film of this embodiment is described below. As described above, the metal oxide film of this embodiment is formed by a sputtering method at room temperature in an atmosphere containing oxygen. With the use of the atmosphere containing oxygen, oxygen vacancies in the metal oxide film can be reduced and a film including a crystal part can be formed. 
     &lt;&lt;Reduction in Oxygen Vacancy&gt;&gt; 
     A reduction of oxygen vacancies in the metal oxide film of this embodiment allows the formation of a film having stable physical properties. In particular, in the case where a semiconductor device is formed using an oxide semiconductor film as the metal oxide film of this embodiment, oxygen vacancies in the oxide semiconductor film cause carriers to be generated; as a result, the electric characteristics of the semiconductor device vary. Thus, a semiconductor device formed using an oxide semiconductor film in which oxygen vacancies are reduced can be highly reliable. 
     Note that it is preferable to increase the oxygen partial pressure in the deposition atmosphere because the oxygen vacancies in the metal oxide film of this embodiment can be further reduced. For example, the oxygen partial pressure in the deposition atmosphere is preferably greater than or equal to 33%. 
       FIG.  7    shows a nanobeam electron diffraction pattern of the metal oxide film of this embodiment which was formed at an oxygen partial pressure of 33%. The metal oxide film of this embodiment shown in  FIG.  7    was formed under conditions similar to those of the metal oxide film shown in  FIGS.  1 A to  1 D  except that a mixture of argon and oxygen (flow rate of Ar and O 2  are 30 sccm and 15 sccm, respectively) was used as the deposition atmosphere. The nanobeam electron diffraction was carried out in a manner similar to that explained for  FIGS.  1 B to  1 D . 
     In the metal oxide film of this embodiment which is formed at an oxygen partial pressure of 33%, circumferentially arranged spots are also observed in the nanobeam electron diffraction pattern shown in  FIG.  7   . This confirms that a metal oxide film including a crystal part is formed. 
     &lt;&lt;Deposition by Sputtering Method&gt;&gt; 
     An oxide target that can be used for forming the metal oxide film of this embodiment is not limited to an In—Ga—Zn-based oxide; for example, an In-M-Zn-based oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf) can be used. 
     The metal oxide film of this embodiment, which includes a crystal part, is preferably formed using a sputtering target including a polycrystalline oxide containing a plurality of crystal grains. The reason is as follows. In the case where the sputtering target contains a plurality of crystal grains and there are interfaces that are likely to cause cleavage of the crystal grains because of weak bondings between the plurality of crystal grains, the crystal grains are cleaved along the interfaces when ions collide with the sputtering target, whereby flat plate-like sputtered particles can be obtained in some cases. The obtained flat plate-like sputtered particles are deposited on a substrate; accordingly, a metal oxide film including a nanocrystal region is formed in some cases. Note that the above mechanism to form the metal oxide film of this embodiment is one consideration. 
     The above-described metal oxide film of this embodiment includes a plurality of crystal parts whose surface orientations are random and whose sizes are different from each other, and the crystal parts are so minute that spots are not observed in the selected-area electron diffraction pattern. 
     Further, the metal oxide film of this embodiment includes a region having a crystal part and has stable physical properties. Accordingly, with the use of the metal oxide film of this embodiment in a semiconductor device, the semiconductor device can have high reliability. 
     COMPARATIVE EXAMPLE 
     In this comparative example, the crystallinity of a metal oxide film formed by a liquid phase method will be described with reference to drawings. 
     A method for forming the metal oxide film of this comparative example will be described below. 
     First, In 2 O 3  (5 wt %), Ga 2 O 3  (3 wt %), ZnO (5 wt %), and a coating agent were mixed so that the mixture contains In, Ga, and Zn at a composition ratio of 1:1:1, and the mixture was applied to a glass substrate by spin coating. The conditions for the spin coating were as follows: a spinner was used; and the spinning rate was changed stepwise from 900 rpm to 2000 rpm. 
     After that, first heat treatment was performed at 150° C. in an air atmosphere for two minutes using a hot plate. 
     Subsequently, second heat treatment was performed at 450° C. in an air atmosphere for one hour. The bonding state of the metal oxide film (formed by a liquid phase method) of this comparative example subjected to the second heat treatment, and the bonding state of the metal oxide film (formed by a sputtering method) of this embodiment formed under the same conditions as those of the metal oxide film shown in  FIG.  7    were analyzed by X-ray photoelectron spectroscopy (XPS).  FIGS.  24 A to  24 D  show the analysis results. 
     The XPS analysis was carried out with Quantera SXM manufactured by Physical Electronics, Inc. as an analysis apparatus.  FIGS.  24 A to  24 D  show the spectra in the regions corresponding to 3d(5/2) orbital of In (see  FIG.  24 A ), 3d orbital of Ga (see  FIG.  24 B ), 3p orbital of Zn (see  FIG.  24 C ), and is orbital of O (see  FIG.  24 D ) of each of the metal oxide films. Solid lines in  FIGS.  24 A to  24 D  corresponds to the analysis results of the In—Ga—Zn oxide film of this comparative example, which was formed by a liquid phase method. Dashed lines in  FIGS.  24 A to  24 D  corresponds to the analysis results of the In—Ga—Zn oxide film of this embodiment, which was formed by a sputtering method (sputtering). 
     In  FIGS.  24 A to  24 D , although there is a slight difference between bond energies, the metal oxide film of this comparative example, which was formed by a liquid phase method, and the metal oxide film of this embodiment, which was formed by a sputtering method, have substantially the same spectral shapes. Thus, the metal oxide film of this comparative example, which was formed by a liquid phase method, was identified as an In—Ga—Zn oxide film. 
     Next, the formed samples of the comparative example were analyzed by XRD.  FIGS.  19 A to  19 D  show the results of the analysis by an out-of-plane method. 
     In the XRD analysis were used the samples of the In—Ga—Zn oxide film which were subjected to the second heat treatment at 350° C., 450° C., or 550° C. in an air atmosphere for one hour after the first heat treatment. 
     In  FIGS.  19 A to  19 D , the vertical axis represents the X-ray diffraction intensity (arbitrary unit) and the horizontal axis represents the diffraction angle 2θ (degree). The XRD measurements were carried out with an X-ray diffractometer, D8 ADVANCE manufactured by Bruker AXS. 
       FIG.  19 A  shows the measurement results of the samples of this comparative example formed by a liquid phase method. The XRD pattern of the sample which is not subjected to the heat treatment is the pattern denoted by “as-depo”. Note that  FIGS.  19 B to  19 D  show the measurement results of indium oxide films, gallium oxide films, and zinc oxide films which are formed by a liquid phase method and subjected to heat treatment at 350° C., 450° C., or 550° C. in an air atmosphere for one hour. 
     As shown in  FIGS.  19 A to  19 D , peaks corresponding to In 2 O 3  crystalline peaks are found in the XRD pattern of the indium oxide films after the heat treatment. In addition, peaks corresponding to ZnO crystalline peaks are found in the XRD pattern of the zinc oxide films after the heat treatment. In the samples of this comparative example subjected to heat treatment at any of the temperature, on the other hand, a crystalline peak is not found unlike in the indium oxide films and the zinc oxide films. 
     Then, the film density of each of the samples which were subjected to the second heat treatment at 450° C. in an air atmosphere for one hour was measured by X-ray reflectometry (XRR). 
     Note that XRR is a measurement method for measuring the density of a deposited thin film, in which X-rays are incident on a measurement sample to measure critical angles and changes in amplitude waveforms of the incident X-rays and theoretical analysis is performed using the critical angles and the amplitude waveforms. 
     Table 1 shows the measured film density. 
     
       
         
           
               
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                   
                 Film Density (g/cm 3 ) 
               
            
           
           
               
               
               
               
            
               
                 Sample 
                 Crystallinity 
                 Observed 
                 Theoretical 
               
               
                   
               
               
                 In-Ga-Zn  
                 No peak 
                 3.27 
                 6.35 
               
               
                 Oxide Film 
                   
                   
                   
               
               
                 (In:Ga:Zn =  
                   
                   
                   
               
               
                 1:1:1) 
                   
                   
                   
               
               
                 Indium Oxide  
                 Peak  
                 4.26 
                 7.12 
               
               
                 Film 
                 assignable to 
                   
                   
               
               
                   
                 In 2 O 3   
                   
                   
               
               
                 Gallium Oxide  
                 No peak 
                 3.61 
                 5.94 
               
               
                 Film 
                   
                   
                   
               
               
                 Zinc Oxide  
                 Peak  
                 4.06 
                 5.67 
               
               
                 Film 
                 assignable to 
                   
                   
               
               
                   
                 ZnO 
               
               
                   
               
            
           
         
       
     
     As shown in Table 1, the films formed by a liquid phase method have extremely low density as compared with the theoretical values calculated on the basis of their single crystal structures. Note that it is difficult to measure the film density with high accuracy because a film formed by a liquid phase method has large roughness. 
     Next, the concentrations of impurities contained in the metal oxide film of this comparative example and the metal oxide film of this embodiment were measured by SIMS. 
       FIG.  18 A  shows concentration profiles of hydrogen (1H) in the metal oxide films of the comparative example and the metal oxide film of this embodiment.  FIG.  18 B  shows concentration profiles of carbon (12C) in the metal oxide films of the  20  comparative example and the metal oxide film of this embodiment. In  FIGS.  18 A and  18 B , the horizontal axis represents a depth (nm) and the vertical axis represents the concentration of hydrogen or carbon (atoms/cm 3 ). 
     Samples formed by a liquid phase method under the conditions similar to those described above were used as the metal oxide films of the comparative example for  FIGS.  18 A and  18 B . Note that filtration using a membrane filter (0.2 μm) was performed on the material before spin coating. In addition, the second heat treatment was performed at 450° C., 500° C., or 550° C. in an air atmosphere for one hour. The other conditions were the same as those of the above metal oxide films formed by a liquid phase method. A sample formed by a sputtering method under the same conditions as those of the metal oxide film shown in  FIG.  7    was used for the metal oxide film of this embodiment. 
     As shown in  FIGS.  18 A and  18 B , large amounts of hydrogen and carbon uniformly exist in the metal oxide films of the comparative example as compared with the metal oxide film of this embodiment. 
     The carbon concentration of the metal oxide film of this embodiment shown in  FIG.  18 B  is gradually decreased from its surface to the inside the film. This suggests that carbon in the metal oxide film of this embodiment is mainly due to the surface contamination. 
     In contrast, the metal oxide films formed under any conditions of the comparative example uniformly contain hydrogen at a density as high as 1×10 22  (atoms/cm 3 ) or more and carbon at a density as high as 4×10 21  (atoms/cm 3 ) or more. It is assumed that carbon in the metal oxide films of the comparative example is due to an organic acid salt which is a raw material of a spin coating material. 
     Next, cross-sectional TEM images of the sample of this comparative example, which was subjected to the second heat treatment at 450° C. in an air atmosphere for one hour, are shown in  FIGS.  20 A to  20 C . The cross section was observed with a transmission electron microscope (“H-9000NAR” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 300 kV.  FIG.  20 A  is a cross-sectional image at a magnification of 500000.  FIG.  20 B  is a cross-sectional image at a magnification of 2000000.  FIG.  20 C  is a cross-sectional observation image at a magnification of 8000000. 
     As seen in  FIGS.  20 A and  20 B , a large part of the sample of this comparative example formed by a liquid phase method is occupied by an amorphous region. In addition, a shade of gray (variation in brightness) due to the difference in film density can be seen. 
     In a region a in the cross-sectional TEM image in  FIG.  20 C , the brightness is high, which means that the region a has low film density. In a region b in the cross-sectional TEM image in  FIG.  20 C , the brightness is low, which means that the region b has high density. 
     The regions a and b in  FIG.  20 C  were observed by nanobeam electron diffraction.  FIGS.  21 A to  21 C  show nanobeam electron diffraction patterns. 
     The nanobeam electron diffraction was carried out with a transmission electron microscope (“HF-2000” manufactured by Hitachi High-Technologies Corporation) at an acceleration voltage of 200 kV and a beam diameter of about 1 nmφ.  FIG.  21 A  shows a nanobeam electron diffraction pattern of the region a in  FIG.  20 C .  FIGS.  21 B and  21 C  show nanobeam electron diffraction patterns of two different portions (denoted by b 1  and b 2 ) in the region b in  FIG.  20 C . 
       FIG.  21 D  shows a nanobeam electron diffraction pattern of the metal oxide film of one embodiment of the present invention, which was formed and observed under the same conditions as those of the metal oxide film shown in  FIG.  7   . 
     As shown in  FIGS.  21 A to  21 C , a pattern, which is different from the circumferentially arranged spots (light spots) observed in the metal oxide film of one embodiment of the present invention shown in  FIG.  21 D , was observed in each region in the metal oxide film of this comparative example formed by a liquid phase method. 
     The nanobeam electron diffraction pattern of the region a shown in  FIG.  21 A  is similar to a halo pattern indicating an amorphous state. The presence of a region having such low crystallinity may be due to the low density and the high impurity concentration of the film. 
     As shown in  FIGS.  21 B and  21 C , spots (denoted by  1  to  3  in  FIGS.  21 B and  21 C ) having regularity that represents crystal parts aligned with a specific plane are observed in the nanobeam electron diffraction patterns of the region b. The analysis results of the diffraction patterns of these spots are shown in Table 2 below. 
     
       
         
           
               
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                   
                 d value (mm) 
               
            
           
           
               
               
               
               
               
               
               
            
               
                 Region 
                 Spot 
                 h 
                 k 
                 l 
                 Theoretical 
                 Observed 
               
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 b1 
                 1 
                 1 
                 0 
                 4 
                 0.261 
                 0.263 
               
               
                   
                 2 
                 2 
                 2 
                 4 
                 0.139 
                 0.138 
               
               
                   
                 3 
                 1 
                 2 
                 0 
                 0.165 
                 0.165 
               
               
                 b2 
                 1 
                 0 
                 0 
                 9 
                 0.290 
                 0.288 
               
               
                   
                 2 
                 1 
                 0 
                 14 
                 0.156 
                 0.155 
               
               
                   
                 3 
                 1 
                 0 
                 5 
                 0.250 
                 0.250 
               
               
                   
               
            
           
         
       
     
     According to Table 2, the observed d values estimated from the spots in  FIG.  21 B  or  FIG.  21 C  are almost the same as the theoretical d values of a plurality of plane orientations in InGaZnO 4 , which means that the In—Ga—Zn oxide film of this comparative example formed by a liquid phase method includes a crystal region due to InZnGaO 4 . 
     Therefore, a region which includes periodic atomic arrangement due to InZnGaO 4  and a region which has extremely low crystallinity and is close to an amorphous state coexist in the InZnGaO 4  film formed by a liquid phase method in spite of the presence of an impurity. 
     Next, the influence of impurities such as hydrogen and carbon in the metal oxide film of the comparative example on the crystallinity of the metal oxide film was evaluated by calculation. 
     In the calculation below, the effect of hydrogen on the crystallization of the metal oxide film was examined by the first-principles calculation. Specifically, an energy difference between an amorphous state and a crystal state was measured in both the case where InGaZnO 4  does not contain hydrogen and the case where the InGaZnO 4  contains hydrogen at 6.67 atom %. An atom density of an In—Ga—Zn—O crystal of 8.54×10 22  atoms/cm 3  and the SIMS analysis results shown in  FIGS.  18 A and  18 B  indicate that this hydrogen concentration is the same as the hydrogen concentration of the metal oxide film of this comparative example. Note that an In—Ga—Zn oxide film containing In, Ga, and Zn at an atomic ratio of 1:1:1 was used as an example of the metal oxide film for the calculation. 
       FIG.  22    illustrates a lattice structure of an In—Ga—Zn—O crystal including 112 atoms used for the calculation. 
     For the calculation, a structure in which no H atom is added to the structure illustrated in  FIG.  22    and a structure in which eight H atoms are added to the structure illustrated in  FIG.  22    were made, and the structures were optimized. Then, energy was calculated. In addition, amorphous structures were formed on the basis of the optimized structure through the steps below. 
     (1) Molecular dynamics calculation with an NVT ensemble at 3000 K. 
     (2) Molecular dynamics calculation with an NVT ensemble at 1000 K for 2 psec. 
     (3) Optimization of the structures. 
     Note that three structures were obtained by the above calculation (1) for 5 psec, 5.5 psec, or 6 psec, and then subjected to the calculation (2) and the optimization (3) to form three amorphous structures for each of the three structures. Then, average values of energy were obtained. In the calculation, first principles calculation software “Vienna Ab initio Simulation Package (VASP)” was used. The calculation conditions are shown in Table 3. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                   
                   
                 Cutoff Energy 
                   
               
               
                 Steps 
                 Functional 
                 (eV) 
                 K Points 
               
               
                   
               
             
            
               
                 (1) 
                 GGA-PBE 
                 500 
                 1 × 1 × 1 
               
               
                 (2) 
                 GGA-PBE 
                 300 
                 1 × 1 × 1 
               
               
                 (3) 
                 GGA-PBE 
                 500 
                 2 × 2 × 3 
               
               
                   
               
            
           
         
       
     
       FIGS.  23 A to  23 D  illustrate part of each structures obtained by the calculation. Table 4 shows the calculation results of the energy difference.  FIG.  23 A  illustrates a structure in which no H atom (0 atom %) is added to a single crystal In—Ga—Zn oxide film.  FIG.  23 B  illustrates a structure in which eight H atoms (6.67 atom %) are added to a single crystal In—Ga—Zn oxide film.  FIG.  23 C  illustrates a structure in which no H atom (0 atom %) is added to an amorphous In—Ga—Zn oxide film  FIG.  23 D  illustrates a structure in which eight H atoms (6.67 atom %) are added to an amorphous In—Ga—Zn oxide film. 
     
       
         
           
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
               
                 Hydrogen  
                   
                 Energy difference 
               
               
                 concentration 
                 Density 
                 (amorphous-single  
               
               
                 (atom %) 
                 (g/cm 3 ) 
                 crystal) 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
            
               
                 0 
                 6.12 
                 1.23 
               
               
                 6.67 
                 5.82 
                 0.54 
               
               
                   
               
            
           
         
       
     
     According to Table 4, the energy of the In—Ga—Zn oxide film greatly decreases when the film is crystallized. Further, the stabilization energy due to crystallization decreases when H atoms are added to the film. Accordingly, it is assumed that the observation of the nanobeam electron diffraction pattern similar to a halo pattern in addition to the spot-containing pattern indicating the periodic atomic arrangement in the metal oxide film of this comparative example formed by a liquid phase method is resulted from destabilization of the crystal structure by hydrogen. 
     As described above, when the metal oxide film contains hydrogen as an impurity, the stability of the crystal is decreased. These calculation results agree with the high concentration of the impurity such as hydrogen and carbon in the metal oxide film of the comparative example, which shows a nanobeam electron diffraction pattern similar to a halo pattern, when compared with the metal oxide film of this embodiment. 
     This embodiment can be implemented in combination with Embodiment described in this specification as appropriate. 
     Embodiment 2 
     In this embodiment, a structural example of a transistor including the metal oxide film which is described as an example in Embodiment 1 and exhibits semiconductor characteristics (an oxide semiconductor film) will be described with reference to drawings. 
     &lt;Structural Example of Transistor&gt; 
       FIG.  9 A  is a schematic cross-sectional view of a transistor  100  which is described below as an example. The transistor  100  is a bottom-gate transistor. 
     The transistor  100  includes a gate electrode  102  provided over a substrate  101 , an insulating layer  103  provided over the substrate  101  and the gate electrode  102 , an oxide semiconductor layer  104  provided over the insulating layer  103  to overlap with the gate electrode  102 , and a pair of electrodes  105   a  and  105   b  in contact with the top surface of the oxide semiconductor layer  104 . Further, an insulating layer  106  is provided to cover the insulating layer  103 , the oxide semiconductor layer  104 , and the pair of electrodes  105   a  and  105   b , and an insulating layer  107  is provided over the insulating layer  106 . 
     The oxide semiconductor film of one embodiment of the present invention can be applied to the oxide semiconductor layer  104  in the transistor  100 . 
     &lt;&lt;Substrate  101 &gt;&gt; 
     There is no particular limitation on the property of a material and the like of the substrate  101  as long as the material has heat resistance enough to withstand at least heat treatment which will be performed later. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, or an yttria-stabilized zirconia (YSZ) substrate may be used as the substrate  101 . Alternatively, a single crystal semiconductor substrate or a polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a compound semiconductor substrate made of silicon germanium or the like, an SOI substrate, or the like can be used as the substrate  101 . Still alternatively, any of these substrates provided with a semiconductor element may be used as the substrate  101 . 
     Still alternatively, a flexible substrate such as a plastic substrate may be used as the substrate  101 , and the transistor  100  may be provided directly on the flexible substrate. Further alternatively, a separation layer may be provided between the substrate  101  and the transistor  100 . The separation layer can be used when part or the whole of the transistor formed over the separation layer is formed and separated from the substrate  101  and transferred to another substrate. Thus, the transistor  100  can be transferred to a substrate having low heat resistance or a flexible substrate. 
     &lt;&lt;Gate Electrode  102 &gt;&gt; 
     The gate electrode  102  can be formed using a metal selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, and tungsten; an alloy containing any of these metals as a component; an alloy containing any of these metals in combination; or the like. Further, one or more metals selected from manganese and zirconium may be used. Furthermore, the gate electrode  102  may have a single-layer structure or a stacked-layer structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a titanium nitride film, a two-layer structure in which a tungsten film is stacked over a tantalum nitride film or a tungsten nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order, and the like can be given. Alternatively, an alloy film containing aluminum and one or more metals selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium; or a nitride film of the alloy film may be used. 
     The gate electrode  102  can also be formed using a light-transmitting conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added. It is also possible to have a stacked-layer structure formed using the above light-transmitting conductive material and the above metal. 
     Further, an In—Ga—Zn-based oxynitride semiconductor film, an In—Sn-based oxynitride semiconductor film, an In—Ga-based oxynitride semiconductor film, an In—Zn-based oxynitride semiconductor film, a Sn-based oxynitride semiconductor film, an In-based oxynitride semiconductor film, a film of metal nitride (such as InN or ZnN), or the like may be provided between the gate electrode  102  and the insulating layer  103 . These films each have a work function higher than or equal to 5 eV or higher than or equal to 5.5 eV, which is higher than the electron affinity of the oxide semiconductor. Thus, the threshold voltage of the transistor including an oxide semiconductor can be shifted in the positive direction, and what is called a normally-off switching element can be achieved. For example, an In—Ga—Zn-based oxynitride semiconductor film having a higher nitrogen concentration than at least the oxide semiconductor layer  104 , specifically, an In—Ga—Zn-based oxynitride semiconductor film having a nitrogen concentration of 7 atomic % or higher is used. 
     &lt;&lt;Insulating Layer  103 &gt;&gt; 
     The insulating layer  103  functions as a gate insulating film. The insulating layer  103  in contact with the bottom surface of the oxide semiconductor layer  104  is preferably an amorphous film. 
     The insulating layer  103  may be formed to have a single-layer structure or a stacked-layer structure using, for example, one or more of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, Ga—Zn-based metal oxide, silicon nitride, and the like. 
     The insulating layer  103  may be formed using a high-k material such as hafnium silicate (HfSiO x ), hafnium silicate to which nitrogen is added (HfSi x O y N z ), hafnium aluminate to which nitrogen is added (HfAl x O y N z ), hafnium oxide, or yttrium oxide, so that gate leakage current of the transistor can be reduced. 
     &lt;&lt;Pair of Electrodes  105   a  and  105   b&gt;&gt;   
     The pair of electrodes  105   a  and  105   b  functions as a source electrode and a drain electrode of the transistor. 
     The pair of electrodes  105   a  and  105   b  can be formed to have a single-layer structure or a stacked-layer structure using, as a conductive material, any of metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, or an alloy containing any of these metals. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is stacked over an aluminum film, a two-layer structure in which a titanium film is stacked over a tungsten film, a two-layer structure in which a copper film is stacked over a copper-magnesium-aluminum alloy film, a three-layer structure in which a titanium film or a titanium nitride film, an aluminum film or a copper film, and a titanium film or a titanium nitride film are stacked in this order, a three-layer structure in which a molybdenum film or a molybdenum nitride film, an aluminum film or a copper film, and a molybdenum film or a molybdenum nitride film are stacked in this order, and the like can be given. Note that a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. 
     &lt;&lt;Insulating Layer  106 ,  107 &gt;&gt; 
     The insulating layer  106  is preferably formed using an oxide insulating film containing oxygen at a higher proportion than oxygen in the stoichiometric composition. Such an oxide insulating film releases oxygen upon heating. For instance, when such an oxide insulating film is heated at a temperature that is equal to or higher than a heat treatment temperature in a manufacturing process of a transistor, the amount of released oxygen converted into oxygen atoms is greater than or equal to 1.0×10 18  atoms/cm 3 , preferably greater than or equal to 3.0×10 20  atoms/cm 3  in thermal desorption spectroscopy (TDS) analysis. 
     As the insulating layer  106 , a silicon oxide film, a silicon oxynitride film, or the like can be formed. 
     Note that the insulating layer  106  also functions as a film which relieves damage to the oxide semiconductor layer  104  at the time of forming the insulating layer  107  later. 
     An oxide film transmitting oxygen may be provided between the insulating layer  106  and the oxide semiconductor layer  104 . 
     As the oxide film transmitting oxygen, a silicon oxide film, a silicon oxynitride film, or the like can be formed. Note that in this specification, a “silicon oxynitride film” refers to a film that contains oxygen at a higher proportion than nitrogen, and a “silicon nitride oxide film” refers to a film that contains nitrogen at a higher proportion than oxygen. 
     The insulating layer  107  can be formed using an insulating film having a blocking effect against oxygen, hydrogen, water, and the like. It is possible to prevent outward diffusion of oxygen from the oxide semiconductor layer  104  and entry of hydrogen, water, or the like into the oxide semiconductor layer  104  from the outside by providing the insulating layer  107  over the insulating layer  106 . As for such an insulating film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, an yttrium oxide film, an yttrium oxynitride film, a hafnium oxide film, and a hafnium oxynitride film can be given as examples. 
     &lt;Example of Manufacturing Method of Transistor&gt; 
     Next, an example of a fabrication method of the transistor  100  illustrated in  FIGS.  9 A to  9 C  will be described. 
     First, as illustrated in  FIG.  10 A , the gate electrode  102  is formed over the substrate  101 , and the insulating layer  103  is formed over the gate electrode  102 . 
     Here, a glass substrate is used as the substrate  101 . 
     &lt;&lt;Formation of Gate Electrode&gt;&gt; 
     A formation method of the gate electrode  102  is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like and then a resist mask is formed over the conductive film using a first photomask by a photolithography process. Then, part of the conductive film is etched using the resist mask to form the gate electrode  102 . After that, the resist mask is removed. 
     Note that instead of the above formation method, the gate electrode  102  may be formed by an electrolytic plating method, a printing method, an ink-jet method, or the like. 
     &lt;&lt;Formation of Gate Insulating Layer&gt;&gt; 
     The insulating layer  103  is formed by a sputtering method, a CVD method, an evaporation method, or the like. 
     In the case where the insulating layer  103  is formed using a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples. 
     In the case of forming a silicon nitride film as the insulating layer  103 , it is preferable to use a two-step formation method. First, a first silicon nitride film with a small number of defects is formed by a plasma CVD method in which a mixed gas of silane, nitrogen, and ammonia is used as a source gas. Then, a second silicon nitride film in which the hydrogen concentration is low and hydrogen can be blocked is formed by switching the source gas to a mixed gas of silane and nitrogen. With such a formation method, a silicon nitride film with a small number of defects and a blocking property against hydrogen can be formed as the insulating layer  103 . 
     Moreover, in the case of forming a gallium oxide film as the insulating layer  103 , a metal organic chemical vapor deposition (MOCVD) method can be employed. 
     &lt;&lt;Formation of Oxide Semiconductor Layer&gt;&gt; 
     Next, as illustrated in  FIG.  10 B , the oxide semiconductor layer  104  is formed over the insulating layer  103 . 
     A formation method of the oxide semiconductor layer  104  is described below. First, an oxide semiconductor film is formed using the method described in Embodiment 1. Then, a resist mask is formed over the oxide semiconductor film using a second photomask by a photolithography process. Then, part of the oxide semiconductor film is etched using the resist mask to form the oxide semiconductor layer  104 . After that, the resist mask is removed. 
     After that, heat treatment may be performed. In such a case, the heat treatment is preferably performed under an atmosphere containing oxygen. 
     &lt;&lt;Formation of Pair of Electrodes&gt;&gt; 
     Next, as illustrated in  FIG.  10 C , the pair of electrodes  105   a  and  105   b  is formed. 
     A formation method of the pair of electrodes  105   a  and  105   b  is described below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, or the like. Then, a resist mask is formed over the conductive film using a third photomask by a photolithography process. Then, part of the conductive film is etched using the resist mask to form the pair of electrodes  105   a  and  105   b . After that, the resist mask is removed. 
     Note that as illustrated in  FIG.  10 B , an upper part of the oxide semiconductor layer  104  is in some cases partly etched and thinned by the etching of the conductive film. For this reason, the oxide semiconductor layer  104  is preferably formed thick. 
     &lt;&lt;Formation of Insulating Layer&gt;&gt; 
     Next, as illustrated in  FIG.  10 D , the insulating layer  106  is formed over the oxide semiconductor layer  104  and the pair of electrodes  105   a  and  105   b , and the insulating layer  107  is successively formed over the insulating layer  106 . 
     In the case where the insulating layer  106  is formed using a silicon oxide film or a silicon oxynitride film, a deposition gas containing silicon and an oxidizing gas are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples. 
     For example, a silicon oxide film or a silicon oxynitride film is formed under the conditions as follows: the substrate placed in a vacuum-evacuated treatment chamber of a plasma CVD apparatus is held at a temperature higher than or equal to 180° C. and lower than or equal to 260° C., preferably higher than or equal to 200° C. and lower than or equal to 240° C., to the treatment chamber is charged a source gas at a pressure greater than or equal to 100 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 200 Pa, and high-frequency power higher than or equal to 0.17 W/cm 2  and lower than or equal to 0.5 W/cm 2 , preferably higher than or equal to 0.25 W/cm 2  and lower than or equal to 0.35 W/cm 2  is supplied to an electrode provided in the treatment chamber. 
     With the application of the high-frequency power, the degradation efficiency of the source gas in plasma is increased, oxygen radicals are increased, and oxidation of the source gas is promoted; therefore, oxygen is contained in the oxide insulating film at a higher proportion than oxygen in the stoichiometric composition. However, the films prepared at the aforementioned substrate temperature release part of oxygen therein upon heating performed in later processes. Thus, it is possible to form an oxide insulating film which contains oxygen at a higher proportion than oxygen in the stoichiometric composition and from which part of oxygen is released by heating. 
     Further, in the case of providing an oxide insulating film between the oxide semiconductor layer  104  and the insulating layer  106 , the oxide insulating film serves as a protective film of the oxide semiconductor layer  104  in the steps of forming the insulating layer  106 . Thus, the insulating layer  106  can be formed using the high-frequency power having a high power density while damage to the oxide semiconductor layer  104  is reduced. 
     For example, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film under the conditions as follows: the substrate placed in a vacuum-evacuated treatment chamber of a plasma CVD apparatus is held at a temperature higher than or equal to 180° C. and lower than or equal to 400° C., preferably higher than or equal to 200° C. and lower than or equal to 370° C., to the treatment chamber is charged a source gas at a pressure greater than or equal to 20 Pa and less than or equal to 250 Pa, preferably greater than or equal to 100 Pa and less than or equal to 250 Pa, and high-frequency power is supplied to an electrode provided in the treatment chamber. Further, when the pressure in the treatment chamber is greater than or equal to 100 Pa and less than or equal to 250 Pa, damage to the oxide semiconductor layer  104  can be reduced. 
     A deposition gas containing silicon and an oxidizing gas are preferably used as a source gas of the oxide insulating film. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples. 
     The insulating layer  107  can be formed by a sputtering method, a CVD method, or the like. 
     In the case where the insulating layer  107  is formed using a silicon nitride film or a silicon nitride oxide film, a deposition gas containing silicon, an oxidizing gas, and a gas containing nitrogen are preferably used as a source gas. Typical examples of the deposition gas containing silicon include silane, disilane, trisilane, and silane fluoride. As the oxidizing gas, oxygen, ozone, dinitrogen monoxide, and nitrogen dioxide can be given as examples. As the gas containing nitrogen, nitrogen and ammonia can be given as examples. 
     Through the above process, the transistor  100  can be formed. 
     &lt;Modification Example of Transistor  100 &gt; 
     A structural example of a transistor, which is partly different from the transistor  100 , will be described below. 
     Modification Example 1 
       FIG.  9 B  is a schematic cross-sectional view of a transistor  110  described as an example below. The transistor  110  is different from the transistor  100  in the structure of an oxide semiconductor layer. Note that descriptions of components having structures or functions similar to those of the other structural examples, which are denoted by the same reference numerals, are omitted below. 
     In an oxide semiconductor layer  114  included in the transistor  110 , an oxide semiconductor layer  114   a  and an oxide semiconductor layer  114   b  are stacked. 
     Since a boundary between the oxide semiconductor layer  114   a  and the oxide semiconductor layer  114   b  is unclear in some cases, the boundary is shown by a dashed line in  FIG.  9 B  and the like. 
     The oxide semiconductor film of one embodiment of the present invention can be applied to one or both of the oxide semiconductor layers  114   a  and  114   b.    
     Typical examples of a material that can be used for the oxide semiconductor layer  114   a  are an In—Ga oxide, an In—Zn oxide, and an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). In the case of using an In-M-Zn oxide for the oxide semiconductor layer  114   a , when summation of In and M is assumed to be 100 atomic % and Zn and oxygen are eliminated from consideration, the proportions of In and M are preferably greater than or equal to 25 atomic % and less than 75 atomic %, respectively, and further preferably greater than or equal to 34 atomic % and less than 66 atomic %, respectively. Further, a material having an energy gap of 2 eV or more, preferably 2.5 eV or more, further preferably 3 eV or more is used for the oxide semiconductor layer  114   a , for example. 
     For example, the oxide semiconductor layer  114   b  contains In or Ga and typically contains an In—Ga oxide, an In—Zn oxide, or In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf). In addition, energy level of the conduction band minimum of the oxide semiconductor layer  114   b  is closer to the vacuum level than that of the oxide semiconductor layer  114   a  is. The difference between energy level of the conduction band minimum of the oxide semiconductor layer  114   b  and energy level of the conduction band minimum of the oxide semiconductor layer  114   a  is preferably 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. 
     When an In-M-Zn oxide is used as the oxide semiconductor layer  114   b , for example, the atomic ratio between In and M is preferably as follows: the atomic percentage of In is less than 50 atomic % and the atomic percentage of M is greater than or equal to 50 atomic %; further preferably, the atomic percentage of In is less than 25 atomic % and the atomic percentage of M is greater than or equal to 75 atomic %, where summation of In and M is assumed to be 100 atomic % and Zn and oxygen are eliminated from consideration. 
     For the oxide semiconductor layer  114   a , an In—Ga—Zn oxide containing In, Ga, and Zn at an atomic ratio of 1:1:1 or 3:1:2 can be used, for example. Further, for the oxide semiconductor layer  114   b , an In—Ga—Zn oxide containing In, Ga, and Zn at an atomic ratio of 1:3:2, 1:6:4, or 1:9:6 can be used. Note that the atomic ratios of the oxide semiconductor layers  114   a  and  114   b  can be different from those of the used targets in some cases and there could be a difference of ±20% therebetween. 
     When an oxide containing a large amount of Ga that serves as a stabilizer is used for the oxide semiconductor layer  114   b  provided over the oxide semiconductor layer  114   a , oxygen can be prevented from being released from the oxide semiconductor layers  114   a  and  114   b.    
     Note that, without limitation to the compositions and materials described above, a material with an appropriate composition may be used depending on required semiconductor characteristics and electrical characteristics (e.g., field-effect mobility and threshold voltage) of a transistor. Further, in order to obtain required semiconductor characteristics of a transistor, it is preferable that the carrier density, the impurity concentration, the defect density, the atomic ratio of a metal element to oxygen, the interatomic distance, the density, and the like of the oxide semiconductor layers  114   a  and  114   b  be set to be appropriate. 
     Although a structure in which two oxide semiconductor layers are stacked is described above as an example of the oxide semiconductor layer  114 , a structure in which three or more oxide semiconductor layers are stacked can also be employed. 
     Modification Example 2 
       FIG.  9 C  is a schematic cross-sectional view of a transistor  120  described as an example below. The transistor  120  is different in the structure of an oxide semiconductor layer from the transistor  100  and the transistor  110 . 
     In an oxide semiconductor layer  124  included in the transistor  120 , an oxide semiconductor layer  124   a , an oxide semiconductor layer  124   b , and an oxide semiconductor layer  124   c  are stacked in this order. 
     The oxide semiconductor layers  124   a  and  124   b  are stacked over the insulating layer  103 . The oxide semiconductor layer  124   c  is provided in contact with the top surface of the oxide semiconductor layer  124   b  and the top surfaces and side surfaces of the pair of electrodes  105   a  and  105   b.    
     The oxide semiconductor film of one embodiment of the present invention can be applied to at least one of the oxide semiconductor layers  124   a ,  124   b , and  124   c.    
     The oxide semiconductor layer  124   b  can have a structure which is similar to that of the oxide semiconductor layer  114   a  described as an example in Modification Example 1, for example. Further, the oxide semiconductor layers  124   a  and  124   c  can each have a structure which is similar to that of the oxide semiconductor layer  114   b  described as an example in Modification Example 1, for example 
     When an oxide containing a large amount of Ga that serves as a stabilizer is used for the oxide semiconductor layer  124   a  and the oxide semiconductor layer  124   c , for example, oxygen can be prevented from being released from the oxide semiconductor layer  124   a , the oxide semiconductor layer  124   b , and the oxide semiconductor layer  124   c.    
     In the case where a channel is mainly formed in the oxide semiconductor layer  124   b , for example, an oxide containing a large amount of In can be used for the oxide semiconductor layer  124   b  and the pair of electrodes  105   a  and  105   b  is provided in contact with the oxide semiconductor layer  124   b ; thus, the on-state current of the transistor  120  can be increased. 
     &lt;Another Structure Example of Transistor&gt; 
     A structure example of a top-gate transistor to which the oxide semiconductor film of one embodiment of the present invention can be applied will be described below. 
     «Structural Example&gt;&gt; 
       FIG.  11 A  is a schematic cross-sectional view of a top-gate transistor  150  which will be described below as an example. 
     The transistor  150  includes the oxide semiconductor layer  104  provided over the substrate  101  on which an insulating layer  151  is provided, the pair of electrodes  105   a  and  105   b  in contact with the top surface of the oxide semiconductor layer  104 , the insulating layer  103  provided over the oxide semiconductor layer  104  and the pair of electrodes  105   a  and  105   b , and the gate electrode  102  provided over the insulating layer  103  to overlap with the oxide semiconductor layer  104 . Further, an insulating layer  152  is provided to cover the insulating layer  103  and the gate electrode  102 . 
     The oxide semiconductor film of one embodiment of the present invention can be applied to the oxide semiconductor layer  104  in the transistor  150 . 
     The insulating layer  151  has a function of suppressing diffusion of impurities from the substrate  101  to the oxide semiconductor layer  104 . For example, a structure similar to that of the insulating layer  107  can be employed. Note that the insulating layer  151  is not necessarily provided. 
     The insulating layer  152  can be formed using an insulating film having a blocking effect against oxygen, hydrogen, water, and the like in a manner similar to that of the insulating layer  107 . Note that the insulating layer  107  is not necessarily provided. 
     Modification Example 
     A structural example of a transistor, which is partly different from the transistor  150 , will be described below. 
       FIG.  11 B  is a schematic cross-sectional view of a transistor  160  described as an example below. The structure of an oxide semiconductor layer in the transistor  160  is different from that in the transistor  150 . 
     In an oxide semiconductor layer  164  included in the transistor  160 , an oxide semiconductor layer  164   a , an oxide semiconductor layer  164   b , and an oxide semiconductor layer  164   c  are stacked in this order. 
     The oxide semiconductor film of one embodiment of the present invention can be applied to at least one of the oxide semiconductor layer  164   a , the oxide semiconductor layer  164   b , and the oxide semiconductor layer  164   c.    
     The oxide semiconductor layer  164   b  can have a structure which is similar to that of the oxide semiconductor layer  114   a  described as an example in Modification Example 1, for example. Further, the oxide semiconductor layers  164   a  and  164   c  can each have a structure which is similar to that of the oxide semiconductor layer  114   b  described as an example in Modification Example 1, for example. 
     An oxide containing a large amount of Ga that serves as a stabilizer is used for the oxide semiconductor layer  164   a  and the oxide semiconductor layer  164   c ; thus, oxygen can be prevented from being released from the oxide semiconductor layer  164   a , the oxide semiconductor layer  164   b , and the oxide semiconductor layer  164   c.    
     The oxide semiconductor layer  164  can be formed in the following manner: the oxide semiconductor layer  164   c  and the oxide semiconductor layer  164   b  are obtained by etching, so that an oxide semiconductor film to be the oxide semiconductor layer  164   a  is exposed; and the oxide semiconductor film is processed into the oxide semiconductor layer  164   a  by a dry etching method. In that case, a reaction product of the oxide semiconductor film is attached to side surfaces of the oxide semiconductor layers  164   b  and  164   c  to form a sidewall protective layer (also referred to as a rabbit ear) in some cases. Note that the reaction product is attached by a sputtering phenomenon or at the time of the dry etching. 
       FIG.  11 C  is a schematic cross-sectional view of a transistor  161  in which a sidewall protective layer  164   d  is formed as a side surface of the oxide semiconductor layer  164  in the above manner. Note that the other components of the transistor  161  are the same as those of the transistor  160 . 
     The sidewall protective layer  164   d  mainly contains the same material as the oxide semiconductor layer  164   a . In some cases, the sidewall protective layer  164   d  contains the constituent (e.g., silicon) of a layer provided below the oxide semiconductor layer  164   a  (the insulating layer  151  here). 
     With a structure in which a side surface of the oxide semiconductor layer  164   b  is covered with the sidewall protective layer  164   d  so as not to be in contact with the pair of electrodes  105   a  and  105   b  as illustrated in  FIG.  11 C , unintended leakage current of the transistor in an off state can be reduced particularly when a channel is mainly formed in the oxide semiconductor layer  164   b ; thus, a transistor having favorable off-state characteristics can be fabricated. Further, when a material containing a large amount of Ga that serves as a stabilizer is used for the sidewall protective layer  164   d , oxygen can be effectively prevented from being released from the side surface of the oxide semiconductor layer  164   b ; thus, a transistor having excellent stability of electric characteristics can be fabricated. 
     This embodiment can be implemented in combination with Embodiment described in this specification as appropriate. 
     Embodiment 3 
     In this embodiment, a structure of a display panel of one embodiment of the present invention will be described with reference to  FIGS.  12 A to  12 C . 
       FIG.  12 A  is a top view of the display panel of one embodiment of the present invention.  FIG.  12 B  illustrates a pixel circuit that can be used in the case where a liquid crystal element is used in a pixel in the display panel of one embodiment of the present invention.  FIG.  12 C  illustrates a pixel circuit that can be used in the case where an organic EL element is used in a pixel in the display panel of one embodiment of the present invention. 
     The transistor in the pixel portion can be formed in accordance with Embodiment 2. Further, the transistor can be easily formed as an n-channel transistor, and thus part of a driver circuit that can be formed using an n-channel transistor can be formed over the same substrate as the transistor of the pixel portion. With the use of the transistor described in Embodiment 2 for the pixel portion or the driver circuit in this manner, a highly reliable display device can be provided. 
       FIG.  12 A  illustrates an example of a block diagram of an active matrix display device. A pixel portion  501 , a first scan line driver circuit  502 , a second scan line driver circuit  503 , and a signal line driver circuit  504  are provided over a substrate  500  in the display device. In the pixel portion  501 , a plurality of signal lines extended from the signal line driver circuit  504  are arranged and a plurality of scan lines extended from the first scan line driver circuit  502  and the second scan line driver circuit  503  are arranged. Note that pixels which include display elements are provided in a matrix in respective regions where the scan lines and the signal lines intersect with each other. The substrate  500  of the display device is connected to a timing control circuit (also referred to as a controller or a controller IC) through a connection portion such as a flexible printed circuit (FPC). 
     In  FIG.  12 A , the first scan line driver circuit  502 , the second scan line driver circuit  503 , and the signal line driver circuit  504  are formed over the same substrate  500  as the pixel portion  501 . Accordingly, the number of components which are provided outside, such as a drive circuit, can be reduced, so that a reduction in cost can be achieved. Further, in the case where the driver circuit is provided outside the substrate  500 , wirings would need to be extended and the number of connections of wirings would be increased, but when the driver circuit is provided over the substrate  500 , the number of connections of the wirings can be reduced. Consequently, an improvement in reliability or yield can be achieved. 
     &lt;Liquid Crystal Panel&gt; 
       FIG.  12 B  illustrates an example of a circuit configuration of the pixel. Here, a pixel circuit which is applicable to a pixel of a VA liquid crystal display panel is illustrated. 
     This pixel circuit can be applied to a structure in which one pixel includes a plurality of pixel electrode layers. The pixel electrode layers are connected to different transistors, and the transistors can be driven with different gate signals. Accordingly, signals applied to individual pixel electrode layers in a multi-domain pixel can be controlled independently. 
     A gate wiring  512  of a transistor  516  and a gate wiring  513  of a transistor  517  are separated so that different gate signals can be supplied thereto. In contrast, a source or drain electrode  514  functioning as a data line is shared by the transistors  516  and  517 . The transistor described in Embodiment 2 can be used as appropriate as each of the transistors  516  and  517 . Thus, a highly reliable liquid crystal display panel can be provided. 
     The shapes of a first pixel electrode layer electrically connected to the transistor  516  and a second pixel electrode layer electrically connected to the transistor  517  are described. The first pixel electrode layer and the second pixel electrode layer are separated by a slit. The first pixel electrode layer has a V shape and the second pixel electrode layer is provided so as to surround the first pixel electrode layer. 
     A gate electrode of the transistor  516  is connected to the gate wiring  512 , and a gate electrode of the transistor  517  is connected to the gate wiring  513 . When different gate signals are supplied to the gate wiring  512  and the gate wiring  513 , operation timings of the transistor  516  and the transistor  517  can be varied. As a result, alignment of liquid crystals can be controlled. 
     Further, a storage capacitor may be formed using a capacitor wiring  510 , a gate insulating film functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode layer or the second pixel electrode layer. 
     The multi-domain pixel includes a first liquid crystal element  518  and a second liquid crystal element  519 . The first liquid crystal element  518  includes the first pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. The second liquid crystal element  519  includes the second pixel electrode layer, a counter electrode layer, and a liquid crystal layer therebetween. 
     Note that a pixel circuit of the present invention is not limited to that shown in  FIG.  12 B . For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be added to the pixel illustrated in  FIG.  12 B . 
     &lt;Organic EL Panel&gt; 
       FIG.  12 C  illustrates another example of a circuit configuration of the pixel portion. Here, a pixel structure of a display panel using an organic EL element is shown. 
     In an organic EL element, by application of voltage to a light-emitting element, electrons are injected from one of a pair of electrodes and holes are injected from the other of the pair of electrodes, into a layer containing a light-emitting organic compound; thus, current flows. The electrons and holes are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element. 
       FIG.  12 C  illustrates an applicable example of a pixel circuit. Here, one pixel includes two n-channel transistors. Note that the metal oxide film of one embodiment of the present invention can be used for channel formation regions of the n-channel transistors. Further, digital time grayscale driving can be employed for the pixel circuit. 
     The configuration of the applicable pixel circuit and operation of a pixel employing digital time grayscale driving will be described. 
     A pixel  520  includes a switching transistor  521 , a driver transistor  522 , a light-emitting element  524 , and a capacitor  523 . A gate electrode layer of the switching transistor  521  is connected to a scan line  526 , a first electrode (one of a source electrode layer and a drain electrode layer) of the switching transistor  521  is connected to a signal line  525 , and a second electrode (the other of the source electrode layer and the drain electrode layer) of the switching transistor  521  is connected to a gate electrode layer of the driver transistor  522 . The gate electrode layer of the driver transistor  522  is connected to a power supply line  527  through the capacitor  523 , a first electrode of the driver transistor  522  is connected to the power supply line  527 , and a second electrode of the driver transistor  522  is connected to a first electrode (a pixel electrode) of the light-emitting element  524 . A second electrode of the light-emitting element  524  corresponds to a common electrode  528 . The common electrode  528  is electrically connected to a common potential line provided over the same substrate. 
     As the switching transistor  521  and the driver transistor  522 , the transistor described in Embodiment 2 can be used as appropriate. In this manner, a highly reliable organic EL display panel can be provided. 
     The potential of the second electrode (the common electrode  528 ) of the light-emitting element  524  is set to be a low power supply potential. Note that the low power supply potential is lower than a high power supply potential supplied to the power supply line  527 . For example, the low power supply potential can be GND, 0V, or the like. The high power supply potential and the low power supply potential are set to be higher than or equal to the forward threshold voltage of the light-emitting element  524 , and the difference between the potentials is applied to the light-emitting element  524 , whereby current is supplied to the light-emitting element  524 , leading to light emission. The forward voltage of the light-emitting element  524  refers to a voltage at which a desired luminance is obtained, and is at least higher than a forward threshold voltage. 
     Note that gate capacitance of the driver transistor  522  may be used as a substitute for the capacitor  523 , so that the capacitor  523  can be omitted. The gate capacitance of the driver transistor  522  may be formed between the channel formation region and the gate electrode layer. 
     Next, a signal input to the driver transistor  522  is described. In the case of a voltage-input voltage driving method, a video signal for turning on or off the driver transistor  522  without fail is input to the driver transistor  522 . In order for the driver transistor  522  to operate in a linear region, voltage higher than the voltage of the power supply line  527  is applied to the gate electrode layer of the driver transistor  522 . Note that voltage higher than or equal to voltage which is the sum of power supply line voltage and the threshold voltage Vth of the driver transistor  522  is applied to the signal line  525 . 
     In the case of performing analog grayscale driving, a voltage greater than or equal to a voltage which is the sum of the forward voltage of the light-emitting element  524  and the threshold voltage Vth of the driver transistor  522  is applied to the gate electrode layer of the driver transistor  522 . A video signal by which the driver transistor  522  is operated in a saturation region is input, so that current is supplied to the light-emitting element  524 . In order for the driver transistor  522  to operate in a saturation region, the potential of the power supply line  527  is set higher than the gate potential of the driver transistor  522 . When an analog video signal is used, it is possible to supply current to the light-emitting element  524  in accordance with the video signal and perform analog grayscale driving. 
     Note that the configuration of the pixel circuit of the present invention is not limited to that shown in  FIG.  12 C . For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit illustrated in  FIG.  12 C . 
     Embodiment 4 
     In this embodiment, structures of a semiconductor device including the metal oxide film of one embodiment of the present invention and electronic devices will be described with reference to  FIG.  13    and  FIGS.  14 A to  14 D . 
       FIG.  13    is a block diagram of an electronic device including the semiconductor device to which the metal oxide film of one embodiment of the present invention is applied. 
       FIGS.  14 A to  14 D  are external views of electronic devices each including the semiconductor device to which the metal oxide film of one embodiment of the present invention is applied. 
     An electronic device illustrated in  FIG.  13    includes an RF circuit  901 , an analog baseband circuit  902 , a digital baseband circuit  903 , a battery  904 , a power supply circuit  905 , an application processor  906 , a flash memory  910 , a display controller  911 , a memory circuit  912 , a display  913 , a touch sensor  919 , an audio circuit  917 , a keyboard  918 , and the like. 
     The application processor  906  includes a CPU  907 , a DSP  908 , and an interface (IF)  909 . Moreover, the memory circuit  912  can include an SRAM or a DRAM. 
     The transistor described in Embodiment 2 is applied to the memory circuit  912 , whereby a highly reliable electronic device which can write and read data can be provided. 
     The transistor described in Embodiment 2 is applied to a register or the like included in the CPU  907  or the DSP  908 , whereby a highly reliable electronic device which can write and read data can be provided. 
     Note that in the case where the off-state leakage current of the transistor described in Embodiment 2 is extremely small, the memory circuit  912  can store data for a long time and can have sufficiently reduced power consumption. Moreover, the CPU  907  or the DSP  908  can store the state before power gating in a register or the like during a period in which the power gating is performed. 
     Further, the display  913  includes a display portion  914 , a source driver  915 , and a gate driver  916 . 
     The display portion  914  includes a plurality of pixels arranged in a matrix. The pixel includes a pixel circuit, and the pixel circuit is electrically connected to the gate driver  916 . 
     The transistor described in Embodiment 2 can be used as appropriate in the pixel circuit or the gate driver  916 . Accordingly, a highly reliable display can be provided. 
     Examples of electronic devices are a television set (also referred to as a television or a television receiver), a monitor of a computer or the like, a camera such as a digital camera or a digital video camera, a digital photo frame, a mobile phone handset (also referred to as a mobile phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproducing device, a large-sized game machine such as a pachinko machine, and the like. 
       FIG.  14 A  illustrates a portable information terminal, which includes a main body  1001 , a housing  1002 , a display portion  1003   a , a display portion  1003   b , and the like. The display portion  1003   b  includes a touch panel. By touching a keyboard button  1004  displayed on the display portion  1003   b , screen operation can be carried out, and text can be input. Needless to say, the display portion  1003   a  may functions as a touch panel. A liquid crystal panel or an organic light-emitting panel is fabricated by using the transistor described in Embodiment 2 as a switching element and applied to the display portion  1003   a  or  1003   b , whereby a highly reliable portable information terminal can be provided. 
     The portable information terminal illustrated in  FIG.  14 A  can have a function of displaying a variety of kinds of data (e.g., a still image, a moving image, and a text image), a function of displaying a calendar, a date, the time, or the like on the display portion, a function of operating or editing data displayed on the display portion, a function of controlling processing by a variety of kinds of software (programs), and the like. Further, an external connection terminal (an earphone terminal, a USB terminal, or the like), a recording medium insertion portion, or the like may be provided on the back surface or the side surface of the housing. 
     The portable information terminal illustrated in  FIG.  14 A  may transmit and receive data wirelessly. Through wireless communication, desired book data or the like can be purchased and downloaded from an electronic book server. 
       FIG.  14 B  illustrates a portable music player including, in a main body  1021 , a display portion  1023 , a fixing portion  1022  with which the portable music player can be worn on the ear, a speaker, an operation button  1024 , an external memory slot  1025 , and the like. A liquid crystal panel or an organic light-emitting panel is fabricated by using the transistor described in Embodiment 2 as a switching element and applied to the display portion  1023 , whereby a highly reliable portable music player can be provided. 
     Furthermore, when the portable music player illustrated in  FIG.  14 B  has an antenna, a microphone function, or a wireless communication function and is used with a mobile phone, a user can talk on the phone wirelessly in a hands-free way while driving a car or the like. 
       FIG.  14 C  illustrates a mobile phone which includes two housings, a housing  1030  and a housing  1031 . The housing  1031  includes a display panel  1032 , a speaker  1033 , a microphone  1034 , a pointing device  1036 , a camera lens  1037 , an external connection terminal  1038 , and the like. The housing  1030  is provided with a solar cell  1040  for charging the mobile phone, an external memory slot  1041 , and the like. In addition, an antenna is incorporated in the housing  1031 . The transistor described in Embodiment 2 is applied to the display panel  1032 , whereby a highly reliable mobile phone can be provided. 
     Further, the display panel  1032  includes a touch panel. A plurality of operation keys  1035  which are displayed as images are indicated by dotted lines in  FIG.  14 C . Note that a boosting circuit by which a voltage output from the solar cell  1040  is increased so as to be sufficiently high for each circuit is also included. 
     For example, a power transistor used for a power supply circuit such as a boosting circuit can also be formed when the metal oxide film of the transistor described in the Embodiment 2 has a thickness greater than or equal to 2 μm and less than or equal to 50 μm. 
     In the display panel  1032 , the direction of display is changed as appropriate depending on the application mode. Further, the mobile phone is provided with the camera lens  1037  on the same surface as the display panel  1032 , and thus it can be used as a video phone. The speaker  1033  and the microphone  1034  can be used for videophone calls, recording, and playing sound, and the like as well as voice calls. Moreover, the housings  1030  and  1031  in a state where they are developed as illustrated in  FIG.  14 C  can shift, by sliding, to a state where one is lapped over the other. Therefore, the size of the mobile phone can be reduced, which makes the mobile phone suitable for being carried around. 
     The external connection terminal  1038  can be connected to an AC adaptor and a variety of cables such as a USB cable, whereby charging and data communication with a personal computer or the like are possible. Further, by inserting a recording medium into the external memory slot  1041 , a larger amount of data can be stored and moved. 
     Further, in addition to the above functions, an infrared communication function, a television reception function, or the like may be provided. 
       FIG.  14 D  illustrates an example of a television set. In a television set  1050 , a display portion  1053  is incorporated in a housing  1051 . Images can be displayed on the display portion  1053 . Moreover, a CPU is incorporated in a stand  1055  for supporting the housing  1051 . The transistor described in Embodiment 2 is applied to the display portion  1053  and the CPU, whereby the television set  1050  can be highly reliable. 
     The television set  1050  can be operated with an operation switch of the housing  1051  or a separate remote controller. Further, the remote controller may be provided with a display portion for displaying data output from the remote controller. 
     Note that the television set  1050  is provided with a receiver, a modem, and the like. With the use of the receiver, the television set  1050  can receive general TV broadcasts. Moreover, when the television set  1050  is connected to a communication network with or without wires via the modem, one-way (from a sender to a receiver) or two-way (between a sender and a receiver or between receivers) information communication can be performed. 
     Further, the television set  1050  is provided with an external connection terminal  1054 , a storage medium recording and reproducing portion  1052 , and an external memory slot. The external connection terminal  1054  can be connected to various types of cables such as a USB cable, whereby data communication with a personal computer or the like is possible. A disk storage medium is inserted into the storage medium recording and reproducing portion  1052 , and reading data stored in the storage medium and writing data to the storage medium can be performed. In addition, an image, a video, or the like stored as data in an external memory  1056  inserted into the external memory slot can be displayed on the display portion  1053 . 
     Further, in the case where the off-state leakage current of the transistor described in Embodiment 2 is extremely small, when the transistor is applied to the external memory  1056  or the CPU, the television set  1050  can have high reliability and sufficiently reduced power consumption. 
     EXPLANATION OF REFERENCE 
     
         
           100 : transistor,  101 : substrate,  102 : gate electrode,  103 : insulating layer,  104 : oxide semiconductor layer,  105   a : electrode,  105   b : electrode,  106 : insulating layer,  107 : insulating layer,  110 : transistor,  114 : oxide semiconductor layer,  114   a : oxide semiconductor layer,  114   b : oxide semiconductor layer,  120 : transistor,  124 : oxide semiconductor layer,  124   a : oxide semiconductor layer,  124   b : oxide semiconductor layer,  124   c : oxide semiconductor layer,  150 : transistor,  151 : insulating layer,  152 : insulating layer,  160 : transistor,  161 : transistor,  164 : oxide semiconductor layer,  164   a : oxide semiconductor layer,  164   b : oxide semiconductor layer,  164   c : oxide semiconductor layer,  164   d : sidewall protective layer,  200 : quartz glass substrate,  202 : dummy substrate,  204 : metal oxide film,  210   a : region,  210   b : region,  500 : substrate,  501 : pixel portion,  502 : scan line driver circuit,  503 : scan line driver circuit,  504 : signal line driver circuit,  510 : capacitor wiring,  512 : gate wiring,  513 : gate wiring,  514 : drain electrode,  516 : transistor,  517 : transistor,  518 : liquid crystal element,  519 : liquid crystal element,  520 : pixel,  521 : switching transistor,  522 : driver transistor,  523 : capacitor,  524 : light-emitting element,  525 : signal line,  526 : scan line,  527 : power supply line,  528 : common electrode,  901 : RF circuit,  902 : analog baseband circuit,  903 : digital baseband circuit,  904 : battery,  905 : power supply circuit,  906 : application processor,  907 : CPU,  908 : DSP,  910 : flash memory,  911 : display controller,  912 : memory circuit,  913 : display,  914 : display portion,  915 : source driver,  916 : gate driver,  917 : audio circuit,  918 : keyboard,  919 : touch sensor,  1001 : main body,  1002 : housing,  1003   a : display portion,  1003   b : display portion,  1004 : keyboard button,  1021 : main body,  1022 : fixing portion,  1023 : display portion,  1024 : operation button,  1025 : external memory slot,  1030 : housing,  1031 : housing,  1032 : display panel,  1033 : speaker,  1034 : microphone,  1035 : operation key,  1036 : pointing device,  1037 : camera lens,  1038 : external connection terminal,  1040 : solar cell,  1041 : external memory slot,  1050 : television set,  1051 : housing,  1052 : storage medium recording and reproducing portion,  1053 : display portion,  1054 : external connection terminal,  1055 : stand, and  1056 : external memory. 
       
    
     This application is based on Japanese Patent Application serial no. 2012-245992 filed with Japan Patent Office on Nov. 8, 2012, Japanese Patent Application serial no. 2013-016242 filed with Japan Patent Office on Jan. 30, 2013, and Japanese Patent Application serial no. 2013-056768 filed with Japan Patent Office on Mar. 19, 2013, the entire contents of which are hereby incorporated by reference.