Patent Publication Number: US-10784894-B2

Title: Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 4/15 and 256-symbol mapping, and bit interleaving method using same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of and claims priority to U.S. application Ser. No. 15/612,972 filed Jun. 2, 2017, which is a continuation of and claims priority to U.S. application Ser. No. 14/718,839 filed May 21, 2015 (now U.S. Pat. No. 9,698,826 issued Jul. 4, 2017), which claims the benefit of Korean Patent Application No. 10-2015-0023862, filed Feb. 17, 2015, which are hereby incorporated by reference herein in their entirety. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates generally to an interleaver and, more particularly, to a bit interleaver that is capable of distributing burst errors occurring in a digital broadcast channel. 
     2. Description of the Related Art 
     Bit-Interleaved Coded Modulation (BICM) is bandwidth-efficient transmission technology, and is implemented in such a manner that an error-correction coder, a bit-by-bit interleaver and a high-order modulator are combined with one another. 
     BICM can provide excellent performance using a simple structure because it uses a low-density parity check (LDPC) coder or a Turbo coder as the error-correction coder. Furthermore, BICM can provide high-level flexibility because it can select modulation order and the length and code rate of an error correction code in various forms. Due to these advantages, BICM has been used in broadcasting standards, such as DVB-T2 and DVB-NGH, and has a strong possibility of being used in other next-generation broadcasting systems. 
     However, in spite of those advantages, BICM suffers from the rapid degradation of performance unless burst errors occurring in a channel are appropriately distributed via the bit-by-bit interleaver. Accordingly, the bit-by-bit interleaver used in BICM should be designed to be optimized for the modulation order or the length and code rate of the error correction code. 
     SUMMARY 
     At least one embodiment of the present invention is directed to the provision of an intra-BICM bit interleaver that can effectively distribute burst errors occurring in a broadcasting system channel. 
     At least one embodiment of the present invention is directed to the provision of a bit interleaver that is optimized for an LDPC coder having a length of 16200 and a code rate of 4/15 and a modulator performing 256-symbol mapping and, thus, can be applied to next-generation broadcasting systems, such as ATSC 3.0. 
     In accordance with an aspect of the present invention, there is provided a bit interleaver, including a first memory configured to store a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 4/15; a processor configured to generate an interleaved codeword by interleaving the LDPC codeword on a bit group basis, the size of the bit group corresponding to a parallel factor of the LDPC codeword; and a second memory configured to provide the interleaved codeword to a modulator for 256-symbol mapping. 
     The 256-symbol mapping may be NUC (Non-Uniform Constellation) symbol mapping corresponding to 256 constellations (symbols). 
     The parallel factor may be 360, and each of the bit groups may include 360 bits. 
     The LDPC codeword may be represented by (u 0 , u 1 , . . . , u N     lpdc     −1 ) (where N ldpc  is 16200), and may be divided into 45 bit groups each including 360 bits, as in the following equation:
 
 X   j   ={u   k |360× j≤k&lt; 360×( j+ 1), 0≤ k&lt;N   ldpc } for 0≤ j&lt;N   group  
 
where X j  is an j-th bit group, N ldpc  is 16200, and N group  is 45.
 
     The interleaving may be performed using the following equation using permutation order:
 
 Y   j   =X   π(j)  0≤ j≤N   group  
 
where X j  is the j-th bit group, Y j  is an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving (bit group-unit interleaving).
 
     The permutation order may correspond to an interleaving sequence represented by the following equation:
 
interleaving sequence={38 20 0 34 33 41 14 30 44 7 37 8 4 9 43 15 19 32 23 5 22 26 10 12 3 31 36 21 24 11 16 18 17 29 35 42 13 40 1 28 2 25 6 39 27}
 
     In accordance with another aspect of the present invention, there is provided a bit interleaving method, including storing an LDPC codeword having a length of 16200 and a code rate of 4/15; generating an interleaved codeword by interleaving the LDPC codeword on a bit group basis corresponding to the parallel factor of the LDPC codeword; and outputting the interleaved codeword to a modulator for 256-symbol mapping. 
     In accordance with still another aspect of the present invention, there is provided a BICM device, including an error-correction coder configured to output an LDPC codeword having a length of 16200 and a code rate of 4/15; a bit interleaver configured to interleave the LDPC codeword on a bit group basis corresponding to the parallel factor of the LDPC codeword and output the interleaved codeword; and a modulator configured to perform 256-symbol mapping on the interleaved codeword. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The above and other objects, features and advantages of the present invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: 
         FIG. 1  is a block diagram illustrating a broadcast signal transmission and reception system according to an embodiment of the present invention; 
         FIG. 2  is an operation flowchart illustrating a broadcast signal transmission and reception method according to an embodiment of the present invention; 
         FIG. 3  is a diagram illustrating the structure of a parity check matrix (PCM) corresponding to an LDPC code to according to an embodiment of the present invention; 
         FIG. 4  is a diagram illustrating the bit groups of an LDPC codeword having a length of 64800; 
         FIG. 5  is a diagram illustrating the bit groups of an LDPC codeword having a length of 16200; 
         FIG. 6  is a diagram illustrating interleaving that is performed on a bit group basis in accordance with an interleaving sequence; 
         FIG. 7  is a block diagram illustrating a bit interleaver according to an embodiment of the present invention; and 
         FIG. 8  is an operation flowchart illustrating a bit interleaving method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Repeated descriptions and descriptions of well-known functions and configurations that have been deemed to make the gist of the present invention unnecessarily obscure will be omitted below. The embodiments of the present invention are intended to fully describe the present invention to persons having ordinary knowledge in the art to which the present invention pertains. Accordingly, the shapes, sizes, etc. of components in the drawings may be exaggerated to make the description obvious. 
     Embodiments of the present invention will be described in detail below with reference to the accompanying drawings. 
       FIG. 1  is a block diagram illustrating a broadcast signal transmission and reception system according to an embodiment of the present invention. 
     Referring to  FIG. 1 , it can be seen that a BICM device  10  and a BICM reception device  30  communicate with each other over a wireless channel  20 . 
     The BICM device  10  generates an n-bit codeword by encoding k information bits  11  using an error-correction coder  13 . In this case, the error-correction coder  13  may be an LDPC coder or a Turbo coder. 
     The codeword is interleaved by a bit interleaver  14 , and thus the interleaved codeword is generated. 
     In this case, the interleaving may be performed on a bit group basis (by a unit of a bit group). In this case, the error-correction coder  13  may be an LDPC coder having a length of 16200 and a code rate of 4/15. A codeword having a length of 16200 may be divided into a total of 45 bit groups. Each of the bit groups may include 360 bits, i.e., the parallel factor of an LDPC codeword. 
     In this case, the interleaving may be performed on a bit group basis (by a unit of a bit group) in accordance with an interleaving sequence, which will be described later. 
     In this case, the bit interleaver  14  prevents the performance of error correction code from being degraded by effectively distributing burst errors occurring in a channel. In this case, the bit interleaver  14  may be separately designed in accordance with the length and code rate of the error correction code and the modulation order. 
     The interleaved codeword is modulated by a modulator  15 , and is then transmitted via an antenna  17 . 
     In this case, the modulator  15  may be based on a concept including symbol mapper (symbol mapping device). In this case, the modulator  15  may be a symbol mapping device performing 256-symbol mapping which maps codes onto 256 constellations (symbols). 
     In this case, the modulator  15  may be a uniform modulator, such as a quadrature amplitude modulation (QAM) modulator, or a non-uniform modulator. 
     The modulator  15  may be a symbol mapping device performing NUC (Non-Uniform Constellation) symbol mapping which uses 256 constellations (symbols). 
     The signal transmitted via the wireless channel  20  is received via the antenna  31  of the BICM reception device  30 , and, in the BICM reception device  30 , is subjected to a process reverse to the process in the BICM device  10 . That is, the received data is demodulated by a demodulator  33 , is deinterleaved by a bit deinterleaver  34 , and is then decoded by an error correction decoder  35 , thereby finally restoring the information bits. 
     It will be apparent to those skilled in the art that the above-described transmission and reception processes have been described within a minimum range required for a description of the features of the present invention and various processes required for data transmission may be added. 
       FIG. 2  is an operation flowchart illustrating a broadcast signal transmission and reception method according to an embodiment of the present invention. 
     Referring to  FIG. 2 , in the broadcast signal transmission and reception method according to this embodiment of the present invention, input bits (information bits) are subjected to error-correction coding at step S 210 . 
     That is, at step S 210 , an n-bit codeword is generated by encoding k information bits using the error-correction coder. 
     In this case, step S 210  may be performed as in an LDPC encoding method, which will be described later. 
     Furthermore, in the broadcast signal transmission and reception method, an interleaved codeword is generated by interleaving the n-bit codeword on a bit group basis at step S 220 . 
     In this case, the n-bit codeword may be an LDPC codeword having a length of 16200 and a code rate of 4/15. The codeword having a length of 16200 may be divided into a total of 45 bit groups. Each of the bit groups may include 360 bits corresponding to the parallel factors of an LDPC codeword. 
     In this case, the interleaving may be performed on a bit group basis (by a unit of a bit group) in accordance with an interleaving sequence, which will be described later. 
     Furthermore, in the broadcast signal transmission and reception method, the encoded data is modulated at step S 230 . 
     That is, at step S 230 , the interleaved codeword is modulated using the modulator. 
     In this case, the modulator may be based on a concept including symbol mapper (symbol mapping device). In this case, the modulator may be a symbol mapping device performing 256-symbol mapping which maps codes onto 256 constellations (symbols). 
     In this case, the modulator may be a uniform modulator, such as a QAM modulator, or a non-uniform modulator. 
     The modulator may be a symbol mapping device performing NUC (Non-Uniform Constellation) symbol mapping which uses 256 constellations (symbols). 
     Furthermore, in the broadcast signal transmission and reception method, the modulated data is transmitted at step S 240 . 
     That is, at step S 240 , the modulated codeword is transmitted over the wireless channel via the antenna. 
     Furthermore, in the broadcast signal transmission and reception method, the received data is demodulated at step S 250 . 
     That is, at step S 250 , the signal transmitted over the wireless channel is received via the antenna of the receiver, and the received data is demodulated using the demodulator. 
     Furthermore, in the broadcast signal transmission and reception method, the demodulated data is deinterleaved at step S 260 . In this case, the deinterleaving of step S 260  may be reverse to the operation of step S 220 . 
     Furthermore, in the broadcast signal transmission and reception method, the deinterleaved codeword is subjected to error correction decoding at step S 270 . 
     That is, at step S 270 , the information bits are finally restored by performing error correction decoding using the error correction decoder of the receiver. 
     In this case, step S 270  corresponds to a process reverse to that of an LDPC encoding method, which will be described later. 
     An LDPC code is known as a code very close to the Shannon limit for an additive white Gaussian noise (AWGN) channel, and has the advantages of asymptotically excellent performance and parallelizable decoding compared to a turbo code. 
     Generally, an LDPC code is defined by a low-density parity check matrix (PCM) that is randomly generated. However, a randomly generated LDPC code requires a large amount of memory to store a PCM, and requires a lot of time to access memory. In order to overcome these problems, a quasi-cyclic LDPC (QC-LDPC) code has been proposed. A QC-LDPC code that is composed of a zero matrix or a circulant permutation matrix (CPM) is defined by a PCM that is expressed by the following Equation 1: 
     
       
         
           
             
               
                 
                   
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     In this equation, J is a CPM having a size of L×L, and is given as the following Equation 2. In the following description, L may be 360. 
     
       
         
           
             
               
                 
                   
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     Furthermore, J i  is obtained by shifting an L×L identity matrix I (J 0 ) to the right i (0≤i&lt;L) times, and J ∞  is an L×L zero matrix. Accordingly, in the case of a QC-LDPC code, it is sufficient if only index exponent i is stored in order to store J i , and thus the amount of memory required to store a PCM is considerably reduced. 
       FIG. 3  is a diagram illustrating the structure of a PCM corresponding to an LDPC code to according to an embodiment of the present invention. 
     Referring to  FIG. 3 , the sizes of matrices A and C are g×K and (N−K−g)×(K+g), respectively, and are composed of an L×L zero matrix and a CPM, respectively. Furthermore, matrix Z is a zero matrix having a size of g×(N−K−g), matrix D is an identity matrix having a size of (N−K−g)×(N−K−g), and matrix B is a dual diagonal matrix having a size of g×g. In this case, the matrix B may be a matrix in which all elements except elements along a diagonal line and neighboring elements below the diagonal line are 0, and may be defined as the following Equation 3: 
                     B     g   ×   g       =     [           I     L   ×   L           0       0       …       0       0       0             I     L   ×   L             I     L   ×   L           0       …       0       0       0           0         I     L   ×   L             I     L   ×   L           ⋮       0       0       0           ⋮       ⋮       ⋮       ⋱       ⋮       ⋮       ⋮           0       0       0       …         I     L   ×   L             I     L   ×   L           0           0       0       0       …       0         I     L   ×   L             I     L   ×   L             ]             (   3   )               
where I L×L  is an identity matrix having a size of L×L.
 
     That is, the matrix B may be a bit-wise dual diagonal matrix, or may be a block-wise dual diagonal matrix having identity matrices as its blocks, as indicated by Equation 3. The bit-wise dual diagonal matrix is disclosed in detail in Korean Patent Application Publication No. 2007-0058438, etc. 
     In particular, it will be apparent to those skilled in the art that when the matrix B is a bit-wise dual diagonal matrix, it is possible to perform conversion into a Quasi-cyclic form by applying row or column permutation to a PCM including the matrix B and having a structure illustrated in  FIG. 3 . 
     In this case, N is the length of a codeword, and K is the length of information. 
     The present invention proposes a newly designed QC-LDPC code in which the code rate thereof is 4/15 and the length of a codeword is 16200, as illustrated in the following Table 1. That is, the present invention proposes an LDPC code that is designed to receive information having a length of 4320 and generate an LDPC codeword having a length of 16200. 
     Table 1 illustrates the sizes of the matrices A, B, C, D and Z of the QC-LDPC code according to the present invention: 
     
       
         
           
               
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 Code 
                 Sizes 
               
            
           
           
               
               
               
               
               
               
               
            
               
                 rate 
                 Length 
                 A 
                 B 
                 C 
                 D 
                 Z 
               
               
                   
               
               
                 4/15 
                 16200 
                 1080 × 
                 1080 × 
                 10800 × 
                 10800 × 
                 1080 × 
               
               
                   
                   
                 4320 
                 1080 
                 5400 
                 10800 
                 10800 
               
               
                   
               
            
           
         
       
     
     The newly designed LDPC code may be represented in the form of a sequence (progression), an equivalent relationship is established between the sequence and matrix (parity bit check matrix), and the sequence may be represented, as follows: 
     
       
         
           
               
             
               
                   
               
               
                 Sequence Table 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
            
               
                   
                 1st row: 19 585 710 3241 3276 3648 6345 9224 9890 10841 
               
               
                   
                 2nd row: 181 494 894 2562 3201 4382 5130 5308 6493 10135 
               
               
                   
                 3rd row: 150 569 919 1427 2347 4475 7857 8904 9903 
               
               
                   
                 4th row: 1005 1018 1025 2933 3280 3946 4049 4166 5209 
               
               
                   
                 5th row: 420 554 778 6908 7959 8344 8462 10912 11099 
               
               
                   
                 6th row: 231 506 859 4478 4957 7664 7731 7908 8980 
               
               
                   
                 7th row: 179 537 979 3717 5092 6315 6883 9353 9935 
               
               
                   
                 8th row: 147 205 830 3609 3720 4667 7441 10196 11809 
               
               
                   
                 9th row: 60 1021 1061 1554 4918 5690 6184 7986 11296 
               
               
                   
                 10th row: 145 719 768 2290 2919 7272 8561 9145 10233 
               
               
                   
                 11st row: 388 590 852 1579 1698 1974 9747 10192 10255 
               
               
                   
                 12nd row: 231 343 485 1546 3155 4829 7710 10394 11336 
               
               
                   
                 13rd row: 4381 5398 5987 9123 10365 11018 11153 
               
               
                   
                 14th row: 2381 5196 6613 6844 7357 8732 11082 
               
               
                   
                 15th row: 1730 4599 5693 6318 7626 9231 10663 
               
               
                   
                   
               
            
           
         
       
     
     An LDPC code that is represented in the form of a sequence is being widely used in the DVB standard. 
     According to an embodiment of the present invention, an LDPC code presented in the form of a sequence is encoded, as follows. It is assumed that there is an information block S=(s 0 , s 1 , . . . , s K−1 ) having an information size K. The LDPC encoder generates a codeword Λ=(λ 0 , λ 1 , λ 2 , . . . , λ N−1 ) having a size of N=K+M 1 +M 2  using the information block S having a size K. In this case, M 1 =g, and M 2 =N−K−g. Furthermore, M 1  is the size of parity bits corresponding to the dual diagonal matrix B, and M 2  is the size of parity bits corresponding to the identity matrix D. The encoding process is performed, as follows: 
     Initialization:
 
λ i   =s   i  for  i= 0,1, . . . , K− 1
 
 p   j =0 for  j= 0,1, . . . , M   1   +M   2 −1  (4)
 
     First information bit λ 0  is accumulated at parity bit addresses specified in the 1st row of the sequence of the Sequence Table. For example, in an LDPC code having a length of 16200 and a code rate of 4/15, an accumulation process is as follows: 
                                        p 19  = p 19  ⊕ λ 0     p 585  = p 585  ⊕ λ 0     p 710  = p 710  ⊕ λ 0         p 3241  = p 3241  ⊕ λ 0     p 3276  = p 3276  ⊕ λ 0     p 3648  = p 3648  ⊕ λ 0         p 6345  = p 6345  ⊕ λ 0     p 9224  = p 9224  ⊕ λ 0     p 9890  = p 9890  ⊕ λ 0         p 10841  = p 10841  ⊕ λ 0                      
where the addition ⊕ occurs in GF(2).
 
     The subsequent L−1 information bits, that is, λ m , m=1, 2, . . . , L−1, are accumulated at parity bit addresses that are calculated by the following Equation 5:
 
( x+m×     1 )mod  M   1  if  x&lt;M   1  
 
 M   1 +{( x−M   1   +m×Q   2 )mod  M   2 } if  x≥M   1   (5)
 
where x denotes the addresses of parity bits corresponding to the first information bit λ 0 , that is, the addresses of the parity bits specified in the first row of the sequence of the Sequence Table, Q 1 =M 1 /L, Q 2 =M 2 /L, and L=360. Furthermore, Q 1  and Q 2  are defined in the following Table 2. For example, for an LDPC code having a length of 16200 and a code rate of 4/15, M 1 =1080, Q 1 =3, M 2 =10800, Q 2 =30 and L=360, and the following operations are performed on the second bit λ 1  using Equation 5:
 
     
       
         
           
               
               
               
             
               
                   
               
             
            
               
                 p 22  = p 22  ⊕ λ 1   
                 p 588  = p 588  ⊕ λ 1   
                 p 713  = p 713  ⊕ λ 1   
               
               
                 p 3271  = p 3271  ⊕ λ 1   
                 p 3306  = p 3306  ⊕ λ 1   
                 p 3678  = p 3678  ⊕ λ 1   
               
               
                 p 6375  = p 6375  ⊕ λ 1   
                 p 9254  = p 9254  ⊕ λ 1   
                 p 9920  = p 9920  ⊕ λ 1   
               
               
                 p 10871  = p 10871  ⊕ λ 1   
               
               
                   
               
            
           
         
       
     
     Table 2 illustrates the sizes of M 1 , Q 1 , M 2  and Q 2  of the designed QC-LDPC code: 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 2 
               
             
            
               
                   
                   
               
               
                   
                 Sizes 
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                   
                 Code rate 
                 Length 
                 M 1   
                 M 2   
                 Q 1   
                 Q 2   
               
               
                   
                   
               
               
                   
                 4/15 
                 16200 
                 1080 
                 10800 
                 3 
                 30 
               
               
                   
                   
               
            
           
         
       
     
     The addresses of parity bit accumulators for new 360 information bits from λ L  to λ 2L−1  are calculated and accumulated from Equation 5 using the second row of the sequence. 
     In a similar manner, for all groups composed of new L information bits, the addresses of parity bit accumulators are calculated and accumulated from Equation 5 using new rows of the sequence. 
     After all the information bits from λ 0  to λ K−1  have been exhausted, the operations of the following Equation 6 are sequentially performed from i=1:
 
 p   i   =p   i   ⊕p   i-1  for  i= 0,1, . . . , M   1 −1  (6)
 
     Thereafter, when a parity interleaving operation, such as that of the following Equation 7, is performed, parity bits corresponding to the dual diagonal matrix B are generated:
 
λ K+L·t+s =  for 0≤ s&lt;L,  0≤ t&lt;Q   1   (7)
 
     When the parity bits corresponding to the dual diagonal matrix B have been generated using K information bits λ 0 , λ 1 , . . . , λ K−1 , parity bits corresponding to the identity matrix D are generated using the M 1  generated parity bits λ K , λ K+1 , . . . , λ K+M     1     −1 . 
     For all groups composed of L information bits from λ K  to λ K+M     1     −1 , the addresses of parity bit accumulators are calculated using the new rows (starting with a row immediately subsequent to the last row used when the parity bits corresponding to the dual diagonal matrix B have been generated) of the sequence and Equation 5, and related operations are performed. 
     When a parity interleaving operation, such as that of the following Equation 8, is performed after all the information bits from λ K  to λ K+M     1     −1  have been exhausted, parity bits corresponding to the identity matrix D are generated:
 
λ K+M     1     +L·t+s =  for 0≤ s&lt;L,  0≤ t&lt;Q   2   (8)
 
       FIG. 4  is a diagram illustrating the bit groups of an LDPC codeword having a length of 64800. 
     Referring to  FIG. 4 , it can be seen that an LDPC codeword having a length of 64800 is divided into 180 bit groups (a 0th group to a 179th group). 
     In this case, 360 may be the parallel factor (PF) of the LDPC codeword. That is, since the PF is 360, the LDPC codeword having a length of 64800 is divided into 180 bit groups, as illustrated in  FIG. 4 , and each of the bit groups includes 360 bits. 
       FIG. 5  is a diagram illustrating the bit groups of an LDPC codeword having a length of 16200. 
     Referring to  FIG. 5 , it can be seen that an LDPC codeword having a length of 16200 is divided into 45 bit groups (a 0th group to a 44th group). 
     In this case, 360 may be the parallel factor (PF) of the LDPC codeword. That is, since the PF is 360, the LDPC codeword having a length of 16200 is divided into 45 bit groups, as illustrated in  FIG. 5 , and each of the bit groups includes 360 bits. 
       FIG. 6  is a diagram illustrating interleaving that is performed on a bit group basis in accordance with an interleaving sequence. 
     Referring to  FIG. 6 , it can be seen that interleaving is performed by changing the order of bit groups by a designed interleaving sequence. 
     For example, it is assumed that an interleaving sequence for an LDPC codeword having a length of 16200 is as follows:
 
interleaving sequence={24 34 15 11 2 28 17 25 5 38 19 13 6 39 1 14 33 37 29 12 42 31 30 32 36 40 26 35 44 4 16 8 20 43 21 7 0 18 23 3 10 41 9 27 22}
 
     Then, the order of the bit groups of the LDPC codeword illustrated in  FIG. 4  is changed into that illustrated in  FIG. 6  by the interleaving sequence. 
     That is, it can be seen that each of the LDPC codeword  610  and the interleaved codeword  620  includes 45 bit groups, and it can be also seen that, by the interleaving sequence, the 24th bit group of the LDPC codeword  610  is changed into the 0th bit group of the interleaved LDPC codeword  620 , the 34th bit group of the LDPC codeword  610  is changed into the 1st bit group of the interleaved LDPC codeword  620 , the 15th bit group of the LDPC codeword  610  is changed into the 2nd bit group of the interleaved LDPC codeword  620 , and the list bit group of the LDPC codeword  610  is changed into the 3rd bit group of the interleaved LDPC codeword  620 , and the 2nd bit group of the LDPC codeword  610  is changed into the 4th bit group of the interleaved LDPC codeword  620 . 
     An LDPC codeword (u 0 , u 1 , . . . , u N     ldpc     −1 ) having a length of N ldpc  (N ldpc =16200) is divided into N group =N ldpc /360 bit groups, as in Equation 9 below:
 
 X   j   ={u   k |360× j≤k&lt; 360×( j+ 1), 0≤ k&lt;N   ldpc } for 0≤ j&lt;N   group   (9)
 
where X j  is an j-th bit group, and each X j  is composed of 360 bits.
 
     The LDPC codeword divided into the bit groups is interleaved, as in Equation 10 below:
 
 Y   j   =X   π(j)  0≤ j≤N   group   (10)
 
where Y j  is an interleaved j-th bit group, and π(j) is a permutation order for bit group-based interleaving (bit group-unit interleaving). The permutation order corresponds to the interleaving sequence of Equation 11 below:
 
interleaving sequence={38 20 0 34 33 41 14 30 44 7 37 8 4 9 43 15 19 32 23 5 22 26 10 12 3 31 36 21 24 11 16 18 17 29 35 42 13 40 1 28 2 25 6 39 27}  (11)
 
     That is, when each of the codeword and the interleaved codeword includes 45 bit groups ranging from a 0th bit group to a 44th bit group, the interleaving sequence of Equation 11 means that the 38th bit group of the codeword becomes the 0th bit group of the interleaved codeword, the 20th bit group of the codeword becomes the 1st bit group of the interleaved codeword, the 0th bit group of the codeword becomes the 2nd bit group of the interleaved codeword, the 34th bit group of the codeword becomes the 3rd bit group of the interleaved codeword, . . . , the 39th bit group of the codeword becomes the 43th bit group of the interleaved codeword, and the 27th bit group of the codeword becomes the 44th bit group of the interleaved codeword. 
     In particular, the interleaving sequence of Equation 11 has been optimized for a case where 256-symbol mapping (NUC symbol mapping) is employed and an LDPC coder having a length of 16200 and a code rate of 4/15 is used. 
       FIG. 7  is a block diagram illustrating a bit interleaver according to an embodiment of the present invention. 
     Referring to  FIG. 7 , the bit interleaver according to the present embodiment includes memories  710  and  730  and a processor  720 . 
     The memory  710  stores an LDPC codeword having a length of 16200 and a code rate of 4/15. 
     The processor  720  generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis corresponding to the parallel factor of the LDPC codeword. 
     In this case, the parallel factor may be 360. In this case, each of the bit groups may include 360 bits. 
     In this case, the LDPC codeword may be divided into 45 bit groups, as in Equation 9. 
     In this case, the interleaving may be performed using Equation 10 using permutation order. 
     In this case, the permutation order may correspond to the interleaving sequence represented by Equation 11. 
     The memory  730  provides the interleaved codeword to a modulator for 256-symbol mapping. 
     In this case, the modulator may be a symbol mapping device performing NUC (Non-Uniform Constellation) symbol mapping. 
     The memories  710  and  730  may correspond to various types of hardware for storing a set of bits, and may correspond to a data structure, such as an array, a list, a stack, a queue or the like. 
     In this case, the memories  710  and  730  may not be physically separate devices, but may correspond to different addresses of a physically single device. That is, the memories  710  and  730  are not physically distinguished from each other, but are merely logically distinguished from each other. 
     The error-correction coder  13  illustrated in  FIG. 1  may be implemented in the same structure as in  FIG. 7 . 
     That is, the error-correction coder may include memories and a processor. In this case, the first memory is a memory that stores an LDPC codeword having a length of 16200 and a code rate of 4/15, and a second memory is a memory that is initialized to 0. 
     The memories may correspond to λ i (i=0, 1, . . . , N−1) and P j (j=0, 1, . . . , M 1 +M 2 −1), respectively. 
     The processor may generate an LDPC codeword corresponding to information bits by performing accumulation with respect to the memory using a sequence corresponding to a parity check matrix (PCM). 
     In this case, the accumulation may be performed at parity bit addresses that are updated using the sequence of the above Sequence Table. 
     In this case, the LDPC codeword may include a systematic part λ 0 , λ 1 , . . . , λ K−1  corresponding to the information bits and having a length of 4320 (=K), a first parity part λ K , λ +1 , . . . , λ K+M     1     −1  corresponding to a dual diagonal matrix included in the PCM and having a length of 1080 (=M 1 =g), and a second parity part λ K+M     1   , λ K+M     1     1 , . . . , λ K+M     1     +M     2     −1  corresponding to an identity matrix included in the PCM and having a length of 10800 (=M 2 ). 
     In this case, the sequence may have a number of rows equal to the sum (4320/360+1080/360=15) of a value obtained by dividing the length of the systematic part, that is, 4320, by a CPM size L corresponding to the PCM, that is, 360, and a value obtained by dividing the length M 1  of the first parity part, that is, 1080, by 360. 
     As described above, the sequence may be represented by the above Sequence Table. 
     In this case, the second memory may have a size corresponding to the sum M 1 +M 2  of the length M 1  of the first parity part and the length M 2  of the second parity part. 
     In this case, the parity bit addresses may be updated based on the results of comparing each x of the previous parity bit addresses, specified in respective rows of the sequence, with the length M 1  of the first parity part. 
     That is, the parity bit addresses may be updated using Equation 5. In this case, x may be the previous parity bit addresses, m may be an information bit index that is an integer larger than 0 and smaller than L, L may be the CPM size of the PCM,    1  may be M 1 /L, M 1  may be the size of the first parity part,    2  may be M 2 /L, and M 2  may be the size of the second parity part. 
     In this case, it may be possible to perform the accumulation while repeatedly changing the rows of the sequence by the CPM size L (=360) of the PCM, as described above. 
     In this case, the first parity part λ K , λ K+1 , . . . , λ K+M     1     −1  may be generated by performing parity interleaving using the first memory and the second memory, as described in conjunction with Equation 7. 
     In this case, the second parity part λ K+M     1   , λ K+M     1     +1 , . . . , λ K+M     1     +M     2     −1  may be generated by performing parity interleaving using the first memory and the second memory after generating the first parity part λ K , λ K+1 , . . . , λ K+M     1     −1  and then performing the accumulation using the first parity part λ K , λ K+1 , . . . , λ K+M     1     −1  and the sequence, as described in conjunction with Equation 8. 
       FIG. 8  is an operation flowchart illustrating a bit interleaving method according to an embodiment of the present invention. 
     Referring to  FIG. 8 , in the bit interleaving method according to the present embodiment, an LDPC codeword having a length of 16200 and a code rate of 4/15 is stored at step S 810 . 
     In this case, the LDPC codeword may be represented by (u 0 , u 1 , . . . , u N     ldpc     −1 ) (where N ldpc  is 16200), and may be divided into 45 bit groups each composed of 360 bits, as in Equation 9. 
     Furthermore, in the bit interleaving method according to the present embodiment, an interleaved codeword is generated by interleaving the LDPC codeword on a bit group basis at step S 820 . 
     In this case, the size of the bit group may correspond to the parallel factor of the LDPC codeword. 
     In this case, the interleaving may be performed using Equation 10 using permutation order. 
     In this case, the permutation order may correspond to the interleaving sequence represented by Equation 11. 
     In this case, the parallel factor may be 360, and each of the bit groups may include 360 bits. 
     In this case, the LDPC codeword may be divided into 45 bit groups, as in Equation 9. 
     Moreover, in the bit interleaving method according to the present embodiment, the interleaved codeword is output to a modulator for 256-symbol mapping at step  830 . 
     In accordance with at least one embodiment of the present invention, there is provided an intra-BICM bit interleaver that can effectively distribute burst errors occurring in a broadcasting system channel. 
     In accordance with at least one embodiment of the present invention, there is provided a bit interleaver that is optimized for an LDPC coder having a length of 16200 and a code rate of 4/15 and a modulator performing 256-symbol mapping and, thus, can be applied to next-generation broadcasting systems, such as ATSC 3.0. 
     Although the specific embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible without departing from the scope and spirit of the invention as disclosed in the accompanying claims.