Patent Publication Number: US-6711666-B1

Title: IBM PC compatible multi-chip module

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This is a continuation of Ser. No. 08/757,896, filed Nov. 27, 1996, which is a continuation-in-part of Ser. No. 08/564,688, filed Nov. 29, 1995, now U.S. Pat. No. 5,742,844. 
    
    
     FIELD OF THE INVENTION 
     This invention relates to a multi-chip module. 
     BACKGROUND OF THE INVENTION 
     The most successful applications of computer technology have been those that people do not see. Microcontrollers and microprocessors govern automotive anti lock braking systems, automatic teller machines, elevators, subway ticket systems, and medical equipment. These hidden computers, otherwise known as embedded systems, permeate our lives. The embedded control market is, in fact, growing significantly faster than the desk top computing market. A major trend is the move from 4- and 8-bit processors to more powerful devices that provide more computing power and enable more “friendly” man-machine interfaces. A study by Desk Top Strategies showed that in 1994 over 320 million 16- and 32-bit embedded control processors were shipped to original equipment manufacturers (OEMs) for use in embedded control applications. In contrast, only 50 million were shipped to desk top computer manufacturers. The compound annual growth rate for 32-bit processors in the embedded market from 1992 to 1997 is projected to be 53 percent, compared with an estimated 32 percent in the desk top market. 
     The area of greatest growth in the embedded control market is the segment of ultra-miniature controllers for portable and transportable instruments. OEMs have indicated a strong interest in developing products with the PC architecture, but have found that size, integration, power, reliability, or cost constraints make existing broad-level products unsuitable for their applications. 
     The Cardio 386 developed by S-Mos Systems comprises a full function, small footprint, X86 computer that includes a CPU, all standard PC-type I/O controllers, PGA graphics, floppy and hard disk drive interfaces, DRAM, flash memory, and transparent power management. It adopts a PC AT architecture which complies with the ISA (industry standard architecture) bus pin configuration. However, it makes use of a unique edge connector comprising a plurality of tracks formed into rows on a card. This is received in a complementary slot for connection to peripheral devices. The use of a connector for connecting the module to a board makes its implementation inherently unreliable since vibrations can compromise the electrical connections between the various tracks forming the pins, and the corresponding contacts of the slot connector. Furthermore, no provision is made for integrating the module with proprietary hardware of OEMs (original equipment manufacturers). 
     Another prior art device is the Northstar III by Micro Module Systems that comprises a multi-chip module, including a Pentium processor, a cache controller, and RAM incorporated in a 349 pin PGA package. Once again, no facility is provided for interfacing with OEM proprietary hardware, Furthermore, the North Star module is packaged in a 349 pin PGA which makes simple direct connection to peripheral devices impossible without complicated track layout design. Therefore it does not allow the module to be simply dropped into an OEM system. 
     OBJECTS AND SUMMARY OF THE INVENTION 
     It is an object of the invention to incorporate a multi-chip module in an ultra-miniature form factor. In particular it is an object of the invention to provide a module the size of a large integrated circuit. 
     It is a further object of the invention to provide an Intel X86 compatible computer module and peripheral controller modules wherein the computer module includes a CPU, I/O (a parallel port and two serial ports), a keyboard interface, a DRAM interface, floppy disk controller, hard disk controller, and flash disk functions based on Intel X86 architecture. Specifically, it is an object of the invention to provide a multi-chip module that provides an OEM (Original Equipment Manufacturer) with the facility for incorporating a feature set that is compatible with IBM PC/AT hardware, software, and bus pin configuration. 
     It is a further object of the invention to provide a module having low power consumption, broad thermal adaptability, low cost, and high reliability by eliminating cables and mounting hardware. 
     It is yet a further object of the invention to provide a module family having identical ISA bus pin configurations to facilitate easy interconnection. 
     It is yet a further object of the invention to provide a development board to form a platform for receiving a multi-chip module of the invention, thereby to provide for the quick development of pilot projects. 
     According to the invention there is provided a multi-chip module comprising a plurality of functional circuits provided on a substrate, the circuits defining a plurality of signal inputs and outputs, and a plurality of module pins secured in a single row along the periphery of the substrate and connected to the inputs and outputs, the module pins including a set of 91 pins, two ground pins, and a power pin, defining an ISA bus means, the signal pins having a configuration complying in number and signal type with the signal pins laid down under the IEEE-P996 specification, and as applied in the ISA (Industry Standard Architecture) requirements. For this reason it will hereinafter be referred as to as the ISA bus. 
     The module can be rectangular in shape, having a first side, a second side opposite the first side, a third side, and a fourth side, and is defined by an upper surface, a lower surface, and a peripheral wall, and wherein the plurality of pins extend from the peripheral wall. 
     The pins of the ISA bus means of the present invention preferably comprise: pin  38  corresponding to signal IOCHCK; pin  39  corresponding to signal SD 07 ; pin  40  corresponding to signal RESETDRV; pin  41  corresponding signal SD 06 ; pin  42  corresponding to signal SD 05 ; pin  43  corresponding to signal IRQ 9 ; pin  44  corresponding to signal SD 04 ; pin  45  corresponding to signal SD 03 ; pin  46  corresponding to signal DRQ 2 ; pin  47  corresponding to signal DRQ 20 UT-; pin  48  corresponding to signal SD 02 ; pin  49  corresponding to signal SD 01 -; pin  50  corresponding to signal  0 WS; pin  51  corresponding to signal SD 00 ; pin  52  corresponding to signal IOCHRDY; pin  53  corresponding to signal SBHE-; pin  54  corresponding to signal MEMSC 16 -; pin  55  corresponding to signal AEN; pin  56  corresponding to signal SMEMW-; pin  57  corresponding to signal LA 23 ; pin  58  corresponding to signal IOCS  16 -; pin  59  corresponding to signal SA 19 ; pin  60  corresponding to signal SMEMR-; pin  61  corresponding to signal LA 22 ; pin  62  corresponding to signal IRQI 0 ; pin  63  corresponding to signal SA 18 ; pin  64  corresponding to signal IOW-; pin  65  corresponding to signal LA 21 ; pin  66  corresponding to signal IRQ 11 ; pin  67  corresponding to GND; pin  68  corresponding to signal SA 17 ; pin  69  corresponding to signal IOR-; pin  70  corresponding to signal LA 20 ; pin  71  corresponding to signal IRQ 12 ; pin  72  corresponding to signal SA 16 ; pin  73  corresponding to signal DACK 3 -; pin  74  corresponding to signal LA 19 ; pin  75  corresponding to signal IRQ 15 ; pin  76  corresponding to signal SA 15 ; pin  77  corresponding to signal DRQ 3 ; pin  78  corresponding to signal LA 18 ; pin  79  corresponding to signal IRQ 14 ; pin  80  corresponding to signal SA 14 ; pin  81  corresponding to signal DACK 1 -; pin  82  corresponding to signal LA 17 ; pin  83  corresponding to signal DACK 0 -; pin  84  corresponding to signal SA 13 ; pin  85  corresponding to VCC; pin  86  corresponding to signal DRQ 1 -; pin  87  corresponding to signal MEMR-; pin  88  corresponding to signal DRQ 0 ; pin  89  corresponding to signal SA 12 ; pin  90  corresponding to signal REFRESH-; pin  91  corresponding to signal MEMW-; pin  92  corresponding to signal DACK 5 -; pin  93  corresponding to signal SA 11 ; pin  94  corresponding to signal SYSCLK; pin  95  conresponding to signal SD 08 ; pin  96  corresponding to signal DRQS; pin  97  corresponding to signal SA 10 ; pin  98  corresponding to signal IRQ 7 ; pin  99  corresponding to signal IRQ 7 OUT; pin  100  corresponding to signal SD 09 ; pin  101  corresponding to signal DACK 6 -; pin  102  corresponding to GND; pin  103  corresponding to signal SA 09 ; pin  104  corresponiding to signal IRQ 6 ; pin  105  corresponding to signal IRQ 6 OUT; pin  106  corresponding to signal SD 10 ; pin  107  corresponding to signal DRQ 6 ; pin  108  corresponding to signal SA 08 ; pin  109  corresponding to signal IRQ 5 ; pin  110  corresponding to signal SD 11 ; pin  111  corresponding to signal DACK 7 -; pin  112  corresponding to signal SA 07 ; pin  113  corresponding to signal IRQ 4 ; pin  114  corresponding to signal SD 12 ; pin  115  corresponding to signal DRQ 7 ; pin  116  corresponding to signal SA 06 ; pin  117  corresponding to signal IRQ 3 ; pin  118  corresponding to signal SD 13 ; pin  119  corresponding to signal SA 05 ; pin  120  corresponding to signal DACK 2 -; pin  121  corresponding to signal SD 14 ; pin  122  corresponding to signal MASTER-; pin  123  corresponding to signal SA 04 ; pin  124  corresponding to signal TC; pin  125  corresponding to signal SD 15 ; pin  126  corresponding to signal SA 03 ; pin  127  corresponding to signal BALE; pin  128  corresponding to signal SA 02 ; pin  129  corresponding to signal SA 01 ; pin  130  corresponding to signal OSC; and pin  131  corresponding to signal SA 00 . 
     The pin of the ISA bus means of the present invention can alternatively comprise: pin  38  corresponding to signal SA 00 ; pin  39  corresponding to signal OSC; pin  40  corresponding to signal SA 01 ; pin  41  corresponding signal SA 02 ; pin  42  corresponding to signal BALE; pin  43  corresponding to signal SA 03 ; pin  44  corresponding to signal SD 15 ; pin  45  corresponding to signal TC; pin  46  corresponding to signal SA 04 ; pin  47  corresponding to signal MASTER-; pin  48  corresponding to signal SD 14 ; pin  49  corresponding to signal DACK 2 -; pin  50  corresponding to signal SA 05 ; pin  51  corresponding to signal SD 13 ; pin  52  corresponding to signal IRQ 3 ; pin  53  corresponding to signal SA 06 ; pin  54  corresponding to signal DRQ 7 ; pin  55  corresponding to signal SD 12 ; pin  56  corresponding to signal IRQ 4 ; pin  57  corresponding to signal SA 07 ; pin  58  corresponding to signal DACK 7 -; pin  59  corresponding to signal SD 11 ; pin  60  corresponding to signal IRQ 5 ; pin  61  corresponding to signal SA 08 ; pin  62  corresponding to signal DRQ 6 ; pin  63  corresponding to signal SD 10 ; pin  64  corresponding to signal IRQ 60 UT; pin  65  corresponding to signal IRQ 6 ; pin  66  corresponding to signal SA 09 ; pin  67  corresponding to GND; pin  68  corresponding to signal DACK 6 -; pin  69  corresponding to signal SD 09 ; pin  70  corresponding to signal IRQ 70 UT; pin  71  corresponding to signal IRQ 7 ; pin  72  corresponding to signal SA 10 ; pin  73  corresponding to signal DRQ 5 ; pin  74  corresponding to signal SD 08 ; pin  75  corresponding to signal SYSCLK; pin  76  corresponding to signal SA 11 ; pin  77  corresponding to signal DACK 5 -; pin  78  corresponding to signal MEMW-; pin  79  corresponding to signal REFRESH-; pin  80  corresponding to signal SA 12 ; pin  81  corresponding to signal DRQ 5 ; pin  82  corresponding to signal MEMR-; pin  83  corresponding to signal DRQ 1 ; pin  84  corresponding to signal SA 13 ; pin  85  corresponding to VCC; pin  86  corresponding to signal DACKO-; pin  87  corresponding to signal LA 17 ; pin  88  corresponding to signal DACK 1 -; pin  89  corresponding to signal SA 14 ; pin  90  corresponding to signal IRQ 14 ; pin  91  corresponding to signal LA 18 ; pin  92  corresponding to signal DRQ 3 ; pin  93  corresponding to signal SA 15 ; pin  94  corresponding to signal IRQ 15 ; pin  95  corresponding to signal LA 19 ; pin  96  corresponding to signal DACK 3 -; pin  97  corresponding to signal SA 16 ; pin  98  corresponding to signal IRQ 12 ; pin  99  corresponding to signal LA 20 ; pin  100  corresponding to signal IOR-; pin  101  corresponding to signal SA 17 ; pin  102  corresponding to GND; pin  103  corresponding to signal IRQ 11 ; pin  104  corresponding to signal LA 21 ; pin  105  corresponding to signal IOW-; pin  106  corresponding to signal SA 18 ; pin  107  corresponding to signal IRQ 10 ; pin  108  corresponding to signal LA 22 ; pin  109  corresponding to signal SMEMR-; pin  110  corresponding to signal SA 19 ; pin  111  corresponding to signal IOCS 16 -; pin  112  corresponding to signal LA 23 ; pin  113  corresponding to signal SMEMW-; pin  114  corresponding to signal AEN; pin  115  corresponding to signal MEMCS  16 -; pin  116  corresponding to signal SBHE-; pin  117  corresponding to signal IOCHRDY; pin  118  corresponding to signal SD 00 ; pin  119  corresponding to signal  0 WS-; pin  120  corresponding to signal SD 00 ; pin  121  corresponding to signal SD 02 ; pin  122  corresponding to signal DRQ 2 OUT; pin  123  corresponding to signal DRQ 2 ; pin  124  corresponding to signal SD 03 ; pin  125  corresponding to signal SD 04 ; pin  126  corresponding to signal IRQ 9 ; pin  127  corresponding to signal SD 05 ; pin  128  corresponding to signal SD 06 ; pin  129  corresponding to signal RESETDRV; pin  130  corresponding to signal SD 07 ; and pin  131  corresponding to signal IOCHCK-.The ISA bus pins preferably extend along the first side and at least partially along the third and fourth sides. The multi-chip module can include  240  module pins. 
     The functional circuits in a module can include a central processing unit. The functional circuits can further include two serial interfaces, a parallel interface, a hard drive interface, a floppy disk interface, a keyboard interface, and flash memory. 
     Other modules can include functional circuits that include a PCMCIA interface, an Ethernet interface, or a display controller. 
     The substrate can comprise a printed circuit board and the functional circuits comprise semiconductor devices which can be packaged or can be in bare die form secured to the printed circuit board. 
     Further, according to the invention, there is provided a multi-chip module comprising a plurality of functional circuits encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side; and a plurality of pins extending laterally from the peripheral wall, wherein the pins include a set of 91 signal pins, two ground pins and a power pin defining an ISA bus means, the signal pins of which comply in number and signal type, with the signal pins laid down under the IEEE-P996, and as applied in the ISA (Industry Standard Architecture) requirements. 
     Still further, according to the invention, there is provided a module family comprising a plurality of functionally different modules, wherein each module has a plurality of pins and the pins of each module include a set of 91 signal pins, two ground pins, and a power pin, defining an ISA bus means, the signal pins of which comply in number and signal type with the signal pins laid down under the IEEE-P996, and as applied in the ISA (Industry Standard Architecture) requirements. 
     Each module can comprise at least one functional circuit encapsulated in a rectangular housing, the housing having an upper surface and a lower surface, and a peripheral wall extending along a first side, a second side opposite the first side, a third side, and a fourth side, and wherein the pins of the module extend laterally from the peripheral wall. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a plan view of a multi-chip module of the invention; 
     FIG. 2 is a side view of the module of FIG. 1; 
     FIG. 3 is a block diagram of a multi-chip module of the invention; 
     FIG. 4 is a schematic representation of the first embodiment of a multi-chip module of the invention indicating the configuration of the pins; 
     FIG. 5 is a schematic representation of the alternative embodiment of a multi-chip module of the invention indicating the configuration of the pins; 
     FIG. 6 shows a PC board layout for a development board showing the mounting site for the module of FIG. 1, and 
     FIG. 7 is a schematic representation of a number of different modules in accordance with the invention connected to each other by means of their ISA buses to form a module family of the invention. 
    
    
     DESCRIPTION OF PREFERRED EMBODIMENTS 
     A need exists in the field of embedded applications for small, highly reliable computer systems that draw little power, are easy to integrate, have broad thermal adaptability and are relatively inexpensive. Applications for such devices include medical instruments, data logging devices, security systems, test equipment, point-of-sale terminals, communications devices, such as Internet and facsimile machines, and navigational instruments. OEMs (original equipment manufacturers) typically use the Intel X86 architecture since it offers the world&#39;s largest body of hardware and software. The present invention has accordingly been developed to address the problems in the prior art by providing a multi-chip module packaged to resemble a large integrated circuit chip comprising a 240 pin QFP having an overall footprint of 59.54×79.88 mm. The module includes a set of pins constituting a bus for connection to the OEM designer&#39;s proprietary internal hardware. The invention specifically contemplates providing this bus with a configuration complying with the ISA (Industry Standard Architecture) requirements. This will allow the OEM designer quickly to incorporate IBM PC/AT hardware and software and to implement the module in ISA compatible proprietary product designs. The module is now described in greater detail with reference to FIGS. 1 and 2 which show a plan view and a side view, respectively, of the module. 
     The module  10  is a 240 pin QFP with gull wing pins having a 0.762 mm. pitch. The body is rectangular, the one side of which measures 76.2 mm and the overall footprint in this embodiment being 59.54×79.88 mm. The pins themselves are typically 0.5 mm wide, and the dimensions of distances  12  and  14  in FIG. 1 are 3.5 mm for this embodiment. By using a chip-like package in which the pins are formed around the periphery of the module  10  in a single row as illustrated in FIGS. 1 and 2, the module  10  can easily be soldered into place to form a very sturdy, reliable set of connections. Furthermore, tracks can be designed to lead directly from the pins to another device by making use of PC board tracks on one or both surfaces of the PC board without the need for several layers to route the various tracks. Since the pins are soldered directly to the interconnecting tracks, the system has inherent reliability in that it eliminates cables and mounting hardware that could otherwise vibrate loose. As many as half a dozen interconnecting cables, assorted connectors and mounting hardware required with many existing prior art single board computers, are thereby eliminated. 
     The module thus provides an Intel X86 compatible computer in an ultra-miniature form factor that can be integrated as easily as a semiconductor device and provides the full functionality of a desk top computer. As is described in greater detail below, the same concepts of using a chip-like module using a QFP package with gull wing pins and having an ISA compatible bus is extended also to peripheral controller modules. 
     By integrating a full X86 AT-compatible computer onto a proprietary OEM design, the need for multiple boards is eliminated, thereby eliminating cables and mounting hardware. 
     The full compatibility with PC-AT ISA allows for easy integration with low-cost hardware peripherals. The ISA, compliant bus makes it easy to interface with proprietary hardware design. 
     One embodiment of the module  10 , having a CPU as one of its functional circuits, is illustrated in FIG.  3  and includes the standard I/O interfaces, serial ports, a parallel port, and floppy and hard disk interfaces allowing standard hardware, cables, and software libraries to be incorporated in the design. The module  10  includes an 80386 SX CPU  20  which is connected to a DRAM bus  22  and an ISA bus  24  by means of core logic  26 . The core logic controls AT-compatible DMA controllers, interrupt controllers, and timers/counters. It also controls the AT keyboard controller  28  and the real time clock  30 . Two serial ports  32 ,  34  and a parallel port  36  are provided, as are a floppy disk controller  40  and an IDE hard drive interface  42 . In order to facilitate total solid state operation, internal flash memory  44  is provided that is controlled by a solid state flash disk controller  46 . Power is controlled by means of a power monitor  48  that provides a power saving function by controlling CPU sleep modes, and by a watch dog timer  50 . The watch dog timer  50  monitors CPU cycles to detect interrupts in the cycle thereby allowing the system to be automatically reset after a predetermined time delay. 
     The microprocessor and various controllers and interfaces comprise chips, optionally in die form, mounted on a multi-layer PC board, e.g. ten-layers. The CPU  20  can be a standard 33 MHz 80386 SX CPU having a DRAM controller for supporting up to 16 M bytes of DRAM. Alternatively, CPU 20  can be another standard microprocessor chip such as another type of 80386 chip or die, a 80486 chip or die, a Pentium chip or die, or any other desired microprocessor which is capable of providing the function of the 80386 device. 
     The standard DRAM interface provides all the signals for connecting standard page-mode DRAMs of various configurations, including standard 8- and 9-bit 30-pin SIMM modules and discrete components, such as standard 1M×4 and 4M×4 DRAM chips. The interface is designed to support 70 ns or faster DRAMs. The DRAM interface consists of. 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 Multiplexed addresses 
                  MA00-MA10 
               
               
                   
                 Bi-directional data 
                 D0-D15 
               
               
                   
                 Column Address Strobes 
                 CASL0- to CASL3- (low byte) 
               
               
                   
                   
                 CASH0- to CASH3- (high byte) 
               
               
                   
                 Row Address Strobes 
                 RAS0- to RAS3- 
               
               
                   
                 Memory Write Strobe 
                 DRWE- 
               
               
                   
                   
               
            
           
         
       
     
     The serial ports  32 ,  34  are PC-compatible asynchronous serial ports, typically treated as COM  1  and COM  2  devices by DOS. 
     
       
         
           
               
            
               
                   
               
               
                 Serial Port Resources 
               
            
           
           
               
               
               
               
               
            
               
                   
                 Serial 
                 Typical 
                 I/O 
                 Standard 
               
               
                   
                 Port 
                 Usage 
                 Address 
                 Interrupt 
               
               
                   
                   
               
               
                   
                 Serial 1 
                 COM1 
                 3F8-3FF 
                 IRQ4 
               
               
                   
                 Serial 2 
                 COM2 
                 2F8-2FF 
                 IRQ3 
               
               
                   
                   
               
            
           
         
       
     
     Either or both serial ports can be disabled using SETUP. When disabled, the port*s I/O address and interrupt are made available for other expansion devices on the PC bus. 
     A full complement of input and output handshaking lines are supported by the serial ports, and all serial port signals are at standard LSTTL levels. In another embodiment, RS232C signal compatibility can be achieved by including a TTL-RS232C level converter to provide the necessary bipolar signal levels. The parallel port is a fully-compatible PC/AT parallel port providing bidirectional operation. It is typically used to support a line printer. As appears from the table below: 
     
       
         
           
               
            
               
                   
               
               
                 Parallel Port Resources 
               
            
           
           
               
               
               
               
               
            
               
                   
                 Parallel 
                 Typical 
                 I/O 
                 Standard 
               
               
                   
                 Port 
                 Usage 
                 Address 
                 Interrupt 
               
               
                   
                   
               
               
                   
                 Parallel 1 
                 LPF1 
                 378H-37FH 
                 IRQ7 
               
               
                   
                   
               
            
           
         
       
     
     4.7K-ohm pull-ups (+5V) are typically provided to the following parallel port signals: 
     STROBE- 
     SLIN- 
     INIT- 
     AUTOFD- 
     Generally, if the parallel port will be connected to a cable for high speed data communication (as opposed to static digital output levels or static TTL level sensing), certain signals require a 2.2 nF capacitor connected to ground. These include: 
     PD 0 -PD 7   
     STRB- 
     Parallel port register are provided for the parallel port as appears from the table set out below: 
     
       
         
           
               
            
               
                   
               
               
                 Parallel Port Registers 
               
            
           
           
               
               
               
               
               
               
            
               
                   
                   
                 Signal 
                   
                 Active 
                 DB25F 
               
               
                 Register 
                 Bit 
                 Name 
                 In/Out 
                 High/Low 
                 Pin 
               
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 DATA 
                 0 
                 PD0 
                 I/O 
                 HIGH 
                 2 
               
               
                 (A + 0) 
                 1 
                 PD1 
                 I/O 
                 HIGH 
                 3 
               
               
                   
                 2 
                 PD2 
                 I/O 
                 HIGH 
                 4 
               
               
                   
                 3 
                 PD3 
                 I/O 
                 HIGH 
                 5 
               
               
                   
                 4 
                 PD4 
                 I/O 
                 HIGH 
                 6 
               
               
                   
                 5 
                 PD5 
                 I/O 
                 HIGH 
                 7 
               
               
                   
                 6 
                 PD6 
                 I/O 
                 HIGH 
                 8 
               
               
                   
                 7 
                 PD7 
                 I/O 
                 HIGH 
                 9 
               
               
                 STATUS 
                 0 
                 1 
                 — 
                 — 
                 — 
               
               
                 (A + 1)) 
                 1 
                 1 
                 — 
                 — 
                 — 
               
               
                   
                 2 
                 1 
                 — 
                 — 
                 — 
               
               
                   
                 3 
                 ERROR- 
                 IN 
                 LOW 
                 15 
               
               
                   
                 4 
                 SLCT- 
                 IN 
                 HIGH 
                 13 
               
               
                   
                 5 
                 PE 
                 IN 
                 HIGH 
                 12 
               
               
                   
                 6 
                 ACK- 
                 IN 
                 HIGH 
                 10 
               
               
                   
                 7 
                 BUSY 
                 IN 
                 LOW 
                 11 
               
               
                 CONTROL 
                 0 
                 STRB- 
                 OUT 
                 LOW 
                 1 
               
               
                 (A + 2) 
                 1 
                 AUTOFD- 
                 OUT 
                 LOW 
                 14 
               
               
                   
                 2 
                 INIT- 
                 OUT 
                 HIGH 
                 16 
               
               
                   
                 3 
                 SLCTIN- 
                 OUT 
                 LOW 
                 17 
               
               
                   
                 4 
                 IRQ ENABLE 
                 — 
                 HIGH 
                 — 
               
               
                   
                 5 
                 1 
                 — 
                 — 
                 — 
               
               
                   
                 6 
                 1 
                 — 
                 — 
                 — 
               
               
                   
                 7 
                 1 
                 — 
                 — 
                 — 
               
               
                   
               
            
           
         
       
     
     The DOS-compatible floppy drive interface  40  allows cable connections for up to four floppy drives. In pC-compatible systems, the BIOS and DOS support two drives. These are configure using the BIOS SETUP function. Hardware controls for two additional drives are provided. 
     The floppy drive interface supports the following standard floppy formats: 
     
       
         
           
               
               
               
               
               
             
               
                   
                   
               
               
                   
                 Capacity 
                 Drive Size 
                 Tracks 
                 Data Rate 
               
               
                   
                   
               
             
            
               
                   
                 360K 
                 5-1/4 inch 
                 40 
                 250 KHz 
               
               
                   
                 1.2M 
                 5-1/4 inch 
                 80 
                 500 KHz 
               
               
                   
                 720K 
                 3-1/2 inch 
                 80 
                 250 KHz 
               
               
                   
                 1.44M 
                 3-1/2 inch 
                 80 
                 500 KHz 
               
               
                   
                   
               
            
           
         
       
     
     The various floppy interface resources are given in the table below 
     
       
         
           
               
            
               
                   
               
               
                 Floppy Interface Resources 
               
            
           
           
               
               
               
            
               
                   
                 Resource 
                 Function 
               
               
                   
                   
               
               
                   
                 I/O Address 
                 3F2 FDC Digital Output Register (LDOR) 
               
               
                   
                 3F0h-3F7h 
                 3F4 FDC Main Status Register 
               
               
                   
                   
                 3F5 FDC Data Register 
               
               
                   
                   
                 3F7 FDC Control Register (LDCR) 
               
               
                   
                 IRQ6 
                 Interrupt 
               
               
                   
                 DRQ2BDACK2 
                 DMA Controller Channel 
               
               
                   
                   
               
            
           
         
       
     
     Outputs to the floppy drive and from the floppy drive are Aopen collector≅. Pull-up resistors are therefore required for proper termination, both on the SMX/386 board and on one of the attached floppy drives (not both). 
     330-Ohm pull-ups are required for the following floppy interface signals: 
     DSKCHG- 
     RDATA- 
     WRPRT- 
     TRK 0 - 
     INDEX- 
     The pin numbers and functions associated with the floppy drive are given in the table below: 
     
       
         
           
               
            
               
                   
               
               
                 Floppy Drive Interface 
               
            
           
           
               
               
               
               
               
               
            
               
                   
                   
                 Floppy 
                   
                   
                   
               
               
                   
                 Pin 
                 Pin 
                 Signal Name 
                 Function 
                 In/Out 
               
               
                   
                   
               
            
           
           
               
               
               
               
               
               
            
               
                   
                 11 
                 2 
                 DENSEL 
                 Speed/Precomp 
                   
               
               
                   
                   
                 4 
                 N/A 
                   
                 N/A 
               
               
                   
                   
                 6 
                 N/S 
                 Key pin 
                 N/A 
               
               
                   
                 12 
                 8 
                 INDEX- 
                 Index Pulse 
                 IN 
               
               
                   
                 13 
                 10 
                 MTR0- 
                 Motor On 0 
                 OUT 
               
               
                   
                 15 
                 12 
                 DRV1- 
                 Drive Select 2 
                 OUT 
               
               
                   
                 18 
                 14 
                 DRV0- 
                 Drive Select 1 
                 OUT 
               
               
                   
                 20 
                 16 
                 MTR1- 
                 Motor On 1 
                 OUT 
               
               
                   
                 22 
                 18 
                 DIR- 
                 Direction Select 
                 OUT 
               
               
                   
                 23 
                 20 
                 STEP- 
                 Step Pulse 
                 OUT 
               
               
                   
                 24 
                 22 
                 WDATA- 
                 Write Data 
                 OUT 
               
               
                   
                 25 
                 24 
                 WGATE- 
                 Write Gate 
                 OUT 
               
               
                   
                 26 
                 26 
                 TRK0- 
                 Track 0 
                 INPUT 
               
               
                   
                 27 
                 28 
                 WRPRT- 
                 Write Protect 
                 INPUT 
               
               
                   
                 28 
                 30 
                 RDATA- 
                 Read Data 
                 INPUT 
               
               
                   
                 29 
                 32 
                 HDSEL- 
                 Head Select 
                 OUT 
               
               
                   
                 30 
                 34 
                 DSKCHG- 
                 Disk Change 
                 INPUT 
               
               
                   
                   
                 1B33 
                 Ground 
                 Ground 
               
               
                   
                   
               
            
           
         
       
     
     The IDE hard drive interface  42  is a standard interface used in PC-compatible systems for haed disk drives. Up to two drives can be connected in a master-slave arrangement. The resources are depicted in the table below: 
     
       
         
           
               
            
               
                   
               
               
                 IDE Hard Disk Resources 
               
            
           
           
               
               
            
               
                 Resource 
                 Function 
               
               
                   
               
               
                 I/O Address 
                 Hard Disk Interface 
               
               
                 1F0h-1F7h 
               
               
                 IRQ14 
                 Interrupt 
               
               
                   
               
            
           
         
       
     
     The IDE interface pins are arranged to easily attach to a male PC-mounted ribbon-cable connector, the IDE drives typically being attached to the drive interface using a 40-pin ribbon cable. 
     The pin configuration for the IDE interface is given in the table below: 
     
       
         
           
               
            
               
                   
               
               
                 IDE Drive Interface 
               
            
           
           
               
               
               
               
               
            
               
                   
                 IDE 
                   
                   
                   
               
               
                 Pin 
                 Pin 
                 Signal Name 
                 Function 
                 In/Out 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 223 
                 1 
                 HDRESET- 
                 Reset signal from host 
                 OUT 
               
               
                   
                 2 
                 GND 
                 Ground 
                 OUT 
               
               
                 224 
                 3 
                 IDED7 
                 Data bit 7 
                 I/O 
               
               
                 225 
                 4 
                 HDD08 
                 Data bit 8 
                 I/O 
               
               
                 226 
                 5 
                 HDD06 
                 Data bit 6 
                 I/O 
               
               
                 227 
                 6 
                 HDD09 
                 Data bit 9 
                 I/O 
               
               
                 228 
                 7 
                 HDD05 
                 Data bit 5 
                 I/O 
               
               
                 229 
                 8 
                 HDD10 
                 Data bit 10 
                 I/O 
               
               
                 230 
                 9 
                 HDD04 
                 Data bit 4 
                 I/O 
               
               
                 231 
                 10 
                 HDD11 
                 Data bit 11 
                 I/O 
               
               
                 232 
                 11 
                 HDD03 
                 Data bit 3 
                 I/O 
               
               
                 233 
                 12 
                 HDD12 
                 Data bit 12 
                 I/O 
               
               
                 234 
                 13 
                 HDD02 
                 Data bit 2 
                 I/O 
               
               
                 235 
                 14 
                 HDD13 
                 Data bit 13 
                 I/O 
               
               
                 236 
                 15 
                 HDD01 
                 Data bit 1 
                 I/O 
               
               
                 237 
                 16 
                 HDD14 
                 Data bit 14 
                 I/O 
               
               
                 238 
                 17 
                 HDD00 
                 Data bit 0 
                 I/O 
               
               
                 239 
                 18 
                 HDD15 
                 Data bit 15 
                 I/O 
               
               
                   
                 19 
                 GND 
                 Ground 
                 OUT 
               
               
                   
                 20 
                 KEY 
                 Keyed pin 
                 N/C 
               
               
                   
                 21 
                 N/A 
                 Reserved 
                 N/C 
               
               
                   
                 22 
                 GND 
                 Ground 
                 OUT 
               
               
                 240 
                 23 
                 HDIOW- 
                 Write strobe 
                 OUT 
               
               
                   
                 24 
                 GND 
                 Ground 
                 OUT 
               
               
                 1 
                 25 
                 HDIOR- 
                 Read strobe 
                 OUT 
               
               
                   
                 26 
                 GND 
                 Ground 
                 OUT 
               
               
                   
                 27 
                 RSVD 
                 Reserved 
                 N/C 
               
               
                 2 
                 28 
                 HDALE 
                 Address latch enable 
                 OUT 
               
               
                   
                 29 
                 RSVD 
                 Reserved 
                 N/C 
               
               
                   
                 30 
                 GND 
                 Ground 
                 OUT 
               
               
                 237 
                 31 
                 HED 14 
                 Drive interrupt request 
                 IN 
               
               
                   
               
            
           
         
       
     
     One embodiment of the pin configuration for the module  10  as a whole is illustrated in FIG.  4  and is given in the pin description table below: 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                 Pin 
                 Pin Name 
                 Description 
                 Type 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 1 
                 HDIOR- 
                 IDE I/O Read, active low. Buffered version of 
                 O24 
               
               
                   
                   
                 IOR 
               
               
                 2 
                 HDALE 
                 IDE Address Latch Enable, active high. 
                 O24 
               
               
                   
                   
                 Buffered version of BALE 
               
               
                 3 
                 IRQ14 
                 IDE Interrupt Request 14. For use with IDE 
                 I 
               
               
                   
                   
                 interface. Same signal appears on pin 90. 
               
               
                 4 
                 IOCS16 
                 IDE I/O Chip Select 16. A low requests a 
                 I 
               
               
                   
                   
                 16-bit transfer on the SA bus. Same signal 
               
               
                   
                   
                 appears on pin 238. This one is used for 
               
               
                   
                   
                 the IDE interface. 
               
               
                 5 
                 HDA1 
                 IDE Address 1. Buffered version of SA1. 
                 O24 
               
               
                 6 
                 HDAO 
                 IDE Address 0. Buffered version of SA0 
                 O24 
               
               
                 7 
                 HDA2 
                 IDE Address 2. Buffered version of SA2 
                 O24 
               
               
                 8 
                 HDCS- 
                 IDE Chip Select. A low indicates that data is 
                 O24 
               
               
                   
                   
                 being transferred to or from the IDE drive. 
               
               
                 9 
                 FDCS- 
                 Floppy disk chip Select. A low indicates that 
                 O24 
               
               
                   
                   
                 data is being transferred to or from the floppy 
               
               
                   
                   
                 disk. 
               
               
                 10 
                 LEDIN 
                 LED signal form IDE drive 
                 I 
               
               
                 11 
                 DENSEL 
               
               
                 12 
                 INDEX- 
                 Floppy disk index pulse, input from drive 
                 I 
               
               
                 13 
                 MTRO- 
                 Floppy disk active lower open drain output 
               
               
                   
                   
                 selects motor driver 0. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s 
               
               
                   
                   
                 Digital Output Register (DOR). 
               
               
                 14 
                 MTR2- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 2. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s 
               
               
                   
                   
                 Digital Output Register (DOR). 
               
               
                 15 
                 DRV1- 
                 Floppy disk active lower open drain output that 
               
               
                   
                   
                 selects floppy drive 1 
               
               
                 16 
                 DRV3- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 3 
               
               
                 17 
                 GND 
               
               
                 18 
                 DRV0- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 0 
               
               
                 19 
                 DRV2- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 2 
               
               
                 20 
                 MTR1- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 1. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s 
               
               
                   
                   
                 Digital Output Register (DOR). 
               
               
                 21 
                 MTR3- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 3. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s 
               
               
                   
                   
                 Digital Output Register (DOR). 
               
               
                 22 
                 DIR 
                 Floppy disk open drain output that controls 
               
               
                   
                   
                 floppy read/write head movement direction. 
               
               
                   
                   
                 Low = set pin. 
               
               
                 23 
                 STEP- 
                 Floppy disk active low output provides the step 
               
               
                   
                   
                 pulse to move the floppy read/write head 
               
               
                 24 
                 WDATA- 
                 Floppy disk active lower signal writes 
               
               
                   
                   
                 precompensated serial data to the selected 
               
               
                   
                   
                 floppy drive. This is a high open current drain 
               
               
                   
                   
                 output and is gated internally with WGATE-. 
               
               
                 25 
                 WGATE- 
                 Floppy disk active low open drain signal that 
               
               
                   
                   
                 enables the head to write onto the floppy disk. 
               
               
                 26 
                 TRK0- 
                 Floppy disk active lower Schmitt input 
                 IS 
               
               
                   
                   
                 indicates that the head is on track 0 of 
               
               
                   
                   
                 the selected drive 
               
               
                 27 
                 WRPRT- 
                 Floppy disk active low Schmitt input indicating 
                 IS 
               
               
                   
                   
                 that the disk is write protected. Any WDATA- 
               
               
                   
                   
                 command is ignored. 
               
               
                 28 
                 RDATA- 
                 Floppy disk active lower Schmitt input that 
                 IS 
               
               
                   
                   
                 reads raw data from the floppy disk. 
               
               
                 29 
                 HDSEL 
                 Floppy disk open drain output that selects the 
               
               
                   
                   
                 head on the selected drive. Low = side 0. 
               
               
                 30 
                 DSKCHG 
                 Floppy disk input signal indicating that the 
                 I 
               
               
                   
                   
                 floppy door has been opened. 
               
               
                 31 
                 5VBB 
               
               
                 32 
                 GND 
               
               
                 33 
                 PFI 
                 Powerfail 
               
               
                 34 
                 PFO 
                 Powerfail 
               
               
                 35 
                 MR- 
                 Powerfail 
               
               
                 36 
                 RTCIRQ 
                 Alarm output from the onboard real time clock 
               
               
                 37 
                 WDO 
                 Watchdog timer 
               
               
                 38 
                 SA00 
                 ISA System Address 00 
                 O24 
               
               
                 39 
                 OSC 
                 ISA 14.318 MHz clock. This clock is 
               
               
                   
                   
                 asynchronous to all other system clocks 
               
               
                 40 
                 SA01 
                 ISA System Address 01 
                 O24 
               
               
                 41 
                 SA02 
                 ISA System Address 02 
                 O24 
               
               
                 42 
                 BALE 
                 ISA Buffered Address Latch Enable 
               
               
                 43 
                 SA03 
                 ISA System Address 03 
                 O24 
               
               
                 44 
                 SD15 
                 ISA System Data 15 
               
               
                 45 
                 TC 
                 ISA DMA Terminal Court 
               
               
                 46 
                 SA04 
                 ISA System Address 04 
                 O24 
               
               
                 47 
                 MASTER- 
                 ISA 
               
               
                 48 
                 SD14 
                 ISA System Data 14 
               
               
                 49 
                 DACK2- 
                 ISA DMA 2 Acknowledge strobe 
               
               
                 50 
                 SA05 
                 ISA System Address 05 
                 O24 
               
               
                 51 
                 SD13 
                 ISA System Data 13 
               
               
                 52 
                 IRQ3 
                 ISA Interrupt Request 3 
                 I 
               
               
                 53 
                 SA06 
                 ISA System Address 06 
                 O24 
               
               
                 54 
                 DRQ7 
                 ISA DMA 7 Request 
                 I 
               
               
                 55 
                 SD12 
                 ISA System Data 12 
               
               
                 56 
                 IRQ4 
                 ISA Interrupt Request 4 
                 I 
               
               
                 57 
                 SA07 
                 ISA System Address 07 
                 O24 
               
               
                 58 
                 DACK7- 
                 ISA DMA 7 Acknowledge strobe 
               
               
                 59 
                 SD11 
                 ISA System Data 11 
               
               
                 60 
                 IRQ5 
                 ISA Interrupt Request 5 
                 I 
               
               
                 61 
                 SA08 
                 ISA System Address 08 
                 O24 
               
               
                 62 
                 DRQ6 
                 ISA DMA 6 Request 
                 I 
               
               
                 63 
                 SD10 
                 ISA System Data 10 
               
               
                 64 
                 IRQ6OUT 
                 Floppy disk interrupt request. Normally 
               
               
                   
                   
                 connects to IRQ6 (pin 65) 
               
               
                 65 
                 IRQ6 
                 ISA Interrupt Request 6 
                 I 
               
               
                 66 
                 SA09 
                 ISA System Address 09 
                 O24 
               
               
                 67 
                 GND 
               
               
                 68 
                 DACK6- 
                 ISA DMA 6 Acknowledge strobe 
               
               
                 69 
                 SD09 
                 ISA System Data 09 
               
               
                 70 
                 IRQ7OUT 
                 Parallel port interrupt request. Normally 
               
               
                   
                   
                 connects to IRQ7 (pin 71). 
               
               
                 71 
                 IRQ7 
                 ISA Interrupt Request 7 
                 I 
               
               
                 72 
                 SA10 
                 ISA System Address 10 
                 O24 
               
               
                 73 
                 DRQ5 
                 ISA DMA 5 Request 
                 I 
               
               
                 74 
                 SD08 
                 ISA System Data 08 
               
               
                 75 
                 SYSCLK 
                 ISA System clock 
               
               
                 76 
                 SA11 
                 ISA System Address 11 
                 O24 
               
               
                 77 
                 DACK5- 
                 ISA DMA 5 Acknowledge strobe 
               
               
                 78 
                 MEMW- 
                 ISA active low memory write strobe 
               
               
                 79 
                 RE- 
                 ISA active low signal indicating current bus 
               
               
                   
                 FRESH- 
                 cycle is a memory refresh 
               
               
                 80 
                 SA12 
                 ISA System Address 12 
                 O24 
               
               
                 81 
                 DRQO 
                 ISA DMA 0 Request 
                 I 
               
               
                 82 
                 MEMR- 
                 ISA active low memory read strobe 
               
               
                 83 
                 DRQ1 
                 ISA DMA 1 Request 
                 I 
               
               
                 84 
                 SA13 
                 ISA System Address 13 
                 O24 
               
               
                 85 
                 VCC 
               
               
                 86 
                 DACKO- 
                 ISA DSMA 0 Acknowledge strobe 
               
               
                 87 
                 LA17 
                 ISA Latched Address 17 
                 O24 
               
               
                 88 
                 DACK1- 
                 ISA DMA 1 Acknowledge strobe 
               
               
                 89 
                 SA14 
                 ISA System Address 14 
                 O24 
               
               
                 90 
                 IRQ14 
                 ISA Interrupt Request 14, normally used for 
                 I 
               
               
                   
                   
                 IDE interface 
               
               
                 91 
                 LA18 
                 ISA Latched address 18 
                 O24 
               
               
                 92 
                 DRQ3 
                 ISA DMA 3 Request strobe 
               
               
                 93 
                 SA15 
                 ISA System Address 15 
                 O24 
               
               
                 94 
                 IRQ15 
                 ISA Interrupt Request 15 
                 I 
               
               
                 95 
                 LA19 
                 ISA Latched Address 19 
                 O24 
               
               
                 96 
                 DACK3- 
                 ISA DMA 3 Acknowledge strobe 
               
               
                 97 
                 SA16 
                 ISA System Address 16 
                 O24 
               
               
                 98 
                 IRQ12 
                 ISA Interrupt Request 12 
                 I 
               
               
                 99 
                 LA20 
                 ISA Latched Address 20 
                 O24 
               
               
                 100 
                 IOR- 
                 ISA I/O Read strobe 
               
               
                 101 
                 SA17 
                 ISA System Address 17 
                 O24 
               
               
                 102 
                 GND 
               
               
                 103 
                 IRQ11  
                 ISA Interrupt Request 11 
                 I 
               
               
                 104 
                 LA21 
                 ISA Latched Address 21 
                 O24 
               
               
                 105 
                 IOW- 
                 ISA I/O Write strobe 
               
               
                 106 
                 SA18 
                 ISA System Address 18 
                 O24 
               
               
                 107 
                 IRQ10 
                 ISA Interrupt Request 10 
                 I 
               
               
                 108 
                 LA22 
                 ISA Latched Address 22 
                 O24 
               
               
                 109 
                 SMEMR- 
                 ISA System Memory Read strobe 
               
               
                 110 
                 SA19 
                 ISA System Address 19 
                 O24 
               
               
                 111 
                 IOCS16- 
                 ISA 16-bit I/O Chip Select request Indicates 
                 I 
               
               
                   
                   
                 that the current I/O transaction is 16-bits. 
               
               
                 112 
                 LA23 
                 ISA Latched Address 23 
                 O24 
               
               
                 113 
                 SMEMW- 
                 ISA System Memory Write strobe 
               
               
                 114 
                 AEN 
                 ISA Address Enable 
               
               
                 115 
                 MEMCS- 
                 ISA 16-bit Memory Chip Select request. 
                 I 
               
               
                   
                 16 
                 Indicates that the current memory transaction is 
               
               
                   
                   
                 16-bits. 
               
               
                 116 
                 SBHE- 
                 ISA System Byte High Enable 
               
               
                 117 
                 IOCH- 
                 ISA I/O Channel Ready. A low adds wait states 
                 I 
               
               
                   
                 RDY 
                 to the current ISA bus cycle 
               
               
                 118 
                 SD00 
                 ISA System Data 00 
               
               
                 119 
                 0WS 
                 ISA active low causing current memory cycle 
                 I 
               
               
                   
                   
                 to be completed without additional wait 
               
               
                   
                   
                 states. 
               
               
                 120 
                 SD01 
                 ISA System Data 01 
               
               
                 121 
                 SD02 
                 ISA System Data 02 
               
               
                 122 
                 DRQ2 
                 Floppy DMA 2 Request Normally connected to 
               
               
                   
                 OUT 
                 DRQ2 (pin 123) 
               
               
                 123 
                 DRQ2 
                 ISA DMA 2 Request strobe 
                 I 
               
               
                 124 
                 SD03 
                 ISA System Data 03 
               
               
                 125 
                 SD04 
                 ISA System Data 04 
               
               
                 126 
                 IRQ9 
                 ISA Interrupt Request 09 
                 I 
               
               
                 127 
                 SD05 
                 ISA System Data 05 
               
               
                 128 
                 SD06 
                 ISA System Data 06 
               
               
                 129 
                 RESET 
                 ISA active high system reset signal 
               
               
                   
                 DRV 
               
               
                 130 
                 SD07 
                 ISA System Data 07 
               
               
                 131 
                 IOCH- 
                 ISA gated non-maskable interrupt input 
                 I 
               
               
                   
                 CHK- 
               
               
                 132 
                 HISPEED 
                 Input to select CPU speed. High = high speed. 
                 I 
               
               
                 133 
                 SPKR 
                 Speaker output 
               
               
                 134 
                 KDATA 
                 Keyboard data 
               
               
                 135 
                 KCLOCK 
                 Keyboard clock 
               
               
                 136 
                 PWRDN- 
               
               
                 137 
                 GND 
               
               
                 138 
                 COLOR 
                 Video Color/Mono jumper 
                 I 
               
               
                 139 
                 KBLOCK 
                 Keyboard lock. Low blocks keyboard input 
                 I 
               
               
                 140 
                 SLCT 
                 Parallel Port 
               
               
                 141 
                 PE 
                 Parallel Port 
               
               
                 142 
                 BUSY 
                 Parallel Port 
               
               
                 143 
                 ACK- 
                 Parallel Port 
               
               
                 144 
                 PD7 
                 Parallel Port Data 7 
               
               
                 145 
                 PD6 
                 Parallel Port Data 6 
               
               
                 146 
                 PD5 
                 Parallel Port Data 5 
               
               
                 147 
                 PD4 
                 Parallel Port Data 4 
               
               
                 148 
                 PD3 
                 Parallel Port Data 3 
               
               
                 149 
                 SLCTIN- 
                 Parallel Port 
               
               
                 150 
                 PD2 
                 Parallel Port Data 2 
               
               
                 151 
                 INIT- 
                 Parallel Port 
               
               
                 152 
                 PD1 
                 Parallel Port Data 1 
               
               
                 153 
                 ERR- 
                 Parallel Port 
               
               
                 154 
                 GND 
               
               
                 155 
                 PD0 
                 Parallel Port Data 0 
               
               
                 156 
                 AUTOFD 
                 Parallel Port 
               
               
                 157 
                 STRB- 
                 Parallel Port 
               
               
                 158 
                 DCD2 
                 Serial Port 2 Data Carrier Detect 
               
               
                 159 
                 DSR2 
                 Serial Port 2 Data Set Ready 
               
               
                 160 
                 RXD2 
                 Serial Port 2 Receive Data 
               
               
                 161 
                 RTS2 
                 Serial Port 2 Request To Send 
               
               
                 162 
                 TXD2 
                 Serial Port 2 Transmit Data 
               
               
                 163 
                 CTS2 
                 Serial Port 2 Clear To Send 
               
               
                 164 
                 DTR2 
                 Serial Port 2 Data Terminal Ready 
               
               
                 165 
                 R12 
                 Serial Port 2 Ring Indicator 
               
               
                 166 
                 DCD1 
                 Serial Port 1 Data Carrier Detect 
               
               
                 167 
                 DSR1 
                 Serial Port 1 Data Set Ready 
               
               
                 168 
                 RXD1 
                 Serial Port 1 Receive Data 
               
               
                 169 
                 RTS1 
                 Serial Port 1 Request to Send 
               
               
                 170 
                 TXD1 
                 Serial Port 1 Transmit Data 
               
               
                 171 
                 CTS1 
                 Serial Port 1 Clear to Send 
               
               
                 172 
                 DTR1 
                 Serial Port 1 Data Terminal Ready 
               
               
                 173 
                 RI1 
                 Serial Port 1 Ring Indicator 
               
               
                 174 
                 GAME- 
               
               
                   
                 CS- 
               
               
                 175 
                 RAS3- 
                 DRAM Row Address Strobe 3 
               
               
                 176 
                 RAS2- 
                 DRAM Row Address Strobe 2 
               
               
                 177 
                 RAS1- 
                 DRAM Row Address Strobe 1 
               
               
                 178 
                 RAS0- 
                 DRAM Row Address Strobe 0 
               
               
                 179 
                 DP1 
                 DRAM parity bit for high byte memory 
               
               
                 180 
                 DP0 
                 DRAM parity bit for low byte memory 
               
               
                 181 
                 D15 
                 DRAM Data Bit 15 
               
               
                 182 
                 D07 
                 DRAM Data Bit 7 
               
               
                 183 
                 D14 
                 DRAM Data Bit 14 
               
               
                 184 
                 D06 
                 DRAM Data Bit 6 
               
               
                 185 
                 DRWE- 
                 DRAM memory write strobe 
               
               
                 186 
                 D13 
                 DRAM Data Bit 13 
               
               
                 187 
                 GND 
               
               
                 188 
                 D05 
                 DRAM Data Bit 5 
               
               
                 189 
                 MA10 
                 DRAM multiplexed memory address 10 
               
               
                 190 
                 MA09 
                 DRAM multiplexed memory address 9 
               
               
                 191 
                 MA08 
                 DRAM multiplexed memory address 8 
               
               
                 192 
                 D12 
                 DRAM Data Bit 12 
               
               
                 193 
                 D04 
                 DRAM Data Bit 4 
               
               
                 194 
                 MA07 
                 DRAM multiplexed memory address 7 
               
               
                 195 
                 MA06 
                 DRAM multiplexed memory address 6 
               
               
                 196 
                 D11 
                 DRAM Data Bit 11 
               
               
                 197 
                 D03 
                 DRAM Data Bit 3 
               
               
                 198 
                 MA05 
                 DRAM multiplexed memory address 5 
               
               
                 199 
                 MA04 
                 DRAM multiplexed memory address 4 
               
               
                 200 
                 D10 
                 DRAM Data Bit 10 
               
               
                 201 
                 D01 
                 DRAM Data Bit 2 
               
               
                 202 
                 MA03 
                 DRAM multiplexed memory address 3 
               
               
                 203 
                 MA02 
                 DRAM multiplexed memory address 2 
               
               
                 204 
                 D09 
                 DRAM Data Bit 9 
               
               
                 205 
                 VCC 
               
               
                 206 
                 D01 
                 DRAM Data Bit 1 
               
               
                 207 
                 MA01 
                 DRAM multiplexed memory address 1 
               
               
                 208 
                 MA00 
                 DRAM multiplexed memory address 0 
               
               
                 209 
                 D08 
                 DRAM Data Bit 8 
               
               
                 210 
                 D00 
                 DRAM Data Bit 0 
               
               
                 211 
                 CASH3- 
                 DRAM Column Address Strobe, High byte 3 
               
               
                 212 
                 CASL3- 
                 DRAM Column Address Strobe, Low byte 3 
               
               
                 213 
                 CASH2- 
                 DRAM Column Address Strobe, High byte 2 
               
               
                 214 
                 CASL2- 
                 DRAM Column Address Strobe, Low byte 2 
               
               
                 215 
                 CASH1- 
                 DRAM Column Address Strobe, High byte 1 
               
               
                 216 
                 CASL1- 
                 DRAM Column Address Strobe, Low byte 1 
               
               
                 217 
                 CASH0- 
                 DRAM Column Address Strobe, High byte 0 
               
               
                 218 
                 CASL0- 
                 DRAM Column Address Strobe, Low byte 0 
               
               
                 219 
                 BDIS 
               
               
                 220 
                 XROM- 
               
               
                   
                 CS- 
               
               
                 221 
                 LEDOUT- 
               
               
                 222 
                 GND 
               
               
                 223 
                 HDRE- 
                 IDE 
               
               
                   
                 SET- 
               
               
                 224 
                 IDED07 
                 IDE Data Bit 7 
               
               
                 225 
                 HDD08 
                 IDE Data Bit 8 
               
               
                 226 
                 HDD06 
                 IDE Data Bit 6 
               
               
                 227 
                 HDD09 
                 IDE Data Bit 9 
               
               
                 228 
                 HDD05 
                 IDE Data Bit 5 
               
               
                 229 
                 HDD10 
                 IDE Data Bit 10 
               
               
                 230 
                 HDD04 
                 IDE Data Bit 4 
               
               
                 231 
                 HDD11 
                 IDE Data Bit 11 
               
               
                 232 
                 HDD03 
                 IDE Data Bit 3 
               
               
                 233 
                 HDD12 
                 IDE Data Bit 12 
               
               
                 234 
                 HDD02 
                 IDE Data Bit 2 
               
               
                 235 
                 HDD13 
                 IDE Data Bit 13 
               
               
                 236 
                 HDD01 
                 IDE Data Bit 1 
               
               
                 237 
                 HED14 
                 IDE Data Bit 14 
               
               
                 238 
                 HDD00 
                 IDE Data Bit 0 
               
               
                 239 
                 HDD15 
                 IDE Data Bit 15 
               
               
                 240 
                 HDIOW- 
                 IDE buffered I/O Write strobe 
               
               
                   
               
            
           
         
       
     
     As mentioned above, the core logic  26  supports a DRAM bus  22  and an ISA compatible expansion bus  24  complying in number and signal type with the IEEE-P996 requirements (and corresponding to the ISA (Industry Standard Architecture) requirements). The pin configuration for the expansion bus  24  is given in the table below with corresponding pin numbers for expansion bus connectors A, B, C, D. The bus  24  comprises 94 pins that includes VCC and two GND pins. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                   
                   
               
               
                   
                   
                 Signal 
                   
                 In/ 
                   
                   
               
               
                   
                 Pin 
                 Name 
                 Function 
                 Out 
                 Current 
                 Load* 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 38 
                 A31 
                 SA00 
                 Address bit 0 
                 I/O 
                 12 mA 
                 PU 
               
               
                 39 
                 B30 
                 OSC 
                 14.318 MHz clock 
                 Out 
                  6 mA 
                 33 SER 
               
               
                 40 
                 A30 
                 SA01 
                 Address bit 1 
                 I/O 
                 12 mA 
                 PU 
               
               
                 41 
                 A29 
                 SA02 
                 Address bit 2 
                 I/O 
                 12 mA 
                 PU 
               
               
                 42 
                 B28 
                 BALE 
                 Address latch enable 
                 Out 
                 12 mA 
               
               
                 43 
                 A28 
                 SA03 
                 Address bit 3 
                 I/O 
                 12 mA 
                 PU 
               
               
                 44 
                 C18 
                 SD15 
                 System Data bit 15 
                 I/O 
                 12 mA 
                 PU 
               
               
                 45 
                 B27 
                 TC 
                 DMA Terminal 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Count 
               
               
                 46 
                 A27 
                 SA04 
                 Address bit 4 
                 I/O 
                 12 mA 
                 PU 
               
               
                 47 
                 D17 
                 MAS- 
                 Bus master assert 
                 In 
                 N/A 
                 330 PU 
               
               
                   
                   
                 TER- 
               
               
                 48 
                 C17 
                 SD14 
                 System Data bit 14 
                 I/O 
                 24 mA 
                 PU 
               
               
                 49 
                 B26 
                 DACK- 
                 DMA Acknowledge 2 
                 Out 
                  4 mA 
               
               
                   
                   
                 2- 
               
               
                 50 
                 A26 
                 SA05 
                 Address bit 5 
                 I/O 
                 12 mA 
                 PU 
               
               
                 51 
                 C16 
                 SD13 
                 System Data bit 13 
                 I/O 
                 24 mA 
                 PU 
               
               
                 52 
                 B25 
                 IRQ3 
                 Interrupt Request 3 
                 In 
                 N/A 
                 PU 
               
               
                 53 
                 A25 
                 SA06 
                 Address bit 6 
                 I/O 
                 12 mA 
                 PU 
               
               
                 54 
                 D15 
                 DRQ7 
                 DMA Request 7 
                 In 
                 N/A 
                 PD 
               
               
                 55 
                 C15 
                 SD12 
                 System Data bit 12 
                 I/O 
                 24 mA 
                 PU 
               
               
                 56 
                 B24 
                 IRQ4 
                 Interrupt Request 4 
                 In 
                 N/A 
                 PU 
               
               
                 57 
                 A24 
                 SA07 
                 Address bit 7 
                 I/O 
                 12 mA 
                 PU 
               
               
                 58 
                 D14 
                 DACK- 
                 DMA Acknowledge 7 
                 Out 
                  4 mA 
               
               
                   
                   
                 7- 
               
               
                 59 
                 C14 
                 SD11 
                 System Data bit 11 
                 I/O 
                 24 mA 
                 PU 
               
               
                 60 
                 B23 
                 IRQ5 
                 Interrupt Request 5 
                 In 
                 N/A 
                 PU 
               
               
                 61 
                 A23 
                 SA08 
                 Address bit 8 
                 I/O 
                 12 mA 
                 PU 
               
               
                 62 
                 D13 
                 DRQ6 
                 DMA Request 6 
                 In 
                 N/A 
                 PD 
               
               
                 63 
                 C13 
                 SD10 
                 System Data bit 10 
                 I/O 
                 24 mA 
                 PU 
               
               
                 64 
                   
                 IRQ6- 
                 Floppy Disk Interrupt 
               
               
                   
                   
                 OUT 
                 Request 
               
               
                 65 
                 B22 
                 IRQ6 
                 Interrupt Request 6 
                 In 
                 N/A 
                 PU 
               
               
                 66 
                 A22 
                 SA09 
                 Address bit 9 
                 I/O 
                 12 mA 
                 PU 
               
               
                 67 
                   
                 GND 
               
               
                 68 
                 D12 
                 DACK- 
                 DMA Acknowledge 6 
                 Out 
                  4 mA 
               
               
                   
                   
                 6- 
               
               
                 69 
                 C12 
                 SD9 
                 System Data bit 9 
                 I/O 
                 24 mA 
                 PU 
               
               
                 70 
                   
                 IRQ7- 
                 Parallel Port Interrupt 
               
               
                   
                   
                 OUT 
                 Request 
               
               
                 71 
                 B21 
                 IRQ7 
                 Interrupt Request 7 
                 In 
                 N/A 
                 PU 
               
               
                 72 
                 A21 
                 SA10 
                 Address bit 10 
                 I/O 
                 12 mA 
                 PU 
               
               
                 73 
                 D11 
                 DRQ5 
                 DMA Request 5 
                 In 
                 N/A 
                 PD 
               
               
                 74 
                 C11 
                 SD08 
                 System Data bit 8 
                 I/O 
                 24 mA 
                 PU 
               
               
                 75 
                 B20 
                 SYS- 
                 System clock (8 
                 Out 
                 12 mA 
               
               
                   
                   
                 CLK 
                 MHz) 
               
               
                 76 
                 A20 
                 SA11 
                 Address bit 11 
                 I/O 
                 12 mA 
                 PU 
               
               
                 77 
                 D10 
                 DACK- 
                 DMA Acknowledge 5 
                 Out 
                  4 mA 
               
               
                   
                   
                 5- 
               
               
                 78 
                 C10 
                 MEM- 
                 Memory Write 
                 I/O 
                  6 mA 
                 PU, 33 
               
               
                   
                   
                 W 
                   
                   
                   
                 SER 
               
               
                 79 
                 B19 
                 REFR- 
                 Memory Refresh 
                 I/O 
                  6 mA 
                 470 PU, 
               
               
                   
                   
                 ESH- 
                   
                   
                   
                 33 SER 
               
               
                 80 
                 A19 
                 SA12 
                 Address bit 12 
                 I/O 
                 12 mA 
                 PU 
               
               
                 81 
                 D9 
                 DRQ0 
                 DMA Request 0 
                 In 
                 N/A 
                 PD 
               
               
                 82 
                 C9 
                 MEMR- 
                 Memory Read 
                 I/O 
                  6 mA 
                 PU, 33 
               
               
                   
                   
                   
                   
                   
                   
                 SER 
               
               
                 83 
                 B18 
                 DRQ1 
                 DMA Request 1 
                 In 
                 N/A 
                 PD 
               
               
                 84 
                 A18 
                 SA13 
                 Address bit 13 
                 I/O 
                 12 mA 
                 PU 
               
               
                 85 
                   
                 VCC 
               
               
                 86 
                 D8 
                 DACK- 
                 DMA Acknowledge 0 
                 Out 
                  4 mA 
               
               
                   
                   
                 0- 
               
               
                 87 
                 C8 
                 LA17 
                 Address bit 17 
                 I/O 
                 24 mA 
               
               
                 88 
                 B17 
                 DACK- 
                 DMA Acknowledge 1 
                 Out 
                  4 mA 
               
               
                   
                   
                 1- 
               
               
                 89 
                 A17 
                 SA14 
                 Address bit 14 
                 I/O 
                 12 mA 
                 PU 
               
               
                 90 
                 D7 
                 IRQ14 
                 Interrupt Request 14 
                 In 
                 N/A 
                 PU 
               
               
                 91 
                 C7 
                 LA18 
                 Address bit 18 
                 I/O 
                 24 mA 
               
               
                 92 
                 B16 
                 DRQ3 
                 DMA Request 3 
                 In 
                 N/A 
                 PD 
               
               
                 93 
                 A16 
                 SA15 
                 Address bit 15 
                 I/O 
                 12 mA 
                 PU 
               
               
                 94 
                 D6 
                 IRQ15 
                 Interrupt Request 15 
                 In 
                 N/A 
                 PU 
               
               
                 95 
                 C6 
                 LA19 
                 Address bit 19 
                 I/O 
                 24 mA 
               
               
                 96 
                 B15 
                 DACK- 
                 DMA Acknowledge 3 
                 Out 
                  4 mA 
               
               
                   
                   
                 3- 
               
               
                 97 
                 A15 
                 SA16 
                 Address bit 16 
                 I/O 
                 12 mA 
                 PU 
               
               
                 98 
                 D5 
                 IRQ12 
                 Interrupt Request 12 
                 In 
                 N/A 
                 PU 
               
               
                 99 
                 C5 
                 LA20 
                 Address bit 20 
                 I/O 
                 24 mA 
               
               
                 100 
                 B14 
                 IOR- 
                 I/O Read 
                 I/O 
                  6 mA 
                 PU 
               
               
                 101 
                 A14 
                 SA17 
                 Address bit 17 
                 I/O 
                 12 mA 
                 PU 
               
               
                 102 
                   
                 GND 
               
               
                 103 
                 D4 
                 IRQ11 
                 Interrupt Request 11 
                 In 
                 N/A 
                 PU 
               
               
                 104 
                 C4 
                 LA21 
                 Address bit 21 
                 I/O 
                 24 mA 
               
               
                 105 
                 B13 
                 IOW- 
                 I/O Write 
                 I/O 
                  6 mA 
                 PU 
               
               
                 106 
                 A13 
                 SA18 
                 Address bit 18 
                 I/O 
                 12 mA 
                 PU 
               
               
                 107 
                 D3 
                 IRQ10 
                 Interrupt Request 10 
                 In 
                 N/A 
                 PU 
               
               
                 108 
                 C3 
                 LA22 
                 Address bit 22 
                 I/O 
                 24 mA 
               
               
                 109 
                 B12 
                 SME- 
                 Mem Read (lower 
                 I/O 
                  6 mA 
                 33 SER 
               
               
                   
                   
                 MR- 
                 1MB) 
               
               
                 110 
                 A12 
                 SA19 
                 Address bit 19 
                 I/O 
                 12 mA 
                 PU 
               
               
                 111 
                 D2 
                 IOCS- 
                 16-bit I/O access 
                 In 
                 N/A 
                 330 PU 
               
               
                   
                   
                 16- 
               
               
                 112 
                 C2 
                 LA23 
                 Address bit 23 
                 I/O 
                 24 mA 
               
               
                 113 
                 B11 
                 SMEM- 
                 Mem Write (lower 1 
                 I/O 
                  6 mA 
                 33 SER 
               
               
                   
                   
                 W 
                 MB) 
               
               
                 114 
                 A11 
                 AEN 
                 Address Enable 
                 I/O 
                 12 mA 
                 PU 
               
               
                 115 
                 D1 
                 MEMC- 
                 16-bit mem access 
                 In 
                 N/A 
                 330 PU 
               
               
                   
                   
                 S16- 
               
               
                 116 
                 C1 
                 SBHE- 
                 Bus High Enable 
                 I/O 
                 12 mA 
                 PU 
               
               
                 117 
                 A10 
                 IOCH 
                 Processor Ready Ctrl 
                 In 
                 N/A 
                 1K PU 
               
               
                   
                   
                 RDY 
               
               
                 118 
                 A9 
                 SD00 
                 System Data bit 0 
                 I/O 
                 24 mA 
                 PU 
               
               
                 119 
                 B8 
                 END- 
                 Zero wait state 
                 I/O 
                 N/A 
                 330 PU 
               
               
                   
                   
                 XFR 
               
               
                   
                   
                 (OWS-) 
               
               
                 120 
                 A8 
                 SD01 
                 System Data bit 1 
                 I/O 
                 24 mA 
                 PU 
               
               
                 121 
                 A7 
                 SD02 
                 System Data bit 2 
                 I/O 
                 24 mA 
                 PU 
               
               
                 122 
                   
                 DRQ2 
                 Floppy DMA 2 
               
               
                   
                   
                 OUT 
                 Request 
               
               
                 123 
                 B6 
                 DRQ2 
                 DMA request 2 
                 In 
                 N/A 
                 PD 
               
               
                 124 
                 A6 
                 SD03 
                 System Data bit 3 
                 I/O 
                 24 mA 
                 PU 
               
               
                 125 
                 A5 
                 SD04 
                 System Data bit 4 
                 I/O 
                 24 mA 
                 PU 
               
               
                 126 
                 B4 
                 IRQ9 
                 Interrupt request 9 
                 In 
                 N/A 
                 PU 
               
               
                 127 
                 A4 
                 SD05 
                 System Data bit 5 
                 I/O 
                 24 mA 
                 PU 
               
               
                 128 
                 A4 
                 SD06 
                 System Data bit 6 
                 I/O 
                 24 mA 
                 PU 
               
               
                 129 
                 B2 
                 RESET 
                 System reset signal 
                 Out 
                 24 mA 
               
               
                   
                   
                 DRY 
               
               
                 130 
                 A2 
                 SD07 
                 System Data bit 7 
                 I/O 
                 24 mA 
                 PU 
               
               
                 131 
                 A1 
                 IOCH- 
                 Sub NMI input 
                 In 
                 N/A 
                 4.7K 
               
               
                   
                   
                 CK- 
                   
                   
                   
                 PU 
               
               
                   
               
            
           
         
       
     
     An alternative embodiment of the pin configuration for the module  10  as a whole is illustrated in FIG.  5  and is given in the pin description table below: 
     
       
         
           
               
               
               
               
             
               
                   
               
               
                 Pin 
                 Pin Name 
                 Description 
                 Type 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
            
               
                 1 
                 HDIOR- 
                 IDE I/O Read, active low. Buffered version of 
                 O24 
               
               
                   
                   
                 IOR 
               
               
                 2 
                 HDALE 
                 IDE Address Latch Enable, active high. 
                 O24 
               
               
                   
                   
                 Buffered version of BALE 
               
               
                 3 
                 IRQ14 
                 IDE Interrupt Request 14. For use with IDE 
                 I 
               
               
                   
                   
                 interface. Same signal appears on pin 90. 
               
               
                 4 
                 IOCS16- 
                 IDE I/O Chip Select 16. A low requests a 16- 
                 I 
               
               
                   
                   
                 bit transfer on the SA bus. Same signal appears 
               
               
                   
                   
                 on pin 238. This one is used for the IDE 
               
               
                   
                   
                 interface. 
               
               
                 5 
                 HDA1 
                 IDE Address 1. Buffered version of SA1. 
                 O24 
               
               
                 6 
                 HDA0 
                 IDE Address 0. Buffered version of SA0 
                 O24 
               
               
                 7 
                 HDA2 
                 IDE Address 2. Buffered version of SA2 
                 O24 
               
               
                 8 
                 HDCS- 
                 IDE Chip Select. A low indicates that data is 
                 O24 
               
               
                   
                   
                 being transferred to or from the IDE drive. 
               
               
                 9 
                 FDCS- 
                 Floppy disk Chip Select. A low indicates that 
                 O24 
               
               
                   
                   
                 data is being transferred to or from the floppy 
               
               
                   
                   
                 disk. 
               
               
                 10 
                 LEDIN 
                 LED signal from IDE drive 
                 I 
               
               
                 11 
                 DENSEL 
               
               
                 12 
                 INDEX- 
                 Floppy disk index pulse, input from drive 
                 I 
               
               
                 13 
                 MTR0- 
                 Floppy disk active lower open drain output 
               
               
                   
                   
                 selects motor driver 0. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s Digital 
               
               
                   
                   
                 Output Register (DOR). 
               
               
                 14 
                 MTR2- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 2. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s Digital 
               
               
                   
                   
                 Output Register (DOR). 
               
               
                 15 
                 DRV1 - 
                 Floppy disk active lower open drain output that 
               
               
                   
                   
                 selects floppy drive 1 
               
               
                 16 
                 DRV3- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 3 
               
               
                 17 
                 GND 
               
               
                 18 
                 DRV0- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 0 
               
               
                 19 
                 DRV2- 
                 Floppy disk active low open drain output that 
               
               
                   
                   
                 selects floppy drive 2 
               
               
                 20 
                 MTR1- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 1. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s Digital 
               
               
                   
                   
                 Output Register (DOR). 
               
               
                 21 
                 MTR3- 
                 Floppy disk active low open drain output 
               
               
                   
                   
                 selects motor driver 3. The motor enable bits 
               
               
                   
                   
                 are software controlled via the floppy&#39;s Digital 
               
               
                   
                   
                 Output Register (DOR). 
               
               
                 22 
                 DIR 
                 Floppy disk open drain output that controls 
               
               
                   
                   
                 floppy read/write head movement direction. 
               
               
                   
                   
                 Low = set pin. 
               
               
                 23 
                 STEP- 
                 Floppy disk active low output provides the step 
               
               
                   
                   
                 pulse to move the floppy read/write head 
               
               
                 24 
                 WDATA- 
                 Floppy disk active lower signal writes 
               
               
                   
                   
                 precompensated serial data to the selected 
               
               
                   
                   
                 floppy drive. This is a high open current drain 
               
               
                   
                   
                 output and is gated internally with WGATE-. 
               
               
                 25 
                 WGATE- 
                 Floppy disk active low open drain signal that 
               
               
                   
                   
                 enables the head to write onto the floppy disk. 
               
               
                 26 
                 TRK0- 
                 Floppy disk active lower Schmitt input 
                 IS 
               
               
                   
                   
                 indicates that the head is on track 0 of the 
               
               
                   
                   
                 selected drive 
               
               
                 27 
                 WRPRT- 
                 Floppy disk active low Schmitt input indicating 
                 IS 
               
               
                   
                   
                 that the disk is write protected. Any WDATA- 
               
               
                   
                   
                 command is ignored. 
               
               
                 28 
                 RDATA- 
                 Floppy disk active lower Schmitt input that 
                 IS 
               
               
                   
                   
                 reads raw data from the floppy disk. 
               
               
                 29 
                 HDSEL 
                 Floppy disk open drain output that selects the 
               
               
                   
                   
                 head on the selected drive. Low = side 0. 
               
               
                 30 
                 DSKCHG 
                 Floppy disk input signal indicating that the 
                 I 
               
               
                   
                   
                 floppy door has been opened. 
               
               
                 31 
                 5VBB 
               
               
                 32 
                 GND 
               
               
                 33 
                 PFI 
                 Powerfail 
               
               
                 34 
                 PFO 
                 Powerfail 
               
               
                 35 
                 MR- 
                 Powerfail 
               
               
                 36 
                 RTCIRQ- 
                 Alarm output from the onboard real time clock 
               
               
                 37 
                 WDO 
                 Watchdog timer 
               
               
                 38 
                 IOCHCK 
                 ISA System Address 00 
                 O24 
               
               
                 39 
                 SD07 
                 ISA 14.318 MHz clock. This clock is 
               
               
                   
                   
                 asynchronous to all other system clocks 
               
               
                 40 
                 RESET- 
                 ISA System Address 01 
                 O24 
               
               
                   
                 DRV 
               
               
                 41 
                 SD06 
                 ISA System Address 02 
                 O24 
               
               
                 42 
                 SD05 
                 ISA Buffered Address Latch Enable 
               
               
                 43 
                 IRQ9 
                 ISA System Address 03 
                 O24 
               
               
                 44 
                 SD04 
                 ISA System Data 15 
               
               
                 45 
                 SD03 
                 ISA DMA Terminal Court 
               
               
                 46 
                 DRQ2 
                 ISA System Address 04 
                 O24 
               
               
                 47 
                 DRQ2- 
                 ISA 
               
               
                   
                 OUT- 
               
               
                 48 
                 SD02 
                 ISA System Data 14 
               
               
                 49 
                 SD01- 
                 ISA DMA 2 Acknowledge strobe 
               
               
                 50 
                 0WS 
                 ISA System Address 05 
                 O24 
               
               
                 51 
                 SD00 
                 ISA System Data 13 
               
               
                 52 
                 IOCH- 
                 ISA Interrupt Request 3 
                 I 
               
               
                   
                 RDY 
               
               
                 53 
                 SBHE- 
                 ISA System Address 06 
                 O24 
               
               
                 54 
                 MEMC- 
                 ISA DMA 7 Request 
                 I 
               
               
                   
                 S16 
               
               
                 55 
                 AEN 
                 ISA System Data 12 
               
               
                 56 
                 SMEMW- 
                 ISA Interrupt Request 4 
                 I 
               
               
                 57 
                 LA23 
                 ISA System Address 07 
                 O24 
               
               
                 58 
                 IOCS16- 
                 ISA DMA 7 Acknowledge strobe 
               
               
                 59 
                 SA19 
                 ISA System Data 11 
               
               
                 60 
                 SMEMR- 
                 ISA Interrupt Request 5 
                 I 
               
               
                 61 
                 LA22 
                 ISA System Address 08 
                 O24 
               
               
                 62 
                 IRQ10 
                 ISA DMA 6 Request 
                 I 
               
               
                 63 
                 SA18 
                 ISA System Data 10 
               
               
                 64 
                 IOW- 
                 Floppy disk interrupt request. Normally 
               
               
                   
                   
                 connects to IRQ6 (pin 65) 
               
               
                 65 
                 LA21 
                 ISA Interrupt Request 6 
                 I 
               
               
                 66 
                 IRQ11 
                 ISA System Address 09 
                 O24 
               
               
                 67 
                 GND 
               
               
                 68 
                 SA17 
                 ISA DMA 6 Acknowledge strobe 
               
               
                 69 
                 IOR- 
                 ISA System Data 09 
               
               
                 70 
                 LA20 
                 Parallel port interrupt request. Normally 
               
               
                   
                   
                 connects to IRQ7 (pin 71). 
               
               
                 71 
                 IRQ12 
                 ISA Interrupt Request 7 
                 I 
               
               
                 72 
                 SA16 
                 ISA System Address 10 
                 O24 
               
               
                 73 
                 DACK3- 
                 ISA DMA 5 Request 
                 I 
               
               
                 74 
                 LA19 
                 ISA System Data 08 
               
               
                 75 
                 IRQ15 
                 ISA System Clock 
               
               
                 76 
                 SA15 
                 ISA System Address 11 
                 O24 
               
               
                 77 
                 DRQ3 
                 ISA DMA 5 Acknowledge strobe 
               
               
                 78 
                 LA18 
                 ISA active low memory write strobe 
               
               
                 79 
                 IRQ14 
                 ISA active low signal indicating current bus 
               
               
                   
                   
                 cycle is a memory refresh 
               
               
                 80 
                 SA14 
                 ISA System Address 12 
                 O24 
               
               
                 81 
                 DACK1- 
                 ISA DMA 0 Request 
                 I 
               
               
                 82 
                 LA17 
                 ISA active low memory read strobe 
               
               
                 83 
                 DACK0- 
                 ISA DMA 1 Request 
                 I 
               
               
                 84 
                 SA13 
                 ISA System Address 13 
                 O24 
               
               
                 85 
                 VCC 
               
               
                 86 
                 DRQ1 
                 ISA DSMA 0 Acknowledge strobe 
               
               
                 87 
                 MEMR- 
                 ISA Latched Address 17 
                 O24 
               
               
                 88 
                 DRQ0 
                 ISA DMA 1 Acknowledge strobe 
               
               
                 89 
                 SA12 
                 ISA System Address 14 
                 O24 
               
               
                 90 
                 RE- 
                 ISA Interrupt Request 14, normally used for 
                 I 
               
               
                   
                 FRESH- 
                 IDE interface 
               
               
                 91 
                 MEMW- 
                 ISA Latched address 18 
                 O24 
               
               
                 92 
                 DACK5- 
                 ISA DMA 3 Request strobe 
               
               
                 93 
                 SA11 
                 ISA System Address 15 
                 O24 
               
               
                 94 
                 SYSCLK 
                 ISA Interrupt Request 15 
                 I 
               
               
                 95 
                 SD08 
                 ISA Latched Address 19 
                 O24 
               
               
                 96 
                 DRQ5 
                 ISA DMA 3 Acknowledge strobe 
               
               
                 97 
                 SA10 
                 ISA System Address 16 
                 O24 
               
               
                 98 
                 IRQ7 
                 ISA Interrupt Request 12 
                 I 
               
               
                 99 
                 IRQ7OUT 
                 ISA Latched Address 20 
                 O24 
               
               
                 100 
                 SD09 
                 ISA I/O Read strobe 
               
               
                 101 
                 DACK6- 
                 ISA System Address 17 
                 O24 
               
               
                 102 
                 GND 
               
               
                 103 
                 SA09 
                 ISA Interrupt Request 11 
                 I 
               
               
                 104 
                 IRQ6 
                 ISA Latched Address 21 
                 O24 
               
               
                 105 
                 IRQ6OUT 
                 ISA I/O Write strobe 
               
               
                 106 
                 SD10 
                 ISA System Address 18 
                 O24 
               
               
                 107 
                 DRQ6 
                 ISA Interrupt Request 10 
                 I 
               
               
                 108 
                 SA08 
                 ISA Latched Address 22 
                 O24 
               
               
                 109 
                 IRQ5 
                 ISA System Memory Read strobe 
               
               
                 110 
                 SD11 
                 ISA System Address 19 
                 O24 
               
               
                 111 
                 DACK7- 
                 ISA 16-bit I/O Chip Select request. Indicates 
                 I 
               
               
                   
                   
                 that the current I/O transaction is 16-bits. 
               
               
                 112 
                 SA07 
                 ISA Latched Address 23 
                 O24 
               
               
                 113 
                 IRQ4 
                 ISA System Memory Write strobe 
               
               
                 114 
                 SD12 
                 ISA Address Enable 
               
               
                 115 
                 DRQ7 
                 ISA 16-bit Memory Chip Select request. 
                 I 
               
               
                   
                   
                 Indicates that the current memory transaction is 
               
               
                   
                   
                 16-bits. 
               
               
                 116 
                 SA06 
                 ISA System Byte High Enable 
               
               
                 117 
                 IRQ3 
                 ISA I/O Channel Ready. A low adds wait states 
                 I 
               
               
                   
                   
                 to the current ISA bus cycle 
               
               
                 118 
                 SD13 
                 ISA System Data 00 
               
               
                 119 
                 SA05 
                 ISA active low causing current memory cycle 
                 I 
               
               
                   
                   
                 to be completed without additional wait states. 
               
               
                 120 
                 DACK2- 
                 ISA System Data 01 
               
               
                 121 
                 SD14 
                 ISA System Data 02 
               
               
                 122 
                 MASTER- 
                 Floppy DMA 2 Request. Normally connected 
               
               
                   
                   
                 to DRQ2 (pin 123) 
               
               
                 123 
                 SA04 
                 ISA DMA 2 Request strobe 
                 I 
               
               
                 124 
                 TC 
                 ISA System Data 03 
               
               
                 125 
                 SD15 
                 ISA System Data 04 
               
               
                 126 
                 SA03 
                 ISA Interrupt Request 09 
                 I 
               
               
                 127 
                 BALE 
                 ISA System Data 05 
               
               
                 128 
                 SA02 
                 ISA System Data 06 
               
               
                 129 
                 SA01 
                 ISA active high system reset signal 
               
               
                 130 
                 OSC 
                 ISA System Data 07 
               
               
                 131 
                 SA00 
                 ISA gated non-maskable interrupt input 
                 I 
               
               
                 132 
                 HISPEED 
                 Input to select CPU speed. High-high speed. 
                 I 
               
               
                 133 
                 SPKR 
                 Speaker output 
               
               
                 134 
                 KDATA 
                 Keyboard data 
               
               
                 135 
                 KCLOCK 
                 Keyboard clock 
               
               
                 136 
                 PWRDN- 
               
               
                 137 
                 GND 
               
               
                 138 
                 COLOR 
                 Video Color/Mono jumper 
               
               
                 139 
                 KBLOCK 
                 Keyboard lock. Low blocks keyboard input 
               
               
                 140 
                 SLCT 
                 Parallel Port 
               
               
                 141 
                 PE 
                 Parallel Port 
               
               
                 142 
                 BUSY 
                 Parallel Port 
               
               
                 143 
                 ACK- 
                 Parallel Port 
               
               
                 144 
                 PD7 
                 Parallel Port Data 7 
               
               
                 145 
                 PD6 
                 Parallel Port Data 6 
               
               
                 146 
                 PD5 
                 Parallel Port Data 5 
               
               
                 147 
                 PD4 
                 Parallel Port Data 4 
               
               
                 148 
                 PD3 
                 Parallel Port Data 3 
               
               
                 149 
                 SLCTIN- 
                 Parallel Port 
               
               
                 150 
                 PD2 
                 Parallel Port Data 2 
               
               
                 151 
                 INIT- 
                 Parallel Port 
               
               
                 152 
                 PD1 
                 Parallel Port Data 1 
               
               
                 153 
                 ERR- 
                 Parallel Port 
               
               
                 154 
                 GND 
               
               
                 155 
                 PD0 
                 Parallel Port Data 0 
               
               
                 156 
                 AUTOFD 
                 Parallel Port 
               
               
                 157 
                 STRB- 
                 Parallel Port 
               
               
                 158 
                 DCD2 
                 Serial Port 2 Data Carrier Detect 
               
               
                 159 
                 DSR2 
                 Serial Port 2 Data Set Ready 
               
               
                 160 
                 RXD2 
                 Serial Port 2 Receive Data 
               
               
                 161 
                 RTS2 
                 Serial Port 2 Request To Send 
               
               
                 162 
                 TXD2 
                 Serial Port 2 Transmit Data 
               
               
                 163 
                 CTS2 
                 Serial Port 2 Clear To Send 
               
               
                 164 
                 DTR2 
                 Serial Port 2 Data Terminal Ready 
               
               
                 165 
                 R12 
                 Serial Port 2 Ring Indicator 
               
               
                 166 
                 DCD1 
                 Serial Port 1 Data Carrier Detect 
               
               
                 167 
                 DSR1 
                 Serial Port 1 Data Set Ready 
               
               
                 168 
                 RXD1 
                 Serial Port 1 Receive Data 
               
               
                 169 
                 RTS1 
                 Serial Port 1 Request to Send 
               
               
                 170 
                 TXD1 
                 Serial Port 1 Transmit Data 
               
               
                 171 
                 CTS1 
                 Serial Port 1 Clear to Send 
               
               
                 172 
                 DTR1 
                 Serial Port 1 Data Terminal Ready 
               
               
                 173 
                 RI1 
                 Serial Port 1 Ring Indicator 
               
               
                 174 
                 GAMECS 
               
               
                 175 
                 RAS3- 
                 DRAM Row Address Strobe 3 
               
               
                 176 
                 RAS2- 
                 DRAM Row Address Strobe 2 
               
               
                 177 
                 RAS1- 
                 DRAM Row Address Strobe 1 
               
               
                 178 
                 RAS0- 
                 DRAM Row Address Strobe 0 
               
               
                 179 
                 DP1 
                 DRAM parity bit for high byte memory 
               
               
                 180 
                 DP0 
                 DRAM parity bit for low byte memory 
               
               
                 181 
                 D15 
                 DRAM Data Bit 15 
               
               
                 182 
                 D07 
                 DRAM Data Bit 7 
               
               
                 183 
                 D14 
                 DRAM Data Bit 14 
               
               
                 184 
                 D06 
                 DRAM Data Bit 6 
               
               
                 185 
                 DRWE- 
                 DRAM memory write strobe 
               
               
                 186 
                 D13 
                 DRAM Data Bit 13 
               
               
                 187 
                 GND 
               
               
                 188 
                 D05 
                 DRAM Data Bit 5 
               
               
                 189 
                 MA10 
                 DRAM multiplexed memory address 10 
               
               
                 190 
                 MA09 
                 DRAM multiplexed memory address 9 
               
               
                 191 
                 MA08 
                 DRAM multiplexed memory address 8 
               
               
                 192 
                 D12 
                 DRAM Data Bit 12 
               
               
                 193 
                 D04 
                 DRAM Data Bit 4 
               
               
                 194 
                 MA07 
                 DRAM multiplexed memory address 7 
               
               
                 195 
                 MA06 
                 DRAM multiplexed memory address 6 
               
               
                 196 
                 D11 
                 DRAM Data Bit 11 
               
               
                 197 
                 D03 
                 DRAM Data Bit 3 
               
               
                 198 
                 MA05 
                 DRAM multiplexed memory address 5 
               
               
                 199 
                 MA04 
                 DRAM multiplexed memory address 4 
               
               
                 200 
                 D10 
                 DRAM Data Bit 10 
               
               
                 201 
                 D01 
                 DRAM Data Bit 2 
               
               
                 202 
                 MA03 
                 DRAM multiplexed memory address 3 
               
               
                 203 
                 MA02 
                 DRAM multiplexed memory address 2 
               
               
                 204 
                 D09 
                 DRAM Data Bit 9 
               
               
                 205 
                 VCC 
               
               
                 206 
                 D01 
                 DRAM Data Bit 1 
               
               
                 207 
                 MA01 
                 DRAM multiplexed memory address 1 
               
               
                 208 
                 MA00 
                 DRAM multiplexed memory address 0 
               
               
                 209 
                 D08 
                 DRAM Data Bit 8 
               
               
                 210 
                 D00 
                 DRAM Data Bit 0 
               
               
                 211 
                 CASH3- 
                 DRAM Column Address Strobe, High byte 3 
               
               
                 212 
                 CASL3- 
                 DRAM Column Address Strobe, Low byte 3 
               
               
                 213 
                 CASH2- 
                 DRAM Column Address Strobe, High byte 2 
               
               
                 214 
                 CASL2- 
                 DRAM Column Address Strobe, Low byte 2 
               
               
                 215 
                 CASH1- 
                 DRAM Column Address Strobe, High byte 1 
               
               
                 216 
                 CASL1- 
                 DRAM Column Address Strobe, Low byte 1 
               
               
                 217 
                 CASH0- 
                 DRAM Column Address Strobe, High byte 0 
               
               
                 218 
                 CASL0- 
                 DRAM Column Address Strobe, Low byte 0 
               
               
                 219 
                 BDIS 
               
               
                 220 
                 XRO- 
               
               
                   
                 MCS- 
               
               
                 221 
                 LEDOUT- 
               
               
                 222 
                 GND 
               
               
                 223 
                 HDRE- 
                 IDE 
               
               
                   
                 SET- 
               
               
                 224 
                 IDED07 
                 IDE Data Bit 7 
               
               
                 225 
                 HDD08 
                 IDE Data Bit 8 
               
               
                 226 
                 HDD06 
                 IDE Data Bit 6 
               
               
                 227 
                 HDD09 
                 IDE Data Bit 9 
               
               
                 228 
                 HDD05 
                 IDE Data Bit 5 
               
               
                 229 
                 HDD10 
                 IDE Data Bit 10 
               
               
                 230 
                 HDD04 
                 IDE Data Bit 4 
               
               
                 231 
                 HDD11 
                 IDE Data Bit 11 
               
               
                 232 
                 HDD03 
                 IDE Data Bit 3 
               
               
                 233 
                 HDD12 
                 IDE Data Bit 12 
               
               
                 234 
                 HDD02 
                 IDE Data Bit 2 
               
               
                 235 
                 HDD13 
                 IDE Data Bit 13 
               
               
                 236 
                 HDD01 
                 IDE Data Bit 1 
               
               
                 237 
                 HDD14 
                 IDE Data Bit 14 
               
               
                 238 
                 HDD00 
                 IDE Data Bit 0 
               
               
                 239 
                 HDD15 
                 IDE Data Bit 15 
               
               
                 240 
                 HDIOW- 
                 IDE buffered I/O Write strobe 
               
               
                   
               
            
           
         
       
     
     A second embodiment of the pin configuration for the expansion bus  24  is given in the table below with corresponding pin numbers for expansion bus connectors A, B, C, D. As mentioned before, bus  24  comprises 94 pins that includes VCC and two GND pins. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                   
                   
               
               
                   
                   
                 Signal 
                   
                   
                   
                   
               
               
                   
                 Pin 
                 Name 
                 Function 
                 In/Out 
                 Current 
                 Load* 
               
               
                   
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                 38 
                 A31 
                 IOCHCK 
                 Address bit 0 
                 I/O 
                 12 mA 
                 PU 
               
               
                 39 
                 B30 
                 SD07 
                 14.318 MHz 
                 Out 
                  6 mA 
                 33 SER 
               
               
                   
                   
                   
                 clock 
               
               
                 40 
                 A30 
                 RESET- 
                 Address bit 1 
                 I/O 
                 12 mA 
                 PU 
               
               
                   
                   
                 DRV 
               
               
                 41 
                 A29 
                 SD06 
                 Address bit 2 
                 I/O 
                 12 mA 
                 PU 
               
               
                 42 
                 B28 
                 SD05 
                 Address latch 
                 Out 
                 12 mA 
               
               
                   
                   
                   
                 enable 
               
               
                 43 
                 A28 
                 IRQ9 
                 Address bit 3 
                 I/O 
                 12 mA 
                 PU 
               
               
                 44 
                 C18 
                 SD04 
                 System Data 
                 I/O 
                 12 mA 
                 PU 
               
               
                   
                   
                   
                 bit 15 
               
               
                 45 
                 B27 
                 SD03 
                 DMA Terminal 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Count 
               
               
                 46 
                 A27 
                 DRQ2 
                 Address bit 4 
                 I/O 
                 12 mA 
                 PU 
               
               
                 47 
                 D17 
                 DRQ2- 
                 Bus master 
                 In 
                 N/A 
                 330 PU 
               
               
                   
                   
                 OUT- 
                 assert 
               
               
                 48 
                 C17 
                 SD02 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 bit 14 
               
               
                 49 
                 B26 
                 SD01- 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 2 
               
               
                 50 
                 A26 
                 0WS 
                 Address bit 5 
                 I/O 
                 12 mA 
                 PU 
               
               
                 51 
                 C16 
                 SD00 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 bit 13 
               
               
                 52 
                 B25 
                 IOCH- 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                 RDY 
                 Request 3 
               
               
                 53 
                 A25 
                 SBHE- 
                 Address bit 6 
                 I/O 
                 12 mA 
                 PU 
               
               
                 54 
                 D15 
                 MEMC- 
                 DMA Request 7 
                 In 
                 N/A 
                 PD 
               
               
                   
                   
                 S16 
               
               
                 55 
                 C15 
                 AEN 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                 bit 12 
               
               
                 56 
                 B24 
                 SMEMW- 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 4 
               
               
                 57 
                 A24 
                 LA23 
                 Address bit 7 
                 I/O 
                 12 mA 
                 PU 
               
               
                 58 
                 D14 
                 IOCS16 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 7 
               
               
                 59 
                 C14 
                 SA19 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 bit 11 
               
               
                 60 
                 B23 
                 SMEMR- 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 5 
               
               
                 61 
                 A23 
                 LA22 
                 Address bit 8 
                 I/O 
                 12 mA 
                 PU 
               
               
                 62 
                 D13 
                 IRQ10 
                 DMA Request 6 
                 In 
                 N/A 
                 PD 
               
               
                 63 
                 C13 
                 SA18 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 bit 10 
               
               
                 64 
                   
                 IOW- 
                 Floppy Disk 
               
               
                   
                   
                   
                 Interrupt 
               
               
                   
                   
                   
                 Request 
               
               
                 65 
                 B22 
                 LA21 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 6 
               
               
                 66 
                 A22 
                 IRQ11 
                 Address bit 9 
                 I/O 
                 12 mA 
                 PU 
               
               
                 67 
                   
                 GND 
               
               
                 68 
                 D12 
                 SA17 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 6 
               
               
                 69 
                 C12 
                 IOR- 
                 System Data bit 9 
                 I/O 
                 24 mA 
                 PU 
               
               
                 70 
                   
                 LA20 
                 Parallel Port 
               
               
                   
                   
                   
                 Interrupt Request 
               
               
                 71 
                 B21 
                 IRQ12 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 7 
               
               
                 72 
                 A21 
                 SA16 
                 Address bit 10 
                 I/O 
                 12 mA 
                 PU 
               
               
                 73 
                 D11 
                 DACK3- 
                 DMA Requests 5 
                 In 
                 N/A 
                 PD 
               
               
                 74 
                 C11 
                 LA19 
                 System Data bit 8 
                 I/O 
                 24 mA 
                 PU 
               
               
                 75 
                 B20 
                 IRQ15 
                 System clock (8 
                 Out 
                 12 mA 
               
               
                   
                   
                   
                 MHz) 
               
               
                 76 
                 A20 
                 SA15 
                 Address bit 11 
                 I/O 
                 12 mA 
                 PU 
               
               
                 77 
                 D10 
                 DRQ3 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 5 
               
               
                 78 
                 C10 
                 LA18 
                 Memory Write 
                 I/O 
                  6 mA 
                 PU. 33 
               
               
                   
                   
                   
                   
                   
                   
                 SER 
               
               
                 79 
                 B19 
                 IRQ14 
                 Memory Refresh 
                 I/O 
                  6 mA 
                 470 
               
               
                   
                   
                   
                   
                   
                   
                 PU. 33 
               
               
                   
                   
                   
                   
                   
                   
                 SER 
               
               
                 80 
                 A19 
                 SA14 
                 Address bit 12 
                 I/O 
                 12 mA 
                 PU 
               
               
                 81 
                 D9 
                 DACK1- 
                 DMA Request 0 
                 In 
                 N/A 
                 PD 
               
               
                 82 
                 C9 
                 LA17 
                 Memory Read 
                 I/O 
                  6 mA 
                 PU. 33 
               
               
                   
                   
                   
                   
                   
                   
                 SER 
               
               
                 83 
                 B18 
                 DACK0- 
                 DMA Request 1 
                 In 
                 N/A 
                 PD 
               
               
                 84 
                 A18 
                 SA13 
                 Address bit 13 
                 I/O 
                 12 mA 
                 PU 
               
               
                 85 
                   
                 VCC 
               
               
                 86 
                 D8 
                 DRQ1- 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 0 
               
               
                 87 
                 C8 
                 MEMR- 
                 Address bit 17 
                 I/O 
                 24 mA 
               
               
                 88 
                 B17 
                 DRQ0 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 1 
               
               
                 89 
                 A17 
                 SA12 
                 Address bit 14 
                 I/O 
                 12 mA 
                 PU 
               
               
                 90 
                 D7 
                 RE- 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                 FRESH- 
                 Request 14 
               
               
                 91 
                 C7 
                 MEMW- 
                 Address bit 18 
                 I/O 
                 24 mA 
               
               
                 92 
                 B16 
                 DACK5- 
                 DMA Request 3 
                 In 
                 N/A 
                 PD 
               
               
                 93 
                 A16 
                 SA11 
                 Address bit 15 
                 I/O 
                 12 mA 
                 PU 
               
               
                 94 
                 D6 
                 SYSCLK 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 15 
               
               
                 95 
                 C6 
                 SD08 
                 Address bit 19 
                 I/O 
                 24 mA 
               
               
                 96 
                 B15 
                 DRQ5 
                 DMA 
                 Out 
                  4 mA 
               
               
                   
                   
                   
                 Acknowledge 3 
               
               
                 97 
                 A15 
                 SA10 
                 Address bit 16 
                 I/O 
                 12 mA 
                 PU 
               
               
                 98 
                 D5 
                 IRQ7 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 12 
               
               
                 99 
                 C5 
                 IRQ7OUT 
                 Address bit 20 
                 I/O 
                 24 mA 
               
               
                 100 
                 B14 
                 SD09 
                 I/O Read 
                 I/O 
                  6 mA 
                 PU 
               
               
                 101 
                 A14 
                 DACK6- 
                 Address bit 17 
                 I/O 
                 12 mA 
                 PU 
               
               
                 102 
                   
                 GND 
               
               
                 103 
                 D4 
                 SA09 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 11 
               
               
                 104 
                 C4 
                 IRQ6 
                 Address bit 21 
                 I/O 
                 24 mA 
               
               
                 105 
                 B13 
                 IRQ6OUT 
                 I/O Write 
                 I/O 
                  6 mA 
                 PU 
               
               
                 106 
                 A13 
                 SD10 
                 Address bit 18 
                 I/O 
                 12 mA 
                 PU 
               
               
                 107 
                 D3 
                 DRQ6 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 Request 10 
               
               
                 108 
                 C3 
                 SA08 
                 Address bit 22 
                 I/O 
                 24 mA 
               
               
                 109 
                 B12 
                 IRQ5 
                 Mem Read (lower 
                 I/O 
                  6 mA 
                 33 SER 
               
               
                   
                   
                   
                 1 MB) 
               
               
                 110 
                 A12 
                 SD11 
                 Address bit 19 
                 I/O 
                 12 mA 
                 PU 
               
               
                 111 
                 D2 
                 DACK7- 
                 16-bit I/O access 
                 In 
                 N/A 
                 330 PU 
               
               
                 112 
                 C2 
                 SA07 
                 Address bit 23 
                 I/O 
                 24 mA 
               
               
                 113 
                 B11 
                 IRQ4 
                 Mem Write 
                 I/O 
                  6 mA 
                 33 SER 
               
               
                   
                   
                   
                 (lower 1 MB) 
               
               
                 114 
                 A11 
                 SD12 
                 Address Enable 
                 I/O 
                 12 mA 
                 PU 
               
               
                 115 
                 D1 
                 DRQ7 
                 16-bit mem 
                 In 
                 N/A 
                 330 PU 
               
               
                   
                   
                   
                 access 
               
               
                 116 
                 C1 
                 SA06 
                 Bus High Enable 
                 I/O 
                 12 mA 
                 PU 
               
               
                 117 
                 A10 
                 IRQ3 
                 Processor 
                 In 
                 N/A 
                 1K PU 
               
               
                   
                   
                   
                 Ready Ctrl 
               
               
                 118 
                 A9 
                 SD13 
                 System Data bit 0 
                 I/O 
                 24 mA 
                 PU 
               
               
                 119 
                 B8 
                 SA05 
                 Zero wait state 
                 In 
                 N/A 
                 330 PU 
               
               
                 120 
                 A8 
                 DACK2- 
                 System Data bit 1 
                 I/O 
                 24 mA 
                 PU 
               
               
                 121 
                 A7 
                 SD14 
                 System Data bit 2 
                 I/O 
                 24 mA 
                 PU 
               
               
                 122 
                   
                 MASTER- 
                 Floppy DMA 2 
               
               
                   
                   
                   
                 Request 
               
               
                 123 
                 B6 
                 SA04 
                 DMA request 2 
                 In 
                 N/A 
                 PD 
               
               
                 124 
                 A6 
                 TC 
                 System Data bit 3 
                 I/O 
                 24 mA 
                 PU 
               
               
                 125 
                 A5 
                 SD15 
                 System Data bit 4 
                 I/O 
                 24 mA 
                 PU 
               
               
                 126 
                 B4 
                 SA03 
                 Interrupt 
                 In 
                 N/A 
                 PU 
               
               
                   
                   
                   
                 request 9 
               
               
                 127 
                 A4 
                 BALE 
                 System Data 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 bit 5 
               
               
                 128 
                 A4 
                 SA02 
                 System Data bit 6 
                 I/O 
                 24 mA 
                 PU 
               
               
                 129 
                 B2 
                 SA01 
                 System reset 
                 Out 
                 24 mA 
               
               
                   
                   
                   
                 signal 
               
               
                 130 
                 A2 
                 OSC 
                 System Data bit 
                 I/O 
                 24 mA 
                 PU 
               
               
                   
                   
                   
                 7- 
               
               
                 131 
                 A1 
                 SA00 
                 Sub NMI input 
                 In 
                 N/A 
                 4.7K 
               
               
                   
                   
                   
                   
                   
                   
                 PU 
               
               
                   
               
            
           
         
       
     
     The exact pin configuration as illustrated for the expansion bus on FIG. 5 is a critical feature of the invention. Since it forms a single row of pins on the module  10 , the pins can be easily connected directly to the expansion bus connectors without having to resort to multiple layer boards to route the PC board tracks from the module  10  to the expansion bus connectors A, B, C, D. Furthermore, as mentioned above, the present invention includes both microprocessor modules as illustrated in FIG. 3, as well as peripheral controller modules such as display controller modules, Ethernet control modules, and PCMCIA compatible modules for extended memory (RAM, ROM, EEPROM, flash memory, etc.), as well as for modem, fax, and network interfaces, and also for wireless communication devices. By providing an identical pin configuration for the ISA buses, the various modules can easily be connected to one another. 
     A further feature of the invention is illustrated in FIG.  6 . FIG. 6 illustrates a card  54  having a mounting site  56  for a module having a pin configuration as described above with reference to FIG.  4 . The card  54  provides an integrated way for system development in standard ISA passive backplane systems. The card includes an AT-bus and a PC/ 104  bus, and occupies a single slot in an AT-class (16-bit) passive backplane. This allows development tQ be performed using a terminal on a serial port as a console. A standard VGA or SVGA display controller can be plugged into another slot on the backplane if desired. Instead, a PC/ 104  display controller can be installed directly on the PC/ 104  header  58  on the card  54 . Since the module  10  is fully compatible with PC/AT ISA, a wide selection of hardware peripherals may be integrated. The ISA-compatible bus allows an OEM to easily interface his proprietary hardware design with the module  10 . Futhermore, the standard BIOS and embedded DOS allows application software to be developed using standard desk top PCs and standard development tools for implementation on the system using one or more modules of the present invention. It will be appreciated that, depending on the nature of the module, the size of the module and the number of pins may vary, however it is an important feature of this invention that the pins for the ISA bus retain their configuration in each module to allow the modules to be readily connected to one another as illustrated in FIG. 7 in which different modules  60 ,  62 ,  64  of the invention are connected to each other by means of bus lines  66 ,  68  extending between the ISA compatible bus pins indicated by reference numerals  70 ,  72 ,  74 , respectively.