Patent Publication Number: US-6665795-B1

Title: Resetting a programmable processor

Description:
BACKGROUND 
     This invention relates to resetting a programmable processor. 
     A programmable processor, such as a microprocessor for a computer or a digital signal processing system, typically supports one or more mechanisms for initializing the processor into a known state. For example, conventional processors often include an interface pin to support a “hard reset” in response to a reset button. In addition, conventional processors support a “soft reset” in which the reset process is initiated by software running on the processor. 
    
    
     DESCRIPTION OF DRAWINGS 
     FIG. 1 is a block diagram illustrating an example of a pipelined programmable processor according to the invention. 
     FIG. 2 is a schematic illustrating an example execution pipeline according to the invention. 
     FIG. 3 is a timing diagram further illustrating the reset process. 
     FIG. 4 is a schematic diagram illustrating example circuits for resetting the processor according to the invention. 
     FIG. 5 is a flowchart illustrating an example process for resetting the pipelined processor. 
    
    
     DESCRIPTION 
     FIG. 1 is a block diagram illustrating a programmable processor  2  having an execution pipeline  4  and a control unit  6 . Control unit  6  controls the flow of instructions and data through pipeline  4  for every clock cycle. For example, during the processing of an instruction, control unit  6  directs the various components of the pipeline to decode the instruction and correctly perform the corresponding operation including, for example, writing the results back to memory. 
     Instructions are loaded into a first stage of pipeline  4  and processed through the subsequent stages. Each stage processes concurrently with the other stages. Data passes between the stages in pipeline  4  in accordance with a system clock. The results of the instructions emerge at the end of the pipeline  4  in rapid succession. 
     Reset unit  8  resets processor  2  in response to three types of reset requests: (1) a hard reset (hard_reset), typically caused by a user cycling power or pressing a reset button, (2) a soft reset (soft_reset), typically initiated by software applications executing on processor  2 , and (3) an emulator reset, typically issued by an in-circuit hardware emulator (ICE). Reset unit  8  detects a reset condition and informs event handler  14  of the reset request. Event handler  14  includes logic for receiving and handling all system events that occur within processor  2  and, as explained in detail below, handles a reset request as a high-priority event. 
     FIG. 2 illustrates an example pipeline  4  according to the invention. Pipeline  4 , for example, has five stages: instruction fetch (IF), instruction decode (DEC), address calculation (AC), execute (EX) and write back (WB). Instructions are fetched from memory, or from an instruction cache, during the first stage (IF) by fetch unit  21  and decoded during the second stage (DEC). At the next clock cycle, the results are passed to the third stage (AC), where data address generators  23  calculate any memory addresses that are necessary to perform the operation. 
     During the execution stage (EX), execution unit  25 , performs the specified operation such as, for example, adding or multiplying two numbers. Execution unit  25  may contain specialized hardware for performing the operations including, for example, one or more arithmetic logic units (ALU&#39;s), floating-point units (FPU) and barrel shifters. A variety of data may be applied to execution unit  25  such as the addresses generated by data address generators  23 , data retrieved from memory or data retrieved from data registers  24 . During the final stage (WB), the results are written back to data memory or to data registers  24 . 
     The stages of pipeline  4  include storage circuits  27 , such as flip-flops, for storing “valid bits” indicating whether the instruction held by the corresponding stage is a valid instruction and should be processed. Initially, fetch unit  21  sets an instruction&#39;s corresponding valid bit when the instruction is successfully fetched and decoded. The valid bit propagates through the storage circuits  27  of pipeline  4  as the instruction is processed. 
     In order to effectively and quickly reset the processor  2 , and to reduce the often excessive power consumption during reset, reset unit  8  clears the valid bits when a reset event is accepted by reset handler. More specifically, reset_unit  8  issues a reset (SE_RESET) to pipeline  4 , which clears storage circuit  27  of the IF stage, thereby invalidating the instruction held within the IF stage. During subsequent clock cycles, the storage circuits  27  of the remaining stages are cleared until SE_RESET is deasserted, effectively invalidating the contents of pipeline  4 . 
     FIG. 3 is a timing diagram further illustrating the reset process in response to a reset condition including, for example, a hard reset, a soft reset or a reset from an emulator. Notably, reset unit  8  is responsive to the length of time the RESET_REQ signal remains active and, in particular, is adapted to hold SE_RESET active after the reset signal has been removed in order to ensure pipeline  4  is fully initialized. More specifically, reset unit  8  assets SE_RESET for at least N clock cycles after the reset request is deasserted, where pipeline  4  is N stages deep. 
     As discussed in detail below, reset unit  8  and event handler  15  support a synchronous reset in that a reset request is treated as a high-priority event that may reset processor  2 , depending on the priority of any other pending event. FIG. 4 is a schematic diagram illustrating an example embodiment for reset unit  8  and event handler  14 . As explained in detail below, reset unit  8  interacts with event handler  14  to ensure that a single cycle pulse on any of the reset inputs is sufficient to fully reset and initialize pipeline  4 . Reset unit  8  has three inputs for receiving three types of reset conditions: HARD_RESET, SOFT_RESET and EM_RESET. In addition, reset unit  8  receives EM_RESET_CLR that is asserted when the emulation reset request has been cleared, respectively. 
     Event handler  14  includes two registers: ILAT register  41  and IPEND register  42 . The ILAT register  41  includes a number of bits for storing requested events that have not been serviced. An “event” is any action or occurrence to which processor  2  must respond including, for example, entering emulation mode, interrupts and exceptions. ILAT register  41  is cleared when the event is taken by event handler  14 . IPEND register  42  is a status register that includes a corresponding bit for each event. Once processor  2  accepts an event and, for example, invokes a corresponding service routine, event handler  14  sets the appropriate bit within IPEND register  42  and clears the corresponding bit in ILAT register  14 . Event handler  14  clears, the status bit of IPEND register  42  when the event service routine returns. 
     In one embodiment, event handler  14  treats a reset event as the second highest priority event, with only emulation mode having a higher priority. When a reset event is received and processor  2  is in emulation mode, the reset event is not taken until processor  2  exits from emulation mode. 
     When HARD_RESET is asserted for at least one clock cycle, signal  43  clears the reset event bit of IPEND register  42 , thereby clearing any pending reset events. Next, after a second clock cycle, signal  49  sets the reset event bit within ILAT  41  to record the pending reset event. Event handler  14  accepts the reset event when processor  2  is not in emulation mode and asserts RESET_MASKED_REQ  46  to indicate that reset unit  8  may generate a reset pulse. More specifically, AND gate  45  drives RESET_MASKED_REQ  46  high when: (1) ILAT register  41  indicates that a reset event has been accepted, (2) processor  2  is not in emulation mode (EM_MODE) and (3) there is not a current emulation request (EM_REQ). Reset unit  8  latches RESET_MASKED_REQ  56  into a series of storage circuits  47  over N clock cycles, causing SE_RESET to be active for N clock cycles after RESET_MASKED_REQ  56  is deasserted. 
     When the reset condition is no longer detected, reset unit  8  instructs event handler  14  to clear SE_RESET. In the case of a hard reset, AND gate  48  drives HARD_RST_FEDGE  44  high when a falling edge is detected on HARD_RESET. Alternatively, EM_RESET_CLR is asserted when an emulation reset request is cleared, respectively. Assertion of either of these two signals causes AND gate  44  to output a zero, thereby clearing the reset event bit within ILAT register  51 . This in turn clears RESET_MASKED_REQ  46  and, N clock cycles later, clears SE_RESET. In this fashion, reset unit  8  holds SE_RESET active for N clock cycles after a reset condition is removed. 
     IPEND register  42  is cleared when SE_RESET is deasserted and when the RST_EXIT signal is asserted, typically upon the conclusion of an event handling service routine by the execution of a return from interrupt instruction (RTI). 
     FIG. 5 is a flowchart illustrating an example process  40  for resetting processor  2 . First, reset logic  6  receives a reset request, such as a hard reset request generated when the user presses a physical reset button. Next, for hard reset requests, reset unit  8  resets the IPEND register  42  to clear the reset event bit one clock cycle after receiving the hard reset request. In addition, reset unit  8  sets the appropriate bit in ILAT register  41  of event handler  14  to record the event request ( 51 ). 
     After receiving the reset request and updating ILAT register  41 , event handler  14  checks whether processor  2  is in emulation mode or whether an emulation request is pending ( 52 ); When no longer in emulation mode, and no emulation request is pending, event handler  14  marks the reset event as accepted by setting the appropriate bit of IPEND register  42  and clearing the appropriate bit of ILAT register  41  ( 53 ). 
     Next, event handler  14  asserts SE_RESET ( 54 ) and monitors the reset requests to detect when the reset request is removed. For example, a software reset request typically lasts for a single clock cycle but a hard reset request may last many clock cycles depending on how long the user presses the reset button. 
     After the reset request is removed ( 55 ), reset unit  8  holds SE_RESET for an additional N cycles to propagate cleared valid bits through pipeline  4 , thereby marking the stages of pipeline  4  as invalid ( 56 ). As described above, the cleared valid bits prevent instruction fetch unit  21  from fetching instructions, causing processor  2  to consume less power during reset. After N cycles, reset unit  8  deasserts SE_RESET ( 57 ) and pipeline  4  proceeds from the initialized state by issuing a reset address to fetch unit  21  ( 58 ). The reset address is typically the starting address for a reset service routine and may be read from a vector table or external input pins. When the reset service routine finishes execution, event handler clears the appropriate bit of IPEND register  42  to indicate completion of the reset process ( 59 ). 
     Various embodiments of the invention have been described. For example, a pipelined processor has been described that includes a reset unit that provides an output reset signal to at least one stage of an execution pipeline. The reset unit handles reset requests, such as hard resets, soft resets and emulation resets, as a reset event having an assigned priority. 
     The processor can be implemented in a variety of systems including general purpose computing systems, digital processing systems, laptop computers, personal digital assistants (PDA&#39;s) and cellular phones. In such a system, the processor may be coupled to a memory device, such as a FLASH memory device or a static random access memory (SRAM), that stores an operating system or other software applications. These and other embodiments are within the scope of the following claims.