Patent Publication Number: US-10318471-B2

Title: Method to share data between semiconductors chips

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority to Great Britain Patent Application No. 1610199.0, filed Jun. 10, 2016, which is incorporated herein by reference in its entirety. 
     TECHNICAL FIELD 
     The technical field relates to a method to share data between semiconductors chips and, in particular, a method to optimize the data communication of semiconductor chips sharing the serial data from a first controller chip to different power chips connected to electrical load, which minimizes the number of connection, output delay and power dissipation problems. 
     BACKGROUND 
     Conventional electronics architectures usually consists in a logic controller chip (e.g. microcontroller, FPGA) and several power chips connected to the logic controller using serial or parallel data lines. In the automotive field, for example, an electronic control unit (ECU) is used to control the internal combustion engine. The microcontroller inside the ECU receives input signals from sensors associated with the internal combustion engine and generates output signals to different devices, as for example driving circuits of actuators provided to control the operation of the internal combustion engine. 
     The connection from the logic controller and the power chips using parallel lines (one for each output) can be critical for the very large number of lines requested and constrains in the logic controller package and related pin numbers; the use of the most serial line protocols (e.g. SPI) can be critical for the output latency. The introduction of the microsecond channel bus (MSC) solves many of the issues stated above and it is already implemented in the most diffused microcontrollers used in the automotive, as well as is available in different power driver output chips. 
     Current microcontrollers can serialize several parallel output lines for controlling many actuators connected to fast signals (e.g. timer outputs) using the microsecond bus. At present, known microcontrollers can support MSC up to 40 MHz with frame up to 40 bits shared between up to two devices connected and selected by the related chip-select ensuring a defined and fast data output refresh (up to 1 μs, thus the name microsecond bus). The MSC bus uses Low-Voltage Differential Signaling (LVDS, also known as TIA/EIA-644) clock and data lines from microcontroller to the devices, non-differential lines are used for chip selects and asynchronous upstream, used for diagnosis, from devices to the microcontroller. The number of chip-select outputs is a big limitation because the power dissipation limits the number of actuators controlled by a single driving circuit. For example, no more than two DC motors can be controlled by the same driving circuit. Therefore, a maximum of four DC motors could be controlled using a single microsecond bus made available by a known microcontroller. 
     SUMMARY 
     In accordance with the present disclosure, a method is provided to share data between a microcontroller and a plurality of driving circuits of actuators which extends the number of the driving circuits and/or the number of the actuators that can be controlled through the microsecond bus. The present disclosure also provides a method to share data between a microcontroller and a plurality of driving circuits of actuators which is fully compatible with current microsecond bus and microcontrollers capability. The present disclosure further provides a method to share data between a microcontroller and a plurality of driving circuits of actuators which reduces the number of microcontroller pins needed to perform the control of the driving circuits. 
     According to an embodiment, a method to share data between a microcontroller and a plurality of driving circuits of actuators includes: providing a microcontroller with a microsecond bus and a plurality of chip-select outputs; providing a plurality of driving circuits having input pins for data signals received from the microcontroller through the microsecond bus, wherein each of the driving circuits has an input pin receiving a signal from a chip-select output of the microcontroller and at least two configuration pins connected to the ground voltage or to a supply voltage; and sending a data frame signal on the microsecond bus. Each of the driving circuits is supplied with a portion of the data frame signal as a function of the chip-select output of the microcontroller and as a function of the voltage connection of the at least two configuration pins. 
     In practice, the driving circuits may be physically divided into different objects and recognize the part of the data frame signal of their interest, but the driving circuits are seen from the microcontroller as a single device. In this way, the data frame signal transferred on the microsecond bus can be shared among a number of more than two driving circuits. This permits usage of the standard electronic control units currently available in this field to increase the number of actuators that can be controlled by the microcontroller embedded in these units. 
     According to an embodiment, at least one of the driving circuits may include an H-bridge circuit to drive the operation of a DC motor. According to an embodiment, at least one of the driving circuits may include a LVDS buffer for clock and data signals in order to improve the signal/noise ratio and assure the correct functioning at the maximum communication speed. 
     According to an embodiment, the method may communicate data signals between the microcontroller and at least one of the driving circuits through the microsecond bus to configure the at least one driving circuit and read back the diagnosis of the at least one driving circuit. 
     According to another aspect of the present disclosure, a computer program product includes computer executable codes to share data between a microcontroller and a plurality of driving circuits of actuators. The microcontroller is provided with a microsecond bus and a plurality of chip-select outputs. A plurality of driving circuits is provided having input pins for data signals received from the microcontroller through the microsecond bus. Each of the driving circuits having an input pin for receiving a signal from a chip-select output of the microcontroller and at least two configuration pins connected to the ground voltage or to a supply voltage. The computer program product can be stored on a suitable storage unit and includes: computer executable codes for sending a data frame signal on the microsecond bus; and computer executable codes for supplying the driving circuits with a portion of the data frame signal as a function of the chip-select output of the microcontroller and as a function of the voltage connection of its at least two configuration pins. According to an embodiment, computer executable codes are provided for communicating data signals between the microcontroller and at least one of the driving circuits through the microsecond bus to configure the at least one driving circuit and read back the diagnosis of the at least one driving circuit. According to an embodiment, the above computer program product can be stored in a computer readable medium. 
     Another aspect of the disclosure relates to a driving circuit having input pins for at least one enable signal, one pulse width modulation signal and one direction signal of at least one actuator, wherein the driving circuit has at least two configuration pins to be connected to the ground voltage or to a supply voltage. 
     According to an embodiment, the driving circuit further includes a LVDS buffer for clock and data signals. 
     According to another embodiment, the driving circuit has an H-bridge circuit to drive the operation of a DC motor. 
     Another aspect of the disclosure relates to an electronic control unit having a microcontroller to perform the above method and/or execute the above computer codes. 
     Another aspect of the disclosure relates to an automotive system including an internal combustion engine, a plurality of actuators, a plurality of driving circuits for the actuators and an electronic control unit having a microcontroller to perform the above method. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The present disclosure will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements. 
         FIG. 1  shows an embodiment of an automotive system including an internal combustion engine; 
         FIG. 2  is a cross-section according to the plane A-A of an internal combustion engine belonging to the automotive system of  FIG. 1 ; 
         FIG. 3  is a scheme of the control of a single driving circuit according to the prior art; 
         FIG. 4  is a scheme of the control of driving circuits of actuators according to the prior art; 
         FIG. 5  is a scheme of the control of driving circuits according to an embodiment of the present disclosure; 
         FIG. 6  is a detail of the control of a single driving circuit of  FIG. 5   
         FIG. 7  is a graph of the time development of control signals according to an embodiment of the present disclosure; 
         FIG. 8  is a schematic representation of a portion of data frame signal of  FIG. 7 ; 
         FIG. 9  is schematic view of another embodiment of a driving circuit of the present disclosure; and 
         FIG. 10  is a scheme of the control by driving circuits of  FIG. 9 . 
     
    
    
     DETAILED DESCRIPTION 
     The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. 
     Some embodiments may include an automotive system  100 , as shown in  FIGS. 1 and 2 , that includes an internal combustion engine (ICE)  110  having an engine block  120  defining at least one cylinder  125  having a piston  140  coupled to rotate a crankshaft  145 . A cylinder head  130  cooperates with the piston  140  to define a combustion chamber  150 . A fuel and air mixture (not shown) is disposed in the combustion chamber  150  and ignited, resulting in hot expanding exhaust gasses causing reciprocal movement of the piston  140 . The fuel is provided by at least one fuel injector  160  and the air through at least one intake port  210 . The fuel is provided at high pressure to the fuel injector  160  from a fuel rail  170  in fluid communication with a high pressure fuel pump  180  that increase the pressure of the fuel received from a fuel source  190 . 
     Each of the cylinders  125  has at least two valves  215 , actuated by the camshaft  135  rotating in time with the crankshaft  145 . The valves  215  selectively allow air into the combustion chamber  150  from the port  210  and alternately allow exhaust gases to exit through a port  220 . In some examples, a cam phaser  155  may selectively vary the timing between the camshaft  135  and the crankshaft  145 . 
     The air may be distributed to the air intake port(s)  210  through an intake manifold  200 . An air intake duct  205  may provide air from the ambient environment to the intake manifold  200 . In other embodiments, a throttle body  330  may be provided to regulate the flow of air into the manifold  200 . In still other embodiments, a forced air system such as a turbocharger  230 , having a compressor  240  rotationally coupled to a turbine  250 , may be provided. Rotation of the compressor  240  increases the pressure and temperature of the air in the duct  205  and manifold  200 . An intercooler  260  disposed in the duct  205  may reduce the temperature of the air. The turbine  250  rotates by receiving exhaust gases from an exhaust manifold  225  that directs exhaust gases from the exhaust ports  220  and through a series of vanes prior to expansion through the turbine  250 . The exhaust gases exit the turbine  250  and are directed into an exhaust system  270 . This example shows a variable geometry turbine (VGT) with a VGT actuator  290  arranged to move the vanes to alter the flow of the exhaust gases through the turbine  250 . In other embodiments, the turbocharger  230  may be fixed geometry and/or include a waste gate. 
     The exhaust system  270  may include an exhaust pipe  275  having one or more exhaust aftertreatment devices  280 . The aftertreatment devices may be any device configured to change the composition of the exhaust gases. Some examples of aftertreatment devices  280  include, but are not limited to, catalytic converters (two and three way), oxidation catalysts, lean NO x  traps, hydrocarbon adsorbers, selective catalytic reduction (SCR) systems, and particulate filters. Other embodiments may include an exhaust gas recirculation (EGR) system  300  coupled between the exhaust manifold  225  and the intake manifold  200 . The EGR system  300  may include an EGR cooler  310  to reduce the temperature of the exhaust gases in the EGR system  300 . An EGR valve  320  regulates a flow of exhaust gases in the EGR system  300 . 
     The automotive system  100  may further include an electronic control unit (ECU)  450  in communication with one or more sensors and/or devices associated with the ICE  110 . The ECU  450  may receive input signals from various sensors configured to generate the signals in proportion to various physical parameters associated with the ICE  110 . The sensors include, but are not limited to, a mass airflow and temperature sensor  340 , a manifold pressure and temperature sensor  350 , a combustion pressure sensor  360 , coolant and oil temperature and level sensors  380 , a fuel rail pressure sensor  400 , a cam position sensor  410 , a crank position sensor  420 , exhaust pressure and temperature sensors  430 , an EGR temperature sensor  440 , and an accelerator pedal position sensor  445 . Furthermore, the ECU  450  may generate output signals to various control devices that are arranged to control the operation of the ICE  110 , including, but not limited to, the fuel pump  180 , fuel injectors  160 , the throttle body  330 , the EGR Valve  320 , the VGT actuator  290 , and the cam phaser  155 . Note, dashed lines are used to indicate communication between the ECU  450  and the various sensors and devices, but some are omitted for clarity. 
     Turning now to the ECU  450 , this apparatus may include a digital central processing unit (CPU) in communication with a memory system  460 , or data carrier, and an interface bus. The CPU is configured to execute instructions stored as a program in the memory system, and send and receive signals to/from the interface bus. The memory system may include various storage types including optical storage, magnetic storage, solid state storage, and other non-volatile memory. The interface bus may be configured to send, receive, and modulate analog and/or digital signals to/from the various sensors and control devices. 
     Instead of an ECU  450 , the automotive system  100  may have a different type of processor to provide the electronic logic, e.g. an embedded controller, an onboard computer, or any processing module that might be deployed in the vehicle. 
     DC motors are an example of actuators used in the automotive system  100  of  FIGS. 1 and 2 . As shown in  FIG. 3 , DC motors can be controlled using H-bridge circuits which are typically integrated in a single integrated circuit solution. A driving circuit ICx can control two DC motors M 1  and M 2  in order to limit the area occupied on a printed circuit board of the electronic control unit  450  and the power dissipation. 
     The microcontroller  20  shall use three signals sent in parallel configuration to the driving circuit ICx to control each DC motor M 1  and M 2 , namely an enable signal EN to enable/disable the related DC motor, a direction signal DIR to select the direction of the rotation (forward or reverse) and a PWM signal to modulate the current supplied to the related motor to impart the rotation. A total of six signals, namely EN-M 1 , DIR-M 1 , PWM-M 1  for DC motor M 1  and EN-M 2 , DIR-M 2 , PWM-M 2  for DC motor M 2 , are therefore sent in parallel configuration to the driving circuit ICx. Moreover, a communication bus SPI (Serial Protocol Interface) can be used for example to configure the driving circuit ICx and read back the diagnosis. 
     The scheme of  FIG. 4  shows an electronic control unit  450  provided with a microcontroller  20 , for example a control process unit (CPU). The microcontroller  20  has a microsecond bus  10  and two chip-select outputs CS 1  and CS 2  for two driving circuits IC 1  and IC 2 . In the exemplary embodiment of  FIG. 4 , reference is made to electric DC motors M 1 -M 4  as actuators driven by the driving circuits IC 1  and IC 2 . 
     The microcontroller  20  can serialize the control of many actuators using the microsecond bus  10  up to 40 MHz. The microcontroller  20  supports 40 bit signals shared between up to two driving circuits IC 1  and IC 2  connected and selected by the related chip-select outputs CS 1  and CS 2 . The number of chip-select outputs is a big limitation because the power dissipation limits the number of actuators controlled by a single driving circuit. For example, no more than two DC motors can be controlled by the same driving circuit. Therefore, according to the prior art scheme of  FIG. 4 , up to a maximum of four DC motors M 1 -M 4  could be controlled using the microsecond bus  10 , so is why the use of microsecond channel bus is not usually applied in high-power driver devices. 
     As shown in the scheme of  FIG. 5 , according to the solution of the present disclosure, it is possible to extend the number of driving circuits, namely up to six driving circuits IC 1 -IC 6 , in order to drive up to twelve DC motors M 1 -M 12  by using the output signals transmitted on the microsecond bus  10  and the only two chip-select signals CS 1  and CS 2  made available by the same microcontroller  20 . 
       FIG. 6  shows one exemplary driving circuit ICi of the six circuits IC 1 -IC 6  of  FIG. 5 . As in the driving circuit ICx of  FIG. 4 , the driving circuit ICi has two H-bridge circuits integrated in a single chip. However, the driving circuit ICi is further provided with two configuration pins CP 1  and CP 2  that can be directly connected by wiring to the ground voltage or to a supply voltage. Configuration pins CP 1  and CP 2  allow the selection of a portion of the data frame signal received from the microsecond bus without the need of changes to the microcontroller  20  currently used in the automotive field. 
     As already stated, the microcontroller  20  may support 40 bit signals and can be operated at 40 MHz. This means that a data frame signal of 40 control bits can be transmitted each microsecond to all the driving circuits IC 1 -IC 6 ; since each driving circuit needs a total of six bits, i.e. three bits for each of the two DC motors driven by a single circuit, each of the driving circuits IC 1 -IC 6  can be configured to consider only the six bits of the related portion of the whole data frame signal of 40 bits. 
     In particular, as shown in the graph of  FIGS. 7 and 8 , the data frame signal sent by the microcontroller  20  is received by all the driving circuits IC 1 -IC 6  connected on the microsecond bus  10 . Each circuit consider only the portion of the data frame selected by the related chip-select CS 1  and CS 2  received by the microcontroller  20  and by the configuration pins CP 1  and CP 2  connected to ground voltage GND or supply voltage VCC. 
     The first three driving circuits IC 1 -IC 3  can be selected by the chip-select signal CS 1  to consider only the first bits  1  to  19  of the data frame signal. Configuration pins CP 1  and CP 2  of the driving circuit IC 1  can be connected for example both to ground voltage GND to set the driving circuit IC 1  in such a way that only bits  1  to  6  are considered. As shown in  FIG. 8 , the first three bits  1 - 3  are the data signal PWM, DIR and EN for the first DC motor M 1 , while the subsequent three bits  4 - 6  are the data signal PWM, DIR and EN for the second DC motor M 2  driven by the same driving circuit IC 1 . Configuration pins CP 1  and CP 2  of the driving circuit IC 2  can be connected for example to ground voltage GND and to VCC voltage, respectively. The driving circuit IC 2  is set to consider only bits  7  to  12 , where bits  7 - 9  are the data signal PWM, DIR and EN for the DC motor M 3  and bits  10 - 12  are the data signal PWM, DIR and EN for DC motor M 4  driven by IC 2 . In the same way, configuration pins CP 1  and CP 2  of the driving circuit IC 3  can be connected for example to VCC voltage and to ground voltage GND, respectively. The driving circuit IC 3  is then set to consider only bits  13  to  18 , where bits  13 - 15  are the data signal PWM, DIR and EN for the DC motor M 5  and bits  14 - 18  are the data signal PWM, DIR and EN for DC motor M 6  driven by IC 3 . 
     The same strategy can be applied for driving circuits IC 4 , IC 5  and IC 6  enabled by CS 2 , therefore considering bits from  21  to  39  of the data frame signal. 
     Bits  0 ,  19 ,  20  and  39  of the data frame signal could assume any logic value because they are not significant in the present protocol. 
       FIG. 9  shows another embodiment of a driving circuit ICz that can be used according to the method of the present disclosure. As in the driving circuit ICi of  FIG. 6 , the driving circuit ICz is provided with two configuration pins CP 1  and CP 2  for the selection of a portion of the data frame signal received from the microsecond bus  10 . The driving circuit is further equipped with a LVDS buffer  30 , shown in dotted lines, which eliminates possible signal reflections on the LVDS lines of the microsecond bus  10 . The buffer  30  improves the signal/noise ratio in order to assure a correct operation at the maximum communication speed. 
       FIG. 10  is a scheme of the connections of the microsecond bus  10  between the microcontroller  20  and driving circuits IC 1 -IC 6  by driving circuits IC 1  and IC 4  provided with a LVDS buffer  30  as the driving circuit ICz of  FIG. 9 . As in the scheme of  FIG. 5 , six driving circuits IC 1 -IC 6  allow to drive up to twelve DC motors M 1 -M 12  by using the output signals transmitted on the microsecond bus  10  and the only two chip-select signals CS 1  and CS 2  made available by the same microcontroller  20 . Driving circuits IC 1  and IC 4  are both provided with a buffer  30  which receives the data frame signal and the clock signal in input and share the buffered signals with driving circuits IC 2 , IC 3  and IC 5 , IC 6  respectively. 
     While at least one exemplary embodiment has been presented in the foregoing detailed description, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment, it being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims and their legal equivalents.