Patent Publication Number: US-2023163091-A1

Title: Electronic package structure and method for manufacturing the same

Description:
BACKGROUND 
     1. Technical Field 
     The present disclosure relates generally to electronic package structures and methods for manufacturing the same. 
     2. Description of the Related Art 
     Undesired warpage of an electronic component may occur due to a CTE (coefficient of thermal expansion) mismatch between a substrate or a printed circuit board and the electronic component bonded thereon. The warpage may cause the distance between a surface of the electronic component and a surface of the substrate to vary from edge to center. For example, a distance between an edge of a surface of the electronic component and a surface of the substrate may be greater than that between a center of the surface of the electronic component and the surface of the substrate. As such, the conductive layers on the edge of the surface of the electronic component may not be able to successfully bond to the corresponding conductive layers on the substrate as they are spaced farther apart, which may affect performance and reliability of the electronic component. For these and other reasons, various electronic package structures and methods for manufacturing the same are being developed. 
     SUMMARY 
     In some arrangements, an electronic package structure includes a first electronic component, a second electronic component, an interconnection element, an insulation layer, and an encapsulant. The second electronic component is disposed adjacent to the first electronic component. The interconnection element is disposed between the first electronic component and the second electronic component. The insulation layer is disposed between the first electronic component and the second electronic component and has a side surface and a top surface connecting to the side surface. The encapsulant surrounds the interconnection element and at least partially covers the top surface of the insulation layer and has an extended portion in contact with the side surface of the insulation layer. 
     In some arrangements, a method for manufacturing an electronic package structure includes: providing a first electronic component including a first conductive layer and a second electronic component including a second conductive layer; pressing the first electronic component to partially interconnect the first conductive layer and the second conductive layer; and applying a condensed energy on the first electronic component to completely interconnect the first conductive layer and the second conductive layer. 
     In some arrangements, an electronic package structure includes an electronic component and an encapsulant. The electronic component is connected to a carrier through a connection structure. The encapsulant accommodates the connection structure and includes an extension between the connection structure and the carrier. The extension is configured to hinder delamination between the encapsulant and an upper surface of the carrier. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    illustrates a cross-sectional view of an electronic package structure according to some arrangements. 
         FIG.  2    illustrates a cross-sectional view of an electronic package structure according to some arrangements. 
         FIG.  3    illustrates a cross-sectional view of an electronic package structure according to some arrangements. 
         FIG.  4 A  and  FIG.  4 B  illustrate various operations in a method for manufacturing an electronic package structure according to some arrangements. 
     
    
    
     DETAILED DESCRIPTION 
     Spatially relative terms, such as “top,” “bottom,” “beneath,” “below,” “above,” “over,” “on,” “upper,” “lower,” “left,” “right,” “vertical,” “horizontal,” “side” and the like, may be used herein for ease of description of one element or feature&#39;s relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected or coupled to the other element, or intervening elements may be present. 
       FIG.  1    illustrates a cross-sectional view of an electronic package structure  100  according to some arrangements of the present disclosure. The electronic package structure  100  of  FIG.  1    includes a first electronic component  101 , a second electronic component  103 , an interconnection element  109 , an insulation layer  111 , and an encapsulant  115 . 
     The first electronic component  101  may include at least one first pad  106  disposed adjacent to a lower surface  101   a  of a main body  102  thereof. The first electronic component  101  may be or include an active component (e.g., a die or a chip). In some examples, the first electronic component  101  may be or include a die. A conductive bump  107  may be disposed adjacent to or on the lower surface  101   a  of the main body  102 . For example, in some arrangements, the conductive bump  107  may be disposed adjacent to or on the first pad  106  of the main body  102 . The conductive bump  107  may electrically connect to the lower surface  101   a  of the main body  102  through the first pad  106 . In some examples, the conductive bump  107  is disposed on (e.g., physically contacts) the first pad  106 . 
     The conductive bump  107  has a first surface (an upper surface)  107   b  facing the first electronic component  101  and a second surface (a lower surface)  107   a  opposite to the first surface  107   b . An edge  107   d  of the first surface  107   b  of the conducive bump  107  may incline toward the first electronic component  101 . The edge  107   d  of the first surface  107   b  of the conductive bump  107  may be closer to the main body  102  than a non-edge portion of the first surface  107   b  is. The first surface  107   b  may include an inclined surface  107   s . In some examples, the inclined surface  107   s  slopes down from the edge  107   d  to a center of the first surface  107   b . The first surface  107   b  may have a sharp corner at the edge  107   d  from a cross-sectional perspective. The second surface  107   a  may be an uneven surface. In some arrangements, the second surface  107   a  may be or include a curved surface. A recess  107   c  may be located at the second surface  107   a . The recess  107   c  may be located at or adjacent to a center of the second surface  107   a . A width of the conductive bump  107  may be greater than a width of the first pad  106 . The conductive bump  107  may be a pillar or a solder/stud bump. 
     The second electronic component  103  is disposed adjacent to the first electronic component  101 . The second electronic component  103  has an upper surface  103   a  facing the second surface  107   a  of the conductive bump  107  and the lower surface  101   a  of the main body  102 . The second electronic component  103  may include a circuit pattern on the upper surface  103   a  and/or a circuit pattern embedded therein. A second pad  105  may be disposed adjacent to or on (e.g., physically contact) the upper surface  103   a  of the second electronic component  103 . The second pad  105  may be a part of the circuit pattern of the second electronic component  103  or may electrically connect to the circuit pattern of the second electronic component  103 . The second electronic component  103  may be, for example but not limited to, a carrier, a substrate, a die or a chip, a quad flat no-lead (QFN) package, a dual flat no-lead (DFN) package, a lead frame, a printed circuit board, an interposer, or a redistribution layer. In some examples, the second electronic component  103  is a substrate or a printed circuit board. 
     The interconnection element  109  is disposed between the first electronic component  101  and the second electronic component  103 . The interconnection element  109  may be disposed between the conductive bump  107  and the second pad  105 . The interconnection element  109  may electrically connect to the conductive bump  107  and the second pad  105 . The interconnection element  109  may bond to the conductive bump  107  and the second pad  105 . The interconnection element  109  may be configured to join the conductive bump  107  to the second pad  105 . The interconnection element  109  has a first surface (an upper surface)  109   a  facing the conductive bump  107 . The first surface (an upper surface)  109   a  may also face the main body  102  of the first electronic component  101 . The first surface  109   a  of the interconnection element  109  may be an uneven surface. The first surface  109   a  may be or include a curved surface. In some examples where the interconnection element  109  connects to the conductive bump  107  directly, the first surface  109   a  (or the second surface  107   a  of the conductive bump  107 ) is also the interface  110  at which the conductive bump  107  and the interconnection element  109  connects. The first surface  109   a  of the interconnection element  109  may conform to the shape of the second surface  107   a  of the conductive bump  107 . In some arrangements, the conductive bump  107  together with the interconnection element  109  may be referred to as “connection structure” or “electrical connection structure.” 
     The interconnection element  109  may include a base  109   d  and a body  109   e  connecting to the base  109   d  and farther from the second pad  105  than the base  109   d  is. The base  109   d  may directly contact the second pad  105 . A width of the base  109   d  may be greater than a width of the body  109   e . The base  109   d  may include a skirt portion  109   s . The body  109   e  may include a narrow top portion  109   t , a wide middle portion  109   m , and a narrow bottom portion  109   b . The wide middle portion  109   m  may connect to the narrow top portion  109   t  and the narrow bottom portion  109   b  and form a substantially continuous and curved lateral surface  109   c  extending from the interface  110  to the base  109   d . The lateral surface  109   c  may be considered substantially continuous when no obvious turning points can be observed under a specific microscope magnification. The interconnection element  109  may include, for example, a soldering material. The soldering material may include Au, Cu, Ni, Sn or a combination of two or more thereof, but is not limited thereto. In some arrangements, the soldering material may include AuSn, CuSn, NiSn, or a combination of two or more thereof, but is not limited thereto. 
     The insulation layer  111  is disposed between the first electronic component  101  and the second electronic component  103 . The insulation layer  111  may be disposed adjacent to or on (e.g., physically contact) the upper surface  103   a  of the second electronic component  103 . The insulation layer  111  has a first surface (an upper surface or a top surface)  111   a  facing the first electronic component  101  and a second surface (a lower surface or a bottom surface)  111   b  opposite to the first surface  111   a . A side surface  111   d  connects to the top surface  111   a  and the bottom surface  111   b . The insulation layer  111  may cover at least a portion of the second pad  105 . The insulation layer  111  may cover an edge (e.g., a peripheral edge) of the second pad  105 . In some examples, the insulation layer  111  covers at least a portion of the second pad  105  and defines a gap  113  with the interconnection element  109 . In some arrangements, the interconnection element  109  has a portion (e.g.,  109   b  and  109   d ) embedded in the insulation layer  111  and connected to the second pad  105  and the gap  113  is defined by the insulation layer  111  and the embedded portion of the interconnection element  109 . The gap  113  may extend between the first surface  111   a  of the insulation layer  111  and the second surface  111   b  of the insulation layer  111 . In some arrangements, the gap  113  may extend from the first surface  111   a  of the insulation layer  111  to underneath the second surface  111   b  of the insulation layer  111 . In some arrangements, the second surface  111   b  may be spaced from the second pad  105  and the base  109   d  of the interconnection element  109  by a portion of the gap  113 . A portion of the base  109   d  may be between the insulation layer  111  and the second pad  105 . The insulation layer  111  may include a curved corner  111   c  adjacent to the gap  113 . In some examples, the corner  111   c  may be a rounded corner. The insulation layer  111  may be, for example, a solder mask (the material of which is, for example, polyimide (PI)), or a passivation layer (the material of which is, for example, a metal oxide). 
     The encapsulant  115  is disposed between the first electronic component  101  and the second electronic component  103 . In some examples, the encapsulant  115  is disposed around the interconnection element  109 . In some examples, the encapsulant  115  surrounds the interconnection element  109  and at least partially covers the top surface  111   a  of the insulation layer  111 . In some examples, the encapsulant  115  accommodates the interconnection element  109 . In some examples, at least an extended portion  115   c  of the encapsulant  115  is in contact with the side surface  111   d  of the insulation layer  111 . By contacting the extended portion  115   c  of the encapsulant  115  with the side surface  111   d  of the insulation layer  111 , the contact surface areas between the encapsulant  115  and the insulation layer  111  may be increased so the encapsulant  115  may hold on to the insulation layer  111  more tightly, which may improve the adhesion of the insulation layer  111  to the second electronic component  103  and diminish the occurrence of the delamination of the insulation layer  111  from the second electronic component  103 . 
     In some examples, at least an extended portion  115   c  of the encapsulant  115  is in the gap  113 . In some examples, at least a portion of an extension  115   c  of the encapsulant  115  is in the gap  113  and configured to hinder delamination between the encapsulant  115  and the upper surface  103   a  of the second electronic component  103  (or the first surface  111   a  of the insulation layer  111 ) as the extension  115   c  may provide mold lock effect to the insulation layer  111 . In some examples, the extension  115   c  may be configured to enhancing the adhesion between the encapsulant  115  and the upper surface  103   a  of the second electronic component  103  (or the first surface  111   a  of the insulation layer  111 ). In some examples where the second electronic component  103  is a carrier and the body  109   e  of the interconnection element  109  includes a soldering material, the extension  115   c  is disposed between the soldering material  109  and the carrier  103  (or the insulation layer  111 ). The encapsulant  115  may include an epoxy resin, a molding compound (e.g., an epoxy molding compound or other molding compounds), polyimide, a phenolic compound or material, a material with a silicone dispersed therein, or a combination thereof. In some arrangements, the encapsulant  115  may include an underfill material. In some arrangements, the encapsulant  115  may include fillers, the material of which is, for example, silica and/or carbon, for reducing stress on the substrate and warpage of a resulting electronic package. 
     By providing a gap  113  defined by the interconnection element  109  and the first insulation layer  111  and filling into the gap a portion (i.e.,  115   c ) of the encapsulant, a mold lock effect may be provided so the encapsulant  115  may not be easily delaminated from the second electronic component  103  (or the first insulation layer  111 ). Accordingly, the adhesion effect of the encapsulant  115  to the second electronic component  103  (or the first insulation layer  111 ) may be improved. 
     In some arrangements, the electronic package structure  100  further includes a second insulation layer  117  adjacent to or disposed on (e.g., physically contact) the lower surface  101   a  of the first electronic component  101 . The second insulation layer  117  may be disposed between the first electronic component  101  and the conductive bump  107  and between the first electronic component  101  and the encapsulant  115 . The second insulation layer  117  may be disposed around a protrusion portion  107   p  of the conductive bump  107 . The portion  107   e  of the conductive bump  107  may protrude beyond a level of the second insulation layer  117 . In some examples, a portion  107   e  of the conductive bump  107  may protrude against the second insulation layer  117 . The second insulation layer  117  may be, for example, a solder mask (the material of which is, for example, polyimide (PI)), or a passivation layer (the material of which is, for example, a metal oxide). 
       FIG.  2    illustrates a cross-sectional view of an electronic package structure  200  according to some arrangements of the present disclosure. The electronic package structure  200  illustrated in  FIG.  2    is similar to that illustrated in  FIG.  1    with a difference being that a first conductive layer  119   a  and a second conductive layer  119   b  is present in the electronic package structure  200 . As illustrated in  FIG.  2   , the first conductive layer  119   a  is disposed on the conductive pump  107  and the second conductive layer  119   b  is disposed on the second pad  105 . The first conductive layer  119   a  may partially contact the second conductive layer  119   b . In some examples, the first conductive layer  119   a  may contact the second conductive layer  119   b  at one or more portions (e.g.,  120   a ,  120   b  and/or  120   c ). In some examples, the first conductive layer  119   a  may contact the second conductive layer  119   b  at a center portion (e.g.,  120   b ) of the interface between the first conductive layer  119   a  and the second conductive layer  119   b . Since the first conductive layer  119   a  does not connect to the second conductive layer  119   b  completely, the bonding strength of the connection structure between the first electronic component  101  and the second electronic component  103  may not be as strong as that shown in  FIG.  1   . In some examples, the electronic package structure  200  may be formed by pressing the first electronic component  101  to contact at least a portion of the first conductive layer  119   a  to at least a portion of the second conductive layer  119   b  by a thermal compression bonding process. 
       FIG.  3    illustrates a cross-sectional view of an electronic package structure  300  according to some arrangements of the present disclosure. The electronic package structure  300  illustrated in  FIG.  3    includes a plurality of connection structures illustrated in  FIG.  1   . In some examples, a warpage of the first electronic component  101  may occur due to a CTE (coefficient of thermal expansion) mismatch between the first electronic component  101  and the second electronic component  103 . As such, a first distance (height) H1 between an edge of a surface of the first electronic component  101  and a surface of the second electronic component  103  may be greater than a second distance (height) H2 between a center of the surface of the first electronic component  101  and the surface of the substrate. The warpage may be alleviated by adopting a thermal compression bonding process. In some arrangements, although slight warpage may still occur after carrying out a thermal compression bonding process, the first electronic component  101  may still successfully connect to the second electronic component  103  through the plurality of the connection structures illustrated in  FIG.  1   . 
       FIGS.  4 A- 4 B  illustrate various operations in a method for manufacturing an electronic package structure such as the electronic package structure of  FIG.  1   . 
     Referring to  FIG.  4 A , a first electronic component  101  and a second electronic component  103   103  are provided. In some examples, the first electronic component  101  is a die and the second electronic component  103  is a substrate. The first electronic component  101  may include a first conductive layer  119   a  disposed on a conductive bump  107  of the first electronic component  101 . The second electronic component  103  may include a second conductive layer  119   b  disposed on a second pad  105  of the second electronic component  103 . The first conductive layer  119   a  may be partially interconnected to the second conductive layer  119   b  by pressing the first electronic component  101  against the second electronic component  103  (or pressing the second electronic component  103  against the first electronic component  101 ) via a thermal compression bonding process. In some examples, the thermal compression bonding process is carried out to form a contact between at least a portion of the first conductive layer  119   a  and at least a portion of the second conductive layer  119   b , which may partially joint the first conductive layer  119   a  to the second conductive layer  119   b . An edge  107   d  of a top surface  107   b  of the conductive bump  107  may incline toward the first electronic component  101 , a recess  107   c  may occur at a bottom surface  107   a  of the conductive bump  107  by the first conductive layer  119   a , and an uneven surface  119   c  of the first conductive layer  119   a  facing the first electronic component  101  may be formed because of the pressure applied during the thermal compression bonding process. Afterwards, an electronic package structure (e.g., an electronic package structure  200  as is illustrated in of  FIG.  2   ) may be obtained. 
     By pressing the first electronic component  101  and/or the second electronic component  103  under a pressure prior to applying a condensed energy on the first electronic component  101  to fully joint the first conductive layer  119   a  to the second conductive layer  119   b , the extent of the warpage of the first electronic component  101  may be reduced, so that the height difference between the first height H1 between an edge of a surface of the first electronic component  101  and a surface of the second electronic component  103  and the second height H2 between a center of the surface of the first electronic component  101  and the surface of the second electronic component  103  may be decreased. Accordingly, the connection between the first conductive layer  119   a  and the second conductive layer  119   b  may be improved as they will not be parted far by the warpage. 
     Referring to  FIG.  4 B , the first conductive layer  119   a  may be completely interconnected to the second conductive layer  119   b  and form a joint structure after application of a condensed energy (such as laser energy) on the first electronic component  101 . The condensed energy may be supplied by carrying out for example, a laser assisted bonding process, but is not limited thereto). The first conductive layer  119   a  connects to the second conductive layer  119   b  at an uneven interface  110 . In some examples, the first metal layer  119   a  may completely joint to the second metal layer  119   b  at this stage. Afterwards, an electronic package structure (e.g., an electronic package structure  100  as is illustrated in of  FIG.  1   ) may be obtained. Since a pressure is applied to the first electronic component  101  and/or the second electronic component  103  to partially joint the first conductive layer  119   a  to the second conductive layer  119   b  prior to applying the condensed energy, the first conductive layer  119   a  may form a complete joint structure with the second conductive layer  119   b  more easily when the condensed energy is applied afterwards. In some examples, a gap  113  is formed between the connection structure (including the conductive bump  107  and the interconnection element  109 ) and the first insulation layer  111  on the second electronic component  103  because the second conductive layer  119   b  may shrink or condense due to the condensed energy. A filling material is filled around the connection structure to form an encapsulant  115 . A portion (i.e.,  115   c ) of the encapsulant  115  may be filled into the gap  113 . As a result, a mold lock effect may be provided so the encapsulant  115  may not be easily delaminated from the second electronic component  103  (or the first insulation layer  111 ). Accordingly, the adhesion effect of the encapsulant  115  to the second electronic component  103  (or the first insulation layer  111 ) may be improved, which may further improve the strength of the connection structure between the first electronic component  101  and the second electronic component  103 . 
     As used herein and not otherwise defined, the terms “substantially” and “about” are used to describe and account for small variations. When used in conjunction with an event or circumstance, the terms can encompass instances in which the event or circumstance occurs precisely as well as instances in which the event or circumstance occurs to a close approximation. For example, when used in conjunction with a numerical value, the terms can encompass a range of variation of less than or equal to ±10% of that numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. As another example, a line or a plane can be substantially flat if a peak or depression of the line or plane is no greater than 5 μm, no greater than 1 μm, or no greater than 0.5 
     As used herein, the singular terms “a,” “an,” and “the” may include plural referents unless the context clearly dictates otherwise. In the description of some arrangements, a component provided “on” or “over” another component can encompass cases where the former component is directly on (e.g., in physical contact with) the latter component, as well as cases where one or more intervening components are located between the former component and the latter component. 
     While the present disclosure has been described and illustrated with reference to specific arrangements thereof, these descriptions and illustrations are not limiting. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not necessarily be drawn to scale. There may be distinctions between the artistic renditions in the present disclosure and the actual apparatus due to manufacturing processes and tolerances. There may be other arrangements of the present disclosure which are not specifically illustrated. The specification and the drawings are to be regarded as illustrative rather than restrictive. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to be within the scope of the claims appended hereto. While the methods disclosed herein have been described with reference to particular operations performed in a particular order, it will be understood that these operations may be combined, subdivided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations are not limitations.