Patent Publication Number: US-7898336-B2

Title: Ground skimming output stage

Description:
PRIORITY CLAIM 
     This application is a continuation of U.S. patent application Ser. No. 11/234,010, filed Sep. 23, 2005 (which will issue as U.S. Pat. No. 7,459,978), which claims priority under 35 U.S.C. 119(e) to U.S. Provisional Patent Application No. 60/612,556, filed Sep. 23, 2004, each of which is incorporated herein by reference. 
    
    
     FIELD OF THE INVENTION 
     Embodiments of the present invention relate to the field of integrated circuits, and more specifically to output stages, e.g., for driving loads. 
     BACKGROUND 
     Traditional AB output stages typically do not allow the output voltage to substantially go to zero volts. More specifically, most output stages include a pair of complimentary emitter follower transistors that are biased so that there is some overlap, with an emitter follower of an N-type on the top side and an emitter follower of a P-type on the bottom side. In this arrangement, the output can only go within V BE  of the upper voltage rail and down to V BE  above the lower voltage rail. Thus, if the lower voltage rail is ground, as is often the case in circuits powered by a single power supply, the output can only go as low as about 0.7V. This, however, is not convenient for a video circuit where it is may be desirable to allow the output to approach ground. 
     SUMMARY OF THE PRESENT INVENTION 
     Embodiments of the present invention are directed to output stages that are designed to drive wideband signals with the ability to provide a high quality output signal substantially all the way to the lower supply rail (e.g., ground). In accordance with an embodiment of the present invention, the output stage of the present invention only requires a single positive power supply, consistent with the recent trend toward integrated circuits which only require a single low voltage power supply. 
     In accordance with an embodiment of the present invention, an output stage includes a translinear current controller, an output transistor and a current mirror. The translinear current controller is connected to a first voltage rail and includes first and second inputs, and an output. The output transistor includes a control terminal (e.g., a base or a gate) that forms an input of the output stage, an emitter (or source) that forms an output of the output stage, and a collector (or drain). The current mirror is connected to a second voltage rail and includes an input and an output. The first input of the translinear current controller is connected to a bias current source. The output of the translinear current controller is connected to the input of the current mirror. The second input of the translinear current controller is connected to the collector (or drain) of the output transistor. The emitter (or source) of the output transistor is connected to the output of the current mirror. 
     Further and alternative embodiments and details, and the features, aspects, and advantages of the present invention will become more apparent from the detailed description set forth below, the drawings and the claims. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIGS. 1A ,  1 B and  1 C are circuit diagrams of output stages according to various embodiments of the present invention. 
         FIG. 2  is a graph showing the relationship for currents I 5  and Iout in the circuits of  FIGS. 1A ,  1 B and  1 C. 
         FIG. 3  is a circuit diagram of an output stage according to another embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Embodiments of the present invention are directed to output stages, which while not limited thereto, are especially useful for driving video loads. In accordance with an embodiment of the present invention, the output stage is designed to drive wideband signals with the ability to provide a high quality output signal substantially all the way to the lower supply rail (e.g., ground). In accordance with an embodiment of the present invention, the output stage of the present invention only requires a single positive power supply (e.g., 3V), consistent with the recent trend toward integrated circuits that only require a single low voltage power supply. In such an embodiment, the lower supply rail is ground, and the output signal can substantially approach ground. Thus, the output stage can be referred to as “ground skimming.” 
     The output stage, according to embodiments of the present invention, can quickly follow a video signal to within a few mV of ground. When the input signal rises back up, the output stage releases from ground quickly with negligible recovery artifacts. 
     While not limited to this use, the output stage of the present invention can be incorporated inside a compound amplifier stage which uses feed-back from the output to improve linearity. 
     In accordance with an embodiment of the present invention, an output stage in accordance with the present invention can replace conventional emitter-followers of an operational amplifier, which are typically biased to either class-AB or class-A. 
     In accordance with embodiments of the present invention, the output stage implements a class-AB emitter-follower function with improved performance. This is accomplished using a unique translinear current controller, which is one of the ways the output stage of the present invention differs from previous implementations which were subject to extreme instabilities, rendering them impractical. Previous attempts to build such a circuit have failed to be practical because they did not use the translinear biasing method of the present invention, rendering them unstable. 
       FIG. 1A  is a circuit diagram of an output stage  102  according to an embodiment of the present invention. In accordance with an embodiment of the present invention, the output stage includes a translinear current controller  110 , an output transistor Q 5  and a current mirror  120 . 
     In accordance with an embodiment of the present invention, the translinear current controller  110  includes bipolar transistors Q 1 , Q 2 , Q 3  and Q 4 , with transistors Q 1 , Q 2  and Q 3  being diode connected. NPN transistor Q 1  and PNP transistor Q 3  form an input leg of the translinear current controller  110 . Similarly, NPN transistor Q 2  and PNP transistor Q 4  form an output leg of the translinear current controller  110 . The base and collector of NPN transistor Q 1  are connected together to a supply voltage rail Vsp (e.g., 3V, 3.5V or 5.0V). Similarly, the base and collector of NPN transistor Q 2  are connected together to the supply voltage rail Vsp. The base and collector of PNP transistor Q 3  are connected together, and the base of PNP transistor Q 3  is connected to the base of PNP transistor Q 4 . In this arrangement, the collector of transistor Q 3  forms a first input (in 1 ) of the translinear current controller  110 , the collector of transistor Q 4  forms the output (out) of the translinear current controller  110 , and the emitters of NPN transistor Q 2  and PNP transistor Q 4  form a second input (in 2 ) of the translinear current controller  110 . 
     The output current of the translinear current controller  110 , which is labeled I 4  (since it is the current at the collector of transistor Q 4 ), is provided to the input of the current mirror  120 . The current mirror  120  has a gain of A, resulting in the current at the output of the current mirror  120  being A*I 4 . The output of the current mirror  120  is connected to the output of the output stage  120 , labeled node (N 1 ). The current mirror  120  can be made of bipolar or MOS devices, with similar results. 
     The base of the output transistor Q 5  forms the input of the output stage  102 . The collector of the output transistor Q 5  is connected to the second input (in 2 ), i.e., node (N 2 ), of the translinear current controller  110 . The emitter of the output transistor Q 5  forms the output node (N 1 ) of the output stage  102 . The output node (N 1 ) will typically be connected to a load that may or may not be AC coupled. If AC coupled, the output stage  102  should draw current from the output load capacitance when the output slews negative, and should push current into the output load capacitance when the output slews positive. More specifically, when a current is pushed into or pulled from the output node (N 1 ), the current through transistor Q 5  should be kept relatively constant so that the output stage functions accurately. Otherwise, if the current through transistor Q 5  becomes too low, the bandwidth of the output stage  102  will die off. 
     The general solution to the circuit of  FIG. 1  is shown below: 
     
       
         
           
             
               
                 
                   
                     
                       Ibias 
                       2 
                     
                     * 
                     
                       ( 
                       
                         
                           Is 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                           * 
                           Is 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           4 
                         
                         
                           Is 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                           * 
                           Is 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                       ) 
                     
                   
                   = 
                   
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           
                             5 
                             2 
                           
                         
                         A 
                       
                       * 
                       
                         ( 
                         
                           1 
                           + 
                           
                             1 
                             A 
                           
                         
                         ) 
                       
                     
                     - 
                     
                       
                         
                           I 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           5 
                           * 
                           Iout 
                         
                         A 
                       
                       * 
                       
                         ( 
                         
                           1 
                           + 
                           
                             2 
                             A 
                           
                         
                         ) 
                       
                     
                     + 
                     
                       
                         Iout 
                         2 
                       
                       
                         A 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   ) 
                 
               
             
           
         
       
     
     where, Is 1 , Is 2 , Is 3  and Is 4  are constants relating to the area and process of transistors Q 1 , Q 2 , Q 3  and Q 4 . 
     The general action of an output sourcing current is to reduce the emitter current of transistor Q 4 . Transistor Q 5  then just sources the output current, and at large output currents transistor Q 4  and the current mirror  120  smoothly approach turn-off. The translinear action of transistors Q 2  and Q 4  provide for this smoothness.  FIG. 2  shows the relationship between the output current Iout and current I 5 . 
     For Iout being a sinking current, transistor Q 5  gradually turns off and stops diverting current from transistor Q 4 . The current mirror  120  sinks more and more output, but transistor Q 5  remains substantially on, controlling the output voltage even though it may be conducting less current than the output of the current mirror  120 . Eventually, a large enough output is sunk that transistor Q 5  is turned off, at which point current I 5 =0, and Iout−, max (the maximum sink current the circuit can provide) is as follows: 
     
       
         
           
             
               
                 
                   
                     Iout 
                     - 
                   
                   , 
                   
                     max 
                     = 
                     
                       A 
                       * 
                       Ibias 
                       * 
                       
                         
                           
                             
                               Is 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                               * 
                               Is 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               4 
                             
                             
                               Is 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               1 
                               * 
                               Is 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   ) 
                 
               
             
           
         
       
     
     An advantage to the circuit of  FIG. 1  is that Iout−, max is not a class-A standing current that creates a large I 5  quiescent, with the relationship of I 5 ,quiescent and Iout−, max shown below:
 
 I out−,max= I 5,quiescent*√{square root over ( A+ 1)}  (Equation 3).
 
     Referring to  FIG. 1A , it can be seen that transistors Q 1  and Q 3  are diode-connected, as mentioned above, and biased with Ibias. If Iout=0, then transistor Q 5  will output a current proportional to Ibias, and a function of the areas of Q 1 -Q 4 . Assuming Iout=0, then the current I 5  will be very close to A*I 4 . Current I 5  acts to diminish current I 4  by diverting current from the emitter of transistor Q 4 , with I 5 ,quiescent being shown below: 
     
       
         
           
             
               
                 
                   
                     I 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     5 
                   
                   , 
                   
                     quiescent 
                     = 
                     
                       Ibias 
                       * 
                       
                         
                           
                             ( 
                             
                               
                                 ( 
                                 
                                   
                                     Is 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     2 
                                     * 
                                     Is 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     4 
                                   
                                   
                                     Is 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     1 
                                     * 
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                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     3 
                                   
                                 
                                 ) 
                               
                               * 
                               
                                 
                                   A 
                                   2 
                                 
                                 
                                   1 
                                   + 
                                   A 
                                 
                               
                             
                             ) 
                           
                         
                         . 
                       
                     
                   
                 
               
               
                 
                   ( 
                   
                     Equation 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     4 
                   
                   ) 
                 
               
             
           
         
       
     
     In one extreme case, when the output load draws sufficient current, transistor Q 2  turns on as a diode to source the majority of the current. In doing so, the V BE  of transistor Q 2  increases, shutting off transistor Q 4  below it, resulting in the current mirror  120  being turned off. In the opposite extreme case, when the output load is pushing sufficient current into the output stage  102 , the current mirror  120  will absorb this current, shutting off the output transistor Q 5 . In this situation, all the current from transistor Q 2  will flow through the transistor Q 4  to bias the current mirror  120 . 
     This translinear bias arrangement of the translinear current controller  110  allows for smooth transitions between these two extreme states with a good overlap region in which the topside currents (sourcing from the transistor Q 2 ) and the low side currents (sourcing from the current mirror  120 ) simultaneously flow through the output transistor Q 5 . This is by definition a class-AB bias stage, which is useful for low distortion wide band signals. 
     In  FIG. 1A , the base and collector transistor Q 1  are connected together, as is also the case for transistors Q 2  and Q 3 . When connected in this manner, transistors are considered to be diode connected, since they generally function as diodes, with the connected together base and collector forming the anode, and the emitter forming the cathode. 
     Since transistor Q 1  in  FIG. 1A  is acting as a diode, the diode connected NPN transistor Q 1  can be replaced with a diode connected PNP transistor, as shown in  FIG. 1B . Similarly, the diode connected NPN transistor Q 2  of  FIG. 1A  can be replaced with a diode connected PNP transistor, as also shown in  FIG. 1B . Additionally, the diode connected PNP transistor Q 3  of  FIG. 1A  can be replaced with a diode connected NPN transistor, as shown in  FIG. 1B . Any and all such replacements are within the scope of the present invention. 
     Since transistors Q 1 , Q 2  and Q 3  are acting as diodes in  FIGS. 1A and 1B , it is also within the scope of the present invention to replace these transistors with discrete diodes, as shown in  FIG. 1C , or with any other device that is connected to function as a diode. Diode connected transistors, or any other device that functions as a diode, including a discrete diode, is referred to hereafter as a diode device. 
     The current mirror  120  is preferably implemented using CMOS transistors, because CMOS transistors do not saturate like bipolar transistors, CMOS transistors can operate close to zero volts, and CMOS transistors have better recovery time. However, in an alternative embodiment, the current mirror  120  can be implemented using bipolar transistors. 
     In addition to the output stage  102  not being restricted to the exact device types shown, components can be added as desired to increase stability of the circuit. 
     While not limited to such uses, the output stage of the present invention is especially useful for driving low voltage video circuits. 
     In the  FIG. 1A  transistors Q 1 , Q 2  and Q 5  are shown as being bipolar NPN (i.e., N-channel) transistors, and transistors Q 3  and Q 4  are shown as being bipolar PNP (i.e., P-channel) transistors. However, in accordance with alternative embodiments of the present invention, the transistors, current sources, and supply polarities can all be inverted together with no alteration to circuit behavior. More specifically, transistors Q 1 , Q 2  and Q 5  can be PNP transistors, and transistors Q 3  and Q 4  can be NPN transistors. 
     The above described equations would stay the same, even if output transistor Q 5  were replaced with an equivalent MOS device. In further embodiments, all of the transistors Q 1 -Q 5  are replaced with MOS devices, as shown in  FIG. 3 . The output stage  102 ′ shown in  FIG. 3  would function similarly to the output stage  102  of  FIG. 1 , but the equations used to explain the circuits would differ. In still another embodiment, transistors Q 1 -Q 4  can be MOS devices, e.g., as shown in  FIG. 3 , while the output transistor Q 5  is a bipolar device, e.g., as shown in  FIG. 1 . 
     It is also within the scope of the present invention that the metal semiconductor (MES) transistors can be used in place of MOS transistors. 
     As would be appreciated by one of ordinary skill in the art, the transistors that make up the current mirror  110  can be simple uncascoded transistors. It is also possible that the transistors of the current mirror  110  be cascoded to reduce offset errors and power supply variation sensitivity. 
     Exemplary ratios of transistors Q 1 -Q 4  are shown in  FIGS. 1A ,  1 B and  3 . However, other ratios are also within the scope of the present invention, and thus, the ratios shown are not meant to be limiting. 
     The forgoing description is of the preferred embodiments of the present invention. These embodiments have been provided for the purposes of illustration and description, but are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Many modifications and variations will be apparent to a practitioner skilled in the art. Embodiments were chosen and described in order to best describe the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention. Slight modifications and variations are believed to be within the spirit and scope of the present invention. It is intended that the scope of the invention be defined by the following claims and their equivalents.