Patent Publication Number: US-6989579-B2

Title: Adhering layers to metals with dielectric adhesive layers

Description:
TECHNICAL FIELD OF THE INVENTION 
   The present invention is directed, in general, to II–VI and III–V compound semiconductors, and more specifically the adhesion insulating layers to inert metals. 
   BACKGROUND OF THE INVENTION 
   In high speed device applications of the microelectronic and telecommunication industries, II–VI and III–V compound semiconductor materials offer a number of advantages over devices based on silicon semiconductors. For instance, the high electron mobility of III–V substrates, such as Indium Phosphide (InP) or Indium Gallium Arsenide (INGaAs) are advantageous in the high speed active device structures used in optical fiber communication applications that include passive device components, such as metal-insulator-metal capacitors. Also, the wide band gap properties of II–VI and III–V semiconductor materials have high break-down voltages that make them useful in modulator driver applications in optoelectronic devices. 
   The broad application of II–VI and III–V compound semiconductors in such devices has been problematic, however. One of the problems encountered, for example, is poor adhesion between capacitor insulating layers, comprising high dielectric constant materials, such as silicon nitride, and conducting layers comprising inert metals, including noble metals, such as gold, palladium or platinum. In comparison, for silicon-based semiconductors, there is better adhesion between insulating layers, such as silicon oxide, and conducting layers comprising non-inert metals, such as aluminum or copper. On the other hand, noble metals are preferred because such metals do not readily diffuse into II–VI or III–V materials and damage the semiconductor structure. 
   Previously proposed solutions to improve adhesion between insulating layers and conducting layers comprising inert metals are not satisfactory. Consider, for example, a metal-insulator-metal capacitor where the insulator is a dielectric material, such as conventional silicon nitride (Si 3 N 4 ), and the upper and lower metal are inert metals, such as a noble metals. Typically, to promote adhesion of the insulator to the inert metal via metal adhesion, thin layers of metal, such as titanium or chromium are deposited between the insulator and the inert metal layers. The use of titanium as an adhesion promoter is problematic, for example, because titanium is readily oxidizable. Oxidation typically occurs during the transfer of a structure having titanium as the adhesion promoter from the tool for depositing the metal to the tool for depositing the insulating layer. Moreover, titanium oxides are not easily removed, requiring transfer to a separate tool for removal thus interfering with forming capacitors using noble metals. Chromium is not a good candidate adhesion promoter because chromium can act as a n-type dopant that readily diffuses into III–V materials. 
   Silicon nitride is known to adhere well to inert metals when deposited at temperatures of 300° C. or higher. Many II–VI and III–V compound semiconductors, however, must be kept at temperatures of less than 300° C. to avoid dissociation of the integrated substrate comprising, layers grown by Molecular Beam Epitaxy, for example, metal contact layers, and overlaying components. At such low temperatures, however, silicon nitride does not deposit on inert metals in a manner that allows acceptable adhesion. 
   Accordingly, an objective of the invention is a process for adhering inert metals to insulating and semiconductor layers without encountering the above-mentioned difficulties. 
   SUMMARY OF THE INVENTION 
   To address the above-discussed deficiencies, one embodiment of the present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal layer over a semiconductor substrate, depositing an adhesive layer on the metal layer, and depositing a dielectric layer on the adhesive layer. The adhesive layer comprises silicon-rich silicon nitride while the dielectric layer has a lower stoichiometric silicon content than the adhesive layer. 
   Another embodiment of the invention is a semiconductor structure comprising a substrate, a metal layer over the substrate, and the above-described adhesive layer on the metal layer, and the above described dielectric layer on the adhesive layer. 
   Yet another embodiment of the present invention is an integrated circuit. The integrated circuit comprises a bipolar transistor, that includes a collector, a base, and emitter on a semiconductor substrate, and a capacitor located over the semiconductor substrate. The capacitor includes a metal layer located over the semiconductor substrate, the above-described adhesive layer on the metal layer, the above-describe dielectric layer on the adhesive layer, and a second metal layer over the dielectric layer. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The invention is best understood from the following detailed description, when read with the accompanying FIGUREs. Various features may not be drawn to scale and may be arbitrarily increased or reduced for clarity of discussion. Reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: 
       FIGS. 1A–1C  illustrate sectional views of the device covered by the present invention at various stages of manufacture; 
       FIG. 2  schematically illustrates a sectional view of a portion of a semiconductor structure of the present invention; and 
       FIG. 3  schematically illustrates a sectional view of a portion of an integrated circuit incorporating the device of the present invention. 
   

   DETAILED DESCRIPTION 
   The present invention recognizes the advantageous use of a silicon rich adhesive layer to adhere a dielectric layer to a metal layer, in particular an inert metal layer. It has been found that good adhesion can be achieved without raising the temperature above about 300° C. Such low temperature adhesion facilitates the fabrication of the semiconductor device with lower defect rates and longer functional life. 
     FIGS. 1A–1C  illustrate sectional views of a device  105  covered by the present invention at various stages of manufacture. As illustrated in  FIG. 1A , a metal layer  110  is located over a semiconductor substrate  115 . The metal layer  110  may be a noble metal, such as gold, palladium, platinum or combinations thereof. Conventional deposition processes, such as physical vapor or chemical vapor deposition, electron beam evaporation and sputtering, may be used to deposit the metal layer  110  on the substrate  115 . In an advantageous embodiment, the semiconductor substrate  115  comprises Group II and IV or Group III and V elements from the Periodic Table of the Elements. In certain preferred embodiments, for example, the semiconductor substrate  115  may be indium phosphide. In other embodiments however, the substrate  115  could comprise silicon, or combinations of silicon and Group II and IV or Group III and V elements. 
   As shown in  FIG. 1B  an adhesive layer  120  of silicon-rich silicon nitride is deposited on the metal layer  110 . The term silicon-rich silicon nitride as used herein refers to any silicon nitride material having a stoichiometric silicon to nitrogen ratio that is greater than conventional silicon nitride (Si 3 N 4 ), i.e., greater than about 0.75. Preferably, the adhesive layer  120  comprises a dielectric material having a stoichiometric ratio of silicon to nitrogen of greater than about 1, and more preferably between about 1.2 and about 1.5. Conventional deposition processes may also be used to deposit or form the silicon-rich adhesive layer  120  on the metal layer  110 . In an advantageous embodiment a conventional dielectric layer  125  may also be deposited over or on the adhesive layer  120 . In certain preferred embodiments of the device  105 , the adhesive layer  120  is at least about 20 Angstroms thick, and more preferably between about 50 Angstroms and about 200 Angstroms thick. 
   The dielectric material  125  may be any conventional material used in the semiconductor industry as insulator or semiconductor materials. For example, the dielectric material  125  may comprise silica glass, and more preferably conventional silicon nitride (Si 3 N 4 ). The adhesive layer  120  of silicon-rich silicon nitride, however, is most advantageously used to adhere less reactive metals, or alloys of inert metals and reactive metals, to the dielectric layer  125 , such as those previously noted above. However, noble metals, such as palladium or platinum, are more preferred because such metals do not readily diffuse into II–VI or III–V semiconductor substrates  115  and damage the semiconductor structure  105 . 
   The greater adhesive properties afforded by the silicon-rich adhesive layer  120  is combined with the advantages of having an insulating layer, comprising the dielectric layer  125 , that allows the device  105 , when configured as a capacitor, for example, to have a constant capacitance over a range of applied voltage. For example, for a ratio of silicon to nitrogen of between about 1.2 and about 1.5, the capacitance varies by less than about 0.5 percent over an applied voltage range of from about −10 Volts to about +10 Volts. If the ratio of silicon to nitrogen exceeds about 2, then there is increased leakage of carriers out of the silicon-rich layer  120  so as to detrimentally affect the insulating properties of the dielectric layer  125 . Insulating layers that are silicon-rich, for example, do not have a constant capacitance with applied voltage. 
   As noted above, it was discovered that adhesive layers comprising silicon-rich silicon nitride  120  are excellent adhesion promoters, even when deposited at temperatures below about 300° C. It is advantageous therefore to deposit the adhesive layer  120  at a temperature of about 200° C. or less, and more advantageously about 90° C. or less, using otherwise well known deposition techniques. 
   The high silicon content of the adhesive layer  120  may be assessed by any number of techniques well known to those skilled in the art. Secondary ionization mass spectroscopy or Auger spectroscopy, for example, may be used to assess the relative proportions of silicon and nitrogen in the layer  120 . Alternatively, laser ellipsometry may used to non-destructively monitor the silicon and nitrogen content of the layer  120 . Another way to monitor the silicon content of silicon nitride is to measure the refractive index of the silicon nitride sample of interest. Conventional silicon nitride (Si 3 N 4 ), for example, has a refractive index of about 1.9 to about 2.0. The silicon-rich adhesive layer  120  of the present invention, on the other hand, has a higher refractive index. Preferably, the adhesive layer  120  has a refractive index of between about 2.3 to about 2.7 at a wavelength of about 632 nm. 
   Turning now to  FIG. 1C , the method of making the semiconductor device  105  may further include depositing a second metal layer  130 , over the dielectric layer  125 . The second metal layer  130  may comprise the same classes of metals as described for the metal layer  110 . In such embodiments, the metal layers  110  and  130  can serve as electrodes for a capacitor. In another embodiment, however, the device  105  may also include an optional second silicon-rich silicon nitride adhesive layer  135  located between the dielectric layer  125  and the second metal layer  130 . 
   Turning now to  FIG. 2 , there is illustrated an alternative embodiment of the device illustrated in  FIGS. 1A–1C , which is generally designated  200 . As before, the device  200  may include layers  110 ,  120 ,  125 ,  135  and  130  as previously discussed with respect to the device illustrated in  FIGS. 1A–1C , including its alternative embodiments. In addition, however, the device  200  further includes an adhesive layer  240  between the substrate  115  and the metal layer  110 . The adhesive layer  240  may comprise a silicon-rich silicon nitride, similar to that described above. In alternative embodiments, however, the adhesive layer  240  may comprise a metallic adhesive comprising transition metals, such as titanium, palladium, tungsten, chromium or mixtures thereof. As shown, the device  200  can serve as a capacitor in an integrated circuit that includes, for example, a heterojunction bipolar transistor (HBT), a field effect transistor (FET) device or combinations thereof. 
     FIG. 3  illustrates yet another embodiment of the present invention, an integrated circuit  300  that incorporates a device as provided by the present invention and similar to that discussed above. The integrated circuit  300  includes a capacitor  305  located over a semiconductor substrate  315 . In this particular embodiment, the capacitor  305  is located on a conventional dielectric layer  335 . However, it should be understood that the capacitor  305  may be located at other levels within the integrated circuit  300 , if so desired. The capacitor  305  comprises the metal layer  110  or first electrode located on the dielectric layer  335 , the silicon-rich adhesive layer  120 , the dielectric layer  125 , and a second metal layer  130  or second electrode located over the dielectric layer  125 . The bipolar transistor  345  may be conventional in design and in such embodiments includes a collector  350 , a base  355 , and emitter  360  on the semiconductor substrate  315 . Examples of preferred bipolar transistors  345  include single and double hetrojunction bipolar transistors. The bipolar transistor  345  is insulated from upper metal levels by a dielectric layer  365  and the dielectric layer  335 . In addition, interconnections  375 , contact the base contact  380 , collector contact  385  and emitter  360  and interconnection  390  ultimately connects the capacitor  305  to the bipolar transistor  345 . It should also be appreciated that other interconnections, which are not shown, interconnect the bipolar transistor  345  and other active or passive device structures that might exist within the integrated circuit  300  to form an operative integrated circuit  300 . 
   Although the present invention has been described in detail, those of ordinary skill in the art should understand that they can make various changes, substitutions and alterations herein without departing from the scope of the invention.