Patent Publication Number: US-11646731-B2

Title: Semiconductor device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority from Japanese Patent Application No. 2021-000625 filed on Jan. 6, 2021, the content of which is hereby incorporated by reference to this application. 
     BACKGROUND 
     The present disclosure relates to a semiconductor device, for example, is applicable to a semiconductor device having a power-on reset circuit. 
     A power-on reset circuit is a circuit, which outputs a reset signal until a power-supply voltage has a predetermined value, in order that a system configured by another semiconductor device etc. or another circuit incorporated in the same semiconductor device is prevented from malfunctioning at power-on. Such a power-on reset circuit is disclosed in, for example, Japanese patent application laid-open No. 2012-48349 as Patent Document 1 and ELECTRONICS LETTERS 28 May 2015 V0l. 51 No. 11 pp. 856-858 as Non-Patent Document 1. 
     SUMMARY 
     In IoT (Internet of Things) equipment or the like, an improvement of battery life due to a reduction in an operational lower limit voltage of a semiconductor device and a reduction in consumed current are expected to advance in the further. Required is a detecting technique of a lower voltage of the power-on reset circuit that issues the reset signal at the operational lower limit voltage or less of the semiconductor device. 
     Other problems and novel features will be apparent from the description of the present specification and the accompanied drawings. 
     An outline of representative one of the present disclosures will briefly be described as follows. 
     That is, a semiconductor device has a power-on reset circuit including: a first bipolar transistor; a second bipolar transistor configured by connecting a plurality of bipolar transistor in parallel; a detection-voltage adjusting resistance element; a temperature-characteristic adjusting resistance element; a current adjusting resistance element; and a comparator. 
     According to the present disclosure, the power-on reset circuit can be made low voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a block diagram showing a configuration of a semiconductor device according to an embodiment 
         FIG.  2    is a diagram for explaining a problem of a power-on reset circuit. 
         FIG.  3    is a circuit diagram showing an example of a configuration of the power-on reset circuit illustrated in  FIG.  1   . 
         FIG.  4    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  3   . 
         FIG.  5    is a circuit diagram showing another example of the configuration of the power-on reset circuit illustrated in  FIG.  1   . 
         FIG.  6    is a circuit diagram showing a configuration of a power-on reset circuit of a first comparative example. 
         FIG.  7    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  6   . 
         FIG.  8    is a circuit diagram showing a configuration of a power-on reset circuit of a second comparative example. 
         FIG.  9    is a diagram for explaining of an operation of the power-on reset circuit illustrated in  FIG.  8   . 
         FIG.  10    is a view showing a configuration of a power-on reset circuit of a third comparative example. 
         FIG.  11    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  10   . 
         FIG.  12    is a circuit diagram showing a configuration of a power-on reset circuit of a fourth comparative example. 
         FIG.  13    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  12   . 
         FIG.  14    is a circuit diagram showing a configuration of a power-on reset circuit of a fifth comparative example. 
         FIG.  15    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  14   . 
         FIG.  16    is a circuit diagram showing a configuration of a current source used in the power-reset circuit illustrated in  FIG.  14   . 
     
    
    
     DETAILED DESCRIPTION 
     Hereinafter, embodiments will be described with reference to the drawings. However, for the sake of clarification of the explanation, the following description and drawings will be omitted or simplified appropriately. Further, in the following description, the same components are denoted by the same reference numerals and a repetitive explanation thereof will be omitted. 
       FIG.  1    is a block diagram showing a configuration of a semiconductor device according to an embodiment. A semiconductor device  1  is an integrated circuit (IC) in which a power-on reset circuit (POR)  10  and an internal circuit (INC)  30  are included in one semiconductor chip. When the semiconductor device  1  is a microcontroller, the internal circuit  30  includes a central processing unit (CPU), a RAM (Random Access Memory), peripheral circuits, and the like. Incidentally, the power-on reset circuit  10  is not built in the semiconductor device  1 , and may be formed on a semiconductor chip different from the semiconductor device  1 . 
     The power-on reset circuit  10  outputs a reset signal (RS) to the internal circuit  30  according to a value of a power-supply voltage (VCC) when power is turned on and when the power-supply voltage (VCC) temporarily drops and the like. When an external power-supply voltage (VCC) is lower than a predetermined voltage, the reset signal (RS) is at a low level (hereinafter referred to as L level), and when the external power-supply voltage (VCC) becomes higher than the predetermined voltage, the reset signal (RS) is switches to a high level (hereinafter referred to as H level). Here, the L level of the reset signal (RS) is called a reset state. The H level of the reset signal (RS) is called a release of the reset state. A specific example of the power-on reset circuit  10  will be described with reference to  FIG.  3   . 
     Here, in order to further clarify the semiconductor device in the embodiment, a problem on the power-on reset circuit  10  will be described with reference to  FIGS.  2 ,  5  and  7   .  FIG.  2    is a diagram for explaining a problem of a power-on reset circuit.  FIG.  5    is a circuit diagram showing a configuration of a power-on reset circuit of a first comparative example.  FIG.  7    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  6   . 
     As shown in  FIG.  5   , a power-on reset circuit of a first comparative example includes a PMOS (Positive Channel Metal Oxide Semiconductor) transistor  51 , a resistance element  52 , and a buffer circuit  53 . The PMOS transistor  51  and the resistance element  52  are provided in series between a power-supply-voltage (VCC) line and a grounding-voltage (GND) line in this order. A gate of the PMOS transistor  51  receives a grounding voltage (GND). A node between the PMOS transistor  51  and the resistance element  52  is connected to the buffer circuit  53 . The buffer circuit  53  outputs a reset signal (RS). 
     When the power-supply voltage (VCC) is 0 (zero) V, an intermediate potential node N 51  is maintained at 0 V. After the power is turned on, a potential of the intermediate potential node N 51  is maintained at 0 V while a gate-source voltage of the PMOS transistor  51  is equal to or lower than a threshold voltage of the transistor. As shown in  FIG.  7   , the reset signal (RS), which is an output of the buffer circuit  53 , is at the L level. This state is the reset state. Thereafter, when the power-supply voltage (VCC) rises to a predetermined voltage and a current driving force of the PMOS transistor  51  becomes larger than a current driving force of the resistance element  52 , a potential of the intermediate potential node N 51  rises. When the potential of the intermediate potential node N 51  exceeds a threshold potential of the buffer circuit  53 , the reset signal (RS) becomes the H level and the reset state is released as shown in  FIG.  7   . Here, the above-mentioned predetermined voltage is referred to as a detection voltage (Vpor). The power-on reset has a detection circuit that detects a detection voltage (Vpor). 
     A battery power supply is discharged, and the power-supply voltage (VCC) drops with the passage of time. As a voltage of the semiconductor device  1  drops, an operational lower limit voltage (VCCmin) drops as shown by an arrow (C) of  FIG.  2   , so that a battery life is improved and an operational time of the semiconductor device  1  is extended as shown by an arrow (D) of  FIG.  2   . 
     As Shown by (A) of  FIG.  2   , when the operational lower limit voltage (VCCmin) is VCC 1 , the power-on reset circuit  10  needs to detect the detection voltage (Vpor) at a voltage lower than that of VCC 1 . That is, the power-on reset circuit  10  needs to operate in a range from VCC 1  of the power-supply voltage to VCC 3  thereof. 
     By making the semiconductor device  1  the lower voltage, as shown in (B) of  FIG.  2   , the power-on reset circuit  10  needs to detect the detection voltage (Vpor) at a voltage lower than the lower voltage (VCC 2 ). If the detection voltage (Vpor) cannot be lowered, the reset signal (RS) cannot be released as shown by a broken line in  FIG.  7   . That is, the power-on reset circuit  10  needs to operate in a range from VCC 2  of the power-supply voltage to VCC 3  thereof. 
     Further, detection variations also need to be reduced as the detection voltage drops. Furthermore, in a battery-powered semiconductor device, a consumed current also needs to be reduced. 
     Next, a power-on reset circuit of a second comparative example in which the detection variations of the detection voltage are reduced lower than those of the first comparative example will be described with reference to  FIGS.  8  and  9   .  FIG.  8    is a circuit diagram showing a configuration of a power-on reset circuit of a second comparative example.  FIG.  9    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  8   . 
     As shown in  FIG.  8   , in a power-on reset circuit of a second comparative example, a detection circuit  62  for adjusting a detection voltage and a constant-current generating circuit  63  are added to the power-on reset circuit of the first comparative example. The detection circuit  62  includes PMOS transistors  54 ,  55  and an NMOS (Negative Channel Metal Oxide Semiconductor) transistor  56 . The PMOS transistors  54 ,  55  and the NMOS transistors  56  are connected in series between a power-supply-voltage (VCC) line and a grounding-voltage (VSS) line. Gates of the PMOS transistors  54 ,  51  are both connected to a drain of the PMOS transistor  54 . The gate of the PMOS transistor  55  is connected to a drain of the PMOS transistor  55  to form a diode. A gate of the NMOS transistor  56  is connected to an output of the constant-current generating circuit  63 . A current of a level corresponding to an output voltage of the constant-current generating circuit  63  flows through the NMOS transistor  56 . 
     The constant-current generating circuit  63  includes PMOS transistors  57 ,  58 , NMOS transistors  59 ,  60 , and a resistance element  61 . The PMOS transistor  57 , the NMOS transistor  59 , and the resistance element  61  are connected in series between a power-supply-voltage (VCC) line and a grounding-voltage (VSS) line. The PMOS transistor  58  and the NMOS transistor  60  are connected in series between the power-supply-voltage (VCC) line and the grounding-voltage (VSS) line. Gates of the PMOS transistors  57 ,  58  are both connected to a drain of the PMOS transistor  58 . Gates of the NMOS transistors  59 ,  60  are both connected to a drain (output of the constant-current generating circuit  63 ) of the NMOS transistor  59 . A value of a constant current of the constant-current generating circuit  63  is determined by a difference between gate voltages of the NMOS transistors  59 ,  60  and by a resistance value of the resistance element  61 . At the output of the constant-current generating circuit  63 , a bias voltage at a level corresponding to the constant current appears. 
     The resistance of the power-on reset circuits and the PMOS transistors in the first comparative example and the second comparative example have large process variations and temperature dependence. The variations of the power-on reset circuit in the second comparative example are smaller than those of the power-on reset circuit in the first comparative example, but the variations (ΔV) of the detection voltage are still about 600 mV. Therefore, as shown in  FIG.  9   , detection-voltage accuracy of the power-on reset circuits in the first comparative example and the second comparative example is considerably poor Incidentally, power consumption of the power-on reset circuit in the second comparative example is about several hundred nA. 
     Moreover, it is difficult to set the detection voltage to about 1 V or more by using only the resistance element  52  and PMOS transistor  51 . Since the detection voltage is raised by Vth with a diode PMOS (PMOS transistor  55 ), it is difficult to adjust it up to a desired voltage. Therefore, it is difficult to adjust the detection voltages of the power-on reset circuits in the first comparative example and the second comparative example. 
     Next, a power-on reset circuit of a third comparative example in which the detection variations of the detection voltage are reduced lower than those of the second comparative example will be described with reference to  FIGS.  10  and  11   .  FIG.  10    is a view showing a configuration of a power-on reset circuit of a third comparative example.  FIG.  11    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  10   . 
     A power-on reset circuit of a third comparative example includes a first power-on reset circuit (PORA)  64  and a second power-on reset circuit (PORB)  65 . The first power-on reset circuit (PORA)  64  is composed of the power-on reset circuit of the first comparative example or the second comparative example, and a first reset signal (RSA) is outputted therefrom. 
     The second power-on reset circuit (PORB)  65  includes resistance elements  65   a ,  65   b , a comparator (CMP)  65   c  operated by a power-supply voltage (VCC), and a bandgap reference circuit (BGR)  65   d . The resistance elements  65   a ,  65   b  are connected in series between a power-supply node that receives the power-supply voltage (VCC) and a grounding node that receives the grounding voltage (GND). A non-inverting input terminal of the comparator  65   c  is connected to a connection node between the resistance elements  65   a ,  65   b . A reference voltage (VR) outputted from a bandgap reference circuit (BGR)  65   d  is inputted to an inverting input terminal of the comparator  65   c . A second reset signal (RSB) is outputted from an output terminal of the comparator  65   c . When a detection voltage of the connection node exceeds the reference voltage (VR), the second reset signal (RSB) becomes the H level and the reset state is released. 
     Since the first power-on reset circuit (PORA)  64  is composed of the power-on reset circuit in the first comparative example or the second comparative example, as shown in  FIG.  11   , initial-rise variations of the first reset signal (RSA) are great. 
     The second power-on reset circuit (PORB)  65  can suppress initial rise variations of the second reset signal (RSB) by comparing the reference voltage (VR) and the power-supply voltage (VCC). However, as shown in  FIG.  11   , the second power-on reset circuit (PORB)  65  performs an indeterminate output until the bandgap reference circuit (BGR)  65   d  operates. Incidentally, the reference voltage (VR) at a time when the bandgap reference circuit (BGR)  65   d  is stable is about 1 V. 
     Therefore, at an operating voltage or less of the bandgap reference circuit (BGR)  65   d , the second reset signal (RSB) is masked by the first reset signal (RSA) of the first power-on reset circuit (PORA)  64  in a synthesis circuit  66 , and compensates for an output of the L level. 
     In the power-on reset circuit of the third comparative example, the detection of the detection voltage (Vpor) can be set only to a value equal to or more than those of the operational lower limit voltage of the bandgap reference circuit (BGR)  65   d  and the detection variations of the first power-on reset circuit (PORA)  64 . For example, the operational lower limit voltage of the bandgap reference circuit (BGR)  65   d  is about 1.5 V, and the detection variations of the first power-on reset circuit (PORA)  64  are about 0.6 V, so the detection voltage (Vpor) is 2 is detected near 2.1 V. Therefore, it is difficult for the power-on reset circuit in the third comparative example to detect a low voltage of the detection voltage (Vpor). Incidentally, the detection variations of the power-on reset circuit in the third comparative example are about 80 mV, which is improved so as to become higher than the detection-voltage accuracy of the power-on reset circuit in the second comparative example. However, the power consumption of the power-on reset circuit in the third comparative example is about several μA, which is higher than the power consumption of the power-on reset circuit in the second comparative example. 
     Incidentally, the output of the bandgap reference circuit (BGR)  65   d  may be used as a reference voltage for other internal circuits, and the bandgap reference circuit (BGR)  65   d  may have a trimming function. At an initial rise of the power-supply voltage, a trimming value from a non-volatile memory such as a flash memory becomes indeterminate. Since the power-on reset circuit is used at the initial rise of power-on, trimming becomes indeterminate and the detection variations increase. Therefore, measures such as trimming and fixing needs to be taken so as not to be affected from such trimming&#39;s indeterminate state and increase in the variations. 
     Next, a power-on reset circuit of a fourth comparative example for making the detection voltage lower will be described with reference to  FIGS.  12  and  13   .  FIG.  12    is a circuit diagram showing an example of a configuration of a power-on reset circuit of a fourth comparative example.  FIG.  13    is a diagram for explaining an operation of the power-on reset circuit illustrated in  FIG.  12   . 
     A power-on reset circuit of a fourth comparative example includes PNP type bipolar transistors  71 ,  72 , resistance elements  73  to  75 , and a comparator  79  composed of an operational amplifier. The bipolar transistor  72  is formed by connecting N bipolar transistors in parallel. Resistance values of the resistance elements  73 ,  75  are R 1 , and a resistance value of the resistance element  74  is R 2 . The comparator  79  operates by the power-supply voltage (VCC). First, connection between these components will be described. 
     The bipolar transistor  71  and the resistance element  73  are connected in series between a grounding node N 71  that receives the grounding voltage (VSS) and a power-supply node N 72  that receives the external power-supply voltage (VCC) in this order. A collector and a base of the bipolar transistor  71  are connected to the grounding node N 71 . An emitter of the bipolar transistor  71  is connected to one end of the resistance element  73 , and its connecting points forms a node N 73 . The other end of the resistance element  73  is connected to the power-supply node N 72 . 
     The bipolar transistor  72  and the resistance elements  74 ,  75  are connected in series between the grounding node N 71  and the power-supply node N 72  in this order. A collector and a base of the bipolar transistor  72  are connected to the grounding node N 71 . An emitter of the bipolar transistor  72  is connected to one end of the resistance element  74 , and its connecting point forms a node N 74 . The other end of the resistance element  74  is connected to one end of the resistance element  75 , and its connecting point forms a node N 74 . The other end of the resistance element  75  is connected to the power-supply node N 72 . 
     The inverting input terminal of the comparator  79  is connected to the node N 74 , and the non-inverting input terminal thereof is connected to the node N 73 . It is detected that a voltage level of the output signal is inverted and the power-supply voltage (VCC) becomes a predetermined voltage value (Vpor) when the input voltages of the inverting input terminal and the non-inverting input terminal of the comparator  79  become the same voltage. At this time, a first current (I 1 ) of the resistance elements  74 ,  75  and a second current (I 2 ) of the resistance element  73  become equal to each other. 
     Since the voltage of the node N 73  and the voltage of the node N 74  are equal, V BE1 =I 1 ×R 2 +V BE2  and the first current (I 1 ) is represented by expression (11) shown in  FIG.  13   . Here, V BE1  is a base-emitter voltage of the bipolar transistor  71 . V BE2  is a base-emitter voltage of the bipolar transistor  72 . Further, since the second current (I 2 ) is equal to the first current (I 1 ), the second current (I 2 ) is represented by expression (11) shown in  FIG.  13   . 
     Further, a potential difference (V BE2 −V BE1 ) between the emitters of the bipolar transistor  71  and the bipolar transistor  72  is represented by expression (12) shown in  FIG.  13   . Here, kb represents the Boltzmann constant, T represents absolute temperature, q represents electron charge, N represents the number of parallel connected bipolar transistors  72 , and In represents natural logarithm. 
     The power-supply voltage (VCC) is a voltage that is obtained by adding V BE1  and a voltage generated by the second current (I 2 ) flowing through the resistance element  73 . That is, the detection voltage (Vpor) serving as the power-supply voltage (VCC), in which the comparator  79  reverses, is represented by expression (13) shown in  FIG.  13   . By substituting expression (11) into expression (13) shown in  FIG.  6   , expression (14) shown in  FIG.  13    can be obtained. Here, a term M 11  of expression (14) has a negative temperature characteristic, and a term M 12  has a positive temperature characteristic. Therefore, adding a voltage having the negative temperature characteristic and a voltage having the positive temperature characteristic make it possible to be canceled and be detected with a voltage value having no temperature dependence. 
     However, if resistance is adjusted so as to reduce the temperature dependence, a right side of expression (14) shown in  FIG.  13    becomes almost constant and the detection voltage (Vpor) can be set only near 1.2 V, so that the detection voltage cannot be adjusted. 
     Further, a detection-voltage equation considering an offset effect is expression (15) shown in  FIG.  13   , and when an offset (Vos) occurs in the comparator  79 , the offset becomes R 1 /R 2  times, thereby increasing the detection variations. In order to reduce the temperature dependence, the R 1 /R 2  needs to be set at about 10 times and, as a result, the offset increases times. Therefore, the detection-voltage accuracy deteriorates. The detection variations of the power-on reset circuit in the fourth comparative example are about 130 mV, and the power consumption is about several hundred nA. 
     Next, a power-on reset circuit of a fifth comparative example, in which the detection voltage can be adjusted, will be described with reference to  FIGS.  14  to  16   .  FIG.  14    is a circuit diagram showing a configuration of a power-on reset circuit of a fifth comparative example.  FIG.  15    is a diagram for explaining an operation of the repower-on reset circuit illustrated in  FIG.  14   .  FIG.  16    is a circuit diagram showing a configuration of a current source used in the power-on reset circuit shown in  FIG.  14   . 
     As shown in  FIG.  14   , a power-on reset circuit of a fifth comparative example includes PNP type bipolar transistors  91 ,  92 , resistance elements  93  to  95 , a comparator  99  composed of an operational amplifier, and PMOS transistors  96  to  98 . The bipolar transistor  92  is formed by connecting N bipolar transistors in parallel. Each resistance value of the resistance elements  93 ,  95  is R 1 , and a resistance value of the resistance element  94  is R 2 . The comparator  99  operates by a power-supply voltage (VCC). First, connection between these components will be described. 
     The bipolar transistor  91  and the PMOS transistor  96  are connected in series between a grounding node N 91  that receives the grounding voltage (VSS) and a power-supply node N 92  that receives the external power-supply voltage (VCC) in this order. A collector and a base of the bipolar transistor  91  are connected to the grounding node N 91 . An emitter of the bipolar transistor  91  is connected to a drain of the PMOS transistor  96 , and its connecting point forms a node N 93 . A source of the PMOS transistor  96  is connected to the power-supply node N 92 . One end of the resistance element  93  is connected to the node N 93 , and the other end thereof is connected to the grounding node N 91 . 
     The bipolar transistor  92 , the resistance element  94 , and the PMOS transistor  97  are connected in series between the grounding node N 91  and the power-supply node N 92  in this order. A collector and abase of the bipolar transistor  92  are connected to the grounding node N 91 . An emitter of the bipolar transistor  92  is connected to one end of the resistance element  94 , and its connecting point forms a node N 94 . The other end of the resistance element  94  is connected to a drain of the PMOS transistor  97 , and its connecting point forms a node N 95 . A source of the PMOS transistor  97  is connected to the power-supply node N 92 . One end of the resistance element  95  is connected to the node N 95 , and the other end thereof is connected to the grounding node N 91 . 
     An inverting input terminal of the comparator  99  is connected to the node N 95 , and a non-inverting input terminal is connected to the node N 93 . It is detected that a voltage level of an output signal is inverted and the power-supply voltage (VCC) becomes (reaches) a predetermined voltage value (Vpor) when input voltages of the inverting input terminal and the non-inverting input terminal of the comparator  99  become the same voltage. 
     Since a voltage of the node N 93  and a voltage of the node N 94  are equal, V BE1 =I A ×R 2 +V BE2  and a first current (I A ) is represented by expression (21) shown in  FIG.  15   . Here, V BE1  is a base-emitter voltage of the bipolar transistor  91 . V BE2  is a base-emitter voltage of the bipolar transistor  92 . ΔV BE  is a potential difference (V BE1 −V BE2 ) between the emitters of the bipolar transistor  91  and the bipolar transistor  92 . Here, kb represents the Boltzmann constant, T represents absolute temperature, q represents electron charge, N represents the number of parallel connected bipolar transistors  92 , and ln represents natural logarithm. Further, a second current (I B ) is represented by expression (22) shown in  FIG.  15   . 
     A current flowing through the PMOS transistor  96  is the same as a current flowing through the PMOS transistor  98  as a current source, and is equal to the sum of the first current (I A ) and the second current (I B ). That is, a detection voltage (Vpor), which is the power-supply voltage (VCC) and which the comparator  99  reverses, is represented by expression (23) shown in  FIG.  15   . Here, R 3  is a resistance value defined by expression (26) shown in  FIG.  16   . By substituting expressions (21) and (22) into expression (23) shown in  FIG.  15   , expression (24) shown in  FIG.  15    can be obtained. Here, a term M 21  of expression (24) has a negative temperature characteristic, and a term M 22  has a positive temperature characteristic. Therefore, by adding a voltage having the negative temperature characteristic and a voltage having the positive temperature characteristic, the added voltages are cancelled and can be detected with a voltage value having no temperature dependence. 
     However, a detection-voltage equation considering an offset effect is expression (25) shown in  FIG.  15   , and when an offset (Vos) occurs in the comparator  79 , the offset becomes (R 3 /R 1 )×(R 1 /R 2 ) times to increase detection variations. When the detection voltage is about 2.4 V, R 3 /R 1  needs to be set at about 2 and R 1 /R 2  needs to be set at about 10 times in order to reduce the temperature dependence. As a result, the offset increases at 20 times. Therefore, the detection-voltage accuracy deteriorates. The detection variations of the power-on reset circuit in the fifth comparative example are about 130 mV, and the power consumption is about several μA. 
     Next, a current generating circuit of the power-on reset circuit shown in  FIG.  14    will be described with reference to  FIG.  16   . A current generating circuit includes resistance elements  101  to  103 , a comparator  104  composed of an operational amplifier, and a PMOS transistor  98 . The comparator  104  operates by the power-supply voltage (VCC). 
     The resistance elements  101 ,  102  are connected in series between a grounding node N 91  and a power-supply node N 92  in this order. One end of the resistance element  101  is connected to the grounding node N 91 , the other end thereof is connected to one end of the resistance element  102 , and its connecting point forms a node N 101 . 
     The resistance element  103  and the PMOS transistor  98  are connected in series between the grounding node N 91  and the power-supply node N 92  in this order. One end of the resistance element  103  is connected to the grounding node N 91 , the other end thereof is connected to a drain of the PMOS transistor  98 , and its connecting point forms a node N 102 . A source of the PMOS transistor  98  is connected to the power-supply node N 92 . 
     An inverting input terminal of the comparator  104  is connected to the node N 101 , a non-inverting input terminal thereof is connected to the node N 102 , and an output terminal thereof is connected to a gate of the PMOS transistor  98 . 
     A current (I) generated by the current generating circuit as shown in  FIG.  16    is represented by expression (26) shown in  FIG.  16   . It is difficult to generate a current of 1/R 3  shown in expression (26). That is, since resistor and capacitance are connected and adjusted so as not to oscillate an output, an area is increased and circuit design becomes complicated. In addition, variations in current increase several tens of times as much as variations in detection voltage. In addition, a lower voltage is difficult to detect since an operational lower limit is difficult to reduce. Furthermore, the consumed current is also difficult to reduce. 
     Next, a configuration of a power-on reset circuit  10  of an embodiment will be described with reference to  FIG.  3   . FIG.  3  is a circuit diagram showing an example of a configuration of the power-on reset circuit illustrated in  FIG.  1   . 
     A power-on reset circuit  10  includes NPN type bipolar transistors  11 ,  12 , resistance elements  13  to  18 , a comparator  19  composed of an operational amplifier, and a PMOS transistor  20 . The bipolar transistor  12  as a second bipolar transistor is formed by connecting N bipolar transistors in parallel. The comparator  19  operates by an external power-supply voltage (VCC). First, connection between these components will be described. 
     The resistance elements  13 ,  14 , the bipolar transistor  11  as a first bipolar transistor, and a resistance element  15  are connected between a power-supply node N 2  that receives the external power-supply voltage (VCC) and a grounding node N 1  that receives the grounding voltage (GND) in this order. Here, the grounding node N 1  is also referred to as a first node, and the power-supply node N 2  is also referred to as a second node. One end of the resistance element  13  as a fourth resistance element is connected to the power-supply node N 2 . The other end of the resistance element  13  is connected to one end of the resistance element  14  as a first resistance element, and its connecting point forms a node N 3  as a third node. The other end of the resistance element  14  is connected to a collector of the bipolar transistor  11 , and its connecting point forms a node N 4  as a fourth node. An emitter of the bipolar transistor  11  is connected to one end of the resistance element  15  as a fifth resistance element, and its connecting point forms a node N 6  as a sixth node. A base of the bipolar transistor  11  is connected to the node N 3 . 
     One end of the resistance element  16  as a second resistance element is connected to a base (node N 3 ) of the bipolar transistor  11 , and the other end thereof is connected to the node N 6 . 
     The resistance element  17  as a third resistance element and the bipolar transistor  12  are connected in series between the node N 3  and the, node N 6  in this order. One end of the resistance element  17  is connected to the node N 3 . The other end of the resistance element  17  is connected to a collector of the bipolar transistor  12 , and its connecting point forms a node N 5 . An emitter of the bipolar transistor  12  is connected to the node N 6 . A base of the bipolar transistor  12  is connected to the node N 4 . 
     Here, the resistance elements  14 ,  17  are temperature-characteristic adjusting resistance elements, and its resistance value is R 1 . The resistance element  16  is a current adjusting resistance element, and its resistance value is R 2 . The resistance elements  13  and  15  are detection-voltage adjusting resistance elements, and each of their resistance values is R 3 . 
     An inverting input terminal of the comparator  19  is connected to the node N 5 , a non-inverting input terminal thereof is connected to the node N 4 , and an output terminal thereof is connected to a gate of the PMOS transistor  20 . 
     The resistance element  18  and the PMOS transistor  20  are connected in series between the grounding node N 1  and the power-supply node N 2  in this order. One end of the resistance element  18  is connected to the grounding node N 1 . The other end of the resistance element  18  is connected to a drain of the PMOS transistor  20 , and its connecting point forms an output node N 7 . A source of the PMOS transistor  20  is connected to the power-supply node N 2 . A reset signal (RS) is outputted from the output node N 7 . Here, the resistance element  18  is a resistance element in order to ensure that the reset signal (RS) is outputted at the L level at a time of a lower voltage thereof. 
     When the power-supply voltage (VCC) is 0 V, the output node N 7  is maintained at 0 V. After power-on, a potential of the output node N 7  is maintained at 0 V while a gate-source voltage of the PMOS transistor  20  is equal to or lower than a threshold voltage of the transistor. This state is the reset state. Thereafter, when the power-supply voltage (VCC) rises to a predetermined voltage and an output of the comparator  19  is inverted to the L level, a current driving force of the PMOS transistor  20  becomes larger than a current driving force of the resistance element  16  and a potential of the output node N 7  rises and the reset state is released. 
     An operation of the power-on reset circuit  10  will be described with reference to  FIGS.  3  and  4   .  FIG.  4    is a diagram for explaining an operation of the power-on reset circuit. 
     It is detected that a voltage level of an output signal is inverted and the power-supply voltage (VCC) becomes a detection voltage (Vpor) when input voltages of the inverting input terminal and the non-inverting input terminal of the comparator  19  become the same voltage. At this time, a first current (I 1 ) of the resistance element  14  and a third current (I 3 ) of the resistance element  17  become equal. 
     The resistance element  14  is connected between the bipolar transistor  11  and the base of the bipolar transistor  12 . The first current (I 1 ) is generated in the resistance element  14  by a potential difference (ΔV BE  (=V BE2 −V BE1 )) between the bipolar transistor  11  and the base of the bipolar transistor  12 . Here, V BE1  is a base-emitter voltage of the bipolar transistor  11 . V BE2  is a base-emitter voltage of the bipolar transistor  12 . 
     The first current (I 1 ) is represented by expression (1) shown in  FIG.  4   . Here, ΔV BE  represents each voltage of the resistance elements  14 ,  17 . kb represents the Boltzmann constant, T represents absolute temperature, C represents electron charge, N represents the number of parallel connected bipolar transistors  12 , and In represents natural logarithm. The first current (I 1 ) has a positive temperature characteristic in which a current value increases as temperature rises. 
     The resistance element  16  is connected between the base and the emitter of the bipolar transistor  11 . The second current (I 2 ) is generated in the resistance element  16  by a base-emitter voltage (V BE1 ). The second current (I 2 ) is represented by expression (2) shown in  FIG.  4   . The second current (I 2 ) has a negative temperature characteristic in which a current value decreases as temperature rises. 
     The resistance element  15  is connected to the grounding node N 1 , and the resistance element  13  is connected to the node N 2 . The power-supply voltage (VCC) becomes a voltage obtained by adding V BE1  and a voltage that is generated by the total current of the first current (I 1 ), the second current (I 2 ), and the third current (I 3 ) flowing through the resistance elements  13 ,  15 . 
     That is, the detection voltage (Vpor), which is the power-supply voltage (VCC) and which the comparator  19  reverses, is represented by expression (3) shown in  FIG.  4   . By substituting expressions (1) and (2) into expression (3) shown in  FIG.  4   , expression (4) shown in  FIG.  4    can be obtained. Here, a term M 1  of expression (4) has a negative temperature characteristic, and a term M 2  has a positive temperature characteristic. Therefore, by adding a voltage having a negative temperature characteristic and a voltage having a positive temperature characteristic, the added voltages are cancelled and can be detected with a voltage value having no temperature dependence. 
     Further, for example, it is assumed that the sum of the term M 1  and the term M 2  in expression (4) is 1.2 V, the resistance values (R 3 ) of the resistance elements  13 ,  15  are adjusted to become a detection voltage obtained by multiplying 1.2 V by (2R 3 /R 2 +1). If the detection voltage has 1.2 V or more, it can be adjusted to a desired value. 
     Furthermore, even if an offset (Vos) occurs in the comparator  19 , such an operation is performed as to be cancelled as described below and the variations in the detection voltage is suppressed. 
     When the current (I 3 ) decreases due to the offset (Vos), the base-emitter voltage (V BE2 ) of the bipolar transistor  12  drops. Consequently, the voltage (ΔV BE ) of the resistance element  14  increases, and the first current (I 1 ) increases. Therefore, such an operation is performed that the total current (I 1 +I 2 +I 3 ) does not change. Since the resistance elements  13 ,  15  perform the detection only with substantially the same current value, the detection variations are small. 
     A detection-voltage equation in consideration of the offset effect is expression (5) shown in  FIG.  4   , thereby being able to suppress its fluctuation by “ln (N)” represented in “(1/ln (N)−1) Vos” of an item M 6  of expression (5). 
     For example, when the detection voltage is about 2.4 V, “(2R 3 /R 2 +1)” of an item M 3  in expression (5) is about 2. In order to reduce the temperature dependence, “(4R 3 /R 1  (2R 3 /R 2 +1))” of the term M 4  in expression (5) needs to be made about 10, so that the “2R 3 /R 1 ” of the term M 5  in expression (5) becomes about 10. Since N, which is the number of parallel connected bipolar transistors  12 , is approximately 4 to 8, “(1/ln (N)−1)” of the item M 6  in expression (5) becomes 0.3 to 0.5, so that the detection variations increase by about 3 to 5 times of Vos. However, these detection variations can be made smaller 10 times than those of the fourth comparative example and 20 times than those of the fifth comparative example. Incidentally, the detection variations of the power-on reset circuit  10  is about 80 mV. 
     The power consumption of the power-on reset circuit  10  is about several hundred nA, which can be made smaller than about several μA of those in the third comparative example and the fifth comparative example. Further, the power-on reset circuit  10  does not require the reference-voltage generating circuit of the third comparative example, and does not require trimming control. Using the power-on reset circuit  10  makes it possible to lower an operation guaranteed voltage of the semiconductor device and to improve the battery life thereof. 
     Another configuration of the power-on reset circuit  10  will be described with reference to  FIG.  5   .  FIG.  5    is a circuit diagram showing another example of the configuration of the power-on reset circuit illustrated in  FIG.  1   . 
     As shown in  FIG.  5   , the power-on reset circuit  10  may not have the resistance element  15  connected between the grounding node N 1  and the node N 6  shown in  FIG.  3   . Further, the power-on reset circuit  10  may not have the resistance element  13  connected between the power-supply node N 2  and the node N 3  shown in  FIG.  3   . 
     The disclosure made by the present disclosers has been specifically described above based on the embodiment. The present disclosure is not limited to the above embodiment and, needless to say, can be variously modified or changed.