Patent Publication Number: US-6662332-B1

Title: Interleaver for burst error correction

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     The present application claims priority of U.S. Provisional Application No. 60/215,945 titled Self-Synchronizing Interleaver for Burst Error Correction, filed Jul. 5, 2000. 
    
    
     STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT 
     N/A 
     BACKGROUND OF THE INVENTION 
     The present invention relates to high-speed data communications techniques. More particularly, the present invention pertains to a method and apparatus for interleaving and de-correlating data transmitted over a serial data channel so that a burst error within the channel of less than or equal to a specified number of bits can be detected and/or corrected. 
     High-speed data transmission often occurs on band-limited channels such as multi-mode fiber and backplane links. It is well understood that high-speed transmissions over band-limited links can cause high levels of Inter-Symbol Interference (ISI). In particular, lasers, amplifiers and other components in the data path can limit the analog bandwidth and compound the problems associated with ISI. Band limiting is known to produce a correlation between errors that leads to a localized group of errors that are generally known as burst errors. A burst error is generally defined as two or more bits in error that occur in close proximity to each other. A burst error can contain a run of good bits that are less than, or equal to, the burst window. 
     High-speed data transmissions are also subject to transmit jitter, near-end crosstalk (NEXT) and far-end crosstalk (FEXT) interference and baseline wander effects that are statistically non-Guassian. These noise and interference sources result in a higher probability of burst errors than in a channel with just white noise. 
     Coding systems that use error correction can be defeated by the presence of burst errors in a channel. Interleaving is one way of dealing with such errors without the added complexity of multiple-bit error correction codes that are longer than the burst length. Interleaving “whitens” the noise in the channel allowing error correction to achieve coding gain closer to the theoretical limits in white noise. More specifically, interleaving reorders the bits prior to transmission so that a burst error in the channel appears as a series of single bit errors after the receiver applies the reverse interleave function to the incoming data stream. 
     Interleaving, however, typically requires a new level of synchronization at the receiver to determine the interleave sequence within the received data stream. 
     It would therefore be desirable to provide an interleave coding and decoding technique that makes burst errors appear as a series of single-bit errors while additionally being self synchronizing when combined with standard frame alignment logic. 
     BRIEF SUMMARY OF THE INVENTION 
     A method and apparatus are disclosed for serially transmitting cells over a data link so that any burst error less than a predetermined size within a single channel is detectable and/or correctable. In a preferred embodiment, transmit interleave logic is provided that maps the bits of an input word into predefined bit locations of a plurality of data words to form a plurality of interleaved data words. The interleaved data words are transmitted over a serial data channel. Receive logic is provided that obtains word alignment on the received words and de-interleaves the received words to obtain the original data words input to the transmit logic. By interleaving the bits of a received data word over a plurality of data words prior to transmission over the serial channel, burst errors of n bits or less occurring in a single channel result in n or less single-bit errors in the plurality of data words. 
     Other features, aspects and advantages of the presently disclosed invention will be apparent from the Detailed Description of the Invention that follows. 
    
    
     BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
     The invention will be more fully understood by reference to the following detailed description of the invention in conjunction with the drawing of which: 
     FIG. 1 is a block diagram illustrating a bi-directional system operative to perform burst interleaving in accordance with the present invention. 
     FIG. 2 is a more detailed block diagram of the data path through the transmit logic and serializer depicted in FIG. 1; 
     FIG. 3 is a block diagram illustrating exemplary logic for the scrambler depicted in FIG. 2; 
     FIG. 4 is a block diagram illustrating burst interleave logic for performing interleaving of a twenty bit word over four interleaved words for transmission over the serial data channel depicted in FIGS. 1 and 2; 
     FIG. 5 a  is a table depicting twenty-bit data words received at the input to the burst interleave logic depicted in FIG. 4; 
     FIG. 5 b  is a table depicting interleaving of received data words by the interleave logic of FIG. 4; 
     FIG. 6 is a more detailed block diagram illustrating the de-serializer and receive logic depicted in FIG. 1; 
     FIG. 7 is a more detailed block diagram illustrating the word framer and de-interleaver logic depicted in FIG. 6 for de-interleaving words interleaved using the logic depicted in FIG. 4; 
     FIG. 8 is a more detailed block diagram of the de-scrambler logic depicted in FIG. 6; 
     FIG. 9 is another embodiment of burst interleave logic for interleaving each received data word over ten interleaved data words; 
     FIG. 10 a  is a table depicting twenty-bit data words received at the input to the burst interleave logic depicted in FIG. 9; 
     FIG. 10 b  is a table depicting interleaving of received data words by the interleave logic of FIG. 9; 
     FIG. 11 is a more detailed block diagram illustrating the word framer and de-interleaver logic depicted in FIG. 6 for de-interleaving words interleaved using the logic depicted in FIG. 9; 
     FIG. 12 is a block diagram illustrating a four channel physical coding sublayer that utilizes burst interleave and de-interleave logic to decorrelate data temporally over the respective serial data channels; 
     FIG. 13 is a more detailed block diagram illustrating the interfaces for the physical coding sublayer logic and the serializers/de-serializers depicted in FIG. 12; 
     FIG. 14 is a more detailed block diagram of the physical coding sublayer logic depicted in FIG. 12; 
     FIG. 15 is an illustrative data structure illustrating an exemplary organization for data transmitted over the four serial data channels depicted in FIG. 12; 
     FIG. 16 is a more detailed block diagram depicting exemplary parity and control ECC encoder logic of FIG. 14; 
     FIG. 17 is a more detailed block diagram depicting word framing logic, inter-channel alignment logic, descrambler logic, de-interleaving and data ECC decoder logic employed within the receive logic of the physical coding sublayer logic; 
     FIG. 18 is a more detailed block diagram depicting exemplary inter-channel alignment logic of FIG. 17; 
     FIG. 19 is a block diagram illustrating control error correction code (ECC) logic depicted in FIG. 17; 
     FIGS. 20 a  and  20   b  are a flow diagram illustrating control correction code decoder operation; 
     FIG. 21 is a block diagram illustrating the data error correction code decoder logic employed within the receive portion of the physical coding sublayer logic; 
     FIGS. 22 a  and  2   b  are a flow diagram depicting an exemplary method of operation of the data ECC decoder within the receive portion of the physical coding sublayer logic; and 
     FIG. 23 is a block diagram of logic for introducing predetermined bit delays into respective serial channels. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     U.S. Provisional Patent Application No. 60/215,945, titled Self-Synchronizing Interleaver for Burst Error Correction and filed Jul. 5, 2000 is hereby incorporated by reference. 
     System Configuration 
     A system operative in accordance with the present invention and employing the presently disclosed interleaving and de-interleaving logic is depicted in FIG.  1 . Referring to FIG. 1, the system includes physical coding logic  10  that is coupled to first serializer/de-serializer (SERDES) logic  12  via parallel buses  22   a  and  22   b  as shown. The physical coding logic  10  includes transmit logic  14  and receive logic  16 . The SERDES logic  12  includes a serializer  18  that is operative to convert a parallel data word into a serial data stream and a de-serializer  20  that is operative to convert a serial data stream into a parallel data word. 
     Within a given data channel, transmit logic  14  receives a series of data words  15 . In a preferred embodiment, an error correction code (ECC) is generated from one or more received data word(s) and the ECC is concatenated with the data word(s) from which the ECC was generated to form an extended data word. The extended data word is scrambled to de-correlate the data. A framing signal that is employed within receive logic  16  of physical coding logic  10  to achieve word framing following transmission over a serial data channel is generated and appended to the scrambled data to form an extended cipher data word. Transmit logic  14  interleaves the data received in each of the extended cipher data words over a plurality of data words as described in greater detail below to allow detection and/or correction of burst errors up to a predetermined length. 
     A serial channel may be considered as having a transmit side upstream of the serial data channel  24  and a receive side downstream of the serial data channel  24 . On the transmit side of the serial data channel  24 , the output from transmit logic  14  is coupled to the input of serializer  18  via the parallel data bus  22   a . The output of the serializer  18  is coupled to the serial data channel  24  and the input of a de-serializer  20  of another SERDES logic  12  device receives a serial data stream from the serial data channel  24 . The de-serializer  20  converts the received serial data stream into parallel words that are coupled to receive logic  16  via a parallel bus  22   b . Receive logic  16  performs word framing on the received data stream. Additionally, receive logic  16  performs de-scrambling of the received cipher data words and de-interleaving of the received extended data words. As a result of the use of the presently described interleaving technique, burst errors of n bits or less in length appear as single bit errors in the original data words recovered following the de-interleaving process. Based upon the error detection and/or correction code employed, single bit errors in the de-interleaved data words can either be detected or corrected. Furthermore, greater levels of error detection and/or correction may be obtained based on the error detection code (EDC) or ECC employed. 
     Transmit Logic 
     Exemplary transmit logic  14  is illustrated in greater detail in FIG.  2 . In the exemplary transmit logic  14  13 bit parallel data words are received at the input of transmit logic  14 . A 5 bit ECC is generated in error code generating logic  30 . In a preferred embodiment, the 5 bit ECC selected may be employed to correct single bit errors in the corresponding data word. The received data word and the ECC are combined to form an 18 bit extended data word and the extended data word is applied to a scrambler  32  that scrambles the input data by exclusive ORing the input data with a pseudo random binary sequence (PRBS). The scrambler  32  provides DC balance, inserts transitions and spreads the signal spectrum across available bandwidth to reduce EMI. In a preferred embodiment, the scrambler  32  comprises a side-stream scrambler. The output from the scrambler  32  is coupled to the input of a framing signal generator  34 . The framing signal generator generates a framing signal that is used by receive logic  16  (FIG. 1) to achieve word alignment following receipt of the serially transmitted data stream over the serial channel  24  (FIG.  1 ). The framing signal may comprise a parity bit, a predetermined number of bits having a specified known value or any other suitable signal that may be used by receive logic  16  to achieve word framing following transmission of the serial data stream over the serial data channel  24 . In the present example, it is assumed that the framing signal comprises a single parity bit. An idle bit is generated to indicate when the transmitted character comprises an idle character. The idle bit is used to reacquire the seed for use by the descrambler  92  (FIG.  6 ). The framing signal and the idle bit are appended to the cipher data word to form an extended cipher data word, which in the illustrated embodiment comprises a twenty-bit wide extended cipher data word. 
     The extended cipher data word is coupled to the input of burst interleave logic  36 . The burst interleave logic  36  interleaves the data contained within the extended cipher data word over a plurality of data words to form a plurality of interleaved data words of width equal to the extended cipher data word. The interleaved data words are serialized by the serializer  18  and transmitted over the serial data channel  24 . 
     Side Stream Scrambler 
     An exemplary side-stream scambler implementation is depicted in FIG.  3 . The side stream scambler includes a three to one MUX  50  that receives a Load Seed signal  52 . The Load Seed signal  52  enables the loading of 15 bits of seed data from a seed register  54 . Additionally, the three to one MUX  50  is coupled to a PRBS register  56  via a MUX output bus. The outputs of the PRBS register  56  are coupled to the inputs of primary feedback logic  58  and secondary feedback logic  60  and the outputs of the primary and secondary feedback logic  58  and  60  are fed back to the inputs of the three to one MUX  50 . The primary or secondary feedback logic outputs are selected as the operative inputs to the three to one MUX  50  in response to a primary/secondary selection control signal  62 . Exclusive OR (XOR) logic  64  receives as inputs, over the TXP bus, the extended data word comprising the received data word(s) and the ECC generated by the Error Code Logic  30  (FIG.  2 ). Additionally, XOR logic  64  receives as inputs the PRBS register  56  outputs denoted as X&lt;m: 0 &gt;. The signals on TXP&lt;m: 0 &gt; and X&lt;m: 0 &gt; are exclusive ORed by XOR logic  64  to produce cipher data TXCI&lt;m: 0 &gt; at the scrambler outputs TXCI&lt;m: 0 &gt;. 
     The two generator polynomials used for the primary and secondary PRBS 15  sequences are: 
     
       
           G   P ( x )=1 +x   14   +x   15   (Primary generator) 
       
     
     
       
           G   S ( x )=1 +x   11   +x   15   (Secondary generator) 
       
     
     These sequences have known linear feedback shift register (LFSR) implementations. To achieve high speed, the physical coding logic  10  employs an 18 bit parallel implementation for the side scramblers  32 . The 18 bit parallelism is obtained by applying 18 levels of recursion to the LFSR equations to produce the bus wide pseudo random binary sequence generator structure illustrated in FIG.  3 . 
     The feedback equations for the primary sequence are shown below. The bit ordering is such that the pseudo random binary sequence will appear on the serial lines in the same order as would be generated by the LFSR approach. 
     XPnext 0 =X 3 +X 4 ; 
     XPnext 1 =X 4 +X 5 ; 
     XPnext 2 =X 5 +X 6 ; 
     XPnext 3 =X 6 +X 7 ; 
     XPnext 4 =X 7 +X 8 ; 
     XPnext 5 =X 8 +X 9 ; 
     XPnext 6 =X 9 +X 10 ; 
     XPnext 7 =X 10 +X 11 ; 
     XPnext 8 =X 11 +X 12 ; 
     XPnext 9 =X 12 +X 13 ; 
     XPnext 10 =X 13 +X 14 ; 
     XPnext 11 =X 0 +X 1 +X 14 ; 
     XPnext 12 =X 0 +X 2 ; 
     XPnext 13 =X 1 +X 3 ; 
     XPnext 14 =X 2 +X 4 ; 
     XPnext 15 =X 3 +X 5 ; 
     XPnext 16 =X 4 +X 6 ; 
     XPnext 17 =X 5 +X 7 ; 
     While a single channel is illustrated in FIG. 1 for transmitting data in respective opposing directions, as discussed below, data may be transmitted in a particular direction over plural serial channels in which case plural transmitters and plural side scramblers  32  may be employed. In such event, it may be desirable to offset the seeds for the respective side scramblers in time to de-correlate the data forwarded over the respective channels. The primary seeds to start up a four-channel transmitter are: 
     S A =0x7FFF (M(0)) 
     S B =0x7F00 (M(½)) 
     S C =0x70FF (M(¼)) 
     S D =0x780F (M(¾)) 
     where M(x) denotes the relative starting position in the maximum length sequence. If a single channel is employed, the value S A  may be used for the initial primary seed value. 
     Similarly, the feedback equations for the secondary sequence are shown below. 
     XSnext 0 =X 3 +X 7 ; 
     XSnext 1 =X 4 +X 8 ; 
     XSnext 2 =X 5 +X 9 ; 
     XSnext 3 =X 6 +X 10 ; 
     XSnext 4 =X 7 +X 11 ; 
     XSnext 5 =X 8 +X 12 ; 
     XSnext 6 =X 9 +X 13 ; 
     XSnext 7 =X 10 +X 14 ; 
     XSnext 8 =X 0 +X 4 +X 11 ; 
     XSnext 9 =X 1 +X 5 +X 12 ; 
     XSnext 10 =X 2 +X 6 +X 13 ; 
     XSnext 11 =X 3 +X 7 +X 14 ; 
     XSnext 12 =X 0 +X 8 ; 
     XSnext 13 =X 1 +X 9 ; 
     XSnext 14 =X 2 +X 10 ; 
     XSnext 15 =X 3 +X 11 ; 
     XSnext 16 =X 4 +X 12 ; 
     XSnext 17 =X 5 +X 13 ; 
     The secondary seeds to start a four-channel transmitter up are: 
     S A =0x7FFF (M(0)) 
     S B =0x00CC (M(½)) 
     S C =0x0AAA (M(¼)) 
     S D =0x0008 (M(¾)) 
     where M(x) denotes the relative starting position in the maximum length sequence. If a single channel transmitter is employed, the value S A  may be used for the initial secondary seed value. 
     The outputs of the side scrambler provides scrambled or cipher data that is identified as TXCIa&lt;m: 0 &gt;. In the illustrated embodiment, the cipher data word comprises an 18 bit word and m=18. The side scrambler output bus is coupled to the inputs of the Framing Signal Generator  34  (FIG.  2 ). 
     Framing Signal Generator 
     A indicated above, the Framing Signal Generator  34  appends the framing signal to the cipher data word TXCI&lt;m: 0 &gt; to form the extended cipher data word. Although the framing signal may comprise a parity signal, a fixed bit, a series of known bits, or any other suitable signal that may be employed for detecting proper word framing, for purposes of the present discussion, it is assumed that the framing signal comprises a single parity bit. The extended cipher data word is coupled from the output of the framing signal generator  34  to the input of the burst interleave logic  36 . 
     Burst  4  Interleave Logic 
     Exemplary burst interleave logic  36  is depicted in greater detail in FIG.  4 . As will be apparent, the burst interleave logic  36  may interleave the extended cipher data words over a desired number of data words to accommodate burst errors of a predetermined length. Interleaving the extended cipher data over a greater number of data words permits burst errors of a greater length to be detected and/or corrected. The burst interleave logic  36  depicted in FIG. 4 is referred to herein as burst  4  interleave logic to denote that the bits of the extended cipher data word are interleaved over four data words so as to permit detection and/or correction of up to a four bit burst error in a channel. More specifically, the bits of the extended cipher data word are scattered across four interleaved data words in a predetermined manner. As a result of this interleaving, each bit of the original extended cipher data word is separated by a minimum distance of four from any other bit in the same word on the serial data channel  24 . A 4-bit burst error in the serial data channel will appear as four single bit errors in four data words following de-interleaving of the received data. Accordingly, based upon the error detection or correction code employed, the single bit errors in the respective data words may be detected or corrected, as applicable. 
     Referring to FIG. 4, the exemplary burst  4  interleave logic  36  includes registers R 0   70 , R- 1   72 , R- 2   74 , R- 3   76  and RIX  78 . Each extended cipher data word (TXCIE&lt; 19 : 0 &gt;) received at the burst interleave logic  36  is stored in the register R 0   70 . The registers R 0   70 , R- 1   72 , R- 2   74 , R- 3   76  and RIX  78  are commonly clocked. Each word appearing at the output of the register RIX  78  thus includes bits from the data word last received at register R 0   70  and the three previously received data words. 
     More specifically, the output bits from the register R 0   70  are divided such that bits R 0 &lt; 4 : 0 &gt; are coupled to selected inputs of register RIX  78  and bits R 0 &lt; 19 : 5 &gt; are coupled to register R- 1   72 . Additionally, the output bits from the register R- 1   72  are coupled to register R- 2   74  and selected input bits of register RIX  78 . More specifically, in the burst  4  interleave logic, bits R- 1 &lt; 9 : 5 &gt; are coupled to selected bits of the input of register RIX  78  and bits of R- 1   72  designated as R- 1 &lt; 19 : 10 &gt; are coupled to the inputs of register R- 2   74 . Furthermore, output bits of register R- 2   74  designated R- 2 &lt; 14 : 10 &gt; are coupled to selected inputs of the register RIX  78  and output bits of R- 2   74  designated R- 2 &lt; 19 : 15 &gt; are coupled to the inputs of register R- 3   56 . Finally, the output bits of register R- 3   76  designated R- 3 &lt; 19 : 15 &gt; are coupled to selected inputs of register RIX  78 . 
     The interleave equation for the burst  4  interleave logic is set forth below: 
     RIX&lt; 19 : 0 &gt;=R- 3 &lt; 19 &gt;, R- 2 &lt; 14 &gt;, R- 1 &lt; 9 &gt;, R&lt; 4 &gt;, R- 3 &lt; 18 &gt;, R- 2 &lt; 13 &gt;, R- 1 &lt; 8 &gt;, R&lt; 3 &gt;, R- 3 &lt; 17 &gt;, R- 2 &lt; 12 &gt;, R- 1 &lt; 7 &gt;, R&lt; 2 &gt;, R- 3 &lt; 16 &gt;, R- 2 &lt; 11 &gt;, R- 1 &lt; 6 &gt;, R&lt; 1 &gt;, R- 3 &lt; 15 &gt;, R- 2 &lt; 10 &gt;, R- 1 &lt; 5 &gt;, R&lt; 0 &gt; 
     The register designated R 0   70  contains the bits in the last received word. Bits designated R- 1 &lt;x:y&gt; are bits received in the word received just prior to the word currently in register R 0   70 . Bits designated R- 2 &lt;x:y&gt; are bits received in the word received two words before the word currently in the register R 0   70 . Finally, bits designated R- 3 &lt;x:y&gt; are bits received in the word received three words before the word currently in the register R 0   70 . 
     The effect of the burst  4  interleave logic  36  is apparent from the interleave functions depicted in FIGS. 5 a  and  5   b . FIG. 5 a  depicts 20-bit input words in columns W- 3  through W 7 . W 7  corresponds to the most recently received word. FIG. 5 a  shows the resulting output words appearing at the output of the RIX register  78  (FIG. 4) following application of the burst  4  interleave function. The contents of the rows designated B 0  through B 19  in FIGS. 5 a  and  5   b  correspond to the data-bits within the input and output words, respectively. 
     In FIG. 5 b , the column designated W 0  represents the first of the illustrated interleaved data words transmitted over the serial data channel  24  (FIGS. 1,  2 ) and the column designated W 7  represents the last of the illustrated data words transmitted over the serial data channel  24  (FIGS. 1,  2 ). The input data word W 0  contains data bits d 0 _ 0  through d 0 _ 19  within bit locations B 0 -B 19  (FIG. 5 a ). As seen in FIG. 5 b , the bits of the received input data word are interleaved among a plurality of data words that are output from the burst  4  interleave logic  36 . More specifically, bits d 0 _ 0 , d 0 _ 1 , d 0 _ 2 , d 0 _ 3  and d 0 _ 4  contained in the received data word W 0  (FIG. 5 a ) are transmitted across the serial data channel  24  within bit locations B 0 , B 4 , B 8 , B 12  and B 16  of the output data word W 0  respectively (FIG. 5 b ). Additionally, bits d 0 _ 5 , d 0 _ 6 , d 0 _ 7 , d 0 _ 8  and d 0 _ 9  contained in the received data word W 0  (FIG. 5 a ) are transmitted across the serial data channel  24  within bit locations B 1 , B 5 , B 9 , B 13  and B 17  of the output data word W 1  respectively (FIG. 5 b ). Furthermore, bits d 0 _ 10 , d 0 _ 11 , d 0 _ 12 , d 0 _ 13  and d 0 _ 14  contained in the received data word W 0  (FIG. 5 a ) are transmitted across the serial data channel  24  within bit locations B 2 , B 6 , B 10 , B 14  and B 18  of the output data word W 2  respectively (FIG. 5 b ). Finally, bits d 0 _ 15  d 0 _ 16 , d 0 _ 17 , d 0 _ 18  and d 0 _ 19  contained in the received data word W 0  (FIG. 5 a ) are transmitted across the serial data channel  24  within bit locations B 3 , B 7 , B 11 , B 15  and B 19  of the output data word W 3  respectively (FIG. 5 b ). As apparent from FIGS. 5 a  and  5   b , the bits of the input data words are scattered across four successive output data words. More specifically, the bits of each input data word are separated by a minimum distance of four from any other bits within the same data word within the serial data channel  24  (FIGS. 1,  2 ). Consequently, a burst error of four bits or less on the serial data channel  24  can produce only a single bit error in any given input data word following de-interleaving of the serialized data when utilizing the burst  4  interleaving technique herein described. 
     Serializer 
     Each interleaved data word appearing at the output of the burst  4  interleave logic  36  is coupled to the input of the corresponding serializer  18  (FIG.  2 ). The serializer  18  converts the parallel interleaved data words into a serialized data stream. The serialized data stream is passed from the serializer  18  to a transmit side physical medium dependent interface as known in the art (not shown) to generate the appropriate voltage and drive characteristics for transmission of the serialized data stream over the serial data channel  24  (FIG.  2 ). 
     De-Serializer 
     At the receive end of the link, the serial data channel  24  terminates at a receive side physical medium dependent interface as known in the art (not shown) that converts the received serial data stream into appropriate logic levels for use by the de-serializer  20 . The de-serializer  20  converts the received serial data stream into a series of parallel data words. In the present illustrative example, the de-serializer converts the serialized data stream into a series of 20-bit wide parallel data words. The output of the de-serializer  20  is coupled to receive logic  16  over a parallel data bus  22   b  (FIG.  1 ). 
     Receive Logic 
     Receive logic  16  is depicted with greater particularity in FIG.  6 . Receive logic  16  includes word framer and de-interleaver logic  90 , de-scrambler  92  and error check logic  94 . The output of the de-serializer  20  is coupled to the word framer and de-interleaver logic  90  via parallel data bus  22   b . The output of the word framer and de-interleaver logic  90  is coupled to the de-scrambler  92 . Error check logic  94  is coupled to the output of the de-scrambler  92 . Error check logic  94  provides an indication of an error in a data word or alternatively, generates a syndrome based upon the received data word that may be employed to correct an error in a recovered data word if an error correction code is used. A more detailed block diagram of the word framer and de-interleaver logic  90  is shown in FIG.  7 . 
     Word Framer and De-interleaver Logic 
     Referring to FIG. 7, the word framer and de-interleaver logic  90  includes multiplexer logic  100  that includes twenty 20:1 multiplexers  100 . The multiplexer logic  100  provides at its output, twenty bits selected from 100 bits comprising five consecutive twenty-bit data words received over the serial data channel  24 . More specifically, each two-bit word received from the de-serializer  20  is stored in register R 0   102 . When the next word is loaded from the de-serializer into register R 0   102 , the content of register  102  is loaded into register R- 1   104 , the content of register R- 1   104  is loaded into register R- 2   106 , the content of register R- 2   106  is loaded into register R- 3   108  and the content of register R- 3   108  is loaded into register R- 4   110 . Thus, multiplexer  100  has access to 100 successively received bits at its inputs. The twenty multiplexers are coupled to the outputs of the respective registers R 0   102 , R- 1   104 , R- 2   106 , R- 3   108  and R- 4   110  such that when proper framing is obtained, the bits forming a single data word will appear at the output A&lt; 17 : 0 &gt; with the two framing bits appearing at A&lt; 19 : 18 &gt;. 
     Proper framing is obtained in the following manner. The MUX Control pointer is initialized by the word framing control logic  116  to an initial pointer value and a series of words are sequentially stored in the output register Rout  112 . The last two bits of the twenty-bit word in the illustrative embodiment are assumed to be the framing bits. The value of the framing bits are checked in the framing check logic  114  over a large number of words by comparing the received framing bits to the expected value for those bits to determine if proper word framing exists. Since bits  0 : 17  of the extended cipher data words are scrambled it is highly improbable that proper framing will be found coincidentally. For example, the test may be performed over 128, 256 or any other suitable number of word samples. If word framing is proper, the correct framing bits will be found in each of the word samples. In this event, the word framing control logic  116  asserts a word lock signal to indicate that proper framing has been achieved. If word framing is improper, the specified framing bits will not be detected in each of the word samples. In the event it is determined that word framing is improper, the MUX Control Pointer is adjusted to select another possible one of the 20 possible positions for proper framing and the above-described test is repeated. 
     While the above-described framing signal comprises a single parity bit, it should be appreciated that a single bit of known value may be employed to achieve word framing in the above-described manner. Additionally, as described above, the framing signal may comprise a parity bit having a predetermined parity value and the framing check logic may verify that the received bit corresponding to the assumed parity has the proper parity for each of the predetermined number of word samples. Any other signal that can be used to verify proper word framing may also be employed noting that if multiple bit framing signals are employed, the interleave equations will need to accommodate a greater number of bits for a given width data word. 
     The multiplexer (MUX)  100  serves to de-interleave one data word upon receipt of each new word at register R 0   102  from the serializer. More particularly, the multiplexer  100  selects the relevant output bits from the registers R 0   102 , R- 1   104 , R- 2   106 , R- 3   108  and R- 4   110  and reassembles the original data words in register Rout  112  once proper word framing has been obtained. Thus, register Rout  112  provides, at its output, the cipher data words generated by the scrambler  32  (FIG.  2 ). The output of the register Rout  112  is coupled to the input of de-scrambler  92  (FIG.  6 ). A logic block diagram depicting the de-scrambler  92  is shown in FIG.  8 . 
     De-Scrambler 
     The de-scrambler  92  uses the same side scrambler structure as the transmit logic  14  with the added complexity of having to acquire the current scrambler state. The receive logic  16  can detect when an Idle cell is being transmitted via control state information conveyed over the serial data channel  24 . Idle cells are transmitted frequently during the Inter Packet Gap (IPG) of a normal Ethernet transmission. Presence of Idle cells can be guaranteed by use of the well known Far End Fault protocol given in the Ethernet standard. The Idle state is defined to have 0x0000 in the 16 least significant bits of the data payload in each channel. The idle cells are scrambled in each channel however, if the data field contains zeros then the lower fifteen bits of the data word constitutes the scrambler state (seed). The scrambler seed may thus recovered and loaded into the receiver de-scramblers during idle cell transmission. The sequence can be completely recovered in one idle period because the sequence length is 15 and the complete state is defined in the data payload. 
     A state machine controls the de-scrambler state acquisition and verifies that the scrambler remains in lock during Idle cells. 
     Referring to FIG. 8, scrambler control logic  136  identifies when an idle character is being transmitted. In the illustrated embodiment, the idle bit is employed to indicate that an idle character is being transmitted and such bit is provided as an input to the scrambler control logic  136 . In response to detection of an idle character, an acquire/run signal is conveyed to the 2:1 MUX  134  to acquire the seed for the respective channel. 
     An exemplary side-stream de-scrambler implementation is depicted in FIG. 8. 2:1 MUX  130  has an output bus that is coupled to PRBS register  132 . The output of PRBS register  132  is coupled to one input of 2:1 MUX  134 . Received cipher data from the de-interleaver logic is coupled to the second input of 2:1 MUX  134 . The MUX  134  is controlled by Scrambler Control  136 . The MUX  134  is set to accept cipher data from the de-interleaver during acquisition or set to accept the output of PRBS register  132  during normal receive operation. The output of the MUX  134  is coupled to the inputs of primary feedback logic  138  and secondary feedback logic  140 . The outputs of the primary and secondary feedback logic  138  and  140  are fed back to the inputs of the 2:1 MUX  130 . Either the primary or secondary feedback logic outputs are selected as the operative input to the 2:1 MUX  130  in response to a primary/secondary selection control signal  142 . Exclusive OR logic  144  receives as inputs cipher data from the word framer and de-interleaver logic  90  (FIG. 6) and the PRBS register  132  outputs. The data from the de-interleave logic  90  and the PRBS Register  132  are exclusive ORed by exclusive OR logic  144  to produce plain data RXP&lt; 17 : 0 &gt; at the de-scrambler output; e.g. RXP&lt; 17 : 0 &gt;. 
     The feedback equations for the primary sequence are the same as for the scrambler  32  (FIGS. 2,  3 ) and are shown below. 
     XPnext 0 =X 3 +X 4 ; 
     XPnext 1 =X 4 +X 5 ; 
     XPnext 2 =X 5 +X 6 ; 
     XPnext 3 =X 6 +X 7 ; 
     XPnext 4 =X 7 +X 8 ; 
     XPnext 5 =X 8 +X 9 ; 
     XPnext 6 =X 9 +X 10 ; 
     XPnext 7 =X 10 +X 11 ; 
     XPnext 8 =X 11 +X 12 ; 
     XPnext 9 =X 12 +X 13 ; 
     XPnext 10 =X 13 +X 14 ; 
     XPnext 11 =X 0 +X 1 +X 14 ; 
     XPnext 12 =X 0 +X 2 ; 
     XPnext 13 =X 1 +X 3 ; 
     XPnext 14 =X 2 +X 4 ; 
     XPnext 15 =X 3 +X 5 ; 
     XPnext 16 =X 4 +X 6 ; 
     XPnext 17 =X 5 +X 7 ; 
     Similarly, the feedback equations for the secondary sequence are the same as for the scrambler  32  (FIGS. 2,  3 ) and are shown below. 
     XSnext 0 =X 3 +X 7 ; 
     XSnext 1 =X 4 +X 8 ; 
     XSnext 2 =X 5 +X 9 ; 
     XSnext 3 =X 6 +X 10 ; 
     XSnext 4 =X 7 +X 11 ; 
     XSnext 5 =X 8 +X 12 ; 
     XSnext 6 =X 9 +X 13 ; 
     XSnext 7 =X 10 +X 14 ; 
     XSnext 8 =X 0 +X 4 +X 11 ; 
     XSnext 9 =X 1 +X 5 +X 12 ; 
     XSnext 10 =X 2 +X 6 +X 13 ; 
     XSnext 11 =X 3 +X 7 +X 14 ; 
     XSnext 12 =X 0 +X 8 ; 
     XSnext 13 =X 1 +X 9 ; 
     XSnext 14 =X 2 +X 10 ; 
     XSnext 15  X 3 +X 11 ; 
     XSnext 16 =X 4 +X 12 ; 
     XSnext 17 =X 5 +X 13 ; 
     The output of the de-scrambler appears at the output of the exclusive OR logic  144  and produces plain data that corresponds to the original data words received at the input to the transmit logic  14  (FIGS. 1,  2 ). 
     Error Check Logic 
     The output of de-scrambler  92  includes the payload plus the ECC as plain unscrambled data. Accordingly, the error check logic  94  (FIG. 6) may be employed to generate an ECC syndrome and to determine whether the received ECC matches the generated ECC. If the two codes do not match, the ECC may be employed to correct a single bit error in the received data word. Alternatively, if the Error Check Logic  94  comprises EDC only, in the event a single bit error is identified, an indication of the single bit error can be provided. 
     Thus, utilizing the burst  4  interleave logic  36  and the burst  4  de-interleave logic  90 , burst errors of 4 bits or less in the serial data channel  24  appear as a single bit error in the recovered data words output from the de-scrambler  92 . The single bit errors are detectable or correctable depending upon the error code employed. 
     While a four bit burst error is detectable or correctable using the burst  4  logic described above, in may be desirable to be able to detect or correct burst errors of lengths greater than four bits. Using the techniques hereinabove described, it should be apparent that burst errors or greater length may be detected or corrected by utilizing variations on the above-described burst interleave logic. Exemplary interleave logic and de-interleave logic are illustrated that serve to scatter bits of a received data word over ten (10) interleaved data words. By scattering the bits of a single received word over the ten interleaved data words a burst error up to ten bits in length on the serial data channel appears as a single bit error in the recovered original data words at the output of the de-scrambler  92 . 
     Burst  10  Interleave Logic 
     Another embodiment of burst interleave logic is illustrated in FIG.  9 . The embodiment depicted in FIG. 9 is referred to herein as burst  10  interleave logic. The burst  10  interleave logic interleaves bits of a received data word over ten successive interleaved data words. 
     More specifically, the burst  10  interleave logic receives extended cipher data words from the framing signal generator  34  as described above in connection with the burst  4  interleave logic and stores the received data words, in register R 0   150   a . Ten registers denoted R 0   150   a -R- 9   150   j  are cascaded and commonly clocked. Upon receipt of each successive extended cipher data word, the contents of each register are clocked into the next downstream register and selected bits from each of the registers are coupled to the output register RIX  152 . 
     The transmit equation for the Burst- 10  interleave function is given below. 
     TXx&lt; 19 : 0 &gt;=R- 9 &lt; 19 &gt;, R- 8 &lt; 17 &gt;, R- 7 &lt; 15 &gt;, R- 6 &lt; 13 &gt;, R- 5 &lt; 11 &gt;, R- 4 &lt; 9 &gt;, R- 3 &lt; 7 &gt;, R- 2 &lt; 5 &gt;, R- 1 &lt; 3 &gt;, R 0 &lt; 1 &gt;, R- 9 &lt; 18 &gt;, R- 8 &lt; 16 &gt;, R- 7 &lt; 14 &gt;, R- 6 &lt; 12 &gt;, R- 5 &lt; 10 &gt;, R- 4 &lt; 8 &gt;, R- 3 &lt; 6 &gt;, R- 2 &lt; 4 &gt;, R- 1 &lt; 2 &gt;, R 0 &lt; 0 &gt; 
     The input data words to the burst  10  interleave logic are depicted in FIG. 10 a  and the interleaved burst  10  output words appearing at the RIX register  152  output are depicted in FIG. 10 b . The mapping of the input bits of the received data words depicted in FIG. 10 a  over ten sequential data words as illustrated in FIG. 10 b  defines the burst  10  interleave function. 
     Burst  10  Word Framing and De-Interleave Logic 
     Referring to FIG. 11, exemplary word framing and de-interleaving logic  90  (FIG. 2) is shown that is configured to perform burst  10  de-interleaving. As shown, the burst  10  word framing and de-interleaving logic includes MUX logic  160  comprising 20 20:1 multiplexers that are employed to select particular bits of eleven cascaded registers R 0   162   a  through R- 10   162   k  based upon the value of the MUX control pointer received from the word framing control logic  116 . The operation and use of the register Rout  112 , framing check logic  114  and word framing control logic  116  are as described above with respect to the burst  4  word framing and de-interleave logic. 
     Dynamic Selection Between Burst  4  and Burst  10  Modes 
     It should be apparent that the burst  10  interleave logic introduces greater delays than the burst  4  interleave logic as a consequence of the need to acquire  10  successive data words in the burst  10  implementation before a data word can be output from the word framing and de-interleave logic. In the burst  4  implementation it is only necessary to acquire four successive data words before a data word can be output from the burst  4  word framing and de-interleaving logic. For this reason it may be desirable in certain applications to switch between the two operational modes based upon measurements of the error rate within the serial data channel  24 . If the error rate is below a first predetermined threshold, the system may employ the burst  4  logic and if the error rate is above a second predetermined threshold, the system may employ the burst  10  logic. It should further be appreciated that burst logic for accommodating burst errors of other burst lengths may be employed and the system may dynamically select among the available burst logic based upon the experienced data rates over the respective serial data channel  24  (FIG.  1 ). 
     Given the above description, it should be appreciated that the presently described interleave functions may be employed without use of the scrambler and descrambler functions. For example, for purposes of illustration, the words to be interleaved may comprise a data word of any desired width, an EDC or ECC code of width sufficient to provide the level of error detection or correction desired, and a framing signal, such as described above. The width of the extended words to be interleaved will thus vary based on the specific application and the interleave equations will vary accordingly. Additionally, the interleave functions described above may be employed without EDC or ECC codes in the event such is not required. For the 20 bit interleave equations described above, such would permit an 18 bit data word with the use of a 2 bit framing signal or a 19 bit data word with a single bit framing signal. The two-bit framing signal may have a value of 01 for a data block or 10 for a control block as described in the IEEE 802.3ae 10 gigabit per second Ethernet standard with respect to the  64   b / 66   b  code and as known in the art. 
     Use of Burst Interleave and De-Interleave Logic in a Multi-Channel System 
     It should be further appreciated that the above-described burst interleave and de-interleave logic may be employed in a multi-channel physical coding sub-layer to reduce the susceptability of the system to burst errors that effect the serial data channels. Accordingly, a system is disclosed, along with a physical coding sublayer employed within the system, for communication of data presented in parallel form across multiple serial channels in short haul copper links (such as backplanes and short cable connections), parallel fiber optic links, and wave division multiplexing (WDM) applications (employing fiber optic media). An exemplary system that utilizes the above described burst interleave and de-interleave logic in plural channels is illustrated in FIG.  12 . Referring to FIG. 12, the system includes an optional system interface  1010  that may include a media access control (MAC) interface  1011 , reconciliation logic  1012 , physical coding sublayer logic  1014 , serializers/deserializers  1016  and a physical medium interface  1018 . The system provides for bidirectional signal transmission and includes a transmit path in which data moves from the system interface  1010  downward through the various blocks as depicted in FIG. 12 for transmission over a plurality of serial data channels (denoted as Channels A-D). The system also includes a receive path in which data moves from the serial data channels A-D upward as depicted in FIG.  12  through the respective logical blocks. In the illustrated embodiment, along the transmit path information received over a system bus  1020  is converted to media access format within the system interface  1010  by the Media Access Control logic MAC  1011  in accordance with a known MAC protocol such as the ten gigabit Ethernet protocol. The media access control logic is coupled to the reconciliation logic  1012 . The reconciliation logic  1012  converts the MAC output to a form that generally comports with the well known XGMII interface  1024 . The media access interface may be the same as the XGMII interface in which case the reconciliation logic  1012  may be omitted. The XGMII interface is coupled to the physical coding sublayer logic  1014 . A monitor bit from a monitor channel  1026  is also coupled to the physical coding sublayer logic  1014 . The information conveyed in the monitor channel is independent of the primary data channel. In the illustrative embodiment, the monitor channel is a 156.25 MB/s full duplex channel and can be employed for the transmission of any control information, management information or data. The physical coding sublayer logic  1014  is operative to (a) receive the monitor channel bit from the monitor channel  1026 , (b) generate an error correction code as a function of parallel data received over the XGMII interface  24  and the monitor channel  26  bit, (c) subdivide the received parallel data word, the monitor channel bit and an ECC code generated based upon the monitor bit and the parallel data word into a plurality of lesser width parallel data words, (d) scramble the bits within each of the plurality of lesser width parallel data words using a side-stream scrambler to form cipher data words that are decorrelated in time, (e) generate a control error correction code (CECC) bit that is appended to each of the cipher data words and (f) generate a parity code that is associated with each of the cipher data words and employed in the process of interchannel alignment. The parity bit and the CECC bit together with the scrambled data form an extended width cipher data word. The extended width cipher data words are coupled to serializers within the serializers/deserializers  16  via a serializer/deserializer (SERDES) interface  1028 . The serializers convert the extended width cipher data words from parallel to serial form. The serialized extended width cipher data words are coupled to the physical medium interface  1018  over respective serial links  1030 . The physical medium interface  1018  drives the respective channels in accordance with the required drive characteristics. More specifically, the physical medium interface  1018  provides the appropriate electrical or electro-optical interface to copper or fiber serial data links  1032 , as applicable. By subdividing the wide parallel data word into a plurality of narrower parallel data words, encoding the narrower parallel data words and transmitting data contained in the plurality of narrower encoded parallel data words serially over a corresponding plurality data of serial channels, the number of printed circuit board runs or fiber transmission channels are significantly reduced and an extremely low bit error rate can be achieved. In the case of copper printed circuit board runs, significant space savings on the printed circuit board may be achieved as fewer printed circuit board runs and fewer connector contacts are necessary. 
     Along the receive path, data moves in the reverse direction from the transmit path. In particular, serialized extended width cipher data words received on serial data channels A-D at the physical medium interface  1018  are converted to the logic levels employed by the deserializers  16 . The deserializers  1016  convert the respective serial extended width cipher data words into parallel extended width cipher data words and the parallel extended width cipher data words are coupled to the physical coding sublayer logic  1014  over the SERDES interface  1028 . The physical coding sublayer logic  1014  decodes the cipher data words to recreate the original parallel data word at the XGMII interface  1024 . The parallel data words are presented to the reconciliation logic  1012 , which, in the disclosed embodiment, converts the signaling from that employed on the XGMII interface  1024  to the internal signaling format employed by the MAC. The system interface  1020  supplies data to the system across the system bus. Bus ordering reflects IEEE 802.3 conventions used on the XGMII bus. Within a channel, bit  0  is transmitted on the wire first which is conventional for 1000B-X and Fibre Channel implementations. 
     On the physical coding sublayer side of the reconciliation logic  1012 , the reconciliation logic  1012  interface generally conforms to the XGMII interface  1024 . In particular, for the transmit path, the XGMII interface  1024  (FIG. 13) includes a parallel data bus TXX_D&lt; 63 : 0 &gt;, a control bus TXX_C&lt; 7 : 0 &gt; and a clock TXX_CLK. Along the receive path the XGMII interface includes a parallel data bus RXX_D&lt; 63 : 0 &gt;, a control bus RXX_C&lt; 7 : 0 &gt; and a receive clock RXX_CLK. The signaling on the XGMII bus  1024  is conventional. A 64-bit implementation of the XGMII is used although the bus signaling definition is independent of width. 
     Normal Ethernet packets are transmitted over the XGMII bus. The Ethernet packets may start and stop on any byte boundary and require delimiters, along with a series of control characters used to signal the bus state, such as idle or error. All bus states are transmitted on a per-byte basis and are encoded using the control bit and data byte for that specific byte. 
     Listed below are the byte states used on the XGMII bus. 
     Data Valid (DV): 
     Used to indicate a valid byte within an Ethernet packet. 
     Idle (I): 
     Used to signal the byte is idle during normal inter-packet gap. 
     Start of Packet-SOP (S): 
     Used to signal the beginning of each packet by replacing the first byte of preamble in an Ethernet packet. 
     End of Packet-EOP (T): 
     Used to signal the end of each packet by asserting for one byte immediately after the last byte of an Ethernet packet. 
     Error (E) 
     Used to signal when an error needs to be forced on the TX bus or when an error is detected by the receive PCS. These XGMII byte states have the specific bit encoding shown below in Table 1. 
     
       
         
           
               
             
               
                 TABLE 1 
               
             
            
               
                   
               
               
                 XGMII Control Characters 
               
            
           
           
               
               
               
               
               
            
               
                   
                   
                 Control Bit 
                   
                   
               
               
                   
                 Byte State 
                 (C) 
                 Data Byte (D) 
                 Description 
               
               
                   
                   
               
               
                   
                 DV 
                 0 
                 X 
                 Data Valid 
               
               
                   
                 I 
                 1 
                 b00000111 
                 Idle 
               
               
                   
                 SOP (S) 
                 1 
                 b11111011 
                 Start of Packet 
               
               
                   
                 EOP (T) 
                 1 
                 b11111101 
                 End of Packet 
               
               
                   
                 Error (E) 
                 1 
                 b11111110 
                 Error 
               
               
                   
                   
               
            
           
         
       
     
     The XGMII bus is depicted in FIG.  14 . The XGMII bus contains 64 data bits (D 6  . . . D 0 ) in each direction which are divided into eight groups, each of eight bits, or a byte. Each of the bytes are accompanied by a control bit (C 7  . . . C 0 ). The control bits C 7  . .C 0  make up the TXX_C&lt; 7 : 0 &gt; bus. All the bits are clocked with a source-synchronous clock labeled TXX_CLK. 
     The interface to the physical coding sublayer logic  1014  and the interfaces for the Serializers/Deserializers  1016  are depicted in FIG.  13 . On the reconciliation logic  1012  side of the physical coding sublayer logic  1014 , the interface comprises the XGMII interface. The SERDES interface  1028  (FIG. 12) includes signals in the transmit path and signals in the receive path. In the transmit path, the SERDES interface  1028  includes a parallel data bus TXCED&lt; 9 : 0 &gt; and a transmit clock TXCE_CLK for each of the respective channels. The data buses in the SERDES interface  1028  for the respective channels in the transmit path are identified as TXCEDa&lt; 9 : 0 &gt;, TXCEDb&lt; 9 : 0 &gt;, TXCEDc&lt; 9 : 0 &gt; and TXCEDd&lt; 9 : 0 &gt; for channels A, B, C and D respectively. Transmit clocks TXCEa_CLK, TXCEb_CLK, TXCEc_CLK and TXCEd_CLK are provided for each of the respective channels. 
     In the receive path, the SERDES interface  1028  includes a parallel data bus RXCED&lt; 9 : 0 &gt; and a differential receive clock comprising signals RXCE_CLK+/− for data received over each of the channels A-D. The data buses in the SERDES interface  1028  in the receive path are identified as RXCEDa&lt; 9 : 0 &gt;, RXCEDb&lt; 9 : 0 &gt;, RXCEDc&lt; 9 : 0 &gt; and RXCEDd&lt; 9 : 0 &gt; for channels A, B, C and D respectively. Differential clocks signals RXCEa_CLK+/−, RXCEb_CLK+/−, RXCEc_CLK+/− and RXCEd_CLK+/− are provided for each channel in the receive path. 
     The serializers/deserializers  1016  include a serializer/deserializer for each channel and are identified as SERDES A  1016   a , SERDES B  1016   b , SERDES C  1016   c , and SERDES D  1016   d  respectively. Each SERDES  1016   a  through  1016   d  is coupled to transmit and receive channels as depicted in FIG.  13 . In the disclosed embodiment, the serial data transmitted between the SERDES logic  1016  and the Physical Medium Interface  1018  is communicated in differential form. Accordingly, differential drivers and receivers are employed within the SERDES logic  1016  for communication between the SERDES logic  1016  and the Physical Medium Interface  1018 . For example, SERDES A  1016   a  drives differential signals TXSOa+/− along the transmit path and receives differential signals RXSOa+/− along the receive path. The physical coding sublayer  1014  and the Serializers/Deserializers  1016  also receive a system clock or reference clock as illustrated in FIG.  13 . The system clock is used by the Serializer as a low jitter reference clock and by the Deserializer to check the frequency of the received serial data. 
     Exemplary transmit path logic within the physical coding sublayer logic  1014  is depicted in FIG.  14 . The use of the presently disclosed physical coding sublayer logic  1014  is particularly beneficial in environments where crosstalk and random noise events are present. Redundancy and a high coding strength are built into the coding to provide extremely low bit error rates. Single bit error correction in both the data and control portions of the code are provided. 
     Transmit Path Operation 
     The transmit path logic within the physical coding sublayer logic  1014  comprises several logical functions that collectively provide the desired performance while maintaining a pipelined design required for high-speed transmission and low power. More specifically, the transmit path logic within the physical coding sublayer logic  1014  includes an XGMII controller  1050 , a data error correction code generator  1052 , an interleave function  1053 , transmit side-scrambler logic  1054 , and a Parity and Control ECC encoder  1056 . All these functions are built into a 4×20-bit cell that carries 64 bits of data and framing compatible with Ethernet and cell applications. The 80-bit cell format comprising four 20 bit channels that are output from the physical coding sublayer logic  1014  is illustrated in FIG.  15 . 
     XGMII Transmit Controller 
     The transmit control block  1050  (FIG. 14) is used to encode XGMII transmit state information into a more compressed format used within the physical coding sublayer logic  1014  transfers. A four-state (two bit) control path C&lt; 1 : 0 &gt; is defined along with additional fields in the data payload to transfer the XGMII control state information on 64-bit boundaries. This control coding limits the Inter Packet Gap (IPG) to 8 bytes minimum. The XGMII Transmit Controller  1050  also generates transmit error signals (not shown) in response to XGMII Errors that are signaled across the link and appear as receive errors at the receive PCS. Transmit Error coding is not required per byte (as defined by XGMII) and needs only to be transmitted on a per-frame basis. Transmit Error (TX_ER) is defined as any XGMII Error (E) which occurs within a packet. 
     The XGMII control information received on the XGMII bus TXX C&lt; 7 : 0 &gt; is translated into 4 basic control states. 
     
       
         
           
               
               
               
             
               
                   
                   
               
             
            
               
                   
                 Idle 
                 No data to be transmitted 
               
               
                   
                 Data Valid all 
                 64 bits of data to be transmitted 
               
               
                   
                 Data Valid Low 
                 1 to 7 bytes of data valid in the 
               
               
                   
                   
                 low order bytes 
               
               
                   
                 Data Valid High 
                 1 to 7 bytes of data valid in the 
               
               
                   
                   
                 high order bytes 
               
               
                   
                   
               
            
           
         
       
     
     The control state is encoded within the XGMII transmit Controller  1050  into the two bits, C&lt; 1 : 0 &gt;, using the mapping in Table 2. 
     
       
         
           
               
             
               
                 TABLE 2 
               
             
            
               
                   
               
               
                 Control State Encoding 
               
            
           
           
               
               
               
               
            
               
                   
                   
                   
                 Control 
               
               
                   
                 C1 
                 C0 
                 State 
               
               
                   
                   
               
               
                   
                 0 
                 0 
                 Idle 
               
               
                   
                 0 
                 1 
                 Data Valid 
               
               
                   
                   
                   
                 Low 
               
               
                   
                 1 
                 0 
                 Data Valid 
               
               
                   
                   
                   
                 High 
               
               
                   
                 1 
                 1 
                 Data Valid 
               
               
                   
                   
                   
                 All 
               
               
                   
                   
               
            
           
         
       
     
     C&lt; 1 : 0 &gt; and TX_ER define primary control states for the data transfers as shown in Table 3. 
     
       
         
           
               
             
               
                 TABLE 3 
               
             
            
               
                   
               
               
                 Transmit Data Bus Control Encoding 
               
            
           
           
               
               
               
               
               
            
               
                 C1 
                 C0 
                 TX_ER 
                 TXD&lt;63:0&gt; 
                 Description 
               
               
                   
               
               
                 0 
                 0 
                 0 
                 0x0000000000000000 
                 Idle 
               
               
                 0 
                 0 
                 1 
                 Reserved 
                 Idle on medium, 
               
               
                   
                   
                   
                   
                 reserved 
               
               
                   
                   
                   
                   
                 communication 
               
               
                 1 
                 1 
                 0 
                 0x00.00 to 0xFF.. 
                 Transmit Data Valid 
               
               
                   
                   
                   
                 FF 
                 All 
               
               
                 0 
                 1 
                 0 
                 See Table 3 
                 Transmit Data Valid 
               
               
                   
                   
                   
                   
                 Low 
               
               
                 1 
                 0 
                 0 
                 See Table 4 
                 Transmit Data Valid 
               
               
                   
                   
                   
                   
                 High 
               
               
                 1 
                 1 
                 1 
                 Not defined 
                 Transmit Error 
               
               
                 0 
                 1 
                 1 
                 Not defined 
                 Transmit Error 
               
               
                 1 
                 0 
                 1 
                 Not defined 
                 Transmit Error 
               
               
                   
               
            
           
         
       
     
     Further encoding of valid data bytes is contained within the data bus itself during the Data Valid High and Data Valid Low states. These are shown in Tables 4 and 5. 
     
       
         
           
               
             
               
                 TABLE 4 
               
             
            
               
                   
               
               
                 Transmit Data Valid Low Encoding 
               
            
           
           
               
               
               
               
               
               
            
               
                 TXD 
                 TXD 
                 TXD 
                 TXD 
                 TXD 
                   
               
               
                 &lt;63:59&gt; 
                 &lt;58&gt; 
                 &lt;57&gt; 
                 &lt;56&gt; 
                 &lt;55:0&gt; 
                 Description 
               
               
                   
               
               
                 Reserved 
                 0 
                 0 
                 0 
                 Reserved 
                 Reserved 
               
               
                 Reserved 
                 0 
                 0 
                 1 
                 Idle*/Data 
                 1 byte valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;7:0&gt; 
               
               
                 Reserved 
                 0 
                 1 
                 0 
                 Idle*/Data 
                 2 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;15:0&gt; 
               
               
                 Reserved 
                 0 
                 1 
                 1 
                 Idle*/Data 
                 3 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;23:0&gt; 
               
               
                 Reserved 
                 1 
                 0 
                 0 
                 Idle*/Data 
                 4 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;31:0&gt; 
               
               
                 Reserved 
                 1 
                 0 
                 1 
                 Idle*/Data 
                 5 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;39:0&gt; 
               
               
                 Reserved 
                 1 
                 1 
                 0 
                 Idle*/Data 
                 6 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;47:0&gt; 
               
               
                 Reserved 
                 1 
                 1 
                 1 
                 Idle*/Data 
                 7 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;55:0&gt; 
               
               
                   
               
               
                 *Unused TXD bytes are set to 0x00  
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 5 
               
             
            
               
                   
               
               
                 Transmit Data Valid High Encoding 
               
            
           
           
               
               
               
               
               
               
            
               
                 TXD 
                 TXD 
                 TXD 
                 TXD 
                 TXD 
                   
               
               
                 &lt;7:3&gt; 
                 &lt;2&gt; 
                 &lt;1&gt; 
                 &lt;0&gt; 
                 &lt;55:0&gt; 
                 Description 
               
               
                   
               
               
                 Reserved 
                 0 
                 0 
                 0 
                 Reserved 
                 Reserved 
               
               
                 Reserved 
                 0 
                 0 
                 1 
                 Data/Idle* 
                 1 byte valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:56&gt; 
               
               
                 Reserved 
                 0 
                 1 
                 0 
                 Data/Idle* 
                 2 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:48&gt; 
               
               
                 Reserved 
                 0 
                 1 
                 1 
                 Data/Idle* 
                 3 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:40&gt; 
               
               
                 Reserved 
                 1 
                 0 
                 0 
                 Data/Idle* 
                 4 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:32&gt; 
               
               
                 Reserved 
                 1 
                 0 
                 1 
                 Data/Idle* 
                 5 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:24&gt; 
               
               
                 Reserved 
                 1 
                 1 
                 0 
                 Data/Idle* 
                 6 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:16&gt; 
               
               
                 Reserved 
                 1 
                 1 
                 1 
                 Data/Idle* 
                 7 bytes valid, 
               
               
                   
                   
                   
                   
                   
                 TXD&lt;63:8&gt; 
               
               
                   
               
               
                 *Unused TXD bytes are set to 0x00  
               
            
           
         
       
     
     Transmit Error (TX_ER) is encoded by the XGMII Transmit Controller as follows. 
     If the current control state is Idle then no action is taken because the error is not within a packet. 
     If the current control state is Data Valid Low the control state is sent with the TXD[ 3 ] bit set in the reserved control space. 
     If the current control state is Data Valid High the control state is sent with the TXD[ 59 ] bit set in the reserved control space. 
     If the current control state is Data Valid All the control state is changed to Data Valid High with the TXD[ 59 ] bit set in the reserved control space. 
     Data ECC Encoder 
     The Data ECC generator  1052  generates seven redundant bits, E&lt; 6 : 0 &gt;, from the 65-bit data payload comprising the data carried on TXD&lt; 63 : 0 &gt; received from the XGMII Transmit Control Logic  1050  and the monitor channel bit of the monitor channel  1026  (FIG.  12 ). The seven ECC bits are generated using a CRC algorithm that provides single bit error correction, double bit error detection and six bit burst error detection. Additional error detection capabilities are realized when the CRC detection is combined with the parity protection added later. This is equivalent to most commonly used 8-bit cyclic redundancy checkers that have (1+x) as a factor in the polynomial. 
     The message polynomial, M(x), is generated from the data and monitor transmit payload, TXD&lt; 63 : 0 &gt; and the monitor bit M, using the convention that the highest polynomial term is the first bit on the wire. 
     
       
           M ( x )= TXD   0   x   64   +TXD   1   x   63   + . . . +TXD   62   x   2   +TXD   63   x +M   
       
     
     The message polynomial is then divided by the generating polynomial, G(x), to produce the quotient, Q(x), and the remainder, E(x).              x   7          M        (   x   )           G        (   x   )         =       Q        (   x   )       +       E        (   x   )         G        (   x   )                           
     where E(x) has the form 
       E ( x )= E   0   x   6   +E   1   x   5   + . . . +E   5   x+E   6   
     The transmit message is then the concatenation of the message, M(x), and the remainder, E(x). 
     
       
           TX ( x )= M ( x )+ E ( x ) 
       
     
     This 72 bit payload is then inserted in the physical coding sublayer cell format depicted in FIG.  15  and has the property that it is divisible by G(x) in the absence of errors. 
     The generating polynomial, G(x), in the preferred embodiment, was chosen to minimize the number of gates in the implementation. 
     
       
           G ( x )= x   7   +x +1 
       
     
     Shown below are the reduced XOR logical equations that constitute the CRC function within the data ECC generator  1052  for the exemplary embodiment herein disclosed. 
     
       
           E   0 = TXD   2 + TXD   5 + TXD   9 + 
       
     
     
       
         TXD 10 + TXD   11 + TXD   16 + TXD   18 + TXD   19 + 
       
     
     
       
         TXD 20 + TXD   21 + TXD   22 + TXD   25 + TXD   27 + 
       
     
     
       
         TXD 29 + TXD   30 + TXD   31 + TXD   34 + TXD   35 + 
       
     
     
       
         TXD 37 + TXD   41 + TXD   44 + TXD   45 + TXD   46 + 
       
     
     
       
         TXD 47 + TXD   51 + TXD   53 + TXD   58 + TXD   59 ; 
       
     
     
       
           E   1 = TXD   0 + TXD   3 + TXD   6 + TXD   10 + 
       
     
     
       
         TXD 11 + TXD   12 + TXD   17 + TXD   19 + TXD   20 + 
       
     
     
       
         TXD 21 + TXD   22 + TXD   23 + TXD   26 + TXD   28 + 
       
     
     
       
         TXD 30 + TXD   31 + TXD   32 + TXD   35 + TXD   36 + 
       
     
     
       
         TXD 38 + TXD   42 + TXD   45 + TXD   46 + TXD   47 + 
       
     
     
       
         TXD 48 + TXD   52 + TXD   54 + TXD   59 + TXD   60 ; 
       
     
     
       
           E   2 = TXD   0 + TXD   1 + TXD   4 + TXD   7 + 
       
     
     
       
         TXD 11 + TXD   12 + TXD   13 + TXD   18 + TXD   20 + 
       
     
     
       
         TXD 21 + TXD   22 + TXD   23 + TXD   24 + TXD   27 + 
       
     
     
       
         TXD 29 + TXD   31 + TXD   32 + TXD   33 + TXD   36 + 
       
     
     
       
         TXD 37 + TXD   39 + TXD   43 + TXD   46 + TXD   47 + 
       
     
     
       
         TXD 48 + TXD   49 + TXD   53 + TXD   55 + TXD   60 + 
       
     
     
       
         TXD 61 ; 
       
     
     
       
           E   3 = TXD   1 + TXD   2 + TXD   5 + TXD   8 + 
       
     
     
       
         TXD 12 + TXD   13 + TXD   14 + TXD   19 + TXD   21 + 
       
     
     
       
         TXD 22 + TXD   23 + TXD   24 + TXD   25 + TXD   28 + 
       
     
     
       
         TXD 30 + TXD   32 + TXD   33 + TXD   34 + TXD   37 + 
       
     
     
       
         TXD 38 + TXD   40 + TXD   44 + TXD   47 + TXD   48 + 
       
     
     
       
         TXD 49 + TXD   50 + TXD   54 + TXD   56 + TXD   61 + TXD   62 ; 
       
     
       E   4 = TXD   0 + TXD   2 + TXD   3 + TXD   6 + 
     
       
         TXD 9 + TXD   13 + TXD   14 + TXD   15 + TXD   20 + 
       
     
     
       
         TXD 22 + TXD   23 + TXD   24 + TXD   25 + TXD   26 + 
       
     
     
       
         TXD 29 + TXD   31 + TXD   33 + TXD   34 + TXD   35 + 
       
     
     
       
         TXD 38 + TXD   39 + TXD   41 + TXD   45 + TXD   48 + 
       
     
     
       
         TXD 49 + TXD   50 + TXD   51 + TXD   55 + TXD   57 + 
       
     
     
       
         TXD 62 + TXD   63 ; 
       
     
     
       
           E   5 = TXD   0 + TXD   1 + TXD   3 + TXD   4 + 
       
     
     
       
         TXD 7 + TXD   10 + TXD   14 + TXD   15 + TXD   16 + 
       
     
     
       
         TXD 21 + TXD   23 + TXD   24 + TXD   25 + TXD   26 + 
       
     
     
       
         TXD 27 + TXD   30 + TXD   32 + TXD   34 + TXD   35 + 
       
     
     
       
         TXD 36 + TXD   39 + TXD   40 + TXD   42 + TXD   46 + 
       
     
     
       
         TXD 49 + TXD   50 + TXD   51 + TXD   52 + TXD   56 + 
       
     
     
       
         TXD 58 + TXD   63 + M;   
       
     
     
       
           E   6 = TXD   1 + TXD   4 + TXD   8 + TXD   9 + 
       
     
     
       
         TXD 10 + TXD   15 + TXD   17 + TXD   18 + TXD   19 + 
       
     
     
       
         TXD 20 + TXD   21 + TXD   24 + TXD   26 + TXD   28 + 
       
     
     
       
         TXD 29 + TXD   30 + TXD   33 + TXD   34 + TXD   36 + 
       
     
     
       
         TXD 40 + TXD   43 + TXD   44 + TXD   45 + TXD   46 + 
       
     
     
       
         TXD 50 + TXD   52 + TXD   57 + TXD   58 + M;   
       
     
     Transmit Channel Assignments 
     The transmit data bus, monitor bit and ECC bits are divided into separate groups which are then scrambled as subsequently described and transmitted over respective channels. In the present embodiment, the 64 data bits comprising the parallel input data word, the monitor bit and the seven (7) ECC bits comprise 72 bits that are split into four 18 bit groups as indicated below. This is the function of the transmit interleaver  1053 . This interleaver may comprise active logic to drive respective signals or alternatively may simply define the coupling of appropriate outputs TXD&lt; 63 : 0 &gt;, E&lt; 6 : 0 &gt; and M to the appropriate inputs of the transmit scrambler logic  54  as defined below. 
     TXPa&lt; 17 : 0 &gt;=&lt;E 0 , M, TXD 15 , TXD 14 , TXD 13 , TXD 12 , TXD 11 , TXD 10 , TXD 9 , TXD 8 , TXD 7 , TXD 6 , TXD 5 , TXD 4 , TXD 3 , TXD 2 , TXD 1 , TXD 0 &gt; 
     TXPb&lt; 17 : 0 &gt;=&lt;E 2 , E 1 , TXD 31 , TXD 30 , TXD 29 , TXD 28 , TXD 27 , TXD 26 , TXD 25 , TXD 24 , TXD 23 , TXD 22 , TXD 21 , TXD 20 , TXD 19 , TXD 18 , TXD 17 , TXD 16 &gt; 
     TXPC&lt; 17 : 0 &gt;=&lt;E 4 , E 3 , TXD 47 , TXD 46 , TXD 45 , TXD 44 , TXD 43 , TXD 42 , TXD 41 , TXD 40 , TXD 39 , TXD 38 , TXD 37 , TXD 36 , TXD 35 , TXD 34 , TXD 33 , TXD 32 &gt; 
     TXPd&lt; 17 : 0 &gt;=&lt;E 6 , E 5 , TXD 63 , TXD 62 , TXD 61 , TXD 60 , TXD 59 , TXD 58 , TXD 57 , TXD 56 , TXD 55 , TXD 54 , TXD 53 , TXD 52 , TXD 51 , TXD 50 , TXD 49 , TXD 48 &gt; 
     Transmit Scrambler 
     Transmit scrambler  1054  is used to provide DC balance, insert transitions, spread the signal spectrum across the available bandwidth and produce low EMI. The incoming data is exclusive ORed with the scrambler&#39;s PRBS. 
     Each channel has a separate side-stream scrambler  1054   a ,  1054   b ,  1054   c  and  1054   d , which is generating the same sequence, but offset in time, so the channels are de-correlated locally in time. The side stream scramblers  1054  correspond to the side stream scramblers  32  previously discussed and illustrated in FIG.  3 . In a preferred embodiment, de-correlation is achieved over +/−2.6 us using a pseudo random binary sequence of length  15 , which is sufficient to de-correlate Near End Crosstalk (NEXT) and Far End Crosstalk (FEXT) contributions from other channels. The time offset of the sequences in the respective channels is achieved by loading different seed values in each channel at startup. Separate scramblers are used to keep global interconnect low while providing a scalable structure. Alternatively, a centralized scrambler may be employed. 
     Offset scramblers also effectively encode channel skew information into the transmission words that could be used by the receiver to establish inter-channel skew. The cell encoder uses a more direct method of establishing inter-channel alignment so checking this relationship within the receiver is optional. 
     In the illustrated embodiment, a pseudo random binary sequence of length  15  (PRBS 15 ) was chosen to allow receiver synchronization within one Idle transmission period. Data in each channel is defined to be constant at 0x00 during an idle transmission. The monitor bit, and, consequently, the error correction bits, E 5  and E 6  bits, are not guaranteed to have a known state during idle. The first 15 bits within each channel, i.e. TXCx &lt; 14 : 0 &gt;, give the state of the scrambler so the 15 bit seed can be recovered completely within each 80-bit idle cell. Each of the scramblers  1054   a ,  1054   b ,  1054   c ,  1054   d  (FIG. 14) employs the logic depicted in FIG. 3 in a preferred embodiment. 
     The outputs of the respective side scramblers provide scrambled or cipher data that are identified as TXCIa&lt; 17 : 0 &gt;, TXCIb&lt; 17 : 0 &gt;, TXCIc&lt; 17 : 0 &gt; and TXCId&lt; 17 : 0 &gt; as indicated above. The side scrambler output buses are coupled to the inputs of a Parity and FEC Control Matrix  1056  (FIG. 14) which is depicted with greater particularity in FIG.  16 . 
     Parity and Control FEC Matrix 
     Referring to FIG. 16, the Parity and Control ECC Logic  1056  generates two additional bits in each channel. The two bits per channel carry transmit control state and provide parity for the respective channels. The bits are used to obtain alignment on word boundaries within each channel (word alignment) and additionally to obtain inter-channel alignment. These added bits are redundant with a Hamming distance of 4 to allow correction of single bit control errors and detection of two-bit errors. The inputs to the parity and control ECC encoder  1056  comprise the control bus c&lt; 1 : 0 &gt; and the TXCI bus data from the scramblers  1054   a - 1054   d  (FIG.  14 ). The parity and Control ECC encoder  1056  generates extended cipher data words TXCEa&lt; 19 : 0 &gt; through TXCEd&lt; 19 : 0 &gt; (FIG. 16) that are coupled to burst interleave logic  1058 , such as the burst  4  interleave logic or the burst  10  interleave logic described above (FIGS. 4,  5   a ,  5   b  and accompanying description, FIGS. 9,  10   a ,  10   b  and accompanying description). The outputs of the burst interleave logic  1058  are coupled to double clock logic  1057  (FIG.  14 ). The double clock logic  1057  clocks out the 20 bit per channel TXCE data as two sequential  10  bit words TXCED&lt; 9 : 0 &gt; to reduce the number of signal lines that need to be accommodated within the system. 
     The first of the two parity bits previously identified as the CECC bit and referred to in the drawing as the R 0  bit, starts with the definition of a new variable, K&lt; 3 : 0 &gt; in a K word generator  1120 . The K word generator  1120  receives as an input the control word C&lt; 1 : 0 &gt; from the XGMII Transmit Control Logic  1050 . The output of the K word generator  1120  comprises a four bit wide bus K&lt; 3 : 0 &gt; that holds the control state redundantly and has zero DC content. The states themselves have a minimum Hamming distance of 2 and require the additional information from the parity bits R 1  discussed below to increase the Hamming distance to 4 and allow correction to be performed. The generation of the K values based upon the C&lt; 1 : 0 &gt; inputs is illustrated below in Table 6. 
     
       
         
           
               
             
               
                 TABLE 6 
               
             
            
               
                   
               
               
                 Control Word Output 
               
            
           
           
               
               
               
               
               
            
               
                   
                 Control State 
                   
                 Coding Output 
                   
               
            
           
           
               
               
               
               
               
               
               
            
               
                   
                 C1 
                 C0 
                 K3 
                 K2 
                 K1 
                 K0 
               
               
                   
                   
               
               
                   
                 0 
                 0 
                 1 
                 1 
                 0 
                 0 
               
               
                   
                 0 
                 1 
                 1 
                 0 
                 0 
                 1 
               
               
                   
                 1 
                 0 
                 0 
                 1 
                 1 
                 0 
               
               
                   
                 1 
                 1 
                 0 
                 0 
                 1 
                 1 
               
               
                   
                   
               
            
           
         
       
     
     Intermediate parity checks, R&lt;a:d&gt;, are calculated on the 72-bit TXCI data payload (data+Monitor+data EVC) in parity check logic  1122   a ,  1122   b ,  1122   c  and  1122   d  as follows:          R   a     =       ∑     k   =   0     17                       TXCI   a          (   k   )                   R   b     =       ∑     k   =   0     17                       TXCI   b          (   k   )                   R   c     =       ∑     k   =   0     17                       TXCI   c          (   k   )                   R   d     =       ∑     k   =   0     17                       TXCI   d          (   k   )                         
     Thus, Ra indicates the parity of the data contained in TXCIa&lt; 17 : 0 &gt;, Rb indicates the parity of the data contained in TXCIb&lt; 17 : 0 &gt;, Rc indicates the parity of the data contained in TXCIc&lt; 17 : 0 &gt; and Rd indicates the parity of the data contained in TXCId&lt; 17 : 0 &gt;. The parity check variables are random if the TXCI payload is random, which will be the case due to the use of side-stream scramblers  1054   a ,  1054   b ,  1054   c  and  1054   d . The intermediate parity bits Ra, Rb, Rc and Rd are XORed with the K bits in R 0  bit generation logic  1124  to scramble the control state and the R 0  bits are further rotated across the channels to permit inter-channel skew detection. The resulting R 0 &lt;a:d&gt; bits are transmitted as the TXCE 18 &lt;a:d&gt; bits in each channel and are defined as follows. 
       TXCE   18   a   =R   0   a   =R   d   +K   0   
     
       
         
           TXCE 
           18 
           b 
           =R 
           0 
           b 
           =R 
           a 
           +K 
           1 
         
       
     
     
       
         
           TXCE 
           18 
           c 
           =R 
           0 
           c 
           =R 
           b 
           +K 
           2 
         
       
     
     
       
         
           TXCE 
           18 
           d 
           =R 
           0 
           d 
           =R 
           c 
           +K 
           3 
         
       
     
     Finally, the overall parity across all 19 bits in each channel is calculated in R 1  bit generation logic  1126  and transmitted in the TXCE 19 &lt;a:d&gt; slot as illustrated in FIG.  15 . These bits are designated as the R 1 &lt;a:d&gt; bits and calculated as indicated below.          TXCE19   a     =       R1   a     =       !       ∑     k   =   0     18            TXC   a          (   k   )           =     !     (       R   a     +     R0   a       )                     TXCE19   b     =       R1   b     =       !       ∑     k   =   0     18            TXC   b          (   k   )           =     !     (       R   b     +     R0   b       )                     TXCE19   c     =       R1   c     =       !       ∑     k   =   0     18            TXC   c          (   k   )           =     !     (       R   c     +     R0   c       )                     TXCE19   d     =       R1   d     =       !       ∑     k   =   0     18            TXC   d          (   k   )           =     !         (       R   d     +     R0   d       )          
     !                   indicates                 inversion                           
     The R 1 &lt;a:d&gt; (TXCE 19 ) bits are used as parity bits to enhance error correction and detection in both the data and control payloads. They also provide correlation information to allow word and channel alignment to be achieved as discussed further below. Inversion of the parity guarantees at least one transition within the 20-bit word. Two worst case words back to back can produce the maximum run length of 38 with a probability of 3.6E-12. 
     Within each channel all bits in a word sum to one in the absence of any errors. This characteristic is used to acquire word alignment and can be employed as the framing signal by the framing signal logic  114  (FIGS.  7  and/or  11 ) as discussed above.            ∑     k   =   0     19                       TX   a          (   k   )         =   1               ∑     k   =   0     19                       TX   b          (   k   )         =   1               ∑     k   =   0     18                       TX   c          (   k   )         =   1               ∑     k   =   0     18                       TX   d          (   k   )         =   1                   
     Additionally, when the channels are correctly aligned all R 1  bits within a cell sum to zero in the absence of errors. 
     
       
           TXCE   19   a   +TXCE   19   b   +TXCE   19   d   +TXCE   19   d =0 
       
     
     
       
           R   1   a   +R   1   b   +R   1   d   +R   1   d =0 
       
     
     This is used to achieve channel alignment as discussed below. 
     Receive Path 
     The receive path through the physical coding sublayer  1014  is depicted in FIG.  17 . Referring to FIG. 17, the receive path roughly follows the transmit path in reverse with the added complexity of having to acquire word and inter-channel alignment and perform error correction. 
     Channels A, B, C and D include channel receive logic that includes word framer and de-interleave logic  1150   a-d  (FIG.  17 ). Each block  1150   a-d  includes one instance of the word framer and de-interleave logic for the burst  4  logic, the burst  10  logic or both. The respective word framer and de-interleave logic functions  1150   a-d  receive parallel data over buses RXCEDa&lt; 9 : 0 &gt;-RXCEDd&lt; 9 : 0 &gt;. The outputs of the word framer and de-interleave logic  1150   a-d  are coupled to inter-channel alignment logic  1156  which in turn has outputs that are coupled to a de-scrambler  1158  such as discussed above with respect to FIG. 8 and a control ECC Decoder  1160 . The outputs from the de-scrambler  1158  are coupled to receive interleave and data ECC decode logic  1162 . The outputs from receive interleave and data ECC logic  1162  and the control ECC decode logic  1160  are coupled to the XGMII receive controller  1164 . The XGMII receive controller  1164  produces at its output the original parallel data word on the bus RXX_D&lt; 63 : 0 &gt;, the original control byte on bus RXX_C&lt; 7 : 0 &gt; and a receive clock RXX_CLK. The receive interleave and data ECC logic  1162  also provides as an output the bit M of the monitor channel as depicted in FIG.  17 . 
     Alignment of receive data is achieved in several steps. Each step is dependent on acquisition of the previous steps. Acquisition starts with achieving word-frame alignment within each channel. Word frame alignment is achieved as discussed above with respect to FIG.  7 . The channels are then de-skewed to achieve inter-channel alignment and finally the scrambler states are acquired during an idle transmission. Receive channels are synchronous but do not have a defined phase at the input to the receiver after de-serialization. All channels are synchronized to a master channel that in the present embodiment is defined to be channel A. Inter-channel alignment is accomplished in the inter-channel alignment block  1156 . The inter-channel alignment block  1156  includes a FIFO structure in the respective channels to permit the changing of clock domains. 
     The bit error rate (BER) during acquisition is assumed to be reasonably good (better than 1E-6) such that there is a high probability that correlation calculations done over 256 words will not experience an error. 
     Word Frame Alignment 
     Word framing logic that may be employed in each of the receive channels is depicted with greater particularity in FIG.  18 . Word framing within each channel of the presently illustrated four channel system is obtained by checking for correct parity across a word (20 bits). More particularly, word framing logic such as illustrated and discussed with respect to  7  and  11  is employed to achieve word frame alignment. In the present case, the frame check logic  112  (FIGS. 7,  11 ) checks for proper parity across a predetermined number of word samples. 
     The parity calculation is done over 20 receive bits to produce the Channel Error (CE) variable.          CE        (   n   )       =     !         ∑     k   =   0     19          RX        (   k   )            0                       
     Each CE bit has roughly a 50% chance of being correct (=0) in a random data stream. Integrating over N samples gives the required low probability of false alignment.            ∑     n   =   0     N                     CE        (   n   )            0                   
     The probability of false alignment is 3E-39 if the calculation is done over 128 words (N=128) and 9E-78 over 256 words (N=256) with random data. 
     The Word Frame Control logic  116  (FIGS. 7,  11 ) uses the output of the Framing Check Logic  114  (FIGS. 7,  11 ) to search through the 20 possible framing options until the correct frame location is acquired. In the present circumstance, the Framing Check Logic  114  comprises logic for varying the received parity indication. More specifically, as indicated above, the framing check logic  114  inspects the 20 bit frame a presented and provides an indication of no error if CE(n)=0 and provides an indication of a channel error if CE(n)=1. The word frame control logic  116  (FIGS. 7,  11 ) provides an output signal Word Lock once proper word framing has been achieved. Correct word framing is virtually assured by confirming correct parity over a large number of samples, such as 128 or 256 samples. 
     Receiver Inter-Channel Alignment 
     FIG. 18 depicts an exemplary block diagram for achieving inter-channel alignment of received parallel data words. Inter-channel alignment is needed to avoid the possibility of word skew between the respective serial channels. Once word framing is achieved in all channels and the R 1  bits (RX 19 ) have been identified in each channel, inter-channel alignment can proceed. Inter-channel alignment relies on the property that the R 1  parity bits sum to zero if the channels are correctly aligned (in the absence of errors). 
       A ( n )= R   1   a   +R   1   b   +R   1   c   +R   1   d =0 
     The A bit has a roughly 50% chance of being correct (=0) in a random data stream. Integrating over N samples gives the required low probability of false alignment.            ∑     n   =   0     N                     A        (   n   )            0                   
     The probability of false alignment is 3E-39 if the calculation is done over 128 words (N=128) and 9E-78 over 256 words (N=256) with random data. 
     Inter-Channel alignment can be achieved by delaying specific channels relative to other channels. Referring to FIG. 18 each channel contains word delay logic  1200 . The delay logic  1200  in the presently disclosed embodiment includes cascaded delay registers  1202 ,  1204 ,  1206  and a MUX  1208  that selects one of the progressively delayed versions of the receive words. The number of delay stages required is a function of the possible skew that may occur during transmission through the channel and is system dependent. The implementation in FIG. 18 allows for an inter-channel skew of +/−1 word. A greater number of cascaded delay registers may be employed. The multiplexer  1208  in each channel can select the appropriate delayed word as the operative input to the MUX  1208 . The Inter-Channel Alignment Control logic  1210  adjusts the delays until the R 1  bits across the four channels sum to 0 over a predetermined number of samples. 
     The FIFO structure of the inter-channel alignment block lends itself to re-synchronizing the B, C and D receive clocks into the channel A clock domain. The FIFOs can be initialized after word alignment has been achieved in each channel, which guarantees an acceptable BER in each channel and the link is operating in a steady state with no phase gradients caused by the phase locked loops (PLLs). 
     The search pattern used to acquire inter-channel alignment is somewhat arbitrary however the highest probability of achieving alignment is around the equal delay point across channels. Searching around this point can minimize acquisition time. Table 7 shows a weighted-search over +/−1 word. Executing the search in Table 8 after Table 7 will achieve a weighted-search over +/−2 words. 
     Channel A is used as the delay reference (always 0) and negative numbers indicate that channel is advanced relative to channel A while positive numbers indicate they are retarded in Tables 7 and 8. 
     
       
         
           
               
             
               
                 TABLE 7 
               
             
            
               
                   
               
               
                 Channel Alignment Search +/− One Word 
               
            
           
           
               
               
               
               
               
            
               
                 Iteration 
                 A 
                 B 
                 C 
                 D 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 1 
                 0 
                 0 
                 0 
                 0 
               
               
                 2 
                 0 
                 −1 
                 0 
                 0 
               
               
                 3 
                 0 
                 0 
                 −1 
                 0 
               
               
                 4 
                 0 
                 0 
                 0 
                 −1 
               
               
                 5 
                 0 
                 0 
                 0 
                 1 
               
               
                 6 
                 0 
                 0 
                 1 
                 0 
               
               
                 7 
                 0 
                 1 
                 0 
                 0 
               
               
                 8 
                 0 
                 −1 
                 −1 
                 0 
               
               
                 9 
                 0 
                 −1 
                 0 
                 −1 
               
               
                 10 
                 0 
                 −1 
                 0 
                 1 
               
               
                 11 
                 0 
                 −1 
                 1 
                 0 
               
               
                 12 
                 0 
                 0 
                 −1 
                 −1 
               
               
                 13 
                 0 
                 0 
                 −1 
                 1 
               
               
                 14 
                 0 
                 0 
                 1 
                 −1 
               
               
                 15 
                 0 
                 0 
                 1 
                 1 
               
               
                 16 
                 0 
                 1 
                 −1 
                 0 
               
               
                 17 
                 0 
                 1 
                 0 
                 −1 
               
               
                 18 
                 0 
                 1 
                 0 
                 1 
               
               
                 19 
                 0 
                 1 
                 1 
                 0 
               
               
                 20 
                 0 
                 −1 
                 −1 
                 −1 
               
               
                 21 
                 0 
                 −1 
                 −1 
                 1 
               
               
                 22 
                 0 
                 −1 
                 1 
                 −1 
               
               
                 23 
                 0 
                 −1 
                 1 
                 1 
               
               
                 24 
                 0 
                 1 
                 −1 
                 −1 
               
               
                 25 
                 0 
                 1 
                 −1 
                 1 
               
               
                 26 
                 0 
                 1 
                 1 
                 −1 
               
               
                 27 
                 0 
                 1 
                 1 
                 1 
               
               
                   
               
            
           
         
       
     
     
       
         
           
               
             
               
                 TABLE 8 
               
             
            
               
                   
               
               
                 Channel Alignment Search +/− Two Words 
               
            
           
           
               
               
               
               
               
            
               
                 Iteration 
                 A 
                 B 
                 C 
                 D 
               
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 28 
                 0 
                 −2 
                 0 
                 0 
               
               
                 29 
                 0 
                 0 
                 −2 
                 0 
               
               
                 30 
                 0 
                 0 
                 0 
                 −2 
               
               
                 31 
                 0 
                 0 
                 0 
                 2 
               
               
                 32 
                 0 
                 0 
                 2 
                 0 
               
               
                 33 
                 0 
                 2 
                 0 
                 0 
               
               
                 34 
                 0 
                 −2 
                 −1 
                 0 
               
               
                 35 
                 0 
                 −2 
                 0 
                 −1 
               
               
                 36 
                 0 
                 −2 
                 0 
                 1 
               
               
                 37 
                 0 
                 −2 
                 1 
                 0 
               
               
                 38 
                 0 
                 −1 
                 −2 
                 0 
               
               
                 39 
                 0 
                 −1 
                 0 
                 −2 
               
               
                 40 
                 0 
                 −1 
                 0 
                 2 
               
               
                 41 
                 0 
                 −1 
                 2 
                 0 
               
               
                 42 
                 0 
                 0 
                 −2 
                 −1 
               
               
                 43 
                 0 
                 0 
                 −2 
                 1 
               
               
                 44 
                 0 
                 0 
                 −1 
                 −2 
               
               
                 45 
                 0 
                 0 
                 −1 
                 2 
               
               
                 46 
                 0 
                 0 
                 1 
                 −2 
               
               
                 47 
                 0 
                 0 
                 1 
                 2 
               
               
                 48 
                 0 
                 0 
                 2 
                 −1 
               
               
                 49 
                 0 
                 0 
                 2 
                 1 
               
               
                 50 
                 0 
                 1 
                 −2 
                 0 
               
               
                 51 
                 0 
                 1 
                 0 
                 −2 
               
               
                 52 
                 0 
                 1 
                 0 
                 2 
               
               
                 53 
                 0 
                 1 
                 2 
                 0 
               
               
                 54 
                 0 
                 2 
                 −1 
                 0 
               
               
                 55 
                 0 
                 2 
                 0 
                 −1 
               
               
                 56 
                 0 
                 2 
                 0 
                 1 
               
               
                 57 
                 0 
                 2 
                 1 
                 0 
               
               
                 58 
                 0 
                 −2 
                 −1 
                 −1 
               
               
                 59 
                 0 
                 −2 
                 −1 
                 1 
               
               
                 60 
                 0 
                 −2 
                 1 
                 −1 
               
               
                 61 
                 0 
                 −2 
                 1 
                 1 
               
               
                 62 
                 0 
                 −1 
                 −2 
                 −1 
               
               
                 63 
                 0 
                 −1 
                 −2 
                 1 
               
               
                 64 
                 0 
                 −1 
                 −1 
                 −2 
               
               
                 65 
                 0 
                 −1 
                 −1 
                 2 
               
               
                 66 
                 0 
                 −1 
                 1 
                 −2 
               
               
                 67 
                 0 
                 −1 
                 1 
                 2 
               
               
                 68 
                 0 
                 −1 
                 2 
                 −1 
               
               
                 69 
                 0 
                 −1 
                 2 
                 1 
               
               
                 70 
                 0 
                 1 
                 −2 
                 −1 
               
               
                 71 
                 0 
                 1 
                 −2 
                 1 
               
               
                 72 
                 0 
                 1 
                 −1 
                 −2 
               
               
                 73 
                 0 
                 1 
                 −1 
                 2 
               
               
                 74 
                 0 
                 1 
                 1 
                 −2 
               
               
                 75 
                 0 
                 1 
                 1 
                 2 
               
               
                 76 
                 0 
                 1 
                 2 
                 −1 
               
               
                 77 
                 0 
                 1 
                 2 
                 1 
               
               
                 78 
                 0 
                 2 
                 −1 
                 −1 
               
               
                 79 
                 0 
                 2 
                 −1 
                 1 
               
               
                 80 
                 0 
                 2 
                 1 
                 −1 
               
               
                 81 
                 0 
                 2 
                 1 
                 1 
               
               
                 82 
                 0 
                 −2 
                 −2 
                 0 
               
               
                 83 
                 0 
                 −2 
                 0 
                 −2 
               
               
                 84 
                 0 
                 −2 
                 0 
                 2 
               
               
                 85 
                 0 
                 −2 
                 2 
                 0 
               
               
                 86 
                 0 
                 0 
                 −2 
                 −2 
               
               
                 87 
                 0 
                 0 
                 −2 
                 2 
               
               
                 88 
                 0 
                 0 
                 2 
                 −2 
               
               
                 89 
                 0 
                 0 
                 2 
                 2 
               
               
                 90 
                 0 
                 2 
                 −2 
                 0 
               
               
                 91 
                 0 
                 2 
                 0 
                 −2 
               
               
                 92 
                 0 
                 2 
                 0 
                 2 
               
               
                 93 
                 0 
                 2 
                 2 
                 0 
               
               
                 94 
                 0 
                 −2 
                 −2 
                 −1 
               
               
                 95 
                 0 
                 −2 
                 −2 
                 1 
               
               
                 96 
                 0 
                 −2 
                 −1 
                 −2 
               
               
                 97 
                 0 
                 −2 
                 −1 
                 2 
               
               
                 98 
                 0 
                 −2 
                 1 
                 −2 
               
               
                 99 
                 0 
                 −2 
                 1 
                 2 
               
               
                 100 
                 0 
                 −2 
                 2 
                 −1 
               
               
                 101 
                 0 
                 −2 
                 2 
                 1 
               
               
                 102 
                 0 
                 −1 
                 −2 
                 −2 
               
               
                 103 
                 0 
                 −1 
                 −2 
                 2 
               
               
                 104 
                 0 
                 −1 
                 2 
                 −2 
               
               
                 105 
                 0 
                 −1 
                 2 
                 2 
               
               
                 106 
                 0 
                 1 
                 −2 
                 −2 
               
               
                 107 
                 0 
                 1 
                 −2 
                 2 
               
               
                 108 
                 0 
                 1 
                 2 
                 −2 
               
               
                 109 
                 0 
                 1 
                 2 
                 2 
               
               
                 110 
                 0 
                 2 
                 −2 
                 −1 
               
               
                 111 
                 0 
                 2 
                 −2 
                 1 
               
               
                 112 
                 0 
                 2 
                 −1 
                 −2 
               
               
                 113 
                 0 
                 2 
                 −1 
                 2 
               
               
                 114 
                 0 
                 2 
                 1 
                 −2 
               
               
                 115 
                 0 
                 2 
                 1 
                 2 
               
               
                 116 
                 0 
                 2 
                 2 
                 −1 
               
               
                 117 
                 0 
                 2 
                 2 
                 1 
               
               
                 118 
                 0 
                 −2 
                 −2 
                 −2 
               
               
                 119 
                 0 
                 −2 
                 −2 
                 2 
               
               
                 120 
                 0 
                 −2 
                 2 
                 −2 
               
               
                 121 
                 0 
                 −2 
                 2 
                 2 
               
               
                 122 
                 0 
                 2 
                 −2 
                 −2 
               
               
                 123 
                 0 
                 2 
                 −2 
                 2 
               
               
                 124 
                 0 
                 2 
                 2 
                 −2 
               
               
                 125 
                 0 
                 2 
                 2 
                 2 
               
               
                   
               
            
           
         
       
     
     Receiver Control Decoder 
     Control decoding can proceed once correct word and inter-channel alignment of the serially received data is achieved. The control portion of the cell is not scrambled and can be decoded without scrambler synchronization. The redundant nature of the control coding allows for correction of any single bit error or detection of double bit errors in the control bits of the cell (R 0  and R 1  in RXCI&lt; 18 &gt; and RXCI&lt; 19 &gt; respectively). A block diagram depicting exemplary Control ECC Decoder Logic  1160  is shown in FIG.  19 . The method used to decode the control word is shown in FIGS. 20 a  and  20   b . The R 0  and R 1  bits (RXCI&lt; 19 : 18 &gt;) are decoded in K word estimation logic  1220  to give an estimate of K in accordance with the equations set forth below. 
     
       
           {circumflex over (K)}   0 =!( R   0   a   +R   0   d   +R   1   d )=!( RX &lt; 18 &gt; a   +RX &lt; 18 &gt; d   +RX &lt; 19 &gt; d ) 
       
     
     
       
           {circumflex over (K)}   1 =!( R   0   b   +R   0   a   +R   1   a )=!( RX &lt; 18 &gt; b   +RX &lt; 18 &gt; a   +RX &lt; 19 &gt; a ) 
       
     
     
       
           {circumflex over (K)}   2 =!( R   0   c   +R   0   b   +R   1   b )=!( RX &lt; 18 &gt; c   +RX &lt; 18 &gt; b   +RX &lt; 19 &gt; b ) 
       
     
     
       
           {circumflex over (K)}   3 =!( R   0   d   +R   0   c   +R   1   c )=!( RX &lt; 18 &gt; d   +RX &lt; 18 &gt; c   +RX &lt; 19 &gt; c ) 
       
     
     The estimated value of K is then checked and corrected, if required, in K word correction logic  1222 . Correction is possible because the control information in K can be recovered from only two channels and the channel parity checks indicate which channel is in error. The dependence of the K value on the channel is clear from the equations above. 
       {circumflex over (K)}   0   =F ( A,D ) 
     
       
           {circumflex over (K)}   1   =F ( A,B ) 
       
     
     
       
           {circumflex over (K)}   2   =F ( B,C ) 
       
     
     
       
           {circumflex over (K)}   3   =F ( C,D ) 
       
     
     Where F(x) indicates the output is a function of x. The coding of K is such that the correct value of K can be regenerated with the loss of any one channel. The Control State, C&lt; 1 : 0 &gt;, is decoded from the corrected K value in K word decode logic  1224  and status flags are generated in status flag generation logic  1226 . In particular, the status flag generator asserts an error signal in the event a single bit error is detected, asserts a MultError signal in the event a multi-bit error is detected and asserts a CorC signal in the event a single bit error in the control field C&lt; 1 : 0 &gt; is detected and corrected. 
     The flow diagram of FIGS. 20 a  and  20   b  illustrates the operation of the control ECC decoder depicted in FIG.  19  and discussed above. Estimated values of K bits are calculated as described above and as illustrated in step  1250 . Inquiry is made whether any parity errors were detected in the respective channels as shown in inquiry steps  1252  and  1254 . 
     If a single parity error is detected in channel A as indicated by a CE&lt;a:d&gt; value of 1000, the correct value of K is calculated based on the R 0  values contained in channels  2  and  3  as indicated in step  1256 . If a single parity error is detected in channel B as indicated by a CE&lt;a:d&gt; value of 0100, as indicated in step  1258 , the correct value of K is calculated based on the R 0  values contained in channels  0  and  4 . If a single parity error is detected in channel C as indicated by a CE&lt;a:d&gt; value of 0010, as indicated in step  1260 , the correct value of K is calculated based on the R 0  values contained in channels  0  and  1 . If a single parity error is detected in channel D as indicated by a CE&lt;a:d&gt; value of 0001, as indicated in step  1262 , the correct value of K is calculated based on the R 0  values contained in channels  1  and  2 . A variable Error is then set to equal true, as depicted in step  1266  to indicate that a single channel error has been detected. If as a result of inquiry step  1254  it is determined that CE&lt;a:d&gt; indicates errors in two or more channels, control passes to step  1278 . 
     A determination is next made whether there is an error in K in inquiry step  1268 . If there is no error in K, the control bits C&lt; 1 : 0 &gt; are decoded as a function of K as illustrated in step  1270 . Inquiry is then made whether the value of K equals the value of K estimated as depicted in step  1272 . If K═K estimated, no control error was detected and control decoding is terminated as illustrated in step  1276 . If K does not equal K estimated, control passes to step  1274 . In step  1274  an indication is recorded that a single bit control error has been detected and corrected. Following step  1274 , control decoding is terminated as indicated in step  1276 . 
     If it is determined in step  1268  that there is an error in K, control passes to step  1278  and an indication of an error and the fact that the error involves a multi-channel error is recorded. The C values are then set to a default condition as illustrated in step  1280  since the multiple errors cannot be corrected. Following step  1280  control passes to step  1276  and control decoding is terminated. 
     Receiver De-Scrambler 
     The De-scrambler  1158  (FIG. 17) corresponds to the de-scrambler discussed hereinabove with respect to FIG.  8 . Each channel has a separate de-scrambler  1158   a ,  1158   b ,  1158   c  and  1158   d  (FIG. 17) and employs the logic depicted in FIG. 8 in a preferred embodiment. The receive logic can detect when an Idle cell is being transmitted with the decoded Control State data appearing on control lines C&lt; 1 : 0 &gt;. This will occur frequently during the Inter Packet Gap (IPG) of a normal Ethernet transmission. Presence of Idle cells can be guaranteed by use of the known Far End Fault protocol provided in the Ethernet standard. The Idle state is defined to have 0x0000 in the 16 least significant bits of the data payload in each channel. The Idle is scrambled in each channel but if the data field is zeros then RXCI&lt; 14 : 0 &gt; is the scrambler state (seed) in each channel. The scrambler seed is recovered and loaded into the receiver scramblers. The sequence can be completely recovered in one idle period because the sequence length is 15 and the complete state is defined in each channel&#39;s data payload. The Monitor bit and its effect on the error correction terms do not effect the bits used for scrambler seed acquisition and are not restricted during idle transmission. Scrambler state can be recovered in each channel separately or the receiver can use the property that all channels have synchronized scrambler states which are offset from each other by a known amount. 
     A state machine controls the scrambler state acquisition and verifies that the scrambler remains in lock during Idle cells. Scrambler states between channels can also be optionally checked. The data ECC decoder  1162  (FIG.  17 ), that follows the de-scrambler  1158 , also provides an indication of loss of de-scrambler sync by recording a high number of multiple errors. 
     The outputs of the respective de-scramblers  1158   a ,  1158   b ,  1158   c  and  1158   d  provide plain data that is identified as TXPa&lt; 17 : 0 &gt;, TXPb&lt; 17 : 0 &gt;, RXPc&lt; 17 : 0 &gt; and RXPd&lt; 17 : 0 &gt; as indicated above. The de-scrambler output buses are coupled to the inputs of the Receive Interleaver and Data ECC Decoder  1162  (FIG.  17 ). 
     Receive Interleave and Data ECC Decoder 
     The Receive Interleave and Data ECC Decoder  1162  (See FIG. 17) recovers the data from each of the channels and performs the Data ECC Decoder functions. An exemplary block diagram of a Receive Interleave and Data ECC Decoder is depicted in FIG.  21 . The receive interleave logic  1320  (FIG. 21) is performed in accordance with the following equations to reproduce the original data ordering to the transmit interleaver  1053  (FIG.  14 ). The interleave function may simply constitute the recombination of the RXP&lt; 17 : 0 &gt; plain data to form the original data word, the ECC bits E&lt; 6 : 0 &gt; and the monitor bit M. 
     RXP&lt; 71 : 0 &gt;=&lt;RXPd 17 , RXPd 16 , RXPc 17 , RXPc 16 , RXPb 17 , RXPb 16 , RXPa 17 , RXPa 16 , RXPd 15 . RXPd 0 , RXPc 15  . . . RXPc 0 , RXPb 15 .RXPb 0 , RXPa 15 . RXPa 0 &gt; 
     Receive Data ECC Decoder 
     The Receive Data ECC Decoder  1162  (FIG. 17) is illustrated in greater detail in FIG.  21 . The receive data ECC decoder  1162  uses the redundant E&lt; 6 : 0 &gt; bits in the physical coding sublayer cell payload contained within the respective RXP channels RXPa, RXPb, RXPC and RXPd to detect and correct errors in the data payload. The data from each channel is combined using the receive interleave logic  1320  (FIG.  21 ). The syndrome S&lt; 6 : 0 &gt; is calculated in the syndrome generator  1322  over the 72-bit payload using the syndrome generation equations set forth below. 
     
       
           S   0 = RXP   2 + RXP   5 + RXP   9 + RXP   10 + 
       
     
     
       
         RXP 11 + RXP   16 + RXP   18 + RXP   19 + RXP   20 + 
       
     
     
       
         RXP 21 + RXP   22 + RXP   25 + RXP   27 + RXP   29 + 
       
     
     
       
         RXP 30 + RXP   31 + RXP   34 + RXP   35 + RXP   37 + 
       
     
     
       
         RXP 41 + RXP   44 + RXP   45 + RXP   46 + RXP   47 + 
       
     
     
       
         RXP 51 + RXP   53 + RXP   58 + RXP   59 + RXP   65 ; 
       
     
     
       
           S   1 = RXP   0 + RXP   3 + RXP   6 + RXP   10 + 
       
     
     
       
         RXP 11 + RXP   12 + RXP   17 + RXP   19 + RXP   20 + 
       
     
     
       
         RXP 21 + RXP   22 + RXP   23 + RXP   26 + RXP   28 + 
       
     
     
       
         RXP 30 + RXP   31 + RXP   32 + RXP   35 + RXP   36 + 
       
     
     
       
         RXP 38 + RXP   42 + RXP   45 + RXP   46 + RXP   47 + 
       
     
     
       
         RXP 48 + RXP   52 + RXP   54 + RXP   59 + RXP   60 + RXP   66 ; 
       
     
       S   2 = RXP   0 + RXP   1 + RXP   4 + RXP   7 + 
     
       
         RXP 11 + RXP   12 + RXP   13 + RXP   18 + RXP   20 + 
       
     
     
       
         RXP 21 + RXP   22 + RXP   23 + RXP   24 + RXP   27 + 
       
     
     
       
         RXP 29 + RXP   31 + RXP   32 + RXP   33 + RXP   36 + 
       
     
     
       
         RXP 37 + RXP   39 + RXP   43 + RXP   46 + RXP   47 + 
       
     
     
       
         RXP 48 + RXP   49 + RXP   53 + RXP   55 + RXP   60 + 
       
     
     
       
         RXP 61 + RXP   67 ; 
       
     
     
       
           S   3 = RXP   1 + RXP   2 + RXP   5 + RXP   8 + 
       
     
     
       
         RXP 12 + RXP   13 + RXP   14 + RXP   19 + RXP   21 + 
       
     
     
       
         RXP 22 + RXP   23 + RXP   24 + RXP   25 + RXP   28 + 
       
     
     
       
         RXP 30 + RXP   32 + RXP   33 + RXP   34 + RXP   37 + 
       
     
     
       
         RXP 38 + RXP   40 + RXP   44 + RXP   47 + RXP   48 + 
       
     
     
       
         RXP 49 + RXP   50 + RXP   54 + RXP   56 + RXP   61 + 
       
     
     
       
         RXP 62 + RXP   68 ; 
       
     
     
       
           S   4 = RXP   0 + RXP   2 + RXP   3 + RXP   6 + 
       
     
     
       
         RXP 9 + RXP   13 + RXP   14 + RXP   15  + RXP   20 + 
       
     
     
       
         RXP 22 + RXP   23 + RXP   24 + RXP   25 + RXP   26 + 
       
     
     
       
         RXP 29 + RXP   31 + RXP   33 + RXP   34 + RXP   35 + 
       
     
     
       
         RXP 38 + RXP   39 + RXP   41 + RXP   45 + RXP   48 + 
       
     
     
       
         RXP 49 + RXP   50 + RXP   51 + RXP   55 + RXP   57 + 
       
     
     
       
         RXP 62 + RXP   63 + RXP   69 ; 
       
     
     
       
           S   5 = RXP   0 + RXP   1 + RXP   3 + RXP   4 + 
       
     
     
       
         RXP 7 + RXP   10 + RXP   14 + RXP   15 + RXP   16 + 
       
     
     
       
         RXP 21 + RXP   23 + RXP   24 + RXP   25 + RXP   26 + 
       
     
     
       
         RXP 27 + RXP   30 + RXP   32 + RXP   34 + RXP   35 + 
       
     
     
       
         RXP 36 + RXP   39 + RXP   40 + RXP   42 + RXP   46 + 
       
     
     
       
         RXP 49 + RXP   50 + RXP   51 + RXP   52 + RXP   56 + 
       
     
     
       
         RXP 58 + RXP   63 + RXP   64 + RXP   70 ; 
       
     
     
       
           S   6 = RXP   1 + RXP   4 + RXP   8 + RXP   9 + 
       
     
     
       
         RXP 10 + RXP   15 + RXP   17 + RXP   18 + RXP   19 + 
       
     
     
       
         RXP 20 + RXP   21 + RXP   24 + RXP   26 + RXP   28 + 
       
     
     
       
         RXP 29 + RXP   30 + RXP   33 + RXP   34 + RXP   36 + 
       
     
     
       
         RXP 40 + RXP   43 + RXP   44 + RXP   45 + RXP   46 + 
       
     
     
       
         RXP 50 + RXP   52 + RXP   57 + RXP   58 + RXP   64 + RXP   71 ; 
       
     
     Any value for the generated syndrome other than zero indicates the presence of an error. All single bit errors will yield a unique syndrome value, which indicates the location of the error within the 72-bit field. The error location is determined in Lookup logic  1324  using the illustrative lookup table shown in Table 9 below. The error is then cross-checked against the channel parity flags using error check logic  1326  and corrected, if possible using error correction logic  1328 . The 64-bit data message and monitor bits are then extracted and coupled to the XGMII receive controller  1164  (FIG.  17 ). 
     
       
         
           
               
             
               
                 TABLE 9 
               
             
            
               
                   
               
               
                 Syndrome to Error Location 
               
            
           
           
               
               
            
               
                 Syndrome Value 
                 Error Location 
               
            
           
           
               
               
               
               
               
               
            
               
                 S&lt;6:0&gt; 
                 S (hex) 
                 S (dec) 
                 (hex) 
                 (dec) 
                 Channel 
               
               
                   
               
            
           
           
               
               
               
               
               
               
            
               
                 0000000 
                 00 
                 0 
                 No Error 
                 No Error 
                 0000 
               
               
                 0000001 
                 01 
                 1 
                 41 
                 65 
                 1000 
               
               
                 0000010 
                 02 
                 2 
                 42 
                 66 
                 0100 
               
               
                 0000011 
                 03 
                 3 
                 3B 
                 59 
                 0001 
               
               
                 0000100 
                 04 
                 4 
                 43 
                 67 
                 0100 
               
               
                 0000101 
                 05 
                 5 
                 35 
                 53 
                 0001 
               
               
                 0000110 
                 06 
                 6 
                 3C 
                 60 
                 0001 
               
               
                 0000111 
                 07 
                 7 
                 0B 
                 11 
                 1000 
               
               
                 0001000 
                 08 
                 8 
                 44 
                 68 
                 0010 
               
               
                 0001001 
                 09 
                 9 
                 05 
                  5 
                 1000 
               
               
                 0001010 
                 0A 
                 10 
                 36 
                 54 
                 0001 
               
               
                 0001011 
                 0B 
                 11 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0001100 
                 0C 
                 12 
                 3D 
                 61 
                 0001 
               
               
                 0001101 
                 0D 
                 13 
                 25 
                 37 
                 0010 
               
               
                 0001110 
                 0E 
                 14 
                 0C 
                 12 
                 1000 
               
               
                 0001111 
                 0F 
                 15 
                 2F 
                 47 
                 0010 
               
               
                 0010000 
                 10 
                 16 
                 45 
                 69 
                 0010 
               
               
                 0010001 
                 11 
                 17 
                 29 
                 41 
                 0010 
               
               
                 0010010 
                 12 
                 18 
                 06 
                  6 
                 1000 
               
               
                 0010011 
                 13 
                 19 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0010100 
                 14 
                 20 
                 37 
                 55 
                 0001 
               
               
                 0010101 
                 15 
                 21 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0010110 
                 16 
                 22 
                 N/A 
                 Mult 
                 11*11 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0011001 
                 19 
                 25 
                 02 
                  2 
                 1000 
               
               
                 0011010 
                 1A 
                 26 
                 26 
                 38 
                 0010 
               
               
                 0011011 
                 1B 
                 27 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0011100 
                 1C 
                 28 
                 0D 
                 13 
                 1000 
               
               
                 0011101 
                 1D 
                 29 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0011110 
                 1E 
                 30 
                 30 
                 48 
                 0001 
               
               
                 0011111 
                 1F 
                 31 
                 16 
                 22 
                 0100 
               
               
                 0100000 
                 20 
                 32 
                 46 
                 70 
                 0001 
               
               
                 0100001 
                 21 
                 33 
                 10 
                 16 
                 0100 
               
               
                 0100010 
                 22 
                 34 
                 2A 
                 42 
                 0010 
               
               
                 0100011 
                 23 
                 35 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0100100 
                 24 
                 36 
                 07 
                  7 
                 1000 
               
               
                 0100101 
                 25 
                 37 
                 1B 
                 27 
                 0100 
               
               
                 0100110 
                 26 
                 38 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0100111 
                 27 
                 39 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101000 
                 28 
                 40 
                 38 
                 56 
                 0001 
               
               
                 0101001 
                 29 
                 41 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101010 
                 2A 
                 42 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101011 
                 2B 
                 43 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101100 
                 2C 
                 44 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101101 
                 2D 
                 45 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0101110 
                 2E 
                 46 
                 20 
                 32 
                 0010 
               
               
                 0101111 
                 2F 
                 47 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0110000 
                 30 
                 48 
                 3F 
                 63 
                 0001 
               
               
                 0110001 
                 31 
                 49 
                 33 
                 51 
                 0001 
               
               
                 0110010 
                 32 
                 50 
                 03 
                  3 
                 1000 
               
               
                 0110011 
                 33 
                 51 
                 23 
                 35 
                 0010 
               
               
                 0110100 
                 34 
                 52 
                 27 
                 39 
                 0010 
               
               
                 0110101 
                 35 
                 53 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0110110 
                 36 
                 54 
                 00 
                  0 
                 1000 
               
               
                 0110111 
                 37 
                 55 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0111000 
                 38 
                 56 
                 0E 
                 14 
                 1000 
               
               
                 0111001 
                 39 
                 57 
                 19 
                 25 
                 0100 
               
               
                 0111010 
                 3A 
                 58 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0111011 
                 3B 
                 59 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0111100 
                 3C 
                 60 
                 31 
                 49 
                 0001 
               
               
                 0111101 
                 3D 
                 61 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 0111110 
                 3E 
                 62 
                 17 
                 23 
                 0100 
               
               
                 0111111 
                 3F 
                 63 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1000000 
                 40 
                 64 
                 47 
                 71 
                 0001 
               
               
                 1000001 
                 41 
                 65 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1000010 
                 42 
                 66 
                 11 
                 17 
                 0100 
               
               
                 1000011 
                 43 
                 67 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1000100 
                 44 
                 68 
                 2B 
                 43 
                 0010 
               
               
                 1000101 
                 45 
                 69 
                 12 
                 18 
                 0100 
               
               
                 1000110 
                 46 
                 70 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1000111 
                 47 
                 71 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1001100 
                 4C 
                 76 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1001101 
                 4D 
                 77 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1001110 
                 4E 
                 78 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1001111 
                 4F 
                 79 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1010000 
                 50 
                 80 
                 39 
                 57 
                 0001 
               
               
                 1010001 
                 51 
                 81 
                 09 
                  9 
                 1000 
               
               
                 1010010 
                 52 
                 82 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1010011 
                 53 
                 83 
                 2D 
                 45 
                 0010 
               
               
                 1010100 
                 54 
                 84 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1010101 
                 55 
                 85 
                 1D 
                 29 
                 0100 
               
               
                 1010110 
                 56 
                 86 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1010111 
                 57 
                 87 
                 14 
                 20 
                 0100 
               
               
                 1011000 
                 58 
                 88 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011001 
                 59 
                 89 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011010 
                 5A 
                 90 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011011 
                 5B 
                 91 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011100 
                 5C 
                 92 
                 21 
                 33 
                 0010 
               
               
                 1011101 
                 5D 
                 93 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011110 
                 5E 
                 94 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1011111 
                 5E 
                 95 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1100000 
                 60 
                 96 
                 40 
                 64 
                 1000 
               
               
                 1100001 
                 61 
                 97 
                 3A 
                 58 
                 0001 
               
               
                 1100010 
                 62 
                 98 
                 34 
                 52 
                 0001 
               
               
                 1100011 
                 63 
                 99 
                 0A 
                 10 
                 1000 
               
               
                 1100100 
                 64 
                 100 
                 04 
                  4 
                 1000 
               
               
                 1100101 
                 65 
                 101 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1100110 
                 66 
                 102 
                 24 
                 36 
                 0010 
               
               
                 1100111 
                 67 
                 103 
                 2E 
                 46 
                 0010 
               
               
                 1101000 
                 68 
                 104 
                 28 
                 40 
                 0010 
               
               
                 1101001 
                 69 
                 105 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1101010 
                 6A 
                 106 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1101011 
                 6B 
                 107 
                 1E 
                 30 
                 0100 
               
               
                 1101100 
                 6C 
                 108 
                 01 
                  1 
                 1000 
               
               
                 1101101 
                 6D 
                 109 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1101110 
                 6E 
                 110 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1101111 
                 6F 
                 111 
                 15 
                 21 
                 0100 
               
               
                 1110000 
                 70 
                 112 
                 0F 
                 15 
                 1000 
               
               
                 1110001 
                 71 
                 113 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1110010 
                 72 
                 114 
                 1A 
                 26 
                 0100 
               
               
                 1110011 
                 73 
                 115 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1110100 
                 74 
                 116 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1110101 
                 75 
                 117 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1110110 
                 76 
                 118 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1110111 
                 77 
                 119 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1111000 
                 78 
                 120 
                 32 
                 50 
                 0001 
               
               
                 1111001 
                 79 
                 121 
                 22 
                 34 
                 0010 
               
               
                 1111010 
                 7A 
                 122 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1111011 
                 7B 
                 123 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1111100 
                 7C 
                 124 
                 18 
                 24 
                 0100 
               
               
                 1111101 
                 7D 
                 125 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1111110 
                 7E 
                 126 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                 1111111 
                 7F 
                 127 
                 N/A 
                 Mult 
                 1111 
               
               
                   
                   
                   
                   
                 Error 
               
               
                   
               
            
           
         
       
     
     Multiple errors are checked using several methods that guarantee detection of all two-bit errors. The R 1  channel parity bits are used to cross check the location of a single bit error. Absence of a parity error with a non-zero syndrome indicates a multiple bit error. A syndrome that does not map to a valid error location indicates a multiple bit error. 
     The method of operation of the data error correction code decoder is further illustrated in the flow chart depicted in FIGS. 22 a  and  22   b . The Data ECC Decoder  1162  (FIG. 17) first checks if multiple errors have been detected by the Control ECC Decoder  1160  (FIG. 17) as shown in the Multiple Errors inquiry step  1350  (FIG. 22 a ). This is determined by examining the MultError input flag. If multiple errors are detected in inquiry step  1350  the Data ECC Decoder  1162  (FIG. 17) does not attempt decoding and terminates through step  1370  setting the MultError and Error status flags and through step  1368 . If no multiple errors were detected by inquiry step  1350  the Data ECC Decoder  1162  calculates the syndrome as shown in step  1352 . The syndrome value is checked as depicted in inquiry step  1354 . If the syndrome value is zero, the Data ECC Decoder  1162  checks if the Error flag is set as shown in inquiry step  1372 . The Error flag indicates an error was detected in any channel by checking the parity. If an error was detected in inquiry step  1372  the Data ECC Decoder  1162  terminates through step  1370  setting the MultError and Error status flags and through step  1368  because it is not possible to get a zero syndrome value and a channel error without having multiple errors. If the Error flag is not set in inquiry step  1372 , then the Data ECC Decoder  1162  terminates through the No Data Error step  1372  and through step  1368  because no error was detected and no correction is required. If the syndrome value checked in inquiry step  1354  is non-zero then an error was detected. The Data ECC Decoder  1162  then checks the Error flag in inquiry step  1356  to determine if a parity error has been found in any channel. If it is determined in inquiry step  1356  that the Error flag is not set, the Data ECC Decoder  1162  terminates through step  1370  setting the MultError and Error status flags and through step  1368  because it is not possible obtain a non-zero syndrome value and no channel error without having multiple errors. If the Error flag detected an error in inquiry step  1356  then the Data ECC Decoder  1162  proceeds to calculate the error location in step  1358  because the syndrome and Error flags are both consistent in detecting an error. As shown in the Calculate Error Location step  1358 , the Data ECC decoder  1162  calculates the error location from the syndrome value which is then checked as depicted in the Valid Error Location inquiry step  1360  (FIG. 22 b ). If it is determined in inquiry step  1360  that the error location is not valid, i.e., does not correspond to any of the 72 received bits in RXP&lt; 71 : 0 &gt;, the Data ECC Decoder  1162  terminates though step  1370  setting the MultError and Error status flags and through step  1368  because it is not possible to have a bad error location without having multiple errors. If the error location is validated by inquiry step  1360 , the Data ECC Decoder  1162  calculates which channel the error occurred in as depicted in the Calculate Error Channel step  1362 . The error channel is calculated from the error location and the known mapping of error location to transmitted channel. After the error channel (EC) is determined as depicted in step  1362 , the error channel is checked against the channel error (CE) determined by the parity checks in each channel as depicted in inquiry step  1364 . If the two error channel indicators do not match, as determined per inquiry step  1364 , the Data ECC Decoder  1162  terminates through step  1370  setting the MultError and Error status flags and through step  1368  because it is not possible to get inconsistent channel errors without having multiple errors. If the channel error indicators match, as depicted in inquiry step  1364 , the Data ECC Decoder  1162  corrects the single bit error in step  1366 . The bit value at the calculated error location is flipped. The Data ECC Decoder  1162  then sets the error flag to false indicating an error is no longer present and sets the corrected data (CorD) flag indicating a single bit error has been corrected in the data field. The Data ECC Decoder  1162  then terminates through step  1368 . 
     XGMII Receive Controller 
     The XGMII receive control logic  1164  (See FIG. 17) translates the receive state and data into XGMII format for delivery to the MAC  1011  within the system interface  1010  (FIG.  12 ). Mapping into the XGMII format is straightforward. Any uncorrected physical coding sublayer cell error received during a packet will generate corresponding symbol error(s) on the equivalent bytes on the XGMII. Cell errors received during idle will typically be discarded. In the event the XGMII interface requires cell errors to be identified to the MAC as a false carrier event, they should be so indicated. 
     Receiver Monitors and Statistics 
     The Receive State Sync Controller  1166  (FIG. 17) assures that synchronization of the received signal is obtained in the correct sequence and monitor the errors within the channel to declare the link down when the error rate reaches an unsustainable level. Synchronization is first achieved within each channel (Word Lock), then inter-channel alignment (Cell Lock), and then scrambler synchronization (Sync Lock). Any loss of synchronization by the lower process will automatically cause loss of the higher level synchronization states. The status of each of the receive blocks is indicated by flags and are collectively shown as RxFlags (FIG.  17 ). Word Lock indicates if word synchronization has been achieved in each channel. Cell Lock indicates that the complete physical coding sublayer cell is correctly aligned across all channels. Sync Lock in each channel indicates that the scramblers have acquired their correct states. 
     After acquisition, receive logic goes into a track mode where errors are detected and counted. Parity errors within each channel are indicated by the channel error variable, CE&lt;a:d&gt; (FIG.  1 ). The corrected control flag, CorC, indicates single control errors. Single data field errors are indicated by the corrected data flag, CorD. Multiple bit errors are indicated by the MultError flag, which can be generated either by the Control FEC Decoder or the Data FEC Decoder. MultError generates symbol error(s) on the receiver XGMII if they occur in a data frame. 
     The two single bit error flags (corrected control, CorC and corrected data, CorD) should be summed. A channel error mask (CE&lt;a:d&gt;) is used to keep separate counters on single bit errors per channel. 
     Multiple bit errors (100% of two-bit errors, lower probability of detection with higher bit errors) are accumulated in a separate counter. The error location of multiple bit errors is not guaranteed using physical coding sublayer encoding so only a single counter is employed in a preferred embodiment. 
     Inter-Channel Skew Circuit 
     An inter-channel skew circuit may optionally be inserted between the physical coding sublayer  1014  and the SERDES logic  1016  in each of the channels within the transmit path. The inter-channel skew circuit offsets the bits in each channel in time so that a burst of noise across all channels will produce errors that fall in different cells and thus can be corrected. An offset of one bit time between channels has been demonstrated to provide good results for NEXT and FEXT terms. 
     An exemplary skew circuit  1400  is illustrated in FIG.  23 . The illustrated skew circuit  1400  provides no skew, a single bit of skew, 2 bits of skew or three bits of skew to provide a single bit of skew between each of the four channels in the preferred embodiment discussed herein. Referring to FIG. 23 the skew circuit includes a pipeline register  1402  that receives 10 bit words from the physical coding sublayer logic  1014  (FIG.  13 ). The least significant bit is identified in FIG. 23 as bit  0  and the most significant bit is identified as bit  9 . Bits  7 ,  8  and  9  of the received data word are coupled to a delay register. A three bit delay register is depicted to provide up to three bits of skew although it should be appreciated that the delay register  1404  may accommodate a larger number of bits should it be desired to provide more than three bits of skew. The outputs of the pipeline register  1402  and the delay register  1404  are coupled to inputs of multiplex logic  1406 . The multiplex logic  1406  selects the bits to be output in response to the skew control inputs to such logic. More specifically, in response to a first skew control input, the multiplex logic provides as an output the 10 bits appearing at the input to the pipeline register  1402 . This first skew control input thus provides no skew. In response to a second skew control input, the multiplex logic  1406  outputs a 10 bit word that includes bit  9  from the delay register  1404  and bits  0  through  8  of the pipeline register  1402  thus introducing a single bit of skew. In response to a third skew control input, the multiplex logic  1406  outputs a 10 bit word that includes bits  8  and  9  from the delay register  1404  and bits  0  through  7  from the pipeline register  1402  thus introducing two bits of skew. Finally, in response to a fourth skew control input the multiplex logic  1406  outputs a 10 bit word that includes bits  7 ,  8  and  9  from the delay register  1404  and bits  0  through  6  from the pipeline register  1402  thus introducing three bits of skew. 
     In the preferred embodiment, no skew is provided in channel A, 1 bit of skew is introduced into channel B, 2 bits of skew are introduced into channel C and 3 bits of skew are introduced into channel D. 
     It will be apparent to those of ordinary skill in the art that modifications to and variations of the above described methods and apparatus for minimizing the susceptability to burst errors may be made without departing from the inventive concepts disclosed herein. Accordingly, the invention should not be viewed as limited except as by the scope and spirit of the appended claims.