Patent Publication Number: US-2012028459-A1

Title: Manufacturing process of circuit substrate

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims the priority benefit of Taiwan application serial no. 99125144, filed on Jul. 29, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a manufacturing process of an electronic component, and more particularly, to a manufacturing process of a circuit substrate. 
     2. Description of Related Art 
     Circuit substrate is one of the most commonly used components in today&#39;s semiconductor packaging technology. A circuit substrate is formed by alternatively stacking a plurality of patterned conductive layers and a plurality of dielectric layers, wherein every two patterned conductive layers may be electrically connected with each other through a conductive via. How to effectively simplify the manufacturing process of circuit substrate has become one of the major subjects along with the increase in the circuit density of circuit substrate. 
     SUMMARY OF THE INVENTION 
     Accordingly, the present invention is directed to a circuit substrate manufacturing process with reduced manufacturing time. 
     The present invention provides a circuit substrate manufacturing process. First, a conductive structure is provided. The conductive structure includes a first patterned conductive layer, a first dielectric layer, a second dielectric layer, a first conductive layer, and a second conductive layer. The first dielectric layer and the second dielectric layer are respectively disposed on two opposite surfaces of the first patterned conductive layer. The first conductive layer and the second conductive layer are respectively disposed on the first dielectric layer and the second dielectric layer, wherein the first dielectric layer is between the first patterned conductive layer and the first conductive layer, and the second dielectric layer is between the first patterned conductive layer and the second conductive layer. Then, a conductive via is formed at the conductive structure, wherein the conductive via electrically connects at least two of the first patterned conductive layer, the first conductive layer, and the second conductive layer. Next, the first conductive layer and the second conductive layer are patterned to respectively form a second patterned conductive layer and a third patterned conductive layer. 
     As described above, in the circuit substrate manufacturing process provided by the present invention, a conductive structure having a patterned conductive layer is first provided, and then a conductive via is formed at the conductive structure and conductive layers on the surfaces of the conductive structure are patterned. Thereby, the manufacturing process is simplified and the manufacturing time is shortened. 
     In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanying figures are described in detail below. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. 
         FIGS. 1A-1F  is a flowchart of a circuit substrate manufacturing process according to an embodiment of the present invention. 
         FIGS. 2A-2E  is a flowchart of a circuit substrate manufacturing process according to another embodiment of the present invention. 
         FIGS. 3A-3C  is a flowchart illustrating some steps in a circuit substrate manufacturing process according to another embodiment of the present invention. 
         FIGS. 4A-4F  is a flowchart of a circuit substrate manufacturing process according to another embodiment of the present invention. 
         FIG. 5 ,  FIG. 6 , and  FIG. 7  are respectively top views of  FIG. 4B ,  FIG. 4D , and  FIG. 4F . 
     
    
    
     DESCRIPTION OF THE EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
       FIGS. 1A-1F  is a flowchart of a circuit substrate manufacturing process according to an embodiment of the present invention. First, referring to  FIG. 1A , a first dielectric layer  110 , a first conductive layer  120   a,  and a third conductive layer  130   a  are provided, wherein the first conductive layer  120   a  and the third conductive layer  130   a  are respectively disposed on two opposite surfaces of the first dielectric layer  110 . Referring to  FIG. 1B , a mask layer  140  is formed to cover the first conductive layer  120   a.  Referring to  FIG. 3C , the third conductive layer  130   a  is patterned to form a first patterned conductive layer  130   b.    
     Then, referring to  FIG. 1D , after the first patterned conductive layer  130   b  is formed, the mask layer  140  is removed, and a second dielectric layer  150  and a second conductive layer  160   a  are formed on the first patterned conductive layer  130   b,  so that the first patterned conductive layer  130   b  is between the first dielectric layer  110  and the second dielectric layer  150 , and the second dielectric layer  150  is between the second conductive layer  160   a  and the first patterned conductive layer  130   b.    
     A conductive structure  50  is formed through foregoing steps. The conductive structure  50  includes the first patterned conductive layer  130   b,  the first dielectric layer  110 , the second dielectric layer  150 , the first conductive layer  120   a,  and the second conductive layer  160   a.  The first dielectric layer  110  and the second dielectric layer  150  are respectively disposed on two opposite surfaces of the first patterned conductive layer  130   b.  The first conductive layer  120   a  and the second conductive layer  160   a  are respectively disposed on the first dielectric layer  110  and the second dielectric layer  150 , wherein the first dielectric layer  110  is between the first patterned conductive layer  130   b  and the first conductive layer  120   a,  and the second dielectric layer  150  is between the first patterned conductive layer  130   b  and the second conductive layer  160   a.    
     Referring to  FIG. 1E , conductive vias  170  (four as illustrated) are formed at the conductive structure  50  (as shown in  FIG. 1D ), wherein the conductive vias  170  electrically connect at least two of the first patterned conductive layer  130   b,  the first conductive layer  120   a,  and the second conductive layer  160   a.  In the present embodiment, some of the conductive vias  170  (two as illustrated) are extended from the first conductive layer  120   a  to the first patterned conductive layer  130   b  via the first dielectric layer  110  to electrically connect the first conductive layer  120   a  and the first patterned conductive layer  130   b,  and the rest conductive vias  170  (two as illustrated) are extended from the second conductive layer  160   a  to the first patterned conductive layer  130   b  via the second dielectric layer  150  to electrically connect the second conductive layer  160   a  and the first patterned conductive layer  130   b.    
     To be specific, the conductive vias  170  illustrated in  FIG. 1E  may be formed by first forming a blind hole  172  at the conductive structure  50  (as shown in  FIG. 1D ) and then electroplating a metal layer  174  on the internal wall of the blind hole  172 . The pattern of the conductive vias  170  is not limited in the present invention, and in another embodiment, the conductive vias  170  may also be extended from the first conductive layer  120   a  to the second conductive layer  160   a  via the first dielectric layer  110 , the first patterned conductive layer  130   b,  and the second dielectric layer  150  to electrically connect the first conductive layer  120   a,  the second conductive layer  160   a,  and the first patterned conductive layer  130   b.    
     Referring to  FIG. 1F , the first conductive layer  120   a  and the second conductive layer  160   a  are patterned to respectively form a second patterned conductive layer  120   b  and a third patterned conductive layer  160   b,  so as to complete the manufacturing process of a circuit substrate  100 . The circuit substrate  100  includes the first patterned conductive layer  130   b,  the first dielectric layer  110 , the second dielectric layer  150 , the second patterned conductive layer  120   b,  the third patterned conductive layer  160   b,  and the conductive vias  170 . 
     The first dielectric layer  110  and the second dielectric layer  150  are respectively disposed on two opposite surfaces of the first patterned conductive layer  130   b.  The second patterned conductive layer  120   b  and the third patterned conductive layer  160   b  are respectively disposed on the first dielectric layer  110  and the second dielectric layer  150 , wherein the first dielectric layer  110  is between the first patterned conductive layer  130   b  and the second patterned conductive layer  120   b,  and the second dielectric layer  150  is between the first patterned conductive layer  130   b  and the third patterned conductive layer  160   b.    
     Some of the conductive vias  170  (two as illustrated) are extended from the second patterned conductive layer  120   b  to the first patterned conductive layer  130   b  via the first dielectric layer  110  to electrically connect the second patterned conductive layer  120   b  and the first patterned conductive layer  130   b,  and the rest conductive vias  170  (two as illustrated) are extended from the third patterned conductive layer  160   b  to the first patterned conductive layer  130   b  via the second dielectric layer  150  to electrically connect the third patterned conductive layer  160   b  and the first patterned conductive layer  130   b.    
     In the present embodiment, the material of the first dielectric layer  110  may be cured resin, and the material of the second dielectric layer  150  may be semi-cured resin. In addition, the material of the first patterned conductive layer  130   b,  the second patterned conductive layer  120   b,  and the third patterned conductive layer  160   b  may be copper. 
       FIGS. 2A-2E  is a flowchart of a circuit substrate manufacturing process according to another embodiment of the present invention. First, referring to  FIG. 2A , a first dielectric layer  210  and a third conductive layer  230   a  are provided, wherein the third conductive layer  230   a  is disposed on the first dielectric layer  210 . Referring to  FIG. 2B , the third conductive layer  230   a  is patterned to form a first patterned conductive layer  230   b.    
     Then, referring to  FIG. 2C , a first conductive layer  220   a  is formed on the first dielectric layer  210 , and a second dielectric layer  250  and a second conductive layer  260   a  are formed on the first patterned conductive layer  230   b,  so that the first dielectric layer  210  is between the first patterned conductive layer  230   b  and the first conductive layer  220   a,  the first patterned conductive layer  230   b  is between the first dielectric layer  210  and the second dielectric layer  250 , and the second dielectric layer  250  is between the first patterned conductive layer  230   b  and the second conductive layer  260   a.    
     A conductive structure  60  is formed through foregoing steps. The conductive structure  60  includes the first patterned conductive layer  230   b,  the first dielectric layer  210 , the second dielectric layer  250 , the first conductive layer  220   a,  and the second conductive layer  260   a.  The first dielectric layer  210  and the second dielectric layer  250  are respectively disposed on two opposite surfaces of the first patterned conductive layer  230   b.  The first conductive layer  220   a  and the second conductive layer  260   a  are respectively disposed on the first dielectric layer  210  and the second dielectric layer  250 , wherein the first dielectric layer  210  is between the first patterned conductive layer  230   b  and the first conductive layer  220   a,  and the second dielectric layer  250  is located between the first patterned conductive layer  230   b  and the second conductive layer  260   a.    
     Referring to  FIG. 2D , conductive vias  270  (two as illustrated) are formed at the conductive structure  60  (as shown in  FIG. 2C ), wherein the conductive vias  270  electrically connect at least two of the first patterned conductive layer  230   b,  the first conductive layer  220   a,  and the second conductive layer  260   a.  In the present embodiment, the conductive vias  270  are extended from the first conductive layer  220   a  to the second conductive layer  260   a  via the first dielectric layer  210 , the first patterned conductive layer  230   b,  and the second dielectric layer  250  to electrically connect the first conductive layer  220   a,  the second conductive layer  260   a,  and the first patterned conductive layer  230   b.    
     To be specific, the conductive vias  270  illustrated in  FIG. 2D  may be formed by first forming a through hole  272  at the conductive structure  60  (as shown in  FIG. 2C ) and then electroplating a metal layer  274  on the internal wall of the through hole  272 . The pattern of the conductive vias  270  is not limited in the present invention, and in another embodiment, the conductive vias  270  may also be extended from the first conductive layer  220   a  to the first patterned conductive layer  230   b  via the first dielectric layer  210  but not extended to the second conductive layer  260   a,  so as to electrically connect the first conductive layer  220   a  and the first patterned conductive layer  230   b.  The conductive vias  270  may also be extended from the second conductive layer  260   a  to the first patterned conductive layer  230   b  via the second dielectric layer  250  but not extended to the first conductive layer  220   a,  so as to electrically connect the second conductive layer  260   a  and the first patterned conductive layer  230   b.    
     Referring to  FIG. 2E , the first conductive layer  220   a  and the second conductive layer  260   a  are patterned to respectively form a second patterned conductive layer  220   b  and a third patterned conductive layer  260   b,  so as to complete the manufacturing process of a circuit substrate  200 . The circuit substrate  200  includes the first patterned conductive layer  230   b,  the first dielectric layer  210 , the second dielectric layer  250 , the second patterned conductive layer  220   b,  the third patterned conductive layer  260   b,  and the conductive vias  270 . 
     The first dielectric layer  210  and the second dielectric layer  250  are respectively disposed on two opposite surfaces of the first patterned conductive layer  230   b.  The second patterned conductive layer  220   b  and the third patterned conductive layer  260   b  are respectively disposed on the first dielectric layer  210  and the second dielectric layer  250 , wherein the first dielectric layer  210  is between the first patterned conductive layer  230   b  and the second patterned conductive layer  220   b,  and the second dielectric layer  250  is between the first patterned conductive layer  230   b  and the third patterned conductive layer  260   b.    
     The conductive vias  270  are extended from the second patterned conductive layer  220   b  to the third patterned conductive layer  260   b  via the first dielectric layer  210 , the first patterned conductive layer  230   b,  and the second dielectric layer  250  to electrically connect the second patterned conductive layer  220   b,  the third patterned conductive layer  260   b,  and the first patterned conductive layer  230   b.    
     In the present embodiment, the material of the first dielectric layer  210  may be cured resin, and the material of the second dielectric layer  250  may be semi-cured resin. However, in another embodiment, the material of the first dielectric layer  210  may also be semi-cured resin. Besides, the material of the first patterned conductive layer  230   b,  the second patterned conductive layer  220   b,  and the third patterned conductive layer  260   b  may be copper or other suitable conductive metals. 
       FIGS. 3A-3C  is a flowchart illustrating some steps in a circuit substrate manufacturing process according to another embodiment of the present invention. First, referring to  FIG. 3A , two first dielectric layers  310  are disposed on a de-bonding layer  380 , and two third conductive layers  330   a  are respectively disposed on the first dielectric layers  310  so that each of the first dielectric layers  310  is between the de-bonding layer  380  and the corresponding third conductive layer  330   a.  Then, referring to  FIG. 3B , the third conductive layers  330   a  are patterned to form two first patterned conductive layers  330   b.  Finally, each of the first dielectric layers  310  is de-bonded from the de-bonding layer  380  to obtain a structure as illustrated in  FIG. 3C . After that, the manufacturing process illustrated in  FIGS. 2B-2E  is carried out on this structure. 
       FIGS. 4A-4F  is a flowchart of a circuit substrate manufacturing process according to another embodiment of the present invention, and  FIG. 5 ,  FIG. 6 , and  FIG. 7  are respectively top views of  FIG. 4B ,  FIG. 4D , and  FIG. 4F . First, referring to  FIG. 4A , a third conductive layer  430   a  is provided. Referring to  FIG. 4B  and  FIG. 5 , the third conductive layer  430   a  is patterned through etching, pressing, or drilling to form a first patterned conductive layer  430   b.  referring to  FIG. 4C , a first dielectric layer  410  and a first conductive layer  420   a  and a second dielectric layer  450  and a second conductive layer  460   a  are respectively formed on two opposite surfaces of the first patterned conductive layer  430   b,  so that the first patterned conductive layer  430   b  is between the first dielectric layer  410  and the second dielectric layer  450 , the first dielectric layer  410  is between the first conductive layer  420   a  and the first patterned conductive layer  430   b,  and the second dielectric layer  450  is between the second conductive layer  460   a  and the first patterned conductive layer  430   b.    
     A conductive structure  70  is formed through foregoing steps. The conductive structure  70  includes the first patterned conductive layer  430   b,  the first dielectric layer  410 , the second dielectric layer  450 , the first conductive layer  420   a,  and the second conductive layer  460   a.  The first dielectric layer  410  and the second dielectric layer  450  are respectively disposed on two opposite surfaces of the first patterned conductive layer  430   b.  The first conductive layer  420   a  and the second conductive layer  460   a  are respectively disposed on the first dielectric layer  410  and the second dielectric layer  450 , wherein the first dielectric layer  410  is between the first patterned conductive layer  430   b  and the first conductive layer  420   a,  and the second dielectric layer  450  is between the first patterned conductive layer  430   b  and the second conductive layer  460   a.    
     Referring to  FIG. 4E , conductive vias  470  (two as illustrate) are formed at the conductive structure  70  (as shown in  FIG. 4C ), wherein the conductive vias  470  electrically connect at least two of the first patterned conductive layer  430   b,  the first conductive layer  420   a,  and the second conductive layer  460   a.  In the present embodiment, the conductive vias  470  are extended from the first conductive layer  420   a  to the second conductive layer  460   a  via the first dielectric layer  410 , the first patterned conductive layer  430   b,  and the second dielectric layer  450  to electrically connect the first conductive layer  420   a,  the second conductive layer  460   a,  and the first patterned conductive layer  430   b.    
     To be specific, the conductive vias  470  illustrated in  FIG. 4E  may be formed by first forming a through hole  472  (as shown in  FIG. 4D  and  FIG. 6 ) at the conductive structure  70  (as shown in  FIG. 4C ) and then electroplating a metal layer  474  on the internal wall of the through hole  472 . The pattern of the conductive vias  470  is not limited in the present invention, and in another embodiment, the conductive vias  470  may also be extended from the first conductive layer  420   a  to the first patterned conductive layer  430   b  via the first dielectric layer  410  but not extended to the second conductive layer  460   a,  so as to electrically connect the first conductive layer  420   a  and the first patterned conductive layer  430   b.  The conductive vias  470  may also be extended from the second conductive layer  460   a  to the first patterned conductive layer  430   b  via the second dielectric layer  450  but not extended to the first conductive layer  420   a,  so as to electrically connect the second conductive layer  460   a  and the first patterned conductive layer  430   b.    
     Referring to  FIG. 4F  and  FIG. 7 , the first conductive layer  420   a  and the second conductive layer  460   a  are patterned to respectively form a second patterned conductive layer  420   b  and a third patterned conductive layer  460   b,  so as to complete the manufacturing process of a circuit substrate  400 . The circuit substrate  400  includes the first patterned conductive layer  430   b,  the first dielectric layer  410 , the second dielectric layer  450 , the second patterned conductive layer  420   b,  the third patterned conductive layer  460   b,  and the conductive vias  470 . 
     The first dielectric layer  410  and the second dielectric layer  450  are respectively disposed on two opposite surfaces of the first patterned conductive layer  430   b.  The second patterned conductive layer  420   b  and the third patterned conductive layer  460   b  are respectively disposed on the first dielectric layer  410  and the second dielectric layer  450 , wherein the first dielectric layer  410  is between the first patterned conductive layer  430   b  and the second patterned conductive layer  420   b,  and the second dielectric layer  450  is between the first patterned conductive layer  430   b  and the third patterned conductive layer  460   b.    
     The conductive vias  470  are extended from the second patterned conductive layer  420   b  to the third patterned conductive layer  460   b  via the first dielectric layer  410 , the first patterned conductive layer  430   b,  and the second dielectric layer  450  to electrically connect the second patterned conductive layer  420   b,  the third patterned conductive layer  460   b,  and the first patterned conductive layer  230   b.    
     To be specific, the first patterned conductive layer  430   b  in  FIG. 4F  has an opening H. One of the conductive vias  470  passes through the first patterned conductive layer  430   b  via the opening H and is not electrically connected to the first patterned conductive layer  430   b,  so that the conductive via  470  can transmit signals between the second patterned conductive layer  420   b  and the third patterned conductive layer  460   b.  The other conductive via  470  in  FIG. 4F  is electrically connected to the second patterned conductive layer  420   b,  the third patterned conductive layer  460   b,  and the first patterned conductive layer  230   b,  so that the second patterned conductive layer  420   b  and the third patterned conductive layer  460   b  can be grounded through the third patterned conductive layer  460   b  or heat generated on the second patterned conductive layer  420   b  and the third patterned conductive layer  460   b  can be dissipated through the third patterned conductive layer  460   b.    
     In the present embodiment, the material of the first dielectric layer  410  and the second dielectric layer  450  may be semi-cured resin, and the material of the first patterned conductive layer  430   b,  the second patterned conductive layer  420   b,  and the third patterned conductive layer  460   b  may be copper or other suitable conductive metals. 
     In summary, in the circuit substrate manufacturing process provided by the present invention, a conductive structure having a patterned conductive layer is first provided, and then a conductive via is formed at the conductive structure and conductive layers on surfaces of the conductive structure are patterned. Thereby, the manufacturing process is simplified and the manufacturing time is shortened. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.