Patent Publication Number: US-10784823-B2

Title: High-voltage power amplification system

Description:
CROSS-REFERENCE TO RELATED APPLICATION(S) 
     This application is a continuation of U.S. application Ser. No. 15/896,037 filed Feb. 13, 2018, entitled RADIO-FREQUENCY AMPLIFICATION SYSTEMS, DEVICES AND METHODS, which is a continuation of U.S. application Ser. No. 14/869,957 filed Sep. 29, 2015, entitled RADIO-FREQUENCY POWER AMPLIFIERS DRIVEN BY BOOST CONVERTER, which claims priority to and the benefit of the filing date of U.S. Provisional Application No. 62/116,452 filed Feb. 15, 2015, entitled RADIO-FREQUENCY POWER AMPLIFIERS DRIVEN BY BOOST CONVERTER, the benefits of the filing dates of which are hereby claimed and the disclosures of which are hereby expressly incorporated by reference herein in their entirety. 
    
    
     BACKGROUND 
     Field 
     The present disclosure generally relates to power amplifiers for radio-frequency (RF) applications. 
     Description of the Related Art 
     In radio-frequency (RF) applications, an RF signal to be transmitted is typically generated by a transceiver. Such an RF signal can then be amplified by a power amplifier (PA), and the amplified RF signal can be routed to an antenna for transmission. 
     SUMMARY 
     In some implementations, the present disclosure relates to a power amplification system that includes a supply system configured to provide a high-voltage (HV) supply signal based on a battery voltage, and a power amplifier (PA) configured to receive the HV supply signal and amplify a radio-frequency (RF) signal. The power amplification system further includes an output path configured to route the amplified RF signal to a filter. 
     In some embodiments, the output path can be substantially free of an impedance transformation circuit. The power amplification system can be configured to operate as an average power tracking (APT) system. The supply system can include a boost DC/DC converter configured to generate the HV supply signal based on the battery voltage. The HV supply signal can be selected such that impedances of the PA and the filter match sufficiently to allow the output path to be substantially free of the impedance transformation circuit. The impedance of the PA can have a value that is greater than approximately 40 Ohms, such as a value of approximately 50 Ohms. 
     In some embodiments, the PA can include a heterojunction bipolar transistor (HBT). Such an HBT can include a gallium arsenide (GaAs) device. The HV supply signal can be provided to a collector of the HBT as VCC. 
     In some embodiments, the filter can be a transmit (Tx) filter configured to operate in a corresponding Tx frequency band. The Tx filter can be part of a duplexer configured to operate in the Tx frequency band and a corresponding receive (Rx) frequency band. 
     In some embodiments, the power amplification system can further include one or more additional PAs, with each being configured to receive the HV supply signal and amplify an RF signal. The power amplification system can further include one or more output paths, with each being configured to receive and route the amplified RF signal of the corresponding additional PA to a corresponding filter. The additional output path can be substantially free of an impedance transformation circuit. 
     In some embodiments, each filter can have associated with it a corresponding PA. The power amplification system can be substantially free of a band selection switch between the PAs and the filters. The power amplification system can have a lower loss than another power amplifier system having similar band handling capability but in which the PAs are operated in low voltage. The power amplification system can be an average power tracking (APT) system, and the other power amplifier system can be an envelope tracking (ET) system. The APT system can have an overall efficiency that is greater than an overall efficiency of the ET system. 
     In accordance with a number of implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a supply system configured to provide a high-voltage (HV) supply signal based on a battery voltage. The power amplification system further includes a plurality of power amplifiers (PAs), with each PA being configured to receive the HV supply signal and amplify a radio-frequency (RF) signal. The power amplification system further includes an output path configured to route the amplified RF signal from the corresponding PA to a corresponding filter. 
     In some embodiments, each of the plurality of PAs can be further configured to drive approximately a characteristic load impedance of the corresponding output filter. Each output path can be substantially free of an impedance transformation circuit between the corresponding PA and output filter. The power amplification system can be substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. The RF module can be, for example, a front-end module (FEM). 
     In some teachings, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components. The FEM further includes a power amplification system implemented on the packaging substrate. The power amplification system includes a supply system configured to provide a high-voltage (HV) supply signal based on a battery voltage. The power amplification system further includes a plurality of power amplifiers (PAs), with each PA being configured to receive the HV supply signal and amplify a radio-frequency (RF) signal. The power amplification system further includes an output path configured to route the amplified RF signal from the corresponding PA to a corresponding filter. The wireless device further includes an antenna in communication with the FEM, with the antenna being configured to transmit the amplified RF signal. 
     According to a number of implementations, the present disclosure relates to a power amplification system that includes a power amplifier (PA) configured to receive and amplify a radio-frequency (RF) signal, and a filter coupled to the PA and configured to condition the amplified RF signal. The PA is further configured to drive approximately a characteristic load impedance of the filter. 
     In some embodiments, the PA can have an impedance that is greater than approximately 40 Ohms. The impedance of the PA can have a value of approximately 50 Ohms. 
     In some embodiments, power amplification system can further include a supply system configured to provide a high-voltage (HV) supply to the PA. The supply system can include a boost DC/DC converter configured to generate the HV supply based on a battery voltage Vbatt. 
     In some embodiments, the PA can include a heterojunction bipolar transistor (HBT). The HBT can be, for example, a gallium arsenide (GaAs) device. The HV supply can be provided to a collector of the HBT as VCC. 
     In some embodiments, the filter can be a transmit (Tx) filter configured to operate in a corresponding Tx frequency band. The Tx filter can be part of a duplexer configured to operate in the Tx frequency band and a corresponding receive (Rx) frequency band. 
     In some embodiments, the filter can be coupled to the PA by an output path that is substantially free of an impedance transformation circuit. 
     In some embodiments, the power amplification system can further include one or more additional PAs, with each being configured to operate with the HV supply and amplify a corresponding RF signal. The power amplification system can further include a filter coupled to each of the one or more additional PAs and configured to condition the corresponding amplified RF signal. Each of the one or more additional PAs can be further configured to drive approximately a characteristic load impedance of the corresponding filter. Each of the one or more additional filters can be coupled to the corresponding PA by an output path that is substantially free of an impedance transformation circuit. 
     In some embodiments, the PA and the one or more additional PAs can form M PAs. In some embodiments, the M PAs can be implemented on a single semiconductor die. The M PAs can be configured to operate in separate frequency bands. The system can be substantially free of a band selection switch between the M PAs and their corresponding filters. 
     In some embodiments, the power amplification system can be configured to operate as an average power tracking (APT) system. The APT system can have a lower loss than another power amplifier system having similar band handling capability but in which the PAs are operated in low voltage. The other power amplifier system can be an envelope tracking (ET) system. The APT system can have an overall efficiency that is greater than an overall efficiency of the ET system. 
     In some teachings, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal. The power amplification system further includes a filter coupled to each PA that is configured to drive approximately a characteristic load impedance of the filter. 
     In some embodiments, each PA can be configured to operate in a high-voltage (HV) supply mode. Each filter can be coupled to the corresponding PA by an output path that is substantially free of an impedance transformation circuit. 
     In some embodiments, the RF module can be substantially free of a band selection switch between the plurality of PAs and their corresponding filters. In some embodiments, the RF module can be, for example, a front-end module (FEM). 
     According to some implementations, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal. The power amplification system further includes a filter coupled to each PA that is configured to drive approximately a characteristic load impedance of the filter. The wireless device further includes an antenna in communication with the FEM, with the antenna being configured to transmit the amplified RF signal. 
     In some teachings, the present disclosure relates to a method for processing a radio-frequency (RF) signal. The method includes amplifying the RF signal with a power amplifier (PA), and routing the amplified RF signal to a filter. The method further includes operating the PA such that the PA drives approximately a characteristic impedance of the filter. 
     In some embodiments, the PA can have an impedance that is approximately 50 Ohms. In some embodiments, operating the PA can include supplying the PA with a high-voltage (HV). 
     In accordance with a number of teachings, the present disclosure relates to a power amplification system that includes a power amplifier (PA) configured to receive and amplify a radio-frequency (RF) signal. The power amplification system further includes an output filter coupled to the PA by an output path that is substantially free of an impedance transformation circuit. 
     In some embodiments, the PA can be further configured to drive approximately a characteristic load impedance of the output filter. The PA being configured to drive approximately the characteristic load impedance of the output filter can be effectuated by the PA being operated with a high-voltage (HV) supply. The output path being substantially free of an impedance transformation circuit can result in a reduction in loss by at least 0.5 dB between the PA and the output filter. 
     In some embodiments, the PA can have an impedance that is greater than approximately 40 Ohms. The impedance of the PA can have a value of approximately 50 Ohms. The impedance of the PA can result in a reduced current drain in the PA. The reduced current drain in the PA can allow the PA to be dimensioned smaller than another PA having a lower impedance. 
     In some embodiments, the power amplification system can further include a supply system configured to provide a high-voltage (HV) supply to the PA. The supply system can include a boost DC/DC converter configured to generate the HV supply based on a battery voltage Vbatt. 
     In some embodiments, the PA can include a heterojunction bipolar transistor (HBT). The HBT can be a gallium arsenide (GaAs) device. The HV supply can be provided to a collector of the HBT as VCC. 
     In some embodiments, the output filter can be a transmit (Tx) filter configured to operate in a corresponding Tx frequency band. The Tx filter can be part of a duplexer configured to operate in the Tx frequency band and a corresponding receive (Rx) frequency band. 
     In some embodiments, the power amplification system can further include one or more additional PAs, with each being configured to operate with the HV supply and amplify a corresponding RF signal. The power amplification system can further include an output filter coupled to each of the one or more additional PAs by an output path that is substantially free of an impedance transformation circuit. Each of the one or more additional PAs can be further configured to drive approximately a characteristic load impedance of the corresponding output filter. 
     In some embodiments, the PA and the one or more additional PAs can form M PAs. The M PAs can be implemented on a single semiconductor die. The M PAs can be configured to operate in separate frequency bands. 
     In some embodiments, the power amplification system can be substantially free of a band selection switch between the M PAs and their corresponding output filters. The power amplification system being substantially free of a band selection switch can result in a reduction in loss by at least 0.3 dB between a given PA and the corresponding output filter. 
     In some embodiments, the power amplification system can be configured to operate as an average power tracking (APT) system. The APT system can have a lower loss than another power amplifier system having similar band handling capability but in which the PAs are operated in low voltage. The other power amplifier system can be an envelope tracking (ET) system. The APT system can have an overall efficiency that is greater than an overall efficiency of the ET system. 
     According to some implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal. The power amplification system further includes an output filter coupled to each of the PAs by an output path that is substantially free of an impedance transformation circuit. 
     In some embodiments, each PA can be configured to operate in a high-voltage (HV) supply mode. Each PA can be further configured to drive approximately a characteristic load impedance of the corresponding output filter. 
     In some embodiments, the RF module can be substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. The RF module can be, for example, a front-end module (FEM). 
     In some implementations, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal. The power amplification system further includes an output filter coupled to each of the PAs by an output path that is substantially free of an impedance transformation circuit. The wireless device further includes an antenna in communication with the FEM, with the antenna being configured to transmit the amplified RF signal. 
     In some teachings, the present disclosure relates to a method for processing a radio-frequency (RF) signal. The method includes amplifying the RF signal with a power amplifier (PA), and routing the amplified RF signal to an output filter substantially without impedance transformation. The method further includes filtering the amplified RF signal with the output filter. 
     In some embodiments, amplifying the RF signal can include operating the PA such that the PA drives approximately a characteristic impedance of the output filter to allow the routing substantially without the impedance transformation. The PA can have an impedance that is approximately 50 Ohms. In some embodiments, operating the PA can include supplying the PA with a high-voltage (HV). 
     In accordance with some teachings, the present disclosure relates to a power amplification system that includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal in a frequency band. The power amplification system can further include an output filter coupled to each of the PAs by a separate output path such that the power amplification system is substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. 
     In some embodiments, each of the PAs can be further configured to drive approximately a characteristic load impedance of the corresponding output filter. Each PA being configured to drive approximately the characteristic load impedance of the corresponding output filter can be effectuated by the PA being operated with a high-voltage (HV) supply. The power amplification system being substantially free of the band selection switch can result in a reduction in loss by at least 0.3 dB between each PA and the corresponding output filter. 
     In some embodiments, each PA can have an impedance that is greater than approximately 40 Ohms. The impedance of each PA can have a value of approximately 50 Ohms. The impedance of each PA results in a reduced current drain in the PA. The reduced current drain in each PA can allow the PA to be dimensioned smaller than another PA having a lower impedance. 
     In some embodiments, the power amplification system can further include a supply system configured to provide a high-voltage (HV) supply to each PA. The supply system can include a boost DC/DC converter configured to generate the HV supply based on a battery voltage Vbatt. 
     In some embodiments, each PA can include a heterojunction bipolar transistor (HBT). The HBT can be a gallium arsenide (GaAs) device. The HV supply can be provided to a collector of the HBT as VCC. 
     In some embodiments, each output filter can be a transmit (Tx) filter configured to operate in a corresponding Tx frequency band. The Tx filter can be part of a duplexer configured to operate in the Tx frequency band and a corresponding receive (Rx) frequency band. 
     In some embodiments, each output filter can be coupled to the corresponding PA by an output path that is substantially free of an impedance transformation circuit. Each output path being substantially free of an impedance transformation circuit can result in a reduction in loss by at least 0.5 dB between the corresponding PA the output filter. 
     In some embodiments, the plurality of PAs can be implemented on a single semiconductor die. In some embodiments, the power amplification system can be configured to operate as an average power tracking (APT) system. The APT system can have a lower loss than another power amplifier system having similar band handling capability but in which the PAs are operated in low voltage. The other power amplifier system can be an envelope tracking (ET) system. The APT system can have an overall efficiency that is greater than an overall efficiency of the ET system. 
     In some teachings, the present disclosure relates to a radio-frequency (RF) module having a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal in a frequency band. The power amplification system further includes an output filter coupled to each of the PAs by a separate output path such that the power amplification system is substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. 
     In some embodiments, each PA can be configured to operate in a high-voltage (HV) supply mode. Each PA can be further configured to drive approximately a characteristic load impedance of the corresponding output filter. 
     In some embodiments, each output path can be substantially free of an impedance transformation circuit between the corresponding PA and output filter. In some embodiments, the RF module can be a front-end module (FEM). 
     According to a number of teachings, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs), with each PA being configured to receive and amplify a radio-frequency (RF) signal in a frequency band. The power amplification system further includes an output filter coupled to each of the PAs by a separate output path such that the power amplification system is substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. The wireless device further includes an antenna in communication with the FEM, with the antenna being configured to transmit the amplified RF signal. 
     In some teachings, the present disclosure relates to a method for processing a radio-frequency (RF) signal. The method includes amplifying the RF signal with a selected one of a plurality of power amplifiers (PAs), with the RF signal being in a frequency band. The method further includes routing the amplified RF signal to an output filter substantially without a band-selection switching operation. The method further includes filtering the amplified RF signal with the output filter. 
     In some embodiments, amplifying the RF signal can include operating the selected PA such that the PA drives approximately a characteristic impedance of the corresponding output filter to allow the routing substantially without an impedance transformation. The PA can have an impedance that is approximately 50 Ohms. 
     In some embodiments, operating the PA can include supplying the PA with a high-voltage (HV). 
     In some implementations, the present disclosure relates to a power amplifier die that includes a semiconductor substrate a plurality of power amplifiers (PAs) implemented on the semiconductor substrate. Each PA is configured to drive approximately a characteristic load impedance of a downstream component along an individual frequency band signal path. Each PA is sized smaller than a wide band PA configured to drive more than one of the frequency bands associated with the plurality of PAs. 
     In some embodiments, the downstream component can include an output filter. The individual frequency band signal path can be a narrow band signal path. Each of the PAs being configured to drive approximately the characteristic load impedance of the corresponding output filter can be effectuated by the PA being operated with a high-voltage (HV) supply. Each PA can have an impedance that is greater than approximately 40 Ohms. The impedance of each PA can have a value of approximately 50 Ohms. The impedance of each PA can result in a reduced current drain in the PA. The reduced current drain in each PA can allow the PA to be dimensioned smaller than another PA having a lower impedance. 
     In some embodiments, each PA can include a heterojunction bipolar transistor (HBT) such as a gallium arsenide (GaAs) device. The HBT can be configured to receive the HV supply through its collector as VCC. 
     In some embodiments, the PAs can be configured to operate in an average power tracking (APT) mode. The APT mode can result in a lower loss than another die having similar band handling capability but in which the PAs are operated in low voltage. The other die can be configured to operate in an envelope tracking (ET) mode. The APT mode can yield an overall efficiency that is greater than an overall efficiency of associated with the ET. 
     According to some implementations, the present disclosure relates to a radio-frequency (RF) module that includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs) implemented on a semiconductor substrate. Each PA is configured to drive approximately a characteristic load impedance of a downstream component along an individual frequency band signal path. Each PA is sized smaller than a wide band PA configured to drive more than one of the frequency bands associated with the plurality of PAs. 
     In some embodiments, each PA can be configured to operate in a high-voltage (HV) supply mode. In some embodiments, the downstream component can include an output filter. The output filter can be coupled to the corresponding PA by a separate output path such that the power amplification system is substantially free of a band selection switch between the plurality of PAs and their corresponding output filters. Each output path can be substantially free of an impedance transformation circuit between the corresponding PA and output filter. The RF module can be, for example, a front-end module (FEM). 
     In some teachings, the present disclosure relates to a wireless device that includes a transceiver configured to generate a radio-frequency (RF) signal, and a front-end module (FEM) in communication with the transceiver. The FEM includes a packaging substrate configured to receive a plurality of components, and a power amplification system implemented on the packaging substrate. The power amplification system includes a plurality of power amplifiers (PAs) implemented on a semiconductor substrate, with each PA being configured to drive approximately a characteristic load impedance of a downstream component along an individual frequency band signal path. Each PA is sized smaller than a wide band PA configured to drive more than one of the frequency bands associated with the plurality of PAs. The wireless device further includes an antenna in communication with the FEM, with the antenna being configured to transmit an amplified RF signal. 
     In some implementations, the present disclosure relates to a method for processing a radio-frequency (RF) signal. The method includes amplifying the RF signal with a selected one of a plurality of power amplifiers (PAs), with the selected PA driving approximately a characteristic load impedance of a downstream component along an individual frequency band signal path. The selected PA is sized smaller than a wide band PA configured to drive more than one of the frequency bands associated with the plurality of PAs. The method further includes routing the amplified RF signal to the downstream component. 
     In some embodiments, the downstream component can include an output filter. Amplifying the RF signal can include supplying the selected PA with a high-voltage (HV). 
     In accordance with some teachings, the present disclosure relates to a method for fabricating a power amplifier die. The method includes forming or providing a semiconductor substrate, and implementing a plurality of individual frequency band signal paths. The method further includes forming a plurality of power amplifiers (PAs) on the semiconductor substrate, with each PA being configured to drive approximately a characteristic load impedance of a downstream component along the corresponding individual frequency band signal path. Each PA is sized smaller than a wide band PA configured to drive more than one of the frequency bands associated with the plurality of PAs. 
     For purposes of summarizing the disclosure, certain aspects, advantages and novel features of the inventions have been described herein. It is to be understood that not necessarily all such advantages may be achieved in accordance with any particular embodiment of the invention. Thus, the invention may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other advantages as may be taught or suggested herein. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  depicts a wireless system or architecture having an amplification system. 
         FIG. 2  shows that the amplification system of  FIG. 1  can include a radio-frequency (RF) amplifier assembly having one or more power amplifiers (PAs). 
         FIGS. 3A-3E  show non-limiting examples of how each PA of  FIG. 2  can be configured. 
         FIG. 4  shows that in some embodiments, the amplification system of  FIG. 2  can be implemented as a high-voltage (HV) power amplification system. 
         FIG. 5  shows that in some embodiments, the HV power amplification system of  FIG. 4  can be configured to operate in an average power tracking (APT) mode. 
         FIG. 6  shows an example envelope tracking (ET) power amplification system. 
         FIG. 7  shows an example high-voltage (HV) average power tracking (APT) power amplification system having one or more features as described herein. 
         FIG. 8  shows an HV APT power amplification system that can be a more specific example of the HV APT power amplification system of  FIG. 7 . 
         FIG. 9  shows example efficiency plots as a function of output power, for power amplifiers operated in Buck ET, Buck APT, and Boost APT configurations. 
         FIG. 10  shows that a power amplification system having one or more features as described herein can have collector efficiency and power-added efficiency (PAE) profiles that are similar to nominal cases. 
         FIG. 11  shows that a power amplification system having one or more features as described herein can have linearity performance that is similar to a nominal case. 
         FIG. 12  shows example plots of power amplifier load current as a function of load voltage. 
         FIG. 13  shows an example where a power amplification system having one or more features as described herein can yield one or more advantageous benefits. 
         FIG. 14  shows another example where a power amplification system having one or more features as described herein can yield one or more advantageous benefits. 
         FIG. 15  shows yet another example where a power amplification system having one or more features as described herein can yield one or more advantageous benefits. 
         FIG. 16  shows yet another example where a power amplification system having one or more features as described herein can yield one or more advantageous benefits. 
         FIG. 17  shows an example voltage supply system including a boost converter and a charge pump. 
         FIG. 18  shows a more specific example of the voltage supply system of  FIG. 17 . 
         FIG. 19  shows an example of a charge pump that can be utilized as the charge pump of  FIG. 17 . 
         FIG. 20  shows a block diagram of a power amplification configuration with an example controller with integrated power amplifier control and power supply control components. 
         FIG. 21  shows a block diagram of a power amplification configuration with an example controller including control registers. 
         FIG. 22  shows an example of how the power supply of  FIG. 21  can generate various voltages for different operating modes. 
         FIG. 23  shows a block diagram of a power amplification system including a boost converter. 
         FIG. 24  shows an example of how a collector supply voltage limitation can be removed or substantially loosened with a variable supply voltage from a boost converter. 
         FIG. 25  shows that in some embodiments, some or all of an HV APT power amplification system having one or more features as described herein can be implemented in a module. 
         FIG. 26  depicts an example wireless device having one or more advantageous features described herein. 
     
    
    
     DETAILED DESCRIPTION OF SOME EMBODIMENTS 
     The headings provided herein, if any, are for convenience only and do not necessarily affect the scope or meaning of the claimed invention. 
     Introduction: 
     Referring to  FIG. 1 , one or more features of the present disclosure generally relate to a wireless system or architecture  50  having an amplification system  52 . In some embodiments, the amplification system  52  can be implemented as one or more devices, and such device(s) can be utilized in the wireless system/architecture  50 . In some embodiments, the wireless system/architecture  50  can be implemented in, for example, a portable wireless device. Examples of such a wireless device are described herein. 
       FIG. 2  shows that the amplification system  52  of  FIG. 1  can include a radio-frequency (RF) amplifier assembly  54  having one or more power amplifiers (PAs). In the example of  FIG. 2 , three PAs  60   a - 60   c  are depicted as forming the RF amplifier assembly  54 . It will be understood that other numbers of PA(s) can also be implemented. It will also be understood that one or more features of the present disclosure can also be implemented in RF amplifier assemblies having other types of RF amplifiers. 
     In some embodiments, the RF amplifier assembly  54  can be implemented on one or more semiconductor die, and such die can be included in a packaged module such as a power amplifier module (PAM) or a front-end module (FEM). Such a packaged module is typically configured to be mounted on a circuit board associated with, for example, a portable wireless device. 
     The PAs (e.g.,  60   a - 60   c ) in the amplification system  52  can be typically biased by a bias system  56 . Further, supply voltages for the PAs can be typically provided by a supply system  58 . In some embodiments, either or both of the bias system  56  and the supply system  58  can be included in the foregoing packaged module having the RF amplifier assembly  54 . 
     In some embodiments, the amplification system  52  can include a matching network  62 . Such a matching network can be configured to provide input matching and/or output matching functionalities for the RF amplifier assembly  54 . 
     For the purpose of description, it will be understood that each PA ( 60 ) of  FIG. 2  can be implemented in a number of ways.  FIGS. 3A-3E  show non-limiting examples of how such a PA can be configured.  FIG. 3A  shows an example PA having an amplifying transistor  64 , where an input RF signal (RF_in) is provided to a base of the transistor  64 , and an amplified RF signal (RF_out) is output through a collector of the transistor  64 . 
       FIG. 3B  shows an example PA having a plurality of amplifying transistors (e.g.,  64   a ,  64   b ) arranged in stages. An input RF signal (RF_in) is shown to be provided to a base of the first transistor  64   a , and an amplified RF signal from the first transistor  64   a  is shown to be output through its collector. The amplified RF signal from the first transistor  64   a  is shown to be provided to a base of the second transistor  64   b , and an amplified RF signal from the second transistor  64   b  is shown to be output through its collector to thereby yield an output RF signal (RF_out) of the PA. 
     In some embodiments, the foregoing example PA configuration of  FIG. 3B  can be depicted as two or more stages as shown in  FIG. 3C . The first stage  64   a  can be configured as, for example, a driver stage; and the second stage  64   b  can be configured as, for example, an output stage. 
       FIG. 3D  shows that in some embodiments, a PA can be configured as a Doherty PA. Such a Doherty PA can include amplifying transistors  64   a ,  64   b  configured to provide carrier amplification and peaking amplification, respectively, of an input RF signal (RF_in), to yield an amplified output RF signal (RF_out). The input RF signal can be split into the carrier portion and the peaking portion by a splitter. The amplified carrier and peaking signals can be combined to yield the output RF signal by a combiner. 
       FIG. 3E  shows that in some embodiments, a PA can be implemented in a cascode configuration. An input RF signal (RF_in) can be provided to a base of the first amplifying transistor  64   a  operated as a common emitter device. The output of the first amplifying transistor  64   a  can be provided through its collector and be provided to an emitter of the second amplifying transistor  64   b  operated as a common base device. The output of the second amplifying transistor  64   b  can be provided through its collector so as to yield an amplified output RF signal (RF_out) of the PA. 
     In the various examples of  FIGS. 3A-3E , the amplifying transistors are described as bipolar junction transistors (BJTs) such as heterojunction bipolar transistors (HBTs). It will be understood that one or more features of the present disclosure can also be implemented in or with other types of transistors such as field-effect transistors (FETs). 
       FIG. 4  shows that in some embodiments, the amplification system  52  of  FIG. 2  can be implemented as a high-voltage (HV) power amplification system  100 . Such a system can include an HV power amplifier assembly  54  configured to include HV amplification operation for some or all of the PAs (e.g.,  60   a - 60   c ). As described herein, such PAs can be biased by a bias system  56 . In some embodiments, the foregoing HV amplification operation can be facilitated by an HV supply system  58 . In some embodiments, an interface system  72  can be implemented to provide interface functionalities between the HV power amplifier assembly  54  and either or both of the bias system  56  and the HV supply system  58 . 
     Examples Related to HV APT Systems: 
     Many wireless devices such as cellular handsets are configured to support multiple frequency bands; and such devices typically require and/or complex power amplification architectures. However, such complexity in power amplification architectures can result in degradation of transmit efficiency as the number of supported bands increases. Such a degradation in efficiency can be due to, for example, increased loss incurred by combining of multiple frequency bands while maintaining competitive size and cost targets. 
     In some radio-frequency (RF) applications, portable transmit solutions can include a battery voltage (e.g., 3.8V) power amplifier (PA) combined with a Buck switching power supply. In such an example approach, maximum transmit power is typically achieved at the 3.8V battery voltage, which typically requires or utilizes a 13:1 impedance transformation network within the PA to support, for example, a nearly 1.5 watt peak power level. 
     In the foregoing example, efficiency improvement at lower transmit power levels can be supported by implementing a Buck power supply at voltages below the battery voltage. Multi-band operation can be accomplished using an RF switch to select a desired filter corresponding to a desired frequency band. It is noted that some or all of the Buck power supply, the impedance transformation network and the RF switch can contribute to loss, which in turn reduces the transmit efficiency. 
     Some wireless systems can include an envelope-tracking (ET) feature implemented into a Buck supply to provide an increase in system efficiency. However, envelope tracking can increase the cost of the Buck switching supply, and can also significantly complicate the system characterization and calibration process. 
     Described herein are examples of systems, circuits, devices and methods that can significantly reduce loss while maintaining or improving competitive levels of size and/or cost.  FIG. 5  shows that in some embodiments, the HV power amplification system  100  of  FIG. 4  can be configured to operate in an average power tracking (APT) mode. In the example of  FIG. 5 , an HV APT power amplification system  100  can include a power amplifier assembly  104  having one or more PAs configured to amplify one or more RF signals (RF_In). Such amplified RF signal(s) can be routed to a duplexer assembly  108  having one or more duplexers, through a match component  106  having one or more matching circuits. 
     The duplexer(s) can allow duplexing of transmit (Tx) and receive (Rx) operations. The Tx portion of such duplexing operations is depicted as one or more amplified RF signals (RF_Out) being output from the duplexer assembly  108  for transmission through an antenna (not shown). In the example of  FIG. 5 , the Rx portion is not shown; however, received signals from an antenna can be received by the duplexer assembly  108  and output to, for example, low-noise amplifiers (LNAs). 
     Various examples are described herein in the context of Tx and Rx operations utilizing duplexers, and such duplexers can facilitate, for example, frequency-division duplexing (FDD) functionality. It will be understood that in some embodiments, an HV power amplification system having one or more features as described herein can also be implemented in other duplexing configurations, including, for example, time-division duplexing (TDD) configuration. 
     In the example of  FIG. 5 , an HV supply system  102  is shown to provide one or more HV supply signals to the power amplifier assembly  104 . More specific examples of how such HV signal(s) can be provided to corresponding PA(s) are described herein in greater detail. 
     In some embodiments, the HV APT power amplification system  100  of  FIG. 5  can be configured to operate in an APT mode and meet or exceed performance provided by envelope tracking (ET) implementations, while maintaining or reducing cost and/or complexity. In some embodiments, such an HV APT power amplification system can utilize high-voltage capability of some PAs such as, for example, gallium arsenide (GaAs) heterojunction bipolar transistor (HBT) PAs. It will be understood that one or more features of the present disclosure can also be implemented with other types of PAs. For example, amplification systems utilizing CMOS devices with LDMOS multiple cascode stages, silicon bipolar devices, and GaN/HEMT devices can also benefit from operation in high-voltage regions. 
     With such HV operation of PAs, one or more lossy components can be eliminated from an amplification system, and/or other advantageous benefit(s) can be realized. For example, PA output matching network(s) can be eliminated. In another example, PA supply efficiency can be increased. In yet another example, some passive components can be removed. Examples related to the foregoing are described herein in greater detail. 
     One or more of the foregoing features associated with HV operation can result in one or more die being implemented in smaller dimensions, thereby allowing greater flexibility in power amplification system designs. For example, a power amplification system can be implemented with an increased number of relatively small PAs, to thereby allow elimination of lossy components such as band switches. Examples related to such elimination of band switches are described herein in greater detail. 
     In some embodiments, the HV APT power amplification system  100  of  FIG. 5  can be configured so as to substantially eliminate or reduce complexities associated with envelope tracking characterization and/or calibration processes. 
     For the purpose of description, it will be understood that high-voltage (HV) can include voltage values that are higher than a battery voltage utilized in portable wireless devices. For example, an HV can be greater than 3.7V or 4.2V. In some situations, an HV can include voltage values that are greater than a battery voltage and at which portable wireless devices can operate more efficiently. In some situations, an HV can include voltage values that are greater than a battery voltage and less than a breakdown voltage associated with a given type of PA. In the example context of GaAs HBT, such a breakdown voltage can be in a range of 15V to 25V. Accordingly, an HV for GaAs HBT PA can be in a range of, for example, 3.7V to 25V, 4.2V to 20V, 5V to 15V, 6V to 14V, 7V to 13V, or 8V to 12V. 
       FIGS. 6 and 7  show a comparison between an envelope tracking (ET) power amplification system  110  ( FIG. 6 ) and a high-voltage (HV) average power tracking (APT) power amplification system  100  ( FIG. 7 ) to demonstrate how some lossy components can be substantially eliminated in the HV APT power amplification system  100 . For the purpose of comparison, it will be assumed that each power amplification system is configured to provide amplification for three frequency bands. However, it will be understood that more or less numbers of frequency bands can be utilized. 
     In the example of  FIG. 6 , the ET power amplification system  110  is shown to include a power amplifier assembly  114  having a broadband amplification path  130  capable of providing amplification for three frequency bands. The amplification path  130  can receive an input RF signal through a common input node  126 , and such an RF signal can be routed to one or more amplification stages through, for example, a DC-block capacitance  128 . The amplification stages can include, for example, a driver stage  132  and an output stage  134 . In some embodiments, the amplification stages  132 ,  134  can include, for example, HBT or CMOS amplification transistors. 
     In the example of  FIG. 6 , the collector of the output stage  134  is shown to be provided with a supply voltage VCC from an envelope tracking (ET) modulator  122  through a choke inductance  124 . The ET modulator  122  is depicted as being part of an ET modulation system  112 . The supply voltage VCC provided by such an ET modulator is typically determined in a dynamic manner, and can have a value in a range of, for example, about 1V to 3V. The ET modulator  122  is shown to generate such a dynamic VCC voltage based on a battery voltage Vbatt. 
     When the amplification path  130  is operated in the foregoing manner, its impedance Z is relatively low (e.g., about 3 to 5Ω); and thus, impedance transformation typically needs to occur to match with impedance associated with a downstream component. In the example of  FIG. 6 , a band switch  138  (depicted as being part of a band switch system  118 ) that receives the output of the amplification path  130  is typically configured as a 50Ω load. Accordingly, and assuming that the impedance (Z) presented by the amplification path  130  is about 4Ω, an impedance transformation of about 13:1 (50:4) needs to be implemented. In the example of  FIG. 6 , such an impedance transformation is shown to be implemented by an output matching network (OMN)  136  which is depicted as being part of a load transform system  116 . 
     In the example of  FIG. 6 , the band switch  138  is depicted as having a single input from the output of the amplification path  130  (through the OMN  136 ), and three outputs corresponding to three example frequency bands. Three duplexers  142   a - 142   c  are shown to be provided for such three frequency bands. 
     Each of the three duplexers  142   a - 142   c  is shown to include TX and RX filters (e.g., bandpass filters). Each TX filter is shown to be coupled to the band switch  138  to receive the corresponding amplified and switch-routed RF signal for transmission. Such an RF signal is shown to be filtered and routed to an antenna port (ANT) ( 144   a ,  144   b  or  144   c ). Each RX filter is shown to receive an RX signal from the corresponding antenna port (ANT) ( 144   a ,  144   b  or  144   c ). Such an RX signal is shown to be filtered and routed to an RX component (e.g., an LNA) for further processing. 
     It is typically desirable to provide impedance matching between a given duplexer and a component that is upstream (in the TX case) or downstream (in the RX case). In the example of  FIG. 6 , the band switch  138  is such an upstream component for the TX filter of the duplexer. Accordingly, matching circuits  140   a - 140   c  (depicted as being parts of, for example, a PI network  120 ) are shown to be implemented between the outputs of the band switch  138  and the respective duplexers  142   a - 142   c . In some embodiments, each of such matching circuits  140   a - 140   c  can be implemented as, for example, a pi-matching circuit. 
     Table 1 lists example values of insertion loss and efficiency for the various components of the ET power amplification system  110  of  FIG. 6 . It will be understood that the various values listed are approximate values. 
                             TABLE 1               Component   Insertion loss   Efficiency                  ET Mod (112)   N/A   83%       Power Amp. Assy. (114)   N/A   70% to 75% (PAE)       Load Transform (116)   0.5 dB to 0.7 dB   85% to 89%       Band Switch (118)   0.3 dB to 0.5 dB   89% to 93%       PI (120)   0.3 dB   93%       Duplex (122)   2.0 dB   63%                    
From Table 1, one can see that the ET power amplification system  110  of  FIG. 6  includes a significant number of loss contributors. Even if each component of the system  110  is assumed to operate at its upper limit of efficiency, the total efficiency of the ET power amplification system  110  is approximately 31% (0.83×0.75×0.89×0.93×0.93×0.63).
 
     In the example of  FIG. 7 , the HV APT power amplification system  100  is depicted as being configured to provide amplification for the same three frequency bands as in the example ET power amplification system  110  of  FIG. 6 . In a power amplifier assembly  104 , three separate amplification paths can be implemented, such that each amplification path provides amplification for its respective frequency band. For example, the first amplification path is shown to include a PA  168   a  which receives an RF signal from an input node  162   a  through a DC-block capacitance  164   a . The amplified RF signal from the PA  168   a  is shown to be routed to a downstream component through a capacitance  170   a . Similarly, the second amplification path is shown to include a PA  168   b  which receives an RF signal from an input node  162   b  through a DC-block capacitance  164   b ; and the amplified RF signal from the PA  168   b  is shown to be routed to a downstream component through a capacitance  170   b . Similarly, the third amplification path is shown to include a PA  168   c  which receives an RF signal from an input node  162   c  through a DC-block capacitance  164   c ; and the amplified RF signal from the PA  168   c  is shown to be routed to a downstream component through a capacitance  170   c.    
     In some embodiments, some or all of the PAs  168   a - 168   c  can include, for example, HBT PAs. It will be understood that one or more features of the present disclosure can also be implemented with other types of PAs. For example, PAs that can be operated to yield impedances that match or are close to downstream components (e.g., by HV operation and/or through other operating parameter(s)) can be utilized to yield one or more of the benefits as described herein. 
     In the example of  FIG. 7 , each PA ( 168   a ,  168   b  or  168   c ) is shown to be provided with a supply voltage VCC from a boost DC/DC converter  160  through a choke inductance ( 166   a ,  166   b  or  166   c ). The boost DC/DC converter  160  is depicted as being part of an HV system  102 . The boost DC/DC converter  160  can be configured to supply such a range of VCC voltage values (e.g., about 1V to 10V), including HV ranges or values as described herein. The boost DC/DC converter  160  is shown to generate such a high VCC voltage based on a battery voltage Vbatt. 
     Additional details and examples related to the foregoing boost DC/DC converter are described herein in reference to  FIGS. 17-24 . One or more features associated with such a boost DC/DC converter can be part of a supply system that could be utilized as the HV system described herein (e.g.,  102  in  FIG. 7 ). Such a supply system can also include other supply components for generating, for example, low voltages (e.g., below battery voltage) and battery-level voltages for various PA applications. In some embodiments, some or all of the various supply components described in reference to  FIGS. 17-24 , individually or in any combination, can be included in an HV power amplification system having one or more features as described herein. 
     As described herein, various performance improvements can be realized by operating PAs with high-voltages. As also described herein, such high-voltage operations of PAs can be supported by boost converters. In some embodiments, uses of such boost converters can provide additional desirable performance improvements. Examples of such uses of boost converters in power amplification systems, as well as how such boost converters can be controlled, are also described in reference to  FIGS. 17-24 . 
     When the PAs  168   a - 168   c  are operated in the foregoing manner with high VCC voltage (e.g., at about 10V), impedance Z of each PA is relatively high (e.g., about 40Ω to 50Ω); and thus, impedance transformation is not necessary to match with impedance associated with a downstream component. In the example of  FIG. 7 , each of the duplexers  174   a - 174   c  (depicted as being parts of a duplex assembly  108 ) that receives the output of the corresponding PA ( 168   a ,  168   b  or  168   c ) is typically configured as a 50Ω load. Accordingly, and assuming that the impedance (Z) presented by the PA ( 168   a ,  168   b  or  168   c ) is about 50Ω, an impedance transformation (such as the load transform system  116  in  FIG. 6 ) is not needed. 
     It is typically desirable to provide impedance matching between a given duplexer and a component that is upstream (in the TX case) or downstream (in the RX case). In the example of  FIG. 7 , the PA ( 168   a ,  168   b  or  168   c ) is such an upstream component for the TX filter of the duplexer ( 174   a ,  174   b  or  174   c ). Accordingly, matching circuits  172   a - 172   c  (depicted as being parts of, for example, a PI network  106 ) can be implemented between the respective outputs of the PAs  168   a - 168   c  and the respective duplexers  174   a - 174   c . In some embodiments, each of such matching circuits  172   a - 172   c  can be implemented as, for example, a pi-matching circuit. 
     In the example of  FIG. 7 , the HV operation of the PAs  168   a - 168   c  can result in each of the PAs  168   a - 168   c  presenting an impedance Z that is similar to the impedance of the corresponding duplexer. Since impedance transformation is not needed in such a configuration, there is no need for an impedance transformer ( 116  in  FIG. 6 ). 
     It is also noted that operation of the PAs  168   a - 168   c  at the higher impedance can result in much lower current levels within the PAs  168   a - 168   c . Such lower current levels can allow the PAs  168   a - 168   c  to be implemented in significantly reduced die size(s). 
     In some embodiments, either or both of the foregoing features (elimination of impedance transformer and reduced PA die size) can provide additional flexibility in power amplification architecture design. For example, space and/or cost savings provided by the foregoing can allow implementation of a relatively small PA ( 168   a ,  168   b  or  168   c  in  FIG. 7 ) for each frequency band, thereby removing the need for a band switch system (e.g.,  118  in  FIG. 6 ). Accordingly, size, cost and/or complexity associated with the HV APT power amplification system  100  of  FIG. 7  can be maintained or reduced when compared to the ET power amplification system  110  of  FIG. 6 , while significantly reducing the overall loss of the power amplification system  100 . 
     Table 2 lists example values of insertion loss and efficiency for the various components of the HV APT power amplification system  100  of  FIG. 7 . It will be understood that the various values listed are approximate values. 
     
       
         
           
               
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
               
                   
                 Component 
                 Insertion loss 
                 Efficiency 
               
               
                   
                   
               
             
            
               
                   
                 HV (102) 
                 N/A 
                 93% 
               
               
                   
                 Power Amp. Assy. (104) 
                 N/A 
                 80% to 82% (PAE) 
               
               
                   
                 PI (106) 
                 0.3 dB 
                 93% 
               
               
                   
                 Duplex (108) 
                 2.0 dB 
                 63% 
               
               
                   
                   
               
            
           
         
       
     
     From Table 2, one can see that the HV APT power amplification system  100  of  FIG. 7  includes a number of loss contributors. However, when compared to the ET power amplification system  110  of  FIG. 6  and Table 1, two significant loss contributors (Load Transform ( 116 ) and Band Switch ( 118 )) are absent in the HV APT power amplification system  100  of  FIG. 7 . Elimination of such loss contributors is shown to remove about 1 dB in the transmit path in the example of  FIG. 7  and Table 2. 
     Also referring to Table 2, if each component of the system  100  is assumed to operate at its upper limit of efficiency (as in the example of Table 1), the total efficiency of the HV APT power amplification system  100  is approximately 45% (0.93×0.82×0.93×0.63). Even if each component is assumed to operate at its lower limit of efficiency, the total efficiency of the HV APT power amplification system  100  is approximately 44% (0.93×0.80×0.93×0.63). One can see that in either case, the total efficiency of the HV APT power amplification system  100  of  FIG. 7  is significantly higher than the total efficiency (approximately 31%) of the ET power amplification system  110  of  FIG. 6 . 
     Referring to  FIGS. 6 and 7 , a number of features can be noted. It is noted that use of the DC/DC boost converter ( 160  in  FIG. 7 ) can allow elimination of one or more other power converters that may be utilized in a PA system. For example, when operated to yield an HV supply voltage (e.g., 10 VDC), 1 Watt (10V) 2 /(2×50Ω)) of RF power can be produced with no harmonic terminations. 
     It is further noted that a PA driven as a 50Ω load (e.g.,  FIG. 7 ) results in a significantly lower loss per Ohm than a PA driven as a 3Ω load (e.g.,  FIG. 6 ). For example, an equivalent series resistance (ESR) of 0.1Ω has an insertion loss of about 0.14 dB when the PA is driven at 3Ω, while for the PA driven at 50Ω, an ESR of 0.1Ω has an insertion loss of about 0.008 dB. Accordingly, the 3Ω PA can have a total insertion loss of about 4.2 dB (0.14 dB×30), while the 50Ω PA can have a total insertion loss of about 4.0 dB (0.008 dB×500), which is still less than the total insertion loss for the 3Ω PA. 
     It is further noted that the 50Ω PA can have a significantly higher gain than the 3Ω PA. For example, gain can be approximated as G M ×R LL ; if G M  is similar for both cases, then the higher value of 50Ω yields a higher gain. 
       FIG. 8  shows an HV APT power amplification system  100  that can be a more specific example of the HV APT power amplification system  100  of  FIG. 7 . In the example of  FIG. 8 , a power amplifier assembly can include a low-band (LB) power amplifier assembly  190 , a mid-band (MB) power amplifier assembly  200 , and a high-band (HB) power amplifier assembly  210 , with some or all of PAs in such assemblies capable of being operated with high-voltage as described herein. The power amplifier assembly can also include other PAs that do not operate in high-voltage. For example, a 2 G power amplifier assembly  220  and power amplifier assemblies  230 ,  232  can be operated in lower voltages. 
     In the example of  FIG. 8 , the foregoing high-voltage(s) can be provided to the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210  from, for example, a front-end power management integrated circuit (FE-PMIC)  160 . In some embodiments, such an FE-PMIC can include a DC/DC boost converter (e.g.,  160  in  FIG. 7 ) as described herein. 
     The FE-PMIC  160  can receive a battery voltage Vbatt and generate a high-voltage output  182  as supply voltages (VCC) for the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210 . In some embodiments, such a high-voltage VCC can have a value of approximately 10V, with a maximum current of approximately 250 mA. It will be understood that other values of such high-voltage VCC and/or maximum current can also be utilized. 
     The FE-PMIC  160  can also generate other output(s). For example, an output  184  can provide bias signals for the PAs associated with the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210 , as well as for the 2 G power amplifier assembly  220 . In some embodiments, such a bias signal can have a value of approximately 4V, with a maximum current of approximately 50 mA. It will be understood that other values of such bias signal and/or maximum current can also be utilized. 
     In the example of  FIG. 8 , the FE-PM IC  160  can be part of an HV system  102  described herein in reference to  FIG. 7 . The FE-PMIC  160  can include one or more interface nodes  180 . Such interface nodes can be utilized to facilitate, for example, control of the FE-PMIC  160 . 
     In the example of  FIG. 8 , supply voltage VCC for the 2 G power amplifier assembly  220  is shown to be provided (e.g., line  186 ) substantially directly from the battery voltage Vbatt. Such Vbatt is also shown to provide operating voltages for various switches associated with the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210 . In some embodiments, such Vbatt can have a value in a range of about 2.5V to 4.5V. It will be understood that other values of such Vbatt can also be utilized. 
     In the example of  FIG. 8 , supply voltages VCC for the power amplifier assemblies  230 ,  232  can be provided from a DC/DC switching regulator  234 . 
     Referring to  FIG. 8 , the LB power amplifier assembly  190  is shown to include separate PAs for eight example frequency bands B27, B28A, B28B, B20, B8, B26, B17 and B13. Each PA is shown to provide its amplified RF signal to a corresponding duplexer. As described herein, such eight PAs can be coupled to their respective duplexers without a band selection switch in between. 
     The LB power amplifier assembly  190  is further shown to include and/or be coupled to an input switch  192  and an output switch  196 . The input switch  192  is shown to include two input nodes  194   a ,  194   b , and eight output nodes corresponding to the eight PAs. In the input switch  192 , the two input nodes  194   a ,  194   b  are shown to be switchable to a common node which is coupled to another common node for switching to one of the eight output nodes. The coupling between such common nodes can include an amplification element. 
     The output switch  196  is shown to include eight input nodes corresponding to the eight duplexers, and two output nodes  198   a ,  198   b . The output switch  196  can further include inputs for receiving an output of the 2 G power amplifier assembly  220  and an output of the power amplifier assembly  230 . 
     It will be understood that the LB power amplifier assembly  190  can include different combinations of frequency bands. 
     Referring to  FIG. 8 , the MB power amplifier assembly  200  is shown to include separate PAs for four example frequency bands B1, B25, B3 and B4. Each PA is shown to provide its amplified RF signal to a corresponding duplexer. As described herein, such four PAs can be coupled to their respective duplexers without a band selection switch in between. 
     The MB power amplifier assembly  200  is further shown to include and/or be coupled to an input switch  202  and an output switch  206 . The input switch  202  is shown to include an input node  204 , and four output nodes corresponding to the four PAs. In the input switch  202 , the input node  204  is shown to be coupled to a common node for switching to one of the four output nodes. The coupling between such nodes can include an amplification element. 
     The output switch  206  is shown to include four input nodes corresponding to the four duplexers, and an output node  208 . The output switch  206  can further include an input for receiving an output of the 2 G power amplifier assembly  220 . 
     It will be understood that the MB power amplifier assembly  200  can include different combinations of frequency bands. 
     Referring to  FIG. 8 , the HB power amplifier assembly  210  is shown to include separate PAs for two example frequency bands B7 and B20. Each PA is shown to provide its amplified RF signal to a corresponding duplexer. As described herein, such two PAs can be coupled to their respective duplexers without a band selection switch in between. 
     The HB power amplifier assembly  210  is further shown to include and/or be coupled to an input switch  212  and an output switch  216 . The input switch  212  is shown to include an input node  214 , and two output nodes corresponding to the two PAs. In the input switch  212 , the input node  214  is shown to be coupled to a common node for switching to one of the two output nodes. The coupling between such nodes can include an amplification element. 
     The output switch  216  is shown to include two input nodes corresponding to the two duplexers, and an output node  218 . The output switch  216  can further include an input for receiving an output of the power amplifier assembly  232 . 
     It will be understood that the HB power amplifier assembly  210  can include different combinations of frequency bands. 
     In the example of  FIG. 8 , the PAs of the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210  can be implemented as one or more die. For example, such PAs can be implemented on a single HBT (e.g., GaAs) die, on separate HBT die corresponding to the LB, MB and HB power amplifier assemblies  190 ,  200 ,  210 , or some combination thereof. 
     In the example of  FIG. 8 , each of the input switches  192 ,  202 ,  212  can be configured to provide switching functionalities as described herein, as well as to facilitate biasing functionalities as described herein. In some embodiments, the switches  192 ,  196 ,  202 ,  206 ,  212 ,  216  can be implemented on, for example, a single silicon-on-insulator (SOI) die, on separate die corresponding to the various functional groups, or some combination thereof. 
       FIG. 9  shows example efficiency plots as a function of output power, for power amplifiers operated in 78% Buck ET, 97% Buck APT, and 87% Boost APT configurations. It is noted that all three of the example configurations yield a similar efficient efficiency profile up to about 15 dBm of output power. Beyond such an output level, one can see that the 87% Boost APT configuration has significantly higher efficiency values over both of the 97% Buck APT and 78% Buck ET configurations. Such a Boost APT configuration can be implemented in either or both of the example HV APT power amplification systems of  FIGS. 7 and 8 . 
       FIG. 10  shows that a power amplification system (e.g., HV APT power amplification system  100  of  FIG. 8 ) having one or more features as described herein can have collector efficiency and power-added efficiency (PAE) profiles that are similar to nominal cases. For example, collector efficiency plots (as a function of output power) associated with the HV APT power amplification system of  FIG. 8  are shown to have substantially same profiles as those of respective nominal collector efficiencies. Similarly, PAE plots (as a function of output power) associated with the HV APT power amplification system of  FIG. 8  are shown to have substantially same profiles as those of respective nominal PAEs. 
       FIG. 11  shows that a power amplification system (e.g., HV APT power amplification system  100  of  FIG. 8 ) having one or more features as described herein can have linearity performance (e.g., adjacent-channel leakage ratio (ACLR)) that is similar to a nominal case. For example, ACLR plots (as a function of output power) associated with the HV APT power amplification system of  FIG. 8  are shown to have substantially same profiles as those of respective nominal ACLRs at higher output power values (e.g., higher than 29 dBm). 
       FIG. 12  shows example plots of power amplifier load current as a function of load voltage for power amplifier configurations indicated as “R99” and “50RB LTE.” Suppose that a relatively low current condition of 40 mA is desired for the power amplifier configurations. For example, such a current of 40 mA can result from subtracting fixed bias current and quiescent current from the supply current (load current in  FIG. 12 ). For the 50RB LTE example in  FIG. 12 , a load current of approximately 104 mA can yield such a low current (40 mA) condition for the power amplifier configuration. Such a load current of 104 mA corresponds to a load voltage (VCC) of approximately 9.5V, as indicated by point  250 . Accordingly, one can see that a high-voltage power amplifier operating configuration as described herein can yield a relatively low current condition for the power amplifier. 
     Examples of Advantageous Features: 
       FIGS. 13-16  show examples of advantageous benefits that can be obtained in HV APT power amplification systems having one or more features as described herein. As described herein,  FIG. 13  shows that in some embodiments, a power amplification system  100  can include a power amplifier (PA) configured to receive a radio-frequency (RF) signal (RF_in) at an input node  260 . Such a PA can be provided with a supply voltage of Vcc, and such a supply voltage can include a high-voltage (HV) value as described herein. The amplified RF signal can be output as RF_out, and be routed to a filter that is configured to condition the amplified RF signal and yield a filtered signal at an output node  262 . The PA can be operated (e.g., in an HV mode) to be driven at approximately a characteristic load impedance of the filter. Such a characteristic load impedance of the filter can be, for example, approximately 50 Ohms. 
     In some embodiments, the foregoing configuration can be implemented in an average-power tracking (APT) PA system so as to yield one or more advantageous features. For example, a less complex supply configuration, reduced loss, and improved efficiency can be realized. In another example, the foregoing PA, a die having the foregoing power amplification system  100 , and/or a module having the foregoing power amplification system  100  can be implemented in as a reduced-sized device. In some embodiments, such reduced-sized device can be realized at least in part due to elimination of some or all of the PA&#39;s output matching networks (OMNs) in a power amplification system. 
       FIG. 14  shows an example of a power amplification system  100  in which an output matching network (OMN) (also referred to herein as an impedance transformation circuit) associated with a PA is substantially eliminated between the PA and a filter. In the example of  FIG. 14 , the PA, its supply voltage Vcc, and the filter can be configured and operated similar to the example of  FIG. 14 . Such a PA configuration can include an HV mode of operation as described herein. 
     In the example of  FIG. 14 , some or all of the power amplification system  100  can be implemented on a device  270  such as a PA die or a PA module. With the foregoing elimination of the OMN, dimensions (e.g., d1×d2) associated with the device  270  can be reduced. Further, other advantageous features such as reduced loss and improved efficiency can also be realized with the elimination of the OMN. 
       FIG. 15  shows an example of a power amplification system  100  configured to process RF signals for a plurality of bands. Such bands can be, for example, Band A and Band B. It will be understood that other numbers of bands can be implemented for the power amplification system  100 . 
     In the example of  FIG. 15 , each band is shown to have associated with it a separate amplification path. In each amplification path, its PA, supply voltage Vcc, and filter can be configured and operated similar to the example of  FIG. 14 . Such a PA configuration can include an HV mode of operation as described herein. 
     In the example of  FIG. 15 , each band having its own dedicated amplification path can allow elimination of a band selection switch. Accordingly, a device  270  (such as a PA die or a PA module) having some or all of the power amplification system  100  can have reduced dimensions (e.g., d3×d4). Further, other advantageous features such as reduced loss and improved efficiency can also be realized with the elimination of the band selection switch. 
       FIG. 16  shows an example of a power amplification system  100  configured to process RF signals for a plurality of bands, similar to the example of  FIG. 15 . In the example of  FIG. 16 , each of some or all of the plurality of amplification path can be substantially free of an output matching network (OMN) (also referred to herein as an impedance transformation circuit), similar to the example of  FIG. 14 . Accordingly, a device  270  (such as a PA die or a PA module) having some or all of the power amplification system  100  can have reduced dimensions (e.g., d5×d6). Further, other advantageous features such as reduced loss and improved efficiency can also be realized with the elimination of the band selection switch and some or all of the OMNs. 
     In the examples of  FIGS. 15 and 16 , the device  270  on which its respective power amplification system  100  is implemented can be, for example, a power amplifier die having a semiconductor substrate. The plurality of PAs can be implemented in parallel as shown on the semiconductor substrate, and each PA can be configured to drive an individual narrow frequency band signal path. Thus, each PA can be sized smaller than a wide band PA capable of driving more than one of the frequency bands associated with the plurality of PAs. As described herein, use of such miniaturized single-band PAs can yield a number of desirable features. 
     Examples Related to Power Supplies for Power Amplification Systems: 
     In some embodiments, including one or more example configurations associated with  FIGS. 7-9 and 13-16 , a boost DC/DC converter can be implemented part of a supply system that could be utilized to provide a high-voltage (HV) for operation of one or more power amplifiers (PAs). Examples related to such a supply system are described in reference to  FIGS. 17-24 . 
       FIG. 17  shows a voltage supply system  500  including a boost converter and a charge pump. The voltage supply system can include a supply device  502  (e.g., a die or a module) having an input node  591  to receive an input voltage (Vbatt) and an output node  592  to supply an output voltage (Vcc). The input node can be coupled to a ground voltage via a first capacitor  531  that shunts variations in the input voltage. The output node  592  can be coupled to the ground voltage via a second capacitor  532  that shunts variations in the output voltage and implements a capacitor of a boost converter. 
     The supply device  502  can include two switching nodes  593   a ,  593   b  coupled, via an inductor  521 , to the input voltage. The inductor  521  can be implemented as an inductor of the boost converter. The supply device  502  cam include two charge pump nodes  594   a ,  594   b  coupled together via a third capacitor  532  that can be implemented as a capacitor of a charge pump. 
     The supply device  502  can include boost converter circuitry  504  that is controllable to generate an output voltage greater than (boost functionality) or equal to (bypass functionality) the input voltage. The output voltage can be provided to, for example, a high-voltage (HV) power amplifier (PA) as a supply voltage. Such an HV PA can include, for example, an HV average power tracking (APT) PA. The voltage supply system  500  can include a boost converter that includes the boost converter circuitry  504 , the inductor  521 , and the second capacitor  532 . 
     The supply device  502  can further include a charge pump circuitry  508  that is controllable to generate an output voltage less than the input voltage. The charge pump circuitry  508  can be configured to generate a low-voltage (LV) output which is shown to be provided to the output node  592  through a bypass circuit  510 . 
     In some embodiments, the charge pump circuitry  508  can operate with the third capacitor  533  (e.g., a flying capacitance) to generate a desired output which can be greater than the input voltage (e.g., twice the input voltage) or less than the input voltage (e.g., half the input voltage). An example charge pump that can be utilized as the charge pump  508  is described in reference to  FIG. 19 . 
       FIG. 18  shows a voltage supply system  600  including a plurality of switches  611 - 613 . The voltage supply system  600  can include a supply device  602  (e.g., a die or a module) having an input node  691  to receive an input voltage (Vbatt) and an output node  692  to supply an output voltage (Vcc). The input node  691  can be coupled to a ground via a first capacitor  631  that shunts variations in the input voltage. The output node  692  can be coupled to the ground via a second capacitor  632  that shunts variations in the output voltage and implements a capacitor of a boost converter. 
     The supply device  602  can include two switching nodes  693   a ,  693   b  coupled, via an inductor  621 , to the input voltage. The inductor  621  can be implemented as an inductor of the boost converter. The boost converter can further include boost converter circuitry  604  residing on the supply device  602  that includes a first switch  611  coupled between the first switching node  693   a  and the ground and a second switch  612  coupled between the second switching node  693   b  and the output node  692 . 
     The first switch  611  and second switch  612  can be controlled (e.g., by the controller  601 ) for the accumulation and transfer of energy associated with the inductor  621  and a capacitor  632  to generate an output voltage at the output node  692  that is greater than the input voltage at the input node  691 . Thus, the controller  601  can be configured to periodically operate the switches  611 ,  612  to boost the input voltage to generate the output voltage at the output node  692 . 
     The first switch  611  and second switch  612  can also be controllable (e.g., by the controller  601 ) to provide a bypass functionality by opening the first switch  611  and closing the second switch  612  such that the output voltage at the output node  692  is approximately equal to the input voltage at the input node  691 . Thus, the controller  601  can be configured to operate the switches  611 - 612  to pass the input voltage as the output voltage to the output node. 
     In some implementations, the supply device  602  can include a bypass circuit (not shown) separate from the boost converter circuitry  604  to pass the input voltage as the output voltage to the output node. For example, in some embodiments, the first switch  611  and second switch  612  can be implemented so as to change state rapidly (while performing boost functionality) at the expense of higher switch loss. Thus, the supply device  602  can include a bypass circuit including a slower switch (coupled in series between the input node  691  and the output node  692 ) that does not change state as rapidly but has lower switch loss than the second switch  612 . 
     The supply device  602  can include two charge pump nodes  694   a ,  694   b  coupled together via a third capacitor  632  that implements a capacitor of a charge pump. The supply device  602  can include a charge pump circuitry  608  that is controllable (e.g., by the controller  601 ) to generate an output voltage less than the input voltage. In some embodiments, the charge pump circuitry  608  can operate with the third capacitor  633  (e.g., a flying capacitance) to generate a desired output which can be, for example, twice the input voltage or half the input voltage. The output of the charge pump circuitry  608  can be provided to the output node  692  through a bypass circuit  610  including a third switch  613  controllable by the controller  601 . 
     The supply device  602  can include one or more control nodes  695  for receiving one or more control signals. The control node  695  can be coupled to the controller  601  which can receive and process the control signals. Thus, the voltage supply system  600  can include a boost converter controllable (e.g., by the controller  601 ) to receive an input voltage at the input node  691  and generate an output voltage when the output voltage is greater than (boost functionality) or equal to (bypass functionality) to the input voltage. The boost converter can include the boost control circuitry  604  residing on the supply device  602  and one or more passive devices external to the supply device  602  (e.g., the inductor  621  and the second capacitor  632 ). The voltage supply system  600  can include a charge pump controllable (e.g., by the controller  601 ) to receive the input voltage at the input node  691  and generate the output voltage when the output voltage is less than the input voltage. The charge pump can include the charge pump circuitry  608  residing on the supply device  602  and one or more passive devices external to the supply device  602  (e.g., the third capacitor  633 ). The voltage supply system  600  can include a controller  601  configured to receive a control signal (e.g., via the control node  695 ) and control the boost converter or the charge pump to generate a desired output voltage at the output node  692  based on the control signal. 
     In some implementations, the control signal can indicate a mode of operation. The control signal can indicate a mode of operation in a number of ways. In some implementations, the control signal can directly indicate one of a plurality of modes. In some implementations, the control signal can indicate a target output power that corresponds to one of a plurality of modes. In some implementations, the control signal can indicate a target supply voltage that corresponds to one of a plurality of modes. 
     In response to the control signal indicating a first mode (e.g., a low-voltage mode, a buck mode, or a voltage decrease mode), the controller  601  can be configured to control the charge pump (e.g., the charge pump circuitry  608  or one or more switches of the charge pump circuitry  608 ) to generate the output voltage less than the input voltage. In some implementations, the controller  601  can be configured to control the charge pump to generate the output voltage of approximately half the input voltage. In some implementations, when the control signal indicates the first mode, the controller  601  can be configured to control the charge pump bypass circuit  610  to pass the output voltage (from the charge pump output) to the output node  692 . For example, the controller  601  can be configured to close the third switch  613  in response to the control signal indicating the first mode. 
     In response to the control signal indicating a second mode (e.g., a medium-voltage mode, a bypass mode, or a voltage equal mode), the controller  601  can be configured to control the boost converter to generate the output voltage approximately equal to the input voltage. In some implementations, the controller  601  can be configured to operate one or more switches of the boost converter to pass the input voltage as the output voltage to the output node  692 . For example, the controller  601  can be configured to open the first switch  611  and close the second switch  612  to pass the input voltage as the output voltage to the output node  692 . 
     As noted above, in some implementations, the supply device  602  can include a bypass circuit (not shown) separate from the boost converter circuitry  604 . Thus, in some implementations, in response to the control signal indicating the second mode, the controller  601  can be configured to control the bypass circuit to pass the input voltage as the output voltage to the output node  692 . 
     In response to the control signal indicating a third mode (e.g., a high-voltage mode, a boost mode, or a voltage increase mode), the controller can be configured to control the boost converter to generate the output voltage greater than the input voltage. In addition to indicating the third mode, the control signal can further indicate a target output voltage. The controller  601  can control the boost converter to boost the input voltage to result in the target output voltage. In some implementations, the controller  601  can be configured to periodically operate one or more switches of the boost converter to boost the input voltage to generate the output voltage at the output node  692 . For example, the controller  601  can be configured to periodically open and close the first switch  611  and second switch  612  to boost the input voltage to generate the output voltage at the output node  692 . 
     As noted above, the boost converter can include the inductor  621  and one or more switches (e.g., the first switch  611  coupled between the inductor  621  and the ground voltage and the second switch  612  coupled between the inductor  621  and the output node  692 ). In some implementations, the boost converter does not include a switch coupled between the inductor  621  and the input node  691 . In particular, the voltage supply system  600  does not include a switch coupled between the inductor  621  and the input node  691 . 
     The charge pump can include one or more capacitors (e.g., the third capacitor  633 ). The charge pump can further include one or more switches (e.g., switches of the charge pump circuitry  608 ). However, in some implementations, the charge pump does not include an inductor. 
     Table 3 includes a state table of the first switch  611  (S1), second switch  612  (S2), and third switch  613  (S3) in response to a control signal indicating a mode. In particular, in response to the control signal indicating a first mode (e.g., a low-voltage mode), the first switch  611  and second switch  612  can be off (e.g., open) and the third switch  613  can be on (e.g., closed). In response to the control signal indicating a second mode (e.g., a medium-voltage mode), the first switch  611  and third switch  613  can be off and the second switch  612  can be on. In response to the control signal indicating a third mode (e.g., a high-voltage mode), the third switch  613  can be off and the first switch  611  and second switch  612  can be operated in a switched mode. 
     
       
         
           
               
               
               
               
             
               
                 TABLE 3 
               
               
                   
               
               
                 Mode 
                 S1 
                 S2 
                 S3 
               
               
                   
               
             
            
               
                 Low-voltage (charge pump) 
                 OFF 
                 OFF 
                 ON 
               
               
                 Medium-voltage (bypass) 
                 OFF 
                 ON 
                 OFF 
               
               
                 High-voltage (boost converter) 
                 Switched mode 
                 Switched mode 
                 OFF 
               
               
                   
               
            
           
         
       
     
       FIG. 19  shows an example of a charge pump circuitry  700  that can be configured and operated to provide both of the voltage-doubling and voltage-halving functionalities. Although various examples are described in the context of doubling and halving, it will be understood that voltage-increasing and voltage-decreasing factors can be other than 2. 
     Referring to  FIG. 19 , the charge pump circuitry  700  can be configured to receive an input voltage V in  (e.g., a battery voltage V batt ) and generate a doubled-voltage output (2×V in ) and a halved-voltage output (V in /2). More particularly, the input voltage V in  is shown to be provided to an input node  702  that is coupled to a node  704  through a first switch S1. A second switch S2 is shown to couple the input node  702  to a node  706  through a second switch S2. The nodes  704  and  706  are shown to be coupled by a flying capacitor (C Fly ). The node  706  is shown to be coupled to ground through a third switch S3. 
     Still referring to  FIG. 19 , the node  704  is shown to be coupled to a first output node  708  through a fourth switch S4, and to a second output node  710  through a fifth switch S5. The node  706  is shown to be coupled to the second output node  710  through a sixth switch S6. The first output node  708  is shown to be coupled to ground by a first holding capacitor (C Hold1 ), and the second output node  710  is shown to be coupled to ground by a second holding capacitor (C Hold2 ). 
     In some embodiments, the charge pump circuit  700  of  FIG. 19  can be operated in four phases (Φ 1 , Φ 2 , Φ 3 , Φ 4 ) to generate both doubled-voltage (2×V in ) and halved-voltage (V in /2) outputs based on an input voltage V in . Table 4 lists switch configurations for each of the four phases. 
     
       
         
           
               
               
               
               
               
               
               
             
               
                 TABLE 4 
               
               
                   
               
               
                 Phase 
                 S1 
                 S2 
                 S3 
                 S4 
                 S5 
                 S6 
               
               
                   
               
             
            
               
                 Φ 1   
                 Closed 
                 Open 
                 Open 
                 Open 
                 Open 
                 Closed 
               
               
                 Φ 2   
                 Open 
                 Open 
                 Closed 
                 Open 
                 Closed 
                 Open 
               
               
                 Φ 3   
                 Closed 
                 Open 
                 Closed 
                 Open 
                 Open 
                 Open 
               
               
                 Φ 4   
                 Open 
                 Closed 
                 Open 
                 Closed 
                 Open 
                 Open 
               
               
                   
               
            
           
         
       
     
     Among others, additional details and examples related to the charge pump circuitry  700  of  FIG. 19  are described in U.S. Provisional Application No. 62/116,457 entitled INTERLEAVED DUAL OUTPUT CHARGE PUMP, and U.S. application Ser. No. 14/861,058 entitled INTERLEAVED DUAL OUTPUT CHARGE PUMP, the disclosure of each of which is hereby expressly incorporated by reference herein in its entirety. 
       FIG. 20  shows a block diagram of a power amplification configuration  750  with an example controller  758  with integrated power amplifier control and power supply control components  764 ,  766 . The power amplification configuration  750  can include a power amplifier  760  and a power supply  754 . In some embodiments, the power supply  754  can include a switching mode power supply (SMPS), such as a boost converter, a buck converter, a buck-boost converter, a charge pump, etc. 
     The power supply  754  can receive an input voltage (e.g., Vbatt from a battery or from another source) and provide a supply voltage (Vcc) to the power amplifier  760 . The power amplifier  760  is shown to be powered by the supply voltage. The magnitude of the supply voltage can be set by a power supply control signal received by the power supply  754  and provided by a controller  758 . In particular, the power supply control signal can be provided by the power supply control component  764  of the controller  758 . The power supply control component  764  can generate the power supply control signal based on a transceiver control signal received from a transceiver  752  via an interface  762  or based on local control signal received from the power amplifier control component  766 . The local control signal can be, for example, based on sensed condition of the power amplifier  760 . As shown in  FIG. 20 , the power supply control component  764  can include a first input coupled to the interface  762  to receive at least a portion of the transceiver control signal and a second input coupled to the power amplifier control component  766  to receive the local control signal from the power amplifier control component  766 . 
     The power amplifier  760  can receive an input signal (RFin) and yield, as an output signal (RFout), an amplified version of the input signal. The input signal can be received from the power amplifier control component  766  that receives the signal from the transceiver  752  via the interface  762  (as shown in  FIG. 20 ), can be received directly from the transceiver  752 , or can be received from another source. The power amplifier  760  can be biased by power amplifier control signal (e.g., a bias signal such as a bias voltage or a bias current) received by the power amplifier  760  and provided by the power amplifier control component  766 . The power amplifier control component  766  can generate the power amplifier control signal based on a transceiver control signal received from the transceiver  752  via the interface  762 . The controller  758  and power amplifier  760  can be integrated onto a single module  756 , referred to herein as a PA master. In particular, the controller  758  and power amplifier  760  can be integrated on a single die. In some implementations, the power supply  754  can also be integrated onto the module or integrated on the die. 
     Thus, the power amplification configuration  750  of  FIG. 20  can include a power amplification control system including the controller  758 . The controller  758  can include an interface  762  configured to receive a transceiver control signal from the transceiver  752 . The controller  758  can include a power amplifier control component  766  configured to generate a power amplifier control signal based on the transceiver control signal from the transceiver  752  and a power supply control component  764  configured to generate a power supply control signal based on the transceiver control signal from the transceiver  752  and to generate the power supply control signal based on a local control signal from the power amplifier control component  766 . 
     In some embodiments, the power amplifier control signal supplied to the power amplifier  760  by the power amplifier control component  766  can include a bias voltage for biasing the power amplifier  760 . In some embodiments, the power amplifier control signal can include an enable signal for enabling (or disabling) the power amplifier  760 . 
     In some embodiments, the power supply control signal supplied to the power supply  754  by the power supply control component  764  can include a reference voltage that indicates a magnitude of the supply voltage to be provided to the power amplifier  760 . In some embodiments, the power supply control signal can include an enable signal for enabling (or disabling) the power supply  754 . 
     In some embodiments, the local control signal supplied to the power supply control component  764  by the power amplifier control component  766  can indicate that the supply voltage is to be increased. In some embodiments, the local control signal can indicate that the supply voltage is to be decreased. In some embodiments, the local control signal can indicate that the power supply  754  is to be disabled. 
     In some embodiments, the local control signal can be based on a sensed condition of the power amplifier  760 . The sensed condition can be a saturation condition or a safety condition. For example, the power amplifier control component  766  can detect that the power amplifier  760  (or one or more transistors of the power amplifier  760 ) is saturated. In response, the power amplifier control component  766  can provide a local control signal to the power supply control component  764  indicating that the supply voltage is to be increased. As another example, the power amplifier control component  766  can detect that the power amplifier  760  is operating in (or approaching operation in) an unsafe condition that could lead to damage to the power amplifier  760 . In response, the power amplifier control component  766  can provide a local control signal to the power supply control component  764  indicating that the supply voltage is to be decreased or the power supply  754  is to be disabled. 
       FIG. 21  shows a power amplification configuration  800  with an example controller  806  including control registers  810 . The power amplification configuration  800  is shown to include a power amplifier  808  and a switching mode power supply (SMPS)  802 . The switching mode power supply can include a boost converter, a buck converter, a buck-boost converter, a charge pump, etc. The power amplifier  808  can be a high-voltage power amplifier. 
     The SMPS  802  is shown to receive an input voltage (e.g., from a battery or from another source) and provide a supply voltage at an output to the power amplifier  808 . The power amplifier  808  can be powered by the supply voltage. The magnitude of the supply voltage can be set by a power supply control signal received by the power supply  802  and provided by a controller  806 . In particular, the power supply control signal can be provided by an SMPS control component  812  of the controller  806 . The power supply control signal can be converted from a digital signal to an analog reference voltage (Vref) by a digital-to-analog converter  816 . The SMPS control component  812  can generate the power supply control signal based on a transceiver control signal received from a modem/transceiver (not shown) via an interface  810  or based on local control signal received from a power amplifier bias control component  814 . The local control signal can be, for example, based on sensed condition of the power amplifier  808 . As shown in  FIG. 21 , the SMPS control component  812  can include a first input coupled to the interface  810  to receive at least a portion of the transceiver control signal and a second input coupled to the power amplifier bias control component  814  to receive the local control signal from the power amplifier bias control component  814 . 
     The SMPS control component  812  can also generate the power supply control signal based on an external control signal received from an alternate PA module  818  including a power amplifier power by the supply voltage of the SMPS  802 . In particular, the external control signal can be received from a power amplifier control component (e.g., a power amplifier bias control component) of the alternate PA module  818 . 
     The power amplifier  808  can receive an input signal (RFin) and provide, as an output signal (RFout), an amplified version of the input signal. The input signal can be received from the power amplifier bias control component  814  that receives the signal from the transceiver via the interface  810  (as shown in  FIG. 21 ), can be received directly from the transceiver, or can be received from another source (such as another power amplifier control component). The power amplifier  808  can be biased by power amplifier control signal (e.g., a bias signal such as a bias voltage or a bias current) received by the power amplifier  808  and provided by the power amplifier bias control component  814 . The power amplifier bias control component  814  can generate the power amplifier control signal based on a transceiver control signal received from the transceiver via the interface  810 . The controller  806  and power amplifier  808  can be integrated onto a single module  804 , referred to herein as a PA master. In particular, the controller  806  and power amplifier  808  can be integrated on a single die. In some implementations, the power supply  802  can also be integrated onto the module or integrated on the die. 
     The interface  810  of the controller  806  can include one or more control registers. The control registers can be, for example, MIPI control registers. In particular, as shown in  FIG. 21 , the interface  810  can include one or more power amplifier control registers and one or more power supply control registers. The interface  810  can further include one-time programmable (OTP) memory. 
     The power amplifier bias control component  814  can be configured to generate the power amplifier control signal based on a portion of the transceiver control signal written to the one or more power amplifier control registers, and the SMPS control component  812  can be configured to generate the power supply control signal based on a portion of the transceiver control signal written to the one or more power supply control registers. In some embodiments, the power amplifier bias control component  814  can be configured to overwrite one or more of the power supply control registers with the local control signal. Thus, the local control signal can be provided, in some implementations, to the SMPS control component  812  via the interface  810 . 
     The interface  810  can include an input/output voltage (VIO) pin, a clock (CLK) pin, a ground (GND) pin, and a data pin. The transceiver control signal can be transmitted from the modem/transceiver (and written to the control registers) via the data pin. 
     Thus, the power amplification configuration  800  of  FIG. 21  can include a power amplification control system including the controller  806 . The controller  806  can include an interface  810  configured to receive a transceiver control signal from the transceiver. The controller  806  can include a power amplifier control component (e.g., the power amplifier bias control component  814 ) configured to generate a power amplifier control signal (e.g., a bias voltage) based on the transceiver control signal from the transceiver and a power supply control component (e.g., the SMPS control component  812 ) configured to generate a power supply control signal (e.g., the reference voltage) based on the transceiver control signal from the transceiver and to generate the power supply control signal based on a local control signal from the power amplifier control component. 
     Table 5 lists examples of control signals that can be generated by the SMPS control component  812  by using a 3-bit signal (which can be written to one of the SMPS control registers) to generate various values of Vref. Table 5 shows that a number of operating modes can be implemented with varying values of Vref, including a disable mode. In the “Boost” mode, the specific Vref output can be indicated using a value written to another of the SMPS control registers. 
     
       
         
           
               
               
               
               
               
             
               
                 TABLE 5 
               
               
                   
               
               
                   
                   
                   
                   
                 Vref 
               
               
                 Control B2 
                 Control B1 
                 Control Bit B0 
                 Mode 
                 output 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
            
               
                 0 
                 0 
                 0 
                 Disable 
                 0 
               
               
                 0 
                 1 
                 0 
                 Forced Bypass 
                 0.6 
               
               
                 0 
                 1 
                 1 
                 Boost 
                 &gt;0.8 
               
               
                 1 
                 0 
                 0 
                 2G Bias 
                 &lt;0.3 
               
               
                 1 
                 0 
                 1 
                 Reserved 
                 NA 
               
               
                 1 
                 1 
                 0 
                 Reserved 
                 NA 
               
               
                 1 
                 1 
                 1 
                 Reserved 
                 NA 
               
               
                   
               
            
           
         
       
     
       FIG. 22  shows an example of how the SMPS  802  of  FIG. 21  can respond to the various inputs of the reference voltage Vref, some of which are listed in Table 5. In the 2 G bias mode (e.g., Vref&lt;0.3V), the SMPS can output a voltage suitable for 2 G biasing purpose. In the buck mode (e.g., Vref between 0.3V and 0.4V), the SMPS can output a voltage that is, for example, half of the battery voltage. In the bypass mode (e.g., Vref between 0.4V and 0.8V), the SMPS can output a voltage that is substantially equal to the battery voltage. In the boost mode (e.g., Vref&gt;0.8V), the SMPS can output a boosted voltage that is proportional to Vref. Such an output can be utilized as, for example, a supply voltage for one or more PAs operating in HV mode. 
       FIG. 23  shows a block diagram of a power amplification system  850  including a boost converter  860 . In some embodiments, such a power amplification system can include high-voltage (HV) amplification capability. The power amplification system can include a power amplifier  862  and a supply system  858  configured to provide a supply voltage to the power amplifier  862 . The power amplifier  862  can be configured to receive an input radio-frequency signal and yield, as an output radio-frequency signal, an amplified version of the input radio-frequency signal. The supply system  858  can be configured to receive a battery voltage (Vbatt) and output a supply voltage (Vcc) to power the power amplifier  862 . The supply system  858  can include, for example, a switching mode power supply (SMPS). The supply system  858  includes a boost converter  860  that can be used to generate a supply voltage greater than (or equal to) the battery voltage. In some implementations, the supply system  858  can further include other components that can be used to, for example, generate a supply voltage less than the battery voltage. 
     The supply system  858  and power amplifier  862  can be controlled by a control system  852  that includes a supply system control component  854  and a power amplifier control component  856 . The control system  852  (e.g., the supply system control component  854 ) can be configured to provide a supply system control signal to the supply system to adjust the supply voltage based on a parameter associated with the power amplifier  862 . In particular, the control system  852  can be configured to provide a boost converter control signal to the boost converter  860  to adjust the supply voltage based on a parameter associated with the power amplifier  860 . 
     The boost converter control signal can be a reference voltage, a delta signal, an enable signal, or any other digital or analog signal. For example, the boost converter control signal can be a reference voltage. In response to an increased reference voltage, the boost converter  860  can be configured to adjust the supply voltage by increasing the supply voltage. Increasing the supply voltage can provide additional headroom for the power amplifier  862 . Similarly, in response to a decreased reference voltage, the boost converter  860  can be configured to adjust the supply voltage by decreasing the supply voltage. Decreasing the supply voltage can improve the power-added efficiency (PAE) of the power amplifier  862 . 
     As another example, the boost converter control signal can be a delta signal. In response to the delta signal, the boost converter  860  can be configured to adjust the supply voltage by increasing the supply voltage a preset amount. 
     In some implementations, the parameter associated with the power amplifier  862  can include a sensed condition of the power amplifier  862 . In some implementations, the power amplifier control component  856  (and, thus, the control system  852 ) can be configured to detect the sensed condition of the power amplifier. In some implementations, the control system  854  can be configured to receive a signal indicative of the sensed condition of the power amplifier  862 . For example, the supply system control component  854  can receive a signal from the power amplifier control component  856  indicative of the sensed condition of the power amplifier. As another example, the control system  852  can receive a signal from a transceiver indicative of the sensed condition of the power amplifier. In some implementations, the control system  852  can be configured to receive a signal based on the sensed condition of the power amplifier  862 . 
     The sensed condition of the power amplifier can be, for example, a saturation condition of the power amplifier  862 . The power amplifier  862  (or one or more transistors of the power amplifier  862 ) can be saturated, reducing the linearity of the power amplifier. 
     In some implementations, the parameter associated with the power amplifier  862  includes an operating mode of the power amplifier  862  and the boost converter control signal can be provided to the boost converter  860  to support the operating mode. For example, the operating mode can be an increased linearity mode. The increased linearity mode can be a high-voltage more or a high output power mode. 
     The control system  852  (e.g., the power amplifier control component  856 ) can be configured to provide a power amplifier control signal to the power amplifier  862 . The power amplifier control signal can be a bias signal (e.g., a bias voltage or a bias current) for biasing the power amplifier  862  (or one or more transistors of the power amplifier  862 ), an enable signal, or any other digital or analog signal. 
     Power amplification systems (such as the power amplification system  850  of  FIG. 23 ) having a capability to boost an input voltage (e.g., a battery voltage supplied by a battery) can provide flexibility in how such boosted supply can be utilized. In some embodiments, such a boosted supply voltage can be variable (e.g. as shown in  FIG. 22 ), depending on a control input such as a reference voltage (Vref). Accordingly, one can utilize such a variable nature of the boosted supply voltage in a number of ways, including implementation of a programmable supply voltage. 
     With the foregoing capability to provide a wide range of supply voltage from a boost converter, one can utilize such capability to obtain beneficial power amplifier performance improvements. Linearity is an example of such a power amplifier performance. Although various examples are described herein in the context of linearity, it will be understood that other power amplifier related performance can be adjusted utilizing the variable nature of the supply voltage. 
     It is noted that power amplifier non-linearity is often limited by amplitude modulation compression determined by the available level of the collector/drain voltage supply. Such amplitude modulation compression can impact other parameters such as in-band error vector magnitude (EVM) and spectral regrowth adjacent channel leakage ratio (ACLR) linearity performance required for radio conformance, and can even impact receiver sensitivity if a duplex gap is sufficiently small. 
       FIG. 24  shows an example of how the foregoing collector supply voltage limitation can be removed or substantially loosened with a variable supply voltage from a boost converter  870 . Such a boost converter is shown to generate and provide a supply voltage Vcc to a power amplifier, to thereby allow the power amplifier to be operated with improved linearity. 
     For example, with the boost converter  870 , a nominal optimal value Vcc nom  can be provided to the power amplifier to achieve a given level of linearity. However, when additional linearity is desired (e.g., with large envelope ( 872 ) amplitudes), setting a higher supply voltage level provides more headroom, and therefore better linearity. Such an increase in headroom may result in degradation of DC consumption and efficiency performance; however, such sacrifice are only suffered in operating situations involving higher level of emission and linearity performance. 
     In the example of  FIG. 24 , the foregoing increased headroom can be achieved by increasing the Vcc from the nominal value Vcc nom  by an amount ΔV so as to yield an increased supply voltage Vcc nom +ΔV. The increased amount ΔV can be selected to accommodate high emission levels as depicted by the example envelope  872 . In some embodiments, operations related to the generation of Vcc by the boost converter  870  can be programmed with respect to values associated with either or both of Vcc nom  and ΔV. 
     The foregoing example where Vcc can be increased by programmed operation of the boost converter is an example of a more general concept as described herein, in which the output of a boost converter can be adjusted based on some power amplifier related parameter. 
     Examples of Products: 
       FIG. 25  shows that in some embodiments, some or all of an HV APT power amplification system having one or more features as described herein can be implemented in a module. Such a module can be, for example, a front-end module (FEM). In the example of  FIG. 25 , a module  300  can include a packaging substrate  302 , and a number of components can be mounted on such a packaging substrate. For example, an FE-PMIC component  102 , a power amplifier assembly  104 , a match component  106 , and a duplexer assembly  108  can be mounted and/or implemented on and/or within the packaging substrate  302 . Other components such as a number of SMT devices  304  and an antenna switch module (ASM)  306  can also be mounted on the packaging substrate  302 . Although all of the various components are depicted as being laid out on the packaging substrate  302 , it will be understood that some component(s) can be implemented over or under other component(s). 
     In some implementations, a power amplification system having one or more features as described herein can be included in an RF device such as a wireless device. Such a power amplification system can be implemented in the wireless device as one or more circuits, as one or more die, as one or more packaged modules, or in any combination thereof. In some embodiments, such a wireless device can include, for example, a cellular phone, a smart-phone, a hand-held wireless device with or without phone functionality, a wireless tablet, etc. 
       FIG. 26  depicts an example wireless device  400  having one or more advantageous features described herein. In the context of a module having one or more features as described herein, such a module can be generally depicted by a dashed box  300 , and can be implemented as, for example, a front-end module (FEM). 
     Referring to  FIG. 26 , power amplifiers (PAs)  420  can receive their respective RF signals from a transceiver  410  that can be configured and operated to generate RF signals to be amplified and transmitted, and to process received signals. The transceiver  410  is shown to interact with a baseband sub-system  408  that is configured to provide conversion between data and/or voice signals suitable for a user and RF signals suitable for the transceiver  410 . The transceiver  410  can also be in communication with a power management component  406  that is configured to manage power for the operation of the wireless device  400 . Such power management can also control operations of the baseband sub-system  408  and the module  300 . 
     The baseband sub-system  408  is shown to be connected to a user interface  402  to facilitate various input and output of voice and/or data provided to and received from the user. The baseband sub-system  408  can also be connected to a memory  404  that is configured to store data and/or instructions to facilitate the operation of the wireless device, and/or to provide storage of information for the user. 
     In the example wireless device  400 , outputs of the PAs  420  are shown to be matched (via respective match circuits  422 ) and routed to their respective duplexers  424 . In some embodiments, the match circuit  422  can be similar to the example matching circuits  172   a - 172   c  described herein in reference to  FIG. 7 . As also described herein in reference to  FIG. 7 , the outputs of the PAs  420  can be routed to their respective duplexers  424  without impedance transformation (e.g., with load transformation  116  in  FIG. 6 ) when the PAs  420  are operated in an HV mode with HV supply. Such amplified and filtered signals can be routed to an antenna  416  through an antenna switch  414  for transmission. In some embodiments, the duplexers  424  can allow transmit and receive operations to be performed simultaneously using a common antenna (e.g.,  416 ). In  FIG. 26 , received signals are shown to be routed through the duplexers  424  to “Rx” paths that can include, for example, one or more low-noise amplifiers (LNAs). 
     In the example of  FIG. 26 , the foregoing HV supply for the PAs  420  can be provided by an HV component  102 . Such an HV component can include, for example, a boost DC/DC converter as described herein. 
     A number of other wireless device configurations can utilize one or more features described herein. For example, a wireless device does not need to be a multi-band device. In another example, a wireless device can include additional antennas such as diversity antenna, and additional connectivity features such as Wi-Fi, Bluetooth, and GPS. 
     As described herein, one or more features of the present disclosure can provide a number of advantages when implemented in systems such as those involving the wireless device of  FIG. 26 . For example, significant current drain reduction can be achieved through an elimination or reduction of output loss. In another example, lower bill of materials count can be realized for the power amplification system and/or the wireless device. In yet another example, independent optimization or desired configuration of each supported frequency band can be achieved due to, for example, separate PAs for their respective frequency bands. In yet another example, optimization or desired configuration of maximum or increased output power can be achieved through, for example, a boost supply voltage system. In yet another example, a number of different battery technologies can be utilized, since maximum or increased power is not necessarily limited by battery voltage. 
     One or more features of the present disclosure can be implemented with various cellular frequency bands as described herein. Examples of such bands are listed in Table 6. It will be understood that at least some of the bands can be divided into sub-bands. It will also be understood that one or more features of the present disclosure can be implemented with frequency ranges that do not have designations such as the examples of Table 6. 
     
       
         
           
               
               
               
               
               
             
               
                   
                 TABLE 6 
               
               
                   
                   
               
               
                   
                   
                   
                 Tx Frequency 
                 Rx Frequency 
               
               
                   
                 Band 
                 Mode 
                 Range (MHz) 
                 Range (MHz) 
               
               
                   
                   
               
             
            
               
                   
                 B1 
                 FDD 
                 1,920-1,980 
                 2,110-2,170 
               
               
                   
                 B2 
                 FDD 
                 1,850-1,910 
                 1,930-1,990 
               
               
                   
                 B3 
                 FDD 
                 1,710-1,785 
                 1,805-1,880 
               
               
                   
                 B4 
                 FDD 
                 1,710-1,755 
                 2,110-2,155 
               
               
                   
                 B5 
                 FDD 
                 824-849 
                 869-894 
               
               
                   
                 B6 
                 FDD 
                 830-840 
                 875-885 
               
               
                   
                 B7 
                 FDD 
                 2,500-2,570 
                 2,620-2,690 
               
               
                   
                 B8 
                 FDD 
                 880-915 
                 925-960 
               
               
                   
                 B9 
                 FDD 
                 1,749.9-1,784.9 
                 1,844.9-1,879.9 
               
               
                   
                 B10 
                 FDD 
                 1,710-1,770 
                 2,110-2,170 
               
               
                   
                 B11 
                 FDD 
                 1,427.9-1,447.9 
                 1,475.9-1,495.9 
               
               
                   
                 B12 
                 FDD 
                 699-716 
                 729-746 
               
               
                   
                 B13 
                 FDD 
                 777-787 
                 746-756 
               
               
                   
                 B14 
                 FDD 
                 788-798 
                 758-768 
               
               
                   
                 B15 
                 FDD 
                 1,900-1,920 
                 2,600-2,620 
               
               
                   
                 B16 
                 FDD 
                 2,010-2,025 
                 2,585-2,600 
               
               
                   
                 B17 
                 FDD 
                 704-716 
                 734-746 
               
               
                   
                 B18 
                 FDD 
                 815-830 
                 860-875 
               
               
                   
                 B19 
                 FDD 
                 830-845 
                 875-890 
               
               
                   
                 B20 
                 FDD 
                 832-862 
                 791-821 
               
               
                   
                 B21 
                 FDD 
                 1,447.9-1,462.9 
                 1,495.9-1,510.9 
               
               
                   
                 B22 
                 FDD 
                 3,410-3,490 
                 3,510-3,590 
               
               
                   
                 B23 
                 FDD 
                 2,000-2,020 
                 2,180-2,200 
               
               
                   
                 B24 
                 FDD 
                 1,626.5-1,660.5 
                 1,525-1,559 
               
               
                   
                 B25 
                 FDD 
                 1,850-1,915 
                 1,930-1,995 
               
               
                   
                 B26 
                 FDD 
                 814-849 
                 859-894 
               
               
                   
                 B27 
                 FDD 
                 807-824 
                 852-869 
               
               
                   
                 B28 
                 FDD 
                 703-748 
                 758-803 
               
               
                   
                 B29 
                 FDD 
                 N/A 
                 716-728 
               
               
                   
                 B30 
                 FDD 
                 2,305-2,315 
                 2,350-2,360 
               
               
                   
                 B31 
                 FDD 
                 452.5-457.5 
                 462.5-467.5 
               
               
                   
                 B33 
                 TDD 
                 1,900-1,920 
                 1,900-1,920 
               
               
                   
                 B34 
                 TDD 
                 2,010-2,025 
                 2,010-2,025 
               
               
                   
                 B35 
                 TDD 
                 1,850-1,910 
                 1,850-1,910 
               
               
                   
                 B36 
                 TDD 
                 1,930-1,990 
                 1,930-1,990 
               
               
                   
                 B37 
                 TDD 
                 1,910-1,930 
                 1,910-1,930 
               
               
                   
                 B38 
                 TDD 
                 2,570-2,620 
                 2,570-2,620 
               
               
                   
                 B39 
                 TDD 
                 1,880-1,920 
                 1,880-1,920 
               
               
                   
                 B40 
                 TDD 
                 2,300-2,400 
                 2,300-2,400 
               
               
                   
                 B41 
                 TDD 
                 2,496-2,690 
                 2,496-2,690 
               
               
                   
                 B42 
                 TDD 
                 3,400-3,600 
                 3,400-3,600 
               
               
                   
                 B43 
                 TDD 
                 3,600-3,800 
                 3,600-3,800 
               
               
                   
                 B44 
                 TDD 
                 703-803 
                 703-803 
               
               
                   
                   
               
            
           
         
       
     
     In the description herein, references are made to various forms of impedance. For example, a PA is sometimes referred to as driving a load impedance of a downstream component such as a filter. In another example, a PA is sometimes referred to as having an impedance value. For the purpose of description, it will be understood that such impedance-related references to a PA may be used interchangeably. Further, an impedance of a PA can include its output impedance as seen on the output side of the PA. Accordingly, such a PA being configured to drive a load impedance of a downstream component can include the PA having an output impedance that is approximately same as the load impedance of the downstream component. 
     Unless the context clearly requires otherwise, throughout the description and the claims, the words “comprise,” “comprising,” and the like are to be construed in an inclusive sense, as opposed to an exclusive or exhaustive sense; that is to say, in the sense of “including, but not limited to.” The word “coupled”, as generally used herein, refers to two or more elements that may be either directly connected, or connected by way of one or more intermediate elements. Additionally, the words “herein,” “above,” “below,” and words of similar import, when used in this application, shall refer to this application as a whole and not to any particular portions of this application. Where the context permits, words in the above Description using the singular or plural number may also include the plural or singular number respectively. The word “or” in reference to a list of two or more items, that word covers all of the following interpretations of the word: any of the items in the list, all of the items in the list, and any combination of the items in the list. 
     The above detailed description of embodiments of the invention is not intended to be exhaustive or to limit the invention to the precise form disclosed above. While specific embodiments of, and examples for, the invention are described above for illustrative purposes, various equivalent modifications are possible within the scope of the invention, as those skilled in the relevant art will recognize. For example, while processes or blocks are presented in a given order, alternative embodiments may perform routines having steps, or employ systems having blocks, in a different order, and some processes or blocks may be deleted, moved, added, subdivided, combined, and/or modified. Each of these processes or blocks may be implemented in a variety of different ways. Also, while processes or blocks are at times shown as being performed in series, these processes or blocks may instead be performed in parallel, or may be performed at different times. 
     The teachings of the invention provided herein can be applied to other systems, not necessarily the system described above. The elements and acts of the various embodiments described above can be combined to provide further embodiments. 
     While some embodiments of the inventions have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the disclosure.