Patent Publication Number: US-9425319-B2

Title: Integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a divisional application of U.S. application Ser. No. 13/759,156, filed Feb. 5, 2013, which is hereby incorporated in its entirety by reference. 
    
    
     TECHNICAL FIELD 
     The technical field relates generally to integrated circuits and methods for fabricating integrated circuits, and more particularly relates to integrated circuits including FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating such integrated circuits. 
     BACKGROUND 
     Transistors such as metal oxide semiconductor field effect transistors (MOSFETs) or simply field effect transistors (FETs) or MOS transistors are the core building blocks of the vast majority of semiconductor integrated circuits (ICs). A FET includes source and drain regions between which a current can flow through a channel under the influence of a bias applied to a gate electrode that overlies the channel. Some semiconductor ICs, such as high performance microprocessors, can include millions of FETs. For such ICs, decreasing transistor size and thus increasing transistor density has traditionally been a high priority in the semiconductor manufacturing industry. Transistor performance, however, must be maintained even as the transistor size decreases. 
     A FINFET is a type of transistor that lends itself to the goals of reducing transistor size while maintaining transistor performance. The FINFET is a non-planar, three dimensional transistor formed in a thin fin that extends upwardly from a semiconductor substrate. One important challenge with the implementation of FINFETs is the formation of contacts to the non-planar source and drain regions of the fins. There are two approaches for contact formation for FINFETs: formation of contacts to merged fins and formation of contacts to unmerged fins. 
     For merged fins, a layer of epitaxial silicon is grown on the fins. As a result of the epitaxial growth, adjacent fins become merged. The resulting contact area is large and lacks topographical variation. Therefore, conventional silicide processes can be used to successfully form silicide contacts on the top surfaces of the merged fins. 
     For unmerged fins, a separate layer of epitaxial doped silicon or silicon germanium is grown on the top of each fin without the epitaxial growth merging adjacent fins. Unmerged fins are required, for example, for Static Random Access Memory (SRAM) devices and the like. Unmerged fins permit the design of SRAM cells with tighter pitch, making the overall chip layout smaller. Interface resistivity (Rs) is a significant factor in the overall contact resistance of an integrated circuit, and the plurality of unmerged fins provides much more contact formation area due to the higher surface area exposed to the silicidation process. The total resistance from the contacts can be significantly lower than that of a merged set of fins, which have a smaller contact surface area and thus higher resistance. However, during contact formation, conductive contact-forming material can be deposited between the lower sections of unmerged fins, leading to higher parasitic capacitance. Lowering the contact resistance of many small unmerged fins and decreasing parasitic capacitance can make a significant difference in circuit performance. 
     Accordingly, it is desirable to provide integrated circuits that include FINFET devices with lower contact resistance and reduced parasitic capacitance and methods for fabricating such integrated circuits. Moreover, it is desirable to provide integrated circuits that include FINFET devices with lower contact resistance unmerged fins while not increasing parasitic capacitance. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background. 
     BRIEF SUMMARY 
     Integrated circuits and methods for fabricating integrated circuits are provided herein. In accordance with an exemplary embodiment, a method for fabricating an integrated circuit includes forming a first fin and a second fin adjacent to each other extending from a semiconductor substrate. A silicon-containing material is selectively epitaxially grown on the first and second fins to form a first epi-portion overlying a first upper section of the first fin and a second epi-portion overlying a second upper section of the second fin. The first and second epi-portions are spaced apart from each other. A first silicide layer is formed overlying the first epi-portion and a second silicide layer is formed overlying the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric material is deposited overlying the first and second silicide layers to form a dielectric spacer that spans the lateral gap. The dielectric material that overlies portions of the first and second silicide layers laterally above the dielectric spacer is removed while leaving the dielectric spacer intact. A contact-forming material is deposited overlying the dielectric spacer and the portions of the first and second silicide layers. 
     In accordance with another exemplary embodiment, a method for fabricating an integrated circuit is provided. The method includes forming a first fin and a second fin adjacent to each other extending from a semiconductor substrate. A silicon-containing material is selectively epitaxially grown on the first and second fins to form a first diamond-shaped/cross-section epi-portion disposed on a first upper section of the first fin and a second diamond-shaped/cross-section epi-portion disposed on a second upper section of the second fin. The first diamond-shaped/cross-section epi-portion has a first upper surface and a first lower surface. The second diamond-shaped/cross-section epi-portion has a second upper surface and a second lower surface. The first and second diamond-shaped/cross-section epi-portions are spaced apart from each other. A first silicide layer is formed along the first upper and lower surfaces of the first diamond-shaped/cross-section epi-portion and a second silicide layer is formed along the second upper and lower surfaces of the second diamond-shaped/cross-section epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric material is deposited overlying the first and second silicide layers to form a dielectric spacer that closes off the lateral gap. The dielectric material is etched to expose upper portions of the first and second silicide layers that overlie the first and second upper surfaces of the first and second diamond-shaped/cross-section epi-portions, respectively, while leaving the dielectric spacer intact. An ILD layer of insulating material is deposited overlying the dielectric spacer and the upper portions of the first and second silicide layers. The ILD layer is etched to form a contact opening that is formed through the ILD layer to expose the upper portions of the first and second silicide layers. A contact-forming material is deposited into the contact opening. 
     In accordance with another exemplary embodiment, an integrated circuit is provided. The integrated circuit includes a semiconductor substrate. A first fin and a second fin are adjacent to each other extending from the semiconductor substrate. The first fin has a first upper section and the second fin has a second upper section. A first epi-portion overlies the first upper section and a second epi-portion overlies the second upper section. The first and second epi-portions are spaced apart from each other. A first silicide layer overlies the first epi-portion and a second silicide layer overlies the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric spacer is formed of a dielectric material and spans the lateral gap. A contact-forming material overlies the dielectric spacer and portions of the first and second silicide layers that are laterally above the dielectric spacer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The various embodiments will hereinafter be described in conjunction with the following drawing figures, wherein like numerals denote like elements, and wherein: 
         FIG. 1  illustrates a FINFET in a partially cut away perspective view; and 
         FIGS. 2-9  illustrate in cross-sectional views an integrated circuit and methods for fabricating an integrated circuit during various stages of its fabrication in accordance with an exemplary embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     The following Detailed Description is merely exemplary in nature and is not intended to limit the various embodiments or the application and uses thereof. Furthermore, there is no intention to be bound by any theory presented in the preceding background or the following detailed description. 
     Integrated circuits (ICs) can be designed with millions of transistors. Many ICs are designed using metal oxide semiconductor (MOS) transistors, also known as field effect transistors (FETs) or MOSFETs. Although the term “MOS transistor” properly refers to a device having a metal gate electrode and an oxide gate insulator, that term used herein refers to any device that includes a conductive gate electrode (whether metal or other conductive material) that is positioned over a gate insulator (whether oxide or other insulator) which, in turn, is positioned over a semiconductor substrate. One type of MOS transistor used in the design of ICs is a FINFET, which can be fabricated as a P-channel transistor or as an N-channel transistor, and can also be fabricated with or without mobility enhancing stress features. A circuit designer can mix and match device types, using P-channel and N-channel, FINFET and other types of MOS transistors, stressed and unstressed, to take advantage of the best characteristics of each device type as they best suit the circuit being designed. 
     The following brief explanation is provided to identify some of the unique features of FINFETs.  FIG. 1  illustrates, in a cut away perspective view, a portion of a FINFET integrated circuit (IC)  10 . As illustrated, the IC  10  includes two fins  12  and  14  that are formed from and extend upwardly from a semiconductor substrate  16  (e.g., a bulk semiconductor substrate or silicon-on-insulator (SOI) semiconductor substrate). A gate electrode  18  overlies the two fins  12  and  14  and is electrically insulated from the fins  12  and  14  by a gate insulator (not illustrated). An end  20  of the fin  12  is appropriately impurity doped to form a source of a FINFET  22 , and an end  24  of the fin  12  is appropriately impurity doped to form a drain of the FINFET  22 . Similarly, the ends  26  and  28  of the fin  14  form the source and drain, respectively, of another FINFET  30 . 
     The illustrated portion of IC  10  thus includes two FINFETs  22  and  30  having a common gate electrode  18 . In another configuration, if the ends  20  and  26  that form the sources are electrically coupled together and the ends  24  and  28  that form the drains are electrically coupled together, the structure would be a two-fin FINFET having twice the gate width of either FINFET  22  or  30 . An oxide layer  32  (e.g., deposited onto the semiconductor substrate  16  if the semiconductor substrate  16  is a bulk semiconductor substrate, or alternatively, is part of the semiconductor substrate  16  if the semiconductor substrate  16  is an SOI semiconductor substrate) forms electrical isolation between the fins  12  and  14  and between adjacent devices as is needed for the circuit being implemented. The channel of the FINFET  22  extends along a sidewall  34  of the fin  12  beneath the gate electrode  18 , along a top  36  of the fin  12 , as well as along an opposite sidewall not visible in this perspective view. The advantage of the FINFET structure is that although the fin  12  has only the narrow width represented by the arrows  38 , the channel has a width represented by at least twice the height of the fin  12  above the oxide layer  32 . The channel width thus can be much greater than fin width. 
     The fins  12  and  14  are formed according to known processes. For instance, when using a SOI semiconductor substrate as the semiconductor substrate  16 , portions of the top silicon layer of the semiconductor substrate  16  are etched or otherwise removed leaving the fins  12  and  14  formed from silicon remaining on the underlying oxide layer  32 . As shown, the gate electrode  18  is formed across the fins  12  and  14 . Gate oxide and/or nitride capping layers (not shown) may be deposited over the fins  12  and  14  before the gate electrode  18  is formed. The gate electrode  18  is formed by typical lithographic processing. 
       FIGS. 2-9  illustrate methods for forming the IC  10  in accordance with various embodiments. In particular,  FIGS. 2-9  are cross-sectional views of the source or drain regions  20 ,  26  or  24 ,  28  of the fins  12  and  14  shown in  FIG. 1  during various subsequent stages in the fabrication of the IC  10 . The described process steps, procedures, and materials are to be considered only as exemplary embodiments designed to illustrate to one of ordinary skill in the art methods for practicing the methods contemplated herein; the methods are not limited to these exemplary embodiments. The illustrated portion of the IC  10  as shown includes only two FINFETs  22  and  30 , although those of skill in the art will recognize that an actual IC could include a large number of such transistors. Various steps in the manufacture of ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well known process details. 
       FIG. 2  illustrates, in cross-sectional view, a portion of the IC  10  at an intermediate fabrication stages in accordance with an exemplary embodiment. As discussed above, the fins  12  and  14  have been formed adjacent to each other extending from the semiconductor substrate  16  and extending above the oxide layer  32 . Further patterning, implanting, and annealing processes are employed to form wells  40  and  42  in the semiconductor substrate  16  below the fins  12  and  14 . A selective epitaxial growth process is used to grow a silicon-containing material overlying the upper sections  48  and  50  of the fins  12  and  14  to form epi-portions  44  and  46 , respectively. In an exemplary embodiment, the silicon-containing material is silicon phosphorus (SiP) for N-type FINFETs or silicon germanium (SiGe) for P-type FINFETs. 
     The epi-portions  44  and  46  are spaced apart from each other such that the fins  12  and  14  are not merged to define unmerged fins  52  and  54 . As illustrated, the epi-portions  44  and  46  are configured as having “diamond-shaped/cross-sections.” The diamond-shaped/cross-sections of the epi-portions  44  and  46  form due to the slower rate of growth of the silicon-containing material on the ( 111 ) surface of the fins  12  and  14 . As such, the epi-portions  44  and  46  have corresponding upper surfaces  56   a ,  56   b ,  58   a , and  58   b  and lower surfaces  60   a ,  60   b ,  62   a , and  62   b . The lower surfaces  60   a ,  60   b ,  62   a , and  62   b  face towards the semiconductor substrate  16  and the upper surfaces  56   a ,  56   b ,  58   a , and  58   b  are positioned beyond the lower surfaces  60   a ,  60   b ,  62   a , and  62   b  facing away from the semiconductor substrate  16 . 
       FIG. 3  illustrates, in cross-sectional view, a portion of the IC  10  at a further advanced fabrication stage in accordance with an exemplary embodiment. Using a silicidation process, silicide layers  61  and  63  are formed over the epi-portions  44  and  46 , respectively. The silicide layers  61  and  63  are formed by depositing a silicide-forming metal overlying the upper surfaces  56   a ,  56   b ,  58   a , and  58   b  and the lower surfaces  60   a ,  60   b ,  62   a , and  62   b  of the epi-portions  44  and  46 , and heating the silicide-forming metal, for example by rapid thermal anneal (RTA), to cause the silicide-forming metal to react with exposed silicon-containing material in the epi-portions  44  and  46 . Examples of silicide-forming metals include, but are not limited to, nickel, cobalt, and alloys thereof. The silicide-forming metal can be deposited, for example by sputtering, to a thickness of from about 3 to about 10 nm, such as about 7 nm. Any unreacted silicide-forming metal can be removed, for example, by wet etching in a H 2 O 2 /H 2 SO 4  or HNO 3 /HCl solution. In an exemplary embodiment, the silicide layers  61  and  63  each have a thickness of from about 3 to about 10 nm. Notably, the silicide formation at both the bottoms and tops of the diamond shaped epi-portions  44  and  46  helps maximizes the contact surface area thus reducing contact resistance. 
     As illustrated, the silicide layers  61  and  63  are spaced apart from each other such that a lateral gap  64  is defined between the silicide layers  61  and  63  proximate the mid-corners  66  and  68  of the diamond-shaped/cross-section of the epi-portions  44  and  46 . In an exemplary embodiment, the lateral gap is from about 3 to about 7 nm. 
     The process continues as illustrated in  FIG. 4  by depositing a dielectric material over the oxide layer  32  and the unmerged fins  52  and  54  including the silicide layers  61  and  63 . In an exemplary embodiment, the dielectric material is deposited using an atomic layer deposition (ALD) process and comprises silicon nitride (SiN), which may be doped with carbon atoms (C), nitrogen atoms (N), and/or oxygen atoms (O). 
     During deposition, the dielectric material accumulates on the upper and lower portions  74   a ,  74   b ,  76   a ,  76   b ,  78   a ,  78   b ,  80   a , and  80   b  of the silicide layers  61  and  63  and the surrounding area to form dielectric films  70  and  72 . As the thicknesses of the dielectric films  70  and  72  increase, the dielectric films  70  and  72  merged together proximate the mid-corners  66  and  68  of the diamond-shaped/cross-sections of the epi-portions  44  and  46  to integrally form a dielectric spacer  82  (indicated by dashed lines). As illustrated, the dielectric spacer  82  spans and closes off the lateral gap  64 . 
     In an exemplary embodiment, the dielectric spacer  82  has a lateral dimension of at least about 3 nm, such as about 3 to about 10 nm, for example from about 3 to about 7 nm to close off the lateral gap  64 . As illustrated, to facilitate keeping the dielectric spacer  82  intact during subsequent processing, as will be discussed in further detail below, the upper dielectric film sections  84  and  86  that overlie the upper portions  74   a ,  74   b ,  76   a , and  76   b  of the silicide layers  61  and  63 , respectively, are formed thicker (e.g., with overgrowth) than the lower dielectric film sections  88  and  90  that overlie the lower portions  78   a ,  78   b ,  80   a , and  80   b  of the silicide layers  61  and  63 , respectively. In an exemplary embodiment, the upper dielectric film sections  84  and  86  are formed each having a thickness of about 5 to about 15 nm and the lower dielectric film sections  88  and  90  are each formed having a thickness of from about 2 to about 7 nm. As illustrated, a void  92  is disposed beneath the dielectric spacer  82  between the semiconductor substrate  16 , the lower sections  94  and  96  of the fins  12  and  14 , and the lower dielectric film sections  88  and  90 . Notably, in an exemplary embodiment, the void  92  enables air trapping beneath the dielectric spacer  82 , and together with the low-k characteristics of the dielectric spacer  82 , enables very low parasitic capacitance. 
       FIG. 5  illustrates, in cross-sectional view, a portion of the IC  10  at a further advanced fabrication stage in accordance with an exemplary embodiment. The upper dielectric film sections  84  and  86  (see  FIG. 4 ) are removed by etching the dielectric material to expose the upper portions  74   a ,  74   b ,  76   a , and  76   b  of the silicide layers  61  and  63  while leaving the dielectric spacer  82  intact. In one embodiment, the dielectric material is etched using a dry etching process, such as a plasma etching process, for example reactive ion etching (RIE). In another embodiment, the dielectric material is etched using a wet etching process, such as a hot phosphoric acid etching process at a temperature of about 160 to about 170° C. By leaving the dielectric spacer  82  intact, the void  92  is protectively covered to reduce, minimize, or prevent further deposition of any conducting materials (e.g., contact-forming material, such as W and/or the like) adjacent to and in between the lower sections  94  and  96  of the fins  12  and  14  that might otherwise increase parasitic capacitance. 
     The method continues as illustrated in  FIGS. 6 and 7  by forming a nitride etch layer  98  overlying the dielectric spacer  82  and the upper portions  74   a ,  74   b ,  76   a , and  76   b  of the silicide layers  61  and  63 . An ILD layer  100  of insulating material (e.g., silicon oxide) is then deposited overlying the nitride etch stop layer  98 . In an exemplary embodiment, the ILD layer  100  is deposited by a low pressure chemical vapor deposition (LPCVD) process. The ILD layer  100  is then planarized, for example, by a chemical mechanical planarization (CMP) process. 
       FIGS. 8-9  illustrate, in cross sectional views, the IC  10  at further advanced fabrication stages in accordance with an exemplary embodiment. The method continues by etching through the ILD layer  100  and the nitride etch stop layer  98  to form a contact opening  102 . As illustrated, the contact opening  102  exposes the dielectric spacer  82  and the upper portions  74   a ,  74   b ,  76   a , and  76   b  of the silicide layers  61  and  63 . A contact-forming material  103  (e.g., conductive metal) is deposited into the contact opening  102  to form a contact plug  104  that overlies the dielectric spacer  82  and the upper portions  74   a ,  74   b ,  76   a , and  76   b  of the silicide layers  61  and  63 . In an exemplary embodiment, the contact-forming material  103  is tungsten (W). As illustrated, the void  92 , which has been protectively covered by the dielectric spacer  82  during deposition of the contact forming material  103 , is substantially free of the contact-forming material  103 , thereby reducing parasitic capacitance compared to conventional ICs with unmerged fins. Additionally, the contact plug  104  contacts the silicide layers  61  and  63  horizontally up from about the mid-corners  66  and  68  of the epi-portions  44  and  46  to the uppermost portions  106  and  108  of the silicide layers  61  and  63 . As such, the FINFETs  22  and  30  have more contact area and thus lower contact resistance than conventional FINFET devices with unmerged fins that have small contacts formed only at the very tops of the fins. Any excess contact-forming material that is disposed above the ILD layer  100  is then removed using CMP. 
     Accordingly, integrated circuits including FINFET devices and methods for fabricating such integrated circuits have been described. In an exemplary embodiment, unmerged fins are formed in which a first fin has a first epi-portion and a second fin has a second epi-portion. A first silicide layer is formed overlying a first epi-portion and a second silicide layer is formed overlying the second epi-portion. The first and second silicide layers are spaced apart from each other to define a lateral gap. A dielectric material is deposited overlying the first and second silicide layers to form a dielectric spacer that spans the lateral gap. The dielectric material that overlies portions of the first and second silicide layers laterally above the dielectric spacer is removed while leaving the dielectric spacer intact. A contact-forming material is deposited overlying the dielectric spacer and the portions of the first and second silicide layers. 
     While at least one exemplary embodiment has been presented in the foregoing detailed description of the disclosure, it should be appreciated that a vast number of variations exist. It should also be appreciated that the exemplary embodiment or exemplary embodiments are only examples, and are not intended to limit the scope, applicability, or configuration of the disclosure in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the disclosure. It being understood that various changes may be made in the function and arrangement of elements described in an exemplary embodiment without departing from the scope of the disclosure as set forth in the appended claims.