Patent Publication Number: US-10789046-B1

Title: Low-power fast current-mode meshed multiplication for multiply-accumulate in artificial intelligence

Description:
CROSS-REFERENCE TO RELATED PATENT APPLICATIONS 
     The present disclosure claims priority from U.S. Provisional Patent Application Ser. No. 62/856,889 filed Jun. 4, 2019 and which is herein specifically incorporated by reference in its entirety. Furthermore, the present disclosure claims priority from U.S. Provisional Patent Application Ser. No. 62/880,885 filed Jul. 31, 2019 and which is herein specifically incorporated by reference in its entirety. Moreover, the present disclosure claims priority from U.S. Provisional Patent Application Ser. No. 62/912,407 filed Oct. 8, 2019 and which is herein specifically incorporated by reference in its entirety. The present disclosure claims priority from U.S. Provisional Patent Application Ser. No. 62/865,845 filed Jun. 24, 2019 and which is herein specifically incorporated by reference in its entirety. Furthermore, the present disclosure claims priority from U.S. Provisional Patent Application Ser. No. 62/862,772 filed Jun. 18, 2019 and which is herein specifically incorporated by reference in its entirety. The present invention is a continuation-in-part of and claims the benefit of priority from U.S. patent application Ser. No. 16/381,245 filed on Apr. 11, 2019; which claims priority from U.S. Provisional Patent Application Ser. No. 62/658,678 filed on Apr. 17, 2018, and which are herein specifically incorporated by reference in their entirety. 
    
    
     FIELD OF DISCLOSURE 
     This disclosure relates to improvements in mixed-signal data-converters, multipliers, and multiply-accumulate for use in integrated circuits (ICs) in general. The disclosure more specifically relates to emerging artificial intelligence and machine learning (AI &amp; ML) applications that are mobile, portable, and near edge and or on sensors, which require ultra-low-power, small-size, low cost (for high-volumes) and asynchronous operations. 
     BACKGROUND 
     One-size-fit-all and standard digital solutions for AI &amp; ML applications offer ease of interface compatibility, programming flexibility, and fast time to market advantages. However, as AI &amp; ML applications expand their foot-print closer to the edge of the network and or on intelligent sensors (where signals are gathered and processed together), more application specific and custom solutions may be required to meet low-power, low-cost, and high-volume objectives. Majority of digital AI &amp; ML chips that are generally deployed on the cloud require bleeding edge deep sub-micron (e.g., 20 nano-meter and smaller) manufacturing which are expensive and power hungry. As such, to deploy AI &amp;ML solutions closer to the edge of communication networks or near sensors and mobile devices, the high cost and high-power consumption of bleeding edge digital solutions become prohibitive. Approximate computing, that can utilize analog and mixed-signal processing, enables AI &amp; ML solutions including in for example in robotics, medical, mobile, drone, portable and private surveillance, and other near sensor applications that need privacy, cannot afford latency, require low cost and low power consumption along with asynchronous signal processing. Moreover, cheaper main-stream manufacturing (e.g., 45 nano-meter to 90 nano-meter) can be sufficient for analog and mixed-signal processors to perform AI &amp; ML operations at lower power consumptions with substantially lower costs. 
     An objective of the present disclosure is to provide data-converters that can be integrated with and seamlessly interface with standard digital logic (e.g., sea of gates), including for hybrid AI &amp; ML signal processing (e.g., main digital signal processors combined with analog mixed-signal accelerators and or co-processors). 
     Another objective of the present disclosure is to provide current-mode data-converters, multipliers, and multiply-accumulate circuits that can interface with digital systems and that can perform some of the signal processing functions in analog and or mixed-signal for AI &amp; ML applications, and at low power consumption and cost effectively. Such current-mode data-converters, multipliers, and multiply-accumulate circuits can also be used in conjunction with fully-digital systems to facilitate hybrid mixed-signal, analog, and digital signal processing (or as acceleration IC engines) for AI &amp; ML applications. 
     Another objective of the present disclosure is to perform some of the signal condition functions of AI &amp; ML asynchronously by utilizing clock-free data-converters, multipliers, and multiply-accumulate circuits, which frees signal processing and computations from clock related cycle-time delay, dynamic power consumption, and noise related to free running clocks. 
     Substantial amount of current consumption in ML &amp; AI computation (based on conventional digital processors) is consumed during memory read-write cycle of conventional digital signal processing. Another objective of this disclosure is to facilitate mixed-mode signal processing for ML &amp; AI that is memory free and thus reduces power consumption. 
     Conventional AI &amp; ML digital signal processing rely on central processors on the cloud which increases the overall application power consumption due in part to the back-and-forth communications with the cloud-based digital processors. This introduces computation latency that may be unacceptable in some applications such as medical. Another objective of this disclosure is to facilitate low power and low cost mixed-mode signal processing for ML &amp; AI that can be performed at the edge or on sensors to help eliminate the latency. 
     Generally, performing AI &amp; ML signal processing on the cloud has privacy risks. Another objective of the present disclosure is to enable low power and low-cost AI &amp; ML analog and mixed signal processing at the edge or on the sensors to avoid sending and receiving information to and from the cloud. 
     Another objective of the present disclosure is to provide AI &amp; ML signal processing and computation platforms, with current-mode data-converters, multipliers, and multiply-accumulate circuits that can be manufactured in main-stream Complementary-Metal-Oxide-Semiconductor (CMOS) fabrication which is not only low cost, rugged, and proven but also that is compatible with digital systems, which facilitates ease of interface with existing digital hardware and software platforms. 
     Another objective of this disclosure is to provide AI &amp; ML signal processing and computation platforms utilizing current-mode data-converters, multipliers, and multiply-accumulate circuits that can operate with low voltage power supplies suitable for portable and battery-operated AI&amp; ML applications. 
     Another objective of this disclosure is to provide AI &amp; ML signal processing and computation in current-mode, which is inherently fast (in part) because voltage swings are kept to a minimal in current-mode signal processing. Moreover, current-mode signal processing enables current-mode data-converters, multipliers, and multiply-accumulate circuits to operate with low voltage power supplies suitable for some portable and battery-operated AI&amp; ML applications. 
     Another objective of the disclosed invention is to provide AI &amp; ML signal processing and computation platforms, utilizing analog and mixed-signal solutions whose input signal zero-scale to full-scale dynamic ranges are not limited to high levels or low levels of current. For example, some analog signal processing units may rely on operating transistors in the subthreshold regions which restricts the input and or output dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units may rely on operating transistors with high currents in the saturation regions which restricts the input and or output dynamic range of analog signal processing circuits to higher current signals. 
     Another objective of the disclosed invention is to provide small size current-mode data-converters, multipliers, and multiply-accumulate circuits for AI &amp; ML applications that require plurality of such circuits to occupy small areas and can be manufactured at low cost. 
     Another objective of the present disclosure is to provide data-converters that can be arranged with minimal digital circuitry (i.e., be digital-light), thereby saving on die size and reducing dynamic power consumption. 
     Another objective of the disclosed invention is to provide low glitch and low dynamic power consuming current-mode data-converters, multipliers, and multiply-accumulate circuits utilized in mixed-mode multipliers for AI &amp; ML applications, which accordingly reduce the glitch and dynamic power consumption of for signal processing in AI &amp; ML end-applications. 
     Another objective of the disclosed invention is to perform analog signal processing in current-mode wherein functions such as addition or subtraction can take small area (e.g., addition of two current signals requires just the coupling of two signals), in addition to being inherently fast. 
     Another objective of the disclosed invention is to perform analog signal processing without using any resistors or capacitors, which reduces manufacturing size and cost for signal processing in AI &amp; ML end-applications. 
     Another objective of the disclosed invention is to achieve higher accuracy multiplication results while utilizing lower resolutions current-mode data converters (which are utilized in the mixed-signal multipliers). For example, for AI &amp; ML end-applications that require plurality of such multipliers, it is advantageous to attain higher accuracy multiplication results by utilizing low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower costs. 
     Another objective of the disclosed invention is to provide current-mode data-converters, multipliers, and multiply-accumulate circuits which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process, temperature, and operating condition variations. Accordingly, temperature coefficient, power supply coefficient, and AC power supply rejection performance of multipliers (that utilize such data converters) for AI &amp; ML applications can be enhanced. 
     Another objective of the disclosed invention is to provide current-mode analog and mixed-signal signal processing (utilizing data-converters, multipliers, and multiply-accumulate circuits) that can be asynchronous, consumes low power, have small die size, and provide approximate computation as a function of input frequency, for example. Analog and mixed-signal processing may experience errors that can result in approximate computation but avoid total failures, which can provide the end-application with approximate results to work with instead of experiencing failed results in most (all) digital based computations. 
     Another objective of the disclosed invention is to take advantage of attenuated contribution of component&#39;s random errors in a summation node. Summing current outputs of a plurality of iDACs would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Another objective of the disclosed invention is to provide analog and mixed signal processors for AI &amp; ML that neither require very expensive nor bleeding-edge deep sub-micron (e.g., 10 nano-meter geometries) manufacturing. Generally, purely digital AI &amp; ML systems can achieve high-speed and high-density relying chiefly on very expensive bleeding-edge deep sub-micron manufacturing (whose transistors are fast and dense) whose costs may be prohibitive in non-cloud high-volume AI &amp; ML applications near the edge or on sensors with intelligence. Moreover, signal processors on the edge or on sensors may not need very high computation speeds given their more dedicated and smaller AI &amp; ML related tasks, in part because such processors may not need to be shared or multi-tasked on edge devices or sensors. Therefore, utilizing analog and mixed signal processing for AI &amp; ML on edge devices and sensors, which can perform to specifications by using inexpensive main-stream manufacturing, avoids the unnecessary (fast and dense) and very expensive bleeding-edge deep sub-micron manufacturing that is generally required by digital AI &amp; ML processors. 
     Another objective of the disclosed invention is to provide plurality of (data-converters, multipliers, and multiply-accumulate circuits to perform) analog and mixed signal processors for AI &amp; ML application, wherein the analog and mixed signal processors can be made small, but their precision can be enhanced via a shared centrally calibrated (or trimmed) network. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a simplified block diagram illustrating a floating current-mode (i) digital-to-analog-converter (iDAC) method. 
         FIG. 2  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that utilizes the floating iDAC method illustrated in  FIG. 1 . 
         FIG. 3  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that combines a plurality of iDACs in order to arrange a higher resolution iDAC, wherein at least one of the plurality of iDACs utilizes the floating iDAC method illustrated in  FIG. 1 . 
         FIG. 4  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that combines a plurality of iDACs in order to arrange a higher resolution iDAC, wherein at least one of the plurality of iDACs utilizes the floating iDAC method illustrated in  FIG. 1 . 
         FIG. 5  is a simplified schematic diagram illustrating a mixed-signal current-mode digital-input to analog-current-output multiplier (XD i I o ) comprising of a first iDAC whose output is coupled to the reference input of a second iDAC, wherein the first and second iDACs utilize the floating iDAC method illustrated in  FIG. 1 . 
         FIG. 6  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that utilizes the floating iDAC method illustrated in  FIG. 1 . 
         FIG. 7  is a simplified functional block diagram illustrating a factorized iDAC method. 
         FIG. 8  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that utilizes the factorized iDAC method illustrated in  FIG. 7 . 
         FIG. 9  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that combines the factorized and floating DAC methods illustrated  FIG. 7  and  FIG. 1 , respectively. 
         FIG. 10  is a simplified circuit schematic diagram illustrating another embodiment of another iDAC that utilizes the factorized and floating DAC methods illustrated  FIG. 7 , and  FIG. 1 , respectively. 
         FIG. 11  is a simplified circuit schematic diagram illustrating an embodiment of a mixed-signal current-mode digital-input to analog-output multiplier (XD i I o ) comprising of a first iDAC whose output is coupled to the reference input of a second iDACs, wherein the first and second iDACs utilize the factorized and floating DAC methods illustrated  FIG. 7 , and  FIG. 1 , respectively. 
         FIG. 12 , including  FIG. 12A  and  FIG. 12B , is a (Simulation Program with Integrated Circuits Emphasis) SPICE circuit simulation showing the linearity waveforms of the mixed-signal current-mode digital-input to analog-current-output multiplier (XD i I o ) that is illustrated in  FIG. 11 . 
         FIG. 13  is a simplified circuit schematic diagram illustrating an embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is a mixed-signal current-mode digital-input to analog-current-output (D i I o ) scalar multiply-accumulate (sMAC) circuit utilizing current-mode digital-to-analog-converters (iDAC). 
         FIG. 14  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to analog-current-output (D i I o ) scalar multiply-accumulate (sMAC) circuit utilizing current-mode digital-to-analog-converters (iDAC). 
         FIG. 15  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to digital-output (D i D o ) scalar multiply-accumulate (sMAC) plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
         FIG. 16  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to digital-output (D i D o ) scalar multiply-accumulate (sMAC) plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
         FIG. 17  is a simplified functional block diagram illustrating an embodiment of a mixed-signal current-mode multiply-accumulate (iMACiDAC) circuit. The disclosed iMACiDAC is a mixed-signal current-mode digital-input to digital-output (D i D o ) multiply-accumulate (iMAC) circuit plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
         FIG. 18  is a simplified functional block diagram illustrating an embodiment of a mixed-signal current-mode Artificial Neural Network (iANN) circuit. The disclosed iANN is a mixed-signal current-mode digital-input to digital-output (D i D o ) iANN circuit utilizing current-mode multiply-accumulate (iMAC) circuits that utilize current-mode digital-to-analog-converter (iDAC) and current-mode analog-to-digital converter (iADC) circuits. 
         FIG. 19  is a simplified circuit schematic diagram illustrating an embodiment of a multi-channel mixed-signal current-mode digital-to-analog converter (iDAC) utilizing the multiple-channel data-converter method, wherein a central reference bias network (RBN) shares its reference bias voltage bus with plurality of current reference networks of respective plurality of data-converters. 
         FIG. 20  is a simplified circuit schematic illustrating an embodiment for a plurality-channels of mixed-mode multiplier (XD i I o ) with digital-input to analog-current-output that is multi-quadrant, wherein the XD i I o  utilizes the multiple-channel data-converter method disclosed in section 19. 
         FIG. 21  is a simplified circuit schematic illustrating an embodiment for a plurality-channels multiplier (XD i I o ) with digital-input to analog-current-output that is single-quadrant, wherein the XD i I o  utilizes the multiple-channel data-converter method disclosed in section 19, and wherein the XD i I o  utilizes a power supply desensitization (PSR) method. 
         FIG. 22A  is a circuit simulation illustrating the error waveform (output current SPICE simulation minus output current ideal) attributed to an output current (I O ) of a current-output DAC (iDAC). Here, the multiple-channel data-converter method of section 19 is utilized where the reference bias network (RBN) is not trimmed, and the iDAC is arranged similar to that of  FIG. 19  but having an 8-bit resolution. 
         FIG. 22B  is a circuit simulation illustrating the error waveform (output current SPICE simulation minus output current ideal) attributed to an output current (I O ) of a current-output DAC (iDAC). Here, the multiple-channel data-converter method of section 19 is utilized where two Most-Significant-Bits (MSBs) of the reference bias network (RBN) are trimmed, and the iDAC is arranged similar to that of  FIG. 19  but having an 8-bit resolution. 
         FIG. 23  is a simplified circuit schematic illustrating an embodiment of a multiplier (XD i I o ) with digital-inputs to analog-current-output that operate in current mode comprising of a first current-output DAC (iDAC) or iDACx 23  whose analog-current-output supplies the reference input to a second current-output iDAC or iDACy 23 . 
         FIG. 24  is a simplified circuit schematic illustrating another embodiment of a multiplier (XD i I o ) with digital-inputs to analog-current-output that operate in current mode comprising of a first current-output DAC (iDAC) or iDACx 24  whose analog-current-output supplies the reference input to a second current-output iDAC or iDACy 24 . 
         FIG. 25  is a simplified circuit schematic illustrating an embodiment of a multiplier (XD i I o ) with digital-input to analog-current-output that operate in current mode equipped with an embodiment of the power supply desensitization (PSR) circuit. 
         FIG. 26  is a simplified circuit schematic illustrating another embodiment of a multiplier (XD i I o ) with digital-input to analog-current-output that operate in current mode equipped with another embodiment of the power supply desensitization (PSR) circuit. 
         FIG. 27  is a simplified circuit schematic illustrating another embodiment of a multiplier (XD i I o ) with digital-input to analog-current-output that operate in current mode comprising of a first current-output DAC (iDAC) or iDACx 27  whose analog-current-output supplies the reference input to a second current-output iDAC or iDACy 27 . 
         FIG. 28  is a circuit simulations illustrating the error waveform (output current SPICE simulation minus output current ideal) attributed to an output current (I O ) of a XD i I o  multiplier arranged similar to that of  FIG. 21  but having an 8-bit digital inputs instead of 3-bits. 
         FIG. 29  is a circuit simulations illustrating the error waveform (output current SPICE simulation minus output current ideal) attributed to an output current (I O ) of a XD i I o  multiplier arranged similar to that of  FIG. 20  but having an 8-bit digital inputs instead of 4-bits. 
         FIG. 30  is a simplified circuit schematic illustrating another embodiment for a plurality-channels multiplier (XD i I o ) with digital-input to analog-current-output that is single-quadrant, wherein the XD i I o  multiplier utilizes the multiple-channel data-converter method disclosed in section 19 and the XD i I o  multiplier utilizes a power supply desensitization (PSR) circuit. 
         FIG. 31  is a circuit simulations showing the error waveform (output current SPICE simulation minus output current ideal) attributed to the output current (I O ) of a XD i I o  multiplier that is arranged similar to that of  FIG. 30  but having an 8-bit digital inputs instead of 3-bits. 
         FIG. 32  is a simplified block diagram illustrating a meshed digital-to-analog multiplication (mD i S o ) method. 
         FIG. 32 ′ is another simplified block diagram illustrating the meshed digital-to-analog multiplication (mD i S o ) method that is disclosed in section 32. 
         FIG. 33  is a simplified circuit schematic illustrating an embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in the prior section 32′. 
         FIG. 34  is a simplified circuit schematic illustrating another embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in section 32 and section 32′. 
         FIG. 35  is a simplified circuit schematic illustrating another embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in section 32. 
         FIG. 36  is a simplified block diagram illustrating a first non-linear digital-to-analog converter (NDAC) method. 
         FIG. 36 ′ is a simplified block diagram illustrating a second non-linear digital-to-analog converter (NDAC) method, which utilizes the meshed digital-to-analog multiplication (mD i S o ) method that is discussed in section 32. 
         FIG. 37  is a simplified block diagram illustrating a third non-linear digital-to-analog converter (NDAC) method. 
         FIG. 38  is a simplified circuit schematic illustrating an embodiment of a non-linear digital-input to analog current output digital-to-analog converter (iNDAC 38 ), which utilizes the NDAC method described in section 37, wherein the non-linear output profile of iNDAC 38  is programmed to approximate a square transfer function. 
         FIG. 39  is a simplified circuit schematic illustrating another embodiment of a non-linear digital-input to analog current output digital-to-analog converter (iNDAC 39 ), which utilizes the NDAC method described in section 36′ wherein the non-linear output profile of iNDAC 39  is programmed to approximate a square transfer function. 
         FIG. 40  is a simplified circuit schematic illustrating another embodiment of the digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in the prior section 32, and wherein the XD i I o  multiplier utilizes the multiple-channel data-converter method disclosed in section 19 when plurality of XD i I o  multipliers are needed by an end-application. 
         FIG. 41  is a simplified circuit schematic illustrating another embodiment of the digital-input to analog current output multiplier (XD i I o ), which can be extended to plurality of XD i I o  multipliers by sharing a central reference bias network (RBN) that bias the current reference network of each of the XD i I o  multipliers. 
         FIG. 42  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) of a XD i I o  multiplier versus the simulated output current (Io simulation ) of a XD i I o  multiplier that is arranged similar to that of  FIG. 34  but having a 4-bit resolution. 
         FIG. 43  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) of a XD i I o  multiplier versus the simulated output current (Io simulation ) of a XD i I o  multiplier that is arranged similar to that of  FIG. 40  but with a 6-bit resolution. 
         FIG. 44  illustrates a SPICE circuit simulations comprising of an ideal square iDAC&#39;s output current (I X   2 ) plot versus the simulated output current (I O   2 ) plot of a square iDAC that is arranged similar to that of  FIG. 38  but with a 7-bit resolution. 
         FIG. 45  illustrates SPICE circuit simulations comprising of an ideal square iDAC&#39;s output current (I X   2 ) plot versus the simulated output current (I O   2 ) plot of a square iDAC that is arranged similar to that of  FIG. 39  but with a 7-bit resolution. 
         FIG. 46  illustrates SPICE circuit simulations comprising of an ideal XD i I o  multiplier&#39;s output current (Io ideal ) plot versus the simulated output current (Io simulation ) plot of a XD i I o  multiplier that is arranged similar to that of  FIG. 41  but with a 7-bit resolution. 
     
    
    
     SUMMARY OF THE DISCLOSURE 
     An aspect of the present disclosure is a floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method comprising: programming a plurality of voltage-controlled-current sources (VCCS) to generate a plurality of current signals to be at least one of equally weighted currents, binarily weighted currents, non-linear weighted currents, and individually weighted currents; summing the plurality of current signals to create a summation current signal (S SUM ) at a reference current input port (A R ); wherein the floating iDAC has a digital input word (D i ) that controls a plurality of current switches (iSW) that respectively steer the plurality of current signals to at least one of a positive current output port (I O   + ), and a negative current output port (I O   − ) of the floating iDAC; wherein the currents flowing through the I O   +  port and the I O   −  port are proportional to the current signal flowing through the A R  port, and responsive to the D i  word of the floating iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: receiving current signals from respective I O   +  ports and I O   −  ports, of at least one of a subsequent iDAC, into the respective at least one of the I O   +  port, and the I O   −  port of the floating iDAC; wherein the A R  port receives a reference current signal (S R ); wherein the reference input signal of each of the subsequent iDACs is proportional to the S R  signal; and wherein the at least one of the subsequent iDACs effectively increases the resolution of the floating iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: receiving the current signal from a first iDAC into a reference input port of a second iDAC, wherein at least one of the first iDAC and the second iDAC is the floating iDAC; generating a multiplicand output current signal (S MULT ) at an output port of the second iDAC; and wherein the S MULT  signal is proportional to the S R  signal and responsive to the product of a digital input word of the first iDAC and, a digital input word of the second iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: generating a plurality of S MULT  signals; and combining the plurality of S MULT  signals to generate a multiply-accumulate current signal (S MAC ), wherein the S MAC  signal is a summation of the plurality of the S MULT  signals. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: combining the S MAC  signal with a bias current signal (S B ) from a bias current iDAC to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is the summation of the S MAC  signal and the S B  signal. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: receiving currents from I O   +  port and I O   −  port, of a plurality of subsequent floating iDACs, into the respective I O   +  port and the I O   −  port of the floating iDAC to generate an I Op   +  and an I Op   − ; generating a plurality of reference current sources (S R )s to be at least one of equally weighted currents, binarily weighted currents, non-linear weighted currents, and individually weighted currents; receiving each of the plurality of S R  signals respectively into the I sR  port of each subsequent floating iDAC; receiving a X digital word of width m, and a Y digital word of width n, wherein each bit weight of the X word of width m corresponds to the respective weight of each of the plurality of reference currents corresponding respectively to each of the floating iDACs, and wherein each bit weight of the Y word of width n corresponds to the digital input word D i  of the plurality of floating iDACs; generating a multiplicand output current signal (S MULT ) in at least one of the I Op   +  port and I O   − p port; wherein the I iMULT  current is proportional to the magnitude of S R  source, and responsive to the product of the X word and the Y word; and wherein the X word and Y word are interchangeable. 
     Another aspect of the present disclosure is a floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method comprising: generating a plurality of currents in a plurality of metal-oxide-semiconductor-field-effect-transistors (MOSFETs), wherein a weighting relationship among each of the plurality of currents in the MOSFETs is at least one of equally weighted, binarily weighted, non-linear weighted, and individually weighted; steering each of the plurality of current signals in the plurality of MOSFETs respectively through each input terminal of a plurality of current switches (iSW); steering each of the plurality of current signals through the plurality of iSWs respectively to each output terminal of the plurality of current switches (iSW) to at least one of a positive current output port (I O   + )), and a negative current output port (I O   − ); receiving a digital input word (D i ), and respectively controlling the steering of each of the plurality of current signals through the plurality of iSWs by the D i ; wherein respective source ports of the plurality of MOSFETs are coupled together, and coupled to a reference current source (S R ); wherein respective gate terminals of the plurality of MOSFETs are coupled together, and coupled to a voltage source (V B ); and wherein the currents flowing through the I O   +  port and the I O   −  port are proportional to the magnitude of the S R  source, and responsive to the D i  word of a floating iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: receiving into the at least one of the I O   +  port, and the I O   −  port of the floating iDAC, currents from respective I O   +  ports and I O   −  ports from at least one of a subsequent iDAC, wherein the at least one of the subsequent iDAC effectively increases the resolution of the floating iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: receiving the output current signal from a first iDAC into a reference input port of a second iDAC, wherein at least one of the first iDAC and the second iDAC is the floating iDAC; and generating a multiplicand output current signal (S MULT ) at an output of the second iDAC. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: generating a plurality of S MULT  signals; and combining the plurality of S MULT  signals to generate a multiply-accumulate current signal (S MAC ), wherein the S MAC  signal is a summation of the plurality of the S MULT  signals. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: generating a bias current signal (S B ) by an iDAC; and combining the S MAC  signal with the S B  signal to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is a summation of the S MAC  signal and the S B  signal. Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the floating current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the floating iDAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). 
     Another aspect of the present disclosure is a mixed-signal current-mode multiply-accumulate (iMAC) method in integrated circuits, the mixed-signal iMAC method comprising: generating a plurality of first current output signals (S 1   O )s by a plurality of first current-mode digital-to-analog converters (iDAC 1 )s; receiving the plurality of S 1   O  signals into a respective plurality of reference input ports (A 2   R ) of a plurality of second current-mode digital-to-analog-converters (iDAC 2 )s; generating a plurality of multiplicand output current signals (S MULT )s at the plurality of A 2   R  ports; combining a plurality of S MULT  signals together to generate a multiply-accumulate current signal (S MAC ); and wherein the S MAC  signal is a summation of a plurality of second current output signals (S 2   O )s of the plurality of iDAC 2   s . Further aspects of the mixed-signal current-mode multiply-accumulate (iMAC) method in integrated circuits, the mixed-signal iMAC method further comprising: generating a bias current signal (S B ) by a bias iDAC; and combining the S MAC  signal with the S B  signal to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is a summation of the S MAC  signal and the S B  signal. Further aspects of the mixed-signal current-mode multiply-accumulate (iMAC) method in integrated circuits, the mixed-signal iMAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the mixed-signal current-mode multiply-accumulate (iMAC) method in integrated circuits, the mixed-signal iMAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). 
     Another aspect of the present disclosure is a factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method comprising: generating a scaled top output current signal (A t F t ) as a product of a top scale factor (F t ) and a top output current signal (A t ) of a top iDAC (iDAC t ), wherein the iDAC t  receives a top digital word (D t ) that is t-bits wide, and wherein the iDAC t  receives a top reference current signal (t R ), and wherein the iDAC t  is binary weighted and wherein F t  and t are each between zero and eight; generating a scaled middle output current signal (A m F m ) as a product of a middle scale factor (F m ) and a middle output current signal (A m ) of a middle iDAC (iDAC t ), wherein the iDAC m  receives a middle digital word (D m ) that is m-bits wide, and wherein the iDAC m  receives a middle reference current signal (m R ), and wherein iDAC m  is binary weighted and wherein the F m  and m are each between zero and eight; combining the A t F t , and the A m F m  signals to generate a summation analog output current signal (A Otm ) of a factorized iDAC; wherein a digital input word (D i ) of the factorized iDAC is t+m bits wide, and wherein the D t  is the most-significant-bits bank of the D i , and wherein the D m  is a remaining-bits bank of the D i , and wherein the factorized iDAC t  is binary weighted; and wherein A Otm =A t F t +A m F m  wherein (F t /F m )×(m R /t R )=2 t ; and wherein the t R , and m R  signals are proportional to one another and proportional to a reference input signal (S R ) of the factorized iDAC. 
     Another aspect of the present disclosure is a factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method comprising: generating a scaled top output current signal (A t F t ) as a product of a top scale factor (F t ) and a top output current signal (A t ) of a top iDAC (iDAC t ), wherein the iDAC t  receives a top digital word (D t ) that is t-bits wide, and wherein the iDAC t  receives a top reference current signal (t R ), and wherein iDAC t  is binary weighted, and wherein F t  and t are each between zero and eight; generating a scaled middle output current signal (A m F m ) as a product of a middle scale factor (F m ) and a middle output current signal (A m ) of a middle iDAC (iDAC t ), wherein the iDAC m  receives a middle digital word (D m ) that is m-bits wide, and wherein the iDAC m  receives a middle reference current signal (m R ), and wherein iDAC m  is binary weighted, and wherein the F m  and m are each between zero and eight; generating a scaled bottom output current signal (A b F b ) by scaling a bottom binary iDAC (DAC b ) output current signal (A b ) by a bottom scale factor F b , wherein the iDAC b  receives a bottom digital word (D b ) that is b-bits wide, and wherein the iDAC b  receives a bottom reference current signal (b R ), and wherein the F b  and b are each integers greater than one and less than eight; combining the A t F t , the A m F m , and the A b F b  signals to generate a summation analog output current signal (A Otm ) of a factorized iDAC; wherein A Otm =A t F t +A m F m +A b F b ; wherein (F t /F b )×(b R /t R )=2 t+m ; wherein the digital input (D i ) of the factorized iDAC is t+m+b bits wide, and wherein the D t  is the most-significant-bits (MSBs) bank of the D i , and wherein the D m  is the intermediate-bits (ISBs) bank of the D i , and wherein the D b  is the least-significant-bits (LSBs) bank of the D i ; and wherein the t R , m R , and b R  signals are proportional to one another and proportional to a reference input signal (S R ) of the factorized iDAC. Further aspects of the factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method further comprising: receiving the output current signal from a first iDAC into a reference input port of a second iDAC, wherein at least one of the first iDAC and the second iDAC is the factorized iDAC; generating a multiplicand output current signal (S MULT ) at an output port of the second iDAC; and wherein the S MULT  signal is proportional to the S R  signal and responsive to the product of digital input words of the first iDAC and the second iDAC. Further aspects of the factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method further comprising: generating a plurality of S MULT  signals; and combining the plurality of S MULT  signals to generate a multiply-accumulate current signal (S MAC ), wherein the S MAC  signal is a summation of the plurality of the S MULT  signals. Further aspects of the factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method further comprising: generating a bias current signal (S B ) by a bias iDAC; and combining the S MAC  signal with the S B  signal to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is a summation of the S MAC  signal and the S B  signal. Further aspects of the factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the factorized current-mode digital-to-analog converter (iDAC) method in an integrated circuit, the factorized iDAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). 
     Another aspect of the present disclosure is a mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method comprising: generating a scalar current (S S ) by a first current-mode DAC (iDAC); replicating the S S  signal to generate a plurality of scalar current replica signals (S SD ); receiving the plurality of S SD  signals respectively into a reference input of each of a plurality of second iDACs; and generating a plurality of current output Signals (S O )s of the plurality of the second iDACs; combining the plurality of S O  signals of the plurality of second iDACs to generate a multiply-accumulate current (S MAC ); and wherein the S MAC  is a summation of the respective plurality of S O  signals. Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method further comprising: combining the S MAC  signal with a bias current signal (S B ) from a bias current iDAC to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is the summation of the S MAC  signal and the S B  signal. Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). 
     Another aspect of the present disclosure is a mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method comprising: receiving a first and subsequent reference current signals, each respectively to a reference port (A R ) of each of first current mode iDAC of a plurality of first current mode iDACs; generating a plurality of output current signals (S O )s by the plurality of first current-mode DACs (iDAC); combining the plurality of S O  signals of the plurality of first iDACs to generate a current signal (S Osum ), wherein the S Osum  is a summation of the plurality of S O  signals; mirroring the S Osum  signal to create a mirrored S Osum  signal, S Osumm ; receiving the S Osumm  signal into a reference input port of a scalar iDAC; and generating a multiply-accumulate current signal (S MAC ) at the output port of the scalar iDAC. Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in integrated circuits, the mixed-signal scalar iMAC method further comprising: combining the S MAC  signal with a bias current signal (S B ) from a bias current iDAC to generate a biased multiply-accumulate current signal (S BMAC ), wherein the S BMAC  signal is the summation of the S MAC  signal and the S B  signal. Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method further comprising: digitizing the S BMAC  signal in a current-mode analog-to-digital converter (iADC). Further aspects of the mixed-signal scalar current-mode multiply-accumulate (iMAC) method in an integrated circuit, the mixed-signal scalar iMAC method further comprising: combining a plurality of S BMAC  signals, wherein the combining the plurality of S BMAC  signals forms a current-mode artificial neural network (iANN). 
     Another aspect of the present disclosure is a non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method comprising: generating a non-linear Most-Significant-Portion (MSP) analog output signal (So MPS   N ) that is proportional to a MSP reference signal (Sr MSP ), and is responsive to a bank of Most-Significant-Bits (MSBs) of a digital input word (Di MSP ); generating a linear Least-Significant-Portion (LSP) analog output signal (So LSP   L ) that is proportional to a LSP reference signal (Sr LSP ), and is responsive to a bank of Least-Significant-Bits (LSBs) of a digital word (Di LSP ), and is responsive to the Di MSP  word; combining the So MPS   N  signal and the So LSP   L  signal to generate a non-linear analog output signal (So N ) that is proportional to a reference signal (S R ), and is responsive to a digital word (D I ); wherein the So LSP   L , signal is a straight-line approximation between non-linear segments of the S R  signal; wherein the Sr MSP  signal, and the Sr LSP  signal, are each proportional to the S R  signal; and wherein the D I  word is comprised of the Di MSP  word and the Di LSP , word. Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: wherein the So MPS   N  signal is generated by a non-linear MSP digital-to-analog converter (DAC MSP   N ) having a reference network comprised of a sequence of scaled MSP reference signals (Sr MSP   N ); and wherein the sequence of scaled Sr MSP   N  signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted. Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: generating the So LSP   L  signal by a plurality of linear LSP Digital-to-Analog Converters (DAC LSP   L )s comprised of a first linear LSP DAC (DAC 1   LSP   L ), and a second linear LSP DAC (DAC 2   LSP   L ); generating an output signal (So 1   LSP   1 ) by the DAC 1   LSP   L  that is proportional to a first LSP reference signal (Sr 1   LSP ), and is responsive to the Di MSP  word; combining the So 1   LSP   L  signal with a reference offset signal (Sr OFS ) to generate a second reference signal (Sr 2   LSP   L ); receiving the Sr 2   LSP   L  signal into a reference input port (Ar 2   LSP   L ) of the DAC 2   LSP   L ; and generating the So LSP  signal at an output port (Ao 2   LSP   L ) of the DAC 2   LSP   L  that is responsive to the Di LSP  word and the Di MSP  word. Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: multiplying the Di LSP  word and the Di MSP  word to generate a multiplicand digital word (Di LSP ×Di MSP ); generating an output signal (So 1   LSP   L ) by a first LSP Digital-to-Analog Converter (DAC 1   LSP   L ), wherein the So 1   LSP   L  signal is proportional to a first LSP reference signal (Sr 1   LSP ), and is responsive to the Di LSP ×Di MSP  word; generating an output offset signal (Sfo LSP   L ) by a second LSP Digital-to-Analog-Converter (DAC 2   LSP   L ), wherein Sfo LSP   L  signal is proportional to a second LSP reference signal (Sr 2   LSP ), and is responsive to the Di LSP  word; and combining the So 1   LSP   L  signal and the Sfo LSP   L  signal to generate the So LSP   L  signal. Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: receiving the Di LSP  word and the Di MSP  word into a linearly meshed digital-input to analog-output multiplier (mDiSo LSP   L ) to generate an output signal (So 1   LSP   L ) that is proportional to a first LSP reference signal (Sr 1   LSP   L ); generating an output offset signal (Sfo LSP   L ) by a second LSP Digital-to-Analog-Converter (DAC 2   LSP   L ) that is proportional to a second LSP reference signal (Sr 2   LSP ), and is responsive to the Di LSP  word; and combining So 1   LSP   L  signal and the Sfo LSP   L  signal to generated the So LSP   L  signal. Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: generating at least one So MSP   N  by at least one non-linear MSP Digital-to-Analog Converter (DACT MSP   N ); generating at least one So LSP   L  by at least one linear LSP Digital-to-Analog Converter (DAC LSP   L ); generating at least one So N  signal that is proportional to the reference signal (S R ), wherein the at least one So N  signal is responsive to at least one D i  word; wherein the reference network of each of the DAC MSP   N  is comprised of a sequence of non-linearly scaled MSP reference signals (Sr MSP   N ) that are proportional to the Sr MSP  signal; wherein the reference network of each of the DAC LSP   L  is comprised of a sequence of scaled LSP reference signals (Sr LSP   L ) that are proportional to the Sr LSP  signal; wherein each of the sequence of Sr MSP   N  signals is at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted; wherein each of the sequence of Sr LSP   L  signals is at least one of binary weighted, linearly weighted, and individually weighted; and wherein each of the sequence of Sr MSP   N  signals and each of the sequence of Sr LSP   L  signals are biased from a common reference bias network (RBN). Further aspects of the non-linear digital-to-analog conversion (NDAC) method in an integrated circuit, the method further comprising: wherein a plurality of the at least one So N  signal has a square profile; wherein a p-channel So N  signal, of the plurality of So N  signals, is responsive to a p-channel D word; wherein a q-channel So N  signal, of the plurality of So N  signals, is responsive to a q-channel D word; wherein the p-channel So N  and the q-channel So N  signals are subtracted from one another to generate a scaled So xy  signal; wherein the p-channel D word is comprised of a scaled X digital word and a scaled Y digital word that are added to one another; wherein the q-channel D word is comprised of a scaled Y digital word and a scaled Y digital word that are subtracted from one another; and wherein the scaled So xy  signal is proportional to the S R , and is an analog representation of a scaled multiplication product of the scaled X digital word and the scaled Y digital word. 
     Another aspect of the present disclosure is a non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system comprising: a first non-linear Digital-to-Analog-Converter (DAC QM ), the DAC QM  including a digital input port (D QM ), an analog output port (Ao QM ), and an analog reference input port (Ar QM ); a first linear Digital-to-Analog-Converter (DAC 1L ), the DAC 1L  having a digital input port (D 1L ), an analog output port (Ao 1L ), and an analog reference input port (Ar 1L ); a second linear Digital-to-Analog-Converter (DAC 2L ), the DAC 2L  having a digital input port (D 2L ), an analog output port (Ao 2L ), and an analog reference input port (Ar 2L ); a digital input word (D) comprised of a Most-Significant-Bits (MSB)s bank word (D MSP ), and a Least-Significant-Bits (LSB)s bank word (D LSP ); a digital multiplier (X ML ), the X ML  having an M input digital word port (M), an N input digital word port (N), and an output digital word port (M×N); the M port coupled to the D MSP  bank word; the N port coupled to the D LSP  bank word; the D 1L  port coupled to the output digital word port M×N; the D 2L  port coupled to the digital word N port; the D QM  port coupled to the digital word M port; wherein a first reference signal (Sr QM ) is coupled to the Ar QM  port; wherein a second reference signal (Sr 1L ) is coupled to the Ar 1L  port; wherein a third reference signal (Sr 2L ) is coupled to the Ar 2L  port; wherein a sum of signals at the Ao 1L  and Ao 2L  ports is a straight-line approximation between non-linear segments of a signal at the Ao QM  port; wherein a sum of signals at the Ao QM , Ao 1L , and Ao 2L  ports generates a non-linear analog output signal (So N ) at an analog output port Ao N ; wherein an analog reference signal (S R ) is proportionally scaled to an Sr QM , the Sr 1L , and the Sr 2L  signals; wherein a sequence of non-linear reference signals (Sr MSP   N ), which form a transfer function of the DAC QM , are proportional to the S R  signal; wherein the sequence of Sr MSP   N  signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted; wherein a sequence of linear reference signals (Sr LSP   L ), which form a transfer function of the DAC 1L  and DAC 2L , are proportional to the S R  signal; wherein the sequence of Sr LSP   L  signals are at least one of binary weighted, linearly weighted, and individually weighted; and wherein the So N  signal substantially follows one of a square, logarithmic, and non-linear profile, is proportional to the S R  signal, and responsive to the D word. Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: wherein the sequence of Sr MSP   N  signals, and the sequence of Sr LSP   L  signals, are biased from a common reference bias network (RBN). Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: a plurality of So N  signals having a square profile; wherein a p-channel So N  signal, of the plurality of So N  signals, is responsive to a p-channel D word; wherein a q-channel So N  signal, of the plurality of So N  signals, is responsive to a q-channel D word; wherein the p-channel So N  and the q-channel So N  signals are subtracted from one another to generate a scaled So xy  signal; wherein the p-channel D word is comprised of a scaled X digital word and a scaled Y digital word that are added to one another; wherein the q-channel D word is comprised of a scaled Y digital word and a scaled Y digital word that are subtracted from one another; and wherein the scaled So xy  signal is proportional to the S R , and is an analog representation of a scaled multiplication product of the scaled X digital word and the scaled Y digital word. Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: the Ao QM  port, Ao 1L  port, and Ao 2L  port are coupled to an output port Ao Q ; and wherein the DAC QM , DAC 1L , and DAC 2L  operate in current mode. 
     Another aspect of the present disclosure is a non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system comprising: a first non-linear digital-to-analog-converter (DAC QM ), the DAC QM  having a digital input port (D QM ), an analog output port (Ao QM ), and an analog reference input port (Ar QM ); a first linear digital-to-analog-converter (DAC 1L ), the DAC 1L  having a digital input port (D 1L ), an analog output port (Ao 1L ), and an analog reference input port (Ar 1L ); a second linear digital-to-analog-converter (DAC 2L ), the DAC 2L  having a digital input port (D 2L ), an analog output port (Ao 2L ), and an analog reference input port (Ar 2L ); a digital input word (D) comprised of a Most-Significant-Bits (MSB)s bank word (D MSP ) and a Least-Significant-Bits (LSB)s bank word (D LSP ); an MSB bank port (M) coupled to the D MSP  word; an LSB bank port (N) coupled to the D LSP  word; the D 1L  port coupled to the M port; the D 2L  port coupled to the N port; the D QM  port coupled to the M port; wherein a first reference signal (Sr QM ) is coupled to the Ar QM  port; wherein a second reference signal (Sr 1L ) is coupled to the Ar 1L  port; wherein a signal at the Ao 1L  port (So 1L ) is combined with a third reference offset signal (Sfr 2L ) and combination of which is coupled to the Ar 2L  port; wherein a signal at the Ao 2L  port is a straight-line approximation between non-linear segments of a signal at the Ao QM  port; wherein a sum of signals at the Ao QM  and the Ao 2L  ports generates a non-linear analog output signal (So N ) at an analog output port Ao N ; wherein an analog reference signal (S r ) is proportionally scaled to the Sr QM , the Sr 1L , and the Sr 2L  signals; wherein a sequence of non-linear reference signals (Sr MSP   N ), which form the transfer function of the DAC QM , are proportional to the S R  signal; wherein the sequence of Sr MSP   N  signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted; wherein the sequence of linear reference signals (Sr LSP   L ), which form the transfer function of the DAC 1L  are proportional to the S R  signal; wherein the sequence of Sr LSP   L  signals are at least one of binary weighted, linearly weighted, and individually weighted; and wherein the So N  signal substantially follows one of a square, logarithmic, and non-linear profile, is proportional to the S R  signal, and responsive to the D word. Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: wherein each of the sequence of Sr MSP   N  signals, and each of the sequence of Sr 1   LSP   L  signals are biased from a common reference bias network (RBN). Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising a plurality of So N  signals having a square profile; wherein a p-channel So N  signal, of the plurality of So N  signals, is responsive to a p-channel D word; wherein a q-channel So N  signal, of the plurality of So N  signals, is responsive to a q-channel D word; wherein the p-channel So N  and the q-channel So N  signals are subtracted from one another to generate a scaled So xy  signal; wherein the p-channel D word is comprised of a scaled X digital word and a scaled Y digital word that are added to one another; wherein the q-channel D word is comprised of a scaled Y digital word and a scaled Y digital word that are subtracted from one another; and wherein the scaled So xy  signal is proportional to the S R  and is an analog representation of a scaled multiplication product of the scaled X digital word and the scaled Y digital word. 
     Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: the Ao QM  port and Ao 2L  port are coupled to an output port Ao Q ; and wherein the DAC QM , DAC 1L , and DAC 2L  operate in current mode. 
     Another aspect of the present disclosure is a non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system comprising: a first non-linear Digital-to-Analog-Converter (DAC QM ), the DAC QM  having a digital input port (D QM ), an analog output port (Ao QM ), and an analog reference input port (Ar QM ); a first linear Digital-to-Analog-Converter (DAC 1L ), the DAC 1L  having a digital input port (D 1L ), an analog output port (Ao 1L ), and an analog reference input port (Ar 1L ); a linearly meshed digital-input to analog-output multiplier (mDiSo LSP   L ), the mDiSo LSP   L  having an M digital input port (M) and a N digital port (N), an analog output port (Ao 2L ), and an analog reference input port (Ar 2L ); a digital input word (D) comprised of a Most-Significant-Bits (MSB)s bank word (D MSP ) and a Least-Significant-Bits (LSB)s bank word (D LSP ); the M port coupled to the D MSP  word; the N port coupled to the D LSP  word; the D 1L  port coupled to the N port; the D QM  port coupled to the M port; wherein a first reference signal (Sr QM ) is coupled to the Ar QM  port; wherein a second reference signal (Sr 1L ) is coupled to the Ar 1L  port; wherein a third reference signal (Sr 2L ) is coupled to the Ar 2L  port; wherein a sum of signals at the Ao 1L  and Ao 2L  ports is a straight-line approximation between non-linear segments of a signal at the Ao QM  port; wherein a sum of signals at the Ao QM , Ao 1L , and Ao 2L  ports generates a non-linear analog output signal (So N ) at an analog output port Ao N ; wherein an analog reference signal (S R ) is proportionally scaled to the Sr QM , the Sr 1L , and the Sr 2L  signals; wherein a sequence of non-linear reference signals (Sr MSP   N ), which form the transfer function of the DAC QM , are proportional to the S R  signal, wherein the sequence of Sr MSP   N  signals are at least one of squarely weighted, logarithmically weighted, non-linearly weighted, and individually weighted; wherein the sequence of linear reference signals (Sr LSP   L ), which form the transfer functions of the DAC 1L  and the mDiSo LSP   L , are proportional to the S R  signal; wherein the sequence of Sr LSP   L  signals are at least one of binary weighted, linearly weighted, and individually weighted; wherein the So N  signal substantially follows one of a square, logarithmic, and non-linear profile, is proportional to the S R  signal, and responsive to the D word. Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated, the system further comprising: wherein each of the sequence of Sr MSP   N  signals, each of the sequence of Sr 1   LSP   L  signals, and each of the sequence of Sr 2   LSP   L  signals are biased from a common reference bias network (RBN). Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: a plurality of So N  signals having a square profile; wherein a p-channel So N  signal, of the plurality of So N  signals, is responsive to a p-channel D word; wherein a q-channel So N  signal, of the plurality of So N  signals, is responsive to a q-channel D word; wherein the p-channel So N  and the q-channel So N  signals are subtracted from one another to generate a scaled So xy  signal; wherein the p-channel D word is comprised of a scaled X digital word and a scaled Y digital word that are added to one another; wherein the q-channel D word is comprised of a scaled Y digital word and a scaled Y digital word that are subtracted from one another; and wherein the scaled So xy  signal is proportional to the S R , and is an analog representation of a scaled multiplication product of the scaled X digital word and the scaled Y digital word. Further aspects of the non-linear digital-to-analog converter (NDAC) system in an integrated circuit, the system further comprising: the Ao QM  port, Ao 1L  port, and Ao 2L  port are coupled to an output port Ao Q ; and wherein the DAC QM , DAC 1L , and DAC 2L  operate in current mode. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter method in an integrated circuit, the method comprising: generating a sequence of reference bias current signals (Si Rb ) from a reference bias network (RBN); mirroring the sequence of Si Rb  signals from the RBN into at least one iDC; wherein the scaling of the mirroring of the sequence of Si Rb  signals from the RBN into at least one iDC, is individually scaled; wherein the sequence of Si Rb  signals from the RBN is weighted at least equally, binarily, non-linearly, and individually; wherein each Si Rb  signal from the sequence of Si Rb  signals from the RBN is scaled proportionately to a reference current signal (S R ); wherein each Si Rb  signal from the sequence of Si Rb  signals from the RBN is mirrored from the S R  signal; wherein the sequence of Si Rb  signals, from the RBN in the at least one iDC, program the reference current network of the at least one iDC, which establishes the input-to-output transfer function of the at least one iDC; wherein the at least one iDC is at least one of current-mode Digital-to-Analog-Converter (iDAC) and current-mode Analog-to-Digital-Converter (iADC); wherein if the at least one iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if the at least one iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: regulating the S R  signal from the RBN; wherein the analog ports of the at least one iDC substantially track power supply voltage variations; and wherein if the at least one iDC includes an iDAC, then the analog output current signal of each iDAC is substantially desensitized with respect to power supply variations; and wherein if the at least one iDC includes an iADC, then a digital output word of each iADC is substantially desensitized with respect to power supply variations. Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: wherein if the at least one iDC includes an iDAC: generating at least one pair of current output signals (S X  and S y ) from at least one pair of iDACs (iDAC X , and iDAC y ), that are proportional to the S R  signal, and responsive to the respective digital input words (D X  and D Y ) of the at least one pair of iDACs; receiving the at least one pair of S X  and S y  signals, respectively, into current input ports A mX  and A mY  of at least one analog current multiplier (iMULT); receiving at least one Si Rb  signal from the sequence Si Rb  signals from the RBN into a reference current input port (A mR ) of the at least one iMULT; and wherein an input-output transfer function of the at least one iMULT follows the relationship S Y /S R =S O /S X , and wherein S O  signal is at least one output current signal of the at least one iMULT. Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: wherein at least one of S R , S y , S X , and S O  signals is generated without cascode. Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: wherein the respective voltages at A mR  and A mY  ports track power supply voltage variations in substantial proportion to one another; wherein the respective voltages at A mX  and A mO  ports track power supply voltage variations in substantial proportion to one another; and wherein the at least one S O  signal of the at least one iMULT is substantially insensitive to power supply voltage variations. Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: wherein if the at least one iDC includes an iDAC: wherein the sequence of Si Rb  signals from the RBN is weighted squarely; summing at least one pair of digital input words (D x  and D y ) together to generate at least a scaled D x+y  digital word; subtracting the at least one pair of digital input words D x  and D y  from one another to generate at least one scaled D x−y  digital word; receiving at least one pair of scaled digital input words (D x+y  and D x−y ) respectively into each of at least one pair of iDACs (iDAC (x+y)     2    and iDAC (x−y)     2   ); generating at least one pair of current output signals (S (x+y)     2    and S (x−y)     2   ) that are proportional to the S R , and responsive to the at least one pair of the scaled D x+y  and D x−y  words of the at least one pair of iDAC (x+y)     2    and iDAC (x−y)     2   ; subtracting from one another, each of the S (x+y)     2    and S (x−y)     2    signals of the at least one pair of iDACs (iDAC (x+y)     2    and iDAC (x−y)     2   ), to generate at least one multiplicand output current signal (S iMULT ), wherein S iMULT  is the analog representation of a scaled product digital word (D x ×D y ). Further aspects of the multiple channel current-mode data converter method in an integrated circuit, the method further comprising: wherein if the at least one iDC includes an iDAC: wherein the sequence of Si Rb  signals from the RBN is weighted logarithmically; receiving at least one pair of digital input words (D X  and D Y ) respectively into at least one pair of the iDACs (iDAC log X , and iDAC log Y ); generating at least one pair of current output signals (S log X  and S log Y ) that are proportional to the S R  signal, and responsive to the at least one pair of D X  and D Y  words; and summing the S log X  and S log Y  signals to generate at least one multiplicand output current (S log MULT ), wherein S log MULT  is the analog representation of a digital logarithmic word (log D x ×D y ). 
     Another aspect of the present disclosure is a power supply desensitization method in a current-mode digital-to-analog converter (iDAC) in an integrated circuit, the method comprising: receiving a digital input word (D X ) into a x-channel iDAC (iDAC X ) having an analog output current signal (S X ), and a reference input signal (S RX ), wherein the iDAC X  is without cascodes; receiving a digital input word (D Y ) into a y-channel iDAC (iDAC Y ) having an analog output current signal (S Y ), and a reference input signal (S RY ), wherein the iDAC X  is without cascodes; receiving the S X  signal into an input port of a power supply desensitization (PSR) circuit; regulating and generating the S RY  reference input signal at an output port of the PSR circuit, wherein the S Y  signal is desensitized from power supply variations; and generating a multiplicand output current (S iMULT ) at the S Y  signal, wherein the S iMULT  signal is an analog representation of the product of the D X  and D Y  digital words. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter system in an integrated circuit, the method comprising: a Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFET)s each having a gate-port, a drain-port, and a source port, and each having a scale (W/L); a sequence of diode-connected MOSFETs, wherein the gate port and the drain port of each MOSFET in the sequence of the MOSFET are coupled together and coupled to a sequence of gate-drain ports; at least one current-mode Data-Converter (iDC), whose input-output transfer function profiles is programmed by a network of current reference signals of the at least one iDC, wherein the network of current reference signals of the at least one iDC is the network of sequence of signals at a sequence of drain ports of a sequence of mirroring MOSFETs; the sequence of gate-drain ports of the sequence of diode-connected MOSFETs coupled to a sequence of gate ports of the mirroring MOSFETs; wherein each S sR  signal in a sequence of S sR  signals is proportional to a current reference signal (S R ); wherein the sequence of S sR  signals is coupled to the respective sequence of gate-drain ports of sequence of diode-connected MOSFETs; wherein the sequence of scaled S sR  signals are scaled at least one of equally weighted currents, binarily weighted currents, non-linear weighted, and individually weighted currents; wherein the W/L scale of each MOSFET is programmed individually; wherein the iDC is at least one of current-mode Digital-to-Analog-Converter (iDAC) and current-mode Analog-to-Digital-Converter (iADC); wherein if the at least one iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if the at least one iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter system in an integrated circuit, the system comprising: a sequence of current mirrors (iCM), each iCM having a current mirror input port (Ai iCM ) for receiving a sequence of scaled reference current signals S R , a current mirror output port (Ao iCM ), and an input-to-output gain factor (G iCM ); a current mode data converter (iDC) having a sequence of reference input ports (Ar iDC ); the Ao iCM  port of each of the sequence of iCMs coupled to the respective Ar iDC  port of the sequence of Ar iDC  ports of the iDC; wherein each scaled reference current S R  of a sequence of scaled S R  signals is coupled respectively to the Ai iCM  port of each iCM of the sequence of iCMs; wherein the G iCM  of each iCM of the sequence of iCM is programmed individually; wherein the iDC is at least one of current-mode Digital-to-Analog-Converter (iDAC), and current-mode Analog-to-Digital-Converter (iADC); wherein the sequence of scaled S R  signals are scaled at least one of equally weighted currents, binarily weighted currents, non-linear weighted currents, and individually weighted currents; wherein if one or more iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if one or more iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter system in an integrated circuit, the system comprising: a sequence of current mirrors (iCM), each iCM having a current mirror input port (Ai iCM ) for receiving a sequence of scaled reference current signals (S R )s, a current mirror output port (Ao iCM ), and an input-to-output gain factor (G iCM ); one or more current mode data converters (iDC), each of the one or more iDCs having a sequence of reference input ports (Ar iDC ); each of the one or more Ao iCM  ports of each iCM of the sequence of iCMs respectively coupled to the Ar iDC  port of the sequence of Ar iDC  ports of the one or more iDCs; wherein each scaled S R  signal of a sequence of scaled S R  signals is coupled respectively to the Ai iCM  port of each iCM of the sequence of iCMs; wherein the G iCM  of each iCM of the sequence of iCMs is programmed individually; wherein the one or more iDCs is at least one of a current-mode Digital-to-Analog-Converter (iDAC), and a current-mode Analog-to-Digital-Converter (iADC); wherein the sequence of scaled S R  signals are scaled at least one of equally weighted currents, binarily weighted currents, non-linear weighted currents, and individually weighted currents; wherein if one or more iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if one or more iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter system in an integrated circuit, the system comprising: a sequence of Current-Controlled-Voltage-Sources (CCVS)s, each CCVS in the sequence of the CCVSs having an input current port (Ai ccvs ) for receiving a sequence of scaled reference current signals (S R )s, an output port (Ao ccvs ) for providing an output voltage signal (So ccvs ), and an input-current to output-voltage gain factor (G ccvs ); a plurality of current mode data converters (iDC); each iDC of the plurality of iDCs having a sequence of Voltage-Controlled-Current-Sources (VCCS)s; each VCCS of the sequence of VCCSs, in each iDC of the plurality of iDCs, having an input voltage port (Ai vccs ), an output current port (Ao vccs ) for providing an output current signal (So vccs ), and an input-voltage to output-current gain factor (G vccs ); each Ao ccvs  port of the sequence of CCVSs, respectively coupled to each Ai vccs  port of the sequence of VCCSs, in each iDC of the plurality of iDCs; wherein each scaled S R  source of a sequence of scaled S R  sources is coupled respectively to the Ai ccvs  port of each CCVS of the sequence of CCVSs; wherein the sequence of VCCS in each iDC arranges the reference current network of each respective iDC which establishes the input-to-output transfer function of each respective iDC; wherein the G ccvs  of each CCVS of the sequence of CCVSs is programmed individually; wherein the G vccs  of each VCCS of the sequence of VVCSs in each iDC of the plurality of iDCs is programmed individually; wherein the one or more iDC of each iDC of the plurality of iDCs is at least one of a current-mode Digital-to-Analog-Converter (iDAC), and a current-mode Analog-to-Digital-Converter (iADC); wherein the sequence of scaled S R  sources are scaled at least one of equally weighted currents, binarily weighted currents, non-linear weighted currents, and individually weighted currents; wherein if one or more iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if one or more iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. 
     Another aspect of the present disclosure is a multiple channel current-mode data converter method in an integrated circuit, the method comprising: generating a sequence of reference bias current signals (Si Rb ); receiving the sequence of Si Rb  signals into a sequence of Current-Controlled-Voltage-Sources (CCVS)s to generate a sequence of reference bias voltage signals (Sv Rb ); receiving the sequence of Sv Rb  signals into at least one sequence of Voltage-Controlled-Current-Sources (VCCS)s in at least one current mode data converter (iDC), wherein the at least one sequence of VCCSs replicates the sequence of Si Rb  signals; wherein the sequence of Si Rb  signals is weighted at least one of equally, binarily, non-linearly, and individually, and wherein each S Rb  signal is scaled proportionately to a reference current signal (S R ); wherein the sequence of VCCS in the at least one iDC arranges the reference current network of each respective iDC which establishes the input-to-output transfer function of each respective iDC; wherein the at least one iDC is at least one of current-mode Digital-to-Analog-Converter (iDAC) and current-mode Analog-to-Digital-Converter (iADC); wherein the analog output current signal of the iDAC is proportional to S R  signal and responsive to the digital input word of the iDAC; 
     wherein the digital output word of the at least one iADC is responsive to the analog input current signal of the at least one iADC and proportional to the S R  signal; wherein if the at least one iDC includes an iDAC, then the analog output current signal of each iDAC is proportional to the S R  signal received by that iDAC, and responsive to a digital input word received by that iDAC; and wherein if the at least one iDC includes an iADC, then a digital output word of each iADC is responsive to the analog input current signal of that iADC and proportional to the S R  signal received by that iADC. 
     Another aspect of the present disclosure is a meshed multiplier system in an integrated circuit, the system comprising: a first digital input port having a of width of M bits of a first digital input word D X ; a second digital input port having a width of N bits of a second digital input word D Y ; a plurality of N scaled current source banks, each scaled current source bank uniquely corresponding to a bit of D Y ; each of the N scaled current source banks comprising a plurality of M scaled current sources, each scaled current source having a corresponding first switch and a corresponding second switch, each current source uniquely corresponding to a bit of the first digital input word D X ; each scaled current source in each scaled current source bank coupled to an input of its corresponding first switch, the first switch responsive to the bit of the first digital input word D X  corresponding to the scaled current source; the first switch having an output coupled to an input of its corresponding second switch, the second switch responsive to the bit of the second digital input word D Y  corresponding to the scaled current source bank; the second switch having an output coupled to an output node; wherein the N scaled current source banks, are at least one of binarily weighted, linearly weighted, and individually weighted; wherein the plurality of M scaled current sources in each scaled current source bank, are at least one of binarily weighted, linearly weighted, and individually weighted; and wherein M is less than 17, and N is less than 17. Further aspects of the meshed multiplier system in an integrated circuit, the system further comprising: wherein M and N are equal. 
     Another aspect of the present disclosure is a meshed multiplier method in an integrated circuit, the method comprising: receiving a first digital input word D X  of width of M bits, wherein M is less than 17; receiving a second digital input word D Y  of width of N bits, wherein N is less than 17; activating one bank of N banks of M scaled current sources responsive to a bit of D Y  corresponding to the one bank of N banks, thereby activating each of the M scaled current sources; receiving current into an output node from one of the activated M scaled current sources responsive to a corresponding bit of D X . Further aspects of the meshed multiplier system in an integrated circuit, the system further comprising: wherein M and N are equal. 
     Another aspect of the present disclosure is a meshed digital-input to analog current-output multiplier system in an integrated circuit, the system comprising: a digital-input to analog-output multiplier (XD i I o ) comprised of a Ao XY  port, a first digital input port (D X ) wherein the D X  port is M-bit wide, a second digital input port (D Y ) wherein the D Y  port is N-bit wide, and a reference port for receiving a S Ru  signal; the XD i I o  comprising: a sequence of M meshed digital-input to analog current-output sub-multipliers (mD i I o ), wherein each mD i I o  is comprised of a first switch bank (iSW 1   B ), a second switch bank (iSW 2   B ), a current reference signals bank (S R   B ), and a first digital 1-bit wide port (B M ); for each mD i I o , each iSW 1   B  switch bank comprised of a sequence of N switches, wherein the N control-ports of the N switches coupled together, and coupled to a 1-bit wide B M  port; for each mD i I o , each iSW 2   B  switch bank comprised of a sequence of N switches, wherein the gate-ports respectively coupled to the D Y  port. for each mD i I o , the output ports of the first sequence of N switches of the iSW 1   B  switch bank coupled to the input ports of the second sequence of N switches of the iSW 2   B  switch bank; for each mD i I o , each S R   B  signal bank comprised of a sequence of N current reference signal ports (A R ) for receiving sequence of N scaled current reference signals (S R ), wherein the sequence of N scaled S R  signals is at least one of binarily weighted, linearly weighted, and individually weighted, and wherein each scaled S R  signal is proportional to the S Ru  signal; for each mD i I o , the sequence of N scaled S R  sources of the S R   B  signal banks coupled respectively to the sequence of N input ports of the iSW 1   B  switch bank; for each mD i I o , the sequence of N output ports of the iSW 2   B  switch bank coupled to the Ao XY  port; for each mD i I o , the sequence of M 1-bit wide B M  ports coupled to the respective M-bit wide D X  ports; wherein for each mD i I o , a sum of the sequence of N of scaled S R  sources of the S R   B  banks is at least one of binarily weighted, linearly weighted, and individually weighted; and wherein the XD i I o  generates an analog multiplicand signal at the Ao XY  port, that is proportional to the S Ru  signal, and responsive to the multiplication product of digital words at the D X  and the D Y  ports. 
     Further aspects of the meshed digital-input to analog current-output multiplier system in an integrated circuit, the system further comprising: a plurality of the XD i I o ; the Ao XY  port from each of the plurality of XD i I o s coupled to an Ao MAC  port; wherein a signal through the Ao MAC  port is a multiply-accumulate current signal (So MAC ), wherein the So MAC  signal is a summation of signals through the plurality of Ao XY  ports; and wherein the So MAC  is proportional to the S Ru  source and responsive to a plurality of digital words that are the multiplication product of pairs of digital words inputted to a plurality of pairs of D X  and D Y  ports. Further aspects of the meshed digital-input to analog current-output multiplier system in an integrated circuit, the system further comprising: a bias current-mode Digital-to-Analog-Converter (iDAC) for generating a bias current signal (S B ), the bias current signal (S B ) coupled to the So MAC  signal to generate a biased multiply-accumulate current signal (So BMAC ), wherein the So BMAC  signal is the summation of the So MAC  signal and the S B  signal. Further aspects of the meshed digital-input to analog current-output multiplier system in an integrated circuit, the system further comprising: a current-mode Analog-to-Digital Converter (iADC) for digitizing the So BMAC  signal to generate a Do BMAC  word that is a digital representation of the So BMAC  signal. Further aspects of the meshed digital-input to analog current-output multiplier system in an integrated circuit, the system further comprising: each scaled S R  source, of the sequence of N scaled S R  sources of each of the S R   B  signal bank of each mD i I o , is biased from a common reference bias network (RBN). Further aspects of the meshed digital-input to analog current-output multiplier system in an integrated circuit, the system further comprising: a Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFET)s each having a gate-port, a drain-port, and a source port, and each having a scale (W/L); and each switch, of the iSW 1   B  switch bank of each mD i I o , is a MOSFET wherein the input of the switch is the source-port of the MOSFET, the output of the switch is the drain-port of the MOSFET, and the control port of the switch is the gate-port of the MOSFET. 
     Another aspect of the present disclosure is a meshed digital-input to analog current-output multiplier system in an integrated circuit, the system comprising: a digital-input to analog-output multiplier (XD i I o ) comprised of a Ao XY  port, a first digital input port (D X ) wherein the D X  port is w-bit wide, a second digital input port (D Y ) wherein the D Y  port is z-bit wide, and a reference input port for receiving a S Ru  signal; the XD i I o  comprising: a plurality of Metal-Oxide-Semiconductor-Field-Effect-Transistors (MOSFET)s, each having a gate-port, a drain-port, and a source port, and each having a scale (W/L); a sequence of M meshed digital-input to analog current-output sub-multipliers (mD i I o ), wherein each mD i I o  is comprised of a first MOSFET bank (M 1   B ), a second MOSFET bank (M 2   B ), a current reference signals bank (S R   B ), and a first digital 1-bit wide port (B w ); for each mD i I o , each M 1   B  comprised of a sequence of z MOSFETs, the gate-ports of the z MOSFETs coupled together, and coupled to a 1-bit wide B M  port; for each mD i I o , each M 2   B  comprised of a sequence of z MOSFETs, the gate-ports respectively coupled to the D Y  port; for each mD i I o , the drain ports of the first sequence of z MOSFETs coupled to the source ports of the second sequence of z MOSFETs; for each mD i I o , each S R   B  signal bank comprised of a sequence of z current reference signal ports (A R ) for receiving z sequence of scaled current reference signals (S R ), wherein the sequence of z scaled S R  signals is at least one of binarily weighted, linearly weighted, and individually weighted, and wherein each scaled S R  signal is proportional to the S Ru  signal; for each mD i I o , the sequence of z scaled S R  sources of the S R   B  signal banks coupled respectively to the sequence of z input ports of the MY switch bank; for each mD i I o , the sequence of z output ports of the MY switch bank coupled to the Ao XY  port; for each mD i I o , the sequence of w 1-bit wide B w  ports coupled to the respective w-bit D X  ports; wherein for each mD i I o , a sum of the sequence of z of scaled S R  sources of the S R   B  banks is at least one of binarily weighted, linearly weighted, and individually weighted; and wherein the XD i I o  generates an analog multiplicand signal at the Ao XY  port, that is proportional to the S Ru  signal, and responsive to the multiplication product of digital words at the D X  and the D Y  ports. 
     DETAILED DESCRIPTION 
     Numerous embodiments are described in the present application and are presented for illustrative purposes only and is not intended to be exhaustive. The embodiments were chosen and described to explain principles of operation and their practical applications. The present disclosure is not a literal description of all embodiments of the disclosure(s). The described embodiments also are not, and are not intended to be, limiting in any sense. One of ordinary skill in the art will recognize that the disclosed embodiment(s) may be practiced with various modifications and alterations, such as structural, logical, and electrical modifications. For example, the present disclosure is not a listing of features which must necessarily be present in all embodiments. On the contrary, a variety of components are described to illustrate the wide variety of possible embodiments of the present disclosure(s). Although particular features of the disclosed embodiments may be described with reference to one or more particular embodiments and/or drawings, it should be understood that such features are not limited to usage in the one or more particular embodiments or drawings with reference to which they are described, unless expressly specified otherwise. The scope of the disclosure is to be defined by the claims. 
     Although process (or method) steps may be described or claimed in a particular sequential order, such processes may be configured to work in different orders. In other words, any sequence or order of steps that may be explicitly described or claimed does not necessarily indicate a requirement that the steps be performed in that order. The steps of processes described herein may be performed in any order possible. Further, some steps may be performed simultaneously despite being described or implied as occurring non-simultaneously (e.g., because one step is described after the other step). Moreover, the illustration of a process by its depiction in a drawing does not imply that the illustrated process is exclusive of other variations and modifications thereto, does not imply that the illustrated process or any of its steps are necessary to the embodiment(s). In addition, although a process may be described as including a plurality of steps, that does not imply that all or any of the steps are essential or required. Various other embodiments within the scope of the described disclosure(s) include other processes that omit some or all of the described steps. In addition, although a circuit may be described as including a plurality of components, aspects, steps, qualities, characteristics and/or features, that does not indicate that any or all of the plurality are essential or required. Various other embodiments may include other circuit elements or limitations that omit some or all of the described plurality. 
     Consider that all the figures comprised of circuits, blocks, or systems illustrated in this disclosure are powered up by positive and negative power supplies, V DD  and V SS  (and V SS  can be connected to the ground potential or zero volts for single supply applications), respectively (unless otherwise specified), and they are not shown for illustrative clarity of the disclosed figures. Terms FET is field-effect-transistor; MOS is metal-oxide-semiconductor; MOSFET is MOS FET; PMOS is p-channel MOS; NMOS is n-channel MOS; BiCMOS is bipolar CMOS. Throughout this disclosure, the body terminal of NMOSFET can be connected to the source terminal of NMOSFET or to V SS . Also, the body terminal of PMOSFET can be connected to the source terminal of PMOSFET or to V DD . The term V GS  is gate-to-source port voltage of a MOSFET. The term V DS  is drain-to-source port voltage of a MOSFET. The term I DS  or I D  is drain current of a MOSFET. The term V A  is a device parameter, and the early voltage a MOSFET. 
     All the data-converters including, analog-to-digital-converters (ADC) as well as digital-to-analog-converters (DAC) may not show, for illustrative clarity, a positive reference and a negative reference input, where the negative reference input can be connected to the ground potential or zero volts. A current-mode DAC is iDAC, and a current-mode ADC is iADC. A current analog switch (iSW) has one input, one digital control signal, and either one or two output ports that receive the iSW input signal. An iSW with two output ports, steer the iSW&#39;s input signal to either of iSW&#39;s output ports depending on the polarity of the iSW digital control signal. An iSW with one output, steer the iSW&#39;s input signal to iSW&#39;s the positive output port or blocks it depending on the polarity of the iSW digital control signal. Most-Significant-Bit is MSB and Least-Significant-Bit is LSB, pertaining to data-converters digital bits. Most-Significant-Portion is MSP and Least-Significant-Portion is LSP, pertaining to the portions of signals represented by the MSB bank digital-word and LSB bank digital-word of data-converters, wherein the data-converter&#39;s whole digital word is comprised of the LSB bank digital-word plus the MSB bank digital-word. 
     The term non-linear data-converter (DAC or ADC) refers to a data-converter whose transfer function (as arranged by the data-converter&#39;s reference network) is non-linearly weighted (e.g., square or logarithmic or individually weighted). Similarly, the term linear data-converter (DAC or ADC) refers to a data-converter whose transfer function (as arranged by the data-converter&#39;s reference network) is linearly weighted (e.g., binary or equally weighted thermometer). 
     Throughout this disclosure, for demonstrative and descriptive clarity, data-converter that may be illustrated with 2 to 8 bits of resolution, but they can be arranged with higher resolutions, unless otherwise specified (e.g., disclosed data-converters can have higher resolutions where 16-bits of resolution is practical). Moreover, for descriptive clarity illustrations are simplified, where their modifications for improvements would be obvious to one skilled in the arts, such as for example cascading current sources by stacking MOSFETs to increase their output impedance. In some instances, analog switches are shown as single FETs with one input, one output, and a control input. In such instances, the one FET acting as a switch can be replaced with two FETs with a common input but opposite control polarity to manage the switch input&#39;s on and off voltage span and improve on-off glitch transients. 
     Consider that other manufacturing technologies, such as Bipolar, BiCMOS, and others can utilize the disclosure in whole or part. 
     Unless otherwise specified, the illustrated data-converters are generally asynchronous (i.e., they are clock free) which eliminates the need for a free running clock and improves dynamic power consumption with lower clock noise. However, the methods, systems, or circuits disclosed generally are applicable to data-converters that are synchronous (i.e., requiring clocks). 
     This disclosure presents several SPICE circuit simulations showing the various waveforms attributed to the disclosed data-converts and multipliers. The simulations are performed in order to demonstrate functionality of the disclosed embodiments. These simulations are not intended to guarantee the embodiment&#39;s performance to a particular range of specifications. Be mindful that circuit simulations use the TOPSPICE simulator, and are based on approximate device models for a typical standard mainstream 0.18 μm CMOS process fabrication. 
     Throughout this disclosure, data-converters utilized in multipliers and multiply-accumulate circuits operate in current-mode and generally have the following benefits: 
     First, data-converters operating in current-mode are inherently fast. 
     Second, current signal processing that occurs within the nodes of data-converters, generally, have small voltage swings which enables operating the current-mode data-converters with lower power supply voltages. 
     Third, operating at low supply voltage reduces power consumption of current-mode data-converters. 
     Fourth, current input and current output zero-scale to full-scale spans of current-mode data-converters are less restricted by power supply voltage levels (e.g., current input and outputs can generally span to full-scale at minimum power supply voltages) 
     Fifth, current mode CMOS data-converters can operate in subthreshold that enables reducing power consumption further. 
     Sixth, summation and subtraction functions in analog current-mode is generally simple and takes small chip area. For example, summation of two analog currents could be accomplished by coupling the current signals. Depending on accuracy and speed requirements, subtraction of analog current signals could be accomplished by utilizing a current mirror where the two analog current signals are applied to the opposite side of the current mirror, for example. 
     Seventh, current-mode data-converters can operate internally in mixed-mode and externally have compatible interface with conventional digital processors. For example, digital-to-analog converters and multipliers can operate in current mode analog and or mixed-mode and subsequently have their current mode computations be converted to digital in order to seamlessly interface with standard digital processors via current-mode analog-to-digital converters. 
     Eight, accuracy of mixed-signal current-mode data-converters, depending on the architecture, generally depends (at least in part) on the matching between FET current sources in the data-converter&#39;s current reference or bias network that programs their transfer function. Moderate conversions speeds with typical accuracies up to 16-bits with trimming or calibration and up to 10-bits without trimming or calibration may be achievable in standard CMOS manufacturing, where non-minimum size FETs are utilized to form the data-converter&#39;s current reference or bias network. Such accuracies can be sufficient for a range of near-edge or near-sensor machine learning and artificial intelligence (ML &amp; AI) applications that may also not require extremely fast computation speeds. As such, some near-edge or near-sensor ML &amp; AI applications can benefit from the low-cost and low-power of mixed-signal current-mode computation that only requires low cost conventional CMOS manufacturing, as compared to high-speed power-hungry high-precision digital processors that require the substantially more expensive deep-sub-micron CMOS technologies. 
     Section 1—Description of FIG.  1   
       FIG. 1  is a simplified block diagram illustrating a floating current-mode (i) digital-to-analog-converter (iDAC) method. 
     The disclosed floating iDAC method, substantially equalizes a reference current signal (I 1   1 ) with the sum of a plurality of currents that are generated by plurality of floating voltage controlled current sources (VCCS). The plurality of VCCS&#39;s currents are scaled by programming each of the VCCS&#39;s voltage-to-current transconductance gains (G). Moreover, the plurality of VCCS&#39;s currents are selected by a plurality of respective current switches (iSWs) wherein the iSWs are controlled by the iDAC&#39;s digital input word, to steer the iSW&#39;s respective outputs to iDAC&#39;s outputs (I O   + , and I O   − ). 
     The floating iDAC method can be utilized in an iDAC having a n-bit (n≤16) wide digital word (Di 1 ), a current reference signal (I 1   1 ), and two analog current outputs such as a first analog current output terminal Io 1   +  and a second analog current output terminal Io 1   −  of (coupled with a bias voltage source such as V 1   1 ). The floating iDAC method is illustrated in a system diagram of  FIG. 1  having plurality (e.g., n=3) of VCCSs or voltage controlled current sources (e.g., G 1   1 , G 2   1 , and G 3   1 ). Each VCCS has a positive input voltage terminal and a negative input voltage terminal (VCCS V   + , and VCCS V   − ) and a positive output current terminal and a negative output current terminal (VCCS I   + , and VCCS I   − ). The respective VCCS&#39;s output currents (e.g., I G3     1   , I G2     1   , and I G1     1   ) flow-in is the respective VCCS&#39;s positive current output terminals VCCS I   + s and flow-out of the respective VCCS&#39;s negative current output terminals VCCS I   − s. At node ng 1 , the floating iDAC method receives a reference current signal I 1   1 . Each of the negative input voltage terminals of the plurality of VCCSs, and each of the negative output current terminals of plurality of VCCSs are coupled together at node ng 1 . Each of the positive input voltage terminal of the plurality of VCCSs are coupled together that is also coupled with a voltage signal from a voltage source V 2   1 . Consider that, I G3     1   , I G2     1   , and I G1     1    current sources are floating on I 1   1  which is a floating iDAC&#39;s reference current source. There is a plurality of current switches (iSW) each with a digital control input, an analog current input, and two analog current output terminals. The respective digital control inputs of the plurality of iSWs are coupled with the respective plurality of iDAC&#39;s digital input bits (that make up the digital word Di 1 ). When the iSW&#39;s digital control input is enabled (e.g., positive polarity), then the iSW&#39;s analog input current is routed to Io 1   +  which a first analog current output of iDAC. When the iSW&#39;s digital control input is disabled (e.g., negative polarity), then the iSW&#39;s analog current input is routed to the second analog current output of iDAC or Io 1   − . 
     In illustration of  FIG. 1 , given V 2   1 −V ng1 =V f1 , then I G1     1   =V f1 ×S 1 ×g, I G2     1   =V f1 ×S 2 ×g, and I G3     1   =V f1 ×S 3 ×g. As noted earlier, the plurality of output currents (e.g., I G1     1   , I G2     1   , and I G3     1   ) of the respective the VCCSs (e.g., G 1   1 , G 2   1 , and G 3   1 , respectively) are fed onto the respective plurality of iSW&#39;s inputs. Accordingly, I G1     1   +I G2     1   +I G3     1   =I 1   1 =I R , where I R  is the reference current to the iDAC and establishes the full-scale out of the iDAC. The V f1  is the voltage input to each of the VCCSs. The transconductance gain of a single unit VCCS is g, which is scaled by programming the gain scale factors (e.g., s 1 , s 2 , and s 3 ) for each respective VCCS. 
     Let&#39;s consider programming the VCCS&#39;s gain factors for a binary weighted iDACs. In a general, a simplified transfer function for an iDAC is: 
                 I   o     =         I   R     ⁢       ∑     i   =   1     n     ⁢       D   i     /     2   i           =         (       I   R     /     2   n       )     ⁢       ∑     i   =   1     n     ⁢       D   i     ×     2     i   -   1             =       Δ   R     ⁢       ∑     i   =   1     n     ⁢       D   i     ×     2     i   -   1                   ,         
where for the iDAC, I o  is the analog output current, I R  is the reference input current that can set the full-scale value of I o , D i  is the digital input word (that is n-bits) wide, and Δ R =(I R /2 n ) is the analog LSB current weight of I o . For an iDAC with n=3, by programming gain scale factors s 1 =1, s 2 =2, and s 3 =4, then I G1     1   =I G1     3   /2=I G1     3   /4 which is a binary weighted current source network, whose binary weighted current sources are selected by iSWs in accordance with the Di i  digital input word of the iDAC. Note that the iDAC&#39;s full scale is I R =I 1   1 =I G1     1   +I G1     2   /2+I G1     3   /4. Note also that the VCCS&#39;s gain scale factors can be programmed to other ratios, including but not limited to, substantially equal ratio (which enables making a thermometer coded current-mode DAC), or non-linear ratio (which enables making for example a logarithmic current-mode DAC or a current-mode DAC with a square transfer fiction). Some of the benefits of the floating iDAC method is highlighted in its embodiment disclosed in  FIG. 2  section 2 next.
 
     Section 2—Description of FIG.  2   
       FIG. 2  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that utilizes the floating iDAC method illustrated in  FIG. 1 . 
     As noted earlier, for illustrated clarity, a n=3 bits binary weighted iDAC is described but n can be as large of 16 bits. Bias voltage V 2   2  provides the positive input voltage to the gate terminal of 3 field-effect-transistors (FETs) M 4   2 , M 5   2 , and M 6   2 , which perform the function of the three VCCSs (corresponding to G 1   1 , G 2   1 , and G 3   1  functions in  FIG. 1 , respectively) as floating current sources. By the scaling width over length ratios (W/L) of M 4   2 , M 5   2 , and M 6   2 , the respective plurality of VCCS&#39;s transconductance gain factors can be programmed. Bear in mind that, I M4     2   , I M5     2   , and I M6     2    may be described as floating current sources on I M2     2   . For nomenclature clarity consider that, as an example, I M2     2    refers to the drain-to-source current of MOSFET M 2   2 , which is a manner of terminology is applied throughout out this disclosure. In a binary weighted iDAC, the gain factors s 1 =1, s 2 =2, and s 3 =4, and as a result I M6     2   =I M5     2   /2=I M4     2   /4. Consider that s 4  scale ratio of M 3   2  is not critical and can be programmed to, for example, 1 in the binary weighted iDAC case, so long as the drain-to-source voltage (V DS ) of M 1   2  and M 2   2  are matched close enough to keep the FET&#39;s early voltage (V A ) mismatch error within design objectives. By operation of the Kirchhoff s current law (KCL) at node ng 2 , I M6     2   +I M5     2   +I M4     2   =I M2     2   , which substantially equalizes the full-scale current of the iDAC to I M2     2   =I R , (notice that I M2     2    of  FIG. 2  is analogous to equivalent of I R =I 1   1  of  FIG. 1 ). The iDAC&#39;s digital-input words, from Most-Significant-Bit (MSB) D 3   2  to Least-Significant-Bit (LSB) D 1   2  control the respective iDAC&#39;s iSWs: M 7   2 -M 8   2 , M 9   2 -M 10   2 , and M 11   2 -M 12   2 . For example, when D 3   2  is in high state (i.e., MSB is on), then the iSW M 8   2  is on and iSW M 7   2  is off and accordingly I M4     2    is steered through M 8   2  to the iDAC&#39;s current output port Io 2   + . If D 3   2  is in low state, then M 4   2 &#39;s current is steered through M 7   2  to the iDAC&#39;s second current output port Io 2   − . Similarly, and in accordance with the polarity of the iDAC&#39;s digital input words, the iSWs steer the respective iDAC&#39;s binary weighted currents I M4     2   , I M5     2   , and I M6     2    onto either the Io 2   +  port (which is the iDAC&#39;s first analog current output port) or the second iDAC analog current output port Io 2   −  (that is in this case shunted onto voltage source V 1   2 ). 
     For illustrative clarity, programming current mirror scale factor a=b=1, then I 1   2 =I M1     2   =I M2     2   =I R′ . The injection currents I 2   2 =I 3   2  are applied to both side of M 1   2 -M 2   2  current mirror to prevent the said mirror from shutting off, thus improving its dynamic response, when I 1   2  is pulsed between zero and full scale. Also, consider that by utilizing the floating iDAC method, the scaling of iDAC reference current network (e.g., M 4   2 , M 5   2 , and M 6   2 ) are decoupled from the scaling of I 1   2  through M 1   2 -M 2   2  mirror W/L ratios. Such decoupling of current reference network scaling, reduces FET&#39;s sizes and lowers the capacitance associated with the small scaled FETs which also improves the iDAC&#39;s transient response and lowers glitch. 
     Note that the floating iDAC disclosed in  FIG. 2  generally utilizes NMOSFETs, including for iSWs and for the floating current source transfer function network. Variations of this disclosure would be obvious to one skilled in the art, including to utilize a complementary floating iDAC comprising of NMOS current reference sources and PMOS iSWs, or combination thereof. 
     In summary, some of the benefits of the floating iDAC method disclosed in section 1  FIG. 1 , and such benefits flowing into the embodiment of the floating iDAC of  FIG. 2 , which are as follows: 
     First, the floating VCCSs generate the scaled current reference network for the iDAC, that can be decoupled from the scaling of I M1     2   , I M2     2    mirror and I 1   2  reference current. The decoupling of scaling of current reference network provides a degree of freedom that helps the iDAC reduce FET scaling and sizes which saves die are, lowers cost, and also lowers the capacitance attributed to larger size FETs in the iDAC&#39;s current reference network which in turn improve the transient response of the iDAC. 
     The decoupling of scaling of current reference network, also provides simple means to improve the dynamic response of the iDAC when its reference input signal I 1   2  is pulsed between zero and full scales. This is accomplished by injecting currents b×I 2   2 =a×I 3   2  to both side of M 1   2 -M 2   2  current mirror to prevent the mirror from shutting off, and hence improving its dynamic response. 
     Second, the iDAC operating in current-mode is inherently fast. 
     Third, voltage swings in current-mode signal processing are small, which enables operating the iDAC with lower power supply voltage and retain the speed and dynamic rage benefits. Also, floating iDAC can operate with low power supplies since its operating headroom can be limited by a FET&#39;s VGS+VDS. Additionally, the flexibility to run the CMOSFETs in subthreshold enables a floating iDAC to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that may require numerous ultra-low power and low power supply DACs for computation. 
     Fourth, operating at low supply voltage reduces power consumption. 
     Fifth, signal processing such as addition or subtraction, in current mode, are also small and fast. 
     Sixth, the VCCS&#39;s gain factor can be programmed for an objective iDAC&#39;s transfer function such as binary weighted, thermometer, logarithmic, square function, or other non-linear iDAC transfer functions, as required by the application. 
     Seventh, by substantially equalizing the terminal voltages at Io 2   +  and Io 2   −  (e.g., to V 1   2 ), the iSW&#39;s transient and glitch responses are improved since the two outputs of iSW at Io 2   +  and Io 2   − , could swing between approximately equal voltages, during on and off iDAC&#39;s digital input code transitions. 
     Eight, there are no passive devices in the embodiment of  FIG. 2 , and as such there is no need for resistors or capacitors, which reduces die size and manufacturing cost. Not requiring any capacitors nor any resistors would facilitates fabricating a floating iDAC in standard digital CMOS manufacturing that is not only low cost, but also main-stream and readily available for high-volume mass production applications, and proven for being rugged and having high quality. 
     Ninth, the precision of the iDAC can be improved by for example utilizing current source segmentation (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code), or cascading the iDAC&#39;s reference current mirrors to improve their output impedance. 
     Tenth, a floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Eleventh, a floating iDAC can utilize same type of MOSFET current sources and MOSFET switches that are arranged in a symmetric, matched, and scaled manner. This trait facilitates devices parameters to track each other over process, temperature, operating condition variations. Accordingly, the iDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Twelfth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents) regions. For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals. 
     Section 3—Description of FIG.  3   
       FIG. 3  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that combines a plurality of iDACs to arrange a higher resolution iDAC, wherein at least one of the plurality of iDACs utilizes the floating iDAC method illustrated in  FIG. 1 . 
     The individual floating iDACs utilized in  FIG. 3  are arranged in a similar manner as that of  FIG. 2  in section 2.  FIG. 3  illustrates a 5-bit iDAC but higher resolutions iDACs can be arranged and up to 16-bits of resolution is practical. The iDAC of  FIG. 3  is comprising of a first 2-bits floating iDAC that is a most-significant bank (MS bank iDAC) and a second 3-bits floating iDAC that is a least-significant bank (LS bank iDAC). Here, the full-scale output current weight of the MS bank iDAC is 2 2 =4 times bigger than that of the LS bank iDAC. The MSB of the 5-bit iDAC is D 5   3  and the LSB of the 5-bit iDAC is D 1   3 . The 5-bit iDAC&#39;s reference current in  FIG. 3  is I 1   3  and the iDAC&#39;s output currents are Io 3   +  and Io 3   − . 
     The upper half of  FIG. 3  (that is outside the Block  3 A dotted area) is the LS bank iDAC (with D 1   3 , D 2   3 , and D 3   3  as its respective digital inputs) that is similar to that of  FIG. 2  described in section 2. The lower half of  FIG. 3  that is inside the Block  3 A dotted area is a 2-bit floating iDAC which is the MS bank iDAC (with D 4   3 , and D 5   3  as its respective digital input bits) generating a positive and a negative output currents Im 3   +  and Im 3   −  (respectively) that are added to (coupled with) the iDAC&#39;s output currents to produce the total Io 3   +  and Io 3   − . 
     To optimize for cost-performance objective, the embodiment illustrated in  FIG. 3  has the flexibility to program the reference current value and iDAC&#39;s input-to-output transfer function. For descriptive clarity of the operations of  FIG. 3 , let&#39;s program the 5-bit iDAC as binary weighted (instead of a non-linear or thermometer input-out transfer function for the iDAC, for example). As an example, with the reference current I 1   3 =8 I R , let&#39;s program the reference current mirror scale factors in the iDAC&#39;s transfer function network as follow: M 13   3 &#39;s c=3, M 2   3 &#39;s b=1, and M 1   3 &#39;s a=1. Also, let&#39;s program s 6 =2×s 5  and analogous to the example in section 2 (pertaining to  FIG. 2 ) s 3 =2×s 2 =4×s 1 . Notice that, I M14     3    and I M15     3    can be viewed as floating current sources on I M13     3   . Similarly, I M4     3   , I M5     3   , I M6     3   , and I M20     3    can be viewed as floating current sources on I M23 . With scale factors programmed as noted above, a binary weighted current reference network can be arranged as follows: I M13     3   =24I R →I M14     3   =16I R , I M15     3   =8I R  for the MS bank iDAC. Also, I M1     3   =I M2     3   =8I R →I M4     3   =4I R , I M5     3   =2I R , and I M6     3   =I R  for the LS bank iDAC. Consider that with I M23 =8I R  and M 20   3 &#39;s S 1 =1, then I M20     3   =I R  which leaves 7I R  to be split in accordance with programmed scaled factors s 3 =2×s 2 =4×s 1  between I M43 =4I R , I M5     3   =2I R , and I M63 =I R . 
     Additionally, bear in mind that I M20     3   =I R  is terminated in Io 3   −  in this example, but I M20     3    can be terminated in Io 3   +  depending on zero-scale or full scale (LSB current) offset requirement of the end-application. Moreover, note that the same voltage source V 2   3  biases the gate terminals of M 14   3 , M 15   3 , and M 20   3 . As means for improving the transient recovery time of M 1   3 , if and when I 1   3 =8I R  is pulsed between zero and full scale, a proportional constant current (Ij 3  which is not shown but) can be added onto I 1   3 , to keep M 1   3  alive, plus two scaled Ij 3  can be injected into nodes ng 3  and ng 3′ . Also consider that similar to  FIG. 2  in section 2, the purpose of utilizing V 1   3  in  FIG. 3  is to substantially equalize the Io 3   +  and Io 3   −  terminal voltages for better matching and dynamic response (e.g., if Io 3   +  is terminated into a diode connected current mirror, then V GS  of a diode connected FET can also be utilized to set the V 1   3  for Io 3   − ). 
     Notice that the floating iDAC disclosed in  FIG. 3  generally utilizes NMOSFETs, including for iSWs and the floating current source transfer function network. It would be obvious to one skilled in the art to utilize a complementary floating iDAC comprising of PMOS or a combination of PMOS and NMOS current reference transfer function and PMOS iSWs. 
     In addition to some of the benefits of the floating iDAC method disclosed in section 2  FIG. 2 , the embodiment of  FIG. 3  illustrates that the floating iADC method is scalable and can be expanded in combination with other iDACs to attain higher resolutions. 
     Section 4—Description of FIG.  4   
       FIG. 4  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that combines a plurality of iDACs to arrange a higher resolution iDAC, wherein at least one of the plurality of iDACs utilizes the floating iDAC method illustrated in  FIG. 1 . 
     The iDAC illustrated in  FIG. 4  is similar to the iDAC described in  FIG. 3  section 3 with the difference being the MS bank iDAC is not a floating iDAC.  FIG. 4  illustrates a 5-bit iDAC but higher resolutions iDACs can be arranged and up to 16-bits of resolution is practical. The iDAC of  FIG. 4  is comprising of a first 2-bits iDAC that is a most significant bank (MS bank iDAC shown inside the dotted line as Block  4 A). The iDAC of  FIG. 4  is also comprising of a second 3-bits floating iDAC that is a least significant bank (LS bank iDAC). In iDAC of  FIG. 4  the full-scale output current weight of the MS bank iDAC is 2 2 =4 times bigger than that of the LS bank iDAC. The MSB of the 5-bit iDAC in  FIG. 4  is D 5   4  and the LSB of the 5-bit iDAC is D 1   4 . The 5-bit iDAC&#39;s reference current in  FIG. 4  is I 1   4  and the iDAC&#39;s output currents are Io 4   +  and Io 4   − . 
     The upper half of  FIG. 4  (that is outside the Block  4 A dotted area) is the LS bank iDAC (with D 1   4 , D 2   4 , and D 3   4  as its respective digital inputs) similar to that of  FIG. 2  and  FIG. 3  that were described in sections 2 and 3, respectively. As noted earlier, the lower half of  FIG. 4  that is inside the Block  4 A dotted area is another 2-bit floating iDAC which is the MS bank iDAC (with D 4   4 , and D 5   4  as its respective digital inputs) generating a positive and a negative output currents Im 4   +  and Im 4   −  (respectively) which are added to (by being coupled with) the first iDAC&#39;s output currents Io 4   +  and Io 4   − . 
     To optimize for cost-performance objective, there is flexibility in programming the iDAC&#39;s reference current value and input-output transfer function network of the iDAC in  FIG. 4 . To describe the operations of  FIG. 4 , let&#39;s program the 5-bit iDAC as binary weighted for the purpose of the disclosure&#39;s descriptive clarity. As an example, with the reference current I 1   4 =8I R , let&#39;s program the reference current mirror W/L scales as follow: M 13   4 &#39;s c=2, M 20   4 &#39;s d=1, M 2   4 &#39;s b=1, and M 1   4 &#39;s a=1. Let&#39;s program S 3 =2×S 2 =4×S 1  in  FIG. 4 . With W/L scales programmed as such, a binary weighted current reference network is arranged comprising of I M13     4   =16I R , I M20     4   =8I R  for the MS bank iDAC. As noted earlier, I M4     4   , I M5     4   , I M6     4   , and I M21     4    current sources can be viewed as floating on I M2     4   . Also, I M1     4   =I M2     4   =8I R →I M4     4   =4I R , I M5     4   =2I R , and I M6     4   =I R  for the LS bank iDAC in  FIG. 4 . Given that I M2     4   =8I R  and M 21   4 &#39;s S 1 =1, then I M21     4   =I R  which leaves 7I R  to be split in accordance with programmed scaled factors S 3 =2×S 2 =4×S 1  between I M44 =4I R , I M5     4   =2I R , and I M64 =I R . 
     Additionally, consider that in  FIG. 4 , I M21     4   =I R  is terminated in Io 4   −  in this example, but I M21     4    can be terminated in Io 4   +  depending on zero-scale or full scale (LSB current) offset requirement of the application. Moreover, consider that the same voltage source V 2   4  biases the gate terminals of M 14   4 , M 15   4 , and M 20   4 . As means for improving the transient recovery time of M 1   4 , when I 1   4 =8I R  is pulsed between full and zero scales, a proportional constant injection DC current (Ij 4  which is not shown but) can be added onto I 1   4 , to keep M 1   4  alive, plus two scaled Ij 4  can be injected into nodes ng 4  and the drain terminals of FETs M 13   4  and M 20   4 . Also bear in mind that similar to  FIG. 2  in section 2, the purpose of utilizing V 1   4  in  FIG. 4  is to substantially equalize the Io 4   +  and Io 4   −  terminal voltages for better matching and dynamic response (e.g., if Io 4   +  is terminated into a diode connected current mirror, then V GS  of a diode connected FET can also be utilized as the V 1   4  for Io 4   − ). 
     In addition to some of the benefits of the floating iDAC method disclosed in section 2  FIG. 2 , the embodiment of  FIG. 4  illustrates that the floating iADC method is scalable and can be expanded through combination with other iDACs to attain higher resolutions. 
     Section 5—Description of FIG.  5   
       FIG. 5  is a simplified schematic diagram illustrating a mixed-signal current-mode digital-input to analog-current-output multiplier (XD i I o ) comprising of a first iDAC whose output supplies the reference input to a second iDAC, wherein the first and second iDACs utilize the floating iDAC method illustrated in  FIG. 1   
     The first and second floating iDACs embodiments are similar to the floating iDAC described and illustrated in section 2  FIG. 2 . 
     For clarity of description, both floating iDACs of  FIG. 5  are arranged as binary-weighted, and accordingly the current reference transfer-function is programmed for FET W/L scales s 3 =2×s 2 =4×s 1 . 
     For illustrative clarity, instead of showing iSWs with FET level circuit schematics (e.g.,  FIG. 2  section 2 where MSB current switch comprising M 7   2 , U 1   2 , and M 8   2  etc.), the iSWs in  FIG. 5  are shown as block diagrams (e.g., MSB current switch S 1   5 , etc.) utilized in floating iDACs. Additionally, bear in mind that the XD i I o  illustrates a 3-bit digital input word Q being multiplied with a 3-bit digital word P, but each P and Q digital input words can be up to 16-bits. 
     The left side of  FIG. 5  illustrates the first floating iDAC (Q-iDAC) with its Q D  digital-input word (comprising of 3-bits Q 1   5 , Q 2   5 , and Q 3   5  where Q 1   5  is the MSB and Q 3   5  is the LSB), and its reference input current I R =I 1   5 . The I 1   5  is fed onto a diode connected FET M 1   5  whose current is scaled and mirrored onto M 2   5  in accordance with the programmed W/L scales a and b of M 1   5  and M 2   5 , respectively. For clarity of this description, let&#39;s set a=b=1, and thus I R =I 1   5 =I M1     5   =I M2     5     .    
     The Q-iDAC&#39;s positive and negative analog output currents Iq 5   +  and Iq 5   −  are generated as a function of its Q digital-input word and I 1   5 . The digital-input to analog-current-output transfer-function of the Q-iDAC, which is binary weighted in  FIG. 5 &#39;s illustration, can mathematically be expressed as 
               Iq   5   +     =         (       I   R     /     2   n       )     ×       ∑     i   =   1     n     ⁢       Q     i   5       ×     2     i   -   1             =       Δ   R     ×       ∑     i   =   1     n     ⁢       Q     i   5       ×       2     i   -   1       .                   
Here, for a=b=1, Iq 5   + =I M8     5   =I M9     5    is the analog-output current of the Q-floating iDAC. Also, Δ R =I R /2 n ) with I R =I 1   5 , and n=3 is the resolution of the Q-floating iDAC. Lastly, Q i     5    is 0 or 1 representing the value of the i th  digital input bits (with 3-bits Q 1   5 , Q 2   5 , and Q 3   5 ) of the Q-floating iDAC. Let&#39;s simplify the Q-floating transfer function representation as Iq 5   + =I 1   5 ×f(Q D ). Consider that the Iq 5   +  is fed onto a diode-connected FET M 8   5  whose current is scaled and mirrored onto M 9   5  to supply the reference current signal for the P-iDAC.
 
     The right side of  FIG. 5  illustrates the P-iDAC with its P D  digital-input word (comprising 3-bits P 1   5 , P 2   5 , and P 3   5  where P 1   5  is the MSB and P 3   5  is the LSB) and its reference input current I M85 =Iq 5   + =I 1   5 ×f(Q D )=I M9     5    considering the programmed W/L scales arrangement where a=b=1. Consider that in  FIG. 5 &#39;s illustration, the iSWs in P-iDACs are PMOSFETs whereas the iSWs in Q-iDACs are NMOSFETs. Accordingly, the Q D  and P D  digital-input words are properly arranged to apply the complementary digital-input signs to the  FIG. 5 &#39;s iSWs. 
     The P-iDAC&#39;s positive and negative analog output currents Ipq 5   +  and Ipq 5   −  are generated as a function of its P-digital-word and I M9     5   . The digital-input to current analog-output transfer-function of the P-iDAC (that is binary weighted in the illustration of  FIG. 5 ) can also mathematically be expressed as: 
               Ipq   5   +     =         (       I     R   ′       /     2   m       )     ×       ∑     j   =   1     m     ⁢       P     j   5       ×     2     j   -   1             =         Δ     R   ′       ×       ∑     j   =   1     m     ⁢       P     j   5       ×     2     j   -   1             =         I     M   ⁢           ⁢     9   5         /     2   m       ×       ∑     j   =   1     m     ⁢       P     j   5       ×     2     j   -   1                       
where Ipq 5   +  is the positive analog output current of the P-iDAC, I M9     5   =I q     5   =I 1   5 ×f(Q D ), and m=3 is the resolution of the P-iDAC and P j     5    is 0 or 1 representing the value of the j th  digital input bits (with 3-bits P 1   5 , P 2   5 , and P 3   5 ) of the P-iDAC. Therefore, the P-iDAC transfer function can be represented in the simplified form: Ipq 5   + =I 1   5 ×f(Q D )×f(P D ) or f(Q D )×f(P D )=I pq     5   /I 1   5  which is an expression that represents the multiplication results of two digital-input words Q D  and P D , where the multiplication result is represented as an analog-output current I pq     5    proportional to a current proportional to I 1   5  which is proportional to a reference current (I R ).
 
     Bear in mind that the Ipq 5   −  is fed onto a voltage source V 2   5  to match terminal voltage at Ipq 5   + . Furthermore, as means to enhance the dynamic response of reference mirror current signals that is subjected to a pulse, I 2   5  is added as a constant current injection (Ij 5 ) to keep M 8   5  alive when for example Iq 5   +  transitions between zero and full scale. As such, a proportional I 3   5  is added to M 9   5  to balance the current mirror M 8   5 -M 9   5 . 
     In summary some of the benefits of the XD i I o  utilizing the floating iDAC method are as follows: 
     First, the decoupling of scaling of current reference network, helps reduce FET sizes which saves die are, lowers cost. This trait also lowers the capacitance attributed to large size FETs in the iDAC&#39;s current reference network, which in turn improves the transient response of the floating iDAC and the multiplier XD i I o  that utilizes such iDACs. The decoupling of scaling of current reference network, also provides simple means to improve the dynamic response of the iDAC and that of the multiplier XD i I o  when the iDAC&#39;s reference input signal is pulsed. One mean of accomplishing this goal is by injecting a scaled DC current on each side of the current mirror that supplies the iDAC&#39;s reference current, which helps prevent the mirror from shutting off, and thus improving its dynamic response. 
     Second, the XD i I o  operating in current-mode is inherently fast. 
     Third, voltage swings in current-mode signal processing are small, which enables operating the XD i I o  with lower power supply voltage. 
     Fourth, operating at low supply voltage reduces power consumption of the XD i I o . Additionally, the flexibility to run the CMOSFETs in subthreshold enables the iDAC to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that may require numerous ultra-low power and low power supply DACs for computation. 
     Fifth, XD i I o &#39;s output signal processing in current-mode such as addition or subtraction functions are also small and fast, which for example is important in ML &amp; AI applications requiring plurality of multiplier&#39;s outputs to be (summed) accumulated. For example, to sum plurality of signals in current-mode simply involves coupling the current signals together. 
     Sixth, by substantially equalizing the terminal voltages at the positive and negative current output of the iDAC, it would improve the iSW&#39;s transient response and reduces glitch between the iSW&#39;s on to off transitions, which helps the transient response of the XD i I o . 
     Seventh, there are no passive devices in the embodiment of  FIG. 5 , and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost of the XD i I o . 
     Eighth, the precision of the iDAC and hence the precision of the XD i I o  multiplier can be improved by for example utilizing current source segmentation (along with digital binary-to-thermometer coding) in the iDAC&#39;s reference current transfer-function, or cascading the iDAC&#39;s reference current mirrors to improve their output impedance. 
     Ninth, utilizing lower resolution iDACs (e.g., 3-bits or 5-bits) in the XD i I o  multiplier, that occupy smaller areas, but have higher accuracy (e.g., 8-bits of resolution corresponding to accuracy of ±0.4%) is beneficial. For example, higher than 3 of 5 bits of accuracy is attainable in standard CMOS fabrication. With proper W/L scaling of FETs used in the current source transfer function of iDACs, 8-bits of accuracy or ±0.4% matching may be achievable. As such, this disclosure can utilize low resolution iDACs that occupy small areas and achieve higher accuracy P A ×Q A  multiplication at lower cost. 
     Tenth, the XD i I o  that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Eleventh, the XD i I o  that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating iDACs, which are symmetric, matched, and scaled. This trait facilitates devices parameters to track each other over process, temperature, and operating conditions variations. Accordingly, the XD i I o &#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Twelfth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents) regions. For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals 
     Section 6—Description of FIG.  6   
       FIG. 6  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that utilizes the floating iDAC method illustrated in  FIG. 1 . 
     The embodiment of floating iDAC illustrated in  FIG. 6  is similar to that of the floating iDAC embodiment disclosed and illustrated in section 2 and  FIG. 2 . The difference is a smaller iSW arrangement which simplifies the iDAC, reduces its size, and lowers its dynamic power consumption. Small size of iDAC is critical in machine learning and artificial intelligence applications that could require numerous iDACs for multiplication purposes. The iSW here is, for example, comprising of M 8   6  and M 7   6 , where in M 8   6  receives the digital bit D 3   6  whereas M 7   6 &#39;s gate terminal is biased at a fixed V 1   6 +V 3   6 . As such, the inverter (compared to, for example, U 1   2  in  FIG. 2 . Section 2) is eliminated which saves are and lowers transient power consumption when digital-inputs are updated. Note that, in this example, V 1   6 +V 3   6  can be programmed such that digital voltage swings at D 3   6  terminal properly turn M 8   6  on and off when D 3   6  bit toggles. Also, depending on cost-performance goals, M 13   6 , M 3   6 , and M 1   6  as well as the iSW&#39;s FET pairs (e.g., M 7   6 -M 8   6 , M 9   6 -M 10   6 , and M 11   6 -M 12   6 ) can be sized to optimize for FETs to operate at or near saturation with increased output impedance, which could improve performance of the current reference transfer function network. 
     In addition to some of the benefits of the floating iDAC method disclosed in section 2  FIG. 2 , the embodiment of  FIG. 6  illustrates another embodiment of floating iDAC with smaller size and lower dynamic power consumption. 
     SECTION 7—Description of FIG.  7   
       FIG. 7  is a simplified functional block diagram illustrating a factorized iDAC method. 
     As noted earlier, a DAC&#39;s input-to-output transfer function can be described as follow: 
                 A   o     =       (       A   r     /     2   i       )     ×       ∑     i   =   1     n     ⁢     [       D   i     ×     2     i   -   1         ]           ,         
where A o  is the DAC&#39;s analog output signal, A r  is the DAC&#39;s analog reference signal, D i  is the DAC&#39;s digital inputs signal that are n-bits wide. For example, for n=6, and A r =1 units which establishes A o &#39;s full scale value of 1 unit. For a ½ unit or half-scale of a 6-bit wide digital word corresponds to D i =100000 or D 6 =1, and D 5 =D 4 =D 3 =D 2 =D 1 =0, the DAC&#39;s input-to-output transfer function would be as follows: A o =(A r /2 6 )×[D 1 ×2 0 +D 2 ×2 1 +D 3 ×2 2 +D 4 ×2 3 +D 5 ×2 4 +D 6 ×2 5 ]=(A r /2 6 )×[0×2 0 +0×2 1 +0×2 2 +0×2 3 +0×2 4 +1×2 5 ]=(A r /2 6 )×[1×2 5 ]=A r /2=½ full-scale.
 
     Notice that the term (A r /2 6 ) carries the analog equivalent weight of a least significant bit (LSB) or A LSB , which is binarily weighted (up to 2 i-1  with 1&lt;i&lt;n=6 where i is an integer) to generate the DAC&#39;s A o  (that is proportional to the DAC&#39;s A r  and) in accordance with the DAC&#39;s D 1 . Here, let 2 i-1 =2 j ×2 k =w i ×f i  where w i  and f represent the factors of 2 i-1 , and where there can be found a pair of w i  and f factors whose sum is the smallest compared to w i ×f i . In other words, there can be found a pair of w i  and f i  where w i +f i &lt;&lt;w i ×f i . For example, for n=i=6→2 i-1 =2 5 =32=2 j ×2 k =2 3 ×2 2 =w 6 ×f 6 =16×2=8×4 where the sum of the pairs of factors here are the smallest compared to the multiplication of the pairs of factors (e.g., with j=2, k=3 or w 6 =8 and f 6 =4 for which 4+8&lt;&lt;8×4). 
     The factorized DAC method factorizes a respective binary DAC weights, which reduces the DAC&#39;s area and cost. The respective binary DAC weights (2 i-1 ) can be generated by feeding the respective binary DAC weight&#39;s factor (2 j =w i ) into its other factor (2 k =f i ) wherein 2 i-1 =2 j ×2 k =w i ×f i . Utilizing the factorized DAC method, the circuit area occupied by the respective binary DAC weight&#39;s factors (2 j =w i  and 2 k =f i  in aggregate) can be optimized to occupy a smaller area compared to that of the conventional respective binary DAC weights (2 i-1 ). 
     For example, a standard 6-bit iDAC is comprised of a plurality of binary scaled switching current source (cells) where each current source cell carries a current weight of A r /2 6  which is a Least-Significant-Bit or LSB. The current source cells are binarily and respectively scaled in parallel to arrange the standard iDAC&#39;s binary weighted current switching reference network. For example, the standard iDAC&#39;s Most-Significant-Bit (MSB) analog current portion is generated by placing in parallel 32 of LSB current source cells (A r /2 6 ) which generates 32×A r /2 6 =A r /2. Accordingly, the MSB of a 6-bit standard iDAC&#39;s switching current sources would occupy the size of 2 1-1 =2 5 =32 of LSB switching current source cells that are arranged in parallel. 
     In comparison, the disclosed factorized iDAC method generates the same 32×A r /2 6 =A r /2 or the MSB analog current portion with more area efficiently. The factorized iDAC method, feeds the output current of 2 j =2 3 =w 6 =8 parallel LSB current switches (where each current switch carries a current with the weight of an A LSB ) onto a current mirror with a gain of 2 k =2 2 =f 6 =4. The current mirrors can be arranged to have the same size as the factorized iDAC&#39;s LSB current source cells for matching purposes. As such, for the factorized iDAC method, the MSB analog current portion of 32×A r /2 6 =A r /2, while occupying an equivalent aggregate current switch area of 2 j +2 k =2 3 +2 2 =8+4=12 LSB current source cells. In comparison, and as noted earlier, an equivalent aggregate current source cell 2 5 =32 LSB current cells would be required for a standard iDAC. 
     Note that there is a trade-off between reducing the area achieved by utilizing the factorized DAC method, and reducing the accuracy of the DAC. For example, the mismatch attributed to current source cells that constitute w 6  (subordinate DAC weight) are multiplied with the mismatch attributed to the current source cells that constitute f 6 . (factorized scale), which lowers the accuracy of the overall DAC while reducing its size. 
     The area reduction benefit of the factorized DAC method can be extended for high resolution DACs comprising of plurality of factorized DACs. For example, a 6-bit DAC can be arranged by utilizing two factorized DACs (e.g., a 3-bit factorized Most-Significant-Portion of MPS DAC, and a 3-bit factorized Least-Significant-Portion or LSP DAC). Alternatively, a 6-bit DAC can be arranged by utilizing three factorized DACs (e.g., a 2-bit factorized top portion DAC, a 2-bit factorized middle portion DAC, and a 2-bit factorized bottom portion DAC). 
     As noted, earlier  FIG. 7  is a functional block diagram illustrating a DAC comprising of three factorized DACs, but the same factorized method is applicable for example to 2 or 4 (instead of 3) factorized DACs. 
     In  FIG. 7 , the digital inputs Di 7  that is i 7 -bit wide is applied to a logic block L 7  that arranges the digital input bits to three segments: First, a t 7 -bit wide top-portion-bits or Dt 7  word. Second, a m 7 -bit wide middle-portion-bits or Dm 7  word. And third, a b 7 -bit wide bottom-portion-bits or Db 7  word. 
     In  FIG. 7 &#39;s illustration of factorized DAC method, the digital input words Dt 7 , Dm 7 , and Db 7  are fed onto three binary weighted subordinated factorized DACs: a top-DAC (DACt 7 ), a middle-DAC (DACm 7 ), and a bottom-DAC (DACb 7 ), respectively. The three respective top, middle, and bottom DACs receive a top-analog-reference signal (tr 7 ), a middle-analog-reference signal (mr 7 ), and a bottom-analog-reference signal (br 7 ), respectively. Accordingly, the three respective top, middle, and bottom subordinated factorized DACs generate a top-weight analog output signal (At 7 ), a middle-weight analog output signal (Am 7 ), and a bottom-weight analog output signal (Ab 7 ), respectively. The At 7 , Am 7 , and Ab 7  are then gained up by top-factor scale (Ft 7 ), a middle-factor scale (Fm 7 ), and a bottom-factor scale (Fb 7 ) whose respective output products At 7 ×Ft 7 , Am 7 ×Fm 7 , and Ab 7 ×Fb 7  are summed by an analog block A 7  to generate a final factorized DAC analog output signal, Ao 7 . The three full-scale weights of At 7 , Am 7 , and Ab 7  can be programmed as a function of the ratio of the three reference analog signals tr 7 , mr 7 , and br 7 . Programming the middle-factor scale Fm 7 =1 as the base-factor, then Ft 7 =2 t     7   /(tr 7 /mr 7 ) relative to the base-factor, and Fb 7 =(½ m     7   )×(mr 7 /br 7 ) relative to the base-factor. 
     Consider that for practical purposes (without any DAC calibration or trimming): The three digital bits t 7 , m 7 , and b 7  can be more than 1-bit and less than 8-bit wide. The three factor scales Ft 7 , Fm 7 , and Fb 7  can be programmed to gains than zero and less than 16 (without calibration or trimming): The ratio of analog reference signals tr 7 /mr 7  and mr 7 /br 7  can be programmed to ratios more than zero and less than 16 (without calibration or trimming). 
     For example, let&#39;s arrange the three subordinated factorized DAC&#39;s digital-bits t 7 =m 7 =b 7 =2 bits each. Let&#39;s also program the three subordinated factorized DAC&#39;s reference analog signals substantially equally as tr 7 =mr 7 =br 7 =1w. Accordingly, the three factor scales are programmed according to: Ft 7 =2 m     7   /(tr 7 /mr 7 )=2 2 /(1)=4 and Fb 7 =(½ m     7   )×(mr 7 /br 7 )=(½ 2 )×(1)=1/4. Again, notice that the three full-scale weights of At 7 , Am 7 , and Ab 7  are programmed as a function of the ratio of the three reference analog signals tr 7 , mr 7 , and br 7 . 
     In an alternative example, arranging the three subordinated factorized DAC&#39;s digital-bits t 7 =m 7 =b 7 =2 bits each, and programming the three subordinated factorized DAC&#39;s reference analog signals as tr 7 =4w, mr 7 =2w, and br 7 =1w, then the three factors are programmed according to: Ft 7 =2 t     7   /(tr 7 /mr 7 )=2 2 /(4w/2w)=2 and Fb 7 =(½ m     7   )×(mr 7 /br 7 )=(½ 2 )×(2w/1w)=2. 
     It is of note that for a standard binary 6-bit DAC, a scale factor of 2 6-1 =32 LSB weights (32x) are needed to generate just the MSB signal as a multiple of the LSB weight. In comparison, for a 6-bit factorized DAC that is described in the above 2 examples, the largest scale factor is 4x to generate any bit, including the MSB. In the above 2 example, the largest scale factor is 4x in the three subordinate factorized DAC s (At 7 , Am 7 , and Ab 7  whose full-scale outputs are programmed with tr 7 /mr 7  and mr 7 /br 7  ratios) as well as in the factor blocks Ft 7 , Fm 7 , and Fb 7 . Accordingly, smaller scale factors result in smaller DAC area and as well as other benefits such as improved dynamic response, which will be described further in the following DAC circuit embodiments that utilize the factorized DAC method. 
     Section 8—Description of FIG.  8   
       FIG. 8  is a simplified circuit schematic diagram illustrating an embodiment of an iDAC that utilizes the factorized iDAC method described and illustrated in section 7  FIG. 7 . 
     In  FIG. 8 , the illustrated factorized iDAC is comprising of three subordinated factorized iDAC blocks DACt 8 , DACm 8 , and DACb 8  which are analogous to DACt 7 , DACm 7 , and DACb 7  of  FIG. 7 . Moreover, in  FIG. 8 , the three factor blocks Ft 8 , Fm 8 , and Fb 8  are analogous to Ft 7 , Fm 7 , and Fb 7  of  FIG. 7 . As noted earlier, the embodiment of the factorized DAC method is illustrated with combining three subordinated factorized iDACs (and their respective factor blocks) in  FIG. 8 . However, the factorized method is flexible in utilizing, for example, two or four subordinated factorized iDACs (and their respective factor blocks), depending on the end-application&#39;s feature-benefit-cost requirements. 
     In  FIG. 8 , the factorized iDAC&#39;s reference current source I 1   8  sets the gate-to-source voltage of M 7   8  which is scaled and mirrored onto M 1   8 -M 2   8 , M 3   8 -M 4   8 , and M 5   8 -M 6   8  which are a binary weighted current source networks, belonging to the three subordinated factorized iDACs: DACt 8 , DACm 8 , and DACb 8 , respectively. The digital word Di 7  in  FIG. 7  is analogous  FIG. 8 &#39;s Di b  digital word comprising of digital bits D 6   8 -D 5   8 -D 4   8 -D 3   8 -D 2   8 -D 1   8 . The digital words Dt 7 , Dm 7 , and Db 7  in  FIG. 7  are analogous to digital words D 6   8 -D 5   8 , D 4   8 -D 3   8 , and D 2   8 -D 1   8  of  FIG. 8 , respectively. Note that for clarity of illustration the factorized iDAC&#39;s resolution is arranged with 6-bit, but the resolution can be higher such as 16-bits. In  FIG. 7 , signals At 7 , Am 7 , and Ab 7  are analogous to current signals designated as At 8 , Am 8 , and Ab 8  in  FIG. 8 , which are the current output signals of subordinated factorized iDAC blocks DACt 8 , DACm 8 , and DACb 8 , respectively. In  FIG. 7 , designated signals Ft 7 ×At 7 , Fm 7 ×Am 7 , and Fb 7 ×Ab 7  are analogous to current signals designated as Ft 8 ×At 8 , Fm 8 ×Am 8 , and Fb 8 ×Ab 8  in  FIG. 8 , which are the current output signals of factor blocks Ft 8 , Fm 8 , and Fb 8 , respectively. In  FIG. 8 , current output signals of factor blocks Ft 8 , Fm 8 , and Fb 8  are coupled (summed) at node A 8 . As such the factorized iDAC output current signal is A 8 =Ft 8 ×At 8 +Fm 8 ×Am 8 +Fb 8 ×Ab 8 . 
     Given that the three subordinated factorized iDACs (i.e., DACt 8 , DACm 8 , and DACb 8 ) in  FIG. 8  are identical, only the subordinated factorized DACt 8 &#39;s operation is briefly described. Let the I 1   8 =w as the DACt 8 &#39;s reference analog current input signal, which is scaled and mirrored onto the subordinated factorized DACt 8 &#39;s current source network comprising of 4 18 =2w and I N2     8   =1w. Consider that M 1   8  and M 2   8  are cascaded by M 8   8  and M 9   8  (biased with V 1   8 ), respectively, to raise the current sources output impedance. The I N1     8   =I N8     8   =2w is coupled with a current switch comprising of M 15   8  and M 21   8 . The M 15   8  is biased at a fixed voltage V 2   8 +V 1   8  that can be biased at approximately (V DD +V SS )/2, which would enable M 15   8 , M 21   8  to switch I N8     8   =I N1     8    to two paths: When D 6   8  is in the low (V SS ) states, I N1     8    flows through M 15   8  (that is turned on) and onto M 27   8 . The aim of diode connected M 27   8  is to substantially equalize the drain terminal voltage of M 8   8  at roughly V DD −V GSpmos , while D 6   8  is toggled between high or low states, which improves the iDAC&#39;s dynamic response. Similarly, I N2     8   =I N9     8   =1w is coupled with a current switch comprising of M 16   8  and M 22   8 . Also, M 16   8  is biased at a fixed voltage V 2   8 +V 1   8 . When D 5   8  is in the high states, the I N2     8    flows through M 22   8  and again onto node At 8 . When D 5   8  is in the low states, the I N2     8    flows through M 16   8  and onto the diode connected M 27   8 , which again substantially equalizes the drain terminal voltage of M 8   8  at roughly V DD -V GSpmos , when D 5   8  is toggled between high or low states, which improves the iDAC&#39;s dynamic response. Notice that the full-scale current signal flowing through the node designated as A t8  is 2×I 1   8 +1×I 1   8 =3×I 1   8 =3w, which is the full-scale output current signal for subordinated factorized DACt 8 . 
     Similarly, the current signals through nodes designated as Am 8  and Ab 8  (which are generated by the subordinated factorized DACm 8  and DACb 8 , respectively) both have a full-scale current of 3w. Consider that tr 8 , mr 8 , and br 8  are the equivalent full-scale reference signal for the subordinated factorized DACt 8 , DACm 8  and DACb 8 , respectively, which are analogous to the terminology tr 7 , mr 7 , br 7  described in section 7,  FIG. 7 . Since the three subordinated factorized iDAC&#39;s reference analog signals (full-scale values) are arranged substantially equally (i.e., equivalent tr 8 =mr 8 =br 8 =3w), then the three other factor scales are programmed according to: Fm 8 =1 as base value, Ft 8 =2 t     8   /(tr 8 /mr 8 )=2 2 /(1)=4 and Fb 8 =(½ m     8   )×(mr 8 /br 8 )=(½ 2 )×(1)=¼, taking into consideration that DACt 8  is a 2-bit DAC (t 8 =2) and DACm 8  is a 2-bit DAC (m 8 =2). 
     Accordingly, the full-scale value of the factorized iDAC which is A 8 =Ft 8 ×At 8 +Fm 8 ×Am 8 +Fb 8 ×Ab 8 =4×3w+1×3w+¼×3w=w×15¾. Given that I 1   8 =w, the full-scale value of A 8  can be adjusted in accordance with w×15¾ (from nano amperes to milliamperes scales) depending on the applications requirements. 
     As noted earlier, the accuracy of the factorized DAC is dominated by matching of components in the signal path of the most significant bits (MSB). As such, design and FET layout care can help the matching between M 1   8 -M 2   8  in the subordinated factorized DACt 8  block and matching between M 34   8 -M 35   8  in the Ft 8  block which arrange the factorized iDAC&#39;s MSB and dominate the accuracy of the overall factorized DAC. Moreover, subordinated factorized DACt 8  can be arranged in a segmented fashion (disclosed next in section 9,  FIG. 9 ) to improve accuracy and reduce the glitch. 
     Also, it would obvious to one skilled in the art to further reduce the size and cost of  FIG. 8 &#39;s circuit by eliminating the cascoded FETs M 28   8  to M 33   8  as well as M 8   8  to M 14   8  in applications where low power supplies with low V DD  variations are available, and or low cost calibration (trimming) is available to adjust gain error and full-scale. 
     The benefits of factorized DAC, including that of factorized iDAC are summarized below: 
     First, factorized iDAC is smaller than standard iDACs, and here is how: A standard binary weighted iDAC&#39;s current source network (as part of the iDAC&#39;s input-to-output transfer function network) is comprising of scaled current sources as follows: the MSB current source sized at 2 5 x=32x scaled through (2 4 x=16x, 2 3 x=8x, 2 2 x=4x, 2 1 x=2x) to the LSB current source cell sized at 2 0 x=1x, where x is an equivalent current source cell that carries an LSB current weight. As such, for a standard 6-bit iDAC, about 63x current sources are required. 
     In comparison (setting aside the cascoded FETs and current switches), a factorized iDAC illustrated in  FIG. 8  would require: 2x+1x, 2x+1x, 2x+1x current source cells for the three subordinated factorized iDACs (DACt 8 , DACm 8 , and DACb 8 ) plus 4x+1x, 1x+1x, 1x+4x (equivalent size x current source cell) for the three current mirrors in factor blocks (Ft 8 , Fm 8 , and Fb 8 ). As such, for a 6-bit iDAC utilizing the factorized DAC method, 21x equivalent current source cells are required, which is about 3 times smaller than a conventional iDAC. 
     For higher resolution DACs, the factorized DAC method is even more area efficient. 
     Second, dynamic response is faster than conventional iDACs because factorized DACs smaller sized input-to-output transfer function network utilizes smaller FETs with smaller capacitances, which can be charged and discharged faster. 
     Third, glitch is lower during code transitions compared to standard DACs, again because factorized DACs smaller input-to-output transfer function network utilizes smaller devices that carry smaller capacitances, which inject fewer analog glitches to the output of the DAC during digital input code transitions. 
     Fourth, dynamic power consumption is lower because a factorized DAC&#39;s smaller sized FETs (in the input-to-output transfer function network) would consume less dynamic current to drive smaller devices during digital input code transitions. 
     Fifth, utilizing the factorized DAC method in a current-mode DAC (iDAC) is inherently fast. 
     Sixth, factorized iDAC can operate with low power supply since its operating headroom can be limited by a FET&#39;s VGS+VDS. 
     Seventh, utilizing the factorized iDACs in subthreshold region can further reduce power consumption and lower power supply voltage. 
     Eight, factorized iDAC can be programmed for a non-linear (e.g., logarithmic or square) input-to-output transfer function. 
     Ninth, running the CMOSFETs in subthreshold enables the factorized iDAC to operate with ultra-low currents, low power supply, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that require numerous ultra-low power and low power supply DACs for computation. 
     Tenth, neither any capacitors nor any resistors are needed, which facilitates fabricating the factorized iDAC in standard digital CMOS manufacturing factory that is low cost, main-stream and readily available for high-volume mass production applications, and proven for being rugged and having high quality. 
     Eleventh, factorized iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Twelfth, factorized iDAC can utilize same type of MOSFET current sources and MOSFET switches that are symmetric, matched, and scaled. This trait facilitates devices parameters to track each other over process, temperature, and operating condition variations. Accordingly, the iDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Thirteenth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents). For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals. 
     Section 9—Description of FIG.  9   
       FIG. 9  is a simplified circuit schematic diagram illustrating another embodiment of an iDAC that combines the factorized and floating iDAC methods described in sections 7 and 1, and illustrated  FIGS. 7 and 1 , respectively. 
     The three subordinated iDACs in  FIG. 9  utilize a combination of both the factorized DAC method and the floating iDAC methods. Also, the top subordinate DACt 9  utilizes floating iDAC method as well as segmentation to improve accuracy and reduce glitch associated with digital input code transitions. 
     In  FIG. 9  illustration, the factorized floating iDAC is comprising of three factorized floating subordinated iDACs depicted in blocks DACt 9 , DACm 9 , and DACb 9  (which are analogous to DACt 8 , DACm 8 , and DACb 8  of  FIG. 8 ). The factor blocks Ft 9 , Fm 9 , and Fb 9  are analogous to Ft 8 , Fm 8 , and Fb 8  of  FIG. 8 . Notice that the digital input word Di 8  comprising of the digital bits D 6   8  to D 1   8  in  FIG. 8  are analogous to the factorized floating iDAC&#39;s digital input word Di 9  comprising of the digital bits D 6   9  to D 1   9  of  FIG. 9 , respectively. Again, bear in mind that for clarity of illustration the main factorized floating iDAC in  FIG. 9  is arranged with 6-bit of resolution (comprising of the three 2-bit factorized floating subordinated iDACs: DACt 9 , DACm 9 , and DACb 9 ) but the factorized floating iDAC resolution can be higher, such as 16-bit. Also, it would be obvious to one skilled in the art that iDACs can be arranged with less than three factorized floating subordinated iDACs (e.g., two) or more than three (e.g., four or five). 
     The factorized floating iDAC&#39;s reference current source I 1   9  sets the gate-to-source voltage of M 4   9  which is scaled and mirrored onto M 1   9 , M 2   9 , and M 3   9  which program the full-scale weights of the three factorized floating subordinated iDACs: DACt 9 , DACm 9 , and DACb 9 , respectively. Also notice that signals At 8 , Am 8 , and Ab 8  in  FIG. 8  are analogous to current signals designated as At 9 , Am 9 , and Ab 9  in  FIG. 9  which are the current output signals of the three subordinated iDAC blocks DACt 9 , DACm 9 , and DACb 9 , respectively. In  FIG. 8 , designated signals Ft 8 ×At 8 , Fm 8 ×Am 8 , and Fb 8 ×Ab 8  analogous to current signals designated as Ft 9 ×At 9 , Fm 9 ×Am 9 , and Fb 9 ×Ab 9  in  FIG. 9 , which are the current output signals of factor blocks Ft 9 , Fm 9 , and Fb 9 , respectively. In  FIG. 9 , current output signals of factor blocks designated as Ft 9 , Fm 9 , and Fb 9  are coupled (summed) at node A 9 . As such the factorized floating iDAC output current signal is A 9 =Ft 9 ×At 9 +Fm 9 ×Am 9 +Fb 9 ×Ab 9 . 
     As noted earlier, the three factorized floating subordinated iDACs in  FIG. 9  utilize a combination of both the factorized DAC method (described in section 7,  FIG. 7 ), and the floating iDAC method (described in section 1,  FIG. 1 ). In  FIG. 9 , a central reference current I 1   9 =w flows through M 4   9  that is sized at 1x, which programs I M4     9   =w that is mirrored and scaled onto: M 1   9  sized at 4x with I M1     9   =4×w, M 2   9  sized at 2x with I M1     9   =2×w, and M 3   9  sized at 1x with I M1     9   =1×w. Consider that I M1     9   , I M2     9   , and I M3     9    are the reference analog signals tr 9 =4w, mr 9 =2w, and br 9 =1w (analogous to the terminology tr 7 , mr 7 , br 7  described in section 7,  FIG. 7 ) that are applied to the factorized floating subordinated DACt 9 , DACm 9  and DACb 9 , respectively, which also set the said three factorized floating subordinated iDAC&#39;s full-scale current output signals through nodes designated as At 9 , Am 9  and Ab 9 , respectively. As such, the three factor scales are programmed according to: For Fm 9 =1 as base factor scale, Ft 9 =2 t     9   /(tr 9 /mr 9 )=2 2 /(2)=2 and Fb 9 =(½ m     9   )×(mr 9 /br 9 )=(½ 2 )×(2)=½, also considering that DACt 9  is a 2-bit iDAC (t 9 =2) and DACm 9  is a 2-bit iDAC (m 9 =2). 
     Accordingly, the full-scale value of the factorized floating iDAC output is A 9 =Ft 9 ×At 9 +FM 9 ×AM 9 +Fb 9 ×Ab 9 =2×4w+1×2w+½×1w=w×10½. Given that I 1   9 =w, the full-scale value of A 9  output signal can be adjusted (from nano amperes to milliamperes scales) depending on the applications requirements. 
     Notice that V 1   9  biases the floating current sources M 5   9  to M 11   9 . For applications where high-accuracy and higher iDAC output currents may be required, instead of one voltage source such as V 1   9 , up to three voltage sources can be utilized: such as one for each group of floating current sources M 5   9  to M 7   9 , one for M 4   9  to M 5   9 , and one for M 10   9  to M 12   9 . In doing so, the V DS  or drain-to-source voltages of M 1   9  to M 4   9  would match which reduces scaled second order systematic error due V DS  mismatch between M 1   9  to M 4   9  currents. The current switches S 1   9  to S 7   9  (when in their off states) are terminated onto a diode connected M 13   9  which is a VGS PMOS  below V DD  that roughly matches (to first order) the VGS PMOS  of diode connected M 20   9 , M 22   9 , and M 24   9 . As such, the transient and dynamic performance of the iDAC is improved since the drain terminal of FETs M 5   9  to M 11   9  are roughly balanced at V DD -VGS PMOS  as the iDAC&#39;s codes toggle between on and off states. 
     Additionally, DACt 9  is arranged with segmentation to improve accuracy since DACt 9  carries the analog weight of the first 2 most significant bits. Here, D 6   9  and D 5   9  are fed to a 2-to-3 bit encoder (comprising of AND 1   9  and OR 1   9 ) whose digital outputs control the DACt 9 &#39;s current switches. As such, the DACt 9 &#39;s substantially equal current source segments (I M5     9   , I M6     9   , and I M7     9   ) are turned on-or-off one at a time (e.g., thermometer fashion), which improves accuracy and lowers the digital input code to analog output glitching. As noted earlier, the motivation for segmenting the MSB (as noted earlier) is that the accuracy of the factorized DAC is dominated by the MSB input-to-output transfer function network. 
     Excluding the cascoded current mirrors and current switches, the disclosed 6-bit iDAC in  FIG. 9  occupies the equivalent area of about 24x current source cells, compared to that of a standard iDAC requiring about 63x current source cells, where x is an equivalent current source cell that carries an LSB current weight. In summary, some of the benefits of the factorized floating iDAC embodiment illustrated in  FIG. 9  includes some of the benefits of the floating iDAC described in section 2,  FIG. 2 , in addition to some of the benefits of the factorized iDAC described in section 8,  FIG. 8 . Moreover, arranging the MSB factorized iDAC (DACt 9 ) in a segmented manner has the benefit of improved accuracy as well as lowering the iDAC&#39;s glitch. 
     Section 10—Description of FIG.  10   
       FIG. 10  is a simplified circuit schematic diagram illustrating another embodiment of another iDAC that utilizes the factorized and floating DAC methods described in sections 7 and 1, and illustrated  FIGS. 7 and 1 , respectively. 
     The two subordinated iDACs in  FIG. 10  utilize a combination of both the factorized DAC method and the floating iDAC methods. The DACt 10 , utilizes conventional 2-bit iDAC that is segmented for improve accuracy and lower glitch associated with the first 2 MSBs code transitions. 
     In  FIG. 10 , the illustrated factorized floating iDAC is comprising of two subordinated iDACs illustrated in blocks DACt 10  (subordinated segmented factorized iDAC) and DACb 10  (subordinated factorized floating iDAC) that operate in conjunction with the factor blocks Ft 10 , and Fb 10 . The iDAC&#39;s digital input word Di 10  comprising of the digital bits D 1   10  to D 6   10 , respectively. Again, bear in mind that for clarity of illustration the overall factorized floating iDAC in  FIG. 10  is arranged with 6-bit of resolution (comprising of DACt 10  that is a subordinated 2-bit segmented factorized iDACs, and the factorized floating 4-bit DACb 10 ) but overall resolution of the factorized floating iDAC can be higher, such as 16-bit. 
     In  FIG. 10 , signals At 10  and Ab 10  depict the current output signals of the two subordinated iDAC blocks DACt 10  and DACb 10 , respectively. Current signals designated as At 10 ×Ft 10  and Ab 10 ×Fb 10  are the current output signals of factor blocks Ft 10  and Fb 10 , respectively. In  FIG. 10 , current output signals of factor block Ft 10  and Fb 10  are coupled (summed) at node A 10 . As such, in  FIG. 10 , the factorized floating iDAC output current signal is A 10 =Ft 10 ×At 10 +Fb 10 ×Ab 10 . 
     The iDAC&#39;s reference current source in  FIG. 10  is I 1   10  which programs the gate-to-source voltage of M 6   10  that is scaled and mirrored onto M 1   10 , M 2   10 , and M 3   10 , which together program the full-scale weights of DACt 10 . Moreover, the gate-to-source voltage of M 6   10  is mirrored onto M 4   10 , and M 5   10 , which together program the full-scale weight of DACb 10 . Note that the drain current of M 5   10  that is I M5     10   , supplies the floating current to the floating section of the DACb 10  comprising of M 11   10 , M 12   10 , M 13   10 , and M 14   10 , which are binary scaled at 4x, 2x, 1x, and 1x, respectively. Let&#39;s set I 1   10 =w, then I M4     10   =I M5     10   =I M6     10   =I 1   10 =I M10     10   =W, I M11     10   =w/2, I M12     10   /4=W/4, I M13     10   =w/8, and I M14     10   =w/8. Also, M 1   10 , M 2   10 , and M 3   10  sized at 1x with I M1     10   =I M2     10   =I M3     10   =I M6     9   =1×w. Accordingly, the full scale value of At 10  which is the output current for DACt 10  is then 3w that also represents tr 10 . The full scale value of Ab 10  which is the output current for DACb 10  is 2w that also represents br 10 . Since there are only a top iDAC (DACt 10 ) and a bottom iDAC(DACb 10 ), the programming of factor values are more straight forward: The LSB weight of DACt 10  is w and the LSB weight of DACb 10  is w/8, which makes their ratio=8. Considering that DACt 10  is a 2-bit iDAC (t 10 =2), then 2 t     10   =4, which computes to 4/8=½ or Ft 10 =1 and Fb 10 =½ for current mirrors with the smallest FET ratio. Accordingly, the full-scale value of the factorized iDAC output A 10 =Ft 10 ×At 10 +Fb 10 ×Ab 10 =1×3w+½×2w=w×4. Given that I 1   10 =w, the full-scale value of A 10  output signal can be adjusted (from nano-amperes to milli-amperes scales) depending on the applications requirements. 
     Notice that V 1   10  and V 2   10  bias the floating current sources M 7   10  to M 9   10  of DACt 10 , and M 10   10  to M 14   10  of DACb 10 , respectively. By having separate V 1   10  and V 2   10 , the V DS  or drain-to-source voltages of M 7   10  to M 14   10  would match better which reduces (scaled) second order systematic error (due to drain-to-source or FET&#39;s V DS  mismatch) between M 1   10  to M 5   10  currents. Also, as stated in the prior section, the iDAC&#39;s current switches (iSWs) S 1   10  to S 7   10 , in their off states, are terminated onto a diode connected M 15   10  which is a VGS PMOS  (below V DD ) that roughly matches the VGS PMOS  of diode connected M 20   10  and M 22   10 . As such, the transient and dynamic performance of the factorized floating iDAC is improved since the drain terminal of FETs M 7   10  to M 13   10  are roughly balanced at V DD -VGS PMOS  as the iDAC&#39;s codes toggle between on and off states. 
     Additionally, DACt 10  is arranged with segmentation to improve accuracy. The two upper MSBs, D 6   10  and D 5   10  are fed to a 2-to-3 bit encoder (comprising of AND 1   10  and OR 1   10 ) whose digital output control the DACt 10 &#39;s switches. As such, the DACt 10 &#39;s substantially equal current source segments (I M1     10   , I M2     10   , and I M3     10   ) turn on-or-off one at a time (e.g., in a thermometer fashion), which improves accuracy and lowers digital input code to analog output glitching. As stated earlier, the motivation for segmenting the MSB (as noted earlier) is that the accuracy of the factorized DAC is dominated by the accuracy of the MSB signal path. 
     Excluding the cascoded current mirrors and current switches, the disclosed 6-bit iDAC in  FIG. 10  occupies the equivalent area of about 18x current source cells, compared to that of a conventional iDAC requiring about 63x current source cells, where x is an equivalent current source cell that carries an LSB current weight. In summary, some of the benefits of the factorized floating iDAC embodiment illustrated in  FIG. 10  includes some of the benefits of the floating iDAC described in section 2,  FIG. 2 , in addition to some of the benefits of the factorized iDAC described in section 8,  FIG. 8 . Moreover, arranging the MSB factorized iDAC (DACt 10 ) in a segmented manner has the benefit of improved accuracy as well as lowering the iDAC&#39;s glitch. 
     Section 11—Description of FIG.  11   
       FIG. 11  is a simplified circuit schematic diagram illustrating an embodiment of a mixed-signal current-mode digital-input to analog-output multiplier (XD i I o ) comprising of a first iDAC whose output supplies the reference input to a second iDACs, wherein the first and second iDACs utilize the factorized and floating DAC methods illustrated  FIG. 7 , and  FIG. 1 , respectively. 
     As noted earlier, a simplified transfer function for an iDAC is: 
                 I   o     =         I   R     ⁢       ∑     i   =   1     k     ⁢       D   i     /     2   i           =         (       I   R     /     2   k       )     ⁢       ∑     i   =   1     k     ⁢       D   i     ×     2     i   -   1             =       Δ   R     ⁢       ∑     i   =   1     k     ⁢       D   i     ×     2     i   -   1                   ,         
where for the iDAC, I o  is the analog output current, I R  is the reference input current that can set the full-scale value of I o , D i  is the digital input word (that is k-bits wide), and Δ R =(I R /2 k ) represents an analog LSB current weight for I o . For example, for a 6-bit iDAC, k=6, and full scale value of I o  set to substantially equal I R =64 nA, then LSB of the iDAC which is Δ R =(I R /2 k )=Δ R =(64 nA/2 6 )=1 nA.
 
     A simplified transfer function of a multiplier XD i I o  where a Y-iDAC&#39;s output supplies the reference input to a second X-iDAC is as follows: For the 
               Y   ⁢     -     ⁢   iDAC   ⁢           ⁢     I   oy       =         I   Ry     ⁢       ∑     y   =   1     m     ⁢       D   y     /     2   y           =         (       I   Ry     /     2   m       )     ×       ∑     y   =   1     m     ⁢       D   y     ×     2     y   -   1             =       Δ   Ry     ×       ∑     y   =   1     m     ⁢       D   y     ×     2     y   -   1                       
where the analog output current is I oy , the reference input current is I Ry  which can set the full-scale value of I oy , the digital input word (that is m-bits) wide is D y , and Δ Ry =(I Ry /2 m ) represents an analog LSB current weight of I oy .
 
     Similarly, for the 
               X   ⁢     -     ⁢   iDAC   ⁢           ⁢     I   ox       =         I   Rx     ⁢       ∑     x   =   1     n     ⁢       D   x     /     2   x           =         (       I   Rx     /     2   n       )     ×       ∑     x   =   1     n     ⁢       D   x     ×     2     x   -   1             =       Δ   Rx     ×       ∑     x   =   1     n     ⁢       D   x     ×     2     x   -   1                       
where the analog output current is I ox  the reference input current is I Rx  which can set the full-scale value of I ox  the digital input word (that is n-bits) wide is D x , and Δ Rx =(I Rx /2 n ) is an analog LSB current weight of I ox .
 
     By feeding the output current of Y-iDAC onto the reference input of the X-iDAC, where 
                 I   Rx     =       I   oy     =       I   Ry     ⁢       ∑     y   =   1     m     ⁢       D   y     /     2   y               ,         
the following transfer function is realized:
 
               I   ox     =       (       I   Ry     ⁢       ∑     y   =   1     m     ⁢       D   y     /     2   y           )     ×       (       ∑     x   =   1     n     ⁢       D   x     /     2   x         )     .             
As such a digital-input to analog-current-output multiplier XD i I o  is realized where
 
     
       
         
           
             
               
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                       = 
                       1 
                     
                     m 
                   
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                       D 
                       y 
                     
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                       2 
                       y 
                     
                   
                 
                 ) 
               
               × 
               
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                       = 
                       1 
                     
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                       D 
                       x 
                     
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                       2 
                       x 
                     
                   
                 
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             = 
             
               
                 I 
                 ox 
               
               / 
               
                 
                   I 
                   Ry 
                 
                 . 
               
             
           
         
       
     
     On the right hand-side of  FIG. 11 , the Y digital-input Dy 11  (that is m-bits wide where m=6 for illustrative clarity) is applied to a Y-iDAC, whose analog current output is Ay 11 =I oY . The Y-iDAC utilizes a combination of floating and factorizing DAC methods, and it is comprised of top, middle, and bottom iDACs and Factor blocks: DAC ty     11   &amp; F ty     11   , DAC my     11    &amp; F my     11   , and DAC by     11   &amp; F by     11   . In  FIG. 11 , for example, the upper half of DAC my     11   &amp; F my     11    block is comprising of the Factor function F my     11   , and the lower half of DAC ty     11   &amp; F ty     11    block is comprising of the subordinated iDAC function DAC my     11   , and so on. For Y-iDAC, a reference current I 1   11  is mirrored by M 8   11  onto M 7   11  which supplies the reference current (via the floating DAC method) onto the three 2-bit subordinated factorized floating iDACs: DAC ty     11    (comprising of M 15     11   -M 16   11 ), DAC my     11    (comprising of M 17   11 -M 18   11 ), and DAC by     11    (comprising of M 19   11 -M 20   11 ). The digital word Dy 11  (that is m=6 bits wide) is applied to the respective Y-iDAC current switches S 7   11  through S 12   11 . The Y-iDAC utilizes NMOSFETs for its three 2-bit subordinated factorized floating iDACs sub-blocks (DAC ty     11   , DAC my     11   , and DAC by     11   ) whose output are fed onto diode-connected PMOSFETs M 33   11 , M 35   11 , and M 37   11 , respectively, which are the inputs of its three Factor sub-blocks (F ty     11   , F my     11   , and F by     11   ), respectively. Similar to the  FIG. 8  in section 8, for illustrative clarity m=6 in  FIG. 11  (but m can be as high as 16-bits), and also similarly the factor values for F ty     11   , F my     11   , and F by     11    (current mirrors) are 4x, 1x, and ¼x, respectively. 
     Also, note for example, when bit D 1   y   11  (the MSB of Y-iDAC, in this case) is off, then the off S 7   11  couples the drain-terminal of M 15   11  (i.e., I M15     11   ) to a bias-voltage (V GS     P    that is a PMOS gate-to-source voltage below V DD , which is not shown for illustrative clarity). The bias-voltage V GS     P    biases the current switches S 7   11  through S 12   11 , in a similar arrangement (and in this respect, similar to the iDAC&#39;s switch arrangement illustrated in  FIGS. 8, 9, and 10 ) when the current switches are in off states. 
     Consider that diode connected NMOS M 21   11  are scaled and biased via I 2   11  (to generate a Vg M21     11   ) such that M 1   11  to M 7   11  have enough drain-to-source voltage head-room to remain in saturation, considering gate-to-source voltage drop of M 9   11  through M 20   11 . Similarly, diode connected PMOS M 32   11  are scaled and biased via I 2   11  (to generate a Vg M32     11   ) such that M 33   11  to M 38   11  have enough drain-to-source voltage head-room to remain is saturation, considering gate-to-source voltage drop of M 23   11  through M 31   11 . 
     The output of the Y-iDAC that is Ay 11 =I oy  supplies the reference current (via the floating DAC method) onto X-iDAC which is described next. 
     On the left hand-side of  FIG. 11 , the X digital-input Dx 11  (that is n-bits wide where n=6 for illustrative clarity) is applied to a X-iDAC, whose analog current output is Ay 11 ×Ax 11 =I ox . The X-iDAC is the complementary version of Y-iDAC described earlier, and it utilizes a combination of floating and factorizing DAC methods, and it is comprised of top, middle, and bottom iDACs and Factor blocks: DAC tx     11   &amp; F tx     11   , DAC mx     11   &amp; F mx     11   , and DAC bx     11   &amp; F x . In  FIG. 11 , for example, the upper half of DAC mx     11   &amp; F mx     11    block is comprising of the Factor function F mx     11   , and the lower-half of DAC tx     11   &amp; F tx     11    is comprising of the subordinated DAC mx     11   , and so on. The output of Y-iDAC or Ay 11 =I oy  supplies the reference current onto X-iDAC&#39;s three of 2-bit factorized floating subordinate iDACs: DAC tx     11    (comprising of M 23   11 -M 24   11 ), DAC mx     11    (comprising of M 25   11 -M 26   11 ), and DAC bx     11    (comprising of M 27   11 -M 28   11 ). The digital word Dx 11  (that is also m=n=6 bits wide) is applied to the respective X-iDAC current switches S 1   11  through S 6   11 . The X-iDAC utilizes PMOSFETs for its three 2-bit DAC tx     11   , DAC mx     11   , and DAC bx     11    whose output are fed onto diode-connected NMOSFETs M 1   11 , M 3   11 , and M 5   11 , respectively, which are the inputs of its three Factor blocks F tx     11   , F mx     11   , and F bx     11   , respectively. Similar to the  FIG. 8  in section 8, for illustrative clarity n=6 in  FIG. 11  (but n can be as high as 16-bits), and also similarly the factor scales or values for F tx     11   , F mx     11   , and F bx     11    (current mirrors) are 4x, 1x, and ¼x, respectively. 
     Also, note for example, when bit D 1   x   11  (the MSB of X-iDAC, in this case) is off, then the off S 1   11  couples the drain-terminal of M 23   11  (i.e., I M23     11   ) to a bias-voltage (V GS     N   ) that is a NMOS gate-to-source voltage above V SS . The bias-voltage (V GS     N   ) is not shown for clarity of illustration, but V GS     N    biases the current switches S 1   11  through S 6   11 , in a similar arrangement (and in this respect, similar to the iDAC&#39;s switch arrangement illustrated in  FIGS. 8,9, and 10 ) when the current switches are in off states. 
     Accordingly, a digital-input to analog-current-output multiplier XD i I o  is realized where 
                   (       ∑     y   =   1     m     ⁢       D   y     /     2   y         )     ×     (       ∑     x   =   1     n     ⁢       D   x     /     2   x         )       =       I     o   ⁢   x       /     I     R   ⁢   y           ,         
where m=n=6, and Ay 11 ×Ax 11 =I ox  which is the analog representation of multiplying two digital codes D y =Dy 11  and D x =Dx 11 . Bear in mind that I Ry  represents a reference weight for the multiplier XD i I o  which is a scaled multiple (g) of I 1   11 . For example, if I 1   11 =i for Y-iDAC, then the full scale output current for each of sub-iDAC blocks DAC ty     11   , DAC my     11   , and DAC by     11    would be
 
                 i   9     ⁢     (       1   ⁢   x     +     2   ⁢   x       )       =     i   /   3           
which is factored by 4x, 1x, and x/4 by its respective blocks F ty     11   , F my     11   , and F by     11   . Consider that x=1 is programmed as the base factor scale in current mirrors of the subordinate iDAC and Factor blocks. Accordingly, Y-iDAC&#39;s full scale output value of
 
                 A     y   ⁢   1   ⁢   1       ⁢           ⁢   is   ⁢           ⁢     i   3     ×     (       4   ⁢   x     +     1   ⁢   x     +     x   4       )       =     i   ×     5.25   /   3.             
Similarly, for the X-iDAC, the full scale output current for each of subordinated iDAC blocks DAC tx     11   , DAC mx     11   , and DAC bx     11    would be
 
                     A     y   ⁢   1   ⁢   1       9     ⁢     (       1   ⁢   x     +     2   ⁢   x       )       =       A     y   ⁢   1   ⁢   1       /   3       ,         
which is also factored by 4x, 1x, and x/4 by its respective factor blocks F tx     11   , F mx     11   , and F bx     11   . As noted earlier, the output of Y-iDAC, which is A y11  that is fed onto X-iDAC for its reference current signal. Therefore, X-iDAC&#39;s full scale output value of
 
                   A     y   ⁢   1   ⁢   1       ×     A     x   ⁢   1   ⁢   1         =           A     y   ⁢   1   ⁢   1       3     ×     (       4   ⁢   x     +     1   ⁢   x     +     x   4       )       =         A     y   ⁢   1   ⁢   1       ×         5   .   2     ⁢   5     3       =       i   ×         5   .   2     ⁢   5     3     ×       5   ⁢   2   ⁢   5     3       =     i   ×       (     5.25   3     )     2               ,         
where
 
               g   =       (         5   .   2     ⁢   5     3     )     2       .         
As such,
 
               I     R   ⁢   y       =       i   ×   g     =       I   ⁢           ⁢     1     1   ⁢   1       ×   g     =     I   ⁢           ⁢     1     1   ⁢   1       ×       (     5.25   3     )     2                 
represents the reference weight for the multiplier XD i I o .
 
     In summary some of the benefits of the XD i I o  utilizing the factorizing iDAC method are as follows: 
     First, the XD i I o  utilizing the factorizing iDAC (described in section 8 of  FIG. 8 ) saves area and helps reduce FET sizes which saves die are, lowers cost, and also lowers the capacitance that can be charged and discharged faster in the iDAC&#39;s current reference network which in turn improve the transient response of the XD i I o . 
     Second, the XD i I o  operating in current-mode, which inherently runs fast. 
     Third, voltage swings in current-mode signal processing are small, which enables operating the XD i I o  with lower power supply voltage. Also, factorized iDAC utilized in XD i I o  can operate with low power supply since its operating headroom can be limited by a FET&#39;s VGS+VDS. 
     Fourth, operating at low supply voltage reduces power consumption of the XD i I o . Moreover, Running the CMOSFETs in subthreshold enables the factorized iDAC used in the in XD i I o  to operate with ultra-low currents, low power supply, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that require numerous XD i I o  that are ultra-low power and operate on low power supply for computation. 
     Fifth, by substantially equalizing the terminal voltages at the positive and negative current output of the factorizing iDAC would improve the transient response of the disclosed XD i I o  and reduces glitch. 
     Sixth, the XD i I o  needs neither any capacitors nor any resistors, which facilitates fabricating the XD i I o  in standard digital CMOS manufacturing factory that is low cost, main-stream and readily available for high-volume mass production applications, and proven for being rugged and having high quality. 
     Seventh, the precision of the iDAC and hence that of the XD i I o  multiplier can be improved by for example utilizing proper sized FETs in the iDAC&#39;s current reference network or by utilizing current source segmentation (along with digital binary-to-thermometer coding) in the iDAC&#39;s reference current transfer-function network. 
     Eighth, the XD i I o  multiplier can lower resolution factorized iDACs (e.g., 3-bits or 5-bits) that occupy smaller areas, but have higher accuracy (e.g., 8-bits of accuracy or 0.4%) which is beneficial for cost-performance. For example, higher than 3 of 5 bits of accuracy is attainable in standard CMOS fabrication. With proper W/L scaling of FETs used in the current source transfer-function of iDACs (8-bits of accuracy or), a ±0.4% matching that can be achievable. As such, this disclosure can utilize low resolution iDACs that occupy small areas and achieve higher accuracy multiplication at lower cost. 
     Ninth, glitch is lower during code transitions in XD i I o  multiplier because factorized iDACs utilized in XD i I o  are smaller given that the input-to-output transfer function network utilizes smaller devices that carry smaller capacitances, which inject fewer analog glitches to the output of the XD i I o  during digital input code transitions. 
     Tenth, dynamic power consumption is lower because the XD i I o  multiplier utilizes factorized DAC that have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Eleventh, the XD i I o  that utilizes factorized iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Twelfth, The XD i I o  that utilizes same type of MOSFET current sources and MOSFET switches in the respective factorized iDACs, which are symmetric, matched, and scaled. This trait facilitates device parameters to track each other over process, temperature, and operating conditions variations. Accordingly, the XD i I o &#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Thirteenth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents). For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals 
     Section 12A &amp; 12B—Description of FIG.  12 A &amp; FIG.  12 B 
       FIG. 12 , including  FIG. 12A  and  FIG. 12B , is a (Simulation Program with Integrated Circuits Emphasis) SPICE circuit simulation showing the input-output and linearity waveforms of the mixed-signal current-mode digital-input to analog-current-output multiplier (XD i I o ) that is illustrated in  FIG. 11 . 
     For the simulations of  FIG. 12A  and  FIG. 12B , the digital signals D y =Dy 11 =Y and D x =Dx 11 =X are spanned from full-scale to zero-scale (shown 1 as full-scale to 0 as zero-scale on the vertical axis) when both X, Y signals are ramped together in time from full-scale to zero-scale over 1 milli-second (shown on the horizontal axis). For the simulations of  FIG. 12B , for clarity of illustration, D y  and D y  are fed onto ideal iDACs and plotted as ‘D y  Analog Equivalent Signal’ and ‘ D x  Analog Equivalent Signal’ that are displayed next to A y11 ×A x11 =Y·X which is the resultant representation of analog output of the multiplier XD i I o .  FIG. 12A  illustrates  10  runs of montecarlo (MC) simulation plotting the difference between an ideal A y11 ×A x11  and MC simulation of the transistor level circuit of  FIG. 11  that generates A y11 ×A x11 .  FIG. 12B  indicates the linearity of the multiplier XD i I o . 
     The FETs in the iDAC and Factor blocks operate in the subthreshold region where most of the mismatch between FETs is due to their threshold voltage (V TH0 ) mismatch. In simulating of  FIG. 11 &#39;s circuit using SPICE, wherein the simulations are depicted in  FIG. 12A  and  FIG. 12B , the V TH0  statistical distribution for FETs is programmed as STAT CMOS V TH0  GAUSS 0.4%+3-3 cc=0.998, which indicated maximum I DS  mismatch of ˜±0.8% (for the 10 MC runs) between two arbitrary FETs (with the same W/L as that of non-digital FETs in the iDAC and Factor blocks). The 10 MC simulation runs in  FIG. 12A , captured a maximum DNL of about ˜±0.3% (and a gain-error of about ˜±0.8% which is mostly due to the reference current mirror mismatch). Note that for a 6-bit DAC, the resolution is ½ 6 =1.6%. 
     Section 13—Description of FIG.  13   
       FIG. 13  is a simplified circuit schematic diagram illustrating an embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is a mixed-signal current-mode digital-input to analog-current-output (D i I o ) scalar multiply-accumulate (sMAC) circuit that utilizes current-mode digital-to-analog-converters (iDAC). 
     A simplified D i I o  sMACiDAC&#39;s transfer function is 
                 ∑     m   =   1     n     ⁢     s   ×     p   m         ,         
where a scalar (s) is multiplied with the sum of plurality (m=n) of p m  weights. The disclosed embodiment of D i I o  sMACiDAC utilizes the distributive property, wherein multiplying the sum of two or more (plurality of) addends by a (scalar) number will give the same result as multiplying each addend individually by the scalar) number and then adding the products together. Accordingly, the disclosed embodiment of D i I o  sMACiDAC utilizes plurality of iDACs whose outputs coupled together in current-mode, which generates a summation current
 
             (       ∑     m   =   1     n     ⁢     p   m       )         
that is then fed onto a current reference terminal of a scalar iDAC, whose output generate
 
             s   ×       ∑     m   =   1     n     ⁢     p   m             
which can also be represented as
 
     
       
         
           
             
               ∑ 
               
                 m 
                 = 
                 1 
               
               n 
             
             ⁢ 
             
               s 
               × 
               
                 
                   p 
                   m 
                 
                 . 
               
             
           
         
       
     
     To accomplish the above objective, the disclosed circuit of  FIG. 13  utilizes a plurality of digital input words (p D ) that are supplied to a plurality (m=n) of iDACs that generate a plurality of respective analog output currents (p A ). The plurality of p A  analog output currents are coupled together which generates a summation current signal that is fed onto an input of a current controlled voltage source (CCVS). A voltage output of the CCVS is then fed onto a voltage controlled current source (VCCS). Then a current output of the VCCS is fed onto a (current) reference terminal of a scalar iDAC whose digital input word is S D . The scalar iDAC generates an analog (current) output signal which is the product of s A  (which represent the analog value of S D ) multiplied by the sum of a plurality p Ai  (for m=n plurality) or 
     
       
         
           
             
               
                 s 
                 A 
               
               × 
               
                 
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                     = 
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                     ⁢ 
                     i 
                   
                 
               
             
             = 
             
               
                 ∑ 
                 
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                   = 
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                 n 
               
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                   A 
                 
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                     p 
                     
                       A 
                       ⁢ 
                       i 
                     
                   
                   . 
                 
               
             
           
         
       
     
     To further describe the disclosed D i I o  sMACiDAC circuit embodiment of  FIG. 13 , let 
                 A   w     =       A     R   ⁢   w       ×       ∑     i   =   1     w     ⁢       D   i     /     2   i             ,       A   x     =       A     R   ⁢   x       ×       ∑     j   =   1     x     ⁢       D   j     /     2   j             ,         
and
 
               A   y     =       A     R   ⁢   y       ×       ∑     k   =   1     y     ⁢       D   k     /       2   k     .                 
For A RW =A Rx =A Ry =A R , then
 
     
       
         
           
             
               
                 A 
                 w 
               
               + 
               
                 A 
                 x 
               
               + 
               
                 A 
                 y 
               
             
             = 
             
               
                 A 
                 R 
               
               × 
               
                 
                   ( 
                   
                     
                       
                         ∑ 
                         
                           i 
                           = 
                           1 
                         
                         w 
                       
                       ⁢ 
                       
                         
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                           2 
                           i 
                         
                       
                     
                     + 
                     
                       
                         ∑ 
                         
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                   ) 
                 
                 . 
               
             
           
         
       
     
     The nomenclatures and terminologies used here are self-explanatory for one skilled in the art, but as an example for the w-channel iDAC, bear in mind that A w  is the analog output, A Rw  is the reference input, D i  is the digital input word that is w-bits wide, and so on. 
     If A R  is fed into reference input of scalar DACz 13 , then 
               A   z     =       A   R     ×       ∑     l   =   1     z     ⁢       D   l     /       2   l     .                 
By feeding A w +A x +A y =A Rz  into the reference input of scalar DACz 13 , then it generates:
 
     
       
         
           
             
               
                 
                   A 
                   o 
                 
                 = 
                 
                   
                     
                       A 
                       Rz 
                     
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                         ∑ 
                         
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                   = 
                   
                     
                       
                         ( 
                         
                           
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                             w 
                           
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                           + 
                           
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                             y 
                           
                         
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                       × 
                       
                         
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                         ⁢ 
                         
                           
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                 × 
                 
                   
                     ∑ 
                     
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                       = 
                       1 
                     
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                       l 
                     
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                         l 
                       
                       . 
                     
                   
                 
               
             
           
         
       
     
     Therefore, 
                   A   o     /     A   R       =       [     (         ∑     i   =   1     w     ⁢       D   i     /     2   i         +       ∑     j   =   1     x     ⁢       D   j     /     2   j         +       ∑     k   =   1     y     ⁢       D   k     /     2   k           )     ]     ×       ∑     l   =   1     z     ⁢       D   l     /     2   l             ,         
which can be represented in the analog domain as A o /A R =(A w +A x +A y )×A z . This represents multiplying scalar z by the accumulation of w, x, and y.
 
     In  FIG. 13 , the scalar iDACs and plurality of iDACs are shown with 3-bit of resolution i=j=k=l=3 and there are three (plurality) of iDACs, as an illustration and for clarity of description but not as a limitation of this disclosure. Resolution of iDACs can be up to 16-bits, and the plurality of iDACs can be a sea of iDACs and for example 1000 channels. 
     As noted earlier, an iDAC transfer function where A o =I i  and A R =I R  can be simplified to: 
               I   o     =         l   R     ⁢       ∑     i   =   1     n     ⁢       D   i     /     2   i           =       (       I   R     /     2   n       )     ×       ∑     i   =   1     n     ⁢       D   i     ×       2     i   -   1       .                   
For example, let&#39;s consider half-scale of a 3-bit wide digital word corresponding to the digital binary word D i =100 or D i =1, and D 2 =D 3 =0 and letting I R  be 1 unit representing full-scale for I o . In such an example, the DAC&#39;s input-to-output transfer function would be as follows: I o =I R ×[D 1 /2 1 +D 2 /2 2 +D 3 ×2 3 ]=(I R )×[½ 1 +0/2 2 +0/2 3 ]=I R /2=½ reference unit, which is ½ of full scale.
 
     Here a more detailed description of embodiment of the D i I o  sMACiDAC&#39;s circuit illustrated in  FIG. 13  is provided. The reference current I 1   13 =I r , is applied to a diode connected M 1   13  whose Vgs M1     13    biases the binary weighted current source network in each of three iDAC: DACw 13 , DACx 13 , and DACy 13 . Notice that M 12   13  and I 2   13  program the Vgs M12     13    that biases the cascoded FETs in binary current sources of DACw 13 , DACx 13 , and DACy 13  to attain higher output impedance of the respective iDAC&#39;s current network with higher accuracy, which can be omitted to save area if lower V DD  with less variation is available in the end-application. 
     A DACw 13  receives a digital word Dw n , and generates an analog output current Aw 13 , wherein Vgs M1     13    biases M 2   13 , M 3   13 , and M 4   13  (according to their respective width-over-length or W/L scales a.x, 1x, 2x, 4x) which programs the DACw 13 &#39;s binary weighted currents as a ratio of the I 1   13 =I r′ . The DACw 13 &#39;s current switches S 1   13 , S 2   13 , and S 3   13  steer the respective M 2   13 , M 3   13 , and M 4   13  currents to either a diode connected M 30   13  (which is coupled with the DACw 13 &#39;s I O   −  port) or the DACw 13  &#39;s I o   +  port (at Aw 13  signal) in accordance with the polarity of digital word Dw n  bits. As it would be clear to one skilled in the art, for example, when Dw n &#39;s MSB in on (high-state), then S 1   13  steers M 2   13 &#39;s current (through the cascoded FET M 14   13 ) onto the DACw 13 &#39;s I o   +  port (carrying the analog output current Aw 13 ). Conversely, when Dw 13 &#39;s MSB in off (low-state), then S 1   13  steers M 2   13 &#39;s current (through the cascoded FET M 14   13 ) onto the DACw 13 &#39;s I O   −  port and onto the diode connected M 30   13  (through the cascoded FET M 25   13 ). 
     A DACx 13  receives a digital word Dx 13 , and generates an analog output current Ax 13 , wherein Vgs M1     13    biases M 5   13 , M 6   13 , and M 7   13  (according to their respective width-over-length or W/L scales a.x, 1x, 2x, 4x) which programs the DACx 13 &#39;s binary weighted currents as a ratio of the I 1   13 =I r′ . The DACx 13 &#39;s current switches S 4   13 , S 5   13 , and S 6   13  steer the respective M 5   13 , M 6   13 , and M 7   13  currents to either the diode connected M 30   13  (which is coupled with the DACx 13 &#39;s I O   −  port) or the DACx 13 &#39;s I o   +  port (for Ax 13  signal) in accordance with the polarity of the Dx 13  bits. 
     A DACy 13  receives a digital word Dy 13 , and generates an analog output current Ay 13 , wherein Vgs M1     13    biases M 8   13 , M 9   13 , and M 10   13  (according to their respective width-over-length or W/L scales a.x, 1x, 2x, 4x) which programs the DACy 13 &#39;s binary weighted currents as a ratio of the I 1   13 =I r′ . The DACy 13 &#39;s current switches S 7   13 , S 8   13 , and S 9   13  steer the respective M 8   13 , M 9   13 , and M 10   13  currents to either the diode connected M 30   13  (which is coupled with the DACy n &#39;s to port) or the DACy 13 &#39;s I O   +  port (for Ay 13  signal) in accordance with the polarity of the Dy 13  bits. 
     As described earlier, the current outputs of DACw 13 , DACx 13 , and DACy 13  are then summed to generate the output current summation Aw 13 +Ax 13 +Ay 13 , which is fed onto the input of a CCVS (or current-to-voltage converter iTv 13 ) comprising of M 26   13  and M 31   13 . An output of the CCVS is Vgs M31     13    which is supplied to the input of a VCCS (or voltage-to-current converter vTi 13 ) comprising of M 32   13 . 
     Consider that for a=1, the full scale output current for each of DACw 13 , DACx 13 , and DACy 13  is (4+2+1)×I r′ =7I r′ . 
     Accordingly, the full-scale output current summation Aw 13 +Ax 13 +Ay 13  would compute to 3×7I r′ =21I r′ . The W/L&#39;s of M 31   13  and M 32   13  (i.e., b.x and c.x) program the combined gain of iTv 13  and vTi 13  which scales the sum of Aw 13 +Ax 13 +Ay 13  before the said sum is supplied to the reference input of a DACz 13 . For clarity of description b=c=1 which provides a combined current scaling (net-gain) of 1 (through iTv 13  to vTi 13 ) for the sum of Aw 13 +Ax 13 +Ay 13  currents that are supplied to the reference input of a DACz 13 . 
     The floating DACz 13  receives a digital word Dz 13 , and generates an analog output current at the DACz 13 &#39;s I o   +  port that is the output current of D i I o  sMACiDAC as being represented in the analog domain and proportional to A R″ : A o /A R″ =(A w +A x +A y )×A z . The DACz 13 &#39;s current switches S 10   13 , S 11   13 , and S 12   13  steer the respective M 27   13 , M 28   13 , and M 29   13  currents to either a diode connected M 11   13  (which is coupled with the DACz 13 &#39;s I O   −  port) or the DACz 13 &#39;s I o   +  port in accordance with the polarity of the Dz 13  bits. 
     As indicated earlier, for a=b=c=1, then A R″  is a scaled reference current where A R″ =21I r′ . Notice that DACz 13  utilizes a floating iDAC method that is disclosed in  FIG. 1  section 1. Also note that M 24   13  and I 2   13  program the Vgs M24     13    that biases the cascoded FETs M 25   13  to M 29   13  which provides sufficient drain-to-source voltages (V DS ) head-room and substantially equalizes the V DS  between M 31   13  and M 32   13  for better current matching and also to maintain their operation in the saturation regions. Also, to enhance the dynamic response of iTv 13  and vTi 13 , a constant current Ij 13  is added to keep the diode connected M 31   13  constantly alive during D i I o  sMACiDAC&#39;s zero and full scale transitions, and accordingly an substantially equal current Ij′ 13  is subtracted from drain terminal of M 32   13  to keep the mirror balanced. 
     Bear in mind that for better dynamic response and substantially equalization between the operating voltages at the I O   −  and I o   +  ports of the DACw 13 , DACx 13 , and DACy 13 , their I O   −  ports can be coupled with drain terminal of M 30   13  (also coupled with source terminal of M 25   13 ), while a current source (e.g., Ij″ 13  not shown in  FIG. 13 ) can be coupled with gate terminal of M 30   13  (also coupled with drain terminal of M 25   13 ). 
     In summary, the embodiment illustrated in  FIG. 13  of a mixed-mode scalar multiply-accumulate (D i I o  sMACiDAC) circuit that processes signals in current-mode utilizing iDACs has the following benefits: 
     First, the disclosed D i I o  sMACiDAC utilizing plurality of iDACs (along with CCVS and VCCS) whose outputs are summed in current-mode and fed onto the reference input terminal of a scalar iDAC saves area and lowers cost, and improved performance with faster dynamic response. This is in part due to the efficacy in performing the distributive property in current-mode, wherein multiplying the sum of two or more addends by a number will give the same result as multiplying each addend individually by the number and then adding the products together. Summation in current-mode is accomplished by simply coupling plurality of addends (i.e., coupling the output of plurality of iDACs together), and feeding the said summation to another scalar iDAC&#39;s reference input. This will result in multiplying each addend individually by the scalar number and then adding the products together, which is fast since signals are processed in current-mode. 
     Second, utilizing the floating iDAC method disclosed in  FIG. 1  section 1, saves area and reduces FETs sizes carrying lower capacitances in the iDAC&#39;s current reference network which in turn lowers the cost, reduces the size, and improves the transient response of the D i I o  sMACiDAC that utilizes such iDACs. 
     Third, as noted earlier, the disclosed D i I o  sMACiDAC utilizing iDACs that operate in current-mode is inherently fast. 
     Fourth, voltage swings in current-mode signal processing are small, which enables operating the disclosed D i I o  sMACiDAC with lower power supply voltage and retain the speed and dynamic rage benefits. 
     Fifth, operating at low supply voltage reduces power consumption of the disclosed D i I o  sMACiDAC. Additionally, the flexibility to run the CMOSFETs in subthreshold enables a iDAC that are utilized in D i I o  sMACiDAC to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that may require numerous ultra-low power and low power supply iDACs for computation. 
     Sixth, the disclosed D i I o  sMACiDAC utilizing iDAC for signal processing such as addition or subtraction operations, in current mode, take small area and can be performed fast. 
     Seventh, by substantially equalizing the terminal voltages at I o   +  and I O   −  ports of plurality of iDACs as well as the I o   +  and I O   −  ports of scalar iDACs utilized in the disclosed D i I o  sMACiDAC, improves the D i I o  sMACiDAC&#39;s transient response and glitch is reduced during on-to-off D i I o  sMACiDAC&#39;s digital input code transitions. 
     Eight, there are no passive devices in the disclosed D i I o  sMACiDAC of  FIG. 13 , and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Ninth, the precision of the disclosed D i I o  sMACiDAC can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Tenth, the disclosed D i I o  sMACiDAC of  FIG. 13  can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication due to (8-bits of accuracy or ±0.4%) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed D i I o  sMACiDAC can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Eleventh, glitch is lower during code transitions in D i I o  sMACiDAC because floating iDACs utilized in D i I o  sMACiDAC can be made smaller given that their input-to-output transfer function network utilizes smaller devices that carry smaller capacitances, which inject fewer analog glitches to the output of the D i I o  sMACiDAC during digital input code transitions. 
     Twelfth, dynamic power consumption is lower because the D i I o  sMACiDAC utilizes floating iDAC that have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Thirteenths, the D i I o  sMACiDAC that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Fourteenth, the D i I o  sMACiDAC that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process-temperature-operation conditions variations. Accordingly, the D i I o  sMACiDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Fifteenth, while digital computation is generally accurate but it may be excessively power hungry. Current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Sixteenth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents). For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals. 
     Seventeenth, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 14—Description of FIG.  14   
       FIG. 14  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to analog-current-output (D i I o ) scalar multiply-accumulate (SMAC) circuit utilizing current-mode digital-to-analog-converters (iDAC). 
     The disclosed embodiment of D i I o  sMACiDAC in  FIG. 14  also utilizes the a multiplication property, wherein multiplying the sum of two or more (plurality of) addends by a (scalar) number will give the same result as multiplying each addend individually by the number and then adding the products together. To accomplish this objective, the disclosed circuit of  FIG. 14  utilizes a scalar iDACs that receives a digital input word (s D ) and generates an analog current (s A ). Concurrently, a plurality of iDACs receive a respective plurality of digital input words (p D ). The s A  is replicated onto plurality of s A s that are supplied to a plurality reference inputs of the plurality of iDACs. The outputs of the plurality of iDACs are couple together to generate a summation current signal, which is the product of s A  (which represent the analog value of S D ) multiplied by the sum of a plurality P At  (which represent a plurality of respective analog value of the respective plurality of p D ) or 
     
       
         
           
             
               
                 s 
                 A 
               
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                     = 
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                 ⁢ 
                 
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             = 
             
               
                 ∑ 
                 
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                   s 
                   A 
                 
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                     p 
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                   . 
                 
               
             
           
         
       
     
     To further describe the disclosed D i I o  sMACiDAC circuit embodiment of  FIG. 14 , let the FET&#39;s W/L factors a=b=c=d=e=1. For an A Rz  feeding the reference input of scalar DACz 14 , its output signal 
               A   z     =       A   Rz     ×       ∑     l   =   1     z     ⁢       D   l     /       2   l     .                 
Similarly,
 
                 A   w     =       A   Rw     ×       ∑     i   =   1     w     ⁢       D   i     /     2   i             ,       A   x     =       A   Rx     ×       ∑     j   =   1     x     ⁢       D   j     /     2   j             ,         
and
 
               A   y     =       A   Ry     ×       ∑     k   =   1     y     ⁢       D   k     /       2   k     .                 
By replicating and feeding substantially equal values of A z  onto the reference inputs of a plurality (e.g., 3 channels) of floating iDACs, namely DACw 14 , DACx 14 , and DACy 14 , then:
 
               A   Rw     =       A   Rx     =       A   Ry     =       A   z     =       A   Rz     ×       ∑     l   =   1     z     ⁢       D   l     /       2   l     .                       
Therefore,
 
     
       
         
           
             
               
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             ; 
           
         
       
       
         
           
             
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     Therefore, the disclosed D i I o  sMACiDAC output current signal which is the summation of w, x, and y-iDAC&#39;s outputs is thus: 
                 A   w     +     A   x     +     A   y       =       A   Rz     ×       ∑     l   =   1     z     ⁢         D   l     /     2   l       ×       (         ∑     i   =   1     w     ⁢       D   i     /     2   i         +       ∑     j   =   1     x     ⁢       D   j     /     2   j         +       ∑     k   =   1     y     ⁢       D   k     /     2   k           )     .                 
Therefore,
 
                   A   o     /     A   R       =       [     (         ∑     i   =   1     w     ⁢       D   i     /     2   i         +       ∑     j   =   1     x     ⁢       D   j     /     2   j         +       ∑     k   =   1     y     ⁢       D   k     /     2   k           )     ]     ×       ∑     l   =   1     z     ⁢       D   l     /     2   l             ,         
which can be mapped in the analog domain as A o /A R =(A w +A x +A y )×A z  representing multiplying scalar z by the accumulation of w, x, and y.
 
     Note that in  FIG. 14 , the scalar DACz 14  and plurality of iDACs (e.g., for 3-channels DACw 14 , DACx 14 , and DACy 14 ) are shown with 3-bit of resolution with i=j=k=l=3. In  FIG. 14 &#39;s illustration of D i I o  sMACiDAC embodiment with 3-bits of resolution and 3 channels is for illustrative clarity of description, but not as a limitation of this disclosure. Resolution of iDACs can be up to 16-bits, and the plurality of iDACs can be a sea of iDACs and for example 1000 channels. 
     Here, a more detailed description of embodiment of the D i I o  sMACiDAC&#39;s circuit illustrated in  FIG. 14  is provided. The reference current I 1   14 =I r′  is applied to a diode connected M 17   14  whose Vgs M17     14    biases the binary weighted current source network of the scalar DACz 14 . Let e=1 for this illustration. Consider that M 18   14  and I 2   14  program the Vgs M18     14    that biases the cascoded FETs is intended to increase (accuracy and) the output impedance of DACz 14 &#39;s current source network. 
     A DACz 14  receives a digital word Dz 14 , and generates an analog output current Az 14 , wherein Vgs M17     14    biases M 23   14 , M 24   14 , and M 25   14  (according to their respective width-over-length or W/L scales e.x, 1x, 2x, 4x) which programs the DACz 14 &#39;s binary weighted currents as a ratio of the I 1   14 =I r′ . The DACz 14 &#39;s current switches S 10   14 , S 11   14 , and S 12   14  steer the respective M 23   14 , M 24   14 , and M 25   14  currents to either a diode connected M 5   14  (which is coupled with the DACz 14 &#39;s to port) or the DACz 14 &#39;s I o   +  port (for Az 14  signal) in accordance with the polarity of the Dz 14  bits. As it would be clear to one skilled in the art, for example, when Dz 14 &#39;s MSB in on (high-state), then S 10   14  steers M 23   14 &#39;s current (through the cascoded FET M 19   14 ) onto the DACz 14 &#39;s I o   +  port (carrying the an analog output current Az 14 ). Conversely, when Dz 14 &#39;s MSB in off (low-state), then S 10   14  steers M 23   14 &#39;s current (through the cascoded FET M 19   14 ) onto the DACz 14 &#39;s I O   −  port and onto the diode connected M 5   14 . Also, notice that for e=1, the DACz 14  full-scale output is I 1   4  (4+2+1)=7I r′ . 
     As noted earlier, Az 14  (which is the current outputs of the DACz 14 ) is replicated and fed onto the reference input terminals of DACw 14 , DACx 14 , and DACy 14 . In the embodiment of  FIGS. 15 and 14 , proportional replication of Az 14  is effectuated via feeding Az 14  onto a current-controlled-voltage source (CCVS) with a gain of 1/g, whose output voltage can then feed plurality of (e.g.,  3 ) voltage-controlled-current-sources (VCCSs) with their gains proportional to g. The plurality of outputs of the VCCSs can then feed the reference input terminals of a plurality of iDACs (e.g., DACw 14 , DACx 14 , and DACy 14 ). 
     More specifically, in  FIG. 14 , the CCVS and VCCSs are implemented by feeding Az 14  current onto a diode connected M 4   14  whose current is scaled and mirrored through M 1   14 , M 2   14 , and M 3   14 . For descriptive clarity, let M 1   14  to M 4   14 &#39;s W/L factors a=b=c=d=1 (which programs the gains of CCVS and VCCS). As described in the floating iDAC of  FIG. 2  section 2, M 1   14 , M 2   14 , and M 3   14  supply the reference current signal for the three floating iDACs here: DACw 14 , DACx 14 , and DACy 14 . Also, bias current I 2   14  and a diode connected M 6   14  program Vgs M6     14    which biases the respective DACw 14 , DACx 14 , and DACy 14 &#39;s binary weighted current networks comprising of M 7   14 -M 9   14 , M 10   14 -M 12   14 , and M 13   14 -M 15   14 , respectively. 
     A DACw 14  receives a digital word Dw 14  at its digital input port, receives a reference current signal that is a proportional replica of Az 14  through a current mirror (M 4   14 , M 1   14 ) and generates an analog output current signal Aw 14 ×Az 14 . As noted earlier, floating DACw 14 &#39;s reference current is proportional to Az 14  that (through M 1   14 ) is binarily distributed between M 7   14 , M 8   14 , and M 9   14 , according to their respective width-over-length or W/L scales 1x, 2x, 4x. The DACw 14 &#39;s current switches S 1   14 , S 2   14 , and S 3   14  steer the respective M 7   14 , M 8   14 , and M 9   14  currents to either a diode connected M 26   14  (which is coupled with the DACw 14 &#39;s I O   −  port) or the DACw 14 &#39;s I o   +  port (carrying a Aw 14 ×Az 14  current signal) in accordance with the polarity of the Dw 14  bits. 
     A DACx 13  receives a digital word Dx 14  at its digital input port, receives a reference current signal that is a proportional replica of Az 14  through a current mirror (M 4   14 , M 2   14 ) and generates an analog output current signal Ax 14 ×Az 14 . As noted earlier, floating DACx 14 &#39;s reference current is proportional to Az 14  that (through M 2   14 ) is binarily distributed between M 10   14 , M 11   14 , and M 12   14 , according to their respective width-over-length or W/L scales 1x, 2x, 4x. The DACx 14 &#39;s current switches S 4   14 , S 5   14 , and S 6   14  steer the respective M 10   14 , M 11   14 , and M 12   14  currents to either a diode connected M 26   14  (which is coupled with the DACx 14 &#39;s I O   −  port) or the DACx 14 &#39;s I o   +  port (carrying a Ax 14 ×Az 14  current signal) in accordance with the polarity of the Dx 14  bits. 
     A DACy 13  receives a digital word Dy 14  at its digital input port, receives a reference current signal that is a proportional replica of Az 14  through a current mirror (M 4   14 , M 3   14 ) and generates an analog output current signal Ay 14 ×Az 14 . As noted earlier, floating DACy 14 &#39;s reference current is proportional to Az 14  that (through M 3   14 ) is binarily distributed between M 13   14 , M 14   14 , and M 15   14 , according to their respective width-over-length or W/L scales 1x, 2x, 4x. The DACy 14 &#39;s current switches S 7   14 , S 8   14 , and S 9   14  steer the respective M 13   14 , M 14   14 , and M 15   14  currents to either a diode connected M 26   14  (which is coupled with the DACy 14 &#39;s I O   −  port) or the DACy 14 &#39;s I o   +  port (carrying a Ay 14 ×Az 14  current signal) in accordance with the polarity of the Dy 14  bits. 
     As indicated earlier, DACz 14 &#39;s full scale output current is 7I 1   4 =7I r′  and as such the DACw 14 , DACx 14 , and DACy 14  full scale can be programmed to 7I r′  with a=b=c=d=e=1. In this case, the summation of DACw 14 , DACx 14 , and DACy 14  full-scale output current or summation of Aw 14 ×Az 14 +Ax 14 ×Az 14 +Ay 14 ×Az 14  would compute to 3×7I r′ =21I r′ . The output of sMACiDAC can be represented in the analog domain and proportional to 21I r′ =A o /A R″ =(A W  A x +A y )×A z . 
     As stated earlier, M 6   14  and I 2   14  program the Vgs M6     14    that biases the floating current sources of DACw 14 , DACx 14 , and DACy 14  as well as provide sufficient drain-to-source voltages (V DS ) head-room and substantially equalizes the V as  between M 1   14  and M 3   14  for better current matching and also to maintain their operation in the saturation regions. Also, to enhance the dynamic response D i I o  sMACiDAC a constant current I 1   14  is added to keep the diode connected M 4   14  alive during DACw 14 &#39;s zero and full scale transitions, and accordingly a proportional current Ij′ 14  (e.g., 3×Ij 14 ) is subtracted from the current output terminal of D i I o  sMACiDAC. 
     In summary, the embodiment of the D i I o  sMACiDAC circuit illustrated in  FIG. 14  that processes signals in current-mode by utilizing iDACs has the following benefits: 
     First, the disclosed D i I o  sMACiDAC utilizing a current mode scalar iDACs whose output is copied and fed onto the reference input terminals of plurality of iDAC saves area and lowers cost, and improved performance with faster dynamic response, in part for its efficacy in performing summation in current-mode that can be accomplished by simply coupling plurality of current signals. 
     Second, utilizing the floating iDAC method disclosed in  FIG. 1  section 1, saves area and reduces FETs sizes (which lower capacitance) in the iDAC&#39;s current reference network which in turn lowers the cost, reduces the size, and improves the transient response of the D i I o  sMACiDAC that utilizes such iDACs. 
     Third, as noted earlier, the disclosed D i I o  sMACiDAC utilizing iDACs that operate in current-mode is inherently fast. 
     Fourth, voltage swings in current-mode signal processing are small, which enables operating the disclosed D i I o  sMACiDAC of  FIG. 14  with lower power supply voltage and retain the speed and dynamic rage benefits. 
     Fifth, operating at low supply voltage reduces power consumption of the disclosed D i I o  sMACiDAC. Additionally, the flexibility to run the CMOSFETs in subthreshold enables a iDAC that are utilized in D i I o  sMACiDAC to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications, especially in AI and ML applications that may require numerous ultra-low power and low power supply iDACs for computation. 
     Sixth, the disclosed D i I o  sMACiDAC utilizing iDAC for signal processing such as addition or subtraction functions (in current mode) take small area and can be performed fast. 
     Seventh, by substantially equalizing the terminal voltages at I o   +  and I O   −  ports of plurality of iDACs as well as the I o   +  and I O   −  ports of scalar iDACs utilized in the disclosed D i I o  sMACiDAC, improves the D i I o  sMACiDAC&#39;s transient response and glitch is reduced during on-and-off D i I o  sMACiDAC&#39;s digital input code transitions. 
     Eight, there are no passive devices in the disclosed D i I o  sMACiDAC of  FIG. 14 , and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Ninth, the precision of the disclosed D i I o  sMACiDAC can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Tenth, the disclosed D i I o  sMACiDAC of  FIG. 14  can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed D i I o  sMACiDAC can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Eleventh, glitch is lower during code transitions in D i I o  sMACiDAC because floating iDACs utilized in D i I o  sMACiDAC can be made smaller given that their input-to-output transfer function network utilizes smaller devices that carry smaller capacitances, which inject fewer analog glitches to the output of the D i I o  sMACiDAC during digital input code transitions. 
     Twelfth, dynamic power consumption is lower because the D i I o  sMACiDAC utilizes floating iDAC that have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Thirteenths, the D i I o  sMACiDAC that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Fourteenth, the D i I o  sMACiDAC that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process, temperature, and operating conditions variations. Accordingly, the D i I o  sMACiDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Fifteenth, while digital computation is generally accurate but it may be excessively power hungry. Current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally may result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Sixteenth, the embodiment disclosed here is not restricted by FETs having to operate either in saturation (high-currents) or subthreshold (low currents). For example, some analog signal processing units rely on operating transistors in the subthreshold regions which restricts the dynamic range of analog signal processing circuits to low current signals. Also, some other analog signal processing units rely on operating transistors with high currents in the saturation regions which restricts the dynamic range of analog signal processing circuits to higher current signals. 
     Seventeenth, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 15—Description of FIG.  15   
       FIG. 15  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to digital-output (D i D o ) scalar multiply-accumulate (sMAC) plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
     Utilizing current-mode data-converters, the D i D o  sMACiDAC embodiment disclosed in  FIG. 15 , first multiplies a scalar current signal by a respective plurality of current signals, whose products are summed together in current-mode and added to a bias current signal to generate a final summation signal. This final summation current signal is digitized via a current-mode analog-to-digital-converter (iADC).  FIG. 15  disclosure performs the multiply-accumulate function by utilizing analog and mixed-signal signal processing in current-mode, by arranging data-converters to leverage the distributive property of multiplication, to save area and improve performance in multiply-accumulate functions needed in AI and ML applications. As such, the embodiment disclosed in  FIG. 15 , performs the function of 
                 ∑     i   =   1     p     ⁢     (       s   ×     W   i       +   b     )       ,         
where s is scalar current signal (e.g., s can be programmed by iDACz 15 ), W i  is plurality of weight current signals with p as pluralities of channels (e.g., p=3 of W i  current signals can be programmed by iDACw 15 , iDACx 15 , and iDAC 15 , respectively), and b is bias current signal (e.g., b current signal can be programmed by DACb 15 ). As indicated in prior sections, the illustration of  FIG. 15  depicts (plurality) p=3 channels for clarity of description, but n can be a sea of channels depending on application and as many as 1000.
 
     In  FIG. 15 , a scalar iDACz 15  is supplied with a reference current signal I 1   15  at its zR 15  port, receives a z-bits wide digital input word Dz 15 , and accordingly iDACz 15  generates an analog output current signal Az 15 . 
     The Az 15  current is inputted to a current-controlled-voltage-source CCVS 15 &#39;s current input port, whose gain is programmed to g 15 . The CCVS 15 &#39;s voltage output port is coupled with a plurality of voltage-controlled-current sources VCCSs 15 , which in the  FIG. 15  illustration are 3-channels VCCS 1   15 , VCCS 2   15 , and VCCS 3   15  but could be more depending on the application requirement. The gains of VCCS 1   15 , VCCS 2   15 , and VCCS 3   15  can be programmed to a/g 15 , b/g 15 , and c/g 15 , respectively. It is of note that the CCVS and plurality of VCCS can be implemented with current mirrors, such as the one illustrated in  FIG. 14  (e.g., M 4   14 , M 1   44 , M 2   14 , and M 3   14 ). A plurality of iDAC&#39;s reference ports are supplied with a respective plurality of proportional replicates of scalar iDAC&#39;s output current signal as follows: 
     An iDACw 15  is supplied with the VCCS 1   15 &#39;s output current (a×Az 15 ) at iDACw 15 &#39;s reference port wR 15  port. The iDACw 15  receives a w-bits wide digital input word Dw 15 , and accordingly iDACw 15  generates an analog output current signal a×Az 15 ×Aw 15 . 
     An iDACx 15  is supplied with the VCCS 2   15 &#39;s output current (b×Az 15 ) at iDACx 15 &#39;s reference port xR 15  port. An iDACx 15  receives a v-bits wide digital input word Dx 15 , and accordingly iDACx 15  generates an analog output current signal b×Az 15 ×Ax 15 . 
     An iDACy 15  is supplied with the VCCS 3   15 &#39;s output current (c×Az 15 ) at iDACy 15 &#39;s reference port yR 15  port. An iDACy 15  receives a y-bits wide digital input word Dy 15 , and accordingly iDACy 15  generates an analog output current signal c×Az 15 ×Ay 15 . 
     A bias iDACb 15  is supplied with a reference current signal I 2   15  at its bR 15  port, receives a b-bits wide digital input word Db 15 , and accordingly iDACb 15  generates an analog output current signal Ab 15 . 
     The current outputs of iDACw 15 , iDACx 15 , iDACy 15 , and iDACb 15  are coupled together to generate a summation current signal of a×Az 15 ×Aw 15 +b×Az 15 ×Ax 15 +c×Az 15 ×Ay 15 +Ab 15 =Az 15 ×(a×Aw 15 +b×Ax 15 +c×Ay 15 )+Ab 15 . This summation current signal is concurrently fed onto a current input port of iADC 15  which is a current-mode analog-to-digital-converter (iADC), which generates a o-bits wide digital output word Do 15  which is the digital representation of the D i D o  iMACiDAC output signal Az 15 ×(a×Aw 15 +b×Ax 15 +c×Ay 15 )+Ab 15 . 
     In summary, the D i D o  sMACiDAC embodiment illustrated in  FIG. 15  that processes signals in current-mode utilizing iDACs has the following benefits: 
     First, the disclosed D i I o  sMACiDAC utilizing plurality of current-mode iDACs whose certain outputs can be coupled together and biased (in current mode) saves area (lower cost) and improved performance (faster dynamic response), in part for its efficacy in performing summation in current-mode that can be accomplished by simply coupling plurality of current signals. 
     Second, standard iDACs or factorized or floating iDACs methods (described earlier in the disclosure) can be utilized, which saves area and reduces FETs sizes with lower capacitances in the iDAC&#39;s current reference network, which in turn lowers the cost, reduces the size, and improves the transient response of the D i D o  sMACiDAC that utilizes such iDACs. 
     Third, as noted earlier, operating in current mode has the following benefits for the disclosed D i D o  sMACiDAC: (a) current mode is inherently fast, (b) voltage swings in current-mode signal processing are small, which enables operating with lower power supply voltage and operating at low supply voltages facilitates reducing power consumption, (c) current-mode signal processing such as addition or subtraction functions take small area and can be performed fast. 
     Fourth, there are no passive devices in the disclosed D i D o  sMACiDAC of  FIG. 15 , and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Fifth, the precision of the disclosed D i D o  sMACiDAC can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Sixth, the disclosed D i D o  sMACiDAC of  FIG. 15  can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%)) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed D i D o  sMACiDAC can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Seventh, dynamic power consumption is lower because the D i D o  sMACiDAC by utilizing floating, factorized, or combination of floating and factorized iDACs which have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Eight, the D i D o  sMACiDAC that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Ninth, the D i D o  sMACiDAC that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating, factorized, or combination of floating and factorized iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process, temperature, operating condition variations. Accordingly, the D i D o  sMACiDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Tenth, while digital computation is generally accurate but it may be excessively power hungry. Current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally may result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Eleventh, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 16—Description of FIG.  16   
       FIG. 16  is a simplified functional block diagram illustrating another embodiment of a mixed-signal current-mode scalar multiply-accumulate (sMACiDAC) circuit. The disclosed sMACiDAC is another mixed-signal current-mode digital-input to digital-output (D i D o ) scalar multiply-accumulate (sMAC) plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
     Utilizing current-mode data-converters, the D i D o  sMACiDAC embodiment disclosed in  FIG. 16 , first a plurality of current signals are summed together, wherein the said summation current signal is multiplied by a scalar current signal, whose products are summed together in current-mode and added to a bias current signal to generate a final summation signal. This final summation current signal is digitized via a current-mode analog-to-digital-converter (iADC).  FIG. 16  disclosure performs the multiply-accumulate function by utilizing analog and mixed-signal signal processing in current-mode, by arranging data-converters to leverage the distributive property of multiplication, to save area and improve performance in multiply-accumulate functions needed in AI and ML applications. As such, the embodiment disclosed in  FIG. 16 , performs the function of 
                 ∑     i   =   1     p     ⁢     (       s   ×     W   i       +   b     )       ,         
where s is scalar current signal (e.g., s can be programmed by iDACz 16 ), W i  is plurality of weight current signals with p as pluralities of channels (e.g., p=3 of W i  current signals can be programmed by iDACw 16 , iDACx 16 , and iDACy 16 , respectively), and b is bias current signal (e.g., b current signal can be programmed by DACb 16 ). As indicated in prior sections, the illustration of  FIG. 16  depicts (plurality) p=3 channels for clarity of description, but n can be a sea of channels depending on application and as many as 1000.
 
     In  FIG. 16 , a plurality of iDAC&#39;s reference ports are supplied with a respective plurality of current reference signals, wherein the plurality of iDACs generate a plurality of output current signals, which are coupled together to generate a summation current signal as follows: An iDACw 16  is supplied with the I 1   16  reference current at iDACw 16 &#39;s reference port wR 16  port. The iDACw 16  receives a w-bits wide digital input word Dw 16 , and accordingly iDACw 16  generates an analog output current signal Aw 16 . An iDACx 16  is supplied with the I 2   16  reference current at iDACx 16 &#39;s reference port xR 16  port. The iDACx 16  receives a v-bits wide digital input word Dx m , and accordingly iDACx 16  generates an analog output current signal Ax 16 . An iDACy 16  is supplied with the I 3   16  reference current at iDACy 16 &#39;s reference port yR 16  port. The iDACy 16  receives a y-bits wide digital input word Dy 16 , and accordingly iDACy 16  generates an analog output current signal Ay 16 . The output currents of the iDACw 16 , iDACx 16 , and iDACy 16  are coupled together to generate a summation current represented by Aw 16 +Ay 16 +Ax 16  which is fed onto an input port of current-controlled-voltage source CCVS 16  (which a gain of g 16 ) whose output is coupled with an input of a voltage-controlled-current-source VCCS 16  (which a gain of a/g 16 ). Considering the net-gain of g 16 ×1/g 16 =a attributed to CCVS 16  and VCCS 16  combination, output current representing (Aw 16 +Ay 16 +Ax 16 )×a is generated at the output port of VCCS 16 . 
     The output current of VCCS 16  is concurrently fed onto zR 16  which is a reference input terminal of a scalar iDACz 16 . The iDACz 16  receives a z-bits wide digital input word Dz 16 , and accordingly iDACz 16  generates an analog output current signal that represents a×Az 16 ×(Aw 16 +Ay 16 +Ax 16 ). 
     Also concurrently, a bias iDACb 16  is supplied with a reference current signal I 4   16  at its bR 16  port, receives a b-bits wide digital input word Db 16 , and accordingly iDACb 16  generates an analog output current signal Ab 16 . 
     The output of iDACz 16  and output of iDACb 16  are coupled together to generate a final summation current signal representing a×Az 16 ×(Aw 16 +Ay 16 +Ax 16 )+Ab 16 . This final summation current signal is concurrently fed onto a current input port of iADC 16  which is a current-mode analog-to-digital-converter (iADC), which generates a o-bits wide digital output word Do 16  which is the digital representation of the D i D o  iMACiDAC output signal a×Az 16 ×(Aw 16 +Ay 16 +Ax 16 )+Ab 16 . 
     Bear in mind that  FIG. 13  can be a circuit embodiment of the functional block diagram illustrating the embodiment of D i D o  sMACiDAC circuit of  FIG. 16 , excluding the iDACb 16  and iADC 16 . Also, keep in mind that similar to the circuit embodiment illustrated in  FIG. 13 , the CCVS 16  and VCCS 16  combination in  FIG. 16  can correspond to the iTv 13  and vTi 13  combination in  FIG. 13  (comprising of M 26   13 , M 27   13 , M 31   13 , and M 32   13  and Ij 13 , Ij′ 13 ). 
     In summary, the embodiment illustrated in  FIG. 16  of a mixed-mode scalar multiply-accumulate (D i D o  sMACiDAC) circuit that processes signals in current-mode utilizing iDACs has the following benefits: 
     First, the disclosed D i I o  sMACiDAC utilizing plurality of current-mode iDACs whose certain outputs can be coupled together and biased in current mode, which saves area and lowers cost, and improved performance with faster dynamic response, in part for its efficacy in performing summation in current-mode that can be accomplished by simply coupling plurality of current signals. 
     Second, standard iDACs or factorized or floating iDACs methods (described earlier in the disclosure) can be utilized, which saves area and reduces FETs sizes carrying lower capacitances in the iDAC&#39;s current reference network, which in turn lowers cost, reduces the size, and improves the transient response of the D i D o  sMACiDAC that utilizes such iDACs. 
     Third, as noted earlier, operating in current mode has the following benefits for the disclosed D i D o  sMACiDAC: (a) current mode is inherently fast, (b) voltage swings in current-mode signal processing are small, which enables operating with lower power supply voltage and operating at low supply voltages facilitates reducing power consumption, (c) current-mode signal processing such as addition or subtraction functions take small area and can be performed fast. 
     Fourth, there are no passive devices in the disclosed D i D o  sMACiDAC of  FIG. 16 , and as such it does not require resistors or capacitors, which reduces manufacturing size and cost. 
     Fifth, the precision of the disclosed D i D o  sMACiDAC can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Sixth, the disclosed D i D o  sMACiDAC of  FIG. 16  can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed D i D o  sMACiDAC can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Seventh, dynamic power consumption is lower because the D i D o  sMACiDAC by utilizing floating, factorized, or combination of floating and factorized iDACs which have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Eight, the D i D o  sMACiDAC that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Ninth, the D i D o  sMACiDAC that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating, factorized, or combination of floating and factorized iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process, temperature, and operating condition variations. Accordingly, the D i D o  sMACiDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Tenth, while digital computation is generally accurate but it may be excessively power hungry. Current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally may result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Thirteenth, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 17—Description of FIG.  17   
       FIG. 17  is a simplified functional block diagram illustrating an embodiment of a mixed-signal current-mode multiply-accumulate (iMACiDAC) circuit. The disclosed iMACiDAC is a mixed-signal current-mode digital-input to digital-output (D i D o ) multiply-accumulate (iMAC) circuit plus bias circuit utilizing current-mode digital-to-analog-converters (iDAC) and current-mode analog-to-digital converters (iADC). 
     The D i D o  iMACiDAC embodiment disclosed in  FIG. 17  is arranged with a plurality of weight iDACs to generate a plurality of weight current signals that feed the reference input of a respective plurality of data iDACs. A respective plurality of the data iDACs outputs generate a respective plurality of products as analog current representations of a respective plurality of the weight iDACs input signals multiplied by a respective plurality of the data iDACs input signals. The respective plurality of the data iDACs outputs are coupled together to generate a summation current signal that is then added to a bias current signal to generate a final summation current signal, wherein the bias current signal is programmed by a bias iDAC. This final summation current signal is digitized via a current-mode analog-to-digital-converter (iADC) whose digital outputs represent a summation of bias iDAC input signal added with a summation of the products of the respective weight iDAC input signals multiplied by the respective data iDAC input signals. 
       FIG. 17  discloses an embodiment that performs a multiply-accumulate function by performing analog and mixed-signal processing utilizing current-mode data-converters, arranged in such a way to leverage the distributive property of multiplication, which save area and improve performance of multiply-accumulate functions needed in AI and ML applications. As such, the embodiment disclosed in  FIG. 17 , performs the function of 
                 ∑     i   =   1     p     ⁢     (         D   i     ×     W   i       +   b     )       ,         
where D i  is plurality of ‘data current signals’ with p as plurality (e.g., p=3 of D i  can be generated by iDACs 17 , iDACt 17 , and iDACu 17 ), W i  is plurality of ‘weight current signals’ with p again as plurality (e.g., again with p=3 of W i  current signals that can be generated by iDACw 16 , iDACx 16 , and iDACy 16 , respectively), and b is ‘bias current signal’ (e.g., b current signal can be generated by DACb 17 ). As indicated in prior sections, the illustration of  FIG. 17  depicts (plurality) p=3 for clarity of description, but n can be a sea of multiplying iDAC channels depending on application and as many as 1000.
 
     In  FIG. 17 , a weight iDACw 17  is supplied with a reference current signal I 4   17  at its wR 17  port. Also, iDACw 17  receives a w-bits wide digital input word Dw 17 , and accordingly iDACw 17  generates an analog output current signal Aw 17 . Concurrently, a data iDACs 17  is supplied with Aw 17  at its sR 17  reference input port, while iDACs 17  receives a s-bits wide digital input word Ds 17 , and accordingly iDACs 17  generates an analog output current signal As 17 ×Aw 17 , which represents the product of w ‘weight current signal’ multiplied by s ‘data current signal’. 
     A weight iDACx 17  is supplied with a reference current signal I 3   17  at its xR 17  port. Also, iDACx 17  receives a v-bits wide digital input word Dx 17 , and accordingly iDACx 17  generates an analog output current signal Ax 17 . Concurrently, a data iDACt 17  is supplied with Ax 17  at its tR 17  reference input port, while iDACt 17  receives a t-bits wide digital input word Dt 17 , and accordingly iDACt 17  generates an analog output current signal At 17 ×Ax 17 , which represents the product of x ‘weight current signal’ multiplied by t ‘data current signal’. 
     A weight iDACy 17  is supplied with a reference current signal I 2   17  at its yR 17  port. Also, iDACy 17  receives a y-bits wide digital input word Dy 17 , and accordingly iDACy 17  generates an analog output current signal Ay 17 . Concurrently, a data iDACu 17  is supplied with Ay 17  at its uR 17  reference input port, while iDACu 17  receives a u-bits wide digital input word Du 17 , and accordingly iDACu 17  generates an analog output current signal Au 17 ×Ay 17 , which represents the product of y ‘weight current signal’ multiplied by u ‘data current signal’. 
     A bias iDACb 17  is supplied with a reference current signal I 1   17  at its bR 17  reference input port. Also, iDACb 17  receives a b-bits wide digital input word Db 17 , and accordingly iDACb 17  generates an analog output current signal Ab 17 . 
     The output of iDACb 17 , iDACs 17 , iDACt 17 , and iDACu 17  are coupled together to generate a final summation current signal representing (Au 17 ×Ay 17 +At 17 ×Ax 17 +As 17 ×Aw 17 )+Ab 17 . 
     This final summation current signal is concurrently fed onto a current input port of iADC 17  which is a current-mode analog-to-digital-converter (iADC), which generates a o-bits wide digital output word Do 17  which is the digital representation of the D i D o  iMACiDAC output signal (Au 17 ×Ay 17 +At 17 ×Ax 17 +As 17 ×Aw 17 )+Ab 17 . 
     In summary, the embodiment of D i D o  sMACiDAC circuit illustrated in  FIG. 17  processes signals in current-mode utilizing iDACs has the following benefits: 
     First, the disclosed D i I o  sMACiDAC utilizing plurality of current-mode iDACs whose certain outputs can be coupled together and biased in current mode, which saves area and lowers cost, and improved performance with faster dynamic response, in part for its efficacy in performing summation in current-mode that can be accomplished by simply coupling plurality of current signals. 
     Second, standard iDACs or factorized or floating iDACs methods (described earlier in the disclosure) can be utilized, which saves area and reduces FETs sizes carrying lower capacitances in the iDAC&#39;s current reference network, which in turn lowers cost, reduces the size, and improves the transient response of the D i D o  sMACiDAC that utilizes such iDACs. 
     Third, as noted earlier, operating in current mode has the following benefits for the disclosed D i D o  sMACiDAC: (a) current mode is inherently fast, (b) voltage swings in current-mode signal processing are small, which enables operating with lower power supply voltage and operating at low supply voltages facilitates reducing power consumption, (c) current-mode signal processing such as addition or subtraction functions take small area and can be performed fast. 
     Fourth, there are no passive devices in the disclosed D i D o  sMACiDAC of  FIG. 17 , and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Fifth, the precision of the disclosed D i D o  sMACiDAC can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Sixth, the disclosed D i D o  sMACiDAC of  FIG. 17  can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed D i D o  sMACiDAC can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Seventh, dynamic power consumption is lower because the D i D o  sMACiDAC by utilizing floating, factorized, or combination of floating and factorized iDACs could have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Eight, the D i D o  sMACiDAC that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Ninth, the D i D o  sMACiDAC that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating, factorized, or combination of floating and factorized iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process-temperature-operation conditions variations. Accordingly, the D i D o  sMACiDAC&#39;s temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Tenth, while digital computation is generally accurate but it may be excessively power hungry. Current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally may result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Eleventh, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 18—Description of FIG.  18   
       FIG. 18  is a simplified functional block diagram illustrating an embodiment of a mixed-signal current-mode Artificial Neural Network (iANN) circuit. The disclosed iANN is a mixed-signal current-mode digital-input to digital-output (D i D o ) iANN circuit utilizing current-mode multiply-accumulate (iMAC) circuits that utilize current-mode digital-to-analog-converter (iDAC) and current-mode analog-to-digital converter (iADC) circuits. 
     Consider that in the  FIG. 18  illustrates 3 channels of iDACs (e.g., iDACm 18 -iDACn 18 -iDACo 18 , or iDACp 18 -iDACq 18 -iDACr 18 , or iDACs 18 -iDACt 18 -iDACu 18 , or iDACx 18 -iDACy 18 -iDACz 18 , or iDACa 18 -iDACb 18 -iDACc 18 , and so on) for clarity of description and illustration purposes only, but 3 channels are not a limitation of this disclosure. For example, a sea of iDACs (e.g., less than 1000 channels) can be utilized here depending on end-applications. 
     In  FIG. 18 , an iDACx 18  receives a reference current signal xR 18 , a x-bits wide digital input word Dx 18 , and generates an analog output current signal Ax 18 . Keep in mind that the Ax 18  can be replicated, as illustrated in  FIG. 15 , and supplied to plurality of reference inputs of a respective plurality of iDACs comprising of iDACm 18 , iDACn 18 , and iDACo 18 . Accordingly, an iDACm 18  receives a m-bits wide digital input word Dm 18 , and generates an analog output current signal Ax 18 ×Am 18 . An iDACn 18  receives a n-bits wide digital input word Dn 18 , and generates an analog output current signal Ax 18 ×An 18 . An iDACo 18  receives a o-bits wide digital input word Do 18 , and generates an analog output current signal Ax 18 ×Ao n . 
     An iDACy 18  receives a reference current signal yR 18 , a y-bits wide digital input word Dy 18 , and generates an analog output current signal Ay 18 . Also, bear in mind that the Ay 18  can be replicated, similarly as illustrated in  FIG. 15 , and supplied to plurality of reference inputs of a respective plurality of iDACs comprising of iDACp 18 , iDACq 18 , and iDACr 18 . Accordingly, an iDACp 18  receives a p-bits wide digital input word Dp 18 , and generates an analog output current signal Ay 18 ×Ap 18 . An iDACq 18  receives a q-bits wide digital input word Da 18 , and generates an analog output current signal Ay 18 ×Aq 18 . An iDACr 18  receives a r-bits wide digital input word Dr 18 , and generates an analog output current signal Ay 18 ×Ar 18 . 
     An iDACz 18  receives a reference current signal zR 18 , a z-bits wide digital input word Dz 18 , and generates an analog output current signal Az 18 . Also, notice that the Az 18  can be replicated, similarly as illustrated in  FIG. 15 , and supplied to plurality of reference inputs of a respective plurality of iDACs comprising of iDACs 18 , iDACt 18 , and iDACu 18 . Accordingly, an iDACs 18  receives a s-bits wide digital input word Ds 18 , and generates an analog output current signal Az 18 ×As 18 . An iDACt 18  receives a t-bits wide digital input word Dt 18 , and generates an analog output current signal Az 18 ×At 18 . An iDACu 18  receives a u-bits wide digital input word Du 18 , and generates an analog output current signal Az 18 ×Au 18 . 
     A bias iDACa 18  receives a reference current signal aR 18 , a a-bits wide digital input word Da n , and generates an analog output current signal Aa 18 . A bias iDACb 18  receives a reference current signal bR 18 , a b-bits wide digital input word Db 18 , and generates an analog output current signal Ab 18 . A bias iDACc 18  receives a reference current signal cR 18 , a c-bits wide digital input word Dc 18 , and generates an analog output current signal Ac 18 . 
     The outputs of iDACm 18 , iDACp 18 , and iDACs 18  are coupled together and coupled with output of bias iDACa 18  which generates the summation analog current signal that is a multiply-accumulate analog current signal Ia iMAC =[Aa 18 +(Ax 18 ×Am 18 +Ay 18 ×Ap 18 +Az 18 ×As 18 )] which can be independently digitized through an iADC or can be fed onto an input of a current mux (iMux) as depicted by iMUX 18 . 
     Also, the outputs of iDACn 18 , iDACq 18 , and iDACt 18  are coupled together and coupled with output of bias iDACb 18  which generates the summation analog current signal that is another multiply-accumulate analog current signal Ib iMAC =[Ab 18 +(Ax 18 ×An 18 +Ay 18 ×Aq 18 +Az 18 ×At 18 )] which can be independently digitized through another input of a current mux (iMux) as depicted by iMUX 18 . 
     Moreover, the outputs of iDACn 18 , iDACq 18 , and iDACt 18  are coupled together and coupled with output of bias iDACb 18  which generates the summation analog current signal that is another multiply-accumulate analog current signal Ic iMAC =[Ab 18  (Ax 18 ×An 18 +Ay 18 ×Aq 18 +Az 18 ×At 18 )] which can be independently digitized through an iADC or can be fed onto another input of a current mux (iMux) as depicted by iMUX 18 . 
     A current mux (such as  FIG. 18  illustration of an iMUX 18  which is a 3-to-1 channel analog current mux) with plurality of inputs and one output can consecutively select with (S 18 ) and steer the multiply-accumulate analog current signals Ia iMAC , Ib iMAC , and Ic iMAC  into iADC 18  to digitize the said multiply-accumulate analog current signals at its output D 18 . 
     Notice that there is flexibility in programming the  FIG. 18 &#39;s iDACs reference signals (e.g., xR 18 , yR 18 , zR 18 , aR 18 , bR 18 , cR 18 , R 18 ) such as programming xR 18 =yR 18 =zR 18 . Also, depending on the end-application requirements, to save area and current consumption, one bias iDAC can be arranged with its output replicated and supplied to plurality of multiply-accumulate analog current nodes, instead of utilizing plurality of bias iDACs (e.g., iDACa 18 , iDACb 18 , and iDACc 18 ). Moreover, the reference signal of the iADC 18  can be programmed to accommodate the zero to full scale current signals of the plurality of multiply-accumulate analog currents (e.g., Ia iMAC , Ib iMAC , and Ic iMAC ). 
     In summary, the current-mode Artificial Neural Network (iANN) circuit in illustrated  FIG. 18  is a mixed-signal digital-input to digital-output (D i D o ) iANN that is arranged with plurality of current-mode multiply-accumulate (iMAC) circuits, wherein the iMAC circuits utilize current-mode digital-to-analog-converter (iDAC) and current-mode analog-to-digital converter (iADC) circuits. As such, the disclosed iANN has the following benefits: 
     First, in part, because summation is a key part of iANN that are arranged with iMAC circuits that utilize iDAC circuits, a simple coupling of iDAC current outputs generates a summation signal in a small area, asynchronously, and at high speeds (since current mode signal processing is inherently fast. 
     Second, standard iDACs or factorized or floating iDACs methods (described earlier in the disclosure) can be utilized here, which saves area and reduces FETs sizes carrying lower capacitances in the iDAC&#39;s current reference network, which in turn lowers cost, reduces the size, and improves the transient response of the iANN. 
     Third, as noted earlier, operating the iANN in current-mode reduces voltage swings, which enables operating with lower power supply voltage and operating at low supply voltages facilitates reducing power consumption. Additionally, the flexibility to run the CMOSFETs in subthreshold enables the iDACs (and hence the iANN) to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications. 
     Fourth, there are no passive devices in the disclosed iANN, and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Fifth, the precision of the disclosed iANN can be improved by improving the accuracy of iDACs (for example) by segmenting the iDAC&#39;s reference current transfer-function (along with digital binary-to-thermometer logic decoding of iDAC&#39;s digital input code). 
     Sixth, the iANN can utilize lower resolution iDACs (e.g., 3-bits or 5-bits) to perform the multiplication function, which occupy smaller areas, but can still deliver higher accuracy (e.g., 8-bits of accuracy or ±0.4%) which is beneficial. For example, higher than 3 of 5 bits of accuracy for iDACs is attainable in standard CMOS fabrication factories due to (8-bits of accuracy or ±0.4%) matching that is achievable between the iDAC&#39;s binary weighted current sources or segmented current sources. As such, the disclosed iANN can utilize low resolution iDACs that occupy small areas but still achieve higher accuracy multiply-accumulate performance at lower cost. 
     Seventh, dynamic power consumption is lower because iANN can utilize floating, factorized, or combination of floating and factorized iDACs which have smaller sized FETs (in the input-to-output transfer function network) which would consume less dynamic current to drive smaller FET devices during digital input code transitions. 
     Eight, the iANN that utilizes floating iDAC can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Ninth, the iANN that utilizes same type of MOSFET current sources and MOSFET switches in the respective floating, factorized, or combination of floating and factorized iDACs, which are symmetric, matched, and scaled. Such arrangement facilitates device parameters to track each other over process-temperature-operation conditions variations. Accordingly, the iANN temperature coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced. 
     Tenth, while digital computation is generally accurate but it may be excessively power hungry. Methods of current-mode analog and mixed-signal computation that is disclosed here can be approximate but signal processing can be accomplished asynchronously and power consumption can be lower. Moreover, analog current errors here generally may result in degradation but (not total failures) of analog computation, which provides the end-application with approximate results to work with instead of experiencing failed results. 
     Eleventh, utilizing plurality of iDACs, whose outputs are summed, would attenuate the statistical contribution of the cumulative iDAC&#39;s random errors (such as random noise, offset, mismatches, linearity, gain, drift, etc.) at the summing node where the iDAC&#39;s current outputs are coupled. The statistical contribution of such cumulative iDAC&#39;s random errors, at the summing node, is the square root of the sum of the squares of such random error terms. 
     Section 19—Description of FIG.  19   
       FIG. 19  is a simplified circuit schematic diagram illustrating an embodiment of a multi-channel mixed-signal current-mode digital-to-analog converter (iDAC) utilizing the multiple-channel data-converter method. 
     One of the objectives of this disclosure is to make multiple-channel (sea of) iDACs with medium-to-high (6-bits to 12-bits) resolution that is small size and low cost. Low cost and small size of sea of iDACs have broad applications, including in machine learning (ML) and artificial intelligence (AI) applications wherein 1000s of iDACs may be utilized as part of for example the multiply-accumulate (MAC) function. 
     Another objective of this disclosure is to make multiple-channel (sea of) current mode analog to digital converters (iADCs). Similarly, low cost and small size of sea of iADCs have broad base of applications including in ML &amp; AI applications where a plurality of sums of the outputs of a plurality of current-mode MACs (iMACs) may need to be converted to digital signals. The first segments of this section describe iDACs. 
     For clarity of description,  FIG. 19  illustrates only 4-channels of 6-bit iDACs, and this illustration is not a limitation of the disclosure here. Depending on application requirements, the disclosed multiple-channel data-converter method could have 1000s of channels where each iDAC can, for example, have 16-bits of resolution. 
     Note that for example, in a conventional 6-bit binary iDACs with an LSB current weight of i, binary current source network comprising of current sources (2 6-1 )i, (2 5-1 )i, (2 4-1 )i, (2 3-1 )i, (2 2-1 )i, and (2 1-1 )i are generated by arranging plurality of paralleled current reference cells. Generally, each current cell is a non-minimum W/L=X carrying an LSB current weight (e.g., i). In a conventional iDAC, identical cells having a 1× (W/L size carrying an LSB current weight of i) are, for example, replicated in parallel 32×, 16×, 8×, 4×, 2×, and 1× times to generate the respective binary reference currents of 32i, 16i, 8i, 4i, 2i, and 1i. Utilizing identical current cells (which dominate the accuracy of an iDACs and that are arranged in parallel to generate the respective binary reference currents,) improves the matching between respective binary weighted reference currents, and optimizes the iDAC&#39;s accuracy. 
     As an example, in a conventional 6-bit iDAC the binary weighted currents would require 127 LSB current cells. A conventional 8-bit iDAC&#39;s binary weighted currents would require 255 LSB current cells. Thus, a 16-channel conventional 6-bit iDAC array would require about 127×16=2032 LSB current cells and an 8-bit iDAC array would require about 255×16=4080 LSB current cells. In order to attain medium to high accuracy targets for the iDACs, the LSB current cells need to be patterned with non-minimum (larger) size W and L, and as such the numerous LSB current cells which are combined in parallel, dominate the area of the iDACs. As such, conventional iDACs with medium to large resolution are generally prohibitively large and impractical for AI and ML applications that require (numerous channels) sea of iDACs. 
     Operating in current mode, an iDAC is generally fast. However, because of the numerous paralleled LSB current cells required in conventional medium to high resolution iDACs, the combined parasitic and stray capacitance associated with the array of paralleled LSB current cells would slow down the circuit. For example, in an 8-bit iDAC, the 8th bit or the MSB is comprised of 128× parallel LSB current cells and 7 th  bit is comprised of 64× parallel LSB current cells and so on. Besides occupying large die area, the large size of paralleled current cells can slow down the dynamic response of the conventional iDACs, cause glitch into the iDAC&#39;s analog output as well as the power supplier, and increase dynamic current consumption. Consequently, the overall dynamic performance of the iDACs and AI and ML end-system could be degraded. 
     The disclosed invention, utilizing a multiple-channel data-converter method, substantially reduces the number of the current cells (and thereby minimizes the area of the disclosed iDACs) which makes feasible utilizing sea of the disclosed iDACs with a low cost. Moreover, plurality of the disclosed iDACs with substantially fewer current cells, lowers the combined associated parasitic and stray capacitance associated with current reference cells, which improves the disclosed iDAC&#39;s dynamic response, lowers glitch, lowers digital injections into power supplies, and reduces the disclosed iDAC&#39;s dynamic power consumption. 
     A multiple-channel data-converter method disclosed here arranges a plurality of n-bit iDACs, wherein each of the iDACs is comprised of a voltage controlled current sources (VCCS) to generate each iDAC&#39;s binary weighted currents. With i representing an LSB current weight, the multiple-channel data-converter method utilizes a reference bias network (RBN 19 ) that generates a sequence of individual binary weighted reference bias currents from (2 n-1 )i to (2 1-1 )i that are inputted to a sequence of current controlled voltage sources (CCVS). In turn, the sequences of CCVSs generate a sequence of reference bias voltage buses that correspond to the sequence of binary weighted reference bias currents (2 n-1 )i to (2 1-1 )i. The respective output ports of CCVSs, which are a sequence of reference bias voltage busses are coupled to the input of the sequence of the respective plurality of iDACs&#39; VCCSs, that correspond to the respective binary weighted reference bias currents from (2 n-1 )i to (2 1-1 )i. 
     By utilizing the multiple-channel data-converter method, the reference current network of an iADC or that of a plurality of iADCs can also be supplied with sequence of reference bias voltage buses that can bias the sequence of binary weighted reference bias currents (2 n-1 )i to (2 1-1 )i of the iADC or the plurality of iADCs. As such, the multiple-channel data-converter method enables decoupling the weight of a current source from the scaling of the size current source node capacitances of the iADC&#39;s current reference networks. This trait, beside saving on die area, can substantially reduce node capacitance along the iADC&#39;s signal paths which can speed up the iADC (e.g., the larger the W/L size of a FET current source the larger its capacitance and the slower the node). 
     Consider that the multiple-channel data-converter method can also be arranged such that a RBN would generate a sequence of individual reference bias currents that are non-linear (e.g., square or logarithmic) where the sequence of individual reference bias currents can then bias the current reference networks (transfer function) for multiple-channels of non-linear iDACs, wherein as a result each of the non-liner iDAC&#39;s current reference network would follow a non-linear (e.g., square or logarithmic) digital input to analog current output transfer function. 
     For example, if a RBN is programmed to approximate a logarithmic transfer function, then a pair of iDACs (e.g., iDAC log X  and iDAC log Y ) whose reference current networks are biased from the logarithmic RBN can each generate logarithmic outputs in response to their digital inputs (e.g., D X , and D Y ). Coupling the outputs of the pair of logarithmic iDAC X  and iDAC Y  would generate a current output that is an analog representation of the product of D log X  and D log Y  in the logarithmic domain (i.e., analog current representation of log[D X ×D Y ]. This can be a cost-performance effective arrangement to perform, for example, 1000s of multiplications on one IC by utilizing plurality of pairs of logarithmic iDACs (whose digital input to analog output transfer functions are programmed logarithmically), wherein each logarithmic iDAC can have small reference current network that is biased from the same logarithmic RBN. 
     An alternative example could be to program a RBN that follows an approximate square function. As such a pair of square iDACs (e.g., iDAC (x+y)     2    and iDAC (x−y)     2   ) whose reference current networks are biased from the square RBN. Accordingly, each pair of iDAC (x+y)     2    and iDAC (x−y)     2    can generate square outputs in response to the summation and subtraction of their respective digital inputs (e.g., D X +D Y , and D Y −D Y ). Bear in mind that multiplication can be performed by a quarter square operation, wherein (X+Y) 2 −(X−Y) 2 =4×X×Y. Therefore, by subtracting the outputs of the pair of iDAC (x+y)     2    and iDAC (x−y)     2   , we can generate a current output that is an analog representation of the product of D X  and D Y  times a scale factor (e.g., scale factor=4). The subtraction operation in current mode can be accomplished cost-performance effectively by feeding the iDAC (x+y)     2    and iDAC (x−y)     2    current outputs to the input port and output port of a current mirror, respectively. This also can be a cost-performance effective arrangement to perform, for example, 1000s of multiplications in one IC by utilizing plurality of pairs of square iDACs (wherein each of the iDAC&#39;s digital input to analog output transfer functions are programmed squarely), wherein each square iDAC has a small reference current network that is biased from the same square RBN.  FIG. 42  illustrates atypical simulations of a square iDAC&#39;s input-output waveform and linearity, which will be described later. 
     As noted earlier, for clarity of description,  FIG. 19  illustrates an embodiment of the multiple-channel data-converter method with a 4-channels of iDACs wherein each iDAC has 6-bits of resolution. Here, the four channels of iDACs are iDACa 19 , iDACb 19 , iDACc 19 , and iDACd 19 , whose current source networks are biased via reference bias network (RBAt 19 ) circuit. 
     In  FIG. 19 , a RBAt 19  generates a sequence of individual binary weighted reference bias currents as follows: P 32   r   19  operating at I D  of (2 6-1 )×i=32i; P 16   r   19  operating at I D  of (2 5-1 )×i=16i; P 8   r   19  operating at I D  of (2 4-1 )×i=8i; P 4   r   19  operating at I D  of (2 3-1 )×i=4i; P 2   r   19  operating at I D  of (2 2-1 )×i=2i; and P 1   r   19  operating at I D  of (2 1-1 )×i=1i. In the embodiment of  FIG. 19 , RBN 19  is comprised of a sequence of CCVS which are implemented as a sequence of diode connected NMOSFETs (N 32   r   19 , N 16   r   19 , N 8   r   19 , N 4   r   19 , N 2   r   19 , and N 1   r   19 ) whose gate and drain ports are coupled together, wherein each NMOSFET is scaled with a W/L=1×. Accordingly, the sequence of binary weighted reference bias currents I 32   r   19  to I 1   r   19  are inputted to the diode connected NMOSFETs (CCVS) which generate a sequence of (gate-to-source) reference bias voltages from reference bias voltage bus V 32   r   19  to reference bias voltage bus V 1   r   19  as follows: I D  of P 32   r   19 =32i is inputted to the (drain-gate ports of the) diode connected N 32   r   19  to generate a reference bias bus voltage of V 32   r   19 ; I D  of P 16   r   19 =16i is inputted to the diode connected N 16   r   19  to generate a reference bias bus voltage of V 16   r   19 ; I D  of P 8   r   19 =8i is inputted to the diode connected N 8   r   19  to generate a reference bias bus voltage of V 8   r   19 ; I D  of P 4   r   19 =4i is inputted to the diode connected N 4   r   19  to generate a reference bias bus voltage of V 4   r   19 ; I D  of P 2   r   19 =2i is inputted to the diode connected N 2   r   19  to generate a reference bias bus voltage of V 2   r   19 ; and I D  of P 1   r   19 =1i is inputted to the diode connected N 1   r   19  to generate a reference bias bus voltage of V 1   r   19 . 
     The iDACa 19  receives a digital input word Da 19  that is a=6 bits wide and generates a positive and a negative output currents I a19   + , and I a19   − , respectively. Here, N 32   a   19  which is scaled with W/L=1× (and functioning as iDACa 19 &#39;s 6 th  bit&#39;s VCCC) receives the reference bias bus voltage V 32   r   19  at its gate port. As such, I D  of N 32   a   19  mirrors that of the N 32   r   19 , and generates I D =32i for iDACa 19  which is steered onto either I a19   +  or I a19   −  in accordance with (the MSB or) the 6 th  bit&#39;s polarity of the Da 19  word. The N 16   a   19  which is also scaled with W/L=1× (and functioning as iDACa 19 &#39;s 5 th  bit&#39;s VCCC) receives the reference bias bus voltage V 16   r   19  at its gate port. As such, I D  of N 16   a   19  mirrors that of the N 16   r   19 , and generates I D =16i for iDACa 19  which is steered onto either I a19   +  or I a19   − , in accordance with the 5 th  bit&#39;s polarity of the Da 19  word. The N 8   a   19  is also scaled with W/L=1× (and functioning as iDACa 19 &#39;s 4 th  bit&#39;s VCCC) receives the reference bias bus voltage V 8   r   19  at its gate port. As such, I D  of N 8   a   19  mirrors that of the N 8   r   19 , and generates I D =8i for iDACa 19  which is steered onto either I a19   +  or I a19   − , in accordance with the 4 th  bit&#39;s polarity of the Da 19  word. The N 4   a   19  which is also scaled with W/L=1× (and functioning as iDACa 19 &#39;s 3 rd  bit&#39;s VCCC) receives the reference bias bus voltage V 4   r   19  at its gate port. As such, I D  of N 4   a   19  mirrors that of the N 4   r   19 , and generates I D =4i for iDACa 19  which is steered onto either I a19   +  or I a19   −  in accordance with the 3 rd  bit&#39;s polarity of the Da 19  word. The N 2   a   19  which is also scaled with W/L=1× (and functioning as iDACa 19 &#39;s 2 nd  bit&#39;s VCCC) receives the reference bias bus voltage V 2   r   19  at its gate port. As such, I D  of N 2   a   19  mirrors that of the N 2   r   19 , and generates I D =2i for iDACa 19  which is steered onto either I a19   +  or I a19   −  in accordance with the 2 nd  bit&#39;s polarity of the Da 19  word. The N 1   a   19  which is also scaled with W/L=1× (and functioning as iDACa 19 &#39;s bit&#39;s VCCC) receives the reference bias bus voltage V 1   r   19  at its gate port. As such, I D  of N 1   a   19  mirrors that of the N 1   r   19 , and generates I D =1i for iDACa 19  which is steered onto either I a19   +  or I a19   −  in accordance with the 1 st  bit&#39;s polarity of the Da 19  word. 
     The iDACb 19  receives a digital input word Db 19  that is b=6 bits wide and generates a positive and a negative output currents I b19   +  and I b19   − , respectively. Here, N 32   b   19  which is scaled with W/L=1× (and functioning as iDACb 19 &#39;s 6 th  bit&#39;s VCCC) receives the reference bias bus voltage V 32   r   19  at its gate port. As such, I D  of N 32   b   19  mirrors that of the N 32   r   19 , and generates I D =32i for iDACb 19  which is steered onto either I b19   +  or I b19   −  in accordance with (the MSB or) the 6 th  bit&#39;s polarity of the Db 19  word. The N 16   b   19  which is also scaled with W/L=1× (and functioning as iDACb 19 &#39;s 5 th  bit&#39;s VCCC) receives the reference bias bus voltage V 16   r   19  at its gate port. As such, I D  of N 16   b   19  mirrors that of the N 16   r   19 , and generates I D =16i for iDACb 19  which is steered onto either or in accordance with the 5 th  bit&#39;s polarity of the Db 19  word. The N 8   b   19  which is also scaled with W/L=1× (and functioning as iDACb 19 &#39;s 4 th  bit&#39;s VCCC) receives the reference bias bus voltage V 8   r   19  at its gate port. As such, I D  of N 8   b   19  mirrors that of the N 8   r   19 , and generates I D =8i for iDACb 19  which is steered onto either I b19   +  or I b19   −  in accordance with the 4 th  bit&#39;s polarity of the Db 19  word. The N 4   b   19  which is also scaled with W/L=1× (and functioning as iDACb 19 &#39;s 3 rd  bit&#39;s VCCC) receives the reference bias bus voltage V 4   r   19  at its gate port. As such, I D  of N 4   b   19  mirrors that of the N 4   r   19 , and generates I D =4i for iDACb 19  which is steered onto either or in accordance with the 3 rd  bit&#39;s polarity of the Db 19  word. The N 2   b   19  which is also scaled with W/L=1× (and functioning as iDACb 19 &#39;s 2 nd  bit&#39;s VCCC) receives the reference bias bus voltage V 2   r   19  at its gate port. As such, I D  of N 2 b 19  mirrors that of the N 2   r   19 , and generates I D =2i for iDACb 19  which is steered onto either or in accordance with the 2 nd  bit&#39;s polarity of the Db 19  word. The N 1   b   19  which is also scaled with W/L=1× (and functioning as iDACb 19 &#39;s 1 st  bit&#39;s VCCC) receives the reference bias bus voltage V 1   r   19  at its gate port. As such, I D  of N 1   b   19  mirrors that of the N 1   r   19 , and generates I D =1i for iDACb 19  which is steered onto either or in accordance with the 1 st  bit&#39;s polarity of the Db 19  word. 
     The iDACc 19  receives a digital input word Dc 19  that is c=6 bits wide and generates a positive and a negative output currents I c19   +  and I c19   − , respectively. Here, N 32   c   19  which is scaled with W/L=1× (and functioning as iDACc 19 &#39;s 6 th  bit&#39;s VCCC) receives the reference bias bus voltage V 32   r   19  at its gate port. As such, I D  of N 32   c   19  mirrors that of the N 32   r   19 , and generates I D =32i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with (the MSB or) the 6 th  bit&#39;s polarity of the Dc 19  word. The N 16   c   19  which is also scaled with W/L=1× (and functioning as iDACc 19 &#39;s 5 th  bit&#39;s VCCC) receives the reference bias bus voltage V 16   r   19  at its gate port. As such, I D  of N 16   c   19  mirrors that of the N 16   r   19 , and generates I D =16i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with the 5 th  bit&#39;s polarity of the Dc 19  word. The N 8   c   19  which is also scaled with W/L=1× (and functioning as iDACc 19 &#39;s 4 th  bit&#39;s VCCC) receives the reference bias bus voltage V 8   r   19  at its gate port. As such, I D  of N 8   c   19  mirrors that of the N 8   r   19 , and generates I D =8i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with the 4 th  bit&#39;s polarity of the Dc 19  word. The N 4   c   19  which is also scaled with W/L=1× (and functioning as iDACc 19 &#39;s 3 rd  bit&#39;s VCCC) receives the reference bias bus voltage V 4   r   19  at its gate port. As such, I D  of N 4   c   19  mirrors that of the N 4   r   19 , and generates I D =4i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with the 3 rd  bit&#39;s polarity of the Dc 19  word. The N 2   c   19  which is also scaled with W/L=1× (and functioning as iDACc 19 &#39;s 2 nd  bit&#39;s VCCC) receives the reference bias bus voltage V 2   r   19  at its gate port. As such, I D  of N 2   c   19  mirrors that of the N 2   r   19 , and generates I D =2i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with the 2 nd  bit&#39;s polarity of the Dc 19  word. The N 1   c   19  which is also scaled with W/L=1× (and functioning as iDACc 19 &#39;s 1 st  bit&#39;s VCCC) receives the reference bias bus voltage V 1   r   19  at its gate port. As such, I D  of N 1   c   19  mirrors that of the N 1   r   19 , and generates I D =1i for iDACc 19  which is steered onto either I c19   +  or I c19   −  in accordance with the 1 st  bit&#39;s polarity of the Dc 19  word. 
     Finally, iDACd 19  receives a digital input word Dd 19  that is d=6 bits wide and generates a positive and a negative output currents I d19   +  and I d19   − , respectively. Here, N 32   d   19  which is scaled with W/L=1× (and functioning as iDACd 19 &#39;s 6 th  bit&#39;s VCCC) receives the reference bias bus voltage V 32   r   19  at its gate port. As such, I D  of N 32   d   19  mirrors that of the N 32   r   19 , and generates I D =32i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with (the MSB or) the 6 th  bit&#39;s polarity of the Dd 19  word. The N 16   d   19  which is also scaled with W/L=1× (and functioning as iDACd 19 &#39;s 5 th  bit&#39;s VCCC) receives the reference bias bus voltage V 16   r   19  at its gate port. As such, I D  of N 16   d   19  mirrors that of the N 16   r   19 , and generates I D =16i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with the 5 th  bit&#39;s polarity of the Dd 19  word. The N 8   d   19  which is also scaled with W/L=1× (and functioning as iDACd 19 &#39;s 4 th  bit&#39;s VCCC) receives the reference bias bus voltage V 8   r   19  at its gate port. As such, I D  of N 8   d   19  mirrors that of the N 8   r   19 , and generates I D =8i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with the 4 th  bit&#39;s polarity of the Dd 19  word. The N 4   d   19  which is also scaled with W/L=1× (and functioning as iDACd 19 &#39;s 3 rd  bit&#39;s VCCC) receives the reference bias bus voltage V 4   r   19  at its gate port. As such, I D  of N 4   d   19  mirrors that of the N 4   r   19 , and generates I D =4i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with the 3 rd  bit&#39;s polarity of the Dd 19  word. The N 2   d   19  which is also scaled with W/L=1× (and functioning as iDACd 19 &#39;s 2 nd  bit&#39;s VCCC) receives the reference bias bus voltage V 2   r   19  at its gate port. As such, I D  of N 2   d   19  mirrors that of the N 2   r   19 , and generates I D =2i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with the 2 nd  bit&#39;s polarity of the Dd 19  word. The N 1   d   19  which is also scaled with W/L=1× (and functioning as iDACd 19 &#39;s 1 st  bit&#39;s VCCC) receives the reference bias bus voltage V 1   r   19  at its gate port. As such, I D  of N 1   d   19  mirrors that of the N 1   r   19 , and generates I D =1i for iDACd 19  which is steered onto either I d19   +  or I d19   −  in accordance with the 1 st  bit&#39;s polarity of the Dd 19  word. 
     In the embodiment of  FIG. 19 , the multiple-channel data-converter method generates the binary weighted reference currents for plurality of iDACs (iDACa 19 , iDACb 19 , iDACc 19 , and iDACd 19 ) via their respective sequence of current source MOSFETs N 32   19 , N 16   19 , N 8   19 , N 4   19 , N 2   19 , and N 1   19 . These MOSFET are only scaled with W/L=1×, which results in significant area savings. For a plurality of 6-bit iDACs (setting aside RBN 19 &#39;s area), every incremental iDAC utilizing the multiple-channel data-converter method requires 6 of 1× size current sources, which is less than 10 times the area as compared to 64 of 1× size current sources required for a conventional 6-bit iDAC which requires a binary scaling of the MOSFET based current source network. Moreover, for a plurality of 8-bit iDACs (setting aside RBAt 19 &#39;s area), every incremental 8-bit iDAC utilizing the multiple-channel data-converter method requires 8 of 1× size current sources, which is less than 25 times the area as compared to 256 of 1× size current sources required for a conventional 8-bit iDAC which requires binary scaled MOSFETs for its current source network. 
     Moreover, dynamic response of the iDACs is improved here because the disclosed multiple-channel data-converter method substantially reduces the number of MOSFETs that form the iDAC&#39;s binary weighted current source network. Fewer MOSFETs result in substantially less capacitance along the iDAC&#39;s signal paths, which in turn improves the dynamic response of the iDACs, including reducing glitch and lowering dynamic power consumption. 
     As indicated earlier, the MOSFETs that form a conventional iDAC&#39;s binary weighted current sources need to be sized with meaningfully larger W and L than minimum geometry for better matching and thereby attaining higher accuracy iDACs. Given their larger W/L sizes, a conventional iDAC&#39;s binary weighted current source network, dominate the area of such iDAC. Utilizing the multiple-channel data-converter method, accuracy is roughly comparable with that of a conventional iDAC by keeping the larger (non-minimum MOSFETs) W/L size of the iDAC&#39;s current source. However, multiple-channel data-converter method reduces the number of non-minimum MOSFET utilizes in the iDAC&#39;s current sources, providing meaningful die size reduction and cost savings. 
     Bear in mind that the multiple-channel data-converter method can be utilized for a portion of an iDAC&#39;s current source network (e.g., MSB bank) and conventional binary weighted iDAC can be utilized for the remainder portion (e.g., LSB bank) of iDAC&#39;s current source network. Also consider that the iDAC&#39;s current sources can utilize cascoded MOSFETs to attain higher output impedance, and the cascoded MOFETs can be biased with an independent bias bus, that feeds plurality of iDACs, similar in arrangement to those generated by RBAt 19  circuit. Also, notice that for example in applications requiring 8 or 16 or 32 channels iDACs, the area savings by utilize g the multiple-channel data-converter method significantly outweighs the additional area due to RBN 19 . 
     In summary, the current-mode multiple-channel data-converter method that is illustrated in the embodiment of  FIG. 19  discloses integrating multiple mid-to-high resolution current-mode data-converters including iDACs with the following benefits: 
     First, substantial area savings is achieved by utilizing the disclosed multiple-channel data-converter method, especially in applications requiring sea of iDACa in a chip. The area savings is achieved in part because the requirement for individually weighted current sources (e.g., binary weighted or non-linearly weighted) is decoupled from requiring individually scaled current sources. 
     Second, the disclosed multiple-channel data-converter method substantially reduces the number of MOSFETs that form the iDAC&#39;s binary weighted current source network. Fewer MOSFETs result in substantially less capacitance along the iDAC&#39;s signal paths, which in turn improves the dynamic response of the iDACs, including reducing glitch and lowering dynamic power consumption. 
     Third, despite area savings attainable by the disclosed multiple-channel data-converter method, the accuracy of individual iDACs is not substantially deterred. All else substantially equal, the matching of MOSFETs that form a data-converter&#39;s reference current network dominate the accuracy of a current-mode data-converter. The scaled MOSFETs in both the (central) reference bias network (RBN) match the 1× scaled MOSFETs in each of the iDAC because they are all arranged with the same (non-minimum W/L size) cell layout and same orientation. 
     Fourth, as noted earlier, operating the disclosed multiple-channel data-converter method in current-mode is inherently fast. Moreover, operating in current mode reduces voltage swings along the pertinent signal paths, which enables operating the iDACs with lower power supply voltages. Operating the data-converters at low power supply voltages facilitates reducing power consumption. 
     Fifth, the flexibility to run the MOSFETs in subthreshold enables the iDACs to operate with ultra-low currents, even lower power supplies, and ultra-low power consumption suitable for mobile applications. 
     Sixth, there are no passive devices in the disclosed iDACs, and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Seventh, the disclosed multiple-channel data-converter method can be arranged free of clock, suitable for asynchronous (clock free) computation. 
     Eighth, the disclosed multiple-channel data-converter method utilize same type of MOSFET current sources and MOSFET switches which are symmetric and matched. Such arrangement facilitates device parameters to track each other over process-temperature-operation conditions variations. Accordingly, each of the data-coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced and matched between the plurality of data-converters. 
     Ninth and as stated earlier, the disclosed multiple-channel data-converter method substantially reduces the number of MOSFETs that for example form the iDAC&#39;s binary weighted current source network, and as such the fewer MOSFETs can be placed closer to each other on a chip. Similarly, oriented and physically closer MOEFETs, that form the current reference of a data-converter, generally match better which in turn improves the accuracy of each of the data-converter and the matching between them in plurality of iDACs in one chip. 
     Tenth, besides iDACs, the multiple-channel data-converter method can be applied to iADCs as well. Generally and all else substantially equal, the larger the W/L size of a FET current source, the larger its capacitance and the slower the node, which capacitively loads an iADC&#39;s current reference networks and can substantially reduce the speed of the iADC. As noted earlier, the multiple-channel data-converter method enables decoupling the weight of a current source from the scaling of the sizes of FETs utilizing in forming the data-converter&#39;s reference current sources. By keeping each of the W/L sizes of the current source FETs the same at 1× and small for example (despite each of their binary weighted currents), the node capacitances of the iADC&#39;s reference current networks can be kept small which helps speeds up the dynamic response of the iADC. More importantly, in applications where plurality (sea of) iADCs are required, by keeping the size of the current reference network of each of the iADC small in the plurality of the iADCs, substantial die area savings can also be realized. 
     Eleventh, in an embodiment of the multiple-channel data-converter method wherein the central RBN is trimmed or calibrated for accuracy, the accuracy of each of the plurality of data-converters whose reference current network is biased from the same central RBN can be improved. 
     Twelfth, in an embodiment of the multiple-channel data-converter method wherein the central RBN is desensitized from power supply variations (e.g., by utilizing the second power supply desensitization method or the second PSR method disclosed in  FIG. 40  and  FIG. 41 ), the power supply insensitivity of each of the plurality of data-converters whose reference current network is biased from the same central RBN can be improved. 
     Thirteenth, the benefits of the multiple-channel data-converter method can be attained in other higher-order systems including but not limited to multipliers, multiply-accumulate (MAC), and artificial-neural-network (ANN) that utilize the multiple-channel data-converter method. 
     Section 20—Description of FIG.  20   
       FIG. 20  is a simplified circuit schematic illustrating an embodiment for a plurality-channels of mixed-mode digital-input to analog-current-output multiplier (XD i I o ) that is multi-quadrant, wherein the XD i I o  utilizes the multiple-channel data-converter method. The XD i I o  of  FIG. 20  (XD i I o     20   ) utilizes an embodiment of the multiple-channel data-converter method disclosed in section 19 of this disclosure, which can save silicon area and improve iDAC&#39;s dynamic performance. The XD i I o     20    also utilizes a multiplier power supply desensitization method (or XPSR method) that substantially desensitize XD i I o &#39;s output current from power supply variations, while eliminating cascodes from current sources (which saves area). 
     For descriptive clarity and illustrative simplicity, the embodiment of the XD i I o     20    that is depicted in  FIG. 20  is a single channel multiplier with 4-bits (x-word digital input) by 4-bits (y-word digital input) of resolution wherein the x and y digital words are sign-magnitude formatted, but the digital input resolutions can be higher (e.g., 6-bits to 12-bits) and the digital inputs can be arranged with other formats (e.g., binary, 2&#39;s complement, binary-offset, etc.) and plurality of channels can be in the 1000s. 
     As presented earlier, XD i I o     20    embodiment utilizes the multiple-channel data-converter method wherein a reference bias network (RBN 20 ) generates a sequence of reference bias currents that are mirrored onto a plurality of iDAC&#39;s current reference networks, which is described in section 19. The same RBN 20  can be utilized to mirror a reference current (Ir 20 ) whose value is programmed at the full-scale of Ix 20  and Iy 20 . 
     The XD i I o     20    is comprising of a first current-output DAC (iDAC) or iDACx 20  that generates an output Ix 20 , a second current-output iDAC or iDACy 20  that generates an out Iy 20 , wherein Ix 20 , Iy 20 , and a reference current (Ir 20 ) are inputted to a current multiplier or iMULT 20 . The resultant analog output product of iMULT 20  is Io 20  which is a single-quadrant current output. The Io 20  is then inputted to a switching current mirror inverter (comprising of P 1   s   20 , P 2   s   20 , NoM 20 , and NoM′ 20 ) section of the iMULT 20  which converts the single-quadrant Io 20  to a multi-quadrant output ±Io 20 , wherein the plus minus sign of Io 20  is controlled by the sign bits of the x and y digital input words (e.g., sign-magnitude format). 
     As noted earlier, the XD i I o &#39;s dynamic performance is improved and silicon area is reduced by utilizing the multiple-channel data-converter method that is described in section 19 of this disclosure. A single bias reference network (RBN 20 ) is shared by biasing a plurality XD i I o  channels, wherein each XD i I o  is comprising of iMULT (e.g., an iMULT 20 ) and pair of iDACs (e.g., iDACx 20  and iDACy 20 ). Here, substantially equal 1× sized current sources in the iDAC&#39;s reference current network is biased separately by RBN 20  wherein each iDAC&#39;s 1× sized current source carries its respective binary weighted current, which improves dynamic performance of the iDACs and save silicon area, especially in machine learning applications were 1000s (plurality) of iDACs can be needed to perform the multiply-accumulate (MAC) functions. 
     Note also that the sign-magnitude logic (LOGIC 20 ) block can be shared between plurality XD i I o  channels by inserting a plurality of latches (to store the x and y digital input words) between the LOGIC 20  block outputs and the plurality of current switches of the respective plurality of iDACx 20  and iDACy 20  pairs, which also saves silicon area. 
     Moreover, additional area is save by utilizing only one RBN 20  that is shared with a plurality of XD i I o     20   , wherein the multiplier power supply desensitization method (or XPSR method) is utilized to substantially desensitize each of the XD i I o     20   &#39;s output currents to V DD  variations, while the chip area attributed to each of the XD i I o     20    is reduced by eliminating the cascoded FETs from the current reference network of each of the iDACx 20  and iDACy 20  pairs. The XPSR method is described next. 
     The multiplier power supply desensitization method substantially desensitizes a multiplier from power supply variations by arranging a first ratio relationship between the first input (I Y ) and the reference input (I R ) to a multiplier wherein the I y  and the I R  both have a substantially equivalent first dependence error (e dd ) to power supply variations (ΔV DD ) and wherein the e dd  cancel each other out due to the first ratio (I y /I R ) relationship in a multiplier. Moreover, multiplier power supply desensitization method substantially desensitizes the multiplier from ΔV DD  by arranging a second ratio (I O /I X ) relationship between the output (I O ) and the second input (I X ) of the multiplier wherein the I O  and the I X  of the multiplier both have a substantially equivalent second dependence error (e′ dd ) to ΔV DD  and wherein the e′ dd  cancel each other out due to the I O /I X  relationship. Also, the I y /I R  is substantially equalized to I O /I X  in the multiplier, and the e dd  and the e′ dd  may be substantially equal or different from one another. This means that for example e dd  can be zero meaning I Y  and I R  have no dependence to power supply variations, and where e′ dd  can be finite meaning I O  and I x  have dependence to power supply variations, and vice versa. Moreover, for example, e dd  and e′ dd  can be zero meaning that I Y , I R , I o , and I x  do not have dependence to power supply variations. 
     Another way of describing the multiplier power supply desensitization (XPSR) method is as follows: An analog multiplier input-output transfer function is I O =I X ×I Y /I R  or I O /I x =I Y /I R , where X is x-input current, I Y  is y-input current, I R  is a reference input current representing the full scale of I X  and I Y , and I O  is the multiplier&#39;s output current. The multiplier power supply desensitization method arranges a multiplier where I O  and I x  can have similar dependence (error) on power supply (V DD ), and I Y  and I R  can have with other similar dependence (error) on V DD . In other words, I O =i o  (1±e dd ), I X =i x  (1±e dd ), I Y =i y  (1±e′ dd ), and I R =i r  (1±e′ dd ), wherein ±e dd  is the scale error attributed to V DD  variations for i o  and i x , and ±e′ dd  is the scale error attributed to V DD  variations for i y  and i r . As such, a scale error term (1±e dd ) attributed to V DD  variations is canceled out in the ratio of I O /I x . Similarly, a scale error terms (1±e′ dd ) attributed to V DD  variations are canceled out in the ratio of I y /I R . Also, note that ±e dd  can be the same as or different from ±e′ dd . 
     First, the XPSR method to help substantially desensitize a XD i I o  from the dependence error of I Y /I R  on power supply variations is described. Let&#39;s arrange the iDACy 20 &#39;s current switches (comprising of N 4   y′   20  through N 1   y′   20  and N 4   y″   20  through N 1   y″   20 ) with low on resistance. Also, let&#39;s arrange V 1   y   20 =V DD −Vgs PMOS  (e.g., placing a diode connected FET between V DD  and V 1   y   20 , which can help lower iDAC&#39;s glitch and improves settling time). One of the current outputs (Iy 20 ) of iDACy 20  that is coupled with the y-input port of iMULT 20  has a bias voltage of V DD  minus a PMOS&#39;s gate-to-source voltage (V gs  of PyM 20 ). Thus, the drain-to-source voltage (V DS ) of FETs in the current reference network of iDACy 20  (comprising of N 4   y   20  through N 1   y   20 ) is V DD −V gs . Be mindful that early voltage (V A ) in FETs can cause I DS  dependence (error) on power supply variations, wherein such I DS  dependence (error) can be reduced by cascading FETs at the expense of increasing silicon area. Accordingly, the iMULT 20 &#39;s current input Iy 20  is arranged in this disclosure to have a dependence error as a function of V DD  variations. Similarly, the reference current input (Ir 20 ) of iMULT 20  that is supplied by an NMOS (i.e., NrM 20 ) has a V DS  that is also V DD  minus V gs  of PrM 20 . As such, the current input that is Ir 20  of iMULT 20  is arranged to have a substantially similar dependence error as a function of V DD  variations to that of Iy 20 . Hence, the I y  and I R  have the same depended error on V DD  variations that is substantially rejected, without the need for cascode FETs (which saves silicon area) in light of iMULT 20  ratio relationship between them that is I y /I R . 
     Next, the XPSR method to help substantially desensitize a XD i I o  from the dependence error of I O /I x  on power supply variations is described. Similar to the y-channel, let&#39;s arrange the iDACx 20 &#39;s current switches (comprising of N 4   x′   20  through N 1   x′   20  and N 4   x″   20  through N 1   x″   20 ) with low on resistance. Similarly, let&#39;s arrange V 1   x   20 =V SS +Vgs NMOS  (which can help lower iDAC&#39;s glitch and improves settling time). One of the current outputs (Ix 20 ) of iDACx 20  that is coupled with the x-input port of iMULT 20  has a bias voltage of V SS  plus a NMOS&#39;s gate-to-source voltage (V gs  of NxM 20 ). Thus, the drain-to-source voltage (V DS ) of FETs in the current reference network of iDACx 20  (comprising of N 4   x   20  through N 1   x   20 ) is V SS +V gs . As such, the iMULT 20 &#39;s current input that is Ix 20  is arranged in this disclosure to have a dependence error as a function of V SS  variations. By biasing Vxy 20 =V SS +Vgs NMOS , then depending on sign (or MSB) of the x or y digital input word, the bias voltage of the current input (Io 20 ) of iMULT 20  would be subject to either V gs  of NoM 20  or that of NoM′ 20 , which are both NMOS. Thus, the iMULT 20 &#39;s current output that is Io 20  is arranged in this disclosure to have the same dependence error as a function of V SS  variations to that of Ix 20 . Hence, the I O  and I X  have the same depended error (on V SS  variations) that is substantially rejected in light of iMULT 20  ratio relationship between them that is I O /I X . 
     Bear in mind that for machine learning applications where plurality (or sea) of XD i I o  channels are required, the reference bias network (RBN) and LOGIC sections can be shared amongst plurality (or sea) of XD i I o  channels. The iDAC&#39;s current reference network can provide binary weighted currents without requiring the current sources to be sized in binary weighted arrangement which saves significant area in each iDAC utilized in XD i I o . Further area savings are realized by eliminating the cascoded FETs from the current (mirror) reference network of each iDAC utilized in XD i I o , while utilizing the PSR method substantially desensitizes the XD i I o  from power supply variations. 
     Each XD i I o  is substantially desensitized from power supply variations by utilizing the multiplier power supply desensitization method which is indicated by SPICE circuit simulations of  FIG. 29 . The  FIG. 29  simulations results are that of a XD i I o  similar to  FIG. 20  circuit with a resolution of 8-bits digital words instead of that of  FIG. 20  with a resolution of 4-bits digital words. A XD i I o  of  FIG. 29  is inputted with an 8-bit (x-word digital input) by an 8-bit (y-word digital input) wherein the x and y words are ramped from zero-scale to full scale where power supply V DD  is varied from 2.2V to 0.8V.  FIG. 29  illustrates a waveform plot that is the error curve (output current simulation minus output current ideal) attributed to I O  of the XD i I o  indicating less than ±0.5% error in DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error). 
     In summary, some of the benefits of the embodiment disclosed in  FIG. 20  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the disclosed embodiment benefits from savings in silicon die area, lower glitch, and faster speed when plurality of XD i I o  are required (e.g., in machine learning applications where 1000s of XD i I o  may be needed) by utilizing the multiple iDAC method that is disclosed in section 19. 
     Third, the disclosed embodiment benefits from further saving in silicon die area as well as desensitization to power supply variations for each XD i I o  by utilizing the multiplier power supply desensitization method, which also facilitates the elimination of the cascoded FETs in iDACs current reference network. 
     Section 21—Description of FIG.  21   
       FIG. 21  is a simplified circuit schematic illustrating an embodiment for a plurality-channels of mixed-mode digital-input to analog-current-output multiplier (XD i I o ) that is single-quadrant, wherein the XD i I o  utilizes the multiple-channel data-converter method. The XD i I o  of  FIG. 21  (XD i I o     21   ) utilizes another embodiment of the multiple-channel data-converter method disclosed in section 19 of this disclosure to save silicon area and improve iDAC&#39;s dynamic performance. The XD i I o     21    also utilizes another embodiment of the multiplier power supply desensitization method that substantially desensitize XD i I o &#39;s output current from power supply variations, while eliminating cascodes from current sources (which saves area). 
     For descriptive clarity and illustrative simplicity, the embodiment of the XD i I o     21    that is depicted in  FIG. 21  is a single channel multiplier with 3-bits (x-word digital input) by 3-bits (y-word digital input) of resolution wherein the x and y words are in binary format, but the digital input resolutions can be higher (e.g., 6-bits to 12-bits) and plurality of channels can be in the 1000s. Let&#39;s assume the iDACy 21 &#39;s current switches (comprising of N 4   y′   21  through N 1   y′   21  and N 4   y″   21  through N 1   y″   21 ) and the iDACx 21 &#39;s current switches (comprising of N 4   x′   21  through N 1   x′   21  and N 4   x″   21  through N 1   x″   21 ) have low on resistances. Also, let&#39;s arrange V 1   xy   21 =V DD −Vgs PMOS  (e.g., placing a diode connected FET between V DD  and Vxy 21 , which can help lower iDAC&#39;s glitch and improves settling time). Moreover, let&#39;s assume that V GSp &gt;&gt;V 15  of PxoM 21  and PyrM 21 , wherein V GSp  is gate-to-source voltage of a PMOS operating at full-scale current in iMULT 21 , 
     As asserted earlier, XD i I o     21    embodiment utilizes the multiple-channel method data-converter wherein a reference bias network (RBN 21 ) circuit generates a sequence of reference bias currents that are mirrored onto a respective plurality of iDAC&#39;s current reference networks, which is described in section 19. The same RBN 21  circuit can be utilized to mirror a fixed reference current (Ir 21 ) programmed at the full-scale of Ix 21  and Iy 21 . 
     The XD i I o     21    is comprising of iDACx 21  that generates an Ix 21 , and iDACy 21  that generates an Iy 21 , wherein Ix 21 , Iy 21 , and a reference current (Ir 21 ) are inputted to a current multiplier or iMULT 21 . The resultant analog output product of iMULT 21  is IoM 21 =Io 21  which is a single-quadrant current output. 
     Note that Ix 21  as output of iDACx 21  is coupled with x-input of iMULT 21  that is biased at about V DD −V GSp  where V GSp  is that of PxoM 21 . Similarly, Iy 21  as output of iDACy 21  is coupled with y-input of iMULT 21  that is also biased at about V DD −V GSp  where V GSp  is that of PyM 21 . Also, Ir 21  provided by NrM 21  is coupled with reference current input of iMULT 21  that is also biased at about V DD −V GSp  where V GSp  is that of PrM 21 . 
     As stated earlier, the XD i I o &#39;s dynamic performance is improved and silicon area is reduced by utilizing the multiple-channel data-converter method that is described in section 19 of this disclosure. A single bias reference network (RBN 21 ) is shared by biasing a plurality XD i I o  channels, wherein each XD i I o  is comprising of iMULT (e.g., an iMULT 21 ) and pair of iDACs (e.g., iDACx 21  and iDACy 21 ). Here, substantially equal 1× sized current sources in the iDAC&#39;s reference current network is biased separately by RBN 21  wherein each iDAC&#39;s 1× sized current source carries its respective binary weighted current. 
     Due to FET&#39;s early voltage (V A ), the I DS  of a current source made of one FET increases with increasing its V DS . As such I DS  of a current source FET is sensitive to V DD  variation, unless the current source is cascoded (to increase the FET&#39;s output impedance) which takes double the area for a given current source. The multiple-channel data-converter method of section 19 is combined with the XPSR method that was described in section 20, in order to (1) avoid the cascoded FETs, (2) substantially desensitize the multiplier from power supply variations, (3) reduce the size of iDAC&#39;s binary weighted current reference network. Such combination of methods is utilized in the embodiment of a RBN 21  &amp; PSR 21  circuit, wherein the RBN 21  &amp; PSR 21  circuit is shared with a plurality of XD i I o     21    channels. 
     Notice that the PSR circuit is comprised of identical sections that are repeated for each sequence of reference bias currents of RBN, and that each multiplier XD i I o     21    channel is comprised of iDACx 21 , iDACy 21 , and an iMULT 21 . 
     For example, the PSR 21  section of the MSB current of RBN 21  is comprising of P 4   c   21 , P 4   c′   21 , P 4   c″   21 , N 4   c   21 , and N 4   c′   21 . The MSB current of the RBN 21  circuit, which is set by the I DS  of N 4   r   21 , is mirrored through P 4   c   21  and the diode connected P 4   c′   21  where P 4   c″   21  regulates the current in N 4   c′   21  and its diode connected N 4   c   21  mirror while keeping the V GS  of P 4   c   21  and P 4   c′   21  substantially equalized. The V DS  of N 4   c′   21  is V DD −V GSp  with V GSp  being that of P 4   c′   21 . The PSR 21  section&#39;s regulation of the MSB current of RBN 21  kicks in when, for example, V DD  falls then I DS  of P 4   c″   21  increases which raises the operating current in N 4   c   21 , N 4   c′   21 , P 4   c′   21 , and P 4   c   21  until the I DS  of P 4   c   21  is substantially equalized with I DS  of N 4   r′   21 , which is independent of V DD  variations (since I DS  of N 4   r′   21  mirrors a multiple of the fixed reference current Ir′ 21 ). 
     In other words, when V DD  varies, the I DS  of N 4   c′   21  and P 4   c′   21  is regulated and independent of V DD  variations, despite N 4   c′   21 &#39;s V DS =V DD −V GSp  The V 4   r   21  that is the V GS  of N 4   c   21  and N 4   c′   21  programs the bus voltage that is coupled with the gate terminals of N 4   y   21  and N 4   x   21  which are the MSB current sources of the current reference network of iDACx 21  and iDACy 21 . Considering that the bias voltage at the drain terminals of N 4   y   21  and N 4   x   21  are coupled with the inputs of iMULT 21  which are about V DD −V GSp , the I DS  of the N 4   y   21  and N 4   x   21  is also independent of V DD  variations because they mirror N 4   c   21  and N 4   c′   21 . 
     Be mindful that the drain terminals of N 4   x   21  and N 4   y   21  (when selected in iDACs) are coupled with the x and y analog input current ports of iMULT 21 , respectively, whose bias voltages are arranged as V GSp  of PxoM 21  and PyM 21 . In summary, the MSB current sources of iDAC&#39;s current reference networks are arranged to be independent of V DD  variations, without cascoded FETs in iDAC&#39;s current reference network, and with the iDAC&#39;s binary weighted current reference network that is not sized in a binary weighted manner, combination of which saves substantial silicon area (especially in machine learning applications where 1000s of iDACs may be required). 
     Note that the same description as above is applicable to N 2   r   21 , N 2   r′   21  and N 1   r   21 , N 1   r′   21  that in conjunction with the regulating mechanism of their respective PSR 21  sections, generate the V 2   r   21  and V 1   r   21  bus voltages. 
     Thus, V 2   r   21  that is the V GS  of N 2   c   21  and N 2   c′   21  is the bus voltage that is coupled with the gate terminals of N 2   y   21  and N 2   x   21  which can be referred to as the second bit current sources of current reference network of iDACx 21  and iDACy 21 . The I DS  of N 2   y   21  and N 2   x   21  is also independent of V DD  variations, without cascoded FETs, as explained above. 
     Similarly, V 1   r   21  that is the V GS  of N 1   c   21  and N 1   c′   21  is the bus voltage that is coupled with the gate terminals of N 1   y   21  and N 1   x   21  which are the LSB current sources of current reference network of iDACx 21  and iDACy 21 . Accordingly, I DS  of N 1   y   21  and N 1   x   21  is independent of V DD  variations, without cascoded FETs. As indicated earlier, V 4   r   21 , V 2   r   21 , and V 1   r   2i  are bus voltages in the reference bias network (RBN) that set the sequence of reference bias currents for plurality of iDACs (e.g., there can be 1000s if iDACs sharing the sequence bus voltages generated by the same RBN). 
     In summary, the sequence of reference bias currents generated in the RBN circuit are substantially desensitized from V DD  variations by the PSR circuit before they are mirrored onto the iDAC&#39;s current reference networks. As such, iDAC&#39;s output currents are arranged to be independent of V DD  variations, without cascoded FETs in iDAC&#39;s current reference network which save silicon area. 
     As presented in section 20, the iMULT 21 &#39;s input output transfer function follows the Iy 21 /Ir 21 =Io 21 /Ix 21  relationship. The Iy 21 /Ir 21  is substantially desensitized to V DD  variations, since iDACy 21  current output that is Iy 21  and Ir 21  are substantially desensitized to V DD  variations without cascoded FETs, as explained earlier. 
     The iDACx 21  current output is also substantially desensitized to V DD  variations without cascoded FETs. The PoM 21  is cascoded with PoM′ 21  to increase the output impedance of output port of iMULT 21  and substantially desensitized Io 21  to V DD  variations. Also, PxM 21  is cascoded with PxM′ 21  to help match the V DS  of PxM 21  and PoM 21 , which helps with Io 21 /Ix 21  insensitivity to V DD  variations. 
     Each XD i I o  is substantially desensitized from power supply variations by utilizing another embodiment of the multiplier power supply desensitization method that is indicated by SPICE circuit simulations of  FIG. 28 . It is the simulations results of a XD i I o  similar to that of  FIG. 21 , but with a resolution of 8-bits digital words instead of that of  FIG. 21  with a resolution of 3-bits digital words. A XD i I o  of  FIG. 29  is inputted with an 8-bit (x-word digital input) by an 8-bit (y-word digital input) wherein the x and y words are ramped from zero-scale to full scale where power supply V DD  is varied from 2.2V to 0.8V.  FIG. 28  illustrates a waveform plot that is the error curve (output current simulation minus output current ideal) attributed to I O  of the XD i I o  indicating less than ±0.75% error in DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error). 
     In summary some of the benefits of the embodiment disclosed in  FIG. 21  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the disclosed embodiment benefits from savings in silicon die area, lower glitch, and faster speed when plurality of XD i I o  are required (e.g., in machine learning applications where 1000s of XD i I o  may be needed) by utilizing the multiple iDAC method that is disclosed in section 19. 
     Third, the disclosed embodiment benefits from further saving in silicon die area as well as desensitization to power supply variations for each XD i I o  by utilizing another embodiment of the multiplier power supply desensitization method, which also facilitates the elimination of the cascoded FETs in iDACs current reference network. 
     Section 22A—Description of FIG.  22 A 
       FIG. 22A  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) iDAC versus the simulated output current (Io simulation ) of one of the iDAC channels as arranged similar to that of  FIG. 19  but with an 8-bit resolution. The reference bias network is not trimmed here. 
     Keeping in mind that 8-bit of resolution computes to about ±0.4% of accuracy,  FIG. 22  indicates DNL (differential non-linearity) and INL (integral non-linearity) of less than about ±0.5%. Note that the iDAC&#39;s digital input word span between zero and full scale. 
     Section 22B—Description of FIG.  22 B 
       FIG. 22B  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) iDAC versus the simulated output current (Io simulation ) of one of the iDAC channels as arranged similar to that of  FIG. 19  but with an 8-bit resolution. The two MSBs of the reference bias network (RBN) is trimmed here, which would improve the linearity of plurality of iDACs (that are biased from the same RBN). 
     Keeping in mind that 8-bit of resolution computes to about ±0.4% of accuracy,  FIG. 22  indicates DNL (differential non-linearity) and INL (integral non-linearity) of less than about ±0.25% which is roughly a factor of 4 improvement. Note that the iDAC&#39;s digital input word span between zero and full scale. 
     Section 23—Description of FIG.  23   
       FIG. 23  is a simplified circuit schematic illustrating an embodiment of a digital-input to analog-current-output multiplier (XD i I o ) that operate in current mode comprising of an iDACx 23  whose analog-current-output supplies the reference input to an iDACy 23 . 
     For descriptive clarity and illustrative simplicity, the XD i I o     23   &#39;s resolution is arranged as a 3-bit (x-channel for iDACx 23 ) by 3-bit (y-channel for iDACy 23 ), but the resolution can be higher (e.g., 16-bits). 
     A current reference (Ir′ 23 ) is inputted and mirrored onto iDACx 23 &#39;s binary weighed current reference network comprising of P 4   x   23  (scaled at 4×), P 2   x   23  (scaled at 2×), and P 1   x   23  (scaled at 1×). The iDACx 23 &#39;s digital inputs (Dx 23  digital word) are D 3   x   23  (as MSB) through D 1   x   23  (as LSB), which control iDACx 23 &#39;s analog current switches P 4   x′   23  through P 1   x′   23  and P 4   x″   23  through P 1   x″   23 . 
     The selected sums of iDACx 23 &#39;s analog current switch outputs are steered through node n 23  onto the reference input of iDACy 23 . 
     The iDACy 23 &#39;s binary weighed current reference network comprising of P 4   y   23  (scaled at 4×), P 2   y   23  (scaled at 2×), and P 1   y   23  (scaled at 1×) have their source terminals coupled together and floating on node n 23 . Moreover, note that the gate terminal of P 4   y   23 , P 2   y   23 , and P 1   y   23  are coupled together with Pr′ 23 &#39;s cascode bias voltage Vy′ 23 , which provides enough headroom for the iDACx 23 &#39;s binary weighed current reference network and improves its output impedance. Similarly, the iDACy 23 &#39;s digital inputs (Dy 23  digital word) are D 3   y   23  (as MSB) through D 1   y   23  (as LSB) control iDACy 23 &#39;s analog current switches P 4   y′   23  through P 1   y′   23  and P 4   y″   23  through P 1   y″   23 . The selected sums of iDACy 23 &#39;s analog current switch outputs are steered through the XD i I o     23    s current-output node IO 23  that generates the analog current product Ax 23 ×Ay 23 /Ar 23 , wherein Ax 23  is the analog current representation of the digital word Dx 23 , Ay 23  is the analog current representation of the digital word Dy 23 , and Ar 23  is a multiple of Ir′ 23 . 
     The disclosed XD i I o     23    benefits from current mode operations, which has been discussed in this disclosure. Another benefit of XD i I o     23    disclosure results from feeding the current output of a first iDAC directly into the reference port of a second iDAC, whose reference input port is floating. The floating iDAC method (that is utilized here) was describe in section 1 of this disclosure. Here, the source terminals of current reference FET network of the second iDAC are coupled together to arrange the floating reference port of the second iDAC. As such, a current mirror (to channel the first iDAC output current onto the second iDAC reference input port) is avoided, which saves area and improves accuracy since it avoids the mismatch associated with the said current mirror. 
     Section 24—Description of FIG.  24   
       FIG. 24  is a simplified circuit schematic illustrating another embodiment of mixed-mode digital-input to analog-current-output multiplier (XD i I o ) that operate in current mode comprising of an iDACx 24  whose analog-current-output supplies the reference input to an iDACy 24 . 
     For descriptive clarity and illustrative simplicity, the XD i I o     24   &#39;s resolution is arranged as a 3-bit (x-channel for iDACx 24 ) by 3-bit (y-channel for iDACy 24 ) but the resolution can be higher (e.g., 16-bits). 
     A current reference (Ir′ 24 ) is inputted and mirrored onto iDACx 24 &#39;s binary weighed current reference network comprising of P 4   x   24  (scaled at 4×), P 2   x   24  (scaled at 2×), and P 1   x   24  (scaled at 1×). The iDACx 24 &#39;s digital inputs (Dx 24  digital word) are D 3   x   24  (as MSB) through D 1   x   24  (as LSB), which control iDACx 24 &#39;s analog current switches P 4   x′   24  through P 1   x′   24  and P 4   x″   24  through P 1   x″   24 . 
     Note that the embodiment of  FIG. 24  does not arrange iDACx 24 &#39;s analog current switches is series with the binary weighed current reference network path. Instead, iDACx 24 &#39;s analog current switches are enabled (turned on) by switch coupling with the gate terminal of Pr 24  or disabled (turned off) by switch coupling with V DD . For example, when D 3   x   24  digital value is high (on), then the analog current switch P 4   x′   24  is on and the analog current switch P 4   x″   24  is off, which causes P 4   x   24 &#39;s binary weighted MSB current (scaled and mirrored by P 4   x   24 -Pr 24  current mirror) to flow onto the iDACx 24  current output port that is node n 24 . Conversely, for example, when D 3   x   24  digital value is low (off), then the analog current switch P 4   x′   24  is off and the analog current switch P 4   x″   24  is on, which shuts off P 4   x   24  and blocks its&#39; binary weighted MSB current from flowing onto the iDACx 24  current output port that is node n 24 . The same principle of operations applies to the other bits of iDACx 24 . 
     The selected sums of iDACx 24 &#39;s analog current switch outputs are steered through the floating node n 24  and onto the reference input of iDACy 24 . 
     The iDACy 24 &#39;s binary weighed current reference network comprising of P 4   y   24  (scaled at 4×), P 2   y   24  (scaled at 2×), and Ply 24  (scaled at 1×) have their source terminals coupled together and floating on node n 24 . Moreover, be mindful that the gate terminal of P 4   y   24 , P 2   y   24 , and Ply 24  are coupled together with Pr′ 24 &#39;s cascode bias voltage Vy′ 24 , which provides enough headroom for the iDACx 24 &#39;s binary weighed current reference network and improves its output impedance. Similarly, the iDACy 24 &#39;s digital inputs (Dy 24  digital word) are D 3   y   24  (as MSB) through D 1   y   24  (as LSB) control iDACy 24 &#39;s analog current switches P 4   y′   24  through Ply′ 24  and P 4   y″   24  through P 1   y″   24 . The selected sums of iDACy 24 &#39;s analog current switch outputs are steered through the XD i I o     24   &#39;s current-output node IO 24  that generates the analog current product Ax 24 ×Ay 24 /Ar 24 , wherein Ax 24  is the analog current representation of the digital word Dx 24 , Ay 24  is the analog current representation of the digital word Dy 24 , and Ar 24  is a multiple of Ir′ 24 . 
     The disclosed XD i I o     24    benefits from current mode operations, which has been discussed in this disclosure. Another benefit of XD i I o     24    disclosure results from feeding the current output of a first iDAC directly into the reference port of a second iDAC, whose reference input port is floating. The floating iDAC method, which is utilized here, was describe in section 1 of this disclosure. Here, the source terminals of current reference FET network of the second iDAC are coupled together to arrange the floating reference port of the second iDAC. As such, a current mirror (to channel the first iDAC output current onto the second iDAC reference input port) is avoided, which saves area and improves accuracy since it avoids the mismatch associated with the said current mirror. 
     Section 25—Description of FIG.  25   
       FIG. 25  is a simplified circuit schematic illustrating another embodiment of a digital-input to analog-current-output multiplier (XD i I o ) that operate in current mode. The XD i I o     25    is comprising of a first current-output iDACx 25  whose analog-current-output supplies the reference input to an iDACy 25 , while a power supply desensitization circuit (PSR 25 ) substantially desensitize the XD i I o     25   &#39;s output current to V DD  variations wherein silicon area is saved by eliminating the need for cascoded FETs in the iDACs. 
     For descriptive clarity and illustrative simplicity, the XD i I o     25   &#39;s resolution is arranged as a 3-bit (x-channel for iDACx 25 ) by 3-bit (y-channel for iDACy 25 ) but the resolution can be higher (e.g., 16-bits). 
     A current reference (Ir′ 25 ) is inputted and mirrored onto iDACx 25 &#39;s binary weighed current reference network comprising of P 4   x   25  (scaled at 4×), P 2   x   25  (scaled at 2×), and P 1   x   25  (scaled at 1×). The iDACx 25 &#39;s digital inputs (Dx 25  digital word) are D 3   x   25  (as MSB) through D 1   x   25  (as LSB), which control iDACx 25 &#39;s analog current switches P 4   x′   25  through P 1   x′   25  and P 4   x″   25  through P 1   x″   25 . 
     Be mindful that generally cascoded FETs are utilized in an iDAC&#39;s current reference network to increase its output impedance and substantially desensitize an iDAC&#39;s output current from power supply variations. 
     Here, the selected sums of iDACx 25 &#39;s analog current switch outputs are steered through node n 25  onto a power supply desensitization circuit (PSR 25 ). One of the objectives of PSR 25  is to substantially desensitize the output current of XD i I o     25    from power supply variations, wherein the cascode FETs are eliminated from the binary weighted current reference network of iDACx 25  and iDACy 25 . Without the cascode FETs, the binary weighted current reference network net-net area is reduced substantially compared to the added area of PSR 25  (and hence the overall area of XD i I o     25    is reduced). 
     In the disclosed embodiment of  FIG. 25 , the PSR 25  receives the iDACx 25  output current at node n 25  whose DC voltage is biased at V DD -VGS pq     25   . As such the binary weighted current reference network output of iDACx 25  (at node n 25 ) tracks the Ir′ 25  (that is a fixed reference current and independent of V DD  by design), wherein iDACx 25  output port is also biased at V DD −VGS pr     25   , which substantially desensitizes iDACx 25 &#39;s output current from V DD  variations. Without the PSR 25  and without the cascoded FETs, the iDACy 25 &#39;s output current would vary with V DD  since the drain-to-source voltage (V DS ) of iDACy 25 &#39;s binary weighted current reference network (N 4   y   25 , N 2   y   25 , and N 1   y   25 ) is subject to V DD  variations and the DC bias voltage of IO 25  port (e.g., V IO     25   =V DD −V GS ). Notice that the V DS  of Pq′ 25  is V DD −VGS Nq     25    and V DS  of Nq′ 25  is V DD −VGS pq     25   . To substantially desensitize the output current of iDACy 25  (without its&#39; cascoded FETs), Pq′ 25  regulates the current through Nq 25  and Nq′ 25  until I DS  of Nq′ 25  and the output current of iDACx 25  (flowing through node n 25 ) are substantially equalized. The I DS  of Nq′ 25  is mirrored onto the current reference network of iDACy 25  (stripped from cascoded FETs to save area), and accordingly the current output of iDACy 25  which is the analog current output of D i I O     25    is substantially desensitized from V DD  variations. 
     The iDACy 25 &#39;s binary weighed current reference network comprising of N 4   y   25  (scaled at 4×), N 2   y   25  (scaled at 2×), and N 1   y   25  (scaled at 1×) are scaled and mirrored to I DS  of Nq′ 25 , and Nq 25 . Here also, the iDACy 25 &#39;s digital inputs (Dy 25  digital word) are D 3   y   25  (as MSB) through D 1   y   25  (as LSB) control iDACy 25 &#39;s analog current switches N 4   y′   25  through N 1   y′   25  and N 4   y″   25  through N 1   y″   25 . The selected sums of iDACy 25 &#39;s analog current switch outputs are steered through the XD i I o     25   &#39;s current-output node IO 25 . The iDACy 25 &#39;s output generates the equivalent analog output current product Ax 25 ×Ay 25 /Ar 25 , wherein Ax 25  is the analog current representation of the digital word Dx 25 , Ay 25  is the analog current representation of the digital word Dy 25 , and Ar 25  is a scaled Ir′ 25 . Again, consider that node IO 25  can be biased at a V GS  below V DD . 
     The disclosed XD i I o     25    benefits from current mode operations, which has been discussed in this disclosure. Another benefit of XD i I o     25    is having a smaller area by utilizing a method of rejecting power supply variations by regulating the first iDAC&#39;s output current before it is fed onto the reference input the second iDAC, wherein the iDAC&#39;s current reference networks are stripped from cascoded FETs. This power supply desensitization method utilized in XD i I o     25    (via the embodiment of a power supply desensitization circuit PSR 25 ) substantially desensitizes XD i I o     25   &#39;s output from V DD  variations, wherein the cascoded FETs (in the iDAC&#39;s current reference networks) are eliminated, which saves silicon area and lowers cost. 
     Section 26—Description of FIG.  26   
       FIG. 26  is a simplified circuit schematic illustrating another embodiment of a digital-input to analog-current-output multiplier (XD i I o ) that operate in current mode. The XD i I o     26    is comprising of an iDACx 26  whose analog-current-output supplies the reference input to a power supply desensitization circuit (PSR 26 ) that biases the current reference network of the iDACy 26 . Here, PSR 26  substantially desensitize the XD i I o     26   &#39;s output current to V DD  variations, while the iDAC&#39;s current reference network areas are reduced by eliminating the cascoded FETs. 
     For descriptive clarity and illustrative simplicity, the XD i I o     26   &#39;s resolution is arranged as a 3-bit (x-channel for iDACx 26 ) by 3-bit (y-channel for iDACy 26 ) but the resolution can be higher (e.g., 16-bits). 
     A current reference (Ir′ 26 ) is inputted and mirrored onto iDACx 26 &#39;s binary weighed current reference network comprising of P 4   x   26  (scaled at 4×), P 2   x   26  (scaled at 2×), and P 1   x   26  (scaled at 1×). The iDACx 26 &#39;s digital inputs (Dx 26  digital word) are D 3   x   26  (as MSB) through D 1   x   26  (as LSB), which control iDACx 26 &#39;s analog current switches P 4   x′   26  through P 1   x′   26  and P 4   x″   26  through P 1   x″   26 . 
     The selected sums of iDACx 26 &#39;s analog current switch outputs are steered through node n 26  onto a power supply desensitization circuit (PSR 26 ). Similar to the disclosure in section 25, one of the objectives of PSR 26  is to substantially desensitize the output current of DD i I O     26    from power supply variations, while the cascode FETs are eliminated from the binary weighted current reference network of iDACx 26  and iDACy 26 . By eliminating the cascode FETs from the binary weighted current reference network, net-net the area of iDACx 26  and iDACy 26  is substantially reduced compared to the added area of PSR 26  (and hence the overall area of XD i I o     26    is reduced). 
     Consider that cascoded FETs may be needed in an iDAC&#39;s current reference network to increase its output impedance and substantially desensitize an iDAC&#39;s output current from power supply variations. Here, the PSR 26  receives the iDACx 26  output current at node n 26  whose DC voltage is biased at V DD −V GS     P    wherein V GS     P    is that of Pq 26 . The Ir′ 26  (that is independent of V DD  by design) is biased at V DD −VGS Pr     26    where Ir′ 26 &#39;s current biases the binary weighted current reference network of iDACx 26 . As such, the reference current input port and the current output (at node n 26 ) of iDACx 26  are biased at V DD −V GS     P    and track each other, which therefore helps iDACx 26  output current to be substantially desensitized from V DD  variations. 
     Moreover, keep in mind that without the PSR 26  and without the cascoded FETs, the iDACy 26 &#39;s output current would also vary with V DD  since the drain-to-source voltage (V DS ) of iDACy 26 &#39;s binary weighted current reference network (N 4   y   26 , N 2   y   26 , and N 1   y   26 ) is subject to V DD  variations and the DC bias voltage of IO 26  port (e.g., V IO     26   =V DD −V GS ). Note that the V DS  of Pq″ 26  is V DD −VGS Nq     26    and V DS  of Nq 26  is V DD −VGS Pq     26   . As such, to substantially desensitize the output current of iDACy 26  (without cascoded FETs), the inverting current amplifier comprising of Pq 26 , Pq′ 26 , and Pq″ 26  regulates the currents through Nq″ 26  and Nq 26  until I DS  of Nq 26  and the output current of iDACx 26  (flowing through node n 26 ) are substantially equalized. The I DS  of Nq″ 26  and Nq 26  are mirrored onto the current reference network of iDACy 26  (stripped from cascoded FETs to save area), and accordingly the current output of iDACy 26  that is the analog current output of XD i I o     26    is substantially desensitized from V DD  variations. 
     The iDACy 26 &#39;s binary weighed current reference network comprising of N 4   y   26  (scaled at 4×), N 2   y   26  (scaled at 2×), and N 1   y   26  (scaled at 1×) are scaled and mirrored to I DS  of Nq″ 26 , Nq 26 . Here also, the iDACy 26 &#39;s digital inputs (Dy 26  digital word) are D 3   y   26  (as MSB) through D 1   y   26  (as LSB) control iDACy 26 &#39;s analog current switches N 4   y′   26  through N 1   y′   26  and N 4   y″   26  through N 1   y″   26 . The selected sums of iDACy 26 &#39;s analog current switch outputs are steered through the XD i I o     26   &#39;s current-output node IO 26  that generates the equivalent analog output current product Ax 26 ×Ay 26 /Ar 26 , wherein Ax 26  is the analog current representation of the digital word Dx 26 , Ay 26  is the analog current representation of the digital word Dy 26 , and Ar 26  is a scaled Ir′ 26 . Again, notice that node IO 26  can be biased at a V GS  below V DD . 
     The disclosed XD i I o     26    benefits from current mode operations, which has been discussed in this disclosure. Another benefit of XD i I o     26    is having a smaller area by utilizing the method of rejecting power supply variations by regulating iDACx 26  output current before it is fed onto the reference input of iDACy 26 , wherein both iDAC&#39;s binary weighted current reference networks are stripped from cascoded FETs. The disclosed embodiment of power supply desensitization method in PSR 26  is utilized in XD i I o     26    which substantially desensitizes iDACx 26  output current from V DD  while PSR 26  regulates iDACy 26 &#39;s reference input current. Thus, the output current of the overall multiplier is substantially desensitized from power supply variations and the cascoded FETs (in both of the iDAC&#39;s current reference networks) are eliminated which saves area and lowers cost. 
     Section 27—Description of FIG.  27   
       FIG. 27  is a simplified circuit schematic illustrating another embodiment of mixed-mode digital-input to analog-current-output multiplier (XD i I o ) that operate in current mode comprising of a first current-output iDAC or iDACx 27  whose analog-current-output supplies the reference input to a second current-output iDAC or iDACy 27 . 
     For descriptive clarity and illustrative simplicity, the XD i I o     27   &#39;s resolution is arranged as a 3-bit (x-channel for iDACx 27 ) by 3-bit (y-channel for iDACy 27 ), but the resolution can be higher (e.g., 16-bits). 
     A current reference (Ir′ 27 ) is inputted and mirrored onto iDACx 27 &#39;s binary weighed current reference network comprising of P 4   27  (scaled at 4×), P 2   27  (scaled at 2×), and P 1   27  (scaled at 1×). The iDACx 27 &#39;s digital inputs (Dx 27  digital word) are D 3 X 27  (as MSB) through D 1 X 27  (as LSB), which control iDACx 27 &#39;s analog current switches P 4 ′ 27  through P 1 ′ 27  and P 4 ″ 27  through P 1 ″ 27 . For example, when D 3   x   27  is in a low state, current switch P 4 ″ 27  turns on and all of P 4   27 &#39;s current flows through P 4 ″ 27  into Vx 27  (which can be coupled with V SS ). Conversely, when D 3   x   27  is in a high state, current switch P 4 ″ 27  turns off and all of P 4   27 &#39;s current flows through P 4 ′ 27  into node n 27  (which is the current output port of iDACx 27 ). Note also that gate terminals of FETs comprising of P 4 ′ 27  through P 1 ′ 27  are coupled to a fixed bias voltage (Vx′ 27 ), and as such, these FETs can serve as analog current switch as well as cascoded FETs that increase the output impedance of iDACx 27 &#39;s current reference network. The output current of iDACx 27  is fed onto Ny 27  to function in a current mirror supplying the current reference input of iDACy 27 . 
     The iDACy 27 &#39;s binary weighed current reference network comprising of N 4   27  (scaled at 4×), N 2   27  (scaled at 2×), and N 1   27  (scaled at 1×) are scaled and mirrored to I DS  of Ny 27 . Here also, the iDACy 27 &#39;s digital inputs (Dy 27  digital word) are D 3   y   27  (as MSB) through D 1   y   27  (as LSB) that control iDACy 27 &#39;s analog current switches N 4 ′ 27  through N 1 ′ 27  and N 4 ″ 27  through N 1 ″ 27 . Similar to the arrangement in iDACx 27 , here for example, when D 3   y   27  is in a high state, current switch N 4 ′ 27  turns on and all of N 4   27 &#39;s current flows through N 4 ′ 27  into IO 27  port. Conversely, when D 3   y   27  is in a low state, current switch N 4 ′ 27  turns off and all of N 4   27 &#39;s current flows through N 4 ″ 27  and onto Vy 27  (which can be coupled with V DD ). Note also that gate terminals of FETs comprising of N 4 ″ 27  through N 1 ″ 27  are coupled to a fixed bias voltage (Vy″ 27 ), and as such, these FETs serve as analog current switch as well as cascode that increase the output impedance of iDACy 27 &#39;s current reference network. The selected sums of iDACy 27 &#39;s analog current switch outputs are steered through the XD i I o     27   &#39;s current-output node IO 27  that generates the equivalent analog output current product Ax 27 ×Ay 27 /Ar 26 , wherein Ax 27  is the analog current representation of the digital word Dx 27 , Ay 27  is the analog current representation of the digital word Dy 27 , and Ar 27  is a scaled Ir′ 27 . 
     The disclosed XD i I o     27    benefits from current mode operations, which has been discussed in this disclosure. Another benefit of XD i I o     27    is having a smaller area by utilizing the same FETs as current switches of each iDAC and as cascoded FETs (to increase the iDAC&#39;s current reference network&#39;s output impedance). 
     Section 28—Description of FIG.  28   
       FIG. 28  is a circuit simulations showing the error waveform (output current SPICE simulation minus output current ideal) attributed to the output current (I O ) of a XD i I o  that is arranged similar to that of  FIG. 21  but having an 8-bit digital inputs instead of 3-bits. 
     As noted, the XD i I o  circuit (whose simulation is provided in  FIG. 28 ) is inputted with an 8-bit (x-word digital input) by an 8-bit (y-word digital input) wherein the x and y words are ramped from zero-scale to full scale while power supply V DD  is varied from 2.2V (the upper waveform of  FIG. 28 ) to 0.8V (the lower waveform of  FIG. 28 ). 
       FIG. 28  illustrates a waveform plot that is the error curve (i.e. XD i I o &#39;s output current I O  simulation minus XD i I o &#39;s output current I O  ideal) indicating under ±0.75% error in DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error).  FIG. 28  indicates that the XD i I o  with 8-bit digital inputs is substantially desensitized from power supply variations by utilizing the multiplier power supply desensitization method. 
     Section 29—Description of FIG.  29   
       FIG. 29  is a circuit simulations showing the error waveform (output current SPICE simulation minus output current ideal) attributed to the output current (I O ) of a XD i I o  that is arranged similar to that of  FIG. 20  but having an 8-bit digital inputs instead of 4-bits. 
     As noted, the XD i I o  circuit whose simulation is provided in  FIG. 29  is inputted with an 8-bit (x-word digital input) by an 8-bit (y-word digital input) wherein the x and y words are ramped from zero-scale to full scale where power supply V DD  is varied from 2.2V (the upper waveform of  FIG. 29 ) to 0.8V (the lower waveform of  FIG. 29 ). 
       FIG. 29  illustrates a waveform plot that is the error curve (i.e. XD i I o &#39;s output current I O  simulation minus XD i I o &#39;s output current I O  ideal) indicating under ±0.5% error in DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error).  FIG. 29  indicates that the XD i I o  with 8-bit digital inputs is substantially desensitized from power supply variations by utilizing the multiplier power supply desensitization method. 
     Section 30—Description of FIG.  30   
       FIG. 30  is a simplified circuit schematic illustrating another embodiment for a plurality-channels of mixed-mode digital-input to analog-current-output multiplier (XD i I o ) that is single-quadrant, wherein the XD i I o  utilizes the multiple-channel data-converter method. The XD i I o  of  FIG. 30  (XD i I o     30   ) utilizes another embodiment of the multiple-channel data-converter method disclosed in section 19 of this disclosure to save silicon area and improve iDAC&#39;s dynamic performance. The XD i I o     30    also utilizes another embodiment of the multiplier power supply desensitization method (or XPSR method) disclosed in section 20 that substantially desensitize XD i I o &#39;s output current from power supply variations, while eliminating cascodes from current sources (which saves area). 
     The overall description of XD i I o  provided in section 21 (illustrated in  FIG. 21 ) is applicable to the XD i I o     30    here. The iDACs and iMULT between  FIG. 21  and  FIG. 30  are identical. Thus, the description provided in section 21 (illustrated in  FIG. 21 ) about the iDACs is applicable to pairs of iDACx 30  and iDACy 30 . Also, the description provided in section 21 (illustrated in  FIG. 21 ) about the iMULT is applicable to iMULT 30 . 
     The embodiment of RBN 30  &amp; PSR 30  utilizes another combination of the multiple-channel data-converter method disclosed in section 19 and the XPSR method disclosed in section 20. In the embodiment of RBN 30  &amp; PSR 30  illustrated in  FIG. 30 , substantial area savings are realized by eliminating the cascode from current sources in iDACx 30 , iDACy 30 , iMULT 30 , and the RBN 30  circuits, while the output current of XD i I o     30    is substantially desensitized from V DD  variations. This is done by regulating the reference bias currents of RBN 30  so that the outputs of iDACx 30  and iDACy 30  (which supplies a pair of the input currents to iMULT 30 ) as well as the reference current input to the iMULT 30  are substantially desensitized to power supply variations, and wherein the voltage at the inputs of iMULT 30  substantially track power supply voltage variations. The power supply desensitization mechanism is explained as follows: 
     Bear in mind that FET early voltage (V A ) causes the FET&#39;s I DS  to vary with varying the FET&#39;s V DS . The V DS  of the N 4   y   30  is about a V GS  of PyoM 30  below V DD , assuming low on resistance (low voltage drop) across iDACx 30  current reference network current switches (N 4   y′   30  and N 4   y″   30 ) which causes the I DS  of the N 4   y   30  to vary. The gate port of N 4   y   30  is coupled with a diode connected N 4   r   30  (whose V DS  and V GS  are substantially equal). The I DS  of the N 4   r   30  would vary with changes in V DD  since the V DS  of P 4   r   30  is about V DD  minus V GS  of N 4   r   30 . The disclosed power supply desensitization circuit (PSR 30 ) emulates a similar signal path from the gate port of P 4   r   30  to gate port of PyoM 30  (which is the output of iDACx 30  and the input of iMULT 30 ). This is done for the current input of iMULT 30  to be insensitive to power supply variations, while all iMULT 30 , iDACx 30 , iDACy 30 , and RBN 30  current sources are without cascodes, which saves substantial silicon area. 
     This is how the PSR 30  circuit emulates a similar signal path from the gate port of P 4   r   30  to gate port of PyoM 30 : The fixed current reference Ir′ 30  is mirrored between Pc′ 30  and Pc″ 30  whose V DS  is V GS  of a PMOS and tracks each other with changes in V DD . The I DS  of diode connected Pc″ 30  changes with V DD  variations in light of V DS  of the Nc′ 30  being V DD  minus V GS  of Pc″ 30 . The Nc′ 30  and diode connected Nc 30  are mirrors, wherein V DS  of Pc 30  is V DD  minus the V GS  of Nc 30  which causes the I DS  of Nc 30  to change with V DD . Now, PcR 30  substantially equalizes Ir′ 30  with the I DS  of Pc′ 30  by regulating the current in Nc″ 30  that is mirrored onto Nr′ 30  which regulates the gate voltage (and thus the I DS ) of Pr′ 30  and Pc 30  as well as the gate voltage (and thus the I DS ) of P 4   r   30 , P 2   r   30 , and P 1   r   30 . Also, consider that I DS  of P 4   r   30 , P 2   r   30 , and P 1   r   30  (establishes the bus voltages V 4   r   30 , V 2   r   30 , and V 1   r   30 ) generate the sequence of reference bias currents from the reference bias network (RBN 30 ). 
     In summary some of the benefits of the embodiment disclosed in  FIG. 30  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the disclosed embodiment benefits from savings in silicon die area, lower glitch, and faster speed when plurality of XD i I o  are required (e.g., in machine learning applications where 1000s of XD i I o  may be needed) by utilizing the multiple iDAC method that is disclosed in section 19. 
     Third, the disclosed embodiment benefits from further saving in silicon die area as well as desensitization to power supply variations for each XD i I o  by combining the multiple iDAC method with another embodiment of the multiplier power supply desensitization method, which also facilitates the elimination of the cascoded FETs in iDACs current reference network as well as the PSR circuit. 
     Section 31—Description of FIG.  31   
       FIG. 31  is a circuit simulations showing the error waveform (output current SPICE simulation minus output current ideal) attributed to the output current (I O ) of a XD i I o  that is arranged similar to that of  FIG. 30  but having an 8-bit digital inputs instead of 3-bits. 
     As noted, the XD i I o  circuit whose simulation is provided in  FIG. 31  is inputted with an 8-bit (x-word digital input) by an 8-bit (y-word digital input) wherein the x and y words are ramped the opposite of one another between zero-scale to full scale where power supply V DD  is varied from 2V (the upper waveform of  FIG. 31 ) to 1V (the lower waveform of  FIG. 31 ). 
       FIG. 31  illustrates a waveform plot that is the error curve (i.e. XD i I o &#39;s output current I O  simulation minus XD i I o &#39;s output current I O  ideal) indicating under ±1% error in DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error) for V DD =2v and V DD =1v, respectively.  FIG. 31  indicates that the XD i I o  with 8-bit digital inputs is substantially desensitized from power supply variations by utilizing the multiplier power supply desensitization method combined with the multiple iDAC method. 
     Section 32—Description of FIG.  32   
       FIG. 32  is a simplified block diagram illustrating a meshed digital-to-analog multiplication (mD i S o ) method. For clarity and not as a limitation, the mD i S o  method is described as receiving two digital words, each having 3-bits of resolution but the digital input word resolution can be higher (e.g., 16-bits). The digital input bits are meshed with analog circuitry, wherein the digital bits controls are meshed with the reference network to perform bit-weight attribution and summation in the analog domain. 
     The mD i S o  method of  FIG. 32  is inputted with two digital input words that are x-bits wide (e.g., Dx 32  word with x=3) and y-bits wide (e.g., Dy 32  word with y=3). The mD i S o  method is also inputted with a reference signal (Sr) that is scaled onto a bank of scaled reference networks (e.g., 1×Sr 32 , 2×Sr 32 , and 4×Sr 32 ). Plurality of y-channel sub-DACs (e.g., DAC 1   y   32 , DAC 2   y   32 , and DAC 3   y   32 ) each receiving the one respective bit of a y-digital input word (e.g., D 1   y   32 , D 2   y   32 , and D 3   y   32 ) control the steering (or transmission) of the scaled reference network to a plurality of x-channel sub-DAC&#39;s reference inputs (e.g., respective reference S R  inputs of DACx 1   32 , DACx 2   32 , and DACx 3   32 ), wherein each x-channel sub-DAC receives the same x-digital input word (e.g., D 1   x   32 , D 2   x   32 , and D 3   x   32 ). The outputs of x-channel sub-DACs are combined to generate the final analog multiplicand representation (Sxy 32 ) of the digital X·Y multiplications. Here, the analog output or S O  of DACx 1   32 , DACx 2   32 , and DACx 3   32  are combined together to generate Sxy 32 . Note that for a binary (linear) multiplier, the scaled reference network is also binarily weighted, but the reference network can be scaled in other fashions (e.g., equal weighted thermometer or non-linear or individually weighted, depending on the transfer function requirement of the end-application). 
     In summary, the binary weighted version of the meshed digital-to-analog multiplication method utilizes a multi-branch binary-weighted current reference network, wherein each of the first binary weighted reference current branches (y-branch) supply the current reference inputs of the sets of second binary weighted reference current branches (set of x-branches). Accordingly, the digital X word or Dx 32  and the digital Y word or Dy 32  control the respective sets of analog switches that steer (or transmit) the combined respective x-branch analog signals to an output port (e.g., Sxy 32 ). Keep in mind that, the X and Y word bits and their respective X and Y DAC channels here are interchangeable give the commutative property of multiplication. Benefits of utilizing the meshed digital-to-analog multiplication method is discussed in the embodiments of the said method, next. 
     Section 32′—Description of FIG.  32 ′ 
       FIG. 32 ′ is another simplified block diagram illustrating the meshed digital-to-analog multiplication (mD i S o ) method. For clarity and not as a limitation, the mD i S o  method here is also described as receiving two digital words, each having 3-bits of resolution but the digital input word resolution can be higher as in for example 16-bits. The digital input bits are also meshed with analog circuitry, wherein they control a reference network that is arranged to perform bit-weight attribution and summation in the analog domain. 
     The mD i S o  method of  FIG. 32 ′ is inputted with two digital input words that are x-bits wide (e.g., Dx 32′  word with x=3) and y-bits wide (e.g., Dy 32′  word with y=3). Here, the mD i S o  method is also inputted with a reference signal (Sr) that is scaled onto three banks of scaled reference networks (e.g., the y1-bank comprising of 0.5×Sr 32′ , Sr 32′ , and 2Sr 32′ ; the y2-bank comprising of Sr 32′ , 2Sr 32′ , and 4Sr 32′ ; and the y3-bank comprising of 2Sr 32′ , 4Sr 32′ , and 8Sr 32′ ). Plurality of y-channel sub-DACs (e.g., DAC 1   y   32′ , DAC 2   y   32′ , and DAC 3   y   32′ ) each receiving the one respective bit of a y-digital input word (e.g., D 1   y   32′ , D 2   y   32′ , and D 3   y   32′ ). 
     A clarification point regarding the  FIG. 32 ′ illustration: In sub-DAC 3   y   32′ , the digital bit D 3   y   32′  controls the 3 y-switches of sub-DAC 3   y   32′  whose inputs receive a sequence of scaled reference signals 8Sr 32′ , 4Sr 32′ , and 4Sr 32′ , wherein the 3 outputs of the sub-DAC 3   y   32′  are coupled to the 3 inputs of 3 x-switches of sub-DACx 3   32′  wherein the x-switches of sub-DACx 3   32′  are controlled by the digital x-word (e.g., D 1   x   32′  to D 3   x   32′  bits). Also, in sub-DAC 2   y   32′ , the digital bit D 2   y   32′  controls the 3 y-switches of sub-DAC 2   y   32′  whose inputs receive a sequence of scaled reference signals 4Sr 32′ , 2Sr 32′ , and 1Sr 32′ , wherein the 3 outputs of the sub-DAC 2   y   32′  are coupled to the 3 inputs of 3 x-switches of sub-DACx 2   32′  wherein the x-switches of sub-DACx 2   32′  are controlled by the digital x-word (e.g., D 1   x   32′  to D 3   x   32′  bits). Lastly, in sub-DAC 1   y   32′ , the digital bit D 1   y   32′  controls the 3 y-switches of sub-DAC 1   y   32′  whose inputs receive a sequence of scaled reference signals 2Sr 32′ , 1Sr 32′ , and 0.5Sr 32′ , wherein the 3 outputs of the sub-DAC 1   y   32′  are coupled to the 3 inputs of 3 x-switches of sub-DACx 1   32′  wherein the x-switches of sub-DACx 1   32′  are controlled by the digital x-word (e.g., D 1   x   32′  to D 3   x   32′  bits). 
     The D 1   y   32′  bit steers the three reference sources 0.5×Sr 32′ , Sr 32′ , and 2Sr 32′  onto the three switches of DACx 1   32′  which are controlled by D 1   x   32′ , D 2   x   32′ , and D 3   x   32′ , respectively. The D 2   y   32′  bit steers the three reference sources Sr 32′ , 2Sr 32′ , and 4Sr 32′  onto the three switches of DACx 2   32′  which are controlled by D 1   x   32′ , D 2   x   32′ , and D 3   x   32′ , respectively. And, the D 3   y   32′  bit steers the three reference sources 2Sr 32′ , 4Sr 32′ , and 8Sr 32′  onto the three switches of DACx 3   32′  which are controlled by D 1   x   32′ , D 2   x   32′ , and D 3   x   32′ , respectively. 
     The outputs of x-channel sub-DACs (e.g., DACx 1   32′ , DACx 2   32′ , and DACx 3   32′ ) are combined to generate the final analog multiplicand representation (Sxy 32′ ) of the digital X·Y multiplications. Here, the analog output or S O  of DACx 1   32′ , DACx 2   32′ , and DACx 3   32′  are added together to generate Sxy 32′ . Note that for a binary (linear) multiplier, the (three) banks of scaled reference network is also binarily weighted, but the reference network can be scaled in other fashions (e.g., thermometer or non-linear). 
     In summary, the binary weighted version of the meshed digital-to-analog multiplication method utilizes banks of multi-branch binary-weighted current reference network, wherein each of the Y-banks of the binary weighted reference current branches (y-branch) supply the current reference inputs of the sets of X-banks of the binary weighted reference current branches (set of x-branches). Accordingly, the digital X word or Dx 32′  and the digital Y word or Dy 32′  control the respective sets of analog switches that steer (or transmit) the combined respective x-branch analog signals to an output port (e.g., Sxy 32′ ). Keep in mind that, the X and Y word bits and their respective X and Y DAC channels here are interchangeable given the commutative property of multiplication. Benefits of utilizing the meshed digital-to-analog multiplication method is discussed in the embodiments of the said method, next. 
     Section 33—Description of FIG.  33   
       FIG. 33  is a simplified circuit schematic illustrating a digital-input to analog current output multiplier (XD i I o ) as a preferred embodiment of the meshed digital-to-analog multiplication (mD i S o ) method described in the prior section 32′ and illustrated in  FIG. 32 ′. Similarly, for clarity and not as a limitation, the XD i I o  multiplier is described as receiving two digital words, each having 3-bits of resolution wherein the digital input word resolution can be as high as 16-bits. 
     The XD i I o  multiplier of  FIG. 33  is inputted with two digital input words Dx 33  word (comprising of 3-bits D 1   x   33 , D 2   x   33 , and D 3   x   33 ) and Dy 33  word (comprising of 3-bits D 1   y   33 , D 2   y   33 , and D 3   y   33 ). 
     The XD i I o  multiplier here is also inputted with a reference current signal (Ir) that is scaled onto a scaled reference network, comprising of 3 banks namely: First scaled reference current bank I 1   r   33 =1×I r , I 2   r   33 =2×I r , and I 4   r   33 =4×I r . Second scaled reference current bank I 2   r′   33 =2×I r , I 4   r′   33 =4×I r , and I 8   r′   3 =8×I r . Third scaled reference current bank I 4   r″   33 =4×I r , I 8   r″   33 =8×I r , and I 16   r″   33 =16×I r . 
     A first y-channel sub-iDAC receives the first scaled reference bank (i.e., I 1   r   33 , I 2   r   33 , and I 4   r   33 ) at its current switch inputs that are the source-nodes of N 1   y   33 , N 1   y′   33 , and N 1   y″   33  whose gate-nodes are controlled by D 1   y   33  bit. Accordingly, I 1   r   33 , I 2   r   33 , and I 4   r   33  currents are respectively steered through, N 1   y   33 , N 1   y′   33 , and N 1   y″   33  which are gated by the D 1   y   33  bit, to provide the first x-channel sub-iDAC&#39;s reference input currents (in accordance with Dy 33  word). Consequently, the said first x-channel sub-iDAC reference currents are steered through current switches N 1   x   33 , N 2   x   33 , and N 3   x   33  that are controlled by the first x-channel DAC&#39;s digital inputs D 1   x   33 , D 2   x   33 , and D 3   x   33 . The drain-node currents of N 1   x   33 , N 2   x   33 , and N 3   x   33  are summed together and coupled to Ixy 33 , which is the analog current output port of XD i I o  multiplier. 
     Similarly, a second y-channel sub-iDAC receives the second scaled reference bank (i.e., I 2   r′   33 , I 4   r′   33 , and I 8   r′   33 ) at its current switch inputs that are the source-nodes of N 2   y   33 , N 2   y′   33 , and N 2   y″   33  whose gate-nodes are controlled by D 2   y   33  bit. Accordingly, I 2   r′   33 , I 4   r′   33 , and I 8   r′   33  currents are respectively steered through N 2   y   33 , N 2   y′   33 , and N 2   y″   33  which are gated by the D 2   y   33  bit, to provide the second x-channel sub-iDAC&#39;s reference input currents (in accordance with Dy 33  word). Consequently, the said second x-channel sub-iDAC reference currents are steered through current switches N 1   x′   33 , N 2   x′   33 , and N 3   x′   33  that are controlled by the second x-channel sub-DAC&#39;s same digital inputs D 1   x   33 , D 2   x   33 , and D 3   x   33 . The drain-node currents of N 1   x′   33 , N 2   x′   33 , and N 3   x′   33  are summed together and also coupled to Ixy 33 . 
     Also, a third y-channel sub-iDAC receives the second scaled reference bank (i.e., I 4   r″   33 , I 8   r″   33 , and I 16   r″   33 ) at its current switch inputs that are the source-nodes of N 3   y   33 , N 3   y′   33 , and N 3   y″   33  whose gate-nodes are controlled by D 3   y   33  bit. Accordingly, I 4   r″   33 , I 8   r″   33 , and I 16   r″   33  currents are respectively steered through, N 3   y   33 , N 3   y′   33 , and N 3   y″   33  which are gated by the D 3   y   33  bit, to provide the third x-channel sub-iDAC&#39;s reference input currents (in accordance with Dy 33  word). Consequently, the said third x-channel sub-iDAC reference currents are steered through current switches N 1   x″   33 , N 2   x″   33 , and N 3   x″   33  that are controlled by the third x-channel sub-DAC&#39;s same digital inputs D 1   x   33 , D 2   x   33 , and D 3   x   33 . The drain-node currents of N 1   x′   33 , N 2   x′   33 , and N 3   x′   33  are summed together and also coupled to Ixy 33 . 
     As noted above, the outputs of the first and second and third x-channel iDACs are summed at Ixy 33  to generate the analog multiplicand representation of X·Y digital multiplications. Note that for a binary (linear) multiplier, the scaled reference network (bank) is also binarily weighted, but the reference network can be scaled in other fashions (e.g., thermometer or non-linear). 
     In summary some of the benefits of the embodiment disclosed in  FIG. 33  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of XD i I o  multiplier is fast also in part because the scaled reference network banks are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where a first iDAC&#39;s output signal supplies the reference signal to a second iDAC, generally through a current mirror) is avoided which helps the speed. 
     Fourth, the minimum power supply can be very low since it is only limited by the drain-to-source voltage of current sources of the scaled reference network. 
     Section 34—Description of FIG.  34   
       FIG. 34  is a simplified circuit schematic illustrating another preferred embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in section 32 and section 32′, and illustrated in  FIG. 32  and  FIG. 32 ′, respectively. Similarly, for clarity and not as a limitation, the XD i I o  multiplier is described as receiving two digital words, each having 3-bits of resolution wherein the digital input word resolution can be as high as 16-bits. 
     The XD i I o  multiplier of  FIG. 34  is inputted with two digital input words Dx 34  word (comprising of 3-bits x 1   34 , x 2   34 , and x 3   34 ) and Dy 34  word (comprising of 3-bits y 1   34 , y 2   34 , and y 3   34 ). 
     The XD i I o  multiplier here is also inputted with a reference current signal (i r =Ir 34 ) that is mirrored and scaled (via Ny 34 ) onto a scaled reference network, comprising of 3 current sources: First scaled reference currents wherein the current through N 1   y   34 =1×i r  that is split according to a programmed weight scale between N 1   x   34  (e.g., scaled at 1×), N 2   x   34  (e.g., scaled at 2×), and N 3   x   34  (e.g., scaled at 4×). Second scaled reference currents wherein the current through N 2   y   34 =2×i r  that is split according to a programmed weight scale between N 1   x′   34  (e.g., scaled at 1×), N 2   x′   34  (e.g., scaled at 2x), and N 3   x′   34  (e.g., scaled at 4x). Third scaled reference currents wherein the current through N 3   y   34 =4×i r  that is split according to a programmed weight scale between N 1   x″   34  (e.g., scaled at 1×), N 2   x″   34  (e.g., scaled at 2×), and N 3   x″   34  (e.g., scaled at 4×). 
     A first y-channel sub-iDAC receives the first scaled reference currents (i.e., I D  of N 1   x   34 , N 2   x   34 , and N 3   x   34 ) at its FET switch inputs (i.e., at source-nodes of coupled pairs M 1   y   34 -M′ 1   y   34 , M 1   y   34 -M′ 1   y   34 , and M 1   y   34 -M′ 1   y   34 ) whose gate-nodes are controlled by the y 1   34  bit. Accordingly, the first y-channel sub-iDAC scaled reference currents, gated by the y 1   34  bit, are outputted through the FETs switches (i.e., as I D  of M 1   y   34 , M 1   yt   34 , and M 1   y″   34 ), which provide the first x-channel sub-iDAC reference currents. Consequently, the said first x-channel sub-iDAC reference currents are steered through its FET current switches (i.e., at source-nodes of coupled pairs M 1   x   34 -M′ 1   x   34 , M 2   x   34 -M′ 2   x   34 , and M 3   x   34 -M′ 3   x   34 ) that are controlled by the first x-channel sub-DAC&#39;s digital inputs x 1   34 , x 2   34 , and x 3   34 . The drain-node currents of M 1   x   34 , M 2   x   34 , and M 3   x   34  are summed together and coupled to Ixy 34 , which is the analog current output port of XD i I o  multiplier. Also, notice that drain-nodes of M′ 1   y   34 , M′ 1   y′   34 , and M′ 1   y″   34  are coupled together and terminated at a voltage source (V 1   34 ). Similarly, drain-nodes of M′ 1   x   34 , M′ 2   x   34 , and M′ 3   x   34  are coupled together and terminated at a voltage source (V 1   34 ). 
     Similarly, a second y-channel sub-iDAC receives the second scaled reference currents (i.e., I D  of N 1   x′   34 , N 2   x′   34 , and N 3   x′   34 ) at its FET switch inputs (i.e., at source-nodes of coupled pairs M 2   y   34 -M′ 2   y   34 , M 2   y   34 -M′ 2   y   34 , and M 2   y   34 -M′ 2   y   34 ) whose gate-nodes are controlled by the y2 34  bit. Accordingly, the second y-channel sub-iDAC scaled reference currents, gated by the y2 34  bit, are outputted through the FETs switches (i.e., as I D  of M 2   y   34 , M 2   yt   34 , and M 2   y″   34 ), which provide the second x-channel sub-iDAC reference currents. Consequently, the said second x-channel sub-iDAC reference currents are steered through its FET current switches (i.e., at source-nodes of coupled pairs M 1   x′   34 -M′ 1   x′   34 , M 2   x′   34 -M′ 2   x′   34 , and M 3   x′   34 -M′ 3   x′   34 ) that are controlled by the second x-channel sub-DAC&#39;s digital inputs x 1   34 , x 2   34 , and x 3   34 . The drain-node currents of M 1   x′   34 , M 2   x′   34 , and M 3   x′   34  are summed together and coupled to Ixy 34  as well. Also, notice that drain-nodes of M′ 2   y   34 , M′ 2   y′   34 , and M′ 2   y″   34  are coupled together and also terminated at V 1   34 . Similarly, drain-nodes of M′ 1   x′   34 , M′ 2   xt   34 , and M′ 3   x′   34  are coupled together and also terminated at V 1   34 . 
     Also, a third y-channel sub-iDAC receives the third scaled reference currents (i.e., I D  of N 1   x″   34 , N 2   x″   34 , and N 3   x″   34 ) at its FET switch inputs (i.e., at source-nodes of coupled pairs M 3   y   34 -M′ 3   y   34 , M 3   y   34 -M′ 3   y   34 , and M 3   y   34 -M′ 3   y   34 ) whose gate-nodes are controlled by the y 3   34  bit. Accordingly, the third y-channel sub-iDAC scaled reference currents, gated by the y 3   34  bit, are outputted through the FETs switches (i.e., as I D  of M 3   y   34 , M 3   y′   34 , and M 3   y″   34 ), which provide the third x-channel sub-iDAC reference currents. Consequently, the said third x-channel sub-iDAC reference currents are steered through its FET current switches (i.e., at source-nodes of coupled pairs M 1   x″   34 -M′ 1   x″   34 , M 2   x″   34 -M′ 2   x″   34 , and M 3   x″   34 -M′ 3   x″   34 ) that are controlled by the third x-channel sub-DAC&#39;s digital inputs x 1   34 , x 2   34 , and x 3   34 . The drain-node currents of M 1   x″   34 , M 2   x″   34 , and M 3   x″   34  are summed together and coupled to Ixy 34  as well. Also, notice that drain-nodes of M′ 3   y   34 , M′ 3   y′   34 , and M′ 3   y″   34  are coupled together and also terminated at V 1   34 . Similarly, drain-nodes of M′ 1   x″   34 , M′ 2   x″   34 , and M′ 3   x″   34  are coupled together and also terminated at V 1   34 . 
     As such the outputs of the three x-channel sub-iDACs is summed at Ixy 34  to generate the analog multiplicand representation of X·Y digital multiplications. Note that for a binary (linear) multiplier, the scaled reference network (bank) is also binarily weighted, but the reference network can be scaled in other fashions (e.g., thermometer or non-linear). 
     Note that coupling the iDAC switches gates to voltage sources V 2   34  and V 3   34  reduces logic gates that would otherwise be needed to drive the iDAC switches and it also reduces iDAC glitch (and thereby lowers the XD i I o  multiplier glitch). 
     In summary some of the benefits of the embodiment disclosed in  FIG. 34  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of XD i I o  multiplier is fast also in part because the scaled reference network banks are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where a first iDAC&#39;s output signal supplies the reference signal to a second iDAC, generally through a current mirror) is avoided which helps the speed. 
     Fourth, utilizing the floating iDAC method surrounding N 3   y   34 , N 2   y   34 , and N 1   y   34  reduces die area. 
     Fifth, biasing one side of the iDAC switches by voltage sources (V 2   34  and V 3   34 ) saves area and lowers the XD i I o  multiplier glitch. 
     Section 35—Description of FIG.  35   
       FIG. 35  is a simplified circuit schematic illustrating another preferred embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method described in section 32. In the embodiment of  FIG. 35 , two digital words are inputted into a set of AND gates whose outputs (via current switches) control the steering of currents of a current reference network, wherein the current reference network is arranged to performs bit-weight attribution and summation in the analog domain (and in current mode). 
       FIG. 35  utilizes a x×y matrix of AND gates that are inputted with two digital input words that are x-bits wide (Dx 35  word) and y-bits wide (Dy 35  word). The outputs of AND gates generate one digital output word that is x×y bits wide (Dxy 35  word), wherein each bit of x×y bits wide word has a respective weight. In  FIG. 35 &#39;s multi-branch binary-weighted current reference network, each of the first binary weighted reference current branches (x-branch) supply the current reference inputs of the sets of second binary weighted reference current branches (set of y-branches). Accordingly, the Dxy 35  bits control the respective sets of analog current switches that steer the respective y-branch currents to either a positive (I 1 O 35 ) or a negative (I 2 O 35 ) output current ports. Here, I 1 O 35  and I 2 O 35  represent the analog current outputs of a digital input to analog current output multiplier (XD i I o     35   ). 
     Consider that for descriptive clarity the embodiment of XD i I o     35    is illustrated with only 3-bit (x-bits) by 3-bit (y-bits) digital input words, but the resolution can be higher (e.g., 3-bits to 12-bits). Moreover, the x and y bits and their respective iDAC channels here are interchangeable give the commutative property of multiplications. 
     A current reference (Ir′ 35 ) is inputted and mirrored onto iDACx 35 &#39;s binary weighed current reference network, which constitutes the first binary weighted reference current branches (x-branch). The iDACx 35  current reference network is comprising of P 4   x   35  (scaled at 4×), P 2   x   35  (scaled at 2×), and P 1   x   35  (scaled at 1×). 
     In the  FIG. 35  embodiment of a digital-input to analog current output multiplier (XD i I o ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method, the functions of Y-branch iDACs and Y-branch iDACs are meshed. Effectively, the multiplication function is performed by digitally decoding the digital X-word and digital Y-word and feeding the digitally decoded results onto respective pairs of iDAC 1   x   35  &amp; iDAC 1   y   35 , iDAC 2   x   35  &amp; iDAC 2   y   35 , and iDAC 3   x   35  &amp; iDAC 3   y   35  which are arranged in a meshed structure. 
     Here also, the floating iDAC method (described earlier in section 1) is utilized, whereby each of the iDAC 1   x   35 , iDAC 2   x   35 , and iDAC 3   x   35  binary weighted reference current branches (via each of the respective PMOSFETs: P 1   x   35 , P 1   x   35 , and P 1   x   35 ) feed a respective current reference inputs of 3 floating y-branch iDACs, which are the next set of three binary weighted reference current branches (set of 3 y-branches: iDAC 1   y   35 , iDAC 2   y   35 , and iDAC 3   y   35 ). 
     First, the drain terminal of P 1   x   35  (scaled at 1×) is coupled with the reference current input port of a first floating iDAC 1   y   35  comprising of P 14   y   35  (scaled at 4×), P 12   y   35  (scaled at 2×), and P 11   y   35  (scaled at 1×). 
     Second, the drain terminal of P 2   x   35  (scaled at 2×) is coupled with the reference current input port of a second floating iDAC 2   y   35  comprising of P 24   y   35  (scaled at 4×), P 22   y   35  (scaled at 2×), and P 21   y   35  (scaled at 1×). 
     Third, the drain terminal of P 4   x   35  (scaled at 4×) is coupled with the reference current input port of a third floating iDAC 3   y   35  comprising of P 44   y   35  (scaled at 4×), P 42   y   35  (scaled at 2×), and P 41   y   35  (scaled at 1×). 
     The x-channel digital inputs (Dx 35  word) are D 3   x   35  (MSB) through D 1   x   35  (LSB). The y-channel digital inputs (Dy 35  word) are D 3   y   35  (MSB) through D 1   y   35  (LSB). 
     The digital decoding can be accomplished by an AND matrix (AND 35 ) that is inputted with digital input words Dx 35  and Dy 35 , whose output is a 3×3 bits wide word (Dxy 35  word). As noted earlier, each bit of the Dxy 35  word has a respective weight and as such the Dxy 35  digital word controls the respective current switches of iDAC 1   y   35  (comprising of P 11 ′ 35 , P 12 ′ 35 , and P 13 ′ 35 ), iDAC 2   y   35  (comprising of P 21 ′ 35 , P 22 ′ 35 , and P 23 ′ 35 ), and iDAC 3   y   35  (comprising of P 31 ′ 35 , P 32 ′ 35 , and P 34 ′ 35 ). For example, when D 3   x   35  is high, then the output of the AND gates U 34   y   35  through U 31   35  respond to D 3   y   35  through D 1   y   35  considering their respective weights. Accordingly, P 4   x   35  current (having its respective weight) flows onto P 44   y   35  through P 41   y   35 , in response to D 3   y   35  through D 1   y   35  states, wherein P 44   y   35  through P 41   y   35  have their respective weights. 
     In the illustrated embodiment, to reduce glitch and lower dynamic current consumption and to save logic area, the inverters and the bus lines (that would otherwise be needed for the opposite polarity of the Dxy 35  word) are eliminated. To attain such benefits, the biasing voltage Vs 35  is coupled with the gate terminals of current switches of iDAC 1   y   35  (comprising of P 11   35 , P 12   35 , and P 13   35 ), iDAC 2   y   35  (comprising of P 21   35 , P 22   35 , and P 23   35 ), and iDAC 3   y   35  (comprising of P 31   35 , P 32   35 , and P 34   35 ). The current switches P 11 ′ 35  through P 34 ′ 35  (whose outputs are coupled with the I 1   o   35  port) and P 11   35  through P 34   35  (whose outputs are coupled with the I 2   o   35  port) steer their respective currents onto the I 1   o   35  and I 2   o   35  ports in accordance with their digital selection, controlled by Dxy 35 . 
     Notice that the 4× binary weighted (scaled) reference current through P 4   x   35  is passed on through (to the iDAC 3   y   35 ) depending on the sign of D 3   x   35 , which is the MSB of the X-word. The 2× binary weighted (scaled) reference current through P 2   x   35  is passed on through (to the iDAC 2   y   35 ) depending on the sign of D 2   x   35 , which is the middle-bit of the X-word. The 1× binary weighted (scaled) reference current through P 1   x   35  is passed on through (to the iDAC 1   y   35 ) depending on the sign of D 1   x   35 , which is the LSB of the X-word. 
     The selected sums of (analog) current switch outputs of iDAC 1   y   35  through iDAC 3   y   35  are steered through the XD i I o     35    s current-output port(s)  1 Io 35  (and  12   o   35 ) that generate the analog current product Ax 35 ×Ay 35 /Ar 35 , wherein Ax 35  is the analog current representation of the digital word Dx 35 , Ay 35  is the analog current representation of the digital word Dy 35 , and Ar 35  is scaled relative to reference current signal Ir′ 35 . 
     Bear in mind that the gate terminals of P 11   y   35  through P 44   y   35  are coupled with a bias voltage source Vr 35 , which leaves enough V DS  headroom for P 1   x   35  through P 4   x   35 . Moreover, P 11   y   35  through P 44   y   35  also function as cascoded FETs which can help increase the output impedance of the (XD i I o     35    and) iDAC&#39;s current reference networks. Also consider that instead of a binary weighted current reference network for the iDACs, other thermometer, linear, or non-linear reference network can be programmed here for different objective transfer functions. 
     The disclosed XD i I o     35    benefits from current mode operations, which has been discussed in this disclosure. Multiplying a 3×3 bit digital words generates a 6-bit word that can then be inputted to a 6-bit iDAC to generate a current output product. Digital multipliers are expensive and power hungry when they operate at full speed due to dynamic power consumption of logic gates whose numbers increase exponentially in with the length of a digital multiplier&#39;s input word. The embodiment of XD i I o     35    that utilizes the disclosed mD i I O  method requires a larger size current reference network compared to that of a conventional a 6-bit iDAC but it requires a substantially smaller digital logic, which net-net has the benefit of yielding a smaller die size. 
     Section 36—Description of FIG.  36   
       FIG. 36  is a simplified block diagram illustrating a first non-linear digital-to-analog converter (NDAC) method. For clarity and not as a limitation, the NDAC method is described as one with a square transfer function. Utilizing the first NDAC method, Most-Significant-Portion (MSP) signals and Least-Significant-Portion (LSP) signals are generated utilizing both non-linear DACs and linear DACs. The transfer function of a non-linear MSP DAC can be arranged to follow a square transfer function or other profiles including but not limited to logarithmic, wherein the linear LSP DACs can be arranged as a linear straight-line approximation to fill the gaps in-between the non-linear MSP DAC&#39;s output segment. 
     The first NDAC method of  FIG. 36  is inputted with a digital input word (D 36 ) comprising of a Most-Significant-Bit (MSB) bank word or Dm 36  that is m-bits wide, and a Least-Significant-Bit (LSB) bank word or Dn 36  that is n-bits wide, and wherein D 36  is m+n bits wide. 
     The first NDAC method of  FIG. 36  is provided with a non-linear MSP DAC (DACQ 36 ) that is inputted with the Dm 36  word. Moreover, DACQ 36  is inputted with a reference signal RSQ 36 . The reference network of DACQ 36  is programmed to follow a non-linear transfer function such as a square in this illustration. 
     Furthermore, the first NDAC method of  FIG. 36  is provided with a linear LSP DAC (DAC 1 L 36 ) that is inputted with the Dn 36  word. The DAC 1 L 36  is inputted with a reference signal RL 1   36 , wherein the magnitude of RL 1   36  is proportional to that of RSQ 36 . The reference network of DAC 1 L 36  is programmed to follow a linear transfer function such as binary. 
     Moreover, the first NDAC method of  FIG. 36  is provided with another linear LSP DAC (DAC 2 L 36 ) that is inputted with the multiplicand product of Dm 36 ×Dn 36  words. The DAC 2 L 36  is inputted with a reference signal RL 2   36 , wherein the magnitude of RL 2   36  is also proportional to that of RSQ 36 . The reference network of DAC 2 L 36  is also programmed to follow a linear transfer function such as binary. 
     The linear outputs of DAC 1 L 36  and DAC 2 L 36  are combined together to generate an output that serves as a straight line approximation to fill the gaps in-between MSP segments of the output of the non-linear DACQ 36 . Utilizing the first NDAC method, a non-linear output signal (CO 36 ) can be generated which is an analog non-linear representation of D 36 , as a function of an analog reference signal (e.g., scaled RSQ 36  signal). 
     In summary, the first non-linear digital-to-analog converter (NDAC) method of  FIG. 36  is provided with at least one non-linear MSP DAC whose output is combined with at least on linear LSP DAC, wherein the output of linear LSP DAC(s) fill the gap in-between the non-linear MSP DAC output segments. Benefits of utilizing the NDAC method is later discussed in the embodiments of the said method. 
     Section 36′—Description of FIG.  36 ′ 
       FIG. 36 ′ is a simplified block diagram illustrating a second non-linear digital-to-analog converter (NDAC) method, which utilizes the meshed digital-to-analog multiplication (mD i S o ) method that is discussed in section 32 and illustrated in  FIG. 32 . Utilization of the mD i S o  method is one of the differences between the second non-linear NDAC method and the first NDAC method disclosed in section 36 and the third NDAC method disclosed in section 37. For clarity and not as a limitation, the second NDAC method is also described as one with a square transfer function. Utilizing the second NDAC method, Most-Significant-Portion (MSP) signals and Least-Significant-Portion (LSP) signals can be generated utilizing non-linear DACs, a meshed digital-input analog-output multiplier, and a linear offset DACs. The transfer function of a non-linear MSP DAC can be arranged to follow a square transfer function or other profiles including but not limited to logarithmic, wherein the linear offset DAC in concert with the meshed digital-input analog-output multiplier can be arranged as a linear straight-line approximation to fill the gaps in-between the non-linear MSP DAC&#39;s output segment. 
     The second NDAC method of  FIG. 36 ′ is inputted with a digital input word (D 36′ ) comprising of a Most-Significant-Bit (MSB) bank word or Dm 36 , that is m-bits wide, and a Least-Significant-Bit (LSB) bank word or Dn 36 , that is n-bits wide, and wherein D 36′  is m+n bits wide. 
     The second NDAC method of  FIG. 36 ′ is provided with a non-linear MSP DAC (DACQ 36′ ) that is inputted with the Dm 36′  word. Moreover, DACQ 36′  is inputted with a reference signal RSQ 36′ . The reference network of DACQ 36′  is programmed to follow a non-linear transfer function such as a square in this illustration. 
     Furthermore, the second NDAC method of  FIG. 36 ′ is provided with a linear offset LSP DAC (DAC 1 L 36′ ) that is inputted with the Dn 36′  word. The DAC 1 L 36′  is inputted with a reference offset signal RL 1   36′ , wherein the magnitude of RL 1   36′  signal is proportional to that of RSQ 36′  signal. The reference network of DAC 1 L 36′  is programmed to follow a linear transfer function such as binary. 
     Moreover, the NDAC method of  FIG. 36 ′ is provided with a meshed digital-to-analog multiplier (XDiSo 36′ ), which utilizes the meshed digital-to-analog multiplication method (mD i S o ) disclosed in section 32. The XDiSo 36′  is inputted with a reference signal (RL 2   36′ ), wherein the magnitude of RL 2   36′  signal is also proportional to that of RSQ 36′  signal. The reference network of DAC 2 L 36′  is also programmed to follow a linear transfer function such as binary. 
     The linear outputs of DAC 1 L 36′  and XDiSo 36′  are combined together to generate an output that serves as a straight line approximation to fill the gaps in-between MSP segments of the output of the non-linear DACQ 36′ . Utilizing the second NDAC method, a non-linear output signal (CO 36′ ) can be generated which is an analog non-linear representation of D 36′ , as a function of an analog reference signal (e.g., scaled RSQ 36′  signal). 
     In summary, the non-linear digital-to-analog converter (NDAC) method of  FIG. 36 ′ is provided with at least one non-linear MSP DAC whose output is combined with a meshed digital-to-analog multiplier and at least on linear (offset) LSP DAC, wherein the combined outputs of the meshed digital-to-analog multiplier, and the linear LSP DAC(s), fill the gap in-between the non-linear MSP DAC output segments. Benefits of utilizing the NDAC method is later discussed in the embodiments of the said method. 
     Section 37—Description of FIG.  37   
       FIG. 37  is a simplified block diagram illustrating a third non-linear digital-to-analog converter (NDAC) method. For clarity and not as a limitation, the third NDAC method here is also described as one with a square transfer function. Utilizing the third NDAC method, Most-Significant-Portion (MSP) signals generated by a non-linear MSP DAC are combined with and Least-Significant-Portion (LSP) signals generated by a pair of linear LSP DACs which are arranged in a multiplying fashion. The non-linear MSP DACs can also be arranged to follow a square (or other) profile(s) including but not limited to logarithmic, wherein the linear LSP DACs can also be arranged as a linear straight-line approximation to fill the gaps in-between the outputs of the non-linear MSP DAC segment. 
     The third NDAC method of  FIG. 37  is inputted with a digital input word (D 37 ) comprising of a Most-Significant-Bit (MSB) bank word or Dm 37  that is m-bits wide, and a Least-Significant-Bit (LSB) bank word or Dn 37  that is n-bits wide, and wherein D 37  word is m+n bits wide. 
     The third NDAC method of  FIG. 37  is provided with a non-linear MSP DAC (DACQ 37 ) that is inputted with the Dm 37  word. Moreover, DACQ 37  is inputted with a reference signal RSQ 37 . The reference network of DACQ 37  is programmed to follow a non-linear transfer function such as a square in this illustration. 
     Furthermore, the third NDAC method of  FIG. 37  is provided with a linear LSP DAC (DAC 1 L 37 ) that is inputted with the MSB bank word Dm 37 . The DAC 1 L 37  is also inputted with a reference signal RL 1   37 , wherein the magnitude of RL 1   37  is also proportional to that of RSQ 37 . The reference network of DAC 1 L 37  is also programmed to follow a linear transfer function such as binary. 
     Moreover, the third NDAC method of  FIG. 37  is provided with another linear LSB DAC (DAC 2 L 37 ) that is inputted with the LSB bank word or Dn 36 . The output of DAC 1 L 37  is combined with a reference signal (RL 2   37 ) and the said combined resultant signal is supplied to the reference input port of DAC 2 L 37 . Note that the magnitude of RL 1   37  signal and RL 1   37  signal are also proportional to RSQ 37  signal. 
     The output the linear DAC 2 L 37  serves as a straight-line approximation to fill the gaps in-between Most-Significant-Portion (MSP) output segments of the non-linear DACQ 36 . Utilizing the third NDAC method, a non-linear output signal (CO 37 ) can be generated which is an analog non-linear representation of D 37 , as a function of an analog reference signal (e.g., scaled RSQ 37  signal). 
     In summary, the third non-linear digital-to-analog converter (NDAC) method of  FIG. 37  is provided with at least one non-linear MPS DAC whose output is combined with a pair of linear LSP multiplying DACs, wherein the output of a first multiplying DAC is coupled with the reference input of a second multiplying DAC, and wherein the output of the second multiplying DAC fill the gap in-between the non-linear MSP DAC segments. Benefits of utilizing the third NDAC method is later discussed in the embodiments of the said method. 
     Section 38—Description of FIG.  38   
       FIG. 38  is a simplified circuit schematic illustrating an embodiment of a non-linear digital-input to analog current output digital-to-analog converter (iNDAC 38 ), which utilizes the NDAC method described in section 37 and illustrated in  FIG. 37 , wherein the non-linear output profile of iNDAC 38  is programmed to approximate a square transfer function. 
     For clarity of description and illustration,  FIG. 38  illustrates only 6-bit iDACs, but this illustration is not a limitation of the disclosure here. Here, the digital input word (Di 38 ) is comprising of D 6   38 , D 5   38 , D 4   38 , D 3   38 , D 2   38 , and D 1   38  bits. Depending on an application requirement, the disclosed iDAC can, for example, have 16-bits of resolution. 
     The non-linear Most-Significant-Portion (MSP) DAC (iDACQ 38 ) is a non-linear thermometer iDAC. The iDACQ 38  non-linear thermometer reference current network is comprised of I 1   r   38 =i r , I 1   r   38 =3i r , I 1   r   38 =5i r , I 1   r   38 =7i r , I 1   r   38 =9i r , I 1   r   38 =11i r , and I 1   r   38 =13i r , wherein i r  is a (unit) scaled reference signal. By inputting the MSB bank word (D 6   38 , D 5   38 , and D 4   38 ) to a 3-bit input to 7-bit output digital encoder (ENC 38 ), a 7-bit digital word is generated. The 7-bit output word of ENC 38  control the current switches P 1   t   38 , P 2   t   38 , P 3   t   38 , P 4   t   38 , P 5   t   38 , P 6   t   38 , and P 7   t   38 , whose inputs are couple to their respective non-linear current source segments of the non-linear thermometer reference current network. The current switches control the steering of the non-linear current source segments. The outputs of the current switches are coupled together at node iQ 38  wherein a non-linear MSP current signal is generated that approximates a square profile. 
     The first linear Least-Significant-Portion (LSP) iDAC (iDAC 1 L 38 ) is a linear binary weighted iDAC. The iDAC 1 L 38  binary weighted reference current network is comprised of I 9   r   38 =8i r , I 10   r   38 =4i r , and I 11   r   38 =2i r . The MSB bank word (D 6   38 , D 5   38 , and D 4   38 ) controls the current switches P 6   d   38 , P 5   d   38 , and P 4   d   38  whose inputs are couple to their respective binary-weighted current sources (e.g., I 9   r   38 =8i r , I 10   r   38 =4i r , and I 11   r   38 =2i r ). The P 6   d   38 , P 5   d   38 , and P 4   d   38  current switches control the steering of the respective binary-weighted current sources. The outputs of P 6   d   38 , P 5   d   38 , and P 4   d   38  current switches are coupled together at node i 1 L 38  wherein a first linear LSP current signal is generated. 
     An offset reference signal I 8   r   38 =i r  is also coupled to the i 1 L 38  node, which is then coupled to the reference current input port of the second linear LSP iDAC (iDAC 2 L 38 ). 
     The second linear LSP iDAC or iDAC 2 L 38  is also a linear binary weighted iDAC. The iDAC 2 L 38  binary scaled reference current network is comprised of PMOSFETs: Pf 38 @ 1×, P 1   d′   38 @1×, P 2   d′   38 @2×, and P 3   d′   38 @4×. The LSB bank word (D 1   38 , D 2   38 , and D 3   38 ) controls the current switches P 1   d   38 , P 2   d   38 , and P 3   d   38  whose inputs are couple to their respective binary-scaled current dividers (e.g., P 1   d′   38 @1×, P 2   d′   38 @ 2×, and P 3   d′   38 @4×). The P 1   d   38 , P 2   d   38 , and P 3   d   38  current switches control the steering of the respective binary-scaled current divider of the (reference input current of iDAC 2 L 38 ) supplied through the i 1 L 38  node. The outputs of P 1   d   38 , P 2   d   38 , and P 3   d   38  current switches are coupled together at node i 2 L 38  wherein a second linear LSP current signal is generated. 
     The i 2 L 38  node and node iQ 38  node are coupled together and coupled to the output node of the iNDAC 38  which is iCO 38 . 
     Note that the current signals at the i 2 L 38  port fills-in the gap between the current signals at the A QM  port. As such, the signal at node iCO 38  follows an approximate profile that is squarely weighted, as a function of the i r , and is responsive to the Di 38  word. 
     In summary some of the benefits of the embodiment disclosed in  FIG. 38  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of the non-linear iDAC is fast also in part because the scaled reference network banks utilized in the non-linear MSP, first linear LSP, and second linear LSP iDACs are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where a first linear LSP iDAC&#39;s output signal supplies the reference signal to a second linear LSP iDAC, generally through a current mirror) is avoided which helps the speed. 
     Fourth, utilizing the floating iDAC method surrounding the first linear LSP iDAC and second linear LSP iDAC reduces die area and cost. 
     Fifth, the iNDAC 38  enables making a fast and low-cost digital input to current analog output multiplier using the quarter square method. Here, by subtracting the current outputs of two iNDAC 38  a multiplicand 4X·Y can be generated, wherein the first iNDAC 38  receives the sum of two digital words and generates (X+Y) 2  and the second iNDAC 38  receives the difference of the same two digital words and generates (X−Y) 2 . 
     Section 39—Description of FIG.  39   
       FIG. 39  is a simplified circuit schematic illustrating another embodiment of a non-linear digital-input to analog current output digital-to-analog converter (iNDAC 39 ), which utilizes the NDAC method described in section 36′ and illustrated in  FIG. 36 ′, wherein the non-linear output profile of iNDAC 39  is programmed to approximate a square transfer function. To generate a liner LSP current signal, the embodiment of  FIG. 39  also utilizes another embodiment of a digital-input to current analog-output multiplier (XDiIo 39 ) that utilizes the meshed digital-to-analog multiplication (mD i S o ) method that is discussed in sections 32 and 32′, and illustrated in  FIGS. 32 and 32 ′. Bear in mind that XDiSo 39  multiplier is similar to the XD i I o  disclosed in section and illustrated in  FIG. 35 . 
     For clarity of description and illustration,  FIG. 39  illustrates only 6-bit iNDACs, but this illustration is not a limitation of the disclosure here. Here, the digital input word (Di 39 ) is comprising of D 6   39 , D 5   39 , D 4   39 , D 3   39 , D 2   39 , and D 1   39  bits. Depending on an application requirement, the disclosed iDAC can, for example, have 16-bits of resolution. 
     The non-linear Most-Significant-Portion (MSP) DAC (iDACQ 39 ) is arranged as a non-linear thermometer iDAC. The iDACQ 39  non-linear thermometer reference current network is comprised of PMOSFETs whose drain currents are scaled as follows: P 1   t   39 @i r , P 1   t   39 @3i r , P 1   t   39 @5i r , P 1   t   39 @7i r , P 1   t   39 @9i r , P 1   t   39 @ 11i r , and P 1   t   39 @13i r , wherein i r  is a (unit) scaled reference signal programmed by Ir 39 =1i r . By inputting the MSB bank word (D 6   39 , D 5   39 , and D 4   39 ) to a 3-bit input to 7-bit output digital encoder (ENC 39 ), a 7-bit digital word is generated. The 7-bit output word of ENC 39  control the PMOSFET current switches comprising of s 1   t   39 , s 2   t   39 , s 3   t   39 , s 4   t   39 , s 5   t   39 , s 6   t   39 , and s 7   t   39 , whose inputs are couple to their respective non-linear current source segments of the respective non-linear thermometer reference current network. As such, the current switches control the steering of the non-linear current source segments onto the outputs of the said current switches which are coupled together at the output node iQ 39 . 
     The first linear offset Least-Significant-Portion (LSP) iDAC (iDAC 1 L 39 ) is a linear binary weighted iDAC. The iDAC 1 L 39  binary weighted reference current network is comprised of PMOSFETs whose drain currents are scaled at: P 1   f   39 @ ½i r , P 2   f   39 @ i r  and P 3   f   39 @ 2i r . The LSB bank word (D 1   39 , D 2   39 , and D 3   39 ) controls the PMSOFET current switches P 1   f   39 , P 2   f   39 , and P 3   f   39  whose inputs are couple to their respective binary-weighted PMOSFET current sources (e.g., P 1   f   39 @ 0.5×, P 2   f   39 @ 1×, and P 3   f   39 @ 2×). The P 1   f   39 , P 2   f   39 , and P 3   f   39  current switches control the steering of the respective binary-weighted current sources. The outputs of P 1   f   39 , P 2   f   39 , and P 3   f   39  current switches are coupled together at node iQ 39 . 
     To generate the linear LSP output signal, the iNDAC 39  also utilizes the XDiSo 39  meshed multiplier, which utilizes the mD i S o  method. 
     Similar to the XD i I o  disclosed in section 35 and illustrated in  FIG. 35 , here in how XDiIo 39  of  FIG. 39  is arranged: 
     The D 4   39  bit is AND gated (e.g., via U 41   39 , U 42   39 , and U 43   39 ) with the LSB bank word (D 3   39 , D 2   39 , D 1   39 ) to generate the control signals for a first sub-iDAC switches (s 1 L 39 , s 2 L 39 , and s 3 L 39 ). The first sub-iDAC switches steer the first bank of binary weighted current reference signals (generated by the PMOSFET binary scaled current reference sources: P 1 L 39 @ 1×, P 2 L 39 @ 2×, and P 3 L 39 @ 4×), wherein the full scale of the first sub-iDAC is 7i r . The output of the first sub-iDAC switches are also coupled together at node iQ 39 . 
     The D 5   39  bit is also AND gated (e.g., via U 51   39 , U 52   39 , and U 53   39 ) with the LSB bank word (D 3   39 , D 2   39 , D 1   39 ) to generate the control signals for a second sub-iDAC switches (s 1 L′ 39 , s 2 L′ 39 , and s 3 L′ 39 ). The second sub-iDAC switches steer the second bank of binary weighted current reference signals (generated by the PMOSFET binary scaled current reference sources: P 1 L′ 39 @ 2×, P 2 L′ 39 @ 4×, and P 3 L′ 39 @ 8×), wherein the full scale of the second sub-iDAC is 14i r . The output of the second sub-iDAC switches are also coupled together at node iQ 39 . 
     The D 6   39  bit is also AND gated (e.g., via U 61   39 , U 62   39 , and U 63   39 ) with the LSB bank word (D 3   39 , D 2   39 , D 1   39 ) to generate the control signals for a third sub-iDAC switches (s 1 L″ 39 , s 2 L″ 39 , and s 3 L″ 39 ). The third sub-iDAC switches that steer the third bank of binary weighted current reference signals (generated by the PMOSFET binary scaled current reference sources: P 1 L″ 39 @ 4×, P 2 L″ 39 @ 8×, and P 3 L″ 39 @ 16×), wherein the full scale of the second sub-iDAC is 28i r . The output of the third sub-iDAC switches are also coupled together at node iQ 39 . 
     Notice that the current output signal of the XDilo 39  combined with the output signal of at the linear offset iDAC 1 L 39  fills-in the gap between segments of the current signal of the iDACQ 39 . As such, the signal at node iQ 39  follows an approximate squarely weighted profile, that is a function of the i r , and is responsive to the Di 39  word. 
     In summary some of the benefits of the iNDAC 39  embodiment disclosed in  FIG. 39  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of the non-linear iDAC is fast also in part because the scaled reference network banks utilized in the non-linear MSP and the linear LSP segments are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where for example a first linear LSP iDAC&#39;s output feeds the reference input port of a second linear LSP iDAC, generally through a current mirror) is avoided which helps the speed. 
     Fourth, utilizing a meshed digital input to analog output multiplier XDiIo 39  is fast and can operate with low V DD . 
     Fifth, the iNDAC 39  enables making a fast and low-cost digital input to current analog output multiplier using the quarter square method. Here, by subtracting the current outputs of two iNDAC 39  a multiplicand 4A·B can be generated, wherein the first iNDAC 39  receives the sum of two digital words and generates (A+B) 2  and the second iNDAC 39  receives the difference of the same two digital words and generates (A−B) 2 . 
     Sixth, the disclosed iNDAC 39  power consumption is event driven in that if there is not event (e.g., data polarity of zero), the iDACs and XDiIo 39  shut of their respective current sources and hence power down. 
     Section 40—Description of FIG.  40   
       FIG. 40  is a simplified circuit schematic illustrating another embodiment of the digital-input to analog current output multiplier (XD i I o ). The XD i I o     40    multiplier utilizes the meshed digital-to-analog multiplication (mD i S o ) method (described in the prior section 32′ and illustrated in  FIG. 32 ′), the multiple-channel data-converter method (disclosed in section 19 and illustrated in  FIG. 19 ), and a second power supply desensitization method (PSR) disclosed here. 
     The XD i I o  of  FIG. 40  (XD i I o     40   ) utilizes a reference bias network circuit (RBN 40 ) which is an embodiment of the multiple-channel data-converter method (disclosed in section 19 and illustrated in  FIG. 19 ), which can save silicon area and improve the dynamic performance sub-iDACs, and thereby improve performance and reduce die size of the XD i I o     40   . For clarity only one channel of XD i I o  is described here, but a sea of XD i I o s can be biased from the same reference bias network to bias the sea of XD i I o  multipliers. 
     The XD i I o     40    multiplier also utilizes the second multiplier power supply desensitization method in the PRS 40  circuit that can substantially desensitize XD i I o     40    multiplier&#39;s output current from power supply variations, while eliminating cascodes from current sources utilized in the current reference networks in the XD i I o     40    multiplier (which saves more area). 
     Also, for clarity and not as a limitation, the XD i I o     40    multiplier is described as receiving two digital words, each having 3-bits of resolution, but the digital input word resolution can be as high as 16-bits. 
     The three sections of XD i I o  multiplier circuit, comprising of RBN 40 , PSR 40 , and XD i I o     40    multiplier, is briefly described here: 
     In  FIG. 40 , a RBN 40  generates a sequence of individual binary weighted reference bias currents as follows: P 16   r   40  operating at  116   r   40  of (2 5-1 )×i=16i r40 ; P 8   r   40  operating at I 8   r   40  of (2 4-1 )×i=8i r40 ; P 4   r   40  operating at I 4   r   40  of (2 3-1 )×i=4i r40 ; P 2   r   40  operating at I 2   r   40  of (2 2-1 )×i=2i r40 ; and P 1   r   40  operating at I 1   r   40  of (2 1-1 )×i=1i r40 . In the embodiment of  FIG. 40 , RBN 40  is comprised of a sequence of CCVS which are implemented as a sequence of diode connected NMOSFETs (N 16   r   40 , N 8   r   40 , N 4   r   40 , N 2   r   40 , and N 1   r   40 ) whose gate and drain ports are coupled together, wherein each NMOSFET is scaled with a W/L=1×. Accordingly, the sequence of binary weighted reference bias currents I 16   r   40  to I 1   r   40  are inputted to the diode connected NMOSFETs (CCVS) which generate a sequence of (gate-to-source) reference bias voltages from reference bias voltage bus V 16   40  to reference bias voltage bus V 1   40  as follows: I D  of P 16   r   40 =16i r40  is inputted to the diode connected N 16   r   40  to generate a reference bias bus voltage of V 16   40 ; I D  of P 8   r   40 =8i r40  is inputted to the diode connected N 8   r   40  to generate a reference bias bus voltage of V 8   40 ; I D  of P 4   r   40 =4i r40  is inputted to the diode connected N 4   r   40  to generate a reference bias bus voltage of V 4   40 ; I D  of P 2   r   40 =2i r40  is inputted to the diode connected N 2   r   40  to generate a reference bias bus voltage of V 2   40 ; and I D  of P 1   r   40 =1i r40  is inputted to the diode connected N 1   r   40  to generate a reference bias bus voltage of V 1   40 . 
     The NMOSFET current sources of the XD i I o     40    multiplier are biased by coupling their gate-port to the respective (reference bias network) RBN 40 &#39;s voltage bus comprising of V 16   40  to V 1   40  as follows: 
     For the first sub-iDAC of the meshed XD i I o     40    multiplier, the gate ports of NMOSFET current sources N 1   v   40 , N 2   v   40 , and N 4   v   40  are coupled with reference bias voltage buses of RBN 40  comprising of V 1   40 , V 2   40 , and V 4   40 , respectively. Accordingly, the drain currents (scaled reference current sources) of N 1   v   40 , N 2   v   40 , and N 4   v   40  operate at 1i r40 , 2i r40 , and 4i r40 , respectively. 
     For the second sub-iDAC of the meshed XD i I o     40    multiplier, the gate ports of NMOSFET current sources N 2   v′   40 , N 4   v′   40 , and N 8   v′   40  are coupled with reference bias voltage buses of RBN 40  comprising of V 2   40 , V 4   40 , and V 8   40 , respectively. Accordingly, the drain currents (scaled reference current sources) of N 2   v′   40 , N 4   v′   40 , and N 8   v′   40  operate at 2i r40 , 4i r40 , and 8i r40 , respectively. 
     For the third sub-iDAC of the meshed XD i I o     40    multiplier, the gate ports of NMOSFET current sources N 4   v″   40 , N 8   v″   40 , and N 16   v″   40  are coupled with reference bias voltage buses of RBN 40  comprising of V 4   40 , V 8   40 , and V 16   40 , respectively. Accordingly, the drain currents (scaled reference current sources) of N 4   v″   40 , N 8   v″   40 , and N 16   v″   40  operate at 4i r40 , 8i r40 , and 16i r40  respectively. 
     As indicated earlier, the PSR 40  circuit utilizes a second PSR method. In the embodiment of PSR 40  illustrated in  FIG. 40 , results in substantial area savings by eliminating the cascode from current sources in the sub-iDACx 40 s of the XD i I o     40    multiplier as well as from that of the RBN 40  circuits, while the output current of XD i I o     40    multiplier is substantially desensitized from V DD  variations. This is done by regulating the reference bias currents of RBN 40  so that the outputs of the sub-iDACx 40 s of the XD i I o     40    multiplier are substantially desensitized to power supply variations. 
     The second power supply desensitization (PSR) method utilized in the PSR 40  circuit is briefly explained as follows: 
     A central reference bias current network (RBN), free of cascodes, generates a reference bias voltage bus, wherein the reference bias voltage bus is shared with a plurality of reference bias current networks of a plurality of cascode-free data-converters. To substantially desensitize the plurality of output currents of the plurality of cascode-free data-converters, a power supply desensitization circuit tracks the power supply variations and varies each reference bias currents of the central RBN. Utilization of the second PSR method PSR 40  is described next. in Bear in mind that FET early voltage (V A ) causes the FET&#39;s I DS  to vary with varying the FET&#39;s V DS . Also, keep in mind that the output port of the XD i I o     40    multiplier could be coupled to an input of a current-mode analog-to-digital converter (iADC), wherein the input port of the iADC could be biased at a V GS  of a MOSFET below or above the V DD  or V SS , respectively (e.g., V DD −Vgs PMOS ). As such, assuming little voltage drop across current switches of the sub-iDACs of the XD i I o     40    multiplier, the drain-terminals of the (digitally selected) scaled reference current sources of the XD i I o     40    multiplier would be biased at V DD −Vgs PMOS  as well. Additionally, keep in mind that the drain-to-source voltage (V DS ) of current sources of the RBN 40  (e.g., P 16   r   40 , P 8   r   40 , P 4   r   40  P 2   r   40 , and P 1   r   40 ) is V DS =V DD −Vgs NMOS . In order to substantially desensitize the output current of the XD i I o     40    multiplier from V DD  variations, the PSR 40  is arranged to operates as follows: P 3   d   40  regulates the I D  of the diode-connected N 2   d   40  (i.e., Vgs NMOS ) whose current is mirrored onto N 1   d   40 . The I D  of N 1   d   40  is coupled into the diode connected P 2   d   40  (i.e., Vgs PMOS ) whose I D  is mirrored onto P 1   d   40 . The I D  of P 1   d   40  is substantially equal to that of the scaled reference current or ir 40 . Accordingly, as the V DD  is varied, the gate port of P 3   d   40  regulates the magnitude of the current sources of the RBN 40  so that the current sources of the RBN 40  track the scaled reference current or ir 40 , which is substantially stable by design. In summary, the disclosed arrangement could substantially desensitize the XD i I o     40    multiplier from V DD  variations while all current sources of the sub-iDACx 40 s of the XD i I o     40    multiplier and that of the RBN 40  current sources are without cascodes, which saves substantial silicon area. 
     Next, the XD i I o     40    multiplier is briefly described, keeping in mind that the embodiment of XD i I o     40    multiplier is similar to the embodiment of the XD i I o  multiplier of  FIG. 33  which utilized the meshed digital-to-analog multiplication (mD i S o ) method (described in the prior section 32′ and illustrated in  FIG. 32 ′). The XD i I o     40    multiplier is inputted with two digital input words Dx 40  word (comprising of 3-bits x 1   40 , x 2   40 , and x 3   40 ) and Dy 40  word (comprising of 3-bits y 1   40 , y2 40 , and y 3   40 ). 
     As described earlier, the XD i I o     40    multiplier is also inputted with a plurality of scaled reference current signals proportional to ir 40 , utilize NMOSFETs that are each scaled with W/L of 1×) comprising of 3 banks namely: The first scaled reference current bank I 1   r   40 =1×ir 40 , I 2   r   40 =1×ir 40 , and I 4   r   40 =4×ir 40 , corresponding to I D  of N 1   v   40 , N 2   v   40 , and N 4   v   40 , respectively. The second scaled reference current bank I 2   r   40 =2×ir 40 , I 4   r   40 =4×ir 40 , and I 8   r   40 =8×ir 40 , corresponding to I D  of N 2   v′   40 , N 4   v′   40 , and N 8   v′   40 , respectively. The third scaled reference current bank I 4   r   40 =4×ir 40 , I 8   r   40 =8×ir 40 , and I 16   r   40 =16×ir 40 , corresponding to I D  of N 4   v″   40 , N 8   v″   40 , and N 16   v″   40 , respectively. 
     A first x-channel sub-iDAC receives the first scaled reference bank (i.e., I 1   r   40 , I 2   r   40 , and I 4   r   40 ) at its current switch inputs that are the source-nodes of N 1   x   40 , N 1   x′   40 , and N 1   x″   40  whose gate-nodes are controlled by x 1   40  bit. Accordingly, each of the I 1   r   40 , I 2   r   40 , and I 4   r   40  currents are respectively steered through, N 1   x   40 , N 1   x′   40 , and N 1   x″   40  which are gated by the x 1   40  bit, to provide the scaled reference input currents to the first y-channel sub-iDAC (in accordance with Dx 40  word). Consequently, the said first y-channel sub-iDAC reference currents are steered through current switches N 1   y   40 , N 2   y   40 , and N 3   y   40  that are controlled by the first y-channel sub-iDAC&#39;s digital inputs y 1   40 , y2 40 , and y 3   40  bits, respectively. The drain-node currents of N 1   y   40 , N 2   y   40 , and N 3   y   40  are summed together and coupled to Ixy 40 , which is the analog current output port of the XD i I o     40    multiplier. 
     Similarly, a second x-channel sub-iDAC receives the second scaled reference bank (i.e., I 2   r   40 , I 4   r   40 , and I 8   r   40 ) at its current switch inputs that are the source-nodes of N 2   x   40 , N 2   x′   40 , and N 2   x″   40  whose gate-nodes are controlled by x 2   40  bit. Accordingly, each of the I 2   r   40 , I 4   r   40 , and I 8   r   40  currents are respectively steered through, N 2   x   40 , N 2   x′   40 , and N 2   x″   40  which are gated by the x 2   40  bit, to provide the scaled reference input currents to the second y-channel sub-iDAC (in accordance with Dx 40  word). Consequently, the said second y-channel sub-iDAC reference currents are steered through current switches N 1   y′   40 , N 2   y′   40 , and N 3   y′   40  that are controlled by the second y-channel sub-iDAC&#39;s digital inputs y 1   40 , y2 40 , and y 3   40  bits, respectively. The drain-node currents of N 1   y′   40 , N 2   y′   40 , and N 3   y′   40  are summed together and coupled to Ixy 40 , which as noted earlier is the analog current output port of the XD i I o     40    multiplier. 
     Lastly, a third x-channel sub-iDAC receives the third scaled reference bank (i.e., I 4   r   40 , I 8   r   40 , and I 16   r   40 ) at its current switch inputs that are the source-nodes of N 3   x   40 , N 3   x′   40 , and N 3   x″   40  whose gate-nodes are controlled by x 3   40  bit. Accordingly, each of the I 4   r   40 , I 8   r   40 , and I 16   r   40  currents are respectively steered through, N 3   x   40 , N 3   x′   40 , and N 3   x″   40  which are gated by the x 3   40  bit, to provide the scaled reference input currents to the third y-channel sub-iDAC (in accordance with Dx 40  word). Consequently, the said third y-channel sub-iDAC reference currents are steered through current switches N 1   y″   40 , N 2   y″   40 , and N 3   y″   40  that are controlled by the third y-channel sub-iDAC&#39;s digital inputs y 1   40 , y2 40 , and y 3   40  bits, respectively. The drain-node currents of N 1   y′″   40 , N 2   y″   40 , and N 3   y″   40  are summed together and coupled to Ixy 40 , which as just noted is the analog current output port of the XD i I o     40    multiplier. 
     In summary, the outputs of the first and second and third y-channel iDACs are summed at Ixy 40  to generate the analog multiplicand representation, proportion to a unit scaled reference current signal, that is the X·Y digital multiplications. Note that for a binary (linear) multiplier, the scaled reference network (bank) is also binarily weighted, but the reference network can be scaled in other fashions (e.g., thermometer or non-linear) for multipliers with different input-to-output transfer functions. 
     In conclusion, some of the benefits of the XD i I o  multiplier embodiment disclosed in  FIG. 40  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of XD i I o  multiplier is fast also in part because the scaled reference network banks are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where a first iDAC&#39;s output signal supplies the reference signal to a second iDAC, generally through a current mirror) is avoided which helps the speed. 
     Fourth, the minimum power supply can be lowered since it is chiefly limited by the drain-to-source voltage of current sources of the scaled reference network. 
     Fifth, for multiple channels of XD i I o  multiplier required in AI &amp; ML applications, the disclosed embodiment enjoys substantial benefits attributed to the multiple-channel data-converter method summarized in section 19. There is an area savings, in utilizing the multiple-channel data-converter method, in part because the requirement for individually weighted current sources (e.g., binary weighted or non-linearly weighted) is decoupled from requiring individually scaled current sources. Here, utilization of RBN 40  to generate a common reference voltage bus that is shared between plurality of sub-iDACs reduces the size of sub-iDACs current reference (cells in the) reference network of each sub-iDACs which lowers cost. Moreover, it lowers the combined associated parasitic and stray capacitance associated with current reference cells, which improves each of the sub-iDAC&#39;s dynamic response, lowers glitch, lowers digital injections into power supplies, and reduces the disclosed sub-iDAC&#39;s dynamic power consumption. The small size and improved performance on each sub-iDAC used in arranging each XD i I o  multipliers are thus enjoyed by the plurality of plurality of such XD i I o  multipliers. 
     Sixth, despite area savings attainable by the disclosed multiple-channel data-converter method in the sub-iDACs and the XD i I o  multipliers, the accuracy of individual the sub-iDACs and the XD i I o  multipliers are not substantially deterred. All else substantially equal, the matching of MOSFETs that form a data-converter&#39;s reference current network dominate the accuracy of a current-mode data-converter. The scaled MOSFETs in both the (central) reference bias network (RBN 40 ) match the 1× scaled MOSFETs in each of the sub-iDACs and the XD i I o  multipliers because they are all arranged with the same (non-minimum W/L size) cell layout and same orientation. 
     Seventh, the disclosed sub-iDACs and the XD i I o  multipliers substantially reduces the number of MOSFETs that for example form the sub-iDAC&#39;s binary weighted current source network, and as such the fewer MOSFETs can be placed closer to each other on a chip. Similarly oriented and physically closer MOEFETs, that form the current reference network of the sub-iDACs and the XD i I o  multipliers, generally match better which in turn improves the accuracy of each of the sub-iDACs and the XD i I o  multipliers and the matching between them in plurality of the sub-iDACs and the XD i I o  multipliers in one chip. 
     Eight, in AI &amp; ML applications the output current of plurality of the XD i I o  multipliers could be coupled together and coupled to the input of iADCs. Generally and all else substantially equal, the larger the W/L size of a FET current source of the XD i I o  multipliers, the larger the capacitance of the XD i I o  multiplier&#39;s output port and the slower the of the XD i I o  multipliers output node. Moreover, the XD i I o  multiplier&#39;s output can capacitively load an iADC&#39;s input port which can also reduce the speed of the iADC right at its input port. As noted earlier, the multiple-channel data-converter method here enables decoupling the weight of a current source from the scaling of the sizes of FETs utilizing in forming the data-converter&#39;s reference current sources. By keeping each of the W/L sizes of the current source FETs the same at 1× and small for example (despite each of their binary weighted currents), the out node capacitances of the XD i I o  multipliers that feeds the input of the iADC can be kept small which can help speeds up the dynamic response of the iADC. 
     Ninth, there are no passive devices in the disclosed sub-iDACs and the XD i I o  multipliers, and as such there is no need for resistors or capacitors, which reduces manufacturing size and cost. 
     Tenth, the disclosed sub-iDACs and the XD i I o  multipliers utilize same type of MOSFET current sources and MOSFET switches which are symmetric and matched. Such arrangement facilitates device parameters to track each other over process-temperature-operation conditions variations. Accordingly, each of the data-coefficient, power supply coefficient, and AC power supply rejection performance can be enhanced and matched between the plurality of data-converters. 
     Eleventh, the disclosed embodiment enjoys the benefits of a second power supply desensitization (PSR) method, which helps eliminate a cascode FET from the scaled current reference sources which saves area and improves the dynamic response of the sub-iDAC and that of the meshed multiplier. 
     Twelfth, in an embodiment of the disclosed sub-iDACs and the XD i I o  multipliers that utilizes the multiple-channel data-converter method wherein the central RBN is trimmed or calibrated for accuracy, the accuracy of each of the plurality of data-converters, sub-iDACs, and the XD i I o  multipliers whose reference current network is biased from the same central RBN can be improved. 
     Thirteenth, in an embodiment of the sub-iDACs and the XD i I o  multipliers that utilizes multiple-channel data-converter method wherein the central RBN is desensitized from power supply variations (e.g., by utilizing the second power supply desensitization method or the second PSR method disclosed in  FIG. 40  and  FIG. 41 ), the power supply insensitivity of each of the plurality of data-converters whose reference current network is biased from the same central RBN can be improved. 
     Fourteenth, the disclosed embodiment enjoys the benefits of meshed digital-to-analog multiplication (mD i S o ) method summarized in sections 32′ and 33. 
     Fifteenth, the benefits of the sub-iDACs and the XD i I o  multipliers utilizing the multiple-channel data-converter method can be attained in other higher-order systems including but not limited to multiply-accumulate (MAC), and artificial-neural-network (ANN) that utilize the multiple-channel data-converter method. 
     Section 41—Description of FIG.  41   
       FIG. 41  is a simplified circuit schematic illustrating another embodiment of the digital-input to analog current output multiplier (XD i I o ), which can be extended for applications requiring plurality of XD i I o  multipliers by sharing a central reference bias network (RBN) that bias the current reference network of each of the XD i I o  multipliers. The XD 1 I O     41    multiplier utilizes a pair of non-linear iDACs, namely iNDAC P41  and iNDAC Q41 , which receive a sum and a difference of two digital words (X and Y) wherein for example P′=X+Y and Q′=X−Y. The outputs of the iNDAC P41  and iNDAC Q41  are then subtracted via SUB 41  circuit which generates a scaled multiplicand analog current of the multiplication on digital P′ word and digital Q′ words. Here, by subtracting the current outputs of iNDAC P41  and iNDAC Q41  a multiplicand 4X·Y can be generated, wherein the first iNDAC P41  receives the sum of two digital words and generates (X+Y) 2  and the second iNDAC Q41  receives the difference of the same two digital words and generates (X−Y) 2 . 
     The XD i I o     41    multiplier utilizes the following circuit and methods disclosed earlier: (a) A RBN 41  circuit that utilizes the multiple-channel data-converter method disclosed in section 19, (b) a pair of iNDAC P41  and iNDAC Q41  that utilizes the second non-linear digital-to-analog converter or the NDAC method disclosed in section 36′. Each of iNDAC P41  and iNDAC Q41  are generally identical and similarly configured as the embodiment depicted in  FIG. 39 , except it does not use AND gate decoding; (c) The linear multiplication sections of iNDAC P41  and iNDAC Q41  are similar to the embodiments of  FIG. 40  and  FIG. 33 , wherein the linear multiplication sections utilized the meshed digital-to-analog multiplication or mD i S o  method summarized in sections 32′, and (d) the PSR 41  circuit is substantially similar to the second power desensitization circuit embodiment and method or PSR summarized in section 40. 
     The RBN 41  circuit generates the following reference bias voltages (bus) on diode connected NMOSFETs for mostly the linear sub-iDACs of iNDAC P41  and iNDAC Q41 : V 1  via V GS  of N 1  whose I D  is set by P 1 &#39;s I D =1i r ; V 2  via V GS  of N 2  whose I D  is set by P 2 &#39;s I D =2i r ; V 4  via V GS  of N 4  whose I D  is set by P 4 &#39;S I D =4i r ; V 8  via V GS  of N 8  whose I D  is set by P 8 &#39;S I D =8i r ; V 16  via V GS  of N 16  whose I D  is set by P 16 &#39;s I D =16i r ; V 32  via V GS  of N 32  whose I D  is set by P 32 &#39;S I D =32i r . 
     Additionally, the RBN 41  circuit generates the following reference bias voltages (bus) on diode connected NMOSFETs for mostly the non-linear iDACs of iNDAC P41  and iNDAC Q41  (e.g., iDACs whose input-output transfer functions approximates a square profile): V 24  via V GS  of N 24  whose I D  is set by P 24 &#39;s=24i r ; V 40  via V GS  of N 40  whose I D  is set by P 40  &#39;s I D =40i r ; V 56  via V GS  of N 56  whose I D  is set by P 56 &#39;s I D =56i r ; V 72  via V GS  of N 72  whose I D  is set by P 72 &#39;s I D =72i r ; V 88  via V GS  of N 88  whose I D  is set by P 88 &#39;s I=88i r ; V 104  via V GS  of N 104  whose I D  is set by P 104 &#39;s I D =104i r . 
     Similar to the circuit in section 40 and illustrated in  FIG. 40 , also in the PSR 41  circuit here, the gate port of Pd 41  (through the loop comprised of Nd 1 , Nd 2 , Pd 2 , and Pd 3  and I r1 ) regulates the scaled current reference sources (e.g., P 1  through P 104 ) in order for the output currents of iNDAC P41  and iNDAC Q41  to be substantially desensitized to V DD  variations. 
     The SUB 41  is a simple embodiment of a current mirror that can perform the subtraction of the outputs current signals of the iNDAC P41  and the iNDAC Q41  and generate the analog multiplicand current signal of 4I XY . Note that to arrange a MAC which requires the summation of a plurality of multiplication results, the output of plurality of pairs of non-linear multiplier&#39;s outputs (e.g., plurality of iNDAC P41  and iNDAC Q41 ) can be coupled to the opposite side of the same current mirror circuit. As such, the current mirror can perform the function of subtraction (needed for pairs of non-linear DACs to generate the multiplicand results) and the function of addition (needed in MAC) with one subtractor circuit and in one shot, which save area, helps speed, and improves accuracy. 
     Next, the different sections of iNDAC P41  circuit is described in accordance with the partitioning of the second non-linear digital-to-analog converter or the NDAC method disclosed in section 36′: 
     The first linear offset LSP iDAC section of iNDAC P41  is a linear binary weighted iDAC whose current reference network is comprised of (NMOSFETs scaled with W/L of 1×) N 1P , N 2P , and N 3P  which operate at I D  of 1i r , 2i r , and 4i r , respectively. The current switches N 1Pf , N 2Pf , and N 3Pf  are controlled by the Least-Significant-Bit (LSB) bank word (e.g., P′ 1 , P′ 2 , and P′ 3  bits) which respectively steer the reference currents 1i r , 2i r , and 4i r  to the output port of the iNDAC P41 . 
     The linear multiplication section of iNDAC P41  utilizes the meshed digital-to-analog multiplication or mD i S o  method summarized in sections 32′, which is described next: 
     As described earlier, the linear multiplication section that utilizes the meshed multiplication in iNDAC P41  is also arranged with a plurality of scaled reference current signals proportional to ir 40  (that utilize NMOSFETs that are each scaled with W/L of 1×) comprising of 3 banks namely: The first scaled reference current bank is comprised of I D =2i, through N 4P , I D =4i r  through N 5P , and I D =8i, through N 6P . The second scaled reference current bank is comprised of I D =4i r  through N 7P , I D =8i r  through N 8P , and I D =816 through N 9P . The third scaled reference current bank is comprised of I D =8i r  through N 10P , I D =16i, through N 11P , and I D =32i r  through N 12P . 
     A first MSP sub-iDAC utilized in the meshed multiplication section of iNDAC P41  receives the first scaled reference bank (i.e., 2i r , 4i r , and 8i r ) at its current switch inputs that are the source-nodes of N 4p  and N 4p′  and N 4p″ . These current switches are controlled by P′ 4  bit. Accordingly, each of 2i r , 4i r , and 8i r  currents, which are gated by the P′ 4  bit, are respectively steered through current switches N 4p  and N 4p′  and N 4p″  to provide the scaled reference input currents to the first LSP sub-iDAC. Next, the said first LSP sub-iDAC reference currents are steered through current switches N 1p  and N 2p  and N 3p  that are controlled by the first LSP sub-iDAC&#39;s digital inputs P′ 1 , P′ 2 , and P′ 3  bits, respectively. The output of current switches N 1p  and N 2p  and N 33p  are summed together and coupled to the output port of the iNDAC P41 . 
     Similarly, a second MSP sub-iDAC utilized in the meshed multiplication section of iNDAC P41  receives the second scaled reference bank (i.e., 4i r , 8i r , and 16i r ) at its current switch inputs that are the source-nodes of N 5p  and N 5p′  and N 5p″ . These current switches are controlled by P′ 5  bit. Accordingly, each of 4i r , 8i r , and 16i r  currents, which are gated by the P′ 5  bit, are respectively steered through current switches N 5p  and N 5p′  and N 5p″  to provide the scaled reference input currents to the first LSP sub-iDAC. Next, the said first LSP sub-iDAC reference currents are steered through current switches N 1p , and N 2p , and N 3p , that are controlled by the first LSP sub-iDAC&#39;s digital inputs P′ 1 , P′ 2 , and P′ 3  bits, respectively. The output of current switches N 1p′  and N 2p′  and N 3p′  are summed together and coupled to the output port of the iNDAC P41 . 
     Furthermore, a third MSP sub-iDAC utilized in the meshed multiplication section of iNDAC P41  receives the second scaled reference bank (i.e., 8i r , 16i r , and 32i r ) at its current switch inputs that are the source-nodes of N 6p  and N 6p′  and N 6p″ . These current switches are controlled by P′ 6  bit. Accordingly, each of 4i r , 8i r , and 16i r  currents, which are gated by the P′ 6  bit, are respectively steered through current switches N 6p  and N 6p′  and N 6p″  to provide the scaled reference input currents to the first LSP sub-iDAC. Next, the said first LSP sub-iDAC reference currents are steered through current switches N 1p″  and N 2p″  and N 3p″  that are controlled by the first LSP sub-iDAC&#39;s digital inputs P′ 1 , P′ 2 , and P′ 3  bits, respectively. The output of current switches N 1p″  and N 2p″  and N 3p″  are summed together and coupled to the output port of the iNDAC P41 . 
     The non-linear MSP iDAC section of the iNDAC P41  is arranged as a non-linear (e.g., to approximate a square transfer function) thermometer iDAC. Here, the non-linear thermometer reference current network is comprised of NMOSFETs that are scaled with W/L of 1×, namely N 13P  through N 19P . The gate-ports N 13P  through N 19P  are respectively coupled to the reference network voltage busV 8 , V 24 , V 40 , V 56 , V 72 , V 88 , and V 104 , which are supplied from RBN 41  circuit. The drain currents of N 13P  through N 10P  are scaled to 8i r , 24i r , 40i r , 56i r , 72i r , 88i r , and 104i r  wherein i r  is programmed by Ir 1 . By inputting the proper polarity of the MSB bank word (xP′ 6 , xP′ 5 , and xP′ 4 ) to a 3-bit input to 7-bit output digital encoder (ENC P ), a 7-bit digital word is generated. The 7-bit output word of ENC control the NMOSFET current switches comprising of N t1p , N t2p , N t3p , N t4p , N t5p , N t6p , and N t7p  whose inputs are couple to their respective non-linear current source segments (e.g., 8i r , 24i r , 40i r , 56i r , 72i r , 88i r , and 104i r ) of the respective non-linear thermometer reference current network. As such, the current switches control the steering of the non-linear current source segments onto the outputs of the said current switches which are coupled together at the output node of the iNDAC P41 . 
     The iNDAC Q41  is arranged and operates the same as iNDAC P41 . 
     As noted earlier, an analog multiplicand current signal of 4X·Y can be generated by (setting P′=X+Y and Q′=X−Y and) inputting the proper polarity of P′ and Q′ into the digital input ports of iNDAC P41  and iNDAC Q41 , and then subtracting the outputs of iNDAC P41  and iNDAC Q41  via SUB 41 . Bear in mind that as such, the iNDAC P41  receives the sum of two digital words and generates (X+Y) 2  and the iNDAC Q41  receives the difference of the same two digital words and generates (X−Y) 2  and the (X+Y) 2 −(X−Y) 2 =4XY. 
     In conclusion, some of the benefits of the XD i I o  multiplier embodiment disclosed in  FIG. 41  are as follows: 
     First, the disclosed embodiment benefits from operating in current mode that has been discussed in this disclosure 
     Second, the dynamic response of XD i I o  multiplier is fast also in part because the scaled reference network banks are constant current sources whose current are steered by single MOFET switches which are inherently fast. 
     Third, current mirror loop associated with conventional multiplying iDACs (where a first iDAC&#39;s output signal supplies the reference signal to a second iDAC, generally through a current mirror) is avoided which reduces die size and helps improve dynamic response. 
     Fourth, the minimum power supply can be lowered since it is chiefly limited by the drain-to-source voltage of current sources of the scaled reference network. 
     Fifth, the disclosed embodiment of XD i I o     41    multiplier enjoys the benefits of the RBN 41  circuit that utilizes the multiple-channel data-converter method disclosed in section 19. 
     Sixth, the disclosed embodiment of XD i I o     41    multiplier enjoys the benefits of the pair of iNDAC P41  and iNDAC Q41  that utilizes the second non-linear digital-to-analog converter method disclosed in section 36′. 
     Seventh, the disclosed embodiment of XD i I o     41    multiplier enjoys the benefits of iNDAC P41  and iNDAC Q41  which are similarly configured to the embodiment disclosed in section 39. 
     Eight, the disclosed embodiment of XD i I o     41    multiplier enjoys the benefits of the linear multiplication sections of iNDAC P41  and iNDAC Q41  which are similar to the embodiments disclosed in sections 40 and 33, wherein the linear multiplication sections utilized the meshed digital-to-analog multiplication method summarized in sections 32′, and 
     Ninth, the disclosed embodiment of XD i I o     41    multiplier enjoys the benefits of the PSR 41  circuit that is substantially similar to the second power desensitization circuit embodiment and method summarized in section 40. 
     An inherent benefit of the disclosed embodiment of XD i I o     41    multiplier is that since both digital inputs to the XD i I o     41    multiplier (e.g., x+y and x y) are squared and subsequently the (x+y) 2  term and the (x−y) 2  term are subtracted from one another, the 4xy multiplicand result can be bi-directional which is beneficial for multi-quadrant signal processing. 
     Section 42—Description of FIG.  42   
       FIG. 42  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) of a XD i I o  versus the simulated output current (Io simulation ) of a XD i I o  that is arranged similar to that of  FIG. 34  but with a 4-bit resolution. 
     Keeping in mind that 4-bit of resolution computes to about 6% of accuracy,  FIG. 42  indicates DNL (differential non-linearity) and INL (integral non-linearity) of less than about ±3%. The X and Y digital input words span in the opposite direction, between zero and full scale, while stepping the digital words with one LSB increments each 1 micro-seconds (μs). The lower graph in  FIG. 42  indicates a power consumption of less than about 80 nano-ampere. 
     Section 43—Description of FIG.  43   
       FIG. 43  is a SPICE circuit simulations that illustrates the linearity error in % between an ideal output current (Io ideal ) of a XD i I o  versus the simulated output current (Io simulation ) of a XD i I o  multiplier that is arranged similar to that of  FIG. 40  but with a 6-bit resolution. 
     As noted, the XD i I o  multiplier of  FIG. 43  is inputted with an 6-bit (X-word digital input) by an 6-bit (Y-word digital input) wherein the X and Y digital input words are ramped in the same direction between zero-scale to full scale. Here, the linearity of XD i I o  is illustrated for power supply V DD =2V (in the lower waveform of  FIG. 43 ) and V DD =2V (in the upper waveform of  FIG. 43 ). 
     Keeping in mind that 6-bit of resolution computes to about 1.6% of accuracy,  FIG. 43  indicates DNL (differential non-linearity), INL (integral non-linearity), and GE (gain-error) of less than about ±1.6% for V DD  between 1V to 2V. By utilizing the multiplier power supply desensitization method combined with the multiple-channel iDAC method in a XD i I o ,  FIG. 43  indicates that the XD i I o  is substantially desensitized from power supply variations. 
     Section 44—Description of FIG.  44   
       FIG. 44  illustrates SPICE circuit simulations comprising of an ideal square iDAC&#39;s output current (I X   2 ) plot versus the simulated output current (I O   2 ) plot of a square iDAC that is arranged similar to that of  FIG. 38  but with a 7-bit resolution. 
     Keeping in mind that 7-bit of resolution computes to about 0.8% of accuracy, the lower graph in  FIG. 44  indicates a % error between I X   2  and I O   2  indicating less than about ±0.8% error in DNL (differential non-linearity) and INL (integral non-linearity). The X and Y digital input words span in the same direction, between full scale and zero. The upper graph in  FIG. 44  is a plot of the square iDAC&#39;s I O  output current simulation versus that of an ideal square iDAC (offset by a few % for clarity of the illustration). 
     Section 45—Description of FIG.  45   
       FIG. 45  illustrates SPICE circuit simulations comprising of an ideal square iDAC&#39;s output current (I X   2 ) plot versus the simulated output current (I O   2 ) plot of a square iDAC that is arranged similar to that of  FIG. 39  but with a 7-bit resolution. 
     Keeping in mind that 7-bit of resolution computes to about 0.8% of accuracy, the upper graph in  FIG. 45  indicates a % error between I X   2  and I O   2  indicating less than about ±0.8% error in DNL (differential non-linearity) and INL (integral non-linearity). The X and Y digital input words span in the same direction, between zero and full scale. The lower graph in  FIG. 44  is a plot of the square iDAC&#39;s I O  output current simulation versus that of an ideal square iDAC (offset by a few % for clarity of the illustration). 
     Section 46—Description of FIG.  46   
       FIG. 46  illustrates SPICE circuit simulations comprising of an ideal XD i I o &#39;s output current (Io ideal ) plot versus the simulated output current (Io simulation ) plot of a XD i I o  multiplier that is arranged similar to that of  FIG. 41  but with a 7-bit resolution. As a reminder the XD i I o  multiplier utilizes iDACs whose transfer functions follows an approximate square transfer function. Also, note that Io ideal =((x+y) 2 −(x−y) 2 )=4xy 
     As noted, the XD i I o  multiplier of  FIG. 41  is inputted with a 7-bit (X+Y) and a 7-bit (X−Y) digital words, wherein X and Y digital words are ramped in the same direction between zero-scale to full scale. 
     Keeping in mind that 7-bit of resolution computes to about 0.8% of accuracy,  FIG. 46  indicates DNL (differential non-linearity) and INL (integral non-linearity) of less than about ±0.8%.