Patent Publication Number: US-6215908-B1

Title: Symmetric filtering based VLSI architecture for image compression

Description:
BACKGROUND 
     (1) Field 
     The present invention relates to signal/image processing. More specifically, the present invention relates to image compression. 
     (2) Background Information 
     Using traditional Fourier analysis transforms, any signal may be approximated as a sum of sinusoidal waveforms of assorted frequencies. While Fourier transforms are ideally suited for signals having repeated behavior, such as speech signals, Fourier transforms fail to efficiently approximate signals with sharp discontinuities such as the edge features of images, or signals encoded for digital communications. 
     Wavelets are used as a way to represent an image in both the frequency and spatial domain. Due to quantization effects, less visual side effects are produced when using wavelets compared to a block based discrete cosine transform (DCT). A transform, similar to the Fourier transform, Discrete Wavelet Transform (DWT), based on Wavelet analysis, has been developed to represent signals with discontinuous features. The DWT is a “discrete” algorithm, that rather than approximating a signal using continuous waveforms, approximates the signal by discrete samples of waveforms. Since the transform is discrete, the DWT may be implemented using digital logics such as Very Large Scale Integrated (VLSI) circuits. Thus DWT may be integrated on a chip with other digital components. 
     The essence of DWT is to decompose an input signal into two or more frequency sub-bands. An input signal may be decomposed into two outputs—a low frequency sub-band output, obtained by using a low-pass filter, and a high frequency sub-band output, obtained by using a high-pass filter. Each of these sub-bands may be encoded separately using a suitable coding system. Each sub-band may further be divided into smaller and smaller sub-bands as is required. 
     In general, DWT is a computationally very intensive process and hence very slow when computed using a general purpose computing system. To make it suitable for real-time applications, a special purpose custom VLSI chip may be used for DWT, exploiting the underlying data parallels to yield high throughput and hence high data rate. Several VLSI architectures for DWT have been proposed. However, most of these complex architectures require large hardware area and yield much less than 100 percent hardware utilization. It is desirable to provide a new DWT architecture for performing image compression that utilizes a reduced number of hardware parts. 
     SUMMARY 
     Briefly, in one embodiment, the present invention provides an apparatus to perform symmetric filtering image compression. The apparatus includes an N-element shift circuit, that has N shifting blocks (SB), to store and shift data elements. Each data element represents a pixel of an image. The apparatus also includes a first plurality of adder circuits to add data elements from a first plurality of pairs of SBs of the N SBs. The apparatus further includes a second plurality of adder circuits to add data elements from a second plurality of pairs of SBs of the N SBs. Additionally, the apparatus includes a first plurality of multiplier circuits, to multiply by corresponding low pass coefficients results of additions performed by the first plurality of adder circuits. The apparatus also includes a second plurality of multiplier circuits, to multiply by corresponding high pass coefficients results of additions performed by the second plurality of adder circuits. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The features, aspects, and advantages of the present invention will become more fully apparent from the following Detailed Description, appended claims, and accompanying drawings in which: 
     FIG. 1 is a block diagram illustrating basic steps involved in the filtering operation implemented by the apparatus according to the present invention; 
     FIG. 2 is a block diagram illustrating the apparatus for performing symmetric filtering image compression according to one embodiment of the present invention; 
     FIG. 3 is a block diagram illustrating the apparatus shown in FIG. 2 where data elements shifted to the right by 2 and two additional data elements added; 
     FIG. 4 is a block diagram illustrating the apparatus of FIG. 3 where data elements are shifted to the right by 2 and two additional elements are added; 
     FIG. 5 is a block diagram illustrating the apparatus of FIG. 4 where data elements stored therein are shifted to the right by 2 and two additional data elements are added; 
     FIG. 6 is a block diagram illustrating the apparatus of FIG. 5 where data elements are shifted to the right by 2 and two data elements are added; 
     FIG. 7 is a block diagram illustrating the apparatus of FIG. 2 with the low pass elements L 0 -L 4  stored therein; and 
     FIG. 8 is a flow chart diagram in connection with an embodiment of a process of obtaining low and high pass coefficients according to the present invention. 
    
    
     DETAILED DESCRIPTION 
     In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art should recognize that the invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention. 
     Discrete wavelet transform (DWT) based image compression is usually a computationally expensive process. Selection of a basis function is an important criteria to achieve expected performance and for efficient implementation. In one embodiment of the present invention, a 9-7 biorthongonal Spline filtering based DWT that is suitable for image compression applications is utilized. A symmetric filtering architecture is utilized for optimal implementation of this particular DWT-based image compression scheme. 
     A DWT decomposes an arbitrary data sequence (hereinafter referred to as “data elements”) d={d 0 , d 1 , . . . d n −1} into a low-pass sub-band        L   =     {     Lo   ,     L   1     ,   …              ,       L   N       2   -   1         }                     
     and a high-pass sub-band        H   =     {     H0   ,   H1   ,   …              ,       H   N       2   -   1         }                     
     which can be represented as 
     
       
         
           L 
           n 
           =Σh 
           2n−k 
           d 
           k 
           , H 
           n 
           =Σg 
           2n−kdk 
         
       
     
     for n=0, 1, . . . N/2−1 
     where h i  and g i  are the low-pass and high-pass filter coefficients respectively and H I  and L I  are data coefficients. The 9-7 biorthogonal spline filter based DWT, which is utilized in one embodiment of the present invention, is well known in the art and is suitable for image compression applications. The 9-7 biorthogonal spline filter has 9 low-pass filter coefficients {h —4 ,h —3 ,h —2 ,h —1 ,h 0 ,h 1 ,h 2 ,h 3 ,h 4 } and 7 high-pass filter coefficients {g —3 , g —2 , g —1 ,g 0 ,g 1 ,g 2 ,g 3 }. Using the 9-7 biorthongonal spline filter, the low-pass sub-band samples L n  for n=0, 1, . . . , N/2−1 may be expressed as, 
     L 0 =h 0 d 0 +2h —1 d 1 +2h —2 d 2 +2h —3 d 3 +2h —4 d 4 , 
     L 1 =h 2 d 0 +h 1 d 1 +h 0 d 2 +h —1 d 3 +h —2 d 4 +h —3 d 5 +h —4 d 6 , +h 4 d 2 +h 3 d 1    
     L 2 =h 4 d 0 +h3d 1 +h 2 d 2 +h 1 d 3 +h 0 d 4 +h —1 d 5 +h —2 d 6 +h —3 d 7 +h —4 d 8    
     The other L i  terms may be expressed in a similar fashion. Since low-pass filter coefficients are symmetric i.e., h —i =h i  the above presented L i  terms for the low-pass sub-band may be rearranged in a fashion as follows: 
     L 0 =h 0 (0+d 0 )+h 1 (d 1 +d 1 )+h 2 (d 2 +d 2 )+h 3 (d 3 +d 3 )+h 4 (d 4 +d 4 ), 
     L 1 =h 0 (0+d 2 )+h 1 (d 1 +d 3 )+h 2 (d 0 +d 4 )+h 3 (d 1 +d 5 )+h 4 (d 2 +d 6 ), 
     L 2 =h 0 (0+d 4 )+h 1 (d 3 +d 5 )+h 2 (d 2 +d 6 )+h 3 (d 1 +d 7 )+h 4 (d 0 +d 8 ) 
     and similarly the other L i  terms. 
     Using the 9-7 biorthongonal spline filter, the high-pass sub-band samples H n  for n=0, 1, . . . , N/2−1 may be expressed as 
     H 0 =g 0 d 1 +g 1 (d 0 +d 2 )+g 2 (d 1 +d 3 )+g 3 (d 2 +d 4 ), 
     H 1 =g 0 d 3 +g 1 (d 2 +d 4 )+g 2 (d 1 +d 5 )+g 3 (d 0 +d 6 ) 
     The other H i  terms may be expressed in a similar fashion. 
     In one embodiment a one dimensional 9-7 biorthongonal-spline-filter-based DWT transforms a N-block of data into an N/2 high pass block of data and N/2 low-pass block of data. This process creates sub-bands that represent the image at different resolutions in varying significance to the human eye. The low-pass filter coefficients and high-pass filter coefficients are symmetrical, where h— i =h i  and g— i =g i . 
     The basic steps involved in a filtering operation are summarized in FIG.  1 . In FIG. 1, incoming data elements d i  are convolved with two filters: h, which is a 9-tap low-pass filter; and g which is a 7-tap high-pass filter. According to Nyquist&#39;s theory, as the resulting filtered representations do not contain the full frequency band width of the original image, one may reconstruct the filtered representation without utilizing all N elements. As a result, an apparatus of the present invention (not shown), based on the scheme of FIG. 1, performs a convolution on every other data element. 
     In Step 1, the following operations may be performed: 
     L 0 =h 0 d 0 +h 1 d 1 2+h 2 d 2 2+h 3 d 3 2+h 4 d 4 2 
     H 0 =g 0 d 1 +g 1 (d 0 +d 2 )+g 2 (d 1 +d 3 )+g 3 (d 2 +d 4 ) 
     where L refers to the low pass coefficient and H to the high pass coefficient. 
     The operations shown above and performed in Step 1 may be easily understood in connection with the following blocks illustrated FIG.  1 . FIG. 1 illustrates block  102  (shown within dotted lines) that includes a sub-block  108  of data elements d 0 -d 7  demarcated by vertical dotted lines  104  and  106 . Block  102  also includes sub-block  110  that includes data elements d 1 , d 2 , d 3 , and d 4 . Data elements d 1 , d 2 , d 3 , and d 4  are symmetrically disposed about data element d 0 . One reason that data is symmetrically disposed about d 0  is to reduce edge effects. Each data element d i  is a 16-bit quantity that characterizes a pixel of an image, or the result of a previous filtering operation. 
     The block diagram illustrated in FIG. 1 illustrates in 4 steps how the low pass coefficients h 0 , h 1 , h 2 , h 3  and h 4  and the high pass coefficients g 0 ,g 1 ,g 2  and g 3  are disposed relative to the block of data  102 . Convolutions between the data elements d i  and the coefficients h i  and g i  may be calculated more easily, when knowing how to dispose coefficients h i  and g i  with respect to the data elements d i  of block  102 . 
     Looking now at the sub-block of data demarcated by dotted lines  112  and  114 , the result of the convolution between this block of data elements and the low pass coefficients h i  may be calculated in the following way. One multiplies each low pass coefficient h i  with its vertically corresponding data element d i . As a result, the multiplication in the vertical direction from left to right yields the following results: 
     h 4 d 4 , h 3 d 3 , h 2 d 2 , h 1 d 1 , h 0 d 0 , h 1 d 1 , h 2 d 2 , h 3 d 3 , and h 4 d 4 , 
     Adding the results of the multiplication horizontally, one may obtain the value: 
     L 0 =h 0 d 0 +h 1 d 1 2+h 2 d 2 2+h 3 d 3 2+h 4 d 4 2. 
     By doing the same multiplication in the vertical direction and addition in the horizontal direction, the convolution between the high pass coefficients gi and data elements di gives rise to the following products: 
     g 3 d 2 , g 2 d 1 , g 1 d 0 , g 0 d 1 , g 1 d 2 , g 2 d 3 , g 3 d 4    
     Adding these results of the multiplication in a horizontal direction one obtains H 0 =g 0 d 1 +g 1 (d 0 +d 2 )+g 2  (d 1 +d 3 )+g 3 (d 2 +d 4 ). 
     At Step 2, the convolution is performed by shifting the blocks of low pass coefficients h i  116 and of high pass coefficients g i  118 by 2 places to the right as is shown in the figure at Step 2. At this step the results of the convolutions between the low pass coefficients h i  and the data elements d i  are calculated in the following way. The multiplication between hi and di in the vertical direction yields the following results: 
     h 4 d 2 , h 3 d 1 , h 2 d 0 , h 1 d 1 , h 0 d 2 , h 1 d 3 , h 2 d 4 , h 3 d 5  and h 4 d 6 . 
     The addition of these results produces: 
     L 1 =h 0 d 2 +h 1 (d 1 +d 3 )+h 2 (d 0 +d 4 )+h 3 (d 1 +d 5 )+h 4 (d 2 +d 6 ). 
     Similarly, the high pass coefficient H 1  is obtained by convolving di with the high pass coefficients gi shifted to the right by 2 relative to the previous high pass coefficients from Step 1. Therefore, the centers of both the low pass and high pass filter have moved two places over to the right. The resulting high pass coefficient H 1  is: 
     H 1 =g 0 d 3 +g 1 (d 2 +d 4 )+g 2 (d 1 +d 5 )+g 3 (d 0 +d 6 ). 
     One thing to note is the data in the double bordered boxes in FIG.  1 . Since the filter is non-causal, one needs to account for this at the boundaries. One technique is to symmetrically extend the data around the boundaries to reduce boundary effects. 
     FIG. 2 illustrates a high level block diagram of an embodiment  200  of an apparatus for performing symmetric filtering image compression according to the present invention. The apparatus  200  includes a N-element shift circuit  201 , shown in dotted lines, that includes N shifting blocks. In one embodiment of the present invention, the N-element shift circuit  201  includes 9 shifting blocks  202 ,  204 ,  206 ,  208 ,  210 ,  212 ,  214 ,  216  and  218 . The shifting blocks are configured to store data elements therein and to shift the data elements stored therein to a next shifting block. In one embodiment of the apparatus of the present invention each shifting block includes a shift register R i . Shift registers R i  are 16-bit shift registers to accommodate the 16-bit data elements d i . Data elements such as d 0 ,d 1 ,d 2 , etc., are shifted between successive registers Ri from left to the right in the figure. 
     Initially five data elements, d 0 -d 4  are provided to circuit  264  which is explained later in this section. Circuit  264  outputs data elements d 0 -d 4 , passed through circuits  260  and  262 , to a multiplexor  266 . During the first pass, that includes steps 1-4, multiplexor  266  selects at an output thereof the data elements passed through circuits  260  and  262 . Data elements d 0 -d 4 , output by multiplexor  266 , are then shifted from left to right in the figure through registers R 0 , R 1 , R 2 , R 3 , R 4 , such that at the end of the shifting operation R 0  stores d 4 , R 1  stores d 3 , R 2  stores d 2 , R 3  stores d 1  and R 4  stores d 0 . 
     FIG. 3 illustrates in diagrammatic form the configuration of apparatus  200  with data elements d 0 ,d 1 ,d 2 ,d 3  and d 4  symmetrically stored in apparatus  200 . After data elements d 0 -d 4  are stored in registers R 4 -R 0  respectively, as shown in FIG. 2, data elements R 3 , R 2 , R 1  and R 0  are symmetrically copied into registers R 5 , R 6 , R 7 , and R 8 , respectively about register R 4  as the arrows  268 ,  270 ,  272  and  274 , indicate. More specifically, d 1  is copied from R 3  to R 5 , d 2  is copied from R 2  to R 6 , d 3  is copied from R 1  to R 7  and d 4  is copied from R 0  to R 8 . 
     The apparatus  200  has the hardware support to perform symmetric copying. The implementation of the hardware support to symmetrically copy data elements about register R 4  is not explained herein as it is within the ambit of the knowledge of persons having ordinary skills in the art. The first pass is performed to obtain the low and the high pass filter coefficients L 0 , H 0 , L 1 , H 1 , L 2 , H 2 , L 3 , H 3 , L 4 , H 4 . In the second pass instead of taking data elements d 0 -d 7  and passing them through registers R 0 -R 8  of the apparatus according to the present invention, elements L 0 , L 1 , L 2 , L 3 , L 4 , H 0 , H 1 , H 2 , H 3 , H 4  are passed directly through registers R 0 -R 8  and the respective operations explained above are performed on these elements. The operations of symmetrically copying data about center register R 4  lead to a sequence of data elements stored in registers R 0 -R 8 . This sequence is the same as the sequence of data elements shown in FIG. 1 in the block demarcated by dotted lines  112  and  114 . In FIG. 1, data elements disposed within lines  112 - 114  are extended symmetrically about d 0 , i.e., the portion of 4 data elements at the left of d 0  is the mirror image of the portion of data elements at the right of d 0 . 
     The operations for obtaining the low pass coefficient L 0  by way of apparatus  200  include the following. Data elements stored in each symmetric pair of registers (R 3 ,R 5 ), (R 2 ,R 6 ), (R 1 ,R 7 ) and (R 0 ,R 8 ) are added therebetween in corresponding circuits  230 ,  232 ,  234  and  236  which are coupled to the above-mentioned symmetric pairs of registers. Hereinafter, circuits  230 ,  232 ,  234  and  236  are called “add-dividers” as these circuits provide two functionality&#39;s: adding the pairs of data elements from the pairs of symmetrically extended registers, coupled to the add-divider; and dividing the result of the addition by 2 by extracting the 16 most significant bits. The reason for the division by 2 is that the addition of two 16-bit data elements gives rise to a 17-bit result. Since the logic of the apparatus illustrated in FIGS. 2-7 utilizes 16 bit buffers, the 17 bits are reduced to 16 bits by shifting out one bit from the left to the right. This is analogous with division by 2. 
     The apparatus of FIG. 3 further includes a plurality of first multipliers  240 ,  242 ,  244 ,  246  and  248 . Multipliers  240 ,  242 ,  244 , and  246  are coupled to corresponding add-dividers  236 ,  234 ,  232 , and  230  respectively. These multipliers multiply the low pass coefficients h 1 , h 2 , h 3  and h 4  with the result obtained by the operations performed by the add-dividers, i.e., addition of two symmetrical data elements and division of the result of the addition by 2. Moreover, the low pass coefficients h 1 -h 4  are multiplied by 2 to compensate the division by 2 of the result of the addition of the symmetric data elements. After these operations are performed, multipliers  240 - 246  produce at the output ports thereof, values 2h 4 d 4 , 2h 3 d 3 , 2h 2 d 2  and 2h 1 d 1  respectively. Data element d 0  is multiplied by h 0  in multiplier  248  coupled to register R 4 . Multipliers  248 ,  246 ,  244 ,  242  and  240  are coupled to adder  250  that adds the results of the multiplications by the multipliers. The result of the addition, in adder  250 , is the first low pass coefficient L 0  which is equal to 
     h 0 d 0 +2h 1 d 1 +2h 2 d 2 +2h 3 d 3 2 +2h 4 d 4 . 
     The apparatus of FIGS. 2 and 3 also calculates the high pass coefficient H 0 . Data elements of a plurality of pairs of registers are added together. Data elements of registers R 2  and R 4  are added together in an add-divider  222 . Data elements of registers R 1  and R 5  are added together in add-divider  224 . Data elements of registers R 0  and R 6  are added together in add-divider  226 . The add-dividers mentioned above are configured to add pairs of data elements that are coupled thereto and then to divide the result of the addition by 2. Accordingly, after adding two data elements, from symmetrically disposed shift registers, add-dividers  222 ,  224 , and  226  are configured to divide the result of the addition by two. In the particular example explained herein in connection with the embodiment illustrated in FIG. 3, data elements d 0  and d 2  are added in add-divider  222  and the result of the addition is divided by 2. Data elements d 3  and d 1  are added in add-divider  224  and the result of the addition is divided by 2. Data elements d 4  and d 2  are added in add-divider  226  and the result of the addition is divided by 2. 
     After the above-mentioned operations are performed, the results of these operations are multiplied by 2g 3 , 2g 2  and 2g in multipliers  227 ,  225  and  223  respectively. The data element d 1  from register  4  is multiplied by the coefficient g 0  in multiplier  221 . The results of the multiplications are then added in adder  251 . Adders  250  and  251  include 32 bit accumulators that store the results of the additions. The results of the addition from adder  250  are then multiplied by the coefficient hfq and the results of the addition in block  251  is multiplied by coefficient gfq. Multiplications by gfq and hfq represent how the accumulated results may be quantized prior to outputting the results. Quantization is a step down in image compression to reduce the range of incoming data by multiplying the element by a fraction. 
     The apparatus  200  according to the present invention takes advantage of the symmetrical configuration of the stored data elements di and of the low and high pass coefficients. Due to the symmetrical configuration, only one multiplication is performed instead of two multiplications. 
     FIG. 4 illustrates the apparatus of FIG. 3 where data elements are shifted to the right by 2 by the shifting circuit  201 . Data elements d 5  and d 6  are shifted into register R 1  and R 0  respectively. 
     The configuration shown in FIG. 4 produces, at Step 2, the low pass and high pass coefficients L 1  and H 1 . In this case d 2  stored in register R 4  is multiplied in multiplier  248  by low pass coefficient h 0 . Data elements d 1  and d 3  stored in symmetrically disposed registers R 5  and R 3  are added by add-divider  230  and the result divided by 2. The result of the addition divided by 2 is then multiplied in multiplier  246  by the quantity 2h 1 . Data stored in registers R 2  and R 6 , i.e., d 4  and d 0 , respectively is added by the add-divider  232  and the result is divided by 2. After that, the result of the addition is multiplied by 2h 2  in multiplier  244 . Data in registers R 7  and R 1 , i.e., d 1  and d 5 , respectively, is added by add-divider  234  and then the result of the addition is divided by 2. The result of the addition is then multiplied by 2h 3  in multiplier  242 . Last, data stored in registers R 0  and R 8 , d 6  and d 2  respectively, is added by add-divider  236  and the result is divided by 2. The result of the addition is provided to multiplier  240  that multiplies it with the quantity 2×h4. The results of the multiplication operations output by multipliers  240 ,  242 ,  244 ,  246  and  248  are added in adder  250  to produce the quantity L 1 . Data stored in registers R 0 -R 8  is subjected to similar operations performed by add-dividers  226 ,  224 ,  222  and multipliers  227 ,  225 ,  223  and  221  to obtain high pass coefficient H 1 . 
     FIG. 5 illustrates the apparatus of FIG. 4 where data elements stored in registers R 0 -R 8  are shifted to the right by 2 and new data elements d 7  and d 6  are stored in registers R 1  and R 0  respectively. The rest of the operations concerning additions between data elements and division by 2, multiplication with low and high pass coefficients hi and gi, and addition of the results by adders  250  and  251  are the same as the operations explained above in connection with the description of the previous figures. 
     FIG. 6 illustrates the apparatus of FIG. 5 where data elements stored in registers R 0 -R 8  are shifted to the right by 2. Data elements d 5  and d 4  are stored in registers R 1  and R 0  respectively. Since d 7  represents the last piece of data in this example, the apparatus starts symmetrically copying data around d 7  to wrap up calculations. 
     Low pass coefficients L 0 -L 4  and high pass coefficients H 0 -H 4  may be obtained after data elements are passed through the shift circuit  201  of the apparatus  200  and the operations explained earlier in connection with additions and multiplications are performed. More passes made with L 0 -L 4  and H 0 -H 4  may then be performed by way of the apparatus  200  and the methodology of processing data explained above. 
     FIG. 7 illustrates the apparatus of FIG. 2 where low pass elements L 0 -L 4  obtained in the first pass are shifted through registers R 0 -R 4 . Then the contents of registers R 3 -R 0  are symmetrically copied, about register R 4 , to registers R 5 ,R 6 ,R 7 , and R 8 . Note that in this case L 0 -L 4  are not processed by circuits  260  and  262  but rather are directly provided to the shift circuit  201  by multiplexor  266  that selects to the output thereof the input directly coupled to L 0 , L 1 , L 2 , L 3  and L 4 . The apparatus  200  then processes the coefficients Li and Hi in a fashion similar to the fashion in which data elements d i  were processed. In the first step of the second pass coefficients LL 0  and HL 0  are obtained. In the second step of the second pass coefficients, LL 1  and HL 1  are obtained and so on. 
     The running sums of the operations are stored in 32 bit accumulators included in adders  250  and  251 . The 32 bit accumulator is advantageous over previous 40 bit and 54 bit accumulators used in digital signal processing. While typically all architectures that perform DWT utilize floating point number representation, the present invention utilizes 16 bit fixed point representation of a fraction. By extracting the 16 left most significant bits of a fraction, one is maintaining as much precision from operation to operation as possible. Since each data element is a 16 bit data element, the results of the additions performed by the add-dividers are also configured to be 16 bit fixed point representations of a fraction. 
     Converting numbers from a floating point to a fixed point arithmetic is an operation that is well known in the art. On the first pass through apparatus  200 , unsigned data elements are converted to fixed point fractions by performing a level shift on the data and normalizing the result. In one embodiment of the present invention, shifting device  260  receives d 0 -d 4  data elements, each having 16 bits, and converts the values of the data elements into fixed point fractions by first subtracting an offset value which in one embodiment of the present invention is 128. The value 128 is subtracted from the value of each data element so that the values of the data elements are between −128 and 127 and, therefore centered around 0. 
     Further to convert into a fraction the value of the data element from which 128 was subtracted, one divides that value by 256 because the maximum value of a 16 bit digital number is 256. The result of this division is a fraction in the floating point sense. To extract the most significant 16 bits of that number, one needs to multiply the number by 2 16 . Multiplying the number by 2 16  and dividing the number by 256 is equivalent to multiplying the number by 2 8  which is equivalent to shifting in 8 zeros to the left. Circuits  260  and  262  that perform level shifting and normalization operations, respectively are standard off-the-shelf circuits known by persons having ordinary skill in the art. The operations described above with respect to obtaining fixed point numbers are performed only during the first pass. 
     FIG. 8 illustrates a flow chart diagram in connection with an embodiment of a process for obtaining coefficients L 0 -L 4  and H 0 -H 4  according to the present invention. The process starts at block  802  where index i is assigned the value “0”. The process then flows to block  804  where data in all registers R 0  through R 8  is shifted to the right by 1. After this step register R 0  stores data element d 0 . Then the index i is assigned a value of i+1. The process then flows to decision block  806  where it is determined whether i=4. In this case, since i=1 the process flows back to block  804  where, again, one new data element is shifted in register R 0  and the contents of the other registers are shifted to the right by 1. After this pass, data element d 1  is stored in register R 0  and data element d 0  is stored in register R 1 . Then the value i is assigned a value “2” and the process flows to decision block  806  where, again, it is determined if i=4. As i equals 4, the process flows back to block  804  where a new data element is shifted into register R 0  and the contents of the rest of the registers are shifted to the right by 1. At this step, register R 0  stores data element d 2 , register R 1  stores data element d 1  and register R 3  stores data element d 0 . Then i is incremented to “3” and the process flows back to decision block  806 . The process flows back to block  804  as i is not yet equal to “4”. A new data element is shifted into R 0  and the contents of the rest of the registers are shifted to the right by one. Data element d 3  is stored in register R 0 , data element d 2  is stored in register R 1 , data element d 1  is stored in register R 2  and data element d 0  is stored in register R 3 . Index “i” is then incremented by “1” therefore becoming equal to “4”. The process flows to block  806  from where it flows to block  814  as i=4. At block  814 , data in the registers R 0  through R 8  is shifted to the right by “1” and register R 0  receives the value d i  which is d 4 . Then the process performs symmetric copying of data about register R 4  which stores data element d 0 . After the symmetric copying of data about register R 4  the apparatus that performed this process is configured as illustrated in FIG.  3 . Coefficients L 0  and H 0  are calculated as explained earlier in this description. 
     The process then follows to block  816  where again data from all registers is shifted to the right by “1” and register R 0  receives the value d i+1  which is d 5 . Then at the same block  816 , data is again shifted from each register to the right by “1” and register R 0  receives data element d i+2  which is d 6  in this embodiment. Coefficients L 1  and H 1  are calculated as explained earlier in this description. 
     From block  816 , the process then flows to block  818  where data from the registers is shifted to the right by “1” and register R 0  receives data element d i+3  which in this embodiment is d 7 . Then data elements in the registers are again shifted to the right by “1” and register R 0  receives the data element d i+2  which is d 6 . Coefficients L 2  and H 2  are calculated as explained earlier in this description. 
     The process then flows to block  820  where data elements are shifted in the registers to the right by “1” and register R 0  receives the value d i+1 . Data is shifted in the registers to the right by “1” and register R 0  receives data element d i . Coefficients L 3  and H 3  are calculated as explained earlier in this description. 
     In the preceding detailed description, the invention is described with reference to specific embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.