Patent Publication Number: US-2017367191-A1

Title: Printed circuit board

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This is a divisional application of patent application Ser. No. 14/848,517, filed on Sep. 9, 2015, assigned to the same assignee, which is based on and claims priority to Chinese Patent Application number 201510279753.5 filed on May 27, 2015, the contents of which are incorporated by reference herein. 
    
    
     FIELD 
     The subject matter herein generally relates to a printed circuit board. 
     BACKGROUND 
     In the field of printed circuit boards, the circuit board generally includes plating wires to electroplate the surface treatment layers for the bonding pads after forming the solder mask layer. The plated wires are extended from the bonding pads to the edge of the printed circuit board and are covered by the solder mask layer. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Implementations of the present technology will now be described, by way of example only, with reference to the attached figures. 
         FIG. 1  is a cross sectional view of a substrate according to one embodiment of the present disclosure. 
         FIG. 2  is a cross sectional view of substrate in  FIG. 1  after drilling a through hole. 
         FIG. 3  is a cross sectional view of a substrate in  FIG. 2  after forming a seed layer on the surfaces of the copper foil layers and the wall of the through hole. 
         FIG. 4  is a cross sectional view of substrate in  FIG. 3  after forming the first and second patterned resist layers on part of the surface of the seed layer. 
         FIG. 5  is a cross sectional view of substrate in  FIG. 4  after forming the first and second conductive layers on part of the surface of the seed layer without removing the first and second patterned resist layers. 
         FIG. 6  is a cross sectional view of substrate in  FIG. 5  after forming the third and fourth patterned resist layers on the surfaces of the first and second patterned resist layers and part of the surfaces of the first and second conductive layers. 
         FIG. 7  is a cross sectional view of substrate in  FIG. 6  after forming the first and second surface treatment patterned layers on the exposed surfaces of the first and second conductive layers. 
         FIG. 8  is a cross sectional view of substrate in  FIG. 7  after removing the first, second, third, and fourth patterned resist layers. 
         FIG. 9  is a cross sectional view of substrate in  FIG. 8  after etching part of the first and second conductive layers without covering the first and second surface treatment patterned layers, the exposed seed layers, and the first and second copper foil layers under the exposed seed layers. 
         FIG. 10  is a cross sectional view of substrate in  FIG. 9  after forming the first solder mask layer and the second solder mask layer on the surfaces of the first and second conductive layers which are not covered with the first and second surface treatment patterned layers and on part of the surfaces of the first and second surface treatment patterned layers. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     It will be appreciated that for simplicity and clarity of illustration, where appropriate, reference numerals have been repeated among the different figures to indicate corresponding or analogous elements. In addition, numerous specific details are set forth in order to provide a thorough understanding of the embodiments described herein. However, it will be understood by those of ordinary skill in the art that the embodiments described herein may be practiced without these specific details. In other instances, methods, procedures, and components have not been described in detail so as not to obscure the related relevant feature being described. Also, the description is not to be considered as limiting the scope of the embodiments described herein. The drawings are not necessarily to scale and the proportions of certain parts may be exaggerated to better illustrate details and features of the present disclosure. 
     The term “comprising,” when utilized, means “including, but not necessarily limited to”; it specifically indicates open-ended inclusion or membership in the so-described combination, group, series, and the like. 
       FIG. 1  to  FIG. 10  illustrate a method of making a printed circuit board  10 . 
       FIGS. 1 to 10  are presented in accordance with an example embodiment. The one or more examples shown in  FIGS. 1 to 10  is provided by way of example, as there are a variety of ways to carry out the method. The method described below can be carried out using the configurations illustrated in  FIGS. 1 to 10 , for example, and various elements of these figures are referenced in explaining example method. Each of  FIGS. 1 to 10  represents one or more processes, methods or subroutines, carried out in the example method. Furthermore, the illustrated order of  FIGS. 1 to 10  is illustrative only and the order of  FIGS. 1 to 10  can change. Additional processes can be added or fewer processes may be utilized, without departing from this disclosure. 
       FIG. 1  illustrates a substrate  11  including a base layer  110 , a first copper foil layer  111  positioned on one side of the base layer  110 , and a second copper foil layer  112  opposite to the first copper foil layer  111  and positioned on other side of the base layer  110 . 
     The base layer  110  can be a flexible resin layer, such as polyimide (PI), polyethylene terephthalate (PET), or polyethylene naphthalate (PEN). In other embodiments, the base layer  110  can be a multilayer flexible substrate, including the alternative multiple conductive resin layers and multiple wiring layers. The first copper foil layer  111  and the second copper foil layer  112  have a uniform thickness. The thickness of the first copper foil layer  111  is the same as the thickness of the second copper foil layer  112  in at least one embodiment. 
       FIG. 2  illustrates a through hole  113  formed on the substrate  11  by a mechanical drilling method or a laser ablation method. The through hole  113  penetrates through the first copper foil layer  111 , the base layer  110 , and the second foil layer  112 . 
       FIG. 3  illustrates a seed layer  120  formed on the surfaces of the first copper foil layer  111  and the second copper foil layer  112  The seed layer  120  is also formed on the wall of the through hole  113 . 
     The seed layer  120  can be formed by a black hole process, a shadow process, or an electroless plating process. In at least one embodiment, the seed layer  120  is formed by electroless copper plating. In other embodiments, the seed layer  120  can be omitted or formed only on the wall of the through hole  113 . 
       FIG. 4  and  FIG. 5  illustrate a first patterned resist layer  121  and a second patterned resist layer  122  respectively formed on the surfaces of the seed layers  120  located on the first copper foil layer  111  and the second copper foil layer  112 . A first conductive layer  131  is then formed by electroplating surface of the seed layer  120  which is exposed from the first patterned resist layer  121  and positioned on the surface of the first copper foil layer  111  A second conductive layer  132  is also formed by electroplating on surface of the seed layer  120  which is exposed from the second patterned resist layer  122  and positioned on the surface of the second copper foil layer  112 . A third conductive layer  130  is also formed by electroplating on the surface of the seed layer  120  which is positioned on the wall of the through hole  113 . After plating the third conductive layer  130 , the through hole  113  with the third conductive layer  130  becomes a conductive through layer  1131 . The conductive through hole  1131  electrically connects the first conductive layer  131  and the second conductive layer  132 . In at least one embodiment, the first patterned resist layer  121  and the second patterned resist layer  122  can be dry film. 
     Both of the first conductive layer  131  and the second conductive layer  132  have a uniform thickness. The thicknesses of the first conductive layer  131  and the second conductive layer  132  are the same and are greater than the thicknesses of the first copper foil layer  111  and the second copper foil layer  112 . In addition, the thickness of the first conductive layer  131  is greater than the sum of the thicknesses of the first copper foil layer  111  and the seed layer  120 . 
     All of the seed layer  120 , the first copper foil layer  111 , and the second copper foil layer  112  which are not covered by the first conductive layer  131 , and the second conductive layer  132 , are formed as a removable plating wire  114 , to electrically connect the first conductive layer  131  and the second conductive layer  132 . 
       FIG. 6  and  FIG. 7  illustrate a third patterned resist layer  123  formed on the surface of the first conductive layer  131  and the first patterned resist layer  121 . The third patterned resist layer  123  covers the full surface of first patterned resist layer  121  and covers part of the surface of the first conductive layer  131 . In addition, a fourth patterned resist layer  124  is formed on the surfaces of the second conductive layer  132  and the second patterned resist layer  122 . The fourth patterned resist layer  124  covers the full surface of the second patterned resist layer  122  and covers part of the surface of the second conductive layer  132 . And then, the first conductive layer  131  which is exposed from the third patterned resist layer  123  and the second conductive layer  132  which is exposed from the fourth patterned resist layer  124  receive a surface treatment process. After the surface treatment process, a first surface treatment patterned layer  133  is formed on the exposed surface of the first conductive layer  131  and a second surface treatment patterned layer  134  is formed on the exposed surface of the second conductive layer  132  for protecting respectively the first conductive layer  131  and the second conductive layer  132 . The first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  can be made of a nickel-gold (Ni—Au) layer, a nickel-platinum-gold (Ni—Pt—Au) layer, or a nickel-palladium-gold (Ni—Pd—Au) layer. As mentioned above, the removable plating wire  114  including all of the seed layer  120 , the first copper foil layer  111 , and the second copper foil layer  112  which are not covered by the first conductive layer  131  or by the second conductive layer  132  is used to electrically connect the first conductive layer  131  and the second conductive layer  132 . The removable plating wire  114  is used for respectively electroplating the first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  on the surfaces of the first conductive layer  131  and the second conductive layer  132  during the surface treatment process. In at least one embodiment, the removable plating wire  114  mentioned above is used as the plating wire for electroplating the surface treatment patterned layers. 
       FIG. 8  and  FIG. 9  illustrate that the first patterned resist layer  121 , the second patterned resist layer  122 , the third patterned resist layer  123 , and the fourth patterned resist layer  124  are removed. After removing the patterned resist layers, each of the seed layer  120 , the first copper foil layer  111 , and the second copper foil layer  112  which are exposed from the first conductive layer  131  or from the second conductive layer  132  are etched. And then, a first conductive pattern  135  and a second conductive pattern  136  are formed on the different sides of the base layer  110 . 
     In at least one embodiment, the first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  are respectively used as mask layers for etching the first conductive layer  131  and the second conductive layer  132 . The first conductive layer  131  and the second conductive layer  132  are used as mask layers for etching the seed layer  120 . The seed layer  120  which is exposed from the first conductive layer  131  or from the second conductive layer  132  is removed by etching. In addition, the first copper foil layer  111  and the second copper foil layer  112  under the exposed seed layer  120  are also removed by etching in the same process. Since all of the seed layer  120 , the first copper foil layer  111 , and the second copper foil layer  112  which are exposed from the first conductive layer  131  or from the second conductive layer  132  are etched, it means that the removable plating wire  114  can be removed by etching without any residual wire extending to the end of the substrate  11 . 
     The first conductive layer  131  and the second conductive layer  132  which are not covered with the first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  are exposed to the etching solution and are also etched to reduce the thicknesses. As mentioned above, the first conductive layer  131  and the second conductive layer  132  both have a uniform thickness. The thicknesses of each of the first conductive layer  131  and the second conductive layer  132  are the same and such thickness is greater than the thicknesses of the first copper foil layer  111  and the second copper foil layer  112 . In addition, the thickness of the first conductive layer  131  is greater than the sum of the thicknesses of the first copper foil layer  111  and the seed layer  120 . Therefore, when removing by etching the seed layer  120 , the first copper foil layer  111 , and the second copper foil layer  112  which are not covered with either the first conductive layer  131  or the second conductive layer  132 , the first conductive layer  131  and the second conductive layer  132  which are not covered with either the first surface treatment patterned layer  133  or the second surface treatment patterned layer  134  are also etched to reduce the thicknesses. After etching, the first conductive pattern  135  is formed by the first copper foil layer  111 , the seed layer  120  on the first copper foil layer  111 , and the first conductive layer  131  on the seed layer  120 . In addition, the second conductive pattern  136  is formed by the second copper foil layer  112 , the seed layer  120  on the second copper foil layer  112 , and the second conductive layer  132  on the seed layer  120 . The first conductive pattern  135  and the second conductive pattern  136  are electrically connected by the conductive through hole  1131 . 
     In the present embodiment, the thickness of the first conductive pattern  135  which is covered with the first surface treatment patterned layer  133  is greater than the thickness of the first conductive pattern  135  which is not covered with the first surface treatment patterned layer  133 . In addition, the thickness of the second conductive pattern  136  which is covered with the second surface treatment patterned layer  134  is greater than the thickness of the second conductive pattern  136  which is not covered with the second surface treatment patterned layer  134 . 
     In this disclosure, the different layers of different thicknesses and characteristics result in different etching rates. The side walls of the first conductive pattern  135  and the second conductive pattern  136  in at least one embodiment are not perpendicular to the base layer  110  and are obliquely tilted with respect to the base layer  110 . Therefore, the cross section of the first conductive pattern  135  and the second conductive pattern  136  is a trapezoidal shape. The width of the first conductive pattern  135  is decreased from the base layer  110  to the first surface treatment patterned layer  133 . In addition, the width of the second conductive pattern  136  is decreased from the base layer  110  to the second surface treatment patterned layer  134 . 
       FIG. 10  illustrates a first solder mask layer  141  and a second solder mask layer  142  formed on the surfaces of the first conductive pattern  135  and the second conductive pattern  136 . Thereby, a printed circuit board  10  is obtained. 
     In at least one embodiment, the first solder mask layer  141  covers the surface of the first conductive pattern  135  which is exposed from the first surface treatment patterned layer  133 , and covers a portion of the surfaces of the first surface treatment patterned layer  133  and the base layer  110  at the same side. The portion of the first surface treatment patterned layer  133  which is exposed from the first solder mask layer  141  is used as a first connective portion  151 . The first connective portion  151  includes a first bonding pad  1511  and a first conductive finger  1512 . In the same process, the second solder mask layer  142  covers the surface of the second conductive pattern  136  which is exposed from the second surface treatment patterned layer  134  and covers a portion of the surfaces of the second surface treatment patterned layer  134  and the base layer  110  at the same side. The portion of the second surface treatment patterned layer  134  which is exposed from the second solder mask layer  142  is used as a second connective portion  152 . The second connective portion  152  includes a second bonding pad  1521  and a second conductive finger  1522 . 
     In this disclosure, the removable plating wire  114  is removed by etching before forming the solder mask layer and without any residual wire needing to be extended to the edge of the substrate  11 . The electroplating process is used for plating the first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  by using the removable plating wire  114 . The electroplating process is simplified by using the removable plating wire  114  instead of the traditional plating wires. The electroplating process eliminates the traditional plated wires under the solder mask layer for plating the first surface treatment patterned layer  133  and the second surface treatment patterned layers  134  and effectively reduces noise in signal transmission and makes finer pitch design in the circuit. 
     It can be understood that the method of manufacturing a printed circuit board  10  further includes the steps to remove the waste parts. 
     A printed circuit board  10  is also disclosed. The printed circuit board  10  includes a substrate  11  comprising a base layer  110 , a first conductive pattern  135  formed on one side of the base layer  110 , and a second conductive pattern  136  which is opposite to the first conductive pattern  135  and formed on another side of the base layer  110 . The substrate  11  also includes a first surface treatment patterned layer  133  formed on part of the surface of the first conductive pattern  135 , and a second surface treatment patterned layer  134  formed on part of the surface of the second conductive pattern  136 . The substrate  11  further comprises a first solder mask layer  141  formed on part of the surface of the first surface treatment patterned layer  133  and the first conductive pattern  135 , and a second solder mask layer  142  formed on part of the surface of the second surface treatment patterned layer  134  and the second conductive pattern  136 . 
     In at least one embodiment, the first solder mask layer  141  covers the surface of the first conductive pattern  135  which is exposed from the first surface treatment patterned layer  133  Certain parts of the surfaces of the first surface treatment patterned layer  133  and the base layer  110  at the same side are also covered by the first solder mask layer  141 . The portion of the first surface treatment patterned layer  133  exposed from the first solder mask layer  141  is used as a first connective portion  151 . The second solder mask layer  142  covers the surface of the second conductive pattern  136  which is exposed from the second surface treatment patterned layer  134  and covers part of the surfaces of the second surface treatment patterned layer  134  and the base layer  110  at the same side. The portion of the second surface treatment patterned layer  134  which is exposed from the second solder mask layer  142  is used as a second connective portion  152 . The printed circuit board  10  further includes at least one through hole  113 . 
     The printed circuit board  10  further includes a first copper foil layer  111  positioned on a surface of the base layer  110 , and a second copper foil layer  112  opposite to the first copper foil layer  111 . 
     The printed circuit board  10  further includes a first conductive layer  131  positioned on the surface of the first copper foil layer  111 , a second conductive layer  132  positioned on the surface of the second foil layer  112 , and a third conductive layer  130  positioned on the wall of the through hole  113 . The through hole  113  thus becomes a conductive through hole  1131 . The conductive through hole  1131  electrically connects with the first conductive pattern  135  and the second conductive pattern  136 . 
     The printed circuit board  10  further includes a seed layer  120  formed on the surface of the first copper foil layer  111 , the surface of the second copper foil layer  112 , and the wall of the conductive through hole  1131 . The seed layer  120  formed on the surface of first copper foil layer  111  is positioned between the first copper foil layer  111  and the first conductive layer  131 . In addition, the seed layer  120  formed on the surface of second copper foil layer  112  is positioned between the second copper foil layer  112  and the second conductive layer  132 . In the illustrated embodiment, the seed layer  120  is positioned under the first conductive layer  131 , the second conductive layer  132 , and the third conductive layer  133 . 
     The first conductive pattern  135  of the printed circuit board  10  can be made by at least one of the first copper foil layer  111 , the second copper foil layer  112 , the seed layer  120 , the first conductive layer  131 , and the second conductive layer  132 . 
     The substrate  11  may include a plurality of units for forming a plurality of printed circuit boards  10 . After the first solder mask layer  141  and the second solder mask layer  142  are formed on the substrate  11 , the substrate  11  can be cut to form a plurality of separate printed circuits boards  10 . 
     The method of manufacturing a printed circuit board  10  in present disclosure is to form a conductive layer by electroplating on the surfaces of the first copper foil layer  111  and the second copper foil layer  112 . The conductive layer includes the first conductive layer  131 , the second conductive layer  132 , and the third conductive layer  130 . Until the first copper foil layer  111  and the second copper foil layer  112  are etched, the first copper foil layer  111  and the second copper foil layer  112  are continuous layers. After electroplating the conductive layer and forming the conductive through hole  1131 , the entire substrate  11  is electrically conductive. All of the first copper foil layer  111 , the second copper foil layer  112 , and the seed layer  120  not covered by either the first conductive layer  131  or the second conductive layer  132  can be used as a removable plating wire  114  to electroplate the first surface treatment patterned layer  133  and the second surface treatment patterned layer  134  on the conductive layer. Using the removable plating wire  114  avoids the residual plated wires having adverse effects on signal transmission and ensures the electrical quality of the printed circuit board. In this disclosure, no additional plated wires are required and the space for the wiring design is increased to allow finer pitch design. In addition, the conductive layer formed by the electroplating has better non-scratch properties. 
     The embodiments shown and described above are only examples. Many details are often found in the art such as the other features of a printed circuit board. Therefore, many such details are neither shown nor described. Even though numerous characteristics and advantages of the present technology have been set forth in the foregoing description, together with details of the structure and function of the present disclosure, the disclosure is illustrative only, and changes may be made in the detail, especially in matters of shape, size, and arrangement of the parts within the principles of the present disclosure, up to and including the full extent established by the broad general meaning of the terms used in the claims. It will therefore be appreciated that the embodiments described above may be modified within the scope of the claims.