Patent Publication Number: US-11380627-B1

Title: Radiofrequency device

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a radiofrequency device, and more particularly, to a radiofrequency device including an inductor structure. 
     2. Description of the Prior Art 
     The micro-processor system comprised of integrated circuits (IC) is a ubiquitous device, being utilized in such diverse fields as automatic control electronics, mobile communication devices and personal computers. With the development of technology and the increasingly imaginative applications of electrical products, the IC device is becoming smaller, more delicate and more diversified. 
     In the modern society, current semiconductor devices often include radiofrequency (RF) circuit structures to perform wireless communication capabilities. In the RF device, the energy efficiency of the device will be influenced by the quality factor (Q-factor) of the inductor directly. Therefore, how to improve the Q-factor of the RF device through design modifications in the structure and/or process is still a continuous issue for those in the related fields. 
     SUMMARY OF THE INVENTION 
     A radiofrequency device is provided in the present invention. A shielding structure located under an inductor structure is covered by a mask pattern for reducing energy loss and improving Q-factor of the inductor structure. 
     According to an embodiment of the present invention, a radiofrequency device is provided. The radiofrequency device includes a semiconductor substrate, an inductor structure, a shielding structure, and a mask pattern. The semiconductor substrate includes a first region and a second region. The inductor structure is disposed on the first region of the semiconductor substrate. The shielding structure is disposed on the first region of the semiconductor substrate and located between the inductor structure and the semiconductor substrate in a vertical direction. The mask pattern is disposed on the semiconductor substrate. A first portion of the mask pattern is disposed on the shielding structure and directly contacts the shielding structure, and a top surface of the shielding structure is completely covered by the first portion of the mask pattern. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic drawing illustrating a radiofrequency device according to an embodiment of the present invention. 
         FIG. 2  is a schematic drawing illustrating a top view of a shielding structure of the radiofrequency device according to an embodiment of the present invention. 
         FIG. 3  is a schematic drawing illustrating a top view of a shielding structure and an inductor structure of the radiofrequency device according to an embodiment of the present invention. 
         FIGS. 4-7  are schematic drawings illustrating a manufacturing method of a radiofrequency device according to the first embodiment of the present invention, wherein  FIG. 5  is a schematic drawing in a step subsequent to  FIG. 4 ,  FIG. 6  is a schematic drawing in a step subsequent to  FIG. 5 , and  FIG. 7  is a schematic drawing in a step subsequent to  FIG. 6 . 
     
    
    
     DETAILED DESCRIPTION 
     The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the present invention. 
     Before the further description of the preferred embodiment, the specific terms used throughout the text will be described below. 
     The terms “on,” “above,” and “over” used herein should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something). 
     The ordinal numbers, such as “first”, “second”, etc., used in the description and the claims are used to modify the elements in the claims and do not themselves imply and represent that the claim has any previous ordinal number, do not represent the sequence of some claimed element and another claimed element, and do not represent the sequence of the manufacturing methods, unless an addition description is accompanied. The use of these ordinal numbers is only used to make a claimed element with a certain name clear from another claimed element with the same name. 
     The term “forming” or the term “disposing” are used hereinafter to describe the behavior of applying a layer of material to the substrate. Such terms are intended to describe any possible layer forming techniques including, but not limited to, thermal growth, sputtering, evaporation, chemical vapor deposition, epitaxial growth, electroplating, and the like. 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic drawing illustrating a radiofrequency device  100  according to an embodiment of the present invention. As shown in  FIG. 1 , the radiofrequency device  100  includes a semiconductor substrate  10 , an inductor structure  70 , a shielding structure SS, and a mask pattern  40 . The semiconductor substrate  10  includes a first region R 1  and a second region R 2 . The inductor structure  70  is disposed on the first region R 1  of the semiconductor substrate  10 . The shielding structure SS is disposed on the first region R 1  of the semiconductor substrate  10  and located between the inductor structure  70  and the semiconductor substrate  10  in a vertical direction Z. The mask pattern  40  is disposed on the semiconductor substrate  10 . A first portion  40 A of the mask pattern  40  is disposed on the shielding structure SS and directly contacts the shielding structure SS, and a top surface TS 1  of the shielding structure SS is completely covered by the first portion  40 A of the mask pattern  40 . 
     In some embodiments, the shielding structure SS located under the inductor structure may be made of an electrically conductive material for blocking electric field lines from penetrating the semiconductor substrate  10  and reducing coupling capacitance between the inductor structure  70  and the semiconductor substrate  10 . In the present invention, the mask pattern  40  covering the shielding structure SS may be used to reduce energy loss and increasing coupling resistance between the inductor structure  70  and the structure underneath the inductor structure  70 , and the quality factor (Q-factor) of the inductor structure  70  may be enhanced accordingly. 
     In some embodiments, the vertical direction Z described above may be regarded as a thickness direction of the semiconductor substrate  10 . The semiconductor substrate  10  may have a top surface TS and a bottom surface BS opposite to the top surface TS in the vertical direction Z, and the inductor structure  70 , the shielding structure SS, and the mask pattern  40  may be disposed at a side of the top surface TS, but not limited thereto. A horizontal direction orthogonal to the vertical direction Z may be substantially parallel with the top surface TS of the semiconductor substrate  10  and/or the bottom surface BS of the semiconductor substrate  10 . 
     Additionally, in this description, a distance between the bottom surface BS of the semiconductor substrate  10  and a relatively higher location and/or a relatively higher part in the vertical direction Z is greater than a distance between the bottom surface BS of the semiconductor substrate  10  and a relatively lower location and/or a relatively lower part in the vertical direction Z. The bottom or a lower portion of each component may be closer to the bottom surface BS of the semiconductor substrate  10  in the vertical direction Z than the top or an upper portion of this component. Another component disposed above a specific component may be regarded as being relatively far from the bottom surface BS of the semiconductor substrate  10  in the vertical direction Z, and another component disposed under a specific component may be regarded as being relatively closer to the bottom surface BS of the semiconductor substrate  10  in the vertical direction Z. 
     Specifically, in some embodiments, the radiofrequency device  100  may further include an isolation structure  12 , at least one gate electrode GS, a first spacer structure (such as a spacer structure SP 2  shown in  FIG. 1 ), and a second spacer structure (such as a spacer structure SP 1  shown in  FIG. 1 ). At least a part of the isolation structure  12  may be disposed in the semiconductor substrate  10  for defining a plurality of areas separated from one another in the semiconductor substrate  10 , such as defining a plurality of active areas in the second region R 2  of the semiconductor substrate  10 , but not limited thereto. The gate structure GS may be disposed on the second region R 2  of the semiconductor substrate  10 , the spacer structure SP 1  may be disposed on a sidewall of the shielding structure SS, and the spacer structure SP 2  may be disposed on a sidewall of the gate structure GS. In some embodiments, a material composition of the spacer structure SP 1  may be identical to a material composition of the spacer structure SP 2 , but not limited thereto. For example, a first spacer  32  and a second spacer  34  may be disposed on the first region R 1  and the second region R 2  of the semiconductor substrate  10 , and the second spacer  34  may be disposed on the first spacer  32 . The spacer structure SP 1  may include a first portion  32 A of the first spacer  32  and a first portion  34 A of the second spacer  34 , and the spacer structure SP 2  may include a second portion  32 B of the first spacer  32  and a second portion  34 B of the second spacer  34 . The first spacer  32  and the second spacer  34  may respectively include a single layer or multiple layers of insulation materials, such as silicon oxide, silicon nitride, or other suitable insulation materials. 
     In some embodiments, the first portion  40 A of the mask pattern  40  may be conformally disposed on the shielding structure SS and the spacer structure SP 1 , and a second portion  40 B of the mask pattern  40  may be conformally disposed on the gate structure GS, the spacer structure SP 2 , and the second region R 2  of the semiconductor substrate  10 . It is worth noting that, in some embodiments, a plurality of the gate structures GS may be disposed on the second region R 2  of the semiconductor substrate  10 , and the two gate structures GS illustrated in  FIG. 1  may be two gate structures GS separated from each other or correspond to cross-sectional conditions of different portions in the same gate structure GS. Therefore, the gate structure GS may be partially covered by the second portion  40 B of the mask pattern  40 , and the gate structure GS is not completely covered by the second portion  40 B of the mask pattern  40 . 
     The mask pattern  40  may include a single layer or multiple layers of insulation materials, such as silicon oxide, silicon nitride, silicon oxynitride, or other suitable insulation materials. In some embodiments, the mask pattern  40  may include a first insulation layer  42  and a second insulation layer  44  conformally disposed on the first insulation layer  42 , and a material composition of the second insulation layer  44  may be different from a material composition of the first insulation layer  42 . For example, the first insulation layer  42  may be a silicon oxide layer, and the second insulation layer  44  may be a silicon nitride layer, but not limited thereto. Additionally, in some embodiments, the first insulation layer  42  may be regarded as a liner layer, and the second insulation layer  44  may be the main mask material. Therefore, the first insulation layer  42  may be thinner than the second insulation layer  44 , and a thickness of the first insulation layer  42  in the vertical direction Z may be less than a thickness of the second insulation layer  44  in the vertical direction Z, but not limited thereto. In some embodiments, the first portion  40 A of the mask pattern  40  may be composed of the first insulation layer  42  and the second insulation layer  44  disposed on the first region R 1  of the semiconductor substrate  10 , and the second portion  40 B of the mask pattern  40  may be composed of the first insulation layer  42  and the second insulation layer  44  disposed on the second region R 2  of the semiconductor substrate  10 . Therefore, a material composition of the first portion  40 A of the mask pattern  40  may be identical to a material composition of the second portion  40 B of the mask pattern  40 . 
     In some embodiments, a material composition of the gate structure GS may be identical to a material composition of the shielding structure SS. For example, a patterned conductive layer  24  may be disposed on the first region R 1  and the second region R 2  of the semiconductor substrate  10 , the shielding structure SS may include a first portion  24 A of the patterned conductive layer  24 , and the gate structure GS may include a second portion  24 B of the patterned conductive layer  24 . The patterned conductive layer  24  may include an electrically conductive material containing silicon, such as a doped polysilicon material or other suitable electrically conductive material, and the patterned conductive layer  24  may be a patterned conductive polysilicon layer accordingly, but not limited thereto. In some embodiments, the radiofrequency device  100  may further include a dielectric layer  22  disposed on the first region R 1  and the second region R 2  of the semiconductor substrate  10 , a first portion  22 A of the dielectric layer  22  may be disposed between the shielding structure SS and the semiconductor substrate  10  in the vertical direction Z, and a second portion  22 B of the dielectric layer  22  may be disposed between the gate structure GS and the semiconductor substrate  10  in the vertical direction Z. The dielectric layer  22  may include an oxide layer, such as a silicon oxide layer, or other suitable dielectric materials, and the second portion  22 B of the dielectric layer  22  may be regarded as a gate dielectric layer. 
     In some embodiments, the shielding structure SS may be an electrically floating conductive structure. For example, the shielding structure SS may be completely encompassed by insulation materials (such as the first portion  40 A of the mask pattern  40 , the spacer structure SP 1 , and the first portion  22 A of the dielectric layer  22  described above), but not limited thereto. In other words, the first portion  24 A of the patterned conductive layer  24  and the second portion  24 B of the patterned conductive layer  24  may be physically separated from each other and electrically separated from each other. Additionally, in some embodiments, the mask pattern  40  may be regarded as a blocking layer for blocking the formation of self-aligned silicide layer, and the self-aligned silicide layer may be formed on the gate structure GS without being covered by the mask pattern  40  on the second region R 2  of the semiconductor substrate  10  and formed on the semiconductor substrate  10  without being covered by the mask pattern  40 . For example, the radiofrequency device  100  may further include a silicide layer  52 A and a silicide layer  52 B. The silicide layer  52 A may be disposed on the second region R 2  of the semiconductor substrate  10  and directly contact the semiconductor substrate  10 , and the silicide layer  52 B may be disposed on the gate structure GS and directly contact the gate structure GS. The silicide layer  52 A and the silicide layer  52 B may include cobalt-silicide, nickel-silicide, or other suitable metal silicide. 
     In some embodiments, the silicide layer  52 B may include a material converted from a part of the gate structure GS, but a top surface TS 3  of the silicide layer  52 B may be still higher than a top surface TS 2  of other portions of the gate structure GS in the vertical direction Z, and a top surface TS 1  of the shielding structure SS and the top surface TS 2  of the gate structure GS may be located within the same plane orthogonal to the vertical direction Z, but not limited thereto. Therefore, compared with a condition where a silicide layer is directly formed on the shielding structure SS, the total electrical resistance of the semiconductor substrate  10  and the shielding structure may be increased by the first portion  40 A of the mask pattern  40  covering the shielding structure SS completely for keeping the silicide layer from being formed on the shielding structure SS, and the energy loss induced by the substrate may be reduced by relatively increasing the distance between the inductor structure  70  and the shielding structure (especially when the first portion  24 A of the patterned conductive layer  24  and a silicide layer formed thereon may be regarded as a shielding structure). In other words, in some embodiments, the shielding structure SS may be formed only with the polysilicon material without including the silicide described above (such as metal silicide). In addition, the Q-factor of the inductor structure  70  is proportional to the ratio of the stored energy to the energy loss in one oscillation cycle (i.e. inversely proportional to the energy loss in one oscillation cycle). The energy loss may include an energy loss induced by metal and an energy loss induced by the substrate. The energy loss induced by metal may include, for example, DC loss and loss induced by skin effect, and the energy loss induced by the substrate may include substrate potential current induced by electric field and loss induced by eddy current. Therefore, the energy loss induced by the substrate may be reduced by completely cover the shielding structure SS with the first portion  40 A of the mask pattern  40  in the vertical direction Z for keeping the silicide layer from being formed on the shielding structure SS, and the Q-factor of the inductor structure  70  and the device performance of the radiofrequency device  100  may be improved accordingly. 
     In some embodiments, the radiofrequency device  100  may further include a dielectric layer  54  disposed on the first region R 1  and the second region R 2  of the semiconductor substrate  10 . A first portion  54 A of the dielectric layer  54  may be disposed on the first region R 1  of the semiconductor substrate  10  and cover the first portion  40 A of the mask pattern  40 , and a second portion  54 B of the dielectric layer  54  may be disposed on the second region R 2  of the semiconductor substrate  10  and cover the gate structure  54 , the silicide layer  52 A, the silicide layer  52 B, the spacer structure SP 2 , and the second portion  40 B of the mask pattern  40 . The silicide layer  52 B may be disposed between the gate structure GS and the second portion  54 B of the dielectric layer  54 , and the silicide layer  52 B may directly contact the gate structure GS and the second portion  54 B of the dielectric layer  54 . Additionally, in some embodiments, the radiofrequency device  100  may further include one or more contact structures  56  penetrating through the dielectric layer  54  on the second region R 2  in the vertical direction Z for contacting the silicide layer  52 A and the silicide layer  52 B and being electrically connected with the silicide layer  52 A and the silicide layer  52 B. In some embodiments, the dielectric layer  54  may be used to provide a planarization effect and has to be relatively thicker accordingly. Therefore, the dielectric layer  54  may be thicker than the mask pattern  40 , and a thickness of the dielectric layer  54  in the vertical direction Z may be greater than a thickness of the mask pattern  40  in the vertical direction Z, but not limited thereto. 
     In some embodiments, the radiofrequency device  100  may further include a dummy metal structure  62 , an interconnection structure  64 , and an interlayer dielectric layer ILD. The interlayer dielectric layer ILD may be disposed on the dielectric layer  54  and located on the first region R 1  and the second region R 2  of the semiconductor substrate  10 . The dummy metal structure  62  may be disposed between the first portion  54 A of the dielectric layer  54  and the inductor structure  70  in the vertical direction Z, and the interconnection structure  64  may be disposed on the second portion  54 B of the dielectric layer  54 . At least a part of the dummy metal structure  62 , at least a part of the interconnection structure  64 , and at least a part of the inductor structure  70  may be disposed in the interlayer dielectric layer ILD. In some embodiments, the dummy metal structure  62  may be an electrically floating metal structure, and the interconnection structure  64  may be electrically connected with active components (such as a transistor composed of the gate structure GS) and/or passive components on the semiconductor substrate  10 . 
     For example, the radiofrequency device  100  may include metal layers (such as a patterned metal layer M 1 , a patterned metal layer M 2 , a patterned metal layer M 3 , a patterned metal layer M 4 , a patterned metal layer M 5 , and a top metal conductive layer TM shown in  FIG. 1 ) disposed on the dielectric layer  54  and stacked in the vertical direction Z. The dummy metal structure  62  may include a first portion M 11  of the patterned metal layer M 1 , a first portion M 21  of the patterned metal layer M 2 , a first portion M 31  of the patterned metal layer M 3 , a first portion M 41  of the patterned metal layer M 4 , and/or a first portion M 51  of the patterned metal layer M 5 . The interconnection structure  64  may include a second portion M 12  of the patterned metal layer M 1 , a second portion M 22  of the patterned metal layer M 2 , a second portion M 32  of the patterned metal layer M 3 , a second portion M 42  of the patterned metal layer M 4 , and a second portion M 52  of the patterned metal layer M 5 . Additionally, the inductor structure  70  may include a first portion TM 1  of the top metal conductive layer TM, and a second portion TM 2  of the top metal conductive layer TM may be disposed on and electrically connected with the interconnection structure  64 . 
     In some embodiments, the radiofrequency device  100  may include connection plugs (such as a connection plug V 1 , a connection plug V 2 , a connection plug V 3 , a connection plug V 4 , and a connection plug V 5  shown in  FIG. 1 ) and the above-mentioned metal layers (such as the second portion M 12  of the patterned metal layer M 1 , the second portion M 22  of the patterned metal layer M 2 , the second portion M 32  of the patterned metal layer M 3 , the second portion M 42  of the patterned metal layer M 4 , the second portion M 52  of the patterned metal layer M 5 , and the second portion TM 2  of the top metal conductive layer TM) alternately stacked and disposed in the vertical direction Z and electrically connected with one another. In addition, the dummy metal structure  62  may be an electrically floating metal structure and electrically separated from the interconnection structure  64 , and the first portion and the second portion of each patterned metal layer described above may be physically and electrically separated from one another. Additionally, in some embodiments, the inductor structure  70  may be electrically separated from the second portion TM 2  of the top metal conductive layer TM, and the inductor structure  70  may be electrically connected with corresponding components, such as a component formed on the second region R 2  of the semiconductor substrate  10  or a component formed on an area outside the first region R 1  and the second region R 2  of the semiconductor substrate  10 , via other portions of the patterned metal layers described above. 
     In some embodiments, the substrate  10  may include a silicon substrate, a silicon germanium semiconductor substrate, a silicon-on-insulator (SOI) substrate, or a substrate made of other suitable materials. The isolation structure  12  may include a single layer or multiple layers of insulation materials, such as silicon oxide, silicon nitride, or other suitable insulation materials. The dielectric layer  22  may include an oxide layer, such as a silicon oxide layer or other suitable dielectric materials. The dielectric layer  54  may include a single layer or multiple layers of insulation materials, such as silicon oxide, silicon nitride, or other suitable dielectric materials. The interlayer dielectric layer ILD may include a single layer or multiple layers of dielectric materials, such as silicon oxide, silicon nitride, silicon carbonitride, fluorosilicate glass (FSG), low dielectric constant (low-k) material or other suitable dielectric materials. The low-k material mentioned above may include a dielectric material with relatively lower dielectric constant (such as dielectric constant lower than 2.9, but not limited thereto), such as benzocyciclobutene (BCB), hydrogen silsesquioxane (HSQ), methyl silesquioxane (MSQ), hydrogenated silicon oxycarbide (SiOC—H), and/or porous dielectric materials. The contact structure  56 , each patterned metal layer, each connection plug, and the top metal conductive layer TM described above may respectively include a low resistance material and a barrier layer. The low resistance material described above may include materials with relatively lower resistivity, such as copper, aluminum, and tungsten, and the barrier layer described above may include titanium nitride, tantalum nitride, or other suitable barrier materials, but not limited thereto. 
     Please refer to  FIG. 2 ,  FIG. 3 , and  FIG. 1 .  FIG. 2  is a schematic drawing illustrating a top view of the shielding structure SS of the radiofrequency device according to an embodiment of the present invention, and  FIG. 3  is a schematic drawing illustrating a top view of the shielding structure SS and the inductor structure  70  of the radiofrequency device according to an embodiment of the present invention. As shown in  FIGS. 1-3 , in some embodiments, the first portion  24 A of the patterned conductive layer  24  may be a pattern with mirror symmetry for uniformly controlling the shielding effect of the shielding structure SS, but not limited thereto. In addition, the inductor structure  70  may include sections  70 S without being directly connected with one another, the sections  70 S may be electrically connected with one another via other portions of the patterned metal layers described above or the sections  70 S may be electrically connected with different components, respectively. It is worth noting that the design of the pattern of the shielding structure SS and the pattern of the inductor structure  70  in this invention is not limited to the conditions illustrated in  FIG. 2  and  FIG. 3 , and the shielding structure SS and the inductor structure  70  with other pattern features may be applied according to other design considerations. Additionally, in some embodiments, the first region R 1  may be regarded as an inductor region in the radiofrequency device  100 , the second region R 2  may be regarded as a circuit region in the radiofrequency device  100 , and there may be not any active component (such as a transistor) disposed in the first region R 1  and/or disposed above the first region R 1  for reducing negative influence on the operation of the inductor structure  70 . 
     Please refer to  FIGS. 4-7  and  FIG. 1 .  FIGS. 4-7  are schematic drawings illustrating a manufacturing method of a radiofrequency device according to the first embodiment of the present invention, wherein  FIG. 5  is a schematic drawing in a step subsequent to  FIG. 4 ,  FIG. 6  is a schematic drawing in a step subsequent to  FIG. 5 ,  FIG. 7  is a schematic drawing in a step subsequent to  FIG. 6 , and  FIG. 1  may be regarded as a schematic drawing in a step subsequent to  FIG. 7 . The manufacturing method of the radiofrequency device in this embodiment may include but is not limited to the following steps. As shown in  FIG. 4 , the isolation structure  12 , the dielectric layer  22 , the patterned conductive layer  24 , the first spacer  32 , and the second spacer  34  may be formed on the semiconductor substrate  10 . The shielding structure SS and the gate structure GS may be formed with the first portion  24 A and the second portion  24 B of the patterned conductive layer  24 , respectively. Therefore, the shielding structure SS and the gate structure GS may be formed concurrently by the same process for simplifying the related manufacturing process, and the top surface TS 1  of the shielding structure SS and the top surface TS 2  of the gate structure GS may be substantially located with the same plane orthogonal to the vertical direction Z. Subsequently, as shown in  FIG. 4  and  FIG. 5 , the mask pattern described above may be formed, and at least a part of the gate structure GS and at least a part of the second region R 2  of the semiconductor substrate  10  may not be covered by the mask pattern  40 . 
     Subsequently, as shown in  FIG. 6 , a metal layer  50  may be formed globally, and the metal layer  50  may directly contact the second region R 2  of the semiconductor substrate  10  without being covered by the mask pattern  40  and the gate structure GS without being covered by the mask pattern  40 . As shown in  FIG. 6  and  FIG. 7 , a thermal treatment may be carried out for reacting the metal layer  50  with the gate structure GS and the semiconductor substrate  10  so as to form the silicide layer  52 B and the silicide layer  52 A described above, and the metal layer  50  may be removed after the silicide layer  52 A and the silicide layer  52 B are formed. In some embodiments, the metal layer  50  may include cobalt, nickel, or other suitable metal materials, and the silicide layer  52 A and the silicide layer  52 B may include cobalt-silicide, nickel-silicide, or other silicide of the metal material of the metal layer  50 . Subsequently, as shown in  FIG. 7  and  FIG. 1 , the dielectric layer  54 , the contact structure  56 , the interlayer dielectric layer ILD, the dummy metal structure  62 , the interconnection structure  64 , the inductor structure  70  and/or other required components may be formed for forming the radiofrequency device  100  shown in  FIG. 1 . 
     To summarize the above descriptions, according to the radiofrequency device in the present invention, the mask pattern may be used to cover the shielding structure underneath the inductor structure for reducing the energy loss and improving Q-factor of the inductor structure. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.