Patent Publication Number: US-11030041-B2

Title: Decoding method, associated flash memory controller and electronic device

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation application and claims the benefit of U.S. Non-provisional application Ser. No. 16/057,839 filed on Aug. 8, 2018, which claims the benefit of U.S. provisional application No. 62/542,318 filed on Aug. 8, 2017. The contents of all of the above are all hereby incorporated by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a decoding method, and more particularly, to a decoding method applicable to a flash memory controller. 
     2. Description of the Prior Art 
     In order to further improve the capacity of storage devices, a three-dimensional (3D) NAND-type flash memory module has been proposed which can improve storage density via a multi-layer stacking process. Since bit lines in the 3D NAND-type flash memory module are vertical lines with a large width-height ratio, the etching process thereof cannot make each sector in a bit line have the same width. For example, the upper end of a bit line is generally thicker, while the upper end of a word line is thinner, raising the possibility of a short-circuit occurring between the bit lines and word lines, or other potential short-circuit/open-circuit issues. More particularly, the above-mentioned short-circuit issue could result in high reliability errors (HRE) in some specific addresses of the 3D NAND-type flash memory. When reading information of the specific addresses and soft decoding the information, some error bits might have higher reliability, which greatly affects the decoding process, even potentially causing the decoding process to fail. 
     SUMMARY OF THE INVENTION 
     Hence, an objective of the present invention is to provide a decoding method, which is capable of solving the increased decoding burdens of the flash memory module due to said high reliability errors. 
     An embodiment of the present invention discloses a decoding method applicable to a flash memory controller. The decoding method comprises: reading first data from a flash memory module; decoding the first data in order to obtain a decoding result and reliability information; comparing the decoding result with the reliability information to determine at least one specific address of the flash memory module with high reliability errors (HRE); and reading second data from the flash memory module, and decoding the second data with regard to said specific address. Data with HRE within the first data represents that the data has high reliability and an incorrect initial bit value. 
     Another embodiment of the present invention discloses a flash memory controller arranged to access a flash memory module. The flash memory controller comprises a read-only memory (ROM), a microprocessor and a decoder. The ROM is arranged to store a program code, and the microprocessor is arranged to execute the program code in order to control accessing of the flash memory module. The decoder reads and decodes the first data from the flash memory module, compares the decoding result with the reliability information to determine at least one specific address of the flash memory module with high reliability errors (HRE), and reads and decodes second data from the flash memory module with regard to said specific address; and data with HRE within the first data represents that the data has high reliability and an incorrect initial bit value. 
     Another embodiment of the present invention discloses an electronic device that comprises a flash memory module, and a flash memory controller arranged to access the flash memory module. The flash memory controller decodes and reads the first data from the flash memory module, and compares the decoding result with the reliability information to determine at least one specific address of the flash memory module with high reliability errors (HRE), and reads and decodes second data from the flash memory module with regard to said specific address; and data with HRE within the first data represents that the data has high reliability and an incorrect initial bit value. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a diagram illustrating a memory device according to an embodiment of the present invention. 
         FIG. 2  is a diagram illustrating a 3D NAND-type flash memory. 
         FIG. 3  is a diagram illustrating a decoder according to an embodiment of the present invention. 
         FIG. 4  is a diagram illustrating reading data from eight floating-gate transistors. 
         FIG. 5  is a diagram illustrating a table according to an embodiment of the present invention. 
         FIG. 6  is a flowchart illustrating a decoding method according to an embodiment of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     Refer to  FIG. 1 , which is a diagram illustrating a memory device  100  according to an embodiment of the present invention. The memory device  100  comprises a flash memory module  120  and a flash memory controller  110 , wherein the flash memory controller  110  is arranged to access the flash memory module  120 . According to this embodiment, the flash memory controller  110  comprises a microprocessor  112 , a read only memory (ROM)  112 M, a control logic  114 , a buffer memory  116 , and an interface logic  118 . The ROM  112 M is arranged to store a program code  112 C, and the microprocessor  112  is arranged to execute the program code  112 C in order to control the access of the flash memory module  120 . The control logic  114  comprises an encoder  132  and a decoder  134 . In this embodiment, the encoder  132  and the decoder  134  are arranged to perform the encoding/decoding operation of a Quasi-Cyclic Low Density Party-Check (QC-LDPC) code. 
     Typically, the flash memory module  120  comprises multiple flash memory chips, each comprising multiple blocks, and the controller (e.g. the flash memory controller  110  executing the program code  112 C via the microprocessor) takes a “block” as the unit of performing operations (e.g. erasing) on the flash memory module  120 . Further, a block may recode a specific number of pages, wherein the controller (e.g. the flash memory controller  110  executing the program code  112 C via the microprocessor) takes a “page” as the unit of writing data to the flash memory module  120 . In this embodiment, flash memory module  120  may be a 3D NAND-type flash memory. 
     In practice, the flash memory controller  110  which executes program code  112 C via the microprocessor  112  may utilize the inner elements thereof to perform various control operations, e.g. utilizing the control logic  114  to control the access operations of the flash memory module  120  (especially the access operation towards at least one block or at least one page), utilizing the buffer memory  116  to perform the required buffering process, and utilizing the interface logic  118  to communicate with a host device  130 . The buffer memory  116  may be a static random access memory (Static RAM (SRAM)), but the present invention is not limited thereto. 
     In an embodiment, the memory device  100  may be a portable memory device (e.g. a memory card conforming to the SD/MMC, CF, MS, XD specifications), and the host device  130  may be an electronic device connectable to a memory device, such as a smartphone, laptop computer, desktop computer, etc. In another embodiment, the memory device  100  may be a solid state drive (SSD) conforming to the Universal Flash Storage (UFS) or an embedded storage device conforming to the Embedded Multi Media Card (EMMC) specification, in order to be installed in an electronic device such as a smartphone, laptop computer, desktop computer, while the host device  130  may be a processor of the electronic device. 
     In this embodiment, the flash memory module  120  is a 3D NAND-type flash memory module. Refer to  FIG. 2  which illustrates an exemplary 3D NAND-type flash memory comprising multiple floating-gate transistors  202 , which construct the 3D NAND-type flash memory structure via multiple bits lines (e.g. the bit lines BL 1 -BL 3 ) and multiple word lines (e.g. the word lines WL 0 -WL 2  and WL 4 -WL 6 ). In  FIG. 2 , taking the uppermost plane as an example, all floating-gate transistors on the word line WL 0  construct at least one page, all floating-gate transistors on the word line WL 1  construct at least another page, and all floating-gate transistors on the word line WL 2  construct at least another page, and so on. In addition, with different methods of writing to flash memories, the definition between the word line WL 0  and pages (such as logic pages) will also be different. More specifically, when perform writing in the Single-Level Cell (SLC) manner, all floating-gate transistors on the word line WL 0  correspond to a single logic page only; and when performing writing in the Multi-Level Cell (MLC) manner, all floating-gate transistors on the word line WL 0  correspond to two, three or even four logic pages, wherein the situation where all floating-gate transistors on the word line WL 0  correspond to three logic pages can be called a Triple-Level Cell (TLC) structure, and the situation where all floating-gate transistors on the word line WL 0  correspond to four logic pages can be called a Quad-Level Cell (QLC) structure. Since one skilled in the art should be readily able to understand the relationship between the 3D NAND-type flash memory structure and word lines/pages, detailed illustrations are omitted here for brevity. Further, in the operations of the flash memory controller  110 , “page” is the smallest writing unit, and “block” is the smallest erasing unit. 
     In an embodiment, the gates and floating-gates of each floating-gate transistor surround the sources and drains, also known as the gate-all-around technique, in order to enhance the channel sensing ability. 
     It should be noted that the example shown in  FIG. 2  is merely for illustrating the 3D NAND-type flash memory and the floating-gate transistor  202 , and is not a limitation of the present invention. One skilled in the art should readily understand that some other types of 3D NAND-type flash memories can also be applied to the present invention, e.g. a portion of the word lines can be configured to connect to each other. 
     As mentioned in the related arts, in the 3D NAND-type flash memory module, the bit lines BL 1 -BL 3  have higher width-to-height ratio, meaning it is unlikely that each sector of the bit line will have the same width during its etching process. Hence, a short-circuit situation between the bit lines BL 1 -BL 3  and the word lines WL 0 -WL 2  and WL 4 -WL 6  may easily happen, as well as other short-circuit/open-circuit problems. The above-mentioned short-circuit issue may cause the HRE issue to occur on some bits stored in the floating-gate transistor  202 . In other words, when reading information on the floating-gate transistor  202  and soft decoding the information, some error bits with higher reliability may occur, which may severely influence the decoding operation or even make the entire decoding fail. More particularly, the above-mentioned short-circuit issue can become even worse as the program/erase (P/E) cycles increase, because with the increase in time of writing/erasing, there will be more floating-gates transistor  202  having high reliability errors, thereby increasing the difficulty of decoding. Hence, the decoder  134  in this embodiment is provided to record the physical addresses of the floating-gate transistors  202  that have high reliability errors, in order to raise the possibility of successfully decoding. 
       FIG. 3  is a diagram illustrating the decoder  134  according to an embodiment of the present invention. As shown in  FIG. 3 , the decoder  134  comprises a digital processing circuit  310 , a low-density parity-check code (LDPC) decoding circuit  320 , an HRE determining circuit  330  and a storage unit  340 , wherein the storage unit  340  comprises a Table  342 . In the beginning of the operations of the decoder  134 , the decoder  134  reads first data from the flash memory module  120 , wherein the first data may be a sector (or a chunk) of a page with a block of the flash memory module  120 . In this embodiment, the first data is obtained via using at least two different sensing voltages to access the floating-gate transistors  202  in the flash memory module  120 , wherein the first data comprises the soft information D_soft of multiple bits, and the soft information D_soft of each bit comprises an initial bit value (or sign bit) and at least two soft bits, wherein the initial bit value within the information of each bit is either “0” or “1”, and said at least two soft bits within the information of each bit are arranged to represent or calculate the reliability of the initial bit value. Some possible combinations of different bit values and their respective results are described as follows: when the initial bit value is “1” and the two soft bits are (1, 1), this shows “the initial bit value 1” has extremely high reliability (or can be considered to occur with high possibility); when the initial bit value is “1” and the two soft bits are (1, 0), this shows the “initial bit value 1” has relatively high reliability; when the initial bit value is “1” and the two soft bits are (0, 1), this shows “the initial bit value 1” has relatively low reliability; and when the initial bit value is “1” and the two soft bits are (0, 0), this shows “the initial bit value 1” has extremely low reliability. Some other possible combinations of different bit values and the respective results thereof are described as follows: when the initial bit value is “0” and the two soft bits are (1, 1), this shows “the initial bit value 1” has extremely low reliability; when the initial bit value is “0” and the two soft bits are either (1, 0) or (0, 1), this shows “the initial bit value 0” has medium reliability; and when the initial bit value is “0” and the two soft bits are (0, 0), this shows “the initial bit value 0” has the highest reliability. 
     It should be noted that the above-mentioned method which uses two soft bits to determine the reliability is only for illustrative purposes, and is not a limitation of the present invention. In some embodiments of the present invention, other than using two soft bits to represent reliability, the flash memory module  120  can adopt another method: for example, referring to a mapping table or other calculation methods. In addition, the determination of the reliability may be performed according to the bit values of both the initial bit value and the soft bits. 
     Next, the LDPC decoding circuit  320  may decode the soft information D_soft, in order to generate multiple final bit values D_hard of the first data. 
     The present invention does not particularly focus on the detailed operations regarding the soft information D_soft or the LDPC decoding circuit  320 ; related details can be known by referring to R.O.C. application No. 100102086 and other related documents. Hence, details of the digital processing circuit  310  and the LDPC decoding circuit  320  are omitted here for brevity. 
     Next, the HRE determining circuit  330  compares the soft information D_soft of the first data with the final bit value D_hard in a bit-by-bit manner, in order to determine which bits within the first data have high reliability and incorrect bit values. Then, the physical addresses corresponding to those bits are recorded into Table  342 . 
     Refer to  FIG. 4 , which is a diagram illustrating the decoder  134  sequentially processing the data read from the eight floating-gate transistors  202 _ 1 - 202 _ 8 . In  FIG. 4 , initially, the decoder  134  reads the floating-gate transistor  202 _ 1 , and it is assumed that the initial bit value of the generated soft information D_soft is “1”, the generated two soft bits are (1, 1), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “0”. Since the initial bit value is different from the final bit value (which means the initial bit value is incorrect) and the two soft bits (1, 1) represent high reliability, the floating-gate transistor  202 _ 1  will be determined as corresponding to bits with high reliability errors (i.e. after being read, the information recorded by the floating-gate transistor  202 _ 1  is determined as error bits with high reliability), and the physical address of the floating-gate transistor  202 _ 1  will be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 2 , and it is assumed that the initial bit value of the generated soft information D_soft is “1”, the two soft bits are (1, 0), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “1”. Since the initial bit value is the same as the final bit value (which means the initial bit value is correct), the floating-gate transistor  202 _ 2  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 2  will not be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 3 , and it is assumed that the initial bit value of the generated soft information D_soft is “1”, the generated two soft bits are (0, 1), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “1”. Since the initial bit value is the same as the final bit value (which means the initial bit value is correct), the floating-gate transistor  202 _ 3  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 3  will not be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 4 , and it is assumed that the initial bit value of the generated soft information D_soft is “1”, the generated two soft bits are (0, 0), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “1”. Although the initial bit value is different from the final bit value (which means the initial bit value is incorrect), the two soft bits (0, 0) still indicate low reliability. Hence, the floating-gate transistor  202 _ 4  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 4  will not be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 5 , and it is assumed that the initial bit value of the generated soft information D_soft is “0”, the two soft bits are (0, 0), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “0”. Since the initial bit value is the same as the final bit value (which means the initial bit value is correct), the floating-gate transistor  202 _ 5  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 5  will not be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 6 , and it is assumed that the initial bit value of the generated soft information D_soft is “0”, the two soft bits are (0, 1), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “0”. Since the initial bit value is the same as the final bit value (which means the initial bit value is correct), the floating-gate transistor  202 _ 6  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 6  will not be recorded in Table  342 . Next, the decoder  134  reads the floating-gate transistor  202 _ 7 , and it is assumed that, the initial bit value of the generated soft information D_soft is “0”, the two soft bits are (1, 0), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “1”. Although the initial bit value is different from the final bit value (which means the initial bit value is incorrect), the two soft bits (1, 0) still represent medium reliability rather than high reliability. Hence, the floating-gate transistor  202 _ 7  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 7  will not be recorded in Table  342 . Finally, the decoder  134  reads the floating-gate transistor  202 _ 8 , and it is assumed that the initial bit value of the generated soft information D_soft is “0”, and the two soft bits are (1, 1), and the final bit value D_hard outputted by the LDPC decoding circuit  320  is “0”. Since the initial bit value is the same as the final bit value (which means the initial bit value is correct), the floating-gate transistor  202 _ 8  will be determined as not corresponding to bits with high reliability errors, and the physical address of the floating-gate transistor  202 _ 8  will not be recorded in Table  342 . 
       FIG. 5  is a diagram illustrating Table  342  according to an embodiment of the present invention. As shown in  FIG. 5 , Table  342  records the block number, page number, block set number and address information of the floating-gate transistor  202  in which high reliability errors have ever occurred. In addition, Table  342  will also record the HRE count of the floating-gate transistor  202  during decoding. 
     In an embodiment, the decoder  134  shown in  FIG. 3  may further comprise a register arranged to temporarily store addresses of the floating-gate transistors  202  that have bits with high reliability errors generated by the HRE determining circuit  330 , and may write the addresses into Table  342  when the number of the temporarily stored addresses reach a threshold value (e.g. ten addresses). 
     Further, since the space of the storage unit  342  is limited, a Least-recently-used (LRU) algorithm can be used when data is written into Table  342 , wherein the LRU algorithm removes the addresses of the floating-gate transistors  202  that have not encountered high reliability errors. 
       FIG. 6  is a flowchart illustrating a decoding method according to an embodiment of the present invention. The detailed steps are as follows. 
     Step  600 : Start. 
     Step  602 : The flash memory controller  110  reads data from the flash memory module  120 . 
     Step  604 : The decoder  134  decodes the data, wherein when the decoding succeeds (meaning the LDPC decoding circuit  320  is able to generate a final bit value), the flow goes to Step  606 ; otherwise (the decoding fails) the flow goes to Step  608 . 
     Step  606 : The decoder  134  outputs the decoded data, and the high-reliability-error determining circuit determines which bits within the data have high reliability and an incorrect bit value, and then records those bits into Table  342 . 
     Step  608 : Determine whether a portion of the addresses in the flash memory module  120  that correspond to the data is recorded in Table  342 ; if so, the flow goes to Step  612 ; otherwise, the flow goes to Step  610 . 
     Step  610 : Use other decoding methods or disk-saving methods (e.g. an error correction method such as the Redundant Array of Independent Disks (RAID)), in order to facilitate the decoding. 
     Step  612 : Modify at least one portion of the bits within the data that correspond to high reliability errors addresses, to generate modified data. 
     Step  614 : Decode the modified data. 
     In Step  612 , the decoder  134  may modify a bit in advance, and then decode it, wherein the bit corresponds to floating-gate transistors that have most high reliability errors. Other bits can then be modified if the decoding fails later on. For example, it is assumed that the floating-gate transistors  202  corresponding to the 1 st , 5 th , 6 th  and 8 th  bits within the data are written in Table  342 , and the floating-gate transistor  202  corresponding to the 5 th  bit has most high reliability errors. In this situation, when the decoding of the data fails, the decoder  134  may flip the initial bit value of the 5 th  bit (e.g. change it from “0” to “1” or vice versa) to generate modified data for the use of decoding. If the decoding still fails, the decoder  134  further flips the respective initial bit values of the 1 st , 6 th  and 8 th  bits in order to generate modified data for the use of follow-up decoding. 
     It should be noted that the previous paragraph is mainly for illustrative purposes, and should not be considered a limitation of the present invention. In some other embodiments, the decoder  134  may flip the respective initial bit values of the 1 st , 5 th , 6 th  and 8 th  bits in the beginning to generate modified data for follow-up decoding. As long as the bit flipping action is made based on the addresses where high reliability errors occur and recorded in a table (e.g. Table  342 ), any modification to the design of the present invention should fall with the scope of the present invention. 
     In an embodiment, the information recorded in Table  342  may also be arranged to determine whether there are too many floating-gate transistors  202  in the block that constantly has high reliability errors, and accordingly determine whether the block should be erased or banned from being used. Specifically, when the content of Table  342  indicates that the number of addresses corresponding to high reliability errors within a specific block is higher than a threshold value, in order to prevent those addresses corresponding to high reliability errors from continuously increasing to the extent where the data cannot be decoded successfully, the microprocessor  112  may move valid data within the data from the specific block to other blocks (such as a garbage collection operation), then mark the specific block as invalid, and set the flash memory controller  110  to not write data into the specific block later on. 
     To summarize, the decoding method provided by the present invention continuously records physical addresses corresponding to the bits with high reliability errors into a table during the decoding process, and the content of the table may be referred to when the follow-up decoding fails. Considering the high possibility of the constant occurrence of high reliability errors on the floating-gate transistors which seriously interferes with decoding, the present invention is able to mitigate the influence of the high reliability errors occurring on floating-gate transistors, thereby increasing the possibility of successful decoding. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.