Patent Publication Number: US-6714076-B1

Title: Buffer circuit for op amp output stage

Description:
REFERENCE TO EARLIER APPLICATIONS 
     This application claims the benefit of provisional patent application Ser. No. 60/330,043 to Kalb, filed Oct. 16, 2001. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to the field of operational amplifiers (op amps), and particularly to the op amp output stages. 
     2. Description of the Related Art 
     An op amp typically includes an input stage which produces a differential current in response to the application of a differential input voltage, and an output stage which produces a single-ended or differential output which varies with the differential current. An example is shown in FIG.  1 . The input stage  10  comprises PMOS transistors MP 1  and MP 2 , and a tail current source  12 . A differential input voltage is applied across the gates of MP 1  and MP 2 , and a differential current is produced at their drain terminals in response. 
     The differential current is connected to a gain stage  14 —typically comprising a number of transistors connected in a folded-cascode configuration (biased with bias voltages V b3 , V b4 , and V b5 )—which drives an output stage  15 . The output stage in FIG. 1 is arranged in what is sometimes called a “Monticelli architecture”, described, for example, in Monticelli, “A Quad CMOS Single-Supply Op Amp with Rail-to-Rail Output Swing,” Journal of Solid-State Circuits, December 1986, pp. 1026-1034, which features a current switch  16  that drives a pair of output transistors MP 3  and MN 1  connected in a back-to-back common-source configuration. The op amp&#39;s output V o  is taken at the junction  17  of MP 3  and MN 1 . The current switch comprises an NMOS transistor MN 2  and a PMOS transistor MP 4 , which receive respective bias voltages V b1  and V b2  and are connected between a pair of nodes  18  and  20 . Nodes  18  and  20  are connected to receive the differential current from gain stage  14 . When properly biased, MN 2  and MP 4  conduct equal currents when the differential current is zero. The voltages developed at nodes  18  and  20  drive output transistors MP 3  and MN 1 , respectively. Output stage  15  typically includes a frequency compensation scheme. One of many possible schemes is shown in FIG. 1, with a first compensation capacitor Cl connected between node  18  and junction  17 , and a second compensation capacitor C 2  connected between node  20  and junction  17 . 
     This circuit arrangement suffers from a number of drawbacks, however. The gate capacitances of output transistors MP 3  and MN 1  can affect the dominant pole in the op amp&#39;s frequency response, which can make the amplifier&#39;s bandwidth dependent on the output transistors used. The gate capacitances can also lower the frequency of the op amp&#39;s secondary pole, which establishes the bandwidth&#39;s upper limit. These problems can be particularly troublesome when the output transistors are external field-effect transistors (FETs), which typically have higher gate capacitances. 
     SUMMARY OF THE INVENTION 
     An op amp output stage is presented which overcomes the problems noted above. The adverse affects of gate capacitance on the amplifier&#39;s dynamic performance are mitigated, and other benefits are realized as well. 
     The present invention includes a pair of buffer amplifiers which are interposed between the current switch and the output transistors in a Monticelli-based output stage. The buffer amps act to buffer the output transistors&#39; gate capacitance, thereby allowing the output transistors to be any desired size without adversely affecting the op amp&#39;s dynamic performance. This enables the op amp&#39;s compensation capacitors to set the amplifier&#39;s bandwidth. It also moves the secondary pole to a higher frequency. The buffer amplifiers can also provide gain, which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. 
     In addition, the buffer amplifiers can be used to provide level translation between the current switch and the output transistors, which can provide additional headroom for the amplifier&#39;s gain stage. 
    
    
     Further features and advantages of the invention will be apparent to those skilled in the art from the following detailed description, taken together with the accompanying drawings. 
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a schematic diagram of a known op amp. 
     FIG. 2 is a schematic diagram of an op amp which includes an output stage in accordance with the present invention. 
     FIG. 3 is a schematic diagram of an op amp which includes another embodiment of an output stage in accordance with the present invention. 
     FIG. 4 is a schematic diagram of a fully differential op amp which includes an output stage in accordance with the present invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An op amp which includes an exemplary embodiment of an output stage in accordance with the present invention is shown in FIG.  2 . As before, the op amp has an input stage  10  which produces a differential current in response to a differential input voltage applied to MP 1  and MP 2 , and a gain stage  14  which is preferably arranged in a folded-cascode configuration (biased with bias voltages V b8 , V b9 , and V b10 ). 
     Novel output stage  30  includes a current switch  32 . 
     The current switch comprises an NMOS transistor MN 3  and a PMOS transistor MP 5 , which receive respective bias voltages V b6  and V b7  and are connected between a pair of nodes  34  and  36 . Nodes  34  and  36  are connected to receive the differential current from gain stage  14 . When properly biased, MN 3  and MP 5  conduct equal currents when the differential current is zero. When the input stage drives the output stage in one direction, current is sourced into nodes  34  and  36 , which causes the voltages at MP 5 &#39;s source and MN 3 &#39;s source to increase, the current in MP 5  to increase, and the current in MN 3  to decrease. When the input stage drives in the other direction, the voltage at MP 5 &#39;s source and MN 3 &#39;s source decreases, so that MP 5 &#39;s current falls and MN 3 &#39;s current increases. In this way, current switch  32  steers current from the MP 5  leg to the MN 3  leg, and vice-versa, such that the voltages developed at nodes  34  and  36  vary with the differential current received from input stage  10 . 
     The output stage also includes a pair of buffer amplifiers A 1  and A 2 . Buffer amplifiers A 1  and A 2  receive the voltages at nodes  34  and  36  at respective inputs, and drive output transistors MP 6  and MN 4  with respective outputs. A pair of resistors R 1  and R 2  might optionally be inserted between A 1 /A 2  and MP 6 /MN 4 , respectively, which can add stability and/or design flexibility under some circumstances. MP 6  and MN 4  are connected in a back-to-back common-source configuration, with their drains connected together at a junction  38 ; junction  38  provides the op amp&#39;s output V o . Output stage  30  preferably includes a frequency compensation scheme; one exemplary scheme is shown in FIG. 2, which has a first compensation capacitor C 3  connected between node  34  and junction  38 , and a second compensation capacitor C 4  connected between node  36  and junction  38 . Note that many other frequency compensation schemes are possible; most notably, the scheme shown in FIG. 2 with resistors connected in series with the capacitors. 
     Buffer amplifiers A 1  and A 2  provide a number of advantages over the prior art. A primary benefit provided by A 1  and A 2  is the buffering of the gate capacitances of output transistors MP 6  and MN 4 . This mitigates the effect of the gate capacitances on the dynamic performance of the op amp. As such, larger output transistors having larger gate capacitances can be used without adverse impact. This is especially helpful if the output stage is used to drive large external FETs, which tend to have larger gate capacitances than do integrated FETs (on the order of nanofarads, as opposed to the picofarads). In the absence of buffer amplifiers A 1  and A 2 , the gate capacitances can have a greater impact on the location of the dominant pole in the op amp&#39;s frequency response that do compensation capacitors C 3  and C 4  (if present). This makes the bandwidth of the op amp dependent on the particular output transistors used. The invention allows the compensation capacitors to be used to set the bandwidth—independently of the choice of output transistor. 
     The use of buffer amplifiers A 1  and A 2  also mitigates the effect of the output transistors&#39; gate capacitances on the location of the secondary pole in the op amp&#39;s frequency response. With the conventional Monticelli architecture shown in FIG. 1, the frequency of the secondary pole location is roughly given by:            2        g   m         C   L       *     1     1   +       C   gs       C   c                           
     where g m  is the transconductance of the output transistors, C L  is the capacitance of a load driven by the op amp, C gs  is the gate-source capacitance of the output transistors, and C c  is the capacitance of the compensation capacitors. (This presumes that the g m &#39;s and the C gs &#39;s are approximately the same for both output transistors, and that the C c &#39;s are approximately the same for both compensation capacitors. The frequency can be precisely calculated by those skilled in the art.) Buffer amplifier&#39;s A 1  and A 2  greatly reduce or eliminate the effect of C gs , such that—with the invention in place—the expression for the secondary pole location reduces to            2        g   m         C   L       .                   
     This effectively moves the secondary pole—and thus the bandwidth&#39;s upper limit—to a higher frequency. One reason that this is useful is that, based on stability considerations, it is generally desired that the secondary pole be at a frequency two or three time higher than the frequency at which the op amp gain has a magnitude of one. 
     One prior art approach to moving the secondary pole to a higher frequency is to increase the size—and thus the transconductance g m —of the output transistors. However, g m  increases with roughly the square root of transistor size, while gate capacitance goes up proportionally to size. This can result in a C gs  which is larger than C c , which has the net effect of lowering the secondary pole location instead of increasing it as desired. With the invention in place, C gs  is no longer a consideration, and the larger g m  of a large output transistor has the desired effect of increasing the secondary pole location. 
     To further improve the secondary pole location, the buffer amplifiers are preferably arranged to provide a gain greater than one. For example, if the buffer amplifiers each have a gain of 2, the secondary pole location is given by        4   *         g   m       C   L       .                     
     This doubles the frequency of the secondary pole location, and thus allows for twice the bandwidth. 
     The buffer amplifiers can also be arranged to provide voltage level translation, which can prevent the output transistors from limiting the headroom of the gain stage of the amplifier. For example, assume the output transistors need to be biased with control voltages which are 0.7 volts from the supply voltages. At the same time, the gain stage of the amplifier must be biased so that its transistors remain in their forward active region. If the control voltages are 0.7 volts from the supply voltages, then the drop across the gain stage is constrained by the same amount (0.7 volts). This is known as the headroom. In general, the more headroom available to the gain stage, the better it performs. To overcome this&#39; constraint, buffer amplifiers A 1  and A 2  can translate the voltage levels applied to the output transistors such that more headroom is provided to the gain stage. Translating the voltage levels with A 1  and A 2  reduces the significance of the output transistors&#39; threshold voltages. If the threshold voltages are lower than desired, the buffer amplifiers can be arranged to add voltage drop in the level translation. Similarly, if the threshold voltages are higher than desired, the buffer amplifiers can be arranged to add a voltage step in the level translation. 
     Note that, though the op amp shown in FIG. 2 is implemented with FETs, the invention is applicable to use with a partial or all-bipolar implementation, or with a partial or all-BiCMOS implementation as well. Also note that, though the amplifier is usually biased to be used as a class A/B amplifier, the invention is equally applicable to situations where the amplifier is biased as a class A or class B amplifier. 
     Buffer amplifiers A 1  and A 2  have no special requirements, other than the need to be able to drive the capacitive load of the output transistors&#39; gates out to a bandwidth necessitated by the design while maintaining sufficient stability margins. The buffer amplifiers preferably provide settable gain to obtain additional improvement in secondary pole location, and voltage translation to provide the previously discussed additional headroom. 
     Another embodiment of an op amp per the present invention is shown in FIG.  3 . Here, an input stage  50  comprises NMOS transistors MN 5  and MN 6 , which receive tail current from an NMOS transistor MN 7  biased with a voltage V tail . The differential current produced by input stage  50  is connected to a folded-cascode gain stage  51 , which drives an output stage  52 . Output stage  52  includes a current switch  54  made from cascoded PMOS transistors MP 7  and MP 8  and cascoded NMOS transistors MN 8  and MN 9  (biased with bias voltages V b11 , V b12 , V b13  and V b14 , respectively), connected between a pair of nodes  56  and  58 . Nodes  56  and  58  are connected to the inputs of buffer amplifiers A 3  and A 4 , respectively. A pair of output FETs MP 9  and MN 10  are connected in a back-to-back common-source configuration, with their drains connected together at a junction  60 . MP 9  and MN 10  are driven by the outputs of A 3  and A 4 , respectively; junction  60  provides the op amp&#39;s output V o . A pair of compensation capacitors C 5  and C 6  are connected between junction  60  and nodes  56  and  58 , respectively. 
     The op amp shown in FIG. 3 operates in the same fashion as that shown in FIG.  2 . Input stage  50  converts a differential input voltage to a differential current which is delivered to gain stage  51 . Current switch  54  receives the differential current and produces first and second voltages which vary with the differential current at nodes  56  and  58 , respectively. The outputs of buffer amplifiers A 3  and A 4  vary with the first and second voltages, and output transistors MP 9  and MN 10  conduct respective currents to junction  60  in response to the outputs of A 3  and A 4 . Buffer amplifiers A 3  and A 4  serve to buffer the gate capacitances of output transistors MP 9  and MN 10 , thereby allowing the output FETs to be nearly any desired size without adversely affecting the op amp&#39;s dynamic performance. Buffer amplifiers A 3  and A 4  can also provide gain which effectively multiplies the transconductance of the output transistors and further extends out the secondary pole location. In addition, the buffer amplifiers can be used to provide level translation between the current switch and the output transistors, which can provide additional headroom for the gain stage. 
     An exemplary embodiment of a fully differential op amp which includes output stages in accordance with the present invention is shown in FIG.  4 . An input stage  100  delivers its differential current to first and second gain stages ( 102 ,  104 ), which in turn drive first and second output stages ( 105 ,  106 ) which include respective current switches ( 107 ,  108 ). The voltages developed across the current switches are delivered to the inputs of respective buffer amplifiers (A 5 -A 8 ), the outputs of which drive respective output transistors (MP 10 /MN 11 ; MP 11 /MN 12 ) to produce a differential output voltage (V o +/V o −). The folded-cascode and current-switch transistors are biased with respective bias voltages (not shown), and the amplifier preferably includes a common-mode control circuit  110 , which is connected to differential outputs V o + and V o − and provides common-mode feedback to the gain stages (typically connected to either the upper PMOS FETs or the lower NMOS FETs). Buffer amplifiers A 5 -A 8  provide this op amp with the same benefits as were described above for the single-ended implementations. The advantages afforded by the present invention could also be realized with an op amp configured like that shown in FIG. 4, but which is implemented with bipolar or BiCMOS transistors. 
     The op amp implementations shown in FIGS. 2-4 are merely exemplary; the invention is useful with op amps which differ from those shown in numerous ways. It is only essential that the op amp configuration be based on the Monticelli architecture, with buffer amplifiers imposed between the output stage&#39;s current-switch and output transistors. 
     While particular embodiments of the invention have been shown and described, numerous variations and alternate embodiments will occur to those skilled in the art. Accordingly, it is intended that the invention be limited only in terms of the appended claims.