Patent Publication Number: US-11652035-B2

Title: Multi-pitch ball grid array

Description:
The present application is a divisional of U.S. patent application Ser. No. 16/146,993, filed on Sep. 28, 2018, the entirety of which is hereby incorporated by reference. 
    
    
     TECHNICAL FIELD 
     This disclosure relates to semiconductor packaging design and fabrication. 
     BACKGROUND 
     A ball grid array (BGA) package is a package having a set of conducting bumps on an insulating substrate. Each ball in the BGA may be an isolated electrical connection through a board via to a circuit node in an integrated circuit (IC) that is attached to the insulating substrate. The IC may rest on an opposite side of the insulating substrate from the BGA, with one or more balls of the BGA connecting to various nodes on the IC. The balls in the BGA may be spaced in a grid array, with each row and column separated by a distance known as a pitch. 
     SUMMARY 
     This disclosure describes a structure for a chip package and a printed circuit board (PCB), where the chip package interconnects to the printed circuit board using a ball grid array (BGA). The package includes a substrate configured to receive an integrated circuit and to connect the integrated circuit through the substrate to a ball grid array of connectors, and through the ball grid array of connectors to a printed circuit board (PCB). The BGA of connectors are arranged as a function of a first and second pitch, with selected pairs of connectors separated by the first pitch and other connectors separated by a second, larger, pitch. If some examples, additional grounds are added in the space cleared through the use of the second pitch. 
     In one example, in a ball grid array (BGA) package having a BGA substrate and a plurality of connectors arranged in an array and connected via signal pads and ground pads to the BGA substrate, a method including placing selected pairs of the signal pads on the BGA substrate at a distance defined by a first pitch P 1 ; placing selected ground pads on the BGA substrate at a distance from adjacent selected pairs of signal pads defined by a second pitch P 2 , wherein P 2 =M*P 1  and M is greater than one; and placing the selected pairs of the signal pads on the BGA substrate at a distance from adjacent selected pairs of the signal pads defined by the second pitch P 2 . 
     In another example, a component comprises a ball grid array package (BGA); and an integrated circuit, wherein the BGA package includes a BGA substrate and an array of BGA connectors, a plurality of pads on the BGA substrate attached to the integrated circuit and a plurality of BGA pads deposited as an array on a side the BGA substrate opposite the pads attached to the integrated circuit and connected to the BGA connectors, wherein the BGA connectors include BGA signal connectors and BGA ground connectors, wherein selected pairs of the BGA signal connectors are placed on the BGA package at a distance defined by a first pitch P 1 , wherein selected BGA ground connectors are placed on the BGA package at a distance from adjacent selected pairs of BGA connectors defined by a second pitch P 2 , wherein P 2 =M*P 1  and M is greater than one, and wherein the selected pairs of BGA signal connectors on the BGA package are separated from adjacent selected pairs of BGA signal connectors on the BGA package by a distance defined by the second pitch. 
     In yet another example, a printed circuit board (PCB) comprises a plurality of layers, including a top layer; and a plurality of pads disposed on the top layer, wherein the plurality of pads are distributed on the top layer in a pattern matching a mixed pitch ball grid array of connectors on a corresponding ball grid array (BGA) package, wherein the plurality of pads includes signal pads and ground pads, wherein selected pairs of signal pads on the top layer are separated by a distance defined by a first pitch, wherein selected ground pads are separated by a distance defined by a second pitch from adjacent selected pairs of signal pads, wherein P 2 =M*P 1  and M is greater than one, and wherein the selected pairs of signal pads are separated from adjacent selected pairs of signal pads by a distance defined by the second pitch. 
     The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. 
    
    
     
       BRIEF DESCRIPTION OF DRAWINGS 
         FIG.  1    is a block diagram illustrating an example mixed pitch BGA package, in accordance with techniques of this disclosure. 
         FIG.  2 A  is a block diagram illustrating example pad placement on a section of a bottom surface of the mixed pitch BGA package of  FIG.  1   , in accordance with techniques of this disclosure. 
         FIG.  2 B  is a block diagram illustrating a printed circuit board configured to receive a BGA package having the mixed pitch BGA substrate of  FIG.  2 A , in accordance with techniques of this disclosure. 
         FIG.  3    is a block diagram illustrating an example top surface of the mixed pitch BGA substrate of  FIG.  1   , in accordance with techniques of this disclosure. 
         FIG.  4 A  is a flowchart illustrating an example technique for distributing connector pads on the BGA substrate  36  of  FIG.  2 A , in accordance with techniques of this disclosure. 
         FIG.  4 B  is a flowchart illustrating an example technique for configuring a printed circuit board to receive the mixed pitch BGA package of  FIG.  2 A , in accordance with techniques of this disclosure. 
         FIG.  5    is a block diagram illustrating example pad placement on a section of a bottom surface of the mixed pitch BGA substrate of  FIG.  1   , in accordance with techniques of this disclosure. 
         FIG.  6 A  is a flowchart illustrating an example technique for distributing connector pads on the BGA substrate of  FIG.  5   , in accordance with techniques of this disclosure. 
         FIG.  6 B  is a flowchart illustrating an example technique for configuring a printed circuit board to receive a BGA package having the mixed pitch BGA substrate of  FIG.  5   , in accordance with techniques of this disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     As communication speeds continue to increase, it becomes increasingly difficult to limit signal-to-signal crosstalk at the BGA. The problem is exacerbated as BGA pin density increases. One approach to limit such crosstalk is to provide one row isolation between adjacent transmit (TX) channels and between adjacent receive (RX) channels in order to limit far end crosstalk. In one example approach, one can add a row of isolation by adding a row of ground pads to the BGA package between the TX to TX channels or between the RX to RX channels. If lower levels of crosstalk are needed, one typically adds additional rows of isolation. The problem is that multiple rows of isolation are not a practical way of limiting crosstalk. One reason is that such an approach increases the size of the BGA package, drastically driving up cost. 
     Instead, one frequently is left with standard isolation techniques which, with a regular 1 mm pitch BGA, result in measures of approximately 20 dB of crosstalk noise at 28 GHz Nyquist. This level of crosstalk noise negatively impacts high speed communications such as 112 Gbps signaling. Traditional methods of increasing crosstalk isolation between serial channels and of increasing signal quality by manipulating TX launch (i.e., by increasing TX signal levels via launch voltage settings in the TX channel) at the package BGA may not, therefore, be sufficient to enable higher speed communications. What is described below is a technique that reduces crosstalk and reduces insertion loss deviation by distributing connectors in a ball grid array in a nonuniform fashion. In some example approaches, the technique pushes channel resonances out beyond 30 GHz to achieve 112 G operation with PAM4 signaling at 28 GHz Nyquist. 
       FIG.  1    is a block diagram illustrating an example mixed pitch BGA package, in accordance with techniques of this disclosure. In the example approach of  FIG.  1   , package  30  couples an IC  32  through a BGA substrate  36  to a printed circuit board (PCB)  44 . In the example approach of  FIG.  1   , package  30  includes an IC  32 , a BGA substrate  36 , and a set of connectors arranged as BGA  38 . BGA packaging material (not shown) may surround and protect some or all of BGA substrate  36 . 
     In one example approach, the connectors of BGA  38  have a first and a second pitch. Each pitch may be indicative of the distance between connectors (e.g., solder balls) in BGA  38 . In the example shown in  FIG.  1   , package  30  is attached to printed circuit board (PCB)  44  and may conduct electricity from BGA  38  connectors attached to the bottom surface  42  of BGA substrate  36  using pads  46  of PCB  44 . In some example approaches, pads  46  are arranged in a BGA package footprint  45  and have a pad size approximately equal to the size of the solder balls used for BGA package  30 . In some such example approaches, pads  46  are formed from a conductive metal such as copper. 
     IC  32  may be coupled to BGA substrate  36  via chip bumps  34 , which in  FIG.  1    are shown as connecting the bottom surface of IC  32  to the top surface  40  of BGA substrate  36 . IC  32  may employ flip-chip technology, also known as controlled collapse chip connection (C4), which may use solder bumps or copper pillars to conduct electricity between IC  32  and BGA substrate  36 . Chip bumps  34  may have a pitch that is smaller than the pitch of BGA  38 . In some examples, the diameter of chip bumps  34  may be on the order of one hundred micrometers. The pitch of chip bumps  34  may also be on the order of one hundred to two hundred micrometers. In some examples, wire bonds (not shown) are used instead of chip bumps  34  to connect IC  32  to BGA substrate  36 . 
     BGA substrate  36  may facilitate electrical connections between chip bumps  34  and the connectors of BGA  38 . BGA substrate  36  may include conductive paths inside of or on either side of BGA substrate  36 . Conductive paths inside BGA substrate  36  may include vertical paths, such as vias, or horizontal paths across BGA substrate  36 . BGA substrate  36  may include through-organic substrate vias (TOSVs) that are formed by laser drilling or preforming processes. 
     In some examples, IC  32  may be in die form and may be separate or combined electrical circuits formed on a single piece of semiconductor such as silicon, germanium, or gallium arsenide. Examples of ICs  32  include, but are not limited to, a digital signal processor (DSP), a general purpose microprocessor, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a combination thereof, or other equivalent integrated or discrete logic circuitry. 
     For purposes of illustration, IC  32  may be a serializer/deserializer (serdes) IC. A serdes IC may translate parallel data streams to serial data streams and may translate serial data streams to parallel data streams. As an example, IC  32  may include four ASIC designs, each ASIC design forming one serdes circuit. For instance, one ASIC design may serialize one hundred and twenty-eight inputs data lines into a single data output and/or deserialize one input data line into one hundred and twenty-eight output data lines. Such a design may be used in switches and routers to serialize data to be transmitted in serial data streams and to deserialize received serial data streams. 
     BGA substrate  36  may be a BGA substrate that includes organic, non-silicon insulating material. BGA substrate  36  may also include conducting material formed as pads on the top and bottom surfaces of BGA substrate  36 . IC  32  may attach to BGA substrate  36  such that the pads on top surface  40  of BGA substrate  36  are electrically connected to the input/output (I/O) points of IC  32 . The pads on top surface  40  of BGA substrate  36  may be coupled to ball-grid array (BGA)  38  on bottom surface  42  of BGA substrate  36  through vias or other electrical connections. In this way, the I/O points of IC  32  may be electrically coupled through BGA substrate  36  to PCB  44 . Examples of the vias through which the I/O pads of IC  32  may connect to the first BGA through BGA substrate  36  include through-organic substrate vias (TOSVs), such as laser-drilled vias, that extend through BGA substrate  36 . Alternatively, or additionally, the electrical connections between the I/O points of IC  32  and PCB  44  may be any other suitable connection. The electrical connections between the I/O points of IC  32  may include conductive paths through the insulating material in BGA substrate  36  or across one or both sides of BGA substrate  36 , or a combination of interior and exterior conductive paths. In some example approaches, BGA substrate  36  includes vias that couple pads on top surface  40  of BGA substrate  36  to BGA  38  connectors on the bottom surface  42  of BGA substrate  36 . 
     In some example approaches, the connectors in a BGA  38  of this disclosure may be selected from connectors such as solder balls, copper bumps, or any other suitable conductive material. In some examples, BGA substrate  36  may include a land-grid array, pads, or any suitable connector instead of or in combination with BGA  38 . A smaller pitch in BGA  38  may mean a higher density of connections, thereby allowing greater fan-out for IC  32 . 
     As noted above, traditional methods of crosstalk isolation and TX launch manipulation at the package BGA may not be sufficient to enable higher speed communications such as 112 G signaling. Instead, by distributing connectors of the BGA  38  in a combination of pitches, one can increase crosstalk isolation without tweaking TX launch voltage settings. In one example approach, connectors of BGA  38  are placed at different pitches across BGA  38 . For instance, as noted above, traditional 1 mm BGA pitch has higher than desired crosstalk noise for applications approaching 100 G communication. Mixed pitch BGA pinouts improve BGA crosstalk performance significantly without negatively impacting BGA package size. In one 1 mm example approach, the BGA pitch between differential signal pairs (such as used for serdes) is increased while the pitch between the P and N pins of the differential pairs is kept at 1 mm. For instance, the pitch between pairs of serdes I/O and adjacent GND pins of IC  32  may be increased by 25% (to 1.25 mm) while the pitch between the differential pair pins is kept at 1 mm. The result is, as described in further detail below, that connectors of BGA  38  may be arranged such that the connectors are not evenly spaced. This selective increase in connector spacing significantly reduces TX-TX and RX-RX crosstalk noise. 
     One may further increase crosstalk noise reduction by adding additional grounds in the space created by the increased pitch. This combined approach has been shown to significantly reduce crosstalk. In simulation TX-TX and RX-RX crosstalk isolation increased from 34 dB to 43 dB by both using mixed pitch BGA pinouts and by inserting grounds in the space created by the increased pitch. Furthermore, the mixed pitch BGA approach may reduce the size of BGA package  30 . One package sizing effort showed approximately 10% improvement in package size by using the mixed pitch BGA approach described above. In addition, by using the mixed pitch BGA techniques described herein, the package for a 112 G serdes circuit is less than 10% larger than package sizes currently being used for 56 G signaling. 
     In one example approach, P and N for each differential pair may be kept on a 1 mm pitch while distance between a Serdes differential pair pin and an adjacent ground pin is 1.25 mm. In some example approaches, this additional distance of 0.25 mm may be used to add ground vias around the serdes pins, which reduces crosstalk significantly. In fact, the additional ground vias mimic the effect of having two ground row isolation without actually increasing the package size drastically. Preliminary simulations show an improvement in crosstalk over the regular BGA arrangement as noted above. In addition, sizing projections indicate that, by using this approach, one may fit a mixed pitch BGA substrate  36  handling 112 gigabit-per-second (112 G) serdes signals within a BGA package  30  that is approximately 10% smaller than an equivalent design that relies on two ground row isolation. 
       FIG.  2 A  is a block diagram illustrating example pad placement on a section of a bottom surface of the mixed pitch BGA package of  FIG.  1   , in accordance with techniques of this disclosure. BGA substrate  36  may be composed of organic, non-silicon insulating material and, in this example approach, includes pads  50  that come in contact with individual connectors of BGA  38 . Each connector may be a solder ball, a copper bump, a solder bump, a copper pillar, or another suitable material for conducting electricity. Each pad  50  is separated from adjacent pads by one or more of the pitches of the BGA  38 . 
     In the example shown in  FIG.  2 A , pads  50  corresponding to the mixed pitch BGA  38  are arranged with columns  52  separated by the same pitch  56  and rows  54  separated by either pitch  56  or pitch  58 . Rows  54  containing one of a differential signal pair  60  are separated from the row  54  containing the other of the pair of differential signals by a pitch  58  while other rows are separated by pitch  56 . Ground pads  62  surround each differential signal pair  60 , with rows and columns of grounds  62  separating each differential signal pair  60 . BGA package footprint  45  of PCB  44  mirrors the configuration of BGA  38 , with pads  46  distributed in a similar multi-pitch manner as discussed for multi-pitch BGA substrate  36  in  FIG.  2 A . As noted above, such an approach significantly reduces TX-TX and RX-RX crosstalk noise over a traditional 1 mm BGA pitch approach. 
     One can further increase crosstalk isolation by inserting ground vias in PCB  44  in the space created by the increased pitch of multi-pitch BGA  38 .  FIG.  2 B  is a block diagram illustrating a printed circuit board configured to receive a BGA package having the mixed pitch BGA substrate of  FIG.  2 A , in accordance with techniques of this disclosure. 
     As shown in  FIG.  2 B , and as reflected in  FIG.  2 A , pads  46  include signal pads  70  and ground pads  72 . In the example approach of  FIG.  2 B , signal pads  70  are arranged in differential pairs, with pairs of signal pads  70  separated by pitch  58 , all columns of pads  46  are separated by pitch  56  while rows without signal pads  70  are also separated by pitch  56 . In the example approach of  FIG.  2 B , as in  FIG.  2 A , ground pads  62  surround pairs of signal pads  60 . 
     In the example approach shown in  FIG.  2 B , ground vias  76  have been added to PCB  44  in the space created by the increase in pitch from pitch  58  to pitch  56 . Ground vias  76  are connected to existing ground pads  72  and, therefore, do not require the addition of extra connectors to BGA  38 , or to BGA package footprint  45 . The combination of increased pitch and additional ground vias has characteristics that approach double row isolation, but without the packaging space penalty of double row isolation. As noted above, when pitch  58  is 1 mm and pitch  56  is 1.25 mm, a simulation of the combination of mixed pitch and additional ground vias  76  increased TX-TX and RX-RX crosstalk isolation from 34 dB to 43 dB. 
     In some example approaches, increased pitch on the outer rows may also be used to increase the antipad size as shown in  FIG.  2 B , which reduces the capacitance and improves launch. VDD and GND pins in the core of package  30  may also be oriented in a way that allows de-coupling caps to be mounted directly without any additional lead inductance. 
       FIG.  3    is a block diagram illustrating an example top surface of the mixed pitch BGA substrate of  FIG.  1   , in accordance with techniques of this disclosure. Top surface  40  may include an array of pads  92 . Each pad  92  is adapted to receive an electrical connector such as a solder bump, a copper pillar, or another suitable material for conducting electricity. Each pad  92  is separated from an adjacent pad in the array of pads  92  by a pitch  94 . 
     Pitch  94  may be smaller than pitch  56  to allow for fan-out of the connections on the top surface of BGA substrate  36 . Fan-out from top surface  40  to bottom surface  42  may connect signals received at pads  92  to traces of PCB  44  through pads  46 . 
       FIG.  4 A  is a flowchart illustrating an example technique for distributing connector pads on the BGA substrate  36  of  FIG.  2 A , in accordance with techniques of this disclosure. The technique is described with reference to the substrate  36  of  FIGS.  1  and  2 A . Define a first pitch P 1  and a second pitch P 2  ( 80 ), where P 2 =M*P 1  and M is greater than one. Place selected pairs of pads  50  on the BGA substrate separated by a distance defined by the first pitch ( 82 ). Place ground pads  62  on the BGA substrate separated from the selected pairs of pads  50  by a distance defined by the second pitch ( 84 ). Place the selected pairs of pads  50  on the BGA substrate such that the selected pairs of pads  50  are separated from other selected pairs of pads  50  by a distance defined by the second pitch ( 86 ). In some example approaches, the selected pairs of pads  50  include differential signal pairs  60 . 
       FIG.  4 B  is a flowchart illustrating an example technique for configuring a printed circuit board to receive the mixed pitch BGA package of  FIG.  2 A , in accordance with techniques of this disclosure. The technique is described with reference to PCB  44  of  FIGS.  1  and  2 B , based on the pitches described with reference to  FIG.  4 A  and shown in  FIG.  2 B . Place pads  46  on the package footprint  45  of PCB  44  to mirror the layout of the mixed pitch BGA package  30  being used ( 100 ). In one example approach, the layout may mirror the pad layout of BGA substrate  36  of  FIG.  2 A . In some example approaches, the layout may be similar to PCB  44  of  FIG.  2 B . Place ground vias  76  in the space created by increasing the separation between ground pads  72  and the selected pairs  70  to a distance defined by the second pitch, as illustrated for example in  FIG.  2 B  ( 102 ). In some example approaches, the selected pairs of pads  46  include signal pads  70 . In some such example approaches, the pairs of signal pads  70  may be used to transmit or receive differential signals. 
     In one example approach, a BGA component  30  includes a BGA package (such as shown in  FIG.  1   ) and an integrated circuit  32 . The BGA package includes a BGA substrate  36  and an array  38  of BGA connectors  48 . A plurality of pads  92  on the BGA substrate  36  are attached to the integrated circuit  32  and a plurality of BGA pads  50  are arranged as an array on a side the BGA substrate  36  opposite the pads  92  and are connected to the BGA connectors  48 . The BGA connectors  48  include BGA signal connectors and BGA ground connectors. Selected pairs of the BGA signal connectors are placed on the BGA package at a distance defined by a first pitch P 1 . Selected BGA ground connectors are placed on the BGA package at a distance from adjacent selected pairs of BGA connectors defined by a second pitch P 2 , wherein P 2 =M*P 1  and M is greater than one. And, the selected pairs of BGA signal connectors on the BGA package are separated from adjacent selected pairs of BGA signal connectors on the BGA package by a distance defined by the second pitch. 
     In one example approach, a corresponding printed circuit board (PCB) includes a plurality of layers, including a top layer and a plurality of pads  46  disposed on the top layer, wherein the plurality of pads  46  are distributed on the top layer in a pattern matching a mixed pitch ball grid array of connectors on a corresponding ball grid array (BGA) package as described above. In one such example approach, the plurality of pads  46  includes signal pads and ground pads, wherein selected pairs of signal pads on the top layer are separated by a distance defined by a first pitch, wherein selected ground pads are separated by a distance defined by a second pitch from adjacent selected pairs of signal pads, wherein P 2 =M*P 1  and M is greater than one, and wherein the selected pairs of signal pads are separated from adjacent selected pairs of signal pads by a distance defined by the second pitch. 
     In one example approach, VDD and GND pads are grouped together in an array of pads  50  separated from adjacent pads by a distance defined by a third pitch. For instance, the VDD and GND pads may be placed in the center of BGA substrate  36 , with differential signal pairs  60  (e.g., serdes I/O pads) and additional GND pads  62  distributed at the periphery of BGA substrate  36 . In one such example approach, substrate  36  may include spacing of 0.8 mm near the VDD and GND pins at the center and spacing of 1.25 mm near the differential signal pairs  60 . Based on this, the pitch between two sets of differential signal pairs would be 2.5 mm instead of the traditional 2 mm. 
       FIG.  5    is a block diagram illustrating example pad placement on a section of a bottom surface of the mixed pitch BGA substrate  36  of  FIG.  1   , in accordance with techniques of this disclosure. BGA substrate  36  may be composed of organic, non-silicon insulating material and, in this example approach, includes pads  50  that come in contact with individual balls of BGA  38 . Each ball may be a solder ball, a copper bump, a solder bump, a copper pillar, or another suitable material for conducting electricity. Each pad  50  is separated from adjacent pads by one or more of the pitches of the BGA  38 . 
     In the example shown in  FIG.  5   , pads  50  corresponding to the mixed pitch BGA  38  are arranged with columns  52  separated by the same pitch  56  and rows  54  separated by either pitch  56  or pitch  58 . Rows  54  containing one of a differential signal pair  60  are separated from the row  54  containing the other of the pair of differential signals by a pitch  58  while other rows are separated by pitch  56 . Ground pads  62  surround each differential signal pair  60 , with rows and columns of grounds  62  separating each differential signal pair  60 . As noted above, such an approach significantly reduces TX-TX and RX-RX crosstalk noise over a traditional 1 mm BGA pitch approach. In contrast to the example shown in  FIGS.  2 A and  2 B , the example approach of  FIG.  5    includes a section  64  having power (VDD) pads  66  and ground pads  62  separated by a third pitch which is less than the first pitch. As noted above, in an example approach where the first pitch is 1 mm and the second pitch is 1.25 mm, the third pitch may be defined as 0.8 mm. As in the example shown in 
       FIG.  2 B , one can further increase crosstalk isolation by inserting ground vias  76  in the space on the corresponding package footprint  45  of PCB  44  created by the increased pitch of the second pitch. 
     In one example approach, one may use the third pitch in sections of bottom surface  42  to reduce the length or width of BGA substrate  36 . Such an approach may be used, for example, for low frequency signal lines. 
       FIG.  6 A  is a flowchart illustrating an example technique for distributing connector pads on the BGA substrate  36  of  FIG.  5   , in accordance with techniques of this disclosure. The technique is described with reference to the substrate  36  of  FIG.  5   . Define a first pitch P 1 , a second pitch P 2 , and a third pitch P 3 , where P 3 &lt;P 1 &lt;P 2  ( 120 ). Place selected pairs of pads on the BGA substrate separated by a distance defined by the first pitch ( 122 ). Place ground pads on the BGA substrate separated from the selected pairs of pads by a distance defined by the second pitch ( 124 ). Place the selected pairs of pads on the BGA substrate such that pairs are separated from other pairs by a distance defined by the second pitch ( 126 ). 
       FIG.  6 B  is a flowchart illustrating an example technique for configuring a printed circuit board to receive a BGA package having the mixed pitch BGA substrate of  FIG.  5   , in accordance with techniques of this disclosure. The technique is described with reference to the substrate  36  of  FIG.  5   , based on the pitches described with reference to  FIG.  6 A  and shown in  FIG.  5   . Place pads  46  on the package footprint  45  of PCB  44  to mirror the layout of the mixed pitch BGA package  30  being used ( 140 ). In one example approach, the layout may mirror the pad layout of BGA substrate  36  of  FIG.  5   . Place ground vias (such as ground vias  76  of  FIG.  2 B ) in the space created by increasing the separation between ground pads  72  and the selected pairs of pads  46  on PCB  44  to a distance defined by the second pitch ( 148 ). As shown in  FIG.  2 B , ground vias  76  may be placed between existing ground pads  72  and existing signal pads  70  to increase TX-TX and RX-RX isolation. 
     The techniques described above provide significant crosstalk noise reduction and better signal launch to enable high speed communication such as 112 G serdes signaling using standard PCB and package manufacturing methods. In addition, the techniques provide an advantage by reducing the package size needed to accommodate high speed communication such as 112 G serdes signaling. Package sizes for the new designs are expected to increase less than 10% per side over the ASIC packages used for lower speed 56 G signaling.