Patent Publication Number: US-10790202-B2

Title: Method for evaluating stability of semiconductor manufacturing process

Description:
CROSS REFERENCE TO RELATED APPLICATIONS 
     This application is a Divisional of application Ser. No. 15/495,942 filed Apr. 24, 2017, and included herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to an overlay mark and a method for evaluating process stability of a semiconductor manufacturing process, and more particularly to an overlay mark integrated in a self-aligned double patterning (SADP) process and a method for evaluating process stability of a SADP process. 
     2. Description of the Prior Art 
     In a variety of manufacturing and production settings, there is a need to control alignment between various layers or within particular layers of a given sample. For example, in the context of semiconductor processing, semiconductor-based devices may be produced by fabricating a series of layers on a substrate, some or all of the layers including various structures. The relative position of the structures both within a single layer and with respect to structures in other layers is critical to the performance of the devices. The misalignment between various structures is known as overlay error. 
     The measurement of overlay error between successive patterned layers on a wafer is one of the most critical process control techniques used in the manufacturing of integrated circuits and devices. Overlay accuracy generally pertains to the determination of how accurately a first patterned layer aligns with respect to a second patterned layer disposed above or below and to the determination of how accurately a first pattern aligns with respect to a second pattern disposed on the same layer. Presently, overlay measurements are performed via test patterns that are printed together with layers of the wafer. However, there are some shortcomings of conventional solutions such as asymmetry of patterned line profile that may bring to measurement error due to the inconsistent in x/y overlay direction measurement. 
     SUMMARY OF THE INVENTION 
     It is one of the primary objectives of the present invention to provide an overlay mark and a method for evaluating process stability of a semiconductor manufacturing process, which can be used in a self-aligned double patterning (SADP) process. 
     To achieve the purpose described above, the present invention provides an overlay mark including a substrate and a plurality set of first pattern blocks and second pattern blocks. The substrate has a first direction and a second direction perpendicular to the first direction defined thereon. In each set of the first pattern blocks and the second pattern blocks, the first pattern block is rotational symmetrical to the second pattern blocks along a center, each of the first pattern blocks comprises a big frame and a plurality of small frames, each of the second pattern blocks comprises a big frame and a plurality of small frames, and widths of the big frames are at least three times greater than widths of the small frames. 
     To achieve the purpose described above, the present invention provides a method for evaluating process stability of a semiconductor manufacturing process including following steps. First of all, a substrate is provided, and the substrate has a first direction and a second direction perpendicular to the first direction defined thereon. Then, a semiconductor process is performed to form an overlay mark, the overlay mark includes a plurality set of first pattern blocks and second pattern blocks, wherein in each set of the first pattern blocks and the second pattern blocks, the first pattern block is rotational symmetrical to the second pattern blocks along a center. Each of the first pattern blocks includes a big frame and a plurality of small frames, each of the second pattern blocks includes s a big frame and a plurality of small frames and the sets of the first pattern blocks and the second pattern blocks include a plurality of first sets and a plurality of second sets, wherein the first sets of the first pattern blocks and the second pattern blocks, long edges of the big frames and the second frames are paralleled to the second direction, and a width of short edges of the big frame is at least three times greater than a width of short edges of the small frames. Next, the overlay mark is measured to obtain a plurality of values G1. Finally, a variation of the values G1 is calculated to decide a process stability of the semiconductor process in the first direction. 
     Overall speaking, the present invention provides an overlay mark and a method for valuating process stability of a semiconductor manufacturing process, and which is preferably integrated with a SADP process, so as to acute measuring the vary widths in the pattern. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic diagram illustrating a position of an overlay mark of the present invention in a wafer. 
         FIG. 2  and  FIG. 3  are schematic diagrams illustrating an overlay mark according to a preferred embodiment of the present invention. 
         FIG. 4  and  FIG. 5  are schematic diagrams illustrating manufacturing steps of an overlay mark of the present invention. 
         FIG. 6  is a schematic diagram illustrating measuring vary dimension of an overlay mark of the present invention. 
         FIG. 7  is a schematic diagram illustrating measuring vary dimension of an overlay mark of the present invention. 
         FIG. 8  is a schematic diagram illustrating an overlay mark according to another preferred embodiment of the present invention. 
         FIG. 9  is a schematic diagram illustrating an overlay mark according to another preferred embodiment of the present invention. 
         FIG. 10  is a process flow illustrating a method for evaluating process stability of a semiconductor manufacturing process of the present invention. 
     
    
    
     DETAILED DESCRIPTION 
     To provide a better understanding of the presented invention, preferred embodiments will be described in detail. The preferred embodiments of the present invention are illustrated in the accompanying drawings with numbered elements. 
     The present invention is directed to an overlay mark. In current semiconductor process, the critical dimension of patterns are shrinking and there are many factors that may affect the final dimension of the fin structures when performing advanced manufacturing process such as self-aligned double patterning (SADP). Thus, the size of each fin structure may be variant. The present invention therefore provides an overlay mark to measure if there are shifts in x-axis or in y-axis when preforming a semiconductor process, thereto evaluate the stability of said semiconductor process. 
     Please refer to  FIG. 1 , which show schematic diagrams of the overlay mark on a wafer according to one embodiment of the present invention. As shown in  FIG. 1 , a wafer  300  has a plurality of die regions  404 , which are arranged in array preferably, and a plurality of dicing regions  406 , which are disposed between the die regions  404 . The dicing regions  406  are parallel to a first direction  400  or a second direction  402 , wherein in preferred embodiment the first direction  400  is perpendicular to the second direction  402 . The overlay mark  302  provided in the present invention can be disposed in the same area as the conventional aligning marks, such as in the dicing regions  406 , and preferably in the dicing region  406  positioned between four die regions  404 . In another embodiment, the overlay mark  302  can be disposed in the die region  404 , depending on the design of products. 
     Please refer to  FIG. 2  and  FIG. 3 , which illustrating a schematic diagram of the overlay mark according to one embodiment of the present invention, wherein  FIG. 3  shows an enlarged picture from  FIG. 2  in region D. Please refer to  FIG. 2  first. The overlay mark  302  in the present invention includes a plurality sets of first pattern blocks  304  and second pattern blocks  306 . The first pattern block  304  and the second pattern block  306  in region D refers to the same set. In one preferred embodiment, the plural sets of the first pattern block  304  and the second pattern block  306  are regularly arranged by lines and rows, so the overlaying mark  302  exhibits a pinwheel array from the top view. Detail speaking, when the overlay mark  302  is rotated 180 degrees with respect to a center A, the patterns before and after rotating are invariant, and thus exhibiting a rotational symmetrically. Taking the embodiment in  FIG. 2  for example, there are four sets of the first pattern blocks  304  and the second pattern blocks  306  in region B, and when rotating 180 degrees for the patterns in region B with respect to center A, the patterns may coincide with the patterns in region B′. Similarly, there are four sets of the first pattern blocks  304  and the second pattern blocks  306 . Also, after rotating, the pattern in region C may coincide with the pattern in region C′. 
     About the detailed structure of the aligning mark, please see  FIG. 3 , which shows one set of the first pattern block  304  and the second pattern block  306 . As shown in  FIG. 3 , the first pattern block  304  includes one big frame  304 B and a plurality of small frames  304 S. The big frame  304 B and the small frame  304  extend along the first direction  400 , meaning that both of the their lengths are parallel to the first direction  400 . In one embodiment, the big frame  304 B and the small frame  306 B have the same frame thickness T. In the first pattern block  304 , the big frame  304 B is positioned at the border of the first pattern block  304 , meaning that all the small frames  304 S are positioned at one side of the big frame  304 B while there are no small frames  304 S at the other side. In one embodiment, the big frame  304 B and the small frame  304 S have the same length L, but the width W B  of the big frame  304 B is substantially  3  times greater than the width W S  of the small frame  304 S. Similarity, the second pattern block  306  includes one big frame  306 B and a plurality of small frames  306 S, wherein the arrangements of these frames are similar to those in the first pattern block  304 . It is noted that the big frame  306 B and the small frame  306 S of the second pattern block  306  would be disposed at the corresponding position with respect to that of the big frame  304 B and the small frame  304 S of the first pattern block  304 . That is, the big frame  304 B of the first pattern block  304  resides at one side of the first pattern block  304  and the second pattern block  306 , and the big frame  306 B of the second pattern block  306  resides at the other side of the first pattern block  304  and the second pattern block  306 . In one embodiment, the number of the small frames  306 S in the second pattern block  306  is equal to the number of the small frames  304 S in the first pattern block  304 , and the small frames  304 S of the first pattern block  304  and the small frames  306 S of the second pattern block  306  are aligned with each other. In this manner, the first pattern block  304  and the second pattern block  306  are rotational asymmetrical with respect to the center E, which refers to the center point of the first pattern block  304  of the second pattern block  306 . 
     The overlay mark is preferably formed in combination with the self-aligning double patterning, SADP) technology. Please refer to  FIG. 4 ,  FIG. 5 , and  FIG. 3 , which illustrating the methods of fabricating the overlay mark according to one embodiment of the present invention. First, as shown in  FIG. 4 , a patterned mandrel  500  is formed on the substrate  300 . The patterned mandrel  500  corresponds to the area encompassed by the big frame  304 B and the small frames  304 S in the first pattern block  304 , and the big frame  306 B and the small frame  306 S in the second pattern block  306 . Next, as shown in  FIG. 5 , a spacer  502  is formed on the sidewall of the patterned mandrel  500  and surrounds the patterned mandrel  500 . The thickness T of the spacer  502  is greater than the distance between each two spacers  502 . Lastly, the patterned mandrel  500  is removed so the remained spacer  502  forms the first block pattern  304  and the second block pattern  306 . 
     By setting plural first pattern blocks  304  and the second pattern blocks  306 , the changes of the pitch of the patterned mandrel  500  may be indirectly obtained by measuring the relative positions of patterns in the first pattern blocks  304  and the second pattern blocks  306 . Please refer to  FIG. 6 , which shows a schematic diagram illustrating measuring of the CD change by using the overlay mark in the present invention. As shown in  FIG. 6 , the top portion of  FIG. 6  illustrates a predicted size of the first pattern blocks  304  and the second pattern blocks  306  in the wafer  300 , wherein a gap between the big frame  304 B of the first pattern block  304  and the big frame  306 B of the second pattern blocks  306  is about G. It is noted that, the aforementioned gap refers the projection distance in the second direction  402 , between an edge of the big frame  304 B of the first pattern blocks  304  and an edge of the big frame  306 B of the second pattern blocks  306  which are opposite with each other. Under such arrangement, while the width (CD for example) of the pattern mandrel layer  500  is increased by the changed parameters in the manufacture process, as shown in the middle portion in  FIG. 6 , the gap G′ between the big frame  304 B of the first pattern block  304  and the big frame  306 B of the second pattern block  306  may decrease accordingly. On the other hand, while the width (CD for example) of the pattern middle-column layer  500  is reduced by the changed parameters in the manufacture process, as shown in the bottom portion in  FIG. 6 , the gap G″ between the big frame  304 B of the first pattern block  304  and the big frame  306 B of the second pattern block  306  may therefore increase. In this way, it is sufficient to obtain the variation of the width of the patterned mandrel layer  500  through measuring the gap between the big frame  304 B and the big frame  306 B. For example, if the gap G′ is greater than the predict value G, the width of the patterned mandrel layer  500  is presumed to increased. On the other hand, if the gap G″ is less than the predict value G, the width of the patterned middle-column layer  500  is presumed to decreased accordingly. Thus, the variation of the dimensions is allowable to be indirectly measured in the present invention, even without using high-resolution photography technique. 
     By setting plural sets of the first pattern blocks  304  and the second pattern blocks  306  can be used to verify the deviation of the CD, so as to monitor the staleness of the process. Please see  FIG. 7 , which shows a schematic diagram of methods of monitoring CD value. In the embodiment of  FIG. 7 , there are eight sets of the first pattern blocks  304  and second pattern blocks  306 , wherein the high of the big frame  304 B is parallel to that of the first pattern block  304  along the first direction  400 , and the big frame  304 B and the big frame  304 B has a distance G 1 . By measuring the 8 gaps value G 1 , a deviation value regarding to the 8 gap G 1  along to the second direction  402  can be obtained. When we got G1 values with small difference, it means that the CD value has not great big variation, so the manufacturing stability can be confirmed along the first direction  400 . Similarly, there are eight sets of the second pattern blocks  306  and second pattern blocks  308 , wherein the high of the big frame  304 B is parallel to that of the first pattern block  304  along the first direction  400 , and the big frame  304 B and the big frame  304 B have a distance G 2  therebetween. By measuring the 8 gaps value G 2 , a deviation value representing the CD deviation along to the second direction  402  can be obtained. When we got G 2  values with small difference, it means that the CD value has not great big variation, so the manufacturing stability can be confirmed along the first direction  400 . It is noted that the sets and the positions of the first pattern block  304  and the second pattern block  306  can be altered arbitrarily according to the design of product. 
     Please refer to  FIG. 8 , in which an overlay mark according to another preferred embodiment of the present invention is shown. As shown in  FIG. 8 , after performing the SADP process to form the overlay mark, a cutting process may be additionally performed to cut off portions of the big frame  304 B,  306 B to form a plurality of half-framed patterns. In a preferred embodiment of the present invention, the big frames  304 B remained in the first pattern blocks  304  face to the second pattern blocks  306 , and the big frames  306 B remained in the second pattern blocks  306  face to the first pattern blocks  304 . That is, openings of two half-frame of the big frames  304 B,  306 B are opposite to each other. 
     In one embodiment, the measuring pattern may also include the big frame only in one direction. Please refer to  FIG. 9 , in which an overlay mark according to another preferred embodiment of the present invention is shown. As shown in  FIG. 9 , only the first measuring patterns  304  and the second measuring patterns  306  paralleled to the first direction  400  have the big frame  304 B and the big frame  306 B. In other words, the first measuring patterns  304  and the second measuring patterns  306  paralleled to the second direction  402  only include the small frames  304 S,  306 S instead of the big frames. 
     Furthermore, the first pattern blocks  304  and the second pattern blocks  306  in one set of the measuring patterns may also be integrated in a general aligning mark, so as to become a part of the general aligning mark or a part of the pre-layer of the general aligning mark. In this way, the variation of the critical dimension may be immediately measured while the aligning process. 
     Please refer to  FIG. 10 , in which a process flow is shown to illustrate a method of evaluating process stability. As shown in  FIG. 10 , the method for evaluating process stability includes following steps: 
     in step  600 : providing a substrate, the substrate having a first direction and a second direction perpendicular to the first direction defined thereon; 
     in step  602 : performing a semiconductor process to form an overlay mark, the overlay mark comprising a plurality sets of first pattern blocks and second pattern blocks, wherein in each set of the first pattern block and the second pattern block, the first pattern block is rotational symmetrical to the second pattern blocks along a center, each of the first pattern blocks comprises a big frame and a plurality of small frames, each of the second pattern blocks comprises a big frame and a plurality of small frames and the sets of the first pattern blocks and the second pattern blocks comprise a plurality of first sets and a plurality of second sets, wherein the first sets of the first pattern blocks and the second pattern blocks, long edges of the big frames and the second frames are paralleled to the second direction, and a width of short edges of the big frame is at least three times greater than a width of short edges of the small frames; 
     in step  604 : measuring the overlay mark, to obtain a plurality of values G 1 ; 
     in step  606 : calculating a variation of the values G1, to decide a process stability of the semiconductor process in the first direction. 
     Overall, the present invention provides an overlay mark and a method for valuating process stability of a semiconductor manufacturing process, and which is preferably integrated with a SADP process, so as to acute measuring the vary widths in the pattern. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.