Patent Publication Number: US-2017365706-A1

Title: Field effect transistors with self-aligned extension portions of epitaxial active regions

Description:
BACKGROUND 
     The present disclosure relates to a semiconductor structure, and particularly to field effect transistors including self-aligned epitaxial active region extensions and a method of manufacturing the same. 
     The gate length of a field effect transistor is determined by the distance between a pair of active region extensions. Typically, a combination of ion implantation and an activation anneal is employed to form active region extensions. The activation anneal is necessary because only electrical dopants located at substitutional sites are effective in providing free electrical charges in a band gap structure. However, the activation anneal also promotes diffusion of the implanted electrical dopants, thereby blurring the p-n junctions between the body region and the active region extensions. As a result, the diffusion of the implanted electrical dopants during the activation anneal has a deleterious effect of increased leakage current and variations in the threshold voltage. Thus, a field effect transistor is desired in which clearly defined p-n junctions are provided between a body region and active region extensions. 
     SUMMARY 
     A gate structure is formed across a single crystalline semiconductor fin. An amorphizing ion implantation is performed employing the gate structure as an implantation mask to amorphize surface portions of the semiconductor fin into inverted U-shaped amorphous semiconductor portions. A gate spacer is formed around the gate structure, and the inverted U-shaped amorphous semiconductor portions are etched selective to a single crystalline portion of the semiconductor fin and the gate structure. A pair of inverted U-shaped cavities is formed underneath the gate spacer and above the remaining portion of the semiconductor fin. A doped epitaxial semiconductor material is deposited by a selective epitaxy process to form doped epitaxial active regions that include self-aligned extension portions underlying the gate spacer. 
     According to an aspect of the present disclosure, a method of forming a semiconductor structure is provided. A semiconductor fin including a single crystalline semiconductor material is formed on a substrate. A gate structure is formed across the semiconductor fin. Surface portions of the semiconductor fin are amorphized employing the gate structure as an implantation mask. A gate spacer is formed around the gate structure and on the amorphous surface portions of the semiconductor fin. The amorphous surface portions of the semiconductor fin are removed while preserving a single crystalline portion of the semiconductor fin. 
     According to another aspect of the present disclosure, a semiconductor structure includes a semiconductor fin located on a substrate and including a first portion having a first height throughout and a pair of second portions. Each of the pair of second portions has a second height throughout and is adjoined to the first portion. The semiconductor structure further includes a gate structure, which includes a gate dielectric and a gate electrode and contacts a top surface and sidewall surfaces of the first portion. The semiconductor structure further includes a gate spacer and an active region. The gate spacer laterally surrounds the gate structure. A bottom surface of the gate spacer is planar with a horizontal interface between the gate structure and the first portion. The active region includes a doped epitaxial semiconductor material and contacts a top surface of one of the second portions, the bottom surface of the gate spacer, and an outer sidewall of the gate spacer. 
    
    
     
       BRIEF DESCRIPTION OF SEVERAL VIEWS OF THE DRAWINGS 
         FIG. 1A  is a top-down view of an exemplary structure after formation of semiconductor fins on a substrate according to an embodiment of the present disclosure. 
         FIG. 1B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 1A . 
         FIG. 1C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 1A . 
         FIG. 1D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 1A . 
         FIG. 2A  is a top-down view of an exemplary structure after formation of a disposable gate structure and amorphization of surface portions of semiconductor fins by ion implantation according to an embodiment of the present disclosure. 
         FIG. 2B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 2A . 
         FIG. 2C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 2A . 
         FIG. 2D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 2A . 
         FIG. 3A  is a top-down view of an exemplary structure after formation of a gate spacer according to an embodiment of the present disclosure. 
         FIG. 3B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 3A . 
         FIG. 3C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 3A . 
         FIG. 3D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 3A . 
         FIG. 4A  is a top-down view of an exemplary structure after removal of amorphized portions of the semiconductor fins by an isotropic etch according to an embodiment of the present disclosure. 
         FIG. 4B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 4A . 
         FIG. 4C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 4A . 
         FIG. 4D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 4A . 
         FIG. 5A  is a top-down view of an exemplary structure after formation of active regions according to an embodiment of the present disclosure. 
         FIG. 5B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 5A . 
         FIG. 5C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 5A . 
         FIG. 5D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 5A . 
         FIG. 5E  is a vertical cross-sectional view of the exemplary structure along the vertical plane E-E′ of  FIG. 5A . 
         FIG. 6A  is a top-down view of an exemplary structure after removal of the disposable gate structure according to an embodiment of the present disclosure. 
         FIG. 6B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 6A . 
         FIG. 6C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 6A . 
         FIG. 6D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 6A . 
         FIG. 7A  is a top-down view of an exemplary structure after formation of a replacement gate structure according to an embodiment of the present disclosure. 
         FIG. 7B  is a vertical cross-sectional view of the exemplary structure along the vertical plane B-B′ of  FIG. 7A . 
         FIG. 7C  is a vertical cross-sectional view of the exemplary structure along the vertical plane C-C′ of  FIG. 7A . 
         FIG. 7D  is a vertical cross-sectional view of the exemplary structure along the vertical plane D-D′ of  FIG. 7A . 
     
    
    
     DETAILED DESCRIPTION 
     As stated above, the present disclosure relates to field effect transistors including self-aligned epitaxial active region extensions and a method of manufacturing the same. Aspects of the present disclosure are now described in detail with accompanying figures. It is noted that like reference numerals refer to like elements across different embodiments. The drawings are not necessarily drawn to scale. As used herein, ordinals such as “first” and “second” are employed merely to distinguish similar elements, and different ordinals may be employed to designate a same element in the specification and/or claims. 
     Referring to  FIGS. 1A-1D , an exemplary structure according to an embodiment of the present disclosure includes semiconductor fins  30  formed on a substrate ( 10 ,  20 ). In one embodiment, a semiconductor-on-insulator (SOI) substrate including a handle substrate  10 , a buried insulator layer  20 , and a top semiconductor layer can be provided. The top semiconductor layer of the SOI substrate can be patterned to form the semiconductor fins  30 . The patterning of the top semiconductor layer can be performed, for example, by applying a photoresist layer over the top surface of the top semiconductor layer, lithographically patterning the top semiconductor layer, and anisotropically etching physically exposed portions of the top semiconductor layer employing the patterned photoresist layer as an etch mask. The anisotropic etch can be, for example, a reactive ion etch. The photoresist layer can be subsequently removed, for example, by ashing. 
     The handle substrate  10  can include a semiconductor material, a conductive material, and/or a dielectric material. The handle substrate  10  can provide mechanical support to the buried insulator layer  20  and the top semiconductor layer, and the semiconductor fins  30  that are remaining portions of the top semiconductor layer after the anisotropic etch. The thickness of the handle substrate  10  can be from 30 microns to 2 mm, although lesser and greater thicknesses can also be employed. 
     The buried insulator layer  20  includes an amorphous dielectric material. The buried insulator layer  20  can include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, sapphire, or a combination thereof. The thickness of the buried insulator layer  20  can be from 50 nm to 5 microns, although lesser and greater thicknesses can also be employed. In one embodiment, the buried insulator layer  20  and the handle substrate  10  can be a single contiguous structure including a same insulator material, i.e., the handle substrate  10  and the buried insulator layer  20  can be merged into a single insulating layer including a same insulating material. In another embodiment, the substrate can be a bulk semiconductor substrate in which a buried insulator layer  20  is not present. 
     The top semiconductor layer, and consequently, the semiconductor fins  30  can include a single crystalline semiconductor material or a polycrystalline material. In one embodiment, the semiconductor fins  30  can include an elemental semiconductor material such as Si or Ge, a semiconductor material primarily composed of Group IV elements such as a silicon-germanium alloy or a silicon-carbon alloy, a III-V compound semiconductor material, a II-VI compound semiconductor material, or an organic semiconductor material. In one embodiment, the semiconductor fins  30  can include a single crystalline elemental semiconductor material, a single crystalline semiconductor material primarily composed of Group IV elements, a single crystalline III-V compound semiconductor material, a single crystalline II-VI compound semiconductor material, or a single crystalline organic semiconductor material. In one embodiment, the semiconductor fins  30  can consist essentially of undoped single crystalline silicon or single crystalline silicon doped with p-type dopant atoms or n-type dopant atoms. 
     As used herein, a “semiconductor fin” refers to a semiconductor structure including a portion having a shape of a rectangular parallelepiped. In one embodiment, the portion having the shape of a rectangular parallelepiped can be the entirety of the semiconductor structure. In another embodiment, the portion having the shape of a rectangular parallelepiped can be included in, and is less than, the entirety of the semiconductor structure. In one embodiment, the surfaces of a semiconductor can include three mutually perpendicular pairs of parallel sidewalls. The direction along which a semiconductor fin laterally extends the most is herein referred to as a “lengthwise direction” of the semiconductor fin. The height of the semiconductor fins  30  can be in a range from 5 nm to 300 nm, although lesser and greater heights can also be employed. The width of each semiconductor fin  30  can be in a range from 5 nm to 100 nm, although lesser and greater widths can also be employed. Multiple semiconductor fins  30  may be arranged such that the multiple semiconductor fins  30  have the same lengthwise direction, and are laterally spaced from each other along a horizontal direction that is perpendicular to the lengthwise direction. In this case, the horizontal direction that is perpendicular to the common lengthwise direction is referred to as a “widthwise direction.” 
     Referring to  FIGS. 2A-2D , a gate structure can be formed across at least one semiconductor fin  30 . In one embodiment, the gate structure can be a disposable gate structure ( 50 ,  51 ). The disposable gate structure ( 50 ,  51 ) is a gate structure that is removed in a subsequent processing step. The disposable gate structure ( 50 ,  51 ) can be formed, for example, by deposition of a disposable material layer and optionally a gate cap dielectric layer, and patterning of the stack of the disposable material layer and the gate cap dielectric layer. A remaining portion of the disposable material layer constitutes a disposable material portion  50 . A remaining portion of the gate cap dielectric layer, if employed, constitutes a gate cap dielectric portion  51 . 
     The disposable material portion  50  can include a semiconductor material, a dielectric material, or a metallic material, provided that the material of the disposable material portion  50  can be removed selective to the materials of a planarization dielectric layer and a gate spacer to be subsequently formed and selective to the material of the semiconductor fins  30 . For example, the disposable material portion  50  can include amorphous carbon, diamond-like carbon (DLC), polycrystalline or amorphous germanium, a silicon-germanium alloy, organosilicate glass, a doped silicate glass, an elemental metal, an alloy of at least two elemental metals, a conductive metallic alloy, or a combination thereof. The disposable gate structure ( 50 ,  51 ) can straddle the semiconductor fins  30  along the widthwise direction of the semiconductor fins  30 . 
     Ions can be implanted into surfaces portions of the semiconductor fins  30  employing the disposable gate structure ( 50 ,  51 ) as an implantation mask. The ions can be ions of an elemental semiconductor material, ions of a noble gas, or ions of a gas including at least one fluorine atom, at least one chlorine atom, at least one oxygen atom, at least one nitrogen atom, at least one phosphor atom, at least one arsenic atom, at least one sulfur atom, and/or at least one boron atom. In one embodiment, the species of the ions can be selected so that the mass of the ions is greater than the average mass of the atoms of the semiconductor material in the semiconductor fins  30 . For example, if the semiconductor fins  30  include a silicon germanium alloy, the implanted ions can be germanium ions. Exemplary species for the ions to be implanted into the surface portions of the semiconductor fins  30  include, but are not limited to, Ge, Si, Kr, Xe, Ne, F 2 , Cl 2 , O 2 , O 3 , N 2 , N 2 O, NO 2 , PH 3 , AsH 3 , SF 6 , and BF 2 . In one embodiment, the species of the implanted ions can be germanium. 
     The energy of the implanted ions is selected such that the semiconductor material of the semiconductor fins  30  becomes amorphized. Further, the species and the energy of the implanted ions are selected such that the amorphized portions of the semiconductor fins  30  are limited to surface portions. Two amorphous surface portions  31 , separated by the disposable gate structure ( 50 ,  51 ), are formed within each semiconductor fin  30 . Each amorphous surface portion  31  is an amorphized semiconductor portion located underneath surfaces of a semiconductor fin  30 , and includes the semiconductor material of the semiconductor fins  30  as provided at the processing steps of  FIGS. 1A-1D , and further includes the implanted ions. 
     In one embodiment, the ion implantation is performed at a non-zero and non-orthogonal angle with respect to a vertical plane passing through the lengthwise direction of the semiconductor fins  30 . The magnitude of the angle α between the vertical plane and the direction of the ion implantation can be in a range from 0.1×π/2 to 0.9×π/2 in radians, although lesser and greater angles can also be employed. In order to convert all surface portions underlying physically exposed surfaces, more than two rounds of ion implantation can be performed at different values of the angle α. For example, a first value for the angle α during a first angled ion implantation can be in a range from 0.1×π/2 to 0.19×π/2 in radians, and a second value of the angle α during the second angled ion implantation can be in a range from −0.9×π/2 to −0.1×π/2 in radians. In one embodiment, the angled implantation angle α during the ion implantation steps can be set to +/−45 degrees. 
     Within each semiconductor fin  30 , two sub-portions of each semiconductor fin  30 , which are spaced from the sidewalls and the top surface of the semiconductor fin  30  and do not underlie the disposable gate structure ( 50 ,  51 ), remain single crystalline after the ion implantation process. Within each semiconductor fin  30 , a single contiguous portion including the two sub-portions and the portion that underlies the disposable gate structure ( 50 ,  51 ) remain single crystalline after the ion implantation process. Within each semiconductor fin  30 , the single contiguous portion including the same single crystalline semiconductor material as the semiconductor fins  30  as provided at the processing steps of  FIGS. 1A-1D  is herein referred to as a single crystalline semiconductor portion  30 ′. Each semiconductor fin  30  includes a single crystalline semiconductor portion  30 ′ and two amorphous surface portions  31 . The width of each vertical portion of an amorphous surface portion  31  can be in a range from 5% to 45% of the width of a semiconductor fin ( 30 ′,  31 ) in which the amorphous surface portion  31  is formed. 
     Referring to  FIGS. 3A-3D , a gate spacer  52  can be formed around the disposable gate structure ( 50 ,  51 ) and on the surfaces of the amorphous surface portions  31  of the semiconductor fins ( 30 ′,  31 ). The gate spacer  52  includes a dielectric material, which can be, for example, silicon nitride, silicon oxide, silicon oxynitride, a dielectric metal oxide, a dielectric metal nitride, or a combination thereof. The inner gate spacer  52  can be formed, for example, by depositing a conformal dielectric material layer, and by anisotropically etching the conformal dielectric material layer. Horizontal portions of the conformal dielectric material layer are removed by the anisotropic etch, and remaining vertical portions of the conformal dielectric material layer constitute the gate spacer  52 . The thickness of the gate spacer  52 , i.e., the lateral dimension between an inner sidewall of the gate spacer  52  and a most proximal portion of the outer sidewall of the gate spacer  52 , can be in a range from 5 nm to 100 nm, although lesser and greater thicknesses can also be employed. 
     Referring to  FIGS. 4A-4D , the amorphous surface portions  31  of the semiconductor fins ( 30 ′,  31 ) are removed selective to the single crystalline semiconductor portions  30 ′ by an isotropic etch. An etch chemistry that provides a greater etch rate for the amorphous semiconductor material in the amorphous surface portions  31  than for the single crystalline semiconductor material in the single crystalline semiconductor portions  30 ′ can be employed. The removal of the amorphous surface portions  31  of the semiconductor fins ( 30 ′,  31 ) is thus performed while preserving a single crystalline portion of the semiconductor fins ( 30 ′,  31 ), i.e., while preserving the entirety, or most, of the single crystalline semiconductor portions  30 ′. 
     In one embodiment, the etch selectivity, i.e., the ratio of the etch rate for the single crystalline semiconductor material in the single crystalline semiconductor portions  30 ′ can be greater than the etch rate for the amorphous semiconductor material in the amorphous surface portions  31 , can be greater than 2. Thus, the amorphous surface portions  31  of the semiconductor fins ( 30 ′,  31 ) are removed by the isotropic etch that etches an amorphized semiconductor material in the amorphous surface portions  31  faster than the single crystalline semiconductor material in the single crystalline semiconductor portions  30 ′ by a factor of at least two. In another embodiment, the etch selectivity can be greater than 3. In yet another embodiment, the etch selectivity can be greater than 10. In still another embodiment, the etch selectivity can be greater than 30. In one embodiment, the removal of the amorphous semiconductor material in the amorphous surface portions  31  can be performed selective to the single crystalline semiconductor material in the single crystalline semiconductor portions  30 ′, i.e., without any substantial removal of the single crystalline semiconductor material in the single crystalline semiconductor portions  30 ′ and while keeping the single crystalline semiconductor portions  30 ′ essentially intact. 
     An undercut region  29  is formed underneath the gate spacer  52  and above each single crystalline semiconductor portions  30 ′, which is a single crystalline portion of the semiconductor fin  30  in the processing steps of  FIGS. 3A-3D , by removal of the amorphous surface portions  31  of the semiconductor fin ( 30 ′,  31 ). Each undercut region  29  has a vertical cross-sectional shape of an inverted U-shape as illustrated in  FIG. 4D . The inverted U-shape is invariant under translation between a vertical plane including an inner sidewall of the gate spacer  52  and perpendicular to the lengthwise direction of the single crystalline semiconductor portions  30 ′ and another vertical plane including an outer sidewall of the gate spacer  52  and perpendicular to the lengthwise direction of the single crystalline semiconductor portions  30 ′. The lengthwise direction of the single crystalline semiconductor portions  30 ′ is the same as the lengthwise direction of the semiconductor fins  30  as provided at the processing steps of  FIGS. 1A-1D . 
     Each single crystalline semiconductor portions  30 ′, which is a single crystalline portion of a semiconductor fin ( 30 ′,  31 ) as provided at the processing steps of  FIGS. 3A-3D , includes a first portion having a first height h 1  throughout and underlying the disposable gate structure ( 50 ,  51 ), and a pair of second portions. Each of the pair of second portions has a second height h 2  throughout, and is adjoined to the first portion. Each periphery at which the pair of second portions adjoin the first portion is within the a vertical plane including an interface between the disposable gate structure ( 50 ,  51 ) and the gate spacer  52  and perpendicular to the lengthwise direction of the single crystalline semiconductor portions  30 ′. 
     The first portion can have a first width w 1 , which is the same as the original width of a semiconductor fin  30  from which the first portion is derived. Each second portion can have a second width w 2 , which is less than the first width w 1  by twice the thickness of a vertical portion of an amorphous surface portion  31 . Each single crystalline semiconductor portion  30 ′ includes three portions, each of the three portions having a shape of a rectangular parallelepiped. 
     Referring to  FIGS. 5A-5E , active regions ( 3 S,  3 D) can be formed on physically exposed semiconductor surfaces of the single crystalline semiconductor portions  30 ′ by selective deposition of a semiconductor material. As used herein, an “active region” can be a source region or a drain region. The active regions ( 3 S,  3 D) include a source region  3 S that is formed on surfaces of the single crystalline semiconductor portions  30 ′ located on one side of the disposable gate structure ( 50 ,  51 ), and a drain region  3 D that is formed on surfaces of the single crystalline semiconductor portions  30 ′ located on the other side of the disposable gate structure ( 50 ,  51 ). 
     In one embodiment, the selective deposition of the semiconductor material can be performed by a selective epitaxy process. During the selective epitaxy process, the deposited semiconductor material grows from physically exposed semiconductor surfaces, i.e., the physically exposed surfaces of the single crystalline semiconductor portions  30 ′. The semiconductor material does not grow from dielectric surfaces such as the surfaces of the gate cap dielectric portion  51 , the gate spacer  52 , or the buried insulator layer  20 . 
     The active regions ( 3 S,  3 D) can be epitaxially aligned to the single crystalline semiconductor portions  30 ′. The active regions ( 3 S,  3 D) can include the same semiconductor material as, or a semiconductor material different from, the semiconductor material of the single crystalline semiconductor portions  30 ′. The growth of the active regions ( 3 S,  3 D) can proceed with, or without, crystallographically faceted surfaces depending on the deposited semiconductor material and the deposition conditions. 
     In one embodiment, the selective epitaxy process can proceed until multiple semiconductor material portions grown from neighboring single crystalline semiconductor portions  30 ′ merge to form merged active regions ( 3 S,  3 D) such that the source region  3 S is a single contiguous structure, and the drain region  3 D is another single contiguous structure. 
     In one embodiment, the active regions ( 3 S,  3 D) can be formed with in-situ doping during the selective epitaxy process. Thus, each portion of the active regions ( 3 S,  3 D) can be formed as doped semiconductor material portions. Alternatively, the active regions ( 3 S,  3 D) can be formed by ex-situ doping. In this case, the active regions ( 3 S,  3 D) can be formed as intrinsic semiconductor material portions and electrical dopants can be subsequently introduced into the active regions ( 3 S,  3 D) to convert the active regions ( 3 S,  3 D) into doped semiconductor material portions. The active regions ( 3 S,  3 D) can have a doping of the opposite conductivity type than the single crystalline semiconductor portions  30 ′. In this case, a p-n junction can be formed at the interface between the single crystalline semiconductor portions  30 ′ and each of the active regions ( 3 S,  3 D). 
     Each single crystalline semiconductor portion  30 ′ is a semiconductor fin including three portions, each having a shape of a parallelepiped. The lengthwise direction of the single crystalline semiconductor portions  30 ′ can be the same, and can be the same as the lengthwise direction of the semiconductor fins  30  as provided at the processing steps of  FIGS. 3A-3D . Thus, each active region ( 3 S,  3 D) is formed directly on, and grows from, surfaces of the single crystalline portions of semiconductor fins. Further, each active region ( 3 S,  3 D) can contacts a horizontal bottom surface of the gate spacer  52  and a pair of vertical sidewalls of the gate spacer  52  that are parallel to the lengthwise direction of the semiconductor fins. 
     Each single crystalline semiconductor portion  30 ′ functions as a body region of the field effect transistor in the exemplary structure, and is herein referred to as a body region  3 B. An extension portion, i.e., a laterally protruding portion, of the source region  3 S fills each undercut on the source side and underneath the gate spacer  52 , and an extension portion of the drain region  3 D fills each undercut on the drain side and underneath the gate spacer  52 . The bottommost surface of the gate spacer  52  can be vertically spaced from a top surface of each body region  3 B by a separation distance d, which is the same as the height of a horizontal sub-portion of the extension portion of the source region  3 S or a horizontal sub-portion of the extension portion of the drain region  3 D. 
     Each extension portion of the source region  3 S can have an inverted U-shape, and each extension portion of the drain region  3 D can have an inverted U-shape, as illustrated in  FIG. 5D . The lateral dimension of each extension portion of the source region  3 S along the lengthwise direction of the body regions  3 B can be the same as the thickness of the gate spacer  52 . Likewise, the lateral dimension of each extension portion of the drain region  3 D along the lengthwise direction of the body regions  3 B can be the same as the thickness of the gate spacer  52 . Outer sidewalls of the extension portions of the source region  3 S and outer sidewalls of the extension portions of the drain region  3 D can be within the same vertical planes as the sidewalls of the first portion of each body region  3 B, i.e., the portion that underlies the disposable gate structure ( 50 ,  51 ) and having the first width w 1 . 
     Referring to  FIGS. 6A-6D , a planarization dielectric layer  60  can be formed over the active regions ( 3 S,  3 D), the disposable gate structure ( 50 ,  51 ), the gate spacer  52 , and the buried insulator layer  20 . The dielectric material of the planarization dielectric layer  60  can be deposited, for example, by chemical vapor deposition (CVD) or spin coating. The planarization dielectric layer  60  includes a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, organosilicate glass (OSG), or a combination thereof. Chemical mechanical planarization (CMP) can be employed to planarized the top surface of the planarization dielectric layer  60 . In one embodiment, the gate cap dielectric portion  51  can be employed as a stopping structure during the planarization process. 
     The disposable gate structure ( 50 ,  51 ) is subsequently removed selective to the planarization dielectric layer  60 , the gate spacer  52 , and the body regions  3 B (which is the single crystalline portion of the semiconductor fins  30  as provided at the processing steps of  FIGS. 3A-3D ). At least one isotropic etch and/or at least one anisotropic etch may be employed to removed the disposable gate structure ( 50 ,  51 ). The gate cap dielectric portion  51  can be removed by a wet etch or a dry etch. Alternately, the gate cap dielectric portion  51  can be removed during the planarization of the top surface of the planarization dielectric layer  60 . If the disposable material portion  50  includes amorphous carbon or diamond-like carbon (DLC), the disposable material portion  50  can be removed by ashing. Depending on the composition of the disposable material portion  50 , a suitable etch chemistry can be selected in order to remove the disposable material portion  50  while minimizing collateral etching of the body regions  3 B. A gate cavity  79  is formed in the volume from which the disposable gate structure ( 50 ,  51 ) is removed. The etch processes that remove the disposable gate structure ( 50 ,  51 ) may, or may not, be selective to the dielectric material of the buried insulator layer  20 . 
     Referring to  FIGS. 7A-7D , a replacement gate structure ( 70 ,  72 ) can be formed in the gate cavity  49  by deposition of a gate dielectric layer and at least one conductive material layer. The gate dielectric layer can include any gate dielectric material known in the art. The at least one conductive material layer can include any conductive material that is known to be suitable for a gate electrode of a field effect transistor. Excess portion of the at least one conductive material layer and the gate dielectric layer can be removed from above the top surface of the planarization dielectric layer  60 , for example, by chemical mechanical planarization (CMP). The remaining portion of the gate dielectric layer constitutes a gate dielectric  70  of the replacement gate structure ( 70 ,  72 ), and the remaining portion of the at least one conductive material layer constitutes a gate electrode  72  of the replacement gate structure ( 70 ,  72 ). 
     The gate dielectric  70  is formed directly on the top surface and the sidewalls of each body region  3 B. In one embodiment, the gate dielectric  70  can be a single contiguous structure that contacts all top surfaces and sidewall surfaces of the body regions  3 B and the inner sidewalls of the gate spacer  52  and the top surface of the buried insulator layer  20 . 
     A contact level dielectric layer  90  can be formed over the planarization dielectric layer  60 . The contact level dielectric layer  90  includes a dielectric material such as organosilicate glass (OSG), silicon oxide, silicon nitride, or a combination thereof. The contact level dielectric layer  90  can be formed, for example, by chemical vapor deposition (CVD) or spin coating. Various contact via structures ( 9 S,  9 D,  9 G) can be formed through the contact level dielectric layer  90  and the planarization dielectric layer  60 . The contact via structures ( 9 S,  9 D,  9 B) can include a source contact via structure  9 S that contacts the source region  3 S, a drain contact via structure  9 D that contacts the drain region  3 D, and a gate contact via structure  9 G that contacts the gate electrode  72 . 
     The exemplary semiconductor structure includes, among others, a semiconductor fin  3 B located on a substrate and including a first portion having a first height h 1  throughout and a pair of second portions. Each of the pair of second portions has a second height h 2  throughout and is adjoined to the first portion. The exemplary semiconductor structure further includes a gate structure ( 70 ,  72 ), which contains a gate dielectric  70  and a gate electrode  72 , and contacts a top surface and sidewall surfaces of the first portion. The exemplary semiconductor structure further includes a gate spacer  52  laterally surrounding the gate structure ( 70 ,  72 ). A bottom surface of the gate spacer  52  is planar with a horizontal interface between the gate structure ( 70 ,  72 ) and the first portion. The exemplary semiconductor structure further includes an active region ( 3 S or  3 D) including a doped epitaxial semiconductor material and contacting a top surface of one of the second portions, the bottom surface of the gate spacer  52 , and an outer sidewall of the gate spacer  52 . 
     In one embodiment, the active region ( 3 S or  3 D) can further contact a sidewall of the first portion. In one embodiment, a contact area between the active region ( 3 S or  3 D) and the sidewall of the first portion can include a horizontal portion having a height that is the same as a different between the first height h 1  and the second height h 2 , and a pair of vertical portions having a uniform width, which can be the same as the difference between the first height h 1  and the second height h 2 . This configuration can result when the angled implantation angle α during the ion implantation steps of  FIGS. 2A-2D  is set to +/−45 degrees. 
     In one embodiment, the sidewalls of the first portion that are perpendicular to the lengthwise direction of the semiconductor fin  3 B can be vertically coincident with an inner sidewall of the gate spacer  52 . In one embodiment, the first portion can have the first width w 1  throughout, and each of the pair of second portions can have the second width w 2  throughout. The second width w 2  can be less than the first width w 1 . In one embodiment, the difference between the first width w 1  and the second width w 2  can be twice the difference between the first height h 1  and the second height h 2 . This configuration can result when the angled implantation angle α during the ion implantation steps of  FIGS. 2A-2D  is set to +/−45 degrees. 
     In one embodiment, the entire interface between the semiconductor fin and the active region constitutes a p-n junction. In one embodiment, the active region ( 3 S or  3 D) includes an extension portion having a vertical cross-sectional shape of an inverted U-shape that is invariant under translation between a vertical plane including an inner sidewall of the gate spacer  52  and another vertical plane including the outer sidewall of the gate spacer  52 . The vertical planes are perpendicular to the lengthwise direction of the body region  3 B. In one embodiment, a vertical interface between the active region ( 3 S or  3 D) and gate spacer  52  can be within a same vertical plane as a vertical interface between the gate structure ( 70 ,  72 ) and the first portion of the body region  3 B. 
     The field effect transistor within the exemplary semiconductor structure includes at least one extension portion of the source region  3 S and at least one extension portion of the drain region  3 D that are self-aligned to the edges of the gate electrode  72 . Each of the at least one extension portion of the source region  3 S can have the same dopant concentration as the rest of the source region  3 S, and each of the at least one extension portion of the drain region  3 D can have the same dopant concentration as the rest of the drain region  3 D. By eliminating any dopant gradient across the entirety of the source region  3 S and across the entirety of the drain region  3 D, external resistance of the field effect transistor can be limited only by the resistivity of the doped semiconductor material within the source region  3 S and the drain region  3 D, and is not limited by any dopant gradient near the extension portions of the source region  3 S or the drain region  3 D. Further, use of selective epitaxy process for formation of the source region  3 S and the drain region  3 D can minimize the junction gradient at the p-n junctions, and provide a sharp transition in the dopant concentration across each p-n junction. The enhancement of the junction gradient (in terms of the dopant concentration change) can provide well-defined transistor characteristics such as the threshold voltage. 
     While the disclosure has been described in terms of specific embodiments, it is evident in view of the foregoing description that numerous alternatives, modifications and variations will be apparent to those skilled in the art. Each of the embodiments described herein can be implemented individually or in combination with any other embodiment unless expressly stated otherwise or clearly incompatible. Accordingly, the disclosure is intended to encompass all such alternatives, modifications and variations which fall within the scope and spirit of the disclosure and the following claims.