Patent Publication Number: US-7901951-B2

Title: Thin film transistor array substrate and method for fabricating same

Description:
FIELD OF THE INVENTION 
     The present invention relates to thin film transistor (TFT) array substrates used in liquid crystal displays (LCDs) and methods for fabricating these substrates, and more particularly to a TFT array substrate having at least one repair line for restoring a data line&#39;s broken gap, and a method for fabricating the TFT array substrate. 
     BACKGROUND 
     A typical liquid crystal display (LCD) is capable of displaying a clear and sharp image through millions of pixels that make up the complete image. Thus, the liquid crystal display has been applied to various electronic equipments in which messages or pictures need to be displayed, such as mobile phones and notebook computers. A liquid crystal panel is a major component of the LCD, and generally includes a TFT array substrate, a color filter substrate opposite to the TFT array substrate, and a liquid crystal layer sandwiched between the two substrates. 
     Referring to  FIG. 17 , part of a typical TFT array substrate  1  is shown. The TFT array substrate  1  includes a plurality of gate lines  13 , a plurality of common lines  14 , and a plurality of data lines  17 . The gate lines  13  are parallel to and spaced from each other. The data lines  17  are parallel to and spaced from each other, and are substantially perpendicular to the gate lines  13 . Two adjacent gate lines  13  and two adjacent data lines  17  cooperatively define a pixel region  100 . The common lines  14  are parallel to the gate lines  13 , and each of the common lines  14  crosses a row of pixel regions  100 . 
     In each pixel region  100 , a TFT  18 , a pixel electrode  190 , and a common electrode  120  are provided. The TFT  18  is arranged in the vicinity of a respective point of intersection of the gate lines  13  and the data lines  17 . The TFT  180  includes a gate electrode  181 , a source electrode  182 , and a drain electrode  183 . 
     The pixel and common electrodes  190 ,  120  are laminated and insulated in the pixel region  100 . The pixel and common electrodes  190 ,  120  are made of transparent conductive materials such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). The common electrode  120  is electrically connected to the common line  14  in order to obtain common voltage signals. 
     Referring to  FIG. 18 , this is an enlarged, cross-sectional view taken along line XVIII-XVIII of  FIG. 1 . The TFT array substrate  10  further includes a substrate  11 , a gate insulating layer  15 , a semiconductor layer  107 , and a passivation material layer  16 . The gate line  13 , the common line  14 , the gate electrode  181 , and the common electrode  120  are arranged on the substrate  11 . The gate insulating layer  15  covers the common electrode  120 , the gate line  13 , the gate electrode  181 , and the common line  14 . The semiconductor layer  107  is formed on the gate insulating layer  15 . The source electrode  182  and the drain electrode  183  are formed on the insulating layer  15  and the semiconductor layer  107  corresponding to the gate electrode  181 . The passivation material layer  16  is formed on the gate insulating layer  15 , the drain electrode  183  and the source electrode  182 . The pixel electrode  190  is formed on the passivation material layer  16 , and is electrically connected to the drain electrode  183  via the through hole  184  formed in the passivation material layer  16 . 
     However, the data line  17  is prone to be damaged when the TFT array substrate  1  is being handled, transported, or cleaned. A broken gap  170  may occur when the corresponding data line  17  is damaged. Thus, the data line  17  is broken and unable to transfer data signals. This results in an impaired image in the pixel regions  100  corresponding to the broken data line  17 . 
     What is needed, therefore, is a method for fabricating a TFT array substrate that can overcome the above-described deficiency. What is also needed is a TFT array substrate fabricated by the above method. 
     SUMMARY 
     In one preferred embodiment, a method for fabricating a thin film transistor (TFT) array substrate includes: providing an insulating substrate; forming a common electrode on the insulating substrate and a repair structure on the insulating substrate by a first photolithograph process, the repair structure having a plurality of gaps; forming a common line, a gate line, and a gate electrode on the insulating substrate by a second photolithograph process, the gate electrode being connected to the gate line; forming a gate insulating layer and a semiconductor layer on the gate insulating layer by a third photolithograph process, the semiconductor layer being above the gate electrode; and forming a data line and source/drain electrodes on the gate insulating layer by a fourth photolithograph process, the data line being above the repair structure and intersecting with the gate line and the common line, wherein the gaps of the repair structure each corresponds to an overlap with the gate line and the common line. 
     An exemplary TFT array substrate includes: an insulating substrate; a gate line and a repair structure arranged on the insulating substrate, the repair structure having a gap; a gate insulating layer covering the gate line and the insulating structure; a data line arranged on the gate insulating layer corresponding to the repair structure, which is insulated from the gate line and intersects with the gate line. The gap of the repair structure is located at where the repair structure overlapping to the gate line. 
     Other novel features and advantages will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, all the views are schematic. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is an abbreviated, top view of part of a TFT array substrate according to an exemplary embodiment of the present invention. 
         FIG. 2  is an enlarged, cross-sectional view taken along line II-II of  FIG. 1 . 
         FIG. 3  is a flowchart summarizing an exemplary method for fabricating the TFT array substrate of  FIG. 1 . 
         FIGS. 4 to 16  are schematic, side cross-sectional views relating to steps of the method of  FIG. 3 . 
         FIG. 17  is an abbreviated, top view of part of a conventional TFT array substrate. 
         FIG. 18  is an enlarged, cross-sectional view taken along line XVIII-XVIII of  FIG. 17 . 
     
    
    
     DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS 
     Referring to  FIG. 1  and  FIG. 2 ,  FIG. 1  is an abbreviated, top view of part of a TFT array substrate according to an exemplary embodiment of the present invention.  FIG. 2  is an enlarged, cross-sectional view taken along line II-II of  FIG. 1 . The TFT array substrate  2  includes a plurality of gate lines  23 , a plurality of common lines  24 , a plurality of data lines  27 , and a plurality of repair lines  272 . The data lines  27  are arranged parallel to each other, and each data line  27  extends along a longitudinal direction. The gate lines  23  are arranged parallel to each other, and each gate line  23  extends along a horizontal direction. Thus, the crossing data lines  27  and gate lines  23  cooperatively define a multiplicity of pixel regions  200 . The common lines  24  are parallel to the gate lines  23 , and each of the common lines  24  crosses a row of pixel regions  200 . Each repair line  272  is disposed corresponding to one of the data lines  27 , and is parallel to the corresponding data line  27 . The repair line  272  defines a plurality of gaps  274  each corresponding to an overlap with the gate line  23  and the common line  24 . 
     In each pixel region  200 , a TFT  28  is provided in the vicinity of a respective point of intersection of the gate lines  23  and the data lines  27 . A comb-shaped pixel electrode  290  and a plate-shaped common electrode  220  are laminated in the pixel region. The TFT  28  has a gate electrode  281  electrically connected with the gate line  23 , a source electrode  282  electrically connected with the data line  27 , and a drain electrode  283  connected to the pixel electrode  290  via a through hole  284 . The common line  24  is disposed between the pixel electrode  290  and a neighboring gate line  23 , and extends along a direction parallel to the gate line  23 . The common line  24  is connected to the common electrode  220  in order to provide common voltage signals thereto. 
     The TFT array substrate  20  further includes an insulating substrate  201 , a gate insulating layer  204 , a semiconductor layer  207  and a passivation material layer  25 . The gate line  23 , the common line  24 , the repair line  272 , the gate electrode  281 , and the common electrode  220  are formed on the substrate  201 . The gate insulating layer  204  is formed on the repair line  272 , the gate electrode  281 , the common electrode  220 , the gate line  23 , and the common line  24 . The semiconductor layer  207  is formed on the gate insulating layer  204  above the gate electrode  281 . The source electrode  282  and the drain electrode  283  are formed on two ends of the semiconductor layer  207  symmetrically. The data line  27  is formed on the gate insulating layer  204  correspondingly above the repair line  272 , and is electrically connected to the source electrode  282 . The passivation material layer  25  is formed on the data line  27 , the TFT  28  and the gate insulating layer  204 . The through hole  284  is formed in the passivation material layer  25 . The pixel electrode  290  is formed on the passivation material layer  25  and is electrically connected to the drain electrode  283  via the through hole  284 . 
     Referring to  FIG. 3 , this is a flowchart summarizing an exemplary method for fabricating the TFT array substrate  2 . For simplicity, the flowchart and the following description are couched in terms that relate to the part of the TFT array substrate  2  shown in  FIG. 1 . The method includes: step S 21 , forming a first transparent conductive layer; step S 22 , forming a common electrode and a repair line; step S 23 , forming a conductive metal layer; step S 24 , forming a common line, a gate line, and a gate electrode; step S 25 , forming a gate insulating layer, an amorphous silicon (a-Si) and a doped a-Si layer; step S 26 , forming a semiconductor layer; step S 27 , forming a source/drain metal layer; step S 28 , forming a data line and source/drain electrodes; step S 29 , forming a passivation material layer; step S 210 , forming a through hole; step S 211 , forming a second transparent conductive layer; and step S 212 , forming a pixel electrode. 
     In step S 21 , referring to  FIG. 4 , an insulating substrate  201  is provided. The substrate  201  may be made from glass or quartz. A first transparent conductive layer  202  and a first photo-resist layer  90  are sequentially formed on the substrate  201 . The transparent conductive layer  202  can be made from indium-tin-oxide (ITO) or indium-zinc-oxide (IZO). A first photo-mask  91  is also provided above the first photo-resist layer  90 . 
     In step S 22 , referring to  FIG. 5  to  FIG. 6 , the first photo-resist layer  90  is exposed by the first photo-mask  91 , and then is developed, thereby forming a first photo-resist pattern  92 . The transparent conductive layer  202  is etched by a wet etching method, thereby forming a pattern of the common electrode  220  and a pattern of the repair line  272 , which correspond to the first photo-resist pattern  92 . In this step, the gaps  274  (as shown in  FIG. 1 ) are also formed. The first photo-resist pattern  92  is then removed by an acetone solution. 
     In step S 23 , referring to  FIG. 7 , a conductive metal layer  203  and a second photo-resist layer (not shown) are sequentially formed on the substrate  201 , the common electrode  220 , and the repair line  272 . The conductive metal layer  203  may be made from material including any one or more items selected from the group consisting of aluminum (Al), molybdenum (Mo), copper (Cu), chromium (Cr), and tantalum (Ta). 
     In step S 24 , referring to  FIG. 8 , the second photo-resist layer is exposed by a second photo-mask (not shown), and then is developed, thereby forming a second photo-resist pattern (not shown). The conductive metal layer  203  is etched, thereby forming a pattern of the gate electrode  281 , the gate line  23 , and the common line  24 , which correspond to the second photo-resist pattern. The gate electrode  281  and the gate line  23  are incorporated. The second photo-resist pattern is then removed by an acetone solution. 
     In step S 25 , referring to  FIG. 9 , a gate insulating layer  204  is formed on the substrate  201  having the gate electrode  281 , the common electrode  220 , the gate line  23 , and the common line  24  by a chemical vapor deposition (CVD) process. In this process, silane (SiH4) reacts with alkaline air (NH4+) to obtain silicon nitride (SiNx), a material of the gate insulating layer  204 . An a-Si layer  205  is deposited on the gate insulating layer  204  by a CVD process. A top layer of the a-Si layer  205  is doped, thereby forming a doped a-Si layer  206 . Then a third photo-resist layer (not shown) is formed on the doped a-Si layer  206 . 
     In step S 26 , referring to  FIG. 10 , an ultraviolet (UV) light source and a third photo-mask (not shown) are used to expose the third photo-resist layer. Then the exposed third photo-resist layer is developed, thereby forming a third photo-resist pattern. Using the third photo-resist pattern as a mask, portions of the doped a-Si layer  206  and the a-Si layer  205  which are not covered by the third photo-resist pattern are etched away, thereby forming an a-Si pattern (not labeled) and a doped a-Si pattern (not labeled). The a-Si pattern and the doped a-Si pattern cooperatively define the semiconductor layer  207 . The third photo-resist pattern is then removed by an acetone solution. 
     In step S 27 , referring to  FIG. 11 , a source/drain metal layer  209  is then deposited on the semiconductor layer  207  and the gate insulating layer  204 . The source/drain metal layer  209  may be made from material including any one or more items selected from the group consisting of aluminum, aluminum alloy, molybdenum, tantalum, and molybdenum-tungsten alloy. Then a fourth photo-resist layer (not shown) is formed on the source/drain metal layer  209 . 
     In step S 28 , referring to  FIG. 12 , the fourth photo-resist layer is exposed by a fourth photo-mask (not shown), and then is developed, thereby forming a fourth photo-resist pattern. The source/drain metal layer  209  is etched, thereby forming a pattern of the source/drain electrodes  282 ,  283  and a data line  27 . The source/drain electrodes  282 ,  283  are formed on two ends of the semiconductor layer  207  symmetrically. The data line  27  is formed essentially above the repair line  272  on the gate insulting layer  204 . A width of the data line  27  is generally equal to a width of the repair line  272 . Using the source/drain electrodes  282 ,  283  as a mask, portions of the doped a-Si pattern  206  which are not covered by the source/drain electrodes  282 ,  283  are etched away, thereby departing the doped a-Si pattern  206  into two parts. The fourth photo-resist pattern is then removed. 
     In step S 29 , referring to  FIG. 13 , the passivation material layer  25  and a fifth photo-resist layer (not shown) are sequentially formed on the source/drain electrodes  282 ,  283 , the data line  27  and the gate insulating layer  204 . The passivation material layer  25  is made from silicon nitride (SiNx) or silicon oxide (SiOx). 
     In step S 210 , referring to  FIG. 14 , the fifth photo-resist layer is exposed by a fifth photo-mask (not shown), and then is developed, thereby forming a fifth photo-resist pattern. A portion of the passivation material layer  25  is etched, thereby forming the through hole  284  in the passivation material layer  25 . The through hole  284  is above the drain electrode  283 , in order to expose a portion of the drain electrode  283 . The fifth photo-resist pattern is then removed. 
     In step S 211 , referring to  FIG. 15 , a transparent conductive layer  26  and a sixth photo-resist layer (not shown) are sequentially formed on the passivation material layer  25 . The second transparent conductive layer  26  fills the through hole  284 . 
     In step S 212 , referring to  FIG. 16 , the sixth photo-resist layer is exposed by a sixth photo-mask (not shown), and then is developed, thereby forming a sixth photo-resist pattern. A portion of the second transparent conductive layer  26  is etched, thereby forming a pattern of the pixel electrode  290 , which corresponds to the sixth photo-resist pattern. The pixel electrode  290  is electrically connected the drain electrode  283  via the though hole  284 . The sixth photo-resist pattern is then removed. 
     In the above-described exemplary method for fabricating the TFT array substrate  2 , the repair line  272  and the common electrode  220  are formed in the same photolithograph process. Therefore, an additional photolithography process is not needed, and a production efficiency of the method for fabricating the TFT array substrate  2  is increased accordingly. 
     The repair line  272  is positioned between the insulating substrate  201  and the gate insulating layer  204 . If the data line  27  has a broken gap, a portion of the gate insulating layer  204  corresponding to the broken gap can be removed by a laser process. Because the repair line  272  is parallel to the gate line  27  and has the gaps  274  located at positions overlapping the gate lines  23  and the common lines  24 , the repair line  272  can be electrically connected to the data line  27  at the broken gap by a welding process. The gate line  23  and the common line  24  are not interfered by the repair line  272 . In this case, the broken gap of the data line  27  is filled and the data line  27  is repaired. The reliability of the TFT array substrate  2  is increased. 
     In an alternative embodiment, a width of the repair line  272  can be just one half of a width of the corresponding data line  27 . In further alternative embodiment, the repair line  272  can be formed in a same photolithograph process with the gate line  23 , the common line  24 , and the gate electrode  281 . 
     It is to be understood, however, that even though numerous characteristics and advantages of the present embodiments have been set out in the foregoing description, together with details of the structures and functions of the embodiments, the disclosure is illustrative only, and changes may be made in detail, especially in matters of shape, size, and arrangement of parts within the principles of the invention to the full extent indicated by the broad general meaning of the terms in which the appended claims are expressed.