Patent Publication Number: US-2023162773-A1

Title: Memory Device with Spin-Harvesting Structure

Description:
BACKGROUND 
     The exemplary embodiments described herein relate generally to memory device design, more specifically, to a memory device with a spin-harvesting structure. 
     BRIEF SUMMARY 
     In one aspect, a memory device includes a first electrical terminal and a second electrical terminal; a magnetic tunnel junction coupled to the second electrical terminal; wherein the magnetic tunnel junction comprises a magnetic free layer, and the magnetic tunnel junction is configured to be displaced by a plurality of distances from a center position of the memory device; a nonmagnetic metallic spin harvesting conductor coupled to the magnetic tunnel junction; wherein the nonmagnetic metallic spin harvesting conductor has a lateral dimension that is larger than that of the magnetic tunnel junction; an electrically insulating spin conductor coupled to the nonmagnetic metallic spin harvesting conductor; wherein the nonmagnetic metallic spin harvesting conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the nonmagnetic metallic spin harvesting conductor; and a spin orbit conduction channel coupled to the electrically insulating spin conductor and to the first electrical terminal; wherein the spin orbit conduction channel generates the spin current from a laterally asymmetric charge current flow; wherein the spin current is conducted by the electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor and further delivered to the magnetic free layer of the magnetic tunnel junction. 
     In another aspect, a memory device includes two terminals comprising a first electrical terminal and a second electrical terminal; a magnetic tunnel junction comprising a free layer coupled to the second electrical terminal; a spin and charge conductor whose lateral dimension is larger than that of the magnetic tunnel junction; an electrically insulating spin conductor coupled to the spin and charge conductor; wherein the spin and charge conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the spin and charge conductor; and a spin orbit channel coupled to the electrically insulating spin conductor and to the first electrical terminal; wherein the electrically insulating spin conductor assists the memory device with asymmetric charge current flow; wherein the asymmetric charge current flow is enhanced by the spin and charge conductor. 
     In another aspect, a method to form a memory device includes coupling a second electrical terminal to a magnetic tunnel junction; wherein the magnetic tunnel junction comprises a magnetic free layer, and the magnetic tunnel junction is configured to be displaced by a plurality of distances from a center position of the memory device; coupling a nonmagnetic metallic spin harvesting conductor to the magnetic tunnel junction; wherein the nonmagnetic metallic spin harvesting conductor has a lateral dimension that is larger than that of the magnetic tunnel junction; coupling an electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor; wherein the nonmagnetic metallic spin harvesting conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the nonmagnetic metallic spin harvesting conductor; and coupling a spin orbit conduction channel to the electrically insulating spin conductor and to a first electrical terminal; wherein the spin orbit conduction channel generates the spin current from a laterally asymmetric charge current flow; wherein the spin current is conducted by the electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor and further delivered to the magnetic free layer of the magnetic tunnel junction. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS 
       The foregoing and other aspects of exemplary embodiments are made more evident in the following Detailed Description, when read in conjunction with the attached Drawing Figures, wherein: 
         FIG.  1    is a cross-sectional view of a spin-harvesting structure, based on the examples described herein; 
         FIG.  2    is another cross-sectional view of the spin-harvesting structure, showing a charge current conducted by the spin-harvesting structure; 
         FIG.  3    is a top view of an example spin-harvesting structure; 
         FIG.  4 A  is a graph showing spin current harvesting performance of the spin-harvesting structure for different nonmagnetic metallic (NM) conductor layer thicknesses, for a 30 nm magnetic tunnel junction (MTJ); 
         FIG.  4 B  is a graph showing spin current harvesting performance of the spin-harvesting structure for different NM conductor layer thicknesses, for a 50 nm MTJ; 
         FIG.  4 C  is a graph showing spin current harvesting performance of the spin-harvesting structure for different NM conductor layer thicknesses, for a 100 nm MTJ; 
         FIG.  5 A  is a graph showing spin current harvesting performance of the spin-harvesting structure for different NM conductor layer thicknesses and across varying positions (δx) of the free layer, for a 250 nm spin-diffusion length; 
         FIG.  5 B  is a graph showing spin current harvesting performance of the spin-harvesting structure for different NM conductor layer thicknesses and across varying positions (δx) of the free layer, for a 100 nm spin-diffusion length; 
         FIG.  5 C  is a graph showing spin current harvesting performance of the spin-harvesting structure for different NM conductor layer thicknesses and across varying positions (δx) of the free layer, for a 50 nm spin-diffusion length; and 
         FIG.  6    is a logic flow diagram that illustrates the operation of an exemplary method, in accordance with an exemplary embodiment of the methods for forming the structures described herein. 
     
    
    
     DETAILED DESCRIPTION 
     The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any embodiment described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments. All of the embodiments described in this Detailed Description are exemplary embodiments provided to enable persons skilled in the art to make or use the invention and not to limit the scope of the invention which is defined by the claims. 
     Described herein is a spin-harvesting structure for a spin-orbit torque (SOT) assisted switch. Further described herein is a method to make use of an SOT-assisted magnetic tunnel junction (MTJ) based spin-transfer-torque (STT) memory element to improve write-characteristics and reduce write current. The method represents an improvement over using an asymmetric electrode to extract a charge-current from an MTJ element to generate an SOT-assisted spin-current to speed up switching and reduce switching current. A drawback of using an asymmetric electrode to extract a charge-current from an MTJ element to generate an SOT-assisted spin-current to speed up switching and reduce switching current, is the lack of ability to separately optimize spin and charge current flow, resulting in reduced SOT assistance. 
     Accordingly, the method described herein resolves a drawback of the asymmetric electrode approach by using a structure for “spin-harvesting” that both increases the asymmetric charge-current flow&#39;s spin-current generation, and the effective collection of spin-current thus generated, so as to achieve the goal of better SOT assistance to MTJ memory switching characteristics. 
     The methods and structures described herein provide a significant (4× estimated) increase in spin-current magnitude from that of the MTJ&#39;s spin-filtering current. In addition, the herein described structure leverages materials and device-physics properties. 
       FIG.  1    shows the spin-harvesting structure  50  for an SOT-assisted switch, as described herein. The structure  50  includes a spin-orbit-conduction channel  100 , otherwise known as a spin-orbit torque (SOT) conductor  100 . The structure  50  further includes a first electrical terminal  110  for a two-terminal memory cell. The structure  50  further includes an electrically insulating or leaky insulating spin-conductor (ISC)  200 . The spin-conductor  200  may for example comprise nickel oxide (NiO) or iron oxide (Fe 3 O 4 ), or other material that conducts charge current at a lower level relative to materials that comprise the spin conductor  300 , but has high conductivity for spin current. The structure  50  further includes such a nonmagnetic metallic (NM) spin conductor  300  functioning as a spin-harvesting conductor. The NM spin conductor  300  may comprise a material such as copper (Cu), silver (Ag), gold (Au), and/or silver-tin alloy (AgSn), and other alloys known to have long spin-diffusion length and high spin conductance. 
     As further shown in  FIG.  1   , the structure  50  includes a magnetic tunnel junction (MTJ) memory element  400 . A magnetic free-layer (FL)  401 , a tunnel barrier (TB)  402  and a reference layer (RL)  403  form the MTJ memory element  400 . Also shown is a second electrical terminal  410  for the two-terminal memory cell  50 , the second electrical terminal  410  being coupled to the MTJ  400  via the RL  403 . The MTJ-based memory element  400  can be displaced from the center position  415  of the structure  50  by a ox amount ( 420 ) to maximize spin-current collection from the NM spin conductor  300 . In an embodiment shown in  FIG.  1   , the structure  50  is fabricated such that the first electrical terminal ( 110 ) is defined by a vertical VIA metal stud through an insulating layer for contacting the edge of SOT channel ( 100 ), and at a position where ( 110 ) is illustrated. Similarly, a top metallic contact can be made to the top of the metal stud forming the MTJ&#39;s second terminal ( 410 ), by chemical-mechanical-polish opening of such a metal stud from its conforming deposited insulators, for example, for contacting circuits lithographically defined above the MTJ layer. 
     The thickness of the free layer  401  is represented by the variable t FL  ( 405 ), the thickness of the NM spin-conductor  300  is represented by the variable t NM  ( 305 ), the thickness of the leaky insulating spin-conductor  200  is represented by the variable t ISC  ( 205 ), and the thickness of the spin-orbit-conduction channel  100  is represented by the variable t SOT  ( 105 ). The spin-orbit-conduction channel  100  generates a spin-orbit torque (SOT). The device structure  50  is hereafter assumed to be situated in an orthonormal coordinate system having the three base unit vectors as e x  ( 20 ), e y  ( 30 ), and e z  ( 40 ), as illustrated by ( 10 ). 
     With reference to  FIG.  2   , the electrically leaky spin-conductor  200  conducts spin-current from the SOT channel  100  to spin harvesting metal (i.e. spin-harvesting conductor  300 ). By making the spin-conductor  200  a “leaky” charge current conductor (as opposed to being perfectly insulating) through materials engineering, the leaky spin-conductor  200  can re-distribute the charge current from the MTJ memory element  400  to the SOT channel conductor  100 , creating a laterally asymmetric current flow  500  increasing in intensity in the −x direction. The increasing intensity of the laterally asymmetric current flow  500  is shown by the arrow in  FIG.  2    becoming thicker from right to left, symbolizing larger net current at positions closer to the first electrical terminal ( 110 ). This charge current  500  generates a corresponding spin-current at the interface  120  between the spin-orbit-conduction channel  100  and the leaky spin-conductor  200  (e.g. the ( 100 )-( 200 ) interface), which is then conducted through the spin-conductor  200  into the NM spin conductor  300  and subsequently to the FL  401  of the MTJ memory element  400 . 
     Accordingly,  FIG.  2    illustrates the process of the SOT conductor channel  100  collecting charge current from the insulating spin conductor (ISC)  200 , forming a lateral current flow whose intensity increases towards terminal  110 . This physical process can be modeled using a numerical simulation. 
     The charge-current  510  arriving at the interface  120  is shown as having components  510 - 1 ,  510 - 2 , up to  510 -N, where N is an integer. These arrows ( 510 - 1 ,  510 - 2 , up to  510 -N) are to illustrate the substantially uniform current density for charge-current to flow across the interface  120 . This charge current  510  is accumulated along the SOT channel ( 100 ), forming the charge current flow ( 500 ) that increases in intensity towards the terminal ( 110 ). The charge-current ( 510 ) is the same current as the charge current flow ( 500 ), and therefore as shown in  FIG.  2   , the arrows representing both the charge-current  510  and the charge current flow ( 500 ) are presented with the same cross-hatching (this could also be done with representing the charge-current ( 510 ) and the current flow ( 500 ) by the same color). The spin-current travels upwards from ( 100 ) to ( 200 ) to ( 300 ). The local spin-current density at the interfaces ( 120 ) and ( 130 ) are substantially proportional to the lateral charge current density inside of SOT channel ( 100 ). 
     The NM element  300  is called a spin-harvesting conductor because the NM element  300  collects spin-current from the entire interface  130  the NM element  300  shares with the leaky spin-conductor  200 , and conducts the spin-current thus collected to the FL  401 , thus “harvesting” spin-current from an area much larger than that of the FL  401  alone. 
     The structure  50  is designed with the expectation of a large lateral current flow  500  that is left-right asymmetric. The spin harvesting layer  300  would be able to pick up more SOT spin current since the spin harvesting layer  300  occupies the entire length of the structure  50 , larger than the footprint of the FL  401 . This design improves upon the more conventional SOT-assisted memory cell where the FL of the MTJ  400  resides directly on the SOT channel ( 100 ), or on top of spin-conductor ( 200 ), gaining an area ratio approaching 
     
       
         
           
             
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     in this case, or limited by the “spin-diffusion length” λ sd  in the NM element  300 , a spin-memory length, beyond which the harvesting action in the NM element  300  is progressively less effective. A transport-equation based numerical study quantifies these statements, as shown in  FIG.  4 A ,  FIG.  4 B ,  FIG.  4 C ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C . 
     As shown in  FIG.  2    and similarly in  FIG.  1   , the SOT conductor  100  is connected to the ISC  200 , and the ISC  200  is connected to the NM conductor  300 . That the elements are connected to each other such as at the ISC/SOT interface  120  and the NM/ISC interface  130  and so forth may in some examples mean that the elements ( 100 ,  200 ,  300 ) or their respective interfaces ( 120 ,  130 ) can contain a minute doping material (e.g. at the interfaces  120 ,  130 ) for promoting material properties, electrical properties, and/or spin properties. In some examples, the SOT conductor  100  is directly connected to the ISC  200 . In some examples, the ISC  200  is directly connected to the NM conductor  300 . 
       FIG.  3    is a top view of a simplified version of the device structure  50 , including only the FL (which FL may be thought of as the MTJ pillar  400  shown in  FIG.  1    and  FIG.  2   ), with dimensions l FL  and w FL    170  whereas the spin-harvesting NM layer  300  has the dimension of L  140  and w c    150 . The numbers are for illustrations used in the numerical model. 
     With reference to  FIG.  3    and as indicated, the area ratio gained is 
     
       
         
           
             
               
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     where L is item  140  (the length of the structure  50  as well as the length of each of conductors  200  and  300 ), w c  is item  150  (or the width of the structure  50 , the width of conductor  200 , and the width of conductor  300 ), l FL  is the length  160  of FL  401 , and W FL  is the width  170  of FL  401 . 
     Accordingly, described herein (including in  FIG.  1   ,  FIG.  2   ,  FIG.  3   ,  FIG.  4   ,  FIG.  5   , and throughout herein), is a two-terminal magnetic tunnel junction-based memory element  50 , assisted by an additional spin-orbit channel  100  with asymmetric charge-current flow, where the charge-current flow asymmetry is enhanced by a spin and charge conductor  300  (such as Ag, Au, Cu, V, etc.), whose lateral dimension is larger than that of a free-layer ferromagnetic memory element  401  of the magnetic tunnel junction  400 . 
     The spin-orbit channel  100  is connected to the spin and charge conductor  300 , either directly, or through a spin-conducting poor electrical conductor  200  (such as NiO, YIG, TIG, and other relatively poorer electrical conductors or insulators that conduct spin-current). The electrical conductance of the spin-conducting poor electrical conductor  200  can be tuned by materials optimization to allow a slight reasonable amount of charge current conduction, so the charge current through the free-layer  401  entering vertically from the free-layer FM  401  will laterally spread, and result in an asymmetric charge current flow  500  in the spin-orbit conduction channel  100 , to be drawn away towards one side at terminal ( 110 ). 
     Of the combination of the charge and spin conductor  300 , spin-conductor  200 , and spin-orbit channel  100 , the net amount of spin-current coupled into the free layer  401  is augmented compared to having the free-layer metal  401  residing directly on the spin-orbit channel  100 . A magnetic tunnel barrier  402  and reference layer  403  may be built on top of the magnetic free-layer  401  to form the said magnetic tunnel junction  400 . 
     Spin-conductance simulation bears out several qualitative arguments. The design begins by starting with the simplest geometry with δx=0. The positioning of the FL  401  can be optimized subsequently. 
       FIG.  4 A ,  FIG.  4 B ,  FIG.  4 C ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C  show the spin current harvesting performance, where the spin current harvesting performance is measured by the ratio of the harvested spin current (I sHarvested ) against the spin-current generated from the MTJ  400  (I sMTJ ) with an assumed MR ratio of 120%, and assuming a symmetric tunnel interface across the tunnel barrier  402 . 
     In particular, the definitions for the quantities plotted in  FIG.  4 A ,  FIG.  4 B ,  FIG.  4 C ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C  are as follows. The y-axis on the plots shown in  FIG.  4 A ,  FIG.  4 B ,  FIG.  4 C ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C  is I sHarvested /I sMTJ . The quantity I sHarvested  is the spin-current harvested from the SOT channel  100  current. The quantity I sMTJ  is the spin-current from the MTJ&#39;s RL  403  spin-filtering. The quantity I sMTJ =I cgη , where I cg  is the charge current between terminal  110  and terminal  410 , η˜√{square root over (m r (m r +2))}/2(m r 1) for symmetric MTJ electrodes across the tunnel barrier  402 , and m r  is the tunnel magnetoresistance of the MTJ  400 . 
     In  FIG.  4 A ,  FIG.  4 B ,  FIG.  4 C ,  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C , for clarity L is L (item  140 , or the length of the structure  50  as well as the length of each of conductors  200  and  300 ), wC is w c  (item  150 , or the width of the structure  50 , the width of conductor  200 , and the width of conductor  300 ), l FL  is 4, (the length  160  of FL  401 ), wFL is w FL  (the width  170  of FL  401 ), and MR is m r  (the tunnel magnetoresistance of the MTJ  400 ). The abbreviation (n.u.) stands for no units since the plotted quantities are ratios. 
     The results in  FIG.  4 A ,  FIG.  4 B , and  FIG.  4 C  show the dependence on λ sd  for different t NM , where λ sd  is the spin-diffusion length. In each of  FIG.  4 A ,  FIG.  4 B , and  FIG.  4 C , plot  450  corresponds to t NM =10 nm, plot  460  corresponds to t NM =25 nm, plot  470  corresponds to t NM =50 nm, plot  480  corresponds to t NM =100 nm, and plot  490  corresponds to t NM =200 nm. For small (30 nm) FLs  401  (e.g. MTJs  400 ), the gain is sizable (4×) even for a small SOT coefficient of Θ SOT =0.05, and an NiO transmissivity ratio of θ i =0.02, if the spin-diffusion length λ sd &gt;100 nm—a value that is realistic for good metal such as Cu and Ag. 
     
       
         
           
             
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     is assumed to be the tunnel-filtered spin-current corresponding to MR=120% of symmetric electrodes. 
     Regarding the role of δx  420 , the spin-harvest enhancement is augmented on the side of δx for the FL  401  to be closer to the charge current  500  downstream direction, i.e. closer to terminal  110 . The effect is more significant for shorter λ sd  and/or thinner NM layer  300  thickness t NM    305 . The exact position δx for best spin-current harvesting can be optimized for a given materials/device design. 
     In each of  FIG.  5 A ,  FIG.  5 B , and  FIG.  5 C , plot  550  corresponds to t NM =10 nm, plot  560  corresponds to t NM =50 nm, plot  570  corresponds to t NM =100 nm, and plot  580  corresponds to t NM =200 nm. 
       FIG.  6    is a logic flow diagram that illustrates the operation of an exemplary method  600 , based on the embodiments described herein. At  601 , the method includes coupling a second electrical terminal to a magnetic tunnel junction. At  602 , the method includes wherein the magnetic tunnel junction comprises a magnetic free layer, and the magnetic tunnel junction is configured to be displaced by a plurality of distances from a center position of the memory device. At  603 , the method includes coupling a nonmagnetic metallic spin harvesting conductor to the magnetic tunnel junction. At  604 , the method includes wherein the nonmagnetic metallic spin harvesting conductor has a lateral dimension that is larger than that of the magnetic tunnel junction. At  605 , the method includes coupling an electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor. At  606 , the method includes wherein the nonmagnetic metallic spin harvesting conductor collects spin current from the electrically insulating spin conductor. At  607 , the method includes wherein the electrically insulating spin conductor has relatively less electrical conductivity than the nonmagnetic metallic spin harvesting conductor. At  608 , the method includes coupling a spin orbit conduction channel to the electrically insulating spin conductor and to a first electrical terminal. At  609 , the method includes wherein the spin orbit conduction channel generates the spin current from a laterally asymmetric charge current flow. At  610 , the method includes wherein the spin current is conducted by the electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor and further delivered to the magnetic free layer of the magnetic tunnel junction. 
     The various blocks of method  600  shown in  FIG.  6    may be viewed as method steps, and/or as operations that result from operation of computer program code, and/or as a plurality of coupled logic circuit elements constructed to carry out the associated function(s). Method  600  may be a lithographic workflow. 
     Referring now to all the Figures, in one exemplary embodiment, a memory device includes a first electrical terminal and a second electrical terminal; a magnetic tunnel junction coupled to the second electrical terminal; wherein the magnetic tunnel junction comprises a magnetic free layer, and the magnetic tunnel junction is configured to be displaced by a plurality of distances from a center position of the memory device; a nonmagnetic metallic spin harvesting conductor coupled to the magnetic tunnel junction; wherein the nonmagnetic metallic spin harvesting conductor has a lateral dimension that is larger than that of the magnetic tunnel junction; an electrically insulating spin conductor coupled to the nonmagnetic metallic spin harvesting conductor; wherein the nonmagnetic metallic spin harvesting conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the nonmagnetic metallic spin harvesting conductor; and a spin orbit conduction channel coupled to the electrically insulating spin conductor and to the first electrical terminal; wherein the spin orbit conduction channel generates the spin current from a laterally asymmetric charge current flow; wherein the spin current is conducted by the electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor and further delivered to the magnetic free layer of the magnetic tunnel junction. 
     The memory device may further include wherein the spin orbit conduction channel is connected to the electrically insulating spin conductor with an interface, the interface may be direct or may contain a minute doping material for promoting at least one of a material property, an electrical property, or a spin property. The memory device may further include wherein the electrically insulating spin conductor is connected to the nonmagnetic metallic spin harvesting conductor with an interface, the interface comprising a minute doping material for promoting at least one of a material property, an electrical property, or a spin property. The memory device may further include wherein the magnetic free layer permits the magnetic tunnel junction to be displaced by the plurality of distances from the center position of the memory device. The memory device may further include wherein the electrically insulating spin conductor redistributes a charge current from the magnetic tunnel junction to the spin orbit conduction channel to create the laterally asymmetric charge current flow, the laterally asymmetric charge current flow increasing in intensity towards the first electrical terminal. The memory device may further include wherein the electrically insulating spin conductor is configured such that its electrical conductance can be tuned so that a charge current flow entering vertically from the magnetic free layer into the electrically insulating spin conductor results in the laterally asymmetric charge current flow towards the first electrical terminal. The memory device may further include wherein a net amount of spin current coupled into the magnetic free layer by a combination of the nonmagnetic metallic spin harvesting conductor, the electrically insulating spin conductor, and the spin orbit conduction channel is augmented compared to having the magnetic free layer residing directly on the spin orbit conduction channel. The memory device may further include wherein the magnetic tunnel junction further comprises a tunnel barrier on the magnetic free layer, and a reference layer on the tunnel barrier, the reference layer being configured to couple the second electrical terminal to the magnetic tunnel junction. 
     In another exemplary embodiment, a memory device includes two terminals comprising a first electrical terminal and a second electrical terminal; a magnetic tunnel junction comprising a free layer coupled to the second electrical terminal; a spin and charge conductor whose lateral dimension is larger than that of the magnetic tunnel junction; an electrically insulating spin conductor coupled to the spin and charge conductor; wherein the spin and charge conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the spin and charge conductor; and a spin orbit channel coupled to the electrically insulating spin conductor and to the first electrical terminal; wherein the electrically insulating spin conductor assists the memory device with asymmetric charge current flow; wherein the asymmetric charge current flow is enhanced by the spin and charge conductor. 
     The memory device may further include wherein the spin orbit channel is connected to the electrically insulating spin conductor with an interface, the interface may be direct or may contain a minute doping material for promoting at least one of a material property, an electrical property, or a spin property. The memory device may further include wherein the electrically insulating spin conductor is configured such that its electrical conductance can be tuned so that a charge current flow entering vertically from the free layer into the electrically insulating spin conductor results in a laterally spread current, the laterally spread current being the asymmetric charge current flow in the spin orbit channel drawn away towards one side. The memory device may further include wherein a net amount of the spin current coupled into the free layer by a combination of the spin and charge conductor, the electrically insulating spin conductor, and the spin orbit channel is augmented compared to having the free layer residing directly on the spin orbit channel. The memory device may further include wherein the magnetic tunnel junction further comprises a tunnel barrier on the free layer, and a reference layer on the tunnel barrier, the reference layer being configured to couple the second electrical terminal to the magnetic tunnel junction. The memory device may further include wherein the magnetic tunnel junction is configured to be laterally displaced by a plurality of distances from a center position of the memory device closer to the first electrical terminal and downstream direction of the asymmetric charge current flow. The memory device may further include wherein the free layer permits the magnetic tunnel junction to be laterally displaced by the plurality of distances from the center position of the memory device. 
     In another exemplary embodiment, a method to form a memory device includes coupling a second electrical terminal to a magnetic tunnel junction; wherein the magnetic tunnel junction comprises a magnetic free layer, and the magnetic tunnel junction is configured to be displaced by a plurality of distances from a center position of the memory device; coupling a nonmagnetic metallic spin harvesting conductor to the magnetic tunnel junction; wherein the nonmagnetic metallic spin harvesting conductor has a lateral dimension that is larger than that of the magnetic tunnel junction; coupling an electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor; wherein the nonmagnetic metallic spin harvesting conductor collects spin current from the electrically insulating spin conductor; wherein the electrically insulating spin conductor has relatively less electrical conductivity than the nonmagnetic metallic spin harvesting conductor; and coupling a spin orbit conduction channel to the electrically insulating spin conductor and to a first electrical terminal; wherein the spin orbit conduction channel generates the spin current from a laterally asymmetric charge current flow; wherein the spin current is conducted by the electrically insulating spin conductor to the nonmagnetic metallic spin harvesting conductor and further delivered to the magnetic free layer of the magnetic tunnel junction. 
     The method may further include connecting the spin orbit conduction channel to the electrically insulating spin conductor with an interface, the interface may be direct or may contain a minute doping material for promoting at least one of a material property, an electrical property, or a spin property. The method may further include wherein the electrically insulating spin conductor redistributes a charge current from the magnetic tunnel junction to the spin orbit conduction channel to create the laterally asymmetric charge current flow, the laterally asymmetric charge current flow increasing in intensity towards the first electrical terminal. The method may further include wherein the electrically insulating spin conductor is configured such that its electrical conductance can be tuned so that a charge current flow entering vertically from the magnetic free layer into the electrically insulating spin conductor results in the laterally asymmetric charge current flow towards one side. The method may further include wherein a net amount of spin current coupled into the magnetic free layer by a combination of the nonmagnetic metallic spin harvesting conductor, the electrically insulating spin conductor, and the spin orbit conduction channel is augmented compared to having the magnetic free layer residing directly on the spin orbit conduction channel. 
     LIST OF ABBREVIATIONS: 
     
         
         3D three-dimensional 
         FL free layer 
         FM ferromagnetic 
         ISC insulating spin-conductor 
         MTJ magnetic tunnel junction 
         MR magnetoresistance 
         NM nonmagnetic metallic 
         n.u. no units 
         RL reference layer 
         sd spin diffusion 
         SOT spin orbit torque 
         STT spin transfer torque 
         TB tunnel barrier 
       
    
     In the foregoing description, numerous specific details are set forth, such as particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide a thorough understanding of the exemplary embodiments disclosed herein. However, it will be appreciated by one of ordinary skill of the art that the exemplary embodiments disclosed herein may be practiced without these specific details. Additionally, details of well-known structures or processing steps may have been omitted or may have not been described in order to avoid obscuring the presented embodiments. It will be understood that when an element as a layer, region, or substrate is referred to as being “on” or “over” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly” over another element, there are no intervening elements present. It will also be understood that when an element is referred to as being “beneath” or “under” another element, it can be directly beneath or under the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly beneath” or “directly under” another element, there are no intervening elements present. 
     The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limiting in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The embodiments were chosen and described in order to best explain the principles of the invention and the practical applications, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular uses contemplated.