Patent Publication Number: US-8536823-B2

Title: Driving method and driving device for driving a polyphase inverter

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application claims priority of Taiwanese application no. 098118543, filed on Jun. 4, 2009. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a driving method and driving device for driving a polyphase inverter. 
     2. Description of the Related Art 
       FIG. 1  illustrates a conventional three-phase inverter  900  that includes three inverter legs, each of which has upper and lower transistors (M 1  and M 2 , M 3  and M 4 , and M 5  and M 6 ). The transistors (M 1  to M 6 ) of the conventional three-phase inverter  900  are switched on and off by driving signals (S 1  to S 6 ) generated by a driving device  950  to thereby permit the conventional three-phase inverter  900  to generate inverter output voltages (Va, Vb, Vc), whereby three sinusoidal signals that have equal amplitudes and that are 120° out of phase are generated. The driving device  950  typically uses a sinusoidal pulse width modulation (SPWM) technique or a space vector PWM (SVPWM) technique to generate the driving signals (S 1  to S 6 ). However, the number of times the transistors (M 1  to M 6 ) of the conventional three-phase inverter  900  are switched on and off when driven by the driving signals (S 1  to S 6 ) generated by the driving device  950  is determined by the carrier frequency of the driving device  950 , is fixed, and is relatively high. This increases power consumption, and thus decreases efficiency of the conventional three-phase inverter  900 . 
     SUMMARY OF THE INVENTION 
     Therefore, an object of the present invention is to provide a driving method for driving a polyphase inverter that can overcome the aforesaid drawbacks of the prior art. 
     Another object of the present invention is to provide a driving device for driving a polyphase inverter that can overcome the aforesaid drawbacks of the prior art. 
     According to an aspect of the present invention, a driving method for driving a polyphase inverter to be implemented by a driving device comprises: 
     A) configuring the driving device to receive a reference input that includes a fundamental frequency component, and a previously generated feedback signal; 
     B) configuring the driving device to generate an error signal that corresponds to a difference between the reference input and the previously generated feedback signal; 
     C) configuring the driving device to attenuate the frequency components of the error signal outside a predetermined frequency band to the minimum; 
     D) configuring the driving device to generate an optimum signal so that the magnitude of error signal within a predetermined frequency band is minimum; and 
     E) configuring the driving device to quantize the optimum signal, and to generate driving signals that correspond to the quantized optimum signal, wherein the driving signals are for driving the polyphase inverter. 
     According to another aspect of the present invention, a driving device for driving a polyphase inverter comprises a subtracting circuit, a filter module, and a quantizing module. The subtracting circuit is configured to receive a reference input that includes a fundamental frequency component, and a previously generated feedback signal and to generate an error signal that corresponds to a difference between the reference input and the previously generated feedback signal. The filter module is coupled to the subtracting circuit, and is configured to attenuate the magnitude of the error signal to the minimum, and to generate an optimum signal. The quantizing module is coupled to the filter module, and is configured to quantize the optimum signal, and to generate driving signals that correspond to the quantized optimum signal. The driving signals are for driving the polyphase inverter. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Other features and advantages of the present invention will become apparent in the following detailed description of the preferred embodiments with reference to the accompanying drawings, of which: 
         FIG. 1  is a circuit diagram of a conventional three-phase inverter; 
         FIG. 2  is a block diagram of the first preferred embodiment of a driving device according to the present invention; 
         FIG. 3  is a block diagram to illustrate driving signals generated by the first preferred embodiment for driving a three-phase inverter; 
         FIG. 4  is a circuit diagram of the three-phase inverter to be driven by the first preferred embodiment; 
         FIG. 5  is a flow chart of the first preferred embodiment of a driving method according to the present invention to be implemented using the driving device shown in  FIG. 2 ; 
         FIG. 6  are plots of frequency spectra of a reference input, a previously generated feedback signal, and an error signal generated by the first preferred embodiment; 
         FIG. 7  is a plot of a frequency spectrum of an error signal generated by the first preferred embodiment; 
         FIGS. 8 and 9  are plots to illustrate possible values for a control signal generated by the first preferred embodiment; 
         FIG. 10  is a block diagram to illustrate a filter module of the first preferred embodiment; 
         FIG. 11  is a block diagram to illustrate a quantizing circuit of the first preferred embodiment; 
         FIG. 12  is a plot to illustrate the number of times the polyphase inverter is switched on and off when driven by the first preferred embodiment as a function of a frequency of a reference input; 
         FIG. 13  is a plot to illustrate the harmonic distortion generated by the polyphase inverter when driven by the first preferred embodiment as a function of the frequency of the reference input; 
         FIG. 14  is a plot to illustrate the number of times the polyphase inverter is switched on and off when driven by the first preferred embodiment as a function of a ratio of an amplitude of the reference input (Vd) to a DC power source (Vdc) of the three-phase inverter; 
         FIG. 15  is a plot to illustrate the harmonic distortion generated by the polyphase inverter when driven by the first preferred embodiment as a function the ratio of the amplitude of the reference input (Vd) to the DC power source (Vdc) of the three-phase inverter; 
         FIG. 16  is a block diagram of the second preferred embodiment of a driving device according to the present invention; 
         FIG. 17  is a block diagram to illustrate driving signals generated by the second preferred embodiment for driving a N-phase inverter, where N&gt;3; 
         FIG. 18  is a block diagram to illustrate a quantizing circuit of the second preferred embodiment; and 
         FIG. 19  is a flow chart of the second preferred embodiment of a driving method according to the present invention to be implemented using the driving device shown in  FIG. 16 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Before the present invention is described in greater detail, it should be noted that like elements are denoted by the same reference numerals throughout the disclosure. 
     Referring to  FIGS. 2 and 3 , the first preferred embodiment of a driving device  100  according to this invention is shown to include a subtracting circuit  1 , a filter module  2 , and a quantizing module  3 . 
     The driving device  100  of this embodiment is applicable to generate driving signals (S 1  to S 6 ) for driving a three-phase inverter  200  to thereby permit the three-phase inverter  200  to generate output voltages that contain three sinusoidal signals that have equal amplitudes and that are 120° out of phase. The three sinusoidal signals generated by the three-phase inverter  200  are for driving a motor  300 , such as a Y-type motor or a Δ-type motor. 
     Although the motor  300  is exemplified as a Y-type motor or a Δ-type motor, it should be apparent to those skilled in the art that the motor  300  may be of any type according to requirements. 
     The three-phase inverter  200  in this embodiment includes three inverter legs  210 , each of which includes upper and lower transistors (M 1  to M 6 ) that are switched on and off, whereby an inverter output voltage (Va, Vb, Vc) is generated by each inverter leg  210 . 
     In order to eliminate the possibility of a short circuit or a floating state, when the upper transistor (M 1 , M 3 , M 5 ) is switched on, the corresponding lower transistor (M 2 , M 4 , M 6 ) is switched off, and when the lower transistor (M 2 , M 4 , M 6 ) is switched on, the corresponding upper transistor (M 1 , M 3 , M 5 ) is switched off. As such, there are eight possible combinations of switch states for the upper and lower transistors (M 1  to M 6 ). The eight possible combinations of the switch states and corresponding output line-to-line voltages (Vab, Vbc, Vca) are shown in Table I, where Vab=Va−Vb, Vbc=Vb−Vc, and Vca=Vc−Va. 
     
       
         
           
               
               
               
               
               
               
               
               
               
             
               
                 TABLE I 
               
               
                   
               
               
                 Vab 
                 Vbc 
                 Vca 
                 M1 
                 M2 
                 M3 
                 M4 
                 M5 
                 M6 
               
               
                   
               
             
            
               
                   
               
            
           
           
               
               
               
               
               
               
               
               
               
            
               
                 0 
                 0 
                 0 
                 Off 
                 On 
                 Off 
                 On 
                 Off 
                 On 
               
               
                 1 
                 0 
                 −1 
                 On 
                 Off 
                 Off 
                 On 
                 Off 
                 On 
               
               
                 0 
                 1 
                 −1 
                 On 
                 Off 
                 On 
                 Off 
                 Off 
                 On 
               
               
                 −1 
                 1 
                 0 
                 Off 
                 On 
                 On 
                 Off 
                 Off 
                 On 
               
               
                 −1 
                 0 
                 1 
                 Off 
                 On 
                 On 
                 Off 
                 On 
                 Off 
               
               
                 0 
                 −1 
                 1 
                 Off 
                 On 
                 Off 
                 On 
                 On 
                 Off 
               
               
                 1 
                 −1 
                 0 
                 On 
                 Off 
                 Off 
                 On 
                 On 
                 Off 
               
               
                 0 
                 0 
                 0 
                 On 
                 Off 
                 On 
                 Off 
                 On 
                 Off 
               
               
                   
               
            
           
         
       
     
     As illustrated in  FIG. 4 , the three-phase inverter  200  is connected across positive (+) and negative (−) terminals of a DC power source (Vdc). In this embodiment, the DC power source is 40 Vdc. As such, the values 1, 0, and −1 for the output line-to-line voltages (Vab, Vbc, Vca) are equivalent to 40V, 0V, and −40V, respectively. 
     The filter module  2  includes a filter circuit  21  connected to the subtracting circuit  1 , and an optimization circuit  22  connected to the filter circuit  21 . The quantizing module  3  includes a first dimension-transforming circuit  31  connected to the optimization circuit  22 , a quantizing circuit  32  connected to the first dimension-transforming circuit  31 , and a driving signal-generating circuit  33  connected to the quantizing circuit  32 . In this embodiment, the quantizing circuit  32  and the driving signal-generating circuit  33  constitute a quantizing unit. 
     The first preferred embodiment of a driving method for driving the three-phase inverter  200  to be implemented by the aforementioned driving device  100  according to this invention will now be described with further reference to  FIG. 5 . 
     In step  10 , the subtracting circuit  1  is configured to receive a reference input (r) and a previously generated feedback signal (u). 
     The reference input (r) received in this step is provided by an alternating current (AC) power source (not shown) and has three AC signals that are each 60 Hz and that are 120° out of phase. 
     It should be understood that the frequency 60 Hz is only exemplary and other frequencies are applicable. 
     The previously generated feedback signal (u) received in this step is a non-periodic digital signal. 
     In this embodiment, the instantaneous sum of the AC signals of the reference input (r) is zero. That is, at any given time, the summation of the AC signals of the reference input (r) is zero. Moreover, in this embodiment, the summation of the output line-to-line voltages (Vab, Vbc, Vca) is zero. As such, [1 1 1] r=0 and [1 1 1] u=0 are always satisfied. 
     In step  20 , the subtracting circuit  1  is configured to generate an error signal (e) that corresponds to a difference between the reference input (r) and the previously generated feedback signal (u) received thereby in step  10  and to send the error signal (e) to the filter circuit  21 . 
     The error signal (e) is generated in this step according to
 
 e=r−u    (1)
 
     As illustrated in  FIG. 6 , the reference input (r) received in step  10  includes a 60-Hz fundamental frequency component, and the previously generated feedback signal (u) received in step  10  includes the fundamental frequency component and noise components. Accordingly, the error signal (e) generated in this step is the signal that we want it to be as small as possible. 
     In step  30 , with further reference to  FIG. 7 , the filter circuit  21  is configured to receive the error signal (e) sent in step  20 , to attenuate the frequency components of the error signal (e) received thereby that are outside of a predetermined frequency range, i.e., from 0 Hz to 120 Hz, to the minimum, thereby achieving noise shaping, to generate a weighted error signal (y), and to send the weighted error signal (y) generated thereby and a state parameter (x) of the filter circuit  21  to the optimization circuit  22 . 
     The weighted error signal (y) is generated in this step using a frequency weighting function, which is defined as
 
 x ( k+ 1)= Ax ( k )+ Be ( k )   (2)
 
and
 
 y ( k )= Cx ( k )+ De ( k )   (3)
 
where: xεR 3n×3n  is the state parameter of the filter circuit  21 ; eεR 3×1  is the error signal; AεR 3n×3n , BεR 3n×3 , CεR 3×3n , and DεR 3×3  are predefined weight parameters; and yεR 3×1  is the weighted error signal.
 
     The output line-to-line voltages (Vab, Vbc, Vca) have a frequency that varies with the desired rotation speed of the motor  300  within the predetermined frequency range. As such, frequencies outside of the predetermined frequency range are regarded as noise and are therefore attenuated, i.e., filtered out, in this step. Accordingly, the attenuated error signal (y) generated in this step includes the frequency components of the error signal (e) that are within the predetermined frequency range. 
     The predetermined frequency range is determined by adjusting the predefined weight parameters (A, B, C, D). 
     As illustrated in  FIG. 10 , the frequency components of the error signal (e) that are outside of the predetermined frequency range may be attenuated by the filter circuit  21  to the minimum by determining appropriate values for the predefined weight parameters (A, B, C, D). 
     In step  40 , the optimization circuit  22  is configured to receive the weighted error signal (y) and the state parameter (x) sent by the filter circuit  21  in step  30  and the reference input (r), to attenuate the weighted error signal (y) to the minimum, to generate an optimum signal (v u ), and to send the optimum signal (v u ) to the first dimension-transforming circuit  31 . 
     In this step, the weighted error signal (y) is attenuated to the minimum using an optimization function, which is defined as
 
 V=y ( k ) T   Py ( k )   (4)
 
where P is a predefined parameter that is in the form of a matrix, P T =P&gt;0, and T is a transformation operation.
 
     The optimum signal (v u ) is generated in this step according to
 
 v   u   =Cx ( k )+ Dr ( k )   (5)
 
     In this embodiment, Equation (5) is derived from Equations (1), (3), and (4). 
     The optimum signal (v u ) generated in this step is a three-dimensional (3-D) vector optimum signal and corresponds to one of the eight aforementioned combinations of the output line-to-line voltages (Vab, Vbc, and Vca), and thus may be further represented as a two-dimensional (2-D) vector optimum signal. 
     In step  50 , the first dimension-transforming circuit  31  is configured to receive the 3-D vector optimum signal (v u ) sent in step  40 , to transform the 3-D vector optimum signal (v u ) received thereby into a 2-D vector optimum signal (v u ′), and to send the 2-D vector optimum signal (v u ′) thus transformed to the quantizing circuit  32 . 
     In this step, the optimum signal (v u ) is transformed into the 2-D vector optimum signal (v u ′) according to
 
v u ′=Q −1 Q −T R T D T Pv u    (6)
 
where v u ′εR 2×1 , Q T Q=R T D T PDR, QεR 2×2 ,
 
             R   =       [         1       0         -   1             0       1         -   1           ]     T           
is a predefined parameter, and P and T are as previously defined in Equation (4).
 
     The 2-D vector optimum signal (v u ′) generated in this step corresponds to one of the eight aforementioned combinations, two of which are identical, of the output line-to-line voltages (Vab and Vbc, Vbc and Vca, or Vab and Vca). 
     In step  60 , the quantizing circuit  32  is configured to receive the 2-D vector optimum signal (v u ′) sent in step  50 , to quantize the 2-D vector optimum signal (v u ′) received thereby, to generate a control signal (u′) that corresponds to the 2-D vector optimum signal (v u ′) quantized thereby, and to send the control signal (u′) generated thereby to the driving signal-generating circuit  33 . 
     The control signal (u′) generated in this step is a 2-D control signal, corresponds to the output line-to-line voltages (Vab and Vbc, Vbc and Vca, or Vca and Vab), and is one of [1 0] T , [0 1] T , [1 −1] T , [0 0] T , [−1 1] T , [0 −1] T  and [−1 0] T . 
       FIGS. 8 and 9  illustrate the seven possible values for the control signal (u′) and corresponding regions for two different values of Q, respectively. In  FIGS. 8 and 9 , the horizontal axis, 
                   [         1       0         ]     ⁢     v   u   ′       =         [         1       0         ]     ⁡     [           v     u   ⁢           ⁢   1     ′               v     u   ⁢           ⁢   2     ′           ]       =     v     u   ⁢           ⁢   1     ′         ,         
is associated with the vector in the first row and first column of the 2-D vector optimum signal (v u ′), and the vertical axis,
 
                   [         0       1         ]     ⁢     v   u   ′       =         [         0       1         ]     ⁡     [           v     u   ⁢           ⁢   1     ′               v     u   ⁢           ⁢   2     ′           ]       =     v     u   ⁢           ⁢   2     ′         ,         
is associated with the vector in the second row and the first column of the 2-D vector optimum signal (v u ′).
 
     It is noted that, in step  50 , Equation (6) is derived by first substituting Equations (1) and (3) into Equation (4) to thereby obtain
 
 V=f ( x,r )+ u′   T   R   T   D   T   PDRu′− 2 u′   T   R   T   D   T   P ( Cx+Dr )   (7)
 
and by substituting QεR 2×2  and Q T Q=R T D T PDR into (7). where
 
     
       
         
           
             
               u 
               ′ 
             
             = 
             
               
                 
                   [ 
                   
                     
                       
                         1 
                       
                       
                         0 
                       
                       
                         0 
                       
                     
                     
                       
                         0 
                       
                       
                         1 
                       
                       
                         0 
                       
                     
                   
                   ] 
                 
                 ⁢ 
                 u 
               
               ∈ 
               
                 
                   R 
                   
                     2 
                     × 
                     1 
                   
                 
                 . 
               
             
           
         
       
     
     In step  70 , the driving signal-generating circuit  33  is configured to receive the control signal (u′) sent in step  60 , and to convert the control signal (u′) received thereby into the driving signals (S 1  to S 6 ) with reference to a predefined look-up table, which corresponds to Table I and which is built into the quantizing module  3 . 
     It is noted that each of the driving signals (S 1 , S 3 , and S 5 ) complements a respective one of the driving signals (S 2 , S 4 , and S 6 ). As such, when the three driving signals (e.g., S 1 , S 3 , S 5 ) are obtained, the remaining driving signals (i.e., S 2 , S 4 , S 6 ) may be obtained using a logic “not” gate. 
     The driving signal-generating circuit  33  may employ digital logic to construct the predefined look-up table. Since the driving signal-generating circuit  33  is known in the art, a detailed description thereof will not be provided herein for the sake of brevity. 
     The driving device  100  further includes a second dimension-transforming circuit  4  and a sampling switch (SW 1 ). The second dimension-transforming circuit  4  is connected to the subtracting circuit  1  and the quantizing circuit  32 , and is configured to transform the control signal (u′) into a 3-D currently generated feedback signal (u). The currently generated feedback signal (u) serves as a next previously generated feedback signal inputted to the subtracting circuit  1  for use in generating a next sequence of driving signals. The sampling switch (SW 1 ) is connected to the subtracting circuit  1 , is configured to sample the reference input (r) prior to receipt by the subtracting circuit  1 , and has a sampling frequency determined based on the rotation speed of the motor  300  and charge/discharge time of the transistors (M 1  to M 6 ) of the three-phase inverter  200 . 
     In this embodiment, as illustrated in  FIG. 11 , the quantizing circuit  32  includes a plurality of polarity comparators (Sign(x)) and a plurality of logic comparators (Logic). Each of the polarity comparators (Sign(x)) is defined as 
               Sign   ⁢           ⁢     (   x   )       =     {           1   ,           x   &gt;   0               0   ,           x   =   0                 -   1     ,           x   &lt;   0                   
and each of the logic comparators (Logic) is defined as
 
               Logic   ⁢           ⁢     (       s   1     ,     s   2       )       =     {           0   ,             s   1     ≠     s   2                 s   1         else                 
It is noted that the 0.707, 1.732, and 1.414 in  FIG. 11  are generated based on the predefined weight parameters (A, B, C, D).
 
     By transforming the 3-D vector optimum signal (v u ) into the 2-D vector optimum signal (v u ′), processing operation and circuit design of the quantizing module  3  are simplified. However, if the complexity of the circuit design of the quantizing module  3  is not an issue, the first dimension-transforming circuit  31  may be dispensed with. As such, step  50  is skipped, the optimization circuit  22  is configured to send the 3-D vector optimum signal (v u ) directly to the quantizing circuit  32  in step  40 , and the quantizing circuit  32  is configured to receive the 3-D vector optimum signal (v u ), to quantize the 3-D vector optimum signal (v u ), and to generate a control signal (u) that corresponds to the 3-D vector optimum signal (v u ) obtained thereby in step  60 . 
     As illustrated in  FIG. 12 , simulation experimental results, where the reference input (r) has a frequency range from 20 Hz to 100 Hz, the sampling switch (SW 1 ) samples the reference input (r) at a sampling frequency of 3 KHz, and the feedback signal (u) has a minimum pulse width of 1/(3 k×2 2 )= 1/12000 seconds, show that the number of times (L 2   a ), i.e., less than 8000 times, the transistors (M 1  to M 6 ) of the three-phase inverter  200  are switched on and off when driven by the driving signals (S 1  to S 6 ) generated by the driving device  100  of this embodiment is at least 30% lower than the number of times (L 1   a ), i.e., 12000 times, the transistors (M 1  to M 6 ) of the three-phase inverter  200  are switched on and off when driven by driving signals generated using space vector pulse wave modulation (SVPWM) technique. 
     In addition, as illustrated in  FIG. 14 , simulation results, where the sampling switch (SW 1 ) samples the reference input (r) at a sampling frequency of 3 KHz and the feedback signal (u) has a minimum pulse width of 1/(3 k×2)= 1/6000 seconds, show that the number of times (L 2   c ) the transistors (M 1  to M 6 ) of the three-phase inverter  200  are switched on and off when driven by the driving signals (S 1  to S 6 ) generated by the driving device  100  of this embodiment is lower than the number of times (L 1   c ) the transistors (M 1  to M 6 ) of the three-phase inverter  200  are switched on and off when driven by driving signals generated using the SVPWM technique. 
     From the foregoing, the three-phase inverter  200  when driven by driving signals (S 1  to S 6 ) generated by the driving device  100  of this embodiment achieves relatively low power consumption and therefore has a high efficiency. 
     Moreover, as illustrated in  FIG. 13 , simulation results, where the reference input (r) has a frequency range from 20 Hz to 100 Hz, the sampling switch (SW 1 ) samples the reference input (r) at a sampling frequency of 3 KHz, and the feedback signal (u) has a minimum pulse width of 1/(3 k×2 2 )= 1/12000 seconds, show that the harmonic distortion (L 2   b ) generated by the three-phase inverter driven by the driving signals (S 1  to S 6 ) generated by the driving device  100  of this embodiment is considerably lower than the harmonic distortion (L 1   b ) generated by the three-phase inverter driven by the driving signals generated using the SVPWM technique. 
     Furthermore, as illustrated in  FIG. 15 , simulation results, where the sampling switch (SW 1 ) samples the reference input (r) at a sampling frequency of 3 KHz and the feedback signal (u) has a minimum pulse width of 1/(3 k×2)= 1/6000 seconds, show that the harmonic distortion (L 2   d ) generated by the three-phase inverter driven by the driving signals (S 1  to S 6 ) generated by the driving device  100  of this embodiment is considerably lower than the harmonic distortion (L 1   d ) generated by the three-phase inverter driven by the driving signals generated using the SVPWM technique. 
       FIG. 16  illustrates the second preferred embodiment of a driving device  100 ′ according to this invention. When compared to the previous embodiment, as illustrated in  FIG. 17 , the driving device  100 ′ of this embodiment is applicable to generate driving signals (S 1  to S 2N ) for driving a N-phase inverter  200 ′, where N&gt;3, to thereby permit the N-phase inverter  200 ′ to generate output voltages that contain sinusoidal signals that have equal amplitude and that are 360°/N out of phase. The sinusoidal signals generated by the N-phase inverter  200 ′ are for driving a motor  300 ′. 
     The driving device  100 ′ includes a subtracting circuit  1 , a filter module  2 , and a quantizing module  3 . The filter module  2  includes a filter circuit  21  connected to the subtracting circuit  1 , and an optimization circuit  22  connected to the filter circuit  21 . In this embodiment, the filter circuit  21  is a N input and N output filter circuit  21 . The quantizing module  3  includes a quantizing circuit  32 ′ and a driving signal-generating circuit  33 ′. In this embodiment, with further reference to  FIG. 18 , the quantizing circuit  32 ′ includes a first vector-arranging unit  321  connected to the optimization circuit  22 , a vector-subtracting unit  322  connected to the first vector-arranging unit  321 , a second vector-arranging unit  323  connected to the vector-subtracting unit  322 , a reference signal-generating unit  324  connected to the first and second vector-arranging units  321 ,  323 , and a signal-converting unit  325  connected to the reference signal-generating unit  324 . The driving signal-generating circuit  33 ′ is connected to the signal-converting unit  325  of the quantizing circuit  32 ′. 
     The second preferred embodiment of a driving method for driving the N-phase inverter  200 ′ to be implemented by the aforementioned driving device  100 ′ according to this invention will now be described with further reference to  FIG. 19 . 
     In step  80 , the subtracting circuit  1  is configured to receive a reference input (r) and a previously generated feedback signal (u). 
     In step  81 , the subtracting circuit  1  is configured to generate an error signal (e) that corresponds to a difference between the reference input (r) and the previously generated feedback signal (u) and to send the error signal (e) to the filter circuit  21 . 
     In step  82 , the filter circuit  21  is configured to receive the error signal (e) sent by the subtracting circuit  1  in step  81 , to attenuate the frequency components of the error signal (e) received thereby that are outside of the predetermined frequency range to the minimum, and to generate a weighted error signal (y) and to send the weighted error signal (y) generated thereby and a state parameter (x) of the filter circuit  21  to the optimization circuit  22 . 
     The weighted error signal (y) is generated in this step using a frequency weighting function, which is defined as
 
 x ( k+ 1)= Ax ( k )+ Be ( k )
 
and
 
 y ( k )= Cx ( k )+ De ( k )
 
where: xεR Nn×Nn  is a state parameter of the filter circuit  21 ; eεR N×1  is the error signal; AεR Nn×Nn , BεR Nn×N , CεR N×Nn  and DεR N×N  are weight parameters; and yεR N×1  is the weighted error signal (y).
 
     In step  83 , the optimization circuit  22  is configured to receive the weighted error signal (y) and the state parameter (x) sent by the filter circuit  21  in step  82  and the reference input (r), to attenuate the weighted error signal (y) to the minimum, to generate an optimum signal (v u ), and to send the optimum signal (v u ) generated thereby to the first vector-arranging unit  321 . 
     In step  84 , the first vector-arranging unit  321  is configured to receive the optimum signal (v u ) sent in step  83 , to arrange vectors of the optimum signal (v u ) received thereby in a descending sequence, to generate a first arranged-vector signal ({circumflex over (V)} u ) that corresponds to the vectors of the optimum signal (v u ) arranged thereby and a first parameter (P m1 ) that describes arrangement of the vectors of the optimum signal (v u ) arranged thereby, and to send first parameter (P m1 ) and the first arranged-vector signal ({circumflex over (V)} u ) generated thereby to the reference signal-generating unit  324  and the vector-subtracting unit  322 , respectively. 
     The first arranged-vector signal ({circumflex over (V)} u ) and the first parameter (P m1 ) are generated in this step according to
 
P m1 v u ={circumflex over (V)} u =[{circumflex over (V)} u1  {circumflex over (V)} u2  . . . {circumflex over (V)} uN ] T  
 
where {circumflex over (V)} u1 ≧{circumflex over (V)} u2 ≧ . . . ≧{circumflex over (V)} uN  and P m1 εR N×N .
 
     In step  85 , the vector-subtracting unit  322  is configured to receive the first arranged-vector signal ({circumflex over (V)} u ) sent in step  84 , to perform subtraction operation on the vectors of the first arranged-vector signal ({circumflex over (V)} u ) received thereby, to generate a vector-difference signal (d) that corresponds to a result of the subtraction operation performed thereby, and to send the vector-difference signal (d) generated thereby to the second vector-arranging unit  323 . 
     The vector-difference signal (d) is generated in this step according to 
     
       
         
           
             d 
             = 
             
               
                 
                   [ 
                   
                     
                       
                         1 
                       
                     
                     
                       
                         
                           
                             V 
                             ^ 
                           
                           u 
                         
                       
                     
                   
                   ] 
                 
                 - 
                 
                   [ 
                   
                     
                       
                         
                           
                             V 
                             ^ 
                           
                           u 
                         
                       
                     
                     
                       
                         0 
                       
                     
                   
                   ] 
                 
               
               ∈ 
               
                 R 
                 
                   
                     ( 
                     
                       N 
                       + 
                       1 
                     
                     ) 
                   
                   × 
                   1 
                 
               
             
           
         
       
     
     In step  86 , the second vector-arranging unit  323  is configured to receive the vector-difference signal (d) sent in step  85 , to arrange vectors of the vector-difference signal (d) received thereby in a descending sequence, to generate a second parameter (P m2 ) that describes arrangement of the vectors of the vector-difference signal (d) arranged thereby, and to send the second parameter (P m2 ) generated thereby to the reference signal-generating unit  324 . 
     The second parameter (P m2 ) is generated in this step according to
 
P m2 d={circumflex over (d)}=[{circumflex over (d)} 1  {circumflex over (d)} 2  . . . {circumflex over (d)} N+1 ] T  
 
     where {circumflex over (d)} is a second arranged-vector signal that corresponds to the vectors of the vector-difference signal (d) arranged by the second vector-arranging unit  323 , {circumflex over (d)} 1 ≧{circumflex over (d)} 2 ≧ . . . ≧{circumflex over (d)} N+1 , and P m2 εR (N+1)×(N+1) . 
     In step  87 , the reference signal-generating unit  324  is configured to receive the first parameter (P m1 ) sent in step  84 , the second parameter (P m2 ) sent in step  86 , and a reference matrix ({circumflex over (D)}), to generate a reference feedback signal (û) based on the first and second parameters (P m1 , P m2 ) and the reference matrix received thereby, and to send the reference feedback signal (û) generated thereby to the signal-converting unit  325 . 
     The reference feedback signal (û) is generated in this step according to 
     
       
         
           
             
               u 
               ^ 
             
             = 
             
               
                 P 
                 
                   m 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   1 
                 
                 T 
               
               ⁢ 
               
                 D 
                 ^ 
               
               ⁢ 
               
                 P 
                 
                   m 
                   ⁢ 
                   
                       
                   
                   ⁢ 
                   2 
                 
                 T 
               
             
           
         
       
       
         
           
             
               where 
               ⁢ 
               
                   
               
               ⁢ 
               
                 D 
                 ^ 
               
             
             = 
             
               
                 [ 
                 
                   
                     
                       0 
                     
                     
                       1 
                     
                     
                       1 
                     
                     
                       ⋯ 
                     
                     
                       1 
                     
                   
                   
                     
                       0 
                     
                     
                       0 
                     
                     
                       ⋱ 
                     
                     
                       
                           
                       
                     
                     
                       ⋮ 
                     
                   
                   
                     
                       ⋮ 
                     
                     
                       ⋮ 
                     
                     
                       ⋯ 
                     
                     
                       
                           
                       
                     
                     
                       1 
                     
                   
                   
                     
                       0 
                     
                     
                       0 
                     
                     
                       ⋯0 
                     
                     
                       
                           
                       
                     
                     
                       1 
                     
                   
                 
                 ] 
               
               ∈ 
               
                 
                   R 
                   
                     N 
                     × 
                     
                       ( 
                       
                         N 
                         + 
                         1 
                       
                       ) 
                     
                   
                 
                 . 
               
             
           
         
       
     
     In step  88 , the signal-converting unit  325  is configured to receive the reference feedback signal (û) sent in step  87 , to convert vectors in the first column of the reference feedback signal (û) received thereby, which correspond to one of the switch states, into a currently generated feedback signal (u), and to send the currently generated feedback signal (u) to the driving signal-generating circuit  33 ′. The currently generated feedback signal (u) serves as a next previously generated feedback signal inputted to the subtracting circuit  1  for use in generating a next sequence of driving signals. 
     In this step, the reference feedback signal (û) is converted into the currently generated feedback signal (u) according to 
             u   =       [         1         -   1         0       ⋯                   0           0       1         -   1         0                   ⋮           ⋮       ⋱       ⋱       ⋱                   0           0                   ⋱       ⋱                     -   1               -   1         0       ⋯       0                   1         ]     ⁢       u   ^     ⁡     [         1           0           ⋮           0         ]                       where   ⁢           [         1         -   1         0       ⋯                   0           0       1         -   1         0                   ⋮           ⋮       ⋱       ⋱       ⋱                   0           0                   ⋱       ⋱                     -   1               -   1         0       ⋯       0                   1         ]     ⁢           ⁢     and   ⁢           [         1           0           ⋮           0         ]           
are constant matrices.
 
     In step  89 , the driving signal-generating circuit  33 ′ is configured to receive the currently generated feedback signal (u) sent in step  88 , and to convert the currently generated feedback signal (u) received thereby into the driving signals (S 1  to S 2N ) with reference to a predefined look-up table built into the quantizing module  3 . 
     While the present invention has been described in connection with what are considered the most practical and preferred embodiments, it is understood that this invention is not limited to the disclosed embodiments but is intended to cover various arrangements included within the spirit and scope of the broadest interpretation so as to encompass all such modifications and equivalent arrangements.