Patent Publication Number: US-3878470-A

Title: Fm demodulator

Description:
United States Patent Boltz, Jr. Apr. 15, 1975 [54] FM DEMODULATOR 3.514.705 /1970 Feiglcson 328/133 3, 2 [75] Inventor: Charles D. Boltz, Jr., Greenwood, 699 /1972 Humbmgcr 3 950 X Ind. OTHER PUBLICATIONS 73 Assignee: RCA Corporation, New York N.Y. Smith, Voltage PUISC Width SGIQCI Circuit- V-OI. 7, [22] F1 d J l 16 1973 No. 1. June 1964 IBM Tech. Disclosure Bulletm, p.  
 l e I u y 9 27.  
 [21] Appl. No.: 379,469  
  Primary ExaminerAlfred L. Brody Attorney, Agent, or Firm-Eugene M. Whitacre; Foreign Application Priority Data Mason Decammis Aug. 18, 1973 United Kingdom 38708/73 52 U s C 3 [57] ABSTRACT 1 29/126 328/] A source of frequency modulated signals is coupled to 329/1 12 329/145 [51] Int Cl H03d 3/04 a coincidence detector by a first and a second signal [58] Field of Search 329/106, 107, 50, 126, P g af i fi i fif I f; uneqgal 329/1 10 l 12, 129 130 145, 146; 328/1 10, s1gna e ay c arac ens so a e co1nc1 ence e- 112 133 tector prov1des an output signal comprised of a serles of substantially constant width pulses wherein pulse width is determined by the difference in signal delay [56] References Clted between the first and second signal paths. A low pass UNITED STATES PATENTS filter is coupled to the coincidence detector for recov- 2,830,179 4/1958 Stenning 328/ X ering the signal modulation represented by the series of substantially constant width pulses.  
 313921337 7/1968 Neuburger 329/ 7 Claims, 2 a g g r s 164 I65 1 1 I63 I i I 73 I 7 LIMITING PHASE E 166 I67 6&#39;; I i CIRCUITRY SPLITTER 1 1 1 I l l l l 1 l I 1 I69 170 171i 174 175 FM 1 I I LOW SIGNAL L L PASS SOURCE FILTER OUTPUT FM DEMODULATOR This invention relates to frequency modulation (FM) detectors of the pulse counter type.  
  FM demodulation by pulse count&#34; techniques has seen increasing use in recent years. particularly in wideband FM systems. FM demodulation by the pulse count method has also been used to overcome the disadvantages of earlier prior art tuned circuit type of FM demodulators which required transformers or tuned circuits which may be subject to frequency drift.  
  In a pulse counter type of FM demodulator. the frequency modulated signals typically are amplified and limited to produce so-called &#34;square waves&#34; which have zero axis crossings spaced in the same manner as the FM waves. The square waves are then converted into pulses of constant amplitude and width (time duration) independent of the frequency of the applied FM signal. Generally a constant width pulse is produced at each zero crossing of the modulated input signal. The resulting signal, in the form ofa series of constant width pulses, is then integrated (or filtered) to reproduce the modulating signal information.  
  Pulse counter demodulators of the type described have been constructed using various forms of frequency doubling in order to improve the quality of the recovered signal information after integration and to provide an increased separation between the recovered pulse signal and the frequency of the modulating signal.  
 This latter feature is of particular importance in wideband FM demodulators used in video systems.  
  In one form of pulse counter demodulator, two oppositely phased. limited square waves derived from the FM wave are coupled to individual one-shot (astable) multivibrators. Pulses produced by each one-shot multivibrator at zero crossover points of the FM signal are then summed in an adder to provide a series of pulses at twice the repetition rate of the frequency deviated carrier wave. A low pass filter integrates this series of pulses to recover the modulating signal.  
  This described form of pulse counter, however, exhibits operating disadvantages. It is difficult to achieve identical one-shot multivibrators. This problem of symmetry of one-shot multivibrators increases as the operating temperature range varies, producing temperature tracking problems. If the one-shot multivibrators are not exactly alike, the pulse that is produced at each zero crossing will differ, i.e., contain different amounts of energy or be of a different width.  
  This non-perfect tracking, due to component as well as temperature variation, produces unwanted harmonics which will appear in the demodulated signals. Similarly, tracking variations in the adder circuit produces unwanted signals in the demodulated output if the adder does not keep both one-shot multivibrator pulse outputs balanced. Pulse counter demodulators have been constructed using a single one-shot multivibrator triggered at each crossover to avoid the difficulties of identical circuit construction and temperature track- ,ing. However, the high frequency operation for which In accordance with the present invention apparatus for demodulating a frequency modulated signal is provided wherein a source of frequency modulated signals is coupled to a coincidence detector by a first and a second signal path. The first and second signal paths have unequal signal delay characteristics so that the coincidence detector provides an output signal comprised of a series of substantially constant width pulses wherein pulse width is determined by the difference in signal delay between the first and second signal paths. A low pass filter is coupled to the coincidence detector for recovering the signal modulation represented by the series of substantially constant width pulses.  
 Referring to the accompanying drawings:  
  FIG. 1 is a block diagram of a pulse counter type of frequency modulation detector constructed in accordance with the invention; and  
  FIG. 2 is a series of waveform diagrams representative of the signal processing of the FM demodulator shown in FIG. 1.  
  In FIG. 1, an FM signal is coupled to a limiter 152 and then to a phase splitter 163 which serve to provide two &#34;squared&#34; signals of opposite phase with zero axis crossings corresponding to the zero crossings ofthe modulated FM signal. The signals from the phase splitter are processed in substantially identical signal channels as follows. A first of the outputs of the phase splitter 163 (signal A) is coupled through a first signal path comprising inverters 166,167,168 and nand gate 172. The input terminals of nand gate 172 are arranged so that it performs the same function as inverters 166,167,168.  
  Inverters 166,167 and 168 are illustrated as included in a first integrated circuit indicated by the dashed outline 164 while nand gate 172 is in a second integrated circuit 165. Nandgate 172 may, in practice, be replaced by an additional inverter on the integrated chip 164. The output of this first path 166,167,168,172 is coupled to one input of a coincidence detector 173. The output of inverter 166 is also coupled via a direct connection to a second input of coincidence detector 173, the inverter 166 and the direct connection providing a second signal path for the signal&#39;A. Coincidence detector 173 will provide an output whenever both of its inputs are of the same status, i.e., coincidence detector 173 will produce a down output when both of its inputs are up.  
  A second signal channel which processes signal B from phase splitter 163 also is provided. In the same manner as was described in connection with the first signal channel, signal B is direct coupled to one input of a coincidence detector via an inverter 169 and is further coupledto a second input of detector 175 through a circuit comprising inverters 170,171 and nand gate 174. The output signals from coincidence detectors 173 and 175 are summed in a summer 176. The combined waveform from the output of summer 176 is integrated in a low pass filter 177 to provide an output signal which corresponds to the modulation signal information contained in the FM input signal applied to the pulse counter demodulator as will be explained below.  
  FIG. 2 shows waveforms useful in describing the operation of the pulse counter demodulator shown in FIG. 1. Waveform 25 is representative of a frequency modulated wave having zero axis crossings which are displaced from those of the carrier wave according to the modulation content imposed on the fundamental carrier frequency. Waveform 26 represents the output waveform of limiter 152 and is ofa squared waveshape having Zero axis crossings corresponding to the zero axis crossings of the input signal which is coupled to the input of limiter 152.  
  The signal represented by waveform 26 is coupled to phase splitter 163 which provides two output signals, one (waveform 27) in phase with the input signal and a second signal (waveform 28) l80 out-of-phase with the input signal 26. The signal represented by waveform 27 is coupled into inverting stage 166. Inverter stage 166 exhibits a signal propagation delay which delays the positive going excursions by a first interval (e.g.. approximately 8 nanoseconds) and the negative going excursions by a second interval (e.g., approximately l2 nanoseconds). These delays are represented by the times T3 and T4 shown in waveform 29 which is representative of the output of inverter 166. In a similar manner, inverter 169 will delay waveform 28, producing waveform 30 which has a negative-going portion delayed, for example, by l2 nanoseconds and a positive-going portion delayed, for example, by 8 nanoseconds. These delays are shown at times T5 and T6.  
  Where each of the inverters is of substantially identical structure. similar delays occur as the signals pass through inverters 167,168, nand gate 172, inverters 170, 171, and nand gate 174. The corresponding delays are shown accumulative in waveforms 31,33,35,32,34, and 36 respectively.  
  The output of inverter 166, represented by waveform 29, and the output of nand gate 172, represented by delayed waveform 35, are coupled to coincidence detector 173. The output of coincidence detector 173 is represented by waveform 37 which is a series of pulses of substantially constant width. The difference in signal delay between the signal paths coupled to coincidence detector 173 will determine the duration that coincidence detector 173 provides an output. The pulse output of coincidence detector 173 therefore is of substantially constant width and would suffice as a signal suitable for demodulation when connected directly to a low pass filter.  
  However as previously mentioned, it is desirable to increase the separation between the recovered signal and the frequency of the modulating signal in a wideband FM system such as used in video recording and demodulation. Therefore, the output of inverter 169, represented by waveform 30, and the output of nand gate 174, represented by delayed waveform 36, are coupled to coincidence detector 175. The output of coincidence detector 175 is represented by waveform 38 which is a series of pulses substantially identical in width to the output of coincidence detector 173, but displaced in time by virtue ofthe 180 phase difference in signals represented by phase splitter waveforms 27 I and 28. Waveform 39 shows the output of the summing circuit 176 which has as its inputs waveforms 37 and 38. The resulting waveform 39 is a series of substantially constant width and constant amplitude pulses at twice the input frequency, i.e., a pulse at each zero crossing of input waveform 25.  
  As was shown above, a typical propagation delay for each of the inverting stages 166 through 172 is 8 nanoseconds for a positive transition and 12 nanoseconds for a negative transition. If a signal is coupled through one stage or an odd number of stages, it can be seen that this will produce some distortion to the signals (waveforms 29 and 30). However, two stages or an even number of stages will restore the proper time relationship between leading and trailing edges of the waveform (waveforms 35 and 36). In one application of this invention relating to the recording of television (video) signals, it is desirable to use a carrier frequency of approximately 6.5 MHz. In that case, three stages of delay are used with an added logic stage. This provides a typical delay of 31 nanoseconds and a maximum delay of 59 nanoseconds. These delays will provide suitable pulse widths at the output of summer circuit 176 (waveforms 39).  
  As can be seen from FIG. 1 and the associated waveforms of FIG. 2, both signal phases are handled substantially identical to provide the desired equal pulse widths and proper time sequence. An even number of logic stages is provided to restore waveform distortion due to the unequal delay for positive and negative transitions. Since the delays are accomplished on the same integrated circuit chips 164,165, substantially equal temperature and device tracking results. The pulse width is a function of the signal propagation delay of the particular device used and can be made to fit within system design limits. Since both signal phases are handled substantially identical, the conventional pulse counter problems previously described resulting from separate one-shot multivibrator and temperature drift are overcome.  
  The illustrated embodiment shown in FIG. 1 may be constructed using a Signetics TTL type 7404 Hex inverter for integrated circuit 164 and a Signetics TTL type 7400 quad nand gate for integrated circuit 165. The system limits were chosen to operate around a carrier frequency of approximately 6 MHz with a deviation of 1 MHz. in actual use, the demodulator may be employed at various higher or lower frequencies. The arrangement utilizing the named devices is expected to function well at least up to approximately 9 MHz of carrier frequency.  
 What is claimed is:  
  1. Apparatus for demodulating a frequency modulated signal comprising:  
 a source of frequency modulated signals having first and second signal output terminals providing first and second signals of opposite phase,  
 a first signal processing channel comprising:  
 a first coincidence detector;  
 a&#39;first signal path coupled from said first signal terminal to said first coincidence detector;  
 a second signal path coupled from said first signal terminal to said first coincidence detector;  
 said first and second signal paths exhibiting unequal signal time delay characteristics whereby said first coincidence detector provides a first output signal which is a series of substantially constant width pulses having a width determined by the difference in signal delay between said first and second signal paths; and  
 a second signal processing channel comprising:  
 a second coincidence detector;  
 a third signal path coupled from said second signal terminal to said second coincidence detector;  
 a fourth signal path coupled from said second signal terminal to said second coincidence detector;  
 said third and fourth signal paths exhibiting unequal signal time delay characteristics whereby said second coincidence detector provides a second output signal which is a series of substantially constant width pulses having a width determined by the difference in signal delay between said third and fourth signal paths. and occurring in timed relation with respect to pulses of said first output signal according to the relative phases of said first and second signals provided by said source of signals. summing means coupled to said first and second coincidence detectors and responsive to their respective output signals to provide a third output signal consisting of a series of substantially constant width pulses, the repetition rate of which is a multiple of said frequency modulated signal repetition rate. and low pass filter means coupled to said summing means and responsive to said third output for recovering the signal modulation represented by the summa tion of said first and second series of substantially constant width pulses. 2. Apparatus in accordance with claim 1 for demodulating a frequency modulated signal wherein:  
 lated signal comprising:  
 a source of frequency modulated signals;  
 a limiter circuit coupled to said source to provide squared signals of substantially constant amplitude and width corresponding in time occurrence to zero axis crossings of said frequency modulated signal;  
 a phase splitter coupled to said limiter output to provide first and second signals of opposite phase;  
 a first signal channel having a first coincidence detector with one input direct coupled through a first signal path to said first phase splitter signal; said first coincidence detector having a second input coupled through a second signal path having first signal delay means;  
 a second signal channel having a second coincidence detector&#39;with one input direct coupled through a third signal path to said second phase splitter signal, said second coincidence detector having a second input coupled through a fourth signal path having second signal delay means;  
 said first and second signal delay means comprising first, second. and third devices for providing a predetermined signal delay so that the output of said first and second coincidence detectors comprises a series of pulses of substantially constant width and substantially constant amplitude. wherein said width is determined by the signal delay of said devices in said second and fourth signal paths as compared to the respective first and third direct coupled signal paths;  
 summing means coupled to the output of said first and second coincidence detectors and responsive to the respective outputs to provide a third output consisting of a series of substantially constant amplitude and constant width pulses having a repetition rate which is a multiple of the repetition rate of said frequency modulated signals;  
 and  
 low pass filter means coupled to said third output for recovering the signal modulation represented by the summation of said first and second series of output pulses.  
 4. Apparatus in accordance with claim 1 for demodulating a frequency modulated signal wherein:  
 lating a frequency modulated signal wherein:  
 said signal delay means comprises at least one signal translating device exhibiting a predetermined delay in response to positive-going and negative-going transitions of said squared signal wave. said predetermined delay determining the width of said pulses of said output signal.  
 6. Apparatus in accordance with claim 1 wherein:  
 said delay means comprises a plurality of signal amplifying stages, each said stage exhibiting a delay whereby the width of said output pulses is determined by the sum of the signal delays of said amplifying stage.  
 7. Apparatus in accordance with claim 1 wherein:  
 said amplifying stages are similarly constructed and are operating in a common thermal environment.  
 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION PATENT NO. 3 7 470 DATED 1 April 15 1975 INVENTOWS) 1 Charles D. Boltz, Jr.  
  It is certified that error appears in the above-identified patent and that said Letters Patent are hereby corrected as shown below: 7 On title sheet under Foreign Application Priority Data that portion reading &#34;Aug. 18, 1973 United Kingdom 38708/73&#34; should read Aug. 18, 1972 United Kingdon 38708/72 On title sheet under Other Publications that portion reading &#34;Smith, Voltage pulse Width Select Circuit&#34; Vol. 7, No. l, June 1964 IBM Tech. Disclosure Bulletin, p. 27&#34; should read Voltage Pulse Width Select Circuit, Vol. 7, No. 1, June 1964 IBM Tech. Disclosure Bulletin, p. 27, 328-112 Column 4, line 23 after &#34;signal&#34; insert from source 150 En&#39;gncd and Scaled this twenty-fifth Day Of November-1975 [SEAL] A ttes t:  
 RUTH c. MASON c. MARSHALL DANN Arresting Officer Commissioner uj&#39;latenls and Trademarks