Patent Publication Number: US-2016231761-A1

Title: Low dropout regulator with hysteretic control

Description:
CLAIM OF PRIORITY 
     The present application is a continuation of co-pending U.S. patent application Ser. No. 13/626,366, titled “Low Dropout Regulator with Hysteretic Control,” that was filed on Sep. 25, 2012, and which is incorporated by reference in its entirety. 
    
    
     BACKGROUND 
     Typical low dropout (LDO) regulator has analog control and slow response. The minimum dropout of the LDO regulator is limited by the pass gate in saturation, yielding reduced output range, maximum efficiency achievable, and may suffer from stability issues during fast power state changes. For example, when power state shifts from an idle state to a wakeup state, stability issues may arise. Typical LDO regulator also exhibits good efficiency at conversion ratios close to one. Switched Capacitor Voltage Regulators (SCVRs) on the other hand exhibit high efficiency across wide range of output voltage and currents. SCVRs also exhibit response times in the order of few nanoseconds, making them great candidates for dynamic voltage and frequency scaling (DVFS). However, SCVR show limited current supplying capabilities per unit area determined by a capacitor. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. 
         FIG. 1  is a low dropout (LDO) regulator with hysteresis unit, according to one embodiment of the disclosure. 
         FIG. 2  is a detailed view of the LDO regulator with the hysteresis unit, according to one embodiment of the disclosure. 
         FIGS. 3A-B  illustrate a charge pump of the LDO regulator, according to one embodiment of the disclosure. 
         FIG. 4  is an adaptive bias unit of the LDO regulator, according to one embodiment of the disclosure. 
         FIG. 5A  is an embedded LDO in an SCVR operating in a switch capacitor mode, according to one embodiment of the disclosure. 
         FIG. 5B  is an embedded LDO in an SCVR operating in a LDO mode, according to one embodiment of the disclosure. 
         FIG. 6  is a detailed view of an embedded LDO in an SCVR operating in a LDO mode with hysteresis unit, according to one embodiment of the disclosure. 
         FIG. 7  is an LDO with a plurality of charge pumps, according to one embodiment of the disclosure. 
         FIG. 8  is an embedded LDO in an SCVR operating in LDO mode, according to another embodiment of the disclosure. 
         FIG. 9  is logic for controlling the output stage of the LDO of  FIG. 7 , according to one embodiment of the disclosure. 
         FIG. 10  is a charge pump of the LDO of  FIG. 7 , according to one embodiment of the disclosure. 
         FIG. 11  is a system-level diagram of a smart device comprising a processor with the LDO regulator, according to one embodiment of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The embodiments herein describe an embedded LDO within an SCVR that allows conversion of an SCVR to an LDO. In some embodiments, a hysteresis control is introduced to allow using a lower bandwidth amplifier to reduce power consumption, and at the same time enhance response time. For example, the hysteresis control provides for digital control of the LDO when the output voltage from the LDO overshoots or undershoots relative to a predetermined level. The LDO discussed herein may generate ultra-fast response time, with 99% current efficiency. 
     The embodiments discussed herein also enable an LDO to have SCVR like response times, and eliminates or reduces stability issues. In one embodiment, the LDO extends the VR current capability when enabled within SCVR in wide output applications. In such an embodiment, the LDO embedded in the SCVR provides better efficiency (than an SCVR without an embedded LDO), better usability range of voltage, higher speed and improved stability in applications where output electrical characteristics are close to input electrical characteristics. 
     The embodiments herein apply digital control to enhance control speed of signals compared to analog signals. The digital control scheme also allows for scaling of the design across process technologies. Other technical effects will be evident from various embodiments discussed herein. 
     The term “scaling” herein refers to converting a design (schematic and layout) from one process technology to another process technology. 
     In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure. 
     Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme. 
     Throughout the specification, and in the claims, the term “connected” means a direct electrical connection between the things that are connected, without any intermediary devices. The term “coupled” means either a direct electrical connection between the things that are connected, or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” means at least one current signal, voltage signal or data/clock signal. The meaning of “a”, “an”, and “the” include plural references. The meaning of “in” includes “in” and “on.” The terms “substantially,” “close,” “approximately,” herein refer to being within +/−20% of a target value. 
     As used herein, unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner. 
     For purposes of the embodiments described herein, the transistors are metal oxide semiconductor (MOS) transistors, which include drain, source, gate, and bulk terminals. Source and drain terminals may be identical terminals and are interchangeably used herein. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors—BJT PNP/NPN, BiCMOS, CMOS, eFET, etc., may be used without departing from the scope of the disclosure. The terms “MN” herein indicates an n-type transistor (e.g., NMOS, NPN BJT, etc) and the term “MP” indicates a p-type transistor (e.g., PMOS, PNP BJT, etc). 
       FIG. 1  is an LDO regulator  100  with hysteresis unit, according to one embodiment of the disclosure. In one embodiment, LDO regulator  100  comprises an amplifier (also called an error amplifier)  101 , an output stage  102 , and a hysteresis unit  103 . In one embodiment, LDO  100  provides a regulated output voltage Vout to a load  104 , where Vout is a regulated version of the input voltage Vin. 
     In one embodiment, the load  104  is a processor core. In one embodiment, the load  104  is a cache/memory. In one embodiment, the load  104  is any logic portion of the processor core. In other embodiments, load  104  is a group of logic units in a voltage domain that operate on the same power supply level. For example, a group of logic units are input-output (I/O) buffers of the processor (not shown). 
     In one embodiment, amplifier  101  drives a gate terminal of a transistor (not shown) of the output stage  102  which receives an input power supply Vin and provides a regulated voltage Vout to the load  104 . In one embodiment, output power supply Vout, or its divided version (e.g., Vout/2) is compared with a reference voltage Vref by the amplifier  101 . 
     In one embodiment, Vref is generated by a bias circuit (not shown). For example, Vref is generated by a bandgap reference circuit. In another example, Vref is generated by a resistor voltage divider. In another example, Vref is generated externally from the processor and routed inside the processor via a pin. In other embodiments, Vref may be generated by other sources. 
     This negative feedback sets the voltage of the gate terminal of M 1  so that Vout is substantially equal to Vref. In one embodiment, hysteresis unit  103  monitors the output voltage Vout to determine whether Vout is undershooting or overshooting relative to a predetermined reference level. In one embodiment, the predetermined reference level is “Vref+delta” (e.g., Vref+20 mv) for determining an overshoot. In one embodiment, the predetermined reference level for determining undershoot is “Vref−delta” (e.g., Vref−20 mV). 
     The LDO regulation is manifested when the load current changes (e.g., because the demand for current increased by the load  104 ) which in turn causes the voltage Vout to lower its previous value. A lower level of Vout causes the amplifier  101  to turn on the output stage transistor (not shown) harder to raise the level of Vout to be substantially equal to Vref, and thus regulating Vout. In one embodiment, when Vout undershoots below “Vref−delta,” then the hysteresis unit  103  adjusts the output opout of the amplifier  101  to cause the output stage  102  to raise the voltage level of Vout. In one embodiment, when Vout overshoots below “Vref+delta,” then the hysteresis unit  103  adjusts the output opout of the amplifier  101  to cause the output stage  102  to decrease the voltage level of Vout. In such an embodiment, the hysteresis unit  103  allows the design of the amplifier  101  to relax (i.e., the amplifier  101  may not need a fast response time) because the hysteresis unit  103  is performing part of the regulation of Vout. 
       FIG. 2  is a detailed view of the LDO regulator  200  with the hysteresis unit  103 , according to one embodiment of the disclosure.  FIG. 2  is described with reference to  FIG. 1 . 
     In one embodiment, LDO regulator  200  comprises an output stage (e.g.,  102  of  FIG. 1 ) having one or more output stages to provide regulated power supply Vout to the load  104 . In the embodiments discussed herein the load  104  is represented as a lumped RC network comprising a load resistor R load  in parallel to the load capacitor C load . However, the load  104  may comprise a distributed RC network. 
     In one embodiment, output stage  102  comprises a first stage  201  coupled to the amplifier  101 ; a second stage  202  operable to be selectively turned on or off by the hysteresis unit  102 ; and a third stage  203  operable to be selectively turned on or off by the hysteresis unit  102 . 
     In one embodiment, first stage  201  comprises a p-type transistor MP 1   1  with its gate terminal coupled to the output of the amplifier  101 , its drain terminal coupled to the output supply node Vout and its source terminal coupled to the input supply node having supply Vin. In this embodiment, the first stage  201  is normally turned on i.e., MP 1   1  is conducting. 
     In one embodiment, second stage  202  comprises a p-type transistor MP 1   2  with its source and drain terminals coupled to the input supply node Vin and the output supply node Vout respectively. In one embodiment, gate terminal of MP 1   2  is operable to be coupled to the output of the amplifier  101  or the input supply node Vin via a first selection unit  208 . In one embodiment, first selection unit  208  is controlled by the hysteresis unit  103 . In one embodiment, first selection unit  208  is a multiplexer with a select input controlled by the hysteresis unit  103 . In one embodiment, second stage  202  provides overshoot protection to the node Vout and is normally turned on i.e., the p-type transistor MP 1   2  is normally turned on and is turned off by the hysteresis unit  103  if overshoot is detected on the node Vout. 
     In one embodiment, third stage  203  comprises a p-type transistor MP 1   3  with its source and drain terminals coupled to the input supply node Vin and the output supply node Vout respectively. In one embodiment, gate terminal of MP 1   3  is operable to be coupled to the output of a bias circuit  204  (also called adaptive bias circuit) or the input supply node Vin via a second selection unit  209 . In one embodiment, second selection unit  209  is controlled by the hysteresis unit  103 . In one embodiment, second selection unit  209  is a multiplexer with a select input controlled by the hysteresis unit  103 . In one embodiment, third stage  203  provides undershoot protection to the node Vout and is normally turned off i.e., the p-type transistor MP 1   3  is normally turned off and is turned on by the hysteresis unit  103  if undershoot is detected on the node Vout. 
     In one embodiment, hysteresis unit  103  comprises a first comparator or amplifier  206  and a second comparator or amplifier  207 . In one embodiment, first comparator  206  generates the control signal for the first selection unit  208 . In this embodiment, first comparator  206  compares the output voltage Vout with “Vref+delta” to determine when to turn off MP 1   2 . Here, Vref is the reference voltage level provided to the amplifier  101  which generates the control voltage for MP 1   1  and MP 1   2  to regulate Vout. In one embodiment, “delta” is 20 mV. In other embodiments, other values of “delta” may be used to determine when to turn off MP 1   2  when overshoot occurs on Vout. 
     For example, when Vout overshoots i.e., Vout rises suddenly above a predetermined level over the steady state (i.e., regulated) Vout level, then the first comparator  206  generates an output which causes the first selection unit  208  to select Vin as input to the gate terminal of MP 1   2 . In such an embodiment, MP 1   2  is turned off during the overshoot period. Once the overshoot subsides because MP 1   2  is no longer providing extra charge to the node Vout, then MP 1   2  is turned on by the first comparator  206  when Vout falls below “Vref+delta.” 
     In one embodiment, second comparator  207  generates the control signal for the second selection unit  209 . In this embodiment, second comparator  207  compares the output voltage Vout with “Vref−delta” to determine when to turn on MP 1   3 . Here, Vref is the reference voltage level provided to the amplifier  101  which generates the control voltage for MP 1   1  and MP 1   2  to regulate Vout. In one embodiment, “delta” is 20 mV. In other embodiments, other values of “delta” may be used to determine when to turn on MP 1   3  when undershoot occurs on Vout. 
     For example, when Vout undershoots i.e., Vout falls suddenly below a predetermined level over the steady state (i.e., regulated) Vout level, then the second comparator  207  generates an output which causes the second selection unit  209  to select a bias voltage from the bias circuit  204 . In one embodiment, bias voltage from the bias circuit  204  is provided as input to the gate terminal of MP 1   3  to turn on MP 1   3  to cause Vout to rise back to its steady state level. In such an embodiment, MP 1   3  is turned on during undershoot period. Once undershoot subsides because MP 1   3  provides extra charge to the node Vout, then MP 1   3  is turned off by the second comparator  207  when Vout rises above “Vref−delta.” In such an embodiment, the output of the second comparator  207  causes the second selection unit  209  to select Vin as input to MP 1   3  to cause it to turn off. 
     In one embodiment, first and second comparators  206  and  207  are clocked comparators. For example, first and second comparators  206  and  207  generate an output on a transition event of a clock signal received by the first and second comparators  206  and  207 . In other embodiments, outputs of the first and second comparators  206  and  207  are asynchronous outputs i.e., not aligned to clock signal transitions. 
     In one embodiment, bias circuit  204  generates a bias signal for adjusting the current strength of MP 1   3 . For example, the bias circuit  204  generates a charging current for adjusting current strength of MP 1   3 , wherein the bias circuit is operable to adjust the charging current according to the reference voltage Vref. In one embodiment, bias circuit  204  comprises a replica regulator including an amplifier (like amplifier  101 ), an output stage (like MP 1   1 ), and a feedback path (like Vout). 
       FIG. 4  is an adaptive bias unit  400  (e.g., bias circuit  204 ), according to one embodiment of the disclosure. In this embodiment, adaptive bias unit  400  is a replica regulator comprising amplifier  401  (same as amplifier  101  of  FIG. 1 ), output stage transistor MP 1  (same as MP 1   1  of  FIG. 2 ), and a feedback network coupling MP 1  to an input of the amplifier  401 . In one embodiment, output of the amplifier  401  is used as input to the second selector unit  209 . In one embodiment, adaptive bias unit  400  behaves as part of a current mirror, where the current through MP 1  of adaptive bias unit  400  is mirrored on MP 1   3  of the third stage  203 . For example, when MP 1   3  is 60 times larger in width than MP 1  of adaptive bias unit  400 , then the output voltage of the amplifier  401  which is received by the gate terminal of MP 1   3  of the third stage  203  via the second selection unit  203 , larger current flows through MP 1   3  which allows MP 1   3  to cancel the effect of undershoot on Vout. 
     In one embodiment, adaptive bias unit  400  comprises another p-type transistor MP 2  coupled in series with MP 1 , where MP 2  is always turned on. In one embodiment, MP 2  is a replica transistor for the MP 2   3  in  FIG. 6 . For a stand-alone LDO as the one in  FIG. 2 , this MP 2  is not needed. In one embodiment, the feedback path is coupled from a resistor divider network which is coupled to MP 2  as shown. In one embodiment the resistors are 5KΩs. In other embodiments, other values of resistors may be used. 
     Referring back to  FIG. 2 , in one embodiment LDO  200  comprises a charge pump  205  which is coupled to an output of the amplifier  101 . In one embodiment, charge pump  205  is operable to adjust a voltage level of the output of the amplifier  101 . For example, the charge pump  205  adds charge to the output of the amplifier  101  when the output supply Vout overshoots relative to a first predetermined threshold. In one embodiment, charge pump  205  is operable to subtract charge from the output of the amplifier  101  when the output supply Vout undershoots relative to a second predetermined threshold. In one embodiment, the second predetermined threshold is different from the first predetermined threshold. For example, the second predetermined threshold is “Vref−delta” and the first predetermined threshold is “Vref+delta.” 
     In one embodiment, charge pump  205  accelerates the settling of the output of the amplifier  101  when Vout is outside the boundaries of the first and second predetermined thresholds. For example, charge pump  205  is activated when Vout is greater than “Vref+delta” or less than “Vref−delta.” In one embodiment, charge pump  205  is not activated when Vout is within the boundaries of the first and second predetermined thresholds. For example, charge pump  205  is deactivated when Vout is less than “Vref+delta” and greater than “Vref−delta.” In such an embodiment, charge pump  205  does not affect the stability of the LDO  200 . 
       FIG. 3A  illustrates a charge pump  300  (e.g., charge pump  205 ), according to one embodiment of the disclosure.  FIG. 3A  is described with reference to  FIG. 2  and  FIG. 3B  which illustrates the hysteresis unit  103  of the LDO regulator  200 / 100 , according to one embodiment of the disclosure. In one embodiment, charge pump  300  comprises a p-type transistor MP, an n-type transistor MN, resistors R 1  and R 2 , and capacitor C. 
     In one embodiment, MP is coupled to the input power supply Vin and a first terminal of the resistor R 1 , where the source terminal of MP is coupled to the supply node Vin, the drain terminal of MP is coupled to the first terminal of R 1 , and the gate terminal of MP is controlled by “Vout_high_b” which is the inverse of the output “Vout_high” of the first comparator  206 . Here, “Vout_high_b” indicates an inverse of “Vout_high.” 
     In one embodiment, MN is coupled to ground and a first terminal of the resistor R 2 , where the source terminal of MN is coupled to ground, the drain terminal of MN is coupled to the first terminal of R 2 , and the gate terminal of MN is controlled by “Vout_low” which is the inverse of the output “Vout_low_b” of the second comparator  207 . In one embodiment, charge pump  300  charges or discharges the output node of the amplifier  101  depending on the outputs of the first and second comparators  206  and  207  respectively. In such an embodiment, charge pump  300  improves the response time of the LDO  200  because the amplifier  101 , which is analog in nature, generally takes longer to respond to changes in Vout (caused by, for example, load changes in load  104 ) under constraints such as loop stability and power budget. 
     In one embodiment, second terminal of R 2  is coupled to the second terminal of R 1  as shown, where the second terminals of R 2  and R 1  provide the output of the charge pump  300 . In one embodiment, a capacitor C is added to the output of the charge pump (also the output of the amplifier  101 ) to provide loop stability across various temperatures and load conditions. In one embodiment, resistors R 1  and R 2  have resistance of 400 Ωs. In other embodiments, other resistances of resistors R 1  and R 2  may be used. In one embodiment, the capacitance of capacitor C is 100 pF. In other embodiments, other capacitance values of capacitor C may be used to provide a phase margin for a stable loop (e.g., a phase margin greater than 45 degrees). 
       FIG. 5A  is an embedded LDO in an SCVR  500  operating in a switch capacitor mode, according to one embodiment of the disclosure. In one embodiment, embedded LDO in the SCVR  500  comprises amplifier  501  (e.g., same as amplifier  101 ), p-type transistors MP 1 , MP 2 , and MP 3 , n-type transistor MN 1 , and fly capacitor C fly . In one embodiment, embedded LDO in the SCVR  500  regulates the voltage Vout, based on the input voltage Vin, provided to the load  504 . 
     In one embodiment, embedded LDO in the SCVR  500  also comprises a coarse control unit  502  to provide initial voltage Phi_ 2  while the amplifier  501  is still determining a response for changing Vout. In one embodiment, in steady state the coarse control unit  502  is deactivated. In one embodiment, coarse control unit  502  is activated when there is a transient changes to Vout caused by, for example, change in load conditions. 
     In one embodiment, when the embedded LDO in the SCVR  500  is operating in switch capacitor mode, MP 2  and MN 1  are turned off in a first phase of the SCVR operation. In this embodiment, both Phi_ 2  and Phi_ 1  are logically low. In one embodiment, when Phi_ 2  is logically low, MP 1  is turned on and when Phi_ 1  is logically low, MP 3  is turned on causing C fly  to store Vin−Vout. In one embodiment, in a second phase of the SCVR operation, Phi_ 2  and Ph_ 1  are logically high. In such an embodiment, both MP 1  and MP 3  are turned off. In one embodiment, during the second phase, MP 2  and MN 1  are turned on (control circuitry not shown), coupling C fly  between ground and Vout nodes. The SCVR toggles between the first and the second phase to provide a 2:1 voltage conversion from Vin to Vout. 
       FIG. 5B  is an embedded LDO in an SCVR  520  operating in a LDO mode, according to one embodiment of the disclosure. So as not to obscure the embodiments of the disclosure, differences between  FIG. 5A  and  FIG. 5B  are discussed.  FIG. 5B  is similar to  FIG. 5A  except that MP 3  is turned off, MP 2  is turned on (gate terminal tied to ground or logical low level), and C fly  behaves like a decoupling capacitor between the terminals of MP 1  and MN 1 , which causes the circuit topology to operate in LDO mode as opposed to switch capacitor mode. In one embodiment, MN 1  may be either turned on or off. For example, when a decoupling capacitor is needed, MN 1  is turned on. 
       FIG. 6  is a detailed view of an embedded LDO in an SCVR  600  operating in LDO mode with hysteresis unit, according to one embodiment of the disclosure. The embodiment of  FIG. 6  is discussed with reference to  FIGS. 5A-B . The embodiment of  FIG. 6  is similar to the embodiment of  FIG. 2  except that the SCVR topology is converted into an LDO. So as not to obscure the embodiments of the disclosure, differences between  FIG. 2  and  FIG. 6  are discussed. 
     In one an embodiment, first  601 , second  602 , and third  603  stages are configured so that MP 2  (of  FIG. 5A ), which are represented as MP 2   1 , MP 2   2 , and MP 2   3  of the first stage  601 , the second stage  602 , and the third stage  603  respectively, are turned on. While the embodiment of  FIG. 6  shows a ground node coupled to the gate terminals of MP 2   1 , MP 2   2 , and MP 2   3 , a logical signal with a logical low level may be provided to the gate terminals of MP 2   1 , MP 2   2 , and MP 2   3  to turn the transistors on. 
     In this embodiment, first  601 , second  602 , and third  603  stages are configured so that MN 1  (of  FIG. 5A ), which are represented as MN 1   1 , MN 1   2 , and MN 1   3  of the first stage  601 , the second stage  602 , and the third stage  603  respectively, are turned on. While the embodiment of  FIG. 6  shows a power supply node coupled to the gate terminals of MN 1   1 , MN 1   2 , and MN 1   3 , a logical signal with a logical high level may be provided to the gate terminals of MN 1   1 , MN 1   2 , and MN 1   3  to turn the transistors on. In this embodiment, the fly capacitor C fly  of  FIG. 5A  operates as a decoupling capacitor between Vout and ground because transistors MP 2   1 , MP 2   2 , and MP 2   3  and MN 1   1 , MN 1   2 , and MN 1   3  are turned on. In one embodiment, MN 1   1 -MN 1   3  can be turned off if capacitor C fly  is not needed as decoupling capacitor. In such an embodiment, the functionality of the embedded LDO operating in LDO mode will not be affected. 
       FIG. 7  is an LDO  700  with a plurality of charge pumps, according to one embodiment of the disclosure. In one embodiment, LDO  700  comprises a logic unit  701  including a plurality of comparators/amplifiers  701   a - d , a charge pump unit including a plurality of charge pumps  702   a - d , and an output stage  703  providing regulated power supply Vout to the load  704 . 
     In one embodiment, output stage  703  is coupled to an input supply Vin (also called input supply node) and provides a regulated power supply Vout to the load  704 . In one embodiment, the input supply Vin is generated off chip and provided to the chip to generated internal power supplied e.g., Vout. In other embodiments, Vin is an internally generated supply (i.e., power supply generated on die). 
     In one embodiment, output stage  703  comprises a p-type transistor MP 1  with its gate terminal coupled to outputs of the plurality of charge pumps  702   a - d . In such an embodiment, the source terminal of MP 1  is coupled to the input supply node Vin, and its drain terminal coupled to the output supply providing Vout to the load  704 . In one embodiment, plurality of charge pumps  702   a - d  is capable of adjusting current strength of the output stage  703  to regulate the power supply Vout. 
     In one embodiment, logic unit  701  monitors the output supply Vout and is operable to control the plurality of charge pumps  702   a - d  according to a voltage level of the output supply Vout and one or more reference voltages—“Vref,” “Vref+d 1 ,” “Vref+d 2 ,” “Vref+d 3 ,” where “Vref+d 3 ” is greater than “Vref+d 2 ” which is greater than “Vref+d 1 ” which is greater than “Vref.” In one embodiment, “d 1 ” and d 3  are 10 mV, and “d 3 ” is 50 mV. In other embodiments, other voltage levels may be used for “d 1 ,” “d 2 ,” and “d 3 .” In one embodiment, when d 1 =d 2 , comparators  701   a  and  701   b  can be combined into a single comparator. 
     In one embodiment, reference voltages—“Vref,” “Vref+d 1 ,” “Vref+d 2 ,” “Vref+d 3 ”—are generated by a resistor divider network. In other embodiments, the reference voltages are generated by bandgap circuits. In another embodiment, the reference voltages are generated off chip by any reference generator and transmitted to the processor having the LDO  700 . In other embodiments, other means for generating the reference voltages may be used. 
     In one embodiment, logic unit  701  comprises a set of comparators  701   a - d  used for regulating the output voltage Vout within first and second predetermined levels determined by first and second reference voltage levels “Vref+d 2 ” and “Vref+d 1 ,” respectively. 
     In one embodiment, first and second comparators  701   a - b  are coupled to first and second charge pumps  702   a - b  via nodes  705   a  and  705   b  respectively. In one embodiment, first comparator  701   a  causes the first charge pump  702   a , from the plurality of charge pumps, to reduce drive strength of the output stage  703  when the output supply Vout is greater than the first reference voltage “Vref+d 2 .” In such an embodiment, when the output stage comprises a p-type transistor MP 1 , the first charge pump  702   a  is operable to add charge to the gate terminal of MP 1  when the first comparator  701   a  indicates (on node  705   a ) that output supply Vout is greater than the first reference voltage “Vref+d 2 .” As the voltage of the gate terminal MP 1  increases because of the added charge by the charge pump  702   a , MP 1  sources less current to Vout causing Vout to fall below “Vref+d 2 ” or be substantially close to “Vref+d 2 .” 
     In one embodiment, second comparator  701   b  causes the second charge pump  702   b , from the plurality of charge pumps, to increase drive strength of the output stage  703  when the output supply Vout is less than the second reference voltage “Vref+d 1 .” In such an embodiment, when the output stage comprises a p-type transistor MP 1 , the second charge pump  702   b  is operable to subtract charge from the gate terminal of MP 1  when the second comparator  701   b  indicates (on node  705   b ) that output supply Vout is less than the second reference voltage “Vref+d 1 .” As the voltage of the gate terminal MP 1  decreases because of the subtracted charge by the charge pump  702   b , MP 1  sources more current to Vout causing Vout to rise above “Vref+d 1 ” or be substantially close to “Vref+d 1 .” 
     In one embodiment, logic unit  701  comprises a third comparator  701   c  to cause a third charge pump  702   c , from the plurality of charge pumps, to reduce drive strength of the output stage  703  when the output supply Vout is greater than the third reference voltage “Vref.” One technical effect of the third comparator  701   c  and the third charge pump  702   c  is to provide a boost to the output supply Vout when Vout undershoots below the third reference level “Vref.” In such an embodiment, when the output stage comprises a p-type transistor MP 1 , the third charge pump  702   c  is operable to subtract charge from the gate terminal of MP 1  when the third comparator  701   c  indicates (on node  705   c ) that output supply Vout is less than the third reference voltage “Vref.” As the voltage of the gate terminal MP 1  decreases because of the subtracted charge by the charge pump  702   c , MP 1  sources more current to Vout causing Vout to rise above “Vref” or be substantially close to “Vref.” In one embodiment, second comparator  701   b  and the second charge pump  702   b  continue to provide charge to Vout to bring Vout substantially close to “Vref+d 1 .” 
     In one embodiment, logic unit  701  comprises: a fourth comparator  701   d  to cause the fourth charge pump  702   d , from the plurality of charge pumps, to increase drive strength of the output stage  703  when the output supply Vout is less than the fourth reference voltage “Vref+d 3 .” One technical effect of the fourth comparator  701   d  and the fourth charge pump  702   d  is to squelch the output supply Vout when Vout overshoots above the fourth reference level “Vref+d 3 .” In such an embodiment, when the output stage  703  comprises a p-type transistor MP 1 , the fourth charge pump  702   d  is operable to add charge to the gate terminal of MP 1  when the fourth comparator  701   d  indicates (on node  705   d ) that output supply Vout is greater than the fourth reference voltage “Vref+d 3 .” As the voltage of the gate terminal MP 1  increases because of the added charge by the fourth charge pump  702   d , MP 1  sources less current to Vout causing Vout to fall below “Vref+d 3 ” or be substantially close to “Vref+d 3 .” In one embodiment, first comparator  701   a  and the first charge pump  702   a  continue to reduce Vout to bring Vout substantially close to “Vref+d 2 .” 
     While the embodiment of  FIG. 7  shows that the outputs of the charge pumps  702   a - d  are shorted together and coupled to the same gate terminal of MP 1 , in one embodiment the outputs of each charge pump are coupled to different output stage drivers. In one embodiment, the charge pumps have different driving strengths. 
     For example, third and fourth charge pumps  702   c  and  702   d  may have higher charging/discharging strengths compared to the first and second charge pumps  702   a  and  702   b  for fast boost from undershoot of Vout and fast squelch of overshoot of Vout. In such an embodiment, third and fourth comparators  701   c  and  701   d  and third and fourth charge pumps  702   c  and  702   d  provide the hysteresis function of hysteresis unit  203  of  FIG. 2 . In one embodiment, pre-driver transistors (not shown) of the output stage  703  are used for providing extra current path from Vin to Vout during an undershoot event on Vout, where the pre-driver transistors are controlled by third charge pump  702   c.    
     In one embodiment, plurality of charge pumps  702   a - d  is implemented as circuits shown in  FIG. 3A . In other embodiments, other implementations of the charge pumps  702   a - d  may be used. 
     Referring back to  FIG. 7 , in one embodiment comparators  701   a - d  are clock gated comparators. In such an embodiment, Vout is updated according to a speed of a clock signal used by the clock gated comparators. In one embodiment, additional combinational logic is coupled to the comparators  701   a - d  to control when to turn on or off the comparators and/or charge pumps to control the strength of the output stage. In other embodiments, any form of comparators may be used. 
       FIG. 8  is an embedded LDO in an SCVR  800  operating in LDO mode, according to another embodiment of the disclosure. The embodiment of  FIG. 8  is similar to  FIG. 7  except that the output stage is reconfigured to convert an SCVR into an LDO. Accordingly, transistors MP 2  and MN 1  are turned on. 
     In one embodiment, MP 3  is turned off, converting the SCVR similar to  FIG. 5A  to an integrated LDO stage. In this embodiment, the additional series resistance of MP 2  is added to the LDO output stage compared to the embodiment of  FIG. 7 . One technical effect of the additional series resistance is to reduce the maximum output current for identical device sizes compared to the embodiment of  FIG. 7 . In one embodiment, an additional output filter comprising the resistances of MN 1  and MP 2  and the capacitance Cfly is available in the embedded LDO in the SCVR  800 . In such an embodiment, the additional filter improves output droop response of the LDO utilizing the available SCVR capacitance by turning on MN 1 . 
       FIG. 9  is logic  900  for controlling the output stage  703  of the LDO of  FIG. 7 , according to one embodiment of the disclosure. In one embodiment, logic  900  comprises combinational logic  901 , an ‘N’ bit counter  902 , and control logic  903  to control the gate of the charge pumps  702   a - d.    
     In one embodiment, combinational logic  901  comprises the comparators  701   a - d  and other logic that determine whether Vout is above or below “Vref,” “Vref+d 1 ,” “Vref+d 2 ,” and “Vref+d 3 .” In one embodiment, the combinational logic  901  is reduced to the comparators of  FIG. 8 . In another embodiment, counter  902  determines the strength of the charge pump  903  to improve stability and response time of the LDO with different load and PVT (process, temperature and voltage) conditions. In one embodiment, for low load currents, the counter  902  changes its count in one direction whereas for relatively higher load currents the counter  902  changes its count in the opposite direction. In such an embodiment, the actual direction of count of the counter  902  depends on the transistors of the charge pump  903  and is not limiting to the scope of the disclosure. In another embodiment, counter  902  may be controlled depending on a variety of input and load conditions without change in design. 
     In one embodiment, the charge pump  903  is fixed in strength with reference to  FIG. 8 . In another embodiment, the strength of the charge pump  903  is controlled by the counter  902  and can charge or discharge the gate of MP 1  at a different rate. In one embodiment, the strength of the charge pump  903  may be changed in a linear fashion. In one embodiment, the strength of the charge pump  903  may be changed in a binary-weighted fashion. In another embodiment, the strength of the charge pump  903  may be a deterministic non-linear or an arbitrary function of the value of the controller  902 &#39;s output. 
       FIG. 10  is a charge pump  1000  of the LDO of  FIG. 7 , according to one embodiment of the disclosure. In one embodiment, charge pump  1000  comprises a weighted transistor array  1001  and a weighted resistor array  1002 . In one embodiment, weighted transistor array  1001  comprises n-type transistors coupled together as shown. In one embodiment, weighted transistor array  1001  is binary weighted. In other embodiments, other weighting techniques may be used. For example, thermometer weighting technique may be used. 
     In one embodiment, resistor array  1002  comprises transistors like the transistors of  1001  but with additional series resistors as shown. In one embodiment, resistor array  1002  and the transistor array  1001  are coupled together at node  1003  which is input to the gate terminal of MP 1  of the output stage  703 . In one embodiment, the transistors and resistors may be weighted in a linear or any arbitrary function of the input bits&lt;5:0&gt;, where “&lt;5:0&gt;” indicates a 6-bit bus. In one embodiment, the charge pump  1001  is the charge pump  702   c  of  FIG. 7  while the charge pump  1002  is the charge pump  702   b  of  FIG. 7 . In one embodiment, charge pumps  702   a  and  702   d  are complementary to charge pumps  702   b  and  702   c . In one embodiment, the charge pumps  702 - d  may have different strengths/sizes. 
       FIG. 11  is a system-level diagram of a smart device  1600  comprising a processor with the LDO regulator, according to one embodiment of the disclosure.  FIG. 11  also illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In one embodiment, computing device  1600  represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in device  1600 . 
     In one embodiment, computing device  1600  includes a first processor  1610  with the digitally phase locked LDO (e.g.,  100 ,  200 ,  600 ,  700 ,  800 ) and a second processor  1690  with the digitally phase locked LDO (e.g.,  100 ,  200 ,  600 ,  700 ,  800 ), according to the embodiments discussed herein. The various embodiments of the present disclosure may also comprise a network interface within  1670  such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant. 
     In one embodiment, processor  1610  can include one or more physical devices, such as microprocessors, application processors, microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor  1610  include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device  1600  to another device. The processing operations may also include operations related to audio I/O and/or display I/O. 
     In one embodiment, computing device  1600  includes audio subsystem  1620 , which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into device  1600 , or connected to the computing device  1600 . In one embodiment, a user interacts with the computing device  1600  by providing audio commands that are received and processed by processor  1610 . 
     Display subsystem  1630  represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device. Display subsystem  1630  includes display interface  1632 , which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface  1632  includes logic separate from processor  1610  to perform at least some processing related to the display. In one embodiment, display subsystem  1630  includes a touch screen (or touch pad) device that provides both output and input to a user. 
     I/O controller  1640  represents hardware devices and software components related to interaction with a user. I/O controller  1640  is operable to manage hardware that is part of audio subsystem  1620  and/or display subsystem  1630 . Additionally, I/O controller  1640  illustrates a connection point for additional devices that connect to device  1600  through which a user might interact with the system. For example, devices that can be attached to the computing device  1600  might include microphone devices, speaker or stereo systems, video systems or other display device, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices. 
     As mentioned above, I/O controller  1640  can interact with audio subsystem  1620  and/or display subsystem  1630 . For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device  1600 . Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller  1640 . There can also be additional buttons or switches on the computing device  1600  to provide I/O functions managed by I/O controller  1640 . 
     In one embodiment, I/O controller  1640  manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device  1600 . The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features). 
     In one embodiment, computing device  1600  includes power management  1650  that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem  1660  includes memory devices for storing information in device  1600 . Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory  1660  can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device  1600 . 
     Elements of embodiments are also provided as a machine-readable medium (e.g., memory  1660 ) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory  1660 ) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, or other type of machine-readable media suitable for storing electronic or computer-executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection). 
     Connectivity  1670  includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device  1600  to communicate with external devices. The device  1600  could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices. 
     Connectivity  1670  can include multiple different types of connectivity. To generalize, the computing device  1600  is illustrated with cellular connectivity  1672  and wireless connectivity  1674 . Cellular connectivity  1672  refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity  1674  refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication. 
     Peripheral connections  1680  include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device  1600  could both be a peripheral device (“to”  1682 ) to other computing devices, as well as have peripheral devices (“from”  1684 ) connected to it. The computing device  1600  commonly has a “docking” connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on device  1600 . Additionally, a docking connector can allow device  1600  to connect to certain peripherals that allow the computing device  1600  to control content output, for example, to audiovisual or other systems. 
     In addition to a proprietary docking connector or other proprietary connection hardware, the computing device  1600  can make peripheral connections  1680  via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other type. 
     Reference in the specification to “an embodiment,” “one embodiment,” “some embodiments,” or “other embodiments” means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of “an embodiment,” “one embodiment,” or “some embodiments” are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic “may,” “might,” or “could” be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to “a” or “an” element, that does not mean there is only one of the elements. If the specification or claims refer to “an additional” element, that does not preclude there being more than one of the additional element. 
     Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive. 
     While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims. 
     In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented i.e., such specifics should be well within purview of one skilled in the art. Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting. 
     The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process. 
     For example, in one embodiment, the apparatus comprises: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; an amplifier to control current strength of the output stage according to the output supply and a reference voltage; and a hysteresis unit to monitor the output supply and operable to control the current strength of the output stage according to a voltage level of the output supply. 
     In one embodiment, the output stage comprises: a first stage coupled to the amplifier; and a second stage operable to be selectively turned on or off by the hysteresis unit. In one embodiment, the first and second stages are normally on. In one embodiment, the second stage is operable to be turned off when the output supply overshoots. In one embodiment, the output stage comprises: a third stage operable to be selectively turned on or off by the hysteresis unit. In one embodiment, the third stage is normally off. In one embodiment, the third stage is operable to be turned on when the output supply undershoots. In one embodiment, the first, second, and third stages comprise first, second, and third p-type transistors respectively coupled between the input supply node and the output node. 
     In one embodiment, the hysteresis unit comprises: a first comparator to compare the output supply relative to a first reference, the first comparator to generate a first output to control current strength of the second stage, wherein the first reference is different from the reference voltage. In one embodiment, the hysteresis unit comprises: a second comparator to compare the output supply relative to a second reference, the second comparator to generate a second output to control current strength of the third stage, wherein the second reference is different from the reference voltage. 
     In one embodiment, the apparatus further comprises: a bias circuit coupled to the third stage, the bias circuit to adjust current strength of the third stage. In one embodiment, the bias circuit to generate a charging current for adjusting current strength of the third stage, wherein the bias circuit is operable to adjust the charging current according to the reference voltage. In one embodiment, the bias circuit comprises a replica regulator. 
     In one embodiment, the apparatus further comprises: a charge pump coupled to an output of the amplifier, the charge pump operable to adjust a voltage level of the output of the amplifier. In one embodiment, the charge pump to add charge to the output of the amplifier when the output supply overshoots. In one embodiment, the charge pump to subtract charge from the output of the amplifier when the output supply undershoots. 
     In one embodiment, a system comprises a memory (e.g., DRAM, SRAM, flash, MROM, etc); a processor, coupled to the memory, the processor including a low dropout regulator according to the apparatus discussed herein; and a wireless interface to communicatively couple the processor with another device. In one embodiment, the system further comprises a display unit. 
     In one embodiment, the apparatus comprises: an output stage having an input supply node to receive an input power supply and an output node to provide an output supply to a load; a plurality of charge pumps to adjust current strength of the output stage; and a logic unit to monitor the output supply and operable to control the plurality of charge pumps according to a voltage level of the output supply and one or more reference voltages. 
     In one embodiment, the logic unit comprises: a first comparator to cause a first charge pump, from the plurality of charge pumps, to reduce drive strength of the output stage when the output supply is greater than a first reference voltage. In one embodiment, the logic unit comprises: a second comparator to cause a second charge pump, from the plurality of charge pumps, to increase drive strength of the output stage when the output supply is less than a second reference voltage. In one embodiment, the logic unit comprises: a third comparator to cause a third charge pump, from the plurality of charge pumps, to reduce drive strength of the output stage when the output supply is greater than a third reference voltage. In one embodiment, the logic unit comprises: a fourth comparator to cause a fourth charge pump, from the plurality of charge pumps, to increase drive strength of the output stage when the output supply is less than a fourth reference voltage. 
     In one embodiment, the apparatus further comprises: a reference generator to generate the first, second, third, and fourth reference voltages. In one embodiment, the fourth reference is higher than the first, second, and third voltage references. In one embodiment, the third reference is lower than the first, second, and fourth voltage references. In one embodiment, the first reference is higher than the second and third voltage references. 
     In one embodiment, the output stage comprises a p-type transistor with a gate terminal coupled directly or indirectly to the plurality of charge pumps, a source terminal coupled directly or indirectly to the input supply node, and a drain terminal coupled directly or indirectly to the output node. In one embodiment, the one or more charge pumps from the plurality of charge pumps are operable to have different charging strengths. 
     An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.