Patent Publication Number: US-6211068-B1

Title: Dual damascene process for manufacturing interconnects

Description:
BACKGROUND OF THE INVENTION 
     1. Field of Invention 
     The present invention relates to a method for manufacturing interconnects. More particularly, the present invention relates to a method for manufacturing interconnects using a dual damascene process. 
     2. Description of Related Art 
     In the fabrication of very large scale integrated (VLSI) circuits, semiconductor devices are generally linked by several metallic interconnecting layers commonly referred to as multilevel interconnects. As the level of circuit integration continues to increase, manufacturing processes are complicated and product yield and reliability is harder to maintain. Dual damascene process is a convenient method for forming multilevel interconnects. Principally, the process includes etching a dielectric layer to form trenches, and then depositing metal into the trenches to form the interconnects. The dual damascene process is capable of producing highly reliable interconnects with a relatively high product yield. Due to its versatility, the dual damascene process has become a predominant method for fabricating interconnects. However, several drawbacks in the method still need to be resolved. For example, photoresist (PR) that remains inside a via hole after a photolithographic operation may affect the profile of the via hole. 
     FIGS. 1A through 1C are schematic, cross-sectional views showing the steps taken in carrying out a conventional dual damascene process for fabricating interconnects. As shown in FIG. 1A, a semiconductor substrate  100  having a metallic layer  102  therein is provided. A silicon nitride layer  104  having a thickness of about 500 Å to 1000 Å is formed over the substrate  100 . An inter-layer dielectric layer  106  having a thickness of about 9000 Å to 16000 Å is formed over the silicon nitride layer  104 . A patterned photoresist layer  108  is formed over the inter-layer dielectric layer  106  using photolithographic techniques. Using the patterned photoresist layer  108  as a mask, the dielectric layer  106  is etched to form a via hole  110 . 
     As shown in FIG. 1B, the photoresist layer  108  is removed. Meanwhile, another photoresist layer  112  to define the metal trench is formed over the inter-layer dielectric  106 . Some of the photoresist material is also deposited into the via hole  110 . The photoresist layer  112  is patterned by removing some photoresist material. However, some photoresist material inside the via hole  110  remains and forms a residual photoresist layer  112   a.    
     As shown in FIG. 1C, using the photoresist layer  112  as a mask, an anisotropic etching operation is conducted to form trenches  114  inside the inter-layer dielectric  106 . Subsequent processing steps are not shown in the figure because those steps should be familiar to the people in the semiconductor field. In brief, subsequent steps includes the removal of the photoresist layer  112 , deposition to form a barrier layer and a copper layer and a final planarization using a chemical-mechanical polishing (CMP) method. 
     As shown in FIG. 1C, due to the difficulties in removing away some of the dielectric material in the neighborhood of the residual photoresist  112   a , an undesirable trench profile is often created. In addition, the dielectric layer  106  is typically a silicon dioxide layer, which is a transparent material. Therefore, an anti-reflection coating is frequently required. However, the formation of the silicon nitride layer  104  as an anti-reflection coating between the metallic layer  102  and the dielectric layer  106  is far from ideal. 
     SUMMARY OF THE INVENTION 
     The invention provides a method of forming a dual damascene structure including the formation of a silicon oxynitride layer over an inter-layer dielectric layer that acts as an anti-reflection coating. The additional anti-reflection coating is able to improve the resulting trench profile after the trench-etching step. Furthermore, a portion of the photoresist material inside via holes is removed before carrying out the trench-forming etching operation. Hence, the photoresist layer inside the via hole no longer impedes the etching of dielectric material around the via hole/contact opening areas as in a conventional dual damascene process. 
     The invention provides a dual damascene process for producing interconnects. The dual damascene process includes forming an etching stop layer over a substrate having a conductive layer therein, and forming an inter-layer dielectric layer over the etching stop layer. A mask layer is formed over the dielectric layer. The mask layer and the inter-layer dielectric layer are patterned to form an opening that exposes a portion of the etching stop layer. The opening is formed above the conductive layer. Photoresist material is deposited over the mask layer and into the opening. The photoresist layer and the mask layer are patterned. After patterning, some of the photoresist may remain in the opening and form a photoresist plug at the same time. A top layer of the photoresist plug is removed. Using the patterned photoresist layer and the mask layer as a mask, an anisotropic etching step is carried out to form a plurality of trenches inside the inter-layer dielectric layer. These trenches overlap with the opening. Metal is finally deposited into the opening and the trenches to complete the dual damascene process. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings, 
     FIGS. 1A through 1C are schematic, cross-sectional views showing the steps taken in carrying out a conventional dual damascene process for fabricating interconnects; and 
     FIGS. 2A through 2E are schematic, cross-sectional views showing the steps for forming interconnects using a dual damascene process according to one preferred embodiment of this invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts. 
     FIGS. 2A through 2E are schematic, cross-sectional views showing the steps for forming interconnects using a dual damascene process according to one preferred embodiment of this invention. 
     As shown in FIG. 2A, a semiconductor substrate  200  having a conductive layer  202  such as a word line, a bit line or a metallic line therein is provided. An etching stop layer  204  is formed over the conductive layer  202  and the substrate  200  using, for example, a chemical vapor deposition (CVD) method. The etching stop layer  204  is preferably a silicon nitride layer having a thickness of between about 500 Å and 1000 Å. An inter-layer dielectric layer  206  is formed over the etching stop layer  204  again using, for example, a CVD method. The dielectric layer  206  is preferably a silicon dioxide layer having a thickness of between about 9000 Å and 16000 Å. 
     A mask layer  208  is formed over the dielectric layer  206 . The mask layer  208  can be, for example, either a silicon nitride or a silicon oxynitride layer, but is preferably a silicon oxynitride layer. Typically, the mask layer  208  preferably having a thickness of between about 400 Å and 1000 Å is formed using, for example, a chemical vapor deposition (CVD) method. The dielectric layer  206  and the mask layer  208  are patterned to form an opening  210  such as a via opening or a contact opening. For example, conventional photolithographic and etching processes are used to form a patterned photoresist layer  212  above the mask layer  208 . Using the patterned photoresist layer  212  as a mask, an anisotropic etching step is carried out to form the opening  210  that exposes a portion of the etching stop layer  204 . After that, the photoresist layer  212  is removed. 
     As shown in FIG. 2B, another photoresist layer  214  is formed over the mask layer  208 . Some of the photoresist material is also deposited into the opening  210 . The photoresist layer  214  is patterned. For example, conventional photolithographic and etching processes are used to transfer the pattern of a second interconnect layer onto the photoresist layer  214 . Meanwhile, some of the photoresist material inside the opening  210  is turned into a photoresist plug  214   a . A top surface of photoresist plug  214   a  is lower than a top surface of the via/contact opening  210 . The mask layer  208  is also patterned by transferring the pattern on the photoresist layer  214  to the mask layer  208 . For example, the patterned photoresist layer  214  is used as a mask in an anisotropic etching step so that portions of the mask layer  208  not covered by the photoresist layer  214  are removed. During the etching step, a portion of the dielectric layer  206  is also removed, forming a schematic, cross-sectional profile similar to FIG.  2 B. 
     As shown in FIG. 2C, a top layer having a thickness  215  is removed from the photoresist plug  214   a  to form a shorter photoresist plug  214   b . Photoresist plug material can be removed by performing, for example, a dry etching operation using oxygen plasma. Note that a top layer is also removed from the photoresist layer  214  when the plug  214   b  is etched so that the photoresist layer  214  is thereafter thinner thereafter. 
     As shown in FIG. 2D, using the photoresist layer  214  and the mask  208  as a mask, a portion of the inter-layer dielectric layer  206  is removed to form trenches  216  and  218 . An anisotropic etching operation, for example, can be used to remove dielectric material from the dielectric layer  206 . The trenches  218  overlap with the via/contact openings  210 . Since a top layer of the photoresist plug  214   a  is removed prior to the etching step, height level of the photoresist plug  214   a  no longer affects the ultimate schematic, cross-sectional profile of the trenches. In other words, the trenches not deep enough to make any contact with the upper portion of the photoresist plug  214   b.    
     In addition, due to the presence of the mask layer  208 , the dielectric layer  206  under the mask layer  208  is not affected by the etching step even though the photoresist layer  214  is already quite thin. Thereafter, the remaining photoresist layer  214   b  is removed. 
     Subsequent processing steps include the removal of the portions of the etching stop layer in the opening, the removal of the mask layer, the formation of a barrier layer  220  over the via/contact opening  210  and the deposition of a metallic layer  222  above the barrier layer  220 . Finally, a chemical-mechanical polishing (CMP) operation is performed to remove a portion of the metallic layer  222  and the barrier layer to form a structure as shown in FIG.  2 E. Since these steps are not directly related to the invention, detailed description is omitted. 
     In summary, one major aspect of the invention is the formation of a silicon oxynitride layer above the inter-metal dielectric layer. The silicon oxynitride layer not only serves as a mask, but also functions as an anti-reflection coating. A second aspect of the invention is the removal of some photoresist material from the top of the photoresist plug before a trench-forming etching step is conducted. Hence, an integral trench profile can be obtained. 
     It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.