Patent Publication Number: US-11653490-B2

Title: Semiconductor memory devices

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     Korean Patent Application No. 10-2020-0117044, filed on Sep. 11, 2020, in the Korean Intellectual Property Office, and entitled: “Semiconductor Memory Devices,” is incorporated by reference herein in its entirety. 
     BACKGROUND 
     1. Field 
     Embodiments relate to semiconductor memory devices. 
     2. Description of the Related Art 
     As electronic products become smaller, multifunctional, and have high performance, in high-capacity semiconductor memory devices, a degree of integration may be increased to provide high-capacity semiconductor memory devices. 
     SUMMARY 
     The embodiments may be realized by providing a semiconductor memory device including a substrate; a semiconductor pattern extending in a first horizontal direction on the substrate; bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the bit lines being at a first end of the semiconductor pattern; word lines extending in a vertical direction on the substrate, the word lines being at a side of the semiconductor pattern; a capacitor structure on a second end of the semiconductor pattern opposite to the first end in the first horizontal direction, the capacitor structure including a lower electrode connected to the semiconductor pattern, an upper electrode spaced apart from the lower electrode, and a capacitor dielectric layer between the lower electrode and the upper electrode; and a capacitor contact layer between the second end of the semiconductor pattern and the lower electrode, the capacitor contact layer including a pair of convex surfaces in contact with the semiconductor pattern. 
     The embodiments may be realized by providing a semiconductor memory device including a substrate; a plurality of semiconductor patterns extending in a first horizontal direction on the substrate, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction; a plurality of bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of bit line being spaced apart from each other in the vertical direction and on a first end of each of the plurality of semiconductor patterns; a plurality of word lines extending in the vertical direction on the substrate, the plurality of word lines being on sides of the plurality of semiconductor patterns; a capacitor structure on a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; a plurality of support layers between two adjacent lower electrodes among the plurality of lower electrodes; and a plurality of capacitor contact layers between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes, wherein the second end of each of the plurality of semiconductor patterns includes a pair of recessed portions. 
     The embodiments may be realized by providing a semiconductor memory device a substrate; a plurality of semiconductor patterns extending in a first horizontal direction on the substrate, the plurality of semiconductor patterns being spaced apart from each other in a vertical direction; a plurality of bit lines extending in a second horizontal direction on the substrate, the second horizontal direction being perpendicular to the first horizontal direction, the plurality of bit lines being spaced apart from each other in the vertical direction, and being on a first end of each of the plurality of semiconductor patterns; a pair of gate electrodes on the substrate and spaced apart from each other in the second horizontal direction, the pair of gate electrodes extending in the vertical direction and being on opposite sides of the plurality of semiconductor patterns; a capacitor structure on a second end of each of the plurality of semiconductor patterns opposite to the first end in the first horizontal direction, the capacitor structure including a plurality of lower electrodes spaced apart from each other in the vertical direction; a plurality of support layers alternately provided with the plurality of lower electrodes in the vertical direction; and a plurality of capacitor contact layers between the second end of each of the plurality of semiconductor patterns and the plurality of lower electrodes, the plurality of capacitor contact layers including a metal silicide, wherein the plurality of capacitor contact layers each include a pair of convex surfaces in contact with the plurality of semiconductor patterns. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Features will be apparent to those of skill in the art by describing in detail exemplary embodiments with reference to the attached drawings in which: 
         FIG.  1    is an equivalent circuit diagram of a cell array of a semiconductor memory device according to embodiments; 
         FIG.  2    is a perspective view of a semiconductor memory device according to embodiments; 
         FIG.  3    is a cross-sectional view taken along lines A 1 -A 1 ′ and A 2 -A 2 ′ of  FIG.  2   ; 
         FIG.  4    is a cross-sectional view taken along line B 1 -B 1 ′ of  FIG.  2   ; 
         FIG.  5    is a top view of a semiconductor memory device; 
         FIG.  6    is an enlarged view of a region CX 1  of  FIG.  3   ; 
         FIG.  7    is an enlarged view of a region CX 2  of  FIG.  5   ; 
         FIG.  8    is a cross-sectional view of a semiconductor memory device according to embodiments; 
         FIG.  9    is a top view of the semiconductor memory device of  FIG.  8   ; 
         FIG.  10    is a cross-sectional view of a semiconductor memory device according to embodiments; 
         FIG.  11    is a cross-sectional view of a semiconductor memory device according to embodiments; 
         FIG.  12    is a cross-sectional view of a semiconductor memory device according to embodiments; and 
         FIGS.  13  to  27 B  illustrate stages in a method of manufacturing a semiconductor memory device according to embodiments. Specifically,  FIGS.  13 ,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A,  20 A,  21 ,  22 A,  23 A,  24 A,  25 A,  26 A, and  27 A  are cross-sectional views taken along lines A 1 -A 1 ′ and A 2 -A 2 ′ of  FIG.  2   .  FIGS.  14 B,  15 B,  16 B,  17 B,  18 B,  19 B,  20 B,  22 B,  23 B,  24 B,  25 B,  26 B, and  27 B  are cross-sectional views taken along line B 1 -B 1 ′ of  FIG.  2   .  FIGS.  14 C,  15 C,  18 C,  19 C, and  22 C  are top views of a semiconductor memory device.  FIGS.  19 D and  19 E  are enlarged views of a region CX 2  of  FIG.  19 C .  FIGS.  22 D,  22 E, and  22 F  are enlarged views of a region CX 1  of  FIG.  22 A . 
     
    
    
     DETAILED DESCRIPTION 
       FIG.  1    is an equivalent circuit diagram of a cell array of a semiconductor memory device according to embodiments. 
     Referring to  FIG.  1   , a cell array of a semiconductor memory device may include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA may be arranged in a first horizontal direction X. 
     The sub cell array SCA may include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of cell transistors CTR. One cell transistor CTR may be between one word line WL and one bit line BL. 
     The plurality of bit lines BL may be a conductive pattern (e.g., metal lines) on a substrate and spaced apart from the substrate. The plurality of bit lines BL may extend in a second horizontal direction Y. Bit lines BL in one sub cell array SCA may be spaced apart from each other in a vertical direction Z. 
     The word lines WL may be a conductive pattern (e.g., metal lines) extending from the substrate in the vertical direction Z. Word lines WL in one sub cell array SCA may be spaced apart from each other in the second horizontal direction Y. 
     A gate of the memory cell transistor CTR may be connected to the word lines WL, and a source of the memory cell transistor CTR may be connected to the bit lines BL. The cell transistor CTR may be connected to a cell capacitor CAP. A drain of the cell transistor CTR may be connected to a first electrode of the cell capacitor CAP, and a second electrode of the cell capacitor CAP may be connected to a ground interconnection PP. 
       FIG.  2    is a perspective view of a semiconductor memory device  100  according to embodiments.  FIG.  3    is a cross-sectional view taken along lines A 1 -A 1 ′ and A 2 -A 2 ′ of  FIG.  2   .  FIG.  4    is a cross-sectional view taken along line B 1 -B 1 ′ of  FIG.  2   .  FIG.  5    is a top view of the semiconductor memory device  100 .  FIG.  6    is an enlarged view of a region CX 1  of  FIG.  3   .  FIG.  7    is an enlarged view of a region CX 2  of  FIG.  5   . In  FIG.  2   , for convenience of illustration, a gate dielectric layer DL and an upper electrode UE are omitted. 
     Referring to  FIGS.  2  to  7   , the semiconductor memory device  100  may include a plurality of semiconductor patterns AP, a plurality of bit lines BL, a plurality of word lines WL, and a capacitor structure CS, which are on the substrate  110 . 
     The substrate  110  may include Si, Ge, or SiGe. In an implementation, the substrate  110  may include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. In an implementation, a peripheral circuit and an interconnection layer connected to the peripheral circuit may be further provided on a region of the substrate  110 . 
     A plurality of semiconductor patterns AP may extend (e.g., lengthwise) on the substrate  110  in a first horizontal direction X and may be spaced apart from each other in a vertical direction Z. A mold insulating layer IL may be between the plurality of semiconductor patterns AP. 
     The plurality of semiconductor patterns AP may be formed of, e.g., an undoped semiconductor material or a doped semiconductor material. In an implementation, the plurality of semiconductor patterns AP may be formed of polysilicon. In an implementation, the plurality of semiconductor patterns AP may include an amorphous metal oxide, a polycrystalline metal oxide, or a combination thereof, e.g., In—Ga-based oxide (IGO), In—Zn-based oxide (IZO), or In—Ga—Zn-based oxide (IGZO). In an implementation, the plurality of semiconductor patterns AP may include a 2D material semiconductor. In an implementation, the 2D material semiconductor may include MoS 2 , WSe 2 , graphene, carbon nano tube, or a combination thereof. As used herein, the term “or” is not an exclusive term, e.g., “A or B” would include A, B, or A and B. 
     The plurality of semiconductor patterns AP may have a line or bar shape extending (e.g., lengthwise) in the first horizontal direction X. Each of the semiconductor patterns AP may include a channel region CH, and a first impurity region SD 1  and a second impurity region SD 2  in or along the first horizontal direction X, e.g., with the channel region CH between the first impurity region SD 1  and the second impurity region SD 2 . The first impurity region SD 1  may be connected to the bit lines BL, and the second impurity region SD 2  may be connected to the capacitor structure CS. 
     The word lines WL may be on at least one sidewall of the plurality of semiconductor patterns AP and extend in a vertical direction Z. The semiconductor memory device  100  may have a double gate transistor structure. In an implementation, each of the word lines WL may include a first gate electrode  130 A 1  and a second gate electrode  130 A 2  on opposite sidewalls of one of the plurality of semiconductor patterns AP. 
     The first gate electrode  130 A 1  and the second gate electrode  130 A 2  may include a doped semiconductor material (doped silicon, doped germanium, or the like), a conductive metal nitride (titanium nitride, tantalum nitride, or the like), a metal (tungsten, titanium, tantalum, or the like), or a metal-semiconductor compound (tungsten silicide, cobalt silicide, titanium silicide, or the like). 
     A gate insulating layer  140  may be between the first gate electrode  130 A 1  and the semiconductor patterns AP and between the second gate electrode  130 A 2  and the semiconductor patterns AP. The gate insulating layer  140  may be formed of a high-k dielectric material having a higher dielectric constant than silicon oxide or a ferroelectric material. In an implementation, the gate insulating layer  140  may be formed of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), or lead scandium tantalum oxide (PbScTaO). 
     A gap-fill insulating layer  142  may be between a first gate electrode  130 A 1  on a sidewall of one semiconductor pattern AP and a second gate electrode  130 A 2  on a sidewall of another semiconductor pattern AP adjacent to the one semiconductor pattern AP. A space between the first gate electrode  130 A 1  and the second gate electrode  130 A 2  adjacent to each other may be filled with the gap-fill insulating layer  142 . The gap-fill insulating layer  142  may include silicon oxide, silicon oxynitride, silicon nitride, carbon-containing silicon oxide, carbon-containing silicon oxynitride, carbon-containing silicon nitride, or a combination thereof. 
     The plurality of bit lines BL may extend on the substrate  110  in the second horizontal direction Y and may be spaced apart from each other in the vertical direction Z. The plurality of bit lines BL may include a doped semiconductor material, a conductive metal nitride, a metal (e.g., a non-compounded metal material), or a metal-semiconductor compound. 
     A contact layer CP 1  may be between the plurality of bit lines BL and the plurality of semiconductor patterns AP connected thereto. The contact layer CP 1  may include a metal silicide material, e.g., titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide. 
     A capacitor contact layer CP 2  may be between the plurality of semiconductor patterns AP and a lower electrode LE connected thereto. In an implementation, as illustrated in  FIG.  7   , one end of a semiconductor pattern AP may be recessed inwardly (e.g., in a direction toward the bit lines BL) with respect to a sidewall of a second vertical insulating structure PL 2 , and a portion of a sidewall of a capacitor contact layer CP 2  may be in contact (e.g., direct contact) with the sidewall of the second vertical insulating structure PL 2 . 
     The capacitor contact layer CP 2  may include a metal silicide material, e.g., titanium silicide, tungsten silicide, cobalt silicide, or nickel silicide. In an implementation, the capacitor contact layer CP 2  may have a thickness of about 20 mm to about 100 nm. The capacitor contact layer CP 2  may be obtained by forming a barrier metal layer  230  (see  FIG.  21 A ) on exposed surfaces of a support layer SL and the semiconductor pattern AP and performing a heat treatment process on the barrier metal layer  230 , before the lower electrode LE is formed. In an implementation, the capacitor contact layer CP 2  may be formed uniformly to a relatively large thickness on an entire exposed area of the semiconductor pattern AP. 
     A first vertical insulating structure PL 1  may be on both sidewalls of a portion of the semiconductor pattern AP adjacent to the plurality of bit lines BL, and the second vertical insulating structure PL 2  may be on both sides of a portion of the semiconductor pattern AP adjacent to the capacitor structure CS. The first vertical insulating structure PL 1  may extend in the vertical direction Z, e.g., on sidewalls of the first impurity region SD 1  and the contact layer CP 1 , and may include a first liner  152  and a first gap fill layer  154 . The second vertical insulating structure PL 2  may extend in the vertical direction Z on sidewalls of the second impurity region SD 2  and the capacitor contact layer CP 2 , and may include a second liner  156  and a second gap fill layer  158 . 
     The capacitor structure CS may include a plurality of lower electrodes LE, a capacitor dielectric layer DL, and an upper electrode UE. The plurality of lower electrodes LE may extend in the first horizontal direction X and may be spaced apart from each other in the vertical direction Z. Each of the plurality of lower electrodes LE may have an inner space extending in the first horizontal direction X, and the inner space may be filled with the capacitor dielectric layer DL and the upper electrode UE. 
     The plurality of lower electrodes LE and a plurality of support layers SL may be alternately arranged in the vertical direction Z. The plurality of lower electrodes LE may be at the same vertical level (e.g., the same distance from the substrate  110  in the vertical direction Z) as the plurality of semiconductor patterns AP. The plurality of support layers SL may be between the plurality of lower electrodes LE to help prevent the plurality of lower electrodes LE from collapsing or leaning in a process of forming the plurality of lower electrodes LE. 
     Each of the plurality of lower electrodes LE may include a pair of first sidewalls LES 1  spaced apart from each other in the second horizontal direction Y, a second sidewall LES 2  connected to the capacitor contact layer CP 2 , and a top surface LEU extending in the first horizontal direction X. As illustrated in  FIG.  6   , a vertical cross-section of each of the plurality of lower electrodes LE viewed from or as a Y-Z plane may have a closed loop shape. In addition, as illustrated in  FIG.  7   , the second sidewall LES 2  may protrude in a direction toward the semiconductor pattern AP with respect to the sidewall of the second vertical insulating structure PL 2 . In an implementation, an end of a lower electrode LE adjacent to the second sidewall LES 2  may be in contact with the second vertical insulating structure PL 2 . 
     The capacitor dielectric layer DL may be conformally provided in the inner space of the lower electrode LE, and on the pair of first sidewalls LES 1  of the lower electrode LE and sidewalls of the support layer SL. The capacitor dielectric layer DL may not be on the top surface LEU of the lower electrode LE. 
     The capacitor dielectric layer DL may be formed of a high-k dielectric material having a higher dielectric constant than silicon oxide or a ferroelectric material. In an implementation, the capacitor dielectric layer DL may be formed of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconate titanate (PZT), strontium bismuth tantalate (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (A 10 ), or lead scandium tantalum oxide (PbScTaO). 
     The upper electrode UE may cover the plurality of lower electrodes LE and the plurality of support layers SL, and the capacitor dielectric layer DL may be therebetween. 
     The lower electrode LE and the upper electrode UE may include a doped semiconductor material, a conductive metal nitride such as titanium nitride, tantalum nitride, niobium nitride or tungsten nitride, a metal such as ruthenium, iridium, titanium or tantalum, a conductive metal oxide such as iridium oxide or niobium oxide, or the like. 
     According to the above-described embodiments, the capacitor contact layer CP 2  may be formed to a relatively large thickness between the lower electrode LE and the semiconductor pattern AP by, e.g., a manufacturing method to be described with reference to  FIGS.  13  to  27 B  below. Accordingly, electrical resistance between the lower electrode LE and the semiconductor pattern AP may be reduced, and the semiconductor memory device  100  may have excellent operating characteristics. 
       FIG.  8    is a cross-sectional view of a semiconductor memory device  100 A according to embodiments.  FIG.  9    is a top view of the semiconductor memory device  100 A.  FIG.  8    is an enlarged view of a portion corresponding to the region CX 1  of  FIG.  3   .  FIG.  9    is an enlarged view of a portion corresponding to the region CX 2  of  FIG.  5   . 
     Referring to  FIGS.  8  and  9   , sidewalls of a semiconductor pattern AP may include a pair of recessed portions APR. The pair of recessed portions APR may be mirror symmetrical to each other with respect to or on either side in the second horizontal direction Y of a center line CL (e.g., bisecting the semiconductor pattern AP and extending in the first horizontal direction X). A capacitor contact layer CP 2 A may be conformally formed on the pair of recessed portions APR of the semiconductor pattern AP, and a second sidewall LES 2 A of a lower electrode LEA in contact with the capacitor contact layer CP 2 A may protrude toward the semiconductor pattern AP. In an implementation, the second sidewalls LES 2 A of the lower electrode LEA may have a (e.g., protruding or convex) shape conforming or complementary to the (e.g., concave) pair of recesses APR, and may be mirror symmetrical to each other with respect to the center line CL. 
     In a manufacturing process according to embodiments, in order to form the lower electrode LEA, a second opening OP 2  may be formed to expose sidewalls of a channel mold layer  210  (see  FIG.  19 A ) between support layers SL, and the channel mold layer  210  may be removed by performing a side recess process on the exposed sidewalls of the channel mold layer  210  through the second opening OP 2 . In an implementation, the side recess process may be performed by exposing the exposed sidewalls of the channel mold layer  210  to an etchant (such as an etching gas) through the second opening OP 2 . In the side recess process, a portion of a sidewall of the semiconductor pattern AP adjacent to the second opening OP 2  may be exposed by the etchant and a pair of recessed portions APR may be formed on the portion of the sidewall of the semiconductor pattern AP. In an implementation, two second openings OP 2  may be adjacent to both edges of one semiconductor pattern AP in a plan view, and the pair of recessed portions APR may be mirror symmetrical to each other with respect to the center line CL. 
     After removing the channel mold layer  210 , the barrier metal layer  230  (see  FIG.  21 A ) may be formed on an exposed surface, e.g., the pair of recessed portions APR, of the semiconductor pattern AP, and then be heat treated to form the capacitor contact layer CP 2 A. Accordingly, the capacitor contact layer CP 2 A may include a pair of convex surfaces CP 2 S protruding toward the pair of recessed portions APR. In an implementation, the capacitor contact layer CP 2 A may have a relatively uniform thickness over the entire area, and the second sidewalls LES 2 A of the lower electrode LEA in contact with the capacitor contact layer CP 2 A may also have a convex shape protruding toward the pair of recessed portions APR. 
     The lower electrode LEA may have a top surface LEUA, and may have a pair of first sidewalls LES 1 A spaced apart from each other in the second horizontal direction Y. The top surface LEUA of the lower electrode LEA may be in contact with the support layer SL and have a flat profile, e.g., without protrusions or recesses. The pair of first sidewalls LES 1 A may be concave inward toward each other with respect to a center of the lower electrode LEA. 
     In an implementation, in order to form the lower electrode LEA, after performing the side recess process, the barrier metal layer  230  may be formed and an etching process may be performed to remove the barrier metal layer  230  from the sidewalls of the support layers SL. In the etching process, a relatively large portion of a first gap-fill material layer  240  filling a space between the support layers SL may be removed, and in this case, profiles of the pair of first sidewalls LES 1 A of the lower electrode LEA may be concave inward toward each other with respect to the center of the lower electrode LEA. 
       FIG.  10    is a cross-sectional view of a semiconductor memory device  100 B according to embodiments.  FIG.  10    is an enlarged view of a portion corresponding to the region CX 1  of  FIG.  3   . 
     Referring to  FIG.  10   , a lower electrode LEB may have a top surface LEUB, and may have a pair of first sidewalls LES 1 B spaced apart from each other in a second horizontal direction Y. The top surface LEUB of the lower electrode LEB may be in contact with a support layer SL and may have a flat profile, e.g., without protrusions or recesses. The pair of first sidewalls LES 1 B may include a plurality of curved portions. 
     In an implementation, in order to form the lower electrode LEB, after performing the side recess process, the barrier metal layer  230  may be formed and the etching process may be performed to remove the barrier metal layer  230  from sidewalls of support layers SL. In the etching process, the barrier metal layer  230  may have concave sidewalls according to a thickness of the barrier metal layer  230  and an etching atmosphere. In this case, a side mold layer  250 , which is formed on a sidewall of the barrier metal layer  230  and serves as a portion of a mold for the lower electrode LEB, may have a plurality of curved portions, and the first sidewalls LES 1 B of the lower electrode LEB on the side mold layer  250  may have a plurality of curved portions. 
       FIG.  11    is a cross-sectional view of a semiconductor memory device  100 C according to embodiments.  FIG.  11    illustrates cross-sectional views corresponding to cross-sections taken along lines A 1 -A 1 ′ and A 2 -A 2 ′ of  FIG.  2   . 
     Referring to  FIG.  11   , a word line WLC may include a first gate electrode  130 C, and the first gate electrode  130 C may extend on (e.g., only) one sidewall of a semiconductor pattern AP in the vertical direction Z. The word line WLC may not be on a sidewall of the semiconductor pattern AP opposite to the one sidewall. The semiconductor memory device  100 C may have a single gate transistor structure. 
       FIG.  12    is a cross-sectional view of a semiconductor memory device  100 D according to embodiments. 
     Referring to  FIG.  12   , a word line WLD may include a first gate electrode  130 D, and the first gate electrode  130 D may surround all sidewalls of a semiconductor pattern AP, and extend in a vertical direction Z. A gate insulating layer  140  may be between the first gate electrode  130 D and the semiconductor pattern AP. The semiconductor memory device  100 D may have a gate-all-around type transistor structure. 
       FIGS.  13  to  27 B  illustrate stages in a method of manufacturing a semiconductor memory device  100  according to embodiments. Specifically,  FIGS.  13 ,  14 A,  15 A,  16 A,  17 A,  18 A,  19 A,  20 A,  21 ,  22 A,  23 A,  24 A,  25 A,  26 A, and  27 A  are cross-sectional views taken along lines A 1 -A 1 ′ and A 2 -A 2 ′ of  FIG.  2   .  FIGS.  14 B,  15 B,  16 B,  17 B,  18 B,  19 B ,  20 B,  22 B,  23 B,  24 B,  25 B,  26 B, and  27 B are cross-sectional views taken along line B 1 -B 1 ′ of  FIG.  2   .  FIGS.  14 C,  15 C,  18 C,  19 C, and  22 C  are top views of the semiconductor memory device  100 .  FIGS.  19 D and  19 E  are enlarged views of a region CX 2  of  FIG.  19 C .  FIGS.  22 D,  22 E, and  22 F  are enlarged views of a region CX 1  of  FIG.  22 A . 
     Referring to  FIG.  13   , a mold stack MS may be formed by alternately and sequentially forming a sacrificial mold layer  212  and a channel mold layer  210  on a substrate  110 . 
     In an implementation, the channel mold layer  210  and the sacrificial mold layer  212  may be formed of materials having an etch selectivity with respect to each other. In an implementation, the channel mold layer  210  and the sacrificial mold layer  212  may be single crystal layers of a Group IV semiconductor, a Group IV-IV semiconductor, a Group II-VI compound semiconductor, or a Group III-V compound semiconductor, and may be formed of different materials. In an implementation, the sacrificial mold layer  212  may be formed of SiGe, and the channel mold layer  210  may be formed of single crystal silicon. Each of the channel mold layer  210  and the sacrificial mold layer  212  may have a thickness (e.g., in the vertical direction Z) of several tens of nm. 
     In an implementation, the channel mold layer  210  and the sacrificial mold layer  212  may be formed by an epitaxy process. In an implementation, the epitaxy process may be vapor-phase epitaxy (VPE), a chemical vapor deposition process such as ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy, or a combination thereof. In the epitaxy process, a liquid or gaseous precursor may be used as a precursor necessary to form the channel mold layer  210  and the sacrificial mold layer  212 . 
     Referring to  FIGS.  14 A to  14 C , a mask pattern may be formed on the mold stack MS, and a portion of the mold stack MS may be removed using the mask pattern as an etching mask to form first openings OP 1 . Sidewalls  210 C of a portion of the channel mold layer  210  corresponding to a channel region CH of a semiconductor pattern AP may be formed by the first openings OP 1 . 
     Thereafter, the sacrificial mold layer  212  exposed through the first openings OP 1  may be removed, and a mold insulating layer IL may be formed in a region from which the sacrificial mold layer  212  is removed. In an implementation, the mold insulating layer IL may be formed using at least one of silicon nitride, silicon oxide, and silicon oxynitride. 
     Thereafter, an insulating layer filling the inside of the first openings OP 1  may be formed on the mold stack MS, and a first gap-fill insulating layer  222  may be formed by removing an upper portion of the insulating layer so that a top surface of the mold stack MS is exposed. 
     Referring to  FIGS.  15 A to  15 C , a mask pattern may be formed on the mold stack MS, and portions of the mold stack MS may be removed using the mask pattern as an etching mask to form second openings OP 2 . 
     Portions of the channel mold layer  210 , the sidewalls of which are defined by two adjacent second openings OP 2 , may be referred to as a lower-electrode sacrificial pattern  210 P. Each of a plurality of lower-electrode sacrificial patterns  210 P may be portions of the channel mold layer  210  that are replaced with lower electrodes LE in a subsequent process. 
     In an implementation, the plurality of lower-electrode sacrificial patterns  210 P may extend in a first horizontal direction X and be spaced apart from each other in the second horizontal direction Y and the vertical direction Z. The plurality of lower-electrode sacrificial patterns  210 P may have a first length L 1  of about 50 nm to about 2,000 nm in the first horizontal direction X. The plurality of lower-electrode sacrificial patterns  210 P may have a first width W 1  of about 5 nm to about 100 nm in the second horizontal direction Y. Here, the first horizontal direction X may be referred to as a longitudinal direction of the lower-electrode sacrificial pattern  210 P or the lower electrode LE, and an aspect ratio in the longitudinal direction (e.g., a ratio of the first length L 1  in the first horizontal direction X to the first width W 1  in the second horizontal direction Y) may be about 5 to about 400. 
     Referring to  FIGS.  16 A and  16 B , third openings OP 3  may be formed by removing the sacrificial mold layer  212  exposed through the second openings OP 2 . Accordingly, top and bottom surfaces of the plurality of lower-electrode sacrificial patterns  210 P may be exposed through the third openings OP 3 . 
       FIG.  16 B  illustrates an example in which sidewalls of the mold insulating layer IL are exposed through the third openings OP 3 . In an implementation, in the process of removing the sacrificial mold layer  212  to form the third openings OP 3 , a portion of the sacrificial mold layer  212  adjacent to the mold insulating layer IL may not be removed. In this case, the portion of the sacrificial mold layer  212  adjacent to the mold insulating layer IL may remain, covering a sidewall of the mold insulating layer IL, and the mold insulating layer IL may not be exposed through the third openings OP 3 . 
     Referring to  FIGS.  17 A and  17 B , an insulating layer may be formed on the mold stack MS to fill the inside of the third openings OP 3 , and an anisotropic etching process may be performed on the insulating layer to form a support layer SL. The support layer SL may be formed of, e.g., silicon nitride. 
     Sidewalls of the support layer SL may be aligned with the sidewalls of the plurality of lower-electrode sacrificial patterns  210 P. A plurality of lower-electrode sacrificial patterns  210 P and a plurality of support layers SL may be alternately arranged in the vertical direction Z. 
     Thereafter, an insulating layer filling the inside of the second openings OP 2  may be formed on the mold stack MS, and an upper portion of the insulating layer may be removed so that the top surface of the mold stack MS is exposed, thereby forming a second gap-fill insulating layer  224 . 
     Referring to  FIGS.  18 A to  18 C , the first gap-fill insulating layer  222  in the first openings OP 1  may be removed, and a gate insulating layer  140  may be conformally formed in the first openings OP 1 . Thereafter, a conductive layer may be formed on both sidewalls of the first openings OP 1  and the anisotropic etching process may be performed on the conductive layer to form a first gate electrode  130 A 1  and a second gate electrode  130 A 2  on both sidewalls of the first openings OP 1 . 
     Thereafter, a gap-fill insulating layer  142  filling a space between the first gate electrode  130 A 1  and the second gate electrode  130 A 2  may be formed. 
     Thereafter, a mask pattern may be formed on the mold stack MS, and a portion of the mold stack MS may be removed using the mask pattern as an etching mask to extend the first openings OP 1  in the first horizontal direction X. Sidewalls of portions of the semiconductor pattern AP corresponding to a first impurity region SD 1  and a second impurity region SD 2  may be exposed through the extended first openings OP 1 . 
     A first vertical insulating structure PL 1  and a second vertical insulating structure PL 2  may be formed in the extended first openings OP 1 . In an implementation, the first vertical insulating structure PL 1  may extend in the vertical direction Z on both sidewalls of a region of the semiconductor pattern AP in which the first impurity region SD 1  is to be formed, and the second vertical insulating structure PL 2  may extend in the vertical direction Z on both sidewalls of a region of the semiconductor pattern AP in which the second impurity region SD 2  is to be formed. 
     Thereafter, impurities may be implanted into a portion of the semiconductor pattern AP by an ion implantation process to form the first impurity region SD 1  and the second impurity region SD 2 . The first impurity region SD 1  and the second impurity region SD 2  may be formed by the ion implantation process, and a channel region CH between the first impurity region SD 1  and the second impurity region SD 2  may be defined. 
     In an implementation, the process of forming the first vertical insulating structure PL 1  and the second vertical insulating structure PL 2  may be performed prior to the process of forming the first and second gate electrodes  130 A 1  and  130 A 2 . In an implementation, the ion implantation process of forming the first impurity region SD 1  and the second impurity region SD 2  may be performed prior to the process of forming the first vertical insulating structure PL 1  and the second vertical insulating structure PL 2 . 
     Thereafter, the second gap-fill insulating layer  224  may be removed and the second opening OP 2  may be exposed again. The sidewalls of the support layer SL and the lower-electrode sacrificial pattern  210 P may be exposed again on the sidewalls of the second opening OP 2 . 
     Referring to  FIGS.  19 A to  19 E , a side recess process may be performed on the lower-electrode sacrificial pattern  210 P exposed by the second opening OP 2 . In the side recess process, the lower-electrode sacrificial pattern  210 P (refer to  FIG.  18 A ) may be removed, and sidewalls of the second impurity region SD 2  of the semiconductor pattern AP may be exposed. 
     In an implementation, the side recess process may be performed by exposing the exposed sidewalls of the lower-electrode sacrificial pattern  210 P to an etchant such as an etching gas through the second opening OP 2 . The side recess process may be performed during an etching time to remove about half of a width of the lower-electrode sacrificial pattern  210 P in the second horizontal direction Y or remove about half of a height of the channel mold layer  210 . In the side recess process, the sidewalls of the lower-electrode sacrificial pattern  210 P corresponding to a total length L 1  thereof (see  FIG.  15 C ) (e.g., a length in the first horizontal direction X) may be exposed to an etching atmosphere, and the etchant may be sufficiently supplied in the second horizontal direction Y from the entire sidewalls of the lower-electrode sacrificial pattern  210 P exposed through the second openings OP 2 . 
     In a manufacturing method according to a comparative example, a mold trench MT 2  (see  FIG.  23 B ) may be formed in an end of the lower-electrode sacrificial pattern  210 P in a longitudinal direction (the first horizontal direction X) in a state in which the sidewalls of the lower-electrode sacrificial pattern  210 P are blocked by the second gap-fill insulating layer  224 , and the lower-electrode sacrificial pattern  210 P may be removed from the mold trench MT 2  in the longitudinal direction (the first horizontal direction X). According to this comparative method, a supply path of the etchant and a path of movement of removed materials may be relatively long, and it may be difficult to accurately control an etching process, e.g., a part of the lower-electrode sacrificial pattern  210 P may not be completely removed. 
     On the other hand, according to an embodiment, the lower-electrode sacrificial pattern  210 P may be removed by performing the side recess process on the sidewalls thereof and thus the supply path of the etchant and the path of movement of removed materials may be significantly reduced. Accordingly, a time to perform the etching process to remove the lower-electrode sacrificial pattern  210 P may be reduced, and the accuracy of the process of etching the lower-electrode sacrificial pattern  210 P may be improved. 
     A space remaining after the lower-electrode sacrificial pattern  210 P is removed by the side recess process may be referred to as a first mold trench MT 1 . The top and bottom surfaces of the support layer SL and the sidewalls of the semiconductor pattern AP may be exposed through the first mold trench MT 1 . In an implementation, as illustrated in  FIG.  19 D , a sidewall of the semiconductor pattern AP may be located on the same plane as a sidewall of the second vertical insulating structure PL 2 . 
     In an implementation, in the side recess process, a sidewall of the semiconductor pattern AP adjacent to the second opening OP 2  may be removed or recessed by a certain width due to exposure to the etchant. Accordingly, as illustrated in  FIG.  19 E , a pair of recessed portions APR (see  FIG.  9   ) may be provided in the sidewall of the semiconductor pattern AP. In an implementation, the pair of recessed portions APR may be mirror symmetrical to each other with respect to the center line CL (see  FIG.  9   ). In this case, the semiconductor memory device  100 A described above with reference to  FIGS.  8  and  9    may be obtained. 
     Referring to  FIGS.  20 A and  20 B , a barrier metal layer  230  may be formed on the sidewalls of the semiconductor pattern AP, the sidewalls of the second vertical insulating structure PL 2 , and the surface of the support layer SL, which are exposed after the lower-electrode sacrificial pattern  210 P is removed, and a heat treatment process may be performed on the barrier metal layer  230  to form a capacitor contact layer CP 2  between the sidewalls of the semiconductor pattern AP and the barrier metal layer  230 . 
     In an implementation, the barrier metal layer  230  may be formed of titanium, tantalum, cobalt, tungsten, titanium nitride, or tantalum nitride. In an implementation, the barrier metal layer  230  may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a metal organic CVD process, or a metal organic ALD process. The barrier metal layer  230  may be formed to a thickness of about 20 nm to about 100 nm. 
     In an implementation, in the heat treatment process, silicidation may occur between silicon included in the exposed surface of the semiconductor pattern AP and a metal material of the barrier metal layer  230  in contact with the semiconductor pattern AP, thus forming a capacitor contact layer CP 2  including a metal silicide material. 
     In the process of forming the barrier metal layer  230  to form the capacitor contact layer CP 2 , the barrier metal layer  230  may be formed on a surface exposed by the second opening OP 2  and the first mold trench MT 1  and a source material of the barrier metal layer  230  may be smoothly supplied to the sidewalls of the semiconductor pattern AP. Accordingly, the barrier metal layer  230  may be formed to a relatively large thickness on the entire sidewalls of the semiconductor pattern AP and the accuracy of a process of forming the barrier metal layer  230  may be improved. 
     In a manufacturing method according to a comparative example, the lower-electrode sacrificial pattern  210 P may be removed in the longitudinal direction (the first horizontal direction X) while the sidewalls of the lower-electrode sacrificial pattern  210 P are blocked by the second gap-fill insulating layer  224 , and the barrier metal layer  230  may be formed in a space from which the lower-electrode sacrificial pattern  210 P is removed. In this case, an aspect ratio in the longitudinal direction of the lower-electrode sacrificial pattern  210 P may be large, and it may be difficult to form the barrier metal layer  230  to a sufficiently large thickness on the semiconductor pattern AP. Accordingly, the capacitor contact layer CP 2  may be formed to a thin or non-uniform thickness due to a reaction between the components of the semiconductor pattern AP and the barrier metal layer  230 , thereby causing an undesired increase in electrical resistance between a cell transistor and a cell capacitor. 
     On the other hand, according to an embodiment, the barrier metal layer  230  may be formed to a relatively large thickness on the entire sidewalls of the semiconductor pattern AP and thus the capacitor contact layer CP 2  may also be formed uniformly to a relatively large thickness. 
     Thereafter, an insulating layer may be formed on the barrier metal layer  230  to fill the inside of the first mold trench MT 1 , and an etch back process or a wet etching process may be performed on the insulating layer so that the barrier metal layer  230  on the sidewall of the support layer SL is exposed, thereby forming the first gap-fill material layer  240 . 
     The first gap-fill material layer  240  may fill a space between two adjacent support layers SL, and the sidewalls of the barrier metal layer  230  may not be covered by the first gap-fill material layer  240  and may be exposed through the second opening OP 2 . 
     Referring to  FIG.  21   , the etch back process or the wet etching process may be performed on the barrier metal layer  230  and the first gap-fill material layer  240  so that the sidewalls of the support layer SL are exposed. Accordingly, a portion of the barrier metal layer  230  covering the sidewalls of the support layer SL may be removed, and the sidewalls of the support layer SL may be exposed through the second opening OP 2 . 
     In an implementation, a portion of the first gap-fill material layer  240  may be also removed in the etch-back or wet etching process, so that the sidewalls of the first gap-fill material layer  240  and the sidewalls of the barrier metal layer  230  may be aligned with each other. Accordingly, a vertical plate type structure in which the support layer SL, the barrier metal layer  230 , and the first gap-fill material layer  240  are stacked may be formed. 
     Referring to  FIGS.  22 A to  22 F , a side mold layer  250  may be formed on sidewalls of a structure in which the support layer SL, the barrier metal layer  230 , and the first gap-fill material layer  240  are stacked, and thereafter, a second gap-fill material layer  260  filling the second opening OP 2  may be formed on the side mold layer  250 . 
     In an implementation, the side mold layer  250  may be formed of a material having an etch selectivity with respect to the support layer SL, the barrier metal layer  230  and the first gap-fill material layer  240 . In an implementation, the side mold layer  250  may be formed of polysilicon, silicon nitride, silicon oxynitride, silicon carbon nitride, or silicon carbon oxide. 
     In an implementation, the sidewalls of the support layer SL, the sidewalls of the barrier metal layer  230 , and the sidewalls of the first gap-fill material layer  240  may be aligned with one another and thus the structure may have relatively flat sidewalls. In this case, as illustrated in  FIG.  22 D , the side mold layer  250  may have relatively flat sidewalls and thus may cover the sidewalls of the support layer SL, the sidewalls of the barrier metal layer  230 , and the sidewalls of the first gap-fill material layer  240 . 
     In an implementation, a portion of the first gap-fill material layer  240  may also be removed during the etch-back or wet etching process of the barrier metal layer  230  and thus the sidewalls of the first gap-fill material layer  240  may be recessed inward with respect to the sidewalls of the barrier metal layer  230 . As illustrated in  FIG.  22 E , the sidewalls of the first gap-fill material layer  240  may be recessed inward, and the sidewalls of the side mold layer  250  in contact with the sidewalls of the first gap-fill material layer  240  may be also concave. In this case, the semiconductor memory device  100 A described above with reference to  FIGS.  8  and  9    may be obtained. 
     In an implementation, both the barrier metal layer  230  and the first gap-fill material layer  240  may have concave sidewalls according to the thickness of the barrier metal layer  230  and an etching atmosphere in the etch back or wet etching process of the barrier metal layer  230 . As illustrated in  FIG.  22 F , both the barrier metal layer  230  and the first gap-fill material layer  240  may have concave sidewalls, and a plurality of curved portions may be provided on the sidewalls of the side mold layer  250  in contact with the barrier metal layer  230  and the first gap-fill material layer  240 . In this case, the semiconductor memory device  100 B described above with reference to  FIGS.  10  and  9    may be obtained. 
     Referring back to  FIGS.  22 B and  22 C , a mask pattern may be formed on the mold stack MS, and a portion of the mold stack MS may be removed using the mask pattern as an etching mask to form a bit line opening BLH. Thereafter, a portion of the channel mold layer  210  exposed through the bit line opening BH may be removed, and bit lines BL may be formed of a conductive material in a region from which the channel mold layer  210  is removed. Before the bit lines BL are formed, a contact layer CP 1  may be further formed of a metal silicide material between the bit lines BL and the semiconductor pattern AP. Thereafter, a bit line insulating layer BIL filling the inside of the bit line opening BH may be formed of an insulating material. 
     Thereafter, a mask pattern may be formed on the mold stack MS, and a portion of the mold stack MS may be removed using the mask pattern as an etching mask to form a second mold trench MT 2 . By forming the second mold trench MT 2 , portions of the channel mold layer  210  and the sacrificial mold layer  212  on an end of the mold stack MS in the first horizontal direction X may be removed. In addition, a sidewall of the first gap-fill material layer  240  may be exposed through the second mold trench MT 2 . 
     Referring to  FIGS.  23 A and  23 B , the first gap-fill material layer  240  (see  FIG.  22 A ) exposed through the second mold trench MT 2  may be removed to form a fourth opening OP 4 . In the process of removing the first gap-fill material layer  240 , the second gap-fill material layer  260  may also be removed and a sidewall of the side mold layer  250  may be exposed. 
     In an implementation, the process of removing the first gap-fill material layer  240  and the second gap-fill material layer  260  may be a wet etching process. 
     The fourth opening OP 4  may be a space defined by two barrier metal layers  230  spaced apart from each other in the vertical direction Z and two side mold layers  250  spaced apart from each other in the second horizontal direction Y, after the first gap-fill material layer  240  is removed. One end of the fourth opening OP 4  in the longitudinal direction (e.g., the first horizontal direction X) may be in communication with (e.g., open to) the second mold trench MT 2 , and another end of the fourth opening OP 4  in the longitudinal direction may expose the capacitor contact layer CP 2  and a portion of the barrier metal layer  230  in contact with the capacitor contact layer CP 2 . 
     Referring to  FIGS.  24 A and  24 B , the barrier metal layer  230  (see  FIG.  23 A ) exposed in the fourth opening OP 4  may be removed. A process of removing the barrier metal layer  230  may be a wet etching process. 
     After the barrier metal layer  230  is removed, the fourth opening OP 4  may be defined by two support layers SL spaced apart from each other in the vertical direction Z and two side mold layers  250  spaced apart from each other in the second horizontal direction Y. 
     Referring to  FIGS.  25 A and  25 B , a lower electrode LE may be formed on an inner wall of the fourth opening OP 4 . 
     In an implementation, a conductive layer may be conformally formed on sidewalls of the support layer SL and the side mold layer  250  in the fourth opening OP 4 , and a portion of the conductive layer on the sidewall of the support layer SL exposed in the second mold trench MT 2  may be removed to separate nodes, thereby forming lower electrodes LE in the fourth opening OP 4 . The lower electrodes LE may be formed in the space (e.g., the inside of the fourth opening OP 4 ) defined by two support layers SL spaced apart from each other in the vertical direction X and two side mold layers  250  spaced apart from each other in the second horizontal direction Y. Each of the lower electrodes LE may not be connected to a lower electrode LE adjacent thereto. 
     In an implementation, a gap-fill insulating layer may be further formed in the fourth opening OP 4  to separate nodes by removing a portion of the conductive layer on the sidewall of the support layer SL exposed in the second mold trench MT 2 . In this case, after filling the inside of the fourth opening OP 4  with the gap-fill insulating layer, a portion of the conductive layer on the sidewall of the support layer SL may be removed during the removing of the gap-fill insulating layer in the second mold trench MT 2 . 
     Referring to  FIGS.  26 A and  26 B , the side mold layer  250  (see  FIG.  25 A ) may be removed, and the sidewalls of the lower electrode LE and the sidewalls of the support layer SL may be exposed. 
     The lower electrode LE and the support layer SL may be alternately provided in the vertical direction Z, and the support layer SL may help prevent the lower electrode LE from collapsing or tilting. 
     Referring to  FIGS.  27 A and  27 B , a gate dielectric layer DL and an upper electrode UE may be formed on the sidewalls of the lower electrode LE and the sidewalls of the support layer SL. 
     In an implementation, the gate dielectric layer DL may be conformally provided on an inner wall of the lower electrode LE in the fourth opening OP 4  and a pair of first sidewalls LES 1  of the lower electrode LE, which are spaced apart from each other in the second horizontal direction Y. In addition, the gate dielectric layer DL may be also provided on the sidewalls of the support layer SL and the substrate  110 . 
     By performing the above-described processes, the semiconductor memory device  100  may be completely manufactured. 
     In a method of manufacturing a semiconductor memory device according to a comparative example, the mold trench MT 2  (see  FIG.  23 B ) may be formed at an end of the lower-electrode sacrificial pattern  210 P in the longitudinal direction (the first horizontal direction X), and the lower-electrode sacrificial pattern  210 P may be removed from the mold trench MT 2  in the longitudinal direction (the first horizontal direction X). According to this method, a supply path of an etchant and a path of movement of removed materials may be relatively long, and it may be difficult to accurately control an etching process, e.g., a portion of the lower-electrode sacrificial pattern  210 P may not be completely removed. 
     In addition, the barrier metal layer  230  may be formed in a space from which the lower-electrode sacrificial pattern  210 P is removed while the sidewall of the lower-electrode sacrificial pattern  210 P is blocked by the gap-fill insulating layer  224 . In this case, an aspect ratio in the longitudinal direction of the lower-electrode sacrificial pattern  210 P may be large, and it may be difficult to form the barrier metal layer  230  to a sufficiently large thickness on the semiconductor pattern AP. Accordingly, the capacitor contact layer CP 2  may be formed to a thin or non-uniform thickness due to a reaction between the components of the semiconductor pattern AP and the barrier metal layer  230 , thereby causing an undesired increase in electrical resistance between a cell transistor and a cell capacitor. 
     On the other hand, according to an embodiment, the lower-electrode sacrificial pattern  210 P may be removed by performing the side recess process on the sidewalls thereof and the supply path of the etchant and the path of movement of removed materials may be significantly reduced. Accordingly, a time to perform the etching process to remove the lower-electrode sacrificial pattern  210 P may be reduced, and the accuracy of the process of etching the lower-electrode sacrificial pattern  210 P may be improved. 
     In addition, the barrier metal layer  230  may be formed to a relatively large thickness on the entire sidewalls of the semiconductor pattern AP and thus the capacitor contact layer CP 2  may also be formed uniformly to a relatively large thickness. Accordingly, electrical resistance between the lower electrode LE and the semiconductor pattern AP may reduce and thus the semiconductor memory device  100  may have excellent operating characteristics. 
     By way of summation and review, degrees of integration of two-dimensional (2D) semiconductor memory devices may be determined by an area occupied by unit memory cells, and the degrees of integration of 2D semiconductor memory devices may be increasing but may still be limited. A 3D semiconductor memory device has been considered, in which a plurality of memory cells are stacked on a substrate in a vertical direction to increase memory capacity. 
     One or more embodiments may provide a three-dimensional (3D) semiconductor memory device. 
     One or more embodiments may provide a three-dimensional (3D) semiconductor memory device with an increased degree of integration. 
     Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as set forth in the following claims.