Patent Publication Number: US-11659299-B2

Title: Imaging apparatus including unit pixel, counter electrode, photoelectric conversion layer, and voltage supply circuit

Description:
CROSS-REFERENCE OF RELATED APPLICATIONS 
     This application is a Continuation of U.S. patent application Ser. No. 16/437,975, filed on Jun. 11, 2019, which is a Continuation of U.S. patent application Ser. No. 16/241,714, filed on Jan. 7, 2019, now U.S. Pat. No. 10,368,027, which is a Continuation of U.S. patent application Ser. No. 15/872,016, filed on Jan. 16, 2018, now U.S. Pat. No. 10,212,379, which in turn claims the benefit of Japanese Application No. 2017-018769, filed on Feb. 3, 2017, the entire disclosures of which Applications are incorporated by reference herein. 
    
    
     BACKGROUND 
     1. Technical Field 
     The present disclosure relates to an imaging apparatus. 
     2. Description of the Related Art 
     Photodiodes capable of photoelectric conversion have been used as a component of image sensors. Examples of the image sensors include CCD image sensors and CMOS image sensors. There have been proposed also image sensors that include an organic semiconductor material capable of photoelectric conversion (e.g., see Japanese Unexamined Patent Application Publication No. 2007-13123). 
     There has been disclosed a method in which a plurality of photoelectric conversion films having different absorption spectra are interposed between a pair of electrodes so as to be stacked on top of one another in order to change the imaging wavelength by controlling the voltage applied between the electrodes (e.g., see Japanese Unexamined Patent Application Publication No. 2008-227092). 
     SUMMARY 
     In one general aspect, the techniques disclosed here feature an imaging apparatus including a unit pixel including a pixel electrode, a charge accumulation region electrically connected to the pixel electrode, and a signal detection circuit electrically connected to the charge accumulation region; a counter electrode facing the pixel electrode; a photoelectric conversion layer disposed between the pixel electrode and the counter electrode, the photoelectric conversion layer converting light incident on the photoelectric conversion layer into charge carriers; and a voltage supply circuit configured to selectively apply any one of a first voltage, a second voltage, and a third voltage between the pixel electrode and the counter electrode. The charge carriers are accumulated at the charge accumulation region. The photoelectric conversion layer exhibits a first wavelength sensitivity characteristic in a wavelength range when the voltage supply circuit applies the first voltage between the pixel electrode and the counter electrode. The photoelectric conversion layer exhibits a second wavelength sensitivity characteristic in the wavelength range when the voltage supply circuit applies the second voltage between the pixel electrode and the counter electrode, the second wavelength sensitivity characteristic being different from the first wavelength sensitivity characteristic. The photoelectric conversion layer becomes insensitive to light having a wavelength in the wavelength range when the voltage supply circuit applies the third voltage between the pixel electrode and the counter electrode. The voltage supply circuit applies the third voltage between the pixel electrode and the counter electrode during at least a part of a period in which the voltage supply circuit changes a voltage applied between the pixel electrode and the counter electrode from the first voltage to the second voltage or from the second voltage to the first voltage. 
     Additional benefits and advantages of the disclosed embodiments will become apparent from the specification and drawings. The benefits and/or advantages may be individually obtained by the various embodiments and features of the specification and drawings, which need not all be provided in order to obtain one or more of such benefits and/or advantages. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG.  1    is a schematic diagram illustrating an exemplary circuit structure of an imaging apparatus according to an embodiment; 
         FIG.  2    is a schematic cross-sectional view of a unit pixel, illustrating an exemplary device structure of the unit pixel; 
         FIG.  3    is a schematic cross-sectional view of a photoelectric conversion layer, illustrating an example structure of the photoelectric conversion layer; 
         FIG.  4    includes timing charts used for explaining an example of the action of an imaging apparatus according to an embodiment; 
         FIG.  5    is a graph illustrating an example of the voltage dependence of the wavelength sensitivity characteristic of a photoelectric conversion layer included in an imaging apparatus according to an embodiment; and 
         FIG.  6    includes timing charts used for explaining a comparative example of the action of an imaging apparatus according to an embodiment. 
     
    
    
     DETAILED DESCRIPTION 
     Underlying Knowledge Forming Basis of the Present Disclosure 
     Organic photoelectric conversion elements that include an organic semiconductor material have a more simple structure and are capable of being produced by a more simple process than inorganic photoelectric conversion elements that include photodiodes which are known in the related art. In addition, it is possible to readily design the wavelength range in which an organic semiconductor material contributes to photoelectric conversion. This makes it possible to realize a photoelectric conversion element having a desired wavelength sensitivity characteristic. 
     In the case where an image sensor that includes a plurality of organic photoelectric conversion elements is used, the sensitivity of the image sensor can be changed for each exposure period by changing the voltages applied to the photoelectric conversion elements, but the imaging wavelength of the image sensor cannot be changed for each exposure period. One of the methods for changing the imaging wavelength is to detachably attach a filter that transmits only light having desired wavelengths onto the front surface of the image sensor. However, in such a case, the size of the apparatus is increased. Furthermore, it is not possible to perform good imaging while the filter is attached to or removed from the image sensor. 
     Accordingly, the present disclosure provides an imaging apparatus capable of changing the imaging wavelength on a frame-to-frame basis. 
     The summary of an embodiment of the present disclosure is described below. 
     An imaging apparatus according to an embodiment of the present disclosure includes: 
     a unit pixel including
         a pixel electrode,   a charge accumulation region electrically connected to the pixel electrode, and   a signal detection circuit electrically connected to the charge accumulation region;       

     a counter electrode facing the pixel electrode; 
     a photoelectric conversion layer disposed between the pixel electrode and the counter electrode, the photoelectric conversion layer converting light incident on the photoelectric conversion layer into charge carriers; and 
     a voltage supply circuit configured to selectively apply any one of a first voltage, a second voltage, and a third voltage between the pixel electrode and the counter electrode. 
     The charge carriers are accumulated at the charge accumulation region. 
     The photoelectric conversion layer exhibits a first wavelength sensitivity characteristic in a wavelength range when the voltage supply circuit applies the first voltage between the pixel electrode and the counter electrode. 
     The photoelectric conversion layer exhibits a second wavelength sensitivity characteristic in the wavelength range when the voltage supply circuit applies the second voltage between the pixel electrode and the counter electrode, the second wavelength sensitivity characteristic being different from the first wavelength sensitivity characteristic. 
     The photoelectric conversion layer becomes insensitive to light having a wavelength in the wavelength range when the voltage supply circuit applies the third voltage between the pixel electrode and the counter electrode. 
     The voltage supply circuit applies the third voltage between the pixel electrode and the counter electrode during at least a part of a period in which the voltage supply circuit changes a voltage applied between the pixel electrode and the counter electrode from the first voltage to the second voltage or from the second voltage to the first voltage. 
     The third voltage at which the photoelectric conversion layer becomes insensitive is theoretically a voltage at which the quantum efficiency reaches 0% but practically may be set such that the amount of signal charge carriers generated in the photoelectric conversion layer by the photoelectric conversion of light in the predetermined wavelength range while the third voltage is applied to the photoelectric conversion layer is sufficiently smaller than the amount of signal charge carriers generated in the photoelectric conversion layer by the photoelectric conversion of the light in the predetermined wavelength range while the first voltage or the second voltage is applied to the photoelectric conversion layer. Specifically, it is considered that the photoelectric conversion layer is substantially insensitive during the period in which the third voltage is applied to the photoelectric conversion layer when the following condition (1) is satisfied:
 
 Q ( V   3 )/ Q ( V   1 )&lt;0.1 and  Q ( V   3 )/ Q ( V   2 )&lt;0.1  (1)
 
     where Q(V 3 ) represents the amount of signal charge carriers generated as a result of the photoelectric conversion layer receiving the light having the predetermined wavelength during the period in which the third voltage is applied to the photoelectric conversion layer, and Q(V 1 ) and Q(V 2 ) represent the amounts of signal charge carriers generated as a result of the photoelectric conversion layer receiving the light having the predetermined wavelength during the period in which the first and second voltages are applied to the photoelectric conversion layer, respectively. 
     More specifically, the following relationship (2) holds:
 
 Q ∝η( V )× T×L   (2)
 
     where Q represents the amount of signal charge carriers; η(V) represents the quantum efficiency corresponding to the voltage applied between the pixel electrode and the counter electrode; T represents the length of period during which the voltage was applied; and L represents the irradiance on the subject. 
     That is, in the case where the subject is imaged at the same irradiance, even when the quantum efficiency achieved as a result of the application of the third voltage is 1/10 of the quantum efficiency achieved as a result of the application of the first voltage, setting the length of the period during which the third voltage is applied to be 10 times the length of the period during which the first voltage is applied makes the amount of signal charge carriers generated during the first-voltage application period substantially equal to the amount of signal charge carriers generated during the third-voltage application period. As a result, the condition (1) above may fail to be satisfied. Therefore, the third voltage may be determined with consideration of not only the absolute value of the quantum efficiency but also the length of the period during which the third voltage is applied and the irradiance on the subject such that the amount of signal charge carriers generated by the application of the third voltage is sufficiently smaller than the amount of signal charge carriers generated by the application of the first or second voltage. 
     The at least a part of the period may be a readout period in which a potential of the charge accumulation region is read. 
     For example, the first wavelength sensitivity characteristic may be a characteristic of having a sensitivity equal to or higher than a first value in the visible region and having a sensitivity equal to or higher than a second value in the infrared region, and the second wavelength sensitivity characteristic may be a characteristic of having a sensitivity equal to or higher than a third value only in the visible region. Each of the sensitivity equal to or higher than the first value, the sensitivity equal to or higher than the second value and the sensitivity equal to or higher than the third value may be higher than the sensitivity of the photoelectric conversion layer when the voltage supply circuit applying the third voltage between the pixel electrode and the counter electrode. The sensitivity equal to or higher than the first value, the sensitivity equal to or higher than the second value and the sensitivity equal to or higher than the third value may be the sensitivity such that the amount of signal charge carriers generated by the photoelectric conversion layer satisfy the relationship (1). The sensitivity equal to or higher than the first value, the sensitivity equal to or higher than the second value and the sensitivity equal to or higher than the third value may be the sensitivity such that the amount of signal charge carriers generated by the photoelectric conversion layer satisfy the relationships (1) and (2). Each of the first, second and third values may be the value such that the quantum efficiency of the photoelectric conversion layer becomes equal to or higher than 10%. Each of the first, second and third values may be the value such that the quantum efficiency of the photoelectric conversion layer becomes equal to or higher than 50%. The photoelectric conversion layer having a quantum efficiency of equal to or higher than 50% is suitable for imaging application because the quantum efficiency of the image sensor which is typically manufactured is equal to or higher than 50%. 
     For example, the voltage supply circuit may apply the first voltage and the second voltage, in an alternating manner, between the pixel electrode and the counter electrode. 
     For example, the voltage supply circuit may change the voltage applied between the pixel electrode and the counter electrode between the first voltage and the second voltage at intervals of frames. 
     For example, the voltage supply circuit may change the voltage applied between the pixel electrode and the counter electrode between the first voltage and the second voltage at a certain frequency. 
     For example, the photoelectric conversion layer may have a multilayer structure including photoelectric conversion films. 
     For example, at least one of the photoelectric conversion films may include an organic material. 
     In the present disclosure, all or a part of a circuit, a unit, a device, a member, or a portion, or a part or all of functional blocks in the block diagrams may be implemented as one or more of electronic circuits including, but not limited to, a semiconductor device, a semiconductor integrated circuit (IC) or a large scale integration (LSI). The LSI or IC may be integrated into one chip, or may alternatively be a combination of plural chips. For example, functional blocks other than a memory may be integrated into one chip. Although an LSI and an IC are referred to above, the terms for the circuits may vary depending on the degree of integration; they may also be referred to as system LSI, very large scale integration (VLSI), or ultra large scale integration (ULSI). A field programmable gate array (FPGA) that can be programmed after manufacturing an LSI or a reconfigurable logic device that allows reconfiguration of the connection or setup of circuit cells inside the LSI can be used for the same purpose. 
     Furthermore, all or a part of the functions or operations of a circuit, a unit, a device, a member, or a portion may be implemented by executing software. In such a case, the software is recorded on one or more non-transitory recording media such as a ROM, an optical disk or a hard disk drive, and when the software is executed by a processor, the software causes the processor together with peripheral devices to execute the functions specified in the software. A system or apparatus may include such one or more non-transitory recording media on which the software is recorded and a processor together with necessary hardware devices such as an interface. 
     Embodiments of the present disclosure are described below in detail with reference to the attached drawings. In the following embodiments, general or specific examples are described. All the values, shapes, materials, components, the arrangement of the components, and the connection between the components, steps, the order of the steps, and the like described in the following embodiments are merely an example and are not intended to limit the scope of the present disclosure. The various aspects described herein may be combined with one another unless a contradiction arises. Among the components described in the following embodiments, components that are not described in any one of the independent claims, which indicate the broadest concepts, are described as optional components. In the following description, components that have substantially the same function are denoted by the same reference numeral, and the description thereof may be omitted. 
     Imaging Apparatus 
       FIG.  1    is an exemplary circuit structure of an imaging apparatus according to an embodiment of the present disclosure. The imaging apparatus  100  illustrated in  FIG.  1    includes a pixel array  200  that includes a plurality of unit pixels  10  arranged in a two-dimensional array.  FIG.  1    schematically illustrates an example where the unit pixels  10  are arranged in a matrix having two rows and two columns. The number and arrangement of the unit pixels  10  included in the imaging apparatus  100  are not limited to those in the example illustrated in  FIG.  1   . 
     The unit pixels  10  each include a photoelectric conversion unit  13  and a signal detection circuit  14 . As described below with reference to the drawings, the photoelectric conversion unit  13  includes two electrodes facing each other and a photoelectric conversion layer interposed therebetween and generates signal charge carriers upon receiving incident light. The photoelectric conversion unit  13  is not necessarily an element in which all the components are exclusively provided for each of the unit pixels  10 . For example, some or all of the components of the photoelectric conversion unit  13  may extend across the plurality of unit pixels  10 . In this embodiment, a portion or the entirety of the incident-light-side electrode extends across the plurality of unit pixels  10 . 
     The signal detection circuit  14  is a circuit that detects the signal generated by the photoelectric conversion unit  13 . In this example, the signal detection circuit  14  includes a signal detection transistor  24  and an address transistor  26 . The signal detection transistor  24  and the address transistor  26  are typically field-effect transistors (FETs). In this example, the signal detection transistor  24  and the address transistor  26  are N-channel metal oxide semiconductor field effect transistors (MOSFETs). 
     As described schematically in  FIG.  1   , the control terminal (i.e., the gate) of the signal detection transistor  24  is electrically connected to the photoelectric conversion unit  13 . The signal charge carriers (i.e., holes or electrons) generated by the photoelectric conversion unit  13  are accumulated at a charge accumulation node  41  (also referred to as “floating diffusion node”), which is located between the gate of the signal detection transistor  24  and the photoelectric conversion unit  13 . The charge accumulation node  41  corresponds to a charge accumulation region. The detailed structure of the photoelectric conversion unit  13  is described below. 
     The photoelectric conversion unit  13  included in each unit pixel  10  is further connected to the corresponding one of sensitivity control lines  42 . In the example structure illustrated in  FIG.  1   , the sensitivity control lines  42  are connected to a voltage supply circuit  32 . The voltage supply circuit  32  is a circuit capable of selectively applying any one of at least three types of voltages, that is, a first voltage, a second voltage, and a third voltage, to the photoelectric conversion units  13 . While the imaging apparatus  100  is operated, the voltage supply circuit  32  applies a predetermined voltage to the photoelectric conversion units  13  through the sensitivity control lines  42 . The voltage supply circuit  32  is not limited to a specific power source circuit. The voltage supply circuit  32  may be a circuit that generates the predetermined voltage or a circuit that converts a voltage applied by another power source into the predetermined voltage. As is described below in detail, upon the voltage supply circuit  32  changing the voltage applied to the photoelectric conversion units  13  among the plurality of voltages different from one another, the accumulation of the signal charge carriers generated by the photoelectric conversion unit  13  at the charge accumulation node  41  is started or terminated. In other words, in this embodiment, upon the voltage supply circuit  32  changing the voltage applied to the photoelectric conversion unit  13  from the third voltage to another voltage, the action of an electronic shutter is executed. An example of the action of the imaging apparatus  100  is described below. 
     The unit pixels  10  are each connected to a power source line  40 , through which a power source voltage VDD is supplied. As illustrated in  FIG.  1   , the power source line  40  is connected to the input terminal (typically, the drain) of the signal detection transistor  24 . The power source line  40  serves as a source-follower power source, which enables the signal detection transistor  24  to amplify the signal charge carriers generated by the photoelectric conversion unit  13  to a voltage appropriate to the signal charge carriers and to output the amplified signal as a signal voltage. 
     The output terminal (i.e., the source) of the signal detection transistor  24  is connected to the input terminal (i.e., the drain) of the address transistor  26 . The output terminal (i.e., the source) of the address transistor  26  is connected to the corresponding one of a plurality of vertical signal lines  47 , which are provided for the respective columns of the pixel array  200 . The control terminal (i.e., the gate) of the address transistor  26  is connected to the corresponding one of address control lines  46 . Controlling the potentials of the address control lines  46  enables the data output from the signal detection transistors  24  to be each selectively read through the corresponding one of the vertical signal lines  47 . 
     In the example illustrated in  FIG.  1   , the address control lines  46  are connected to a vertical scanning circuit  36  (also referred to as “row scanning circuit”). The vertical scanning circuit  36  selects a plurality of the unit pixels  10  disposed in each row on a row-by-row basis by applying a predetermined voltage to the corresponding one of the address control lines  46 . This enables the readout of the signals from the selected unit pixels  10 . 
     The vertical signal lines  47  are main signal lines through which pixel signals output from the pixel array  200  are transmitted to the peripheral circuits. The vertical signal lines  47  are each connected to the corresponding one of column-signal processing circuits  37  (also referred to as “row-signal accumulation circuits”). The column-signal processing circuits  37  perform noise-reduction signal processing, such as correlated double sampling, analog-digital conversion (AD conversion), and the like. As illustrated in  FIG.  1   , the column-signal processing circuits  37  are provided for the respective columns of the unit pixels  10  in the pixel array  200 . The column-signal processing circuits  37  are connected to a horizontal signal readout circuit  38  (also referred to as “column-scanning circuit”), which sequentially reads a signal from each of the column-signal processing circuits  37  to a horizontal common signal line  49 . 
     In the example structure illustrated in  FIG.  1   , the unit pixels  10  each include a reset transistor  28 . The reset transistor  28  is a field-effect transistor or the like, similarly to the signal detection transistor  24  and the address transistor  26 . In the example described below, the reset transistor  28  is an N-channel MOSFET unless otherwise specified. As illustrated in  FIG.  1   , the reset transistor  28  is connected to a reset voltage line  44 , through which a reset voltage Vr is supplied, and to the charge accumulation node  41 . The control terminal (i.e., the gate) of the reset transistor  28  is connected to the corresponding one of reset control lines  48 , and the potential of the charge accumulation node  41  can be reset to the reset voltage Vr by controlling the potential of the reset control line  48 . In this example, the reset control lines  48  are connected to the vertical scanning circuit  36 . Thus, it is possible to reset a plurality of the unit pixels  10  which are disposed in each row on a row-by-row basis by the vertical scanning circuit  36  applying a predetermined voltage to the corresponding one of the reset control lines  48 . 
     In this example, the reset voltage line  44 , through which the reset voltage Vr is supplied to the reset transistors  28 , is connected to a reset voltage source  34 . The reset voltage source  34  may have any structure that allows a predetermined reset voltage Vr to be supplied through the reset voltage line  44  during the operation of the imaging apparatus  100  and is not limited to a specific power source circuit, similarly to the voltage supply circuit  32  described above. The voltage supply circuit  32  and the reset voltage source  34  may be parts of a single voltage supply circuit or independent voltage supply circuits. One or both of the voltage supply circuit  32  and the reset voltage source  34  may be a part of the vertical scanning circuit  36 . Alternatively, a sensitivity control voltage may be applied by the voltage supply circuit  32  to the unit pixels  10  via the vertical scanning circuit  36 , and/or the reset voltage Vr may be applied by the reset voltage source  34  to the unit pixels  10  via the vertical scanning circuit  36 . 
     The power source voltage VDD supplied to the signal detection circuits  14  may be used also as a reset voltage Vr. In such a case, the reset voltage source  34  may be used also as a voltage supply circuit (not illustrated in  FIG.  1   ) that supplies a power source voltage to the unit pixels  10 . Furthermore, it is possible to use the power source line  40  also as the reset voltage line  44 , which allows the arrangement of wires in the pixel array  200  to be simplified. However, setting the reset voltage Vr to be different from the power source voltage VDD supplied to the signal detection circuits  14  increases the degree of flexibility in the control of the imaging apparatus  100 . 
     Device Structure of Unit Pixel 
       FIG.  2    schematically illustrates an exemplary device structure of the unit pixels  10 . In the exemplary structure illustrated in  FIG.  2   , the above-described signal detection transistor  24 , the address transistor  26 , and the reset transistor  28  are disposed on a semiconductor substrate  20 . The semiconductor substrate  20  is not limited to a substrate the entirety of which is composed of a semiconductor and may be an insulating substrate that includes a semiconductor layer disposed on a surface thereof on which a photosensitive region is to be formed. In the example described below, a p-type silicon (Si) substrate is used as a semiconductor substrate  20 . 
     The semiconductor substrate  20  includes impurity regions (in this example, N-type regions)  26   s ,  24   s ,  24   d ,  28   d , and  28   s . The semiconductor substrate  20  also includes element separation regions  20   t  in order to electrically separate the unit pixels  10  from one another. In this example, an element separation region  20   t  is interposed also between the impurity regions  24   d  and  28   d . The element separation regions  20   t  can be formed by, for example, injecting acceptor ions into the semiconductor substrate  20  under predetermined injection conditions. 
     The impurity regions  26   s ,  24   s ,  24   d ,  28   d , and  28   s  are typically diffusion layers formed in the semiconductor substrate  20 . As schematically illustrated in  FIG.  2   , the signal detection transistor  24  includes impurity regions  24   s  and  24   d  and a gate electrode  24   g  (typically, a polysilicon electrode). The impurity regions  24   s  and  24   d  serve as, for example, the source region and the drain region, respectively, of the signal detection transistor  24 . The channel region of the signal detection transistor  24  is formed between the impurity regions  24   s  and  24   d.    
     Similarly to the signal detection transistor  24 , the address transistor  26  includes impurity regions  26   s  and  24   s  and a gate electrode  26   g  (typically, a polysilicon electrode), which is connected to the corresponding one of the address control lines  46  (see  FIG.  1   ). In this example, the signal detection transistor  24  and the address transistor  26  are electrically connected to each other by sharing the impurity region  24   s . The impurity region  26   s  serves as, for example, the source region of the address transistor  26 . The impurity region  26   s  is connected to the corresponding one of vertical signal lines  47 , which is not illustrated in  FIG.  2    (see  FIG.  1   ). 
     The reset transistor  28  includes impurity regions  28   d  and  28   s  and a gate electrode  28   g  (typically, a polysilicon electrode) connected to the corresponding one of reset control lines  48  (see  FIG.  1   ). The impurity region  28   s  serves as, for example, the source region of the reset transistor  28 . The impurity region  28   s  is connected to the reset voltage line  44 , which is not illustrated in  FIG.  2    (see  FIG.  1   ). 
     An interlayer insulating layer  50  (typically, a silicon dioxide layer) is disposed on the semiconductor substrate  20  so as to cover the signal detection transistor  24 , the address transistor  26 , and the reset transistor  28 . The interlayer insulating layer  50  may include a wiring layer  56  formed therein as illustrated in  FIG.  2   . The wiring layer  56  is typically composed of a metal, such as copper, and may include wires such as the vertical signal lines  47  described above. The number of insulating sublayers constituting the interlayer insulating layer  50  and the number of wiring sublayers constituting the wiring layer  56  formed in the interlayer insulating layer  50  may be set appropriately and not limited to those in the example illustrated in  FIG.  2   . 
     The above-described photoelectric conversion unit  13  is disposed on the interlayer insulating layer  50 . In other words, in this embodiment, a plurality of unit pixels  10  constituting a pixel array  200  (see  FIG.  1   ) are formed on the semiconductor substrate  20 . The unit pixels  10 , which are arranged on the semiconductor substrate  20  in a two-dimensional array, form a photosensitive region. The distance (i.e., pixel pitch) between a pair of adjacent unit pixels  10  is, for example, about 2 μm. 
     The photoelectric conversion unit  13  includes a pixel electrode  11 , a counter electrode  12 , and a photoelectric conversion layer  15  interposed therebetween. In this example, the counter electrode  12  and the photoelectric conversion layer  15  are formed so as to extend across a plurality of the unit pixels  10 . 
     On the other hand, each of the unit pixels  10  is provided with one pixel electrode  11 . Each of the pixel electrodes  11  is electrically separated from other pixel electrodes  11  included in the adjacent unit pixels  10  by being spatially separated from them. 
     The counter electrode  12  is typically a transparent electrode composed of a transparent conducting material. The counter electrode  12  is disposed on a side of the photoelectric conversion layer  15  on which light enters. That is, light that have permeated through the counter electrode  12  enters the photoelectric conversion layer  15 . The wavelength of light that can be detected by the imaging apparatus  100  is not limited to be within the wavelength range (e.g., 380 nm or more and 780 nm or less) of visible light. The term “transparent” used herein refers to passing at least part of light having a wavelength that falls within the detectable wavelength range. Hereinafter, all electromagnetic waves including infrared radiation and ultraviolet radiation are collectively referred to as “light” for the sake of convenience. The counter electrode  12  may be composed of, for example, a transparent conducting oxide (TCO), such as indium-doped tin oxide (ITO), indium zinc oxide (IZO), aluminium-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), SnO 2 , TiO 2 , or ZnO 2 . 
     The photoelectric conversion layer  15  generates electron-hole pairs upon receiving the incident light. In this embodiment, the photoelectric conversion layer  15  is composed of an organic material. Specific examples of the material for the photoelectric conversion layer  15  are described below. 
     As described above with reference to  FIG.  1   , the counter electrode  12  is connected to the corresponding one of the sensitivity control lines  42 , which are connected to the voltage supply circuit  32 . In this embodiment, the counter electrode  12  is formed so as to extend across a plurality of the unit pixels  10 . This enables the voltage supply circuit  32  to apply a desired sensitivity control voltage to a plurality of the unit pixels  10  at a time through the sensitivity control lines  42 . Each of the unit pixels  10  may be provided with one counter electrode  12  as long as a desired sensitivity control voltage can be applied from the voltage supply circuit  32 . Similarly, each of the unit pixels  10  may be provided with one photoelectric conversion layer  15 . 
     As described below in detail, the voltage supply circuit  32  applies different voltages to the counter electrode  12  during the exposure period and the non-exposure period. The term “exposure period” used herein refers to the period in which positive or negative charge carriers generated by the photoelectric conversion are accumulated at the charge accumulation region and may be referred to also as “charge accumulation period”. The term “non-exposure period” used herein refers to the period in which the imaging apparatus is operated and which is other than the exposure period. The “non-exposure period” is not limited to the period during which the photoelectric conversion unit  13  is not irradiated with light and may include the period during which the photoelectric conversion unit  13  is irradiated with light. 
     Controlling the potential of the counter electrode  12  with respect to the pixel electrode  11  enables holes or electrons of the electron-hole pairs generated in the photoelectric conversion layer  15  by photoelectric conversion to be collected by the pixel electrode  11 . For example, in the case where holes are used as signal charge carriers, setting the potential of the counter electrode  12  to be higher than that of the pixel electrode  11  enables the holes to be selectively collected by the pixel electrode  11 . In the example described below, holes are used as signal charge carriers. Needless to say that electrons may alternatively be used as signal charge carriers. 
     The pixel electrode  11 , which faces the counter electrode  12 , collects positive or negative charge carriers generated in the photoelectric conversion layer  15  by photoelectric conversion upon an appropriate bias voltage being applied between the counter electrode  12  and the pixel electrode  11 . The pixel electrode  11  is composed of a metal, such as aluminium or copper, a nitride of the metal, or a polysilicon or the like which is made conductive by being doped with an impurity. 
     The pixel electrode  11  may have a light-blocking property. When the pixel electrode  11  is, for example, a TaN electrode having a thickness of 100 nm, the pixel electrode  11  may have a sufficient light-blocking property. Using an electrode having a light-blocking property as a pixel electrode  11  may reduce the intrusion of light that permeates through the photoelectric conversion layer  15  into the channel regions or the impurity regions of the transistors (in this example, at least one of the signal detection transistor  24 , the address transistor  26 , and the reset transistor  28 ) formed on the semiconductor substrate  20 . A light-blocking film may optionally be formed in the interlayer insulating layer  50  by using the wiring layer  56  described above. Reducing the intrusion of the light into the channel regions of the transistors formed on the semiconductor substrate  20  may limit a shift of the properties of the transistors (e.g., the fluctuations in threshold voltage). Reducing the intrusion of the light into the impurity regions formed on the semiconductor substrate  20  may limit the mixing of noises generated as a result of unintended photoelectric conversion occurring in the impurity regions. Thus, reducing the intrusion of the light into the semiconductor substrate  20  increases the reliability of the imaging apparatus  100 . 
     As schematically illustrated in  FIG.  2   , the pixel electrode  11  is connected to the gate electrode  24   g  of the signal detection transistor  24  with a plug  52 , a wire  53 , and a contact plug  54 . In other words, the gate of the signal detection transistor  24  is electrically connected with the pixel electrode  11 . The plug  52  and the wire  53  are composed of, for example, a metal, such as copper. The plug  52 , the wire  53 , and the contact plug  54  constitute at least a part of the charge accumulation node  41  (see  FIG.  1   ), which is located between the signal detection transistor  24  and the photoelectric conversion unit  13 . The wire  53  may constitute a part of the wiring layer  56 . The pixel electrode  11  is also connected to the impurity region  28   d  with the plug  52 , the wire  53 , and a contact plug  55 . In the exemplary structure illustrated in  FIG.  2   , the gate electrode  24   g  of the signal detection transistor  24 , the plug  52 , the wire  53 , the contact plugs  54  and  55 , and the impurity region  28   d , which serves as a source or drain region of the reset transistor  28 , serve as a charge accumulation region at which the signal charge carriers collected by the pixel electrode  11  are accumulated. 
     Upon the signal charge carriers being collected by the pixel electrode  11 , a voltage responsive to the amount of signal charge carriers accumulated at the charge accumulation region is applied to the gate of the signal detection transistor  24 . The signal detection transistor  24  amplifies the voltage. The voltage amplified by the signal detection transistor  24  is selectively read as a signal voltage via the address transistor  26 . 
     Example Structure of Photoelectric Conversion Layer 
     As described above, when the photoelectric conversion layer  15  is irradiated with light and a bias voltage is applied between the pixel electrode  11  and the counter electrode  12 , positive or negative charge carriers generated by photoelectric conversion are collected by the pixel electrode  11  and the collected charge carriers are accumulated at the charge accumulation region. In this embodiment, the photoelectric conversion unit  13  includes a photosensitive layer  15 A including two photoelectric conversion films that have different absorption spectra and stacked on top of each other under specific conditions, which is described below. This enables the wavelength sensitivity characteristic of the photoelectric conversion layer  15 , that is, the imaging wavelength range, to be changed by controlling the difference in potential between the pixel electrode  11  and the counter electrode  12 . Furthermore, limiting the difference in potential between the pixel electrode  11  and the counter electrode  12  to be equal to or smaller than a predetermined potential prevents the migration of the signal charge carriers accumulated at the charge accumulation region into the counter electrode  12  through the photoelectric conversion layer  15 . Limiting the difference in potential between the pixel electrode  11  and the counter electrode  12  to be equal to or smaller than a predetermined potential also reduces the likelihood of the signal charge carriers being further accumulated at the charge accumulation region. The above is one of the findings made by the inventors. That is, it is possible to achieve a global shutter and electrical switchover of the imaging wavelength by controlling the bias voltage applied to the photoelectric conversion layer  15  without optional elements such as transfer transistors being disposed on the respective pixels. A typical example of the action of the imaging apparatus  100  is described below. 
     An example structure of the photoelectric conversion layer  15  and the wavelength sensitivity characteristic of the photoelectric conversion layer  15  are described below. 
       FIG.  3    is a schematic cross-sectional view of a photoelectric conversion layer  15 , illustrating an example structure of the photoelectric conversion layer  15 . In the structure illustrated in  FIG.  3   , the photoelectric conversion layer  15  includes a hole-blocking layer  15   h , the photosensitive layer  15 A, and an electron-blocking layer  15   e . The hole-blocking layer  15   h  is interposed between the photosensitive layer  15 A and the counter electrode  12 . The electron-blocking layer  15   e  is interposed between the photosensitive layer  15 A and the pixel electrode  11 . The photoelectric conversion layer  15  typically includes a semiconductor material. In this embodiment, an organic semiconductor material is used as a semiconductor material. The organic semiconductor material may be any organic semiconductor material that has absorption peaks at imaging wavelengths required for imaging. Common photoelectric conversion films are produced from a mixture of an electron-donating organic semiconductor material and an electron-accepting organic semiconductor material. This enables the strength of electric field required for separating excitons generated in the photoelectric conversion layer  15  into electrons and holes to be reduced to a level adequate for use as a semiconductor element. In other words, the quantum efficiency at the same voltage may be increased, and the photoelectric conversion characteristic may be improved. 
     In this embodiment, a first photoelectric conversion film  150   a  disposed on the counter-electrode- 12 -side has a wavelength sensitivity characteristic such that the first photoelectric conversion film  150   a  is sensitive only in the visible region, and the second photoelectric conversion film  150   b  disposed on the pixel-electrode- 11 -side has a wavelength sensitivity characteristic such that the second photoelectric conversion film  150   b  has a sensitivity in the visible region and a higher sensitivity in the infrared region than in the visible region. Hereinafter, having a sensitivity lower than one tenth of the peak wavelength is considered to be having no sensitivity. 
     Since the photoelectric conversion layer  15  is composed of organic semiconductor materials, it is possible to control the amount of signal charge carriers that reach the pixel electrode  11  by changing the voltage applied between the counter electrode  12  and the pixel electrode  11 . This is because an organic semiconductor material has a considerably low carrier transporting capability and, therefore, the charge carriers generated in the photoelectric conversion layer  15  may be lost as a result of, for example, recombination while migrating through the photoelectric conversion layer  15  when the strength of the electric field that attracts the charge carriers toward the pixel electrode  11  is not large. 
     In this embodiment, the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  that have different absorption spectra are interposed between the counter electrode  12  and the pixel electrode  11 . This enables the amount of signal charge carriers transported to the pixel electrode  11  to be controlled in accordance with the voltage applied between the counter electrode  12  and the pixel electrode  11  only when the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  satisfy predetermined conditions. This is also one of the findings made by the inventors. 
     An example of the predetermined conditions is to make the resistances of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  different from each other by a certain degree or more. The voltage applied between the counter electrode  12  and the pixel electrode  11  is distributed at the ratio between the resistances of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b . Making the resistances of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  different from each other by, for example, 44 times or more enables most of the voltage applied between the electrodes to be distributed to the photoelectric conversion film having a higher resistance and the voltage distributed to the other photoelectric conversion film to be reduced to the photoelectric conversion threshold or less. Therefore, when the voltage applied between the counter electrode  12  and the pixel electrode  11  is low, an electric field equal to or higher than the photoelectric conversion threshold is applied only to the photoelectric conversion film having a higher resistance, and only the signal charge carriers generated in the photoelectric conversion film having a higher resistance are transported to the pixel electrode  11 . When the voltage applied between the counter electrode  12  and the pixel electrode  11  is increased, an electric field equal to or higher than the photoelectric conversion threshold is applied also to the photoelectric conversion film having a lower resistance, and the photoelectric conversion film having a lower resistance becomes capable of transporting the signal charge carriers to the pixel electrode  11 . The resistance of each of the photoelectric conversion films can be adjusted by changing the energy levels of an electron-donating material and an electron-accepting material that constitute the photoelectric conversion film, the mixing ratio between the electron-donating material and the electron-accepting material, the thickness of the photoelectric conversion film, and the like. 
     When the voltage applied to the photoelectric conversion layer  15  (i.e., the voltage applied between the counter electrode  12  and the pixel electrode  11 ) is lower than both of the photoelectric conversion thresholds of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  stacked on top of each other, both photoelectric conversion layers become incapable of transporting the signal charge carriers to the pixel electrode. As a result, the sensitivities of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  become substantially zero, and the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  become insensitive. Thus, by selecting the voltage applied between the counter electrode  12  and the pixel electrode  11 , it is possible to perform a switchover among the state in which the photoelectric conversion films do not have a photoelectric conversion sensitivity over the entire wavelength range, the state in which only one of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  constituting the photosensitive layer  15 A has a photoelectric conversion sensitivity, and the state in which both of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  constituting the photosensitive layer  15 A have a photoelectric conversion sensitivity. As described above, it is possible to change the wavelength sensitivity characteristic of the photoelectric conversion layer  15 , that is, the imaging wavelength range, and to execute the action of an electronic shutter by changing the difference in potential between the pixel electrode  11  and the counter electrode  12 . 
     The first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  may be, for example, a film formed by the code position of 2-{[7-(5-N,N-ditolylaminothiophen-2-yl)-2,1,3-benzothiadiazol-4-yl]methylene}malononitrile (DTDCTB) and C 70  fullerene or a film formed by the code position of tin naphthalocyanine and C 70  fullerene. Specifically, the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  may be composed of the following materials. The first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  typically each include an electron-donating (i.e., donor-type or p-type) molecule and an electron-accepting (i.e., acceptor-type or n-type) molecule. 
     A typical example of the electron-donating molecule is a p-type organic semiconductor which is likely to donate electrons, such as a hole-transporting organic compound. Examples of the p-type organic semiconductor include triarylamines, such as DTDCTB; benzidines; pyrazolines; styrylamines; hydrazones; triphenylmethanes; carbazoles; polysilanes; thiophenes, such as α-sexithiophene (α-6T) and poly-3-hexylthiophene (P3HT); phthalocyanines; cyanines; merocyanines; oxonols; polyamines; indoles; pyrroles; pyrazoles; polyarylenes; condensed aromatic carbocyclic compounds (e.g., a naphthalene derivative, an anthracene derivative, a phenanthrene derivative, a tetracene derivative, such as rubrene, a pyrene derivative, a perylene derivative, and a fluoranthene derivative); and metal complexes including a ligand that is a nitrogen-containing heterocyclic compound. Examples of the phthalocyanines include copper phthalocyanine (Cu Pc), subphthalocyanine (SubPc), aluminum chloride phthalocyanine (CIAIPc), Si(OSiR 3 ) 2 Nc (where R represents an alkyl group having 1 to 18 carbon atoms and Nc represents naphthalocyanine), tin naphthalocyanine (SnNc), and lead phthalocyanine (PbPc). Examples of the donor-type organic semiconductor are not limited to the above compounds. Any organic compound having a lower ionization potential than an organic compound used as an n-type (acceptor-type) organic compound may be used as a donor-type organic semiconductor. The ionization potential is the difference in energy level between the vacuum level and the highest occupied molecular orbital (HOMO). 
     A typical example of the electron-accepting molecule is an n-type organic semiconductor that is likely to accept electrons, such as an electron-transporting organic compound. Examples of the n-type organic semiconductor include fullerene (e.g., C 60  or C 70 ), fullerene derivatives (e.g., phenyl-C 61 -butyric acid methyl ester (PCBM)), condensed aromatic carbocyclic compounds (e.g., a naphthalene derivative, an anthracene derivative, a phenanthrene derivative, a tetracene derivative, a pyrene derivative, a perylene derivative, and a fluoranthene derivative), five- or seven-membered heterocyclic compounds containing a nitrogen atom, an oxygen atom, or a sulfur atom (e.g., pyridine, pyradine, pyrimidine, pyridadine, triazine, quinoline, quinoxaline, quinazoline, phthalazine, cinnoline, isoquinoline, pteridine, acridine, phenazine, phenanthroline, tetrazole, pyrazole, imidazole, thiazole, oxazole, indazole, benzimidazole, benzotriazole, benzoxazole, benzothiazole, carbazole, purine, triazolopyridadine, triazolopyrimidine, tetrazaindene, oxadiazole, imidazopyridine, pyrrolidine, pyrrolopyridine, thiadiazolopyridine, dibenzazepine, and tribenzazepine), subphthalocyanines (SubPc), polyarylenes, fluorenes, cyclopentadienes, silyl compounds, perylenetetracarboxylic diimides (PTCDI), and metal complexes including a nitrogen-containing heterocyclic compound as a ligand. Examples of the acceptor-type organic semiconductor are not limited to the above compounds. Any organic compound having a larger electron affinity than an organic compound used as a p-type (donor-type) organic compound may be used as an acceptor-type organic semiconductor. The electron affinity is the difference in energy level between the vacuum level and the lowest unoccupied molecular orbital (LUMO). 
     The first photoelectric conversion film  150   a  may be composed of, for example, an organic semiconductor material having a photoelectric conversion sensitivity in the visible region. The second photoelectric conversion film  150   b  may be composed of, for example, an organic semiconductor material having a sensitivity in the infrared region. 
     The above-described advantageous effects may also be achieved by creating an energy barrier at the interface between the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  of the photosensitive layer  15 A. For example, in the case where holes are to be accumulated as signal charge carriers, the ionization potentials of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  are selected such that an energy barrier of, for example, 0.2 eV or more to holes is created at the interface between the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b  of the photosensitive layer  15 A. 
     In the case where an energy barrier is not created at the interface between the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b , the voltage dependence of the wavelength sensitivity characteristic varies with the resistances of the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b , and the order in which the photoelectric conversion films are stacked on top of each other does not affect the action of switchover of the wavelength sensitivity characteristic. However, there are preferable stacking conditions in terms of the efficiency of photoelectric conversion. As described above, the photoelectric conversion films are commonly composed of a mixture of an electron-donating organic semiconductor material and an electron-accepting organic semiconductor material. The electron-accepting material may be C 60  fullerene, C 70  fullerene, or an analog to these fullerenes. This is because the LUMO of fullerene spreads spatially in the form of a spherical shell, which enables electrons to migrate from an electron-donating organic semiconductor material that is brought into contact with the electron-accepting material into fullerene molecules with high efficiency. Accordingly, in order to produce a high-efficiency photoelectric conversion element, the photoelectric conversion films may be formed using a mixture of an electron-donating organic semiconductor material having an absorption at desired wavelengths and fullerene or an analog to fullerene. It is known that fullerene and analogs to fullerene commonly have a strong absorption in the visible region and, in particular, at wavelengths corresponding to blue. Therefore, an infrared photoelectric conversion film composed of an electron-donating organic semiconductor material having an absorption at the infrared region and fullerene or an analog to fullerene has an absorption in not only the infrared region but also the visible region. In such a case, if the photoelectric conversion films are stacked on top of each other such that the first photoelectric conversion film  150   a  is the infrared photoelectric conversion film and the second photoelectric conversion film  150   b  is a visible photoelectric conversion film sensible in the visible region, the first photoelectric conversion film disposed on the light-incident side absorbs part of the visible light and reduces the amount of visible light incident on the second photoelectric conversion film, which is a visible photoelectric conversion film. Therefore, in such a case, using the visible photoelectric conversion film and the infrared photoelectric conversion film as the first photoelectric conversion film  150   a  and the second photoelectric conversion film  150   b , respectively, may limit the reduction in the amount of visible light incident on the second photoelectric conversion film. On the other hand, a visible photoelectric conversion film composed of an electron-donating organic semiconductor capable of absorbing visible light and fullerene or an analog to fullerene does not have an absorption in the infrared region. Therefore, even when the above visible photoelectric conversion film is disposed on the light-incident side, it allows infrared light to transmit therethrough and enables a sufficient amount of infrared light to reach the infrared photoelectric conversion film. As described above, in order to perform imaging in a suitable manner, the order in which the plurality of photoelectric conversion films are stacked on top of one another may be determined such that a sufficient amount of light of desired wavelengths reaches a desired photoelectric conversion film. 
     Example Action of Imaging Apparatus  100   
       FIG.  4    includes timing charts for explaining an example of the action of the imaging apparatus according to an embodiment of the present disclosure.  FIGS.  4 ( a ) and  4 ( b )  each illustrate the timing of the rise or fall of a synchronizing signal.  FIG.  4 ( c )  illustrates a change in the bias voltage applied to the photoelectric conversion layer  15  with time.  FIG.  4 ( d )  illustrates the timing of the reset and exposure of each row of the pixel array  200  (see  FIG.  1   ). Specifically,  FIG.  4 ( a )  illustrates the timing of the rise or fall of a vertical synchronizing signal Vss.  FIG.  4 ( b )  illustrates the timing of the rise or fall of a horizontal synchronizing signal Hss.  FIG.  4 ( c )  illustrates a change, with time, in the voltage Vb applied from the voltage supply circuit  32  to the counter electrodes  12  via the sensitivity control lines  42 .  FIG.  4 ( d )  illustrates the timing of the reset and exposure of each row of the pixel array  200 . The change, with time, in the voltage Vb applied from the voltage supply circuit  32  to the counter electrodes  12  via the sensitivity control lines  42  corresponds to a change, with time, in the potential of the counter electrode  12  with respect to the potential of the pixel electrode  11 . 
     While  FIG.  4    illustrates an example case where the pixel array  200  includes unit pixels  10  arranged in three rows for the sake of simplicity, the unit pixels included in the pixel array  200  may be arranged in four or more rows. 
     An example of the action of the imaging apparatus  100  is described below with reference to  FIGS.  1 ,  2 , and  4   . For the sake of simplicity, an example of the action of an imaging apparatus  100  that includes a pixel array  200  including pixels arranged in three rows in total, that is, the row &lt; 0 &gt;, the row &lt; 1 &gt;, and the row &lt; 2 &gt;, is described below. 
     For acquiring an image, first, the charge accumulation region of each of the unit pixels  10  included in the pixel array  200  is reset and, when the pixel array  200  has been exposed to light prior to resetting, a pixel signal is read from each of the reset unit pixels  10 . For example, as illustrated in  FIG.  4   , the resetting of a plurality of pixels in the row &lt; 0 &gt; is started in response to the vertical synchronizing signal Vss (Time t 0 ). In  FIG.  4   , the shaded rectangular portions schematically represent a period in which a signal is read. The readout period includes a resetting period in which the potential of the charge accumulation region of each unit pixel  10  is reset. 
     For resetting the pixels in the row &lt; 0 &gt;, the address transistors  26  whose gates are connected to the specific one of the address control lines  46  which is associated with the row &lt; 0 &gt; are turned on by controlling the potential of the address control line  46 . Furthermore, the reset transistors  28  whose gates are connected to the specific one of the reset control lines  48  which is associated with the row &lt; 0 &gt; are turned on by controlling the potential of the reset control line  48 . Thus, the charge accumulation node  41  and the reset voltage line  44  are connected to each other, and a reset voltage Vr is supplied to the charge accumulation node  41 , which is the charge accumulation region. Specifically, the potential of the gate electrode  24   g  of each signal detection transistor  24  and the potential of the pixel electrode  11  of each photoelectric conversion unit  13  are reset to be the reset voltage Vr. Subsequently, a pixel signal is read from each of the reset unit pixels  10  in the row &lt; 0 &gt; via the corresponding one of the vertical signal lines  47 . These pixel signals are responsive to the reset voltage Vr. Subsequent to the readout of the pixel signals, the reset transistors  28  and the address transistors  26  are turned off. 
     In this example, the pixels in each of the row &lt; 0 &gt;, the row &lt; 1 &gt;, and the row &lt; 2 &gt; are reset sequentially on a row-by-row basis in response to the horizontal synchronizing signal Hss as schematically illustrated in  FIG.  4   . Hereinafter, the intervals between the pulses of the horizontal synchronizing signal Hss, that is, the period from when a row is selected to when the next row is selected, is referred to as “1H period”. In this example, the period between Time t 0  and Time t 1  corresponds to the 1H period. 
     As illustrated in  FIG.  4   , a third voltage V 3  at which the sensitivity of the photoelectric conversion layer  15  in a predetermined wavelength range becomes substantially zero is applied by the voltage supply circuit  32  between the pixel electrode  11  and the counter electrode  12  during at least a resetting period in which all of the charge accumulation regions included in the respective unit pixels  10  of the pixel array  200  are reset and the period (Time t 0  to Time t 3 ) from the start of the acquisition of the image to the end of the resetting of all the rows of the pixel array  200  and the readout of pixel signals. The third voltage V 3  is, for example, 0 volt (V). In other words, applying a bias voltage, that is, the third voltage V 3 , to the photoelectric conversion layer  15  included in the photoelectric conversion unit  13  creates the period from the timing (Time t 0 ) of the start of the acquisition of the image signal from the pixel array  200  to the start (Time t 3 ) of the exposure period, that is, the non-exposure period. 
     While the bias voltage, that is, the third voltage V 3 , is applied to the photoelectric conversion layer  15 , the migration of signal charge carriers from the photoelectric conversion layer  15  to the charge accumulation region is negligible. This is presumably because, while the bias voltage, that is, the third voltage V 3 , is applied to the photoelectric conversion layer  15 , positive and negative charge carriers generated as a result of the photoelectric conversion layer  15  being irradiated with light quickly recombine with each other and disappear before collected by the pixel electrode  11 . Accordingly, while the bias voltage, that is, the third voltage V 3 , is applied to the photoelectric conversion layer  15 , the accumulation of signal charge carriers at the charge accumulation region is negligible even when the photoelectric conversion layer  15  is irradiated with light. This reduces the occurrence of unintended sensitivity in the non-exposure period (hereinafter, this sensitivity is referred to as “parasitic sensitivity”). 
     In a row (e.g., the row &lt; 0 &gt;) of  FIG.  4 ( d ) , the periods represented by the heavily shaded rectangular portion and the lightly shaded rectangular portion are non-exposure periods. The third voltage V 3  is not limited to be 0 V. 
     Subsequent to the resetting of all the rows of the pixel array  200  and the readout of pixel signals, exposure is started in response to the horizontal synchronizing signal Hss (Time t 3 ). In  FIG.  4 ( d ) , the blank rectangular portions schematically represent the exposure period in each row. In  FIG.  4   , the non-exposure periods denoted by the shaded rectangle portions have the same length as the exposure periods denoted by the blank rectangular portions for the sake of simplicity; the non-exposure periods and the exposure periods do not necessarily have the same length. The length of the exposure periods may be adjusted adequately in accordance with the darkness of the subject, the speed of motion of the subject, and the like. The exposure period starts upon the voltage supply circuit  32  changing the voltage applied between the pixel electrode  11  and the counter electrode  12  to a first voltage V 1  or a second voltage V 2  which is different from the third voltage V 3 . The first voltage V 1  is, for example, the voltage at which the photoelectric conversion thresholds of all the sublayers of the photosensitive layer  15 A are reached and all the sublayers of the photosensitive layer  15 A come to have a sensitivity. Upon the first voltage V 1  being applied to the photoelectric conversion layer  15 , the signal charge carriers (in this example, holes) generated in the photoelectric conversion layer  15  are collected by the pixel electrode  11  and accumulated at the charge accumulation region.  FIG.  5    illustrates an example of the voltage dependence of the wavelength sensitivity characteristic of the photoelectric conversion layer  15  included in the imaging apparatus  100  according to the embodiment. 
     In this embodiment, signal charge carriers generated by the photoelectric conversion of light in the visible and infrared regions are accumulated at the charge accumulation region in accordance with the wavelength sensitivity characteristic illustrated in  FIG.  5   . In  FIG.  4 ( d ) , the periods denoted by the blank rectangular portions labeled as “RGB+IR” are the exposure periods during which signal charge carriers generated by the photoelectric conversion of light in the visible and infrared regions are accumulated at the charge accumulation region. 
     The exposure period is terminated upon the voltage supply circuit  32  changing the voltage applied between the pixel electrode  11  and the counter electrodes  12  to the third voltage V 3  (Time t 6 ). Subsequently, signal charge is read from the pixels in each row of the pixel array  200  in response to the horizontal synchronizing signal Hss. In this example, signal charge is read from the pixels in each of the row &lt; 0 &gt;, the row &lt; 1 &gt;, and the row &lt; 2 &gt; sequentially on a row-by-row basis from Time t 6 . Hereinafter, the period from when pixels in a row are selected to when the pixels in the row are again selected may be referred to as “1V period”. In this example, the period from Time t 0  to Time t 6  corresponds to the 1V period. The 1V period corresponds to one frame. In the exposure period of an 1V period next to the 1V period in which the first voltage V 1  is applied to the photoelectric conversion layer  15 , the voltage applied to the photoelectric conversion layer  15  is changed to a second voltage V 2  different from the first voltage V 1  or the third voltage V 3 . The second voltage V 2  is, for example, a voltage at which one of the photoelectric conversion thresholds of the sublayers of the photosensitive layer  15 A is reached. The second voltage V 2  is, for example, a voltage intermediate between the first voltage V 1  and the third voltage V 3 . In this embodiment, while the voltage applied to the photoelectric conversion layer  15  is the second voltage V 2 , signal charge carriers generated by the photoelectric conversion of only the light in the visible region are accumulated at the charge accumulation region as illustrated in  FIG.  5   . In  FIG.  4 ( d ) , the periods denoted by the blank rectangular portions labeled as “RGB” are the exposure periods during which signal charge carriers generated by the photoelectric conversion of only the light in the visible region are accumulated at the charge accumulation region. 
     The exposure period is terminated when the voltage applied to the photoelectric conversion layer  15  is changed to the third voltage V 3  (Time t 12 ). Subsequently, signal charge is read from the pixels in each row of the pixel array  200  in response to the horizontal synchronizing signal Hss. 
     In the above-described embodiment of the present disclosure, the voltage applied between the pixel electrode  11  and the counter electrode  12  is set to the first voltage V 1  or the second voltage V 2  during the exposure period and to the third voltage V 3  while the voltage applied to the photoelectric conversion layer  15  is changed from the first voltage V 1  to the second voltage V 2  or from the second voltage V 2  to the first voltage V 1 , that is, during the non-exposure period that includes at least the period in which signal charge is read from all the charge accumulation regions. This enables two images to be acquired from the photoelectric conversion layer  15  with different wavelength sensitivity characteristics in a “global shutter” mode. 
     In addition, repeating an 1V period during which the first voltage V 1  is applied between the pixel electrode  11  and the counter electrode  12  and an 1V period during which the second voltage V 2  is applied between the pixel electrode  11  and the counter electrode  12  in an alternating manner enables acquisition of two moving images from the photoelectric conversion layer  15  with different wavelength sensitivity characteristics to be achieved substantially simultaneously with one imaging apparatus  100 . Since the two moving images are acquired electrically in a global shutter mode, the distortion of a fast-moving subject can be reduced in any of the moving images. 
     The period during which the first voltage V 1  is applied between the pixel electrode  11  and the counter electrode  12  and the period during which the second voltage V 2  is applied between the pixel electrode  11  and the counter electrode  12  are not necessarily repeated alternately, and the switchover between the two voltages may be performed at any frequency. The frequency at which the switchover between the two voltages is performed may be determined in accordance with the number of frames. For example, the switchover between the two voltages may be performed once every several tens of frames. The switchover between the two voltages is not necessarily performed periodically and may be performed at a timing based on a trigger. In another case, in order to detect infrared light at desired timings, imaging information based on infrared light may be acquired, for example, only once a second in an imaging mode in which visible light and infrared light are used, while a color image is acquired, in normal times, in an imaging mode in which visible light is used. 
     In this embodiment, upon the first voltage V 1  being applied to the photoelectric conversion layer  15 , the photoelectric conversion layer  15  exhibits a wavelength sensitivity characteristic such that the photoelectric conversion layer  15  has a sensitivity equal to or higher than a first value in the visible region and a sensitivity equal to or higher than a second value in the infrared region. Upon the second voltage V 2  lower than the first voltage V 1  being applied to the photoelectric conversion layer  15 , the photoelectric conversion layer  15  exhibits a wavelength sensitivity characteristic such that the photoelectric conversion layer  15  has a sensitivity equal to or higher than a third value only in the visible region. This enables the switchover between an exposure period in which visible and infrared wavelengths are used and an exposure period in which only visible wavelengths are used. As is clear from  FIG.  4   , in this example, the initiation (Time t 3  and Time t 9 ) and the termination (Time t 6  and Time t 12 ) of the exposure period are each performed at the same timing over all the pixels included in the pixel array  200 . In other words, the action described above is a “global shutter” mode. 
     On the other hand, in the case where the voltage applied between the pixel electrode  11  and the counter electrode  12  is not set to the third voltage V 3  when it is changed between the first voltage V 1  and the second voltage V 2  as illustrated in  FIG.  6   , it is not possible to electrically create the non-exposure state. Consequently, the acquisition of images is done in a “rolling shutter” mode. Furthermore, as illustrated in the row &lt; 1 &gt; and the row &lt; 2 &gt;, the two types of signal charge carriers which are generated in the photoelectric conversion layer  15  with different wavelength sensitivity characteristics, that is, the signal charge carriers resulting from only visible light and the signal charge carriers resulting from light of visible and infrared wavelengths, are accumulated at the charge accumulation region in a mixed state. This makes it difficult to acquire a correct image. 
     In this embodiment, subsequent to the termination of the exposure period, the address transistors  26  in the row &lt; 0 &gt; are turned on in order to read signal charge from the pixels in the row &lt; 0 &gt;. This allows the pixel signals responsive to the amounts of charge carriers accumulated at the respective charge accumulation regions during the exposure period to be output through the vertical signal lines  47 . Subsequent to the readout of the pixel signals, the pixels may be reset by turning on the reset transistors  28  in order to read the reset voltage of the pixels as a reference signal of the pixels. Subsequent to the readout of the pixel signals, the address transistors  26  and the reset transistors  28  are turned off. Subsequent to the readout of the signal charge from the pixels in each row of the pixel array  200 , the difference between the pixel signals read at Time t 0  and the reference signals read at Time t 3  is determined in order to remove fixed noises contained in the signals. 
     In the above period, the third voltage V 3  is applied between the pixel electrode  11  and the counter electrode  12 , that is, a bias voltage is applied to the photoelectric conversion layer  15  such that the sensitivity of the photoelectric conversion layer  15  becomes substantially zero. Therefore, in the above period, the accumulation of signal charge carriers at the charge accumulation region is negligible even when the photoelectric conversion layer  15  is irradiated with light. This reduces the likelihood of noise being caused as a result of unintended charge carriers mixing in the photoelectric conversion layer  15 . 
     Alternatively, in order to further reduce the likelihood of the signal charge carriers being accumulated at the charge accumulation region during the non-exposure period, the exposure period may be terminated by applying a voltage having the same magnitude as the third voltage V 3  and a polarity opposite to the third voltage V 3  between the pixel electrode  11  and the counter electrode  12 . However, simply reversing the polarity of the voltage applied between the pixel electrode  11  and the counter electrode  12  may cause the signal charge carriers accumulated at the charge accumulation region to migrate into the counter electrode  12  through the photoelectric conversion layer  15 . The migration of the signal charge carriers is observed as black dots in the acquired image. That is, the migration of the signal charge carriers from the charge accumulation region to the counter electrode  12  through the photoelectric conversion layer  15  during the non-exposure period may result in a negative parasitic sensitivity. 
     In this embodiment, the exposure period is terminated by changing the voltage applied to the photoelectric conversion layer  15  to the third voltage V 3 , that is, a bias voltage at which the sensitivity of the photoelectric conversion layer  15  becomes substantially zero is applied to the photoelectric conversion layer  15  subsequent to the accumulation of the signal charge carriers at the charge accumulation region. While the third voltage V 3  is applied to the photoelectric conversion layer  15  as a bias voltage, the likelihood of the signal charge carriers accumulated at the charge accumulation region migrating to the counter electrode  12  through the photoelectric conversion layer  15  can be reduced. In other words, applying the third voltage V 3  to the photoelectric conversion layer  15  enables the signal charge carriers accumulated during the exposure period to be stored at the charge accumulation region. That is, applying the third voltage V 3  to the photoelectric conversion layer  15  may reduce the likelihood of the negative parasitic sensitivity being caused as a result of the signal charge carriers being lost from the charge accumulation region. 
     As described above, in this embodiment, the initiation and termination of the exposure period and the imaging wavelength during the exposure period are controlled by changing the voltage Vb applied between the pixel electrode  11  and the counter electrode  12 . That is, according to this embodiment, it is possible to perform imaging by simultaneously changing the imaging wavelength of each of the unit pixels  10 . Applications of Imaging Apparatus According to the Present Disclosure 
     The imaging apparatus according to the embodiment of the present disclosure may be used as a camera for medical use, a camera for robots, a security camera, an on-vehicle camera, or the like. 
     For example, labels put on the surfaces of products transported by a high-speed conveyor belt in a factory or the like contain the following information recorded thereon: 
     1) Information or design formed using a visible ink or the like, and 
     2) Code formed using an IR ink that is invisible to the human eye but reflects or emits infrared radiation. 
     In such a case, the labels are imaged with the imaging apparatus according to the embodiment of the present disclosure while the imaging mode is changed as needed. The information or design formed using a visible ink or the like can be recognized as an image in the visible region when imaged with the imaging apparatus according to the embodiment of the present disclosure. This enables the inspection of the appearance of the products including the labels containing the image. Since the code formed using an IR ink that reflects infrared radiation can be recognized as an image in the infrared region when imaged with the imaging apparatus according to the embodiment of the present disclosure, monitoring the acquired images enables, for example, the identification of the code that is invisible to the naked eye and embedded in the label and the readout of the information. This makes it possible to acquire the distribution identification information of products, such as lot numbers, without impairing the design of the product. 
     In the case where personal authentication is performed using an imaging apparatus, an image is taken with the imaging apparatus according to the embodiment of the present disclosure in an RGB mode in which the photoelectric conversion layer  15  has a sensitivity only in the visible region. The color information of the human face, such as skin tone, hair color, and eye color, is acquired from the resulting image in the visible region. Furthermore, near-infrared light is impinged to the subject, and imaging is performed with the imaging apparatus according to the embodiment of the present disclosure in an RGB+IR mode in which the photoelectric conversion layer  15  has a sensitivity in the visible region and the infrared region. The pattern of the human iris or the pattern of the finger venous can be acquired from the resulting image. The facial color information and the pattern of the human iris or finger venous are, for example, merged and recorded or stored as personal information, which is used for personal authentication. When the imaging apparatus according to the embodiment of the present disclosure is used, the above processes can be achieved by using only one imaging apparatus. This may increase the accuracy of personal authentication by using a plurality of biological informations in combination.