Patent Publication Number: US-2015077174-A1

Title: Half-ratio charge pump circuit

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention generally relates to a charge pump circuit, and more particularly to a half-ratio charge pump circuit that generates an output voltage at approximately half the input voltage. 
     2. Description of Related Art 
     A charge pump circuit is one of power converters that convert a source of direct current (DC) from one voltage level to another voltage level. The charge pump circuit commonly uses capacitors as energy storage elements to generate either a higher or lower voltage power. The charge pump circuit may commonly be adopted at I/O level, for example, of a source driver for driving a liquid crystal display (LCD). 
     Multiple capacitors, typically known as flying capacitors, are required in the charge pump circuit for generating positive and negative output voltages, respectively. It is known that the capacitor with significant capacitance will occupy a substantial circuit area, which is unfavorable for an integrated circuit design. 
     High-voltage devices such as high-voltage transistors are also required in the charge pump circuit for obtaining a voltage level comparable with the I/O level, for example, of the source driver. In addition to their stringent design requirements, the high-voltage devices take up more layout area than low-voltage devices. 
     Low-dropout (LDO) regulator or circuit is commonly used to construct a power converter to generate an output voltage at half the input voltage adaptable to the source driver. One disadvantage of the LDO circuit, however, is its low power efficiency. 
     For the foregoing reasons, a need has arisen to propose a novel charge pump circuit for generating specific output voltages with simpler circuit architecture and less layout area. 
     SUMMARY OF THE INVENTION 
     In view of the foregoing, it is an object of the embodiment of the present invention to provide a half-ratio charge pump circuit with high power efficiency and small layout area, in which a single flying capacitor is used to generate a positive output voltage at approximately half the positive input voltage, and generate a negative output voltage at approximately half the negative input voltage. 
     According to one embodiment, a half-ratio charge pump circuit includes a flying capacitor, eight switches, a first reservoir capacitor and a second reservoir capacitor. The flying capacitor is electrically coupled between a first node and a second node. The eight switches including first to eighth switches are controlled to carry out first to fourth operating phases during which charges are stored on and transferred from the flying capacitor. The first reservoir capacitor is electrically coupled to the first node via the third switch, and the second reservoir capacitor is electrically coupled to the second node via the fourth switch. A positive input voltage is electrically coupled to the first node via the first switch, a negative input voltage is electrically coupled to the second node via the second switch, the first node is electrically coupled to ground via the fifth switch, the second node is electrically coupled to ground via the sixth switch, the first node provides a positive output voltage via the seventh switch, and the second node provides a negative output voltage via the eighth switch, thereby generating the positive output voltage at approximately half the positive input voltage, and generating the negative output voltage at approximately half the negative input voltage. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  shows a circuit diagram illustrating a half-ratio charge pump circuit according to one embodiment of the present invention; and 
         FIG. 2  to  FIG. 5  show the charge pump circuits of  FIG. 1  with switches closed or opened complying with operating phases 1-4 of the embodiment, respectively. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
       FIG. 1  shows a circuit diagram illustrating a half-ratio charge pump circuit  100  according to one embodiment of the present invention. The charge pump circuit  100  receives a positive input voltage VSP and a negative input voltage VSN. The charge pump circuit  100  accordingly generates a positive output voltage VCI at approximately half the positive input voltage VSP, and generates a negative output voltage VCL at approximately half the negative input voltage VSN. The charge pump circuit  100  is called “half-ratio” charge pump on the basis that a ratio of the output voltage VCI/CL and the input voltage VSP/VSN is approximately a half. 
     The charge pump circuit  100  of the embodiment includes a flying capacitor C F  electrically coupled between a first node A and a second node B. It is noted that the embodiment uses only one flying capacitor C F , instead of two flying capacitors as in conventional counterparts. In the embodiment, eight switches SW 1 -SW 8  are utilized and then controlled (for example, by a controller) to carry out four operating phases 1 to 4 during which charges may be stored and then transferred. It is appreciated that a person skilled in the pertinent art would implement each of the switches SW 1 -SW 8  by using conventional electronic devices such as metal-oxide-semiconductor (MOS) transistors. Otherwise stated, the term “switch” in the specification may be referred generally to a switching electronic device, rather than strictly to a mechanical switching element. It is appreciated that complementary MOS (CMOS) manufacturing technology may be well adapted to the circuit architecture illustrated in the embodiment. 
     It is further noted that the embodiment may use only low-voltage (LV) devices such as LV MOS transistors, compared with conventional counterparts requiring some high-voltage (HV) devices. As a result, the embodiment demands less layout area to achieve high power efficiency than the conventional counterparts. In the specification, the term “high voltage (or HV)” or “low voltage (or LV)” is a relative notion, depending on the technology and application. For example, low voltage may be defined as any voltage lower than a nominal (low) voltage, e.g., 5V, 3.3V or even lower, and high voltage may thus be any voltage higher than the nominal voltage. High-voltage devices may commonly be adopted at I/O level of an electronic system, for example, a source driver for driving a liquid crystal display (LCD). 
     Referring to  FIG. 1 , specifically speaking, the positive input voltage VSP may be electrically coupled to the first node A via a first switch SW 1 , and the negative input voltage VSN may be electrically coupled to the second node B via a second switch SW 2 . A first reservoir capacitor C r1  may be electrically coupled to the first node A via a third switch SW 3 , and a second reservoir capacitor C r2  may be electrically coupled to the second node B via a fourth switch SW 4 . The first/second reservoir capacitor C r1 /C r2  may typically be directed to smoothing pulse signals. In the embodiment, the capacitances of the first/second reservoir capacitor C r 1 /C r2  and the flying capacitor C F  are substantially the same. The first node A may be electrically coupled to ground via a fifth switch SW 5 , and the second node B may be electrically coupled to ground via a sixth switch SW 6 . The first node A may provide the positive output voltage VCI via a seventh switch SW 7 , and the second node B may provide the negative output voltage VCL via an eighth switch SW 8 . 
       FIG. 2  shows the charge pump circuit  100  of  FIG. 1  with switches closed or opened complying with a first operating phase of the embodiment. Specifically, in the operating phase 1, the first switch SW 1  and the fourth switch SW 4  are closed, and other switches (that is, SW 2 -SW 3  and SW 5 -SW 8 ) are opened. Accordingly, the positive input voltage VSP charges the flying capacitor C F  (via the closed first switch SW 1 ) and charges the second reservoir capacitor C r2  (via the closed fourth switch SW 4 ). As a result, charges corresponding to the positive input voltage 
     VSP may be stored on the flying capacitor C F  and the second reservoir capacitor C r2 . Therefore, the flying capacitor C F  may be charged to a voltage (at the first node A with respect to the second node B) at approximately half the positive input voltage VSP. 
     Subsequently, in the operating phase 2, as shown in  FIG. 3 , the sixth switch SW 6  and the seventh switch SW 7  are closed, and other switches (that is, SW 1 -SW 5  and SW 8 ) are opened. Accordingly, the charges stored on the flying capacitor C F  in the previous operating phase (i.e., the first operating phase) may be transferred (via the closed seventh switch SW 7 ) from the first node A. As a result, a voltage at approximately half the positive input voltage VSP may be provided as the positive output voltage VCI. 
     In the following operating phases (i.e., the third and the fourth operating phases), the negative output voltage VCL may be obtained in a manner similar to the operations performed in the first and the second operating phases to obtain the positive output voltage VCI.  FIG. 4  shows the charge pump circuit  100  of  FIG. 1  with switches closed or opened complying with the third operating phase of the embodiment. Specifically, in the operating phase 3, the second switch SW 2  and the third switch SW 3  are closed, and other switches (that is, SW 1  and SW 4 -SW 8 ) are opened. Accordingly, the negative input voltage VSN charges the flying capacitor C F  (via the closed second switch SW 2 ) and charges the first reservoir capacitor C r1  (via the closed third switch SW 3 ). As a result, charges corresponding to the negative input voltage VSN may be stored on the flying capacitor C F  and the first reservoir capacitor C r1 . Therefore, the flying capacitor C F  may be charged to a voltage (at the second node B with respect to the first node A) at approximately half the negative input voltage VSN. 
     Subsequently, in the operating phase 4, as shown in  FIG. 5 , the fifth switch SW 5  and the eighth switch SW 8  are closed, and other switches (that is, SW 1 -SW 4  and SW 6 -SW 7 ) are opened. Accordingly, the charges stored on the flying capacitor C F  in the previous operating phase (i.e., the third operating phase) may be transferred (via the closed eighth switch SW 8 ) from the second node B. As a result, a voltage at approximately half the negative input voltage VSN may be provided as the negative output voltage VCL. 
     According to the embodiment described above, the charge pump circuit  100  as illustrated above uses only one flying capacitor C F , which is used as the flying capacitor of a positive charge pump in the operating phases 1-2, and is used as the flying capacitor of a negative charge pump in the operating phases 3-4. In other words, the charge pump circuit  100  of the embodiment may be used as the positive charge pump and the negative charge pump in turn, and the single flying capacitor C F  is shared for the operating phases 1-2 and the operating phases 3-4. 
     Moreover, the charge pump circuit  100  of the embodiment consumes less current compared with, for example, the conventional power converter implemented using the LDO. Therefore, the charge pump circuit  100  of the embodiment possesses higher power efficiency than the conventional counterpart. 
     Although specific embodiments have been illustrated and described, it will be appreciated by those skilled in the art that various modifications may be made without departing from the scope of the present invention, which is intended to be limited solely by the appended claims.