Patent Publication Number: US-5021785-A

Title: Floating point digital to analog converter with bias to establish range midpoint

Description:
This is a continuation of copending application Ser. No. 07/115,581 filed on Oct. 23, 1987  which is a continuation of Ser. No. 06/781,767 filed Sept. 30, 1985, both now abandoned. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     This invention relates to a digital-to-analog converter suitable for use in, for example, a digital audio device. 
     In a signal reproduction circuit of a digital audio device such as a compact disc player, a digital signal reproduced from a recording medium is converted into an analog signal. In such a case, since the digital reproduction signal generally takes the form of a binary fixed-point number, a digital-to-analog converter (hereinafter referred to as &#34;D/A converter&#34;) of the type in which all bits of the digital reproduction signal are directly supplied to a weighted register network or an R-2R resistor ladder network is generally used. 
     As is well known, one of the most important features of a digital audio device is the reproducibility of a small signal with less distortion. It is also well known that distortion contained in the output signal of a D/A converter of this type increases with the decrease of magnitude of the input data. And therefore, for example, when it is desired to reproduce a signal at a level of -60 dB (full-scale level is 0 dB) with a distortion less than 1%, the D/A converter must have such a high accuracy that a signal at a level of 0 dB can be reproduced with a distortion less than 0.001%, which accuracy is equivalent to fifteen to sixteen bits. However, it is extremely difficult to improve the accuracy of a D/A converter of this type to such an extent. 
     SUMMARY OF THE INVENTION 
     It is therefore an object of the present invention to provide a D/A converter which can convert a digital signal into an analog signal with less distortion even when the magnitude of the digital input signal is small. 
     It is another object of the present invention to provide such a D/A converter which can deal with a digital input data in the form of a fixed-point number. 
     According to one aspect of the present invention, there is provided a digital-to-analog converter of the floating-point type which converts digital data in the floating-point representation composed of a mantissa part and an exponent part into an analog output signal comprising an R-2R resistor ladder network for converting the mantissa part into a first analog signal, each 2R resistor of the R-2R resistor ladder network being supplied with a corresponding bit of the mantissa part, the first analog signal being derived from one terminal end of the R-2R ladder network; an r-2r resistor ladder network directly connected at one terminal end thereof to the one terminal end of the R-2R resistor ladder network for producing second analog signals whose voltages are 2 -n  (n=0, 1, 2, 3, . . . ) magnifications of the first analog signal; and switch circuit means connected to the r-2r resistor ladder network for selectively outputting one of the second analog signals as the analog output signal in accordance with the exponent part of the digital data. 
     According to another aspect of the present invention, there is provided a digital-to-analog converter for converting fixed-point binary data into an analog output signal comprising data converting means for converting the fixed-point binary data into floating point digital data composed of a mantissa part and an exponent part; digital-to-analog converting means for converting the mantissa part into a first analog signal; circuit means responsive to the first analog signal to produce second analog signals whose voltages are 2 -n  (n=0, 1, 2, 3, . . . ) magnifications of the first analog signal; and switch circuit means connected to the circuit means for selectively outputting one of the second analog signals as the analog output signal in accordance with the exponent part of the floating point data. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a circuit diagram of a D/A converter 100 provided in accordance with the present invention; 
     FIG. 2 is a circuit diagram of an equivalent circuit of each of the inverters 11 and 12 of the D/A converter 100 of FIG. 1; 
     FIG. 3 is a circuit diagram of a modified D/A converter 200 provided in accordance with the present invention; 
     FIG. 4 is a circuit diagram of the shift number detection circuit 107 of the D/A converter 200 of FIG. 3; and 
     FIG. 5 is a circuit diagram of the data shift circuit 106 of the D/A converter 200 of FIG. 3. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS OF THE INVENTION 
     The embodiments of the invention will now be described with reference to the accompanying drawings in which like reference characters denote corresponding parts in several views. 
     Referring now to FIG. 1, there is shown a D/A converter 100 provided in accordance with the present invention. This D/A converter 100 is of a floating-point type which can implement a digital-to-analog conversion of a small signal with less distortion as will become apparent from the following description. Shown at TD 9  to TD 0  in FIG. 1 are input terminals for being supplied respectively with bits D 9  to D 0  of a ten-bit mantissa part (or fractional part) of a floating-point digital input data to be converted into an analog signal, the bit D 9  being the MSB (most significant bit) of the mantissa part. Each bit of the input data is supplied to a ten-stage R-2R resistor ladder network 10 through serially connected two inverters 11 and 12. Each stage of the ladder network 10 comprises a 2R resistor composed of serially connected two resistors each having a resistance value of R, which are disposed transversely of the ladder, and an R resistor composed of a resistor having a resistance value of R which is disposed longitudinally of the ladder. In this case, the bits D.sub. 9 to D 0  of the input data are fed respectively to the 2R resistors of the first (MSB) to tenth stages of the ladder network 10. Each of the inverters 11 and 12 is equivalent to an analog switch circuit shown in FIG. 2 which is so arranged that a voltage of V DD  is outputted when a &#34;1&#34;  signal is inputted and that a ground level signal is outputted when a &#34;0&#34; signal is inputted. The inverters 11 and 12 may alternatively output a voltage of V SS , which is lower than the voltage V DD , when a &#34;0&#34; signal is applied thereto. One terminal end 13 of the R-2R resistor ladder network 10 on the LSB (least significant bit) side is connected to a source of the reference voltage of V DD  through serially connected two resistors 14 and 15 each having a resistance value of R. The terminal end 13 is also connected to the ground through serially connected resistors 16 and 17 each having a resistance value of R. The resistor 17 may alternatively be connected to a source of the voltage V SS . And in this case, the inverters 11 and 12, the R-2R resistor ladder network 10 and the resistors 14 to 17 constitute a D/A conversion section 101 for the mantissa part. 
     Shown at 102 is a D/A conversion section for converting a three-bit exponent part of the digital input data. This D/A conversion section 102 analogically shifts the output voltage appearing at the other terminal end 18 of the ladder network 10 on the MSB side by an amount of voltage determined by the magnitude of the exponent part. The D/A conversion section 102 comprises a six-stage r-r/2 resistor ladder network 20 and seven analog switches SW 0  to SW 6  each comprising a field effect transistor (hereinafter referred to as &#34;FET&#34;). Each stage of the ladder network 20 except for the LSB stage comprises a (1/2)r resistor composed of parallel-connected two resistors each having a resistance value of r and disposed longitudinally of the ladder and an r resistor composed of a resistor having a resistance value of r and disposed transversely of the ladder. The LSB stage of the ladder network 20 is composed of two (1/2)r, resistors. The analog switch SW 0  is connected between one terminal end 21 of the ladder network 20 on the MSB side (or a 2 0  output terminal of the ladder network 20) and an output terminal 22 of this D/A converter 100, and the analog switch SW 1  is connected between the junction point of the (1/2)r and r resistors of the MSB stage of the ladder network 20 (or a 2 -1  output terminal of the ladder network 20) and the output terminal 22. In a similar manner, the analog switches SW 2  to SW 6  are connected respectively between 2 -2  to 2 -6  output terminals of the ladder network 20 and the output terminal 22. The analog switches SW 0  to SW 6  are so arranged that one of them is selectively conducted in accordance with an output of a binary-to-decimal decoder 103. The one terminal end 21 of the r-r/2 resistor ladder network 20 is connected to the terminal end 18 of the ladder network 10. The r resistors of the first (MSB) to fifth stages of the ladder network 20 and the transversely disposed (1/2)r resistor of the LSB stage of the ladder network 20 are connected to a bias terminal 23 to which a bias voltage of V M  equal in potential to half of the voltage V DD  is supplied. This bias voltage V M  defines the center of range of an output voltage V OUT  of this D/A converter 100 which is derived from the output terminal 22. The voltage V M  applied to the bias terminal 23 may alternatively be (V DD  +V SS )/2. The decoder 103 decodes bits S 2  (MSB) to S 0  (LSB) of the exponent part of the input data and outputs as the result of the decoding a signal P N  (&#34;N&#34; is one of &#34;0&#34; to &#34;6&#34;) to the D/A conversion section 102 to cause the Nth analog switch SW N  to conduct. In this case, the &#34;N&#34; is expressed as follows: 
     
         N=S.sub.2 ·2.sup.2 +S.sub.1 ·2.sup.1 +S.sub.0(1) 
    
     Also, the output voltage V OUT  of the above-described D/A converter 100 is expressed by the following formula (2): 
     
         V.sub.OUT =1/2V.sub.DD +1/4V.sub.DD (-1+D.sub.9 +D.sub.8 ·2.sup.-1 + . . . D.sub.0 ·2.sup.-9 +2.sup.-10)·2.sup.-N(2) 
    
     As is appreciated from the formula (2), with the structure of the above-described floating-point type D/A converter 100, a dynamic range of ten bits can be obtained by the mantissa part and a dynamic range of six bits can be obtained by the exponent part. And therefore, this D/A converter 100 as a whole has a resolution of sixteen bits. Moreover, when the &#34;N&#34; is &#34;6&#34;, that is, when the exponent part is minimum, an error contained in the output voltage V OUT  is rendered 2 -6  times smaller, so that zero-cross distortion at a small signal level is very small. Thus, with this D/A converter 100, D/A conversion can be achieved with less distortion even when the input data is small. In addition, this D/A converter 100 is advantageous in that the center of range of the output voltage V OUT  can be set to any desired value by applying a proper bias voltage to the bias terminal 23. 
     Although the floating-point type D/A converter 100 has various advantages as described above, the input data to be applied thereto must be in the form of a floating-point number. And therefore, in the case where the data to be converted into an analog signal is ordinary binary data or data in a fixed-point form, the input data must be converted into data in a floating-point form. This is, however, troublesome. 
     A D/A converter 200 modified so that ordinary fixed-point binary data can be directly applied will now be described. 
     In FIG. 3, a digital input data of sixteen binary weighted bits M 15  to M 0  in two&#39;s complement form is supplied to input terminals IN 15  to IN 0  of the D/A converter 200. The MSB M 15  (sign bit) of the digital input data supplied to the input terminal IN 15  is inverted by an inverter 105 and fed to an input terminal TD 9  of a mantissa-part D/A conversion section 101 through serially connected two inverters 11 and 12. The remaining bits M 14  to M 0  supplied to the input terminals IN 14  to IN 0  are fed to input terminals I 14  to I 0  of a data shift circuit 106, respectively. Also, the bits M 15  to M 9  of the input data are supplied to input terminals I 15  to I 9  of a shift number detection circuit 107. This shift number detection circuit 107 selectively outputs one of seven signals P 0  to P 6  to the data shift circuit 106 and an exponent-part D/A conversion section 102 in accordance with the bits M 15  to M 9  of the input data. 
     As shown in FIG. 4, the shift number detection circuit 107 comprises six exclusive-OR gates 109 to 114 to which the bits M 9  to M 14  are supplied, respectively, at one input terminals thereof. The other input terminals of the exclusive-OR gates 109 to 114 are supplied with the bit M 15  of the input data. This shift number detection circuit 107 further comprises seven AND gates AN 0  to AN 6 . Input terminals of each of the AND gates AN 0  to AN 6  are indicated by circles on an input signal line of the corresponding one of the AND gates. Output terminals of the exclusive-OR gates 114 to 109 are connected to the first input terminals of the AND gates AN 0  to AN 5 , respectively. The output terminals of the exclusive-OR gates 109 to 114 are also connected to input terminals of inverters 116 to 121, respectively. An output terminal of the inverter 116 is connected to the first input terminal of the AND gate AN 6 , and an output terminal of the inverter 117 is connected to the second input terminals of the AND gates AN 5  and AN 6 . An output terminal of the inverter 118 is connected to the second input terminal of the AND gate AN 4  and the third input terminals of the AND gates AN 5  and AN 6 . In a similar manner, an output terminal of the inverter 119 is connected to the input terminals of the AND gates AN 3  to AN 6 , an output terminal of the inverter 120 to the input terminals of AND gates AN 2  to AN 6 , and an output terminal of the inverter 121 to the input terminals of the AND gates AN 1  to AN 6 . When opened, the AND gates AN 0  to AN 6  output the signal P 0  to P 6 , respectively. With this shift number detection circuit 107, when the bit M 15  is &#34;0&#34;, that is to say, when the input data of this D/A converter 200 is a positive value, the &#34;N&#34; of the outputted signal P N  is determined by the number of &#34;0&#34; bits of the input data counted from the bit M 14  toward the bit M 9  until a &#34;1&#34; bit is first detected. In other words, the &#34;N&#34; is determined by the number of leading &#34;0&#34; bits of the input data. For example, when the bit M 15  is &#34;0&#34; and if only the bits M 13  and M 11  are &#34;1&#34;, the number of leading &#34;0&#34; bits of the input data is &#34;1&#34;, so that the signal P 1  is outputted. On the other hand, when the bit M 15  is &#34;1&#34;, that is to say, when the input data of this D/A converter 100 is negative, the &#34;N&#34; of the signal P N  is determined by the number of &#34;1&#34; bits of the input data counted from the bit M 14  toward the bit M 9  until a &#34;0&#34; bit is first detected In other words, the &#34;N&#34; is determined by the number of leading &#34;1&#34; bits of the input data. For example, in the case where only the bits M 10  and M 9  are &#34;0&#34;, the number of leading &#34;1&#34; bits of the input data is &#34;4&#34;, so that the signal P 4  is outputted. Thus, the shift number detection circuit 107 determines the &#34;N&#34; of the signal P N  based on the number of those bits of the input data which are counted from the bit M 14  toward the bit M 9  until a bit different in state from the bit M 15  is first detected. In the case where a bit which is different in state from the bit M 15  is not detected from the bits M 14  to M 9 , the shift number detection circuit 107 outputs the signal P 6  irrespective of the state of the bit M 15 . Thus, the shift number detection circuit 107 selectively outputs the signal P N  (&#34;N&#34; is one of &#34;0&#34; to &#34;6&#34;) in accordance with the absolute value of the input data represented by the bits M 14  to M 0 , wherein the &#34;N&#34; becomes greater when the absolute value of the input data becomes smaller. 
     The data shift circuit 106 shown in FIG. 3 selects, based on the signal P N  supplied from the shift number detection circuit 107, consecutive nine bits among the bits M 14  to M 0  and supplies the selected consecutive nine bits respectively to input terminals TD 8  to TD 0  of the mantissa-part D/A conversion section 101. This data shift circuit 106 comprises seven columns of switches S 11  to S 19 , S 21  to S 29 , . . . S 71  to S 79 , as shown in FIG. 5. These switches may be constituted by FETs, transistors or the like. In this case, all of the switches of the same column are closed when the corresponding one of the signals P 0  to P 6  is applied thereto For example, the switches S 11  to S 19  of the first column are closed when the signal P 0  is supplied thereto. In this case, the bits M 14  to M 6  of the input data are supplied respectively to the input terminals TD 8  to TD 0  of the mantissa-part D/A conversion section 101. In a similar manner, when the signal P 1  is supplied to the data shift circuit 106, the switches S 21  to S 29  are closed, so that the bits M 13  to M 5  of the input data are supplied respectively to the input terminals TD 8  to TD 0  of the mantissa-part D/A conversion section 101 And, when the signal P 6  is supplied to the data shift circuit 106, the switches S 71  to S 79  are closed, so that the bits M 8  to M 0  of the input data are supplied respectively to the input terminals TD 8  to TD 0  of the mantissa-part D/A conversion section 101. 
     In this embodiment, all of the above-described circuits are formed in a single chip of semiconductor. 
     The operation of this D/A converter 200 will now be described. 
     When a digital input data of sixteen bits M 15  to M 0  is supplied to the input terminals IN 15  to IN 0 , the shift number detection circuit 107 determines, in accordance with the bits M 15  to M 9  of the input data, the number of bit &#34;N&#34; (&#34;N&#34; is one of &#34;0&#34; to &#34;6&#34;) the data shift circuit 106 should shift the input data, and outputs the signal P N . The data shift circuit 106 shifts in response to the signal P N  the bits M 14  to M 0  of the input data in the direction of the higher significant bits by &#34;N&#34; bits, and outputs the result of the shift to the input terminals TD 8  to TD 0  of the mantissa-part D/A conversion section 101. The mantissa-part D/A conversion section 101 converts the magnitude of the data supplied to the input terminals TD 8  to TD 0  into an analog voltage having a polarity determined by the bit M 15  supplied to the input terminal TD 9  and outputs this voltage to the exponent-part D/A conversion section 102. The exponent-part D/A conversion section 102 then analogically shifts the voltage supplied from the mantissa-part D/A conversion section 101 by an amount determined by the signal P N  and outputs the resultant voltage to the output terminal 22 as an output voltage V OUT  which is expressed as follows: ##EQU1## In the above formula (3), the &#34;N&#34; is determined, as described above, based on the number of leading bits of the input data which are different in state from the bit M 15 . 
     With this D/A converter 200, in the case where the absolute value of the input data represented by the bits M 14  to M 0  thereof is large, only higher significant bits of the input data are supplied to the mantissa-part D/A conversion section 101 and the remaining lower significant bits thereof are neglected. In this case, however, the value represented by the neglected bits is sufficiently smaller than that represented by all of the bits M 14  to M 0 , and therefore, the neglect of the lower significant bits has little effect on the output voltage V OUT  of this D/A converter 200. On the other hand, in the case where the absolute value of the input data is small, lower significant bits of the input data are supplied to the mantissa-part D/A conversion section 101, and therefore, this D/A converter 200 can converts a small signal accurately. For example, in the case where the &#34;N&#34; is &#34;6&#34;, the bits M 8  to M 0  of the input data are supplied to the mantissa-part D/A conversion section 101, and in addition the error which may occur in the conversion of these bits is rendered 2 -6  times smaller, as will be appreciated from the formula (3), and therefore the zero-cross distortion of the output signal V OUT  is minimized. 
     As described above, with the structure of this D/A converter 200, an error in D/A conversion at a small signal level is minimized, and the input digital data to be converted into an analog form may be applied thereto in the form of an ordinary fixed-point binary data, i.e., data composed only of binary weighted bits. Furthermore, this D/A converter 200 can easily be formed on a single chip of semiconductor to eliminate noise interference from the exterior circuits and to reduce its manufacturing cost. The D/A converter thus formed in a single chip of semiconductor is easy to use since digital data in the form of an ordinary binary data can be directly applied to the digital data input terminals thereof. 
     Though the described embodiments are examples in which a ten bit mantissa section and a six bit exponent section cooperatively convert sixteen bit digital data, the present invention is not limited thereto and each of the mantissa section and the exponent section may handle digital data of other bit structure to convert the sixteen bit digital data or to convert digital data other than sixteen bits.