Patent Publication Number: US-2023139971-A1

Title: Semiconductor memory device and method of controlling the same

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This application is a continuation of and claims the benefit of priority under 35 U.S.C. § 120 to U.S. Ser. No. 17/317,280, filed May 11, 2021, which is a continuation of U.S. Ser. No. 16/357,696, filed Mar. 19, 2019, (now U.S. Pat. No. 11,038,536 issued Jun. 15, 2021), which is a continuation of U.S. Ser. No. 15/421,746, filed Feb. 1, 2017, which is continuation of U.S. Ser. No. 14/920,510, filed Oct. 22, 2015, which is a continuation of U.S. Ser. No. 14/601,664 filed Jan. 21, 2015 (now U.S. Pat. No. 9,384,090 issued Jul. 5, 2016), which is a continuation of U.S. Ser. No. 14/231,140, filed Mar. 31, 2014 (now U.S. Pat. No. 8,959,411 issued Feb. 17, 2015), which is a continuation of U.S. Ser. No. 13/757,935, filed Feb. 4, 2013, (now U.S. Pat. No. 8,732,544, issued May 20, 2014), which is a divisional of U.S. Ser. No. 13/465,624, filed May 7, 2012 (now U.S. Pat. No. 8,386,881 issued Feb. 26, 2013), which is a continuation of U.S. Ser. No. 13/090,539, filed Apr. 20, 2011 (now U.S. Pat. No. 8,196,008 issued Jun. 5, 2012), which is a continuation of U.S. Ser. No. 12/404,861, filed Mar. 16, 2009 (now U.S. Pat. No. 8,117,517 issued Feb. 14, 2012), which is a continuation of PCT Application No. PCT/JP08/063344, filed Jul. 17, 2008, which was published under PCT Article 21(2) in Japanese, and also claims the benefit of priority from Japanese Patent Application No. 2007-225996 filed Aug. 31, 2007, the entire contents of each of which are incorporated herein by reference. 
    
    
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a semiconductor memory device and a method of controlling the same and, for example, to a memory device which nonvolatilely stores information and has an error correction circuit, and a method of controlling the memory device. 
     2. Description of the Related Art 
     In some kinds of nonvolatile memory devices, the state of the physical quantity that controls data storage changes along with the elapse of time. If the elapsed time has reached a predetermined length, the data may be lost. There are various types of memory devices having such a characteristic feature. One of such memory devices is, e.g., a nonvolatile semiconductor memory device which uses transistors having a so-called laminated gate structure as memory cells. 
     The laminated gate structure includes a tunnel insulating film, floating gate electrode, inter-electrode insulating film, and control gate electrode which are sequentially stacked on a substrate. To store information in a memory cell, electrons are injected from the substrate to the floating gate electrode through the tunnel insulating film. The electric charges accumulated in the floating gate electrode retain information. The electric charges accumulated in the floating gate electrode leak to the substrate through the tunnel insulating film as the time elapses. For this reason, the information retained in the memory cell can be lost along with the elapse of time (an error can occur in the information). 
     If the elapsed time from the information storage time is short, an error can rarely occur in the information. On the other hand, if a long time has elapsed after information storage, an error may occur in the information at a high probability. A memory device having a plurality of such memory cells sometimes includes an error correction mechanism for restoring erroneous information to a correct state. 
     Generally, to correct a number of errors which are contained in data formed from a plurality of bits due to, e.g., the elapse of time from information recording, a correction mechanism having a high error correction capability is necessary. A correction mechanism with a high error correction capability has a large circuit scale and requires high power consumption and a long time for processing. Normally, to guarantee to restore correct information even after the elapse of a long time from information storage, a memory device uses a correction mechanism having a high error correction capability. The high-performance error correction mechanism is applied equally regardless of the length of the elapsed time from information storage. 
     For this reason, even in reading information which has been stored for only a short time, the high-performance error correction mechanism is used. Since the information to be read contains not so many errors, the use of the high-performance error correction mechanism is wasteful. This leads to a waste of power in the memory device. 
     To increase the error correction capability, generally, the size of the error correction target information needs to be large. For example, an error-correcting code is generated not for 512-byte data but for, e.g., 4-kbyte data obtained by concatenating a plurality of 512-byte data. This increases the error correction capability. In this method, however, it is necessary to always read out 4-kbyte data even in reading out 512-byte data. This also results in a waste of power in the memory device. 
     Prior-art reference information related to this application is
     JP-A 63-275225 (KOKAI)   

     In the reference, a correction apparatus which has a high error correction capability is disclosed. 
     BRIEF SUMMARY OF THE INVENTION 
     According to an aspect of the present invention, there is provided a semiconductor memory device comprising: a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively; a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code; a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks; and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code. 
     According to an aspect of the present invention, there is provided a semiconductor memory device comprising: A method of controlling a semiconductor memory device, the method comprising: generating a plurality of detecting codes to detect errors in a plurality of data items, respectively; generating a plurality of first correcting codes to correct errors in a plurality of first data block, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code; generating a second correcting code to correct errors in a second data block, the second data block containing the first data blocks; and nonvolatilely storing the second data block, the first correcting codes, and the second correcting code. 
    
    
     
       BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING 
         FIG.  1    is a block diagram schematically illustrating a semiconductor memory device according to an embodiment; 
         FIG.  2    is a block diagram illustrating the main portion of an error correction circuit associated with data write; 
         FIG.  3    is a view illustrating a data state in a temporary storage circuit  3  in write; 
         FIG.  4    is a view illustrating a state following  FIG.  3   ; 
         FIG.  5    is a view illustrating a state following  FIG.  4   ; 
         FIG.  6    is a block diagram illustrating the main portion of the error correction circuit associated with data read; 
         FIG.  7    is a view illustrating an example of the operation of a second error correction unit; 
         FIG.  8    is a graph illustrating the relationship between the necessary correction capability and the elapsed time from write; 
         FIG.  9    is a view illustrating the concept of the process range of a first error correction unit  11  and that of the second error correction unit  13 ; 
         FIG.  10    is a graph illustrating the relationship between the error rate and the use probability of the second error correction unit; and 
         FIG.  11    is a graph illustrating the relationship between the error rate and averaged Chien search of the second error correction unit. 
     
    
    
     DETAILED DESCRIPTION OF THE INVENTION 
     An embodiment of the present invention will now be described with reference to the accompanying drawing. In the following description, the same reference numerals denote constituent elements having almost the same functions and arrangements, and a repetitive explanation will be made only when necessary. 
     The embodiments to be described below are mere examples of an apparatus or method to embody the technical scope of the present invention. The technical scope of the present invention does not limit the materials, shapes, structures, and arrangements of the components to those described below. The technical scope of the present invention allows various changes and modifications in the appended claims. 
     The functional blocks of the embodiments of the present invention can be implemented by hardware, computer software, or a combination thereof. The blocks will be described below generally from the viewpoint of their functions while clarifying that they can be implemented by both of hardware and software. Whether to execute a function as hardware or software depends on the specific embodiments or design restrictions on the entire system. Those skilled in the art can implement the function by various methods for each of the specific embodiments, and the present invention incorporates such implementation. 
       FIG.  1    is a block diagram schematically illustrating a semiconductor memory device according to an embodiment. 
     As shown in  FIG.  1   , a semiconductor memory device  10  includes an error correction circuit  1  and a semiconductor memory  2 . The error correction circuit  1  and the semiconductor memory  2  are formed as, e.g., one semiconductor integrated circuit on a single semiconductor chip. The semiconductor memory  2  can be any memory device if it can nonvolatilely store information, and the stored data can be changed. An example of the semiconductor memory  2  is a NAND flash memory. 
     A NAND flash memory has a plurality of memory cells. Each memory cell is formed from a MOSFET (metal oxide semiconductor field effect transistor) having a so-called laminated gate structure. A MOS transistor with the laminated gate structure includes a tunnel insulating film, floating gate electrode, inter-electrode insulating film, control gate electrode, and source and drain diffusion layers. The threshold voltage of each memory cell transistor is changed in accordance with the amount of electric charge accumulated in the floating gate electrode, and each memory cell transistor stores information corresponding to the change in the threshold voltage. The memory cell transistor can be designed to store either 1-bit information or information of a plurality of bits. A control circuit including a sense amplifier and a potential generation circuit in the semiconductor memory  2  can write data supplied to the semiconductor memory  2  in the memory cell transistors, or output data stored in the memory cell transistor outside the semiconductor memory  2 . 
     The control gate electrodes of memory cell transistors belonging to the same row are connected to a single word line. A select gate transistor is provided at each of the ends of memory cell transistors which belong to the same column and are connected in series. One select gate transistor is connected to a bit line. Based on this rule, the memory cell transistors, select gate transistors, word lines, and bit lines are provided. Data write and read are done for each set of a plurality of memory cell transistors. A storage area formed from a set of memory cell transistors corresponds to one page. A plurality of pages form a block. The NAND flash memory erases data in each block. 
     Data (write data) required to be written in the semiconductor memory  2  is externally supplied to the semiconductor memory device  10 . The error correction circuit  1  adds an error-correcting code and an error-detecting code to the write data and supplies it to the semiconductor memory  2 . The semiconductor memory  2  stores the write data with the error-correcting code and the error-detecting code. 
     In response to a control signal supplied to the semiconductor memory device  10 , the semiconductor memory  2  supplies data (read data) required to be read, and an error-correcting code and an error-detecting code added to the read data to the error correction circuit  1 . The error correction circuit  1  detects and corrects an error in the read data. If an error exists, the error correction circuit  1  corrects it, removes the error-correcting code and the error-detecting code, and outputs the read data to an external device. 
     [Arrangement of Write System Circuit] 
       FIG.  2    is a block diagram illustrating the main portion of the error correction circuit  1  associated with data write. The error correction circuit  1  generates an error-correcting code for each of a plurality of write data each having a predetermined size and also generates another error-correcting code for the set of plurality of write data. The number of write data is decided in accordance with the error correction capability desired to achieve and the error-correcting codes to be employed. An example in which the number of write data is 8 will be described below. 
     As shown in  FIG.  2   , the error correction circuit  1  receives write data items Da 1  to Da 8 . The first size can match, e.g., the size of write or read data of the semiconductor memory  2 . More specifically, when a NAND flash memory is used as the semiconductor memory  2 , the write data size corresponds to the size of one page, which is, e.g., 512 bytes. In the following example, the first size is 512 bytes, for descriptive convenience. 
     The error correction circuit  1  has a temporary storage circuit  3 . The temporary storage circuit  3  is formed from, e.g., a volatile storage circuit and can be, e.g., a DRAM (dynamic random access memory). The temporary storage circuit  3  serves as a temporary storage area in write when generating an error-detecting code and an error-correcting code for write data to the semiconductor memory  2 . In write, the temporary storage circuit  3  receives the write data items Da 1  to Da 8 . The temporary storage circuit  3  stores the write data items Da 1  to Da 8 . 
     The write data items Da 1  to Da 8  are supplied to error-detecting code generation units  41  to  48  (some are not illustrated), respectively. 
     The error-detecting code generation units  41  to  48  generate (data of) error-detecting codes Db 1  to Db 8  for the write data items Da 1  to Da 8 , respectively. The error-detecting codes Db 1  to Db 8  are used to detect errors in the write data items Da 1  to Da 8 . A code that allows the error-detecting code generation units to easily calculate codes and reduce the power consumption while achieving the above-described object is used as the error-detecting codes Db 1  to Db 8 . For example, CRC (Cyclic Redundancy Checksum) 32 or CRC16 is usable as the error-detecting code. The error-detecting codes Db 1  to Db 8  are supplied to the temporary storage circuit  3 . 
     The error-detecting codes Db 1  to Db 8  are also supplied to first error-correcting code generation units  61  to  68 , respectively. The first error-correcting code generation units  61  to  68  also receive the write data items Da 1  to Da 8 , respectively. 
     The first error-correcting code generation units  61  to  68  generate first error-correcting codes using the write data items Da 1  to Da 8  and the error-detecting codes Db 1  to Db 8 . The first error-correcting code generated by the first error-correcting code generation unit  61  is used to correct errors in the write data item Da 1  and the error-detecting code data Db 1 . Similarly, the first error-correcting codes generated by the first error-correcting code generation units  62  to  68  are used to correct errors in the write data items Da 2  to Da 8  and the error-detecting code data Db 2  to Db 8 . 
     As the first error-correcting code, for example, a code which has a relatively low error correction capability of about 1 bit, requires no high power and no long time for calculation, and needs only a small scale circuit for execution is usable. More specifically, for example, a Hamming code is usable as the first error-correcting code. 
     The first error-correcting code generation units  61  to  68  output (data of) first error-correcting codes Dc 1  to Dc 8 , respectively. The first error-correcting codes Dc 1  to Dc 8  are supplied to the temporary storage circuit  3 . 
     The error-detecting codes Db 1  to Db 8  are supplied to a second error-correcting code generation unit  8 . The second error-correcting code generation unit  8  also receives the write data items Da 1  to Da 8 . The second error-correcting code generation unit  8  generates a second error-correcting code using the write data items Da 1  to Da 8  and the error-detecting codes Db 1  to Db 8 . The second error-correcting code is used to correct errors in the write data items Da 1  to Da 8  and the error-detecting codes Db 1  to Db 8 . 
     As the second error-correcting code, for example, a code which enables error correction at a higher capability than the error correction using the first error-correcting code and can correct errors of multiple bits, although the calculation amount is large, is usable. More specifically, for example, a BHC code, Reed-Solomon (RS) code, or LDPC (Low Density Parity Check) code is usable as the second error-correcting code. The circuit scale, power consumption, and calculation time of the second error-correcting code generation unit  8  exceed those of the first error-correcting code generation units  61  to  68  because of the large calculation amount. However, the second error-correcting code generation unit  8  has a higher error correction capability than the first error-correcting code generation units  61  to  68 . 
     The second error-correcting code generation unit  8  supplies (data of) a second error-correcting code Dd to the temporary storage circuit  3 . The temporary storage circuit  3  supplies, to the semiconductor memory  2 , the write data items Da 1  to Da 8 , error-detecting codes Db 1  to Db 8 , first error-correcting codes Dc 1  to Dc 8 , and second error-correcting code Dd, which have structures to be described later. 
     [Operation in Data Write] 
     The operation of the error correction circuit  1  in data write will be described next with reference to  FIGS.  3  to  6   .  FIGS.  3  to  6    schematically show data states in the temporary storage circuit  3  in write sequentially. 
     First, as shown in  FIG.  3   , the eight write data items Da 1  to Da 8  to be written in the semiconductor memory  2  are supplied to the error correction circuit  1 . The write data items Da 1  to Da 8  are stored in the temporary storage circuit  3 . 
     Next, as shown in  FIG.  4   , the write data items Da 1  to Da 8  are supplied to the error-detecting code generation units  41  to  48 , respectively. The error-detecting code generation units  41  to  48  generate the error-detecting codes Db 1  to Db 8  for the write data items Da 1  to Da 8 , respectively. When CRC32 is used as the error-detecting codes, each of the error-detecting codes Db 1  to Db 8  has a size of 32 bits. 
     The write data item Da 1  and the error-detecting code Db 1  concatenated after the write data item Da 1  form first data block D 1  that is a unit of error correction. Similarly, the write data items Da 2  to Da 8  and the error-detecting codes Db 2  to Db 8  concatenated after them form first data blocks D 2  to D 8 . The first data blocks D 1  to D 8  are stored in the temporary storage circuit  3 . Those skilled in the art already know the detailed arrangement of the error-detecting code generation units  41  to  48 , and a description thereof will be omitted. In this embodiment, the error-detecting code generation units  41  to  48  perform the detecting code generation operations in parallel. The parallel operations of the error-detecting code generation units  41  to  48  shorten the processing time. 
     Next, as shown in  FIG.  5   , the first data blocks D 1  to D 8  are supplied to the first error-correcting code generation units  61  to  68 , respectively. The first error-correcting code generation unit  61  generates, using the first data block D 1 , the first error-correcting code Dc 1  for correcting errors in the first data block D 1 . The first error-correcting code Dc 1  is concatenated after the error-detecting code Db 1  and before the write data item Da 2  and stored in the temporary storage circuit  3 . 
     Similarly, the first error-correcting code generation units  62  to  68  respectively generate, using the first data blocks D 2  to D 8 , the first error-correcting codes Dc 2  to Dc 8  for correcting errors in the first data blocks D 2  to D 8 . The first error-correcting code Dc 2  is concatenated after the error-detecting code Db 2  and before the write data item Da 3  and stored in the temporary storage circuit  3 . Similarly, the first error-correcting codes Dc 3  to Dc 7  are respectively concatenated after the error-detecting codes Db 3  to Db 7  and before the write data items Da 4  to Da 8  and stored in the temporary storage circuit  3 . The first error-correcting code Dc 8  is concatenated after the error-detecting code Db 8  and stored in the temporary storage circuit  3 . 
     When the Hamming code is used as the first error-correcting code, each of the first data blocks D 1  to D 8  has a size corresponding to write data (4096 bits)+error-detecting code (32 bits). To correct a 1-bit error in the first data block D 1  to D 8 , each of the first error-correcting codes Dc 1  to Dc 8  has a size of, e.g., 13 bits. Those skilled in the art already know the detailed arrangement of the first error-correcting code generation units  61  to  68 , and a description thereof will be omitted. In this embodiment, the first error-correcting code generation units  61  to  68  perform the correcting code generation operations in parallel. The parallel operations of the first error-correcting code generation units  61  to  68  shorten the processing time. 
     The first data blocks D 1  to D 8  are concatenated in order to form a second data block. The second data block is supplied to the second error-correcting code generation unit  8 . The second data block is a unit of data to be used by the second error-correcting code generation unit to generate the second error-correcting code. The second error-correcting code generation unit  8  generates, using the second data block, the second error-correcting code Dd for correcting errors in the second data block. The second error-correcting code Dd is concatenated after the second data block and stored in the temporary storage circuit  3 . 
     When the RS code is used as the second error-correcting code, the second data block has a size corresponding to write data (4096 bits)×8+error-detecting code (32 bits)×8 and corrects a 12-bit error in the second data block. To correct an error having such a size in the second data block, the second error-correcting code Dd has a size of, e.g., 192 bits. Those skilled in the art already know the detailed arrangement of the second error-correcting code generation unit  8 , and a description thereof will be omitted. 
     The second error-correcting code Dd is concatenated after the second data block in the above-described processes, thereby obtaining a transfer data block (the structure in the temporary storage circuit  3  in  FIG.  5   ). The transfer data block is supplied to the semiconductor memory  2 . The semiconductor memory  2  stores each transfer data block. 
     [Arrangement of Read System Circuit] 
       FIG.  6    is a block diagram illustrating the main portion of the error correction circuit  1  associated with data read. 
     As shown in  FIG.  6   , the semiconductor memory  2  supplies a signal S 1  to a first error correction unit  11 . The signal S 1  is formed from a transfer data block (the structure in the temporary storage circuit  3  in  FIG.  5   ). 
     If the first data blocks D 1  to D 8  contain errors, the first error correction unit  11  corrects the errors in the first data blocks D 1  to D 8  using the first error-correcting codes Dc 1  to Dc 8  in the signal S 1 , respectively, within the bounds of the capability of the first error correction unit  11 . More specifically, the first error correction unit  11  corrects the errors in the first data block D 1  using the first error-correcting code Dc 1 . Similarly, the first error correction unit  11  corrects the errors in the first data blocks D 2  to D 8  using the error-correcting codes Dc 2  to Dc 8 , respectively, within the bounds of the capability of the first error correction unit  11 . 
     The first error correction unit  11  outputs a signal S 2  obtained by correcting the errors in the signal S 1  using the first error-correcting codes. If the number of error bits in the first data blocks D 1  to D 8  before error correction is equal to or less than the error correction capability of the first error correction unit  11 , the first data blocks D 1  to D 8  in the signal S 2  after error correction contain no errors. However, if the number of error bits in the first data blocks D 1  to D 8  before error correction exceeds the error correction capability of the first error correction unit  11 , the first data blocks D 1  to D 8  in the signal S 2  after error correction still contain errors. 
     The signal S 2  is supplied to an error detection unit  12  and a second error correction unit  13 . The error detection unit  12  detects errors in the write data items Da 1  to Da 8  using the error-detecting codes Db 1  to Db 8 . The error detection unit  12  directly supplies the signal S 2  to a selection unit  14 . The error detection unit  12  also supplies, to the selection unit  14 , a signal S 3  representing the presence/absence of error detection in all the first data blocks D 1  to D 8 . The error detection unit  12  supplies, to the second error correction unit  13 , a signal S 4  containing information representing error detection locations in the first data blocks D 1  to D 8  in addition to the presence/absence of error detection. 
     The second error correction unit  13  analyzes the signal S 4  and acquires information representing whether errors are detected upon error detection by the error detection unit  12 . If no errors are detected, error correction is not necessary any more. For example, the second error correction unit  13  stops the operation for the signal S 2  of the process target as power supply from a power supply circuit (not shown) or clock signal supply from a clock circuit (not shown) stops. 
     Upon analyzing the signal S 4  and acquiring information representing that errors are detected in the signal S 2 , the second error correction unit  13  corrects the errors in the first data blocks D 1  to D 8  using the second error-correcting code Dd. At this time, the second error correction unit  13  executes error correction for only the first data blocks D 1  to D 8  containing errors.  FIG.  7    shows an example of this state. 
       FIG.  7    shows an example in which errors are detected in the first data blocks D 2 , D 4 , and D 5 . The second error correction unit  13  executes syndrome calculation using the second error-correcting code Dd for all the first data blocks D 1  to D 8 . On the other hand, the second error correction unit  13  executes Chien search for only the first data blocks D 2 , D 4 , and D 5  containing the detected errors. The second error correction unit  13  corrects the errors in the first data blocks D 2 , D 4 , and D 5  using the second error-correcting code Dd. The second error correction unit  13  outputs a signal S 5  obtained by correcting the errors in the signal S 2  using the second error-correcting code. 
     Error correction by the second error correction unit  13  is sequentially executed for the errors detected in the first data blocks D 1  to D 8 , unlike the prior art. That is, no error correction circuit dedicated to each of the first data blocks D 1  to D 8  is provided. This reduces the circuit scale and power consumption of the second error correction unit  13 . 
     Depending on the number of first data blocks to be subjected to error correction, the necessary time may be longer than in parallel error correction by the dedicated circuits of the first data blocks D 1  to D 8 . In this embodiment, however, the second error correction unit  13  executes Chien search for only, of the first data blocks D 1  to D 8 , data blocks containing detected errors. In addition, the first error-correcting code is designed to be able to correct most (nearly 100%) of the errors in the first data blocks D 1  to D 8  by only correction using the first error-correcting code. For this reason, the second error-correcting code is rarely used. In this embodiment, it is therefore possible to reduce the circuit scale and power consumption of the second error correction unit  13  without any increase in the processing time by sharing the error correction circuit for the first data blocks D 1  to D 8 . 
     Assume that in a process of repeatedly reading certain a transfer data block from the memory device, the error detection unit  12  detects no error in the transfer data block which is read for the first time. In this case, at least one of power supply and clock signal supply to the second error correction unit  13  is stopped in advance in reading the transfer data block for the second and subsequent times. This largely reduces the power consumption in the error correction circuit  1  in reading the same transfer data block. 
     How to decide the correction capability of the first error correction unit  11  and that of the error detection unit  12  will be described next. Note that the correction capability of the first error correction unit  11  also includes the process of causing the first error-correcting code generation units  61  to  68  to generate the first error-correcting codes Dc 1  to Dc 8 . Similarly, the correction capability of the second error correction unit  13  also includes the process of causing the second error-correcting code generation unit  8  to generate the second error-correcting code Dd. 
       FIG.  8    is a graph illustrating the relationship between the necessary correction capability and the elapsed time from data write in the semiconductor memory  2 . As shown in  FIG.  8   , as the elapsed time becomes long, the number of errors in the data written in the semiconductor memory  2  increases. The error correction capability is changed in accordance with the increase in the number of errors. The error correction capability of the first error correction unit  11  and that of the second error correction unit  13  are decided so that an excessive or insufficient error correction capability are used. More specifically, the error correction capability of the first error correction unit  11  and that of the second error correction unit  13  are decided such that error correction can be done solely by the first error correction unit  11  when the elapsed time is short, while the first error correction unit  11  and the second error correction unit  13  can execute error correction when the elapsed time exceeds a predetermined time (the time when the number of errors abruptly increases). 
       FIG.  9    shows the concept of the process range of the first error correction unit  11  and that of the second error correction unit  13  according to this embodiment. The abscissa in  FIG.  9    represents the number of errors within a predetermined range (a page of a NAND flash memory) of the semiconductor memory  2 . The ordinate represents the error occurrence probability. The broken line indicates the relationship before degradation of the semiconductor memory  2  (immediately after write). The solid line indicates the relationship after degradation of the semiconductor memory  2  (after the guaranteed data retention time has elapsed). 
     As shown in  FIG.  9   , the error correction capability of the first error correction unit  11  is decided such that only the first error correction unit  11  can correct all errors when the number of errors within the predetermined range is small. More specifically, the number of correctable bits, error correction method, and the number of bits of an error-correcting code are decided. For example, the error correction capability of the first error correction unit  11  is decided such that it can correct almost 100% of errors before degradation and about 99% of errors after degradation. On the other hand, the error correction capability of the second error correction unit  13  is decided to correct the remaining 1% of errors after degradation. 
     As a result, the use probability of the second error correction unit  13  rises along with the increase in the error rate, as shown in  FIG.  10   . 
     As described above, the first error correction unit  11 , which has a lower error correction capability but requires a shorter processing time and lower power consumption, corrects almost all errors. The second error correction unit  13 , which requires a longer processing time and higher power consumption but has a higher error correction capability, corrects the remaining errors. The error correction circuit  1  can therefore achieve a short processing time, low power consumption, and small circuit scale while maintaining a high error correction capability. 
       FIG.  11    shows the relationship between the error rate and the averaged Chien search range of the second error correction unit  13 . In this embodiment (solid line), the error correction capability of the first error correction unit  11  is set such that most errors can be corrected by only the first error correction unit  11 , as described above. For this reason, even when the error rate is high, the second error correction unit  13  is rarely involved in error correction, as compared to the prior art (broken line). 
     As described above, according to the semiconductor memory device of the embodiment, the plurality of first data blocks D 1  to D 8  each containing a corresponding one of a plurality of write data items are formed. The plurality of first error-correcting codes Dc 1  to Dc 8  are generated for the plurality of first data blocks D 1  to D 8 , respectively. Additionally, the second error-correcting code Dd is generated for a second data block formed from the plurality of first data blocks D 1  to D 8 . When the number of error bits is small, correction is done using the first error-correcting codes Dc 1  to Dc 8  which have a low capability but require low power consumption and a small circuit scale. When the number of error bits is large, correction is done using both the first error-correcting codes Dc 1  to Dc 8  and the second error-correcting code Dd which requires high power consumption and a large circuit scale but allows correction with a high capability. Hence, there is provided a semiconductor memory device whose error correction circuit  1  has an appropriate circuit scale and power consumption and shortens the error correction time without sacrificing the error correction capability. 
     In this embodiment, error correction using the second error-correcting code Dd is executed for, of the first data blocks D 1  to D 8 , only data containing errors even after error correction using the first error-correcting codes Dc 1  to Dc 8 . This can greatly reduce the circuit scale of the second error correction unit  13  as compared to an example in which circuits for executing error correction using the second error-correcting code Dd are provided in correspondence with the plurality of first data blocks D 1  to D 8 . 
     Additional advantages and modifications will readily occur to those skilled in the art. Therefore, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents.