Patent Publication Number: US-10311845-B2

Title: Filter characteristics changing device

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
     This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2017-050164, filed Mar. 15, 2017, the entire contents of which are incorporated herein by reference. 
     BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The present invention relates to a filter characteristics changing device, a filter characteristics changing method, a program, and an electronic instrument for solving unnaturalness occurring at the time of changing filter characteristics. 
     2. Description of the Related Art 
     Effect providing devices have been known which provide various effects (sound effects) such as reverb, delay, and echo to musical sound data generated from a sound source of an electronic instrument or the like. For example, Japanese Utility Model Publication No. 01-012320 discloses an effect providing device which separately forms an initial reflection sound acquired by delaying and changing input musical sound data and a reverberation sound generated based on musical sound data divided into a plurality of frequency bands and acquired by synthesizing reverberation signals having different delay change modes for each band, and thereby acquires a reverberation effect close to a natural sound. Also, in recent years, an effect providing device using a DSP (Digital Signal Processor) which performs waveform arithmetic processing at high speeds has been known, and an example of this type of device is disclosed in Japanese Patent No. 3620264. 
     This effect providing device structured by using a DSP which performs waveform arithmetic processing at high speeds can provide various effects (sound effects) by rewriting a microprogram to be executed and control data. For example, as for reverb known as a reverberation effect, a plurality of reverb types with different reverberation characteristics can be supported. The reverb types herein are types of sound fields of different reverberation characteristics. 
     SUMMARY OF THE INVENTION 
     In accordance with one aspect of the present invention, there is provided a filter characteristics changing device comprising: a set filter which includes a plurality of partial filters and forms a specified characteristic by combining the plurality of partial filters; and a processor which performs, as crossfading processing for a first filter and a second filter among the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of the first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of the second filter to the characteristic, when an instruction is provided for changing the characteristic formed by the set filter. 
     In accordance with another aspect of the present invention, there is provided a filter characteristics changing method, wherein a device performs, when an instruction is provided for changing a characteristic of a set filter which includes a plurality of partial filters and forms a specified characteristic by combining the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of a first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of a second filter to the characteristic, as crossfading processing for the first filter and the second filter among the plurality of partial filters. 
     In accordance with another aspect of the present invention, there is provided a non-transitory computer-readable storage medium having stored thereon a program that is executable by a computer to perform functions comprising; performing, when an instruction is provided for changing a characteristic of a set filter which includes a plurality of partial filters and forms a specified characteristic by combining the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of a first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of a second filter to the characteristic, as crossfading processing for the first filter and the second filter among the plurality of partial filters. 
     The above and further objects and novel features of the present invention will more fully appear from the following detailed description when the same is read in conjunction with the accompanying drawings. It is to be expressly understood, however, that the drawings are for the purpose of illustration only and are not intended as a definition of the limits of the invention. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1A  is an external view of an electronic keyboard instrument  100  according to an embodiment of the present invention and  FIG. 1B  is a block diagram showing the electric structure of the electronic keyboard instrument  100 ; 
         FIG. 2A  is a memory map showing the data structure of a ROM (Read Only Memory)  11  and  FIG. 2B  is a memory map showing the data structure of a RAM  13  (Random Access Memory) for a CPU (Central Processing Unit); 
         FIG. 3  is a block diagram showing the configuration of a reverberator actualized by a microprogram executed by a DSP  16 ; 
         FIG. 4A  is a block diagram showing the structure of a high-pass filter HPF section  162  and  FIG. 4B  is a block diagram showing the structure of a low-pass filter LPF section  166 ; 
         FIG. 5  is a block diagram showing the structure of an all-pass filter (APF) section  163 ; 
         FIG. 6  is a block diagram showing the structure of a comb filter (CF) section (L)  164 ; 
         FIG. 7A  is a flowchart of the operation of the main routine to be performed by a CPU  10  and  FIG. 7B  is a flowchart of the operation of reverb switching processing to be executed by the CPU  10 ; 
         FIG. 8A  is a flowchart of the operation of all-pass filter switching processing to be executed by the CPU  10  and  FIG. 8B  is a diagram showing an example of the operation of all-pass filter assign processing; 
         FIG. 9  is a flowchart of the operation of all-pass filter delay time change processing to be executed by the CPU  10 ; 
         FIG. 10A  is a flowchart of the operation of comb filter switching processing and  FIG. 10B  is a diagram showing an example of the operation of comb filter assign processing; 
         FIG. 11  is a flowchart of the operation of comb filter delay time change processing to be executed by the CPU  10 ; and 
         FIG. 12  is a flowchart of the operation of various amplification-related switching processing to be executed by the CPU  10 . 
     
    
    
     DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     An embodiment of the present invention will hereinafter be described with reference to the drawings. 
     A. External Appearance and Entire Structure 
     The external appearance and the entire structure of the embodiment are described with reference to  FIG. 1A  and  FIG. 1B .  FIG. 1A  is an external view of an electronic keyboard instrument  100  according to the embodiment of the present invention, and  FIG. 1B  is a block diagram showing the electric structure of the electronic keyboard instrument  100 . 
     In these drawings, a keyboard  1  is arranged in the longitudinal direction of an instrument housing having a rectangular parallelepiped appearance, and generates a signal in accordance with musical performance input (key depressing/releasing operation). The signal generated by the keyboard  1  is detected by a key scanner  7  for key scanning, and acquired by a CPU  10  via an I/O controller  9 . 
     In the CPU  10 , the signal generated by the keyboard  1  is acquired to generate musical performance input information. The musical performance input information includes a key-on/key-off signal representing a key depressing/releasing operation, a key number, a velocity, and the like. This musical performance input information is converted into musical performance data represented by a note-on/note-off event in MIDI format, and then supplied to a sound source section  15 . 
     On the operation panel surface of the instrument housing, a panel switch  2  is arranged. The panel switch  2  includes, for example, a power supply switch for power-on/power-off of a device power supply as well as various operation switches such as a reverb type switching switch for selecting a desired reverberation characteristic. The event of each operation switch generated by the panel switch  2  is detected by the key scanner  7 , and acquired by the CPU  10  via the I/O controller  9 . 
     Also, on the operation panel surface of the instrument housing, a display panel  3  is arranged. On the display panel  3  constituted by an LCD panel, a display control signal generated by the CPU  10  is supplied via the I/O controller  9  to an LCD controller  6 , whereby the screen display of, for example, the setting status or the operation status of each section of the musical instrument is performed. 
     On the left side of the operation panel of the instrument housing, a bender wheel (VH)  4  and a modulation wheel (MH)  5  are arranged. The bender wheel  4  generates a bender output in accordance with a wheel rotating operation by a user (performer). The modulation wheel  5  generates a modulation output in accordance with a wheel rotating operation by the user (performer). 
     The bender output and the modulation output are AD-converted by an AD converter (ADC)  8 , and then acquired by the CPU  10  via the I/O controller  9 . The bender output acquired by the CPU  10  is used as a pitch bend for smooth pitch control to a high-pitched sound side or low-pitched sound side centering on the pitch of a sound being emitted. On the other hand, the modulation output acquired by the CPU  10  is used as a value for specifying a depth of a modulation effect. 
     The I/O controller  3  controls inputs/outputs of each of the above-described devices (the LCD controller  6 , the key scanner  7 , and the ADC  8 ) for data exchange. A ROM  11  in  FIG. 1B  is constituted by, for example, a flash memory known as a non-volatile memory, and includes a program data area PDA, a waveform data area WDA, and a DSP data area DDA shown in  FIG. 2A . 
     In the program data area PDA of the ROM  11 , various control programs to be executed by the CPU  10  and control data therefor are stored. In the present embodiment, when a DSP  16  described below is to function as a reverberator for adding a reverberation effect, the CPU  10  sets a reverberation characteristic of the DSP  16  (reverberator) by following reverb parameters RP. Accordingly, the reverb parameters RP that are used as control data are stored in the program data area PDA. 
     The reverb parameters RP set reverberation characteristics (such as a delay time and reverberation time of a reverberation sound) of eight different sound fields such as “small room” and “medium room”. Specifically, as shown in  FIG. 2B , the reverb parameters RP of eight reverb types are provided, and one of them is selected by the reverb type switching switch. 
     The reverb parameter RP of each reverb type includes an APF section parameter, a CF section (L) parameter, a CF section (R) parameter, an LPF section (L) parameter, an LPF section (R) parameter, an HPF section parameter, and an output level. These parameters each include a coefficient (gain) and a delay time that are supplied to each section of a reverberator (described further below) actualized by a microprogram executed by the DSP  16 , which will be described in detail further below. 
     In initialization processing executed by the CPU  10  at the time of startup (this processing will be described further below), these various control programs and control data (including the reverb parameters RP) stored in the program data area PDA of the ROM  11  are transferred from the program data area PDA of the ROM  11  via a flash memory controller  12  to a RAM  13  for the CPU. 
     In the waveform data area WDA of the ROM  11 , the waveform data of various tones is stored. In the initialization processing executed by the CPU  10  at the time of startup (this processing will be described further below), this waveform data is read from the waveform data area WDA via the flash memory controller  12  and then transferred to a waveform memory  14 . 
     In the DSP data area WDA of the ROM  11 , various programs that can be executed by the DSP  16 , their corresponding parameter data, and the like are stored. Among these various microprograms, parameter data, and the like, an effect-related microprogram to be executed by the DSP  16  and parameter data are read via the flash memory controller  12  under the control of the CPU  10 . The microprogram read out from the DSP data area WDA is written in the DSP  16  under the control of the CPU  10 . 
     In the waveform memory  14 , the waveform data of various tones read out by the CPU  10  from the waveform data area WDA (refer to  FIG. 2A ) of the ROM  11  described above is stored. The sound source section  15  is configured using a known waveform memory reading method, and includes a plurality of sound-emission channels. This sound source section  15  generates musical sound data by using the waveform data of a tone specified by the CPU  10  among the waveform data of various tones stored in the waveform memory  14 . 
     That is, in response to a note-on event, the sound source section  15  assigns a sound-emission channel that is in an unassigned state, reads out from the waveform memory  14  the waveform data of a tone specified by the CPU  10  at a phase velocity corresponding to a sound-emission pitch (pitch specified by the key number of a depressed key) to form musical sound data, and stops (mutes) the formed musical sound data at the time of a note-off event. 
     The DSP  16  that is a processor dedicated for waveform arithmetic processing provides a predetermined effect (sound effect) to musical sound data generated by the sound source section  15 . This effect (sound effect) to be provided by the DSP  16  is defined by the microprogram and the control data read out from the RAM  17  for the DSP. In the present embodiment, the DSP  16  functions as a reverberator which provides a reverberation effect to musical sound data generated by the sound source section  15 . The configuration of the reverberator that is actualized by the DSP  16  will be described further below. 
     A DA converter (DAC)  18  in  FIG. 1B  DA-converts musical data provided with a predetermined effect by the DSP  16  into a musical sound signal in an analog signal format and outputs it to the next stage. An amplifier  19  in  FIG. 1B  removes unnecessary noise from the musical sound signal outputted from the DA converter  18  and then amplifies the signal at a predetermined level. A loudspeaker  20  in  FIG. 1B  emits the musical sound of the musical sound signal amplified by the amplifier  19  at the predetermined level. 
     B. Configuration of Reverberator 
       FIG. 3  is a block diagram showing the functional configuration of the reverberator actualized by the microprogram executed by the DSP  16 . The reverberator shown in the drawing outputs, based on a reverberation algorithm called the Schroeder type, a stereo output OUT(L) of a left channel component and a stereo output OUT(R) of a right channel component acquired by a reverberation sound being added to a musical sound signal INPUT (musical sound data) inputted from the sound source section  15 . 
     Next, the configuration of the reverberator is described with reference to  FIG. 3 . The musical sound signal INPUT (musical sound data) generated by the sound source section  15  is inputted to a multiplier  161  and is also inputted to the adders  170  and  171  on a subsequent stage. The multiplier  161  amplifies the musical sound signal INPUT at a predetermined level and supplies the resultant signal to a high-pass filter (HPF) section  162 . The high-pass filter (HPF) section  162  cuts off an unnecessary low-frequency component from the output from multiplier  161 . 
     The high-pass filter (HPF) section  162  is constituted by a multiplier  162   a , a subtractor  162   b , a delay element  162   c , and a multiplier  162 , as shown in  FIG. 4A . For example, in a case where the high-pass filter (HPF) section  162  is constituted by a primary recursive type, the multiplier  162   a  multiples an input signal by a gain (coefficient)  1 - b  for output. The subtractor  162   b  subtracts a one-sample delay output from the output from the multiplier  162   b  for output. The delay element  162   c  delays the output from the subtractor  162   b  by one sample for output. The multiplier  162   d  multiplies the output from the delay element  162   c  by a gain (coefficient) b to control the level of the one-sample delay output. Note that the gain (coefficient) b to be provided to the multiplier  162   d  is an HPF section parameter that is read out from the reverb parameters RP (refer to  FIG. 2B ) in various amplification-related switching processing performed by the CPU  10  in accordance with switching of a reverb type (refer to  FIG. 12 ), which will be described further below. 
     An all-pass filter (APF) section  163  in  FIG. 3  functions as a circuit element which simulates an initial dispersion process of a reverb sound. The configuration of this all-pass filter (APF) section  163  will be described further below. An output from the all-pass filter (APF) section  163  is converted by a comb filter (CF) section (L)  164  and a comb filter (CF) section (L)  165  into a stereo signal type of left and right channels. The all-pass filter (APF) section  163  functions as a circuit element which simulates random reflection of a reverb sound and a dispersion process thereof on these left and right channels. As the configurations of the comb filter (CF) section (L)  164  and the comb filter (CF) section (R)  165 , the configuration of the comb filter (CF) section (L)  164  will be taken as an example and described further below. 
     A low-pass filter (LPF) section (L)  166  and a low-pass filter (LPF) section (R)  167  in  FIG. 3  adjust the sound quality of each reverberation sound for a left channel output from the comb filter (CF) section (L)  164  and a right channel output from the comb filter (CF) section (R)  165 , respectively. 
     The low-pass filter (LPF) section (L)  166  is constituted by a multiplier  166   a , an adder  166   b , a delay element  166   c , and a multiplier  166   d , as shown in  FIG. 4B . For example, in a case where the low-pass filter (LPF) section (L)  166  is constituted by a primary recursive type, the multiplier  166   a  multiples an input signal by a gain (coefficient)  1 - a  for output. The adder  166   b  adds a one-sample delay output to the output from the multiplier  166   b  for output. The delay element  166   c  delays the output from the adder  166   b  by one sample for output. The multiplier  166   d  multiplies the output from the delay element  166   c  by a gain (coefficient) a to control the level of the one-sample delay output. 
     This gain (coefficient) a to be provided to the multiplier  166   d  is an LPF section parameter of the above-described reverb parameters RP (refer to  FIG. 2B ). The CPU  10  smoothly changes the value to a target value by interpolating the gain (coefficient) a. This interpolation is performed by the CPU  10  in the various amplification-related switching processing (refer to  FIG. 12 ) described further below. 
     A multiplier  168  in  FIG. 3  adjusts the level of a left channel reverberation sound whose sound quality has been adjusted by the low-pass filter (LPF) section (L)  166  so as to perform static control. Similarly, a multiplier  169  in  FIG. 3  adjusts the level of a right channel reverberation sound whose sound quality has been adjusted by the low-pass filter (LPF) section (R)  167  so as to perform static control. The multipliers  168  and  169  which adjust the levels of the left and right channels to perform static control are provided with an output level Otlvl. The output level Otlvl is a parameter to be read out from the above-described reverb parameters RP (refer to  FIG. 2B ) in the various amplification-related switching processing performed by the CPU  10  in accordance with switching of a reverb type (refer to  FIG. 12 ), which will be described further below. 
     An adder  170  in  FIG. 3  adds a statically-controlled reverberation sound on the left channel to an original sound (the musical sound signal INPUT generated by the sound source section  15 ) so as to generate a stereo output OUT(L) of a left channel component. An adder  171  in  FIG. 3  adds a statically-controlled reverberation sound on the right channel to an original sound (the musical sound signal INPUT generated by the sound source section  15 ) so as to generate a stereo output OUT(R) of a right channel component. 
     In the reverberator configured as described above, filters for signal amplification such as the high-pass filter (HPF) section  162 /low-pass filter (LPF) section (L)  166  and low-pass filter (LPF) section (R)  167  are referred to as amplification-related filters. Among these amplification-related filters, a filter which includes a circulating section and a delay section not for the purpose of signal delay and has a very-short fixed delay time (for example, one sample time) is referred to as a primary recursive filter. 
     Also, as the all-pass filter (APF) section  163 /comb filter (CF) section (L)  164  and comb filter (CF) section (R)  165 , filters for the purpose of signal delay and having a long, variable delay time are referred to as delay recursive filters. 
     C. Configuration, of All-Pass Filter (APF) Section  163   
     Next, the configuration of the all-pass filter (APF) section  163  functioning as a circuit element which simulates an initial dispersion process of a reverberation sound is described with reference to  FIG. 5 . The all-pass filter (APF) section  163  is constituted by five all-pass filter blocks (which will be described further below) connected in series, as shown in  FIG. 5 . Here, all the all-pass filter blocks have the same configuration and therefore this configuration is described focusing on the configuration of the all-pass filter block at the first stage among the five all-pass filter blocks connected in series. 
     The all-pass filter block at the first stage includes an all-pass filter APF 1  and a bypass crossfading section. The all-pass filter APF 1  is a known primary recursive filter which repeatedly outputs an input signal in a predetermined cycle (delay time T 1 ) while attenuating the input signal, and has an adder  40   a , an attenuator  41   a , a delay element  42   a , an adder  43   a , and a multiplier  44   a . The adder  40   a  adds a delay input to the input signal, and the attenuator  41   a  multiplies an output from the adder  40   a  by a gain (coefficient) −g 1  for attenuation output. The delay element  42   a  delays and outputs the output from the adder  40   a  (delay time T 1 ), and the adder  43   a  adds the attenuation output from the attenuator  41   a  to the delay output from the delay element  42   a . The multiplier  44   a  multiplies the delay output from the delay element  42   a  by a gain (coefficient) +g 1  for output. 
     Note that the crossfading described below is processing of gradually degreasing (fading-out) effects from any of a plurality of filters connected in series or parallel and gradually increasing (fading-in) effects from the other filters. To perform crossfading with the plurality of filters being connected in series, an effect of each individual filter is changed by bypass control. 
     The bypass crossfading section is a circuit for crossfading with the above-described plurality of filters being connected in series, and is constituted by a multiplier  30   a , a multiplier  31   a , a multiplier  32   a , and an adder  33   a . The multiplier  30   a  multiplies an input signal by a gain (coefficient) i 1  for supply to the adder  40   a  of the all-pass filter APF 1 . The multiplier  31   a  outputs a direct input (a signal not via the above-described all-pass filter AP) acquired by multiplying the input signal by a gain (coefficient) d 1 . The multiplier  32   a  multiplies an all-pass output outputted from the adder  43   a  of the all-pass filter APF 1  by a gain (coefficient) o 1 . The adder  33   a  adds a direct input outputted from the multiplier  31   a  and an all-pass output outputted from the multiplier  32   a  together for output to an all-pass filter block at the next stage. 
     In the bypass crossfading section configured as described above, when a bypass state is to be set in which no input signal is supplied to the all-pass filter APF 1 , the gain (coefficient) d 1  of the multiplier  31   a  which outputs a direct input is set at “1”, and the gain (coefficient) i 1  of the multiplier  30   a  and the gain (coefficient) o 1  of the multiplier  32   a  are set at “0”. Also, when a filter output of the all-pass filter APF 1  is to be set, the gain (coefficient) i 1  of the multiplier  30   a  is set at “1”, the gain (coefficient) d 1  of the multiplier  31   a  is set at “0”, and the gain (coefficient) of the multiplier  32   a  is set at “1”. 
     As described above, all of the all-pass filter blocks have the same configuration. That is, an all-pass filter APF 2  forming an all-pass filter block at the second stage is constituted by an adder  40   b , a subtractor  41   b , a delay element  42   b , an adder  43   b , and a multiplier  44   b . Also, a bypass crossfading section forming the all-pass filter block at the second stage is constituted by a multiplier  30   b , a multiplier  31   b , a multiplier  32   b , and an adder  33   b.    
     Furthermore, an all-pass filter block at the third stage includes an all-pass filter APF 3  constituted by components  40   c ,  41   c ,  42   c ,  43   c , and  44   c  and a bypass crossfading section constituted by components  30   c ,  31   c ,  32   c , and  33   c . An all-pass filter block at the fourth stage includes an all-pass filter APF 4  constituted by components  40   d ,  41   d    42   d ,  43   d , and  44   d  and a bypass crossfading section constituted by components  30   d ,  31   d ,  32   d , and  33   d . An all-pass filter block at the fifth stage includes an all-pass filter APF 5  constituted by components  40   e ,  41   e ,  42   e ,  43   e , and  44   e  and a bypass crossfading section constituted by components  30   e ,  31   e ,  32   e , and  33   e.    
     In the all-pass filter (APF) section  163 , among the five all-pass filter blocks connected in series, four all-pass filter blocks are normally set to function as circuit components which simulate a reverberation-sound dispersion process, and the remaining one all-pass filter block is set as a backup system. When a change in delay time is required at the time of reverb type switching, the CPU  10  performs all-pass filter switching processing (which will be described further below). 
     As will be described in detail further below, in the all-pass filter switching processing, a modulo arithmetic expression (which will be described further below) is used to assign an M-th all-pass filter APF[M] which is caused to make a transition from “filter output to a bypass state” for each of switching stages  1  to  4  and an N-th all-pass filter APF[N] which is caused to make a transition “from a bypass state to filter output” from among the five all-pass filters. 
     Then, based on the assigned all-pass filters APF[M] and APF[N], parameters (delay time T, coefficient g) of the all-pass filter APF[N] read out from the reverb parameters RP (refer to  FIG. 2B ) are set to the all-pass filter APF[N] for parameter update. After a lapse of a transient period corresponding to the delay time T, crossfading by envelope multiplication is performed to cause the all-pass filter APF[M] to make a transition to a bypass state and cause the all-pass filter APF[N] to make a transition to filter output. This switching processing is performed for each of the switching stages  1  to  4 . 
     D. Configuration of Comb Filter (CF) Section (L)  164   
     Next, the configuration of the comb filter (CF) section (L)  164  functioning as a circuit element which simulates random reflection of a reverb sound and a dispersion process thereof is described. The comb filter (CF) section (R)  165  has the same configuration as that of the comb filter (CF) section (L)  164 , and therefore is not described herein. 
     The comb filter (CF) section (L)  164  includes five comb filter blocks CF 1  to CF 5  connected in parallel and a mixer  54  which adds outputs from these comb filter blocks CF 1  to CF 5  together to generate a reverberation sound, as shown in  FIG. 6 . The comb filter block CF 1  at the first stage connected in parallel is constituted by a comb filter CF 1  and a multiplier  53   a.    
     The comb filter CF 1  is a known primary recursive filter which repeatedly outputs an input signal in a predetermined cycle (delay time) while attenuating the input signal, and includes an adder  50   a , a delay element  51   a , and a multiplier  52   a . The adder  50   a  adds a delay input to the input signal, and the delay element  51   a  delays an output from the adder  50   a  for output (delay time T 1 ). The multiplier  52   a  multiplies the output from the delay element  51   a  by a gain (coefficient) g 1  for output, and a multiplier  53   a  multiplies the output from the comb filter CF 1  by a gain (coefficient) c 1  for supply to the mixer  54  at the subsequent stage. This mixer  54  functions as a circuit for crossfading with a plurality of filters being connected in parallel. 
     Note that the comb filter block CF 2  at the second stage includes a comb filter CF 2  constituted by an adder  50   b , a delay element  51   b , and a multiplier  52   b , and a multiplier  53   b  which multiplies an output from this comb filter CF 2  by a gain (coefficient) c 2 . Similarly, the comb filter block CF 3  at the third stage includes a comb filter CF 3  (an adder  50   c , a delay element  51   c , and a multiplier  52   c ) and a multiplier  53   c  which multiplies an output from the comb filter CF 3  by a gain (coefficient) c 3 . 
     Also, the comb filter block CF 4  at the fourth stage includes a comb filter CF 4  (an adder  50   d , a delay element  51   d , and a multiplier  52   d ) and a multiplier  53   d  which multiplies an output from the comb filter CF 4  by a gain (coefficient) c 4 . Furthermore, the comb filter block CF 5  at the fifth stage includes a comb filter CF 5  (an adder  50   e , a delay element  51   e , and a multiplier  52   e ) and a multiplier  53   e  which multiplies an output from the comb filter CF 5  by a gain (coefficient) c 5 . 
     In the comb filter (CF) section (L)  164 , among the five comb filter blocks CF 1  to CF 5  connected in parallel, four comb filter blocks are normally set to function as circuit components which simulate reflection of a left channel reverberation sound and a dispersion process thereof, and the remaining one comb filter block is set as a backup system. The same configuration applies to the comb filter (CF) section (R)  165 . 
     When a change of the CF section (L)/CF section (R) parameters (refer to  FIG. 2B ) is required in accordance with reverb type switching, the CPU  10  performs comb filter switching processing (which will be described further below) to perform parameter update and switching of the comb filter blocks in both of the comb filter (CF) section (L)  164  and the comb filter (CF) section (R)  165 . 
     The comb-filter switching processing is briefly described herein although its details will be described further below. A modulo arithmetic expression (which will be described further below) is used to assign an O-th comb filter block CF[O] which is caused to make a transition from “filter output to a bypass state” and a P-th comb filter block CF[P] which is caused to make a transition “from a bypass state to filter-output” from among the five comb filters connected in parallel. 
     Then, based on the assigned comb filter blocks CF[O] and CF[P], parameters (delay time T, coefficient g) from the reverb parameters RF (refer to  FIG. 2B ) are set to the comb filter block CF[P] for parameter update. After a lapse of a transient period corresponding to the delay time T, crossfading by envelope multiplication is performed to cause the comb filter block CF[O] to make a transition to a bypass state, and cause the comb filter block CF[P] to make a transition to filter output. This switching processing is performed for each of the switching stages  1  to  4 . 
     As with the above-described all-pass filter (APF) section  163  and the comb filter (CF) section (L)  164 , a filter constituted by a plurality of filter blocks (the all-pass filter blocks APF 1  to APF 5 /the comb filter blocks CF 1  to CF 5 ) being combined so as to form a predetermined characteristic is referred to as a set filter. 
     Also, each of the plurality of filter blocks (all-pass filter blocks APF 1  to APF 5 /the comb filter blocks CF 1  to CF 5 ) constituting the set filter is referred to as a partial filter. 
     E. Operation 
     Next, the main routine, the reverb switching processing called from the main routine, the all-pass filter switching processing forming the reverb switching processing (the all-pass filter assign processing and the all-pass filter delay time change processing), the comb filter switching processing (the comb filter assign processing and the comb filter delay time change processing), and the various amplification-related switching processing to be performed by the CPU  10  of the above-structured electronic keyboard instrument  100  are described with reference to  FIG. 7  to  FIG. 12 . In the following descriptions of the operation, the subject of the operation is the CPU  10  unless otherwise specified. 
     1. Operation of Main Routine 
       FIG. 7A  is a flowchart showing the operation of the main routine to be performed by the CPU  10 . When the electronic keyboard instrument  100  is powered on, the CPU  10  performs the main routine, proceeds to Step SA 1  shown in  FIG. 7A , and performs initialization processing of initializing each section of the instrument. In this initialization processing, for example, the CPU  10  reads out various control programs and control data (including the reverb parameters RP) from the program data area PDA in the ROM  11  so as to transfer them to the RAM  13  for the CPU, transfers the waveform data of a predetermined tone read out from the waveform data area WDA of the ROM  11  to the waveform memory  14 , and writes a predetermined microprogram, parameter data, and the like read out from the DSP data area WDA of the ROM  11  in the RAM  17  for the DSP. 
     Next, the CPU  10  proceeds to Step SA 2 , and performs switching processing corresponding to a switch event of a type generated by a user operation on the panel switch  2 . For example, when the user operates the reverb type switching switch for selecting a reverberation characteristic, the CPU  10  performs switching processing of generating a reverb type change request and reading from the RAM  13  for the CPU the reverb parameter RP indicating the reverberation characteristic specified by that switch operation so as to display it on the display panel  3 . 
     Then, at Step SA 3 , when a key-depressing operation is detected based on a scanning result of the key scanner  7  which scans each key of the keyboard  1 , the CPU  10  performs key depression/release detection processing of generating a note-on event including a note number representing a pitch to be emitted, its velocity, and the like. On the other hand, when a key-releasing operation is detected, the CPU  10  generates a note-off event including a pitch to be muted. 
     Subsequently, at Step SA 4 , the CPU  10  performs wheel operation detection processing based on an output from the AD converter  8 . In this wheel operation detection processing, when a bender output in accordance with a rotating operation on the bender wheel  4  by the user (performer) is detected, the CPU  10  instructs the sound source section  15  to make a pitch bend based on the bender output. On the other hand, when a modulation output in accordance with a rotating operation on the modulation wheel  5  is detected, the CPU  10  gives an instruction regarding the depth of a modulation effect based on the modulation output to the DSP  16  adding the modulation effect. 
     Next, at Step SA 5 , when the DSP  16  is functioning as the above-described reverberator, and the user (performer) operates the reverb type switching switch to generate a reverb type change request, the CPU  10  starts performing the reverb switching processing. Details of the reverb switching processing will be described further below. Note that, when the DSP  16  is not functioning as a reverberator and no reverb type change request has been generated, the CPU  10  does not perform the reverb switching processing at Step SA 5 , and proceeds to the next Step SA 6 . 
     Next, the CPU  10  proceeds to Step SA 6 , and performs sound source processing of sending a note-on event generated at Step SA 3  described above to the sound source section  15  so as to instruct the sound source section  15  to emit a sound or sending a note-off event to instruct the sound source section  15  to mute the sound. The sound source section  15  generates musical sound data based on the note-on event supplied from the CPU  10  as described above, or stops the musical sound data based on the note-off event. 
     The reverb switching processing at Step SA 5  is, in practice, repeatedly preformed concurrently and asynchronously with the sound source processing at Step SA 6  (and each of Steps SA 2  to SA 4  and SA 7 ). Even when the emission of a musical sound specified by the sound source processing is continuing, reverb switching is effective. That is, when reverb switching is performed while the emission of one musical sound is continuing, the filter effect can be gradually switched without unnaturalness in audibility within a period in which the emission of this musical sound is continuing. 
     Then, at Step SA 7 , when the DSP  16  can perform a function of adding any of various effects except the above-described reverberator, the CPU  10  performs another effect processing of adding any of various effects such as reverb, delay, echo, chorus, or the like to the musical sound data generated by the sound source section  15 . The CPU  10  then returns to the above-described Step SA 2 , and repeats the processing at Steps SA 2  to SA 7  described above until the electronic keyboard instrument  100  is powered off. 
     2. Operation of Reverb Switching Processing 
     Next, the operation of the reverb switching processing to be performed by the CPU  10  is described with reference to  FIG. 7B . When the reverb switching processing indicated by Step SA 5  of the above-described main routine (refer to  FIG. 7A ) (which is, in practice, repeatedly performed concurrently and asynchronously) is started, the CPU  10  starts the processing shown in  FIG. 7B  to proceed to Step SB 1 . At Step SB 1 , the CPU  10  judges whether a reverb change request has been received, that is, whether the user (performer) has operated the reverb type switching switch. 
     At Step SA 2  of the above-described main routine, when the user (performer) has not operated the reverb type switching switch and no reverb type change request has been received, the judgment result at Step SB 1  is “NO”, and therefore the CPU  10  ends the reverb switching processing. 
     Conversely, at Step SA 2  of the above-described main routine, when the user (performer) has operated the reverb type switching switch for selecting a reverberation characteristic to generate a reverb type change request, the judgment result at Step SB 1  is “YES”, and therefore the CPU  10  performs the all-pass filter switching processing via the next Step SB 2 . 
     When a reverb type change request is generated, a delay time from that time point is measured by a timer. Based on this measured timer value, the CPU  10  sequentially judges the progress at each stage. At each stage, the processing at Steps SB 2 , SB 3 , and SB 4  are concurrently and simultaneously performed. 
     (1) Operation of All-Pass Filter Switching Processing 
     Next, the operation of the all-pass filter switching processing is described with reference to  FIG. 8A  and  FIG. 8B . When the all-pass filter switching processing is started via Step SB 2  shown in  FIG. 7B , the CPU  10  proceeds to Step SC 1  shown in  FIG. 8A , and performs the all-pass filter assign processing. 
     a. Operation of All-Pass Filter Assign Processing 
     As shown in  FIG. 5 , among the five all-pass filter blocks connected in series, the all-pass filter (APF) section  163  normally causes four all-pass filter blocks to function as circuit elements which simulate a reverberation sound dispersion process and causes the remaining one all-pass filter block to function as a backup system. 
     In the all-pass filter assign processing at Step SC 1  shown in  FIG. 8A , in accordance with the stage progress, the CPU  10  assigns an all-pass filter block which is caused to make a transition “from filter output to a bypass state” and an all-pass filter block which is caused to make a transition “from a bypass state to filter output” from among the five all-pass filter blocks connected in series. 
     Specifically, when the number of the all-pass filter which is caused to make a transition “from filter output to a bypass state” is “N” and the number of the all-pass filter which is caused to make a transition “from a bypass state to filter output” is “M”, a relation therebetween can be represented by the following modulo arithmetic operation (residue arithmetic operation).
 
 N =mod( M+ 4,5)  (1)
 
     To associate the numbers N and M with APF numbers (APF 1  to APF 5 ) of the all-pass filter blocks in the operation example shown in  FIG. 8B , each of them is incremented by 1. That is, as the stage progresses, “N” and “M” change in a circulating manner within a range of the number of filters. 
     Here, a case is exemplarily described in which, in an example shown in  FIG. 8B , reverb type switching is performed in a situation where the all-pass filter blocks APF 1  to APF 4  at the first stage to the fourth stage are caused to function and the all-pass filter block APF 5  at the fifth stage is in a bypass state (unassigned). 
     In this case, when the number M of the all-pass filter block which is caused to make a transition “from filter output to a bypass state” at the initial switching stage  1  is set at “0:(APF 1 )”, the number N of the all-pass filter block which is caused to make a transition “from a bypass state to filter output” is “4:(APF 5 )” based on the above equation (1). 
     Then, when the all-pass filter assign processing is performed corresponding to the operation example shown in  FIG. 8B , the CPU  10  acquires assignment results (M, N) corresponding to the switching stages  1  to  4  based on the above equation (1) as described below, and the results are temporarily stored in a work area WA of the RAM  13  for the CPU. 
     Switching stage  1 : APF 1  (M=0)→APF 5  (N=4) 
     Switching stage  2 : APF 2  (M=1)→APF 1  (N=0) 
     Switching stage  3 : APF 3  (M=2)→APF (N=1) 
     Switching stage  4 : APF 4  (M=3)→APF 3  (N=2) 
     b. All-Pass Filter Delay Time Change Processing 
     When the all-pass filter assign processing at Step SC 1  is completed as described above, the CPU  10  performs the all-pass filter delay time change processing via the next Step SC 2  (refer to  FIG. 8A ). When the all-pass filter delay time change processing is started, the CPU  10  performs processing at Step SD 1  and the following processing shown in  FIG. 9  for each of the switching stages  1  to  4 . 
     &lt;Operation of Switching Stage  1 &gt; 
     At Step SD 1 , the CPU  10  reads cut the parameters (delay time T 5 , coefficient g 5 ) of the all-pass filter block APF 5  (N=4) in a bypass state from the reverb parameters RP stored in the RAM  13  for the CPU. The CPU  10  then sets the delay time T 5  to the delay element  42   e  (refer to  FIG. 5 ) of the all-pass filter APF 5  and sets a gain (coefficient) −g 5  to the multiplier  41   e  and a gain (coefficient) +g 5  to the multiplier  44   e.    
     Here, since a gain (coefficient) i 5  of the multiplier  30   e  and a gain (coefficient) o 5  of the multiplier  32   e  of the all-pass filter block APF 5  (N=4) are “0”, the parameters (delay time T 5 , coefficient g 5 ) of the all-pass filter APF 5  can be updated without providing a delay change to the next stage. Then, when the update of the parameters (delay time T 5 , coefficient g 5 ) is ended, the CPU  10  sets “1” to the gain (coefficient) i 5  of the multiplier  30   e  of the all-pass filter block APF 5  (N=4). 
     Subsequently, at Step SD 2 , the CPU  10  waits until a transient period corresponding to the delay time T 5  set to the delay element  42   e  elapses. When the transient period elapses, the judgment result at Step SD 2  is “YES”, and therefore the CPU  10  proceeds to Step SD 3 . At Step SD 3 , by crossfading by envelope multiplication, the CPU  10  sets the gain (coefficient) d 1  of the multiplier  31   a  at “1”, sets the gain (coefficient) o 1  of the multiplier  30   a  at “0”, and sets the gain (coefficient) o 1  of the multiplier  32   a  at “0” in the all-pass filter block APF 1  (M=0). Also, the CPU  10  sets a gain (coefficient) d 5  of the multiplier  31   e  at “0” and sets the gain (coefficient) o 5  of the multiplier  32   e  at “1” in the all-pass filter block APF 5  (N=4). This causes the “all-pass filter block APF 1  (M=0)” to make a transition to a bypass state and causes the “all-pass filter block APF 5  (N=4)” to make a transition to filter output. 
     This crossfading is performed based on the time value for judging the stage progress, and gradually changes the setting value such that crossfading is completed within a time period in which the stage is switched (note that a time until one crossfading is completed can be set across a plurality of stages). 
     Then, the CPU  10  proceeds to Step SD 4 , and judges whether parameter rewrite has been ended, that is, whether the processing has been performed for all of the above-described switching stages  1  to  4 . If the processing has not been performed for all of the above-described switching stages  1  to  4 , the judgment result is “NO”, and therefore the CPU  10  returns to the above-described Step SD 1 . Thereafter, the CPU  10  repeats the above-described Steps SD 1  to SD 4  until the processing is performed for all of the switching stages  1  to  4 . 
     Note that, to proceed to the next switching stage, the number M of the all-pass filter block which is caused to make a transition “from filter output to a bypass state” is incremented by one step, and then stored in a memory. Also, in the all-pass filter block APF[M] caused to make a transition to a bypass state by crossfading, the CPU  10  sets a gain (coefficient) im of the multiplier  30  at “0”. 
     &lt;Operation of Switching Stage  2 &gt; 
     At the switching stage  2 , the CPU  10  reads out the parameters (delay time T 1 , coefficient g 1 ) of the all-pass filter block APF 1  (N=0) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 1  to the delay element  42   a  (refer to  FIG. 5 ), sets the gain (coefficient) −g 1  to the multiplier  41   a , and sets the gain (coefficient) +g 1  to the multiplier  44   a  in the all-pass filter APF 1 . 
     Here, since the gain (coefficient) i 1  of the multiplier  30   a  and the gain (coefficient) o 1  of the multiplier  32   a  of the all-pass filter block APF 1  (N=0) are “0”, the parameters (delay time T 1 , coefficient g 1 ) of the all-pass filter APF 1  can be updated without providing a delay change to the next stage. Then, when the update of the parameters is ended, the CPU  10  sets “1” to the gain (coefficient) i 1  of the multiplier  30   a  of the all-pass filter block APF 1  (N=0), and then waits until a transient period corresponding to the delay time T 1  elapses. 
     When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets a gain (coefficient) d 2  of the multiplier  31   b  at “1”, sets a gain (coefficient) i 2  of the multiplier  30   b  at “0”, and sets a gain (coefficient) o 2  of the multiplier  32   b  at “0” in the all-pass filter block APF 2  (M=0). Also, the CPU  10  sets the gain (coefficient) d 1  of the multiplier  31   a  at “0” and sets the gain (coefficient) o 1  of the multiplier  32   a  at “1” in the all-pass filter block APF 1  (N=0). This causes the “all-pass filter block APF 2  (M=1)” to make a transition to a bypass state and causes the “all-pass filter block APF 1  (N=0)” to make a transition to filter output. 
     &lt;Operation of Switching Stage  3 &gt; 
     At the switching stage  3 , the CPU  10  reads out the parameters (delay time T 2 , coefficient g 2 ) of the all-pass filter block APF 2  (N=1) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 2  to the delay element  42   b  (refer to  FIG. 5 ), sets a gain (coefficient) −g 2  to the multiplier  41   b , and sets a gain (coefficient) +g 2  to the multiplier  44   b  in the all-pass filter APF 2 . Here, since the gain (coefficient) i 2  of the multiplier  30   b  and the gain (coefficient) o 2  of the multiplier  32   b  of the all-pass filter block APF 2  (N=1) are “0”, the parameters can be updated without providing a delay change to the next stage. 
     When the update of the parameters is ended, the CPU  10  sets “1” to the gain (coefficient) i 2  of the multiplier  30   b  of the all-pass filter block APF 2  (N=1), and then waits until a transient period corresponding to the delay time T 2  elapses. When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets a gain (coefficient) d 3  of the multiplier  31   c  at “1”, sets a gain (coefficient) i 3  of the multiplier  30   c  at “0”, and sets a gain (coefficient) o 3  of the multiplier  32   c  at “0” in the all-pass filter block APF 3  (M=2). Also, the CPU  10  sets the gain (coefficient) d 2  of the multiplier  31   b  at “0” and sets the gain (coefficient) o 2  of the multiplier  32   b  at “1” in the all-pass filter block APF 2  (N=1). This causes the “all-pass filter block APF 3  (M=2)” to make a transition to a bypass state and causes the “all-pass filter block APF 2  (N=1)” to make a transition to filter output. 
     &lt;Operation of Switching Stage  4 &gt; 
     At the switching stage  4 , the CPU  10  reads out the parameters (delay time T 3 , coefficient g 3 ) of the all-pass filter block APF 3  (N=2) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 3  to the delay element  42   c  (refer to  FIG. 5 ), sets a gain (coefficient) −g 3  to the multiplier  41   c , and sets a gain (coefficient) +g 3  to the multiplier  44   c  in the all-pass filter APF 3 . Here, since the gain (coefficient) i 3  of the multiplier  30   c  and the gain (coefficient) o 3  of the multiplier  32   c  of the all-pass filter block APF 3  (N=2) are “0”, the parameters can be updated without providing a delay change to the next stage. 
     When the update of the parameters is ended, the CPU  10  sets “1” to the gain (coefficient) i 3  of the multiplier  30   c  of the all-pass filter block APF 3  (N=2), and then waits until a transient period corresponding to the delay time T 3  elapses. When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets a gain (coefficient) d 4  of the multiplier  31   d  at “1”, sets a gain (coefficient) i 4  of the multiplier  30   d  at “0”, and sets a gain (coefficient) o 4  of the multiplier  32   d  at “0” in the all-pass filter block APF 4  (M=3). Also, the CPU  10  sets the gain (coefficient) d 3  of the multiplier  31   c  at “0” and sets the gain (coefficient) o 3  of the multiplier  32   c  at “1” in the all-pass filter block APF 3  (N=2). This causes the “all-pass filter block APF 4  (M=3)” to make a transition to a bypass state and causes the “all-pass filter block APF 3  (N=2)” to make a transition to filter output. 
     When the processing at all the switching stages  1  to  4  is ended, the judgment result at Step SD 4  is “YES”. Therefore, after ending the processing, the CPU  10  proceeds to the next Step SB 3  to perform the comb filter switching processing. 
     (3) Operation of Comb Filter Switching Processing 
     Next, the operation of the comb filter switching processing is described with reference to  FIG. 10A  and  FIG. 10B . When the comb filter switching processing is started via Step SB 3  shown in  FIG. 7B , the CPU  10  proceeds to Step SE 1  shown in  FIG. 10A , and performs comb filter assign processing. 
     The comb filter assign processing is performed on both of the comb filter (CF) section (L)  164  which simulates random reflection of a reverberation sound and a dispersion process thereof on the left channel and the comb filter (CF) section (R)  165  which simulates random reflection of a reverberation sound and a dispersion process thereof on the right channel. However, here, only the comb filter switching processing to be performed in the comb filter (CF) section (L)  164  is described for simplification of description. 
     a. Operation of Comb Filter Assign Processing 
     In the comb filter assign processing, from among the five comb filter blocks connected in parallel, a comb filter block which is caused to make a transition “from filter output to a bypass state” and a comb filter block which is caused to make a transition “from a bypass state to filter output” are assigned in accordance with the stage progress. 
     Specifically, as with the above-described all-pass filter assign processing (refer to  FIG. 8A ), when the number of the comb filter CF which is caused to make a transition “from filter output to a bypass state” is “O” and the number of the comb filter CF which is caused to make a transition “from a bypass state to filter output” is “P”, a relation therebetween can be represented by the following modulo arithmetic operation (1) described above (O=mod(P+4, 5)). Note that, to associate the numbers [O] and [P] with numbers CF 1  to CF 5  of the comb filter blocks in the operation example shown in  FIG. 10B , each of them is incremented by “1”. That is, as the stage progresses, “O” and “P” change in a circulating manner within a range of the number of filters. 
     Here, a case is exemplarily described in which, in an example shown in  FIG. 10B , reverb type switching is performed in a situation where the comb filter blocks CF 1  to CF 4  at the first stage to the fourth stage connected in parallel are caused to function and the comb filter block CF 5  at the fifth stage is in a bypass state (unassigned). 
     In this case, when the number P of the comb filter block which is caused to make a transition “from filter output to a bypass state” at the initial switching stage  1  is set at “0: (CF 1 )”, the number P of the comb filter block which is caused to make a transition “from a bypass state to filter output” is “4: (CF 5 )” based on the above equation (1). 
     Then, when the comb filter assign processing is performed corresponding to the operation example shown in  FIG. 10B , the CPU  10  acquires assignment results (O, P) corresponding to the switching stages  1  to  4  base on the above equation (1) as described below, and the results are temporarily stored in the work area WA of the RAM  13  for the CPU. 
     Switching stage  1 : CF 1  (O=0)→CF 5  (P=4) 
     Switching stage  2 : CF 2  (O=1)→CF 1  (P=0) 
     Switching stage  3 : CF 3  (O=2)→CF 2  (P=1) 
     Switching stage  4 : CF 4  (O=3)→CF 3  (P=2) 
     b. Comb Filter Delay Time Change Processing 
     When, the comb filter assign processing at Step SE 1  is completed as described above, the CPU  10  performs the comb filter delay time change processing via the next Step SE 2  (refer to  FIG. 10A ). When the comb filter delay time change processing is started, the CPU  10  proceeds to Step SF 1  shown in  FIG. 11 . In the following descriptions, the operations of the present processing to be performed at the above switching stages  1  to  4  are described. 
     &lt;Operation of Switching Stage  1 &gt; 
     At Step SF 1 , the CPU  10  reads out the parameters (delay time T 5 , coefficient g 5 ) of the comb filter block CF 5  (P=4) in a bypass state from the reverb parameters RP stored in the RAM  13  for the CPU. The CPU  10  then sets the delay time T 5  to the delay element  51   e  (refer to  FIG. 6 ) of the comb filter CF 5  and sets the gain (coefficient) +g 5  to the multiplier  52   e . Here, since the gain (coefficient) c 5  of the multiplier  53   e  is “0”, the parameters (delay time T 5 , coefficient g 5 ) of the comb filter CF 5  can be updated without providing a delay change to the outside. 
     Next, at Step SF 2 , the CPU  10  waits until a transient period corresponding to the delay time T 5  set to the delay element  51   e  elapses. When the transient period elapses, the judgment result at Step SF 2  is “YES”, and therefore the CPU  10  proceeds to Step SF 3 . At Step SF 3 , by crossfading by envelope multiplication, the CPU  10  sets the gain (coefficient) c 1  of the multiplier  53   a  at “0” and sets the gain (coefficient) g 1   
     of the multiplier  52   a  at “0” in the comb filter block CF 1  (O=0). Also, the CPU  10  sets the gain (coefficient) c 5  of the multiplier  53   e  at “1” in the comb filter block CF 5  (P=4). This causes the “comb filter block CF 1  (O=0)” to make a transition to a bypass state and causes the “comb filter block CF 5  (P=4)” to make a transition to filter output. 
     Note that, as with the crossfading in the all-pass filters APF, crossfading in the all-pass filter APF is performed based on the timer value for judging the stage progress. 
     Then, the CPU  10  proceeds to Step SF 4 , and judges whether parameter rewrite has been ended, that is, whether the processing has been performed for all of the above-described switching stages  1  to  4 . If the processing has not been performed for all of the above-described switching stages  1  to  4 , the judgment result is “NO”, and therefore the CPU  10  return to the above-described Step SF 1 . Thereafter, the CPU  10  repeats the above-described Steps SF 1  to SF 4  until the processing is performed for all of the switching stages  1  to  4 . 
     Note that, to proceed to the next switching stage, the number O of the comb filter block which is caused to make a transition “from filter output to a bypass state” is incremented by one step, and then stored in a memory. Also, in the comb filter block CF[O] caused to make a transition to a bypass state by crossfading, the CPU  10  sets a gain (coefficient) io of the multiplier  53  at “0”. 
     &lt;Operation of Switching Stage  2 &gt; 
     At the switching stage  2 , the CPU  10  reads out the parameters (delay time T 1 , coefficient g 1 ) of the comb filter block CF 1  (P=0) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 1  to the delay element  51   a  and sets the gain (coefficient) +g 1  to the multiplier  52   a  in the comb filter CF 1 . 
     Here, since the gain (coefficient) c 1  of the multiplier  53   a  of the comb filter block CF 1  (P=0) is “0”, the parameters (delay time T 1 , coefficient g 1 ) of the comb filter CF 1  can be updated without providing a delay change to the next stage. Then, when the update of the parameters is ended, the CPU  10  waits until a transient period corresponding to the delay time T 1  elapses. 
     When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets the gain (coefficient) c 2  of the multiplier  53   b  at “0” and sets the gain (coefficient) g 2  of the multiplier  52   b  at “0” in the comb filter block CF 2  (O=1). Also, the CPU  10  sets the gain (coefficient) c 1  of the multiplier  53   a  at “1” in the comb filter block CF 1  (P=0). This causes the “comb filter block CF 2  (O=1)” to make a transition to a bypass state and causes the “comb filter block CF 1  (P=0)” to make a transition to filter output. 
     &lt;Operation of Switching Stage  3 &gt; 
     At the switching stage  3 , the CPU  10  reads out the parameters (delay time T 2 , coefficient g 2 ) of the comb filter block CF 2  (P=1) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 2  to the delay element  51   b  and sets the gain (coefficient) +g 2  to the multiplier  52   b  in the comb filter CF 2 . 
     Here, since the gain (coefficient) c 2  of the multiplier  53   b  of the comb filter block CF 2  (P=1) is “0”, the parameters (delay time T 2 , coefficient g 2 ) can be updated without providing a delay change to the outside. When the update of the parameters is ended, the CPU  10  waits until a transient period corresponding to the delay time T 2  elapses. 
     When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets the gain (coefficient) c 3  of the multiplier  53   c  at “0”, and sets the gain (coefficient) g 3  of the multiplier  52   c  at “0” in the comb filter block CF 3  (O=2). Also, the CPU  10  sets the gain (coefficient) c 1  of the multiplier  53   a  at “1” in the comb filter block CF 2  (p=1). This causes the “comb filter block CF 3  (O=2)” to make a transition to a bypass state and causes the “comb filter block CF 2  (P=1)” to make a transition to filter output. 
     &lt;Operation of Switching Stage  4 &gt; 
     At the switching stage  4 , the CPU  10  reads out the parameters (delay time T 3 , coefficient g 3 ) of the comb filter block CF 3  (P=2) in a bypass state from the reverb parameters RP. The CPU  10  then sets the delay time T 3  to the delay element  51   c , and sets the gain (coefficient) +g 3  to the multiplier  52   c  in the comb filter CF 3 . 
     Here, since the gain (coefficient) c 3  of the multiplier  53   c  of the comb filter block CF 3  (P=2) is “0”, the parameters (delay time T 3 , coefficient g 3 ) of the comb filter CF 3  can be updated without providing a delay change to the outside. When the update of the parameters is ended, the CPU  10  waits until a transient period corresponding to the delay time T 3  elapses. 
     When the transient period elapses, by crossfading by envelope multiplication, the CPU  10  sets the gain (coefficient) c 4  of the multiplier  53   d  at “0”, and sets the gain (coefficient) g 4  of the multiplier  52   d  at “0” in the comb filter block CF 4  (O=3). Also, the CPU  10  sets the gain (coefficient) c 2  of the multiplier  53   b  at “1” in the comb filter block CF 3  (P=2). This causes the “comb filter block CF 4  (O=3)” to make a transition to a bypass state and causes the “comb filter block CF 3  (P=2)” to make a transition to filter output. When the processing at all the switching stages  1  to  4  is completed, the judgment result at Step SF 4  is “YES”. Therefore, after ending the processing, the CPU  10  proceeds to the next Step SB 4  to perform the various amplification-related switching processing. 
     (4) Operation of Various Amplification-Related Switching Processing 
     Next, the operation of various amplification-related switching processing is described with reference to  FIG. 12 . When various amplification-related switching processing is performed via Step SB 4  shown in  FIG. 7B , the CPU  10  proceeds to Step SG 1  shown in  FIG. 12 , and performs low-pass filter (LPF) section (L) change processing. In switching of various parameters in this amplification-related switching processing, the setting values are gradually changed based on the timer value for judging the stage progress such that parameter switching is completed within a stage switching time, as with the crossfading of the comb filter CF and the all-pass filter APF. 
     In the low-pass filter (LPF) section (L) change processing, in accordance with the switching of the reverb type, the CPU  10  reads out the gain (coefficient) a as an LPF section parameter from the reverb parameters RP (refer to  FIG. 2B ), and provides the gain (coefficient) a to the multiplier  166   d  of the low-pass filter (LPF) section (L)  166  (refer to  FIG. 4B ) and provides a gain (coefficient)  1 - a  to the multiplier  166   a.    
     The CPU  10  then smoothly changes the value to a target value by interpolating the gain (coefficient)  1 - a  provided to the multiplier  166   d  and the gain (coefficient)  1 - a  provided to the multiplier  166   a , which makes the delay output smoothly follow an input change so as to adjust the sound quality of the reverberation sound on the left channel output of the comb filter (CF) section (L)  164 . 
     Next at Step SG 2 , the CPU  10  performs the low-pass filter (LPF) section (R) change processing. In this processing, in accordance with the switching of the reverb type, the CPU  10  reads out the gain (coefficient) a as an LPF section parameter from the reverb parameters RP (refer to  FIG. 2B ), and provides the gain (coefficient) a to the amplifier  167   d  of the low-pass filter (LPF) section (R)  167  and the gain (coefficient)  1 - a  to a multiplier  167   a.    
     The CPU  10  then smoothly changes the value to a target value by interpolating the gain (coefficient) a provided to the multiplier  167   d  and the gain (coefficient)  1 - a  provided to the multiplier  167   a , which, makes the delay output smoothly follow an input change so as to adjust the sound quality of the reverberation sound on the right channel output of the comb filter (CF) section (R)  165 . 
     Next at Step SG 3 , the CPU  10  performs the high-pass filter (HPF) section change processing. In this processing, in accordance with the switching of the reverb type, the CPU  10  reads out a gain (coefficient) b as an HPF section parameter from the reverb parameters RP (refer to  FIG. 2B ), and provides the gain (coefficient) b to the multiplier  162   c  of the high-pass filter (HPF) section  162 . Then, at the multiplier  162   c , the CPU  10  gradually shifts the gain (coefficient) provided so far to the newly-provided gain (coefficient) b so as to smoothly change the delay output. 
     Then, at Step SG 4 , the CPU  10  performs the output level change processing. In this processing, in accordance with the switching of the reverb type, the CPU  10  reads out the output level Otlvl from the reverb parameters RP (refer to  FIG. 2B ), and provides the output level to the multipliers  168  and  169  (refer to  FIG. 3 ) as their multiplication coefficients which adjust the level on the left and right channels for static control. Then, at each of the multipliers  168  and  169 , the CPU  10  gradually shifts the output level provided so far to the newly-provided output level Otlvl so as to make a smooth output change. 
     As such, in the various amplification-related switching processing, interpolation is performed at amplification related components which generate characteristics of the high-pass filter HPF and the low-pass filters LPF, a reverberation time in accordance with a delay feedback input amount, a reverberation sound density, and a reverb output level, in accordance with reverb type switching, and a change to a target value is smoothly achieved. 
     As described above, in the above-described embodiment, the delay recursive filters (all-pass filters APF, comb filters CF) of the plurality of systems functioning as circuit elements which simulate reverberation-sound random reflection and dispersion based on the reverberation algorithm include at least one backup system. The delay recursive filters being used in the plurality of systems are switched one by one by crossfading to an unassigned delay recursive filter for which parameter setting has been performed, in accordance with reverb type switching. This processing is repeated as many as the number of delay recursive filters included in the plurality of systems, whereby switching to a desired reverberation characteristic is smoothly performed. As a result of this configuration, unnaturalness occurring when a filter characteristic is changed can be solved. 
     This unnaturalness occurring when a filter characteristic is changed can be solved by a method in which reverb processing functions of two systems capable of being concurrently performed are provided, and a reverberation sound corresponding to a reverb type before switching which occurs at one system and a reverberation sound corresponding to a reverb type after the switching which occurs at the other system are subjected to crossfading. However, this method is not practical because an extra processing system which causes more resource waste in cost is required to be provided. By contrast, the present embodiment has a merit in cost in that unnaturalness occurring when a filter characteristic is changed can be solved without causing resource waste. 
     The above-described embodiment is configured to omit input volumes (input multipliers) of the comb filter blocks CF 1  to CF 5  constituting each of the comb filter (CF) section (L)  164  which simulates random reflection of a reverberation sound and a dispersion process thereof on the left channel and the comb filter (CF) section (R)  165  which simulates random reflection of a reverberation sound and a dispersion process thereof on the right channel. However, the present invention is not limited thereto, and input volumes (input multipliers) equivalent to the multipliers  30   a  to  30   e  of the all-pass filter blocks APF 1  to APF 5  (refer to  FIG. 5 ) may be provided. This circuit configuration can completely prevent a delay change to the outside. 
     Also, the all-pass filter assign processing (refer to Step SC 1  of  FIG. 8A ) and the comb filter assign processing (refer to Step SE 1  of  FIG. 10A ) in the above-described embodiment are merely examples of specific processing operations, and another assignment method may be adopted, such as a method of prioritizing and assigning a value closer to a target value between the current parameter value and a parameter value to be newly set or a method of changing the value stepwise when the change range of a parameter to be set is large. 
     Also, in the above-described embodiment, the control section which performs various control operations is actualized by the CPU (general-purpose processor) executing programs stored in the ROM (memory). However, a structure may be adopted in which the plural control operations are dividedly achieved by respective dedicated processors. In this structure, each dedicated processor may be constituted by a general-purpose processor (electronic circuit) which can execute a program and a control program tailored to each control, or may be constituted by a dedicated electronic circuit tailored to each program. 
     Also, in the above-described embodiment, the various filters are actualized by the digital circuit. However, they may be actualized by an analog circuit. 
     Furthermore, devices for acquiring the above-described various effects are not necessarily required to be structured as described above, and may be structured as follows. 
     (Structural Example 1) 
     A structure including:
         a set filter which includes a plurality of partial filters and forms a specified characteristic by combining the plurality of partial filters; and   a processor which performs, as crossfading processing for a first filter and a second filter among the plurality of partial filters, fade-out processing of gradually decreasing a degree of contribution of the first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of the second filter to the characteristic, when an instruction is provided for changing the characteristic formed by the set filter.       

     (Structural Example 2) 
     The structure of Structural Example 1, in which the processor takes a partial filter used for characteristic formation before the instruction as the first filter, takes a partial filter not used for the characteristic formation before the instruction and associated with the characteristic indicated by the instruction as the second filter, and performs the crossfading processing such that a partial filter contributing to the characteristic is switched from the first filter to the second filter. 
     (Structural Example 3) 
     The structure of Structural Example 1, in which the set filter is constituted by the plurality of partial filters including at least one backup partial filter, and
         in which the processor takes a partial filter used for characteristic formation before the instruction as the first filter, takes the backup partial filter as the second filter after setting a parameter corresponding to the characteristic indicated by the instruction to the backup partial filter, and performs the crossfading processing such that a partial filter contributing to the characteristic is switched from the first filter to the second filter.       

     (Structural Example 4) 
     The structure of Structural Example 3, in which the processor causes a characteristic that is set to the set filter to be selected from among a plurality of different characteristics, sets a parameter corresponding to the selected characteristic to the backup partial filter when an instruction for changing to the selected characteristic is provided, takes the backup partial filter as the second filter, and performs the crossfading processing such that the partial filter contributing to the characteristic is switched from the first filter to the second filter. 
     (Structural Example 5) 
     The structure of Structural Example 1, in which the plurality of partial filters is a plurality of delay recursive filters,
         in which the set filter forms a predetermined reverberation characteristic by combining the plurality of delay recursive filters including at least one backup delay recursive filter, and   in which the processor, when an instruction for changing a reverberation characteristic of the set filter is provided, switches a delay recursive filter used for reverberation characteristic formation before the instruction among the delay recursive filters constituting the set filter to an unused delay recursive filter associated with the reverberation characteristic indicated by the instruction, by using crossfading.       

     (Structural Example 6) 
     The structure of Structural Example 1, in which the set filter is constituted by a delay recursive filter which includes a circulating section and a delay section and is capable of varying a delay time of a signal and an amplification-related filter which is different from the delay recursive filter and is incapable of varying the delay time of the signal, and
         in which the processor performs switching by the crossfading processing for the delay recursive filter, and performs, for the amplification-related filter, processing of gradually changing each parameter of the amplification-related filter without using the crossfading processing,       

     (Structural Example 7) 
     The structure of Structural Example 1, in which the processor generates musical performance input information in accordance with a musical performance input operation and, when causing a sound source section to emit a musical sound in accordance with the generated musical performance input information, controls to emit the musical sound after adding a sound effect by the set filter. 
     (Structural Example 8) 
     A structure including:
         a characteristic formation section which includes a plurality of filters and forms a specified characteristic;   a change instruction section which provides an instruction for changing the characteristic formed by the characteristic formation section; and   a crossfading processing section which performs, as crossfading processing for a first filter and a second filter among the plurality of filters, fade-out processing of gradually decreasing a degree of contribution of the first filter to the characteristic and fade-in processing of gradually increasing a degree of contribution of the second filter to the characteristic, in response to the instruction from the change instruction section.       

     While the present invention has been described with reference to the preferred embodiments, it is intended that the invention be not limited by any of the details of the description therein but includes all the embodiments which fall within the scope of the appended claims.