Patent Publication Number: US-2004046598-A1

Title: I/o pad overvoltage protection circuitry

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS  
     [0001] This application is related to co-pending application “CMOS Transmission Gate with High Impedance at Power-Off”, application Ser. No. 10/119,101, filed Apr. 8, 2002, and “Input Termination with High Impedance at Power Off”, application Ser. No. 10/093,227, filed Mar. 5, 2002. 
    
    
     
       BACKGROUND OF THE INVENTION  
       [0002] The present invention relates generally to I/O circuits, and in particular to transmission gates with over-voltage protection.  
       [0003] The transmission gate is an integrated circuit which connects between an internal, core circuit and an I/O pad. The transmission gate circuit acts as a low-impedance connection to the pad under normal conditions where the supply voltage Vdd is greater than the voltage at the pad, which is also greater than zero or ground. However, when the I/O pad is subject to voltage spikes, or acts as an input, it is possible that its voltage may exceed that of the supply voltage. For example, a chip designed with a 3.3 volt power supply may be connected to another chip which uses 5-volt levels.  
       [0004]FIG. 1 illustrates a prior art transmission gate circuit. NMOS transmission gate transistor M 10  and PMOS transmission gate transistor M 9  connect core circuitry  10  to an I/O pad  12 . The P-well  14  of transistor M 10  is connected to ground, while the N-well  16  of transistor M 9  is connected to the power supply, V dd .  
       [0005] During normal conditions, when V dd  is greater than the voltage at the pad, V pad , which is greater than zero, the transmission gate is on. If the voltage at the pad should exceed the supply voltage by more than a threshold amount, the P-channel transistor M 10  is still on, effectively connecting pad terminal  12  to the internal core circuit. Thus, this circuit does not isolate the internal circuitry from the I/O pad when the pad voltage exceeds the supply voltage. If the voltage on the pad is greater than the supply voltage, the intrinsic PN diode between the source and the bulk (P-well  16 ) of transistor M 9  will turn on, shorting pad  12  to V dd . Alternately, the channel of PMOS transistor M 9  can simply turn on due to negative gate-to-source potential with the gate at zero and the source at a positive potential.  
       BRIEF SUMMARY OF THE INVENTION  
       [0006] The present invention provides a protection circuit for a transmission gate having a PMOS transmission gate transistor and an NMOS transmission gate transistor coupled between a core circuit and an I/O pad. A biasing transistor is coupled to a gate of the NMOS transmission gate transistor to turn it on during normal operation. A protection circuit will turn off the NMOS transmission gate transistor when the voltage at the pad exceeds the supply voltage by more than a threshold amount. This protection circuit includes a first protection transistor coupled between the gate of the biasing transistor and the pad to turn the biasing transistor off when the voltage on the pad exceeds the supply voltage by more than the threshold amount.  
       [0007] In one embodiment, one or more NMOS protection transistors are coupled between the gate of the PMOS transmission gate transistor and ground, with the gate of the PMOS transmission gate transistor being connected to the first protection transistor. In addition, an N-well biasing circuit is provided with a PMOS transistor coupled between the N-well and the pad, with the gate coupled to the supply voltage. Additionally, a second PMOS transistor is connected between the supply voltage V dd  and the N-well, with its gate connected to the first protection transistor.  
       [0008] In one embodiment, a second NMOS transmission gate transistor is added to limit the voltage drop across the first NMOS transmission gate transistor.  
       [0009] For a further understanding of the nature and advantages of the invention, reference should be made to the following description taken in conjunction with the accompanying drawings. 
     
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS  
     [0010]FIG. 1 is a diagram of a prior art transmission gate circuit.  
     [0011]FIG. 2 is a circuit diagram of one embodiment of the invention. 
    
    
     DETAILED DESCRIPTION OF THE INVENTION  
     [0012]FIG. 2 is a circuit diagram of an embodiment of the invention. As can be seen, transmission gates M 9  and M 10  connect between core circuitry  10  and I/O pad  12  as in FIG. 1. A second NMOS transmission gate transistor M 3  is added in one embodiment of the invention, to limit the voltage drop across transistor M 10  during an over-voltage condition.  
     [0013] The gate of NMOS transmission gate transistor M 10  is controlled by a signal GATEN, which is connected between a transistor M 1  and a resistor R 1 . R 1  connects to ground, while M 1  connects to the supply voltage, Vdd. The gate of PMOS transmission gate transistor M 9  is controlled by a signal OVERVOLT, which is connected to a protection transistor M 6 . The protection transistor M 6  is connected between the output pad  12  and the OVERVOLT line  19 , with its gate connected to the supply voltage, Vdd. Transistor M 6  is normally off, but turns on when the pad voltage  12  exceeds Vdd. This will cause it to turn on, connecting the OVERVOLT line  18  to the pad  12 , turning off transistor M 1 , thus allowing resistor R 1  to pull the gate of transistor M 10  to ground. This ensures that transistor M 10  is shut off, causing a high impedance between pad  12  and core circuitry  10 . In order to limit this voltage drop so that it is not all across transistor M 10 , a second transistor M 3  may be added, with its gate connected to the supply voltage Vdd. This is particularly useful for small geometry transistors.  
     [0014] Transistors M 7  and M 2  bias the N-well of the PMOS transistors. This N-well is indicated by BULK line  20 . Under an overvoltage condition, transistor M 7  will turn on, pulling the N-well BULK line  20  to the pad voltage. M 2  maintains the N-well at Vdd during normal operation.  
     [0015] Transistors M 4  and M 5  connect the gate of PMOS transmission gate transistor M 9  to ground. When the pad voltage exceeds the supply voltage, node  18  (OVERVOLT) is connected to the pad voltage, ensuring that the PMOS transmission gate transistor M 9  is also turned off, thus isolating the core.  
     [0016] The cascode connection of N-channel transistors M 3  and M 10  reduces their gate-to-source and drain-to-source voltages, protecting them from the excess voltage at the pad and thus preventing gate rupture. Devices M 4  and M 5  are long-channel devices, that together with M 6  form a ratioed logic when V PAD &gt;V dd &gt;0, and allow M 6  to pull up node OVERVOLT  18  to the pad voltage. Under normal conditions of V pad &lt;V dd , OVERVOLT  18  is pulled to ground, turning M 9  on. M 1  is also turned on, pulling the gate of M 10  to Vdd and turning it on. This connects the core to the pad under normal conditions.  
     [0017] As will be understood by those with skill in the art, the present invention may be embodied in other specific forms without departing from the essential characteristics thereof. For example, transistor M 3  is optional, and could be left out if transistor M 10  is of a sufficient size to handle the overvoltage. Alternately, the protection circuitry of the invention could be implemented at the core circuit level, rather than at the transmission gate. However, by implementing at the transmission gate, only a single circuit is needed for each pad. Accordingly, the foregoing description is intended to be illustrative, but not limiting, of the scope of the invention which is set forth in the following claims.