Patent Publication Number: US-6909652-B2

Title: SRAM bit-line reduction

Description:
FIELD 
   The present invention relates to digital circuits, and more particularly, to SRAM (Static Random Access Memory). 
   BACKGROUND 
   SRAM is used to store instructions or data in computer systems. For example, consider a computer system, such as that illustrated in FIG.  1 . In  FIG. 1 , microprocessor die  102  comprises many sub-blocks, such as register files  104  and on-chip cache  106 . Microprocessor  102  may also communicate to other levels of cache, such as off-chip cache  108 . Higher memory hierarchy levels, such as system memory  110 , are accessed via host bus  112  and chipset  114 . In addition, other off-chip functional units, such as graphics accelerator  116  and network interface controller (NIC)  118 , to name just a few, may communicate with microprocessor  102  via appropriate busses or ports. SRAM is used in register files  104  and on-chip cache  106 , as well as perhaps other functional units shown in FIG.  1 . 
   As technology scales to smaller dimensions, bit-line leakage current in SRAM may be a problem if not properly addressed. Consider a prior art SRAM shown in  FIG. 2 , comprising N transistor cells, where for simplicity only three cells are shown explicitly. Each cell comprises 6 transistors, two for each of the two cross-coupled inverters and two access transistors with their gates connected to a wordline. During pre-charge, Prech-Eq line  202  is held LOW so that pre-charge pMOSFETs  204  and  205  are ON to charge complementary bitlines  208  and  210  HIGH, and pMOSFET  212  is ON to equalize the voltages on complementary bitlines  208  and  210 . After pre-charge, when a cell is read, its corresponding wordline is held HIGH, and a sense amplifier (not shown) senses differential current developed on complementary bitlines  208  and  210  as a result of the read operation. 
   Suppose the data stored in the SRAM is such that node  214  in the top-most cell shown in  FIG. 2  is LOW and nodes  216  in all the other cells are LOW. This presents a worse-case scenario regarding leakage current, as is now discussed. Consider a read operation performed on the top-most cell. With wordline  218  HIGH, access transistor  218  is ON to sink a current I drive  from bitline  208 . The other wordlines are LOW, but because of the non-zero drain-to-source voltages in access transistors  222 , each access transistor  222  leaks some current I leak  from bitline  210 . As a result, the effective current for developing a differential signal senses by the sense amplifier is I drive −(N−1)I leak , and the effective current is thereby reduced when the leakage current increases. Consequently, as leakage current increases, there may be an increase in the likelihood of an incorrect read operation. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a high level abstraction of a computer system. 
       FIG. 2  is a prior art SRAM. 
       FIG. 3  is a SRAM according to an embodiment of the present invention. 
       FIG. 4  is a memory cell in the SRAM of FIG.  3 . 
   

   DESCRIPTION OF EMBODIMENTS 
     FIG. 3  shows a column of N memory cells in a SRAM for an embodiment of the present invention, where for simplicity only three memory cells  302 ,  304 , and  306  of the N memory cells are explicitly shown.  FIG. 4  shows the circuit for a memory cell in the embodiment of FIG.  3 . Four voltages are indicated in FIG.  3 . Supply rail  308  is at a supply voltage V CC , supply rail  310  is at a voltage V SS , supply rail  312  is at a voltage −V EE , and supply rail  314  is at a voltage V CCL , where −V EE &lt;V SS &lt;V CCL &lt;V CC . 
   It is to be understood that the term “supply rail” as used in the above discussion is in general some kind of conductive material, such as a copper interconnect, power plane, doped polysilicon, or may be the integrated circuit substrate itself upon which the circuit of  FIG. 3  is formed. The voltage V SS  of supply rail  310  may not necessarily refer to the substrate voltage, and it may not necessarily be a ground voltage. However, because only voltage differences have physical significance, for ease of discussion it is convenient to take V SS =0, in which case −V EE  is a negative voltage. A typical range for V EE  might be between 100 mV and 250 mV, for example. 
   During pre-charge, Prech-Eq line  316  is held at V SS , and when no pre-charge is being performed, Prech-Eq line  316  is driven to V CC . Pre-charge pMOSFETs  318  and  320  have their sources connected to rail  314 , so that their sources are at V CCL . Drivers  322 ,  324 , and  326  indicate that during a read operation on a memory cell, its corresponding wordline is driven to the supply voltage V CC , and when no read operation is performed, the wordline is driven to the negative voltage −V EE . As seen in  FIG. 3 , the voltage V CCL  is provided to each of the memory cells. Referring to the memory cell of  FIG. 4 , the sources of the pMOSFETs used in the cross-coupled inverters, pMOSFETs  402  and  404 , are at the voltage V CCL . 
   To maintain transistor reliability, the voltages should also satisfy the relationship: V EE ≦V CC −V CCL , or equivalently, V CCL +V EE ≦V CC . Because the magnitude of the largest voltage difference between the gate and source/drain of an access transistor is V CCL +V EE , this voltage relationship ensures that the magnitude of gate to source/drain voltage difference does not exceed V CC . 
   Before describing the roles of pMOSFETs  328  and  330 , assume that rail  314  is maintained at the voltage V CCL  that satisfies the earlier voltage relationship, −V EE &lt;V SS &lt;V CCL &lt;V CC . During pre-charge, the bitlines are pre-charged to V CCL . In an evaluation phase, the selected wordline is raised to V CC  and the non-selected wordlines are driven to the negative voltage −V EE . The leakage current through the access transistors in a non-selected cell is now greatly reduced because of the negative wordline voltage. For example, suppose that the data bit stored in the memory cell in  FIG. 4  is such that node  406  is V SS  and node  408  is V CCL . The gate-to-source voltage of access transistor  410  is −V EE , instead of zero for the prior art SRAM in  FIG. 2 , and consequently the subthreshold leakage current is significantly reduced. 
   The voltage V CCL  is derived from V CC  by pMOSFETs  328  and  330 , with their drains connected to rail  314  and their sources connected to supply rail  308 . The gate of pMOSFET  328  is connected to supply rail  310 . pMOSFET  330  is diode-connected, with its gate connected to its drain. The beta of pMOSFET  330  is greater than the beta of pMOSFET  328 . For example, the ratio of the beta of pMOSFET  330  to the beta of pMOSFET  328  may be at least 5, or for example, at least 10. 
   Suppose for the moment that pMOSFET  330  were not present, and V CCL  was provided only by using pMOSFET  328 . During pre-charge, the ON resistance of pMOSFET  328  provides a voltage drop due to the current demand of the pre-charge. This voltage drop determines V CCL , and because the current demand for every pre-charge is approximately the same throughout the array structure of a SRAM, the size of pMOSFET  328  may be readily determined in the design stage to provide a desired voltage for V CCL  during a pre-charge phase. However, current demand is not constant in time because of the large peak currents during an evaluation. If the beta of pMOSFET  328  is too large, these peak currents may cause too large of a voltage drop, resulting in a V CCL  that is too low. When V CCL  is too low, the performance of the sense amplifier connected to the bitlines may be adversely affected, and the memory cell stability decreases. On the other hand, if the beta of pMOSFET  328  is too small, the voltage drop may be too small, in which case the voltage relationship V EE ≦V CC −V CCL  may not be satisfied to ensure transistor reliability. 
   It is expected that the combination of both pMOSFET  328  and pMOSFET  330  as shown in the embodiment of  FIG. 3 , where the beta of pMOSFET  330  is substantially larger than that of pMOSFET  328 , may be designed so as to provide a proper V CCL  for both a pre-charge and an evaluation. Diode-connected pMOSFET  330  runs ON when the voltage difference between V CC  and V CCL  is greater than its threshold voltage. During an evaluation phase when the current is large, pMOSFET  330  pulls V CCL  slightly below V CC −V T , where V T  is the threshold voltage of pMOSFET  330 . pMOSFET  330  turns OFF when V CCL  is pulled above V CC −V T . pMOSFET  328  is sized to supply non-peak current to the bitlines and memory cells, and maintains the desired voltage difference between V CC  and V CCL . 
   Various modifications may be made to the disclosed embodiments without departing from the scope of the invention as claimed below.