Patent Publication Number: US-7721026-B2

Title: Interface controller, method for controlling read access, and information processing apparatus provided with the interface controller

Description:
CROSS-REFERENCE TO RELATED APPLICATION 
   This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-334525, filed on Dec. 12, 2006; the entire contents of which are incorporated herein by reference. 
   BACKGROUND OF THE INVENTION 
   The present invention relates to an interface controller which controls communication with a storage device, a method for controlling read access, and an information processing apparatus provided with the interface controller; and more particularly, relates to an interface controller which continuously issues read requests, a method for controlling read access which continuously issues read requests, and an information processing apparatus provided with the interface controller. 
   Peripheral component interconnect express (referred to as PCI EXPRESS™) is known as an interface which is for connecting two devices. Communication in the PCI EXPRESS™ (e.g., an interface which is for connecting two devices) is to send a packet (read request) which requires memory read and receives read response sent back from the other side device in the case when performing memory access (memory read access) for memory read which reads data stored in a memory with respect to the other side device including the memory. The received read response is stored in a receiving buffer and then sent to an upper system bus. 
   As a method which is for storing the read response in the receiving buffer and improving performance, there is a method in which a read request issuer (for example, a central processing unit (referred to as CPU), direct memory access (referred to as DMA), or the like) continuously issues in view of a receiving buffer size. In this case, in order not to generate overflow in the receiving buffer which receives the read response, the read request issuer needs to calculate a data sending amount in memory read access on the basis of a sideband signal which acquaints a receiving buffer size and status and to control the data sending amount. 
   However, when the data sending amount is calculated, a load is generated on the read request issuer. Further, a system bus is required for sending and receiving the sideband signal; and consequently, versatility as a device is reduced (Japanese Patent Application Laid-Open No. 2005-322308). 
   BRIEF SUMMARY OF THE INVENTION 
   According to the first aspect of the present invention, an interface controller connected to a read request device which performs a read request to a storage device stored with data, said interface controller comprising a receiving buffer which stores a read response of said storage device with respect to the read request sent from said read request device; and a control unit which performs read request authorization to said read request device on the basis of a capacity of said receiving buffer, a read request size and a read response size. 
   According to the second aspect of the present invention, a method for controlling read access which controls a read request of a read request device with respect to a storage device stored with data, said method comprising storing a read response of said storage device with respect to the read request sent from said read request device in a receiving buffer; and performing read request authorization to said read request device on the basis of a capacity of said receiving buffer, a read request size and a read response size. 
   According to the third aspect of the present invention, an information processing apparatus connected to a storage device which stores data, said information processing apparatus comprising a read request device which performs a read request with respect to said storage device in response to read request authorization, and an interface controller including a receiving buffer which stores a read response of said storage device with respect to said read request; and a control unit which performs the read request authorization to said read request device on the basis of a capacity of said receiving buffer, a read request size and a read response size. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. 1  is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention; 
       FIG. 2  is a block diagram showing an internal configuration of an interface controller  104  according to an embodiment of the present invention; 
       FIG. 3  is a block diagram showing an internal configuration of a protocol interpreting unit A  201  according to an embodiment of the present invention; 
       FIG. 4  is a block diagram showing an internal configuration of a read issue control unit  202  according to an embodiment of the present invention; 
       FIG. 5  is a flow chart showing a processing procedure in a request process of the interface controller  104  according to an embodiment of the present invention; 
       FIG. 6  is a flow chart showing a processing procedure in a response process of the interface controller  104  according to an embodiment of the present invention; and 
       FIG. 7  is a flow chart showing a processing procedure in a read issue control process (S 505  shown in  FIG. 5 ) of the read issue control unit  202  according to an embodiment of the present invention. 
   

   DETAILED DESCRIPTION OF THE INVENTION 
   Embodiments according to the present invention will be described with reference to the drawings hereinafter. In addition, the following embodiment is one embodiment of the present invention; and does not limit a scope of the present invention. 
     FIG. 1  is a block diagram showing a configuration of an information processing system according to an embodiment of the present invention. 
   The information processing system according to an embodiment of the present invention includes an information processing apparatus  100  and a storage device  110 , and both are connected with each other. 
   The information processing apparatus  100  includes a CPU  101 , a DMA  102 , a CPU  103 , an interface controller  104 , and a random access memory (referred to as RAM)  105 ; and these devices are mutually connected via a bus A  106 . The CPU  101 , the DMA  102  and the CPU  103  are devices which perform memory access (request) with respect to the storage device  110 ; the CPU  101  and the DMA  102  operate as a read request device; and the CPU  103  operates as a write request and read response device. The interface controller  104  controls the memory access by the CPU  101 , the DMA  102  and the CPU  103 . The RAM  105  stores read response sent from the storage device  110 . The bus A  106  performs communication in accordance with a general purpose protocol (for example, open core protocol (referred to as OCP)). In addition, the CPU  103  may be operated as the request device with respect to the storage device  110  or as the response device with respect to requests from the storage device  110 . 
   The storage device  110  includes a storage device interface controller  111  and a memory  112 , and these devices are mutually connected via a bus B  113 . The storage device interface controller  111  controls communication which is for sending responses sent from the memory  112  to the information processing apparatus  100  in accordance with a protocol of the bus B  113 . For example, a storage device interface controller  111  is the controller for the PCI EXPRESS™ (e.g., an interface which is for connecting two devices). The memory  112  can store various data for use in the information processing apparatus  100 ; and perform reading and writing data in response to the memory access by the CPU  101 , the DMA  102  and the CPU  103  in the information processing apparatus  100 . 
     FIG. 2  is a block diagram showing an internal configuration of the interface controller  104  according to an embodiment of the present invention. In addition, solid line arrows ( 1 ) to ( 14 ) included in  FIG. 2  denote data paths when a “read request” is performed by the CPU  101  or the DMA  102 ; dotted line arrows ( 1 )′ to ( 3 )′ denote data paths when a “write request or read response” is performed by the CPU  103 ; and dotted line arrows ( 4 )′ to ( 7 )′ denote data paths when a “read request or the like (read request, write request or read response) with respect to the information processing apparatus  100 ” is performed by the storage device  110 . 
   The interface controller  104  according to an embodiment of the present invention includes a protocol interpreting unit A  201 , a read issue control unit  202 , a protocol generating unit B  203 , a busy signal generating unit  204 , a protocol interpreting unit B  205 , a receiving buffer  206  and a protocol generating unit A  207 . The protocol interpreting unit A  201  and the protocol generating unit A  207  are connected to the bus A  106 . The protocol generating unit B  203  and the protocol interpreting unit B  205  are connected to the storage device interface controller  111 . The busy signal generating unit  204  is connected to the bus A  106  and to the storage device interface controller  111 . The respective units  201  to  207  are realized by an electric circuit (not shown in the drawing). 
   First, the case when the “read request” is performed by the CPU  101  or the DMA  102  will be described. (1) The protocol interpreting unit A  201  receives the read request in accordance with the protocol of the bus A  106 , and interprets contents of the protocol. (2) The protocol interpreting unit A  201  appends interpreting part identification information (information which represents as to the read request is interpreted by which interpreting part of the protocol interpreting unit A  201  (see  FIG. 3 )) to the read request, and sends the read request to the read issue control unit  202 . (3) The protocol interpreting unit A  201  sends the interpreting part identification information to the protocol generating unit A  207 . (4) The read issue control unit  202  performs a read issue control process (see  FIG. 7 ) (to be described later) with respect to the read request sent from the protocol interpreting unit A  201 , and sends the read request to the protocol generating unit B  203 . (5) The read issue control unit  202  appends the interpreting part identification information to a generated read busy signal, and sends the read busy signal to the busy signal generating unit  204  when the read busy signal is generated in the read issue control process. (6) The protocol generating unit B  203  receives the read request sent from the read issue control unit  202 , converts to the protocol of the bus B  113 , and sends the read request to the storage device interface controller  111 . (7) The busy signal generating unit  204  receives a bus B busy signal representing a busy state of the bus B  113  from the storage device interface controller  111 . (8) The busy signal generating unit  204  generates a busy signal with respect to the bus A  106 , and sends the busy signal to the bus A  106  when receiving the read busy signal or the bus B busy signal. (9) The protocol interpreting unit B  205  receives a read response from the storage device interface controller  111  in accordance with the protocol of the bus B  113 . (10) The receiving buffer  206  temporarily stores the read response sent from the protocol interpreting unit B  205 . (11) The receiving buffer  206  sends a receiving buffer size (maximum capacity of receiving buffer) to the read issue control unit  202 . (12) The receiving buffer  206  sends a read response size (data size of read response) to the read issue control unit  202 . (13) The receiving buffer  206  sends the read response to the protocol generating unit A  207 . (14) The protocol generating unit A  207  converts the read response sent from the receiving buffer  206  to the protocol of the bus A  106 , and sends the read response to the bus A  106  associating with the interpreting part identification information sent from the protocol interpreting unit A  201 . 
   Next, the case when the “write request or read response” is performed by the CPU  103  will be described. (1)′ The protocol interpreting unit A  201  receives the write request or the read response in accordance with the protocol of the bus A  106 , and interprets contents of the protocol. (2)′ The protocol interpreting unit A  201  sends the write request or the read response to the protocol generating unit B  203  on the basis of an interpreted result. (3)′ The protocol generating unit B  203  receives the write request or the read response sent from the protocol interpreting unit A  201 , converts to the protocol of the bus B  113 , and sends the write request or read response to the storage device interface controller  111 . 
   Next, the case when the “read request or the like with respect to the information processing apparatus  100 ” is performed by the storage device  110  will be described. (4)′ The protocol interpreting unit B  205  receives the read request or the like with respect to the information processing apparatus  100  from the storage device interface controller  111  in accordance with the protocol of the bus B  113 . (5)′ The receiving buffer  206  temporarily stores the read request or the like with respect to the information processing apparatus  100  sent from the protocol interpreting unit B  205 . (6)′ The receiving buffer  206  sends the read request or the like with respect to the information processing apparatus  100  to the protocol generating unit A  207 . (7)′ The protocol generating unit A  207  converts the read request or the like with respect to the information processing apparatus  100  sent from the receiving buffer  206  to the protocol of the bus A  106 , and sends the read request or the like to the bus A  106 . 
   In addition, a capacity of the receiving buffer  206  needs a capacity larger than a read request size (data size of the response which can require for one read request) of the bus B  113 . For example, when the capacity of the receiving buffer  206  is eight times as large as the read request size, read requests of maximum eight times can be continuously issued. In addition, in embodiment of the present invention, the configuration provided with one receiving buffer  206  is described; however, a plurality of receiving buffers  206  may be provided for each interpreted result by the protocol interpreting unit B  205 . 
     FIG. 3  is a block diagram showing an internal configuration of the protocol interpreting unit A  201  according to embodiment of the present invention. 
   The protocol interpreting unit A  201  according to an embodiment of the present invention includes a first interpreting part  311  connected to a first buffer  312 , a second interpreting part  321  connected to a second buffer  322  and a third interpreting part  331  connected to a third buffer  332 ; and the respective interpreting parts  311  to  331  are connected to the bus A  106 . The respective interpreting parts  311  to  331  are realized by an electric circuit (not shown in the drawing). 
   The first interpreting part  311  to the third interpreting part  331  are provided for each issue source of the request or the response sent via the bus A  106 . In embodiment of the present invention, the first interpreting part  311  interprets a protocol of the request issued by the CPU  101 ; the second interpreting part  321  interprets a protocol of the request issued by the DMA  102 ; and the third interpreting part  331  interprets a protocol of the request or the response issued by the CPU  103 . 
   The first interpreting part  311  receives the read request issued by the CPU  101  via the bus A  106 , stores the read request in the first buffer  312 , and interprets the protocol. In addition, the read request stored in the first buffer  312  is continued to be kept till the read request is sent to the read issue control unit  202 . The second interpreting part  321  and the second buffer  322 , and the third interpreting part  331  and the third buffer  332  are the same as the first interpreting part  311  and the first buffer  312 ; and therefore, their description will be omitted. 
     FIG. 4  is a block diagram showing an internal configuration of the read issue control unit  202  according to embodiment of the present invention. 
   The read issue control unit  202  according to an embodiment of the present invention includes a selecting unit of a protocol interpreting part  401 , a first accumulating unit  402 , a second accumulating unit  403 , a first calculating unit  404 , a second calculating unit  405 , a comparing unit  406  and a read busy signal generating unit  407 . The respective units  401  to  407  are realized by an electric circuit (not shown in the drawing). 
   The selecting unit of the protocol interpreting part  401  selects an protocol interpreting part to be an object of the read issue control process on the basis of a predetermined priority order when a plurality of the requests are sent in parallel from the first interpreting part  311 , the second interpreting part  321 , and the third interpreting part  331  of the protocol interpreting unit A  201 . The priority order is determined by, for example, a round-robin fashion (fashion which changes the priority order of the first interpreting part  311  to the third interpreting part  331  with time) or a fixing fashion (fashion based on a predetermined priority order). 
   The first accumulating unit  402  accumulates a total value (m 2 ) of a read request size of the read request in which the read issue has been completed. The second accumulating unit  403  accumulates a total value (n 1 ) of a read response size of the read response in which the response process has been completed. 
   The first calculating unit  404  calculates the sum (M (=m 1 +m 2 )) of a read request size (m 1 ) of the read request of the interpreting part selected by the selecting unit of the protocol interpreting part  401  and the total value (m 2 ) of the read request size accumulateed in the first accumulating unit  402 . The second calculating unit  405  calculates the sum (N (=n 1 +n 2 )) of the total value (n 1 ) of the read response size accumulateed in the second accumulating unit  403  and a receiving buffer size (n 2 ) sent from the receiving buffer  206 . 
   The comparing unit  406  compares magnitude relation between the calculated result (M) of the first calculating unit  402  and the calculated result (N) of the second calculating unit  405 . The read busy signal generating unit  407  generates the read busy signal and sends the busy signal to the busy signal generating unit  204  when a compared result of the comparing unit  406  is M&gt;N. 
     FIG. 5  is a flow chart showing a processing procedure in the request process of the interface controller  104  according to embodiment of the present invention. 
   First, the interface controller  104  according to embodiment of the present invention receives the request in accordance with the protocol of the bus A  106  (S 501 ). Next, contents of the protocol of the received request are interpreted (S 502 ). In addition, steps S 501  and S 502  are performed in parallel by the respective interpreting parts  311  to  331 . 
   Next, the interpreting part to be processed (any one of the first interpreting part  311  to the third interpreting part  331 ) is selected on the basis of the predetermined priority order (S 503 ). Next, when an interpreted result of the interpreting part selected in step S 503  is the “read request” (S 504 -Yes), the “read issue control process (FIG.  7 )” (to be described later) is performed (S 505 ). Next, the process returns to step S 503  when the read busy signal is generated (S 505 -Yes), or when the bus B busy signal is sent from the storage device interface controller  111  (S 506 -Yes). 
   Meanwhile, when both the read busy signal and the bus B busy signal are absent (S 506 -No and S 507 -No), a read request size of the read request in which the read issue control process is performed in step S 505  is added to the value of m 2  (issued read request size) to update (S 508 ). Next, the read request of the interpreting part selected in step S 503  is converted to the protocol of the bus B  113  (S 509 ). Next, the read request is sent to the storage device interface controller  111  in accordance with the protocol of the bus B  113  (S 510 ). 
   On the other hand, when the interpreted result of the interpreting part selected in step S 503  is the “write request or read response” (S 504 -No), a write request process or a read response process with respect to from the bus A  106  to the bus B  113  is performed (S 511 ). A description of the write request process or the read response process will be omitted. Next, the write request or the read response processed in step S 511  is converted to the protocol of the bus B  113  (S 509 ). Next, the write request or the read response is sent to the storage device interface controller  111  in accordance with the protocol of the bus B  113  (S 510 ). 
     FIG. 6  is a flow chart showing a processing procedure in the response process of the interface controller  104  according to embodiment of the present invention. In addition, the response process is a process with respect to the request performed by the CPU  101 , the DMA  102  or the CPU  103 . 
   First, the interface controller  104  according to embodiment of the present invention receives the response in accordance with the protocol of the bus B  113  (S 601 ). Next, contents of the protocol of the received response are interpreted (S 602 ). 
   Next, when an interpreted result in step S 602  is the “read response” (S 603 -Yes), the read response is stored in the receiving buffer  206  (S 604 ). Next, the interpreting part identification information of the interpreting part selected in step S 503  shown in  FIG. 5  is associated with the read response stored in the receiving buffer  206  (S 605 ). Next, the read response size of the read response associated in step S 605  is added to the total value (n 2 ) of the read response size accumulateed in the second accumulating unit  302  to update (S 606 ). Next, the read response stored in the receiving buffer  206  in step S 604  is converted to the protocol of the bus A  106  (S 607 ). Next, the read response is sent to the bus A  106  in accordance with the protocol of the bus A  106  (S 608 ). 
   Meanwhile, when the interpreted result in step S 602  is the “read request or the write request” (S 603 -No), the read request process or the write request process with respect to from the bus B  113  to the bus A  106  is performed (S 609 ). A description of the read request process or the write request process will be omitted. Next, the read request or the write request processed in step S 609  is converted to the protocol of the bus A  106  (S 607 ). Next, the read request or the write request is sent to the bus A  106  in accordance with the protocol of the bus A  106  (S 608 ). 
     FIG. 7  is a flow chart showing a processing procedure in the read issue control process of the read issue control unit  202  (S 505  shown in  FIG. 5 ) according to embodiment of the present invention. 
   First, the read issue control unit  202  according to embodiment of the present invention obtains the read request size (m 1 ) of the interpreting part selected in step S 503  (S 701 ). Next, the total value (m 2 ) of the read request size accumulateed in the first accumulating unit  402  is obtained (S 702 ). Next, M (=m 1 +m 2 ) is calculated (S 703 ). 
   Furthermore, the total value (n 1 ) of the read response size accumulateed in the second accumulating unit  403  is obtained (S 704 ). Next, the receiving buffer size (n 2 ) of the receiving buffer  206  is obtained (S 705 ). Next, N (=n 1 +n 2 ) is calculated (S 706 ). 
   Next, magnitude relation between M and N is compared (S 707 ). If the relation is M&gt;N (S 707 -Yes), the read busy signal is generated, and it is sent to the busy signal generating unit  204  (S 708 ). Meanwhile, the relation is M&lt;N (S 707 -No), read issue is performed, and the read request is sent to the protocol generating unit B  203  (S 709 ). 
   According to of the present invention, only when the relation is M≦N the read issue is performed (S  709 ); and therefore, overflow is not occurred in the receiving buffer  206 . Therefore, the CPU  101  and the DMA  102  can continuously issue the read request without occurring the overflow in the receiving buffer  206 . 
   In addition, the CPU  101  and the DMA  102  issue the read request on the basis of a state whether or not the busy signal is generated by the busy signal generating unit  204  (that is, whether or not the bus A is in a busy state). That is, when the bus A is not in the busy state, the CPU  101  and the DMA  102  issue the read request without calculating the read request size. Therefore, the CPU  101  and the DMA  102  do not need to perform a process for calculating the read request size; and consequently, an extra load is not occurred.