Patent Publication Number: US-10778110-B2

Title: DC-DC power converter

Description:
BACKGROUND 
     CROSS-REFERENCE TO RELATED APPLICATION 
     This application is a U.S. National stage of International Application No. PCT/US2015/055338, filed Oct. 13, 2015. 
     Field of the Invention 
     The present invention generally relates to a power converter. 
     Background Information 
     A power system that can be used for powering a vehicle, such as an electric vehicle or a hybrid electric vehicle, is conventionally known in the art. For example, in the vehicle, a dual-voltage power system is used, for example, in which the 12V system to feed the electric load, such as head and tail lights, heating fans, audio system and so forth, and the high voltage system to feed the traction inverter, motor and so forth, are present. With the dual-voltage power system, it is convenient to transfer energy between the two voltage systems. For this purpose, a power converter is installed in the vehicle. 
     Specifically, a phase-shift type full bridge converter is provided in “A 1 kW 500 kHz Front-End Converter for a Distributed Power Supply System” by Mweene et al., IEEE Transactions on Power Electronics, vol. 6, no. 3, pp. 398-407, July 1991 (hereinafter “Non-Patent Literature 1”), for example. Also, a three-port converter is provided in “Idling Port Isolation Control of Three-Port Bidirectional Converter for EVs” by Kim et al., IEEE Transactions on Power Electronics, vol. 27, no. 5, pp. 2495-2506, May 2012 (hereinafter “Non-Patent Literature 2”), for example. With this three-port converter of Non-Patent Literature 2, the power flow to a predetermined port can be prevented to idle the port. 
     SUMMARY 
     With the converter of Non-Patent Literature 1, the power flow between the power sources and the loads is controllable. However, with this converter, it is difficult to reduce the size and cost of the converter. On the other hand, with the converter of Non-Patent Literature 2, the number of parts of the converter can be reduced. However, with this converter, a complex switching action is required to idle a port, and it is difficult to prevent an energy loss at the idling port, which in turn requires the component design to take the heat generation due to the loss into account. Thus, with this converter, it is also difficult to reduce the size and cost of the converter. 
     One aspect is to provide a power converter with which the size and cost thereof can be reduced. 
     In view of the state of the known technology and in accordance with a first aspect, a power converter includes at least three switching circuits, at least one power source, at least one load, and a resonant circuit, input terminals of the switching circuits being connected to either the at least one power source or the at least one load, and output terminals of the switching circuits being electrically serially connected to the resonant circuit to form a closed circuit. 
     With the power converter according to the first aspect, the power between a plurality of ports can be controlled as desired. Thus, it is possible to provide a power converter with which the number of parts can be reduced and the size and the cost thereof can be reduced. 
     In accordance with a second aspect, the power converter according to the first aspect, wherein the sum of the fundamental component of voltage waveform generated by a set of the switching circuits that is connected to the at least one power source is substantially equal to the sum of the fundamental component of voltage waveform applied to a set of the switching circuits that is connected to the at least one load. 
     With the power converter according to the second aspect, the power between a plurality of ports can be controlled as desired by making the sum of the fundamental component of the at least one power source selectively filtered by the resonant circuit to be equal to the sum of fundamental component of the at least one load. 
     In accordance with a third aspect, the power converter according to the first or second aspect, wherein the frequencies of the voltage waveforms are substantially equal to the resonant frequency of the resonant circuit. 
     With the power converter according to the third aspect, the fundamental component can be selectively obtained by making the frequencies of the voltage waveforms to be near the resonant frequency of the resonant circuit. 
     In accordance with a fourth aspect, the power converter according to any one of first to third aspects, wherein the phases of the voltage waveforms are substantially equal to each other. 
     With the power converter according to the fourth aspect, the sum of the fundamental component of the at least one power source and the sum of the fundamental component of the at least one load can be made equal to each other by making the voltage waveforms to be the same phase. 
     In accordance with a fifth aspect, the power converter according to any one of the first to fourth aspects, wherein at least one of the output terminals of the switching circuits is serially connected to the closed circuit via an isolation transformer. 
     With the power converter according to the fifth aspect, a desired output terminal can be electrically isolated from the other output terminal by connecting at least one pair of output terminals via the transformer. 
     In accordance with a sixth aspect, the power converter according to any one of the first to fifth aspects, wherein the characteristic impedance of the resonant circuit is higher than the total effective load resistance value serially connected to the closed circuit. 
     With the power converter according to the sixth aspect, the fundamental component of the voltage waveform can be effectively filtered by the resonant circuit by making the characteristic impedance of the resonant circuit to be higher than the total effective load resistance value. 
     In accordance with a seventh aspect, the power converter according to any one of the first to sixth aspects, wherein at least one of the output terminals of the switching circuits is electrically shorted via a switching element of an upper arm or a switching element of a lower arm in the switching circuit. 
     With the power converter according to seventh aspect, the at least one of the output terminals of the switching circuits is electrically shorted via the switching element of the upper arm or the switching element of the lower arm in the switching circuit. Thus, the power input to the shorted output terminal and the power output from the shorted output terminal can be zero, thereby decreasing the loss at the switching element. 
     In accordance with an eighth aspect, the power converter according to the seventh aspect, wherein the at least one of the output terminals of the switching circuits is electrically shorted alternately via the switching element of the upper arm and the switching element of the lower arm in the switching circuit. 
     With the power converter according to the eighth aspect, the at least one of the output terminals of the switching circuits is electrically shorted alternately via the switching element of the upper arm and the switching element of the lower arm in the switching circuit. Thus, the excessive temperature increase at the switching element used for the short circuit can be prevented. 
     In accordance with a ninth aspect, the power converter according to the seventh or eighth aspect, wherein at least one of the switching circuits includes a full bridge circuit. 
     With the power converter according to the ninth aspect, the output terminal of the switching circuit can be easily electrically shorted by making the at least one of the switching circuits include the full bridge circuit. 
     In accordance with a tenth aspect, the power converter according to any one of first to ninth aspect further includes a calculation unit configured to calculate a load resistance value based on the applied voltage to the at least one load and the average current to the at least one load, and a control unit configured to determine the duty ratio of the switching circuits based on the load resistance value, the power source voltage value and the target voltage value to the at least one load. 
     With the power converter according to tenth aspect, the power converter includes the calculation unit configured to calculate the load resistance value based on the applied voltage to the at least one load and the average current to the at least one load, and the control unit configured to determine the duty ratio of the switching circuits based on the load resistance value, the power source voltage value and the target voltage value to the at least one load. Thus, the power between a plurality of ports can be controlled as desired. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Referring now to the attached drawings which form a part of this original disclosure: 
         FIG. 1  is a circuit diagram illustrating a circuit structure of a power converter in accordance with a first embodiment; 
         FIG. 2  is a circuit diagram illustrating a circuit structure that is identical to the circuit structure illustrated in  FIG. 1 , except that second and third isolation transformers are added to second and third ports, respectively; 
         FIG. 3  is a circuit diagram illustrating an AC equivalent circuit of the circuit structure illustrated in  FIG. 2 ; 
         FIG. 4  illustrates voltage waveforms illustrating relationship between v FC1 (t) and v SQ1 (t); 
         FIG. 5  is a circuit diagram illustrating a circuit structure of the second port illustrated in  FIG. 2 ; 
         FIG. 6  is a circuit diagram illustrating an AC equivalent circuit of the circuit structure of the second port illustrated in  FIG. 5 ; 
         FIG. 7  is a waveform of i 2 (t); 
         FIG. 8  is a graph of an average current I AVE2  flowing through a second load resistance; 
         FIG. 9  illustrates graphs expressing sin(β) and sin(γ) as functions of sin(α); 
         FIG. 10  illustrates graphs illustrating relationships between a duty ratio of a first port and equivalent resistances R E2  and R E3 ; 
         FIG. 11  illustrates graphs illustrating relationships between the duty ratio of the first port and duty ratios of the second and third ports; 
         FIG. 12  illustrates a graph illustrating relationship between the duty ratio of the first port and a peak voltage of the voltage v FC1 (t); 
         FIG. 13  illustrates a graph illustrating relationship between the duty ratio of the first port and a peak resonant current of the current I R ; 
         FIG. 14  illustrates a graph illustrating relationship between the duty ratio of the first port and a Q factor; 
         FIG. 15  illustrates a circuit diagram used in the simulation; 
         FIG. 16  illustrates waveforms of v SQ1 (t), v SQ2 (t), and v SQ3 (t); 
         FIG. 17  illustrates waveforms of i R (t), i 1 (t), i 2 (t), and i 3 (t); 
         FIG. 18  illustrates waveforms of output voltages V DC2  and V DC3  of the second and third ports, respectively; 
         FIG. 19  is a circuit diagram illustrating a circuit structure of a power convertor in accordance with a second embodiment; 
         FIG. 20  is a circuit diagram illustrating a circuit structure of a power convertor in accordance with a third embodiment; 
         FIG. 21  is a circuit diagram illustrating a circuit structure of a power convertor in accordance with a fourth embodiment; 
         FIG. 22  is a circuit diagram illustrating a circuit structure of a power convertor in accordance with a fifth embodiment; 
         FIG. 23  is a circuit diagram illustrating an AC equivalent circuit of the circuit structure illustrated in  FIG. 22 ; and 
         FIG. 24  is a circuit diagram illustrating a circuit structure of a power convertor in accordance with a modified example of the fifth embodiment. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     Selected embodiments will now be explained with reference to the drawings. It will be apparent to those skilled in the art from this disclosure that the following descriptions of the embodiments are provided for illustration only and not for the purpose of limiting the invention as defined by the appended claims and their equivalents. Like reference numerals in the drawings denote like similar or identical elements or features, and thus the descriptions of the similar or identical elements or features may be omitted in later embodiments. 
     First Embodiment 
     Referring to  FIGS. 1 to 18 , and Tables 1 and 2, a power converter  100  is illustrated in accordance with a first embodiment.  FIG. 1  is a circuit diagram illustrating a circuit structure of the power converter  100 . As shown in  FIG. 1 , the power converter  100  is the so-called multi-port converter with three ports, such as a first port  201 , a second port  202 , and a third port  203 . The first port  201  includes a first switching circuit  101  and a first power source  4 . The second port  202  includes a second switching circuit  102 , a second smoothing capacitor  5  and a second load resistance  6 . The third port  203  includes a third switching circuit  103 , a third smoothing capacitor  7  and a third load resistance  8 . As illustrated in  FIG. 1 , each of the first, second and third switching circuits  101 ,  102  and  103  includes four switching elements, such as MOSFET or any other elements as needed and/or desired. In the illustrated embodiment, each of the first, second and third switching circuits  101 ,  102  and  103  includes a full bridge circuit. However, the first, second and third switching circuits  101 ,  102  and  103  can be a different type of circuit, such as a half bridge circuit. 
     The power converter  100  also includes a controller  110  having a calculation unit  112  and a control unit  114 . The controller  110  controls the first, second and third switching circuits  101 ,  102  and  103 , respectively, using the pulse width modulation (PWM). In particular, in the illustrated embodiment, the controller  110  controls the first, second and third switching circuits  101 ,  102  and  103 , respectively, using the phase shifted PWM. The controller  110  basically determines the duty ratios of the first, second and third switching circuits  101 ,  102  and  103 , respectively, to obtain desired output voltages at the second and third load resistances  6  and  8  relative to a predetermined input voltage at the first power source  4 . The operation of the controller  110  will be explained later. 
     As can be appreciated by one skilled in the art, the controller  110  preferably includes at least one microcomputer with a control program that controls the components of the controller  110  as discussed below. Thus, the microcomputer or microcomputers can be configured and programmed to embody any or all of the calculation unit  112  and the control unit  114 . The controller  110  includes other conventional components such as an input interface circuit, an output interface circuit, and storage devices such as a ROM (Read Only Memory) device and a RAM (Random Access Memory) device. It will be apparent to those skilled in the art from this disclosure that the precise structure and algorithms for the controller  110  can be any combination of hardware and software that will carry out the functions of the present invention. In other words, “means plus function” clauses as utilized in the specification and claims should include any structure or hardware and/or algorithm or software that can be utilized to carry out the function of the “means plus function” clause. In addition, although several of the components of the controller  110  are described as modules or units, these components need not be individual or separate components, and one component or module can perform the operations of multiple components or modules discussed herein. Also, each module can include a microcontroller as discussed above or multiple modules can share one or more microcontrollers. 
     The power converter  100  can be used for powering a vehicle, for example. In the illustrated embodiment, as illustrated in  FIG. 1 , the power converter  100  is a DC-DC converter with the first power source  4  as a single input and the second and third load resistances  6  and  8  as multiple (a pair of) outputs. However, the number of input of the power converter  100  can be different as desired and/or needed, and the number of output of the power converter  100  can be different as desired and/or needed. As illustrated in  FIG. 1 , the first power source  4  is a DC power source, such as a battery. However, as understood in the art, with the power convertor  100 , power can be delivered from its ultimate source as AC power. In this case, the delivered AC power is then transformed into DC power using a rectifier arrangement or any other suitable arrangement. Then, the transformed DC power can be applied to the power converter  100  as an input. Also, as understood in the art, the outputs of the power converter  100  can be connected to the dual voltage power system installed in the vehicle, for example. 
     As illustrated in  FIG. 1 , with the power converter  100 , a first output terminal  301  of the first switching circuit  101 , a second output terminal  302  of the second switching circuit  102 , a third output terminal  303  of the third switching circuit  103  and a series resonant circuit  1  are connected in series with respect to each other to form a closed circuit. The series resonant circuit  1  includes a resonant capacitor  2  and a resonant inductor  3 . 
     Referring now to  FIG. 2 , the operation of the power converter  100  will be explained.  FIG. 2  illustrates a circuit structure that is identical to the circuit structure illustrated in  FIG. 1 , except that second and third isolation transformers  21  and  22  are added to the second and third ports  202  and  203 , respectively. As shown in  FIG. 2 , the numbers of turns of the second isolation transformer  21  are n 2P  and n 2S , respectively, while the numbers of turns of the third isolation transformer  22  are n 3P  and n 3S , respectively. With the configuration shown in  FIG. 2 , the first, second and third ports  201 ,  202  and  203  are electrically isolated with respect to each other. 
     Referring to  FIG. 2 , the operation of the power converter  100  will be explained by taking the turns ratios of the second and third isolation transformers  21  and  22  into account. The circuit configuration shown in  FIG. 1  is achieved by setting the numbers of turns shown  FIG. 2  as follows: n 2P =n 2S  and n 3P =n 3S . 
     In  FIG. 2 , V DC1  represents the voltage of the first power source  4 , R 2  represents the resistance value of the second load resistance  6 , V DC2  represents the voltage applied to the second load resistance  6 , R 3  represents the resistance value of the third load resistance  8 , and V DC3  represents the voltage applied to the third load resistance  8 . Also, in  FIG. 2 , v SQ1 (t), V SQ2 (t) and v SQ3 (t) represent the differential voltages of the output terminals of the first, second and third ports  201 ,  202  and  203 , respectively. Furthermore, in  FIG. 2 , i R (t) represents the current that flows through the series resonant circuit  1 . 
       FIG. 3  illustrates an AC equivalent circuit of the multi-port converter circuit shown in  FIG. 2 . The AC equivalent circuit shown in  FIG. 3  includes a first equivalent alternating current (AC) power source  31 , a second equivalent load resistance  32 , and a third equivalent load resistance  33 . The first equivalent AC power source  31  has a voltage component of v FC1 (t). In  FIG. 3 , R E2  represents the resistance value of the second equivalent load resistance  32 , and v FC2 (t) represents the voltage value applied to the second equivalent load resistance  32 . Also, in  FIG. 3 , R E3  represents the resistance value of the third equivalent load resistance  33 , and v FC3 (t) represents the voltage value applied to the third equivalent load resistance  33 . 
     With the AC equivalent circuit shown in  FIG. 3 , the frequencies f S  of the voltages v FC1 (t), v FC2 (t), and v FC3 (t) are set to be substantially equal to the resonance frequency f R  of the series resonant circuit  1 . Under this frequency condition, as understood from the principle of the series resonance, the impedance of the series resonant circuit  1  becomes substantially zero and the voltage applied to the series resonant circuit  1  becomes substantially zero. Therefore, the following formulas (1) to (3) are satisfied: 
     
       
         
           
             
               
                 
                   
                     
                       
                         v 
                         
                           FC 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       ⁡ 
                       
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                   = 
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                           ⁢ 
                           
                               
                           
                           ⁢ 
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                           ⁢ 
                           
                               
                           
                           ⁢ 
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                           R 
                           
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                             ⁢ 
                             
                                 
                             
                             ⁢ 
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                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                     
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                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
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                         ( 
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                         ) 
                       
                     
                   
                 
               
               
                 
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                           ⁢ 
                           
                               
                           
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                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         + 
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                     
                     ⁢ 
                     
                       
                         v 
                         
                           FC 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           1 
                         
                       
                       ⁡ 
                       
                         ( 
                         t 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   3 
                   ) 
                 
               
             
           
         
       
     
       FIG. 4  illustrates the voltage waveforms illustrating the relationship between v FC1 (t) and v SQ1 (t). In  FIG. 4 , v FC1 (t) is illustrated with a dot-dash line, while v SQ1 (t) is illustrated with a solid line. Here, v SQ1 (t) represents the square wave generated by the first power source  4  and the first switching circuit  101 . The square wave such as this can be generated by the phase shift control, as understood in the art. In the illustrated embodiment, v SQ1 (t) is the square wave as illustrated in  FIG. 4 , where a represents the conduction angle of the first switching circuit  101 . The fundamental component v FC1 (t) of this square wave is expressed by the following formula (4): 
     
       
         
           
             
               
                 
                   
                     
                       v 
                       
                         FC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ⁡ 
                     
                       ( 
                       t 
                       ) 
                     
                   
                   = 
                   
                     
                       4 
                       π 
                     
                     ⁢ 
                     
                       V 
                       
                         DC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         α 
                         ) 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         
                           ω 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           t 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   4 
                   ) 
                 
               
             
           
         
       
     
     Similarly, the fundamental component v FC2 (t) of v SQ2 (t) and the fundamental component v FC3 (t) of v SQ3 (t) are expressed by the following formulas (5) and (6) when taking the turns ratios of the second and third isolation transformers  21  and  22  into account, where β represents the conduction angle of v SQ2 (t) and γ represents the conduction angle of v SQ3 (t). 
     
       
         
           
             
               
                 
                   
                     
                       v 
                       
                         FC 
                         ⁢ 
                         
                             
                         
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                         2 
                       
                     
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                       t 
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                   = 
                   
                     
                       - 
                       
                         ( 
                         
                           
                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
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                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
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                               S 
                             
                           
                         
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                     ⁢ 
                     
                       4 
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                     ⁢ 
                     
                       V 
                       
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                         ⁢ 
                         
                             
                         
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                       sin 
                       ⁡ 
                       
                         ( 
                         β 
                         ) 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         
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                   ( 
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                   ) 
                 
               
             
             
               
                 
                   
                     
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                       π 
                     
                     ⁢ 
                     
                       V 
                       
                         DC 
                         ⁢ 
                         
                             
                         
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                         3 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         γ 
                         ) 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         
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                           ⁢ 
                           
                               
                           
                           ⁢ 
                           t 
                         
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   6 
                   ) 
                 
               
             
           
         
       
     
     Furthermore, the amplitudes of v FC1 (t), v FC2 (t), and v FC3 (t) are expressed by the following formulas (7) to (9): 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       FC 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       1 
                     
                   
                   = 
                   
                     
                       4 
                       π 
                     
                     ⁢ 
                     
                       V 
                       
                         DC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         α 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   7 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     
                       FC 
                       ⁢ 
                       
                           
                       
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                       2 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           n 
                           
                             2 
                             ⁢ 
                             
                                 
                             
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                           n 
                           
                             2 
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                             ⁢ 
                             S 
                           
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       4 
                       π 
                     
                     ⁢ 
                     
                       V 
                       
                         DC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         β 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   8 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     
                       FC 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                   = 
                   
                     
                       ( 
                       
                         
                           n 
                           
                             3 
                             ⁢ 
                             
                                 
                             
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                           n 
                           
                             3 
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                             S 
                           
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       4 
                       π 
                     
                     ⁢ 
                     
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                         DC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         3 
                       
                     
                     ⁢ 
                     
                       sin 
                       ⁡ 
                       
                         ( 
                         γ 
                         ) 
                       
                     
                   
                 
               
               
                 
                   ( 
                   9 
                   ) 
                 
               
             
           
         
       
     
     Based on these formulas (7) to (9), the following formulas (10) and (11) are obtained as understood in the art: 
     
       
         
           
             
               
                 
                   
                     V 
                     
                       FC 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   = 
                   
                     
                       
                         R 
                         
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                           2 
                         
                       
                       
                         
                           R 
                           
                             E 
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                             2 
                           
                         
                         + 
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                     
                     ⁢ 
                     
                       V 
                       
                         FC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   10 
                   ) 
                 
               
             
             
               
                 
                   
                     V 
                     
                       FC 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                   = 
                   
                     
                       
                         R 
                         
                           E 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                       
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         + 
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                     
                     ⁢ 
                     
                       V 
                       
                         FC 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                   
                 
               
               
                 
                   ( 
                   11 
                   ) 
                 
               
             
           
         
       
     
     Next, referring to  FIGS. 5 to 8 , the equivalent resistance of the second port  202  will be explained.  FIG. 5  illustrates a circuit structure of the second port  202 , while  FIG. 6  illustrates the AC equivalent circuit thereof. 
     In  FIG. 5 , i 2 (t) represents the current flows from the second switching circuit  102  to the second smoothing capacitor  5  and the second load resistance  6 .  FIG. 7  illustrates the waveform of i 2 (t), while  FIG. 8  illustrates the graph of the average current I AVE2  flowing through the second load resistance  6 . In  FIG. 7 , i 2 (t) is illustrated with a solid line, while i R (t) is illustrated with a dashed line. Hereinafter, for simplifying the explanation, the turns ratio of the second isolation transformer  21  is assumed to be 1. While the conduction angle of the second switching circuit  102  is β, i 2 (t) is equal to the current flowing through the series resonant circuit  1 . Since the voltage V DC2  applied to the second load resistance  6  is constant, the current I AVE2  flowing through the second load resistance  6  is also constant. Therefore, the following formula (12) is satisfied, as understood in the art, since the average of i 2 (t) is equal to I AVE2 : 
     
       
         
           
             
               
                 
                   
                     I 
                     
                       AVE 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       2 
                     
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               P 
                             
                           
                           
                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               S 
                             
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         1 
                         
                           ( 
                           
                             π 
                             2 
                           
                           ) 
                         
                       
                       ⁢ 
                       
                         I 
                         R 
                       
                       ⁢ 
                       
                         
                           ∫ 
                           
                             π 
                             2 
                           
                           
                             
                               π 
                               2 
                             
                             + 
                             φ 
                           
                         
                         ⁢ 
                         
                           sin 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           θ 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           d 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           θ 
                         
                       
                     
                     = 
                     
                       
                         ( 
                         
                           
                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               P 
                             
                           
                           
                             n 
                             
                               2 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               S 
                             
                           
                         
                         ) 
                       
                       ⁢ 
                       
                         2 
                         π 
                       
                       ⁢ 
                       
                         I 
                         R 
                       
                       ⁢ 
                       sin 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       β 
                     
                   
                 
               
               
                 
                   ( 
                   12 
                   ) 
                 
               
             
           
         
       
     
     Also, the current amplitude I R  is expressed by the following formula (13), as understood in the art: 
     
       
         
           
             
               
                 
                   
                     I 
                     R 
                   
                   = 
                   
                     
                       ( 
                       
                         
                           n 
                           
                             2 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             S 
                           
                         
                         
                           n 
                           
                             2 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             P 
                           
                         
                       
                       ) 
                     
                     ⁢ 
                     
                       π 
                       2 
                     
                     ⁢ 
                     
                       1 
                       
                         sin 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         β 
                       
                     
                     ⁢ 
                     
                       I 
                       
                         AVE 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         2 
                       
                     
                   
                 
               
               
                 
                   ( 
                   13 
                   ) 
                 
               
             
           
         
       
     
     Thus, the equivalent resistance R E2  is calculated based on the formulas (8) and (12) as shown in the following formula (14): 
     
       
         
           
             
               
                 
                   
                     
                       
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         = 
                           
                         ⁢ 
                         
                           
                             V 
                             
                               FC 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                           
                           
                             I 
                             R 
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             
                               ( 
                               
                                 
                                   n 
                                   
                                     2 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     P 
                                   
                                 
                                 
                                   n 
                                   
                                     2 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     S 
                                   
                                 
                               
                               ) 
                             
                             2 
                           
                           ⁢ 
                           
                             8 
                             
                               π 
                               2 
                             
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 sin 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 β 
                               
                               ) 
                             
                             2 
                           
                           ⁢ 
                           
                             
                               V 
                               
                                 DC 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                             
                               I 
                               
                                 AVE 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 2 
                               
                             
                           
                         
                       
                     
                   
                   
                     
                       
                         = 
                           
                         ⁢ 
                         
                           
                             
                               ( 
                               
                                 
                                   n 
                                   
                                     2 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     P 
                                   
                                 
                                 
                                   n 
                                   
                                     2 
                                     ⁢ 
                                     
                                         
                                     
                                     ⁢ 
                                     S 
                                   
                                 
                               
                               ) 
                             
                             2 
                           
                           ⁢ 
                           
                             8 
                             
                               π 
                               2 
                             
                           
                           ⁢ 
                           
                             
                               ( 
                               
                                 sin 
                                 ⁢ 
                                 
                                     
                                 
                                 ⁢ 
                                 β 
                               
                               ) 
                             
                             2 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   14 
                   ) 
                 
               
             
           
         
       
     
     Similarly, as understood in the art, the equivalent resistance R E3  of the third port  203  is also calculated as shown in the following formula (15): 
     
       
         
           
             
               
                 
                   
                     R 
                     
                       E 
                       ⁢ 
                       
                           
                       
                       ⁢ 
                       3 
                     
                   
                   = 
                   
                     
                       
                         ( 
                         
                           
                             n 
                             
                               3 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               P 
                             
                           
                           
                             n 
                             
                               S 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                           
                         
                         ) 
                       
                       2 
                     
                     ⁢ 
                     
                       8 
                       
                         π 
                         2 
                       
                     
                     ⁢ 
                     
                       
                         ( 
                         
                           sin 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           γ 
                         
                         ) 
                       
                       2 
                     
                     ⁢ 
                     
                       R 
                       3 
                     
                   
                 
               
               
                 
                   ( 
                   15 
                   ) 
                 
               
             
           
         
       
     
     The conduction angles β and γ are calculated as a function of a as shown in the following formulas (16) and (17), respectively, by substituting the formulas (7) to (9), (14) and (15) for the formulas (10) and (11): 
     
       
         
           
             
               
                 
                   
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     β 
                   
                   = 
                   
                     
                       
                         
                           R 
                           3 
                         
                         ⁢ 
                         
                           V 
                           
                             DC 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         ⁢ 
                         
                           V 
                           
                             DC 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       
                         
                           
                             V 
                             
                               DC 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                             2 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                         + 
                         
                           
                             V 
                             
                               DC 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             2 
                           
                           ⁢ 
                           
                             R 
                             3 
                           
                         
                       
                     
                     ⁢ 
                     
                       
                         n 
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           S 
                         
                       
                       
                         n 
                         
                           2 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           P 
                         
                       
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     α 
                   
                 
               
               
                 
                   ( 
                   16 
                   ) 
                 
               
             
             
               
                 
                   
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     γ 
                   
                   = 
                   
                     
                       
                         
                           R 
                           2 
                         
                         ⁢ 
                         
                           V 
                           
                             DC 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                         ⁢ 
                         
                           V 
                           
                             DC 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             1 
                           
                         
                       
                       
                         
                           
                             V 
                             
                               DC 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               3 
                             
                             2 
                           
                           ⁢ 
                           
                             R 
                             2 
                           
                         
                         + 
                         
                           
                             V 
                             
                               DC 
                               ⁢ 
                               
                                   
                               
                               ⁢ 
                               2 
                             
                             2 
                           
                           ⁢ 
                           
                             R 
                             3 
                           
                         
                       
                     
                     ⁢ 
                     
                       
                         n 
                         
                           3 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           S 
                         
                       
                       
                         n 
                         
                           3 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           P 
                         
                       
                     
                     ⁢ 
                     sin 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     α 
                   
                 
               
               
                 
                   ( 
                   17 
                   ) 
                 
               
             
           
         
       
     
     The current amplitude I R  is calculated by the following formula (18): 
     
       
         
           
             
               
                 
                   
                     I 
                     R 
                   
                   = 
                   
                     
                       V 
                       
                         R 
                         ⁢ 
                         
                             
                         
                         ⁢ 
                         1 
                       
                     
                     
                       
                         R 
                         
                           E 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           2 
                         
                       
                       + 
                       
                         R 
                         
                           E 
                           ⁢ 
                           
                               
                           
                           ⁢ 
                           3 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   18 
                   ) 
                 
               
             
           
         
       
     
     The Quality factor (Q factor) of the resonance circuit is calculated by the following formula (19): 
     
       
         
           
             
               
                 
                   Q 
                   = 
                   
                     
                       
                         2 
                         ⁢ 
                         
                           π 
                           · 
                           
                             f 
                             S 
                           
                         
                         ⁢ 
                         
                           L 
                           R 
                         
                       
                       
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             2 
                           
                         
                         + 
                         
                           R 
                           
                             E 
                             ⁢ 
                             
                                 
                             
                             ⁢ 
                             3 
                           
                         
                       
                     
                     = 
                     
                       1 
                       
                         
                           
                             ( 
                             
                               
                                 R 
                                 
                                   E 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   2 
                                 
                               
                               + 
                               
                                 R 
                                 
                                   E 
                                   ⁢ 
                                   
                                       
                                   
                                   ⁢ 
                                   3 
                                 
                               
                             
                             ) 
                           
                           · 
                           2 
                         
                         ⁢ 
                         
                           π 
                           · 
                           
                             f 
                             S 
                           
                         
                         ⁢ 
                         
                           C 
                           R 
                         
                       
                     
                   
                 
               
               
                 
                   ( 
                   19 
                   ) 
                 
               
             
           
         
       
     
     Generally, as long as the Q factor is high, the AC approximation is satisfied. 
     As understood from the formulas (16) and (17), sin(β) and sin(γ) is proportional to sin(α). Thus, if α is set to a value, then β and γ can be calculated based on the circuit parameters. 
                                                 TABLE 1                  V DC1  [V]   40   R 2  [Ω]   20   n 2P  [Turns]   1   f S  [Hz]   100,000       V DC2  [V]   40   R 3  [Ω]   5   n 2S  [Turns]   1   C R  [F]   5.00E−08       V DC3  [V]   10           n 3P  [Turns]   1   L R  [H]   5.07E−05                       n 3S  [Turns]   1                    
Table 1 above illustrates an example of the circuit parameters.
 
       FIG. 9  illustrates the graphs expressing sin(β) and sin(γ) as functions of sin(α). In  FIG. 9 , the relationship between sin(α) and sin(β) is illustrated with a gray solid line, while the relationship between sin(α) and sin(γ) is illustrated with a black dashed line. In other words, as understood in the art, as long as sin(β), sin(γ), and sin(α) satisfy the relationships shown in  FIG. 9 , the values of V DC2 , V DC3  are obtained as shown in Table 1. 
       FIGS. 10 to 14  illustrate graphs expressing the parameters as functions of the duty ratio of the first port  201 , respectively.  FIG. 10  illustrates a graph illustrating the relationships between the duty ratio of the first port  201  (Duty 1 ) and the equivalent resistances R E2  and R E3 . In  FIG. 10 , the relationship between Duty 1  and the equivalent resistance R E2  is illustrated with a gray solid line, while the relationship between Duty 1  and the equivalent resistance R E3  is illustrated with a black dashed line.  FIG. 11  illustrates graphs illustrating the relationships between the duty ratio of the first port  201  (Duty 1 ) and the duty ratios of the second and third ports  202  and  203  (Duty 2  and Duty 3 ). In  FIG. 11 , the relationship between Duty 1  and Duty 2  is illustrated with a gray solid line, while the relationship between Duty 1  and Duty 3  is illustrated with a black dashed line.  FIG. 12  illustrates a graph illustrating the relationship between the duty ratio of the first port  201  (Duty 1 ) and the peak voltage of the voltage v FC1 (t).  FIG. 13  illustrates a graph illustrating the relationship between the duty ratio of the first port  201  (Duty 1 ) and the peak resonant current of the current I R .  FIG. 14  illustrates a graph illustrating the relationship between the duty ratio of the first port  201  (Duty 1 ) and the Q factor. 
     The duty ratios of the first, second and third ports  201 ,  202  and  203  correspond to the conduction angles, respectively, as shown in the following formulas (20) to (22), as understood in the art: 
     
       
         
           
             
               
                 
                   
                     Duty 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     1 
                   
                   = 
                   
                     α 
                     
                       π 
                       / 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   20 
                   ) 
                 
               
             
             
               
                 
                   
                     Duty 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     2 
                   
                   = 
                   
                     β 
                     
                       π 
                       / 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   21 
                   ) 
                 
               
             
             
               
                 
                   
                     Duty 
                     ⁢ 
                     
                         
                     
                     ⁢ 
                     3 
                   
                   = 
                   
                     γ 
                     
                       π 
                       / 
                       2 
                     
                   
                 
               
               
                 
                   ( 
                   22 
                   ) 
                 
               
             
           
         
       
     
     As shown in  FIG. 13 , the amplitude of the resonant current I R  decreases as Duty 1  increases. The lower the amplitude of the resonant current I R  becomes, the lower the conduction loss of the transformer wirings or the semiconductor device become. Thus, from the point of view of the conduction loss, it is preferable for Duty 1  to be high. On the other hand, the Q factor decreases as Duty 1  becomes higher. 
     With this power convertor  100 , the Q factor can be kept equal to or more than 1 by setting the impedance at the switching frequency of the series resonant circuit  1  to be higher than the total effective load resistance value, thereby the AC approximation used in the above-mentioned analysis being satisfied. As a result, the output voltages are obtained as desired. 
     With the power convertor  100 , the controller  110  controls the first, second and third switching circuits  101 ,  102  and  103 , respectively, to obtain the desired output voltages. In particular, in the illustrated embodiment, the calculation unit  112  of the controller  110  calculates the resistance values R 2  and R 3  (e.g., the load resistance values) of the second and third load resistances  6  and  8  based on the applied voltages V DC2  and V DC3  to the second and third load resistances  6  and  8  and the average currents I AVE2  and I AVE3  to the second and third load resistances  6  and  8 , respectively, as understood in the art. More specifically, the calculation unit  112  calculates the resistance value R 2  by dividing the applied voltage V DC2  by the average current I AVE2 , and calculates the resistance value R 3  by dividing the applied voltage V DC3  by the average current I AVE3 . Here, the applied voltages V DC2  and V DC3  are detected by voltage sensors (not shown) that are configured and arranged to detect the applied voltages to the second and third load resistances  6  and  8 , respectively, while the average currents I AVE2  and I AVE3  are detected by current sensors (not shown) that are configured and arranged to detect the average currents flowing through the second and third load resistances  6  and  8 , respectively. 
     Then, the control unit  114  of the controller  110  determines the duty ratios of the first, second and third switching circuits  101 ,  102  and  103  based on the load resistance values R 2  and R 3 , the target power source voltage value V DC1  and the target voltage values V DC2  and V DC3  to the second and third load resistances  6  and  8 , as understood in the art. In the illustrated embodiment, the target power source voltage value V DC1  and the target voltage values V DC2  and V DC3  are preset or pre-stored to the control unit  114  of the controller  110 , while the load resistance values R 2  and R 3  are calculated by the calculation unit  112  of the controller  110 . More specifically, in the illustrated embodiment, as shown in Table 1 above, the target power source voltage value V DC1  and the target voltage values V DC2  and V DC3  are preset to 40[V], 40[V], and 10[V], respectively. 
     As understood in the art, the formula (19) can be transformed to express the relationship between the Q factor and the conduction angle α using the formulas (14) to (17). In particular, by substituting the target power source voltage value V DC1 , the target voltage values V DC2  and V DC3 , and the load resistance values R 2  and R 3  for the formulas (16) and (17), the relation between sin(α) and sin(β) and the relation between sin(α) and sin(γ) can be obtained. In other words, using the formulas (16) and (17), sin(β) and sin(γ) can be expressed as functions of sin(α), respectively. Furthermore, as understood in the art, by substituting sin(β) and sin(γ) that have been obtained as functions of sin(α) and the load resistance values R 2  and R 3  that have been calculated by the calculation unit  112  for the formulas (14) and (15), the effective load resistance values R E2  and R E3  can be calculated as functions of sin(α). Then, by substituting the effective load resistance values R E2  and R E3  that have been calculated and the circuit parameters fs and C R  that have been preset or pre-stored for the formula (19), the relation between the Q factor and the conduction angle α can be obtained. In the illustrated embodiment, as shown in Table 1 above, the circuit parameters fs and C R  are preset to 100,000 [Hz] and 5.00E-08[F], respectively. 
     As mentioned above, it is preferable for the Q factor to be kept enough high. For example, to well satisfy the AC approximation used in the above-mentioned analysis, the characteristic impedance is set to be higher than the total effective load resistance value, and in this case, the Q factor need to be equal to or more than 1. In other words, in the illustrated embodiment, the Q factor is set to be equal to or more than 1. In the illustrated embodiment, the Q factor is set to 4.134, for example, as described below. Once the Q factor is determined, the conduction angle α can be obtained from the above-mentioned relation between the Q factor and the conduction angle α, as understood in the art. Also, once the conduction angle α is obtained, the conduction angles β and γ can be obtained from the above-mentioned relations between sin(α) and sin(β) and between sin(α) and sin(γ) using the formulas (16) and (17), for example. 
     Then, the control unit  114  of the controller  110  determines the duty ratios Duty 1 , Duty 2  and Duty 3  of the first, second and third switching circuits  101 ,  102  and  103  based on the calculation results of the conduction angles α, β and γ. In particular, the control unit  114  calculates the duty ratios Duty 1 , Duty 2  and Duty 3  according to the formulas (20), (21) and (22), respectively. Then, the control unit  116  controls the switching elements of the first, second and third switching circuits  101 ,  102  and  103 , respectively, using the phase shifted PWM, such that the duty ratios Duty 1 , Duty 2  and Duty 3  can be obtained at the first, second and third ports  201 ,  202  and  203 , respectively. The phase shifted PWM for the switching elements are well known in the art. Thus, the detailed descriptions will be omitted for the sake of brevity. 
     In the illustrated embodiment, the calculations performed by the calculation unit  112  and the control unit  114  of the controller  110  are described step-by-step. However, of course, the plurality steps of calculations can be performed as a single step of calculation. For example, in the illustrated embodiment, the duty ratios Duty 1 , Duty 2  and Duty 3  are ultimately obtained as functions of the applied voltages V DC2  and V DC3  detected by the voltage sensors and the average currents I AVE2  and I AVE3  detected by the current sensors when the target voltage values V DC1 , V DC2  and V DC3 , the target value of the Q factor, and the circuit parameters, such as n 2P , n 2S , n 3P , n 3S , fs and C R , are given. Thus, the controller  110  can also calculate the duty ratios Duty 1 , Duty 2  and Duty  3  in response to obtaining the applied voltages V DC2  and V DC3  from the voltage sensors and the average currents I AVE2  and I AVE3  from the current sensors. Also, the above-mentioned calculations explained as using the preset target values, such as the target voltage values V DC1 , V DC2  and V DC3 , and the target value of the Q factor can be performed by using the values detected by sensors or the values calculated in a manner well known in the art, as needed and/or desired. Similarly, the above-mentioned calculations explained as using the values detected by sensors can be performed by using the preset target values, as needed and/or desired. 
     Next, the simulation results of the above-mentioned operations of the power converter  100  will be explained. 
       FIG. 15  illustrates the circuit diagram used in the simulation. The circuit diagram shown in  FIG. 15  basically has an identical topology as the circuit diagram shown in  FIG. 1  in regards to the main components. Additional components or terminals in  FIG. 15  are shown for the purposes of simulation. However, as understood in the art, the circuits shown by the circuit diagrams shown in  FIGS. 1 and 15  are basically identically operated. Specifically, switches sw 01  to sw 04  and diodes D 01  to D 04  shown in  FIG. 15  correspond to the switching elements of the first switching circuit  101  shown in  FIG. 1 , switches sw 05  to sw 08  and diodes D 05  to D 08  shown in  FIG. 15  correspond to the switching elements of the second switching circuit  102 , and switches sw 09  to sw 12  and diodes D 09  to D 12  shown in  FIG. 15  correspond to the switching elements of the third switching circuit  103 . 
     With this simulation, the circuit parameters shown in Table 1 are also used. Furthermore, with this simulation, the duty ratios and the Q factor shown in Table 2 below are used. 
     
       
         
           
               
               
               
             
               
                   
                 TABLE 2 
               
               
                   
                   
               
             
            
               
                   
                 Duty1 
                 0.560 
               
               
                   
                 Duty2 
                 0.423 
               
               
                   
                 Duty3 
                 0.423 
               
               
                   
                 Q 
                 4.134 
               
               
                   
                   
               
            
           
         
       
     
       FIG. 16  illustrates the waveforms of v SQ1 (t), v SQ2 (t), and v SQ3 (t). The waveforms of v SQ1 (t), v SQ2 (t), and v SQ3 (t) has the peak voltages V DC1 , V DC2 , and V DC3 , respectively, and has the duty ratios shown in Table 2. 
       FIG. 17  illustrates the waveforms of i R (t), i 1 (t), i 2 (t), and i 3 (t). With this simulation, since the Q factor is set to be a high value of 4.134 as shown in Table 2, i R (t) is a sin wave. 
       FIG. 18  illustrates the waveforms of the output voltages V DC2  and V DC3  of the second and third ports  202  and  203 , respectively. The average output voltage values are 39.6V and 9.97V, respectively, which are substantially equal to the target voltages 40V and 10V shown in Table 1, respectively. Thus, with this power convertor  100 , the desired output voltages at the second and third ports  202  and  203  can be obtained. 
     In the illustrated embodiment, the power converter  100  includes the first, second and third switching circuits  101 ,  102  and  103  (e.g., at least three switching circuits), the first power source  4  (e.g., at least one power source), the second and third load resistances  6  and  8  (e.g., at least one load), and the series resonant circuit  1  (e.g., a resonant circuit). The input terminals of the first, second and third switching circuits  101 ,  102  and  103  are connected to either the first power source  4  (e.g., the at least one power source) or the second and third load resistances  6  and  8  (e.g., the at least one load). The output terminals  301 ,  302  and  303  of the first, second and third switching circuits  101 ,  102  and  103  are electrically serially connected to the series resonant circuit  1  to form a closed circuit. 
     With this power converter  100 , the power between a plurality of ports  201 ,  202  and  203  can be controlled as desired. Thus, it is possible to provide a power converter with which the number of parts can be reduced and the size and the cost thereof can be reduced. 
     In the illustrated embodiment, with the power converter  100 , the sum of the fundamental component of voltage waveform v FC1 (t) generated by the first switching circuit (e.g., a set of the switching circuits) that is connected to the first power source  4  (e.g., the at least one power source) is substantially equal to the sum of the fundamental components of voltage waveforms V FC2 (t), and v FC3 (t) applied to the second and third switching circuits  102  and  103  (e.g., a set of the switching circuits) that are connected to the second and third load resistances  6  and  8  (e.g., the at least one load). 
     With this power converter  100 , the power between a plurality of ports  201 ,  202  and  203  can be controlled as desired by making the sum of the fundamental component of the at least one power source selectively filtered by the series resonant circuit  1  to be equal to the sum of fundamental component of the at least one load. 
     In the illustrated embodiment, with the power converter  100 , the frequencies f S  of the voltage waveforms v FC1 (t), V FC2 (t), and v FC3 (t) are substantially equal to the resonant frequency f R  of the series resonant circuit  1 . 
     With this power converter  100 , the fundamental component can be selectively obtained by making the frequencies f S  of the voltage waveforms v FC1 (t), V FC2 (t), and v FC3 (t) to be near the resonant frequency f R  of the series resonant circuit  1 . 
     In the illustrated embodiment, with the power converter  100 , the phases of the voltage waveforms v SQ1 (t), v SQ2 (t), and v SQ3 (t) are substantially equal to each other. 
     With this power converter  100 , the sum of the fundamental component v FC1 (t) of the first power source (e.g., the at least one power source) and the sum of the fundamental components V FC2 (t), and v FC3 (t) of the second and third load resistances  6  and  8  (e.g., the at least one load) can be made equal to each other by making the voltage waveforms v SQ1 (t), v SQ2 (t), and v SQ3 (t) to be the same phase. 
     In the illustrated embodiment, with the power converter  100 , the output terminals of the second and third switching circuits  102  and  103  are serially connected to the closed circuit via the second and third isolation transformers  21  and  22 . 
     With this power converter  100 , a desired output terminal can be electrically isolated from the other output terminal by connecting the desired output terminal via the isolation transformer. 
     In the illustrated embodiment, with the power converter  100 , the characteristic impedance of the resonant circuit is higher than the total effective load resistance value serially connected to the closed circuit. 
     With the power converter according to the sixth aspect, the fundamental component of the voltage waveform can be effectively filtered by the resonant circuit by making the characteristic impedance of the series resonant circuit  1  to be higher than the total effective load resistance value R E2  and R E3 . 
     In the illustrated embodiment, with the power converter  100 , the first, second and third switching circuits  101 ,  102  and  103  (e.g., at least one of the switching circuits) include a full bridge circuit. 
     In the illustrated embodiment, the power converter  100  includes the calculation unit  112  configured to calculate the load resistance values R 2  and R 3  based on the applied voltages V DC2  and V DC3  to the second and third load resistances  6  and  8  (e.g., the at least one load) and the average currents I AVE2  and I AVE3  to the second and third load resistances  6  and  8  (e.g., the at least one load), and the control unit  114  configured to determine the duty ratios Duty 1 , Duty 2  and Duty 3  of the first, second and third switching circuits  101 ,  102  and  103  based on the load resistance values R 2  and R 3  (e.g., the load resistance value), the target power source voltage value V DC1  (e.g., the power source voltage value) and the target voltage values V DC2  and V DC3  (e.g., the target voltage values) to the second and third load resistances  6  and  8  (e.g., the at least one load). 
     With this power converter  100 , the power between a plurality of ports  201 ,  202  and  203  can be controlled as desired. 
     Second Embodiment 
       FIG. 19  is a circuit diagram illustrating a circuit structure of a power convertor  100  in accordance with the second embodiment. The power convertor  100  illustrated in  FIG. 19  is basically identical to the power convertor  100  illustrated in  FIG. 1 , except that a second power source  9  is connected to the second port  202  instead of the second load resistance  6  illustrated in  FIG. 1 . 
     More specifically, with the power convertor  100  in accordance with the first embodiment, two loads are connected to a single power source. On the other hand, with the power convertor  100  in accordance with the second embodiment, a single load is connected to two power sources. In other words, the power convertor  100  forms a DC-DC convertor with the first and second power sources  4  and  9  as multiple (a pair of) inputs and the third load resistance  8  as a single output. 
     With this power convertor  100  in accordance with the second embodiment, as shown in  FIG. 19 , even if two power sources are provided, the power convertor  100  can be operated in the similar manner as explained in the first embodiment, as understood in the art. 
     Third Embodiment 
       FIG. 20  is a circuit diagram illustrating a circuit structure of a power convertor  100  in accordance with the third embodiment. The power convertor  100  illustrated in  FIG. 20  is basically identical to the power convertor  100  illustrated in  FIG. 2 , except that a first isolation transformer  23  is inserted at a location where the first port  201  is connected to the series resonant circuit  1 . 
     More specifically, as shown in  FIG. 20 , the numbers of turns of the first isolation transformer  23  are n 1P  and n 1S , and the first port  201  is electrically isolated from the closed circuit. With this configuration, each of the first, second and third ports  201 ,  202  and  203  can be isolated from the series resonant circuit  1 , as understood in the art. Also, the power convertor  100  can be operated in the similar manner as explained in the first embodiment, as understood in the art, by taking the numbers of turns of the first isolation transformer  23  into account. 
     Fourth Embodiment 
       FIG. 21  is a circuit diagram illustrating a circuit structure of a power convertor  100  in accordance with the fourth embodiment. The power convertor  100  illustrated in  FIG. 21  is basically identical to the power convertor  100  illustrated in  FIG. 1 , except that more than three ports (N ports: N is more than three)  201 ,  202 ,  203 , . . . , and  204  are provided to the power convertor  100 . 
     Specifically, in the illustrated embodiment, an N-th port  204  includes an N-th switching circuit  104 , an N-th smoothing capacitor  10  and an N-th load resistance  11  with the load resistance value R N . In other words, in the illustrated embodiment, the power convertor  100  forms a DC-DC convertor with the first power source  4  as a single input and the second, third, . . . , and N-th load resistances  6 ,  8 , . . . , and  11  as multiple (N−1) outputs. 
     As shown in  FIG. 21 , even if the number of ports is more than three ports that are illustrated in  FIG. 1 , the power convertor  100  illustrated in  FIG. 21  can be operated in the similar manner as explained in the first embodiment, as understood in the art. 
     In the illustrated embodiment, the multiple ports  201 ,  202 ,  203 , . . . , and  204  of the power converter  100  has a single power source  4 . However, of course, the multiple ports  201 ,  202 ,  203 , . . . , and  204  can includes a plurality of power sources, as needed and/or desired. 
     Fifth Embodiment 
       FIG. 22  is a circuit diagram illustrating a circuit structure of a power convertor  100  in accordance with the fifth embodiment. The power convertor  100  illustrated in  FIG. 22  is basically identical to the power convertor  100  illustrated in  FIG. 2 . With the power convertor  100  illustrated in  FIG. 22 , the third port  203  is idled by making the power exchange at the third port  203  to be zero. 
     With the conventional converter such as illustrated in Non-Patent Literature 2, a complex control is required to make the power exchange at a desired port to be zero. Thus, the loss due to the switching loss or the conduction loss at the switching circuit of the idled port is generated, which decreases the energy efficiency. On the other hand, with the power convertor  100  illustrated in  FIG. 22 , the current flowing through the third load resistance  8  is made zero by turning on the pair of switching elements on the lower arm of the third switching circuit  103  and turning off the pair of switching elements on the upper arm of the third switching circuit  103 . This is because, as shown in the AC equivalent circuit of the power convertor  100  in  FIG. 23 , the ports  201 ,  202  and  203  are equivalently connected in series, and thus the third port  203  can equivalently shorted. On the other hand, with the multi-port converter having a plurality of wirings relative to a single isolation transformer, as illustrated in Non-Patent Literature 2, if the output terminal of the full bridge circuit is shorted similar to the present application, the voltage applied to the wirings of the isolation transformer becomes zero, which prevents the power exchange at the other ports. On the other hand, with the present application, the power exchange at the desired port (e.g., the third port  203  in  FIG. 22 ) can be easily made zero by keep turning on either the switching elements on the upper arm or the switching elements on the lower arm, and the switching loss of the switching elements or switching circuit can be decreased. Thus, it is possible to provide a high efficiency circuit. 
       FIG. 24  is a circuit diagram illustrating a circuit structure of a power convertor  100  in accordance with a modified example of the fifth embodiment. The power convertor  100  illustrated in  FIG. 24  is basically identical to the power convertor  100  illustrated in  FIG. 22 . With the power converter  100  illustrated in  FIG. 24 , the pair of switching elements on the upper arm is turned on. Generally, the switching loss at the switching elements that have been turned on is zero, but the conduction loss is generated, which generates the heat. To prevent only one of the upper arm and the lower arms from being heated up, the state in which the lower arm is turned on and the state in which the upper arm is turned on are alternately switched for a predetermined interval. This disperses the generated heat, and lowers the required current rating of the switching elements. Thus, it is possible to provide a low-cost circuit. 
     In the illustrated embodiment, an example in which the output terminal of the third switching circuit  103  is electrically shorted has been explained. Of course, the output terminal of the second switching circuit  102  can also be electrically shorted in the same manner as explained above. 
     In the illustrated embodiment, with the power converter  100 , the output terminal of third switching circuit  103  (e.g., at least one of the output terminals of the switching circuits) is electrically shorted via the switching elements of the upper arm or the switching elements of the lower arm in the third switching circuit  103 . 
     With this power converter  100 , the output terminal of the third switching circuit  103  is electrically shorted via the switching elements of the upper arm or the switching elements of the lower arm in the third switching circuit  103 . Thus, the power input to the shorted output terminal and the power output from the shorted output terminal can be zero, thereby decreasing the loss at the switching element of the third switching circuit  103 . 
     In the illustrated embodiment, with power converter  100 , the output terminal of third switching circuit  103  (e.g., at least one of the output terminals of the switching circuits) is electrically shorted alternately via the switching elements of the upper arm and the switching elements of the lower arm in the third switching circuit  103 . 
     With this power converter  100 , the output terminal of third switching circuit  103  (e.g., at least one of the output terminals of the switching circuits) is electrically shorted alternately via the switching elements of the upper arm and the switching elements of the lower arm in the third switching circuit  103 . Thus, the excessive temperature increase at the switching elements used for the short circuit can be prevented. 
     In the illustrated embodiment, with the power converter  100 , the first, second and third switching circuits  101 ,  102  and  103  (e.g., at least one of the switching circuits) include a full bridge circuit. 
     With this power converter  100 , the output terminal of the third switching circuit  103  can be easily electrically shorted by making the third switching circuit  103  include the full bridge circuit. 
     GENERAL INTERPRETATION OF TERMS 
     In understanding the scope of the present invention, the term “comprising” and its derivatives, as used herein, are intended to be open ended terms that specify the presence of the stated features, elements, components, groups, integers, and/or steps, but do not exclude the presence of other unstated features, elements, components, groups, integers and/or steps. The foregoing also applies to words having similar meanings such as the terms, “including”, “having” and their derivatives. Also, the terms “part,” “section,” “portion,” “member” or “element” when used in the singular can have the dual meaning of a single part or a plurality of parts. The terms of degree such as “substantially”, “about” and “approximately” as used herein mean a reasonable amount of deviation of the modified term such that the end result is not significantly changed. 
     It will be understood that, although the terms “first”, “second”, etc. may be used herein to describe various elements, components, regions, layers, positions and/or sections, these elements, components, regions, layers, positions and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, position or section from another element, component, region, layer, position or section. Thus, a first element, component, region, layer, position or section discussed above could be termed a second element, component, region, layer, position or section without departing from the teachings of illustrative embodiments. 
     While only selected embodiments have been chosen to illustrate the present invention, it will be apparent to those skilled in the art from this disclosure that various changes and modifications can be made herein without departing from the scope of the invention as defined in the appended claims. For example, the size, shape, location or orientation of the various components can be changed as needed and/or desired. Components that are shown directly connected or contacting each other can have intermediate structures disposed between them. The functions of one element can be performed by two, and vice versa. The structures and functions of one embodiment can be adopted in another embodiment. It is not necessary for all advantages to be present in a particular embodiment at the same time. Every feature which is unique from the prior art, alone or in combination with other features, also should be considered a separate description of further inventions by the applicant, including the structural and/or functional concepts embodied by such features. Thus, the foregoing descriptions of the embodiments according to the present invention are provided for illustration only, and not for the purpose of limiting the invention as defined by the appended claims and their equivalents.