Patent Publication Number: US-8526262-B2

Title: Multi-channel semiconductor integrated circuit devices for controlling direct current generators and memory systems including the same

Description:
CLAIM OF PRIORITY 
     This application claims priority to Korean Patent Application No. 10-2009-0091170, filed Sep. 25, 2009, the disclosure of which is hereby incorporated herein by reference as if set forth in its entirety. 
     FIELD 
     The present inventive concept is directed to semiconductor integrated circuit devices, and more particularly, to multi-channel semiconductor integrated circuit devices including a plurality of memory devices that are independently accessible and related memory systems. 
     BACKGROUND 
     A multi-channel semiconductor integrated circuit device including at least one memory device may be independently operated for each memory device. In other words, for each channel, direct current consumption is relatively large, compared to that of a semiconductor integrated circuit device having the same density. Thus, a direct current power generator and a node are shared in order to reduce the direct current consumption. 
     However, in the multi-channel semiconductor integrated circuit device independently operating for each channel, active (ACT) timing may be irregular in each channel and the deviation in the amount of consumption of charge is relatively large. Accordingly, it is difficult to anticipate a direct current voltage level to be generated. Furthermore, in the multi-channel semiconductor integrated circuit device independently operating for each channel, during standby (STBY) operation, standby voltages ripple and standby currents increase, compared to the semiconductor integrated circuit device having the same density. 
     SUMMARY 
     Some embodiments of the inventive concept provide a multi-channel semiconductor integrated circuit (IC) device independently operating for each channel which may integrally and efficiently control generation of power, and a memory system including the multi-channel semiconductor integrated circuit device. 
     According to further embodiments of the inventive concept, there is provided a multi-channel semiconductor integrated circuit device including a plurality of memory devices, a detection unit, and a common control unit. The plurality of memory devices are independently accessible and each of the plurality of memory devices includes at least one power generation unit and a control unit for controlling an operation of the at least one power generation unit. The detection unit detects an operation state of the plurality of memory devices. The common control unit commonly controls an operation of the at least one power generation unit of the plurality of memory devices, according to the operation state of the plurality of memory devices detected by the detection unit. 
     In the multi-channel semiconductor integrated circuit device, the control unit of each of the plurality of memory devices controls the operation of the at least one power generation unit of a corresponding one of the plurality of memory devices. 
     According to still further aspects of the inventive concept, there is provided a multi-channel semiconductor integrated circuit device including a plurality of memory devices and a detection unit. 
     The plurality of memory devices is independently accessible and each of the plurality of memory devices includes at least one power generation unit. The detection unit detects an operation state of the plurality of memory devices. In the multi-channel semiconductor integrated circuit device, the at least one power generation unit of the plurality of memory devices is independently controlled for each of the plurality of memory devices or commonly controlled for the plurality of memory devices, according to a control mode determined by the operation state of the plurality of memory devices detected by the detection unit. 
     According to some embodiments of the inventive concept, there is provided a memory system including the multi-channel semiconductor integrated circuit device, a controller for controlling the multi-channel semiconductor integrated circuit device, and a plurality of channels, each independently interfacing a corresponding one of the plurality of memory devices and the controller. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  schematically illustrates the structure of a multi-channel semiconductor integrated circuit device according some embodiments of the present inventive concept. 
         FIG. 2A  is a block diagram illustrating an operational structure according to some embodiments of the present inventive concept. 
         FIG. 2B  is a block diagram illustrating an operational structure according to some embodiments of the present inventive concept. 
         FIG. 3A  is a flowchart illustrating operations according to some embodiments illustrated in  FIG. 2A . 
         FIG. 3B  is a flowchart illustrating operations according to some embodiments illustrated in  FIG. 2B . 
         FIGS. 4A through 4D  illustrate operation states of multi-channel semiconductor integrated circuit devices according to some embodiments illustrated in  FIG. 2A . 
         FIGS. 5A through 5D  illustrate operation states of multi-channel semiconductor integrated circuit devices according to some embodiments illustrated in  FIG. 2B . 
         FIGS. 6A through 6C  are graphs illustrating a supply current of the power generation unit for each of the operation states of the multi-channel semiconductor integrated circuit devices according to some embodiments in  FIG. 2A . 
         FIG. 7  is a block diagram schematically illustrating the structure of a system including multi-channel semiconductor integrated circuit devices according to some embodiments of the present inventive concept. 
     
    
    
     DETAILED DESCRIPTION OF EMBODIMENTS 
     The inventive concept now will be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. 
     It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items and may be abbreviated as “/”. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first signal could be termed a second signal, and, similarly, a second signal could be termed a first signal without departing from the teachings of the disclosure. 
     The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof. 
     Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. 
     Referring first to  FIG. 1 , a schematic illustration of the structure of multi-channel semiconductor integrated circuit device  100  according to some embodiments of the present inventive concept will be discussed. As illustrated in  FIG. 1 , the multi-channel semiconductor integrated circuit device  100  according to the some embodiments includes a plurality of, for example, four, memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 , a detection unit  500 , and a common control unit  600 . The multi-channel semiconductor integrated circuit device  100  may be an integrated circuit device in which the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are integrated in a single chip. Each of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  separately includes a command and data input/output unit (not shown) so as to be independently accessible. 
     The memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 , respectively, include a plurality of power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4 , control units  300   a ,  300   b ,  300   c , and  300   d , and bank blocks  400   a ,  400   b ,  400   c , and  400   d . Each of the bank blocks  400   a ,  400   b ,  400   c , and  400   d  may include a memory array (not shown) and a circuit to read/write data with respect to the memory array. 
     The power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  supply internal power, for example, direct current voltage and/or direct current, which is needed for the operation of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     Furthermore, the control units  300   a ,  300   b ,  300   c , and  300   d  control the operation of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  according to the internal voltage of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     The detection unit  500  detects the operation states of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . For example, the detection unit  500  may detect whether each operation state of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  is in an active operation state or a standby operation state. 
     The common control unit  600  determines a control mode according to the operation state of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  detected by the detection unit  500 . The control mode includes an individual control mode and a common control mode. 
     For example, when all of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are in the standby operation state, the common control mode may be determined by the common control unit  600 . In these embodiments, the common control unit  600  may control the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  for the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 , and also control the number and/or operation order of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4 . 
     In particular, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, the common control unit  600  may operate only some of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     Furthermore, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, the common control unit  600  may operate only one, for example, the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1 , of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     The common control unit  600  controls the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1 , to be sequentially operated one by one, so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     For example, the power generation unit  200   a   1  of MBL 1  is first operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the power generation unit  200   b   1  of MBL 2  is operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the power generation unit  200   c   1  of MBL 3  is operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the power generation unit  200   d   1  of MBL 4  is first operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     Furthermore, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, each of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  may further include standby power generation units  700   a ,  700   b ,  700   c , and  700   d  for supplying power to the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     When the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the active operation state, the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  may be active power generation units that supply power to the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     In these embodiments, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  respectively supply power to the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     When the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state which is detected by the detection unit  500 , the common control unit  600  may control the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  and adjust the number of the operating standby power generation units  700   a ,  700   b ,  700   c , and  700   d.    
     In particular, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, the common control unit  600  operates some of the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 , thereby operating the multi-channel semiconductor integrated circuit device  100 . 
     Furthermore, when the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state, the common control unit  600  operates only one of the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 , thereby operating the multi-channel semiconductor integrated circuit device  100 . 
     The common control unit  600  controls the standby power generation units  700   a ,  700   b ,  700   c , and  700   d , to be sequentially operated one by one, so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     For example, the standby power generation unit  700   a  of MBL 1  is first operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the standby power generation unit  700   b  of MBL 2  is operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the standby power generation unit  700   c  of MBL 3  is operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. Next, the standby power generation unit  700   d  of MBL 4  is first operated so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     Referring now to  FIG. 2A , a block diagram illustrating details of multi-channel semiconductor integrated circuit device  100  according to some embodiments of the present inventive concept will be discussed. As illustrated in  FIG. 2A , the detection unit  500  detects the operation state of the multi-channel semiconductor integrated circuit device  100 . 
     When any one of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  is determined to be in the active operation state, each of the four control units  300  controls the power generation unit  200  for each of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . When all of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are determined to be in the standby operation state, the common control unit  600  commonly controls the power generation unit  200  of each of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     Referring now to  FIG. 2B , a block diagram illustrating details of multi-channel semiconductor integrated circuit device  100  according to some embodiments of the present inventive concept. A illustrated in  FIG. 2B , the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  further include a standby power generation unit  700  that supplies power to the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  when the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are in the standby operation state. 
     As illustrated in  FIG. 2B , the detection unit  500  detects the operation state of the multi-channel semiconductor integrated circuit device  100 . When any one of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  is determined to be in the active operation state, each control unit  300  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  controls the power generation unit  200  and the standby power generation unit  700  of each of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . When all of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are determined to be in the standby operation state, the common control unit  600  commonly controls the four standby power generation units  700  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     Referring now to  FIG. 3A , a flowchart illustrating operations according to some embodiments illustrated in  FIG. 2A  will be discussed. As illustrated in  FIG. 3A , the detection unit  500  determines whether the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state. When the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all determined to be in the standby operation state, the common control unit  600  controls all power generation units  200  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  (S 200 ). When any one of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  is determined to be in the active operation state, the control unit  300  controls all power generation units  200  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  (S 300 ). 
     Referring now to  FIG. 3B , a flowchart illustrating operations according to some embodiments illustrated in  FIG. 2B  will be discussed. As illustrated in  FIG. 3B , the detection unit  500  determines whether the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all in the standby operation state. When the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are all determined to be in the standby operation state, the common control unit  600  controls the four standby power generation units  700  (S 20 ). 
     When any one of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  is determined to be in the active operation state, the control unit  300  controls the power generation unit  200  and the standby power generation unit  700  of each of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  (S 30 ). 
     Referring now to  FIG. 4A through 4D , operation states of the multi-channel semiconductor integrated circuit device  100  according to  FIG. 2A  will be discussed. As illustrated in  FIG. 4A , the operation state of the multi-channel semiconductor integrated circuit device  100  in which MBL 1  is in the active operation state and MBL 2 -MBL 4  are in the standby operation state. As illustrated in  FIG. 4B , the operation state of the multi-channel semiconductor integrated circuit device  100  in which MBL 1  and MBL 4  are in the active operation state and MBL 2  and MBL 3  are in the standby operation state. 
     As illustrated in  FIG. 4C , the multi-channel semiconductor integrated circuit device  100  is shown in which MBL 1 -MBL 4  are all in the active operation state. As further illustrated in  FIG. 4D , the multi-channel semiconductor integrated circuit device  100  is shown in which MBL 1 -MBL 4  are all in the standby operation state. 
     In  FIGS. 4A-4C , the control units  300   a ,  300   b ,  300   c , and  300   d  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  control the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     In  FIG. 4D , the common control unit  600  controls the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . In  FIG. 4D , the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  are sequentially operated, for example, in order of the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1 , so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     Referring now to  FIGS. 5A-5D , the operation states of the multi-channel semiconductor integrated circuit device  100  according to  FIG. 2B  will be discussed. As illustrated in  FIG. 5A , the multi-channel semiconductor integrated circuit device  100  is shown in which MBL 1  is in the active operation state and MBL 2 -MBL 4  are in the standby operation state. As illustrated in  FIG. 5B , the multi-channel semiconductor integrated circuit device  100  is shown in which MBL 1  and MBL 4  are in the active operation state and MBL 2  and MBL 3  are in the standby operation state. 
     In  FIG. 5C , the operation state of the multi-channel semiconductor integrated circuit device  100  in which MBL 1 -MBL 4  are all in the active operation state. In  FIG. 5D , the operation state of the multi-channel semiconductor integrated circuit device  100  in which MBL 1 -MBL 4  are all in the standby operation state. 
     In  FIGS. 5A-5C , the control units  300   a ,  300   b ,  300   c , and  300   d  of the four memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4  control the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  and the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . 
     In  FIG. 5D , the common control unit  600  controls the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 4 . In  FIG. 5D , the standby power generation units  700   a ,  700   b ,  700   c , and  700   d  of the memory devices MBL 1 , MBL 2 , MBL 3 , and MBL 5  are sequentially operated, for example, in order of the standby power generation units  700   a ,  700   b ,  700   c , and  700   d , so that the multi-channel semiconductor integrated circuit device  100  may be operated. 
     The power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  supply current for the internally required voltage according to the operation state of the multi-channel semiconductor integrated circuit device  100 . 
     Referring now to  FIGS. 6A-6C , graphs showing supply current of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  for each of the operation states of the multi-channel semiconductor integrated circuit device  100  according to  FIG. 2A  will be discussed. In  FIGS. 6A-6C , the horizontal axis denotes time and the vertical axis denotes supply current. 
     In the current graphs of MBL 1 , MBL 2 , MBL 3 , and MBL 4  of  FIGS. 6A-6C , the fourth graph corresponds to a graph of the current supplied by the power generation unit  200   a   1  of  FIG. 1 . Also, the first to third graphs correspond to graphs of the current supplied by the power generation units  200   b   1 ,  200   c   1 , and  200   d   1 . 
     Referring to  FIG. 6A , in the operation state of the multi-channel semiconductor integrated circuit device  100 , MBL 1  is in the active operation state and MBL 2 -MBL 4  are in the standby operation state. In MBL 1 , the current needed in the active state is supplied by the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4  of MBL 1 . Since the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4  of MBL 1  sequentially supply the current needed in the active operation state, as illustrated in  FIG. 6A , the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4  supply a predetermined current to MBL 1  with a time difference. 
     Referring to  FIG. 6B , in the operation state of the multi-channel semiconductor integrated circuit device  100 , MBL 1 -MBL 4  are all in the active operation state. In MBL 1 -MBL 4 , the current needed in the active state is supplied by each of the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of the MBL 1 -MBL 4 . The power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  of MBL 1 -MBL 4  sequentially supply the current needed in the active operation state. Thus, as illustrated in  FIG. 6B , the power generation units  200   a   1 ,  200   a   2 ,  200   a   3 , and  200   a   4 ;  200   b   1 ,  200   b   2 ,  200   b   3 , and  200   b   4 ;  200   c   1 ,  200   c   2 ,  200   c   3 , and  200   c   4 ; and  200   d   1 ,  200   d   2 ,  200   d   3 , and  200   d   4  supply a predetermined current to MBL 1 -MBL 4  with a time difference. 
     Referring to  FIG. 6C , in the operation state of the multi-channel semiconductor integrated circuit device  100 , MBL 1 -MBL 4  are all in the standby operation state. In MBL 1 -MBL 4 , the current needed in the standby state is supplied by the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1  of MBL 1 -MBL 4 . Since the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1  of MBL 1 -MBL 4  sequentially supply the current needed in the standby operation state, as illustrated in  FIG. 6C , the power generation units  200   a   1 ,  200   b   1 ,  200   c   1 , and  200   d   1  supply a predetermined current to MBL 1 -MBL 4  with a time difference. 
     Referring now to  FIG. 7 , a block diagram schematically illustrating the structure of a system  1  including the multi-channel semiconductor integrated circuit device  100  according to some embodiments of the present inventive concept. As illustrated in  FIG. 7 , the system  1  according to the present exemplary embodiment includes the multi-channel semiconductor integrated circuit device  100  and a controller  10 . The system  1  of  FIG. 7  may be implemented as a memory card. 
     The controller  10  may be configured to communicate with an external device(for example, a host) via any one of USB(Universal Serial Bus), MMC(MultiMediaCard) interface, PCI-E(PCI-Express) interface, SATA(Serial AT Attachment), PATA(Parallel AT Attachment), SCSI(Small Computer System Interface), ESDI(Enhanced Small Disk Interface), and IDE(Integrated Drive Electronics) interface, etc. The multi-channel semiconductor integrated circuit device  100  may be used as a data memory device or a code memory device for mobile devices such as a cellular phone, a PDA(Personal digital assistant), a digital camera, a portable game console, and a MP3 player. The multi-channel semiconductor integrated circuit device  100  may be used as a data memory device or a code memory device for mobile devices such as a cellular phone, a PDA(Personal digital assistant), a digital camera, a portable game console, and a MP3 player. Furthermore, the multi-channel semiconductor integrated circuit device  100  may be used as a data memory device or a code memory device for home application system such as a computer, a HDTV(High-definition television), a DVD(‘Digital Versatile Disc’ or ‘Digital Video Disc’), a router, and a GPS(Global Positioning System) 
     The multi-channel semiconductor integrated circuit device  100  and/or the controller  10  according to some embodiments of the present inventive concept may be packed in various types of packages. For example, the various packages may include PoP(Package on Package), Ball grid arrays(BGAs), Chip scale packages(CSPs), Plastic Leaded Chip Carrier(PLCC), Plastic Dual In-Line Package(PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In-Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed Stack Package(WSP). 
     As described above, according to some embodiments of the present inventive concept, since the multi-channel semiconductor integrated circuit device including a plurality of channels that are independently operated is integrally controlled, deviation in the charge consumption amount according to the active timing of each channel may be reduced. Furthermore, during the standby operation, the standby voltage ripple and standby current may be reduced. 
     While the inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the following claims. For example, although, in the above-described embodiments and drawings, a particular number, for example, 4, is referred to as the number of the memory devices and the number of the power generation units included in each memory device for convenience of explanation, the number is a merely an example and may be changed without limit.