Patent Publication Number: US-2023165016-A1

Title: Semiconductor memory device

Description:
CROSS-REFERENCE TO RELATED APPLICATIONS 
     This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2021-0160628, filed on Nov. 19, 2021, in the Korean Intellectual Property Office, the entire contents of which are hereby incorporated by reference. 
     BACKGROUND 
     The present disclosure relates to a semiconductor memory device, and in particular, to a spin-orbit torque (SOT)-based semiconductor memory device. 
     As the demand for electronic devices having increased speed and/or reduced power consumption characteristics increases, the demand for semiconductor memory devices with faster operating speeds and/or lower operating voltages is increasing. Magnetic memory devices have been proposed to satisfy such a demand. The magnetic memory device may have technical advantages, such as reduced latency and/or non-volatility, and thus, it is emerging as a next-generation semiconductor memory device. Accordingly, various studies are being conducted to develop a magnetic memory device with higher integration density and/or lower power consumption. 
     SUMMARY 
     Embodiments of the inventive concept provide a spin-orbit torque (SOT)-based semiconductor memory device of a high integration density. 
     According to some embodiments of the inventive concept, a semiconductor memory device may include a magnetic tunnel junction pattern, a spin-orbit torque (SOT) pattern in contact with a first portion of the magnetic tunnel junction pattern, a first transistor electrically connected to a second portion of the magnetic tunnel junction pattern and configured to be controlled by a first word line, and a second transistor electrically connected to a first end of the spin-orbit torque pattern and configured to be controlled by a second word line. An effective channel width of the first transistor may be different from an effective channel width of the second transistor. 
     According to some embodiments of the inventive concept, a semiconductor memory device may include a first word line and a second word line that extend in a first direction, a bit line and a source line that extend in a second direction that is perpendicular to the first direction, and a plurality of memory cells. Each of the plurality of memory cells may include a spin-orbit torque (SOT) pattern having a first end electrically connected to the source line, and having a second end that is opposite to the first end, a magnetic tunnel junction pattern on the SOT pattern, a first transistor electrically connected to a first end of the magnetic tunnel junction pattern wherein the first transistor is between the first end of the magnetic tunnel junction pattern and the bit line and is configured to be controlled by the first word line, and a second transistor electrically connected to the second end of the SOT pattern wherein the second transistor is between the second end of the SOT pattern and the bit line and is configured to be controlled by the second word line. The first word line and the second word line may cross an active region of a semiconductor substrate, and an overlapping area between the first word line and the active region may be smaller than an overlapping area between the second word line and the active region. 
     According to some embodiments of the inventive concept, a semiconductor memory device may include a semiconductor substrate including a first cell region and a second cell region, each of the first and second cell regions including first and second active patterns which protrude from the semiconductor substrate, a first writing word line on the first cell region wherein the first writing word line crosses the first and second active patterns, a second writing word line on the second cell region wherein the second writing word line crosses the first and second active patterns, a first reading word line on the first cell region, wherein the first reading word line i spaced apart from the first active pattern, crosses the second active pattern and is between the first and second writing word lines, a second reading word line on the second cell region wherein the second reading word line is spaced apart from the first active pattern, crosses the second active pattern, and is between the first reading word line and the second writing word line, first source/drain patterns at a side of the first writing word line and at an opposite side of the second writing word line, second source/drain patterns between the first reading and writing word lines and between the second reading and writing word lines, a third source/drain pattern between the first and second reading word lines, first and second magnetic tunnel junction patterns electrically connected to the second source/drain patterns, respectively, first and second spin-orbit torque (SOT) patterns on the first and second magnetic tunnel junction patterns, respectively, a source line that crosses the first and second writing word lines and the first and second reading word lines and is electrically connected to the first and second SOT patterns, and a bit line that crosses the first and second writing word lines and the first and second reading word lines and is electrically connected to the second source/drain patterns. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       FIG. lA is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  1 B  is a circuit diagram schematically illustrating a memory cell of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  2    is a plan view illustrating first and second transistors, which are provided in a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIGS.  3 A,  3 B,  3 C, and  3 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  2    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  4    is a plan view illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIGS.  5 A,  5 B,  5 C, and  5 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  4    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
         FIGS.  6 ,  7 , and  8    are plan views, each of which illustrates a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  9    is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  10    is a plan view illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIGS.  11 A,  11 B, and  11 C  are sectional views, which are respectively taken along lines I-I′, and of  FIG.  10    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  12    is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
         FIG.  13    is a diagram illustrating a single sub-array in a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
     
    
    
     DETAILED DESCRIPTION 
     Example embodiments of the inventive concepts will now be described more fully with reference to the accompanying drawings, in which example embodiments are shown. 
       FIG.  1 A  is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept.  FIG.  1 B  is a circuit diagram schematically illustrating a memory cell of a semiconductor memory device according to some embodiments of the inventive concept. 
     Referring to  FIGS.  1 A and  1 B , the cell array may include a plurality of writing word lines WWL 0 , WWL 1 , and WWL 2 , a plurality of reading word lines RWL 0 , RWL 1 , and RWL 2 , a plurality of bit lines BL 0 , BL 1 , and BL 2 , a plurality of source lines SL 0 , SL 1 , and SL 2 , and a plurality of memory cells MC. 
     The memory cells MC may be arranged to form a plurality of rows and a plurality of columns. The memory cells MC of each row may be connected to a pair of reading and writing word lines RWL 0 - 2  and WWL 0 - 2 . The memory cells MC of each column may be connected to a pair of source and bit lines SL and BL. 
     First transistors M 1  of the memory cells MC of each row may be connected in common to a corresponding reading word line RWL 0 - 2 , and second transistors M 2  of the memory cells MC of each row may be connected in common to a corresponding writing word line WWL 0 - 2 . 
     Spin-orbit torque (SOT) patterns SOT of the memory cells MC of each column may be connected in common to a corresponding one of the source lines SL, and the first and second transistors M 1  and M 2  of the memory cells MC of each column may be connected in common to a corresponding one of the bit lines BL. 
     Each of the memory cells MC may include a magnetic tunnel junction (MTJ) pattern MTJ, a spin-orbit torque (SOT) pattern SOT, the first or reading transistor M 1 , and the second or writing transistor M 2 . 
     In more detail, the MTJ pattern MTJ may be disposed between the SOT pattern SOT and a first source/drain electrode of the first transistor M 1 . The MTJ pattern MTJ may include a pinned magnetic pattern PL, a free magnetic pattern FL, and a tunnel barrier pattern TBL therebetween, as shown in  FIG.  1 B . 
     The free magnetic pattern FL may be disposed between the SOT pattern SOT and the tunnel barrier pattern TBL, and the pinned magnetic pattern PL may be spaced apart from the free magnetic pattern FL with the tunnel barrier pattern TBL interposed therebetween. The free magnetic pattern FL may have a first surface and a second surface, which are opposite to each other and are in contact with the tunnel barrier pattern TBL and the SOT pattern SOT, respectively. 
     The free magnetic pattern FL may have a magnetization direction, which can be changed by the SOT pattern SOT. The free magnetic pattern FL may have a perpendicular magnetic anisotropy. The structure of the free magnetic pattern FL may be modified to a single-layered or multi-layered structure. 
     The free magnetic pattern FL may be formed of or include at least one of magnetic materials (e.g., iron (Fe), cobalt (Co), nickel (Ni), boron (B), silicon (Si), platinum (Pt), palladium (Pd), and/or alloys thereof). 
     The free magnetic pattern FL may be formed of or include at least one of intrinsic and/or extrinsic perpendicular magnetic materials. The intrinsic perpendicular magnetic material may include a material exhibiting a perpendicular magnetization property, even when there is no external cause. The extrinsic perpendicular magnetic material may include a material, which exhibits an intrinsic in-plane magnetization property when there is no external cause but exhibits a perpendicular magnetization property by an external cause. As an example, the free magnetic pattern FL may be a cobalt layer. As another example, the free magnetic pattern FL may be formed of or include Co 60 Fe 20 B 20 . 
     The pinned magnetic pattern PL may be disposed between the first source/drain electrode of the first transistor M 1  and the tunnel barrier pattern TBL. The pinned magnetic pattern PL may have a fixed magnetization direction and may have a perpendicular magnetic anisotropy. The pinned magnetic pattern PL may have a synthetic anti-ferromagnetic (SAF) structure. In this case, the pinned magnetic pattern PL may include a first pinned pattern, a second pinned pattern, and an exchange coupling pattern between the first and second pinned patterns. The first pinned pattern may be formed of or include a magnetic material, and a magnetization direction of the first pinned pattern may be fixed by the second pinned pattern. The first pinned pattern and the second pinned pattern may be coupled to each other in an anti-parallel manner by the exchange coupling pattern. In some embodiments, the pinned magnetic pattern PL may be formed of or include at least one of Co, Al, Ir, Ru, Pt, Ta, or Hf. In some embodiments, the pinned magnetic pattern PL may be formed of or include at least one of Ni, Fe, Co, B, Ge, Mn, and/or alloys of Ni, Fe, Co, B, Ge, and Mn. In some embodiments, the pinned magnetic pattern PL may be formed of or include compounds or mixtures (e.g., NiFe, CoFe, or CoFeB) including the above elements. In some embodiments, the pinned magnetic pattern PL may include one of, for example, Co/Pt, Co/Pd, and/or Co/Ni super lattices. 
     The tunnel barrier pattern TBL may be formed of or include at least one of magnesium oxide, titanium oxide, aluminum oxide, magnesium-zinc oxide, or magnesium-boron oxide. 
     The SOT pattern SOT may be configured to exert a spin-orbit torque on the free magnetic pattern FL of the MTJ pattern MTJ. A portion of the SOT pattern SOT may be in contact with the free magnetic pattern FL. The SOT pattern SOT may switch the magnetization direction of the free magnetic pattern FL using a spin Hall effect or a Rashba effect which is caused by a spin-orbit torque when there is an in-plane current passing through the SOT pattern SOT adjacent to the free magnetic pattern FL. 
     The SOT pattern SOT may have a first end and a second end, which are opposite to each other. The first end of the SOT pattern SOT may be connected to a first source/drain electrode of the second transistor M 2  of the SOT pattern SOT. The second end of the SOT pattern SOT may be connected to the source line SL. 
     In some embodiments, the SOT pattern SOT may be formed of or include at least one of heavy metals or materials doped with heavy metals. The SOT pattern SOT may include a non-magnetic material. For example, the SOT pattern SOT may be formed of or include at least one of tantalum (Ta), platinum (Pt), bismuth (Bi), titanium (Ti), or tungsten (W). 
     The first transistor M 1  of the memory cell MC may be provided between and connected to the MTJ pattern MTJ and the bit line BL. A gate electrode of the first transistor M 1  may be connected to a reading word line RWL. The first transistor M 1  may be used to control an electric connection between the MTJ pattern MTJ and the bit line BL. 
     The second transistor M 2  of the memory cell MC may be provided between and connected to the first end of the SOT pattern SOT and the bit line BL. A gate electrode of the second transistor M 2  may be connected to a writing word line WWL. The second transistor M 2  may be used to control an electric connection between the SOT pattern SOT and the bit line BL. 
     The bit line BL may be connected to a sense amplifier (not shown). The sense amplifier may compare a sensing voltage of the bit line BL with a reference voltage to determine data, which is stored in the memory cell MC, and then may output the data to the outside. In the cell array, each bit line BL may be connected in common to memory cells of each column. 
     The source line SL may be connected to the second end of the SOT pattern SOT. In the cell array, each source line SL may be connected in common to memory cells of each column. 
     When a writing operation is performed on a selected memory cell, the second transistor M 2  may be turned on by the writing word line WWL and the first transistor M 1  may be turned off. Accordingly, a writing current may flow through the SOT pattern SOT. A direction of the writing current may be changed, depending on voltages applied to the bit line BL and the source line SL. 
     The writing current may be an in-plane current exerting a spin-orbit torque on the free magnetic pattern FL of the MTJ pattern MTJ. The writing current may flow parallel to an interface between the SOT pattern SOT and the free magnetic pattern FL of the MTJ pattern MTJ and along a region adjacent thereto. Due to the spin Hall effect and the Rashba effect, there may be a spin current flowing in a direction, which is perpendicular to the interface between the SOT pattern SOT and the free magnetic pattern FL of the MTJ pattern MTJ, during the flow of the writing current, and as a result, a spin-orbit torque may be exerted on the MTJ pattern MTJ. A magnetization direction of the free magnetic pattern FL of the MTJ pattern MTJ may be switched to be substantially parallel or antiparallel to a magnetization direction of the pinned magnetic pattern PL, depending on an amount of the writing current induced along a surface of the SOT pattern SOT. 
     When a reading operation is performed on a selected memory cell, the first transistor M 1  may be turned on by the reading word line RWL, and the second transistor M 2  may be turned off. During the reading operation, a reading current may flow from the bit line BL to the source line SL. The reading current may flow through a portion of the SOT pattern SOT and the MTJ pattern MTJ. The reading current may be produced to flow through the MTJ pattern MTJ in a direction, which is perpendicular to an interface between the SOT pattern SOT and the MTJ pattern MTJ. 
       FIG.  2    is a plan view illustrating first and second transistors, which are provided in a cell array of a semiconductor memory device according to some embodiments of the inventive concept.  FIGS.  3 A,  3 B,  3 C, and  3 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  2    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
     Referring to  FIGS.  2 ,  3 A,  3 B,  3 C, and  3 D , a semiconductor substrate  100  including first cell regions MC 1  and second cell regions MC 2  may be provided. In some embodiments, the semiconductor substrate  100  may be a silicon wafer, a germanium wafer, or a silicon germanium wafer. The first cell regions MC 1  may be arranged in a first direction D 1 , and the second cell regions MC 2  may be adjacent to the first cell regions MC 1  in a second direction D 2  crossing the first direction D 1 . In other words, the first cell regions MC 1  and the second cell regions MC 2  may be next to one another with respect to the second direction D 2 . 
     In each of the first and second cell regions MC 1  and MC 2 , the semiconductor substrate  100  may include first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b.  The first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  may be spaced apart from each other in the first direction D 1  and may be extended in the second direction D 2  and parallel to each other. Each of the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  may be a vertically-protruding portion of the semiconductor substrate  100 . 
     The first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  may have different lengths from each other in the second direction D 2 . As an example, when measured in the second direction D 2 , the first active pattern F 1   a/ F 1   b  may have a first length, and the second active pattern F 2   a/ F 2   b  may have a second length larger than the first length. 
     The first and second active patterns F 1   b  and F 2   b  of the second cell region MC 2  may be spaced apart from the first and second active patterns F 1   a  and F 2   a  of the first cell region MC 1  in the second direction D 2 . When viewed in a plan view, the first and second active patterns F 1   b  and F 2   b  of the second cell region MC 2  and the first and second active patterns F 1   a  and F 2   a  of the first cell region MC 1  may be arranged to have a point symmetry about a first symmetry point P 1 . When viewed in a plan view, the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  of the first and second cell regions MC 1  and MC 2  may be partially overlapped with each other in the first direction Dl. 
     Device isolation patterns  101  may be disposed between the first and second active patterns F la/F 1   b  and F 2   a/ F 2   b.  Top surfaces of the device isolation patterns  101  may be located at a level lower than top surfaces of the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b,  and upper portions of the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  may protrude from the top surfaces of the device isolation patterns  101  in an upward direction. The device isolation patterns  101  may be formed of or include at least one of, for example, silicon oxide, silicon oxynitride, or silicon nitride. 
     First and second writing word lines WWL 0  and WWL 1  and first and second reading word lines RWL 0  and RWL 1  may be disposed on the semiconductor substrate  100  to be spaced apart from each other by a specific distance. The first and second reading word lines RWL 0  and RWL 1  may be disposed between the first and second writing word lines WWL 0  and WWL 1 . The first and second writing word lines WWL 0  and WWL 1  and the first and second reading word lines RWL 0  and RWL 1  may be disposed on the semiconductor substrate  100 , and a gate dielectric layer may be interposed therebetween. Gate capping patterns GCP may be respectively disposed on the first and second writing word lines WWL 0  and WWL 1  and the first and second reading word lines RWL 0  and RWL 1 . 
     The first and second writing word lines WWL 0  and WWL 1  and the first and second reading word lines RWL 0  and RWL 1  may be formed of or include at least one of doped semiconductor materials (e.g., doped silicon), metallic materials (e.g., tungsten, aluminum, titanium, and/or tantalum), conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride), or metal-semiconductor compounds (e.g., metal silicide). The gate capping patterns GCP may be formed of or include at least one of insulating materials (e.g., silicon oxide or silicon nitride). 
     The first and second writing word lines WWL 0  and WWL 1  may be extended in the first direction D 1  to cross the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  and may be spaced apart from each other in the second direction D 2 . The first and second writing word lines WWL 0  and WWL 1  may be provided to cover or overlap opposite side surfaces and top surfaces of the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b.    
     The first and second reading word lines RWL 0  and RWL 1  may be extended in the first direction D 1  to cross the second active patterns F 2   a/ F 2   b  and may be spaced apart from each other in the second direction D 2 . The first and second reading word lines RWL 0  and RWL 1  may be provided to cover or overlap opposite side surfaces and top surfaces of the second active patterns F 2   a/ F 2   b.    
     In some embodiments, the first and second transistors of each memory cell may be fin-type FETs having fin-shaped channels protruding from the semiconductor substrate  100 . 
     The first reading word line RWL 0  may be provided to cross the second active patterns F 2   a  of the first cell regions MC 1 . Portions of the first reading word line RWL 0  may be disposed between the first active pattern F 1   a  of the first cell region MC 1  and the second active pattern F 2   b  of the second cell region MC 2 . 
     The second reading word line RWL 1  may be provided to cross the second active patterns F 2   b  of the second cell regions MC 2 . Portions of the second reading word line RWL 1  may be disposed between the second active pattern F 2   a  of the first cell region MC 1  and the first active pattern F 1   b  of the second cell region MC 2 . 
     First source/drain patterns SD 1  may be provided in upper portions of the first and second active patterns Fla, F 2   a/ F lb, and F 2   b,  which are located at a side of the first writing word line WWL 0  and at an opposite side of the first writing word line WWL 1 . 
     Second source/drain patterns SD 2  may be provided in upper portions of the first and second active patterns F la, F 2   a/ F 1   b,  and F 2   b,  which are located between the first writing word line WWL 0  and the first reading word line RWL 0  and between the second writing word line WWL 1  and the second reading word line RWL 1 . 
     Third source/drain patterns SD 3  may be provided in upper portions of the second active patterns F 2   a  and F 2   b,  which are located between the first and second reading word lines RWL 0  and RWL 1 . 
     In some embodiments, a top surface of each of the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be located at substantially the same level as the top surfaces of the first and second active patterns F 1   a,  F 2   a/ F 1   b,  and F 2   b.  In some embodiments, the top surfaces of the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be higher than the top surface of the first and second active patterns F 1   a,  F 2   a/ F 1   b,  and F 2   b  adjacent thereto. 
     The first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be doped to have a conductivity type different from that of the first and second active patterns F 1   a,  F 2   a/ F 1   b,  and F 2   b.  The first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be formed of a semiconductor material having a different lattice constant from that of the first and second active patterns F 1   a,  F 2   a/ F 1   b,  and F 2   b.  In some embodiments, the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be formed of or include silicon carbide or silicon germanium. A metal silicide layer (not shown) may be disposed on the first, second, and third source/drain patterns SD  1 , SD 2 , and SD 3 . 
     In some embodiments, the first and second source/drain patterns SD 1  and SD 2  and the first writing word line WWL 0  may be a first transistor (e.g., M 1  of  FIGS.  1 A and  1 B ) of a first memory cell. The second and third source/drain patterns SD 2  and SD 3  and the first reading word line RWL 0  may be a second transistor (e.g., M 2  of  FIGS.  1 A and  1 B ) of the first memory cell. 
     The first and second source/drain patterns SD 1  and SD 2  and the second writing word line WWL 1  may be a first transistor (e.g., M 1  of  FIGS.  1 A and  1 B ) of a second memory cell. The second and third source/drain patterns SD 2  and SD 3  and the second reading word line RWL 1  may be a second transistor (e.g., M 2  of  FIGS.  1 A and  1 B ) of the second memory cell. 
     In some embodiments, a channel width of the first or reading transistor (e.g., M 1  of  FIGS.  1 A and  1 B ) may be smaller than a channel width of the second or writing transistor (e.g., M 2  of  FIGS.  1 A and  1 B ). In other words, an overlapping area between the first and second writing word lines WWL 0  and WWL 1  and the first and second active patterns F  1 a/F 1   b  and F 2   a/ F 2   b  may be larger than an overlapping area between the first and second reading word lines RWL 0  and RWL 1  and the second active patterns F 2   a/ F 2   b.  In this case, a current driving ability of the second transistor M 2  of  FIGS.  1 A and  1 B  may be greater than a current driving ability of the first transistor M 1  of  FIGS.  1 A and  1 B , and thus, it may be possible to reduce an energy required for a writing operation on a memory cell. 
     A first interlayer insulating layer  110  may be disposed on a front surface of the semiconductor substrate  100 . The first interlayer insulating layer  110  may cover or overlap the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3 . The first interlayer insulating layer  110  may be formed of or include at least one of nitride materials (e.g., silicon nitride) and/or oxynitride materials (e.g., silicon oxynitride). 
     First, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115   a/   115   b  may be provided to penetrate the first interlayer insulating layer  110  and may be coupled to the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3 , respectively. When viewed in a plan view, the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115   a/   115   b  may be bar-shaped patterns extended in the first direction D 1 . The third active contact pattern  115   a/   115   b  may be connected to each of the second active patterns F 2   a  and F 2   b  of the first and second cell regions MC 1  and MC 2  or may be connected in common to both of the second active patterns F 2   a  and F 2   b  of the first and second cell regions MC 1  and MC 2 . 
     Each of the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  may include a barrier metal pattern and a metal pattern. The first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  may be formed of or include at least one of metallic materials (e.g., tungsten, titanium, tantalum, and cobalt) and/or conductive metal nitrides (e.g., titanium nitride, tantalum nitride, and/or tungsten nitride). 
     Silicide patterns (not shown) may be respectively interposed between the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  and the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3 . The silicide pattern may be formed of or include at least one of metal silicide materials (e.g., titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, and/or cobalt silicide). 
     In some embodiments, the first and second transistors M 1  and M 2  of each memory cell may be a three-dimensional field effect transistor (e.g., a multi-bridge-channel FET (MBCFET) or a gate-all-around FET (GAAFET)), in which a gate electrode is provided to three-dimensionally surround a nano wire channel or a nano sheet channel. In this case, the semiconductor memory device may include channel patterns, which are stacked on each of the first and second active patterns F 1   a/ F 1   b  and F 2   a/ F 2   b  to be vertically spaced apart from each other, and each of the first and second writing and reading word lines WWL 0 , WWL 1 , RWL 0 , and RWL 1  may be provided to surround the channel patterns. 
       FIG.  4    is a plan view illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept.  FIGS.  5 A,  5 B,  5 C, and  5 D  are sectional views, which are respectively taken along lines A-A′, B-B′, C-C′, and D-D′ of  FIG.  4    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
     As previously described with reference to  FIGS.  2 ,  3 A,  3 B,  3 C, and  3 D , the first and second transistors of the memory cells may be provided on the first and second cell regions. The first and second memory cells may be configured to have the same features and structures as those described with reference to  FIGS.  2 ,  3 A,  3 B,  3 C, and  3 D , and thus, a detailed description thereof will be omitted. 
     Referring to  FIGS.  4 ,  5 A,  5 B,  5 C, and  5 D , a second interlayer insulating layer  120  may be disposed on the first interlayer insulating layer  110 , and first, second, and third lower plugs  121   a/   121   b,    123   a/   123   b,  and  125   a/   125   b  may be disposed in the second interlayer insulating layer  120 . The first lower plugs  121   a/   121   b  may be coupled to the first active contact patterns  111   a  and  111   b,  and the second lower plugs  123   a  and  123   b  may be coupled to the second active contact patterns  113   a  and  113   b.  The third lower plugs  125   a/   125   b  may be coupled to the third active contact patterns  115   a/   115   b.    
     First, second, and third conductive patterns  131 ,  133 , and  135  may be disposed on the second interlayer insulating layer  120 . The first conductive pattern  131  may be coupled to the first lower plug  121   a/   121   b,  and the second conductive pattern  133  may be coupled to the second lower plug  123   a  and  123   b.  The third conductive pattern  135  may be coupled to the third lower plug  125   a/   125   b.    
     A third interlayer insulating layer  130  may be disposed on the second interlayer insulating layer  120 . First and second MTJ patterns MTJa and MTJb may be disposed on the third interlayer insulating layer  130 . Each of the first and second MTJ patterns MTJa and MTJb may be connected to the third conductive pattern  135  through a lower contact plug  139 . In other words, the first and second MTJ patterns MTJa and MTJb may be electrically connected to the third source/drain patterns SD 3 , respectively. 
     Each of the first and second MTJ patterns MTJa and MTJb may include the free magnetic pattern FL, the pinned magnetic pattern PL, and the tunnel barrier pattern TBL therebetween, as previously described with reference to  FIG.  1 B . 
     Each of the first and second MTJ patterns MTJa and MTJb may further include lower and upper electrodes (not shown), and in this case, the free magnetic pattern FL, the pinned magnetic pattern PL, and the tunnel barrier pattern TBL therebetween may be disposed between the lower and upper electrodes. In some embodiments, the first and second MTJ patterns MTJa and MTJb may be provided to have the same stacking structure. 
     The first and second MTJ patterns MTJa and MTJb, which include magnetic materials, may be formed by a patterning process. Each of the first and second MTJ patterns MTJa and MTJb may have substantially the same width in the first and second directions D 1  and D 2 . An upper width of each of the first and second MTJ patterns MTJa and MTJb may be smaller than a lower width thereof. In this case, each of the first and second MTJ patterns MTJa and MTJb may have a substantially trapezoidal vertical section. 
     A fourth interlayer insulating layer  140  may be disposed on the third interlayer insulating layer  130 . In some embodiments, the fourth interlayer insulating layer  140  may fill a space between the first and second MTJ patterns MTJa and MTJb. The fourth interlayer insulating layer  140  may be formed of or include at least one of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and/or oxynitride materials (e.g., silicon oxynitride). 
     A first connection contact plug  141   a/   141   b  may be provided to penetrate the third and fourth interlayer insulating layers  130  and  140  and may be coupled to the first conductive pattern  131 . 
     First and second SOT patterns SOTa and SOTb may be disposed on the fourth interlayer insulating layer  140 . The first SOT pattern SOTa may be provided in the first cell region MC 1 , and the second SOT pattern SOTb may be provided in the second cell region MC 2 . 
     The first and second SOT patterns SOTa and SOTb may be connected to the first and second MTJ patterns MTJa and MTJb, respectively. The first and second SOT patterns SOTa and SOTb may be adjacent to or in contact with the free magnetic patterns FL of the first and second MTJ patterns MTJa and MTJb. Each of the first and second SOT patterns SOTa and SOTb may be provided to have a long axis parallel to the second direction D 2 . The first SOT pattern SOTa may be provided to cross the first reading and writing word lines RWL 0  and WWL 0 . The second SOT pattern SOTb may be provided to cross the second reading and writing word lines RWL 1  and WWL 1 . The first and second SOT patterns SOTa and SOTb may be overlapped with the second active patterns F 2   a  and F 2   b,  when viewed in a plan view. The first and second SOT patterns SOTa and SOTb may be disposed to have a point symmetry about the first symmetry point P 1 , when viewed in a plan view. 
     The first SOT pattern SOTa may be connected to the first connection contact plug  141   a  and the first MTJ pattern MTJa. The second SOT pattern SOTb may be connected to the first connection contact plug  141   b  and the second MTJ pattern MTJb. In other words, the first SOT pattern SOTa may be in contact with a top surface of the first connection contact plug  141   a  and a top surface of the first MTJ pattern MTJa. The second SOT pattern SOTb may be in contact with a top surface of the first connection contact plug  141   b  and a top surface of the second MTJ pattern MTJb. 
     A fifth interlayer insulating layer  150  may be disposed on the fourth interlayer insulating layer  140 . The fifth interlayer insulating layer  150  may cover the first and second SOT patterns SOTa and SOTb. The fifth interlayer insulating layer  150  may be formed of or include at least one of oxide materials (e.g., silicon oxide), nitride materials (e.g., silicon nitride), and/or oxynitride materials (e.g., silicon oxynitride). 
     A second connection contact plug  151   a/   151   b  may be provided to penetrate the third interlayer insulating layers  130  and to be coupled to each of the first and second SOT patterns SOTa and SOTb. 
     The source line SL may be disposed on the fifth interlayer insulating layer  150 . The source line SL may be overlapped with the second active patterns F 2   a  and F 2   b  of the first and second cell regions MC 1  and MC 2  and may be extended in the second direction D 2 . The source line SL may include a connection portion extending in the first direction D 1 . 
     The source line SL may be coupled to the second connection contact plug  151   a/   151   b.  The source line SL may be electrically connected in common to the first and second SOT patterns SOTa and SOTb through the second connection contact plug  151   a/   151   b.  The source line SL may be overlapped with the first active patterns F 1   a  and F 1   b  of the first and second cell regions MC 1  and MC 2 . 
     A sixth interlayer insulating layer  160  may be provided on the fifth interlayer insulating layer  150  to cover the source line SL. 
     The bit line BL may be disposed on the sixth interlayer insulating layer  160 . When viewed in a plan view, the bit line BL may cross the source line SL and may be extended in the second direction D 2 . The bit line BL may be overlapped with the first active patterns F 1   a  and F 1   b  of the first and second cell regions MC 1  and MC 2 . A portion of the bit line BL may be overlapped with a portion of the source line SL. 
     The bit line BL may be connected to the second source/drain patterns SD 2  of the first and second cell regions MC 1  and MC 2  through a third connection contact plug  161 , the second conductive pattern  133 , the second lower plug  123   a/   123   b,  and the second active contact pattern  113   a/   113   b.    
       FIGS.  6 ,  7 , and  8    are plan views, each of which illustrates a cell array of a semiconductor memory device according to some embodiments of the inventive concept. For concise description, a previously-described element may be identified by a similar or identical reference number without repeating an overlapping description thereof. 
     Referring to  FIG.  6   , the semiconductor substrate  100  may include first cell regions MC 1 , second cell regions MC 2 , third cell regions MC 3 , and fourth cell regions MC 4 . 
     The first to fourth cell regions MC 1 , MC 2 , MC 3 , and MC 4  may be sequentially arranged in the second direction D 2 . Each of the first to fourth cell regions MC 1 , MC 2 , MC 3 , and MC 4  may include a first active pattern (e.g., F 1   a/ F 1   b  of  FIG.  6   ), which has a first length in the second direction D 2 , and a second active pattern (e.g., F 2   a/ F 2   b  of  FIG.  6   ), which has a second length larger than the first length, as described above. 
     As described above, the first and second active patterns F 1   b  and F 2   b  of the second cell region MC 2  and the first and second active patterns F 1   a  and F 2   a  of the first cell region MC 1  may be arranged to have a point symmetry about the first symmetry point P 1 , when viewed in a plan view. 
     The third and fourth cell regions MC 3  and MC 4  and the first and second cell regions MC 1  and MC 2  may be provided to have a plane symmetry about an imaginary line parallel to the first direction D 1 . For example, the first and second active patterns F 1   b  and F 2   b  of the third cell region MC 3  and the first and second active patterns F 1   b  and F 2   b  of the second cell region MC 2  may have a mirror symmetry. The first and second active patterns F 1   a  and F 2   a  of the fourth cell region MC 4  and the first and second active patterns F 1   b  and F 2   b  of the third cell region MC 3  may be arranged to have a point symmetry about a second symmetry point P 2 , when viewed in a plan view. The first and second active patterns F 1   a  and F 2   a  of the fourth cell region MC 4  and the first and second active patterns F 1   a  and F 2   a  of the first cell region MC 1  may have a mirror symmetry. 
     The first writing and reading word lines WWL 0  and RWL 0  may be provided on the first cell regions MC 1  arranged in the first direction D 1 , and the second writing and reading word lines WWL 1  and RWL 1  may be provided on the second cell regions MC 2  arranged in the first direction D 1 . 
     The third writing and reading word lines WWL 2  and RWL 2  may be provided on the third cell regions MC 3  arranged in the first direction D 1 , and fourth writing and reading word lines WWL 3  and RWL 3  may be provided on the fourth cell regions MC 4  arranged in the first direction D 1 . 
     As described above, the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be provided in the first and second cell regions MC 1  and MC 2 . Similarly, the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3  may be provided in the third and fourth cell regions MC 3  and MC 4 , and here, the first, second, and third source/drain patterns SD  1 , SD 2 , and SD 3  of the third and fourth cell regions MC 3  and MC 4  and the first, second, and third source/drain patterns SD  1 , SD 2 , and SD 3  of the first and second cell regions MC 1  and MC 2  may have a mirror symmetry. 
     In addition, as described above, the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  may be respectively coupled to the first, second, and third source/drain patterns SD  1 , SD 2 , and SD 3 . Here, the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  of the first and second cell regions MC 1  and MC 2  and the first, second, and third active contact patterns  111   a/   111   b,    113   a/   113   b,  and  115  of the third and fourth cell regions MC 3  and MC 4  may have a mirror symmetry. 
     Referring to  FIGS.  6  and  7   , as described above, the first and second MTJ patterns MTJa and MTJb may be provided in the first and second cell regions MC 1  and MC 2 , respectively. Similarly, the first and second MTJ patterns MTJa and MTJb may be provided in the third and fourth cell regions MC 3  and MC 4 , respectively. The first and second MTJ patterns MTJa and MTJb of the third and fourth cell regions MC 3  and MC 4  and the first and second MTJ patterns MTJa and MTJb of the first and second cell regions MC 1  and MC 2  may have a mirror symmetry. 
     As described above, the first and second SOT patterns SOTa and SOTb may be provided in the first and second cell regions MC 1  and MC 2 , respectively, and the first and second SOT patterns SOTa and SOTb may be provided in the third and fourth cell regions MC 3  and MC 4 . Here, the first and second SOT patterns SOTa and SOTb of the third and fourth cell regions MC 3  and MC 4  and the first and second SOT patterns SOTa and SOTb of the first and second cell regions MC 1  and MC 2  may have a mirror symmetry, when viewed in a plan view. 
     Referring to  FIGS.  6 ,  7 , and  8   , the bit line BL may be extended in the second direction D 2  and may be overlapped with the second active patterns F 2   a  and F 2   b  of the first to fourth cell regions MC 1  to MC 4 . 
     The bit line BL may be connected to the second source/drain patterns SD 2  of the first to fourth cell regions MC 1  to MC 4  through the third connection contact plug  161 , the second conductive pattern  133  of  FIG.  5 A , the second lower plug  123   a/   123   b  of  FIG.  5 A , and the second active contact pattern  113   a/   113   b  of  FIG.  5 A . 
     The source line SL may be extended in the second direction D 2  to cross the bit line BL, when viewed in a plan view. The source line SL may be overlapped with the second active patterns F 2   a  and F 2   b  of the first to fourth cell regions MC 1 -MC 4 . 
     The source line SL may be electrically connected in common to the first and second SOT patterns SOTa and SOTb of the first to fourth cell regions MC 1  to MC 4  through the second connection contact plugs  151   a  and  151   b  of  FIGS.  5 A and  5 D . 
       FIG.  9    is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
     Referring to  FIG.  9   , the cell array may include a plurality of writing word lines WWL 0 , WWL 1 , WWL 2 , and WWL 3 , a plurality of reading word lines RWL 0 , RWL 1 , RWL 2 , and RWL 3 , a plurality of bit lines BL 0 , BL 1 , and BL 2 , a plurality of source lines SL 0 , SL 1 , and SL 2 , and a plurality of memory cells MC. 
     The memory cells MC may be arranged to form a plurality of rows and a plurality of columns. The memory cells MC of each row may be connected to a pair of reading and writing word lines RWL 0 - 3  and WWL 0 - 3 . The memory cells MC of each column may be connected to a pair of source and bit lines SL and BL. 
     Each of the memory cells MC may include the MTJ pattern MTJ, the SOT pattern SOT, and the first and second transistors M 1  and M 2 . 
     The SOT pattern SOT may have a first end and a second end which are opposite to each other. The first end of the SOT pattern SOT may be connected to the source line SL, and the second end of the SOT pattern SOT may be connected to the first source/drain electrode of the second transistor M 2 . A portion of the SOT pattern SOT may be in contact with the free magnetic pattern FL of the MTJ pattern MTJ. 
     The first or reading transistor M 1  of the memory cell MC may be provided between and connected to the MTJ pattern MTJ and the bit line BL. A gate electrode of the first transistor M 1  may be connected to and controlled by a corresponding one of the reading word lines RWL 0  to RWL 3 . 
     The second or writing transistor M 2  of the memory cell MC may be provided between and connected to the MTJ pattern MTJ and the second end of the SOT pattern SOT. A gate electrode of the second transistor M 2  may be connected to and controlled by a corresponding one of the writing word lines WWL 0  to WWL 3 . 
     The reading transistors M 1  of the memory cells MC of each row may be connected in common to a corresponding one of the reading word lines RWL 0 -RWL 3 , and the second transistors M 2  of the memory cells MC of each row may be connected in common to a corresponding one of the writing word lines WL 0 - 3 . 
     The SOT patterns SOT of the memory cells MC of each column may be connected in common to a corresponding one of the source lines SL, and the first transistors M 1  of the memory cells MC of each column may be connected in common to a corresponding one of the bit lines BL. 
       FIG.  10    is a plan view illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept.  FIGS.  11 A,  11 B, and  11 C  are sectional views, which are respectively taken along lines I-I′, and of  FIG.  10    to illustrate a semiconductor memory device according to some embodiments of the inventive concept. 
     Referring to  FIGS.  10 ,  11 A,  11 B, and  11 C , the device isolation pattern  101  may be disposed in the semiconductor substrate  100  to define first and second active regions ACT 1  and ACT 2 . 
     In some embodiments, the first and second active regions ACT 1  and ACT 2  may be disposed in the second direction D 2 . Each of the first and second active regions ACT 1  and ACT 2  may include a first portion and a second portion, which are respectively provided to have a first width W 1  and a second width W 2  smaller than the first width W 1 , when measured in the first direction D 1 . Here, the first and second active regions ACT 1  and ACT 2  may be disposed to have a point symmetry about the first symmetry point P 1 , when viewed in a plan view. 
     The first and second writing word lines WWL 0  and WWL 1  and the first and second reading word lines RWL 0  and RWL 1  may be disposed on the semiconductor substrate  100 . The first and second reading word lines RWL 0  and RWL 1  may be disposed between the first and second writing word lines WWL 0  and WWL 1 . 
     The first and second writing word lines WWL 0  and WWL 1  may be provided to cross the first portions of the first and second active regions ACT 1  and ACT 2 , and the first and second reading word lines RWL 0  and RWL 1  may be provided to cross the second portions of the first and second active regions ACT 1  and ACT 2 . In other words, an overlapping area between the first writing word line WWL 0  and the first active region ACT 1  may be larger than an overlapping area between the first reading word line RWL 0  and the first active region ACT 1 . That is, in the memory cell MC shown in  FIG.  9   , an effective channel width of the second transistor M 2  may be larger than an effective channel width of the first transistor M 1 . 
     The first source/drain patterns SD 1  may be provided in upper portions of the first and second active regions ACT 1  and ACT 2 , which are located at a side of the first writing word line WWL 0  and at an opposite side of the second writing word line WWL 1 . 
     The second source/drain patterns SD 2  may be provided in upper portions of the first and second active regions ACT 1  and ACT 2 , which are located between the first writing word line WWL 0  and the first reading word line RWL 1  and between the second writing word line WWL 1  and the second reading word line RWL 1 . 
     The third source/drain patterns SD 3  may be provided in upper portions of the first and second active regions ACT 1  and ACT 2 , which are located between the first and second reading word lines RWL 0  and RWL 1 . 
     First, second, and third active contact patterns  211   a/   211   b,    213   a/   213   b,  and  215   a/   215   b  may be provided to penetrate the first interlayer insulating layer  110  and may be coupled to the first, second, and third source/drain patterns SD 1 , SD 2 , and SD 3 , respectively. The first, second, and third active contact patterns  211   a,    213   a,  and  215   a  on the first active region ACT 1  and the first, second, and third active contact patterns  211   b,    213   b,  and  215   b  on the second active region ACT 2  may be configured to have a point symmetry about the first symmetry point P 1 . 
     The second interlayer insulating layer  120  may be disposed on the first interlayer insulating layer  110 , and first to third conductive patterns  221   a/   221   b,    223   a/   223   b,  and  225  may be disposed in the second interlayer insulating layer  120 . The first conductive patterns  221   a  and  221   b  may be coupled to the first active contact patterns  211   a  and  211   b,  and the second conductive patterns  223   a  and  223   b  may be coupled to the second active contact patterns  213   a  and  213   b.  A third conductive pattern  225  may be coupled in common to the third active contact patterns  215   a  and  215   b.    
     The first and second MTJ patterns MTJa and MTJb may be disposed on the second interlayer insulating layer  120 . The first and second MTJ patterns MTJa and MTJb may be disposed on the second conductive patterns  223   a  and  223   b.  The first and second MTJ patterns MTJa and MTJb may be configured to have a point symmetry about the first symmetry point P 1 . 
     The third interlayer insulating layer  130  may be disposed on the second interlayer insulating layer  120 . In some embodiments, the third interlayer insulating layer  130  may fill a space between the first and second MTJ patterns MTJa and MTJb. 
     The first and second SOT patterns SOTa and SOTb may be disposed on the third interlayer insulating layer  130 . The first and second SOT patterns SOTa and SOTb may be disposed to have a point symmetry about the first symmetry point P 1 . 
     A first and second lower contact plug  231   a/   231   b  may be provided to penetrate the third interlayer insulating layer  130  and may be coupled to the first conductive pattern  221   a/   221   b.  The first and second lower contact plug  231   a/   231   b  may connect the first or second SOT pattern SOTa or SOTb to the first conductive pattern  221   a/   221   b.    
     The first and second SOT patterns SOTa and SOTb may be connected to the first and second MTJ patterns MTJa and MTJb, respectively. The first and second SOT patterns SOTa and SOTb may be adjacent to or in contact with the free magnetic patterns FL of the first and second MTJ patterns MTJa and MTJb. Each of the first and second SOT patterns SOTa and SOTb may be provided to have a long axis parallel to the second direction D 2 . 
     The first SOT pattern SOTa may be connected to the first lower contact plug  231   a  and the first MTJ pattern MTJa. The second SOT pattern SOTb may be connected to the second lower contact plug  231   b  and the second MTJ pattern MTJb. In other words, the first SOT pattern SOTa may be in contact with a top surface of the first lower contact plug  231   a  and a top surface of the first MTJ pattern MTJa. The second SOT pattern SOTb may be in contact with a top surface of the second lower contact plug  231   b  and a top surface of the second MTJ pattern MTJb. 
     The fourth interlayer insulating layer  140  may be disposed on the third interlayer insulating layer  130 . The fourth interlayer insulating layer  140  may cover or overlap the first and second SOT patterns SOTa and SOTb. 
     First and second upper plugs  241   a  and  241   b  may be provided to penetrate the fourth interlayer insulating layer  140  and may be coupled to the first and second SOT patterns SOTa and SOTb, respectively. 
     The source line SL may be disposed on the fourth interlayer insulating layer  140  and may be extended in the second direction D 2 . The source line SL may be coupled in common to the first and second upper plugs  241   a  and  241   b.  The source line SL may be electrically connected in common to the first and second SOT patterns SOTa and SOTb through the first and second upper plugs  241   a  and  241   b.  In some embodiments, the source line SL may be overlapped with the first and second SOT patterns SOTa and SOTb and may be extended in the second direction D 2 . 
     The fifth interlayer insulating layer  150  may be disposed on the fourth interlayer insulating layer  140 . The bit line BL may be disposed on the fifth interlayer insulating layer  150 . The bit line BL may be extended in the second direction D 2  but may not be overlapped with the first and second SOT patterns SOTa and SOTb. The bit line BL may be provided to cross a portion of the source line SL. The bit line BL may be connected to the third conductive pattern  225  through a bit line contact plug  251 . 
       FIG.  12    is a circuit diagram illustrating a cell array of a semiconductor memory device according to some embodiments of the inventive concept.  FIG.  13    is a diagram illustrating a single sub-array in a cell array of a semiconductor memory device according to some embodiments of the inventive concept. 
     Referring to  FIGS.  12  and  13   , the memory cell array may include a plurality of sub-arrays SA. The sub-arrays SA may be provided between and connected to a pair of the bit and source lines BL and SL. 
     Each of the sub-arrays SA may be connected to one write word line WWL and one read word line RWL. Each of the sub-arrays SA may include the memory cells MC arranged in the row direction, the SOT pattern SOT connected in common to the memory cells MC, and one second transistor M 2 . Each sub-array SA may include a plurality of memory cells. As an example, each sub-array SA may include three memory cells, as shown in  FIG.  13   . Each of the memory cells MC may include a data storage device (e.g., the MTJ pattern MTJ) and the first transistor Ml. 
     In some embodiments, the MTJ patterns MTJ in each sub-array SA may share one SOT pattern SOT. Thus, each of the memory cells MC may require or need a device that is configured to allow for a dynamic program of changing a direction of spin accumulation (e.g., SOT polarity) in each memory cell MC during a data writing operation. That is, there is a need for an additional element capable of selectively programming the memory cells MC of each sub-array SA during supplying a current to the SOT pattern SOT in a specific direction. Thus, each MTJ patterns MTJ may include an oxygen storage layer, and in this case, by using an oxygen migration, which is caused by a voltage or electric field applied to the oxygen storage layer, and a modulation of polarity of a spin-orbit torque (SOT), it may be possible to realize a data programming operation. 
     The second transistor M 2  may include gate, source, and drain electrodes, which are connected to the writing word line WWL, the source line SL, and the SOT pattern SOT, respectively. 
     The first transistors M 1  of the memory cells MC may be connected to data lines DL, respectively. Each data line DL may be connected to a sense amplifier (not shown) through a drive transistor SW, and a sensing voltage of the data line DL may be compared with a reference voltage to determine data stored in the memory cell MC. 
     The first transistor M 1  may include gate, drain, and source electrodes, which are connected to the reading word line RWL, the data line DL, and the MTJ pattern MTJ, respectively. 
     In some embodiments, each of the first transistors M 1  in each sub-array SA may have a size different from the second transistor M 2 . For example, similar to the aforementioned embodiments, an effective channel width of the first transistor M 1  may be smaller than an effective channel width of the second transistor M 2 . As an example, an overlapping area between the gate electrode of the first transistor M 1  and the active region may be smaller than an overlapping area between the gate electrode of the second transistor M 2  and the active region. 
     According to some embodiments of the inventive concept, a first or reading transistor and a second or writing transistor provided in a unit memory cell may have different effective channel widths from each other, and this may make it possible to increase an integration density of a semiconductor memory device. 
     Furthermore, a channel width of a second transistor, which is connected to a spin-orbit torque pattern, may be larger than a channel width of a first transistor, and in this case, it may be possible to reduce a writing energy required for a writing operation on a semiconductor memory device. 
     While example embodiments of the inventive concept have been particularly shown and described, it will be understood by one of ordinary skill in the art that variations in form and detail may be made therein without departing from the spirit and scope of the attached claims.