Patent Publication Number: US-3969638-A

Title: Integrated circuit breaker

Description:
FIELD OF THE INVENTION 
     Our present invention relates to a circuit breaker of the integrated kind, serving for the selective completion and interruption of a signal path, as well as to a switching system incorporating a plurality of such circuit breakers for the selective energization of a load from a corresponding number of input terminals carrying different signals. 
     BACKGROUND OF THE INVENTION 
     Semiconductive devices are widely used as electronic switches. Besides the usual bipolar transistors, field-effect transistors (FETs) can be used for this purpose, especially those of the MOS (metal-oxide-semiconductor) type known as MOSFETs. With transistors of this nature it is possible to combine a multiplicity of switching circuits into an integrated and miniaturized module also including associated impedance elements such as resistors and capacitors. 
     In a system requiring complete cutoff of a signal path, however, the inherent capacitance of the MOSFET constitutes a residual admittance whose presence prevents complete insulation of the load from the signal input. In a time-division-multiplex (TDM) telecommunication system, for example, such incomplete insulation gives rise to cross-talk between the individual communication links. 
     Another problem heretofore encountered in such switching circuits is the need for an ancillary or pilot transistor to which a control voltage independent of the input signal is applied for turning the main or switching transistor on and off, this pilot transistor normally drawing a certain amount of current even in the nonconducting state of the switching transistor. Since in a TDM system each switching transistor generally is to conduct only during a small fraction of a cycle, the dissipation of energy by the associated pilot transistors is particularly wasteful. 
     OBJECTS OF THE INVENTION 
     An important object of our invention, therefore, is to provide an improved integrated switching circuit of the character described which draws virtually no current in the open-circuit condition. 
     Another object is to provide improved means in such a circuit, fully integrated therewith, for effectively decoupling the signal input from the load during cutoff. 
     SUMMARY OF THE INVENTION 
     In accordance with the present invention, we provide a first and a second MOSFET respectively serving as the aforementioned switching and pilot transistors, each of these MOSFETs having the usual two principal electrodes (source and drain) at opposite ends of a channel and a gate conductively isolated from that channel but capacitively coupled therewith. The channel of the first MOSFET is connected, by way of an output resistance, across a supply of direct current which also feeds the channel of the second MOSFET in series with a biasing resistor. The gate of the first MOSFET is connected to this biasing resistor while that of the second MOSFET is connected to a control unit for alternately turning the first MOSFET on and off through the energization of de-energization of the biasing resistor. 
     According to another feature of our invention, a third MOSFET acting as a decoupling transistor has its channel connected in series with that of the first MOSFET and also with the output resistance, the gate of this third MOSFET receiving the input signal which is to be transmitted to the output resistance or to a load connected across the latter. Thus, the first MOSFET lies in cascade with the second MOSFET but in tandem with the third MOSFET so as to disconnect one of the principal electrodes of this third MOSFET from the power supply when the first MOSFET is rendered nonconductive by the application of a cutoff voltage to the gate of the second MOSFET. 
     Advantageously, all three MOSFETs are of the same conductivity type (e.g. P-channel) and have substrates connected to a supply terminal other than the one to which the biasing resistor is connected, these substrates being biased positive in the case of P-channel MOSFETs. 
     With incorporation of a plurality of such three-transistor circuits into a common module serving as a switching matrix, the output resistance referred to above may be constituted by a resistor common to the several signal paths. 
    
    
     BRIEF DESCRIPTION OF THE DRAWING 
     The above and other features of our invention will now be described in detail with reference to the accompanying drawing in which: 
     FIG. 1 diagrammatically shows an integrated circuit embodying our invention; and 
     FIG. 2 is a diagram illustrating an integrated switching system incorporating a plurality of circuits as shown in FIG. 1. 
    
    
     SPECIFIC DESCRIPTION 
     In FIG. 1 we have shown a block or wafer 10 of semiconductive material with three integrated stages, i.e., a switching stage I, a pilot stage II and a decoupling stage III. The three stages consist essentially of three substantially identical MOSFETs T 1 , T 2  and T 3  each formed in an N-type substrate and comprising P-type drain and source electrodes S 1 , D 1 , S 2 , D 2  and S 3 , D 3  at opposite ends of a P-channel which is separated from an associated gate electrode G 1 , G 2 , G 3 . A d-c power supply comprises a negative bus bar 11 and a positive bus bar 12, bus bar 12 being connected via an output resistance R to source S 1  and directly to source S 2  whereas bus bar 11 is connected via a biasing resistor R 1  to drain D 2  and directly to drain D 3 . Drain D 1  and source S 3  are tied together so that the channels of MOSFETs T 1  and T 3  are serially interconnected, with their respective principal electrodes S 1 , S 3  and D 1 , D 3 , across these bus bars in series with resistance R. An output terminal U, which may be connected to a nonillustrated load, is tied to source S 1 . MOSFETs T 1 , T 2  and T 3  have substrates all connected to positive bus bar 12. 
     Gate G 1  is connected to drain D 2  whereas gate G 3  is joined to a tap of a voltage divider R 2 , R 3  bridges across bus bars 11 and 12. Gate G 3  receives input signals s, to be transmitted to output terminal U, whereas gate G 2  is energizable with positive control pulses p to cut off the MOSFET T 2 , thereby driving negative the gate G 1  of MOSFET T 1  which thus conducts. In the present of a positive voltage p, therefore, the signal s (which could be an amplitude sample of a voice message in a TDM telephone system) can pass through the circuit of FIG. 1 to reach the load terminal U. 
     In the absence of a positive control voltage p, i.e. with the gate G 2  held at substantially the potential of negative bus bar 11, MOSFET T 2  conducts whereby gate G 1  is biased positive from bus bar 11 through resistor R 1  so that MOSFET T 1  is cut off. Source S 3  is then effectively disconnected from its current supply 12 so that MOSFET T 3  does not respond to the input signal s. It should be noted that the nonillustrated generator of this input signal sees substantially the same impedance whether or not transistor T 1  conducts. 
     In FIG. 2 we have shown an expanded version of module 10 accommodated a number n of signal paths each similar to that of FIG. 1. The corresponding switching, pilot and decoupling transistors have been shown in FIG. 2 as MOSFETs T 1a , T 1b , . . . T 1n , T 2a , T 2b , . . . T 2n  and T 3a , T 3b , . . . T 3n . The gates of switching transistors T 1a  - T 1n  are connected to negative potential via respective biasing resistors R 1a , R 1b , . . . R 1n  whereas their sources extend to positive potential by way of a common outut resistor R. The gates of decoupling transistors T 3a  - T 3n  receive respective input signals s a , s b , . . . s n . Control pulses P a , P b , . . . P n  are delivered to the gates of pilot transistors T 2a  - T 2n , in a predetermined sequence, by a switching unit SC which may be a decoder of distribution signals accompanying a group of line signals s a  - s n  as well known per se. Thus, as described above with reference to FIG. 1, only one signal path at a time is completed while all the others are blocked to avoid any cross-talk between the several communication links. 
     It will be apparent that the decoupling transistor T 3  of any signal path draws no current when the associated switching transistor T 1  is cut off, owing to the fact that the two transistors are in cascade. The substrates of these transistors are connected to one supply terminal (here positive) whereas the gate of transistor T 1  is connected through resistor R 1  to the opposite supply terminal (here negative). The polarities of bus bars 11 and 12 will have to be changed if P-type substrates with N-channel MOSFETs are used in lieu of the arrangement described.