Patent Publication Number: US-5157698-A

Title: Method for clock pulse synchronization

Description:
BACKGROUND OF THE INVENTION 
     The invention relates to a method and to a circuit arrangement for implementing a synchronization method in a receiver of digital data transmissions including a timing error detector to which are fed in in-phase component and a quadrature component of a demodulated received signal produced from products of the received signal and an output signal of a carrier oscillator and lowpass filtering of the products to suppress harmonics. An output signal of the timing error detector serves as a control signal u TI  for a clock pulse generator which produces clock pulses for sampling the received signal. The control signal u TI  is produced by means of two bandpass filters in the timing error detector which convert the demodulated received signal into two respective complex signals which are in turn linked together by means of a linkage circuit in the timing error detector to form the control signal u TI . The control signal u TI  is used to actuate a timing error correction circuit of the clock pulse generator to synchronize the clock pulses with the received signal. 
     Such methods are known, for example from the article by Gardner, entitled &#34;A BPSK/QPSK Timing-Error Detector for Sampled Receivers,&#34; in IEEE Com.-34, No. 5, May, 1986, pages 423-429. 
     In digital data transmission it is important for the receiver to derive the exact sampling moment from the received data. For this purpose, a timing error detector generates by way of non-linear operations an output signal u TI  whose fundamental mode corresponds to the clock pulse frequency and whose zero passages permit derivation of the sampling moment. 
     FIG. 1 shows a clock pulse control loop as disclosed in the above Gardner article and as it is employed, for example, for QPSK (quadrature phase shift keyed) data transmission. The incoming received signal s(t) is demodulated in that the carrier signal is fed to it multiplicatively once directly and once with a phase shift of -π/2. By means of lowpass filters TP, the products of the double frequency are suppressed. The normal component, i.e. the real component x(t), and the quadrature component, i.e. the imaginary component y(t), of the demodulated input signal are obtained from the outputs of the lowpass filters and fed to a subsequent timing error detector TD. Its output signal u TI  is fed via a loop filter (SF) to a timing error correction device TPK which actuates a sampling device A for sampling, for example, the non-demodulated or the demodulated input signal. Such sampling is necessary if the signals are to be processed in the receiver in a time discrete manner. 
     In FIG. 1, for example, sampling occurs before demodulation. However, such sampling could also be done at any other desired location, for example after demodulation or after lowpass filtering. It is here assumed that the output signal of the timing error detector is present as a sampled signal u TI  (kT), where T is the symbol interval or the step length which, according to the relationship of f Nyq  =1/2T is a function of the Nyquist frequency f Nyq . The sampling phase of the sampler A present in the receiver is changed by way of loop filter SF and timing error correction circuit TPK until the sampled values at the output of the timing error detector average zero: u TI  (k·T)=0, where k is an integer which numbers the clock pulses. 
     FIG. 2 shows the typical characteristic of a timing error detector. The sampling phase ε , i.e. the deviation Δt/T of the actual sampling moments from the correct sampling moments (in the case where transmitter and receiver clock pulse are coherent, ε=0) are plotted in the direction of the abscissa and the averages of u TI  are plotted in the direction of the ordinate. For ε=0 and ε=±0.5, u TI  =0. The center ε=0 of this sinusoidal curve is stable while at ε=±0.5, synchronization may be labile, i.e. it is possible that the synchronization is caught at the labile point for a longer or shorter period of time, thus noticeably lengthening the synchronization time. 
     SUMMARY OF THE INVENTION 
     It is the object of the present invention to provide a method of the above-mentioned type which is able to substantially suppress the above-described getting-caught and permits much faster synchronization. 
     The solution is effected as follows: By means of a second linkage circuit in the timing error detector, the two complex signals from the bandpass filters are linked together to form a second control signal u TR  in such a manner that the two control signals u TR  and u TI  can be interpreted as the real component and the imaginary component of a complex control value u T  =u TR  +ju TI . The two control signals u TR  and u TI  are subjected to averaging. Thereafter, the thus averaged values u TR  and u TI  are evaluated by means of an evaluation circuit to form an actuation value δ which actuates the timing error correction circuit. 
     The method according to the invention has the advantage that the above-described getting-caught is substantially suppressed and thus synchronization can take place much faster. The additional costs for this are relatively low. 
    
    
     BRIEF DESCRIPTION OF THE DRAWINGS 
     FIG. 1 is a block circuit diagram of a clock pulse control loop according to the prior art; 
     FIG. 2 shows a graph of a characteristic of an output signal of a timing error detector; 
     FIG. 3 is a plot of averages of real and imaginary components of a complex timing error detector output signal; 
     FIG. 4 is a plot of the phase angle of a complex timing error detector output vector as a function of the sampling phase; 
     FIG. 5 is a block diagram of a circuit for carrying out a method of synchronizing clock pulses according to an embodiment of the invention; 
     FIG. 5a is a block diagram of the timing error detection circuit; 
     FIG. 5b in a block diagram of the linkage circuit, of the timing error detector circuit, for producing the real component u TR  of the complex control value u T  ; 
     FIG. 5c is a block diagram of the linkage circuit, of the timing error detector circuit, for producing the imaginary component u TI  of the complex control value u T  ; 
     FIG. 6 is a block diagram of a circuit for carrying out a second embodiment of the method of the invention; 
     FIGS. 7a-7f, 8a and 8b are plots illustrating several ways of evaluating the averaged values u TR , u TI  ; and 
     FIG. 9 illustrates a circuit arrangement for carrying out a still further embodiment of the method of the invention. 
    
    
     DESCRIPTION OF THE PREFERRED EMBODIMENTS 
     Applicant&#39;s German Application P 37 07 763 (corresponding to applicant&#39;s allowed copending U.S. application Ser. No. 07/423,391, filed Sept. 11, 1989) now U.S. Pat. No. 5,031,199 issued Jul. 9, 1991. discloses combined frequency and timing error detectors in which the timing error detector generates two output signals u TR  and u TI  which can be interpreted as the real and the imaginary component of a complex timing error detector output signal u T  =u TR  +ju TI . Details of the timing error detector are described below. If one plots the average of u TR  and u TI  as the real component and the imaginary component in a complex plane, a complex vector of a length ρ=√u TR   2  +u TI   2  and the phase angle φ=arc tan u TI  /u TR  results, see FIG. 3. 
     The use of φ=arc tan u TI  /u TR  as the actuation signal for the subsequent timing error correction circuit leads to improved acquisition behavior. The relationship between ε and φ is shown in FIG. 4. 
     The method according to the invention will now be described with reference to FIG. 5 which shows an arrangement according to the invention. The real component u TR  and the imaginary component u TI  of the clock pulse oscillation are generated with the aid of a timing error detector TD, as disclosed in the above identified German application and in the corresponding U.S. Pat. No. 5,031,197 and illustrated in FIGS. 5a, 5b and 5c as described below. As is illustrated in FIG. 5a, the timing error detector TD includes two bandpass filters BP+ and two combining or linkage circuits VTR and VTI. The two bandpass filters BP+ respectively bandpass filter the lowpass filtered demodulated in-phase component x and quadrature component y or a received signal, to obtain two respective complex signals (rx)+j(iy) and (ry)+(j(iy), where j+√-1, rx and ry are real components and ix and iy are imaginary components. The linkage circuits VTR and VTI link the two complex signals in different ways to produce the output signals u TR  and u TI  as respectively illustrated in FIGS. 5b and 5c. As shown in FIG. 5b, linkage circuit VTR squares the respective components rx, ry, ix and iy and then combines the squared components to obtain u TR  =(rx) 2  +(iy) 2  -(ix) 2  -(iy) 2 , and as shown in FIG. 5c, multiples the components in pairs, to obtain the products (rx)(ix) and (ry)(iy), sums the products the and multiplies the sum by 2 to obtain u TI  2{(rx)(ix)+(ry)(iy)}. 
     The real component and imaginary component should be present either as samples u TR  (k·T), u TI  (K·T) or they are sampled at the sampling rate f S  =1/T, with the sampling phase or, more precisely, its deviation, being assumed to be ε=Δt/T. Such a sampling of the two output signals of timing error detector TD is shown in FIG. 5. The samples of the two components are then averaged over m clock pulses in average formers MW. In special cases, m=1, i.e. no averaging is possible. After an averaging time of m·T, the averages are fed to an evaluation circuit AS which feeds an adjustment or control information δ to the subsequent timing error correction circuit TPK. The latter, in turn, puts out the sampling clock pulse at a sampling phase corrected by δ. 
     The function of evaluation circuit AS will be described with reference to FIGS. 7a-7f, 8a and 8b. These figures show several possibilities for evaluating the two averages. 
     A first possible way is shown in FIGS. 7a and 7b. The phase φ=arc tan u TI  /u TR  is formed from the two averages u TR   and u TI . A linear relationship of δ=0.5·φπ exists between the phase φ and δ as shown in FIG. 7b. The precise determination of phase φ is somewhat complicated. It is simplified if regions are formed in the u TR , u TI  plane which are easily queried and fixed phase values φ Q  are then assigned to these regions. 
     This second possible way is shown in FIGS. 7c and 7d. In FIG. 7c, a vector is assigned to each hatched region identified by encircled numerals, with the respective vector bearing the same numeral. The asterisks identify the tips of the respective vector. Thus each region has associated with it as φ Q  the phase of the corresponding vector. This corresponds to quantizing of φ as shown in FIG. 7d. The linear relationship between δ and φ according to FIG. 7a thus changes to a stepped curve as shown in FIG. 7d in which the following applies: δ=0.5·φ Q  /π and which shows the association of the regions with the fixed phase values of the table below. The division into regions shown in FIG. 7c is merely an example. Other types of regional divisions may of course also be realized; they differ in the magnitude of the expenditures for the query logic. 
     
                       TABLE                                                       
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Phase angle region of φ.sup.--                                        
                        φ.sub.Q                                       
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-π/16 ≧ φ.sup.--  ≦ + π/16                        
                        0                                                 
π/16 &lt; φ.sup.--  ≦ π/4                                   
                        π/16                                           
π/4 &lt; φ.sup.--  ≦ π/2                                    
                        π/4                                            
π/2 &lt; φ.sup.--  ≦ π                                      
                        3π/4                                           
-π/16 &gt; φ.sup.-- -π/16. -π/4                                 
-π/4 &gt; φ.sup.--  ≧ -π/2                                  
                        -π/4                                           
-π/2 &gt; φ.sup.--  &gt; -π                                           
                        -3π/4                                          
______________________________________                                    
 
    
     A third possible way shown in FIGS. 7e and 7f is very inexpensive. Here the quantized value φ Q  =φ min  is fixed for positive phases φ and the quantized value φ Q  =-φ min  is fixed for negative phases φ, so that δ=±δ min  =±0.5·φ min  /π. Thus, in this manner of proceeding, only the sign of imaginary component u TI  is evaluated and the actuation value δ is realized according to the equation δ=δ min  ·sign(u TI ). However, in this very simple procedure, the problem of the timing control being caught occurs again, namely at a sampling error of ±50%. The problem can be prevented by the evaluation shown in FIGS. 8a and 8b . The quantization characteristic according to FIG. 8b includes a hysteresis in phase regions π/2&lt;φ&lt;3φ/2 and -3φ/2&lt;φ&lt;-π/2, respectively, while region -π/2 ≦φ ≦φ/2 corresponds precisely to the corresponding region of the quantization characteristic of FIG. 7f. The use of a hysteresis is made possible, for example, in that the region of the complex u TR , u TI  plane is divided into three regions, namely the first quadrant, the fourth quadrant and a region covering the second and third quadrants, i.e. for negative u TR  values. A phase value assignment of +φ min  applies for the first quadrant and a phase value assignment of -φ min  for the fourth quadrant. The second and third quadrants receive phase value assignments of ±α·φ min , where α≧1. However, the assignments are made in such a way that if phase φ is enlarged out of the first quadrant, the assignment will continue with a positive value +φ min  or &gt;+ min  and only if the phase changes from the third into the fourth quadrant, is the phase value of -φ min  assigned which is applicable there. Conversely, if phase φ becomes smaller and changes, for example, from the fourth quadrant to the third and second quadrants, the phase value of -φ min  assigned to the fourth quadrant is retained or reduced further (α&gt;1). Only if a change should occur from the second to the first quadrant, is the new phase value +φ min  existing there assigned again. Thus, the actuation value δ is assigned according to the equation δ+0.5 sgn (u TI ). φ min  /π if sgn (u TR ) is positive, and according to the equation δ=0.5 sgn (u TIP )·α·φ min  /π if sgn (u TR ) is negative, wherein α≧1 and sgn (u TIP ) is the sign of uTI at a most recent time that u TR  was positive. The division into regions and the assignment of phase values can be seen in FIG. 8a. Of course, another regional division may be realized as well. The regional assignment shown here, however, is particularly inexpensive; it merely necessitates a query for the second and third quadrants whether the real component of the average of the timing error detector output signal is negative. 
     According to FIG. 5, the real and imaginary components of the complex output signal of timing error detector TD are sampled at intervals of a step length T, i.e. at the clock pulse rate f S  =1/T. 
     FIG. 6 shows an arrangement in which averaging is performed analogously, e.g. by means of lowpass filters. The sampling here does not take place until downstream of the average formers and at the reduced sampling rate f S  /m. The requirements for the subsequent analog-digital conversion are thus reduced as well. In contrast to FIG. 5, the block circuit diagram of FIG. 6 shows a demodulator module DEM included between timing error detector TD and average formers MW, with f T  being the clock pulse frequency. 
     Basically, two possibilities exist to correct the sampling moment: firstly by way of a feedback arrangement and secondly by an arrangement for forward correction. 
     The first is shown in FIG. 1. The feedback arrangement is distinguished in that the timing error detector is influenced by the corrected sampling phase itself. If the sampling phase is correct, the output signal of the timing error detector will average zero. 
     An arrangement for forward correction is shown in FIG. 9. Here, the output signal of timing error detector TD is influenced not by the correction of the sampling phase, rather the output signal of timing error correction circuit TPK is utilized only to set the sampling phase A in the data signal branch. 
     The arrangements of FIGS. 5 and 6 permit many possible combinations of averaging duration m·T and evaluation circuit AS. 
     Both arrangements and their combinations can be utilized for the timing control according to FIG. 1 and also for the forward timing control of FIG. 9. 
     In a feedback arrangement according to FIG. 1 it is favorable to select m to be small, e.g. m=1, and to perform only a rough quantization of the sampling phase in evaluation circuit AS in any of the ways described above with reference to FIGS. 7c-7f, 8a and 8b. 
     The costs for realization will then become correspondingly low. 
     For the forward correction of the clock pulse shown in FIG. 9, however, wherein the signal s(t) is applied to a demodulator Dem and a preequalizer VE before being sampled according to the output of timing error circuit TPK, it is necessary foe the evaluation circuit AS to furnish the most accurate possible linear estimate of the sampling phase. This is the case if, in the circuit arrangement according to FIG. 5 or 6, the averaging time m·T is large, i.e. m is high, and in evaluation circuit AS phase φ  is determined as accurately as possible, e.g. by effecting the evaluation according to the equation δ=0.5·φ/π, where φ=arc tan u TI  /u TR , as illustrated in FIGS. 7a and 7b.