Patent Publication Number: US-9853123-B2

Title: Semiconductor structure and fabrication method thereof

Description:
BACKGROUND OF THE INVENTION 
     1. Field of the Invention 
     The invention generally is related to a semiconductor structure and a method of making the same. More particularly, the invention is related to a high-k metal gate (HK/MG) semiconductor device that can avoid tungsten seam issues. 
     2. Description of the Prior Art 
     Continuing advances in semiconductor manufacturing processes have resulted in semiconductor devices with finer features and higher degrees of integration. 
     As the size of the integrated circuit devices continues to scale down, the polysilicon gate and the silicon dioxide insulating layer of a metal-oxide-semiconductor field effect transistor (MOSFET) structure have confronted with the physical limits of the materials themselves. To meet the demands of scalability, it is necessary to incorporate high-k metal gate (HK/MG) process. 
     Today, two main integration options remain: gate-first (often referred to as MIPS, metal inserted poly-silicon) and gate-last (also called RMG, replacement metal gate). The terminology “first” and “last” refers to whether the metal electrode is deposited before or after the high temperature activation anneal of the flow. 
     The RMG process typically involves a bulk tungsten filling process in a gate trench to form a low-resistance metal layer in the composite metal gate structure. After bulk tungsten filling, tungsten seams or voids are often observed in the bulk tungsten layer. Such tungsten seams are commonly exposed during subsequent chemical mechanical polishing (CMP) process, which results in electrical device degradation. 
     Therefore, there is a need in this technical field to provide an improved semiconductor structure such as a high-k metal gate semiconductor device without such tungsten seam issues. 
     SUMMARY OF THE INVENTION 
     It is one object of the invention to provide an improved semiconductor structure such as a high-k metal gate semiconductor device and fabrication method thereof, which is able to eliminating the tungsten seam or void. 
     According to one aspect of the invention, a semiconductor structure includes a substrate having thereon a dielectric layer. An opening is disposed in the dielectric layer. The opening includes a bottom surface and a sidewall surface. A diffusion barrier layer is conformally disposed along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally disposed on the diffusion barrier layer. A bulk metal layer is disposed on the nucleation metal layer. A film-growth retarding layer is disposed between the nucleation metal layer and the bulk metal layer. The diffusion barrier layer comprises titanium nitride. 
     According to one embodiment, the bulk metal layer comprises tungsten. The film-growth retarding layer comprises tungsten nitride. The film-growth retarding layer is disposed only on an upper surface of the nucleation metal layer within the opening. 
     According to one embodiment, the opening is a gate trench opening and the substrate is a semiconductor substrate. The dielectric layer is a silicon nitride spacer layer. The semiconductor structure further includes high-k dielectric layer and a work function metal layer between the substrate and the diffusion barrier layer. 
     According to another embodiment, the opening is a contact hole opening. The dielectric layer is an inter-layer dielectric (ILD) layer. A conductive region is disposed in the substrate and the diffusion barrier layer is in direct contact with the conductive region. 
     According to another aspect of the invention, a method for fabricating a semiconductor structure is disclosed. A substrate having thereon a dielectric layer is provided. An opening is formed in the dielectric layer. The opening comprises a bottom surface and a sidewall surface. A diffusion barrier layer is conformally deposited along the sidewall surface and the bottom surface of the opening. A nucleation metal layer is conformally deposited on the diffusion barrier layer. A film-growth retarding layer is then formed on an upper surface of the nucleation metal layer. A bulk metal layer is then deposited on the nucleation metal layer to fill up the opening. 
     These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       The accompanying drawings are included to provide a further understanding of the embodiments, and are incorporated in and constitute apart of this specification. The drawings illustrate some of the embodiments and, together with the description, serve to explain their principles. In the drawings: 
         FIG. 1  is a schematic, cross-sectional diagram showing an exemplary semiconductor structure without tungsten seam in accordance with one embodiment of the invention; 
         FIG. 2  to  FIG. 8  are schematic, cross-sectional diagram showing an exemplary method for fabricating the semiconductor structure without tungsten seam as set forth in  FIG. 1  in accordance with one embodiment of the invention; and 
         FIG. 9  is a schematic, cross-sectional diagram showing an exemplary semiconductor structure without tungsten seam in accordance with another embodiment of the invention. 
     
    
    
     DETAILED DESCRIPTION 
     The present invention has been particularly shown and described with respect to certain embodiments and specific features thereof. The embodiments set forth herein below are to be taken as illustrative rather than limiting. It should be readily apparent to those of ordinary skill in the art that various changes and modifications in form and detail may be made without departing from the spirit and scope of the invention. 
     The term substrate is understood to include semiconductor wafers. The term substrate is also used to refer to semiconductor structures during processing, and may include other layers that have been fabricated thereupon. The term “horizontal” as used herein is defined as a plane parallel to the conventional major plane or surface of the semiconductor substrate, regardless of its orientation. The term “vertical” refers to a direction perpendicular to the horizontal as just defined. Terms, such as “on”, “above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”, “lower”, “over”, and “under”, are defined with respect to the horizontal plane. 
     It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. 
     The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined only by the appended claims, along with the full scope of equivalents to which such claims are entitled. 
     Please refer to  FIG. 1 .  FIG. 1  is a schematic, cross-sectional diagram showing an exemplary semiconductor structure  1  without tungsten seam in accordance with one embodiment of the invention. According to one embodiment, the semiconductor structure  1  may be a metal-oxide-semiconductor (MOS) transistor. For example, the semiconductor structure  1  may be a PMOS transistor or an NMOS transistor according to various embodiments of the invention. 
     As shown in  FIG. 1 , the semiconductor structure  1  includes a substrate  100 . For example, the substrate  100  may be a silicon substrate or any other suitable semiconductor substrates such as SiGe substrate or a silicon-on-insulator (SOI) substrate, but not limited thereto. According to one embodiment, for example, the substrate  100  may be a P-type doped silicon substrate. The substrate  100  may comprise at least a fin structure, but not limited thereto. 
     The semiconductor structure  1  further includes a dielectric layer  110  on a main surface  100   a  of the substrate  100 . According to one embodiment, the dielectric layer  110  may be a spacer layer such as a silicon nitride spacer or a spacer layer comprising multiple dielectric materials such as silicon dioxide, silicon nitride, silicon oxynitride, silicon carbide, or a combination thereof, but not limited thereto. According to one embodiment, a contact etch stop layer (CESL)  112  and an inter-layer dielectric (ILD) layer  114  may be formed on the substrate  100  around the dielectric layer  110 . A lightly doped drain (LDD) region  102  and a source/drain (S/D) region  104  may be formed in the substrate  100 . 
     An opening  111  is formed in the dielectric layer  110 . The opening  111  is a gate trench, which includes a bottom surface and a sidewall surface. The sidewall surface of the opening  111  may be the interior sidewall surface of the dielectric layer  110 . The bottom surface of the opening  11  may be the main surface  100   a  of the substrate. In some cases, an interfacial layer (not explicitly shown in this figure), such as a thin silicon oxide layer, may be formed on the bottom surface of the opening  111 . 
     A high-k dielectric layer  210  is conformally disposed along the sidewall surface and the bottom surface of the opening  111 . The high-k dielectric layer  210  may be composed of a material selected from the group including hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), etc. 
     A metal layer  212  is conformally disposed on the high-k dielectric layer  210  within the opening  111  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the metal layer  212  may comprise a work function metal layer. According to one embodiment, the metal layer  212  may further comprise a bottom barrier layer (not explicitly shown) between the high-k dielectric layer  210  and the work function metal layer. 
     The bottom barrier layer may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. The work function metal layer may comprise a single or a composite layer with desired work function which meets the transistor&#39;s requirement. For example, the work function metal layer may be composed of a material selected from the group including titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl), aluminum titanium nitride (TiAlN), etc. 
     According to one embodiment, the semiconductor structure  1  further includes a top barrier layer (or diffusion barrier layer)  214  that is conformally disposed on the metal layer  212  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the top barrier layer  214  may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. 
     According to one embodiment, the semiconductor structure  1  further includes a nucleation metal layer  216  that is conformally disposed on the top barrier layer  214  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the nucleation metal layer  216  comprises tungsten. 
     According to one embodiment, the semiconductor structure  1  further includes a film-growth retarding layer  218  that is disposed only on an upper surface of the nucleation metal layer  216  within the opening  111 . The film-growth retarding layer  218  comprises tungsten nitride (WN). 
     According to one embodiment, the semiconductor structure  1  further includes a bulk metal layer  220  disposed on the nucleation metal layer  218  and on the film-growth retarding layer  218 . According to one embodiment, the film-growth retarding layer  218  is disposed between an upper portion of the nucleation metal layer  218  and an upper portion of the bulk metal layer  220 . According to one embodiment, the bulk metal layer  220  comprises tungsten. 
     The metal layer  212 , the top barrier layer  214 , the nucleation metal layer  216 , the film-growth retarding layer  218 , and the bulk metal layer  220  constitute a replacement gate structure  200 . According to one embodiment, the replacement gate structure  200  has a flat top surface that is substantially flush with a top surface of the dielectric layer  110  and the ILD layer  114 . It is understood that in some embodiments, a portion of the ILD layer  114  and a portion of the CESL  112  may be removed to form a contact hole that exposes the underlying S/D region  104 . Subsequently, a contact plug (not shown) may be formed within the contact hole. 
       FIG. 2  to  FIG. 8  are schematic, cross-sectional diagram showing an exemplary method for fabricating the semiconductor structure  1  without tungsten seam as set forth in  FIG. 1  in accordance with one embodiment of the invention, wherein like numeral numbers designate like regions, layers, or elements. As shown in  FIG. 2 , first, a substrate  100  is provided. For example, the substrate  100  may be a silicon substrate or any other suitable semiconductor substrates such as SiGe substrate or an SOI substrate, but not limited thereto. According to one embodiment, for example, the substrate  100  may be a P-type doped silicon substrate. The substrate  100  may comprise at least a fin structure, but not limited thereto. 
     A dielectric layer  110  is formed on a main surface  100   a  of the substrate  100 . According to one embodiment, the dielectric layer  110  may be a spacer layer such as a silicon nitride spacer, but not limited thereto. According to one embodiment, a contact etch stop layer (CESL)  112  and an inter-layer dielectric (ILD) layer  114  may be formed on the substrate  100  around the dielectric layer  110 . An LDD region  102  and a S/D region  104  may be formed in the substrate  100 . 
     An opening  111  is then formed in the dielectric layer  110  by removing a dummy poly gate (not shown). The opening  111  is a gate trench, which includes a bottom surface and a sidewall surface. The sidewall surface of the opening  111  may be the interior sidewall surface of the dielectric layer  110 . The bottom surface of the opening  11  may be the main surface  100   a  of the substrate. In some cases, an interfacial layer (not explicitly shown in this figure), such as a thin silicon oxide layer, may be formed on the bottom surface of the opening  111 . 
     The opening  111  has a width W and a height H. According to one embodiment, the width W may range between 20 angstroms and 130 angstroms. For example, for a PMOS transistor, the width W of the opening  111  is about 40 angstroms, while for an NMOS transistor, the width W of the opening  111  is about 100˜130 angstroms. According to one embodiment, the height H of the opening  111  may range between 1200 angstroms and 1800 angstroms, for example, 1500 angstroms. 
     As shown in  FIG. 3 , a high-k dielectric layer  210  is conformally deposited along the sidewall surface and the bottom surface of the opening  111 . The high-k dielectric layer  210  may be composed of a material selected from the group including hafnium oxide (HfO 2 ), hafnium silicon oxide (HfSiO 4 ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al 2 O 3 ), lanthanum oxide (La 2 O 3 ), tantalum oxide (Ta 2 O 5 ), yttrium oxide (Y 2 O 3 ), zirconium oxide (ZrO 2 ), strontium titanate oxide (SrTiO 3 ), zirconium silicon oxide (ZrSiO 4 ), hafnium zirconium oxide (HfZrO 4 ), strontium bismuth tantalate (SrBi 2 Ta 2 O 9 , SBT), lead zirconate titanate (PbZr x Ti 1-x O 3 , PZT), or barium strontium titanate (Ba x Sr 1-x TiO 3 , BST), etc. 
     After depositing the high-k dielectric layer  210 , a metal layer  212  is conformally disposed on the high-k dielectric layer  210  within the opening  111  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the metal layer  212  may comprise a work function metal layer. According to one embodiment, the metal layer  212  may further comprise a bottom barrier layer (not explicitly shown) between the high-k dielectric layer  210  and the work function metal layer. 
     The bottom barrier layer may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. The work function metal layer may comprise a single or a composite layer with desired work function which meets the transistor&#39;s requirement. For example, the work function metal layer may be composed of a material selected from the group including titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), tantalum carbide (TaC), tungsten carbide (WC), titanium aluminide (TiAl), aluminum titanium nitride (TiAlN), etc. 
     The high-k dielectric layer  210  and the metal layer  212  are also deposited on the dielectric layer  110  and the inter-layer dielectric (ILD) layer  114  outside the opening  111 . 
     As shown in  FIG. 4 , a top barrier layer (or diffusion barrier layer)  214  is conformally deposited on the metal layer  212  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the top barrier layer  214  may comprise a single or composite layer comprising tantalum nitride (TaN) or titanium nitride (TiN), etc. 
     As shown in  FIG. 5 , a nucleation metal layer  216  that is conformally disposed on the top barrier layer  214  along the sidewall surface and the bottom surface of the opening  111 . According to one embodiment, the nucleation metal layer  216  comprises tungsten. According to one embodiment, the nucleation metal layer  216  may be deposited by atomic layer deposition (ALD) methods, but not limited thereto. For example, the substrate  100  or wafer may be exposed to tungsten hexafluoride (WF 6 ) and reducing gas such as silane (SiH 4 ) or diborane (B 2 H 6 ) to deposit a tungsten nucleation layer on the top barrier layer  214 . Such tungsten nucleation layer deposition process may be carried out in a CVD tool such as Altus Max system, but not limited thereto. 
     As shown in  FIG. 6 , optionally, a trimming process is performed to partially etch an upper portion of the nucleation metal layer  216 . According to one embodiment, the trimming process comprises a step of etching the upper portion of the nucleation metal layer  216  using an activated fluorine species such as fluorine radicals, but not limited thereto. By partially etching away only an upper portion of the nucleation metal layer  216 , a more vertical sidewall is present in the opening  111  at this stage and a remaining space at the upper end of the opening  111  may be widened. 
     According to one embodiment, the activated fluorine species may be provided by a remote plasma source using a fluorine source gas comprising NF 3  under a power ranging between 800 W and 1800 W and a NF 3  flowrate ranging between 5 sccm and 20 sccm. The nucleation metal layer  216  may be exposed to the activated fluorine species for a time period of about 1˜50 seconds. 
     As shown in  FIG. 7 , subsequently, a film-growth retarding layer  218  is formed only on an upper surface of the nucleation metal layer  216 . The film-growth retarding layer  218  comprises tungsten nitride (WN). To partially form the film-growth retarding layer  218  only on the upper surface of the nucleation metal layer  216 , the nucleation metal layer  216  may be exposed to activated nitrogen species such as nitrogen radicals. The tungsten atoms react with the nitrogen radicals to form the tungsten nitride. According to one embodiment, the activated nitrogen species may be provided by a remote plasma source using a nitrogen source gas such as N 2  under a power of about 1800 W and a N 2  flowrate ranging between 1 sccm and 5 sccm. The nucleation metal layer  216  may be exposed to the activated nitrogen species for a time period of about 5˜10 seconds. 
     Subsequently, a bulk metal layer  220  is deposited on the nucleation metal layer  218  and on the film-growth retarding layer  218 . According to one embodiment, the film-growth retarding layer  218  is disposed between an upper portion of the nucleation metal layer  218  and an upper portion of the bulk metal layer  220 . According to one embodiment, the bulk metal layer  220  comprises tungsten. 
     Due to the presence of the film-growth retarding layer  218  on the upper surface of the nucleation metal layer  216 , the tungsten deposition is basically a bottom-up deposition/growth process. The tungsten deposition/growth rate on the surface of the nucleation metal layer  216  at the bottom surface of the opening  111  is higher than the tungsten deposition/growth rate at the upper surface of the opening  111  with the film-growth retarding layer  218 . Therefore, no seam or void is observed in the opening  111  after the bulk metal layer  220  is deposited. 
     According to one embodiment, the bulk metal layer  220  may be deposited by chemical layer deposition (CLD) methods, but not limited thereto. For example, the substrate  100  or wafer may be exposed to tungsten hexafluoride (WF 6 ) and reducing gas such as hydrogen (H 2 ) to deposit a bulk tungsten layer on the nucleation metal layer  216 . Such bulk tungsten layer deposition process may be carried out in a CVD tool such as Altus Max system, but not limited thereto. 
     As shown in  FIG. 8 , a chemical mechanical polishing (CMP) process is then performed to polish the bulk metal layer  220 , the film-growth retarding layer  218 , the nucleation metal layer  216 , the top barrier layer  214 , the metal layer  212 , and the high-k dielectric layer  210  outside the opening  111  to thereby form a flat top surface. Subsequently, the ILD layer  114  and a portion of the CESL  112  may be removed to form a contact hole (not shown) that exposes the underlying S/D region  104 . Subsequently, a contact plug (not shown) may be formed within the contact hole. 
     Since the presence of the film-growth retarding layer  218  overlying the dielectric layer  110  and the ILD layer  114 , the thickness of the bulk tungsten layer  220  deposited outside the opening  111  may be reduced. Therefore, the processing time for the CMP process can also be reduced. This is beneficial because the throughput of the wafer fabrication can be increased. 
       FIG. 9  is a schematic, cross-sectional diagram showing an exemplary semiconductor structure  3  without tungsten seam in accordance with another embodiment of the invention. As shown in  FIG. 9 , the semiconductor structure  3  includes a substrate  300  having thereon a dielectric layer  310 . An opening  311  such as a contact hole or via hole is formed in the dielectric layer  310 . The opening  311  comprises a bottom surface  311   a  and a sidewall surface  311   b . A diffusion barrier layer  414  is conformally disposed along the sidewall surface  311   a  and the bottom surface  311   b  of the opening  311 . A nucleation metal layer  416  is conformally disposed on the diffusion barrier layer  414 . A bulk metal layer  418  is deposited on the nucleation metal layer  420  and fills up the opening  111 . A film-growth retarding layer  418  is disposed between an upper portion of the nucleation metal layer  416  and an upper portion of the bulk metal layer  420 . 
     According to another embodiment, the opening  111  is a contact hole opening. The dielectric layer  310  may be an inter-layer dielectric (ILD) layer such as silicon oxide, but not limited thereto. A conductive region  302  may be disposed in the substrate  300  and the diffusion barrier layer  414  is in direct contact with the conductive region  302 . 
     According to another embodiment, the diffusion barrier layer comprises titanium nitride. According to another embodiment, the nucleation metal layer comprises tungsten. According to another embodiment, the bulk metal layer comprises tungsten. According to another embodiment, the film-growth retarding layer comprises tungsten nitride. According to another embodiment, the film-growth retarding layer is disposed only on an upper surface of the nucleation metal layer within the opening. 
     Various processes may be used to form the nucleation metal layer  416 , including but not limited to, chemical vapor deposition (CVD) processes, atomic layer deposition (ALD) processes, and pulsed nucleation layer (PNL) deposition processes. 
     Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.