Patent Publication Number: US-11038030-B2

Title: Transistor having low capacitance field plate structure

Description:
CROSS REFERENCE TO RELATED APPLICATION 
     This is a Divisional application of application Ser. No. 15/791,771 filed Oct. 24, 2017 which application is hereby incorporated herein by reference in its entirety. 
    
    
     TECHNICAL FIELD 
     This disclosure relates generally to transistors having field plate structures and more particularly to transistors having low capacitance field plate structures. 
     BACKGROUND 
     As is known in the art, field plate structures are used in some transistors to improve the efficiency of such transistors in many high power applications. One such field plate structure used with Field Effect Transistors (FETs) is a so-called source connected field plate (SCFP) structure having one end connected to the source, typically referenced to ground potential, through a SCFP connector section and a second end providing a SCFP region disposed over a region between the gate and the drain but separated or spaced from the drain. Two types of such source connected field plate structures are shown in:  FIGS. 1A and 1B ; and  2 A and  2 B, respectively; see for example U.S. Pat. Nos. 7,915,644 and 7,893,500, respectively. In both types, the SCFP structures include one end connected to the source through the SCFP connector section and a second end providing the SCFP region disposed over a region between the gate and the drain, it being noted that the end of the SCFP is spaced from the drain. That is, the two types of FETs differ in that with the type shown in  FIGS. 1A and 1B  the SCFP is connected to the source by a U-shaped SCFP connector section that does not pass over the semiconductor region, or active region, here for example, aluminum gallium arsenide (AlGaN) which may be a mesa on the substrate; whereas in the type shown in  FIGS. 2A and 2B  the SCFP structure is connected to the source by a SCFP connector section that does pass, as a canopy, over the semiconductor (or active region). With either type there is a continuous, solid dielectric structure of the same material that extends from the terminating end of the SCPF structure and the drain. Here, the FETs are adapted for use in high power, microwave frequency applications; here GaN FETs having a GaN buffer with an AlGaN semiconductor layer (sometimes referred to as the active region) as shown in  FIGS. 1A, 1B and 2A and 2B . 
     SUMMARY 
     In accordance with the present disclosure, a Field Effect Transistor (FET) is provided having: a first electrode structure, a second electrode structure; a gate electrode structure disposed laterally along a surface of a semiconductor for controlling a flow of carriers between the first electrode structure and the second electrode structure; and a field plate structure: having one end connected to the first electrode structure and having a second end disposed between the gate electrode structure and the second electrode structure, the second end being separated from the second electrode structure by a gap. A dielectric structure is disposed over the semiconductor, having: a first portion disposed under the second end of the field plate structure; and, a second, thinner portion under the gap. 
     In one embodiment, the first electrode structure is as source electrode structure and the second electrode structure is a drain electrode structure. 
     In one embodiment, the Field Effect Transistor (FET) includes a second gap in a third portion of the dielectric structure, the second gap being disposed between the first electrode structure and the gate electrode structure; and, wherein third portion of the dielectric structure is thinner under the second gap than the first portion of the dielectric structure. 
     In one embodiment, the first portion of the dielectric structure includes: a bottom layer; an intermediate layer disposed on the bottom layer; and an upper layer disposed on the intermediate layer. The second portion of the dielectric layer comprises an extended portion of the bottom layer. The upper layer and the bottom layer are of the same material. The intermediate layer is a material different from the upper layer and the bottom layer. 
     In one embodiment, the intermediate layer is an etch stop layer. 
     In one embodiment, the bottom layer and the upper layer have an etch rate to a predetermined etchant at least an order of magnitude greater than the etch rate of the intermediate layer. 
     In one embodiment, the intermediate layer has a etch rate faster that the etch rate of the bottom layer to an etchant different from the above-mentioned predetermined etchant. 
     In one embodiment, the intermediate layer is in direct contact with the bottom layer and the upper layer is in direct contact with the intermediate layer and the bottom layer and upper layer are of the same material. 
     In one embodiment, a method is provided for forming a Field Effect Transistor (FET). The method includes: providing a structure comprising: a first electrode structure; a second electrode structure; a gate electrode structure disposed on a surface of a semiconductor for controlling a flow of carriers between the first electrode structure and the second electrode structure; and a field plate structure connected to the first, and disposed over a region between the first electrode structure and the gate electrode structure; and a dielectric structure extending laterally over the surface of the semiconductor between the first electrode structure and the second electrode structure, the dielectric structure comprising: a bottom layer; an intermediate layer disposed in direct contact with the bottom layer; and an upper layer disposed in direct contact with the intermediate, etch stop, layer wherein the bottom layer and upper layer are of the same material; applying a first etchant to a portion of the dielectric structure disposed between an edge of the field plate structure and the second electrode structure, such first etchant removing the upper layer and stopping at an exposed portion of the etch stop layer producing a gap between the outer edged of the field plate structure and the second electrode structure. 
     In one embodiment, the method includes applying a second etchant, different from the first etchant to the exposed portion of the etch stop layer, such etchant removing the etch stop layer and stopping at the bottom layer. 
     With such an arrangement, a FET with a SCFP structure is provided having lower dielectric loading and reduced parasitic capacitance and thereby provides higher efficiency under high voltage operation. 
     The details of one or more embodiments of the disclosure are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the disclosure will be apparent from the description and drawings, and from the claims. 
    
    
     
       DESCRIPTION OF DRAWINGS 
         FIGS. 1A and 1B  simplified, diagrammatical plan and cross sectional sketches of one type of Source Connected Field Plate Field Effect Transistor according to the PRIOR ART; 
         FIGS. 2A and 2B  are simplified, diagrammatical plan and cross section sketches of a type of Source Connected Field Plate Field Effect Transistor according to the PRIOR ART; 
         FIG. 3A  is a simplified, diagrammatical plan view sketch of a Source Connected Field Plate Field Effect Transistor according to the disclosure; 
         FIG. 3B  is a simplified, diagrammatical cross sectional sketch of the Source Connected Field Plate Field Effect Transistor of  FIG. 3A , such cross section being taken along line  3 B- 3 B of  FIG. 3A ; 
         FIGS. 4A-4N  are simplified, diagrammatical cross sectional sketches of the Source Connected Field Plate Field Effect Transistor of  FIGS. 3A and 3B  at various stages in the fabrication thereof according to the disclosure; 
         FIGS. 4J ′,  4 K′ and  4 L′ are simplified, diagrammatical cross sectional sketches of the Source Connected Field Plate Field Effect Transistor of  FIGS. 3A and 3B  at various stages in the fabrication thereof according to another embodiment of the disclosure 
         FIG. 5A  is a simplified, diagrammatical plan view sketch of another type of Source Connected Field Plate Field Effect Transistor according to the disclosure; 
         FIG. 5B  is a simplified, diagrammatical cross sectional sketch of the Source Connected Field Plate Field Effect Transistor of  FIG. 5A , such cross section being taken along line  5 B- 5 B of  FIG. 5A ; 
         FIG. 5C  is a simplified, diagrammatical cross sectional sketch of the Source Connected Field Plate Field Effect Transistor of  FIG. 5A , such cross section being taken along line  5 C- 5 C of  FIG. 5A ; 
         FIG. 5D  is a simplified, diagrammatical cross sectional sketch of the Source Connected Field Plate Field Effect Transistor of  FIG. 5A , such cross section being taken along line  5 D- 5 D of  FIG. 5A ; and 
         FIGS. 6A-6B  are simplified, diagrammatical cross sectional sketches of the Source Connected Field Plate Field Effect Transistor of  FIGS. 5A and 5B  at various stages in the fabrication thereof according to the disclosure. 
     
    
    
     Like reference symbols in the various drawings indicate like elements. 
     DETAILED DESCRIPTION 
     Referring now to  FIGS. 3A and 3B , a Source Connected Field Plate (SCFP) Field Effect Transistor (FET)  10  is shown having substrate  11 , here for example Silicon Carbide, having a Gallium Nitride (GaN) buffer layer  12  with a semiconductor layer  14  (the active region), here, for example, Aluminum Gallium Nitride (AlGaN) mesa on an upper surface of the substrate  11 . It should be understood that other materials may be used for the substrate  11 . Source, gate, and drain electrode structures  16 ,  18  and  20 , respectively, are disposed on a surface of the semiconductor layer  14 , as shown. The source and drain electrode structures  16  and  20 , have lower portions  16   a  and  20   a , respectively, in ohmic contact with the semiconductor layer  14  and upper interconnect layers  16   b ,  20   b , respectively on the lower portions  16   a  and  20   a , respectively, as shown. The gate electrode structure  18  has a lower portion  18   a  in Schottky contact with the semiconductor layer  14  and an upper portion  18   b  shaped to form a T-shaped or gamma-shaped gate electrode structure  18 . The gate electrode controls the flow of carriers between the source electrode structure  16  and the drain electrode structure  20 . The gate electrode  18  is connected to a gate pad  19 , through a conductive via  19   a  as shown, such via  19   a  being formed with upper interconnect layers  16   b ,  20   b.    
     A field plate structure  22 , here a source connected field plate (SCFP) structure, is electrically connected to the source electrode structure  16  through a SCFP connector section  23  and extends has over a portion of the gate electrode structure  18  of the FET  10  as shown. The field plate structure  22 , has an outer SCFP region portion (sometimes also referred to herein as a field plate region)  24  disposed over a region  25  of the semiconductor  14  between the gate electrode structure  18  and the drain electrode structure  20  to provide a SCFP region  24 , as shown. 
     A dielectric structure  30  has: a pair of lower dielectric layers  32 ,  34 , here for example, silicon nitride, extending laterally over the surface of the semiconductor  14  between the source electrode structure  16  and the drain electrode structure  20 ; an etch stop layer  36 , here for example aluminum oxide (Al 2 O 3 ) disposed over layer  34 . It should be understood that other materials may be used for layers  32 ,  34  and  36 . For example, layers  32  and  34  may be aluminum oxide (Al 2 O 3 ) in which case etch stop layer  36  may be, for example, silicon dioxide (SiO 2 ). The etch stop layer  36  has a gap  37  therein over the region R, as shown in  FIG. 3B . An upper dielectric layer  38 , here the same material as used for dielectrics layer  32 ,  34  is disposed over the etch stop layer  36 , having the gap  37  therein, as shown. It is noted that the same metal  22   a  used to form the field plate structure  22  is disposed on the upper portion of the source electrode structure  16  and the upper portion of the drain electrode structure  20 ; however while a portion of the metal  22   a  is disposed on and hence connected to the source electrode structure  16 , (thereby connecting the SCFP structure  22  to the source electrode structure  16 ), the portion of metal  22   a  on the drain electrode structure  20  is electrically isolated from the portion of the metal on the source electrode structure  16  by the gap  37 . It is noted that the SCFP structure  22  has the SCFP connector section, such section  23  having, as noted above one end E 1  connected to the source electrode structure  16  and a second end E 2  connected to the SCFP region  24 ; the SCFP region  24  being over a region between the gate electrode structure  18  and the drain electrode structure  20  but separated or spaced from the drain electrode structure  20  by a gap provide by the region, R, as shown in  FIG. 3B . 
     Referring now to  FIGS. 4A-4N  the process for forming the Source Connected Field Plate Field Effect Transistor  10  of  FIGS. 3M and 3B  will be described. Referring to  FIG. 4A , a structure is provided having the substrate  11 , semiconductor layers  12  and  14 , and the lower portion  16   a ,  20   a  of the source and drain electrode structures  16 ,  20  formed thereon using any conventional process. 
     Referring to  FIG. 4B , the dielectric layer  32  is deposited with uniform thickness over the lower portions  16   a ,  20   a  of the source and drain electrode structures  16 ,  20  as shown in  FIG. 3B . 
     Referring now to  FIG. 4C , an opening  33  is formed through a portion of the layer  32  where the gate electrode structure  18  is to be formed using any conventional lithographic-etching process. 
     Referring to  FIG. 4D , a layer of Schottky contact metal, here for example a stack of nickel, then platinum then gold (Ni/Pt/Au) is deposited with uniform thickness over the surface of the structure shown in  FIG. 4C  with a portion of such metal passing through the opening  33  onto the exposed portion of the semiconductor layer  14 . The structure is then processed in any conventional manner to form a Schottky contact with the Schottky contact metal and the semiconductor  14  to thereby form the gate electrode structure  18 . Residual portions of the Schottky contact metal are removed using any process, such as a lift-off process. 
     Referring to  FIG. 4E , the dielectric layer  34  is formed with uniform thickness over the structure, as shown. 
     Referring now to  FIG. 4F , apertures  39  are formed through dielectric layers  32  and  34  over the lower portions  16   a ,  20   a  of the source and drain electrodes structures  16 ,  20 , as shown. 
     Referring now to  FIG. 4G , the upper portions of the source and drain electrodes  16   b  and  20   b  respectively are formed as shown using any conventional process. 
     Referring now to  FIG. 4H , the dielectric etch stop layer  36  is deposited with uniform thickness over the structure as shown. In the case where layers  32  and  34  are silicon nitride, the etch stop layer  36  is aluminum oxide (Al 2 O 3 ) and for the case where layers  32  and  34  are aluminum oxide (Al 2 O 3 ), the etch stop layer  36  is silicon dioxide (SiO2). 
     Referring to  FIG. 4I , the dielectric layer  38  is deposited with uniform thickness over the etch stop layer  36 , as shown. In the case where the etch stop layer  36  is aluminum oxide, dielectric layer  38  is, for example, silicon nitride and in the case where the etch stop layer  36  is silicon dioxide, the dielectric layer  38  would be, for example, aluminum oxide. 
     Referring now to  FIG. 4J , apertures  55  are formed through layers  38  and  36  using photolithographic-etching processing. In the case where layers  32  and  34  are silicon nitride and the etch stop layer  36  is aluminum oxide (Al 2 O 3 ), the etchant for layers  32  and  34  is, for example, a fluorine based etchant for etching the silicon nitride layers  32  and  34 , such etching stopping at the aluminum oxide layer  36  and for the case where layers  32  and  34  are aluminum oxide (Al 2 O 3 ) and the etch stop layer  36  is silicon dioxide (SiO2), the etchant for layers  32  and  34  is for example, a chorine based etchant or ammonia hydroxide, such etching stopping at the silicon dioxide etch stop layer  36 . Thus, in either case, the etch stop layer  36  acts as an etch stop because it etches at a rate at least an order of magnitude slower than the etchant used for etching layers  32  and  34 . It should be noted that here the upper portions  16   b ,  20   b  of the source and drain electrode structures  16 ,  20  is, for example. a tri-metal layer of titanium, then platinum, then gold (Ti/Pt/Au) or a bi-metal layer of Ti/Au so that the upper portions  16   b ,  20   b  of the source and drain electrode structures  16 ,  18  serve as an etch stop layer in this process step, thereby exposing the upper portions  16   b ,  20   b  of the source and drain electrode structures  16 ,  20 . 
     Referring now to  4 K, a photoresist layer  21  is patterned over the surface of the structure, exposing regions of the surface of the structure where the metal layer  22   a  is to be formed on the upper portion of the source electrode structure  16  and drain electrode structure  20  and where the field plate structure  22  is to be formed. Thus, the layer  22   a  is deposited using, for example, electron-beam evaporation, over the photoresist  21  and onto portions of the structure exposed by the photoresist  21  layer, as shown. 
     Referring again to  FIG. 4K , the photoresist  21  is removed thereby forming the structure shown in  FIG. 4L  using a conventional lift-off process with the gap  37  ( FIGS. 4A and 4B ) being formed between the outer edge or end E 2  of the SCFP region  24  of the field plate structure  22  and the drain electrode  20 . It is noted that the upper portion of the field plate structure  22  extends along the surface of the dielectric layer  38  from above the source electrode structure  16  and terminates at the outer edge or end E 2  of the SCFP region  24 . Thus, the field plate structure  22  does not extend above a region R between the gate electrode structure  18  and the drain electrode structure  20 . 
     Referring to  FIG. 4M , a photoresist mask  61  is formed over the structure with an opening  63  therein over the region R as shown using any conventional process to expose the portion of the dielectric layer  38  in the region R. The exposed portion of layer  38  is selectively etched away. In the case where the layer  38  is silicon nitride and the etch stop layer  36  is Aluminum oxide, the etchant used to remove the dielectric layer  38  is a fluorine based etchant and in the case where layer  38  is aluminum oxide the etchant is a chlorine based etchant or ammonia hydroxide. 
     Next the etch stop layer  36  is selectively removed, as shown in  FIG. 4N , (here using a chlorine or ammonium hydroxide based etchant for the an aluminum oxide etch stop layer  36  in the case where layer  38  is silicon nitride or using a fluorine based etchant in the case where the etch stop layer  38  is silicon dioxide and layer  38  is aluminum oxide) below the region R ( FIG. 4M ); it being noted that the etch rate of the aluminum oxide etch stop layer  36  is much slower to the chlorine or ammonium hydroxide based etchant than to a silicon nitride layer  38  and the chlorine or ammonia hydroxide etchant is much slower to the silicon dioxide etch stop layer  36  than to an aluminum oxide layer  38 . The mask  61  is then removed completing the Source Connected Field Plate Field Effect Transistor  10  shown in  FIGS. 3A and 3B . 
     Referring now to  FIGS. 4J ′- 4 L′, an alternative process is described. Here, after forming the structure shown in  FIG. 4I , an aperture  55 ′ is formed at the same time apertures  55  are formed, as shown in  FIG. 4J ′. The photoresist material  21  is here patterned as shown in  FIG. 4K ′ over the surface of the structure as shown in  FIG. 4K ′ exposing regions of the surface of the structure where the metal layer  22   a  is to be formed on the upper portion of the source electrode structure  16  and drain electrode structure  20 , and where the field plate structure  22  is to be formed, as shown in  FIG. 4K ′. Thus, the layer  22   a  is deposited over the photoresist  21  and onto portions of the structure exposed by the photoresist  21  layer, as shown. Next, the photoresist layer  21  is removed, as shown in  FIG. 4L ′ completing the Source Connected Field Plate Field Effect Transistor  10  shown in  FIGS. 4A and 4B . 
     Another type of SCFP FET structure  10 ′, here a U-shaped SCFP where the SCFP connector  23  is off of the active region mesa  14 , is shown in  FIGS. 5A, 5B, 5C and 5D . Here, after forming the structure shown in  FIG. 4J , the metal layer  22   a  is deposited over the structure and patterned as shown in  FIG. 5A  using any conventional lift-off process such as described above in connection with  FIGS. 4K and 4K ′. It is noted that the upper, connector section of the SCFP structure  22  extends along the surface of the dielectric layer  38  from above the source electrode structure  16 , but is outside of the active region  14 , (that is off of the mesa  14 ; or to put it another way, the SCFP connector section  23  of the SCFP structure  22  is not vertically above the semiconductor layer  14 ,  FIG. 5B ), and terminates at the end  27 ). Thus, the field plate structure  22  does not extend above a region R between the gate electrode structure  18  and the drain electrode structure  20 . Here again the gate  18  is connected to the gate pad  19  through a conductive via  19   a , as shown in  FIG. 5D . 
     Referring also to  FIGS. 6A and 6B ; here in addition to the gap  37  being formed over the Region R through layers  38 , and  34  as described above in connection with  FIGS. 4M and 4N , a second gap  37 ′; is formed, in like manner, simultaneously with gap  37  between the source  16  and the gate  18 , as shown in  FIG. 5B . It is also noted that here an additional gap  37 ′ ( FIGS. 5A and 5B ); is formed over the semiconductor layer  16  between the source electrode structure as shown, using the same etching process described above in connection with  FIGS. 4M and 4N  to form gap  37 . Thus both gap  37  and gap  37 ′ terminate at the silicon nitride layer  34 , as shown in  FIGS. 5A and 5B . In this regard, the gap  37 ′ is formed through the dielectric layer  38  and through the etch stop layer  36  in the region over the mesa or semiconductor layer  14  and does not extend in the region outside of the mesa or semiconductor layer  14  which supports the SCFP connection section  23  of the SCFP structure  22 . Thus, the total thickness of stacks having layers  32  and  34  under the gap  37  and under gap  37 ′ is less than the thickness a stack having layers  32 ,  34 ,  36  and  38 . In other words, the gaps  37  and  37 ′ have reduced the thickness of the dielectric structure between the source  16  and the gate  18  and also reduced the thickness of the dielectric structure the between the gate  18  and the drain  20 . 
     A number of embodiments of the disclosure have been described. Nevertheless, it will be understood that various modifications may be made without departing from the spirit and scope of the disclosure. For example, field plates may be connected to the drain of a FET. Accordingly, other embodiments are within the scope of the following claims.