Patent Publication Number: US-6983023-B2

Title: Data transmission system of directional coupling type using forward wave and reflection wave

Description:
CROSS-REFERENCES TO RELATED APPLICATIONS 
     This application relates to applications U.S. Ser. No. 09/297,359 filed on Apr. 30, 1999 entitled “GAP-COUPLING TYPE BUS SYSTEM” by Osaka et al, U.S. Ser. No. 09/429,441 filed on Oct. 28, 1999 entitled “DIRECTIONAL BUS SYSTEM USING PRINTED BOARD” by Osaka et al, and U.S. Ser. No. 09/569,876 filed on May 12, 2000 entitled “DIRECTIONAL COUPLING MEMORY MODULE” by Osaka et al all assigned to the assignee of the present application. The disclosures of the above applications are incorporated by reference into that of the present application. 
     BACKGROUND OF THE INVENTION 
     The present invention relates to techniques for signal transmission between devices such as multiprocessors or memories (for example, digital circuits constructed of CMOS&#39;s or between their functional blocks) in an information processing apparatus and more particularly, to a technique of increasing the speed of bus transmission in which a plurality of devices are connected to the same transmission line and data transfer is carried out between the devices. Especially, the present invention is concerned with a bus for connecting a plurality of memory modules and a memory controller and a system using the bus. 
     As a bus system connected with many nodes to perform high-speed data transfer, a non-contact bus wiring line has been known as disclosed in U.S. Pat. No. 5,638,402 (JP-A-7-141079). A fundamental system of this type is shown in  FIG. 2 . In the system, data transfer between two nodes is effected using a crosstalk generation portion or directional coupler having a length of L. More particularly, in the known transfer technique, data transfer between a bus master  10 - 1  and slaves  10 - 2  to  10 - 3  is carried out using crosstalk between two lines, that is, between a terminated wiring line  1 — 1  and terminated wiring lines  1 - 2  and  1 - 3  each having a length of L. This is suited to one to multiple inter-transfer such as data transfer between the single bus master  10 - 1  and the plural slaves  10 - 2  and  10 - 3  and is suitably applied to data transfer between a memory controller and memories. 
     In the prior art disclosed in U.S. Pat. No. 5,638,402 (JP-A-7-141079) assigned to the present assignee, however, the line length L occupied by the directional coupler determines the pitch between the bus slaves  10 - 2  and  10 - 3 . In  FIG. 2 , the wiring length occupied by the two bus slaves DRAM&#39;s  10 - 1  and  10 - 2  is 2L at the minimum and the pitch between the DRAM&#39;s amounts up to L. 
     A simple way to increase the density in the system, that is, to decrease the pitch between the DRAM&#39;s is to shorten the wiring length L of the directional coupler but this expedient leads to a decrease in transmission efficiency or coupling degree and therefore, the pitch cannot be reduced to below a predetermined value, for example, 30 mm. 
     SUMMARY OF THE INVENTION 
     A first object of the present invention is to narrow the pitch between memories such as DRAM&#39;s with a view to packaging a memory system in high density. 
     A second object of the present invention is to solve a problem that the latency in write data is long in a memory module system using a DQS signal for latching a DQ signal, for example, a DDR-SDRAM (Double Data Rate Synchronous DRAM). 
     A SSTL (Stub Series Terminated Logic) interface adopted in the DDR-SDRAM has a HiZ state identical to a termination voltage of Vtt and a reference voltage Vref of a receiver is approximately equal to the termination voltage Vtt. Here, the HiZ state means a state in which the driver of the interface does not deliver data, that is, a high-impedance state. Therefore, transition from HiZ state to L (low) state or from HiZ state to H (high) state cannot be recognized (here, L state and H state are called with respect to Vtt). Accordingly, before data transfer, a strobe signal is once shifted from HiZ state to L state and thereafter, data transfer is caused to proceed. This portion is especially called a preamble and because of the presence of the preamble, the write access time is prolonged. 
     Further, when the bus uses the SSTL driver and the directional coupler, that is, when the main line and the sub coupling lines as shown in  FIG. 2  are terminated, the amplitude of the preamble portion is half the amplitude of data transfer. In other words, the signal amplitude during the transition of the drive amplitude from HiZ state to L state or from HiZ state to H state is about half the signal amplitude during the transition of the drive amplitude from L state to H state or vice versa. Consequently, in the preamble portion, the amplitude inputted to the receiver during write data and read data is half the amplitude in the data portion and so a shortage of sensitivity of the receiver results, making it necessary to assure the signal amplitude. 
     As described above, in case the SSTL driver is used, the strobe signal must be once shifted from HiZ state to L state to assure the signal amplitude and as a result, the access time is prolonged during memory write. 
     In order to accomplish the first object, according to one embodiment of the present invention, a driver for signal transmission of a main controller (MC)  10 - 1  has an impedance equal to a characteristic impedance Zo of a wiring line (main line)  1 — 1  connected to the driver so that re-reflection at the driver may be avoided. Further, the main line has a remote or far end that is an open-ended to cause a signal to undergo total reflection at the open-end. A directional coupler formed of two parallel wiring lines has, as named so, a characteristic for discriminating signals in signal transmission direction. More particularly, in case a signal propagates on the main line, representing one line of the directional coupler, and induces a signal in the other line (sub coupling line) of the directional coupler, the signal is induced only at a terminal close to the MC when a forward wave travels on the main line in the leaving direction as viewed from the MC  10 - 1  but the signal is induced only at a terminal remote from the MC when a reflection wave returns on the main line to approach the MC. 
     The directional coupler can pick up separately crosstalk signals due to the forward wave and reflection wave of the signal propagating on the main line at the opposite ends of the sub coupling line, respectively. Therefore, two memory modules can be connected to one coupler. In other words, two memories can be connected within the line length of the directional coupler to thereby double the packaging density. 
     When the main line is folded or turned around, directional couplers can be formed in different layers, so that the directional couplers can overlap each other to further halve the pitch between the memories. Consequently, the pitch between the memory modules can be narrowed to a great extent as compared to that in the prior art and advantageously, the packaging area can be reduced. 
     In order to accomplish the second object, according to another embodiment of the present invention, the memory controller has a signal for data transfer that is binary and has, on the side near the memory controller, its impedance equal to the characteristic impedance of the wiring line. More particularly, a HiZ state in which data is not transferred and a H state are at the same potential and the MC is driven through the impedance equal to the characteristic impedance of the wiring line. In other words, the input impedance equals the characteristic impedance. During L state of data, the L signal is driven through the same impedance as the characteristic impedance. In this manner, the reflection wave can be absorbed. 
     When the signal is driven from HiZ state to L state and from H state to L state, the amplitude remains unchanged and as a result, signals passing through the coupler during two transfer operations can have the same amplitude. Thus, during any transition of signal, the signal amplitude remains unchanged and the preamble is unneeded. Because the preamble is unnecessary, the memory access time can be shortened and the bus utilization efficiency can be raised to thereby improve the system performance. 
     Other objects, features and advantages of the present invention will become apparent from the following description of the embodiments of the invention-taken in conjunction with the accompanying drawings. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
         FIG. 1  is a schematic block circuit diagram for explaining a first embodiment of a bus system according to the present invention. 
         FIG. 2  is a schematic block circuit diagram showing an example of construction of the prior art system. 
         FIG. 3  is a schematic block circuit diagram for explaining the first embodiment. 
         FIG. 4  is a timing chart of write from a MC to a DRAM in the first embodiment. 
         FIG. 5  is a timing chart of read from a DRAM  10 - 1  to the MC in the first embodiment. 
         FIG. 6  is a timing chart of read from a DRAM  10 - 2  to the MC in the first embodiment. 
         FIG. 7  is a sectional diagram showing a first embodiment of wiring mode according to the invention. 
         FIG. 8  shows an equivalent circuit for write simulation from the MC to the DRAM in the first embodiment of the bus system. 
         FIG. 9  is a time chart showing write data waveforms from the MC to the DRAM in the first embodiment of the bus system. 
         FIG. 10  shows an equivalent circuit for read simulation from the DRAM  10 - 1  to the MC in the first embodiment of the bus system. 
         FIG. 11  is a time chart showing read data waveforms from the DRAM  10 - 1  to the MC in the first embodiment of the bus system. 
         FIG. 12  is a time chart showing read data waveforms from the DRAM  10 - 2  to the MC in the first embodiment of the bus system. 
         FIG. 13  is a circuit diagram showing an I/O circuit of the MC in the first embodiment of the bus system. 
         FIG. 14  is a circuit diagram showing an I/O circuit of the DRAM in the first embodiment of the bus system. 
         FIG. 15  is a sectional diagram showing a first embodiment of packaging according to the invention. 
         FIG. 16  is a sectional diagram showing a second embodiment of packaging. 
         FIG. 17  is a sectional diagram showing a second embodiment of the wiring mode. 
         FIG. 18  is a sectional diagram showing a third embodiment of the wiring mode. 
         FIG. 19  is a schematic circuit diagram for explaining a second embodiment of the bus system according to the invention. 
         FIG. 20  is a schematic block circuit diagram of a third embodiment of the bus system. 
         FIG. 21  is a schematic block circuit diagram of a fourth embodiment of the bus system. 
         FIG. 22  is a timing chart of memory write in the prior art DDR-SDRAM. 
         FIG. 23  is a timing chart of memory write using the first embodiment of the bus system according to the invention. 
         FIG. 24  is a circuit diagram of a DRAM interface capable of doubling the input amplitude. 
         FIG. 25  is a timing chart of memory write to the DRAM of  FIG. 24 . 
         FIG. 26  is a block diagram showing an embodiment in which the bus system of the invention is applied to an information processing system provided with a memory bus using a main line having an open-end/short-circuit end. 
         FIG. 27  is a block diagram showing another embodiment in which the bus system is applied to an information processing system having a cache memory bus using a main line having open-end/short-circuit end. 
         FIG. 28  is a schematic block circuit diagram for explaining a fifth embodiment of the bus system according to the invention. 
         FIG. 29  is a timing chart of write from MC  10 - 1  to DRAM&#39;s  10 - 2  and  10 - 3  in the fifth embodiment. 
         FIG. 30  is a timing diagram of read from the DRAM  10 - 2  to the MC in the fifth embodiment. 
         FIG. 31  is a timing chart of read from the DRAM  10 - 3  to the MC in the fifth embodiment. 
         FIG. 32  is a time chart showing waveforms of write data from the MC  10 - 1  to the DRAM&#39;s  10 - 2  and  10 - 3  in the fifth embodiment. 
         FIG. 33  is a time chart showing waveforms of read data from the DRAM  10 - 2  to the MC in the fifth embodiment. 
         FIG. 34  is a sectional diagram showing board packaging in the fifth embodiment. 
         FIG. 35  is a sectional diagram showing board packaging (in the case of packaging a terminated board) in the fifth embodiment. 
         FIG. 36  is a schematic block diagram for explaining a sixth embodiment of the bus system according to the invention. 
         FIG. 37  is a schematic block diagram for explaining a seventh embodiment of the bus system according to the invention. 
         FIG. 38  is a schematic block diagram for explaining an eighth embodiment of the bus system according to the invention. 
         FIG. 39  is a time chart showing simulation waveforms (memory write) in the eighth embodiment. 
         FIG. 40  is a time chart showing simulation waveforms (memory read) in the eighth embodiment. 
         FIG. 41  is table showing input impedances of the MC  10 - 1 , DRAM  10 - 2  and DRAM  10 - 3  in the eighth embodiment. 
         FIG. 42  is a schematic block circuit diagram showing still another embodiment of the I/O circuit. 
         FIG. 43  is a sectional diagram showing still another embodiment in which the bus system of the invention is applied to a multi-chip module. 
     
    
    
     DETAILED DESCRIPTION OF THE EMBODIMENTS 
     A first embodiment of a bus system according to the invention will be described with reference to  FIG. 1 . 
     The bus system comprises an LSI chip  10 - 1  having a memory controller control mechanism (hereinafter simply referred to as a MC (memory controller)  10 - 1 ) and memory chips  10 - 2  to  10 - 5  (hereinafter simply referred to as DRAM&#39;s  10 - 2  to  10 - 5 ). 
     The MC  10 - 1  operates to read/write data from/to the DRAM&#39;s  10 - 2  to  10 - 5 . Wiring lines  1 — 1  to  1 - 3  for read/write data transfer are provided, among which the line  1 — 1  connected to the MC  10 - 1  is especially called a main line. The line  1 - 2  includes three parts including a sub coupling line having a length of L and wired in parallel with the main line  1 — 1  to form a directional coupler and two stub lines led from both ends of the sub coupling line physically vertically thereof. In  FIG. 1 , the L-length sub coupling lines of lines  1 - 2  and  1 - 3  cooperate with the main line  1 — 1  to form directional couplers Cl and C 2 , respectively. Therefore, each of the directional couplers does not include the led stub lines. 
     Data signal propagation between the MC  10 - 1  and each of the DRAM&#39;s  10 - 2  to  10 - 5  is carried out by means of the respective directional couplers C 1  and C 2  indicated by inverted “C” mark. These directional couplers are equivalent to those described in JP-A-7-141079. According to the literature, data transfer between two nodes is carried out using crosstalk that represents coupling between two parallel wiring lines (directional coupler). More particularly, data transfer between the MS (bus master)  10 - 1  and each of the memory chips (bus slaves)  10 - 2  to  10 - 5  is effected using crosstalk between the two lines, that is, between the main line  1 — 1  and each of the wiring lines  1 - 2  and  1 - 3 . 
     An I/O circuit of each of the DRAM&#39;s  10 - 2  to  10 - 5  has a built-in termination resistor. Thus, the I/O circuit of each of the DRAM&#39;s  10 - 2  to  10 - 5  has an input impedance equal to a characteristic impedance of each of the lines  1 - 2  to  1 - 3  connected to the I/O circuits. Consequently, no reflection takes place at the I/o circuit. With this construction, a signal generated by each directional coupler C 1  or C 2  propagates to the stub line and it is not reflected at the input terminal of each of the DRAM&#39;s  10 - 2  to  10 - 5 . The termination as above may be implemented by means of either a MOS transistor inside the DRAM or an externally provided resistor. 
     One end of the main line  1 — 1 , remote as viewed from the MC  10 - 1 , terminates in a very high impedance as compared to a characteristic impedance owned by the main line  1 — 1 , particularly terminating in an open-end in the case of  FIG. 1 . The main line  1 — 1  has a reflection coefficient of approximately 1 and voltage on the main line undergoes total reflection. 
     A driver of I/O of the MC  10 - 1  has an impedance equal to the characteristic impedance of the main line  1 — 1  and no reflection takes place at the driver. In  FIG. 1 , the four DRAM&#39;s  10 - 2  to  10 - 5  are provided but the number of DRAM&#39;s may be either increased or decreased without impairing the effects of the invention. 
     Referring now to  FIGS. 3 and 4 , operation of signal propagation between the MC  10 - 1  and each of the DRAM&#39;s  10 - 2  to  10 - 5  shown in  FIG. 1 . 
     The same components as those in  FIG. 1  are designated by the same reference numerals in  FIGS. 3 and 4  and will not be described again. 
     Functionally, the main line  1 — 1  can be sorted into portions constituting the couplers C 1  and C 2  (sub coupling lines) and wiring lines connecting the sub coupling lines. In the sub coupling lines, the portions of the main line  1 — 1  are wired or laid in parallel to the sub coupling lines in wiring lines  1 - 2  and  1 - 3  at the directional couplers C 1  and C 2 . Assumptively, a signal propagation delay time between the MC  10 - 1  and the far end of main line  1 — 1  is expressed by T 1 . Also, a propagation delay time at the sub coupling line of each of the couplers C 1  and C 2  is expressed by T 2 . There also exist partial lines of portions not constituting the directional couplers on the main line  1 — 1  but it is assumed that these partial lines are so short that their propagation delay time is negligible for simplification of explanation. In other words, given that T 1 =2×T 2 , the following description will be given. 
     The opposite ends of the main line  1 — 1  are designated by (A) and (B). The end (A) is close to the MC  10 - 1  and the end (B) is the remote open-end of the main line  1 — 1 . Similarly, the opposite ends of the line  1 - 2  are designated by (C) and (D) and the opposite ends of the line  1 - 3  are designated by (E) and (F). Voltage waveforms at the individual points (A) to (F) are diagrammatically illustrated in  FIGS. 4 ,  5  and  6 . 
       FIG. 4  shows a signal state in which a data signal is transmitted (for write) from the MC  10 - 1 ,  FIG. 5  shows a signal state in which a memory read signal is transmitted from the DRAM  10 - 2  to the MC  10 - 1 , and  FIG. 6  shows a signal state in which a memory read signal is transmitted from the DRAM  10 - 3  to the MC  10 - 1 . In these figures, abscissa represents time and vertical dotted lines are drawn at intervals of T 2 . Ordinate represents signal voltage. 
     In  FIG. 4 , waveform (A) is an output waveform of the driver of MC  10 - 1 , which waveform shifts from L state to H state. The driver of MC  10 - 1  has an output impedance equal to the impedance of the main line  1 — 1 . Such a driver as above is particularly called a source impedance matching driver. The drive waveform shifting from L state to H state is of a divisional voltage by the impedance of driver and that of main line  1 — 1  and so a half the drive voltage is delivered. After having propagated for time T 1  on the main line  1 — 1  to the right in the drawing, the drive signal reaches the remote end (B). In this phase, the voltage undergoes total reflection because of the open-ended (B) terminal and a forward wave is superimposed on a reflection wave to produce a doubled voltage. 
     After time T 1  from the drive initiation, the reflection wave propagates on the main line  1 — 1  to the left and reaches the (A) end. Till then, time 2×T 1  has elapsed following the drive initiation. Voltage in this phase is the superimposed voltage of the forward wave and reflection wave, equaling the drive voltage of the MC  10 - 1 . The driver is in source impedance matching and therefore no reflection takes place at the driver, so that the signal does not repeat reflection but stably keeps the H state. 
     Next, the individual points of the wiring lines  1 - 2  and  1 - 3  will be noticed. By the forward wave flowing on the main line  1 — 1 , a backward signal is generated in the coupler C 1 . Backward herein referred to means a direction inverse to the direction of the forward wave and corresponds to the end or terminal (C) in  FIG. 3 . In other words, backward crosstalk is generated. The signal generated in the (C) terminal direction is absorbed in the DRAM  10 - 2  in  FIG. 3  and is not reflected. This is because the DRAM  10 - 2  terminates in the impedance equal to the characteristic impedance Zo of the line  1 - 2 . 
     When the coupler is constructed of a strip line that is a wiring line surrounded by a metal plane, an induced voltage due to an inductance between the two lines cancels an induced voltage due to an electrostatic capacitance therebetween, with the result that no signal is generated at the forward end (D). Accordingly, so-called forward crosstalk does not occur. Thus, in with the directional coupler Cl in  FIG. 4 , backward crosstalk due to the forward wave on the main line  1 — 1  is generated at the terminal (C) whereas no forward crosstalk is generated at the terminal (D). The backward crosstalk generated by the coupler C 1  has a length corresponding to time (=2×T 2 ) for reciprocation over the coupler C 1 . 
     This pulse width is grounded on the following reasons. 
     The backward crosstalk is generated by the wavefront of the forward wave and is kept to be induced in the sub coupling line until the forward wave coming into the coupler goes out of it. Time T 2  is required for the forward wave to propagate from entrance to exit of each coupler and time T 2  is required for a signal generated near the exit of the sub coupling line to propagate through the sub coupling line, so that the signal is induced during the total of 2T 2 . 
     After T 2  from the drive initiation, the forward wave traveling on the main line  1 — 1  reaches the coupler C 2  and thereafter acts on the coupler C 2  similarly to the coupler C 1 . As a result, a signal similar to the waveform (C) is induced at the terminal (E) of the DRAM  10 - 4 . Of course, no reflection takes place at this terminal. As in the case of the terminal (D), the forward wave propagating through the coupler C 2  does not induce any voltage at the terminal (F). 
     When the reflection wave is generated at the open-end (B) of the main line  1 — 1  after time T 1 , an inverse process proceeds. Since the (B) terminal is the open-end, the signal wave undergoes total reflection. The voltage amplitude of the reflection wave is the same as that of the forward wave and its travel direction is inversed. On the way to return to the MC  10 - 1  through the main line  1 — 1 , the reflection wave first induces backward crosstalk at the coupler C 2 . Thus, a signal is induced at the terminal (F) that is backward as viewed from the reflection wave on the main line  1 — 1 . Given that the wiring resistance does not exist and the wave traveling on the main line  1 — 1  is not distorted, the reflection wave on the main line  1 — 1  induces, at the terminal (F), the same waveform as that at the terminal (C). The timing coincides with the expiration of time T 1 , measured by starting with the initiation of signal transmission by the MC  10 - 1 , at which the reflection wave is generated. The pulse width of the wave at the terminal (F) is twice the T 2 . Obviously, this reflection wave does not induce any voltage at the forward terminal (E) through the coupler C 2 . 
     After time T 1 +T 2 , the reflection wave on the main line  1 — 1  comes into the coupler Cl to induce backward crosstalk at the terminal (D) in a similar manner. This pulse width is also twice the T 2 . 
     As described above, the signal traveling on the main line  1 — 1  from the MC  10 - 1  provides the forward wave and the reflection wave generated at the terminal (B) that generate backward crosstalk in the couplers C 1  and C 2 , respectively. Since the couplers C 1  and C 2  perform selective signal generation depending on the directions of the forward and reflection waves, the thus generated signals do not superimpose mutually and they do not act as noise on each other. Consequently, pulses each having a width of twice the T 2  that equals propagation delay time for reciprocation over each of the couplers C 1  and C 2  are generated at the individual terminals (C) to (F) of the DRAM&#39;s  10 - 2  to  10 - 5 , demonstrating that the pulse generation as above coincides with that in JP-A-7-141079, having comparable signal waveform quality. Signals are generated in order of timing at the terminals (C), (E), (F) and (D), indicating that the terminal (C) of DRAM  10 - 2  is the temporally closest to the MC  10 - 1  and the second terminal (D) of DRAM  10 - 3  is the temporally remotest from the MC  10 - 1 . Signal propagation delay times from the MC  10 - 1  to the individual DRAM&#39;s  10 - 2  to  10 - 5  are indicated by the following equations (1) to (4), respectively.
 
Signal propagation delay time from MC 10 - 1  to DRAM 10 - 2 ( C )=0  (1)
 
Signal propagation delay time from MC 10 - 1  to DRAM 10 - 3 ( D )=T1+T2  (2)
 
Signal propagation delay time from MC 10 - 1  to DRAM 10 - 4 ( E )=T2  (3)
 
Signal propagation delay time from MC 10 - 1  to DRAM 10 - 5 ( F )=T1  (4)
 
Accordingly, in individual events, signals arrive after the delay times indicated by equations (1) to (4).
 
     It will be seen that by connecting the two terminated DRAM&#39;s  10 - 2  and  10 - 3  to the opposite ends of the directional coupler Cl and the two terminated DRAM&#39;s  10 - 4  and  10 - 5  to the opposite ends of the directional coupler C 2 , as shown in  FIGS. 1 and 3 , signal transmission from the MC  10 - 1  to the DRAM&#39;s  10 - 2  to  10 - 5  can be achieved. 
     Next, by making reference to  FIGS. 5 and 6 , signal transmission from the DRAM&#39;s  10 - 2  to  10 - 5  to the MC  10 - 1  in the read direction of memory will be considered. Waveforms participating in transfer from the DRAM  10 - 2  to the MC  10 - 1  developing at the individual points are illustrated in  FIG. 5  and waveforms participating in transfer from the DRAM  10 - 3  to the MC  10 - 1  are illustrated in  FIG. 6 . Waveforms participating in transfer from the DRAM&#39;s  10 - 4  and  10 - 5  to the MC  10 - 1  are grounded on the same mechanism as that in  FIGS. 5 and 6  and will not be described. 
     Firstly, in  FIG. 5 , the signal state changes from L state to H state at DRAM  10 - 2  (C) and a pulse is delivered therefrom. Then, after time T 2 , the signal reaches the terminal (D). The DRAM  10 - 3  (D) has an input impedance equal to the characteristic impedance of line and no reflection occurs. The coupler C 1  induces backward crosstalk in the main line  1 — 1 . The duration of this pulse equals propagation delay time (=2×T 2 ) for reciprocation over the coupler as in the case  FIG. 4 . No forward crosstalk takes place on the main line  1 — 1  and so, no signal is induced at the terminal (B). Consequently, even when the terminal (B) of the main line  1 — 1  is open-end, crosstalk can be generated at the MC  10 - 1  by driving the pulse signal from the DRAM  10 - 2 . This signal has the same pulse width as that in the prior art, JP-A-7-141079. 
     Transfer from the DRAM  10 - 3  (D) to the MC  10 - 1 (A) in  FIG. 6  is an inverse generation process. A pulse from the DRAM  10 - 3  (D) reaches the terminal (C) after time T 2 . Backward crosstalk is induced in the coupler C 1  and it propagates on the main line  1 — 1  toward the terminal (B). After time T 2  following the drive initiation at the terminal (D), the backward crosstalk generated by the coupler C 1  reaches the terminal (B). The backward crosstalk undergoes total reflection at that end and travels inversely on the main line  1 — 1 . After time T 2 +T 1  following the drive initiation, the backward crosstalk reaches the MC  10 - 1 . In  FIG. 6 , the pulse reaching the MC  10 - 1  (A) also has a width that is twice the T 2 , equaling the pulse width in  FIG. 4 . 
     Signal propagation delay times from the individual DRAM&#39;s  10 - 2  to  10 - 5  to the MC  10 - 1  during read operation are the same as those in  FIG. 4 . Namely, they are indicated by the following equations (5) to (8).
 
Signal propagation delay time from DRAM  10 - 2 ( C ) to MC 10 - 1 = 0   (5)
 
Signal propagation delay time from DRAM 10 - 3 ( D ) to MC 10 - 1 =T 2 +T 1   (6)
 
Signal propagation delay time from DRAM 10 - 4 ( E ) to MC 10 - 1 =T 2   (7)
 
Signal propagation delay time from DRAM 10 - 5 ( F ) to MC 10 - 1 =T 1   (8)
 
Accordingly, in individual events, signals arrive after the delay times indicated by the above equations. These equations (5) to (8) are equal to the equations (1) to (4), demonstrating that for both the write operation and the read operation, the propagation delay time between the MC  10 - 1  and the DRAM&#39;s  10 - 2  to  10 - 5  is the same. This is comparable to the use of the prior art, exhibiting characteristics important for timing design in the memory system. In other words, the conventional timing design method as it is can be followed by the present invention, leading to reduction in the number of steps in development.
 
     It will be seen that a bus for bi-directional signal transmission can be constructed by connecting the four DRAM&#39;s to the bus and using only two couplers. Through this, the packaging area of DRAM&#39;s can be halved as compared to the prior art of  FIG. 2  to ensure high-density packaging. More particularly, the prior art of JP-A-7-141079 faces a problem that the directional couplers are aligned in sequence as shown in  FIG. 2  and the pitch between the DRAM&#39;s  10 - 2  to  10 - 5  cannot be less than the length of the coupler. But, by making the main line the open-end, placing the driver of MC  10 - 1  in source impedance matching and using the terminated DRAM&#39;s  10 - 2  to  10 - 5  as shown in  FIG. 1  or  3 , the same line length can be used for the same main line to connect the doubled number of DRAM&#39;s, thereby permitting high-density packaging in the system. 
     Next, the signal transmission is confirmed through simulation. The simulation will be described with reference to  FIGS. 7 to 12 . 
     Referring first to  FIG. 7 , a first embodiment of the wiring mode according to the invention will be described. In  FIG. 7 , the directional couplers are illustrated in sectional form. Various shapes of the coupler can be considered in accordance with requirements imposed by the system. In the general technique, however, a material of FR-4 for a printed circuit board is used to attain a wiring line width (W=154 μm) and a wiring pitch (S=216.7 μm) in personal computers (PC&#39;s) and PC servers. The above data is subjected to an electromagnetic field analysis to obtain electrical characteristics between wiring lines as below.
 
Capacitance matrix between two lines CMATRIX (F/um)=1.446e−16 −6.644e−17 −6.644e−17 1.446e−16  (9)
 
Inductance matrix between two lines LMATRIX (H/um)=4.487e−13 2.062e−13 2.062e−13 4.487e−13  (10)
 
Characteristic impedance matrix Real part=6.272e+01 2.882e+01 2.882e+01 6.272e+01  (11)
 
Imaginary part=−3.336e−01 −1.694e−02 −1.694e−02 −3.336e−01  (12)
 
Consequently, effective impedance Zeff of the two lines was 55 Ω. In the above equations, “e” represents power of base of 10.
 
     Further, in the backward crosstalk coefficient,
 
Real part=1.000e+00 2.433e−01 2.433e−01 1.000e+00  (13)
 
Imaginary part=000e+00 1.441e−03 441e−03 0.000e+00  (14)
 
It will therefore be seen that when a signal of 1V is incident, a backward crosstalk signal of 0.2433V is induced.
 
     By using these couplers, write data waveforms from the MC  10 - 1  to the DRAM&#39;s  10 - 2  to  10 - 5  shown in  FIG. 3  are simulated in accordance with an equivalent circuit as shown in  FIG. 8 . A simulator used is a SPICE (Simulation Program for Integrated Circuit Emphasis) for circuit analysis. As an equivalent circuit of the driver of MC  10 - 1 , a pulse voltage source and a resistor rs are used. Known transmission line models T1, T3 and T5 are connected to set up an equivalent circuit of the main line  1 — 1 , known lossy coupled transmission line models Y 2  and Y 4  are connected to set up the directional couplers and one end S 6  of the transmission line T5 is terminated by a resistor rk of high resistance. The resistor rk has a high resistance of 100 kΩ and can therefore be regarded as an open-end. The terminals (A) and (B) in  FIG. 3  correspond to terminals S 1  and S 2  in  FIG. 8 . 
     The DRAM&#39;s  10 - 2  to  10 - 5  are represented by parallel connections of termination resistors rk 1 , rk 2 , rj 1  and rj 2  and input electrostatic capacitors rk 1  and ck 1 , rk 2 , cj 1  and cj 2 . The ends (C) and (D) in  FIG. 3  correspond to nodes K 1  and k 4  in  FIG. 8  and the ends (E) and (F) in  FIG. 3  correspond to nodes J 1  and J 4 . Termination potential is indicated by Vtt. Constants of these elements will be shown as below.
 
VPULSE: amplitude=1.8V, rise time=0.1ns  (15)
 
rs=55Ω  (16)
 
t 1 , t 3 , t 5 , t 6 , t 8 , t 9 , t 10 : characteristic impedance z 0 =55Ω, td=1.0 ns  (17)
 
Y 2 , Y 4 : wiring line length=40 mm  (18)
 
rk=100 KΩ  (19)
 
rk 1 , rk 2 , rj 1 , rj 2 =55Ω  (20)
 
Vtt=0.9V  (21)
 
ck 1 , ck 2 , cj 1 , cj 2 =0.1 pF  (22)
 
     Resulting simulation waveforms are illustrated in  FIG. 9 . This is an example where Vtt=0.9V. Like  FIG. 4 , smart rectangular pulses are generated at the terminals K 1 , K 4 , J 1  and J 4  corresponding to the DRAM&#39;s  10 - 2  to  10 - 5 , indicating that any great disturbance does not take place. It will be noted that while the amplitude of drive pulse is 0.9V, the amplitude of crosstalk is 108 mV to 200 mV and the amplitude levels at the terminals K 1 , J 1 , J 4  and K 4  decrease slightly gradually in sequence owing to the wiring resistance of the main line  1 — 1 . A signal of about 100 mV is at a voltage level that can be discriminated sufficiently even by a semiconductor using a C-MOS. It will also be seen that the time sequence of occurrence of crosstalk at the terminals K 1 , J 1 , J 4  and K 4  is the same as that in  FIG. 4 . 
     Next, waveforms during the signal transmission (read) from the DRAM  10 - 2  to the MC  10 - 1  will be described with reference to  FIGS. 10 and 11 . Like  FIG. 8 ,  FIG. 10  shows an equivalent circuit. A voltage source serving as a read signal is connected to a point KO corresponding to the DRAM  10 - 2  in  FIG. 1 . The impedance of the driver of DRAM  10 - 2  is represented by rk 1  and is set to 10Ω that is smaller than the wiring impedance Zo (=55Ω) with the aim of increasing the signal amplitude of pulse. 
     A resistor rs having a resistance of 55Ω equal to the characteristic impedance Zo of the wiring is connected to a point S 1  on main line corresponding to the MC  10 - 1 . Other circuit constants are the same as those in  FIG. 8 . Waveforms obtained through this circuit analysis are illustrated in  FIG. 11 . A pulse of 368 mV reaches the S 1  point of the MC  10 - 1  and waveforms leading to noise are hardly seen at other points. This waveform is almost equal to that in  FIG. 5 . 
     Next, signal waveforms from the DRAM  10 - 3  to the MC  10 - 1  are illustrated in  FIG. 12 . In comparison with the equivalent circuit of  FIG. 10 , the pulse voltage source is connected to the resistor rk 2  and the resistor rk 1  is connected to the termination voltage source VTT through the characteristic impedance as in the case of  FIG. 8 . Like the resistor rk 1  in  FIG. 10 , the resistor rk 2  has a low impedance of 10Ω. Resulting waveforms are illustrated in  FIG. 12 . 
     In  FIG. 12 , when a drive pulse from the terminal K 4 , indicated by dotted line, passes through the coupler Y 2  of  FIG. 10 , crosstalk is generated on the main line. The pulse traveling on the main line is reflected at the terminal S 6 . Since the reflection is total reflection, the amplitude of the pulse is doubled. The reflected pulse reaches the terminal S 1 , resulting in a pulse of 302 mV amplitude. The time for arrival is longer than that in  FIG. 11  and is equal to the delay time between the terminals S 1  and K 4  in  FIG. 9 . A noise of about 80 mV is superimposed on a waveform at the terminal J 4  but this does not matter because this transfer is read transfer from the DRAM  10 - 3  to the MC  10 - 1  and the DRAM  10 - 5  does not utilize this signal. 
     The read waveforms from the DRAM&#39;s  10 - 4  and  10 - 5  are similar in mechanism. Accordingly, read data can be transferred to the MC  10 - 1 . Further, it will be seen that the propagation delay time in this case is the same as that in  FIG. 9 . 
     Referring now to  FIGS. 13 and 14 , the I/O circuits of the MC  10 - 1  and DRAM&#39;s  10 - 2  to  10 - 5  will be described. 
     The I/O circuit of MC  10 - 1  is shown in  FIG. 13 . In the figure, the driver of the MC  10 - 1  designated by reference numeral  51  and a receiver  52  are connected to each other at the same potential through an input/output terminal (I/O PAD). The driver  51  is in source impedance matching to have an impedance equal to the characteristic impedance of the wiring line connected with the driver regardless of whether data is transmitted or not. Transistors in the final stage of the driver  51  are designated by Ml and M 2 . The transistors M 1  and M 2  are totem pole connected. The transistor M 1  is a P-MOS transistor connected to the output terminal (I/O PAD) and a power supply VDDQ. The transistor M 2  is an N-MOS transistor connected to the output terminal and ground (VSS). Each of the two transistors M 1  and M 2  has the impedance that can be changed by changing the gate width of the transistor. Therefore, by adjusting the transistor gate width with an impedance adjusting circuit not shown in  FIG. 3 , the impedance can be matched to the characteristic impedance of the main line  1 — 1 . 
     The MC  10 - 1  controls the transistors M 1  and M 2  in accordance with data to be delivered. When output data is designated by DATA and an output enable signal is designated by OE, the driver to be owned by the MC  10 - 1  of  FIG. 1  has a driver characteristic as shown at table in  FIG. 13 . More particularly, only when DATA=L (logical low) and OE=L, the transistor M 2  is turned on to deliver L signal. In other states, the transistor M 1  is turned on. As a result, regardless of either transmission or reception of data, the impedance of the driver matches the characteristic impedance of the main line. The driver  51  is connected with the main line having the open-end and hence, with the construction as above, any current is not consumed unless the L signal is driven. 
     Turning now to the receiver  52 , this receiver has a hysteresis characteristic for discrimination of signals generated by the directional coupler. More particularly, when the signal coming into the directional coupler shifts from L (logical low) to H (logical high), a pulse of positive polarity is generated by the receiver  52  and when the signal shifts from H to L, a pulse of negative polarity is generated. Thus, the hysteresis characteristic ensures one method for discrimination between two signals of different polarities. 
     When the driver of MC  10 - 1  in  FIG. 13  is connected to the bus in  FIG. 1 , the read data read by the MC  10 - 1  generates a pulse of positive/negative polarity with respect to potential in H state outputted by the driver  51 . The reasons for this are as follows. In the directional coupler, DC coupling does not take place between the two lines and so, an AC pulse is superposed on the output potential of the driver  51  in MC  10 - 1  regardless of the DC level of the drive voltage outputted by DRAM. And then, during read, data is by no means delivered out of the driver and the terminal potential on the main line equals VDDQ of H state. 
     Accordingly, in the receiver  52 , the signal from the I/O PAD is compared with the H potential of driver  51 , that is, VDDQ. This accounts for the fact that a circuit of receiver  52  for reception of the signal is operated by VDD higher than VDDQ and for example, if VDD=2.5V for VDDQ=1.8V, the receiver  52  can be implemented with a C-MOS without causing any problem. 
     As described above, when having the I/O circuit as shown in  FIG. 13 , the MC  10 - 1  of  FIG. 1  can transmit and receive the signal stably. 
     Next, an example of the I/O circuit of each of the DRAM&#39;s  10 - 2  to  10 - 5  will be described with reference to  FIG. 14 . 
     The I/O circuit of each of the DRAM&#39;s  10 - 2  to  10 - 5  is substantially the same as that of the MC  10 - 1  in  FIG. 13  excepting for a driver  51 ′. The transistor M 2  has an impedance lower than that of the wiring line. Other components are identical to those of  FIG. 13 . 
     The above construction is grounded on the following reasons. The line on the DRAM side is terminated at the opposite ends when data is inputted to the DRAM. When delivering data, the other DRAM is placed in matching termination condition. In other words, no reflection wave returns from the remote end. This differs from the condition that the main line connected to the MC  10 - 1  has the open-end. Therefore, the driver  51 ′ need not be terminated. Namely, the driver  51 ′ need not be in source impedance matching. Accordingly, the signal generated by the coupler can be made to be higher by making the drive pulse higher. To this end, the impedance of the transistor M 2  is lowered to maintain the large amplitude. The output impedance of the driver  51 ′ can of course be matched to the characteristic impedance of the line. In that case, the signal amplitude of the drive pulse is decreased but it does not matter if the receiver of the MC  10 - 1  can discriminate the data. In this case, the I/O circuit is constructed identically to  FIG. 13 . When receiving data, the driver delivers H state to make its impedance match with the characteristic impedance of the main line. As a result, both the drivers  51 ′ of two DRAM&#39;s  10 - 2  and  10 - 3  connected to the same line deliver H output but this potential equals VDDQ and no consumption current flows under this condition. In other words, during H drive or HiZ state of data, the consumption current does not flow. With this construction, no current is consumed unless L signal is driven and the same power saving effect as that with the main line of  FIG. 13  can be obtained. 
     Even when the potential on the main line assumes VDDQ during reception as in the case of  FIGS. 13 and 14 , the signal amplitude generated by the directional coupler does not change. Accordingly, even with the MC  10 - 1  placed in H state, L state or HiZ state, a binary signal can be delivered under the condition that the output impedance matches the impedance of the wiring line and therefore, even when the main line has the open-end, no reflection takes place at the driver and a less distorted drive pulse can be delivered. Further, by making the driver  51 ′ of each of the DRAM&#39;s  10 - 2  to  10 - 5  have a low impedance only in L state, the signal amplitude can be maintained and the waveform cannot be distorted. Therefore, data can be transmitted/received stably at a high speed. 
     Referring now to  FIG. 15 , a first embodiment of packaging when the system is packaged in a printed circuit board will be described. Memory modules  2 — 2  to  2 - 7  carry the DRAM&#39;s  10 - 2  to  10 - 7 , respectively. A mother board  1  carries the MC  10 - 1  and the memory modules  2 — 2  to  2 - 7 . The memory modules  2 — 2  to  2 - 7  are connected to the mother board  1  by connectors. In the mother board  1 , solid line represents a wiring layer for carrying parts and dashed lines m 1  and x 1  represent inner signal line layers. 
     In  FIG. 15 , the main line  1 — 1  from the MC  10 - 1  is wired straightly from right to left in the inner wiring layer m 1 . In case the main line  1 — 1  has to run around through-holes for connector lead wiring and power supply pins, it may be curved. The main line  1 — 1  cooperates with parts of lines  1 - 2  to  1 - 4  spaced apart from the main line in parallel therewith to form couplers C 1  to C 3 . Stub lines to DRAM&#39;s are connected to the opposite ends of the sub coupling line of each of the couplers C 1  to C 3 . The couplers C 1  to C 3  are aligned sequentially in relation to the main line  1 — 1  without overlapping each other. With this wiring mode, wiring associated with the individual memory modules  22  to  2 - 7  can be laid in the same wiring density. 
     The main line  1 — 1  terminates in the open-end at the right end (remote end) in  FIG. 15 . 
     In order to carry out data transmission/reception between the MC  10 - 1  and the DRAM&#39;s  10 - 2  to  10 - 7 , a forward wave on the main line  1 — 1  and backward crosstalk due to the couplers C 1  to C 3  are utilized for the DRAM&#39;s  10 - 2 ,  10 - 4  and  10 - 6  and a reflection wave at the remote end and its backward crosstalk signal are utilized for the DRAM&#39;s  10 - 3 ,  10 - 5  and  10 - 7 . 
     With the construction as above, a doubled number of memory modules  2 — 2  to  2 - 7  can be connected over the same length of the main line  1 — 1  as compared to the prior art system of  FIG. 2 . In  FIG. 15 , the two inner layers are used to form the directional couplers but the same effects can be attained by using two adjacent wiring lines in one layer. In that case, the number of inner layers can be reduced from two to one but the wiring density per layer is doubled. Thus, a choice can be made depending on requirements imposed by the system. 
     Of the memory modules  2 — 2  to  2 - 7  to be carried in  FIG. 15 , a particular memory module will not be carried depending on the system configuration. In that case, in order to suppress reflection generated at a vacant memory module, a termination module carrying a resistor for making the wiring line matching-terminate in the termination power supply must be inserted. The termination power supply and the memory modules  2 — 2  to  2 - 7  are at the same potential and the termination resistance equals the impedance of each of the DRAM&#39;s  10 - 2  to  10 - 7 . Obviously, the characteristic impedance of the wiring in the termination module is set to be equal to the impedance of the memory module. By constructing the termination module in this manner and inserting it in the connector of the vacant memory module, reflection noise due to the wiring can be eliminated and bus operation can be accomplished stably. 
     A second embodiment of packaging will be described with reference to  FIG. 16 . 
     The present embodiment intends to package memory modules in higher density than that in the first embodiment of the wiring mode by utilizing the technique disclosed in the previously described U.S. Ser. No. 09/569,876 filed May 12, 2000 by the present applicant. 
     In U.S. Pat. No. 5,638,402 (JP-A-7-141079), there arises a problem that the directional couplers are aligned sequentially and so the pitch between the memory modules  2 — 2  to  2 - 9  carried in the mother board  1  cannot be less than the length of the coupler. 
     Contrary to  FIG. 15 , in the construction of the present embodiment, the wiring of the main line  1 — 1  is led in a signal layer m 1  to the right in the drawing as viewed from the MC  10 - 1  and is relayed at the right end to a signal line layer m 2  via a through-hole so as to run to the left, ultimately being opened at the remotest end. 
     The main line  1 — 1  in signal layer m 1  cooperates with a wiring line  1 - 2  between DRAM&#39;s  10 - 2  and  10 - 4  and a wiring line  1 - 4  between DRAM&#39;s  10 - 6  and  10 - 8  to form couplers C 1  and C 3 , respectively. The folded or turned-round main line  1 — 1  in the signal layer m 2  cooperates with a wiring line  1 - 5  between DRAM&#39;s  10 - 7  and  10 - 9  and a wiring line  1 - 3  between DRAM&#39;s  10 - 3  and  10 - 5  to form couplers C 4  and C 2 , respectively. 
     The lines  1 - 2  and  1 - 4  constitute sub coupling lines in a signal line layer x 1  and the lines  1 - 3  and  1 - 5  constitute sub coupling lines in the signal line layer x 2 . Accordingly, the couplers C 1  and C 3  are constructed of the wiring layers x 1  and m 1  and the couplers C 2  and C 4  are constructed of the wiring layers m 2  and x 2 . Thus, the couplers C 1  and C 3  will be described as being constructed of upper layers and the couplers C 2  and C 4  will be described as being constructed of lower layers. 
     The couplers C 1  to C 4  are sequentially laid such that they have a constant characteristic impedance of wiring relative to the main line  1 — 1 . Arrangement and wiring is such that data transfer between the MC  10 - 1  and each of the DRAM&#39;s  10 - 2  and  10 - 9  is carried out using backward crosstalk in any couplers. More particularly, for the DRAM&#39;s  10 - 2  and  10 - 6  connected to the couplers C 2  and C 4  in the upper layers, backward crosstalk is induced by a forward wave traveling on the m 1  layer of main line  1 — 1  and for the DRAM&#39;s  10 - 9  and  10 - 5  connected to the couplers C 4  and C 2  in the lower layers, backward crosstalk is induced by a forward wave traveling on the m 2  layer of main line  1 — 1 . Then, for the DRAM&#39;s  10 - 3  and  10 - 7  connected to the couplers C 2  and C 4  in the lower layers, backward crosstalk is induced by a reflection wave traveling on the m 2  layer of main line  1 — 1  and for the DRAM&#39;s  10 - 8  and  104 , backward crosstalk is induced through the couplers C 3  and C 1  in the upper layers by a reflection wave traveling on the m 1  layer of main line  1 — 1 . In this manner, the components are so arranged as to generate backward crosstalk in any transfer operations. 
     Since the main line  1 — 1  serving as the sub coupling line constituting the couplers can be once folded from one layer to the other so as to form the directional couplers in the respective layers, the pitch between adjacent ones of the memory modules  2 — 2  to  2 - 9  can be approximately half the length of coupler wiring line of each of the directional couplers C 1  to C 4 . As a result, the memory modules can be packaged in one mother board in high density. Specifically, the package density can be twice higher than that in the first embodiment of  FIG. 15  and four times higher than that in the prior art of  FIG. 2 . Even with this construction, the coupling length necessary for coupling remains unchanged and the coupling level necessary for signal propagation can also remain unchanged, thus exhibiting the signal waveform quality comparable to that in JP-A-7-141079 of  FIG. 2 . 
     To explain, in the prior art disclosed in JP-A-7-141079, the directional couplers are aligned sequentially as shown in  FIG. 2 , raising a problem that the pitch between adjacent ones of the memory modules  2 — 2  to  2 - 4  carried in the mother board  1  cannot be less than the length of the coupler. But, by folding the main line as shown in  FIG. 16 , the pitch between adjacent ones of the memory modules  2 — 2  to  2 - 9  carried in the mother board  1  can be ¼ of the length of the coupler to permit high-density packaging in the system. 
     In some applications, like the first embodiment of the wiring mode, one of the memory modules  2 — 2  to  2 - 9  to be carried is not carried depending on the system construction in the embodiment of  FIG. 16 . In that case, reflection is generated at a vacant memory module and for the purpose of suppressing the reflection, a termination module carrying a resistor for making the wiring line matching-terminate in the termination power supply must be inserted. The termination power supply is at the same potential as that of the memory modules  2 — 2  to  2 - 9  and the termination resistor has a resistance equal to the impedance of each of the DRAM&#39;s  10 - 2  to  10 - 9 . Of course, the characteristic impedance of the wiring in the termination module is set to be equal to the impedance of the memory module. By constructing the termination module in this manner and inserting it in the connector of the vacant memory module, reflection noise due to the wiring can be eliminated and stable bus operation can be ensured. 
     Referring now to  FIG. 17 , there is illustrated a second embodiment of the wiring mode showing an example of layer construction of mother board  1  adapted to the embodiment of  FIG. 16 .  FIG. 17  is a longitudinal sectional view in a direction vertical to the main line  1 — 1  in the mother board  1  of  FIG. 16 . In this example, starting from the uppermost layer of CAP 1  layer, a power supply layer (V 1 ), a ground layer (G 1 ), a signal layer (x 1 ), a signal layer (m 1 ), a ground layer (G 2 ), a power supply layer (V 2 ), a signal layer (m 2 ), a signal layer (x 2 ), a ground layer (G 3 ), a power supply layer (V 3 ) and a CAP 2  layer are stacked. Generally, in the printed circuit board, cupper foiled plates having upper and lower sides covered with cupper are bonded with prepreg that is represented by two corrugated lines. 
     Of the directional couplers, the coupler C 1  in  FIG. 16  is formed of parallel wiring lines  1 — 1  and  1 - 2  laid in parallel in the overlying and underlying x 1  and m 1  layers. Similarly, the coupler C 2  in  FIG. 16  is formed of parallel lines  1 — 1  and  1 - 3  laid in parallel in the overlying and underlying layers m 2  and x 2 . Here, main line  1 — 1  associated with the signal layer m 1  and main line  1 — 1  associated with the signal layer m 2  are formed of the same wiring line folded in  FIG. 16 . 
     A ground layer or power supply layer is positioned between the coupler formed of the x 1  and m 1  layers and the coupler formed of the m 2  and x 2  layers, functioning to prevent signal noise representing coupling between the directional couplers C 1  and C 2 . With this construction, signal coupling between the couplers, that is, leakage noise can be reduced to ensure data transfer at a high speed. 
     The wiring mode can be implemented according to a third embodiment as shown in  FIG. 18 . In the present embodiment, the couplers are arranged and coupled in the lateral direction in the longitudinal section. In the lateral direction as referred to herein, couplers are formed of the same layer. For example, a coupler C 1   a  surrounded by an ellipse includes a main line  1 - 1   a  and a coupling line  1 - 2   a  and the main line  1 - 1   a  is folded to cooperate with a coupling line  1 - 3   a  so as to form a coupler C 2   a  in the m 2  layer. Similarly, a main line  1 - 1   b  of different signal bit couples with a coupling line  1 - 2   b  in the m 1  layer to form a coupler C 1   b  and the folded main line  1 - 1   b  cooperates with a coupling line  1 - 3   b  to form a coupler C 2   b . In order to reduce the noise level representing coupling between adjacent ones of the couplers C 1   a , C 1   b , C 2   a  and C 2   b , a planar power supply layer is inserted between the layers and the signal lines  1 - 1   a  and  1 - 1   b  are distanced from each other. The couplers are constructed as above and advantageously, the number of layers can be reduced as compared to the embodiment of  FIG. 17 . 
     Referring now to  FIG. 19 , a second embodiment of the bus system will be described. 
     The present embodiment is directed to an example of construction in which the remote end of the main line  1 — 1  is short-circuited in contrast to the construction in  FIG. 1 . 
     Short-circuit herein referred to means that an impedance very lower than the impedance of the wiring is connected and in  FIG. 19 , the main line is connected to a power supply having an internal impedance of zero. With this connection, total reflection is generated at the remote end but in this case, the reflection coefficient is −1 and a reflection wave has a polarity different from that of a forward wave. Consequently, backward crosstalk generated at the DRAM&#39;s  10 - 5  and  10 - 3  also has a sign inverted to that in  FIG. 1 , having a negative logic relative to the DRAM&#39;s  10 - 2  and  10 - 4 . In other words, the receiver of each of the DRAM&#39;s  10 - 3  and  10 - 5  is at negative logic as compared to that of each of the DRAM&#39;s  10 - 2  and  104 . Similarly, the driver of each of the DRAM&#39;s  10 - 3  and  10 - 5  is also at negative logic. 
     The power supply to be short-circuited herein may be at either ground or VDDQ. The output impedance of the driver in the MC  10 - 1  is identical to the characteristic impedance of the wiring as in the case of the driver in the first embodiment ( FIG. 1 ) but the output potential conditioned not to deliver data in HiZ state is of course set to be identical to this short-circuit potential. This is because if the above requirement is not satisfied, current flows out of the driver even when data transfer is not carried out to raise consumption power. 
     With the construction as above, signals of positive logic and negative logic can coexist for use. Even when the construction of the DRAM&#39;s  10 - 2  to  10 - 5  remains unchanged, a particular signal will sometimes be desired to have different polarities for even DRAM&#39;s and odd DRAM&#39;s depending on the system. For example, there arises such a desirability that the rise edge and fall edge of the clock signal inputted to the DRAM&#39;s are desired to be used. Of the connected DRAM&#39;s, DRAM&#39;s in the latter half in terms of temporal sequence as viewed from the MC are at negative logic and so, the phase of clock can be changed for the former half and the latter half. This can be used in time phase adjustment when the period of clock becomes shorter than the propagation delay time of the main line. 
     In the case of the construction in  FIGS. 15 and 16 , even modules can selectively be rendered to be at negative logic by making the wiring for a particular signal in the mother board open-ended or short-circuited even when the same modules are used. For example, when a chip select signal from the MC  10 - 1  is used in common to the DRAM&#39;s  10 - 2  and  10 - 3 , the DRAM&#39;s  10 - 2  and  10 - 3  can be selected exclusively and the number of chip select signals can be reduced. 
     Further, in comparison with the main line  1 — 1  having its remote terminal open-ended, the electromagnetic field is shielded and as a result, electromagnetic wave confined in a space and radiated to a free space can be reduced. In other words, electromagnetic radiation noise can be reduced. 
     Referring now to  FIG. 20 , a third embodiment of the bus system will be described. 
     In the present embodiment, the embodiment of  FIG. 19  is applied to a differential signal. A differential driver in MC  10 - 1  is in source impedance matching and a main line  1 — 1  from the driver forms a ring. DRAM&#39;s  10 - 2  to  10 - 5  are connected to form couplers C 1  to C 4  together with the ring-formed main line  1 — 1 . Differential I/O circuits in the DRAM&#39;s  10 - 2  and  10 - 4  are connected at positive logic terminal to the couplers C 1  and C 3  and connected at negative logic terminal to the couplers C 2  and C 4 . On the other hand, differential I/O circuits in the DRAM&#39;s  10 - 3  and  10 - 5  are connected at positive logic terminal to the couplers C 2  and C 4  and are connected at negative logic terminal to the couplers C 1  and C 3 . The clockwise wiring length from the MC  10 - 1  to the coupler C 1  equals the counterclockwise wiring length from the MC  10 - 1  to the coupler C 2  and the pulse reaches the couplers C 1  and C 2  at identical time. That is the case with the couplers C 3  and C 4 . 
     The ring-formed main line  1 — 1  is folded at the right end in  FIG. 20  and equipotential pulses of different polarities of the differential pulse from the MC  10 - 1  overlap each other at the folding point, thus giving rise to the same behavior as the short-circuiting in  FIG. 19 . More particularly, the drive pulse from the positive logic side of MC  10 - 1  propagates in the form of a forward wave of positive polarity from left to right to reach the folding point but when passing through the folding point, it meets a forward wave of negative polarity delivered out of the negative pole of the driver and traveling from left to right. These waveforms result in the same state as short-circuiting at the remote end from the MC  10 - 1 . 
     With the construction as above, even DRAM&#39;s can selectively be operative at negative logic even for the differential signal. 
     Referring to  FIG. 21 , a fourth embodiment of the bus system will be described. In the present embodiment, the differential line is constructed as shown in  FIG. 21 . 
     Source lines  1 - 1   a  and  1 - 1   b  that constitute a differential signal wiring line from the MC  10 - 1  being in source impedance matching are constructed of two wiring lines having open-ends. Positive total reflection waves are generated at the open-ends and so inputs to receivers of DRAM&#39;s  10 - 3  and  10 - 5  are inverse to those in  FIG. 20 . More particularly, DRAM&#39;s  10 - 2  and  10 - 3  are connected to a coupler C 1  at the positive logic terminal and they are connected to a coupler C 2  at the negative logic terminal. With this construction, a differential signal being totally at positive logic can be transmitted. 
     By combining  FIGS. 20 and 21  and making the main line take a ring form or have two open-ends for the same DRAM&#39;s in bus connection, even DRAM&#39;s can selectively be operated at either positive logic or negative logic. This can be accomplished by simply making the wiring lines in the mother board shown in  FIGS. 15 and 16  short-circuited or open-ended without resort to any other parts. Accordingly, the degree of freedom of system design can be expanded. 
     Incidentally, in a memory module system using a DQS (data strobe) signal for latching a DQ (data) signal, for example, a DDR-SDRAM (Double Data Rate Synchronous DRAM), there arise a problem that latency of write data is long. This will be explained with reference to  FIG. 22 . 
     In a SSTL (Stub Series Terminated Logic) interface adopted in the DDR-SDRAM, the Hiz state is identical to termination voltage Vtt and reference voltage Vref of its receiver is also substantially identical to the terminating voltage Vtt, raising a problem that shifting or transition from Hiz state to L state or from Hiz state to H state can be detected. 
     To explain the problem more specifically with reference to  FIG. 22 , a command referenced to clock CK is issued and data is transmitted. For example, a write command is issued in stage  1  and write data (DAO) is transmitted from stage  2 . A strobe signal DQS is once dropped from Hiz state to L state in stage  1  to drive a strobe signal for latching data in stage  2 , with the result that one cycle wait is inserted in the data signal. 
     Reasons for this are as follows. The memory cannot detect the transition of the DQS from Hiz state to L state and cannot discriminate the transition of the DQS until the DQS changes from L to H. Therefore, for recognition of the DQS transition, the wait representing a preamble of one stage is inserted. 
     In contrast thereto, when the directional coupler of the first embodiment of the bus system is used, data can be issued in synchronism with the command as shown in  FIG. 23 , where DQTx represents a data signal waveform transmitted from the MC  10 - 1  and DQRx represents backward crosstalk induced by the directional coupler, which backward crosstalk is a data signal waveform inputted to the receiver of the DRAM. Similarly, in the case of strobe, DQSTx and DQSRx represent the output signal from MC and the input signal to the DRAM, respectively. 
     As will be seen from  FIG. 23 , the write command and DQTx representing data can simultaneously be issued from the MC and DQSTx representing the strobe signal can also be driven in stage  1 . In other words, as the DQSTx changes from Hiz to L, a pulse is generated in the DQSRx signal and this pulse can be discriminated by the DRAM. Accordingly, there is no need of providing the preamble for the DQS and the write command and write data can be issued simultaneously. This accounts for the fact that the access latency of the memory write can be shortened by one stage. Thus, latency for memory access in the system can be improved and the system performance can be promoted. 
     In the case of the bus using the directional coupler based on the SSTL driver, that is, when the main line and the sub coupling line are terminated as in the case of the prior art of  FIG. 2 , the amplitude of the preamble is half the amplitude of data transfer. In other words, the drive amplitude during transition from Hiz state to L state or Hiz state to H state is approximately half the signal during transition from L state to H state or vice versa. As a result, the amplitude inputted to the receiver is halved and the receiver runs short of sensitivity and therefore, the amplitude must be assured. Thus, in case the SSTL driver is used, it is necessary that the strobe signal be once shifted from Hiz state to L state to assure the signal amplitude so that access time may be prolonged during memory write. 
     In the memory controller, the signal for data transfer is binary and the memory controller is set to have an impedance equal to the characteristic impedance of the wiring line. Namely, the Hiz state during no data transfer and the H state are at the same potential and the memory controller is driven with the same impedance as the characteristic impedance of the line. During L state of data, too, the L signal is driven with the same impedance as the characteristic impedance. This permits the reflection wave to be absorbed. 
     The amplitude remains unchanged for the case where the signal is driven from Hiz state to L state and the case where the signal is driven from H state to L state and therefore, signals passing through the coupler during two transfer operations have the same amplitude. In this manner, the same signal amplitude can be kept during any signal transition and the preamble is unneeded. Since the preamble is unneeded, the memory access time can be shortened to raise the bus utilization efficiency and the system performance can be promoted. 
     Next, a method of increasing the signal amplitude of memory write data will be described with reference to  FIGS. 24 and 25 . 
     As in the case of  FIG. 14 , the input impedance of the DRAM also matches the impedance of the wiring. Accordingly, as the data signal for memory write, a signal of the same amplitude as that of the signal generated by the directional coupler is inputted. This signal amplitude can be increased with the construction of  FIG. 24 . 
     A driver in the present embodiment is designated by reference numeral  51   a . A receiver  52  has the same construction as that in  FIG. 14 . As compared to  FIG. 14 , the driver  51   a  is added with a control signal (WRITE). Operation is indicated at table in  FIG. 24 . More particularly, when the WRITE signal is at H, operation is the same as that in  FIG. 14  but when the WRITE signal assumes L, transistors M 1  and M 2  also assume HiZ and as a result, the input impedance of the DRAM assumes HiZ. In other words, the impedance of driver  51   a  of the DRAM to which the WRITE signal at L is inputted becomes HiZ and the signal from the line undergoes total reflection. Thus, the signal amplitude from the line is doubled and then inputted to the receiver  52 . Accordingly, the sensitivity of the receiver  52  is increased as compared to that in  FIG. 14  and in addition, the noise margin is increased to raise the noise immunity. 
     The DRAM having this circuit is connected, in one to one relation, to a DRAM or a termination module having the same impedance as the characteristic impedance of the line through the directional coupler as shown in  FIG. 1 . Accordingly, even when the DRAM having the  FIG. 24  I/O circuit assumes HiZ and the signal from the directional coupler undergoes total reflection, a reflection wave can be absorbed if the WRITE signal for the other DRAM assumes H or the termination module is connected. Thus, even with the driver  51   a  rendered to assume HiZ, the signal on the line  1 - 2  for connecting the DRAM&#39;s is not disturbed to permit stable operation. 
     Next, the output timing of WRITE signal will be described with reference to  FIG. 25 . 
       FIG. 25  shows, like  FIG. 22 , an example where there is a vacancy of one stage between issuance of WRITE command and delivery of write data. The WRITE command is delivered out of the MC and reaches a DRAM after propagation delay time of the wiring line. This signal reaching the DRAM is designated at COMMANDRx. The DRAM receives, in addition to this WRITE command, a chip select signal and another control signal to recognize that the DRAM of its own is an object to be written. 
     After one stage following the issuance of the WRITE command, DQTx and DQSTx are delivered to reach the DRAM after the same wiring delay time. The reaching DQTx and DQSTx are designated at DQRx and DQSRx. The WRITE signal at negative logic is delivered after a WRITE command signal representing an internal signal of the DRAM is received. Then, the duration of L state of the WRITE signal is substantially equal to or longer than the burst length of data. Accordingly, during this period, the input impedance of the DRAM representing the write object assumes HiZ, so that the signal amplitude is doubled only during reception of the write data. Thus, the noise margin of the receiver can be assured and waveform distortion is lessened to permit stable operation. 
     Referring now to  FIG. 26 , there is illustrated an embodiment to which the memory bus system using directional couplers of the invention is applied. 
     In  FIG. 26 , four CPU&#39;s, generally designated at  30 , are mutually connected to a chip set  300  by a processor bus  201 . The chip set  300  incorporates a memory controller  10 - 1  for controlling DRAM&#39;s and the memory controller  10 - 1  is mutually connected to the DRAM&#39;s by a memory bus  202 . Further, an I/O LSI, generally designated at  50 , for connection of such a peripheral unit as a PCI (peripheral connect interface) is mutually connected to the chip set  300  by an I/O bus  203 . The chip set  300  is connected to a graphic control LSI  40  through a graphic bus  204  to form a graphic port. 
     These buses  201  to  204  are connected to the chip set  300  which is in charge of data transmission/reception between the buses  201  to  204 . 
     Here, data transfer using the couplers is applied to the memory bus  202 . Advantageously, this permit high-speed operation of memory access so as to improve the throughput and to shorten the latency, thereby improving the system performance. 
       FIG. 27  shows another embodiment to which the bus system is applied. In this embodiment, the memory bus system is applied to a cache memory bus  410  in a processor module  400  as shown in  FIG. 27  to attain comparable effects. In this case, couplers are formed in the processor module. For example, when a technique for packaging many semiconductors in one package, such as MCM (Multi Chip Module), is used, a processor incorporating a cache controller can be connected with a cache memory by means of packaged couplers to permit high-speed data transfer. 
     A fifth embodiment of the bus system will be described with reference to  FIG. 28 . 
     A signal of one bit of a bus essentially constructed of multiple bits is taken out in  FIG. 28  for convenience of explanation of the present embodiment. In the present embodiment, data transfer between one MC and two DRAM&#39;s is carried out by using one directional coupler to increase the signal level to be generated. 
     In the bus of the present embodiment, MC  10 - 1  and DRAM&#39;s  10 - 2  and  10 - 3  are connected and the MC  10 - 1  and DRA  10 - 3  have inner impedances, as viewed from their pins, which are equal to a characteristic impedance of the line, thus setting up so-called source impedance matching. The DRAM  10 - 2 , however, has an input impedance of HiZ. Of ends of a directional coupler C 1 , one end of line  1 - 2  on the MC  10 - 1  side is connected to the DRAM  10 - 2  and this line is very short. For example, in a mother board carrying the MC  10 - 1 , the DRAM  10 - 2  is directly attached immediately below the coupler C 1  in order to minimize the length of that wiring line. 
     A wiring line from the DRAM  10 - 3  other end of the coupler C 1  to a terminal (D) of DRAM  10 - 3  may have an appreciable length, for example, in the case of module configuration. It is to be noted that of the line  1 - 2 , a sub coupling line constituting the coupler merges, at its end on the DRAM  10 - 3  side, into a line vertically confronting an end (B) of sub coupling line  1 — 1  and extending therefrom. Thus, there is no extra wiring on the side of the sub coupling line. 
     Referring to  FIG. 29 , waveforms during memory write operation based on the wiring configuration of  FIG. 28  will be described. For convenience of explanation, it is assumed that the wiring length from the MC  10 - 1  to the coupler and the wiring length from the sub coupling line to the DRAM  10 - 3  are negligibly short. 
     Waveforms of memory write data from the MC  10 - 1  are illustrated in  FIG. 29 . A waveform at (A) is in source impedance matching and like the waveform (A) in  FIG. 4 , keeps a voltage (V 1 ), approximately half the drive voltage, during the period for reciprocative propagation delay time T 2  of the directional coupler. Thereafter, a reflection wave returns and the voltage rises to (2×V 1 ). At the end (B) of line  1 — 1  opposite to the MC  10 - 1 , a forward wave arrives after the delay time T 2  and at the same time, a reflection wave is generated. The reflection wave is superimposed on the forward wave to assume a voltage of (2×V 1 ). 
     A backward crosstalk signal (Kb×V 1 ) generated when the forward wave propagates from end (A) to end (B) through the coupler C 1  is transmitted to the terminal (C) of the line  1 - 2 . Since the (C) end assumes HiZ, the backward crosstalk signal undergoes total reflection so as to be doubled, producing a signal voltage of (2×Kb×V 1 ) at the terminal (C). 
     A voltage of (2×Kb×V 1 ) propagates to the terminal (D) of the line  1 - 2 . This results from the superimposition of the two backward crosstalk signals. 
     To explain, a signal generated at the (C) end by the forward wave in the coupler C 1  is reflected at the end (C) of the line  1 - 2 , thus forming the first backward crosstalk that propagates to the end (D) of line  1 - 2 . This propagating signal assumes Kb×V 1 . The forward wave propagating through the coupler C 1  is reflected at the (B) end of wiring line  1 — 1  and a reflection wave generates the second backward crosstalk signal (Kb×V 1 ) at the (D) end of line  1 - 2  through the coupler C 1 . These two backward crosstalk signals are in phase and superimposed on each other in phase to generate the doubled signal (2×Kb×V 1 ). The input impedance of the DRAM  10 - 3  matches the characteristic impedance of the wiring line and therefore the wave is absorbed at the terminal of the DRAM  10 - 3  without undergoing reflection again. In this embodiment, the signal amplitude is doubly increased as compared to that in  FIG. 4 . 
     Namely, during the memory write operation, reflection at the ends (C) and (D) is utilized to double the signal amplitude. Accordingly, the noise immunity of the DRAM&#39;s  10 - 2  and  10 - 3  is promoted to realize stable and high-speed data transfer. 
     Waveforms during memory read operation based on the wiring configuration of  FIG. 28  will be described with reference to  FIG. 30 . 
       FIG. 30  shows waveforms of memory read data from the DRAM  10 - 2 . The driver of the DRAM  10 - 2  is driven through an impedance lower than the characteristic impedance of the line and therefore a waveform of substantially full amplitude (2×V 1 ) is delivered to the end (C). The driven signal is absorbed at the end (D) after delay time T 2 . This is because by virtue of the source impedance matching function owned by the DRAM  10 - 3 , matching termination is set up. The signal from DRAM  10 - 2  transmitting through the line  1 - 2  generates backward crosstalk and a voltage developing at the end (A) assumes 2×V 1 ×Kb. It is to be noted that source impedance matching is also set up at the end (A) and no reflection takes place there. 
       FIG. 31  shows memory read data waveforms from the DRAM  10 - 3 . 
     An output from the DRAM  10 - 3  having the source impedance matching driver has amplitude (V 1 ) which is half the power supply voltage and it assumes full amplitude owing to a reflection wave after (2×T 2 ) as in the case of  FIG. 29 . A drive signal voltage heading for the end (C) from the end (D) through the sub coupling line generates a backward cross voltage (V 1 ×Kb) at the end (B) and immediately thereafter, it is reflected at the end (B) so as to head for the end (A). Further, a signal undergoing total reflection at the end (C) of the sub coupling line is then returned toward the end (D). At that time, a backward crosstalk signal (V 1 ×Kb) is also generated at the end (A) of the sub coupling line. The two signals on the sub coupling line superimpose each other in phase to generate a doubled signal at the end (A). Accordingly, the memory read data from the DRAM  10 - 3  also assumes (2×V 1 ×Kb) and the signal level is doubled. 
     As will be seen from the above, for the memory read data from the DRAM&#39;s  10 - 2  and  10 - 3 , the signal level can also become (2×V 1 ×Kb). 
     In this manner, during both the memory write operation and the memory read operation, the signal amplitude can be doubled amounting up to (2×V 1 ×Kb) and consequently, in the data transfer between the MC  10 - 1  and the DRAM&#39;s  10 - 2  and  10 - 3 , the noise immunity can be promoted and stable and high-speed data transfer can be realized. 
     As shown in  FIGS. 32 and 33 , the above behavior of memory access is confirmed through simulation. 
       FIG. 32  shows memory write data waveforms delivered out of the MC  10 - 1 . The coupling line has geometrical dimensions indicated in the wiring sectional view of  FIG. 7  and the wiring length of the coupler is the same as that in  FIG. 8 , amounting up to 40 mm. In  FIGS. 32 and 33 , it is assumed as in the precedence that the wiring lengths of a lead wiring of line  1 — 1  from the MC  10 - 1  to the coupler and a wiring line of line  1 - 2  from the sub coupling line to the DRAM  10 - 3  are negligibly short. 
     Results of the simulation show that in the memory writ data waveforms of  FIG. 32 , the signal assumes, at the ends (C) and (D), about 390 mV that is about 1.8 times the 220 mV level at the ends K 1  and J 1  in  FIG. 9 . This results from the fact that the crosstalk superimposes on the reflection wave in phase as described previously. 
       FIG. 33  shows data waveforms during memory read from the DRAM  10 - 2 . The output impedance of the DRAM  10 - 2  amounts to 10Ω that is lower than the characteristic impedance of the wiring, and so the DRAM  10 - 2  is driven at substantially full amplitude to propagate data to the end (A), that is, the MC  10 - 1  by means of the directional coupler C 1  in  FIG. 28 . The signal amplitude at that time is also about 320 mV, indicating that the signal amplitude is substantially the same as that in  FIG. 11 . As will be seen from  FIGS. 32 and 33 , the time width of the generated signal equals the reciprocative propagation delay time (2×T 2 ) amounting up to 0.48 ns and it also equals the backward crosstalk width in  FIGS. 9 ,  11  and  12 . 
     Data transmission waveforms from the DRAM  10 - 3  to the MC  10 - 1  are substantially the same as those in  FIG. 32 . This is because the load condition as viewed from the DRAM  10 - 3  substantially coincides with the load condition as viewed from the MC  10 - 1 . The load condition as viewed from the DRAM  10 - 3  covers the wiring to the coupler and the directional coupler not terminated, and the wiring condition for the other wiring  1 — 1  constituting the coupler is MC  10 - 1  in which the near end is open and the remote end is terminated with respect to DRAM  10 - 3  and is equal to the load condition as viewed from MC  10 - 1 . The load condition of the DRAM  10 - 3  differs from the load condition of the MC  10 - 1  only in that the DRAM  10 - 2  is connected to the wiring line on the DRAM  10 - 3  side. But the input impedance of the DRAM  10 - 2  is HiZ and is regarded as substantially open-ended and so the read data waveforms from the DRAM  10 - 3  are substantially identical to those in  FIG. 32 . In other words, in  FIG. 32 , waveform (A) in dotted line corresponds to the output waveform form the DRAM  10 - 3 , waveform (B) corresponds to a waveform at the end (C) of DRAM  10 - 2 , waveform (C) corresponds to a waveform at the end (B) and waveform (D) corresponds to the input waveform to the MC  10 - 1 . 
     The results of the simulation as above show that with the construction of  FIG. 28 , both the memory write data signal from the MC  10 - 1  and the read data waveforms from the DRAM&#39;s  10 - 2  and  10 - 3  have the amplitude in excess of 350 mV and the signal voltage for memory write is increased as compared to that in FIG.  1 . 
     In the fifth embodiment of  FIG. 28 , the bus system can be packaged as shown in  FIGS. 34 and 35  in sectional form. 
     Like  FIGS. 15 and 16 ,  FIG. 34  shows a mother board  1  in longitudinal sectional form. In  FIG. 34 , the DRAM  10 - 2  having the input impedance Hiz in  FIG. 28  is directly packaged to the mother board  1  and the DRAM  10 - 3  having the input impedance in source impedance matching is packaged to a memory module  2 — 2  and connected to the mother board through a connector. A directional coupler for connecting the individual chips is formed in the mother board  1  and the line  1 — 1  including the sub coupling line from the MC  10 - 1  is formed in a layer m 1 , with the line  1 - 2  including the sub coupling line formed in a layer x 1 . It is to be noted that the main line  1 — 1  ends at a point where the sub coupling line  1 - 2  is led to the memory module  2 — 2 . Advantageously, this permits the backward crosstalk to superimpose on the reflection in phase so as to amplify the signal. 
     The DRAM  10 - 3  has been described as being terminated (being in source impedance matchin) but a method may of course be employed in which an external resistor is added to the DRAM having the input impedance HiZ to cause it to be terminated. In that case, the DRAM&#39;s  10 - 2  and  10 - 3  having the same construction can be used. 
     In  FIG. 35 , a termination board  2 – 2 ′ is inserted in the connector in place of the memory module  2 — 2  in  FIG. 34 . This example is therefore applicable to a system in which the memory capacity required by the system is satisfied at the minimum from the standpoint of the system construction by packaging the DRAM  10 - 2  and the system constructed as shown in  FIG. 35  is shipped without alteration. When the memory is required to be expanded later with the aim of, for example, improving the system performance, the termination board  2 – 2 ′ in  FIG. 35  is removed and the memory module  2 — 2  carrying the DRAM  10 - 3  as shown in  FIG. 34  can be inserted to expand the memory. Thus, the packaging method having potential expandability of the system as shown in  FIGS. 34 and 35  can be employed in the present embodiment. 
     Even when the DRAM  10 - 2  is not carried but only the memory module  2 — 2  is carried in  FIG. 34 , the same signal can be generated to permit data transfer between the MC  10 - 1  and the DRAM  10 - 3 . Even when restriction imposed on packaging prevents the DRAM  10 - 2  to be carried, the signal level can be doubled to advantage. 
     A sixth embodiment of the bus system will be described with reference to  FIG. 36 . 
     In comparison with the fifth embodiment of  FIG. 28 , the capacity of DRAM&#39;s that can be carried is increased in the present embodiment. 
     In a bus of the present embodiment, MC  10 - 1  and DRAM&#39;s  10 - 2  to  10 - 5  are connected and the inner impedance of each of the MC  10 - 1  and DRAM&#39;s  10 - 3  and  10 - 5 , as viewed from its pin, is equal to the characteristic impedance of the line, thus being in source impedance matching. The input impedance of each of the DRAM&#39;s  10 - 2  and  10 - 4  is HiZ. Sub coupling lines  1 - 2   a  and  1 - 2   b  constitute a directional coupler C 1  and the DRAM  10 - 2  is connected to one end of the sub coupling line  1 - 2   a , with the DRAM  10 - 4  connected to one end of the sub coupling line  1 - 2   b . For example, the DRAM&#39;s  10 - 2  and  10 - 4  can be directly attached immediately below and above the coupler C 1  in the mother board carrying the MC  10 - 1 , respectively. 
     The wiring lines from the other ends of the sub coupling lines  1 - 2   a  and  1 - 2   b  constituting the coupler C 1  to the DRAM&#39;s  10 - 3  and  10 - 5  can have an appreciable length as in the case of the module configuration of  FIG. 34 . But, the other ends of the sub coupling lines on the side of the DRAM&#39;s  10 - 3  and  10 - 5  are led vertically of the sub coupling line at positions confronting the end of the sub coupling line and the sub coupling line does not jut out of or is not short of the sub coupling lines. 
     In the directional coupler C 1 , the wiring lines  1 - 2   a  and  1 - 2   b  are laid on both sides of the line  1 — 1  connected to the MC  10 - 1  and they are so adjusted as to have the same backward crosstalk coefficient. In other words, the lines  1 - 2   a  and  1 - 2   b  are arranged to have the same line width, the same wiring length, and the same pitch with respect to the main line. Since the lines  1 - 2   a  and  1 - 2   b  are constructed in this manner, the memory write data signal has the same waveform for the DRAM&#39;s  10 - 2  and  10 - 4  or the DRAM&#39;s  10 - 3  and  10 - 5  as described in connection with  FIG. 29 . In other words, for the DRAM&#39;s  10 - 2  to  10 - 5 , the signal amplitude is uniformly increased so as to be doubled, amounting up to (2×Kb×V 1 ), by virtue of the superimposition of the reflection wave. 
     In the directional coupler C 1 , the sub coupling lines  1 - 2   a  and  1 - 2   b  are so constructed as to have the same coupling coefficient with respect to the line  1 — 1  connected to the MC  10 - 1  as described previously and therefore, waveforms of memory read data from the DRAM&#39;s  10 - 2  and  10 - 4  similarly have the same amplitude, amounting to (2×Kb×V 1 ) as described in connection with  FIG. 30 . The memory read waveforms from the DRAM  10 - 3  or  10 - 5  also have the same magnitude as that in  FIG. 31 , amounting up to (2×Kb×V 1 ). 
     With the construction shown in  FIG. 36 , the four DRAM&#39;s  10 - 2  to  10 - 5  can be connected to one MC  10 - 1  and the memory capacity can advantageously be increased as compared to the fifth embodiment. Obviously, the DRAM&#39;s  10 - 3  and  10 - 5  may be carried in modules and when the system suffices less memory capacity, the module may terminate in a terminating board but when extension is needed the memory modules may be exchanged with those packaging the DRAM&#39;s  10 - 3  and  10 - 5 , thus providing the system with memory extensibility. 
     A seventh embodiment of the bus system will be described using  FIG. 37 . 
     In the present embodiment, connecting means such as a MOS switch intervenes in the sub coupling line of  FIG. 36  to expand the memory carrying capacity. 
     There are provided MOS switches  3 - 1  and  3 - 2  that are controllable by switching means (selector)  4  provided in MC  10 - 1 . The MOS switches  3 - 1  and  3 - 2  are inserted in a line  1 — 1  connected to the MC  10 - 1  and a partial line  1 — 1  (A) between the MOS switch  3 - 1  and the MC  10 - 1  cooperates with lines  1 - 2   a  and  1 - 2   b  to form a directional coupler C 1 . A partial line  1 — 1  (B) between the MOS switches  3 - 1  and  3 - 2  cooperates with lines  1 - 3   a  and  1 - 3   b  to form a directional coupler C 2 . A partial line  1 — 1  (C) between the MOS switch  3 - 2  and the end cooperates with lines  1 - 4   a  and  1 - 4   b  to form a directional coupler C 3 . The coupler C 1  is connected with DRAM&#39;s  10 - 2  to  10 - 5 , the coupler C 2  is connected with DRAM&#39;s  10 - 8  to  10 - 9  and the coupler C 3  is connected with DRAM&#39;s  10 — 10  to  10 - 13 . The connection mode between the couplers C 1  to C 3  and the DRAM&#39;s  10 - 2  to  10 - 1  is the same as that in  FIG. 36 . 
     When data is transferred between the MC  10 - 1  and one of the DRAM&#39;s  10 - 2  to  10 - 5 , the MOS switch  3 - 1  is controlled by the switching means  4  such that the partial line  1 — 1  (A) is disconnected from the partial line  1 — 1  (B). Consequently, a signal propagating on the partial line  1 — 1  (A) undergoes substantially total reflection at the end of the MOS switch  3 - 1 . Accordingly, the MC  10 - 1  and the DRAM&#39;s  10 - 2  to  10 - 5  operate in quite the same way as that in  FIG. 36 . 
     Next, in case data is transferred between the MC  10 - 1  and one of the DRAM&#39;s  10 - 6  to  10 - 9 , the MOS switch  3 - 1  is controlled by the switching means  4  such that the partial line  1 — 1  (A) conducts to the line  1 — 1  (B) and the MOS switch  3 - 2  is controlled by the switching means  4  such that the partial line  1 — 1  (B) is disconnected from the partial line  1 — 1  (C). Consequently, a signal propagating on the partial line  1 — 1  (B) undergoes substantially total reflection at the end of the MOS switch  3 - 2 . Accordingly, the MC  10 - 1  and the DRAM&#39;s  10 - 6  to  10 - 9  operate in quite the same way as that in  FIG. 36 . The DRAM&#39;s  10 - 2  to  10 - 5  and the lines  1 - 2   a  and  1 - 2   b  do not contact the partial line  1 — 1  (A) and the partial lines  1 — 1  (A) and  1 — 1  (B) have the same characteristic impedance, so that the signals transmitting on the lines  1 — 1  (A) and  1 — 1  (B) are not distorted. Of course, it is preferable that the conduction resistance of the MOS  3 - 1  is very smaller than the line impedance. Advantageously, this suppresses waveform distortion due to impedance mismatch. 
     Similarly, in case data is transferred between the MC  10 - 1  and one of the DRAM&#39;s  10 — 10  to  10 - 13 , the MOS switches  3 - 1  and  3 - 2  are controlled by the switching means  4  such that they are rendered to be placed in conduction. Consequently, a signal propagating on the partial line  1 — 1  (C) undergoes substantially total reflection at the remote end. Accordingly, the MC  10 - 1  and the DRAM&#39;s  10 - 9  to  10 - 13  operate in quite the same way as that in  FIG. 36 . 
     By rendering the MOS switches  3 - 1  and  3 - 2  non-conductive or conductive in this manner, data can be transferred selectively between the MC  10 - 1  and one of the DRAM&#39;s  10 - 2  and  10 - 13 . In other words, as compared to the case of  FIG. 36 , the number of DRAM&#39;s to be carried on the system can be increased to advantage. The switching means may be used in common with a signal of chip selector used in the DRAM. 
     Further, it depends on the condition of the system whether all of the DRAM&#39;s  10 - 2  to  10 - 13  are carried. Accordingly, a small number of DRAM&#39;s are first carried and as the function extension is requested, DRAM&#39;s may be added. The terminating board  2 – 2 ′ as shown in  FIG. 35  may be used, as necessary. 
     An eighth embodiment of the bus system will be described by using  FIG. 38 . 
     In  FIG. 38 , a directional coupler C 1  is constituted by a wiring line  1 — 1  and lines  1 - 2   a  and  1 - 2   b  laid on both side of the wiring line  1 — 1  equidistantly from the wiring line  1 — 1  in close proximity and in parallel relation thereto, as in the case of  FIG. 36  and in particular, ends of the lines  1 - 2   a  and  1 - 2   b , close to MC  10 - 1 , are connected in common to the MC  10 - 1 . The other ends of the lines  1 - 2   a  and  1 - 2   b  merge into lead lines extending vertically of the line  1 — 1  toward DRAM&#39;s  10 - 2  and  10 - 3 . 
     The input impedance owned by each of the DRAM&#39;s  10 - 2  and  10 - 3  changes depending on whether access to its memory is present. In the presence of the memory access, the input impedance assumes HiZ and in other cases, it is placed in source impedance matching condition. The MC  10 - 1  is always placed in source impedance matching condition. With this construction, the signal level can be increased by four times, amounting up to 4×Kb×V 1 . 
       FIG. 39  shows simulation waveforms of data during memory write. The simulation condition is the same excepting for a portion concerning wiring. A mechanism is as below. In the figure, waveforms for data transfer from the MC  10 - 1  to the DRAM  10 - 2  are illustrated. 
     An output from terminal (A) of the MC  10 - 1  is a step-like wave because the impedance of the MC  10 - 1  equals the characteristic impedance of the wiring. A signal propagating on the line  1 — 1  is designated by V 1 . This signal generates backward crosstalk in the lines  1 - 2   a  and  1 - 2   b  and the backward crosstalk amounts up to Kb×V 1 . The backward crosstalk generated in the line  12   b  propagates to terminal (D) through the line  1 - 2   a . The signal propagating through the line  1 — 1  undergoes total reflection at the terminal (B) and this reflection wave again generates backward crosstalk in the lines  1 - 2   a  and  1 - 2   b . The thus generated backward crosstalk amounts up to (Kb×V 1 ) and superimposes, in phase, on the backward crosstalk generated in the line  1 - 2   b  by a forward wave on the line  1 — 1 . Consequently, the amplitude of the signal heading for the DRAM  10 - 2  on the line  1 - 2   a  is (2×Kb×V 1 ). Further, when the signal reaches the terminal (D) of the DRAM  10 - 2 , it undergoes total reflection there because the input impedance of the DRAM  10 - 2  is HiZ and as a result, it takes a signal waveform of (4×Kb×V 1 ) In  FIG. 36 , it amounts up to about 640 mV. The time width of this signal is 0.48 ns equaling the reciprocative propagation delay time of the coupler C 1 . It will therefore understood that only the signal amount is increased. 
     Similarly, by matching the impedance of the DRAM  10 - 2  to the characteristic impedance of the wiring and making the input impedance of the DRAM  10 - 3  HiZ, data transfer from the MC  10 - 1  to the DRAM  10 - 3  has the same waveforms as those in  FIG. 39  and write data can be transferred in the form of a signal of (4×Kb×V 1 ). Next,  FIG. 40  shows simulation waveforms of memory read data from the DRAM  10 - 2  to the MC  10 - 1 . 
     The output impedance of the DRAM  10 - 2  is lower than the characteristic impedance of the line, amounting up to 10Ω. Accordingly, the amplitude of drive waveform (D) is substantially full, amounting up to about (2×V 1 ) and backward crosstalk amounting to (2×Kb×V 1 ) is generated in the line  1 — 1  by this drive signal toward the terminal (B). At the termination (B), the backward crosstalk undergoes total reflection and this backward crosstalk, as it is, propagates toward the terminal (A). A drive waveform from the DRAM  10 - 2  propagates to the line  1 - 2   b  through the line  1 - 2   a  and the drive waveform propagating on the line  1 - 2   b  generates backward crosstalk having an amplitude of (2×Kb×V 1 ) in the line  1 — 1 . This backward crosstalk superimposes, in phase, on the backward crosstalk previously reflected at the terminal (B) to generate a signal of (4×Kb×V 1 ) which in turn is inputted to and terminated in the MC  10 - 1 . It will be seen that in  FIG. 40 , a voltage of about 580 mV is inputted to the terminal (A). The signal waveform has the same time width as that in  FIG. 39 . 
     Referring to  FIG. 41 , the input impedances of the MC  10 - 1  and DRAM&#39;s  10 - 2  and  10 - 3  during each memory access are indicated. The MC  10 - 1  is in source impedance matching during memory write and memory read and this is indicated by RTT. During memory write, a targeted DRAM assumes HiZ but a non-targeted DRAM is placed in RTT condition. During memory read, a DRAM delivering memory read data has a low output impedance (LOW) but a DRAM not delivering data has its impedance being RTT. It can be recognized by a chip select (CS) signal whether the DRAM&#39;s  10 - 2  and  10 - 3  are objects in charge of data transfer. 
     Through construction and operation as above, the signal can be approximately four times increased, amounting to (4×Kb×V 1 ). In other words, even when the drive signal is reduced in amplitude, a sufficient signal level can be obtained to advantage. Obviously, by cascading the MOS switches as shown in  FIG. 38 , the number of DRAM&#39;s connected to the bus can be increased. 
     Still another embodiment of the I/O circuit will be described by using  FIG. 42 . 
       FIG. 42  shows the construction of an I/O circuit of DRAM or MC  10 - 1  having a driver and receiver or termination means. Reference numeral  53  designates termination means,  51 - 1  a driver,  52 - 1  a receiver having a hysteresis characteristic and  52 - 2  a receiver not having any hysteresis characteristic. Switching means  73  switches the receivers  52 - 1  and  52 - 2 . Bonding switching means  72  is connected when a semiconductor device including the present I/O circuit is fabricated and is transferable to either VDD or GND during fabrication. In the figure, VDD or HIGH logical signal is applied to the switching means  73 . Similarly, means  71  can be switched during fabrication to either turn on or turn off the termination means  53 . 
     Therefore, even in the case where the input impedance of the DRAM  10 - 2  differs from that of the DRAM  10 - 3  as in the case of, for example,  FIG. 28 , these DRAM&#39;s are formed using the same semiconductor mask but two functions can be provided using one mask when the bonding switching means  71  is switched during fabrication. Similarly, the receiver  52 - 2  such as SSTL representing the conventional DRAM interface and the receiver  52 - 1  having the hysteresis characteristic suitable for the directional coupler can be formed using the same semiconductor mask and are switched during fabrication, thereby reducing the fabrication cost. 
     Still another embodiment to which the bus system is applied will be described by using  FIG. 43 . 
     In the present embodiment, a portion consisting of a plurality of chips is packaged in one multi-chip module as in the case of the processor module  400  in  FIG. 27  and the previous embodiment, for example, the wiring method of  FIG. 28  is applied. A processor (CPU)  31  and a cache memory  32  are provided in a multi-chip module (MCM)  400  and data transfer between them can be carried out through the wiring system shown in  FIG. 28 , that is, the directional coupler C 1 . Accordingly, high-speed data transfer can be ensured between the CPU  31  and the cache memory  32 . Of course, the multi-chip module can be handled as a device that is improved in performance by having not only the function of CPU  31  but also the additional function of cache memory  32 . Further, there is no need of providing MCM  400  for data transfer between the CPU  31  and the cache memory  32  in a printed circuit board packaging the CPU  31  and therefore, the construction of the printed board can be simplified to advantage. 
     As has been described in the foregoing embodiments, in the present invention, the remote end of the main line connected to the MC is made to be open-ended or short-circuited to cause total reflection and the reflection wave and a forward wave are used to generate backward crosstalk at the opposite ends of the directional coupler, thereby ensuring that data transfer can be effected between the DRAM and the MC connected to the opposite ends of the directional coupler, respectively. The directional coupler is used in common by two DRAM&#39;s to halve the pitch between DRAM modules. 
     The open-ended or short-circuited main line is folded and directional couplers are formed in cooperation with the folded main line, so that the pitch between the DRAM modules can be ¼ of the coupler wiring line length of the directional coupler. 
     Further, by setting up open-end or short-circuit for a signal of the DRAM, the DRAM in connection can selectively assume positive logic or negative logic and as a result, the number of signals such as chip select signals to be controlled exclusively can be reduced to advantage. 
     In the memory controller, a signal for data transfer is made to be binary and the impedance for the binary signal is made to be equal to a characteristic impedance of the wiring on the memory controller side. More particularly, the HiZ state for no data transfer and the H state are at the same potential such that the memory controller is driven through the impedance equal to the characteristic impedance of the wiring. When data is in L state, L signal is also driven through the impedance equal to the characteristic impedance. Through this, the reflection wave can be absorbed. 
     The amplitude remains unchanged when the signal is driven from HiZ state to L state and when the signal is driven from H state to L state and consequently, signals passing through the coupler during two transfer operations have the same amplitude. Thus, the signal amplitude remains unchanged during any transition of signal and the preamble can be unneeded. Since the preamble becomes unnecessary, the memory access time can be shortened and the bus utilization efficiency can be raised to thereby improve the system performance.