Patent Publication Number: US-6903578-B2

Title: Logic isolator

Description:
RELATED APPLICATIONS 
   This application claims the benefit under 35 U.S.C. § 120 of U.S. application Ser. No. 10/373,903, entitled “LOGIC ISOLATOR FOR TRANSMITTING PERIODIC SIGNALS ACROSS AN ISOLATION BARRIER,” filed on Feb. 25, 2003, which is herein incorporated by reference in its entirety. 

   BACKGROUND OF THE INVENTION 
   This invention relates to a logic isolator for transmitting digital logical signals across an isolation barrier. 
   A logic isolator is a device or circuit for transmitting status or control signals across an isolation barrier from a sending side to a receiving side. The two sides are electronically isolated such that transient signals do not inadvertently trigger erroneous status or control information. U.S. Pat. No. 5,952,849, which is commonly assigned with the present application and is expressly incorporated by reference herein, shows circuitry for providing such isolation with a transformer as the barrier. Other barriers that are used include capacitors or optical devices. 
   In a logic isolator, when a signal is received having a low to high transition and then a high to low transition, the system can transmit across the barrier either a signal that is essentially the same as the signal that is received on the input side; alternatively, using two lines through a flip-flop, it can transmit a pulse on one line indicating a low to high transition, and a pulse on the other line indicating a high to low transition. The use of such pulses are shown, for example, in the incorporated patent. 
   The incorporated patent also shows the use of refresh pulses to indicate a current state of the logic line in addition to the changes in the state. This feature is useful because a logic line could be in one state for an extended period of time, and thus the refresh pulse tells the receiving side the state so the receiving side can distinguish no change from an error in the system. 
   SUMMARY OF THE INVENTION 
   A logic isolator has an input for providing a logic signal, an isolation barrier, a transmitter circuit for transmitting to the isolation barrier a signal indicating changes from one state to another in the logic signal, and a receiver circuit for receiving from the isolation barrier the signal indicating changes in the state and providing an output signal indicating changes in the logic signal. The output signal may also indicate the state of the logic signal. The transmitter circuit receives logical transitions and provides a periodic signal across the isolation barrier. The receiver circuit then receives these periodic signals and converts them to transitions as provided at the input. 
   The periodic signal can be provided as a short burst that indicates that a transition in state has appeared. Alternatively, the periodic signal can be provided in a continuous manner, thus indicating both changes in the state and the state of the logic signal itself. The system preferably uses two separate lines and barriers so that, in the burst embodiment, the presence of the periodic signal on one line indicates a low to high transition, and on the other line indicates a high to low transition; in the continuous embodiment, a continuous periodic signal on one line indicates a high state, and on the other line indicates a low state. 
   The isolation barrier preferably includes a transformer, which may or may not be shielded, although the isolation barrier could employ some other method, such as capacitive coupling. 
   The invention also includes methods for transmitting logic signals across an isolation barrier, including converting a transition in a logic signal to a periodic signal, transmitting the periodic signal across an isolation barrier, receiving the periodic signal from the isolation barrier in a receiving circuit, and converting that periodic signal to a logical transition. The transmitting and converting processes may be with a short periodic signal that indicates a transition in the signal or a longer signal that continuously indicates the state of the signal. 
   In the burst mode of operation, refresh pulses can be provided as described in the incorporated patent to periodically indicate the state of the logic signal. In the continuous mode, refresh signals are not required because the periodic signal continuously indicates the state of the logic signal. The device preferably also includes detection circuitry for indicating when there has been a disconnection across the barrier, in particular to distinguish an intentionally high or low state, and the loss of a connection. 
   A continuous signal can also be provided through frequency modulation and demodulation, whereby an oscillator transmits to the isolation barrier a first frequency for a first state and a second frequency for a second state. A receiver circuit includes a frequency discriminator to determine the state from the signal received from the isolation barrier. 
   Other features and advantages will become apparent from the following description of preferred embodiments, drawings, and claims. 

   
     BRIEF DESCRIPTION OF THE DRAWINGS 
     The accompanying drawings, are not intended to be drawn to scale. In the drawings, each identical or nearly identical component that is illustrated in various figures is represented by a like numeral. For purposes of clarity, not every component may be labeled in every drawing. In the drawings: 
       FIG. 1  is a block diagram of a logic isolator circuit; 
       FIG. 2  is a set of waveforms showing the conversion of the transitions to a periodic signal in a burst mode and a continuous mode; 
       FIGS. 3 and 3A  are a schematic of a transmitter and a waveform diagram; 
       FIGS. 4 and 5 , and  4 A and  5 A, are schematics of receiver circuits and waveform diagrams; 
       FIG. 6  is a schematic of the output of two receivers and error detection circuitry; 
       FIG. 7  is a schematic of a receiver with a capacitively coupled isolation barrier; 
       FIGS. 8 and 8A  are a schematic and a waveform diagram of a system that uses frequency modulation and demodulation across a barrier; and 
       FIGS. 9 and 9A  are a schematic and a waveform diagram of a phase modulated isolator. 
   

   DETAILED DESCRIPTION 
   This invention is not limited in its application to the details of construction and the arrangement of components set forth in the following description or illustrated in the drawings. The invention is capable of other embodiments and of being practiced or of being carried out in various ways. Also, the phraseology and terminology used herein is for the purpose of description and should not be regarded as limiting. The use of “including,” “comprising,” or “having,” “containing”, “involving”, and variations thereof herein, is meant to encompass the items listed thereafter and equivalents thereof as well as additional items. 
   Referring to  FIGS. 1 and 2 , input signal  10  is provided to a Schmitt trigger  12  to produce an input signal LOGIC IN. LOGIC IN is provided to a first transmitter circuit  14  and through an inverter  16  to a second transmitter circuit  18 . Transmitter circuits  14  and  18  each provide a signal across an isolation barrier  20  to a respective receiver  22  and  24 . The receivers each provide an output to one of two inputs of a flip-flop  26 , the output of which is a logic output signal that indicates transitions in the LOGIC IN signal. 
   Referring also to  FIG. 2 , LOGIC IN is shown with a low to high transition  30  and a high to low transition  32 . In one embodiment referred to here as the burst mode, transition  30  is converted by transmitter circuit  14  to a short periodic burst as shown on signal (A), and transmitter circuit  18  converts transition  32  into a short burst as shown in signal (B). After being transmitted across barrier  20 , receiver circuits  22  and  24  convert these burst signals into pulses as indicated by signals (C) and (D). These pulses are provided to the set and reset terminals of the flip-flop to produce a logic signal that is essentially the same as LOGIC IN. Refresh pulse circuitry such as that shown in the incorporated patent could be added to the transmitter circuitry so that pulses are sent on signals (C) and (D) when the signal is high and low, respectively, e.g., at 3 to 4 microsecond intervals. 
   In another embodiment referred to here as the continuous mode, the transmitter circuits provide a continuous periodic signal indicating the state of LOGIC IN. Thus, signal (A′) has a continuous periodic signal when LOGIC IN is high, and signal (B′) has a continuous periodic signal when LOGIC IN is low. The continuous mode thus indicates not only transitions but also the state at any given time, such that the output can be corrected very quickly, e.g., in 1 nanosecond. 
   Barrier  20  can include coils, and electromagnetic immunity is provided by switches  25  and  27 , which short out the respective windings when not transmitting data. 
   Referring to  FIG. 3 , an embodiment of a transmitter  14  or  18  is shown. Transmitter circuit  14  has a ring oscillator  40  with inverters  42 ,  44  and NAND gate  46 . With an odd number of inverting logic gates connected in a ring, when an input signal is provided to the NAND gate from node  62 , the output signal at node  50  will be a periodic signal, with a transition from high to low in the periodic signal equal to the sum of the propagation delays through inverters  42 ,  44  and NAND gate  46 , and thus the period of the signal is twice that sum. 
   Referring also to  FIG. 3A , LOGIC IN is provided through an inverter  56  to the control terminal of a transistor Q 1  at node  60 . When LOGIC IN is low, transistor Q 1  is turned on, thereby shunting the signal at node  54  and providing a low output. 
   The signal on node  60  is also provided to another inverter  57  and to a control terminal of transistor Q 2 . When LOGIC IN is low, node  61  is low, and transistor Q 2  is off. Node  63  is thus high through its coupling to a supply rail through resistor R. Capacitors C 1  and C 2  are thus each charged, capacitor C 1  through NAND gate  46 , and capacitor C 2  through the voltage supply with node  54  provided through transistor Q 1 . 
   When LOGIC IN goes high and transistor Q 1  shuts off, capacitors C 1 , C 2 , and C 3  are all discharged through a coil  52 , which is part of the isolation barrier. 
   As shown in  FIG. 3A , LOGIC IN is shown as a signal with a low to high transition and a high to low transition. The signal on node  50  is high (when LOGIC IN is high, and it oscillates when LOGIC IN is low. The signal on node  63  is transferred to the coil in response to the low to high transition in LOGIC IN. On the high to low transition, the turning on of transistor Q 1  produces a fast shut-off. 
   The circuit of  FIG. 3  will thus provide a continuous periodic signal during the time that LOGIC IN is high. At the same time, as indicated in  FIG. 1 , an inverted signal is provided to another transmitter that provides a continuous periodic signal when LOGIC IN is low using essentially the same circuitry. The signal that is provided to the isolation barrier is thus of the continuous mode type as shown in signals A′ and B′ of FIG.  2 . Inverter  16  ( FIG. 1 ) uses non-overlap timing to prevent both signals from being high at the same time. 
   To convert the circuit of  FIG. 2  from one for use in the continuous mode to one for use in the burst mode (as shown with signals A and B of FIG.  2 ), a monostable multivibrator (known as a “one-shot”) is inserted at node  62 . A one-shot detects an edge of a signal and outputs a pulse with a width set by the circuitry of the one-shot. With a one-shot, in response to a transition edge, the signal provided to node  48 , capacitor C 2 , and transistor Q 1  is a pulse instead of a continuous level until the state changes. Consequently, the periodic signal is a burst of a periodic signal for some period. The width of the pulse from the one-shot should be sufficiently long so that several cycles of the periodic signal are transmitted to the isolation barrier, e.g., three to five cycles at 1.1 GHz. 
   The coils can be formed on a chip as 2×4 micron copper, about 20 to 25 nHy, with high Q and self-resonant frequencies in a range of about 300 MHz to 1.5 GHz. The secondaries can be formed on a chip with an electrostatic (Faraday) shield over the secondaries and the primaries over the shield. The shield provides high transient voltage immunity. The circuitry can thus be provided as a structure as shown in W099/21332, with the GMR replaced by two coils, or with the coils and GMR replaced with four capacitor plates. 
   Alternative receiver circuits are shown in  FIGS. 4 and 5 , with the receiver circuit of  FIG. 4  being adapted for use with the burst mode of operation, and the receiver circuit of  FIG. 5  for use with the continuous mode. The two circuits have in common that each receives a periodic signal and rectifies it in some manner. 
   Referring to  FIG. 4 , coil  60  receives the induced signal from coil  52  (FIG.  3 ). That periodic signal on coil.  60  is provided to a source follower transistor Q 2  with a drain coupled to a supply rail and a source coupled to an RC circuit that rectifies the periodic signal. 
   Referring also to  FIG. 4A , an input and resulting output are shown with a short burst of a periodic signal. A pulse is also shown for comparison and for explanation. If a pulse is input into transistor Q 2 , on the leading edge of the pulse, the capacitor is charged until the pulse goes low, at which time the voltage on the capacitor decays with a time constant that is a function of the resistance and capacitance of the RC circuit. Similarly with a burst  66  of the periodic signal, the capacitor is charged until the signal goes negative, at which time the capacitor is discharged. Because the periodic signal has sufficiently high frequency relative to the RC time constant, the capacitor does not have sufficient time to discharge, and thus the resulting output is similar to that from a pulse. The output from the RC circuit can also be coupled to a Schmitt trigger. 
   As indicated in  FIG. 1 , there would typically be two such receivers which may be coupled to a flip-flop such that the set and reset of the flip-flop would indicate either a low to high or high to low transition. 
   Referring to  FIG. 5 , a receiver circuit is shown for the continuous mode of transmitting a periodic signal across an isolation barrier. In this circuit, a receiver coi  167  is connected to the source of transistor Q 3 . A current mirror including a current source  68  and transistors Q 4  (which acts as a resistor) causes a small current (e.g., 100 uA) referred to as the “idle current” from current source  70  to be provided to the drains of each oftransistors Q 3  and Q 5 . Transistors Q 3  and Q 5 , when turned on by a high gate voltage, produces a current much larger than the idle current, e.g., 1 mA, referred to as the peak current. The specific values for the idle current and peak current are not significant, but there should be a fairly large difference in them, such as one order of magnitude. When the signal on coil  67  is at zero in a quiescent state (e.g., the logic level is continuously low, transistors Q 3  an Q 5  each conduct half of the idle current. Because there is little current, at this point, there is little voltage drop across resistor R 2 , so the voltage at VI is high. 
   Referring also to  FIG. 5A , when the logic signal goes high, there is a periodic signal on coil  67 . As the signal on coil  67  goes high, transistor Q 3  only conducts the idle current, but transistor Q 5  conducts the peak current as shown in current  12  in FIG.  5 A). As the voltage on coil  67  goes down, the current on transistor Q 5  declines and the current on transistor Q 3  increases to the peak current as shown in current  11 . The sum of  11  and  12  produce a full wave rectified current. When this current is high, there is a significant drop across resistor R 2 , so the voltage at V 1  is low. 
   A substantially identical circuit with an inverted input is provided for a second coil to produce a corresponding output signal V 2 , where V 2  is high when the logic signal is high, and V 2  is low when the logic signal is low (inverse of V 1 ). 
   Referring to  FIG. 6 , the receiving circuitry of  FIG. 5  is shown with a pair of receivers of the type shown in  FIG. 5  with error detection circuitry. Receivers  80  and  82  are each connected to a coil (not shown). As indicated above, when the logic signal received is low, V 1  is high and V 2  is low. Transistor Q 6  is thus off, transistor Q 9  is on, causing current to conduct through transistor Q 8  (which serves as a resistor), causing transistor Q 7  to conduct, and thus causing the signal OUT to go low. Similarly, when the received logic signal is high, V 1  is low and V 2  is high, causing Q 6  to be turned on, Q 7  to be turned off, and OUT to be high. The circuit can also include a Schmitt trigger after OUT. 
   Voltages V 1  and V 2  should always have one high and one low. Error detection circuitry  84  is provided to monitor these voltages. If both voltages go low, an error signal is produced to indicate that the output is not reliable. 
   The system has thus far been shown in the embodiments with sets of coils as the isolation barrier, but other isolation approaches can be used. As shown, for example, in  FIG. 7 , a periodic signal can be provided when the isolation barrier is capacitively coupled as represented by barrier  90 . The circuit of  FIG. 7  is similar to the circuit of  FIG. 4 , except that a large resistor R 3  is coupled from the control terminal of the transistor to ground. As with the previous embodiment, the source follower transistor and RC circuit of capacitor C 5  and resistor R 4  rectifies the periodic signal provided by the capacitor plates. 
   Referring to  FIG. 8 , in another embodiment, a logic isolation system uses frequency modulation and demodulation. An input signal LOGIC IN is provided to an oscillator  90 , such as a Colpits oscillator. Referring also to  FIG. 8A , when the logic signal is low, the oscillator produces a signal with a frequency f 1 , and when the logic signal is high, the oscillator produces a signal with a frequency f 2  (shown greater than f 1 , but it need not be). The signal is transmitted across isolation barrier  92  to a frequency discriminator  94 , such as a Foster-Seeley detector of the type used in the radio receiving field. Discriminator  94  provides a high or low output depending on whether the signal is at f 1  or f 2 . The resulting output is provided to a Schmitt trigger  96 . 
     FIG. 9  shows a logic isolator  100  that uses phase modulation. The isolator has a first coil and driver  102  and a second coil and driver  104 . The input to the second coil and driver is provided by an oscillating signal from an oscillator  106 . The oscillating signal and the logic input signal LOGIC IN are provided to an XOR gate  108  and then to the driver for the first coil. 
   Referring also to  FIG. 9A , when LOGIC IN is low, the oscillating signal, the signal on the first coil, and the signal on the second coil are all in phase. In response to a transition  110  from low to high, the signal on the first coil goes from low to high and thereafter the signals on the first and second coils are out of phase with each other. 
   Referring again to  FIG. 9 , on the receiving side, first and second receiving coils are provided to a multiplier  112  and then to an inverter  114  to an output  116 . Multiplier  112  yields a positive value when the signal on the coils are in phase, and an inverse signal when the signals on the coils are in antiphase. As a result, the signal at output  116  indicates the value of LOGIC IN. Because the signals are continuously transmitted, the state is constantly refreshed. 
   Having described certain preferred embodiments, it should be apparent that modifications can be made without departing from the scope of the invention as defined by the appended claims. While only one channel is shown, the device could have multiple channels together in one device for control and/or status signals as shown in the incorporated patent. The circuitry can be formed from discrete components, or it can be integrated onto one or more semiconductor substrates, along with the isolation barrier itself.