Patent Publication Number: US-11664454-B2

Title: Method for forming semiconductor device structure

Description:
PRIORITY CLAIM AND CROSS-REFERENCE 
     This application is a divisional application of U.S. patent application Ser. No. 16/395,731, filed on Apr. 26, 2019, entitled of “SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME,” which is incorporated herein by reference in its entirety. 
    
    
     BACKGROUND 
     The electronics industry is experiencing an ever-increasing demand for smaller and faster electronic devices which are simultaneously able to support a greater number of increasingly complex and sophisticated functions. Accordingly, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). So far, these goals have been achieved in large part by scaling down semiconductor IC dimensions (e.g., minimum feature size) and thereby improving production efficiency and lowering associated costs. However, such miniaturization has introduced greater complexity into the semiconductor manufacturing process. Thus, the realization of continued advances in semiconductor ICs and devices calls for similar advances in semiconductor manufacturing processes and technology. 
     Recently, multi-gate devices have been introduced in an effort to improve gate control by increasing gate-channel coupling, reduce OFF-state current, and reduce short-channel effects (SCEs). One such multi-gate device that has been introduced is the gate-all around transistor (GAA). The GAA device gets its name from the gate structure which can extend around the channel region providing access to the channel on two or four sides. GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes and their structure allows them to be aggressively scaled-down while maintaining gate control and mitigating SCEs. In conventional processes. GAA devices provide a channel in a silicon nanowire. However, integration of fabrication of the GAA features around the nanowire can be challenging. For example, while the current methods have been satisfactory in many respects, continued improvements are still needed. 
    
    
     
       BRIEF DESCRIPTION OF THE DRAWINGS 
       Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying Figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. 
         FIGS.  1 A- 1 M  are perspective views illustrating the formation of a semiconductor device at various intermediate stages, in accordance with some embodiments of the disclosure. 
         FIGS.  1 A- 1  through  1 M- 1    are cross-sectional views of semiconductor structures along line I-I in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure. 
         FIGS.  1 E- 2  through  1 M- 2    are cross-sectional views of semiconductor structures along line II-II in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure. 
         FIGS.  1 F- 3  through  1 M- 3    are cross-sectional views of semiconductor structure along line III-III in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure. 
         FIGS.  2 A- 2 E  are perspective views illustrating the formation of a semiconductor device at various intermediate stages, in accordance with some embodiments of the disclosure. 
         FIGS.  2 A- 1  through  2 E- 1    are cross-sectional views of semiconductor structures along line I-I in  FIGS.  2 A- 2 E , in accordance with some embodiments of the disclosure. 
         FIGS.  2 B- 2  through  2 E- 2    are cross-sectional views of semiconductor structures along line II-II in  FIGS.  2 A- 2 E , in accordance with some embodiments of the disclosure. 
         FIGS.  2 B- 3  through  2 E- 3    are cross-sectional views of semiconductor structures along line III-III in  FIGS.  2 A- 2 E  in accordance with some embodiments of the disclosure. 
     
    
    
     DETAILED DESCRIPTION 
     The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. 
     Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numerals are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method. 
     The gate all around (GAA) transistor structures described below may be patterned by any suitable method. For example, the structures may be patterned using one or more photolithography processes, including double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes, allowing patterns to be created that have, for example, smaller pitches than what is otherwise obtainable using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed alongside the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers may then be used to pattern the GAA structure. 
     Embodiments of a semiconductor device structure are provided. The semiconductor device structure may include a semiconductor fin structure, an isolation structure, source/drain spacers, and a source/drain feature. The isolation structure includes a vertical portion surrounding the semiconductor fin structure. The source/drain spacers are formed directly above the vertical portion of the isolation structure. The source/drain feature is interposed between the source/drain spacers. Because the source/drain spacers confine the lateral growth of the source/drain feature, the source/drain feature can be formed to have a narrower width. As a result, the parasitic capacitance of the semiconductor device can be reduced, thereby enhancing the operation speed of the semiconductor device. 
       FIGS.  1 A- 1 M  are perspective views illustrating the formation of a semiconductor device  100  at various intermediate stages, in accordance with some embodiments of the disclosure.  FIGS.  1 A- 1  through  1 M- 1    are cross-sectional views of semiconductor structures along line I-I in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure.  FIGS.  1 E- 2  through  1 M- 2    are cross-sectional views of semiconductor structures along line II-II in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure.  FIGS.  1 F- 3  through  1 M- 3    are cross-sectional views of semiconductor structures along line III-III in  FIGS.  1 A- 1 M , in accordance with some embodiments of the disclosure. 
     A substrate  102  is provided, as shown in  FIGS.  1 A and  1 A- 1   , in accordance with some embodiments. Semiconductor fin structures  104  are formed over the substrate  102 , in accordance with some embodiments. 
     In some embodiments, the substrate  102  is a semiconductor substrate such as a silicon substrate. In some embodiments, the substrate  102  includes an elementary semiconductor such as germanium; a compound semiconductor such as gallium nitride (GaN), silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and/or indium antimonide (InSb); an alloy semiconductor such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or a combination thereof. 
     In some embodiments, the substrate  102  includes an epitaxial layer (epi-layer) formed thereon. In some embodiments, the substrate  102  is a semiconductor-on-insulator (SOI) substrate which includes a semiconductor substrate, a buried oxide layer over the substrate, and a semiconductor layer over the buried oxide layer. 
     The semiconductor fin structures  104  are arranged in the X direction and extend in the Y direction, in accordance with some embodiments. The semiconductor fin structures  104  each include a lower portion  104 L and an upper portion  104 U, in accordance with some embodiments. The lower portion  104 L of the semiconductor fin structure  104  is formed by a portion of the substrate  102 , in accordance with some embodiments. The upper portion  104 U of the semiconductor fin structure  104  is formed by a stacked semiconductor structure, which includes first semiconductor layers  106  and second semiconductor layers  108  alternately stacked over the lower portion  104 L, in accordance with some embodiments. 
     As explained in detail below, the first semiconductor layers  106  of the semiconductor fin structures  104  will be removed so that the second semiconductor layers  108  of the semiconductor fin structures  104  form nanowire structures which extend between source/drain features, in accordance with some embodiments. The nanowire structure of the second semiconductor layers  108  will be surrounded by a gate stacks to serve as a channel region of the semiconductor device, in accordance with some embodiments. For example, the embodiments described in  FIGS.  1 A through  1 M- 3    illustrate processes and materials that may be used to form nanowire structures with a GAA design for n-type FinFETs and/or p-type FinFETs. 
     In some embodiments, the formation of the semiconductor fin structures  104  includes forming a stacked semiconductor structure including a first semiconductor material for the first semiconductor layers  106  and a second semiconductor material for the second semiconductor layers  108  over the substrate  102 . 
     The first semiconductor material for the first semiconductor layers  106  is a material having a different lattice constant than that of the second semiconductor material for the second semiconductor layers  108 , in accordance with some embodiments. In some embodiments, the first semiconductor layers  106  are made of SiGe, where the percentage of germanium (Ge) in the SiGe is in the range from about 20 atomic % to about 50 atomic %, and the second semiconductor layers  108  are made of silicon. In some embodiments, the first semiconductor layers  106  are Si 1-x Ge x , where x is more than about 0.3, or Ge (x=1.0) and the second semiconductor layers  108  are Si or Si 1-y Ge y , where y is less than about 0.4, and x&gt;y. 
     In some embodiments, the first semiconductor material and the second semiconductor material are formed using low-pressure chemical vapor deposition (LPCVD), epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE). 
     In some embodiments, the thickness of each of the first semiconductor layers  106  is in a range from about 1.5 nanometers (nm) to about 20 nm. In some embodiments, the first semiconductor layers  106  are substantially uniform in thickness. In some embodiments, the thickness of each of the second semiconductor layers  108  is in a range from about 1.5 nm to about 20 nm. In some embodiments, the second semiconductor layers  108  are substantially uniform in thickness. 
     Afterward, the stacked semiconductor structure including the first semiconductor material and the second semiconductor material and the underlying substrate  102  are patterned into the fin structures  104 . 
     In some embodiments, the patterning process includes forming bi-layered hard mask layers (including hard mask layers  110  and  112 ) over the stacked semiconductor structure, and etching the stacked semiconductor structure and the underlying substrate  102  through the bi-layered hard mask layers. In some embodiments, the first hard mask layer  110  is a pad oxide layer made of a silicon oxide, which is formed by thermal oxidation or CVD. In some embodiments, the second hard mask layer  112  is made of silicon nitride, which is formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD). 
     In some embodiments, the etching process of the patterning process removes portions of the stacked semiconductor structure uncovered by the bi-layered hard mask layers and further recesses the substrate  102  so as to form trenches  105 . 
     In some embodiments, after the etching process, the substrate  102  has portions which protrude from between the trenches  105  to form the lower portions  104 L of the semiconductor fin structures  104 . In some embodiments, remaining portions of the stacked semiconductor structure directly above the lower portions  104 L form the upper portions  104 U of the semiconductor fin structures  104 . 
     An insulating material  114  is conformally formed along the semiconductor fin structures  104  and the substrate  102 , as shown in  FIGS.  1 B and  1 B- 1   , in accordance with some embodiments. The insulating material  114  is further formed along the bi-layered hard mask layers, in accordance with some embodiments. The insulating material  114  covers the upper surface of the substrate  102 , the sidewalls of the semiconductor fin structures  104 , and upper surfaces and sidewalls of the bi-layered hard mask layers, in accordance with some embodiments. The trenches  105  are partially filled by the insulating material  114 , in accordance with some embodiments. 
     In some embodiments, the insulating material  114  includes silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, the insulating material is formed using LPCVD, PECVD, high density plasma CVD (HDP-CVD), high aspect ratio process (HARP), flowable CVD (FCVD), ALD, another suitable method, or a combination thereof. 
     Dielectric fin structures  116  are formed to fill remaining portions of the trenches  105 , as shown in  FIGS.  1 C and  1 C- 1   , in accordance with some embodiments. The dielectric fin structures  116  are formed adjacent to the semiconductor fin structures  104  and over the insulating material  114 , in accordance with some embodiments. The dielectric fin structures  116  are spaced apart from the semiconductor fin structures  104  by the insulating material  114 , in accordance with some embodiments. The dielectric fin structures  116  are arranged in the X direction and extend in the Y direction, in accordance with some embodiments. In some embodiments, the dielectric fin structures  116  have the upper surfaces at a level below the upper surfaces of the semiconductor fin structures  104 . 
     In some embodiments, the dielectric fin structures  116  are made of a dielectric material with a dielectric constant less than about 7. In some embodiments, the dielectric material for the dielectric fin structures  116  is SiN SiCN, SiOC, SiOCN, or a combination thereof. In some embodiments, the formation of the dielectric fin structures  116  includes depositing a dielectric material over the insulating material  114  and filling the trenches  105  followed by an etch-back process. In some embodiments, the deposition process is LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof. In some embodiments, the etch-back process is an isotropic etching process such a dry chemical etching or wet etching, or an anisotropic etching process such as dry plasma etching. 
     Protection layers  118  are formed to fill remaining portions of the trenches  105 , as shown in  FIGS.  1 C and  1 C- 1   , in accordance with some embodiments. The protection layers  118  are formed directly above the dielectric fin structures  116  in the trenches  105 , in accordance with some embodiments. The remaining portions of the trenches  105  are substantially entirely filled by the protection layers  118 , in accordance with some embodiments. 
     In some embodiments, the protection layers  118  are made of a dielectric material with a dielectric constant greater than about 7. In some embodiments, the dielectric material for the protection layers  118  is Al 2 O 3 , HfO 2 , ZrO 2 , HfAlO, HfSiO, or a combination thereof. In some embodiments, the formation of the protection layers  118  includes depositing a dielectric material over the dielectric fin structures  116  and filling the trenches  105  followed by an etch-back process. In some embodiments, the deposition process is LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof. In some embodiments, the etch-back process is an isotropic etching process such a dry chemical etching or wet etching, or an anisotropic etching process such as dry plasma etching. 
     The insulating material  114  formed above the semiconductor fin structures  104  is removed to expose the upper surfaces of the semiconductor fin structures  104 , as shown in  FIGS.  1 C and  1 C- 1   , in accordance with some embodiments. The bi-layered hard mask layers (including layers  110  and  112 ) are also removed, in accordance with some embodiments. In some embodiments, the removal process is chemical mechanical polishing (CMP) process or an etch-back process. In some embodiments, after the planarization, the upper surfaces of the semiconductor fin structures  104 , the insulating material  114 , and the protection layers  118  are substantially coplanar, in accordance with some embodiments. 
     The insulating material  114  is recessed to form gaps  122 , as shown in  FIGS.  1 D and  1 D- 1   , in accordance with some embodiments. Each of the gaps  122  is formed between one semiconductor fin structure  104  and one dielectric fin structure  116 , in accordance with some embodiments. The gaps  122  expose the sidewalls of the upper portions  104 U of the semiconductor fin structures  104 , the sidewalls of the dielectric fin structures  116  and the sidewalls of the protection layers  118 , in accordance with some embodiments. In some embodiments, the recessing process includes a dry etching, wet etching, or a combination thereof. 
     After the recessing process, remaining portions of the insulating material  114  form an isolation structure  120 , in accordance with some embodiments. The isolation structure  120  includes vertical portions  120 V and horizontal portions  120 H, in accordance with some embodiments. 
     The vertical portions  120 V of the isolation structure  120  surround the lower portions  104 L of the semiconductor fin structures  104 , in accordance with some embodiments. The vertical portions  120 V of the isolation structure  120  also surround the lower portions of the dielectric fin structures  116 , in accordance with some embodiments. Each of the vertical portions  120 V of the isolation structure  120  is interposed between one semiconductor fin structures  104  and one dielectric fin structures  116 , in accordance with some embodiments. 
     The horizontal portions  120 H of the isolation structure  120  extend along the upper surface of the substrate  102  between two neighboring semiconductor fin structures  104 , in accordance with some embodiments. The dielectric fin structures  116  are formed over the horizontal portions  120 H of the isolation structure  120 , in accordance with some embodiments. 
     Dummy gate structures  124  are formed across the semiconductor fin structures  104  and the dielectric fin structures  116 , as shown in  FIGS.  1 E,  1 E- 1  and  1 E- 2   , in accordance with some embodiments. The dummy gate structures  124  are arranged in the Y direction and extend in the X direction, in accordance with some embodiments. The dummy gate structures  124  are filled into the gaps  122 , in accordance with some embodiments. The dummy gate structures  124  cover the upper surfaces and the sidewalls of the semiconductor fin structures  104 , the sidewalls of the dielectric fin structures  116 , and the upper surfaces and the sidewalls of the protection layers  118 , in accordance with some embodiments. 
     In some embodiments, the dummy gate structures  124  define the source/drain regions and the channel region of a semiconductor device. 
     The dummy gate structures  124  include dummy gate dielectric layers  126  and dummy gate electrode layers  128 , in accordance with some embodiments. In some embodiments, the dummy gate dielectric layers  126  are made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO 2 , HfZrO, HfSiO, HfTiO, HfAlO, or a combination thereof. In some embodiments, the dielectric material is formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof. 
     In some embodiments, the dummy gate electrode layers  128  are made of a conductive material. In some embodiments, the conductive material includes polycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metals, or a combination thereof. In some embodiments, the conductive material is formed using CVD, PVD, or a combination thereof. 
     In some embodiments, the formation of the dummy gate structures  124  includes conformally forming a dielectric material for the dummy gate dielectric layers  126  along the substrate  102 , the semiconductor fin structures  104 , the dielectric fin structures  116 , and the protection layers  118 ; forming a conductive material for the dummy gate electrode layers  128  over the dielectric material; and forming bi-layered hard mask layers  130  over the conductive material. 
     In some embodiments, the formation of the bi-layered hard mask layers  130  includes forming an oxide layer (e.g., silicon oxide) over the conductive material, forming a nitride layer (e.g., silicon nitride) over the oxide layer, and patterning the oxide layer into layers  132  and the nitride layer into layers  134  using photolithography and etching processes. 
     In some embodiments, the formation of the dummy gate structures  124  also includes etching the dielectric material and the conductive material through the bi-layered hard mask layers  130  to remove the dielectric material and the conductive material uncovered by the bi-layered hard mask layers  130 . After the etching process, the source/drain regions of the semiconductor fin structures  104  are exposed. In some embodiments, the etching process includes one or more dry etching processes, wet etching processes, or a combination thereof. 
     A dielectric material  136  is globally formed over the semiconductor structure of  FIG.  1 E , as shown in  FIGS.  1 F,  1 F- 1 ,  1 F- 2  and  1 F- 3   , in accordance with some embodiments. The dielectric material  136  is conformally formed along the upper surfaces and the sidewalls of the bi-layered hard mask layers  130 , the sidewalls of the dummy gate structures  124 , the upper surfaces of the semiconductor fin structures  104 , and the upper surfaces of the protection layers  118 , in accordance with some embodiments. The dielectric material  136  is filled into the gaps  122  to cover the sidewalls of the semiconductor fin structures  104 , the sidewalls of the protection layers  118 , the sidewalls of the dielectric fin structures  116 , and the upper surfaces of the vertical portions  120 V of the isolation structure  120 , in accordance with some embodiments. In some embodiments, the gaps  122  are substantially entirely filled by the dielectric material  136 . 
     In some embodiments, the dielectric material  136  has a dielectric constant greater than about 7. For example, the dielectric material  136  is Al 2 O 3 , HfO 2 , ZrO 2 , HfAlO, HfSiO, or a combination thereof. In some embodiments, the dielectric material  136  is formed using LPCVD, PECVD, HDP-CVD, HARP, FCVD, ALD, another suitable method, or a combination thereof. 
     The dielectric material  136  is etched to form source/drain spacers  138 , as shown in  FIGS.  1 G,  1 G- 1 ,  1 G- 2  and  1 G- 3   , in accordance with some embodiments. In some embodiments, the etching process is an isotropic etching process such a dry chemical etching or wet etching, or an anisotropic etching process such as dry plasma etching. The etching process removes portions of the dielectric material  136  formed above the semiconductor fin structures  104  and the protection layers  118 , in accordance with some embodiments. After the etching process, upper portions of the sidewalls of the dummy gate structures  124 , the upper surfaces of the semiconductor fin structures  104 , and the upper surfaces of the protection layers  118  are exposed, in accordance with some embodiments. 
     Remaining portions of the dielectric material  136  leaves in the gaps  122  to form the source/drain spacers  138 , in accordance with some embodiments. The source/drain spacers  138  are formed directly above the vertical portions  120 V of the isolation structure  120  and between the semiconductor fin structures  104  and the dielectric fin structures  116 , in accordance with some embodiments. The source/drain spacers  138  are formed along lower portions of the sidewalls of the dummy gate structures  124 , in accordance with some embodiments. The source/drain spacers  138  are used to confine the lateral growth of the subsequently formed source/drain features, thereby forming the source/drain features with a desirable profile. 
     Gate spacers  140  are formed along sidewalls of the dummy gate structures  124 , as shown in  FIGS.  1 H,  1 H- 1 ,  1 H- 2  and  1 H- 3   , in accordance with some embodiments. The gate spacers  140  are further formed along the sidewalls of the bi-layered hard mask layers  130 , in accordance with some embodiments. The gate spacers  140  partially cover the semiconductor fin structures  104 , the source/drain spacers  138  and the protection layers  118 , in accordance with some embodiments. 
     In some embodiments, the gate spacers  140  are made of a dielectric material, such as silicon oxide (SiO 2 ), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof. In some embodiments, the gate spacers  140  are formed using a deposition process followed by an etching process. In some embodiments, the deposition process includes CVD (such as PECVD, LPCVD or HARP) and/or ALD. In some embodiments, the etching process is an anisotropic etching process such as a dry plasma etching process. 
     The semiconductor fin structures  104  are recessed to form source/drain recesses  142 , as shown in  FIGS.  1 I,  1 I- 1 ,  1 I- 2  and  1 I- 3   , in accordance with some embodiments. The etching process recesses the semiconductor fin structures  104  uncovered by the gate spacers  140 , the dummy gate structures  124 , and the bi-layered hard mask layers  130 , in accordance with some embodiments. The source/drain recesses  142  are formed between the source/drain spacers  138  and expose the upper surface of the lower portions  104 L of the semiconductor fin structures  104 , in accordance with some embodiments. In some embodiments, the recessing process includes a dry etching process, a wet etching process, or a combination thereof. 
     During the etching process of recessing the semiconductor fin structures  104 , the etchant also etches dielectric materials of the semiconductor structures, in accordance with some embodiments. During the etching process, the etching rate of the dielectric material with a higher dielectric constant (such as the source/drain spacers  138  and the protection layers  118 ) is lower than the etching rate of the dielectric material with a lower dielectric constant (such as the dielectric fin structures  116 ), in accordance with some embodiments. As a result, the source/drain spacers  138  and the protection layers  118  can protect the dielectric fin structures  116  during the etching process. 
     The etching process partially removes upper portions of the source/drain spacers  138 , uncovered by the gate spacers  140 , in accordance with some embodiments. After the etching process, the recessed source/drain spacers  138  has protruding portions  138 P at their upper surfaces covered by the gate spacers  140 , in accordance with some embodiments. 
     The etching process also removes the protection layers  118 , uncovered by the gate spacers  140 , the dummy gate structures  124 , and the bi-layered hard mask layers  130 , in accordance with some embodiments. After the etching process, the upper surfaces of the dielectric fin structures  116  are exposed, in accordance with some embodiments. 
     Source/drain features  144  are formed in the source/drain recesses  142 , as shown in  FIGS.  1 J,  1 J- 1 ,  1 J- 2  and  1 J- 3   , in accordance with some embodiments. The source/drain features  144  are formed directly above the lower portions  104 L of the semiconductor fin structures  104 , in accordance with some embodiments. The source/drain features  144  are formed between and protruding from between the source/drain spacers  138 , in accordance with some embodiments. 
     In some embodiments, the source/drain features  144  are made of any suitable material for an n-type semiconductor device and a p-type semiconductor device, such as Ge, Si, GaAs, AlGaAs, SiGe. GaAsP, SiP, SiC, SiCP, or a combination thereof. In some embodiments, the source/drain features  144  are formed using epitaxial growth process, such as MBE, MOCVD, VPE, another suitable epitaxial growth process, or a combination thereof. 
     In some embodiments, the source/drain features  144  are in-situ doped during the epitaxial growth process. For example, the source/drain features  144  may be the epitaxially grown SiGe doped with boron (B). For example, the source/drain features  134  may be the epitaxially grown Si doped with carbon to form silicon:carbon (Si:C) source/drain features, phosphorous to form silicon:phosphor (Si:P) source/drain features, or both carbon and phosphorous to form silicon carbon phosphor (SiCP) source/drain features. In some embodiments, the source/drain features  144  are doped in one or more implantation processes after the epitaxial growth process. 
     Because the source/drain feature  144  is grown from between the source/drain spacers  138 , the lateral growth of the source/drain feature  144  is confined by the source/drain spacers  138 , in accordance with some embodiments. As a result, the source/drain feature  144  has a body portion  144 B between the source/drain spacers  138 . The body portion  144 B confined by the source/drain spacers  138  has a column profile, in accordance with some embodiments. 
     The source/drain feature  144  continues to grow beyond above the source/drain spacers  138 , in accordance with some embodiments. As a result, the source/drain feature  144  has a head portion  144 H protruding from the source/drain spacers  138 , in accordance with some embodiments. Without being confined by the source/drain spacers  138 , the head portion  144 H is laterally grown and have a faceted profile, in accordance with some embodiments. 
     In some embodiments, the body portion  144 B has a width W 1  at the bottom surface of the body portion  144 B measured in the X direction. In some embodiments, the width W 1  ranges from about 8 nm to about 70 nm. In some embodiments, the body portion  144 B has a width W 2  at the middle height of the body portion  144 B measured in the X direction. In some embodiments, the width W 2  ranges from about 8 nm to about 70 nm. In some embodiments, the body portion  144 B has a width W 3  at the top of the body portion  144 B (or at the position of the upper surface of the source/drain spacer  138 ) measured in the X direction. In some embodiments, the width W 3  ranges from about 8 nm to about 70 nm. In some embodiments, the width W 1  is equal to or less than the width W 2 . In some embodiments, the width W 2  is equal to or less than the width W 3 . That is, the body portion  144 B may have a substantially consistent width or an upwardly tapering width. 
     In some embodiments, the body portion  144 B has a height H 1  measured in the Z direction. In some embodiments, the height H 1  ranges from about 40 nm to about 80 nm. In some embodiments, the ratio of the height H 1  to the width W 1  ranges from about 0.5 to about 10. 
     In some embodiments, the head portion  144 H has a maximum width W 4  measured in the X direction. In some embodiments, the width W 4  ranges from about 14 nm to about 90 nm. In some embodiments, the ratio of the width W 4  to the width W 1  ranges from about 1.2 to about 1.8. 
     In some embodiments, the head portion  144 H has a height H 2  measured in the Z direction. In some embodiments, the height H 2  ranges from about 14 nm to about 90 nm. In some embodiments, the ratio of the height H 1  to the height H 2  ranges from about 0.8 to about 3. 
     Because the source/drain spacers  138  confine the lateral growth of the source/drain features  144 , the source/drain features  144  can have a more slender column profile (i.e. a higher ratio of height H 1  to width W 1 ) than if the source/drain spacers are not formed. 
     A contact etching stop layer (CESL)  146  is formed over the semiconductor structure of  FIG.  1 J , as shown in  FIGS.  1 K,  1 K -A,  1 K- 2  and  1 K- 3 , in accordance with some embodiments. An interlayer dielectric (ILD) layer  148  is formed over the CESL  146 , in accordance with some embodiments. 
     The CESL  146  is conformally formed along the faceted surfaces of the head portions  144 H of the source/drain features  144 , the upper surfaces of the source/drain spacers  138 , the upper surfaces of the dielectric fin structures  116 , the sidewalls of the protruding portions of the source/drain spacers  138 , the sidewalls of the protection layers  118 , and the sidewalls of the gate spacers  140 , in accordance with some embodiments. 
     In some embodiments, the CESL  146  is made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. In some embodiments, the dielectric material for the CESL  146  is globally deposited over the semiconductor structure of  FIG.  1 J . The deposition process includes CVD (such as PECVD, HARP, or a combination thereof), ALD, another suitable method, or a combination thereof. 
     In some embodiments, the ILD layer  148  is made of a dielectric material, such as tetraethylorthosilicate (TEOS) oxide, un-doped silicate glass (USG), or doped silicon oxide such as borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), and/or another suitable dielectric material. In some embodiments, the dielectric material for the ILD layer  148  is formed using CVD (such as HDP-CVD, PECVD, or HARP), ALD, another suitable method, or a combination thereof. 
     Afterward, a planarization process such as CMP or an etch-back process is performed on the dielectric materials for the CESL  146  and ILD layer  148 , in accordance with some embodiments. The dielectric materials formed above the dummy gate structures  124  are removed to expose the upper surfaces of the dummy gate electrode layers  128 , in accordance with some embodiments. The planarization process also removes the bi-layered hard mask layers  130 , in accordance with some embodiments. 
     The dummy gate structures  124  are replaced with metal gate stacks  150 , as shown in  FIGS.  1 L,  1 L- 1 ,  1 L- 2  and  1 L- 3   , in accordance with some embodiments. The replacement process includes removing the dummy gate structures  124 , removing the first semiconductor layers  106  of the semiconductor fin structure  104 , and forming the metal gate stacks  150  to surround the second semiconductor layers  106 , in accordance with some embodiments. 
     In some embodiments, the dummy gate structures  124  (including the dummy gate electrode layers  128  and the dummy gate dielectric layers  126 ) are removed to form trenches (not shown) between the gate spacers  140 . The removal process includes one or more etching processes. For example, when the dummy gate electrode layers  128  are polysilicon, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the dummy gate electrode layers  128 . For example, the dummy gate dielectric layers  126  may be thereafter removed using a plasma dry etching, a dry chemical etching, and/or a wet etching. 
     In some embodiments, the first semiconductor layers  106  of the semiconductor fin structure  104  are removed to form gaps (not shown) between the second semiconductor layers  108  and between the lowermost second semiconductor layer  108  and the lower portion  104 L. After removing the first semiconductor layers  106 , four main surfaces (an upper surface, two side surfaces, and a bottom surface) of each of the second semiconductor layers  108  are exposed, in accordance with some embodiments. The exposed second semiconductor layers  108  form nanowire structures, which function as a channel region of the resulting semiconductor device and are surrounded by the metal gate stacks  150 , in accordance with some embodiments. 
     In some embodiments, the etching process includes a selective wet etching process, such as APM (e.g., ammonia hydroxide-hydrogen peroxide-water mixture) etching process. In some embodiments, the wet etching process uses etchants such as ammonium hydroxide (NH 4 OH), TMAH, ethylenediamine pyrocatechol (EDP), and/or potassium hydroxide (KOH) solutions. 
     An interfacial layer  152 , a gate dielectric layer  154 , and a gate electrode layer  156  are sequentially formed in the trenches and gaps where the dummy gate structures  124  and the first semiconductor layers  106  are removed, in accordance with some embodiments. The interfacial layer  152 , the gate dielectric layer  154  and the gate electrode layer  156  together functions as the metal gate stacks  150 , in accordance with some embodiments. 
     The metal gate stacks  150  surround the nanowire structures of the second semiconductor layers  108 , in accordance with some embodiments. The metal gate stacks  150  are arranged in the Y direction and extend in the X direction, in accordance with some embodiments. The metal gate stacks  150  extend across the semiconductor fin structures  104  and the dielectric fin structure  116 , in accordance with some embodiments. 
     The interfacial layer  152  is conformally formed along the main surfaces of the second semiconductor layers  108  to surround the second semiconductor layers  108 , in accordance with some embodiments. In some embodiments, the interfacial layer  152  is made of a chemically formed silicon oxide. 
     The gate dielectric layer  154  is conformally formed on the interfacial layer  152  to surround the second semiconductor layers  108 , in accordance with some embodiments. The gate dielectric layer  154  is further formed along the upper surfaces and the sidewalls of the protection layers  118 , the sidewalls of the dielectric fin structures  116 , the upper surfaces of the isolation structure  120 , and the upper surfaces of the lower portion  104 L of the semiconductor fin structures  104 , in accordance with some embodiments. In some embodiments, the gate dielectric layer  154  is further formed along the upper surface of the ILD layer  148 . 
     In some embodiments, the gate dielectric layer  154  is made of one or more layers of a dielectric material, such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO 2 —Al2O 3 ) alloy, another suitable high-k dielectric material, or a combination thereof. In some embodiments, the gate dielectric layer  154  is formed using CVD, ALD, another suitable method, or a combination thereof. 
     The gate electrode layer  156  is formed on the gate dielectric layer  154 , in accordance with some embodiments. Remaining portions of the trenches and gaps, where the dummy gate structures  124  and the first semiconductor layers  106  are removed, are substantially entirely filled by the gate electrode layer  156 , in accordance with some embodiments. 
     In some embodiments, the gate electrode layer  156  is made of one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layer  156  is formed using CVD, ALD, electroplating, another suitable method, or a combination thereof. 
     Afterward, a planarization process such as CMP or an etch-back process is performed on the metal gate stacks  150  to remove the metal gate stacks  150  formed above the ILD layer  148 , in accordance with some embodiments. After the planarization process, the upper surface of the ILD layer  148  is exposed, in accordance with some embodiments. 
     An isolation structure  162  is formed through the ILD  148  and the metal gate stacks  150 , as shown in  FIGS.  1 M,  1 M- 1 ,  1 M- 2  and  1 M- 3   , in accordance with some embodiments. The isolation structure  162  extends in the Y direction, in accordance with some embodiments. The isolation structure  162  is formed directly above the dielectric fin structure  116  and the protection layers  118 , in accordance with some embodiments. 
     In some embodiments, the isolation structure  162  is made of an insulating material. In some embodiments, the insulating material for the isolation structure  162  includes SiO 2 , SiON, SiN, SiC, SiOC, SiOCN, or a combination thereof. 
     In some embodiments, the formation of the isolation structure  162  includes performing a cutting process to form a trench through the ILD layer  148  and the metal gate stacks  150 . The cutting process cuts the metal gate stacks  150  into sub-metal gate stacks  151 . In some embodiments, the trench exposes the upper surfaces and sidewalls of the protection layers  118  and the upper surface of the dielectric fin structures  116 . In some embodiments, the cutting process includes photolithography and etching process. 
     In some embodiments, an insulating material for the isolation structure  162  is deposited to fill the trench. In some embodiments, the insulating material is further deposited over the ILD layer  148  and the metal gate stacks  150 . 
     In some embodiments, afterward, the insulating material over the ILD layer  148  and the metal gate stacks  150  are removed. In some embodiments, the removal process is CMP or etch-back process. 
     Contact openings (not shown) are formed through the ILD layer  148  and CESL  146 , in accordance with some embodiments. In some embodiments, the contact openings are formed using a photolithography process and an etching process. The contact openings expose the upper surfaces of the source/drain features  144 , in accordance with some embodiments. In some embodiments, the etching process further recesses the head portion  144 H of the source/drain features  144 . 
     In some embodiments, after the etching process, the head portion  144 H has a width W 5  at the upper surface of the head portion  144 H measured in the X direction. In some embodiments, the width W 5  ranges from about 14 nm to about 90 nm. In some embodiments, the ratio of the width W 5  to the width W 1  ranges from about 1.2 to about 1.8. 
     In some embodiments, after the etching process, the head portion  144 H of source/drain feature  144  has a height H 3  measured in the Z direction. In some embodiments, the height H 3  ranges from about 7 nm to about 45 nm. In some embodiments, the ratio of the height H 1  to the height H 3  ranges from about 1.5 to about 6. 
     Silicides  158  are formed on the upper surfaces of the source/drain features  144 , as shown in  FIGS.  1 M,  1 M- 1 ,  1 M- 2  and  1 M- 3   , in accordance with some embodiments. 
     In some embodiments, the silicides  158  are made of WSi, NiSi, TiSi, CoSi, and/or another suitable silicide material. In some embodiments, the formation of the silicides  158  includes depositing a metal material over the ILD layer  148  and along the sidewalls and bottom surfaces of the contact openings, annealing the metal material so that the metal material reacts with the source/drain features  144 , and etching away the unreacted portion of the metal material. In some embodiments, the deposition process includes CVD, ALD, PVD, and/or another suitable method. In some embodiments, the anneal process includes a rapid temperature anneal (RTA) process. In some embodiments, the etching process includes a wet etching. 
     Contacts  160  are formed through the ILD layer  148  and land on the silicides  158 , as shown in  FIGS.  1 M,  1 M- 1 ,  1 M- 2  and  1 M- 3   , in accordance with some embodiments. 
     In some embodiments, the contacts  160  are made of a conductive material, such as Co, Ni, W, Ti, Ta, Cu, Al, TiN, TaN, and/or another suitable conductive material. The formation of the contacts  160  includes depositing a conductive material over the ILD layer  148  and filling the contact openings, and removing the conductive material over the ILD layer  148 . In some embodiments, the deposition process includes CVD, ALD, PVD, and/or another suitable method. In some embodiments, the removal process is CMP. 
     After the contacts  160  are formed, the semiconductor device  100  is obtained. 
     By forming the source/drain spacer  138  to confine the lateral growth of the source/drain feature  144 , the source/drain feature  144  can have a body portion  144 B with a slender column profile. The source/drain feature  144  having a narrower width can reduce the parasitic capacitance between the gate stack and the source/drain feature, thereby enhancing the operation speed of the semiconductor device. 
     In addition, the source/drain spacers  138  are formed of the dielectric material with a high dielectric constant (such as greater than 7) so that the consumption of the source/drain spacers  138  during the etching process of forming the source/drain recesses  142  may be reduced. If consumption of the source/drain spacers  138  is too high, the height H 1  of the body portion  144 B of the source/drain feature  144  may be decreased. Therefore, the source/drain feature  144  can be formed to have a larger proportion of the body portion  144 B and a smaller proportion of the head portion  144 H. That is, the ratio of the height H 1  to the height H 3  is increased. As a result, the parasitic capacitance between the gate stack and the source/drain feature can be reduced further, thereby further enhancing the operation speed of the semiconductor device. 
     Although the embodiments described above in  FIGS.  1 A through  1 M- 3    are used in the GAA device, the concept of the embodiments may be also used in the FinFET device and be described in  FIGS.  2 A through  2 E- 3   . 
       FIGS.  2 A- 2 E  are perspective views illustrating the formation of a semiconductor device  200  at various intermediate stages, in accordance with some embodiments of the disclosure.  FIGS.  2 A- 1  through  2 E- 1    are cross-sectional views of semiconductor structures along line I-I in  FIGS.  2 A- 2 E , in accordance with some embodiments of the disclosure.  FIGS.  2 B- 2  through  2 E- 2    are cross-sectional views of semiconductor structures along line II-II in  FIGS.  2 A- 2 E , in accordance with some embodiments of the disclosure.  FIGS.  2 B- 3  through  2 E- 3    are cross-sectional views of semiconductor structures along line III-III in  FIGS.  2 A- 2 E  in accordance with some embodiments of the disclosure. 
     A substrate  102  is provided, as shown in  FIGS.  2 A and  2 A- 1   , in accordance with some embodiments. Semiconductor fin structures  204  are formed over the substrate  102 , in accordance with some embodiments. The semiconductor fin structures  204  are arranged in the X direction and extend in the Y direction, in accordance with some embodiments. 
     In some embodiments, the semiconductor fin structures  204  are formed by a portion of the substrate  102 . For example, a patterning process may performed on the substrate  102  to form the fin structures  204 . 
     An isolation structure  120 , dielectric fin structures  116 , protection layers  118  are formed over the substrate  102 , as shown in  FIGS.  2 A and  2 A- 1   , in accordance with some embodiments. The methods of forming the isolation structure  120 , the dielectric fin structures  116 , and the protection layers  118  may be the same as or similar to those described above in  FIGS.  1 B through  1 D- 1   . 
     The isolation structure  120  includes vertical portions  120 V and horizontal portions  120 H, in accordance with some embodiments. The vertical portions  120 V of the isolation structure  120  surround the lower portions of the semiconductor fin structures  204  and the lower portions of the dielectric fin structures  116 , in accordance with some embodiments. The horizontal portions  120 H of the isolation structure  120  extend along the upper surface of the substrate  102  between two neighboring semiconductor fin structures  204 , in accordance with some embodiments. 
     The dielectric fin structures  116  are formed adjacent to the semiconductor fin structures  204  and over the horizontal portions  120 H of the insulating material  114 , in accordance with some embodiments. The dielectric fin structures  116  are arranged in the X direction and extend in the Y direction, in accordance with some embodiments. The protection layers  118  are formed directly above the dielectric fin structures  116 , in accordance with some embodiments. 
     Dummy gate structures  124  are formed across the semiconductor fin structures  204  and the dielectric fin structures  116 , as shown in  FIGS.  2 B,  2 B- 1 ,  2 B- 2  and  2 B- 3   , in accordance with some embodiments. The bi-layered hard mask layers  130  are formed over the dummy gate structures  124 , in accordance with some embodiments. The dummy gate structures  124  are arranged in the Y direction and extend in the X direction, in accordance with some embodiments. The dummy gate structures  124  are filled into the gaps  122 , in accordance with some embodiments. 
     Source/drain spacers  138  are formed in the gaps  122 , as shown in  FIGS.  2 B,  2 B- 1 ,  2 B- 2  and  2 B- 3   , in accordance with some embodiments. The source/drain spacers  138  are form directly above the vertical portions of the isolation structures  120  and between the semiconductor fin structures  204  and the dielectric fin structures  116 , in accordance with some embodiments. The source/drain spacers  138  are formed along lower portions of the sidewalls of the dummy gate structures  124 , in accordance with some embodiments. 
     Gate spacers  140  are formed along sidewalls of the dummy gate structures  124 , as shown in  FIGS.  2 C,  2 C- 1 ,  2 C- 2  and  2 C- 3   , in accordance with some embodiments. The gate spacers  140  partially cover the source/drain spacers  138  and the protection layers  118 , in accordance with some embodiments. 
     The semiconductor fin structures  204  are recessed to form source/drain recesses, in accordance with some embodiments. Source/drain features  144  are formed in the source/drain recesses, as shown in  FIGS.  2 C,  2 C- 1 ,  2 C- 2  and  2 C- 3   , in accordance with some embodiments. The source/drain features  144  are formed directly above the lower portions  204 L of the semiconductor fin structures  204 , in accordance with some embodiments. The source/drain features  144  are formed between and protruding from between the source/drain spacers  138 , in accordance with some embodiments. 
     The CESL  146  is conformally formed along the faceted surfaces of the head portions  144 H of the source/drain features  144 , the upper surfaces of the source/drain spacers  138 , the upper surfaces of the dielectric fin structures  116 , the sidewalls of the protruding portions of the source/drain spacers  138 , the sidewalls of the protection layers  118 , and the sidewalls of the gate spacers  140 , as shown in  FIGS.  2 D,  2 D- 1 ,  2 D- 2  and  2 D- 3   , in accordance with some embodiments. An ILD layer  148  is formed over the CESL  146 , in accordance with some embodiments. 
     The dummy gate structures  124  are replaced with metal gate stacks  150 , as shown in  FIGS.  2 D,  2 D- 1 ,  2 D- 2 , and  2 D- 3   , in accordance with some embodiments. The replacement process includes removing the dummy gate structures  124  by one or more etching process, and forming the metal gate stacks  150  to cover the upper portions  204 U of the semiconductor fin structures  204 , in accordance with some embodiments. 
     The metal gate stacks  150  include an interfacial layer  152 , a gate dielectric layer  154 , and a gate electrode layer  156 , in accordance with some embodiments. The interfacial layer  152  is conformally formed along the upper surfaces and the sidewalls of the semiconductor fin structures  204 , in accordance with some embodiments. 
     The gate dielectric layer  154  is conformally formed on the interfacial layer  152 , in accordance with some embodiments. The gate dielectric layer  154  is further formed along the upper surfaces and the sidewalls of the protection layers  118 , the sidewalls of the dielectric fin structures  116 , and the upper surfaces of the isolation structure  120 , in accordance with some embodiments. The gate electrode layer  156  is formed on the gate dielectric layer  154 , in accordance with some embodiments. 
     An isolation structure  162  is formed through the ILD and the metal gate stacks  150 , as shown in  FIGS.  2 E,  2 E- 1 ,  2 E- 2  and  2 E- 3   , in accordance with some embodiments. The isolation structure  162  extends in the Y direction, in accordance with some embodiments. The isolation structure  162  is formed directly above the dielectric fin structure  116  and the protection layers  118 , in accordance with some embodiments. 
     After forming the isolation structure  162 , the metal gate stacks  150  are cut into sub-metal gate stacks  151 , in accordance with some embodiments. 
     Silicides  158  are formed on the source/drain features  144 , as shown in  FIGS.  2 E,  2 E- 1 ,  2 E- 2  and  2 E- 3   , in accordance with some embodiments. Contacts  160  are formed through the ILD layer  148  and land on the silicides  158  to form a semiconductor device  200 , in accordance with some embodiments. The methods of forming the silicides  158  and the contacts  160  may be the same as or similar to those described above in  FIGS.  1 M  though  1 M- 3 . 
     As described above, the semiconductor device structure includes a substrate  102 , a semiconductor fin structure  104 , an isolation structure  120 , source/drain spacers  138 , and a source/drain feature  144 , in accordance with some embodiments. The isolation structure  120  includes a vertical portion  120 V surrounding the semiconductor fin structure  104 , in accordance with some embodiments. The source/drain spacers  138  are formed directly above the vertical portion  120 V of the isolation structure  120 , in accordance with some embodiments. The source/drain feature  144  is interposed between the source/drain spacers  138 , in accordance with some embodiments. Because the source/drain spacers  138  confine the lateral growth of the source/drain feature  144 , the source/drain feature  144  can be formed to have a narrower width than if the source/drain spacers are not formed, in accordance with some embodiments. As a result, the source/drain feature  144  having a narrower width can reduce the parasitic capacitance between the gate stack and the source/drain feature, thereby enhancing the operation speed of the semiconductor device, in accordance with some embodiments. 
     Embodiments of a semiconductor device structure may be provided. The semiconductor device structure may include a semiconductor fin structure, an isolation structure surrounding the semiconductor fin structure, source/drain spacers over the isolation structure, and a source/drain feature interposed between the source/drain spacers. Because the source/drain spacers confine the lateral growth of the source/drain feature, the source/drain feature may have a narrower width. As a result, the parasitic capacitance of the semiconductor device may be reduced, thereby enhancing the operation speed of the semiconductor device. 
     In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, forming a dielectric fin structure laterally spaced apart from the semiconductor fin structure, forming a source/drain spacer between the semiconductor fin structure and the dielectric fin structure, etching an upper portion of the semiconductor fin structure to expose a lower portion of the semiconductor fin structure, and forming a source/drain feature over the lower portion of the semiconductor fin structure. The source/drain spacer is interposed between the source/drain feature and the dielectric fin structure. 
     In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, forming a dummy gate structure across the semiconductor fin structure, forming a dielectric material along the dummy gate structure and the semiconductor fin structure, removing a first portion of the dielectric material to expose a sidewall of the dummy gate structure while leaving a second portion of the dielectric material covering sidewalls of the semiconductor fin structure to form source/drain spacers, etching a source/drain region of the semiconductor fin structure to form a recess between the source/drain spacers, and epitaxially growing a source/drain feature from the recess. 
     In some embodiments, a method for forming a semiconductor device structure is provided. The method includes forming a semiconductor fin structure over a substrate, conformally forming an insulating material along the semiconductor fin structure and the substrate, forming a dielectric fin structure adjacent to the semiconductor fin structure and over the insulating material, recessing the insulating material to form a gap between the semiconductor fin structure and the dielectric fin structure, forming a first dielectric material over the semiconductor fin structure and the dielectric fin structure and filling the gap, etching a first portion of the first dielectric material over the semiconductor fin structure and the dielectric fin structure to form a source/drain spacer in the gap, etching an upper portion of the semiconductor fin structure thereby exposing a lower portion of the semiconductor fin structure, and forming a source/drain feature over the lower portion of the semiconductor fin structure. 
     The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.